[thirdparty/gcc.git] / gcc / config / arm / unspecs.md

;; Unspec defintions.
;; Copyright (C) 2012-2019 Free Software Foundation, Inc.
;; Contributed by ARM Ltd.

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.

;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.

;; UNSPEC Usage:
;; Note: sin and cos are no-longer used.
;; Unspec enumerators for Neon are defined in neon.md.
;; Unspec enumerators for iwmmxt2 are defined in iwmmxt2.md

(define_c_enum "unspec" [
  UNSPEC_PUSH_MULT      ; `push multiple' operation:
                        ;   operand 0 is the first register,
                        ;   subsequent registers are in parallel (use ...)
                        ;   expressions.
  UNSPEC_PIC_SYM        ; A symbol that has been treated properly for pic
                        ; usage, that is, we will add the pic_register
                        ; value to it before trying to dereference it.
  UNSPEC_PIC_BASE       ; Add PC and all but the last operand together,
                        ; The last operand is the number of a PIC_LABEL
                        ; that points at the containing instruction.
  UNSPEC_PRLG_STK       ; A special barrier that prevents frame accesses
                        ; being scheduled before the stack adjustment insn.
  UNSPEC_REGISTER_USE   ; As USE insns are not meaningful after reload,
                        ; this unspec is used to prevent the deletion of
                        ; instructions setting registers for EH handling
                        ; and stack frame generation.  Operand 0 is the
                        ; register to "use".
  UNSPEC_CHECK_ARCH     ; Set CCs to indicate 26-bit or 32-bit mode.
  UNSPEC_WSHUFH         ; Used by the intrinsic form of the iWMMXt WSHUFH instruction.
  UNSPEC_WACC           ; Used by the intrinsic form of the iWMMXt WACC instruction.
  UNSPEC_TMOVMSK        ; Used by the intrinsic form of the iWMMXt TMOVMSK instruction.
  UNSPEC_WSAD           ; Used by the intrinsic form of the iWMMXt WSAD instruction.
  UNSPEC_WSADZ          ; Used by the intrinsic form of the iWMMXt WSADZ instruction.
  UNSPEC_WMACS          ; Used by the intrinsic form of the iWMMXt WMACS instruction.
  UNSPEC_WMACU          ; Used by the intrinsic form of the iWMMXt WMACU instruction.
  UNSPEC_WMACSZ         ; Used by the intrinsic form of the iWMMXt WMACSZ instruction.
  UNSPEC_WMACUZ         ; Used by the intrinsic form of the iWMMXt WMACUZ instruction.
  UNSPEC_CLRDI          ; Used by the intrinsic form of the iWMMXt CLRDI instruction.
  UNSPEC_WALIGNI        ; Used by the intrinsic form of the iWMMXt WALIGN instruction.
  UNSPEC_TLS            ; A symbol that has been treated properly for TLS usage.
  UNSPEC_PIC_LABEL      ; A label used for PIC access that does not appear in the
                        ; instruction stream.
  UNSPEC_PIC_OFFSET     ; A symbolic 12-bit OFFSET that has been treated
                        ; correctly for PIC usage.
  UNSPEC_GOTSYM_OFF     ; The offset of the start of the GOT from a
                        ; a given symbolic address.
  UNSPEC_THUMB1_CASESI  ; A Thumb1 compressed dispatch-table call.
  UNSPEC_RBIT           ; rbit operation.
  UNSPEC_SYMBOL_OFFSET  ; The offset of the start of the symbol from
                        ; another symbolic address.
  UNSPEC_MEMORY_BARRIER ; Represent a memory barrier.
  UNSPEC_UNALIGNED_LOAD	; Used to represent ldr/ldrh instructions that access
			; unaligned locations, on architectures which support
			; that.
  UNSPEC_UNALIGNED_STORE ; Same for str/strh.
  UNSPEC_PIC_UNIFIED    ; Create a common pic addressing form.
  UNSPEC_LL		; Represent an unpaired load-register-exclusive.
  UNSPEC_VRINTZ         ; Represent a float to integral float rounding
                        ; towards zero.
  UNSPEC_VRINTP         ; Represent a float to integral float rounding
                        ; towards +Inf.
  UNSPEC_VRINTM         ; Represent a float to integral float rounding
                        ; towards -Inf.
  UNSPEC_VRINTR         ; Represent a float to integral float rounding
                        ; FPSCR rounding mode.
  UNSPEC_VRINTX         ; Represent a float to integral float rounding
                        ; FPSCR rounding mode and signal inexactness.
  UNSPEC_VRINTA         ; Represent a float to integral float rounding
                        ; towards nearest, ties away from zero.
  UNSPEC_PROBE_STACK    ; Probe stack memory reference
  UNSPEC_NONSECURE_MEM	; Represent non-secure memory in ARMv8-M with
			; security extension
  UNSPEC_SP_SET		; Represent the setting of stack protector's canary
  UNSPEC_SP_TEST	; Represent the testing of stack protector's canary
			; against the guard.
])

(define_c_enum "unspec" [
  UNSPEC_WADDC		; Used by the intrinsic form of the iWMMXt WADDC instruction.
  UNSPEC_WABS		; Used by the intrinsic form of the iWMMXt WABS instruction.
  UNSPEC_WQMULWMR	; Used by the intrinsic form of the iWMMXt WQMULWMR instruction.
  UNSPEC_WQMULMR	; Used by the intrinsic form of the iWMMXt WQMULMR instruction.
  UNSPEC_WQMULWM	; Used by the intrinsic form of the iWMMXt WQMULWM instruction.
  UNSPEC_WQMULM		; Used by the intrinsic form of the iWMMXt WQMULM instruction.
  UNSPEC_WQMIAxyn	; Used by the intrinsic form of the iWMMXt WMIAxyn instruction.
  UNSPEC_WQMIAxy	; Used by the intrinsic form of the iWMMXt WMIAxy instruction.
  UNSPEC_TANDC		; Used by the intrinsic form of the iWMMXt TANDC instruction.
  UNSPEC_TORC		; Used by the intrinsic form of the iWMMXt TORC instruction.
  UNSPEC_TORVSC		; Used by the intrinsic form of the iWMMXt TORVSC instruction.
  UNSPEC_TEXTRC		; Used by the intrinsic form of the iWMMXt TEXTRC instruction.
])


;; UNSPEC_VOLATILE Usage:

(define_c_enum "unspecv" [
  VUNSPEC_BLOCKAGE      ; `blockage' insn to prevent scheduling across an
                        ;   insn in the code.
  VUNSPEC_EPILOGUE      ; `epilogue' insn, used to represent any part of the
                        ;   instruction epilogue sequence that isn't expanded
                        ;   into normal RTL.  Used for both normal and sibcall
                        ;   epilogues.
  VUNSPEC_THUMB1_INTERWORK ; `prologue_thumb1_interwork' insn, used to swap
			;   modes from arm to thumb.
  VUNSPEC_ALIGN         ; `align' insn.  Used at the head of a minipool table
                        ;   for inlined constants.
  VUNSPEC_POOL_END      ; `end-of-table'.  Used to mark the end of a minipool
                        ;   table.
  VUNSPEC_POOL_1        ; `pool-entry(1)'.  An entry in the constant pool for
                        ;   an 8-bit object.
  VUNSPEC_POOL_2        ; `pool-entry(2)'.  An entry in the constant pool for
                        ;   a 16-bit object.
  VUNSPEC_POOL_4        ; `pool-entry(4)'.  An entry in the constant pool for
                        ;   a 32-bit object.
  VUNSPEC_POOL_8        ; `pool-entry(8)'.  An entry in the constant pool for
                        ;   a 64-bit object.
  VUNSPEC_POOL_16       ; `pool-entry(16)'.  An entry in the constant pool for
                        ;   a 128-bit object.
  VUNSPEC_TMRC          ; Used by the iWMMXt TMRC instruction.
  VUNSPEC_TMCR          ; Used by the iWMMXt TMCR instruction.
  VUNSPEC_ALIGN8        ; 8-byte alignment version of VUNSPEC_ALIGN
  VUNSPEC_WCMP_EQ       ; Used by the iWMMXt WCMPEQ instructions
  VUNSPEC_WCMP_GTU      ; Used by the iWMMXt WCMPGTU instructions
  VUNSPEC_WCMP_GT       ; Used by the iwMMXT WCMPGT instructions
  VUNSPEC_EH_RETURN     ; Use to override the return address for exception
                        ; handling.
  VUNSPEC_ATOMIC_CAS	; Represent an atomic compare swap.
  VUNSPEC_ATOMIC_XCHG	; Represent an atomic exchange.
  VUNSPEC_ATOMIC_OP	; Represent an atomic operation.
  VUNSPEC_LL		; Represent a load-register-exclusive.
  VUNSPEC_LDRD_ATOMIC	; Represent an LDRD used as an atomic DImode load.
  VUNSPEC_SC		; Represent a store-register-exclusive.
  VUNSPEC_LAX		; Represent a load-register-acquire-exclusive.
  VUNSPEC_SLX		; Represent a store-register-release-exclusive.
  VUNSPEC_LDA		; Represent a store-register-acquire.
  VUNSPEC_STL		; Represent a store-register-release.
  VUNSPEC_GET_FPSCR	; Represent fetch of FPSCR content.
  VUNSPEC_SET_FPSCR	; Represent assign of FPSCR content.
  VUNSPEC_PROBE_STACK_RANGE ; Represent stack range probing.
  VUNSPEC_CDP		; Represent the coprocessor cdp instruction.
  VUNSPEC_CDP2		; Represent the coprocessor cdp2 instruction.
  VUNSPEC_LDC		; Represent the coprocessor ldc instruction.
  VUNSPEC_LDC2		; Represent the coprocessor ldc2 instruction.
  VUNSPEC_LDCL		; Represent the coprocessor ldcl instruction.
  VUNSPEC_LDC2L		; Represent the coprocessor ldc2l instruction.
  VUNSPEC_STC		; Represent the coprocessor stc instruction.
  VUNSPEC_STC2		; Represent the coprocessor stc2 instruction.
  VUNSPEC_STCL		; Represent the coprocessor stcl instruction.
  VUNSPEC_STC2L		; Represent the coprocessor stc2l instruction.
  VUNSPEC_MCR		; Represent the coprocessor mcr instruction.
  VUNSPEC_MCR2		; Represent the coprocessor mcr2 instruction.
  VUNSPEC_MRC		; Represent the coprocessor mrc instruction.
  VUNSPEC_MRC2		; Represent the coprocessor mrc2 instruction.
  VUNSPEC_MCRR		; Represent the coprocessor mcrr instruction.
  VUNSPEC_MCRR2		; Represent the coprocessor mcrr2 instruction.
  VUNSPEC_MRRC		; Represent the coprocessor mrrc instruction.
  VUNSPEC_MRRC2		; Represent the coprocessor mrrc2 instruction.
  VUNSPEC_SPECULATION_BARRIER ; Represents an unconditional speculation barrier.
])

;; Enumerators for NEON unspecs.
(define_c_enum "unspec" [
  UNSPEC_ASHIFT_SIGNED
  UNSPEC_ASHIFT_UNSIGNED
  UNSPEC_CRC32B
  UNSPEC_CRC32H
  UNSPEC_CRC32W
  UNSPEC_CRC32CB
  UNSPEC_CRC32CH
  UNSPEC_CRC32CW
  UNSPEC_AESD
  UNSPEC_AESE
  UNSPEC_AESIMC
  UNSPEC_AESMC
  UNSPEC_SHA1C
  UNSPEC_SHA1M
  UNSPEC_SHA1P
  UNSPEC_SHA1H
  UNSPEC_SHA1SU0
  UNSPEC_SHA1SU1
  UNSPEC_SHA256H
  UNSPEC_SHA256H2
  UNSPEC_SHA256SU0
  UNSPEC_SHA256SU1
  UNSPEC_VMULLP64
  UNSPEC_LOAD_COUNT
  UNSPEC_VABD_F
  UNSPEC_VABD_S
  UNSPEC_VABD_U
  UNSPEC_VABDL_S
  UNSPEC_VABDL_U
  UNSPEC_VADD
  UNSPEC_VADDHN
  UNSPEC_VRADDHN
  UNSPEC_VADDL_S
  UNSPEC_VADDL_U
  UNSPEC_VADDW_S
  UNSPEC_VADDW_U
  UNSPEC_VBSL
  UNSPEC_VCAGE
  UNSPEC_VCAGT
  UNSPEC_VCALE
  UNSPEC_VCALT
  UNSPEC_VCEQ
  UNSPEC_VCGE
  UNSPEC_VCGEU
  UNSPEC_VCGT
  UNSPEC_VCGTU
  UNSPEC_VCLS
  UNSPEC_VCONCAT
  UNSPEC_VCVT
  UNSPEC_VCVT_S
  UNSPEC_VCVT_U
  UNSPEC_VCVT_S_N
  UNSPEC_VCVT_U_N
  UNSPEC_VCVT_HF_S_N
  UNSPEC_VCVT_HF_U_N
  UNSPEC_VCVT_SI_S_N
  UNSPEC_VCVT_SI_U_N
  UNSPEC_VCVTH_S
  UNSPEC_VCVTH_U
  UNSPEC_VCVTA_S
  UNSPEC_VCVTA_U
  UNSPEC_VCVTM_S
  UNSPEC_VCVTM_U
  UNSPEC_VCVTN_S
  UNSPEC_VCVTN_U
  UNSPEC_VCVTP_S
  UNSPEC_VCVTP_U
  UNSPEC_VEXT
  UNSPEC_VHADD_S
  UNSPEC_VHADD_U
  UNSPEC_VRHADD_S
  UNSPEC_VRHADD_U
  UNSPEC_VHSUB_S
  UNSPEC_VHSUB_U
  UNSPEC_VLD1
  UNSPEC_VLD1_LANE
  UNSPEC_VLD2
  UNSPEC_VLD2_DUP
  UNSPEC_VLD2_LANE
  UNSPEC_VLD3
  UNSPEC_VLD3A
  UNSPEC_VLD3B
  UNSPEC_VLD3_DUP
  UNSPEC_VLD3_LANE
  UNSPEC_VLD4
  UNSPEC_VLD4A
  UNSPEC_VLD4B
  UNSPEC_VLD4_DUP
  UNSPEC_VLD4_LANE
  UNSPEC_VMAX
  UNSPEC_VMAX_U
  UNSPEC_VMAXNM
  UNSPEC_VMIN
  UNSPEC_VMIN_U
  UNSPEC_VMINNM
  UNSPEC_VMLA
  UNSPEC_VMLA_LANE
  UNSPEC_VMLAL_S
  UNSPEC_VMLAL_U
  UNSPEC_VMLAL_S_LANE
  UNSPEC_VMLAL_U_LANE
  UNSPEC_VMLS
  UNSPEC_VMLS_LANE
  UNSPEC_VMLSL_S
  UNSPEC_VMLSL_U
  UNSPEC_VMLSL_S_LANE
  UNSPEC_VMLSL_U_LANE
  UNSPEC_VMLSL_LANE
  UNSPEC_VFMA_LANE
  UNSPEC_VFMS_LANE
  UNSPEC_VMOVL_S
  UNSPEC_VMOVL_U
  UNSPEC_VMOVN
  UNSPEC_VMUL
  UNSPEC_VMULL_P
  UNSPEC_VMULL_S
  UNSPEC_VMULL_U
  UNSPEC_VMUL_LANE
  UNSPEC_VMULL_S_LANE
  UNSPEC_VMULL_U_LANE
  UNSPEC_VPADAL_S
  UNSPEC_VPADAL_U
  UNSPEC_VPADD
  UNSPEC_VPADDL_S
  UNSPEC_VPADDL_U
  UNSPEC_VPMAX
  UNSPEC_VPMAX_U
  UNSPEC_VPMIN
  UNSPEC_VPMIN_U
  UNSPEC_VPSMAX
  UNSPEC_VPSMIN
  UNSPEC_VPUMAX
  UNSPEC_VPUMIN
  UNSPEC_VQABS
  UNSPEC_VQADD_S
  UNSPEC_VQADD_U
  UNSPEC_VQDMLAL
  UNSPEC_VQDMLAL_LANE
  UNSPEC_VQDMLSL
  UNSPEC_VQDMLSL_LANE
  UNSPEC_VQDMULH
  UNSPEC_VQDMULH_LANE
  UNSPEC_VQRDMULH
  UNSPEC_VQRDMULH_LANE
  UNSPEC_VQDMULL
  UNSPEC_VQDMULL_LANE
  UNSPEC_VQMOVN_S
  UNSPEC_VQMOVN_U
  UNSPEC_VQMOVUN
  UNSPEC_VQNEG
  UNSPEC_VQSHL_S
  UNSPEC_VQSHL_U
  UNSPEC_VQRSHL_S
  UNSPEC_VQRSHL_U
  UNSPEC_VQSHL_S_N
  UNSPEC_VQSHL_U_N
  UNSPEC_VQSHLU_N
  UNSPEC_VQSHRN_S_N
  UNSPEC_VQSHRN_U_N
  UNSPEC_VQRSHRN_S_N
  UNSPEC_VQRSHRN_U_N
  UNSPEC_VQSHRUN_N
  UNSPEC_VQRSHRUN_N
  UNSPEC_VQSUB_S
  UNSPEC_VQSUB_U
  UNSPEC_VRECPE
  UNSPEC_VRECPS
  UNSPEC_VREV16
  UNSPEC_VREV32
  UNSPEC_VREV64
  UNSPEC_VRSQRTE
  UNSPEC_VRSQRTS
  UNSPEC_VSHL_S
  UNSPEC_VSHL_U
  UNSPEC_VRSHL_S
  UNSPEC_VRSHL_U
  UNSPEC_VSHLL_S_N
  UNSPEC_VSHLL_U_N
  UNSPEC_VSHL_N
  UNSPEC_VSHR_S_N
  UNSPEC_VSHR_U_N
  UNSPEC_VRSHR_S_N
  UNSPEC_VRSHR_U_N
  UNSPEC_VSHRN_N
  UNSPEC_VRSHRN_N
  UNSPEC_VSLI
  UNSPEC_VSRA_S_N
  UNSPEC_VSRA_U_N
  UNSPEC_VRSRA_S_N
  UNSPEC_VRSRA_U_N
  UNSPEC_VSRI
  UNSPEC_VST1
  UNSPEC_VST1_LANE
  UNSPEC_VST2
  UNSPEC_VST2_LANE
  UNSPEC_VST3
  UNSPEC_VST3A
  UNSPEC_VST3B
  UNSPEC_VST3_LANE
  UNSPEC_VST4
  UNSPEC_VST4A
  UNSPEC_VST4B
  UNSPEC_VST4_LANE
  UNSPEC_VSTRUCTDUMMY
  UNSPEC_VSUB
  UNSPEC_VSUBHN
  UNSPEC_VRSUBHN
  UNSPEC_VSUBL_S
  UNSPEC_VSUBL_U
  UNSPEC_VSUBW_S
  UNSPEC_VSUBW_U
  UNSPEC_VTBL
  UNSPEC_VTBX
  UNSPEC_VTRN1
  UNSPEC_VTRN2
  UNSPEC_VTST
  UNSPEC_VUZP1
  UNSPEC_VUZP2
  UNSPEC_VZIP1
  UNSPEC_VZIP2
  UNSPEC_MISALIGNED_ACCESS
  UNSPEC_VCLE
  UNSPEC_VCLT
  UNSPEC_NVRINTZ
  UNSPEC_NVRINTP
  UNSPEC_NVRINTM
  UNSPEC_NVRINTX
  UNSPEC_NVRINTA
  UNSPEC_NVRINTN
  UNSPEC_VQRDMLAH
  UNSPEC_VQRDMLSH
  UNSPEC_VRND
  UNSPEC_VRNDA
  UNSPEC_VRNDI
  UNSPEC_VRNDM
  UNSPEC_VRNDN
  UNSPEC_VRNDP
  UNSPEC_VRNDX
  UNSPEC_DOT_S
  UNSPEC_DOT_U
  UNSPEC_VFML_LO
  UNSPEC_VFML_HI
])
Commit	Line	Data
5944e3a8	1	;; Unspec defintions.
a5544970	2	;; Copyright (C) 2012-2019 Free Software Foundation, Inc.
5944e3a8 KT	3	;; Contributed by ARM Ltd.
	4
	5	;; This file is part of GCC.
	6
	7	;; GCC is free software; you can redistribute it and/or modify it
	8	;; under the terms of the GNU General Public License as published
	9	;; by the Free Software Foundation; either version 3, or (at your
	10	;; option) any later version.
	11
	12	;; GCC is distributed in the hope that it will be useful, but WITHOUT
	13	;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	14	;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	;; License for more details.
	16
	17	;; You should have received a copy of the GNU General Public License
	18	;; along with GCC; see the file COPYING3. If not see
	19	;; <http://www.gnu.org/licenses/>.
	20
79739965 KT	21	;; UNSPEC Usage:
	22	;; Note: sin and cos are no-longer used.
	23	;; Unspec enumerators for Neon are defined in neon.md.
	24	;; Unspec enumerators for iwmmxt2 are defined in iwmmxt2.md
	25
	26	(define_c_enum "unspec" [
	27	UNSPEC_PUSH_MULT ; `push multiple' operation:
	28	; operand 0 is the first register,
	29	; subsequent registers are in parallel (use ...)
	30	; expressions.
	31	UNSPEC_PIC_SYM ; A symbol that has been treated properly for pic
	32	; usage, that is, we will add the pic_register
	33	; value to it before trying to dereference it.
	34	UNSPEC_PIC_BASE ; Add PC and all but the last operand together,
	35	; The last operand is the number of a PIC_LABEL
	36	; that points at the containing instruction.
	37	UNSPEC_PRLG_STK ; A special barrier that prevents frame accesses
	38	; being scheduled before the stack adjustment insn.
	39	UNSPEC_REGISTER_USE ; As USE insns are not meaningful after reload,
	40	; this unspec is used to prevent the deletion of
	41	; instructions setting registers for EH handling
	42	; and stack frame generation. Operand 0 is the
	43	; register to "use".
	44	UNSPEC_CHECK_ARCH ; Set CCs to indicate 26-bit or 32-bit mode.
	45	UNSPEC_WSHUFH ; Used by the intrinsic form of the iWMMXt WSHUFH instruction.
	46	UNSPEC_WACC ; Used by the intrinsic form of the iWMMXt WACC instruction.
	47	UNSPEC_TMOVMSK ; Used by the intrinsic form of the iWMMXt TMOVMSK instruction.
	48	UNSPEC_WSAD ; Used by the intrinsic form of the iWMMXt WSAD instruction.
	49	UNSPEC_WSADZ ; Used by the intrinsic form of the iWMMXt WSADZ instruction.
	50	UNSPEC_WMACS ; Used by the intrinsic form of the iWMMXt WMACS instruction.
	51	UNSPEC_WMACU ; Used by the intrinsic form of the iWMMXt WMACU instruction.
	52	UNSPEC_WMACSZ ; Used by the intrinsic form of the iWMMXt WMACSZ instruction.
	53	UNSPEC_WMACUZ ; Used by the intrinsic form of the iWMMXt WMACUZ instruction.
	54	UNSPEC_CLRDI ; Used by the intrinsic form of the iWMMXt CLRDI instruction.
	55	UNSPEC_WALIGNI ; Used by the intrinsic form of the iWMMXt WALIGN instruction.
	56	UNSPEC_TLS ; A symbol that has been treated properly for TLS usage.
	57	UNSPEC_PIC_LABEL ; A label used for PIC access that does not appear in the
	58	; instruction stream.
	59	UNSPEC_PIC_OFFSET ; A symbolic 12-bit OFFSET that has been treated
	60	; correctly for PIC usage.
	61	UNSPEC_GOTSYM_OFF ; The offset of the start of the GOT from a
	62	; a given symbolic address.
	63	UNSPEC_THUMB1_CASESI ; A Thumb1 compressed dispatch-table call.
	64	UNSPEC_RBIT ; rbit operation.
	65	UNSPEC_SYMBOL_OFFSET ; The offset of the start of the symbol from
	66	; another symbolic address.
	67	UNSPEC_MEMORY_BARRIER ; Represent a memory barrier.
	68	UNSPEC_UNALIGNED_LOAD ; Used to represent ldr/ldrh instructions that access
	69	; unaligned locations, on architectures which support
	70	; that.
	71	UNSPEC_UNALIGNED_STORE ; Same for str/strh.
	72	UNSPEC_PIC_UNIFIED ; Create a common pic addressing form.
	73	UNSPEC_LL ; Represent an unpaired load-register-exclusive.
	74	UNSPEC_VRINTZ ; Represent a float to integral float rounding
	75	; towards zero.
	76	UNSPEC_VRINTP ; Represent a float to integral float rounding
	77	; towards +Inf.
	78	UNSPEC_VRINTM ; Represent a float to integral float rounding
	79	; towards -Inf.
	80	UNSPEC_VRINTR ; Represent a float to integral float rounding
	81	; FPSCR rounding mode.
	82	UNSPEC_VRINTX ; Represent a float to integral float rounding
	83	; FPSCR rounding mode and signal inexactness.
	84	UNSPEC_VRINTA ; Represent a float to integral float rounding
85	; towards nearest, ties away from zero.
4fb94ef9	86	UNSPEC_PROBE_STACK ; Probe stack memory reference
c92e08e3 AV	87	UNSPEC_NONSECURE_MEM ; Represent non-secure memory in ARMv8-M with
c92e08e3 AV	88	; security extension
89d75572 TP	89	UNSPEC_SP_SET ; Represent the setting of stack protector's canary
	90	UNSPEC_SP_TEST ; Represent the testing of stack protector's canary
	91	; against the guard.
79739965 KT	92	])
	93
	94	(define_c_enum "unspec" [
	95	UNSPEC_WADDC ; Used by the intrinsic form of the iWMMXt WADDC instruction.
	96	UNSPEC_WABS ; Used by the intrinsic form of the iWMMXt WABS instruction.
	97	UNSPEC_WQMULWMR ; Used by the intrinsic form of the iWMMXt WQMULWMR instruction.
	98	UNSPEC_WQMULMR ; Used by the intrinsic form of the iWMMXt WQMULMR instruction.
	99	UNSPEC_WQMULWM ; Used by the intrinsic form of the iWMMXt WQMULWM instruction.
	100	UNSPEC_WQMULM ; Used by the intrinsic form of the iWMMXt WQMULM instruction.
	101	UNSPEC_WQMIAxyn ; Used by the intrinsic form of the iWMMXt WMIAxyn instruction.
	102	UNSPEC_WQMIAxy ; Used by the intrinsic form of the iWMMXt WMIAxy instruction.
	103	UNSPEC_TANDC ; Used by the intrinsic form of the iWMMXt TANDC instruction.
	104	UNSPEC_TORC ; Used by the intrinsic form of the iWMMXt TORC instruction.
	105	UNSPEC_TORVSC ; Used by the intrinsic form of the iWMMXt TORVSC instruction.
	106	UNSPEC_TEXTRC ; Used by the intrinsic form of the iWMMXt TEXTRC instruction.
	107	])
	108
	109
	110	;; UNSPEC_VOLATILE Usage:
	111
	112	(define_c_enum "unspecv" [
	113	VUNSPEC_BLOCKAGE ; `blockage' insn to prevent scheduling across an
	114	; insn in the code.
	115	VUNSPEC_EPILOGUE ; `epilogue' insn, used to represent any part of the
	116	; instruction epilogue sequence that isn't expanded
	117	; into normal RTL. Used for both normal and sibcall
	118	; epilogues.
	119	VUNSPEC_THUMB1_INTERWORK ; `prologue_thumb1_interwork' insn, used to swap
	120	; modes from arm to thumb.
	121	VUNSPEC_ALIGN ; `align' insn. Used at the head of a minipool table
	122	; for inlined constants.
	123	VUNSPEC_POOL_END ; `end-of-table'. Used to mark the end of a minipool
	124	; table.
	125	VUNSPEC_POOL_1 ; `pool-entry(1)'. An entry in the constant pool for
	126	; an 8-bit object.
	127	VUNSPEC_POOL_2 ; `pool-entry(2)'. An entry in the constant pool for
	128	; a 16-bit object.
	129	VUNSPEC_POOL_4 ; `pool-entry(4)'. An entry in the constant pool for
	130	; a 32-bit object.
	131	VUNSPEC_POOL_8 ; `pool-entry(8)'. An entry in the constant pool for
	132	; a 64-bit object.
	133	VUNSPEC_POOL_16 ; `pool-entry(16)'. An entry in the constant pool for
	134	; a 128-bit object.
	135	VUNSPEC_TMRC ; Used by the iWMMXt TMRC instruction.
	136	VUNSPEC_TMCR ; Used by the iWMMXt TMCR instruction.
	137	VUNSPEC_ALIGN8 ; 8-byte alignment version of VUNSPEC_ALIGN
	138	VUNSPEC_WCMP_EQ ; Used by the iWMMXt WCMPEQ instructions
	139	VUNSPEC_WCMP_GTU ; Used by the iWMMXt WCMPGTU instructions
	140	VUNSPEC_WCMP_GT ; Used by the iwMMXT WCMPGT instructions
	141	VUNSPEC_EH_RETURN ; Use to override the return address for exception
	142	; handling.
	143	VUNSPEC_ATOMIC_CAS ; Represent an atomic compare swap.
	144	VUNSPEC_ATOMIC_XCHG ; Represent an atomic exchange.
	145	VUNSPEC_ATOMIC_OP ; Represent an atomic operation.
	146	VUNSPEC_LL ; Represent a load-register-exclusive.
74a00288	147	VUNSPEC_LDRD_ATOMIC ; Represent an LDRD used as an atomic DImode load.
79739965	148	VUNSPEC_SC ; Represent a store-register-exclusive.
5ad29f12 KT	149	VUNSPEC_LAX ; Represent a load-register-acquire-exclusive.
	150	VUNSPEC_SLX ; Represent a store-register-release-exclusive.
	151	VUNSPEC_LDA ; Represent a store-register-acquire.
	152	VUNSPEC_STL ; Represent a store-register-release.
f10743d3 KV	153	VUNSPEC_GET_FPSCR ; Represent fetch of FPSCR content.
f10743d3 KV	154	VUNSPEC_SET_FPSCR ; Represent assign of FPSCR content.
f58101cf	155	VUNSPEC_PROBE_STACK_RANGE ; Represent stack range probing.
d57daa0c AV	156	VUNSPEC_CDP ; Represent the coprocessor cdp instruction.
d57daa0c AV	157	VUNSPEC_CDP2 ; Represent the coprocessor cdp2 instruction.
3811581f AV	158	VUNSPEC_LDC ; Represent the coprocessor ldc instruction.
	159	VUNSPEC_LDC2 ; Represent the coprocessor ldc2 instruction.
	160	VUNSPEC_LDCL ; Represent the coprocessor ldcl instruction.
	161	VUNSPEC_LDC2L ; Represent the coprocessor ldc2l instruction.
	162	VUNSPEC_STC ; Represent the coprocessor stc instruction.
	163	VUNSPEC_STC2 ; Represent the coprocessor stc2 instruction.
	164	VUNSPEC_STCL ; Represent the coprocessor stcl instruction.
	165	VUNSPEC_STC2L ; Represent the coprocessor stc2l instruction.
ecc9a25b AV	166	VUNSPEC_MCR ; Represent the coprocessor mcr instruction.
	167	VUNSPEC_MCR2 ; Represent the coprocessor mcr2 instruction.
	168	VUNSPEC_MRC ; Represent the coprocessor mrc instruction.
	169	VUNSPEC_MRC2 ; Represent the coprocessor mrc2 instruction.
f3caa118 AV	170	VUNSPEC_MCRR ; Represent the coprocessor mcrr instruction.
	171	VUNSPEC_MCRR2 ; Represent the coprocessor mcrr2 instruction.
	172	VUNSPEC_MRRC ; Represent the coprocessor mrrc instruction.
	173	VUNSPEC_MRRC2 ; Represent the coprocessor mrrc2 instruction.
bb8b0096	174	VUNSPEC_SPECULATION_BARRIER ; Represents an unconditional speculation barrier.
79739965 KT	175	])
	176
	177	;; Enumerators for NEON unspecs.
	178	(define_c_enum "unspec" [
	179	UNSPEC_ASHIFT_SIGNED
	180	UNSPEC_ASHIFT_UNSIGNED
582e2e43 KT	181	UNSPEC_CRC32B
	182	UNSPEC_CRC32H
	183	UNSPEC_CRC32W
	184	UNSPEC_CRC32CB
	185	UNSPEC_CRC32CH
	186	UNSPEC_CRC32CW
021b5e6b KT	187	UNSPEC_AESD
	188	UNSPEC_AESE
	189	UNSPEC_AESIMC
	190	UNSPEC_AESMC
	191	UNSPEC_SHA1C
	192	UNSPEC_SHA1M
	193	UNSPEC_SHA1P
	194	UNSPEC_SHA1H
	195	UNSPEC_SHA1SU0
	196	UNSPEC_SHA1SU1
	197	UNSPEC_SHA256H
	198	UNSPEC_SHA256H2
	199	UNSPEC_SHA256SU0
	200	UNSPEC_SHA256SU1
	201	UNSPEC_VMULLP64
79739965	202	UNSPEC_LOAD_COUNT
94f0f2cc JG	203	UNSPEC_VABD_F
	204	UNSPEC_VABD_S
	205	UNSPEC_VABD_U
	206	UNSPEC_VABDL_S
	207	UNSPEC_VABDL_U
79739965 KT	208	UNSPEC_VADD
79739965 KT	209	UNSPEC_VADDHN
94f0f2cc JG	210	UNSPEC_VRADDHN
	211	UNSPEC_VADDL_S
	212	UNSPEC_VADDL_U
	213	UNSPEC_VADDW_S
	214	UNSPEC_VADDW_U
79739965 KT	215	UNSPEC_VBSL
	216	UNSPEC_VCAGE
	217	UNSPEC_VCAGT
55a9b91b MW	218	UNSPEC_VCALE
55a9b91b MW	219	UNSPEC_VCALT
79739965 KT	220	UNSPEC_VCEQ
	221	UNSPEC_VCGE
	222	UNSPEC_VCGEU
	223	UNSPEC_VCGT
	224	UNSPEC_VCGTU
	225	UNSPEC_VCLS
	226	UNSPEC_VCONCAT
	227	UNSPEC_VCVT
94f0f2cc JG	228	UNSPEC_VCVT_S
	229	UNSPEC_VCVT_U
	230	UNSPEC_VCVT_S_N
	231	UNSPEC_VCVT_U_N
d403b8d4 MW	232	UNSPEC_VCVT_HF_S_N
	233	UNSPEC_VCVT_HF_U_N
	234	UNSPEC_VCVT_SI_S_N
	235	UNSPEC_VCVT_SI_U_N
	236	UNSPEC_VCVTH_S
	237	UNSPEC_VCVTH_U
	238	UNSPEC_VCVTA_S
	239	UNSPEC_VCVTA_U
	240	UNSPEC_VCVTM_S
	241	UNSPEC_VCVTM_U
	242	UNSPEC_VCVTN_S
	243	UNSPEC_VCVTN_U
	244	UNSPEC_VCVTP_S
	245	UNSPEC_VCVTP_U
79739965	246	UNSPEC_VEXT
94f0f2cc JG	247	UNSPEC_VHADD_S
	248	UNSPEC_VHADD_U
	249	UNSPEC_VRHADD_S
	250	UNSPEC_VRHADD_U
	251	UNSPEC_VHSUB_S
	252	UNSPEC_VHSUB_U
79739965 KT	253	UNSPEC_VLD1
	254	UNSPEC_VLD1_LANE
	255	UNSPEC_VLD2
	256	UNSPEC_VLD2_DUP
	257	UNSPEC_VLD2_LANE
	258	UNSPEC_VLD3
	259	UNSPEC_VLD3A
	260	UNSPEC_VLD3B
	261	UNSPEC_VLD3_DUP
	262	UNSPEC_VLD3_LANE
	263	UNSPEC_VLD4
	264	UNSPEC_VLD4A
	265	UNSPEC_VLD4B
	266	UNSPEC_VLD4_DUP
	267	UNSPEC_VLD4_LANE
	268	UNSPEC_VMAX
94f0f2cc	269	UNSPEC_VMAX_U
0a18c19f	270	UNSPEC_VMAXNM
79739965	271	UNSPEC_VMIN
94f0f2cc	272	UNSPEC_VMIN_U
0a18c19f	273	UNSPEC_VMINNM
79739965	274	UNSPEC_VMLA
79739965	275	UNSPEC_VMLA_LANE
94f0f2cc JG	276	UNSPEC_VMLAL_S
	277	UNSPEC_VMLAL_U
	278	UNSPEC_VMLAL_S_LANE
	279	UNSPEC_VMLAL_U_LANE
79739965	280	UNSPEC_VMLS
79739965	281	UNSPEC_VMLS_LANE
94f0f2cc JG	282	UNSPEC_VMLSL_S
	283	UNSPEC_VMLSL_U
	284	UNSPEC_VMLSL_S_LANE
	285	UNSPEC_VMLSL_U_LANE
79739965	286	UNSPEC_VMLSL_LANE
55a9b91b MW	287	UNSPEC_VFMA_LANE
55a9b91b MW	288	UNSPEC_VFMS_LANE
94f0f2cc JG	289	UNSPEC_VMOVL_S
94f0f2cc JG	290	UNSPEC_VMOVL_U
79739965 KT	291	UNSPEC_VMOVN
79739965 KT	292	UNSPEC_VMUL
94f0f2cc JG	293	UNSPEC_VMULL_P
	294	UNSPEC_VMULL_S
	295	UNSPEC_VMULL_U
79739965	296	UNSPEC_VMUL_LANE
94f0f2cc JG	297	UNSPEC_VMULL_S_LANE
	298	UNSPEC_VMULL_U_LANE
	299	UNSPEC_VPADAL_S
	300	UNSPEC_VPADAL_U
79739965	301	UNSPEC_VPADD
94f0f2cc JG	302	UNSPEC_VPADDL_S
94f0f2cc JG	303	UNSPEC_VPADDL_U
79739965	304	UNSPEC_VPMAX
94f0f2cc	305	UNSPEC_VPMAX_U
79739965	306	UNSPEC_VPMIN
94f0f2cc	307	UNSPEC_VPMIN_U
79739965 KT	308	UNSPEC_VPSMAX
	309	UNSPEC_VPSMIN
	310	UNSPEC_VPUMAX
	311	UNSPEC_VPUMIN
	312	UNSPEC_VQABS
94f0f2cc JG	313	UNSPEC_VQADD_S
94f0f2cc JG	314	UNSPEC_VQADD_U
79739965 KT	315	UNSPEC_VQDMLAL
	316	UNSPEC_VQDMLAL_LANE
	317	UNSPEC_VQDMLSL
	318	UNSPEC_VQDMLSL_LANE
	319	UNSPEC_VQDMULH
	320	UNSPEC_VQDMULH_LANE
94f0f2cc JG	321	UNSPEC_VQRDMULH
94f0f2cc JG	322	UNSPEC_VQRDMULH_LANE
79739965 KT	323	UNSPEC_VQDMULL
79739965 KT	324	UNSPEC_VQDMULL_LANE
94f0f2cc JG	325	UNSPEC_VQMOVN_S
94f0f2cc JG	326	UNSPEC_VQMOVN_U
79739965 KT	327	UNSPEC_VQMOVUN
79739965 KT	328	UNSPEC_VQNEG
94f0f2cc JG	329	UNSPEC_VQSHL_S
	330	UNSPEC_VQSHL_U
	331	UNSPEC_VQRSHL_S
	332	UNSPEC_VQRSHL_U
	333	UNSPEC_VQSHL_S_N
	334	UNSPEC_VQSHL_U_N
79739965	335	UNSPEC_VQSHLU_N
94f0f2cc JG	336	UNSPEC_VQSHRN_S_N
	337	UNSPEC_VQSHRN_U_N
	338	UNSPEC_VQRSHRN_S_N
	339	UNSPEC_VQRSHRN_U_N
79739965	340	UNSPEC_VQSHRUN_N
94f0f2cc JG	341	UNSPEC_VQRSHRUN_N
	342	UNSPEC_VQSUB_S
	343	UNSPEC_VQSUB_U
79739965 KT	344	UNSPEC_VRECPE
	345	UNSPEC_VRECPS
	346	UNSPEC_VREV16
	347	UNSPEC_VREV32
	348	UNSPEC_VREV64
	349	UNSPEC_VRSQRTE
	350	UNSPEC_VRSQRTS
94f0f2cc JG	351	UNSPEC_VSHL_S
	352	UNSPEC_VSHL_U
	353	UNSPEC_VRSHL_S
	354	UNSPEC_VRSHL_U
	355	UNSPEC_VSHLL_S_N
	356	UNSPEC_VSHLL_U_N
79739965	357	UNSPEC_VSHL_N
94f0f2cc JG	358	UNSPEC_VSHR_S_N
	359	UNSPEC_VSHR_U_N
	360	UNSPEC_VRSHR_S_N
	361	UNSPEC_VRSHR_U_N
79739965	362	UNSPEC_VSHRN_N
94f0f2cc	363	UNSPEC_VRSHRN_N
79739965	364	UNSPEC_VSLI
94f0f2cc JG	365	UNSPEC_VSRA_S_N
	366	UNSPEC_VSRA_U_N
	367	UNSPEC_VRSRA_S_N
	368	UNSPEC_VRSRA_U_N
79739965 KT	369	UNSPEC_VSRI
	370	UNSPEC_VST1
	371	UNSPEC_VST1_LANE
	372	UNSPEC_VST2
	373	UNSPEC_VST2_LANE
	374	UNSPEC_VST3
	375	UNSPEC_VST3A
	376	UNSPEC_VST3B
	377	UNSPEC_VST3_LANE
	378	UNSPEC_VST4
	379	UNSPEC_VST4A
	380	UNSPEC_VST4B
	381	UNSPEC_VST4_LANE
	382	UNSPEC_VSTRUCTDUMMY
	383	UNSPEC_VSUB
	384	UNSPEC_VSUBHN
94f0f2cc JG	385	UNSPEC_VRSUBHN
	386	UNSPEC_VSUBL_S
	387	UNSPEC_VSUBL_U
	388	UNSPEC_VSUBW_S
	389	UNSPEC_VSUBW_U
79739965 KT	390	UNSPEC_VTBL
	391	UNSPEC_VTBX
	392	UNSPEC_VTRN1
	393	UNSPEC_VTRN2
	394	UNSPEC_VTST
	395	UNSPEC_VUZP1
	396	UNSPEC_VUZP2
	397	UNSPEC_VZIP1
	398	UNSPEC_VZIP2
	399	UNSPEC_MISALIGNED_ACCESS
	400	UNSPEC_VCLE
	401	UNSPEC_VCLT
	402	UNSPEC_NVRINTZ
	403	UNSPEC_NVRINTP
	404	UNSPEC_NVRINTM
	405	UNSPEC_NVRINTX
	406	UNSPEC_NVRINTA
	407	UNSPEC_NVRINTN
5f2ca3b2 MW	408	UNSPEC_VQRDMLAH
5f2ca3b2 MW	409	UNSPEC_VQRDMLSH
d403b8d4 MW	410	UNSPEC_VRND
	411	UNSPEC_VRNDA
	412	UNSPEC_VRNDI
	413	UNSPEC_VRNDM
	414	UNSPEC_VRNDN
	415	UNSPEC_VRNDP
	416	UNSPEC_VRNDX
f8e109ba TC	417	UNSPEC_DOT_S
f8e109ba TC	418	UNSPEC_DOT_U
06e95715 KT	419	UNSPEC_VFML_LO
06e95715 KT	420	UNSPEC_VFML_HI
79739965	421	])