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5944e3a8 | 1 | ;; Unspec defintions. |
a5544970 | 2 | ;; Copyright (C) 2012-2019 Free Software Foundation, Inc. |
5944e3a8 KT |
3 | ;; Contributed by ARM Ltd. |
4 | ||
5 | ;; This file is part of GCC. | |
6 | ||
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
9 | ;; by the Free Software Foundation; either version 3, or (at your | |
10 | ;; option) any later version. | |
11 | ||
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. | |
20 | ||
79739965 KT |
21 | ;; UNSPEC Usage: |
22 | ;; Note: sin and cos are no-longer used. | |
23 | ;; Unspec enumerators for Neon are defined in neon.md. | |
24 | ;; Unspec enumerators for iwmmxt2 are defined in iwmmxt2.md | |
25 | ||
26 | (define_c_enum "unspec" [ | |
27 | UNSPEC_PUSH_MULT ; `push multiple' operation: | |
28 | ; operand 0 is the first register, | |
29 | ; subsequent registers are in parallel (use ...) | |
30 | ; expressions. | |
31 | UNSPEC_PIC_SYM ; A symbol that has been treated properly for pic | |
32 | ; usage, that is, we will add the pic_register | |
33 | ; value to it before trying to dereference it. | |
34 | UNSPEC_PIC_BASE ; Add PC and all but the last operand together, | |
35 | ; The last operand is the number of a PIC_LABEL | |
36 | ; that points at the containing instruction. | |
37 | UNSPEC_PRLG_STK ; A special barrier that prevents frame accesses | |
38 | ; being scheduled before the stack adjustment insn. | |
39 | UNSPEC_REGISTER_USE ; As USE insns are not meaningful after reload, | |
40 | ; this unspec is used to prevent the deletion of | |
41 | ; instructions setting registers for EH handling | |
42 | ; and stack frame generation. Operand 0 is the | |
43 | ; register to "use". | |
44 | UNSPEC_CHECK_ARCH ; Set CCs to indicate 26-bit or 32-bit mode. | |
45 | UNSPEC_WSHUFH ; Used by the intrinsic form of the iWMMXt WSHUFH instruction. | |
46 | UNSPEC_WACC ; Used by the intrinsic form of the iWMMXt WACC instruction. | |
47 | UNSPEC_TMOVMSK ; Used by the intrinsic form of the iWMMXt TMOVMSK instruction. | |
48 | UNSPEC_WSAD ; Used by the intrinsic form of the iWMMXt WSAD instruction. | |
49 | UNSPEC_WSADZ ; Used by the intrinsic form of the iWMMXt WSADZ instruction. | |
50 | UNSPEC_WMACS ; Used by the intrinsic form of the iWMMXt WMACS instruction. | |
51 | UNSPEC_WMACU ; Used by the intrinsic form of the iWMMXt WMACU instruction. | |
52 | UNSPEC_WMACSZ ; Used by the intrinsic form of the iWMMXt WMACSZ instruction. | |
53 | UNSPEC_WMACUZ ; Used by the intrinsic form of the iWMMXt WMACUZ instruction. | |
54 | UNSPEC_CLRDI ; Used by the intrinsic form of the iWMMXt CLRDI instruction. | |
55 | UNSPEC_WALIGNI ; Used by the intrinsic form of the iWMMXt WALIGN instruction. | |
56 | UNSPEC_TLS ; A symbol that has been treated properly for TLS usage. | |
57 | UNSPEC_PIC_LABEL ; A label used for PIC access that does not appear in the | |
58 | ; instruction stream. | |
59 | UNSPEC_PIC_OFFSET ; A symbolic 12-bit OFFSET that has been treated | |
60 | ; correctly for PIC usage. | |
61 | UNSPEC_GOTSYM_OFF ; The offset of the start of the GOT from a | |
62 | ; a given symbolic address. | |
63 | UNSPEC_THUMB1_CASESI ; A Thumb1 compressed dispatch-table call. | |
64 | UNSPEC_RBIT ; rbit operation. | |
65 | UNSPEC_SYMBOL_OFFSET ; The offset of the start of the symbol from | |
66 | ; another symbolic address. | |
67 | UNSPEC_MEMORY_BARRIER ; Represent a memory barrier. | |
68 | UNSPEC_UNALIGNED_LOAD ; Used to represent ldr/ldrh instructions that access | |
69 | ; unaligned locations, on architectures which support | |
70 | ; that. | |
71 | UNSPEC_UNALIGNED_STORE ; Same for str/strh. | |
72 | UNSPEC_PIC_UNIFIED ; Create a common pic addressing form. | |
73 | UNSPEC_LL ; Represent an unpaired load-register-exclusive. | |
74 | UNSPEC_VRINTZ ; Represent a float to integral float rounding | |
75 | ; towards zero. | |
76 | UNSPEC_VRINTP ; Represent a float to integral float rounding | |
77 | ; towards +Inf. | |
78 | UNSPEC_VRINTM ; Represent a float to integral float rounding | |
79 | ; towards -Inf. | |
80 | UNSPEC_VRINTR ; Represent a float to integral float rounding | |
81 | ; FPSCR rounding mode. | |
82 | UNSPEC_VRINTX ; Represent a float to integral float rounding | |
83 | ; FPSCR rounding mode and signal inexactness. | |
84 | UNSPEC_VRINTA ; Represent a float to integral float rounding | |
85 | ; towards nearest, ties away from zero. | |
4fb94ef9 | 86 | UNSPEC_PROBE_STACK ; Probe stack memory reference |
c92e08e3 AV |
87 | UNSPEC_NONSECURE_MEM ; Represent non-secure memory in ARMv8-M with |
88 | ; security extension | |
89d75572 TP |
89 | UNSPEC_SP_SET ; Represent the setting of stack protector's canary |
90 | UNSPEC_SP_TEST ; Represent the testing of stack protector's canary | |
91 | ; against the guard. | |
8b63716e | 92 | UNSPEC_PIC_RESTORE ; Use to restore fdpic register |
53cd0ac6 KT |
93 | |
94 | UNSPEC_SXTAB16 ; Represent the SXTAB16 operation. | |
95 | UNSPEC_UXTAB16 ; Represent the UXTAB16 operation. | |
96 | UNSPEC_SXTB16 ; Represent the SXTB16 operation. | |
97 | UNSPEC_UXTB16 ; Represent the UXTB16 operation. | |
98 | UNSPEC_QADD8 ; Represent the QADD8 operation. | |
99 | UNSPEC_QSUB8 ; Represent the QSUB8 operation. | |
100 | UNSPEC_SHADD8 ; Represent the SHADD8 operation. | |
101 | UNSPEC_SHSUB8 ; Represent the SHSUB8 operation. | |
102 | UNSPEC_UHADD8 ; Represent the UHADD8 operation. | |
103 | UNSPEC_UHSUB8 ; Represent the UHSUB8 operation. | |
104 | UNSPEC_UQADD8 ; Represent the UQADD8 operation. | |
105 | UNSPEC_UQSUB8 ; Represent the UQSUB8 operation. | |
106 | UNSPEC_QADD16 ; Represent the QADD16 operation. | |
107 | UNSPEC_QASX ; Represent the QASX operation. | |
108 | UNSPEC_QSAX ; Represent the QSAX operation. | |
109 | UNSPEC_QSUB16 ; Represent the QSUB16 operation. | |
110 | UNSPEC_SHADD16 ; Represent the SHADD16 operation. | |
111 | UNSPEC_SHASX ; Represent the SHASX operation. | |
112 | UNSPEC_SHSAX ; Represent the SSAX operation. | |
113 | UNSPEC_SHSUB16 ; Represent the SHSUB16 operation. | |
114 | UNSPEC_UHADD16 ; Represent the UHADD16 operation. | |
115 | UNSPEC_UHASX ; Represent the UHASX operation. | |
116 | UNSPEC_UHSAX ; Represent the USAX operation. | |
117 | UNSPEC_UHSUB16 ; Represent the UHSUB16 operation. | |
118 | UNSPEC_UQADD16 ; Represent the UQADD16 operation. | |
119 | UNSPEC_UQASX ; Represent the UQASX operation. | |
120 | UNSPEC_UQSAX ; Represent the UQSAX operation. | |
121 | UNSPEC_UQSUB16 ; Represent the UQSUB16 operation. | |
122 | UNSPEC_SMUSD ; Represent the SMUSD operation. | |
123 | UNSPEC_SMUSDX ; Represent the SMUSDX operation. | |
124 | UNSPEC_USAD8 ; Represent the USAD8 operation. | |
125 | UNSPEC_USADA8 ; Represent the USADA8 operation. | |
2b5b5e24 KT |
126 | UNSPEC_SMLALD ; Represent the SMLALD operation. |
127 | UNSPEC_SMLALDX ; Represent the SMLALDX operation. | |
128 | UNSPEC_SMLSLD ; Represent the SMLSLD operation. | |
129 | UNSPEC_SMLSLDX ; Represent the SMLSLDX operation. | |
79739965 KT |
130 | ]) |
131 | ||
53cd0ac6 | 132 | |
79739965 KT |
133 | (define_c_enum "unspec" [ |
134 | UNSPEC_WADDC ; Used by the intrinsic form of the iWMMXt WADDC instruction. | |
135 | UNSPEC_WABS ; Used by the intrinsic form of the iWMMXt WABS instruction. | |
136 | UNSPEC_WQMULWMR ; Used by the intrinsic form of the iWMMXt WQMULWMR instruction. | |
137 | UNSPEC_WQMULMR ; Used by the intrinsic form of the iWMMXt WQMULMR instruction. | |
138 | UNSPEC_WQMULWM ; Used by the intrinsic form of the iWMMXt WQMULWM instruction. | |
139 | UNSPEC_WQMULM ; Used by the intrinsic form of the iWMMXt WQMULM instruction. | |
140 | UNSPEC_WQMIAxyn ; Used by the intrinsic form of the iWMMXt WMIAxyn instruction. | |
141 | UNSPEC_WQMIAxy ; Used by the intrinsic form of the iWMMXt WMIAxy instruction. | |
142 | UNSPEC_TANDC ; Used by the intrinsic form of the iWMMXt TANDC instruction. | |
143 | UNSPEC_TORC ; Used by the intrinsic form of the iWMMXt TORC instruction. | |
144 | UNSPEC_TORVSC ; Used by the intrinsic form of the iWMMXt TORVSC instruction. | |
145 | UNSPEC_TEXTRC ; Used by the intrinsic form of the iWMMXt TEXTRC instruction. | |
146 | ]) | |
147 | ||
148 | ||
149 | ;; UNSPEC_VOLATILE Usage: | |
150 | ||
151 | (define_c_enum "unspecv" [ | |
152 | VUNSPEC_BLOCKAGE ; `blockage' insn to prevent scheduling across an | |
153 | ; insn in the code. | |
154 | VUNSPEC_EPILOGUE ; `epilogue' insn, used to represent any part of the | |
155 | ; instruction epilogue sequence that isn't expanded | |
156 | ; into normal RTL. Used for both normal and sibcall | |
157 | ; epilogues. | |
158 | VUNSPEC_THUMB1_INTERWORK ; `prologue_thumb1_interwork' insn, used to swap | |
159 | ; modes from arm to thumb. | |
160 | VUNSPEC_ALIGN ; `align' insn. Used at the head of a minipool table | |
161 | ; for inlined constants. | |
162 | VUNSPEC_POOL_END ; `end-of-table'. Used to mark the end of a minipool | |
163 | ; table. | |
164 | VUNSPEC_POOL_1 ; `pool-entry(1)'. An entry in the constant pool for | |
165 | ; an 8-bit object. | |
166 | VUNSPEC_POOL_2 ; `pool-entry(2)'. An entry in the constant pool for | |
167 | ; a 16-bit object. | |
168 | VUNSPEC_POOL_4 ; `pool-entry(4)'. An entry in the constant pool for | |
169 | ; a 32-bit object. | |
170 | VUNSPEC_POOL_8 ; `pool-entry(8)'. An entry in the constant pool for | |
171 | ; a 64-bit object. | |
172 | VUNSPEC_POOL_16 ; `pool-entry(16)'. An entry in the constant pool for | |
173 | ; a 128-bit object. | |
174 | VUNSPEC_TMRC ; Used by the iWMMXt TMRC instruction. | |
175 | VUNSPEC_TMCR ; Used by the iWMMXt TMCR instruction. | |
176 | VUNSPEC_ALIGN8 ; 8-byte alignment version of VUNSPEC_ALIGN | |
177 | VUNSPEC_WCMP_EQ ; Used by the iWMMXt WCMPEQ instructions | |
178 | VUNSPEC_WCMP_GTU ; Used by the iWMMXt WCMPGTU instructions | |
179 | VUNSPEC_WCMP_GT ; Used by the iwMMXT WCMPGT instructions | |
180 | VUNSPEC_EH_RETURN ; Use to override the return address for exception | |
181 | ; handling. | |
182 | VUNSPEC_ATOMIC_CAS ; Represent an atomic compare swap. | |
183 | VUNSPEC_ATOMIC_XCHG ; Represent an atomic exchange. | |
184 | VUNSPEC_ATOMIC_OP ; Represent an atomic operation. | |
185 | VUNSPEC_LL ; Represent a load-register-exclusive. | |
74a00288 | 186 | VUNSPEC_LDRD_ATOMIC ; Represent an LDRD used as an atomic DImode load. |
79739965 | 187 | VUNSPEC_SC ; Represent a store-register-exclusive. |
5ad29f12 KT |
188 | VUNSPEC_LAX ; Represent a load-register-acquire-exclusive. |
189 | VUNSPEC_SLX ; Represent a store-register-release-exclusive. | |
190 | VUNSPEC_LDA ; Represent a store-register-acquire. | |
191 | VUNSPEC_STL ; Represent a store-register-release. | |
f10743d3 KV |
192 | VUNSPEC_GET_FPSCR ; Represent fetch of FPSCR content. |
193 | VUNSPEC_SET_FPSCR ; Represent assign of FPSCR content. | |
f58101cf | 194 | VUNSPEC_PROBE_STACK_RANGE ; Represent stack range probing. |
d57daa0c AV |
195 | VUNSPEC_CDP ; Represent the coprocessor cdp instruction. |
196 | VUNSPEC_CDP2 ; Represent the coprocessor cdp2 instruction. | |
3811581f AV |
197 | VUNSPEC_LDC ; Represent the coprocessor ldc instruction. |
198 | VUNSPEC_LDC2 ; Represent the coprocessor ldc2 instruction. | |
199 | VUNSPEC_LDCL ; Represent the coprocessor ldcl instruction. | |
200 | VUNSPEC_LDC2L ; Represent the coprocessor ldc2l instruction. | |
201 | VUNSPEC_STC ; Represent the coprocessor stc instruction. | |
202 | VUNSPEC_STC2 ; Represent the coprocessor stc2 instruction. | |
203 | VUNSPEC_STCL ; Represent the coprocessor stcl instruction. | |
204 | VUNSPEC_STC2L ; Represent the coprocessor stc2l instruction. | |
ecc9a25b AV |
205 | VUNSPEC_MCR ; Represent the coprocessor mcr instruction. |
206 | VUNSPEC_MCR2 ; Represent the coprocessor mcr2 instruction. | |
207 | VUNSPEC_MRC ; Represent the coprocessor mrc instruction. | |
208 | VUNSPEC_MRC2 ; Represent the coprocessor mrc2 instruction. | |
f3caa118 AV |
209 | VUNSPEC_MCRR ; Represent the coprocessor mcrr instruction. |
210 | VUNSPEC_MCRR2 ; Represent the coprocessor mcrr2 instruction. | |
211 | VUNSPEC_MRRC ; Represent the coprocessor mrrc instruction. | |
212 | VUNSPEC_MRRC2 ; Represent the coprocessor mrrc2 instruction. | |
bb8b0096 | 213 | VUNSPEC_SPECULATION_BARRIER ; Represents an unconditional speculation barrier. |
79739965 KT |
214 | ]) |
215 | ||
216 | ;; Enumerators for NEON unspecs. | |
217 | (define_c_enum "unspec" [ | |
218 | UNSPEC_ASHIFT_SIGNED | |
219 | UNSPEC_ASHIFT_UNSIGNED | |
582e2e43 KT |
220 | UNSPEC_CRC32B |
221 | UNSPEC_CRC32H | |
222 | UNSPEC_CRC32W | |
223 | UNSPEC_CRC32CB | |
224 | UNSPEC_CRC32CH | |
225 | UNSPEC_CRC32CW | |
021b5e6b KT |
226 | UNSPEC_AESD |
227 | UNSPEC_AESE | |
228 | UNSPEC_AESIMC | |
229 | UNSPEC_AESMC | |
230 | UNSPEC_SHA1C | |
231 | UNSPEC_SHA1M | |
232 | UNSPEC_SHA1P | |
233 | UNSPEC_SHA1H | |
234 | UNSPEC_SHA1SU0 | |
235 | UNSPEC_SHA1SU1 | |
236 | UNSPEC_SHA256H | |
237 | UNSPEC_SHA256H2 | |
238 | UNSPEC_SHA256SU0 | |
239 | UNSPEC_SHA256SU1 | |
240 | UNSPEC_VMULLP64 | |
79739965 | 241 | UNSPEC_LOAD_COUNT |
84ae7213 PW |
242 | UNSPEC_VABAL_S |
243 | UNSPEC_VABAL_U | |
94f0f2cc JG |
244 | UNSPEC_VABD_F |
245 | UNSPEC_VABD_S | |
246 | UNSPEC_VABD_U | |
247 | UNSPEC_VABDL_S | |
248 | UNSPEC_VABDL_U | |
79739965 KT |
249 | UNSPEC_VADD |
250 | UNSPEC_VADDHN | |
94f0f2cc JG |
251 | UNSPEC_VRADDHN |
252 | UNSPEC_VADDL_S | |
253 | UNSPEC_VADDL_U | |
254 | UNSPEC_VADDW_S | |
255 | UNSPEC_VADDW_U | |
79739965 KT |
256 | UNSPEC_VBSL |
257 | UNSPEC_VCAGE | |
258 | UNSPEC_VCAGT | |
55a9b91b MW |
259 | UNSPEC_VCALE |
260 | UNSPEC_VCALT | |
79739965 KT |
261 | UNSPEC_VCEQ |
262 | UNSPEC_VCGE | |
263 | UNSPEC_VCGEU | |
264 | UNSPEC_VCGT | |
265 | UNSPEC_VCGTU | |
266 | UNSPEC_VCLS | |
267 | UNSPEC_VCONCAT | |
268 | UNSPEC_VCVT | |
94f0f2cc JG |
269 | UNSPEC_VCVT_S |
270 | UNSPEC_VCVT_U | |
271 | UNSPEC_VCVT_S_N | |
272 | UNSPEC_VCVT_U_N | |
d403b8d4 MW |
273 | UNSPEC_VCVT_HF_S_N |
274 | UNSPEC_VCVT_HF_U_N | |
275 | UNSPEC_VCVT_SI_S_N | |
276 | UNSPEC_VCVT_SI_U_N | |
277 | UNSPEC_VCVTH_S | |
278 | UNSPEC_VCVTH_U | |
279 | UNSPEC_VCVTA_S | |
280 | UNSPEC_VCVTA_U | |
281 | UNSPEC_VCVTM_S | |
282 | UNSPEC_VCVTM_U | |
283 | UNSPEC_VCVTN_S | |
284 | UNSPEC_VCVTN_U | |
285 | UNSPEC_VCVTP_S | |
286 | UNSPEC_VCVTP_U | |
79739965 | 287 | UNSPEC_VEXT |
94f0f2cc JG |
288 | UNSPEC_VHADD_S |
289 | UNSPEC_VHADD_U | |
290 | UNSPEC_VRHADD_S | |
291 | UNSPEC_VRHADD_U | |
292 | UNSPEC_VHSUB_S | |
293 | UNSPEC_VHSUB_U | |
79739965 KT |
294 | UNSPEC_VLD1 |
295 | UNSPEC_VLD1_LANE | |
296 | UNSPEC_VLD2 | |
297 | UNSPEC_VLD2_DUP | |
298 | UNSPEC_VLD2_LANE | |
299 | UNSPEC_VLD3 | |
300 | UNSPEC_VLD3A | |
301 | UNSPEC_VLD3B | |
302 | UNSPEC_VLD3_DUP | |
303 | UNSPEC_VLD3_LANE | |
304 | UNSPEC_VLD4 | |
305 | UNSPEC_VLD4A | |
306 | UNSPEC_VLD4B | |
307 | UNSPEC_VLD4_DUP | |
308 | UNSPEC_VLD4_LANE | |
309 | UNSPEC_VMAX | |
94f0f2cc | 310 | UNSPEC_VMAX_U |
0a18c19f | 311 | UNSPEC_VMAXNM |
79739965 | 312 | UNSPEC_VMIN |
94f0f2cc | 313 | UNSPEC_VMIN_U |
0a18c19f | 314 | UNSPEC_VMINNM |
79739965 | 315 | UNSPEC_VMLA |
79739965 | 316 | UNSPEC_VMLA_LANE |
94f0f2cc JG |
317 | UNSPEC_VMLAL_S |
318 | UNSPEC_VMLAL_U | |
319 | UNSPEC_VMLAL_S_LANE | |
320 | UNSPEC_VMLAL_U_LANE | |
79739965 | 321 | UNSPEC_VMLS |
79739965 | 322 | UNSPEC_VMLS_LANE |
94f0f2cc JG |
323 | UNSPEC_VMLSL_S |
324 | UNSPEC_VMLSL_U | |
325 | UNSPEC_VMLSL_S_LANE | |
326 | UNSPEC_VMLSL_U_LANE | |
79739965 | 327 | UNSPEC_VMLSL_LANE |
55a9b91b MW |
328 | UNSPEC_VFMA_LANE |
329 | UNSPEC_VFMS_LANE | |
94f0f2cc JG |
330 | UNSPEC_VMOVL_S |
331 | UNSPEC_VMOVL_U | |
79739965 KT |
332 | UNSPEC_VMOVN |
333 | UNSPEC_VMUL | |
94f0f2cc JG |
334 | UNSPEC_VMULL_P |
335 | UNSPEC_VMULL_S | |
336 | UNSPEC_VMULL_U | |
79739965 | 337 | UNSPEC_VMUL_LANE |
94f0f2cc JG |
338 | UNSPEC_VMULL_S_LANE |
339 | UNSPEC_VMULL_U_LANE | |
340 | UNSPEC_VPADAL_S | |
341 | UNSPEC_VPADAL_U | |
79739965 | 342 | UNSPEC_VPADD |
94f0f2cc JG |
343 | UNSPEC_VPADDL_S |
344 | UNSPEC_VPADDL_U | |
79739965 | 345 | UNSPEC_VPMAX |
94f0f2cc | 346 | UNSPEC_VPMAX_U |
79739965 | 347 | UNSPEC_VPMIN |
94f0f2cc | 348 | UNSPEC_VPMIN_U |
79739965 KT |
349 | UNSPEC_VPSMAX |
350 | UNSPEC_VPSMIN | |
351 | UNSPEC_VPUMAX | |
352 | UNSPEC_VPUMIN | |
353 | UNSPEC_VQABS | |
94f0f2cc JG |
354 | UNSPEC_VQADD_S |
355 | UNSPEC_VQADD_U | |
79739965 KT |
356 | UNSPEC_VQDMLAL |
357 | UNSPEC_VQDMLAL_LANE | |
358 | UNSPEC_VQDMLSL | |
359 | UNSPEC_VQDMLSL_LANE | |
360 | UNSPEC_VQDMULH | |
361 | UNSPEC_VQDMULH_LANE | |
94f0f2cc JG |
362 | UNSPEC_VQRDMULH |
363 | UNSPEC_VQRDMULH_LANE | |
79739965 KT |
364 | UNSPEC_VQDMULL |
365 | UNSPEC_VQDMULL_LANE | |
94f0f2cc JG |
366 | UNSPEC_VQMOVN_S |
367 | UNSPEC_VQMOVN_U | |
79739965 KT |
368 | UNSPEC_VQMOVUN |
369 | UNSPEC_VQNEG | |
94f0f2cc JG |
370 | UNSPEC_VQSHL_S |
371 | UNSPEC_VQSHL_U | |
372 | UNSPEC_VQRSHL_S | |
373 | UNSPEC_VQRSHL_U | |
374 | UNSPEC_VQSHL_S_N | |
375 | UNSPEC_VQSHL_U_N | |
79739965 | 376 | UNSPEC_VQSHLU_N |
94f0f2cc JG |
377 | UNSPEC_VQSHRN_S_N |
378 | UNSPEC_VQSHRN_U_N | |
379 | UNSPEC_VQRSHRN_S_N | |
380 | UNSPEC_VQRSHRN_U_N | |
79739965 | 381 | UNSPEC_VQSHRUN_N |
94f0f2cc JG |
382 | UNSPEC_VQRSHRUN_N |
383 | UNSPEC_VQSUB_S | |
384 | UNSPEC_VQSUB_U | |
79739965 KT |
385 | UNSPEC_VRECPE |
386 | UNSPEC_VRECPS | |
387 | UNSPEC_VREV16 | |
388 | UNSPEC_VREV32 | |
389 | UNSPEC_VREV64 | |
390 | UNSPEC_VRSQRTE | |
391 | UNSPEC_VRSQRTS | |
94f0f2cc JG |
392 | UNSPEC_VSHL_S |
393 | UNSPEC_VSHL_U | |
394 | UNSPEC_VRSHL_S | |
395 | UNSPEC_VRSHL_U | |
396 | UNSPEC_VSHLL_S_N | |
397 | UNSPEC_VSHLL_U_N | |
79739965 | 398 | UNSPEC_VSHL_N |
94f0f2cc JG |
399 | UNSPEC_VSHR_S_N |
400 | UNSPEC_VSHR_U_N | |
401 | UNSPEC_VRSHR_S_N | |
402 | UNSPEC_VRSHR_U_N | |
79739965 | 403 | UNSPEC_VSHRN_N |
94f0f2cc | 404 | UNSPEC_VRSHRN_N |
79739965 | 405 | UNSPEC_VSLI |
94f0f2cc JG |
406 | UNSPEC_VSRA_S_N |
407 | UNSPEC_VSRA_U_N | |
408 | UNSPEC_VRSRA_S_N | |
409 | UNSPEC_VRSRA_U_N | |
79739965 KT |
410 | UNSPEC_VSRI |
411 | UNSPEC_VST1 | |
412 | UNSPEC_VST1_LANE | |
413 | UNSPEC_VST2 | |
414 | UNSPEC_VST2_LANE | |
415 | UNSPEC_VST3 | |
416 | UNSPEC_VST3A | |
417 | UNSPEC_VST3B | |
418 | UNSPEC_VST3_LANE | |
419 | UNSPEC_VST4 | |
420 | UNSPEC_VST4A | |
421 | UNSPEC_VST4B | |
422 | UNSPEC_VST4_LANE | |
423 | UNSPEC_VSTRUCTDUMMY | |
424 | UNSPEC_VSUB | |
425 | UNSPEC_VSUBHN | |
94f0f2cc JG |
426 | UNSPEC_VRSUBHN |
427 | UNSPEC_VSUBL_S | |
428 | UNSPEC_VSUBL_U | |
429 | UNSPEC_VSUBW_S | |
430 | UNSPEC_VSUBW_U | |
79739965 KT |
431 | UNSPEC_VTBL |
432 | UNSPEC_VTBX | |
433 | UNSPEC_VTRN1 | |
434 | UNSPEC_VTRN2 | |
435 | UNSPEC_VTST | |
436 | UNSPEC_VUZP1 | |
437 | UNSPEC_VUZP2 | |
438 | UNSPEC_VZIP1 | |
439 | UNSPEC_VZIP2 | |
440 | UNSPEC_MISALIGNED_ACCESS | |
441 | UNSPEC_VCLE | |
442 | UNSPEC_VCLT | |
443 | UNSPEC_NVRINTZ | |
444 | UNSPEC_NVRINTP | |
445 | UNSPEC_NVRINTM | |
446 | UNSPEC_NVRINTX | |
447 | UNSPEC_NVRINTA | |
448 | UNSPEC_NVRINTN | |
5f2ca3b2 MW |
449 | UNSPEC_VQRDMLAH |
450 | UNSPEC_VQRDMLSH | |
d403b8d4 MW |
451 | UNSPEC_VRND |
452 | UNSPEC_VRNDA | |
453 | UNSPEC_VRNDI | |
454 | UNSPEC_VRNDM | |
455 | UNSPEC_VRNDN | |
456 | UNSPEC_VRNDP | |
457 | UNSPEC_VRNDX | |
f8e109ba TC |
458 | UNSPEC_DOT_S |
459 | UNSPEC_DOT_U | |
06e95715 KT |
460 | UNSPEC_VFML_LO |
461 | UNSPEC_VFML_HI | |
c2b7062d TC |
462 | UNSPEC_VCADD90 |
463 | UNSPEC_VCADD270 | |
464 | UNSPEC_VCMLA | |
465 | UNSPEC_VCMLA90 | |
466 | UNSPEC_VCMLA180 | |
467 | UNSPEC_VCMLA270 | |
79739965 | 468 | ]) |