projects / thirdparty / gcc.git / blame
| Commit | Line | Data |
|---|---|---|
| 9b66ebb1 | 1 | ;; ARM VFP coprocessor Machine Description |
| 5b3e6663 | 2 | ;; Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc. |
| 9b66ebb1 PB |
3 | ;; Written by CodeSourcery, LLC. |
| 4 | ;; | |
| 5 | ;; This file is part of GCC. | |
| 6 | ;; | |
| 7 | ;; GCC is free software; you can redistribute it and/or modify it | |
| 8 | ;; under the terms of the GNU General Public License as published by | |
| 9 | ;; the Free Software Foundation; either version 2, or (at your option) | |
| 10 | ;; any later version. | |
| 11 | ;; | |
| 12 | ;; GCC is distributed in the hope that it will be useful, but | |
| 13 | ;; WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 15 | ;; General Public License for more details. | |
| 16 | ;; | |
| 17 | ;; You should have received a copy of the GNU General Public License | |
| 18 | ;; along with GCC; see the file COPYING. If not, write to the Free | |
| 39d14dda KC |
19 | ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA |
| 20 | ;; 02110-1301, USA. */ | |
| 9b66ebb1 PB |
21 | |
| 22 | ;; Additional register numbers | |
| 23 | (define_constants | |
| 24 | [(VFPCC_REGNUM 95)] | |
| 25 | ) | |
| 26 | ||
| 27 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 28 | ;; Pipeline description | |
| 29 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 30 | ||
| 31 | (define_automaton "vfp11") | |
| 32 | ||
| 33 | ;; There are 3 pipelines in the VFP11 unit. | |
| 34 | ;; | |
| 35 | ;; - A 8-stage FMAC pipeline (7 execute + writeback) with forward from | |
| 36 | ;; fourth stage for simple operations. | |
| 37 | ;; | |
| 38 | ;; - A 5-stage DS pipeline (4 execute + writeback) for divide/sqrt insns. | |
| 39 | ;; These insns also uses first execute stage of FMAC pipeline. | |
| 40 | ;; | |
| 41 | ;; - A 4-stage LS pipeline (execute + 2 memory + writeback) with forward from | |
| 42 | ;; second memory stage for loads. | |
| 43 | ||
| 44 | ;; We do not model Write-After-Read hazards. | |
| 59b9a953 KH |
45 | ;; We do not do write scheduling with the arm core, so it is only necessary |
| 46 | ;; to model the first stage of each pipeline | |
| 9b66ebb1 | 47 | ;; ??? Need to model LS pipeline properly for load/store multiple? |
| 59b9a953 | 48 | ;; We do not model fmstat properly. This could be done by modeling pipelines |
| 9b66ebb1 PB |
49 | ;; properly and defining an absence set between a dummy fmstat unit and all |
| 50 | ;; other vfp units. | |
| 51 | ||
| 52 | (define_cpu_unit "fmac" "vfp11") | |
| 53 | ||
| 54 | (define_cpu_unit "ds" "vfp11") | |
| 55 | ||
| 56 | (define_cpu_unit "vfp_ls" "vfp11") | |
| 57 | ||
| 75fe7b2f RE |
58 | (define_cpu_unit "fmstat" "vfp11") |
| 59 | ||
| 60 | (exclusion_set "fmac,ds" "fmstat") | |
| 61 | ||
| 9b66ebb1 | 62 | ;; The VFP "type" attributes differ from those used in the FPA model. |
| 112cdef5 | 63 | ;; ffarith Fast floating point insns, e.g. abs, neg, cpy, cmp. |
| 9b66ebb1 | 64 | ;; farith Most arithmetic insns. |
| 59b9a953 | 65 | ;; fmul Double precision multiply. |
| 9b66ebb1 PB |
66 | ;; fdivs Single precision sqrt or division. |
| 67 | ;; fdivd Double precision sqrt or division. | |
| 75fe7b2f RE |
68 | ;; f_flag fmstat operation |
| 69 | ;; f_load[sd] Floating point load from memory. | |
| 70 | ;; f_store[sd] Floating point store to memory. | |
| 9b66ebb1 PB |
71 | ;; f_2_r Transfer vfp to arm reg. |
| 72 | ;; r_2_f Transfer arm to vfp reg. | |
| 75fe7b2f | 73 | ;; f_cvt Convert floating<->integral |
| 9b66ebb1 PB |
74 | |
| 75 | (define_insn_reservation "vfp_ffarith" 4 | |
| 75fe7b2f | 76 | (and (eq_attr "generic_vfp" "yes") |
| 9b66ebb1 PB |
77 | (eq_attr "type" "ffarith")) |
| 78 | "fmac") | |
| 79 | ||
| 80 | (define_insn_reservation "vfp_farith" 8 | |
| 75fe7b2f RE |
81 | (and (eq_attr "generic_vfp" "yes") |
| 82 | (eq_attr "type" "farith,f_cvt")) | |
| 9b66ebb1 PB |
83 | "fmac") |
| 84 | ||
| 85 | (define_insn_reservation "vfp_fmul" 9 | |
| 75fe7b2f | 86 | (and (eq_attr "generic_vfp" "yes") |
| 9b66ebb1 PB |
87 | (eq_attr "type" "fmul")) |
| 88 | "fmac*2") | |
| 89 | ||
| 90 | (define_insn_reservation "vfp_fdivs" 19 | |
| 75fe7b2f | 91 | (and (eq_attr "generic_vfp" "yes") |
| 9b66ebb1 PB |
92 | (eq_attr "type" "fdivs")) |
| 93 | "ds*15") | |
| 94 | ||
| 95 | (define_insn_reservation "vfp_fdivd" 33 | |
| 75fe7b2f | 96 | (and (eq_attr "generic_vfp" "yes") |
| 9b66ebb1 PB |
97 | (eq_attr "type" "fdivd")) |
| 98 | "fmac+ds*29") | |
| 99 | ||
| 100 | ;; Moves to/from arm regs also use the load/store pipeline. | |
| 101 | (define_insn_reservation "vfp_fload" 4 | |
| 75fe7b2f RE |
102 | (and (eq_attr "generic_vfp" "yes") |
| 103 | (eq_attr "type" "f_loads,f_loadd,r_2_f")) | |
| 9b66ebb1 PB |
104 | "vfp_ls") |
| 105 | ||
| 106 | (define_insn_reservation "vfp_fstore" 4 | |
| 75fe7b2f RE |
107 | (and (eq_attr "generic_vfp" "yes") |
| 108 | (eq_attr "type" "f_stores,f_stored,f_2_r")) | |
| 9b66ebb1 PB |
109 | "vfp_ls") |
| 110 | ||
| 75fe7b2f RE |
111 | (define_insn_reservation "vfp_to_cpsr" 4 |
| 112 | (and (eq_attr "generic_vfp" "yes") | |
| 113 | (eq_attr "type" "f_flag")) | |
| 114 | "fmstat,vfp_ls*3") | |
| 9b66ebb1 PB |
115 | |
| 116 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 59b9a953 | 117 | ;; Insn pattern |
| 9b66ebb1 PB |
118 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| 119 | ||
| 120 | ;; SImode moves | |
| 121 | ;; ??? For now do not allow loading constants into vfp regs. This causes | |
| 59b9a953 | 122 | ;; problems because small constants get converted into adds. |
| 9b66ebb1 | 123 | (define_insn "*arm_movsi_vfp" |
| 5b3e6663 PB |
124 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r ,m,*w,r,*w,*w, *Uv") |
| 125 | (match_operand:SI 1 "general_operand" "rI,K,N,mi,r,r,*w,*w,*Uvi,*w"))] | |
| 9b66ebb1 PB |
126 | "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT |
| 127 | && ( s_register_operand (operands[0], SImode) | |
| 128 | || s_register_operand (operands[1], SImode))" | |
| 5b3e6663 PB |
129 | "* |
| 130 | switch (which_alternative) | |
| 131 | { | |
| 132 | case 0: | |
| 133 | return \"mov%?\\t%0, %1\"; | |
| 134 | case 1: | |
| 135 | return \"mvn%?\\t%0, #%B1\"; | |
| 136 | case 2: | |
| 137 | return \"movw%?\\t%0, %1\"; | |
| 138 | case 3: | |
| 139 | return \"ldr%?\\t%0, %1\"; | |
| 140 | case 4: | |
| 141 | return \"str%?\\t%1, %0\"; | |
| 142 | case 5: | |
| 143 | return \"fmsr%?\\t%0, %1\\t%@ int\"; | |
| 144 | case 6: | |
| 145 | return \"fmrs%?\\t%0, %1\\t%@ int\"; | |
| 146 | case 7: | |
| 147 | return \"fcpys%?\\t%0, %1\\t%@ int\"; | |
| 148 | case 8: case 9: | |
| 149 | return output_move_vfp (operands); | |
| 150 | default: | |
| 151 | gcc_unreachable (); | |
| 152 | } | |
| 153 | " | |
| 154 | [(set_attr "predicable" "yes") | |
| 155 | (set_attr "type" "*,*,*,load1,store1,r_2_f,f_2_r,ffarith,f_loads,f_stores") | |
| 156 | (set_attr "pool_range" "*,*,*,4096,*,*,*,*,1020,*") | |
| 157 | (set_attr "neg_pool_range" "*,*,*,4084,*,*,*,*,1008,*")] | |
| 158 | ) | |
| 159 | ||
| 160 | (define_insn "*thumb2_movsi_vfp" | |
| 161 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*w,r,*w,*w, *Uv") | |
| 162 | (match_operand:SI 1 "general_operand" "rI,K,N,mi,r,r,*w,*w,*Uvi,*w"))] | |
| 163 | "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT | |
| 164 | && ( s_register_operand (operands[0], SImode) | |
| 165 | || s_register_operand (operands[1], SImode))" | |
| 166 | "* | |
| 167 | switch (which_alternative) | |
| 168 | { | |
| 169 | case 0: | |
| 170 | return \"mov%?\\t%0, %1\"; | |
| 171 | case 1: | |
| 172 | return \"mvn%?\\t%0, #%B1\"; | |
| 173 | case 2: | |
| 174 | return \"movw%?\\t%0, %1\"; | |
| 175 | case 3: | |
| 176 | return \"ldr%?\\t%0, %1\"; | |
| 177 | case 4: | |
| 178 | return \"str%?\\t%1, %0\"; | |
| 179 | case 5: | |
| 180 | return \"fmsr%?\\t%0, %1\\t%@ int\"; | |
| 181 | case 6: | |
| 182 | return \"fmrs%?\\t%0, %1\\t%@ int\"; | |
| 183 | case 7: | |
| 184 | return \"fcpys%?\\t%0, %1\\t%@ int\"; | |
| 185 | case 8: case 9: | |
| 186 | return output_move_vfp (operands); | |
| 187 | default: | |
| 188 | gcc_unreachable (); | |
| 189 | } | |
| 190 | " | |
| 9b66ebb1 | 191 | [(set_attr "predicable" "yes") |
| 5b3e6663 PB |
192 | (set_attr "type" "*,*,*,load1,store1,r_2_f,f_2_r,ffarith,f_load,f_store") |
| 193 | (set_attr "pool_range" "*,*,*,4096,*,*,*,*,1020,*") | |
| 194 | (set_attr "neg_pool_range" "*,*,*, 0,*,*,*,*,1008,*")] | |
| 9b66ebb1 PB |
195 | ) |
| 196 | ||
| 197 | ||
| 198 | ;; DImode moves | |
| 199 | ||
| 200 | (define_insn "*arm_movdi_vfp" | |
| fdd695fd PB |
201 | [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv") |
| 202 | (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))] | |
| d5b6e637 PB |
203 | "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP |
| 204 | && ( register_operand (operands[0], DImode) | |
| 205 | || register_operand (operands[1], DImode))" | |
| 9b66ebb1 PB |
206 | "* |
| 207 | switch (which_alternative) | |
| 208 | { | |
| 9b901d50 RE |
209 | case 0: |
| 210 | return \"#\"; | |
| 211 | case 1: | |
| 212 | case 2: | |
| 213 | return output_move_double (operands); | |
| 9b66ebb1 | 214 | case 3: |
| 94634f14 | 215 | return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\"; |
| 9b66ebb1 | 216 | case 4: |
| 94634f14 | 217 | return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\"; |
| 9b66ebb1 PB |
218 | case 5: |
| 219 | return \"fcpyd%?\\t%P0, %P1\\t%@ int\"; | |
| 5b3e6663 PB |
220 | case 6: case 7: |
| 221 | return output_move_vfp (operands); | |
| 9b66ebb1 | 222 | default: |
| e6d29d15 | 223 | gcc_unreachable (); |
| 9b66ebb1 PB |
224 | } |
| 225 | " | |
| 75fe7b2f | 226 | [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarith,f_loadd,f_stored") |
| 9b66ebb1 PB |
227 | (set_attr "length" "8,8,8,4,4,4,4,4") |
| 228 | (set_attr "pool_range" "*,1020,*,*,*,*,1020,*") | |
| 229 | (set_attr "neg_pool_range" "*,1008,*,*,*,*,1008,*")] | |
| 230 | ) | |
| 231 | ||
| 5b3e6663 PB |
232 | (define_insn "*thumb2_movdi_vfp" |
| 233 | [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv") | |
| 234 | (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))] | |
| 235 | "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 236 | "* | |
| 237 | switch (which_alternative) | |
| 238 | { | |
| 239 | case 0: case 1: case 2: | |
| 240 | return (output_move_double (operands)); | |
| 241 | case 3: | |
| 242 | return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\"; | |
| 243 | case 4: | |
| 244 | return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\"; | |
| 245 | case 5: | |
| 246 | return \"fcpyd%?\\t%P0, %P1\\t%@ int\"; | |
| 247 | case 6: case 7: | |
| 248 | return output_move_vfp (operands); | |
| 249 | default: | |
| 250 | abort (); | |
| 251 | } | |
| 252 | " | |
| 253 | [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarith,f_load,f_store") | |
| 254 | (set_attr "length" "8,8,8,4,4,4,4,4") | |
| 255 | (set_attr "pool_range" "*,4096,*,*,*,*,1020,*") | |
| 256 | (set_attr "neg_pool_range" "*, 0,*,*,*,*,1008,*")] | |
| 257 | ) | |
| 258 | ||
| 9b66ebb1 PB |
259 | |
| 260 | ;; SFmode moves | |
| 221b2a64 PB |
261 | ;; Disparage the w<->r cases because reloading an invalid address is |
| 262 | ;; preferable to loading the value via integer registers. | |
| 9b66ebb1 PB |
263 | |
| 264 | (define_insn "*movsf_vfp" | |
| 221b2a64 PB |
265 | [(set (match_operand:SF 0 "nonimmediate_operand" "=w,?r,w ,Uv,r ,m,w,r") |
| 266 | (match_operand:SF 1 "general_operand" " ?r,w,UvE,w, mE,r,w,r"))] | |
| 9b66ebb1 PB |
267 | "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP |
| 268 | && ( s_register_operand (operands[0], SFmode) | |
| 269 | || s_register_operand (operands[1], SFmode))" | |
| 5b3e6663 PB |
270 | "* |
| 271 | switch (which_alternative) | |
| 272 | { | |
| 273 | case 0: | |
| 274 | return \"fmsr%?\\t%0, %1\"; | |
| 275 | case 1: | |
| 276 | return \"fmrs%?\\t%0, %1\"; | |
| 277 | case 2: case 3: | |
| 278 | return output_move_vfp (operands); | |
| 279 | case 4: | |
| 280 | return \"ldr%?\\t%0, %1\\t%@ float\"; | |
| 281 | case 5: | |
| 282 | return \"str%?\\t%1, %0\\t%@ float\"; | |
| 283 | case 6: | |
| 284 | return \"fcpys%?\\t%0, %1\"; | |
| 285 | case 7: | |
| 286 | return \"mov%?\\t%0, %1\\t%@ float\"; | |
| 287 | default: | |
| 288 | gcc_unreachable (); | |
| 289 | } | |
| 290 | " | |
| 9b66ebb1 | 291 | [(set_attr "predicable" "yes") |
| 75fe7b2f | 292 | (set_attr "type" "r_2_f,f_2_r,ffarith,*,f_loads,f_stores,load1,store1") |
| 9b66ebb1 PB |
293 | (set_attr "pool_range" "*,*,1020,*,4096,*,*,*") |
| 294 | (set_attr "neg_pool_range" "*,*,1008,*,4080,*,*,*")] | |
| 295 | ) | |
| 296 | ||
| 5b3e6663 PB |
297 | (define_insn "*thumb2_movsf_vfp" |
| 298 | [(set (match_operand:SF 0 "nonimmediate_operand" "=w,?r,w ,Uv,r ,m,w,r") | |
| 299 | (match_operand:SF 1 "general_operand" " ?r,w,UvE,w, mE,r,w,r"))] | |
| 300 | "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP | |
| 301 | && ( s_register_operand (operands[0], SFmode) | |
| 302 | || s_register_operand (operands[1], SFmode))" | |
| 303 | "* | |
| 304 | switch (which_alternative) | |
| 305 | { | |
| 306 | case 0: | |
| 307 | return \"fmsr%?\\t%0, %1\"; | |
| 308 | case 1: | |
| 309 | return \"fmrs%?\\t%0, %1\"; | |
| 310 | case 2: case 3: | |
| 311 | return output_move_vfp (operands); | |
| 312 | case 4: | |
| 313 | return \"ldr%?\\t%0, %1\\t%@ float\"; | |
| 314 | case 5: | |
| 315 | return \"str%?\\t%1, %0\\t%@ float\"; | |
| 316 | case 6: | |
| 317 | return \"fcpys%?\\t%0, %1\"; | |
| 318 | case 7: | |
| 319 | return \"mov%?\\t%0, %1\\t%@ float\"; | |
| 320 | default: | |
| 321 | gcc_unreachable (); | |
| 322 | } | |
| 323 | " | |
| 324 | [(set_attr "predicable" "yes") | |
| 325 | (set_attr "type" "r_2_f,f_2_r,ffarith,*,f_load,f_store,load1,store1") | |
| 326 | (set_attr "pool_range" "*,*,1020,*,4092,*,*,*") | |
| 327 | (set_attr "neg_pool_range" "*,*,1008,*,0,*,*,*")] | |
| 328 | ) | |
| 329 | ||
| 9b66ebb1 PB |
330 | |
| 331 | ;; DFmode moves | |
| 332 | ||
| 333 | (define_insn "*movdf_vfp" | |
| 221b2a64 PB |
334 | [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,r, m,w ,Uv,w,r") |
| 335 | (match_operand:DF 1 "soft_df_operand" " ?r,w,mF,r,UvF,w, w,r"))] | |
| d5b6e637 PB |
336 | "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP |
| 337 | && ( register_operand (operands[0], DFmode) | |
| 338 | || register_operand (operands[1], DFmode))" | |
| 9b66ebb1 PB |
339 | "* |
| 340 | { | |
| 341 | switch (which_alternative) | |
| 342 | { | |
| 343 | case 0: | |
| 344 | return \"fmdrr%?\\t%P0, %Q1, %R1\"; | |
| 345 | case 1: | |
| 346 | return \"fmrrd%?\\t%Q0, %R0, %P1\"; | |
| 9b901d50 | 347 | case 2: case 3: |
| 9b66ebb1 | 348 | return output_move_double (operands); |
| 5b3e6663 PB |
349 | case 4: case 5: |
| 350 | return output_move_vfp (operands); | |
| 9b66ebb1 PB |
351 | case 6: |
| 352 | return \"fcpyd%?\\t%P0, %P1\"; | |
| 9b901d50 RE |
353 | case 7: |
| 354 | return \"#\"; | |
| 9b66ebb1 | 355 | default: |
| e6d29d15 | 356 | gcc_unreachable (); |
| 9b66ebb1 PB |
357 | } |
| 358 | } | |
| 359 | " | |
| 75fe7b2f | 360 | [(set_attr "type" "r_2_f,f_2_r,ffarith,*,load2,store2,f_loadd,f_stored") |
| 9b66ebb1 PB |
361 | (set_attr "length" "4,4,8,8,4,4,4,8") |
| 362 | (set_attr "pool_range" "*,*,1020,*,1020,*,*,*") | |
| 363 | (set_attr "neg_pool_range" "*,*,1008,*,1008,*,*,*")] | |
| 364 | ) | |
| 365 | ||
| 5b3e6663 PB |
366 | (define_insn "*thumb2_movdf_vfp" |
| 367 | [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,r, m,w ,Uv,w,r") | |
| 368 | (match_operand:DF 1 "soft_df_operand" " ?r,w,mF,r,UvF,w, w,r"))] | |
| 369 | "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 370 | "* | |
| 371 | { | |
| 372 | switch (which_alternative) | |
| 373 | { | |
| 374 | case 0: | |
| 375 | return \"fmdrr%?\\t%P0, %Q1, %R1\"; | |
| 376 | case 1: | |
| 377 | return \"fmrrd%?\\t%Q0, %R0, %P1\"; | |
| 378 | case 2: case 3: case 7: | |
| 379 | return output_move_double (operands); | |
| 380 | case 4: case 5: | |
| 381 | return output_move_vfp (operands); | |
| 382 | case 6: | |
| 383 | return \"fcpyd%?\\t%P0, %P1\"; | |
| 384 | default: | |
| 385 | abort (); | |
| 386 | } | |
| 387 | } | |
| 388 | " | |
| 389 | [(set_attr "type" "r_2_f,f_2_r,ffarith,*,load2,store2,f_load,f_store") | |
| 390 | (set_attr "length" "4,4,8,8,4,4,4,8") | |
| 391 | (set_attr "pool_range" "*,*,4096,*,1020,*,*,*") | |
| 392 | (set_attr "neg_pool_range" "*,*,0,*,1008,*,*,*")] | |
| 393 | ) | |
| 394 | ||
| 9b66ebb1 PB |
395 | |
| 396 | ;; Conditional move patterns | |
| 397 | ||
| 398 | (define_insn "*movsfcc_vfp" | |
| 399 | [(set (match_operand:SF 0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r") | |
| 400 | (if_then_else:SF | |
| 401 | (match_operator 3 "arm_comparison_operator" | |
| 402 | [(match_operand 4 "cc_register" "") (const_int 0)]) | |
| 403 | (match_operand:SF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w") | |
| 404 | (match_operand:SF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))] | |
| 405 | "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 406 | "@ | |
| 407 | fcpys%D3\\t%0, %2 | |
| 408 | fcpys%d3\\t%0, %1 | |
| 409 | fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1 | |
| 410 | fmsr%D3\\t%0, %2 | |
| 411 | fmsr%d3\\t%0, %1 | |
| 412 | fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1 | |
| 413 | fmrs%D3\\t%0, %2 | |
| 414 | fmrs%d3\\t%0, %1 | |
| 415 | fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1" | |
| 416 | [(set_attr "conds" "use") | |
| 417 | (set_attr "length" "4,4,8,4,4,8,4,4,8") | |
| 418 | (set_attr "type" "ffarith,ffarith,ffarith,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")] | |
| 419 | ) | |
| 420 | ||
| 5b3e6663 PB |
421 | (define_insn "*thumb2_movsfcc_vfp" |
| 422 | [(set (match_operand:SF 0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r") | |
| 423 | (if_then_else:SF | |
| 424 | (match_operator 3 "arm_comparison_operator" | |
| 425 | [(match_operand 4 "cc_register" "") (const_int 0)]) | |
| 426 | (match_operand:SF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w") | |
| 427 | (match_operand:SF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))] | |
| 428 | "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 429 | "@ | |
| 430 | it\\t%D3\;fcpys%D3\\t%0, %2 | |
| 431 | it\\t%d3\;fcpys%d3\\t%0, %1 | |
| 432 | ite\\t%D3\;fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1 | |
| 433 | it\\t%D3\;fmsr%D3\\t%0, %2 | |
| 434 | it\\t%d3\;fmsr%d3\\t%0, %1 | |
| 435 | ite\\t%D3\;fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1 | |
| 436 | it\\t%D3\;fmrs%D3\\t%0, %2 | |
| 437 | it\\t%d3\;fmrs%d3\\t%0, %1 | |
| 438 | ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1" | |
| 439 | [(set_attr "conds" "use") | |
| 440 | (set_attr "length" "6,6,10,6,6,10,6,6,10") | |
| 441 | (set_attr "type" "ffarith,ffarith,ffarith,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")] | |
| 442 | ) | |
| 443 | ||
| 9b66ebb1 PB |
444 | (define_insn "*movdfcc_vfp" |
| 445 | [(set (match_operand:DF 0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r") | |
| 446 | (if_then_else:DF | |
| 447 | (match_operator 3 "arm_comparison_operator" | |
| 448 | [(match_operand 4 "cc_register" "") (const_int 0)]) | |
| 449 | (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w") | |
| 450 | (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))] | |
| 451 | "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 452 | "@ | |
| 453 | fcpyd%D3\\t%P0, %P2 | |
| 454 | fcpyd%d3\\t%P0, %P1 | |
| 455 | fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1 | |
| 456 | fmdrr%D3\\t%P0, %Q2, %R2 | |
| 457 | fmdrr%d3\\t%P0, %Q1, %R1 | |
| 458 | fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1 | |
| 459 | fmrrd%D3\\t%Q0, %R0, %P2 | |
| 460 | fmrrd%d3\\t%Q0, %R0, %P1 | |
| 461 | fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1" | |
| 462 | [(set_attr "conds" "use") | |
| 463 | (set_attr "length" "4,4,8,4,4,8,4,4,8") | |
| 464 | (set_attr "type" "ffarith,ffarith,ffarith,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")] | |
| 465 | ) | |
| 466 | ||
| 5b3e6663 PB |
467 | (define_insn "*thumb2_movdfcc_vfp" |
| 468 | [(set (match_operand:DF 0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r") | |
| 469 | (if_then_else:DF | |
| 470 | (match_operator 3 "arm_comparison_operator" | |
| 471 | [(match_operand 4 "cc_register" "") (const_int 0)]) | |
| 472 | (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w") | |
| 473 | (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))] | |
| 474 | "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 475 | "@ | |
| 476 | it\\t%D3\;fcpyd%D3\\t%P0, %P2 | |
| 477 | it\\t%d3\;fcpyd%d3\\t%P0, %P1 | |
| 478 | ite\\t%D3\;fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1 | |
| 479 | it\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2 | |
| 480 | it\t%d3\;fmdrr%d3\\t%P0, %Q1, %R1 | |
| 481 | ite\\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1 | |
| 482 | it\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2 | |
| 483 | it\t%d3\;fmrrd%d3\\t%Q0, %R0, %P1 | |
| 484 | ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1" | |
| 485 | [(set_attr "conds" "use") | |
| 486 | (set_attr "length" "6,6,10,6,6,10,6,6,10") | |
| 487 | (set_attr "type" "ffarith,ffarith,ffarith,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")] | |
| 488 | ) | |
| 489 | ||
| 9b66ebb1 PB |
490 | |
| 491 | ;; Sign manipulation functions | |
| 492 | ||
| 493 | (define_insn "*abssf2_vfp" | |
| 494 | [(set (match_operand:SF 0 "s_register_operand" "=w") | |
| 495 | (abs:SF (match_operand:SF 1 "s_register_operand" "w")))] | |
| 5b3e6663 | 496 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
497 | "fabss%?\\t%0, %1" |
| 498 | [(set_attr "predicable" "yes") | |
| 499 | (set_attr "type" "ffarith")] | |
| 500 | ) | |
| 501 | ||
| 502 | (define_insn "*absdf2_vfp" | |
| 503 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
| 504 | (abs:DF (match_operand:DF 1 "s_register_operand" "w")))] | |
| 5b3e6663 | 505 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
506 | "fabsd%?\\t%P0, %P1" |
| 507 | [(set_attr "predicable" "yes") | |
| 508 | (set_attr "type" "ffarith")] | |
| 509 | ) | |
| 510 | ||
| 511 | (define_insn "*negsf2_vfp" | |
| 81632f11 RE |
512 | [(set (match_operand:SF 0 "s_register_operand" "=w,?r") |
| 513 | (neg:SF (match_operand:SF 1 "s_register_operand" "w,r")))] | |
| 5b3e6663 | 514 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 81632f11 RE |
515 | "@ |
| 516 | fnegs%?\\t%0, %1 | |
| 517 | eor%?\\t%0, %1, #-2147483648" | |
| 9b66ebb1 PB |
518 | [(set_attr "predicable" "yes") |
| 519 | (set_attr "type" "ffarith")] | |
| 520 | ) | |
| 521 | ||
| 81632f11 RE |
522 | (define_insn_and_split "*negdf2_vfp" |
| 523 | [(set (match_operand:DF 0 "s_register_operand" "=w,?r,?r") | |
| 524 | (neg:DF (match_operand:DF 1 "s_register_operand" "w,0,r")))] | |
| 5b3e6663 | 525 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 81632f11 RE |
526 | "@ |
| 527 | fnegd%?\\t%P0, %P1 | |
| 528 | # | |
| 529 | #" | |
| 5b3e6663 | 530 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && reload_completed |
| 81632f11 RE |
531 | && arm_general_register_operand (operands[0], DFmode)" |
| 532 | [(set (match_dup 0) (match_dup 1))] | |
| 533 | " | |
| 534 | if (REGNO (operands[0]) == REGNO (operands[1])) | |
| 535 | { | |
| 536 | operands[0] = gen_highpart (SImode, operands[0]); | |
| 537 | operands[1] = gen_rtx_XOR (SImode, operands[0], GEN_INT (0x80000000)); | |
| 538 | } | |
| 539 | else | |
| 540 | { | |
| 541 | rtx in_hi, in_lo, out_hi, out_lo; | |
| 542 | ||
| 543 | in_hi = gen_rtx_XOR (SImode, gen_highpart (SImode, operands[1]), | |
| 544 | GEN_INT (0x80000000)); | |
| 545 | in_lo = gen_lowpart (SImode, operands[1]); | |
| 546 | out_hi = gen_highpart (SImode, operands[0]); | |
| 547 | out_lo = gen_lowpart (SImode, operands[0]); | |
| 548 | ||
| 549 | if (REGNO (in_lo) == REGNO (out_hi)) | |
| 550 | { | |
| 551 | emit_insn (gen_rtx_SET (SImode, out_lo, in_lo)); | |
| 552 | operands[0] = out_hi; | |
| 553 | operands[1] = in_hi; | |
| 554 | } | |
| 555 | else | |
| 556 | { | |
| 557 | emit_insn (gen_rtx_SET (SImode, out_hi, in_hi)); | |
| 558 | operands[0] = out_lo; | |
| 559 | operands[1] = in_lo; | |
| 560 | } | |
| 561 | } | |
| 562 | " | |
| 9b66ebb1 | 563 | [(set_attr "predicable" "yes") |
| 81632f11 | 564 | (set_attr "length" "4,4,8") |
| 9b66ebb1 PB |
565 | (set_attr "type" "ffarith")] |
| 566 | ) | |
| 567 | ||
| 568 | ||
| 569 | ;; Arithmetic insns | |
| 570 | ||
| 571 | (define_insn "*addsf3_vfp" | |
| 572 | [(set (match_operand:SF 0 "s_register_operand" "=w") | |
| 573 | (plus:SF (match_operand:SF 1 "s_register_operand" "w") | |
| 574 | (match_operand:SF 2 "s_register_operand" "w")))] | |
| 5b3e6663 | 575 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
576 | "fadds%?\\t%0, %1, %2" |
| 577 | [(set_attr "predicable" "yes") | |
| 578 | (set_attr "type" "farith")] | |
| 579 | ) | |
| 580 | ||
| 581 | (define_insn "*adddf3_vfp" | |
| 582 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
| 583 | (plus:DF (match_operand:DF 1 "s_register_operand" "w") | |
| 584 | (match_operand:DF 2 "s_register_operand" "w")))] | |
| 5b3e6663 | 585 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
586 | "faddd%?\\t%P0, %P1, %P2" |
| 587 | [(set_attr "predicable" "yes") | |
| 588 | (set_attr "type" "farith")] | |
| 589 | ) | |
| 590 | ||
| 591 | ||
| 592 | (define_insn "*subsf3_vfp" | |
| 593 | [(set (match_operand:SF 0 "s_register_operand" "=w") | |
| 594 | (minus:SF (match_operand:SF 1 "s_register_operand" "w") | |
| 595 | (match_operand:SF 2 "s_register_operand" "w")))] | |
| 5b3e6663 | 596 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
597 | "fsubs%?\\t%0, %1, %2" |
| 598 | [(set_attr "predicable" "yes") | |
| 599 | (set_attr "type" "farith")] | |
| 600 | ) | |
| 601 | ||
| 602 | (define_insn "*subdf3_vfp" | |
| 603 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
| 604 | (minus:DF (match_operand:DF 1 "s_register_operand" "w") | |
| 605 | (match_operand:DF 2 "s_register_operand" "w")))] | |
| 5b3e6663 | 606 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
607 | "fsubd%?\\t%P0, %P1, %P2" |
| 608 | [(set_attr "predicable" "yes") | |
| 609 | (set_attr "type" "farith")] | |
| 610 | ) | |
| 611 | ||
| 612 | ||
| 613 | ;; Division insns | |
| 614 | ||
| 615 | (define_insn "*divsf3_vfp" | |
| 616 | [(set (match_operand:SF 0 "s_register_operand" "+w") | |
| 617 | (div:SF (match_operand:SF 1 "s_register_operand" "w") | |
| 618 | (match_operand:SF 2 "s_register_operand" "w")))] | |
| 5b3e6663 | 619 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
620 | "fdivs%?\\t%0, %1, %2" |
| 621 | [(set_attr "predicable" "yes") | |
| 622 | (set_attr "type" "fdivs")] | |
| 623 | ) | |
| 624 | ||
| 625 | (define_insn "*divdf3_vfp" | |
| 626 | [(set (match_operand:DF 0 "s_register_operand" "+w") | |
| 627 | (div:DF (match_operand:DF 1 "s_register_operand" "w") | |
| 628 | (match_operand:DF 2 "s_register_operand" "w")))] | |
| 5b3e6663 | 629 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
630 | "fdivd%?\\t%P0, %P1, %P2" |
| 631 | [(set_attr "predicable" "yes") | |
| 632 | (set_attr "type" "fdivd")] | |
| 633 | ) | |
| 634 | ||
| 635 | ||
| 636 | ;; Multiplication insns | |
| 637 | ||
| 638 | (define_insn "*mulsf3_vfp" | |
| 639 | [(set (match_operand:SF 0 "s_register_operand" "+w") | |
| 640 | (mult:SF (match_operand:SF 1 "s_register_operand" "w") | |
| 641 | (match_operand:SF 2 "s_register_operand" "w")))] | |
| 5b3e6663 | 642 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
643 | "fmuls%?\\t%0, %1, %2" |
| 644 | [(set_attr "predicable" "yes") | |
| 645 | (set_attr "type" "farith")] | |
| 646 | ) | |
| 647 | ||
| 648 | (define_insn "*muldf3_vfp" | |
| 649 | [(set (match_operand:DF 0 "s_register_operand" "+w") | |
| 650 | (mult:DF (match_operand:DF 1 "s_register_operand" "w") | |
| 651 | (match_operand:DF 2 "s_register_operand" "w")))] | |
| 5b3e6663 | 652 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
653 | "fmuld%?\\t%P0, %P1, %P2" |
| 654 | [(set_attr "predicable" "yes") | |
| 655 | (set_attr "type" "fmul")] | |
| 656 | ) | |
| 657 | ||
| 658 | ||
| 659 | (define_insn "*mulsf3negsf_vfp" | |
| 660 | [(set (match_operand:SF 0 "s_register_operand" "+w") | |
| 661 | (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "w")) | |
| 662 | (match_operand:SF 2 "s_register_operand" "w")))] | |
| 5b3e6663 | 663 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
664 | "fnmuls%?\\t%0, %1, %2" |
| 665 | [(set_attr "predicable" "yes") | |
| 666 | (set_attr "type" "farith")] | |
| 667 | ) | |
| 668 | ||
| 669 | (define_insn "*muldf3negdf_vfp" | |
| 670 | [(set (match_operand:DF 0 "s_register_operand" "+w") | |
| 671 | (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w")) | |
| 672 | (match_operand:DF 2 "s_register_operand" "w")))] | |
| 5b3e6663 | 673 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
674 | "fnmuld%?\\t%P0, %P1, %P2" |
| 675 | [(set_attr "predicable" "yes") | |
| 676 | (set_attr "type" "fmul")] | |
| 677 | ) | |
| 678 | ||
| 679 | ||
| 680 | ;; Multiply-accumulate insns | |
| 681 | ||
| 682 | ;; 0 = 1 * 2 + 0 | |
| 683 | (define_insn "*mulsf3addsf_vfp" | |
| 684 | [(set (match_operand:SF 0 "s_register_operand" "=w") | |
| 685 | (plus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "w") | |
| 686 | (match_operand:SF 3 "s_register_operand" "w")) | |
| 687 | (match_operand:SF 1 "s_register_operand" "0")))] | |
| 5b3e6663 | 688 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
689 | "fmacs%?\\t%0, %2, %3" |
| 690 | [(set_attr "predicable" "yes") | |
| 691 | (set_attr "type" "farith")] | |
| 692 | ) | |
| 693 | ||
| 694 | (define_insn "*muldf3adddf_vfp" | |
| 695 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
| 696 | (plus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w") | |
| 697 | (match_operand:DF 3 "s_register_operand" "w")) | |
| 698 | (match_operand:DF 1 "s_register_operand" "0")))] | |
| 5b3e6663 | 699 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
700 | "fmacd%?\\t%P0, %P2, %P3" |
| 701 | [(set_attr "predicable" "yes") | |
| 702 | (set_attr "type" "fmul")] | |
| 703 | ) | |
| 704 | ||
| 705 | ;; 0 = 1 * 2 - 0 | |
| 706 | (define_insn "*mulsf3subsf_vfp" | |
| 707 | [(set (match_operand:SF 0 "s_register_operand" "=w") | |
| 708 | (minus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "w") | |
| 709 | (match_operand:SF 3 "s_register_operand" "w")) | |
| 710 | (match_operand:SF 1 "s_register_operand" "0")))] | |
| 5b3e6663 | 711 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
712 | "fmscs%?\\t%0, %2, %3" |
| 713 | [(set_attr "predicable" "yes") | |
| 714 | (set_attr "type" "farith")] | |
| 715 | ) | |
| 716 | ||
| 717 | (define_insn "*muldf3subdf_vfp" | |
| 718 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
| 719 | (minus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w") | |
| 720 | (match_operand:DF 3 "s_register_operand" "w")) | |
| 721 | (match_operand:DF 1 "s_register_operand" "0")))] | |
| 5b3e6663 | 722 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
723 | "fmscd%?\\t%P0, %P2, %P3" |
| 724 | [(set_attr "predicable" "yes") | |
| 725 | (set_attr "type" "fmul")] | |
| 726 | ) | |
| 727 | ||
| 728 | ;; 0 = -(1 * 2) + 0 | |
| 729 | (define_insn "*mulsf3negsfaddsf_vfp" | |
| 730 | [(set (match_operand:SF 0 "s_register_operand" "=w") | |
| 731 | (minus:SF (match_operand:SF 1 "s_register_operand" "0") | |
| 732 | (mult:SF (match_operand:SF 2 "s_register_operand" "w") | |
| 733 | (match_operand:SF 3 "s_register_operand" "w"))))] | |
| 5b3e6663 | 734 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
735 | "fnmacs%?\\t%0, %2, %3" |
| 736 | [(set_attr "predicable" "yes") | |
| 737 | (set_attr "type" "farith")] | |
| 738 | ) | |
| 739 | ||
| 740 | (define_insn "*fmuldf3negdfadddf_vfp" | |
| 741 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
| 742 | (minus:DF (match_operand:DF 1 "s_register_operand" "0") | |
| 743 | (mult:DF (match_operand:DF 2 "s_register_operand" "w") | |
| 744 | (match_operand:DF 3 "s_register_operand" "w"))))] | |
| 5b3e6663 | 745 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
746 | "fnmacd%?\\t%P0, %P2, %P3" |
| 747 | [(set_attr "predicable" "yes") | |
| 748 | (set_attr "type" "fmul")] | |
| 749 | ) | |
| 750 | ||
| 751 | ||
| 752 | ;; 0 = -(1 * 2) - 0 | |
| 753 | (define_insn "*mulsf3negsfsubsf_vfp" | |
| 754 | [(set (match_operand:SF 0 "s_register_operand" "=w") | |
| 755 | (minus:SF (mult:SF | |
| 756 | (neg:SF (match_operand:SF 2 "s_register_operand" "w")) | |
| 757 | (match_operand:SF 3 "s_register_operand" "w")) | |
| 758 | (match_operand:SF 1 "s_register_operand" "0")))] | |
| 5b3e6663 | 759 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
760 | "fnmscs%?\\t%0, %2, %3" |
| 761 | [(set_attr "predicable" "yes") | |
| 762 | (set_attr "type" "farith")] | |
| 763 | ) | |
| 764 | ||
| 765 | (define_insn "*muldf3negdfsubdf_vfp" | |
| 766 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
| 767 | (minus:DF (mult:DF | |
| 768 | (neg:DF (match_operand:DF 2 "s_register_operand" "w")) | |
| 769 | (match_operand:DF 3 "s_register_operand" "w")) | |
| 770 | (match_operand:DF 1 "s_register_operand" "0")))] | |
| 5b3e6663 | 771 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
772 | "fnmscd%?\\t%P0, %P2, %P3" |
| 773 | [(set_attr "predicable" "yes") | |
| 774 | (set_attr "type" "fmul")] | |
| 775 | ) | |
| 776 | ||
| 777 | ||
| 778 | ;; Conversion routines | |
| 779 | ||
| 780 | (define_insn "*extendsfdf2_vfp" | |
| 781 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
| 782 | (float_extend:DF (match_operand:SF 1 "s_register_operand" "w")))] | |
| 5b3e6663 | 783 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
784 | "fcvtds%?\\t%P0, %1" |
| 785 | [(set_attr "predicable" "yes") | |
| 75fe7b2f | 786 | (set_attr "type" "f_cvt")] |
| 9b66ebb1 PB |
787 | ) |
| 788 | ||
| 789 | (define_insn "*truncdfsf2_vfp" | |
| 790 | [(set (match_operand:SF 0 "s_register_operand" "=w") | |
| 791 | (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))] | |
| 5b3e6663 | 792 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
793 | "fcvtsd%?\\t%0, %P1" |
| 794 | [(set_attr "predicable" "yes") | |
| 75fe7b2f | 795 | (set_attr "type" "f_cvt")] |
| 9b66ebb1 PB |
796 | ) |
| 797 | ||
| 798 | (define_insn "*truncsisf2_vfp" | |
| 799 | [(set (match_operand:SI 0 "s_register_operand" "=w") | |
| 800 | (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "w"))))] | |
| 5b3e6663 | 801 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
802 | "ftosizs%?\\t%0, %1" |
| 803 | [(set_attr "predicable" "yes") | |
| 75fe7b2f | 804 | (set_attr "type" "f_cvt")] |
| 9b66ebb1 PB |
805 | ) |
| 806 | ||
| 807 | (define_insn "*truncsidf2_vfp" | |
| 808 | [(set (match_operand:SI 0 "s_register_operand" "=w") | |
| 809 | (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))] | |
| 5b3e6663 | 810 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
811 | "ftosizd%?\\t%0, %P1" |
| 812 | [(set_attr "predicable" "yes") | |
| 75fe7b2f | 813 | (set_attr "type" "f_cvt")] |
| 9b66ebb1 PB |
814 | ) |
| 815 | ||
| 6f6c1f6d PB |
816 | |
| 817 | (define_insn "fixuns_truncsfsi2" | |
| 818 | [(set (match_operand:SI 0 "s_register_operand" "=w") | |
| 819 | (unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "w"))))] | |
| 5b3e6663 | 820 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 6f6c1f6d PB |
821 | "ftouizs%?\\t%0, %1" |
| 822 | [(set_attr "predicable" "yes") | |
| 75fe7b2f | 823 | (set_attr "type" "f_cvt")] |
| 6f6c1f6d PB |
824 | ) |
| 825 | ||
| 826 | (define_insn "fixuns_truncdfsi2" | |
| 827 | [(set (match_operand:SI 0 "s_register_operand" "=w") | |
| 828 | (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))] | |
| 5b3e6663 | 829 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 6f6c1f6d PB |
830 | "ftouizd%?\\t%0, %P1" |
| 831 | [(set_attr "predicable" "yes") | |
| 75fe7b2f | 832 | (set_attr "type" "f_cvt")] |
| 6f6c1f6d PB |
833 | ) |
| 834 | ||
| 835 | ||
| 9b66ebb1 PB |
836 | (define_insn "*floatsisf2_vfp" |
| 837 | [(set (match_operand:SF 0 "s_register_operand" "=w") | |
| 838 | (float:SF (match_operand:SI 1 "s_register_operand" "w")))] | |
| 5b3e6663 | 839 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
840 | "fsitos%?\\t%0, %1" |
| 841 | [(set_attr "predicable" "yes") | |
| 75fe7b2f | 842 | (set_attr "type" "f_cvt")] |
| 9b66ebb1 PB |
843 | ) |
| 844 | ||
| 845 | (define_insn "*floatsidf2_vfp" | |
| 846 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
| 847 | (float:DF (match_operand:SI 1 "s_register_operand" "w")))] | |
| 5b3e6663 | 848 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
849 | "fsitod%?\\t%P0, %1" |
| 850 | [(set_attr "predicable" "yes") | |
| 75fe7b2f | 851 | (set_attr "type" "f_cvt")] |
| 9b66ebb1 PB |
852 | ) |
| 853 | ||
| 854 | ||
| 6f6c1f6d PB |
855 | (define_insn "floatunssisf2" |
| 856 | [(set (match_operand:SF 0 "s_register_operand" "=w") | |
| 857 | (unsigned_float:SF (match_operand:SI 1 "s_register_operand" "w")))] | |
| 5b3e6663 | 858 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 6f6c1f6d PB |
859 | "fuitos%?\\t%0, %1" |
| 860 | [(set_attr "predicable" "yes") | |
| 75fe7b2f | 861 | (set_attr "type" "f_cvt")] |
| 6f6c1f6d PB |
862 | ) |
| 863 | ||
| 864 | (define_insn "floatunssidf2" | |
| 865 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
| 866 | (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "w")))] | |
| 5b3e6663 | 867 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 6f6c1f6d PB |
868 | "fuitod%?\\t%P0, %1" |
| 869 | [(set_attr "predicable" "yes") | |
| 75fe7b2f | 870 | (set_attr "type" "f_cvt")] |
| 6f6c1f6d PB |
871 | ) |
| 872 | ||
| 873 | ||
| 9b66ebb1 PB |
874 | ;; Sqrt insns. |
| 875 | ||
| 876 | (define_insn "*sqrtsf2_vfp" | |
| 877 | [(set (match_operand:SF 0 "s_register_operand" "=w") | |
| 878 | (sqrt:SF (match_operand:SF 1 "s_register_operand" "w")))] | |
| 5b3e6663 | 879 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
880 | "fsqrts%?\\t%0, %1" |
| 881 | [(set_attr "predicable" "yes") | |
| 882 | (set_attr "type" "fdivs")] | |
| 883 | ) | |
| 884 | ||
| 885 | (define_insn "*sqrtdf2_vfp" | |
| 886 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
| 887 | (sqrt:DF (match_operand:DF 1 "s_register_operand" "w")))] | |
| 5b3e6663 | 888 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
889 | "fsqrtd%?\\t%P0, %P1" |
| 890 | [(set_attr "predicable" "yes") | |
| 891 | (set_attr "type" "fdivd")] | |
| 892 | ) | |
| 893 | ||
| 894 | ||
| 895 | ;; Patterns to split/copy vfp condition flags. | |
| 896 | ||
| 897 | (define_insn "*movcc_vfp" | |
| 898 | [(set (reg CC_REGNUM) | |
| 899 | (reg VFPCC_REGNUM))] | |
| 5b3e6663 | 900 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
901 | "fmstat%?" |
| 902 | [(set_attr "conds" "set") | |
| 75fe7b2f | 903 | (set_attr "type" "f_flag")] |
| 9b66ebb1 PB |
904 | ) |
| 905 | ||
| 906 | (define_insn_and_split "*cmpsf_split_vfp" | |
| 907 | [(set (reg:CCFP CC_REGNUM) | |
| 908 | (compare:CCFP (match_operand:SF 0 "s_register_operand" "w") | |
| 909 | (match_operand:SF 1 "vfp_compare_operand" "wG")))] | |
| 5b3e6663 | 910 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 | 911 | "#" |
| 5b3e6663 | 912 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
913 | [(set (reg:CCFP VFPCC_REGNUM) |
| 914 | (compare:CCFP (match_dup 0) | |
| 915 | (match_dup 1))) | |
| 916 | (set (reg:CCFP CC_REGNUM) | |
| 917 | (reg:CCFP VFPCC_REGNUM))] | |
| 918 | "" | |
| 919 | ) | |
| 920 | ||
| 921 | (define_insn_and_split "*cmpsf_trap_split_vfp" | |
| 922 | [(set (reg:CCFPE CC_REGNUM) | |
| 923 | (compare:CCFPE (match_operand:SF 0 "s_register_operand" "w") | |
| 924 | (match_operand:SF 1 "vfp_compare_operand" "wG")))] | |
| 5b3e6663 | 925 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 | 926 | "#" |
| 5b3e6663 | 927 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
928 | [(set (reg:CCFPE VFPCC_REGNUM) |
| 929 | (compare:CCFPE (match_dup 0) | |
| 930 | (match_dup 1))) | |
| 931 | (set (reg:CCFPE CC_REGNUM) | |
| 932 | (reg:CCFPE VFPCC_REGNUM))] | |
| 933 | "" | |
| 934 | ) | |
| 935 | ||
| 936 | (define_insn_and_split "*cmpdf_split_vfp" | |
| 937 | [(set (reg:CCFP CC_REGNUM) | |
| 938 | (compare:CCFP (match_operand:DF 0 "s_register_operand" "w") | |
| 939 | (match_operand:DF 1 "vfp_compare_operand" "wG")))] | |
| 5b3e6663 | 940 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 | 941 | "#" |
| 5b3e6663 | 942 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
943 | [(set (reg:CCFP VFPCC_REGNUM) |
| 944 | (compare:CCFP (match_dup 0) | |
| 945 | (match_dup 1))) | |
| 946 | (set (reg:CCFP CC_REGNUM) | |
| 947 | (reg:CCFPE VFPCC_REGNUM))] | |
| 948 | "" | |
| 949 | ) | |
| 950 | ||
| 951 | (define_insn_and_split "*cmpdf_trap_split_vfp" | |
| 952 | [(set (reg:CCFPE CC_REGNUM) | |
| 953 | (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w") | |
| 954 | (match_operand:DF 1 "vfp_compare_operand" "wG")))] | |
| 5b3e6663 | 955 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 | 956 | "#" |
| 5b3e6663 | 957 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
958 | [(set (reg:CCFPE VFPCC_REGNUM) |
| 959 | (compare:CCFPE (match_dup 0) | |
| 960 | (match_dup 1))) | |
| 961 | (set (reg:CCFPE CC_REGNUM) | |
| 962 | (reg:CCFPE VFPCC_REGNUM))] | |
| 963 | "" | |
| 964 | ) | |
| 965 | ||
| 966 | ||
| 967 | ;; Comparison patterns | |
| 968 | ||
| 969 | (define_insn "*cmpsf_vfp" | |
| 970 | [(set (reg:CCFP VFPCC_REGNUM) | |
| 971 | (compare:CCFP (match_operand:SF 0 "s_register_operand" "w,w") | |
| 972 | (match_operand:SF 1 "vfp_compare_operand" "w,G")))] | |
| 5b3e6663 | 973 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
974 | "@ |
| 975 | fcmps%?\\t%0, %1 | |
| 976 | fcmpzs%?\\t%0" | |
| 977 | [(set_attr "predicable" "yes") | |
| 978 | (set_attr "type" "ffarith")] | |
| 979 | ) | |
| 980 | ||
| 981 | (define_insn "*cmpsf_trap_vfp" | |
| 982 | [(set (reg:CCFPE VFPCC_REGNUM) | |
| 983 | (compare:CCFPE (match_operand:SF 0 "s_register_operand" "w,w") | |
| 984 | (match_operand:SF 1 "vfp_compare_operand" "w,G")))] | |
| 5b3e6663 | 985 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
986 | "@ |
| 987 | fcmpes%?\\t%0, %1 | |
| 988 | fcmpezs%?\\t%0" | |
| 989 | [(set_attr "predicable" "yes") | |
| 990 | (set_attr "type" "ffarith")] | |
| 991 | ) | |
| 992 | ||
| 993 | (define_insn "*cmpdf_vfp" | |
| 994 | [(set (reg:CCFP VFPCC_REGNUM) | |
| 995 | (compare:CCFP (match_operand:DF 0 "s_register_operand" "w,w") | |
| 996 | (match_operand:DF 1 "vfp_compare_operand" "w,G")))] | |
| 5b3e6663 | 997 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
998 | "@ |
| 999 | fcmpd%?\\t%P0, %P1 | |
| 1000 | fcmpzd%?\\t%P0" | |
| 1001 | [(set_attr "predicable" "yes") | |
| 1002 | (set_attr "type" "ffarith")] | |
| 1003 | ) | |
| 1004 | ||
| 1005 | (define_insn "*cmpdf_trap_vfp" | |
| 1006 | [(set (reg:CCFPE VFPCC_REGNUM) | |
| 1007 | (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w,w") | |
| 1008 | (match_operand:DF 1 "vfp_compare_operand" "w,G")))] | |
| 5b3e6663 | 1009 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 9b66ebb1 PB |
1010 | "@ |
| 1011 | fcmped%?\\t%P0, %P1 | |
| 1012 | fcmpezd%?\\t%P0" | |
| 1013 | [(set_attr "predicable" "yes") | |
| 1014 | (set_attr "type" "ffarith")] | |
| 1015 | ) | |
| 1016 | ||
| 1017 | ||
| 1018 | ;; Store multiple insn used in function prologue. | |
| 1019 | ||
| 1020 | (define_insn "*push_multi_vfp" | |
| 1021 | [(match_parallel 2 "multi_register_push" | |
| 1022 | [(set (match_operand:BLK 0 "memory_operand" "=m") | |
| 1023 | (unspec:BLK [(match_operand:DF 1 "s_register_operand" "w")] | |
| 1024 | UNSPEC_PUSH_MULT))])] | |
| 5b3e6663 | 1025 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |
| 8edfc4cc | 1026 | "* return vfp_output_fstmd (operands);" |
| 75fe7b2f | 1027 | [(set_attr "type" "f_stored")] |
| 9b66ebb1 PB |
1028 | ) |
| 1029 | ||
| 1030 | ||
| 1031 | ;; Unimplemented insns: | |
| 1032 | ;; fldm* | |
| 1033 | ;; fstm* | |
| 1034 | ;; fmdhr et al (VFPv1) | |
| 59b9a953 | 1035 | ;; Support for xD (single precision only) variants. |
| 9b66ebb1 | 1036 | ;; fmrrs, fmsrr |