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[thirdparty/gcc.git] / gcc / config / arm / vfp.md
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3f4d9b98
PB		 1;; ARM VFP instruction patterns
2;; Copyright (C) 2003, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
3;; Written by CodeSourcery.
9b66ebb1
PB		 4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published by
2f83c7d6 9;; the Free Software Foundation; either version 3, or (at your option)
9b66ebb1
PB		 10;; any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but
13;; WITHOUT ANY WARRANTY; without even the implied warranty of
14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15;; General Public License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
2f83c7d6
NC		 18;; along with GCC; see the file COPYING3. If not see
19;; <http://www.gnu.org/licenses/>. */
9b66ebb1
PB		 20
21;; Additional register numbers
22(define_constants
f1adb0a9 23 [(VFPCC_REGNUM 127)]
9b66ebb1
PB		 24)
25
9b66ebb1 26;; The VFP "type" attributes differ from those used in the FPA model.
51c69ddb
PB		 27;; fcpys Single precision cpy.
28;; ffariths Single precision abs, neg.
29;; ffarithd Double precision abs, neg, cpy.
30;; fadds Single precision add/sub.
31;; faddd Double precision add/sub.
32;; fconsts Single precision load immediate.
33;; fconstd Double precision load immediate.
34;; fcmps Single precision comparison.
35;; fcmpd Double precision comparison.
a8e17e9e
PB		 36;; fmuls Single precision multiply.
37;; fmuld Double precision multiply.
38;; fmacs Single precision multiply-accumulate.
39;; fmacd Double precision multiply-accumulate.
9b66ebb1
PB		 40;; fdivs Single precision sqrt or division.
41;; fdivd Double precision sqrt or division.
75fe7b2f
RE		 42;; f_flag fmstat operation
43;; f_load[sd] Floating point load from memory.
44;; f_store[sd] Floating point store to memory.
9b66ebb1
PB		 45;; f_2_r Transfer vfp to arm reg.
46;; r_2_f Transfer arm to vfp reg.
75fe7b2f 47;; f_cvt Convert floating<->integral
9b66ebb1 48
9b66ebb1
PB		 49;; SImode moves
50;; ??? For now do not allow loading constants into vfp regs. This causes
59b9a953 51;; problems because small constants get converted into adds.
9b66ebb1 52(define_insn "*arm_movsi_vfp"
f5c630c3 53 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *Uv")
d58bc084 54 (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
9b66ebb1
PB		 55 "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT
56 && ( s_register_operand (operands[0], SImode)
57 || s_register_operand (operands[1], SImode))"
5b3e6663
PB		 58 "*
59 switch (which_alternative)
60 {
f5c630c3 61 case 0: case 1:
5b3e6663 62 return \"mov%?\\t%0, %1\";
5b3e6663 63 case 2:
f5c630c3 64 return \"mvn%?\\t%0, #%B1\";
5b3e6663 65 case 3:
f5c630c3 66 return \"movw%?\\t%0, %1\";
5b3e6663 67 case 4:
f5c630c3 68 return \"ldr%?\\t%0, %1\";
5b3e6663 69 case 5:
f5c630c3 70 return \"str%?\\t%1, %0\";
5b3e6663 71 case 6:
f5c630c3 72 return \"fmsr%?\\t%0, %1\\t%@ int\";
5b3e6663 73 case 7:
f5c630c3
PB		 74 return \"fmrs%?\\t%0, %1\\t%@ int\";
75 case 8:
5b3e6663 76 return \"fcpys%?\\t%0, %1\\t%@ int\";
f5c630c3 77 case 9: case 10:
5b3e6663
PB		 78 return output_move_vfp (operands);
79 default:
80 gcc_unreachable ();
81 }
82 "
83 [(set_attr "predicable" "yes")
51c69ddb 84 (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
f5c630c3
PB		 85 (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*")
86 (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
5b3e6663
PB		 87)
88
89(define_insn "*thumb2_movsi_vfp"
f5c630c3 90 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m,*t,r, *t,*t, *Uv")
d58bc084 91 (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
5b3e6663
PB		 92 "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT
93 && ( s_register_operand (operands[0], SImode)
94 || s_register_operand (operands[1], SImode))"
95 "*
96 switch (which_alternative)
97 {
f5c630c3 98 case 0: case 1:
5b3e6663 99 return \"mov%?\\t%0, %1\";
5b3e6663 100 case 2:
f5c630c3 101 return \"mvn%?\\t%0, #%B1\";
5b3e6663 102 case 3:
f5c630c3 103 return \"movw%?\\t%0, %1\";
5b3e6663 104 case 4:
f5c630c3 105 return \"ldr%?\\t%0, %1\";
5b3e6663 106 case 5:
f5c630c3 107 return \"str%?\\t%1, %0\";
5b3e6663 108 case 6:
f5c630c3 109 return \"fmsr%?\\t%0, %1\\t%@ int\";
5b3e6663 110 case 7:
f5c630c3
PB		 111 return \"fmrs%?\\t%0, %1\\t%@ int\";
112 case 8:
5b3e6663 113 return \"fcpys%?\\t%0, %1\\t%@ int\";
f5c630c3 114 case 9: case 10:
5b3e6663
PB		 115 return output_move_vfp (operands);
116 default:
117 gcc_unreachable ();
118 }
119 "
9b66ebb1 120 [(set_attr "predicable" "yes")
51c69ddb 121 (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_load,f_store")
f5c630c3
PB		 122 (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*")
123 (set_attr "neg_pool_range" "*,*,*,*, 0,*,*,*,*,1008,*")]
9b66ebb1
PB		 124)
125
126
127;; DImode moves
128
129(define_insn "*arm_movdi_vfp"
fdd695fd
PB		 130 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv")
131 (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))]
d5b6e637
PB		 132 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
133 && ( register_operand (operands[0], DImode)
134 || register_operand (operands[1], DImode))"
9b66ebb1
PB		 135 "*
136 switch (which_alternative)
137 {
9b901d50
RE		 138 case 0:
139 return \"#\";
140 case 1:
141 case 2:
142 return output_move_double (operands);
9b66ebb1 143 case 3:
94634f14 144 return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
9b66ebb1 145 case 4:
94634f14 146 return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
9b66ebb1
PB		 147 case 5:
148 return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
5b3e6663
PB		 149 case 6: case 7:
150 return output_move_vfp (operands);
9b66ebb1 151 default:
e6d29d15 152 gcc_unreachable ();
9b66ebb1
PB		 153 }
154 "
51c69ddb 155 [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
9b66ebb1 156 (set_attr "length" "8,8,8,4,4,4,4,4")
54f52b81 157 (set_attr "predicable" "yes")
9b66ebb1
PB		 158 (set_attr "pool_range" "*,1020,*,*,*,*,1020,*")
159 (set_attr "neg_pool_range" "*,1008,*,*,*,*,1008,*")]
160)
161
5b3e6663
PB		 162(define_insn "*thumb2_movdi_vfp"
163 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv")
164 (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))]
165 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
166 "*
167 switch (which_alternative)
168 {
169 case 0: case 1: case 2:
170 return (output_move_double (operands));
171 case 3:
172 return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
173 case 4:
174 return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
175 case 5:
176 return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
177 case 6: case 7:
178 return output_move_vfp (operands);
179 default:
180 abort ();
181 }
182 "
51c69ddb 183 [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_load,f_store")
5b3e6663
PB		 184 (set_attr "length" "8,8,8,4,4,4,4,4")
185 (set_attr "pool_range" "*,4096,*,*,*,*,1020,*")
186 (set_attr "neg_pool_range" "*, 0,*,*,*,*,1008,*")]
187)
188
0fd8c3ad
SL		 189;; HFmode moves
190(define_insn "*movhf_vfp"
191 [(set (match_operand:HF 0 "nonimmediate_operand" "= t,Um,r,m,t,r,t,r,r")
192 (match_operand:HF 1 "general_operand" " Um, t,m,r,t,r,r,t,F"))]
193 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_NEON_FP16
194 && ( s_register_operand (operands[0], HFmode)
195 || s_register_operand (operands[1], HFmode))"
196 "*
197 switch (which_alternative)
198 {
199 case 0: /* S register from memory */
200 return \"vld1.16\\t{%z0}, %A1\";
201 case 1: /* memory from S register */
202 return \"vst1.16\\t{%z1}, %A0\";
203 case 2: /* ARM register from memory */
204 return \"ldrh\\t%0, %1\\t%@ __fp16\";
205 case 3: /* memory from ARM register */
206 return \"strh\\t%1, %0\\t%@ __fp16\";
207 case 4: /* S register from S register */
208 return \"fcpys\\t%0, %1\";
209 case 5: /* ARM register from ARM register */
210 return \"mov\\t%0, %1\\t%@ __fp16\";
211 case 6: /* S register from ARM register */
212 return \"fmsr\\t%0, %1\";
213 case 7: /* ARM register from S register */
214 return \"fmrs\\t%0, %1\";
215 case 8: /* ARM register from constant */
216 {
217 REAL_VALUE_TYPE r;
218 long bits;
219 rtx ops[4];
220
221 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
222 bits = real_to_target (NULL, &r, HFmode);
223 ops[0] = operands[0];
224 ops[1] = GEN_INT (bits);
225 ops[2] = GEN_INT (bits & 0xff00);
226 ops[3] = GEN_INT (bits & 0x00ff);
227
228 if (arm_arch_thumb2)
229 output_asm_insn (\"movw\\t%0, %1\", ops);
230 else
231 output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
232 return \"\";
233 }
234 default:
235 gcc_unreachable ();
236 }
237 "
238 [(set_attr "conds" "unconditional")
239 (set_attr "type" "*,*,load1,store1,fcpys,*,r_2_f,f_2_r,*")
240 (set_attr "neon_type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,*,*,*,*,*,*,*")
241 (set_attr "length" "4,4,4,4,4,4,4,4,8")]
242)
243
9b66ebb1
PB		 244
245;; SFmode moves
221b2a64
PB		 246;; Disparage the w<->r cases because reloading an invalid address is
247;; preferable to loading the value via integer registers.
9b66ebb1
PB		 248
249(define_insn "*movsf_vfp"
f1adb0a9
JB		 250 [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t ,t ,Uv,r ,m,t,r")
251 (match_operand:SF 1 "general_operand" " ?r,t,Dv,UvE,t, mE,r,t,r"))]
9b66ebb1
PB		 252 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
253 && ( s_register_operand (operands[0], SFmode)
254 || s_register_operand (operands[1], SFmode))"
5b3e6663
PB		 255 "*
256 switch (which_alternative)
257 {
258 case 0:
259 return \"fmsr%?\\t%0, %1\";
260 case 1:
261 return \"fmrs%?\\t%0, %1\";
f1adb0a9
JB		 262 case 2:
263 return \"fconsts%?\\t%0, #%G1\";
264 case 3: case 4:
5b3e6663 265 return output_move_vfp (operands);
5b3e6663 266 case 5:
f1adb0a9 267 return \"ldr%?\\t%0, %1\\t%@ float\";
5b3e6663 268 case 6:
f1adb0a9 269 return \"str%?\\t%1, %0\\t%@ float\";
5b3e6663 270 case 7:
f1adb0a9
JB		 271 return \"fcpys%?\\t%0, %1\";
272 case 8:
5b3e6663
PB		 273 return \"mov%?\\t%0, %1\\t%@ float\";
274 default:
275 gcc_unreachable ();
276 }
277 "
9b66ebb1 278 [(set_attr "predicable" "yes")
f1adb0a9 279 (set_attr "type"
51c69ddb 280 "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*")
f1adb0a9
JB		 281 (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
282 (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")]
9b66ebb1
PB		 283)
284
5b3e6663 285(define_insn "*thumb2_movsf_vfp"
f1adb0a9
JB		 286 [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t, t ,Uv,r ,m,t,r")
287 (match_operand:SF 1 "general_operand" " ?r,t,Dv,UvE,t, mE,r,t,r"))]
5b3e6663
PB		 288 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
289 && ( s_register_operand (operands[0], SFmode)
290 || s_register_operand (operands[1], SFmode))"
291 "*
292 switch (which_alternative)
293 {
294 case 0:
295 return \"fmsr%?\\t%0, %1\";
296 case 1:
297 return \"fmrs%?\\t%0, %1\";
f1adb0a9
JB		 298 case 2:
299 return \"fconsts%?\\t%0, #%G1\";
300 case 3: case 4:
5b3e6663 301 return output_move_vfp (operands);
5b3e6663 302 case 5:
f1adb0a9 303 return \"ldr%?\\t%0, %1\\t%@ float\";
5b3e6663 304 case 6:
f1adb0a9 305 return \"str%?\\t%1, %0\\t%@ float\";
5b3e6663 306 case 7:
f1adb0a9
JB		 307 return \"fcpys%?\\t%0, %1\";
308 case 8:
5b3e6663
PB		 309 return \"mov%?\\t%0, %1\\t%@ float\";
310 default:
311 gcc_unreachable ();
312 }
313 "
314 [(set_attr "predicable" "yes")
f1adb0a9 315 (set_attr "type"
51c69ddb 316 "r_2_f,f_2_r,fconsts,f_load,f_store,load1,store1,fcpys,*")
f1adb0a9
JB		 317 (set_attr "pool_range" "*,*,*,1020,*,4092,*,*,*")
318 (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
5b3e6663
PB		 319)
320
9b66ebb1
PB		 321
322;; DFmode moves
323
324(define_insn "*movdf_vfp"
f1adb0a9
JB		 325 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r")
326 (match_operand:DF 1 "soft_df_operand" " ?r,w,Dv,mF,r,UvF,w, w,r"))]
d5b6e637
PB		 327 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
328 && ( register_operand (operands[0], DFmode)
329 || register_operand (operands[1], DFmode))"
9b66ebb1
PB		 330 "*
331 {
332 switch (which_alternative)
333 {
334 case 0:
335 return \"fmdrr%?\\t%P0, %Q1, %R1\";
336 case 1:
337 return \"fmrrd%?\\t%Q0, %R0, %P1\";
f1adb0a9
JB		 338 case 2:
339 return \"fconstd%?\\t%P0, #%G1\";
340 case 3: case 4:
9b66ebb1 341 return output_move_double (operands);
f1adb0a9 342 case 5: case 6:
5b3e6663 343 return output_move_vfp (operands);
9b901d50 344 case 7:
f1adb0a9
JB		 345 return \"fcpyd%?\\t%P0, %P1\";
346 case 8:
9b901d50 347 return \"#\";
9b66ebb1 348 default:
e6d29d15 349 gcc_unreachable ();
9b66ebb1
PB		 350 }
351 }
352 "
f1adb0a9 353 [(set_attr "type"
51c69ddb 354 "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
f1adb0a9 355 (set_attr "length" "4,4,4,8,8,4,4,4,8")
54f52b81 356 (set_attr "predicable" "yes")
f1adb0a9
JB		 357 (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*")
358 (set_attr "neg_pool_range" "*,*,*,1008,*,1008,*,*,*")]
9b66ebb1
PB		 359)
360
5b3e6663 361(define_insn "*thumb2_movdf_vfp"
f1adb0a9
JB		 362 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r")
363 (match_operand:DF 1 "soft_df_operand" " ?r,w,Dv,mF,r,UvF,w, w,r"))]
5b3e6663
PB		 364 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
365 "*
366 {
367 switch (which_alternative)
368 {
369 case 0:
370 return \"fmdrr%?\\t%P0, %Q1, %R1\";
371 case 1:
372 return \"fmrrd%?\\t%Q0, %R0, %P1\";
f1adb0a9
JB		 373 case 2:
374 return \"fconstd%?\\t%P0, #%G1\";
375 case 3: case 4: case 8:
5b3e6663 376 return output_move_double (operands);
f1adb0a9 377 case 5: case 6:
5b3e6663 378 return output_move_vfp (operands);
f1adb0a9 379 case 7:
5b3e6663
PB		 380 return \"fcpyd%?\\t%P0, %P1\";
381 default:
382 abort ();
383 }
384 }
385 "
f1adb0a9 386 [(set_attr "type"
51c69ddb 387 "r_2_f,f_2_r,fconstd,load2,store2,f_load,f_store,ffarithd,*")
f1adb0a9
JB		 388 (set_attr "length" "4,4,4,8,8,4,4,4,8")
389 (set_attr "pool_range" "*,*,*,4096,*,1020,*,*,*")
390 (set_attr "neg_pool_range" "*,*,*,0,*,1008,*,*,*")]
5b3e6663
PB		 391)
392
9b66ebb1
PB		 393
394;; Conditional move patterns
395
396(define_insn "*movsfcc_vfp"
f1adb0a9 397 [(set (match_operand:SF 0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
9b66ebb1
PB		 398 (if_then_else:SF
399 (match_operator 3 "arm_comparison_operator"
400 [(match_operand 4 "cc_register" "") (const_int 0)])
f1adb0a9
JB		 401 (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
402 (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
9b66ebb1
PB		 403 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
404 "@
405 fcpys%D3\\t%0, %2
406 fcpys%d3\\t%0, %1
407 fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
408 fmsr%D3\\t%0, %2
409 fmsr%d3\\t%0, %1
410 fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
411 fmrs%D3\\t%0, %2
412 fmrs%d3\\t%0, %1
413 fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
414 [(set_attr "conds" "use")
415 (set_attr "length" "4,4,8,4,4,8,4,4,8")
51c69ddb 416 (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
9b66ebb1
PB		 417)
418
5b3e6663 419(define_insn "*thumb2_movsfcc_vfp"
f1adb0a9 420 [(set (match_operand:SF 0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
5b3e6663
PB		 421 (if_then_else:SF
422 (match_operator 3 "arm_comparison_operator"
423 [(match_operand 4 "cc_register" "") (const_int 0)])
f1adb0a9
JB		 424 (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
425 (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
5b3e6663
PB		 426 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
427 "@
428 it\\t%D3\;fcpys%D3\\t%0, %2
429 it\\t%d3\;fcpys%d3\\t%0, %1
430 ite\\t%D3\;fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
431 it\\t%D3\;fmsr%D3\\t%0, %2
432 it\\t%d3\;fmsr%d3\\t%0, %1
433 ite\\t%D3\;fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
434 it\\t%D3\;fmrs%D3\\t%0, %2
435 it\\t%d3\;fmrs%d3\\t%0, %1
436 ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
437 [(set_attr "conds" "use")
438 (set_attr "length" "6,6,10,6,6,10,6,6,10")
51c69ddb 439 (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
5b3e6663
PB		 440)
441
9b66ebb1
PB		 442(define_insn "*movdfcc_vfp"
443 [(set (match_operand:DF 0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
444 (if_then_else:DF
445 (match_operator 3 "arm_comparison_operator"
446 [(match_operand 4 "cc_register" "") (const_int 0)])
447 (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
448 (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
449 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
450 "@
451 fcpyd%D3\\t%P0, %P2
452 fcpyd%d3\\t%P0, %P1
453 fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
454 fmdrr%D3\\t%P0, %Q2, %R2
455 fmdrr%d3\\t%P0, %Q1, %R1
456 fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
457 fmrrd%D3\\t%Q0, %R0, %P2
458 fmrrd%d3\\t%Q0, %R0, %P1
459 fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
460 [(set_attr "conds" "use")
461 (set_attr "length" "4,4,8,4,4,8,4,4,8")
51c69ddb 462 (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
9b66ebb1
PB		 463)
464
5b3e6663
PB		 465(define_insn "*thumb2_movdfcc_vfp"
466 [(set (match_operand:DF 0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
467 (if_then_else:DF
468 (match_operator 3 "arm_comparison_operator"
469 [(match_operand 4 "cc_register" "") (const_int 0)])
470 (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
471 (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
472 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
473 "@
474 it\\t%D3\;fcpyd%D3\\t%P0, %P2
475 it\\t%d3\;fcpyd%d3\\t%P0, %P1
476 ite\\t%D3\;fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
477 it\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2
478 it\t%d3\;fmdrr%d3\\t%P0, %Q1, %R1
479 ite\\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
480 it\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2
481 it\t%d3\;fmrrd%d3\\t%Q0, %R0, %P1
482 ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
483 [(set_attr "conds" "use")
484 (set_attr "length" "6,6,10,6,6,10,6,6,10")
51c69ddb 485 (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
5b3e6663
PB		 486)
487
9b66ebb1
PB		 488
489;; Sign manipulation functions
490
491(define_insn "*abssf2_vfp"
f1adb0a9
JB		 492 [(set (match_operand:SF 0 "s_register_operand" "=t")
493 (abs:SF (match_operand:SF 1 "s_register_operand" "t")))]
5b3e6663 494 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 495 "fabss%?\\t%0, %1"
496 [(set_attr "predicable" "yes")
51c69ddb 497 (set_attr "type" "ffariths")]
9b66ebb1
PB		 498)
499
500(define_insn "*absdf2_vfp"
501 [(set (match_operand:DF 0 "s_register_operand" "=w")
502 (abs:DF (match_operand:DF 1 "s_register_operand" "w")))]
5b3e6663 503 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 504 "fabsd%?\\t%P0, %P1"
505 [(set_attr "predicable" "yes")
51c69ddb 506 (set_attr "type" "ffarithd")]
9b66ebb1
PB		 507)
508
509(define_insn "*negsf2_vfp"
f1adb0a9
JB		 510 [(set (match_operand:SF 0 "s_register_operand" "=t,?r")
511 (neg:SF (match_operand:SF 1 "s_register_operand" "t,r")))]
5b3e6663 512 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
81632f11
RE		 513 "@
514 fnegs%?\\t%0, %1
515 eor%?\\t%0, %1, #-2147483648"
9b66ebb1 516 [(set_attr "predicable" "yes")
51c69ddb 517 (set_attr "type" "ffariths")]
9b66ebb1
PB		 518)
519
81632f11
RE		 520(define_insn_and_split "*negdf2_vfp"
521 [(set (match_operand:DF 0 "s_register_operand" "=w,?r,?r")
522 (neg:DF (match_operand:DF 1 "s_register_operand" "w,0,r")))]
5b3e6663 523 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
81632f11
RE		 524 "@
525 fnegd%?\\t%P0, %P1
526 #
527 #"
5b3e6663 528 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && reload_completed
81632f11
RE		 529 && arm_general_register_operand (operands[0], DFmode)"
530 [(set (match_dup 0) (match_dup 1))]
531 "
532 if (REGNO (operands[0]) == REGNO (operands[1]))
533 {
534 operands[0] = gen_highpart (SImode, operands[0]);
535 operands[1] = gen_rtx_XOR (SImode, operands[0], GEN_INT (0x80000000));
536 }
537 else
538 {
539 rtx in_hi, in_lo, out_hi, out_lo;
540
541 in_hi = gen_rtx_XOR (SImode, gen_highpart (SImode, operands[1]),
542 GEN_INT (0x80000000));
543 in_lo = gen_lowpart (SImode, operands[1]);
544 out_hi = gen_highpart (SImode, operands[0]);
545 out_lo = gen_lowpart (SImode, operands[0]);
546
547 if (REGNO (in_lo) == REGNO (out_hi))
548 {
549 emit_insn (gen_rtx_SET (SImode, out_lo, in_lo));
550 operands[0] = out_hi;
551 operands[1] = in_hi;
552 }
553 else
554 {
555 emit_insn (gen_rtx_SET (SImode, out_hi, in_hi));
556 operands[0] = out_lo;
557 operands[1] = in_lo;
558 }
559 }
560 "
9b66ebb1 561 [(set_attr "predicable" "yes")
81632f11 562 (set_attr "length" "4,4,8")
51c69ddb 563 (set_attr "type" "ffarithd")]
9b66ebb1
PB		 564)
565
566
567;; Arithmetic insns
568
569(define_insn "*addsf3_vfp"
f1adb0a9
JB		 570 [(set (match_operand:SF 0 "s_register_operand" "=t")
571 (plus:SF (match_operand:SF 1 "s_register_operand" "t")
572 (match_operand:SF 2 "s_register_operand" "t")))]
5b3e6663 573 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 574 "fadds%?\\t%0, %1, %2"
575 [(set_attr "predicable" "yes")
51c69ddb 576 (set_attr "type" "fadds")]
9b66ebb1
PB		 577)
578
579(define_insn "*adddf3_vfp"
580 [(set (match_operand:DF 0 "s_register_operand" "=w")
581 (plus:DF (match_operand:DF 1 "s_register_operand" "w")
582 (match_operand:DF 2 "s_register_operand" "w")))]
5b3e6663 583 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 584 "faddd%?\\t%P0, %P1, %P2"
585 [(set_attr "predicable" "yes")
51c69ddb 586 (set_attr "type" "faddd")]
9b66ebb1
PB		 587)
588
589
590(define_insn "*subsf3_vfp"
f1adb0a9
JB		 591 [(set (match_operand:SF 0 "s_register_operand" "=t")
592 (minus:SF (match_operand:SF 1 "s_register_operand" "t")
593 (match_operand:SF 2 "s_register_operand" "t")))]
5b3e6663 594 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 595 "fsubs%?\\t%0, %1, %2"
596 [(set_attr "predicable" "yes")
51c69ddb 597 (set_attr "type" "fadds")]
9b66ebb1
PB		 598)
599
600(define_insn "*subdf3_vfp"
601 [(set (match_operand:DF 0 "s_register_operand" "=w")
602 (minus:DF (match_operand:DF 1 "s_register_operand" "w")
603 (match_operand:DF 2 "s_register_operand" "w")))]
5b3e6663 604 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 605 "fsubd%?\\t%P0, %P1, %P2"
606 [(set_attr "predicable" "yes")
51c69ddb 607 (set_attr "type" "faddd")]
9b66ebb1
PB		 608)
609
610
611;; Division insns
612
613(define_insn "*divsf3_vfp"
f1adb0a9
JB		 614 [(set (match_operand:SF 0 "s_register_operand" "+t")
615 (div:SF (match_operand:SF 1 "s_register_operand" "t")
616 (match_operand:SF 2 "s_register_operand" "t")))]
5b3e6663 617 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 618 "fdivs%?\\t%0, %1, %2"
619 [(set_attr "predicable" "yes")
620 (set_attr "type" "fdivs")]
621)
622
623(define_insn "*divdf3_vfp"
624 [(set (match_operand:DF 0 "s_register_operand" "+w")
625 (div:DF (match_operand:DF 1 "s_register_operand" "w")
626 (match_operand:DF 2 "s_register_operand" "w")))]
5b3e6663 627 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 628 "fdivd%?\\t%P0, %P1, %P2"
629 [(set_attr "predicable" "yes")
630 (set_attr "type" "fdivd")]
631)
632
633
634;; Multiplication insns
635
636(define_insn "*mulsf3_vfp"
f1adb0a9
JB		 637 [(set (match_operand:SF 0 "s_register_operand" "+t")
638 (mult:SF (match_operand:SF 1 "s_register_operand" "t")
639 (match_operand:SF 2 "s_register_operand" "t")))]
5b3e6663 640 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 641 "fmuls%?\\t%0, %1, %2"
642 [(set_attr "predicable" "yes")
a8e17e9e 643 (set_attr "type" "fmuls")]
9b66ebb1
PB		 644)
645
646(define_insn "*muldf3_vfp"
647 [(set (match_operand:DF 0 "s_register_operand" "+w")
648 (mult:DF (match_operand:DF 1 "s_register_operand" "w")
649 (match_operand:DF 2 "s_register_operand" "w")))]
5b3e6663 650 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 651 "fmuld%?\\t%P0, %P1, %P2"
652 [(set_attr "predicable" "yes")
a8e17e9e 653 (set_attr "type" "fmuld")]
9b66ebb1
PB		 654)
655
656
657(define_insn "*mulsf3negsf_vfp"
f1adb0a9
JB		 658 [(set (match_operand:SF 0 "s_register_operand" "+t")
659 (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
660 (match_operand:SF 2 "s_register_operand" "t")))]
5b3e6663 661 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 662 "fnmuls%?\\t%0, %1, %2"
663 [(set_attr "predicable" "yes")
a8e17e9e 664 (set_attr "type" "fmuls")]
9b66ebb1
PB		 665)
666
667(define_insn "*muldf3negdf_vfp"
668 [(set (match_operand:DF 0 "s_register_operand" "+w")
669 (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
670 (match_operand:DF 2 "s_register_operand" "w")))]
5b3e6663 671 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 672 "fnmuld%?\\t%P0, %P1, %P2"
673 [(set_attr "predicable" "yes")
a8e17e9e 674 (set_attr "type" "fmuld")]
9b66ebb1
PB		 675)
676
677
678;; Multiply-accumulate insns
679
680;; 0 = 1 * 2 + 0
681(define_insn "*mulsf3addsf_vfp"
f1adb0a9
JB		 682 [(set (match_operand:SF 0 "s_register_operand" "=t")
683 (plus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
684 (match_operand:SF 3 "s_register_operand" "t"))
9b66ebb1 685 (match_operand:SF 1 "s_register_operand" "0")))]
5b3e6663 686 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 687 "fmacs%?\\t%0, %2, %3"
688 [(set_attr "predicable" "yes")
a8e17e9e 689 (set_attr "type" "fmacs")]
9b66ebb1
PB		 690)
691
692(define_insn "*muldf3adddf_vfp"
693 [(set (match_operand:DF 0 "s_register_operand" "=w")
694 (plus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
695 (match_operand:DF 3 "s_register_operand" "w"))
696 (match_operand:DF 1 "s_register_operand" "0")))]
5b3e6663 697 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 698 "fmacd%?\\t%P0, %P2, %P3"
699 [(set_attr "predicable" "yes")
a8e17e9e 700 (set_attr "type" "fmacd")]
9b66ebb1
PB		 701)
702
703;; 0 = 1 * 2 - 0
704(define_insn "*mulsf3subsf_vfp"
f1adb0a9
JB		 705 [(set (match_operand:SF 0 "s_register_operand" "=t")
706 (minus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
707 (match_operand:SF 3 "s_register_operand" "t"))
9b66ebb1 708 (match_operand:SF 1 "s_register_operand" "0")))]
5b3e6663 709 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 710 "fmscs%?\\t%0, %2, %3"
711 [(set_attr "predicable" "yes")
a8e17e9e 712 (set_attr "type" "fmacs")]
9b66ebb1
PB		 713)
714
715(define_insn "*muldf3subdf_vfp"
716 [(set (match_operand:DF 0 "s_register_operand" "=w")
717 (minus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
718 (match_operand:DF 3 "s_register_operand" "w"))
719 (match_operand:DF 1 "s_register_operand" "0")))]
5b3e6663 720 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 721 "fmscd%?\\t%P0, %P2, %P3"
722 [(set_attr "predicable" "yes")
a8e17e9e 723 (set_attr "type" "fmacd")]
9b66ebb1
PB		 724)
725
726;; 0 = -(1 * 2) + 0
727(define_insn "*mulsf3negsfaddsf_vfp"
f1adb0a9 728 [(set (match_operand:SF 0 "s_register_operand" "=t")
9b66ebb1 729 (minus:SF (match_operand:SF 1 "s_register_operand" "0")
f1adb0a9
JB		 730 (mult:SF (match_operand:SF 2 "s_register_operand" "t")
731 (match_operand:SF 3 "s_register_operand" "t"))))]
5b3e6663 732 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 733 "fnmacs%?\\t%0, %2, %3"
734 [(set_attr "predicable" "yes")
a8e17e9e 735 (set_attr "type" "fmacs")]
9b66ebb1
PB		 736)
737
738(define_insn "*fmuldf3negdfadddf_vfp"
739 [(set (match_operand:DF 0 "s_register_operand" "=w")
740 (minus:DF (match_operand:DF 1 "s_register_operand" "0")
741 (mult:DF (match_operand:DF 2 "s_register_operand" "w")
742 (match_operand:DF 3 "s_register_operand" "w"))))]
5b3e6663 743 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 744 "fnmacd%?\\t%P0, %P2, %P3"
745 [(set_attr "predicable" "yes")
a8e17e9e 746 (set_attr "type" "fmacd")]
9b66ebb1
PB		 747)
748
749
750;; 0 = -(1 * 2) - 0
751(define_insn "*mulsf3negsfsubsf_vfp"
f1adb0a9 752 [(set (match_operand:SF 0 "s_register_operand" "=t")
9b66ebb1 753 (minus:SF (mult:SF
f1adb0a9
JB		 754 (neg:SF (match_operand:SF 2 "s_register_operand" "t"))
755 (match_operand:SF 3 "s_register_operand" "t"))
9b66ebb1 756 (match_operand:SF 1 "s_register_operand" "0")))]
5b3e6663 757 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 758 "fnmscs%?\\t%0, %2, %3"
759 [(set_attr "predicable" "yes")
a8e17e9e 760 (set_attr "type" "fmacs")]
9b66ebb1
PB		 761)
762
763(define_insn "*muldf3negdfsubdf_vfp"
764 [(set (match_operand:DF 0 "s_register_operand" "=w")
765 (minus:DF (mult:DF
766 (neg:DF (match_operand:DF 2 "s_register_operand" "w"))
767 (match_operand:DF 3 "s_register_operand" "w"))
768 (match_operand:DF 1 "s_register_operand" "0")))]
5b3e6663 769 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 770 "fnmscd%?\\t%P0, %P2, %P3"
771 [(set_attr "predicable" "yes")
a8e17e9e 772 (set_attr "type" "fmacd")]
9b66ebb1
PB		 773)
774
775
776;; Conversion routines
777
778(define_insn "*extendsfdf2_vfp"
779 [(set (match_operand:DF 0 "s_register_operand" "=w")
f1adb0a9 780 (float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))]
5b3e6663 781 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 782 "fcvtds%?\\t%P0, %1"
783 [(set_attr "predicable" "yes")
75fe7b2f 784 (set_attr "type" "f_cvt")]
9b66ebb1
PB		 785)
786
787(define_insn "*truncdfsf2_vfp"
f1adb0a9 788 [(set (match_operand:SF 0 "s_register_operand" "=t")
9b66ebb1 789 (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))]
5b3e6663 790 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 791 "fcvtsd%?\\t%0, %P1"
792 [(set_attr "predicable" "yes")
75fe7b2f 793 (set_attr "type" "f_cvt")]
9b66ebb1
PB		 794)
795
0fd8c3ad
SL		 796(define_insn "extendhfsf2"
797 [(set (match_operand:SF 0 "s_register_operand" "=t")
798 (float_extend:SF (match_operand:HF 1 "s_register_operand" "t")))]
799 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_NEON_FP16"
800 "vcvtb%?.f32.f16\\t%0, %1"
801 [(set_attr "predicable" "yes")
802 (set_attr "type" "f_cvt")]
803)
804
805(define_insn "truncsfhf2"
806 [(set (match_operand:HF 0 "s_register_operand" "=t")
807 (float_truncate:HF (match_operand:SF 1 "s_register_operand" "t")))]
808 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_NEON_FP16"
809 "vcvtb%?.f16.f32\\t%0, %1"
810 [(set_attr "predicable" "yes")
811 (set_attr "type" "f_cvt")]
812)
813
9b66ebb1 814(define_insn "*truncsisf2_vfp"
f1adb0a9
JB		 815 [(set (match_operand:SI 0 "s_register_operand" "=t")
816 (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
5b3e6663 817 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 818 "ftosizs%?\\t%0, %1"
819 [(set_attr "predicable" "yes")
75fe7b2f 820 (set_attr "type" "f_cvt")]
9b66ebb1
PB		 821)
822
823(define_insn "*truncsidf2_vfp"
f1adb0a9 824 [(set (match_operand:SI 0 "s_register_operand" "=t")
9b66ebb1 825 (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))]
5b3e6663 826 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 827 "ftosizd%?\\t%0, %P1"
828 [(set_attr "predicable" "yes")
75fe7b2f 829 (set_attr "type" "f_cvt")]
9b66ebb1
PB		 830)
831
6f6c1f6d
PB		 832
833(define_insn "fixuns_truncsfsi2"
f1adb0a9
JB		 834 [(set (match_operand:SI 0 "s_register_operand" "=t")
835 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
5b3e6663 836 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
6f6c1f6d
PB		 837 "ftouizs%?\\t%0, %1"
838 [(set_attr "predicable" "yes")
75fe7b2f 839 (set_attr "type" "f_cvt")]
6f6c1f6d
PB		 840)
841
842(define_insn "fixuns_truncdfsi2"
f1adb0a9
JB		 843 [(set (match_operand:SI 0 "s_register_operand" "=t")
844 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))]
5b3e6663 845 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
6f6c1f6d
PB		 846 "ftouizd%?\\t%0, %P1"
847 [(set_attr "predicable" "yes")
75fe7b2f 848 (set_attr "type" "f_cvt")]
6f6c1f6d
PB		 849)
850
851
9b66ebb1 852(define_insn "*floatsisf2_vfp"
f1adb0a9
JB		 853 [(set (match_operand:SF 0 "s_register_operand" "=t")
854 (float:SF (match_operand:SI 1 "s_register_operand" "t")))]
5b3e6663 855 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 856 "fsitos%?\\t%0, %1"
857 [(set_attr "predicable" "yes")
75fe7b2f 858 (set_attr "type" "f_cvt")]
9b66ebb1
PB		 859)
860
861(define_insn "*floatsidf2_vfp"
862 [(set (match_operand:DF 0 "s_register_operand" "=w")
f1adb0a9 863 (float:DF (match_operand:SI 1 "s_register_operand" "t")))]
5b3e6663 864 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 865 "fsitod%?\\t%P0, %1"
866 [(set_attr "predicable" "yes")
75fe7b2f 867 (set_attr "type" "f_cvt")]
9b66ebb1
PB		 868)
869
870
6f6c1f6d 871(define_insn "floatunssisf2"
f1adb0a9
JB		 872 [(set (match_operand:SF 0 "s_register_operand" "=t")
873 (unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))]
5b3e6663 874 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
6f6c1f6d
PB		 875 "fuitos%?\\t%0, %1"
876 [(set_attr "predicable" "yes")
75fe7b2f 877 (set_attr "type" "f_cvt")]
6f6c1f6d
PB		 878)
879
880(define_insn "floatunssidf2"
881 [(set (match_operand:DF 0 "s_register_operand" "=w")
f1adb0a9 882 (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))]
5b3e6663 883 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
6f6c1f6d
PB		 884 "fuitod%?\\t%P0, %1"
885 [(set_attr "predicable" "yes")
75fe7b2f 886 (set_attr "type" "f_cvt")]
6f6c1f6d
PB		 887)
888
889
9b66ebb1
PB		 890;; Sqrt insns.
891
892(define_insn "*sqrtsf2_vfp"
f1adb0a9
JB		 893 [(set (match_operand:SF 0 "s_register_operand" "=t")
894 (sqrt:SF (match_operand:SF 1 "s_register_operand" "t")))]
5b3e6663 895 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 896 "fsqrts%?\\t%0, %1"
897 [(set_attr "predicable" "yes")
898 (set_attr "type" "fdivs")]
899)
900
901(define_insn "*sqrtdf2_vfp"
902 [(set (match_operand:DF 0 "s_register_operand" "=w")
903 (sqrt:DF (match_operand:DF 1 "s_register_operand" "w")))]
5b3e6663 904 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 905 "fsqrtd%?\\t%P0, %P1"
906 [(set_attr "predicable" "yes")
907 (set_attr "type" "fdivd")]
908)
909
910
911;; Patterns to split/copy vfp condition flags.
912
913(define_insn "*movcc_vfp"
914 [(set (reg CC_REGNUM)
915 (reg VFPCC_REGNUM))]
5b3e6663 916 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 917 "fmstat%?"
918 [(set_attr "conds" "set")
75fe7b2f 919 (set_attr "type" "f_flag")]
9b66ebb1
PB		 920)
921
922(define_insn_and_split "*cmpsf_split_vfp"
923 [(set (reg:CCFP CC_REGNUM)
f1adb0a9
JB		 924 (compare:CCFP (match_operand:SF 0 "s_register_operand" "t")
925 (match_operand:SF 1 "vfp_compare_operand" "tG")))]
5b3e6663 926 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1 927 "#"
5b3e6663 928 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 929 [(set (reg:CCFP VFPCC_REGNUM)
930 (compare:CCFP (match_dup 0)
931 (match_dup 1)))
932 (set (reg:CCFP CC_REGNUM)
933 (reg:CCFP VFPCC_REGNUM))]
934 ""
935)
936
937(define_insn_and_split "*cmpsf_trap_split_vfp"
938 [(set (reg:CCFPE CC_REGNUM)
f1adb0a9
JB		 939 (compare:CCFPE (match_operand:SF 0 "s_register_operand" "t")
940 (match_operand:SF 1 "vfp_compare_operand" "tG")))]
5b3e6663 941 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1 942 "#"
5b3e6663 943 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 944 [(set (reg:CCFPE VFPCC_REGNUM)
945 (compare:CCFPE (match_dup 0)
946 (match_dup 1)))
947 (set (reg:CCFPE CC_REGNUM)
948 (reg:CCFPE VFPCC_REGNUM))]
949 ""
950)
951
952(define_insn_and_split "*cmpdf_split_vfp"
953 [(set (reg:CCFP CC_REGNUM)
954 (compare:CCFP (match_operand:DF 0 "s_register_operand" "w")
955 (match_operand:DF 1 "vfp_compare_operand" "wG")))]
5b3e6663 956 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1 957 "#"
5b3e6663 958 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 959 [(set (reg:CCFP VFPCC_REGNUM)
960 (compare:CCFP (match_dup 0)
961 (match_dup 1)))
962 (set (reg:CCFP CC_REGNUM)
963 (reg:CCFPE VFPCC_REGNUM))]
964 ""
965)
966
967(define_insn_and_split "*cmpdf_trap_split_vfp"
968 [(set (reg:CCFPE CC_REGNUM)
969 (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w")
970 (match_operand:DF 1 "vfp_compare_operand" "wG")))]
5b3e6663 971 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1 972 "#"
5b3e6663 973 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 974 [(set (reg:CCFPE VFPCC_REGNUM)
975 (compare:CCFPE (match_dup 0)
976 (match_dup 1)))
977 (set (reg:CCFPE CC_REGNUM)
978 (reg:CCFPE VFPCC_REGNUM))]
979 ""
980)
981
982
983;; Comparison patterns
984
985(define_insn "*cmpsf_vfp"
986 [(set (reg:CCFP VFPCC_REGNUM)
f1adb0a9
JB		 987 (compare:CCFP (match_operand:SF 0 "s_register_operand" "t,t")
988 (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
5b3e6663 989 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 990 "@
991 fcmps%?\\t%0, %1
992 fcmpzs%?\\t%0"
993 [(set_attr "predicable" "yes")
51c69ddb 994 (set_attr "type" "fcmps")]
9b66ebb1
PB		 995)
996
997(define_insn "*cmpsf_trap_vfp"
998 [(set (reg:CCFPE VFPCC_REGNUM)
f1adb0a9
JB		 999 (compare:CCFPE (match_operand:SF 0 "s_register_operand" "t,t")
1000 (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
5b3e6663 1001 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 1002 "@
1003 fcmpes%?\\t%0, %1
1004 fcmpezs%?\\t%0"
1005 [(set_attr "predicable" "yes")
51c69ddb 1006 (set_attr "type" "fcmpd")]
9b66ebb1
PB		 1007)
1008
1009(define_insn "*cmpdf_vfp"
1010 [(set (reg:CCFP VFPCC_REGNUM)
1011 (compare:CCFP (match_operand:DF 0 "s_register_operand" "w,w")
1012 (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
5b3e6663 1013 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 1014 "@
1015 fcmpd%?\\t%P0, %P1
1016 fcmpzd%?\\t%P0"
1017 [(set_attr "predicable" "yes")
51c69ddb 1018 (set_attr "type" "fcmpd")]
9b66ebb1
PB		 1019)
1020
1021(define_insn "*cmpdf_trap_vfp"
1022 [(set (reg:CCFPE VFPCC_REGNUM)
1023 (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w,w")
1024 (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
5b3e6663 1025 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 1026 "@
1027 fcmped%?\\t%P0, %P1
1028 fcmpezd%?\\t%P0"
1029 [(set_attr "predicable" "yes")
51c69ddb 1030 (set_attr "type" "fcmpd")]
9b66ebb1
PB		 1031)
1032
1033
1034;; Store multiple insn used in function prologue.
1035
1036(define_insn "*push_multi_vfp"
1037 [(match_parallel 2 "multi_register_push"
1038 [(set (match_operand:BLK 0 "memory_operand" "=m")
1039 (unspec:BLK [(match_operand:DF 1 "s_register_operand" "w")]
1040 UNSPEC_PUSH_MULT))])]
5b3e6663 1041 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
8edfc4cc 1042 "* return vfp_output_fstmd (operands);"
75fe7b2f 1043 [(set_attr "type" "f_stored")]
9b66ebb1
PB		 1044)
1045
1046
1047;; Unimplemented insns:
1048;; fldm*
1049;; fstm*
1050;; fmdhr et al (VFPv1)
59b9a953 1051;; Support for xD (single precision only) variants.
9b66ebb1 1052;; fmrrs, fmsrr
Mirror of https://gcc.gnu.org/git/gcc.git