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3f4d9b98 | 1 | ;; ARM VFP instruction patterns |
8d9254fc | 2 | ;; Copyright (C) 2003-2020 Free Software Foundation, Inc. |
3f4d9b98 | 3 | ;; Written by CodeSourcery. |
9b66ebb1 PB |
4 | ;; |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published by | |
2f83c7d6 | 9 | ;; the Free Software Foundation; either version 3, or (at your option) |
9b66ebb1 PB |
10 | ;; any later version. |
11 | ;; | |
12 | ;; GCC is distributed in the hope that it will be useful, but | |
13 | ;; WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | ;; General Public License for more details. | |
16 | ;; | |
17 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | ;; along with GCC; see the file COPYING3. If not see |
19 | ;; <http://www.gnu.org/licenses/>. */ | |
9b66ebb1 | 20 | |
50df9464 MW |
21 | ;; Patterns for HI moves which provide more data transfer instructions when VFP |
22 | ;; support is enabled. | |
23 | (define_insn "*arm_movhi_vfp" | |
24 | [(set | |
25 | (match_operand:HI 0 "nonimmediate_operand" | |
26 | "=rk, r, r, m, r, *t, r, *t") | |
27 | (match_operand:HI 1 "general_operand" | |
28 | "rIk, K, n, r, mi, r, *t, *t"))] | |
00ea1506 | 29 | "TARGET_ARM && TARGET_HARD_FLOAT |
4ffc8099 | 30 | && !TARGET_VFP_FP16INST |
50df9464 MW |
31 | && (register_operand (operands[0], HImode) |
32 | || register_operand (operands[1], HImode))" | |
33 | { | |
34 | switch (which_alternative) | |
35 | { | |
36 | case 0: | |
37 | return "mov%?\t%0, %1\t%@ movhi"; | |
38 | case 1: | |
39 | return "mvn%?\t%0, #%B1\t%@ movhi"; | |
40 | case 2: | |
41 | return "movw%?\t%0, %L1\t%@ movhi"; | |
42 | case 3: | |
43 | return "strh%?\t%1, %0\t%@ movhi"; | |
44 | case 4: | |
45 | return "ldrh%?\t%0, %1\t%@ movhi"; | |
46 | case 5: | |
47 | case 6: | |
48 | return "vmov%?\t%0, %1\t%@ int"; | |
49 | case 7: | |
50 | return "vmov%?.f32\t%0, %1\t%@ int"; | |
51 | default: | |
52 | gcc_unreachable (); | |
53 | } | |
54 | } | |
55 | [(set_attr "predicable" "yes") | |
56 | (set_attr_alternative "type" | |
57 | [(if_then_else | |
58 | (match_operand 1 "const_int_operand" "") | |
59 | (const_string "mov_imm") | |
60 | (const_string "mov_reg")) | |
61 | (const_string "mvn_imm") | |
62 | (const_string "mov_imm") | |
89b2133e JG |
63 | (const_string "store_4") |
64 | (const_string "load_4") | |
50df9464 MW |
65 | (const_string "f_mcr") |
66 | (const_string "f_mrc") | |
67 | (const_string "fmov")]) | |
69ba69c9 | 68 | (set_attr "arch" "*, *, v6t2, *, *, *, *, *") |
50df9464 MW |
69 | (set_attr "pool_range" "*, *, *, *, 256, *, *, *") |
70 | (set_attr "neg_pool_range" "*, *, *, *, 244, *, *, *") | |
71 | (set_attr "length" "4")] | |
72 | ) | |
73 | ||
74 | (define_insn "*thumb2_movhi_vfp" | |
75 | [(set | |
76 | (match_operand:HI 0 "nonimmediate_operand" | |
c7be0832 | 77 | "=rk, r, l, r, m, r, *t, r, *t, Up, r") |
50df9464 | 78 | (match_operand:HI 1 "general_operand" |
c7be0832 SP |
79 | "rk, I, Py, n, r, m, r, *t, *t, r, Up"))] |
80 | "TARGET_THUMB2 && TARGET_VFP_BASE | |
4ffc8099 | 81 | && !TARGET_VFP_FP16INST |
50df9464 MW |
82 | && (register_operand (operands[0], HImode) |
83 | || register_operand (operands[1], HImode))" | |
84 | { | |
85 | switch (which_alternative) | |
86 | { | |
87 | case 0: | |
88 | case 1: | |
89 | case 2: | |
90 | return "mov%?\t%0, %1\t%@ movhi"; | |
91 | case 3: | |
92 | return "movw%?\t%0, %L1\t%@ movhi"; | |
93 | case 4: | |
94 | return "strh%?\t%1, %0\t%@ movhi"; | |
95 | case 5: | |
96 | return "ldrh%?\t%0, %1\t%@ movhi"; | |
97 | case 6: | |
98 | case 7: | |
99 | return "vmov%?\t%0, %1\t%@ int"; | |
100 | case 8: | |
101 | return "vmov%?.f32\t%0, %1\t%@ int"; | |
c7be0832 SP |
102 | case 9: |
103 | return "vmsr%?\t P0, %1\t@ movhi"; | |
104 | case 10: | |
105 | return "vmrs%?\t %0, P0\t@ movhi"; | |
50df9464 MW |
106 | default: |
107 | gcc_unreachable (); | |
108 | } | |
109 | } | |
110 | [(set_attr "predicable" "yes") | |
111 | (set_attr "predicable_short_it" | |
c7be0832 | 112 | "yes, no, yes, no, no, no, no, no, no, no, no") |
50df9464 | 113 | (set_attr "type" |
89b2133e | 114 | "mov_reg, mov_imm, mov_imm, mov_imm, store_4, load_4,\ |
c7be0832 SP |
115 | f_mcr, f_mrc, fmov, mve_move, mve_move") |
116 | (set_attr "arch" "*, *, *, v6t2, *, *, *, *, *, mve, mve") | |
117 | (set_attr "pool_range" "*, *, *, *, *, 4094, *, *, *, *, *") | |
118 | (set_attr "neg_pool_range" "*, *, *, *, *, 250, *, *, *, *, *") | |
119 | (set_attr "length" "2, 4, 2, 4, 4, 4, 4, 4, 4, 4, 4")] | |
50df9464 MW |
120 | ) |
121 | ||
4ffc8099 MW |
122 | ;; Patterns for HI moves which provide more data transfer instructions when FP16 |
123 | ;; instructions are available. | |
124 | (define_insn "*arm_movhi_fp16" | |
125 | [(set | |
126 | (match_operand:HI 0 "nonimmediate_operand" | |
127 | "=r, r, r, m, r, *t, r, *t") | |
128 | (match_operand:HI 1 "general_operand" | |
129 | "rIk, K, n, r, mi, r, *t, *t"))] | |
130 | "TARGET_ARM && TARGET_VFP_FP16INST | |
131 | && (register_operand (operands[0], HImode) | |
132 | || register_operand (operands[1], HImode))" | |
133 | { | |
134 | switch (which_alternative) | |
135 | { | |
136 | case 0: | |
137 | return "mov%?\t%0, %1\t%@ movhi"; | |
138 | case 1: | |
139 | return "mvn%?\t%0, #%B1\t%@ movhi"; | |
140 | case 2: | |
141 | return "movw%?\t%0, %L1\t%@ movhi"; | |
142 | case 3: | |
143 | return "strh%?\t%1, %0\t%@ movhi"; | |
144 | case 4: | |
145 | return "ldrh%?\t%0, %1\t%@ movhi"; | |
146 | case 5: | |
147 | case 6: | |
5b2b17db | 148 | return "vmov.f16\t%0, %1\t%@ int"; |
4ffc8099 MW |
149 | case 7: |
150 | return "vmov%?.f32\t%0, %1\t%@ int"; | |
151 | default: | |
152 | gcc_unreachable (); | |
153 | } | |
154 | } | |
5b2b17db | 155 | [(set_attr "predicable" "yes, yes, yes, yes, yes, no, no, yes") |
4ffc8099 MW |
156 | (set_attr_alternative "type" |
157 | [(if_then_else | |
158 | (match_operand 1 "const_int_operand" "") | |
159 | (const_string "mov_imm") | |
160 | (const_string "mov_reg")) | |
161 | (const_string "mvn_imm") | |
162 | (const_string "mov_imm") | |
89b2133e JG |
163 | (const_string "store_4") |
164 | (const_string "load_4") | |
4ffc8099 MW |
165 | (const_string "f_mcr") |
166 | (const_string "f_mrc") | |
167 | (const_string "fmov")]) | |
69ba69c9 | 168 | (set_attr "arch" "*, *, v6t2, *, *, *, *, *") |
4ffc8099 MW |
169 | (set_attr "pool_range" "*, *, *, *, 256, *, *, *") |
170 | (set_attr "neg_pool_range" "*, *, *, *, 244, *, *, *") | |
171 | (set_attr "length" "4")] | |
172 | ) | |
173 | ||
174 | (define_insn "*thumb2_movhi_fp16" | |
175 | [(set | |
176 | (match_operand:HI 0 "nonimmediate_operand" | |
c7be0832 | 177 | "=rk, r, l, r, m, r, *t, r, *t, Up, r") |
4ffc8099 | 178 | (match_operand:HI 1 "general_operand" |
c7be0832 SP |
179 | "rk, I, Py, n, r, m, r, *t, *t, r, Up"))] |
180 | "TARGET_THUMB2 && (TARGET_VFP_FP16INST || TARGET_HAVE_MVE) | |
4ffc8099 MW |
181 | && (register_operand (operands[0], HImode) |
182 | || register_operand (operands[1], HImode))" | |
183 | { | |
184 | switch (which_alternative) | |
185 | { | |
186 | case 0: | |
187 | case 1: | |
188 | case 2: | |
189 | return "mov%?\t%0, %1\t%@ movhi"; | |
190 | case 3: | |
191 | return "movw%?\t%0, %L1\t%@ movhi"; | |
192 | case 4: | |
193 | return "strh%?\t%1, %0\t%@ movhi"; | |
194 | case 5: | |
195 | return "ldrh%?\t%0, %1\t%@ movhi"; | |
196 | case 6: | |
197 | case 7: | |
5b2b17db | 198 | return "vmov.f16\t%0, %1\t%@ int"; |
4ffc8099 MW |
199 | case 8: |
200 | return "vmov%?.f32\t%0, %1\t%@ int"; | |
c7be0832 | 201 | case 9: |
ef684c78 | 202 | return "vmsr%?\t P0, %1\t%@ movhi"; |
c7be0832 SP |
203 | case 10: |
204 | return "vmrs%?\t%0, P0\t%@ movhi"; | |
4ffc8099 MW |
205 | default: |
206 | gcc_unreachable (); | |
207 | } | |
208 | } | |
5b2b17db | 209 | [(set_attr "predicable" |
c7be0832 | 210 | "yes, yes, yes, yes, yes, yes, no, no, yes, yes, yes") |
4ffc8099 | 211 | (set_attr "predicable_short_it" |
c7be0832 | 212 | "yes, no, yes, no, no, no, no, no, no, no, no") |
4ffc8099 | 213 | (set_attr "type" |
89b2133e | 214 | "mov_reg, mov_imm, mov_imm, mov_imm, store_4, load_4,\ |
c7be0832 SP |
215 | f_mcr, f_mrc, fmov, mve_move, mve_move") |
216 | (set_attr "arch" "*, *, *, v6t2, *, *, *, *, *, mve, mve") | |
217 | (set_attr "pool_range" "*, *, *, *, *, 4094, *, *, *, *, *") | |
218 | (set_attr "neg_pool_range" "*, *, *, *, *, 250, *, *, *, *, *") | |
219 | (set_attr "length" "2, 4, 2, 4, 4, 4, 4, 4, 4, 4, 4")] | |
4ffc8099 MW |
220 | ) |
221 | ||
9b66ebb1 PB |
222 | ;; SImode moves |
223 | ;; ??? For now do not allow loading constants into vfp regs. This causes | |
59b9a953 | 224 | ;; problems because small constants get converted into adds. |
9b66ebb1 | 225 | (define_insn "*arm_movsi_vfp" |
f5c630c3 | 226 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *Uv") |
d58bc084 | 227 | (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))] |
00ea1506 | 228 | "TARGET_ARM && TARGET_HARD_FLOAT |
9b66ebb1 PB |
229 | && ( s_register_operand (operands[0], SImode) |
230 | || s_register_operand (operands[1], SImode))" | |
5b3e6663 PB |
231 | "* |
232 | switch (which_alternative) | |
233 | { | |
f5c630c3 | 234 | case 0: case 1: |
5b3e6663 | 235 | return \"mov%?\\t%0, %1\"; |
5b3e6663 | 236 | case 2: |
f5c630c3 | 237 | return \"mvn%?\\t%0, #%B1\"; |
5b3e6663 | 238 | case 3: |
f5c630c3 | 239 | return \"movw%?\\t%0, %1\"; |
5b3e6663 | 240 | case 4: |
f5c630c3 | 241 | return \"ldr%?\\t%0, %1\"; |
5b3e6663 | 242 | case 5: |
f5c630c3 | 243 | return \"str%?\\t%1, %0\"; |
5b3e6663 | 244 | case 6: |
35cb3e53 | 245 | return \"vmov%?\\t%0, %1\\t%@ int\"; |
5b3e6663 | 246 | case 7: |
35cb3e53 | 247 | return \"vmov%?\\t%0, %1\\t%@ int\"; |
f5c630c3 | 248 | case 8: |
35cb3e53 | 249 | return \"vmov%?.f32\\t%0, %1\\t%@ int\"; |
f5c630c3 | 250 | case 9: case 10: |
5b3e6663 PB |
251 | return output_move_vfp (operands); |
252 | default: | |
253 | gcc_unreachable (); | |
254 | } | |
255 | " | |
256 | [(set_attr "predicable" "yes") | |
89b2133e | 257 | (set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load_4,store_4, |
5b2b17db | 258 | f_mcr,f_mrc,fmov,f_loads,f_stores") |
f5c630c3 PB |
259 | (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*") |
260 | (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")] | |
5b3e6663 PB |
261 | ) |
262 | ||
28907f9a MS |
263 | ;; See thumb2.md:thumb2_movsi_insn for an explanation of the split |
264 | ;; high/low register alternatives for loads and stores here. | |
956a95a5 KT |
265 | ;; The l/Py alternative should come after r/I to ensure that the short variant |
266 | ;; is chosen with length 2 when the instruction is predicated for | |
267 | ;; arm_restrict_it. | |
5b3e6663 | 268 | (define_insn "*thumb2_movsi_vfp" |
c7be0832 SP |
269 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r,l,*hk,m,*m,*t,\ |
270 | r,*t,*t,*Uv, Up, r,Uf,r") | |
271 | (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,*mi,l,*hk,r,*t,\ | |
272 | *t,*UvTu,*t, r, Up,r,Uf"))] | |
273 | "TARGET_THUMB2 && TARGET_VFP_BASE | |
5b3e6663 PB |
274 | && ( s_register_operand (operands[0], SImode) |
275 | || s_register_operand (operands[1], SImode))" | |
276 | "* | |
277 | switch (which_alternative) | |
278 | { | |
956a95a5 KT |
279 | case 0: |
280 | case 1: | |
5b3e6663 | 281 | case 2: |
956a95a5 | 282 | return \"mov%?\\t%0, %1\"; |
5b3e6663 | 283 | case 3: |
956a95a5 | 284 | return \"mvn%?\\t%0, #%B1\"; |
5b3e6663 | 285 | case 4: |
956a95a5 | 286 | return \"movw%?\\t%0, %1\"; |
5b3e6663 | 287 | case 5: |
c7be0832 | 288 | case 6: |
8d33eae8 TP |
289 | /* Cannot load it directly, split to load it via MOV / MOVT. */ |
290 | if (!MEM_P (operands[1]) && arm_disable_literal_pool) | |
291 | return \"#\"; | |
956a95a5 | 292 | return \"ldr%?\\t%0, %1\"; |
75088696 | 293 | case 7: |
75088696 | 294 | case 8: |
c7be0832 | 295 | return \"str%?\\t%1, %0\"; |
75088696 | 296 | case 9: |
c7be0832 SP |
297 | return \"vmov%?\\t%0, %1\\t%@ int\"; |
298 | case 10: | |
299 | return \"vmov%?\\t%0, %1\\t%@ int\"; | |
300 | case 11: | |
35cb3e53 | 301 | return \"vmov%?.f32\\t%0, %1\\t%@ int\"; |
c7be0832 | 302 | case 12: case 13: |
5b3e6663 | 303 | return output_move_vfp (operands); |
c7be0832 SP |
304 | case 14: |
305 | return \"vmsr\\t P0, %1\"; | |
306 | case 15: | |
307 | return \"vmrs\\t %0, P0\"; | |
308 | case 16: | |
309 | return \"mcr\\tp10, 7, %1, cr1, cr0, 0\\t @SET_FPSCR\"; | |
310 | case 17: | |
311 | return \"mrc\\tp10, 7, %0, cr1, cr0, 0\\t @GET_FPSCR\"; | |
5b3e6663 PB |
312 | default: |
313 | gcc_unreachable (); | |
314 | } | |
315 | " | |
9b66ebb1 | 316 | [(set_attr "predicable" "yes") |
c7be0832 SP |
317 | (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no,no,no,no,no,\ |
318 | no,no,no,no,no") | |
319 | (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_imm,load_4,load_4,\ | |
320 | store_4,store_4,f_mcr,f_mrc,fmov,f_loads,f_stores,mve_move,\ | |
321 | mve_move,mrs,mrs") | |
322 | (set_attr "length" "2,4,2,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4") | |
323 | (set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*,*,*,*,1018,*,*,*,*,*") | |
324 | (set_attr "arch" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,mve,mve,mve,mve") | |
325 | (set_attr "neg_pool_range" "*,*,*,*,*, 0, 0,*,*,*,*,*,1008,*,*,*,*,*")] | |
9b66ebb1 PB |
326 | ) |
327 | ||
328 | ||
329 | ;; DImode moves | |
330 | ||
0127c76f | 331 | (define_insn "*movdi_vfp" |
02204940 | 332 | [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,!r,w,w, Uv") |
c7be0832 SP |
333 | (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,r,r,w,w,UvTu,w"))] |
334 | "TARGET_32BIT && TARGET_VFP_BASE | |
7baa7c13 | 335 | && ( register_operand (operands[0], DImode) |
00a3a76a | 336 | || register_operand (operands[1], DImode)) |
c7be0832 SP |
337 | && !((TARGET_NEON || TARGET_HAVE_MVE) && CONST_INT_P (operands[1]) |
338 | && simd_immediate_valid_for_move (operands[1], DImode, NULL, NULL))" | |
7baa7c13 BS |
339 | "* |
340 | switch (which_alternative) | |
341 | { | |
342 | case 0: | |
7baa7c13 BS |
343 | case 1: |
344 | case 2: | |
7baa7c13 | 345 | case 3: |
0127c76f | 346 | return \"#\"; |
7baa7c13 | 347 | case 4: |
7baa7c13 | 348 | case 5: |
8d33eae8 TP |
349 | /* Cannot load it directly, split to load it via MOV / MOVT. */ |
350 | if (!MEM_P (operands[1]) && arm_disable_literal_pool) | |
351 | return \"#\"; | |
352 | /* Fall through. */ | |
0127c76f | 353 | case 6: |
3598da80 | 354 | return output_move_double (operands, true, NULL); |
0127c76f | 355 | case 7: |
35cb3e53 | 356 | return \"vmov%?\\t%P0, %Q1, %R1\\t%@ int\"; |
0127c76f | 357 | case 8: |
35cb3e53 | 358 | return \"vmov%?\\t%Q0, %R0, %P1\\t%@ int\"; |
0127c76f | 359 | case 9: |
c7be0832 | 360 | if (TARGET_VFP_SINGLE || TARGET_HAVE_MVE) |
35cb3e53 | 361 | return \"vmov%?.f32\\t%0, %1\\t%@ int\;vmov%?.f32\\t%p0, %p1\\t%@ int\"; |
7baa7c13 | 362 | else |
35cb3e53 | 363 | return \"vmov%?.f64\\t%P0, %P1\\t%@ int\"; |
0127c76f | 364 | case 10: case 11: |
7baa7c13 BS |
365 | return output_move_vfp (operands); |
366 | default: | |
367 | gcc_unreachable (); | |
368 | } | |
369 | " | |
89b2133e | 370 | [(set_attr "type" "multiple,multiple,multiple,multiple,load_8,load_8,store_8,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored") |
1df07b3d | 371 | (set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 8) |
0127c76f RR |
372 | (eq_attr "alternative" "2") (const_int 12) |
373 | (eq_attr "alternative" "3") (const_int 16) | |
1df07b3d WD |
374 | (eq_attr "alternative" "4,5,6") |
375 | (symbol_ref "arm_count_output_move_double_insns (operands) * 4") | |
0127c76f RR |
376 | (eq_attr "alternative" "9") |
377 | (if_then_else | |
b75b1be2 | 378 | (match_test "TARGET_VFP_SINGLE") |
0127c76f RR |
379 | (const_int 8) |
380 | (const_int 4))] | |
381 | (const_int 4))) | |
1df07b3d | 382 | (set_attr "predicable" "yes") |
88f519b2 MGD |
383 | (set_attr "arm_pool_range" "*,*,*,*,1020,4096,*,*,*,*,1020,*") |
384 | (set_attr "thumb2_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*") | |
635a48fb | 385 | (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*") |
1df07b3d | 386 | (set (attr "ce_count") (symbol_ref "get_attr_length (insn) / 4")) |
0127c76f | 387 | (set_attr "arch" "t2,any,any,any,a,t2,any,any,any,any,any,any")] |
7baa7c13 BS |
388 | ) |
389 | ||
2e87b2f4 | 390 | ;; HFmode and BFmode moves |
4ffc8099 | 391 | |
2e87b2f4 SMW |
392 | (define_insn "*mov<mode>_vfp_<mode>16" |
393 | [(set (match_operand:HFBF 0 "nonimmediate_operand" | |
6abd4286 | 394 | "= ?r,?m,t,r,t,r,t, t, Uj,r") |
2e87b2f4 | 395 | (match_operand:HFBF 1 "general_operand" |
6abd4286 | 396 | " m,r,t,r,r,t,Dv,Uj,t, F"))] |
4ffc8099 | 397 | "TARGET_32BIT |
6abd4286 | 398 | && (TARGET_VFP_FP16INST || TARGET_HAVE_MVE) |
2e87b2f4 SMW |
399 | && (s_register_operand (operands[0], <MODE>mode) |
400 | || s_register_operand (operands[1], <MODE>mode))" | |
4ffc8099 MW |
401 | { |
402 | switch (which_alternative) | |
403 | { | |
404 | case 0: /* ARM register from memory. */ | |
2e87b2f4 | 405 | return \"ldrh%?\\t%0, %1\\t%@ __<fporbf>\"; |
4ffc8099 | 406 | case 1: /* Memory from ARM register. */ |
2e87b2f4 | 407 | return \"strh%?\\t%1, %0\\t%@ __<fporbf>\"; |
4ffc8099 | 408 | case 2: /* S register from S register. */ |
2e87b2f4 | 409 | return \"vmov\\t%0, %1\t%@ __<fporbf>\"; |
4ffc8099 | 410 | case 3: /* ARM register from ARM register. */ |
2e87b2f4 | 411 | return \"mov%?\\t%0, %1\\t%@ __<fporbf>\"; |
4ffc8099 MW |
412 | case 4: /* S register from ARM register. */ |
413 | case 5: /* ARM register from S register. */ | |
414 | case 6: /* S register from immediate. */ | |
2e87b2f4 | 415 | return \"vmov.f16\\t%0, %1\t%@ __<fporbf>\"; |
4ffc8099 | 416 | case 7: /* S register from memory. */ |
6abd4286 RS |
417 | if (TARGET_HAVE_MVE) |
418 | return \"vldr.16\\t%0, %1\"; | |
419 | else | |
420 | return \"vld1.16\\t{%z0}, %A1\"; | |
4ffc8099 | 421 | case 8: /* Memory from S register. */ |
6abd4286 RS |
422 | if (TARGET_HAVE_MVE) |
423 | return \"vstr.16\\t%1, %0\"; | |
424 | else | |
425 | return \"vst1.16\\t{%z1}, %A0\"; | |
4ffc8099 MW |
426 | case 9: /* ARM register from constant. */ |
427 | { | |
428 | long bits; | |
429 | rtx ops[4]; | |
430 | ||
431 | bits = real_to_target (NULL, CONST_DOUBLE_REAL_VALUE (operands[1]), | |
2e87b2f4 | 432 | <MODE>mode); |
4ffc8099 MW |
433 | ops[0] = operands[0]; |
434 | ops[1] = GEN_INT (bits); | |
435 | ops[2] = GEN_INT (bits & 0xff00); | |
436 | ops[3] = GEN_INT (bits & 0x00ff); | |
437 | ||
438 | if (arm_arch_thumb2) | |
439 | output_asm_insn (\"movw\\t%0, %1\", ops); | |
440 | else | |
441 | output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops); | |
442 | return \"\"; | |
443 | } | |
444 | default: | |
445 | gcc_unreachable (); | |
446 | } | |
447 | } | |
1500cb68 SD |
448 | [(set_attr "conds" "*, *, unconditional, *, unconditional, unconditional,\ |
449 | unconditional, unconditional, unconditional,\ | |
450 | unconditional") | |
451 | (set_attr "predicable" "yes, yes, no, yes, no, no, no, no, no, no") | |
4ffc8099 MW |
452 | (set_attr "predicable_short_it" "no, no, no, yes,\ |
453 | no, no, no, no,\ | |
454 | no, no") | |
455 | (set_attr_alternative "type" | |
89b2133e | 456 | [(const_string "load_4") (const_string "store_4") |
4ffc8099 MW |
457 | (const_string "fmov") (const_string "mov_reg") |
458 | (const_string "f_mcr") (const_string "f_mrc") | |
459 | (const_string "fconsts") (const_string "neon_load1_1reg") | |
460 | (const_string "neon_store1_1reg") | |
461 | (if_then_else (match_test "arm_arch_thumb2") | |
462 | (const_string "mov_imm") | |
463 | (const_string "multiple"))]) | |
464 | (set_attr_alternative "length" | |
465 | [(const_int 4) (const_int 4) | |
466 | (const_int 4) (const_int 4) | |
467 | (const_int 4) (const_int 4) | |
468 | (const_int 4) (const_int 4) | |
469 | (const_int 4) | |
470 | (if_then_else (match_test "arm_arch_thumb2") | |
471 | (const_int 4) | |
472 | (const_int 8))])] | |
473 | ) | |
474 | ||
2e87b2f4 SMW |
475 | (define_insn "*mov<mode>_vfp_neon" |
476 | [(set (match_operand:HFBF 0 "nonimmediate_operand" "= t,Um,?r,?m,t,r,t,r,r") | |
477 | (match_operand:HFBF 1 "general_operand" " Um, t, m, r,t,r,r,t,F"))] | |
4ffc8099 MW |
478 | "TARGET_32BIT |
479 | && TARGET_HARD_FLOAT && TARGET_NEON_FP16 | |
480 | && !TARGET_VFP_FP16INST | |
2e87b2f4 SMW |
481 | && ( s_register_operand (operands[0], <MODE>mode) |
482 | || s_register_operand (operands[1], <MODE>mode))" | |
0fd8c3ad SL |
483 | "* |
484 | switch (which_alternative) | |
485 | { | |
486 | case 0: /* S register from memory */ | |
487 | return \"vld1.16\\t{%z0}, %A1\"; | |
488 | case 1: /* memory from S register */ | |
489 | return \"vst1.16\\t{%z1}, %A0\"; | |
490 | case 2: /* ARM register from memory */ | |
2e87b2f4 | 491 | return \"ldrh\\t%0, %1\\t%@ __<fporbf>\"; |
0fd8c3ad | 492 | case 3: /* memory from ARM register */ |
2e87b2f4 | 493 | return \"strh\\t%1, %0\\t%@ __<fporbf>\"; |
0fd8c3ad | 494 | case 4: /* S register from S register */ |
35cb3e53 | 495 | return \"vmov.f32\\t%0, %1\"; |
0fd8c3ad | 496 | case 5: /* ARM register from ARM register */ |
2e87b2f4 | 497 | return \"mov\\t%0, %1\\t%@ __<fporbf>\"; |
0fd8c3ad | 498 | case 6: /* S register from ARM register */ |
35cb3e53 | 499 | return \"vmov\\t%0, %1\"; |
0fd8c3ad | 500 | case 7: /* ARM register from S register */ |
35cb3e53 | 501 | return \"vmov\\t%0, %1\"; |
0fd8c3ad SL |
502 | case 8: /* ARM register from constant */ |
503 | { | |
0fd8c3ad SL |
504 | long bits; |
505 | rtx ops[4]; | |
506 | ||
34a72c33 | 507 | bits = real_to_target (NULL, CONST_DOUBLE_REAL_VALUE (operands[1]), |
2e87b2f4 | 508 | <MODE>mode); |
0fd8c3ad SL |
509 | ops[0] = operands[0]; |
510 | ops[1] = GEN_INT (bits); | |
511 | ops[2] = GEN_INT (bits & 0xff00); | |
512 | ops[3] = GEN_INT (bits & 0x00ff); | |
513 | ||
514 | if (arm_arch_thumb2) | |
515 | output_asm_insn (\"movw\\t%0, %1\", ops); | |
516 | else | |
517 | output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops); | |
518 | return \"\"; | |
519 | } | |
520 | default: | |
521 | gcc_unreachable (); | |
522 | } | |
523 | " | |
524 | [(set_attr "conds" "unconditional") | |
f7379e5e | 525 | (set_attr "type" "neon_load1_1reg,neon_store1_1reg,\ |
89b2133e | 526 | load_4,store_4,fmov,mov_reg,f_mcr,f_mrc,multiple") |
0fd8c3ad SL |
527 | (set_attr "length" "4,4,4,4,4,4,4,4,8")] |
528 | ) | |
529 | ||
e0dc3601 | 530 | ;; FP16 without element load/store instructions. |
2e87b2f4 SMW |
531 | (define_insn "*mov<mode>_vfp" |
532 | [(set (match_operand:HFBF 0 "nonimmediate_operand" "=r,m,t,r,t,r,r") | |
533 | (match_operand:HFBF 1 "general_operand" " m,r,t,r,r,t,F"))] | |
4ffc8099 | 534 | "TARGET_32BIT |
00ea1506 | 535 | && TARGET_HARD_FLOAT |
1b81a1c1 | 536 | && !TARGET_NEON_FP16 |
4ffc8099 | 537 | && !TARGET_VFP_FP16INST |
2e87b2f4 SMW |
538 | && ( s_register_operand (operands[0], <MODE>mode) |
539 | || s_register_operand (operands[1], <MODE>mode))" | |
e0dc3601 PB |
540 | "* |
541 | switch (which_alternative) | |
542 | { | |
543 | case 0: /* ARM register from memory */ | |
2e87b2f4 | 544 | return \"ldrh\\t%0, %1\\t%@ __<fporbf>\"; |
e0dc3601 | 545 | case 1: /* memory from ARM register */ |
2e87b2f4 | 546 | return \"strh\\t%1, %0\\t%@ __<fporbf>\"; |
e0dc3601 | 547 | case 2: /* S register from S register */ |
35cb3e53 | 548 | return \"vmov.f32\\t%0, %1\"; |
e0dc3601 | 549 | case 3: /* ARM register from ARM register */ |
2e87b2f4 | 550 | return \"mov\\t%0, %1\\t%@ __<fporbf>\"; |
e0dc3601 | 551 | case 4: /* S register from ARM register */ |
35cb3e53 | 552 | return \"vmov\\t%0, %1\"; |
e0dc3601 | 553 | case 5: /* ARM register from S register */ |
35cb3e53 | 554 | return \"vmov\\t%0, %1\"; |
e0dc3601 PB |
555 | case 6: /* ARM register from constant */ |
556 | { | |
e0dc3601 PB |
557 | long bits; |
558 | rtx ops[4]; | |
559 | ||
34a72c33 | 560 | bits = real_to_target (NULL, CONST_DOUBLE_REAL_VALUE (operands[1]), |
2e87b2f4 | 561 | <MODE>mode); |
e0dc3601 PB |
562 | ops[0] = operands[0]; |
563 | ops[1] = GEN_INT (bits); | |
564 | ops[2] = GEN_INT (bits & 0xff00); | |
565 | ops[3] = GEN_INT (bits & 0x00ff); | |
566 | ||
567 | if (arm_arch_thumb2) | |
568 | output_asm_insn (\"movw\\t%0, %1\", ops); | |
569 | else | |
570 | output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops); | |
571 | return \"\"; | |
572 | } | |
573 | default: | |
574 | gcc_unreachable (); | |
575 | } | |
576 | " | |
577 | [(set_attr "conds" "unconditional") | |
89b2133e | 578 | (set_attr "type" "load_4,store_4,fmov,mov_reg,f_mcr,f_mrc,multiple") |
e0dc3601 PB |
579 | (set_attr "length" "4,4,4,4,4,4,8")] |
580 | ) | |
581 | ||
9b66ebb1 PB |
582 | |
583 | ;; SFmode moves | |
221b2a64 PB |
584 | ;; Disparage the w<->r cases because reloading an invalid address is |
585 | ;; preferable to loading the value via integer registers. | |
9b66ebb1 PB |
586 | |
587 | (define_insn "*movsf_vfp" | |
f1adb0a9 | 588 | [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t ,t ,Uv,r ,m,t,r") |
35cb3e53 | 589 | (match_operand:SF 1 "general_operand" " ?r,t,Dv,UvE,t, mE,r,t,r"))] |
00ea1506 | 590 | "TARGET_ARM && TARGET_HARD_FLOAT |
9b66ebb1 PB |
591 | && ( s_register_operand (operands[0], SFmode) |
592 | || s_register_operand (operands[1], SFmode))" | |
5b3e6663 PB |
593 | "* |
594 | switch (which_alternative) | |
595 | { | |
596 | case 0: | |
35cb3e53 | 597 | return \"vmov%?\\t%0, %1\"; |
5b3e6663 | 598 | case 1: |
35cb3e53 | 599 | return \"vmov%?\\t%0, %1\"; |
f1adb0a9 | 600 | case 2: |
35cb3e53 | 601 | return \"vmov%?.f32\\t%0, %1\"; |
f1adb0a9 | 602 | case 3: case 4: |
5b3e6663 | 603 | return output_move_vfp (operands); |
5b3e6663 | 604 | case 5: |
f1adb0a9 | 605 | return \"ldr%?\\t%0, %1\\t%@ float\"; |
5b3e6663 | 606 | case 6: |
f1adb0a9 | 607 | return \"str%?\\t%1, %0\\t%@ float\"; |
5b3e6663 | 608 | case 7: |
35cb3e53 | 609 | return \"vmov%?.f32\\t%0, %1\"; |
f1adb0a9 | 610 | case 8: |
5b3e6663 PB |
611 | return \"mov%?\\t%0, %1\\t%@ float\"; |
612 | default: | |
613 | gcc_unreachable (); | |
614 | } | |
615 | " | |
9b66ebb1 | 616 | [(set_attr "predicable" "yes") |
f1adb0a9 | 617 | (set_attr "type" |
89b2133e | 618 | "f_mcr,f_mrc,fconsts,f_loads,f_stores,load_4,store_4,fmov,mov_reg") |
f1adb0a9 JB |
619 | (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*") |
620 | (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")] | |
9b66ebb1 PB |
621 | ) |
622 | ||
5b3e6663 | 623 | (define_insn "*thumb2_movsf_vfp" |
f1adb0a9 | 624 | [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t, t ,Uv,r ,m,t,r") |
8d33eae8 | 625 | (match_operand:SF 1 "hard_sf_operand" " ?r,t,Dv,UvHa,t, mHa,r,t,r"))] |
c7be0832 | 626 | "TARGET_THUMB2 && TARGET_VFP_BASE |
5b3e6663 PB |
627 | && ( s_register_operand (operands[0], SFmode) |
628 | || s_register_operand (operands[1], SFmode))" | |
629 | "* | |
630 | switch (which_alternative) | |
631 | { | |
632 | case 0: | |
35cb3e53 | 633 | return \"vmov%?\\t%0, %1\"; |
5b3e6663 | 634 | case 1: |
35cb3e53 | 635 | return \"vmov%?\\t%0, %1\"; |
f1adb0a9 | 636 | case 2: |
35cb3e53 | 637 | return \"vmov%?.f32\\t%0, %1\"; |
f1adb0a9 | 638 | case 3: case 4: |
5b3e6663 | 639 | return output_move_vfp (operands); |
5b3e6663 | 640 | case 5: |
f1adb0a9 | 641 | return \"ldr%?\\t%0, %1\\t%@ float\"; |
5b3e6663 | 642 | case 6: |
f1adb0a9 | 643 | return \"str%?\\t%1, %0\\t%@ float\"; |
5b3e6663 | 644 | case 7: |
35cb3e53 | 645 | return \"vmov%?.f32\\t%0, %1\"; |
f1adb0a9 | 646 | case 8: |
5b3e6663 PB |
647 | return \"mov%?\\t%0, %1\\t%@ float\"; |
648 | default: | |
649 | gcc_unreachable (); | |
650 | } | |
651 | " | |
652 | [(set_attr "predicable" "yes") | |
f1adb0a9 | 653 | (set_attr "type" |
89b2133e | 654 | "f_mcr,f_mrc,fconsts,f_loads,f_stores,load_4,store_4,fmov,mov_reg") |
88f519b2 | 655 | (set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*") |
f1adb0a9 | 656 | (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")] |
5b3e6663 PB |
657 | ) |
658 | ||
9b66ebb1 PB |
659 | ;; DFmode moves |
660 | ||
661 | (define_insn "*movdf_vfp" | |
c76623e7 JW |
662 | [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w,w ,Uv,r, m,w,r") |
663 | (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,G,UvF,w ,mF,r,w,r"))] | |
00ea1506 | 664 | "TARGET_ARM && TARGET_HARD_FLOAT |
d5b6e637 PB |
665 | && ( register_operand (operands[0], DFmode) |
666 | || register_operand (operands[1], DFmode))" | |
9b66ebb1 PB |
667 | "* |
668 | { | |
669 | switch (which_alternative) | |
670 | { | |
671 | case 0: | |
35cb3e53 | 672 | return \"vmov%?\\t%P0, %Q1, %R1\"; |
9b66ebb1 | 673 | case 1: |
35cb3e53 | 674 | return \"vmov%?\\t%Q0, %R0, %P1\"; |
f1adb0a9 | 675 | case 2: |
e0dc3601 | 676 | gcc_assert (TARGET_VFP_DOUBLE); |
35cb3e53 | 677 | return \"vmov%?.f64\\t%P0, %1\"; |
c76623e7 JW |
678 | case 3: |
679 | gcc_assert (TARGET_VFP_DOUBLE); | |
680 | return \"vmov.i64\\t%P0, #0\\t%@ float\"; | |
681 | case 4: case 5: | |
5b3e6663 | 682 | return output_move_vfp (operands); |
c76623e7 | 683 | case 6: case 7: |
3598da80 | 684 | return output_move_double (operands, true, NULL); |
c76623e7 | 685 | case 8: |
e0dc3601 | 686 | if (TARGET_VFP_SINGLE) |
35cb3e53 | 687 | return \"vmov%?.f32\\t%0, %1\;vmov%?.f32\\t%p0, %p1\"; |
e0dc3601 | 688 | else |
35cb3e53 | 689 | return \"vmov%?.f64\\t%P0, %P1\"; |
c76623e7 | 690 | case 9: |
9b901d50 | 691 | return \"#\"; |
9b66ebb1 | 692 | default: |
e6d29d15 | 693 | gcc_unreachable (); |
9b66ebb1 PB |
694 | } |
695 | } | |
696 | " | |
c76623e7 | 697 | [(set_attr "type" "f_mcrr,f_mrrc,fconstd,neon_move,f_loadd,f_stored,\ |
89b2133e | 698 | load_8,store_8,ffarithd,multiple") |
c76623e7 JW |
699 | (set (attr "length") (cond [(eq_attr "alternative" "6,7,9") (const_int 8) |
700 | (eq_attr "alternative" "8") | |
e0dc3601 | 701 | (if_then_else |
b75b1be2 | 702 | (match_test "TARGET_VFP_SINGLE") |
e0dc3601 PB |
703 | (const_int 8) |
704 | (const_int 4))] | |
705 | (const_int 4))) | |
c76623e7 JW |
706 | (set_attr "predicable" "yes,yes,yes,no,yes,yes,yes,yes,yes,yes") |
707 | (set_attr "pool_range" "*,*,*,*,1020,*,1020,*,*,*") | |
708 | (set_attr "neg_pool_range" "*,*,*,*,1004,*,1004,*,*,*") | |
709 | (set_attr "arch" "any,any,any,neon,any,any,any,any,any,any")] | |
9b66ebb1 PB |
710 | ) |
711 | ||
5b3e6663 | 712 | (define_insn "*thumb2_movdf_vfp" |
c76623e7 | 713 | [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w,w ,Uv,r ,m,w,r") |
8d33eae8 | 714 | (match_operand:DF 1 "hard_df_operand" " ?r,w,Dy,G,UvHa,w, mHa,r, w,r"))] |
c7be0832 | 715 | "TARGET_THUMB2 && TARGET_VFP_BASE |
de7c74be RB |
716 | && ( register_operand (operands[0], DFmode) |
717 | || register_operand (operands[1], DFmode))" | |
5b3e6663 PB |
718 | "* |
719 | { | |
720 | switch (which_alternative) | |
721 | { | |
722 | case 0: | |
35cb3e53 | 723 | return \"vmov%?\\t%P0, %Q1, %R1\"; |
5b3e6663 | 724 | case 1: |
35cb3e53 | 725 | return \"vmov%?\\t%Q0, %R0, %P1\"; |
f1adb0a9 | 726 | case 2: |
e0dc3601 | 727 | gcc_assert (TARGET_VFP_DOUBLE); |
35cb3e53 | 728 | return \"vmov%?.f64\\t%P0, %1\"; |
c76623e7 JW |
729 | case 3: |
730 | gcc_assert (TARGET_VFP_DOUBLE); | |
731 | return \"vmov.i64\\t%P0, #0\\t%@ float\"; | |
732 | case 4: case 5: | |
5b3e6663 | 733 | return output_move_vfp (operands); |
c76623e7 | 734 | case 6: case 7: case 9: |
3598da80 | 735 | return output_move_double (operands, true, NULL); |
c76623e7 | 736 | case 8: |
e0dc3601 | 737 | if (TARGET_VFP_SINGLE) |
35cb3e53 | 738 | return \"vmov%?.f32\\t%0, %1\;vmov%?.f32\\t%p0, %p1\"; |
e0dc3601 | 739 | else |
35cb3e53 | 740 | return \"vmov%?.f64\\t%P0, %P1\"; |
5b3e6663 PB |
741 | default: |
742 | abort (); | |
743 | } | |
744 | } | |
745 | " | |
c76623e7 | 746 | [(set_attr "type" "f_mcrr,f_mrrc,fconstd,neon_move,f_loadd,\ |
89b2133e | 747 | f_stored,load_8,store_8,ffarithd,multiple") |
c76623e7 JW |
748 | (set (attr "length") (cond [(eq_attr "alternative" "6,7,9") (const_int 8) |
749 | (eq_attr "alternative" "8") | |
e0dc3601 | 750 | (if_then_else |
b75b1be2 | 751 | (match_test "TARGET_VFP_SINGLE") |
e0dc3601 PB |
752 | (const_int 8) |
753 | (const_int 4))] | |
754 | (const_int 4))) | |
c76623e7 JW |
755 | (set_attr "pool_range" "*,*,*,*,1018,*,4094,*,*,*") |
756 | (set_attr "neg_pool_range" "*,*,*,*,1008,*,0,*,*,*") | |
757 | (set_attr "arch" "any,any,any,neon,any,any,any,any,any,any")] | |
5b3e6663 PB |
758 | ) |
759 | ||
9b66ebb1 PB |
760 | |
761 | ;; Conditional move patterns | |
762 | ||
763 | (define_insn "*movsfcc_vfp" | |
f1adb0a9 | 764 | [(set (match_operand:SF 0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r") |
9b66ebb1 PB |
765 | (if_then_else:SF |
766 | (match_operator 3 "arm_comparison_operator" | |
767 | [(match_operand 4 "cc_register" "") (const_int 0)]) | |
f1adb0a9 JB |
768 | (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t") |
769 | (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))] | |
00ea1506 | 770 | "TARGET_ARM && TARGET_HARD_FLOAT" |
9b66ebb1 | 771 | "@ |
35cb3e53 KT |
772 | vmov%D3.f32\\t%0, %2 |
773 | vmov%d3.f32\\t%0, %1 | |
774 | vmov%D3.f32\\t%0, %2\;vmov%d3.f32\\t%0, %1 | |
775 | vmov%D3\\t%0, %2 | |
776 | vmov%d3\\t%0, %1 | |
777 | vmov%D3\\t%0, %2\;vmov%d3\\t%0, %1 | |
778 | vmov%D3\\t%0, %2 | |
779 | vmov%d3\\t%0, %1 | |
780 | vmov%D3\\t%0, %2\;vmov%d3\\t%0, %1" | |
9b66ebb1 PB |
781 | [(set_attr "conds" "use") |
782 | (set_attr "length" "4,4,8,4,4,8,4,4,8") | |
292b89b3 | 783 | (set_attr "type" "fmov,fmov,fmov,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")] |
9b66ebb1 PB |
784 | ) |
785 | ||
5b3e6663 | 786 | (define_insn "*thumb2_movsfcc_vfp" |
f1adb0a9 | 787 | [(set (match_operand:SF 0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r") |
5b3e6663 PB |
788 | (if_then_else:SF |
789 | (match_operator 3 "arm_comparison_operator" | |
790 | [(match_operand 4 "cc_register" "") (const_int 0)]) | |
f1adb0a9 JB |
791 | (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t") |
792 | (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))] | |
c7be0832 | 793 | "TARGET_THUMB2 && TARGET_VFP_BASE && !arm_restrict_it" |
5b3e6663 | 794 | "@ |
35cb3e53 KT |
795 | it\\t%D3\;vmov%D3.f32\\t%0, %2 |
796 | it\\t%d3\;vmov%d3.f32\\t%0, %1 | |
797 | ite\\t%D3\;vmov%D3.f32\\t%0, %2\;vmov%d3.f32\\t%0, %1 | |
798 | it\\t%D3\;vmov%D3\\t%0, %2 | |
799 | it\\t%d3\;vmov%d3\\t%0, %1 | |
800 | ite\\t%D3\;vmov%D3\\t%0, %2\;vmov%d3\\t%0, %1 | |
801 | it\\t%D3\;vmov%D3\\t%0, %2 | |
802 | it\\t%d3\;vmov%d3\\t%0, %1 | |
803 | ite\\t%D3\;vmov%D3\\t%0, %2\;vmov%d3\\t%0, %1" | |
5b3e6663 PB |
804 | [(set_attr "conds" "use") |
805 | (set_attr "length" "6,6,10,6,6,10,6,6,10") | |
292b89b3 | 806 | (set_attr "type" "fmov,fmov,fmov,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")] |
5b3e6663 PB |
807 | ) |
808 | ||
9b66ebb1 PB |
809 | (define_insn "*movdfcc_vfp" |
810 | [(set (match_operand:DF 0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r") | |
811 | (if_then_else:DF | |
812 | (match_operator 3 "arm_comparison_operator" | |
813 | [(match_operand 4 "cc_register" "") (const_int 0)]) | |
814 | (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w") | |
815 | (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))] | |
e0dc3601 | 816 | "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
9b66ebb1 | 817 | "@ |
35cb3e53 KT |
818 | vmov%D3.f64\\t%P0, %P2 |
819 | vmov%d3.f64\\t%P0, %P1 | |
820 | vmov%D3.f64\\t%P0, %P2\;vmov%d3.f64\\t%P0, %P1 | |
821 | vmov%D3\\t%P0, %Q2, %R2 | |
822 | vmov%d3\\t%P0, %Q1, %R1 | |
823 | vmov%D3\\t%P0, %Q2, %R2\;vmov%d3\\t%P0, %Q1, %R1 | |
824 | vmov%D3\\t%Q0, %R0, %P2 | |
825 | vmov%d3\\t%Q0, %R0, %P1 | |
826 | vmov%D3\\t%Q0, %R0, %P2\;vmov%d3\\t%Q0, %R0, %P1" | |
9b66ebb1 PB |
827 | [(set_attr "conds" "use") |
828 | (set_attr "length" "4,4,8,4,4,8,4,4,8") | |
003bb7f3 | 829 | (set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcr,f_mrrc,f_mrrc,f_mrrc")] |
9b66ebb1 PB |
830 | ) |
831 | ||
5b3e6663 PB |
832 | (define_insn "*thumb2_movdfcc_vfp" |
833 | [(set (match_operand:DF 0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r") | |
834 | (if_then_else:DF | |
835 | (match_operator 3 "arm_comparison_operator" | |
836 | [(match_operand 4 "cc_register" "") (const_int 0)]) | |
837 | (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w") | |
838 | (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))] | |
c7be0832 SP |
839 | "TARGET_THUMB2 && TARGET_VFP_BASE && TARGET_VFP_DOUBLE |
840 | && !arm_restrict_it" | |
5b3e6663 | 841 | "@ |
35cb3e53 KT |
842 | it\\t%D3\;vmov%D3.f64\\t%P0, %P2 |
843 | it\\t%d3\;vmov%d3.f64\\t%P0, %P1 | |
844 | ite\\t%D3\;vmov%D3.f64\\t%P0, %P2\;vmov%d3.f64\\t%P0, %P1 | |
845 | it\t%D3\;vmov%D3\\t%P0, %Q2, %R2 | |
846 | it\t%d3\;vmov%d3\\t%P0, %Q1, %R1 | |
847 | ite\\t%D3\;vmov%D3\\t%P0, %Q2, %R2\;vmov%d3\\t%P0, %Q1, %R1 | |
848 | it\t%D3\;vmov%D3\\t%Q0, %R0, %P2 | |
849 | it\t%d3\;vmov%d3\\t%Q0, %R0, %P1 | |
850 | ite\\t%D3\;vmov%D3\\t%Q0, %R0, %P2\;vmov%d3\\t%Q0, %R0, %P1" | |
5b3e6663 PB |
851 | [(set_attr "conds" "use") |
852 | (set_attr "length" "6,6,10,6,6,10,6,6,10") | |
594726e4 | 853 | (set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcrr,f_mrrc,f_mrrc,f_mrrc")] |
5b3e6663 PB |
854 | ) |
855 | ||
9b66ebb1 PB |
856 | |
857 | ;; Sign manipulation functions | |
858 | ||
859 | (define_insn "*abssf2_vfp" | |
f1adb0a9 JB |
860 | [(set (match_operand:SF 0 "s_register_operand" "=t") |
861 | (abs:SF (match_operand:SF 1 "s_register_operand" "t")))] | |
00ea1506 | 862 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
436c249d | 863 | "vabs%?.f32\\t%0, %1" |
9b66ebb1 | 864 | [(set_attr "predicable" "yes") |
51c69ddb | 865 | (set_attr "type" "ffariths")] |
9b66ebb1 PB |
866 | ) |
867 | ||
868 | (define_insn "*absdf2_vfp" | |
869 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
870 | (abs:DF (match_operand:DF 1 "s_register_operand" "w")))] | |
e0dc3601 | 871 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
436c249d | 872 | "vabs%?.f64\\t%P0, %P1" |
9b66ebb1 | 873 | [(set_attr "predicable" "yes") |
51c69ddb | 874 | (set_attr "type" "ffarithd")] |
9b66ebb1 PB |
875 | ) |
876 | ||
877 | (define_insn "*negsf2_vfp" | |
f1adb0a9 JB |
878 | [(set (match_operand:SF 0 "s_register_operand" "=t,?r") |
879 | (neg:SF (match_operand:SF 1 "s_register_operand" "t,r")))] | |
00ea1506 | 880 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
81632f11 | 881 | "@ |
436c249d | 882 | vneg%?.f32\\t%0, %1 |
81632f11 | 883 | eor%?\\t%0, %1, #-2147483648" |
9b66ebb1 | 884 | [(set_attr "predicable" "yes") |
51c69ddb | 885 | (set_attr "type" "ffariths")] |
9b66ebb1 PB |
886 | ) |
887 | ||
81632f11 RE |
888 | (define_insn_and_split "*negdf2_vfp" |
889 | [(set (match_operand:DF 0 "s_register_operand" "=w,?r,?r") | |
890 | (neg:DF (match_operand:DF 1 "s_register_operand" "w,0,r")))] | |
e0dc3601 | 891 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
81632f11 | 892 | "@ |
436c249d | 893 | vneg%?.f64\\t%P0, %P1 |
81632f11 RE |
894 | # |
895 | #" | |
e0dc3601 | 896 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && reload_completed |
81632f11 RE |
897 | && arm_general_register_operand (operands[0], DFmode)" |
898 | [(set (match_dup 0) (match_dup 1))] | |
899 | " | |
900 | if (REGNO (operands[0]) == REGNO (operands[1])) | |
901 | { | |
902 | operands[0] = gen_highpart (SImode, operands[0]); | |
4199c859 JJ |
903 | operands[1] = gen_rtx_XOR (SImode, operands[0], |
904 | gen_int_mode (0x80000000, SImode)); | |
81632f11 RE |
905 | } |
906 | else | |
907 | { | |
908 | rtx in_hi, in_lo, out_hi, out_lo; | |
909 | ||
910 | in_hi = gen_rtx_XOR (SImode, gen_highpart (SImode, operands[1]), | |
4199c859 | 911 | gen_int_mode (0x80000000, SImode)); |
81632f11 RE |
912 | in_lo = gen_lowpart (SImode, operands[1]); |
913 | out_hi = gen_highpart (SImode, operands[0]); | |
914 | out_lo = gen_lowpart (SImode, operands[0]); | |
915 | ||
916 | if (REGNO (in_lo) == REGNO (out_hi)) | |
917 | { | |
f7df4a84 | 918 | emit_insn (gen_rtx_SET (out_lo, in_lo)); |
81632f11 RE |
919 | operands[0] = out_hi; |
920 | operands[1] = in_hi; | |
921 | } | |
922 | else | |
923 | { | |
f7df4a84 | 924 | emit_insn (gen_rtx_SET (out_hi, in_hi)); |
81632f11 RE |
925 | operands[0] = out_lo; |
926 | operands[1] = in_lo; | |
927 | } | |
928 | } | |
929 | " | |
9b66ebb1 | 930 | [(set_attr "predicable" "yes") |
81632f11 | 931 | (set_attr "length" "4,4,8") |
51c69ddb | 932 | (set_attr "type" "ffarithd")] |
9b66ebb1 PB |
933 | ) |
934 | ||
d403b8d4 MW |
935 | ;; ABS and NEG for FP16. |
936 | (define_insn "<absneg_str>hf2" | |
937 | [(set (match_operand:HF 0 "s_register_operand" "=w") | |
938 | (ABSNEG:HF (match_operand:HF 1 "s_register_operand" "w")))] | |
939 | "TARGET_VFP_FP16INST" | |
940 | "v<absneg_str>.f16\t%0, %1" | |
941 | [(set_attr "conds" "unconditional") | |
942 | (set_attr "type" "ffariths")] | |
943 | ) | |
944 | ||
945 | (define_expand "neon_vabshf" | |
946 | [(set | |
947 | (match_operand:HF 0 "s_register_operand") | |
948 | (abs:HF (match_operand:HF 1 "s_register_operand")))] | |
949 | "TARGET_VFP_FP16INST" | |
950 | { | |
951 | emit_insn (gen_abshf2 (operands[0], operands[1])); | |
952 | DONE; | |
953 | }) | |
954 | ||
955 | ;; VRND for FP16. | |
956 | (define_insn "neon_v<fp16_rnd_str>hf" | |
957 | [(set (match_operand:HF 0 "s_register_operand" "=w") | |
958 | (unspec:HF | |
959 | [(match_operand:HF 1 "s_register_operand" "w")] | |
960 | FP16_RND))] | |
961 | "TARGET_VFP_FP16INST" | |
962 | "<fp16_rnd_insn>.f16\t%0, %1" | |
963 | [(set_attr "conds" "unconditional") | |
964 | (set_attr "type" "neon_fp_round_s")] | |
965 | ) | |
966 | ||
967 | (define_insn "neon_vrndihf" | |
968 | [(set (match_operand:HF 0 "s_register_operand" "=w") | |
969 | (unspec:HF | |
970 | [(match_operand:HF 1 "s_register_operand" "w")] | |
971 | UNSPEC_VRNDI))] | |
972 | "TARGET_VFP_FP16INST" | |
973 | "vrintr.f16\t%0, %1" | |
974 | [(set_attr "conds" "unconditional") | |
975 | (set_attr "type" "neon_fp_round_s")] | |
976 | ) | |
9b66ebb1 PB |
977 | |
978 | ;; Arithmetic insns | |
979 | ||
d403b8d4 MW |
980 | (define_insn "addhf3" |
981 | [(set | |
982 | (match_operand:HF 0 "s_register_operand" "=w") | |
983 | (plus:HF | |
984 | (match_operand:HF 1 "s_register_operand" "w") | |
985 | (match_operand:HF 2 "s_register_operand" "w")))] | |
986 | "TARGET_VFP_FP16INST" | |
987 | "vadd.f16\t%0, %1, %2" | |
988 | [(set_attr "conds" "unconditional") | |
989 | (set_attr "type" "fadds")] | |
990 | ) | |
991 | ||
9b66ebb1 | 992 | (define_insn "*addsf3_vfp" |
f1adb0a9 JB |
993 | [(set (match_operand:SF 0 "s_register_operand" "=t") |
994 | (plus:SF (match_operand:SF 1 "s_register_operand" "t") | |
995 | (match_operand:SF 2 "s_register_operand" "t")))] | |
00ea1506 | 996 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
436c249d | 997 | "vadd%?.f32\\t%0, %1, %2" |
9b66ebb1 | 998 | [(set_attr "predicable" "yes") |
51c69ddb | 999 | (set_attr "type" "fadds")] |
9b66ebb1 PB |
1000 | ) |
1001 | ||
1002 | (define_insn "*adddf3_vfp" | |
1003 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
1004 | (plus:DF (match_operand:DF 1 "s_register_operand" "w") | |
1005 | (match_operand:DF 2 "s_register_operand" "w")))] | |
e0dc3601 | 1006 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
436c249d | 1007 | "vadd%?.f64\\t%P0, %P1, %P2" |
9b66ebb1 | 1008 | [(set_attr "predicable" "yes") |
51c69ddb | 1009 | (set_attr "type" "faddd")] |
9b66ebb1 PB |
1010 | ) |
1011 | ||
d403b8d4 MW |
1012 | (define_insn "subhf3" |
1013 | [(set | |
1014 | (match_operand:HF 0 "s_register_operand" "=w") | |
1015 | (minus:HF | |
1016 | (match_operand:HF 1 "s_register_operand" "w") | |
1017 | (match_operand:HF 2 "s_register_operand" "w")))] | |
1018 | "TARGET_VFP_FP16INST" | |
1019 | "vsub.f16\t%0, %1, %2" | |
1020 | [(set_attr "conds" "unconditional") | |
1021 | (set_attr "type" "fadds")] | |
1022 | ) | |
9b66ebb1 PB |
1023 | |
1024 | (define_insn "*subsf3_vfp" | |
f1adb0a9 JB |
1025 | [(set (match_operand:SF 0 "s_register_operand" "=t") |
1026 | (minus:SF (match_operand:SF 1 "s_register_operand" "t") | |
1027 | (match_operand:SF 2 "s_register_operand" "t")))] | |
00ea1506 | 1028 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
436c249d | 1029 | "vsub%?.f32\\t%0, %1, %2" |
9b66ebb1 | 1030 | [(set_attr "predicable" "yes") |
51c69ddb | 1031 | (set_attr "type" "fadds")] |
9b66ebb1 PB |
1032 | ) |
1033 | ||
1034 | (define_insn "*subdf3_vfp" | |
1035 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
1036 | (minus:DF (match_operand:DF 1 "s_register_operand" "w") | |
1037 | (match_operand:DF 2 "s_register_operand" "w")))] | |
e0dc3601 | 1038 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
436c249d | 1039 | "vsub%?.f64\\t%P0, %P1, %P2" |
9b66ebb1 | 1040 | [(set_attr "predicable" "yes") |
51c69ddb | 1041 | (set_attr "type" "faddd")] |
9b66ebb1 PB |
1042 | ) |
1043 | ||
1044 | ||
1045 | ;; Division insns | |
1046 | ||
d403b8d4 MW |
1047 | ;; FP16 Division. |
1048 | (define_insn "divhf3" | |
1049 | [(set | |
1050 | (match_operand:HF 0 "s_register_operand" "=w") | |
1051 | (div:HF | |
1052 | (match_operand:HF 1 "s_register_operand" "w") | |
1053 | (match_operand:HF 2 "s_register_operand" "w")))] | |
1054 | "TARGET_VFP_FP16INST" | |
1055 | "vdiv.f16\t%0, %1, %2" | |
1056 | [(set_attr "conds" "unconditional") | |
1057 | (set_attr "type" "fdivs")] | |
1058 | ) | |
1059 | ||
a89b02c0 RE |
1060 | ; VFP9 Erratum 760019: It's potentially unsafe to overwrite the input |
1061 | ; operands, so mark the output as early clobber for VFPv2 on ARMv5 or | |
1062 | ; earlier. | |
9b66ebb1 | 1063 | (define_insn "*divsf3_vfp" |
a89b02c0 RE |
1064 | [(set (match_operand:SF 0 "s_register_operand" "=&t,t") |
1065 | (div:SF (match_operand:SF 1 "s_register_operand" "t,t") | |
1066 | (match_operand:SF 2 "s_register_operand" "t,t")))] | |
00ea1506 | 1067 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
436c249d | 1068 | "vdiv%?.f32\\t%0, %1, %2" |
9b66ebb1 | 1069 | [(set_attr "predicable" "yes") |
a89b02c0 | 1070 | (set_attr "arch" "*,armv6_or_vfpv3") |
9b66ebb1 PB |
1071 | (set_attr "type" "fdivs")] |
1072 | ) | |
1073 | ||
1074 | (define_insn "*divdf3_vfp" | |
a89b02c0 RE |
1075 | [(set (match_operand:DF 0 "s_register_operand" "=&w,w") |
1076 | (div:DF (match_operand:DF 1 "s_register_operand" "w,w") | |
1077 | (match_operand:DF 2 "s_register_operand" "w,w")))] | |
e0dc3601 | 1078 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
436c249d | 1079 | "vdiv%?.f64\\t%P0, %P1, %P2" |
9b66ebb1 | 1080 | [(set_attr "predicable" "yes") |
a89b02c0 | 1081 | (set_attr "arch" "*,armv6_or_vfpv3") |
9b66ebb1 PB |
1082 | (set_attr "type" "fdivd")] |
1083 | ) | |
1084 | ||
1085 | ||
1086 | ;; Multiplication insns | |
1087 | ||
d403b8d4 MW |
1088 | (define_insn "mulhf3" |
1089 | [(set | |
1090 | (match_operand:HF 0 "s_register_operand" "=w") | |
1091 | (mult:HF (match_operand:HF 1 "s_register_operand" "w") | |
1092 | (match_operand:HF 2 "s_register_operand" "w")))] | |
1093 | "TARGET_VFP_FP16INST" | |
1094 | "vmul.f16\t%0, %1, %2" | |
1095 | [(set_attr "conds" "unconditional") | |
1096 | (set_attr "type" "fmuls")] | |
1097 | ) | |
1098 | ||
9b66ebb1 | 1099 | (define_insn "*mulsf3_vfp" |
0498a2be | 1100 | [(set (match_operand:SF 0 "s_register_operand" "=t") |
f1adb0a9 JB |
1101 | (mult:SF (match_operand:SF 1 "s_register_operand" "t") |
1102 | (match_operand:SF 2 "s_register_operand" "t")))] | |
00ea1506 | 1103 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
14d9aa9f | 1104 | "vmul%?.f32\\t%0, %1, %2" |
9b66ebb1 | 1105 | [(set_attr "predicable" "yes") |
a8e17e9e | 1106 | (set_attr "type" "fmuls")] |
9b66ebb1 PB |
1107 | ) |
1108 | ||
1109 | (define_insn "*muldf3_vfp" | |
0498a2be | 1110 | [(set (match_operand:DF 0 "s_register_operand" "=w") |
9b66ebb1 PB |
1111 | (mult:DF (match_operand:DF 1 "s_register_operand" "w") |
1112 | (match_operand:DF 2 "s_register_operand" "w")))] | |
e0dc3601 | 1113 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
14d9aa9f | 1114 | "vmul%?.f64\\t%P0, %P1, %P2" |
9b66ebb1 | 1115 | [(set_attr "predicable" "yes") |
a8e17e9e | 1116 | (set_attr "type" "fmuld")] |
9b66ebb1 PB |
1117 | ) |
1118 | ||
d403b8d4 MW |
1119 | (define_insn "*mulsf3neghf_vfp" |
1120 | [(set (match_operand:HF 0 "s_register_operand" "=t") | |
1121 | (mult:HF (neg:HF (match_operand:HF 1 "s_register_operand" "t")) | |
1122 | (match_operand:HF 2 "s_register_operand" "t")))] | |
1123 | "TARGET_VFP_FP16INST && !flag_rounding_math" | |
1124 | "vnmul.f16\\t%0, %1, %2" | |
1125 | [(set_attr "conds" "unconditional") | |
1126 | (set_attr "type" "fmuls")] | |
1127 | ) | |
1128 | ||
1129 | (define_insn "*negmulhf3_vfp" | |
1130 | [(set (match_operand:HF 0 "s_register_operand" "=t") | |
1131 | (neg:HF (mult:HF (match_operand:HF 1 "s_register_operand" "t") | |
1132 | (match_operand:HF 2 "s_register_operand" "t"))))] | |
1133 | "TARGET_VFP_FP16INST" | |
1134 | "vnmul.f16\\t%0, %1, %2" | |
1135 | [(set_attr "conds" "unconditional") | |
1136 | (set_attr "type" "fmuls")] | |
1137 | ) | |
1138 | ||
9b66ebb1 | 1139 | (define_insn "*mulsf3negsf_vfp" |
0498a2be | 1140 | [(set (match_operand:SF 0 "s_register_operand" "=t") |
f1adb0a9 JB |
1141 | (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t")) |
1142 | (match_operand:SF 2 "s_register_operand" "t")))] | |
00ea1506 | 1143 | "TARGET_32BIT && TARGET_HARD_FLOAT && !flag_rounding_math" |
1f71aee9 SN |
1144 | "vnmul%?.f32\\t%0, %1, %2" |
1145 | [(set_attr "predicable" "yes") | |
1f71aee9 SN |
1146 | (set_attr "type" "fmuls")] |
1147 | ) | |
1148 | ||
1149 | (define_insn "*negmulsf3_vfp" | |
1150 | [(set (match_operand:SF 0 "s_register_operand" "=t") | |
1151 | (neg:SF (mult:SF (match_operand:SF 1 "s_register_operand" "t") | |
1152 | (match_operand:SF 2 "s_register_operand" "t"))))] | |
00ea1506 | 1153 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
14d9aa9f | 1154 | "vnmul%?.f32\\t%0, %1, %2" |
9b66ebb1 | 1155 | [(set_attr "predicable" "yes") |
a8e17e9e | 1156 | (set_attr "type" "fmuls")] |
9b66ebb1 PB |
1157 | ) |
1158 | ||
1159 | (define_insn "*muldf3negdf_vfp" | |
0498a2be | 1160 | [(set (match_operand:DF 0 "s_register_operand" "=w") |
9b66ebb1 PB |
1161 | (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w")) |
1162 | (match_operand:DF 2 "s_register_operand" "w")))] | |
1f71aee9 SN |
1163 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE |
1164 | && !flag_rounding_math" | |
1165 | "vnmul%?.f64\\t%P0, %P1, %P2" | |
1166 | [(set_attr "predicable" "yes") | |
1f71aee9 SN |
1167 | (set_attr "type" "fmuld")] |
1168 | ) | |
1169 | ||
1170 | (define_insn "*negmuldf3_vfp" | |
1171 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
1172 | (neg:DF (mult:DF (match_operand:DF 1 "s_register_operand" "w") | |
1173 | (match_operand:DF 2 "s_register_operand" "w"))))] | |
e0dc3601 | 1174 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
14d9aa9f | 1175 | "vnmul%?.f64\\t%P0, %P1, %P2" |
9b66ebb1 | 1176 | [(set_attr "predicable" "yes") |
a8e17e9e | 1177 | (set_attr "type" "fmuld")] |
9b66ebb1 PB |
1178 | ) |
1179 | ||
1180 | ||
1181 | ;; Multiply-accumulate insns | |
1182 | ||
1183 | ;; 0 = 1 * 2 + 0 | |
d403b8d4 MW |
1184 | (define_insn "*mulsf3addhf_vfp" |
1185 | [(set (match_operand:HF 0 "s_register_operand" "=t") | |
1186 | (plus:HF | |
1187 | (mult:HF (match_operand:HF 2 "s_register_operand" "t") | |
1188 | (match_operand:HF 3 "s_register_operand" "t")) | |
1189 | (match_operand:HF 1 "s_register_operand" "0")))] | |
1190 | "TARGET_VFP_FP16INST" | |
1191 | "vmla.f16\\t%0, %2, %3" | |
1192 | [(set_attr "conds" "unconditional") | |
1193 | (set_attr "type" "fmacs")] | |
1194 | ) | |
1195 | ||
9b66ebb1 | 1196 | (define_insn "*mulsf3addsf_vfp" |
f1adb0a9 JB |
1197 | [(set (match_operand:SF 0 "s_register_operand" "=t") |
1198 | (plus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t") | |
1199 | (match_operand:SF 3 "s_register_operand" "t")) | |
9b66ebb1 | 1200 | (match_operand:SF 1 "s_register_operand" "0")))] |
00ea1506 | 1201 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
14d9aa9f | 1202 | "vmla%?.f32\\t%0, %2, %3" |
9b66ebb1 | 1203 | [(set_attr "predicable" "yes") |
a8e17e9e | 1204 | (set_attr "type" "fmacs")] |
9b66ebb1 PB |
1205 | ) |
1206 | ||
1207 | (define_insn "*muldf3adddf_vfp" | |
1208 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
1209 | (plus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w") | |
1210 | (match_operand:DF 3 "s_register_operand" "w")) | |
1211 | (match_operand:DF 1 "s_register_operand" "0")))] | |
e0dc3601 | 1212 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
14d9aa9f | 1213 | "vmla%?.f64\\t%P0, %P2, %P3" |
9b66ebb1 | 1214 | [(set_attr "predicable" "yes") |
a8e17e9e | 1215 | (set_attr "type" "fmacd")] |
9b66ebb1 PB |
1216 | ) |
1217 | ||
1218 | ;; 0 = 1 * 2 - 0 | |
d403b8d4 MW |
1219 | (define_insn "*mulhf3subhf_vfp" |
1220 | [(set (match_operand:HF 0 "s_register_operand" "=t") | |
1221 | (minus:HF (mult:HF (match_operand:HF 2 "s_register_operand" "t") | |
1222 | (match_operand:HF 3 "s_register_operand" "t")) | |
1223 | (match_operand:HF 1 "s_register_operand" "0")))] | |
1224 | "TARGET_VFP_FP16INST" | |
1225 | "vnmls.f16\\t%0, %2, %3" | |
1226 | [(set_attr "conds" "unconditional") | |
1227 | (set_attr "type" "fmacs")] | |
1228 | ) | |
1229 | ||
9b66ebb1 | 1230 | (define_insn "*mulsf3subsf_vfp" |
f1adb0a9 JB |
1231 | [(set (match_operand:SF 0 "s_register_operand" "=t") |
1232 | (minus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t") | |
1233 | (match_operand:SF 3 "s_register_operand" "t")) | |
9b66ebb1 | 1234 | (match_operand:SF 1 "s_register_operand" "0")))] |
00ea1506 | 1235 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
14d9aa9f | 1236 | "vnmls%?.f32\\t%0, %2, %3" |
9b66ebb1 | 1237 | [(set_attr "predicable" "yes") |
a8e17e9e | 1238 | (set_attr "type" "fmacs")] |
9b66ebb1 PB |
1239 | ) |
1240 | ||
1241 | (define_insn "*muldf3subdf_vfp" | |
1242 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
1243 | (minus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w") | |
1244 | (match_operand:DF 3 "s_register_operand" "w")) | |
1245 | (match_operand:DF 1 "s_register_operand" "0")))] | |
e0dc3601 | 1246 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
14d9aa9f | 1247 | "vnmls%?.f64\\t%P0, %P2, %P3" |
9b66ebb1 | 1248 | [(set_attr "predicable" "yes") |
a8e17e9e | 1249 | (set_attr "type" "fmacd")] |
9b66ebb1 PB |
1250 | ) |
1251 | ||
1252 | ;; 0 = -(1 * 2) + 0 | |
d403b8d4 MW |
1253 | (define_insn "*mulhf3neghfaddhf_vfp" |
1254 | [(set (match_operand:HF 0 "s_register_operand" "=t") | |
1255 | (minus:HF (match_operand:HF 1 "s_register_operand" "0") | |
1256 | (mult:HF (match_operand:HF 2 "s_register_operand" "t") | |
1257 | (match_operand:HF 3 "s_register_operand" "t"))))] | |
1258 | "TARGET_VFP_FP16INST" | |
1259 | "vmls.f16\\t%0, %2, %3" | |
1260 | [(set_attr "conds" "unconditional") | |
1261 | (set_attr "type" "fmacs")] | |
1262 | ) | |
1263 | ||
9b66ebb1 | 1264 | (define_insn "*mulsf3negsfaddsf_vfp" |
f1adb0a9 | 1265 | [(set (match_operand:SF 0 "s_register_operand" "=t") |
9b66ebb1 | 1266 | (minus:SF (match_operand:SF 1 "s_register_operand" "0") |
f1adb0a9 JB |
1267 | (mult:SF (match_operand:SF 2 "s_register_operand" "t") |
1268 | (match_operand:SF 3 "s_register_operand" "t"))))] | |
00ea1506 | 1269 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
14d9aa9f | 1270 | "vmls%?.f32\\t%0, %2, %3" |
9b66ebb1 | 1271 | [(set_attr "predicable" "yes") |
a8e17e9e | 1272 | (set_attr "type" "fmacs")] |
9b66ebb1 PB |
1273 | ) |
1274 | ||
1275 | (define_insn "*fmuldf3negdfadddf_vfp" | |
1276 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
1277 | (minus:DF (match_operand:DF 1 "s_register_operand" "0") | |
1278 | (mult:DF (match_operand:DF 2 "s_register_operand" "w") | |
1279 | (match_operand:DF 3 "s_register_operand" "w"))))] | |
e0dc3601 | 1280 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
14d9aa9f | 1281 | "vmls%?.f64\\t%P0, %P2, %P3" |
9b66ebb1 | 1282 | [(set_attr "predicable" "yes") |
a8e17e9e | 1283 | (set_attr "type" "fmacd")] |
9b66ebb1 PB |
1284 | ) |
1285 | ||
1286 | ||
1287 | ;; 0 = -(1 * 2) - 0 | |
d403b8d4 MW |
1288 | (define_insn "*mulhf3neghfsubhf_vfp" |
1289 | [(set (match_operand:HF 0 "s_register_operand" "=t") | |
1290 | (minus:HF (mult:HF | |
1291 | (neg:HF (match_operand:HF 2 "s_register_operand" "t")) | |
1292 | (match_operand:HF 3 "s_register_operand" "t")) | |
1293 | (match_operand:HF 1 "s_register_operand" "0")))] | |
1294 | "TARGET_VFP_FP16INST" | |
1295 | "vnmla.f16\\t%0, %2, %3" | |
1296 | [(set_attr "conds" "unconditional") | |
1297 | (set_attr "type" "fmacs")] | |
1298 | ) | |
1299 | ||
9b66ebb1 | 1300 | (define_insn "*mulsf3negsfsubsf_vfp" |
f1adb0a9 | 1301 | [(set (match_operand:SF 0 "s_register_operand" "=t") |
9b66ebb1 | 1302 | (minus:SF (mult:SF |
f1adb0a9 JB |
1303 | (neg:SF (match_operand:SF 2 "s_register_operand" "t")) |
1304 | (match_operand:SF 3 "s_register_operand" "t")) | |
9b66ebb1 | 1305 | (match_operand:SF 1 "s_register_operand" "0")))] |
00ea1506 | 1306 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
14d9aa9f | 1307 | "vnmla%?.f32\\t%0, %2, %3" |
9b66ebb1 | 1308 | [(set_attr "predicable" "yes") |
a8e17e9e | 1309 | (set_attr "type" "fmacs")] |
9b66ebb1 PB |
1310 | ) |
1311 | ||
1312 | (define_insn "*muldf3negdfsubdf_vfp" | |
1313 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
1314 | (minus:DF (mult:DF | |
1315 | (neg:DF (match_operand:DF 2 "s_register_operand" "w")) | |
1316 | (match_operand:DF 3 "s_register_operand" "w")) | |
1317 | (match_operand:DF 1 "s_register_operand" "0")))] | |
e0dc3601 | 1318 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
14d9aa9f | 1319 | "vnmla%?.f64\\t%P0, %P2, %P3" |
9b66ebb1 | 1320 | [(set_attr "predicable" "yes") |
a8e17e9e | 1321 | (set_attr "type" "fmacd")] |
9b66ebb1 PB |
1322 | ) |
1323 | ||
76f722f4 MGD |
1324 | ;; Fused-multiply-accumulate |
1325 | ||
d403b8d4 MW |
1326 | (define_insn "fmahf4" |
1327 | [(set (match_operand:HF 0 "register_operand" "=w") | |
1328 | (fma:HF | |
1329 | (match_operand:HF 1 "register_operand" "w") | |
1330 | (match_operand:HF 2 "register_operand" "w") | |
1331 | (match_operand:HF 3 "register_operand" "0")))] | |
1332 | "TARGET_VFP_FP16INST" | |
1333 | "vfma.f16\\t%0, %1, %2" | |
1334 | [(set_attr "conds" "unconditional") | |
1335 | (set_attr "type" "ffmas")] | |
1336 | ) | |
1337 | ||
1338 | (define_expand "neon_vfmahf" | |
1339 | [(match_operand:HF 0 "s_register_operand") | |
1340 | (match_operand:HF 1 "s_register_operand") | |
1341 | (match_operand:HF 2 "s_register_operand") | |
1342 | (match_operand:HF 3 "s_register_operand")] | |
1343 | "TARGET_VFP_FP16INST" | |
1344 | { | |
1345 | emit_insn (gen_fmahf4 (operands[0], operands[2], operands[3], | |
1346 | operands[1])); | |
1347 | DONE; | |
1348 | }) | |
1349 | ||
76f722f4 MGD |
1350 | (define_insn "fma<SDF:mode>4" |
1351 | [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>") | |
1352 | (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>") | |
1353 | (match_operand:SDF 2 "register_operand" "<F_constraint>") | |
1354 | (match_operand:SDF 3 "register_operand" "0")))] | |
490d1b4a | 1355 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA <vfp_double_cond>" |
76f722f4 MGD |
1356 | "vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" |
1357 | [(set_attr "predicable" "yes") | |
29637783 | 1358 | (set_attr "type" "ffma<vfp_type>")] |
76f722f4 MGD |
1359 | ) |
1360 | ||
d403b8d4 MW |
1361 | (define_insn "fmsubhf4_fp16" |
1362 | [(set (match_operand:HF 0 "register_operand" "=w") | |
1363 | (fma:HF | |
1364 | (neg:HF (match_operand:HF 1 "register_operand" "w")) | |
1365 | (match_operand:HF 2 "register_operand" "w") | |
1366 | (match_operand:HF 3 "register_operand" "0")))] | |
1367 | "TARGET_VFP_FP16INST" | |
1368 | "vfms.f16\\t%0, %1, %2" | |
1369 | [(set_attr "conds" "unconditional") | |
1370 | (set_attr "type" "ffmas")] | |
1371 | ) | |
1372 | ||
1373 | (define_expand "neon_vfmshf" | |
1374 | [(match_operand:HF 0 "s_register_operand") | |
1375 | (match_operand:HF 1 "s_register_operand") | |
1376 | (match_operand:HF 2 "s_register_operand") | |
1377 | (match_operand:HF 3 "s_register_operand")] | |
1378 | "TARGET_VFP_FP16INST" | |
1379 | { | |
1380 | emit_insn (gen_fmsubhf4_fp16 (operands[0], operands[2], operands[3], | |
1381 | operands[1])); | |
1382 | DONE; | |
1383 | }) | |
1384 | ||
76f722f4 MGD |
1385 | (define_insn "*fmsub<SDF:mode>4" |
1386 | [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>") | |
1387 | (fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand" | |
1388 | "<F_constraint>")) | |
1389 | (match_operand:SDF 2 "register_operand" "<F_constraint>") | |
1390 | (match_operand:SDF 3 "register_operand" "0")))] | |
490d1b4a | 1391 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA <vfp_double_cond>" |
76f722f4 MGD |
1392 | "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" |
1393 | [(set_attr "predicable" "yes") | |
29637783 | 1394 | (set_attr "type" "ffma<vfp_type>")] |
76f722f4 MGD |
1395 | ) |
1396 | ||
d403b8d4 MW |
1397 | (define_insn "*fnmsubhf4" |
1398 | [(set (match_operand:HF 0 "register_operand" "=w") | |
1399 | (fma:HF (match_operand:HF 1 "register_operand" "w") | |
1400 | (match_operand:HF 2 "register_operand" "w") | |
1401 | (neg:HF (match_operand:HF 3 "register_operand" "0"))))] | |
1402 | "TARGET_VFP_FP16INST" | |
1403 | "vfnms.f16\\t%0, %1, %2" | |
1404 | [(set_attr "conds" "unconditional") | |
1405 | (set_attr "type" "ffmas")] | |
1406 | ) | |
1407 | ||
76f722f4 MGD |
1408 | (define_insn "*fnmsub<SDF:mode>4" |
1409 | [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>") | |
1410 | (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>") | |
1411 | (match_operand:SDF 2 "register_operand" "<F_constraint>") | |
1412 | (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))] | |
490d1b4a | 1413 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA <vfp_double_cond>" |
76f722f4 MGD |
1414 | "vfnms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" |
1415 | [(set_attr "predicable" "yes") | |
29637783 | 1416 | (set_attr "type" "ffma<vfp_type>")] |
76f722f4 MGD |
1417 | ) |
1418 | ||
d403b8d4 MW |
1419 | (define_insn "*fnmaddhf4" |
1420 | [(set (match_operand:HF 0 "register_operand" "=w") | |
1421 | (fma:HF (neg:HF (match_operand:HF 1 "register_operand" "w")) | |
1422 | (match_operand:HF 2 "register_operand" "w") | |
1423 | (neg:HF (match_operand:HF 3 "register_operand" "0"))))] | |
1424 | "TARGET_VFP_FP16INST" | |
1425 | "vfnma.f16\\t%0, %1, %2" | |
1426 | [(set_attr "conds" "unconditional") | |
1427 | (set_attr "type" "ffmas")] | |
1428 | ) | |
1429 | ||
76f722f4 MGD |
1430 | (define_insn "*fnmadd<SDF:mode>4" |
1431 | [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>") | |
1432 | (fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand" | |
1433 | "<F_constraint>")) | |
1434 | (match_operand:SDF 2 "register_operand" "<F_constraint>") | |
1435 | (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))] | |
490d1b4a | 1436 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA <vfp_double_cond>" |
76f722f4 MGD |
1437 | "vfnma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" |
1438 | [(set_attr "predicable" "yes") | |
29637783 | 1439 | (set_attr "type" "ffma<vfp_type>")] |
76f722f4 MGD |
1440 | ) |
1441 | ||
9b66ebb1 PB |
1442 | |
1443 | ;; Conversion routines | |
1444 | ||
1445 | (define_insn "*extendsfdf2_vfp" | |
1446 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
f1adb0a9 | 1447 | (float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))] |
e0dc3601 | 1448 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
14a082a3 | 1449 | "vcvt%?.f64.f32\\t%P0, %1" |
9b66ebb1 | 1450 | [(set_attr "predicable" "yes") |
75fe7b2f | 1451 | (set_attr "type" "f_cvt")] |
9b66ebb1 PB |
1452 | ) |
1453 | ||
1454 | (define_insn "*truncdfsf2_vfp" | |
f1adb0a9 | 1455 | [(set (match_operand:SF 0 "s_register_operand" "=t") |
9b66ebb1 | 1456 | (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))] |
e0dc3601 | 1457 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
14a082a3 | 1458 | "vcvt%?.f32.f64\\t%0, %P1" |
9b66ebb1 | 1459 | [(set_attr "predicable" "yes") |
75fe7b2f | 1460 | (set_attr "type" "f_cvt")] |
9b66ebb1 PB |
1461 | ) |
1462 | ||
0fd8c3ad SL |
1463 | (define_insn "extendhfsf2" |
1464 | [(set (match_operand:SF 0 "s_register_operand" "=t") | |
1465 | (float_extend:SF (match_operand:HF 1 "s_register_operand" "t")))] | |
4ffc8099 | 1466 | "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FP16 || TARGET_VFP_FP16INST)" |
0fd8c3ad SL |
1467 | "vcvtb%?.f32.f16\\t%0, %1" |
1468 | [(set_attr "predicable" "yes") | |
1469 | (set_attr "type" "f_cvt")] | |
1470 | ) | |
1471 | ||
5e0f10a0 JG |
1472 | (define_insn "*truncdfhf2" |
1473 | [(set (match_operand:HF 0 "s_register_operand" "=t") | |
1474 | (float_truncate:HF (match_operand:DF 1 "s_register_operand" "w")))] | |
1475 | "TARGET_32BIT && TARGET_FP16_TO_DOUBLE" | |
1476 | "vcvtb%?.f16.f64\\t%0, %P1" | |
1477 | [(set_attr "predicable" "yes") | |
5e0f10a0 JG |
1478 | (set_attr "type" "f_cvt")] |
1479 | ) | |
1480 | ||
1481 | (define_insn "*extendhfdf2" | |
1482 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
1483 | (float_extend:DF (match_operand:HF 1 "s_register_operand" "t")))] | |
1484 | "TARGET_32BIT && TARGET_FP16_TO_DOUBLE" | |
1485 | "vcvtb%?.f64.f16\\t%P0, %1" | |
1486 | [(set_attr "predicable" "yes") | |
5e0f10a0 JG |
1487 | (set_attr "type" "f_cvt")] |
1488 | ) | |
1489 | ||
0fd8c3ad SL |
1490 | (define_insn "truncsfhf2" |
1491 | [(set (match_operand:HF 0 "s_register_operand" "=t") | |
1492 | (float_truncate:HF (match_operand:SF 1 "s_register_operand" "t")))] | |
4ffc8099 | 1493 | "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FP16 || TARGET_VFP_FP16INST)" |
0fd8c3ad SL |
1494 | "vcvtb%?.f16.f32\\t%0, %1" |
1495 | [(set_attr "predicable" "yes") | |
1496 | (set_attr "type" "f_cvt")] | |
1497 | ) | |
1498 | ||
9b66ebb1 | 1499 | (define_insn "*truncsisf2_vfp" |
f1adb0a9 JB |
1500 | [(set (match_operand:SI 0 "s_register_operand" "=t") |
1501 | (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))] | |
00ea1506 | 1502 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
14a082a3 | 1503 | "vcvt%?.s32.f32\\t%0, %1" |
9b66ebb1 | 1504 | [(set_attr "predicable" "yes") |
7b49c9e1 | 1505 | (set_attr "type" "f_cvtf2i")] |
9b66ebb1 PB |
1506 | ) |
1507 | ||
1508 | (define_insn "*truncsidf2_vfp" | |
f1adb0a9 | 1509 | [(set (match_operand:SI 0 "s_register_operand" "=t") |
9b66ebb1 | 1510 | (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))] |
e0dc3601 | 1511 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
14a082a3 | 1512 | "vcvt%?.s32.f64\\t%0, %P1" |
9b66ebb1 | 1513 | [(set_attr "predicable" "yes") |
7b49c9e1 | 1514 | (set_attr "type" "f_cvtf2i")] |
9b66ebb1 PB |
1515 | ) |
1516 | ||
6f6c1f6d PB |
1517 | |
1518 | (define_insn "fixuns_truncsfsi2" | |
f1adb0a9 JB |
1519 | [(set (match_operand:SI 0 "s_register_operand" "=t") |
1520 | (unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))] | |
00ea1506 | 1521 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
14a082a3 | 1522 | "vcvt%?.u32.f32\\t%0, %1" |
6f6c1f6d | 1523 | [(set_attr "predicable" "yes") |
7b49c9e1 | 1524 | (set_attr "type" "f_cvtf2i")] |
6f6c1f6d PB |
1525 | ) |
1526 | ||
1527 | (define_insn "fixuns_truncdfsi2" | |
f1adb0a9 JB |
1528 | [(set (match_operand:SI 0 "s_register_operand" "=t") |
1529 | (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))] | |
e0dc3601 | 1530 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
14a082a3 | 1531 | "vcvt%?.u32.f64\\t%0, %P1" |
6f6c1f6d | 1532 | [(set_attr "predicable" "yes") |
7b49c9e1 | 1533 | (set_attr "type" "f_cvtf2i")] |
6f6c1f6d PB |
1534 | ) |
1535 | ||
1536 | ||
9b66ebb1 | 1537 | (define_insn "*floatsisf2_vfp" |
f1adb0a9 JB |
1538 | [(set (match_operand:SF 0 "s_register_operand" "=t") |
1539 | (float:SF (match_operand:SI 1 "s_register_operand" "t")))] | |
00ea1506 | 1540 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
14a082a3 | 1541 | "vcvt%?.f32.s32\\t%0, %1" |
9b66ebb1 | 1542 | [(set_attr "predicable" "yes") |
7b49c9e1 | 1543 | (set_attr "type" "f_cvti2f")] |
9b66ebb1 PB |
1544 | ) |
1545 | ||
1546 | (define_insn "*floatsidf2_vfp" | |
1547 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
f1adb0a9 | 1548 | (float:DF (match_operand:SI 1 "s_register_operand" "t")))] |
e0dc3601 | 1549 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
14a082a3 | 1550 | "vcvt%?.f64.s32\\t%P0, %1" |
9b66ebb1 | 1551 | [(set_attr "predicable" "yes") |
7b49c9e1 | 1552 | (set_attr "type" "f_cvti2f")] |
9b66ebb1 PB |
1553 | ) |
1554 | ||
1555 | ||
6f6c1f6d | 1556 | (define_insn "floatunssisf2" |
f1adb0a9 JB |
1557 | [(set (match_operand:SF 0 "s_register_operand" "=t") |
1558 | (unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))] | |
00ea1506 | 1559 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
14a082a3 | 1560 | "vcvt%?.f32.u32\\t%0, %1" |
6f6c1f6d | 1561 | [(set_attr "predicable" "yes") |
7b49c9e1 | 1562 | (set_attr "type" "f_cvti2f")] |
6f6c1f6d PB |
1563 | ) |
1564 | ||
1565 | (define_insn "floatunssidf2" | |
1566 | [(set (match_operand:DF 0 "s_register_operand" "=w") | |
f1adb0a9 | 1567 | (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))] |
e0dc3601 | 1568 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
14a082a3 | 1569 | "vcvt%?.f64.u32\\t%P0, %1" |
6f6c1f6d | 1570 | [(set_attr "predicable" "yes") |
7b49c9e1 | 1571 | (set_attr "type" "f_cvti2f")] |
6f6c1f6d PB |
1572 | ) |
1573 | ||
1574 | ||
9b66ebb1 PB |
1575 | ;; Sqrt insns. |
1576 | ||
d403b8d4 MW |
1577 | (define_insn "neon_vsqrthf" |
1578 | [(set (match_operand:HF 0 "s_register_operand" "=w") | |
1579 | (sqrt:HF (match_operand:HF 1 "s_register_operand" "w")))] | |
1580 | "TARGET_VFP_FP16INST" | |
1581 | "vsqrt.f16\t%0, %1" | |
1582 | [(set_attr "conds" "unconditional") | |
1583 | (set_attr "type" "fsqrts")] | |
1584 | ) | |
1585 | ||
1586 | (define_insn "neon_vrsqrtshf" | |
1587 | [(set | |
1588 | (match_operand:HF 0 "s_register_operand" "=w") | |
1589 | (unspec:HF [(match_operand:HF 1 "s_register_operand" "w") | |
1590 | (match_operand:HF 2 "s_register_operand" "w")] | |
1591 | UNSPEC_VRSQRTS))] | |
1592 | "TARGET_VFP_FP16INST" | |
1593 | "vrsqrts.f16\t%0, %1, %2" | |
1594 | [(set_attr "conds" "unconditional") | |
1595 | (set_attr "type" "fsqrts")] | |
1596 | ) | |
1597 | ||
a89b02c0 RE |
1598 | ; VFP9 Erratum 760019: It's potentially unsafe to overwrite the input |
1599 | ; operands, so mark the output as early clobber for VFPv2 on ARMv5 or | |
1600 | ; earlier. | |
9b66ebb1 | 1601 | (define_insn "*sqrtsf2_vfp" |
a89b02c0 RE |
1602 | [(set (match_operand:SF 0 "s_register_operand" "=&t,t") |
1603 | (sqrt:SF (match_operand:SF 1 "s_register_operand" "t,t")))] | |
00ea1506 | 1604 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
c2786584 | 1605 | "vsqrt%?.f32\\t%0, %1" |
9b66ebb1 | 1606 | [(set_attr "predicable" "yes") |
a89b02c0 | 1607 | (set_attr "arch" "*,armv6_or_vfpv3") |
b86923f0 | 1608 | (set_attr "type" "fsqrts")] |
9b66ebb1 PB |
1609 | ) |
1610 | ||
1611 | (define_insn "*sqrtdf2_vfp" | |
a89b02c0 RE |
1612 | [(set (match_operand:DF 0 "s_register_operand" "=&w,w") |
1613 | (sqrt:DF (match_operand:DF 1 "s_register_operand" "w,w")))] | |
e0dc3601 | 1614 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
c2786584 | 1615 | "vsqrt%?.f64\\t%P0, %P1" |
9b66ebb1 | 1616 | [(set_attr "predicable" "yes") |
a89b02c0 | 1617 | (set_attr "arch" "*,armv6_or_vfpv3") |
b86923f0 | 1618 | (set_attr "type" "fsqrtd")] |
9b66ebb1 PB |
1619 | ) |
1620 | ||
1621 | ||
1622 | ;; Patterns to split/copy vfp condition flags. | |
1623 | ||
1624 | (define_insn "*movcc_vfp" | |
1625 | [(set (reg CC_REGNUM) | |
1626 | (reg VFPCC_REGNUM))] | |
00ea1506 | 1627 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
5a150108 | 1628 | "vmrs%?\\tAPSR_nzcv, FPSCR" |
9b66ebb1 | 1629 | [(set_attr "conds" "set") |
75fe7b2f | 1630 | (set_attr "type" "f_flag")] |
9b66ebb1 PB |
1631 | ) |
1632 | ||
e0e4be48 MI |
1633 | (define_insn "push_fpsysreg_insn" |
1634 | [(set (mem:SI (post_dec:SI (match_operand:SI 0 "s_register_operand" "+&rk"))) | |
1635 | (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "n")] | |
1636 | VUNSPEC_VSTR_VLDR))] | |
1637 | "TARGET_HAVE_FPCXT_CMSE && use_cmse" | |
1638 | { | |
1639 | static char buf[32]; | |
1640 | int fp_sysreg_enum = INTVAL (operands[1]); | |
1641 | ||
1642 | gcc_assert (IN_RANGE (fp_sysreg_enum, 0, NB_FP_SYSREGS - 1)); | |
1643 | ||
1644 | snprintf (buf, sizeof (buf), \"vstr%%?\\t%s, [%%0, #-4]!\", | |
1645 | fp_sysreg_names[fp_sysreg_enum]); | |
1646 | return buf; | |
1647 | } | |
1648 | [(set_attr "predicable" "yes") | |
1649 | (set_attr "type" "store_4")] | |
1650 | ) | |
1651 | ||
1652 | (define_insn "pop_fpsysreg_insn" | |
1653 | [(set (mem:SI (post_inc:SI (match_operand:SI 0 "s_register_operand" "+&rk"))) | |
1654 | (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "n")] | |
1655 | VUNSPEC_VSTR_VLDR))] | |
1656 | "TARGET_HAVE_FPCXT_CMSE && use_cmse" | |
1657 | { | |
1658 | static char buf[32]; | |
1659 | int fp_sysreg_enum = INTVAL (operands[1]); | |
1660 | ||
1661 | gcc_assert (IN_RANGE (fp_sysreg_enum, 0, NB_FP_SYSREGS - 1)); | |
1662 | ||
1663 | snprintf (buf, sizeof (buf), \"vldr%%?\\t%s, [%%0], #4\", | |
1664 | fp_sysreg_names[fp_sysreg_enum]); | |
1665 | return buf; | |
1666 | } | |
1667 | [(set_attr "predicable" "yes") | |
1668 | (set_attr "type" "load_4")] | |
1669 | ) | |
1670 | ||
0b1c7b27 MI |
1671 | ;; The operands are validated through the clear_multiple_operation |
1672 | ;; match_parallel predicate rather than through constraints so enable it only | |
1673 | ;; after reload. | |
1674 | (define_insn "*clear_vfp_multiple" | |
1675 | [(match_parallel 0 "clear_vfp_multiple_operation" | |
1676 | [(unspec_volatile [(const_int 0)] | |
1677 | VUNSPEC_VSCCLRM_VPR)])] | |
1678 | "TARGET_HAVE_FPCXT_CMSE && use_cmse && reload_completed" | |
1679 | { | |
1680 | int num_regs = XVECLEN (operands[0], 0); | |
1681 | char pattern[30]; | |
0b1c7b27 MI |
1682 | rtx reg; |
1683 | ||
1684 | strcpy (pattern, \"vscclrm%?\\t{%|\"); | |
1685 | if (num_regs > 1) | |
1686 | { | |
1687 | reg = XEXP (XVECEXP (operands[0], 0, 1), 0); | |
1688 | strcat (pattern, reg_names[REGNO (reg)]); | |
1689 | if (num_regs > 2) | |
1690 | { | |
1691 | strcat (pattern, \"-%|\"); | |
1692 | reg = XEXP (XVECEXP (operands[0], 0, num_regs - 1), 0); | |
1693 | strcat (pattern, reg_names[REGNO (reg)]); | |
1694 | } | |
1695 | strcat (pattern, \", \"); | |
1696 | } | |
1697 | ||
1698 | strcat (pattern, \"VPR}\"); | |
1699 | output_asm_insn (pattern, operands); | |
1700 | return \"\"; | |
1701 | } | |
1702 | [(set_attr "predicable" "yes") | |
1703 | (set_attr "type" "mov_reg")] | |
1704 | ) | |
1705 | ||
0ab81d9c MI |
1706 | (define_insn "lazy_store_multiple_insn" |
1707 | [(set (match_operand:SI 0 "s_register_operand" "+&rk") | |
1708 | (post_dec:SI (match_dup 0))) | |
1709 | (unspec_volatile [(const_int 0) | |
1710 | (mem:SI (post_dec:SI (match_dup 0)))] | |
1711 | VUNSPEC_VLSTM)] | |
1712 | "use_cmse && reload_completed" | |
1713 | "vlstm%?\\t%0" | |
1714 | [(set_attr "predicable" "yes") | |
1715 | (set_attr "type" "store_4")] | |
1716 | ) | |
1717 | ||
1718 | (define_insn "lazy_load_multiple_insn" | |
1719 | [(set (match_operand:SI 0 "s_register_operand" "+&rk") | |
1720 | (post_inc:SI (match_dup 0))) | |
1721 | (unspec_volatile:SI [(const_int 0) | |
1722 | (mem:SI (match_dup 0))] | |
1723 | VUNSPEC_VLLDM)] | |
1724 | "use_cmse && reload_completed" | |
1725 | "vlldm%?\\t%0" | |
1726 | [(set_attr "predicable" "yes") | |
1727 | (set_attr "type" "load_4")] | |
1728 | ) | |
1729 | ||
9b66ebb1 PB |
1730 | (define_insn_and_split "*cmpsf_split_vfp" |
1731 | [(set (reg:CCFP CC_REGNUM) | |
f1adb0a9 JB |
1732 | (compare:CCFP (match_operand:SF 0 "s_register_operand" "t") |
1733 | (match_operand:SF 1 "vfp_compare_operand" "tG")))] | |
00ea1506 | 1734 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
9b66ebb1 | 1735 | "#" |
00ea1506 | 1736 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
9b66ebb1 PB |
1737 | [(set (reg:CCFP VFPCC_REGNUM) |
1738 | (compare:CCFP (match_dup 0) | |
1739 | (match_dup 1))) | |
1740 | (set (reg:CCFP CC_REGNUM) | |
1741 | (reg:CCFP VFPCC_REGNUM))] | |
1742 | "" | |
1743 | ) | |
1744 | ||
1745 | (define_insn_and_split "*cmpsf_trap_split_vfp" | |
1746 | [(set (reg:CCFPE CC_REGNUM) | |
f1adb0a9 JB |
1747 | (compare:CCFPE (match_operand:SF 0 "s_register_operand" "t") |
1748 | (match_operand:SF 1 "vfp_compare_operand" "tG")))] | |
00ea1506 | 1749 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
9b66ebb1 | 1750 | "#" |
00ea1506 | 1751 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
9b66ebb1 PB |
1752 | [(set (reg:CCFPE VFPCC_REGNUM) |
1753 | (compare:CCFPE (match_dup 0) | |
1754 | (match_dup 1))) | |
1755 | (set (reg:CCFPE CC_REGNUM) | |
1756 | (reg:CCFPE VFPCC_REGNUM))] | |
1757 | "" | |
1758 | ) | |
1759 | ||
1760 | (define_insn_and_split "*cmpdf_split_vfp" | |
1761 | [(set (reg:CCFP CC_REGNUM) | |
1762 | (compare:CCFP (match_operand:DF 0 "s_register_operand" "w") | |
1763 | (match_operand:DF 1 "vfp_compare_operand" "wG")))] | |
e0dc3601 | 1764 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
9b66ebb1 | 1765 | "#" |
e0dc3601 | 1766 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
9b66ebb1 PB |
1767 | [(set (reg:CCFP VFPCC_REGNUM) |
1768 | (compare:CCFP (match_dup 0) | |
1769 | (match_dup 1))) | |
1770 | (set (reg:CCFP CC_REGNUM) | |
510bc854 | 1771 | (reg:CCFP VFPCC_REGNUM))] |
9b66ebb1 PB |
1772 | "" |
1773 | ) | |
1774 | ||
1775 | (define_insn_and_split "*cmpdf_trap_split_vfp" | |
1776 | [(set (reg:CCFPE CC_REGNUM) | |
1777 | (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w") | |
1778 | (match_operand:DF 1 "vfp_compare_operand" "wG")))] | |
e0dc3601 | 1779 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
9b66ebb1 | 1780 | "#" |
e0dc3601 | 1781 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
9b66ebb1 PB |
1782 | [(set (reg:CCFPE VFPCC_REGNUM) |
1783 | (compare:CCFPE (match_dup 0) | |
1784 | (match_dup 1))) | |
1785 | (set (reg:CCFPE CC_REGNUM) | |
1786 | (reg:CCFPE VFPCC_REGNUM))] | |
1787 | "" | |
1788 | ) | |
1789 | ||
1790 | ||
1791 | ;; Comparison patterns | |
1792 | ||
c2786584 KT |
1793 | ;; In the compare with FP zero case the ARM Architecture Reference Manual |
1794 | ;; specifies the immediate to be #0.0. However, some buggy assemblers only | |
1795 | ;; accept #0. We don't want to autodetect broken assemblers, so output #0. | |
9b66ebb1 PB |
1796 | (define_insn "*cmpsf_vfp" |
1797 | [(set (reg:CCFP VFPCC_REGNUM) | |
f1adb0a9 JB |
1798 | (compare:CCFP (match_operand:SF 0 "s_register_operand" "t,t") |
1799 | (match_operand:SF 1 "vfp_compare_operand" "t,G")))] | |
00ea1506 | 1800 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
9b66ebb1 | 1801 | "@ |
c2786584 KT |
1802 | vcmp%?.f32\\t%0, %1 |
1803 | vcmp%?.f32\\t%0, #0" | |
9b66ebb1 | 1804 | [(set_attr "predicable" "yes") |
51c69ddb | 1805 | (set_attr "type" "fcmps")] |
9b66ebb1 PB |
1806 | ) |
1807 | ||
1808 | (define_insn "*cmpsf_trap_vfp" | |
1809 | [(set (reg:CCFPE VFPCC_REGNUM) | |
f1adb0a9 JB |
1810 | (compare:CCFPE (match_operand:SF 0 "s_register_operand" "t,t") |
1811 | (match_operand:SF 1 "vfp_compare_operand" "t,G")))] | |
00ea1506 | 1812 | "TARGET_32BIT && TARGET_HARD_FLOAT" |
9b66ebb1 | 1813 | "@ |
c2786584 KT |
1814 | vcmpe%?.f32\\t%0, %1 |
1815 | vcmpe%?.f32\\t%0, #0" | |
9b66ebb1 | 1816 | [(set_attr "predicable" "yes") |
7dd8ecf0 | 1817 | (set_attr "type" "fcmps")] |
9b66ebb1 PB |
1818 | ) |
1819 | ||
1820 | (define_insn "*cmpdf_vfp" | |
1821 | [(set (reg:CCFP VFPCC_REGNUM) | |
1822 | (compare:CCFP (match_operand:DF 0 "s_register_operand" "w,w") | |
1823 | (match_operand:DF 1 "vfp_compare_operand" "w,G")))] | |
e0dc3601 | 1824 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
9b66ebb1 | 1825 | "@ |
c2786584 KT |
1826 | vcmp%?.f64\\t%P0, %P1 |
1827 | vcmp%?.f64\\t%P0, #0" | |
9b66ebb1 | 1828 | [(set_attr "predicable" "yes") |
51c69ddb | 1829 | (set_attr "type" "fcmpd")] |
9b66ebb1 PB |
1830 | ) |
1831 | ||
1832 | (define_insn "*cmpdf_trap_vfp" | |
1833 | [(set (reg:CCFPE VFPCC_REGNUM) | |
1834 | (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w,w") | |
1835 | (match_operand:DF 1 "vfp_compare_operand" "w,G")))] | |
e0dc3601 | 1836 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
9b66ebb1 | 1837 | "@ |
c2786584 KT |
1838 | vcmpe%?.f64\\t%P0, %P1 |
1839 | vcmpe%?.f64\\t%P0, #0" | |
9b66ebb1 | 1840 | [(set_attr "predicable" "yes") |
51c69ddb | 1841 | (set_attr "type" "fcmpd")] |
9b66ebb1 PB |
1842 | ) |
1843 | ||
d742ff4b | 1844 | ;; Fixed point to floating point conversions. |
7f3d8f56 RR |
1845 | (define_insn "*combine_vcvt_f32_<FCVTI32typename>" |
1846 | [(set (match_operand:SF 0 "s_register_operand" "=t") | |
1847 | (mult:SF (FCVT:SF (match_operand:SI 1 "s_register_operand" "0")) | |
d742ff4b | 1848 | (match_operand 2 |
7f3d8f56 RR |
1849 | "const_double_vcvt_power_of_two_reciprocal" "Dt")))] |
1850 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math" | |
d742ff4b RE |
1851 | "vcvt%?.f32.<FCVTI32typename>\\t%0, %1, %v2" |
1852 | [(set_attr "predicable" "yes") | |
d742ff4b | 1853 | (set_attr "type" "f_cvti2f")] |
7f3d8f56 | 1854 | ) |
9b66ebb1 | 1855 | |
7f3d8f56 RR |
1856 | ;; Not the ideal way of implementing this. Ideally we would be able to split |
1857 | ;; this into a move to a DP register and then a vcvt.f64.i32 | |
1858 | (define_insn "*combine_vcvt_f64_<FCVTI32typename>" | |
1859 | [(set (match_operand:DF 0 "s_register_operand" "=x,x,w") | |
1860 | (mult:DF (FCVT:DF (match_operand:SI 1 "s_register_operand" "r,t,r")) | |
d742ff4b | 1861 | (match_operand 2 |
7f3d8f56 | 1862 | "const_double_vcvt_power_of_two_reciprocal" "Dt,Dt,Dt")))] |
d742ff4b | 1863 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math |
7f3d8f56 RR |
1864 | && !TARGET_VFP_SINGLE" |
1865 | "@ | |
d742ff4b RE |
1866 | vmov%?.f32\\t%0, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2 |
1867 | vmov%?.f32\\t%0, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2 | |
1868 | vmov%?.f64\\t%P0, %1, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2" | |
1869 | [(set_attr "predicable" "yes") | |
1870 | (set_attr "ce_count" "2") | |
d742ff4b RE |
1871 | (set_attr "type" "f_cvti2f") |
1872 | (set_attr "length" "8")] | |
7f3d8f56 | 1873 | ) |
9b66ebb1 | 1874 | |
c75d51aa | 1875 | (define_insn "*combine_vcvtf2i" |
d31e00d4 RR |
1876 | [(set (match_operand:SI 0 "s_register_operand" "=t") |
1877 | (fix:SI (fix:SF (mult:SF (match_operand:SF 1 "s_register_operand" "0") | |
c75d51aa RL |
1878 | (match_operand 2 |
1879 | "const_double_vcvt_power_of_two" "Dp")))))] | |
1880 | "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math" | |
d31e00d4 | 1881 | "vcvt%?.s32.f32\\t%0, %1, %v2" |
c75d51aa | 1882 | [(set_attr "predicable" "yes") |
d31e00d4 | 1883 | (set_attr "type" "f_cvtf2i")] |
c75d51aa RL |
1884 | ) |
1885 | ||
d403b8d4 MW |
1886 | ;; FP16 conversions. |
1887 | (define_insn "neon_vcvth<sup>hf" | |
1888 | [(set (match_operand:HF 0 "s_register_operand" "=w") | |
1889 | (unspec:HF | |
1890 | [(match_operand:SI 1 "s_register_operand" "w")] | |
1891 | VCVTH_US))] | |
1892 | "TARGET_VFP_FP16INST" | |
1893 | "vcvt.f16.<sup>%#32\t%0, %1" | |
1894 | [(set_attr "conds" "unconditional") | |
1895 | (set_attr "type" "f_cvti2f")] | |
1896 | ) | |
1897 | ||
1898 | (define_insn "neon_vcvth<sup>si" | |
1899 | [(set (match_operand:SI 0 "s_register_operand" "=w") | |
1900 | (unspec:SI | |
1901 | [(match_operand:HF 1 "s_register_operand" "w")] | |
1902 | VCVTH_US))] | |
1903 | "TARGET_VFP_FP16INST" | |
1904 | "vcvt.<sup>%#32.f16\t%0, %1" | |
1905 | [(set_attr "conds" "unconditional") | |
1906 | (set_attr "type" "f_cvtf2i")] | |
1907 | ) | |
1908 | ||
1909 | ;; The neon_vcvth<sup>_nhf patterns are used to generate the instruction for the | |
1910 | ;; vcvth_n_f16_<sup>32 arm_fp16 intrinsics. They are complicated by the | |
1911 | ;; hardware requirement that the source and destination registers are the same | |
1912 | ;; despite having different machine modes. The approach is to use a temporary | |
1913 | ;; register for the conversion and move that to the correct destination. | |
1914 | ||
1915 | ;; Generate an unspec pattern for the intrinsic. | |
1916 | (define_insn "neon_vcvth<sup>_nhf_unspec" | |
1917 | [(set | |
1918 | (match_operand:SI 0 "s_register_operand" "=w") | |
1919 | (unspec:SI | |
1920 | [(match_operand:SI 1 "s_register_operand" "0") | |
1921 | (match_operand:SI 2 "immediate_operand" "i")] | |
1922 | VCVT_HF_US_N)) | |
1923 | (set | |
1924 | (match_operand:HF 3 "s_register_operand" "=w") | |
1925 | (float_truncate:HF (float:SF (match_dup 0))))] | |
1926 | "TARGET_VFP_FP16INST" | |
1927 | { | |
d57daa0c | 1928 | arm_const_bounds (operands[2], 1, 33); |
d403b8d4 MW |
1929 | return "vcvt.f16.<sup>32\t%0, %0, %2\;vmov.f32\t%3, %0"; |
1930 | } | |
1931 | [(set_attr "conds" "unconditional") | |
1932 | (set_attr "type" "f_cvti2f")] | |
1933 | ) | |
1934 | ||
1935 | ;; Generate the instruction patterns needed for vcvth_n_f16_s32 neon intrinsics. | |
1936 | (define_expand "neon_vcvth<sup>_nhf" | |
1937 | [(match_operand:HF 0 "s_register_operand") | |
1938 | (unspec:HF [(match_operand:SI 1 "s_register_operand") | |
1939 | (match_operand:SI 2 "immediate_operand")] | |
1940 | VCVT_HF_US_N)] | |
1941 | "TARGET_VFP_FP16INST" | |
1942 | { | |
1943 | rtx op1 = gen_reg_rtx (SImode); | |
1944 | ||
d57daa0c | 1945 | arm_const_bounds (operands[2], 1, 33); |
d403b8d4 MW |
1946 | |
1947 | emit_move_insn (op1, operands[1]); | |
1948 | emit_insn (gen_neon_vcvth<sup>_nhf_unspec (op1, op1, operands[2], | |
1949 | operands[0])); | |
1950 | DONE; | |
1951 | }) | |
1952 | ||
1953 | ;; The neon_vcvth<sup>_nsi patterns are used to generate the instruction for the | |
1954 | ;; vcvth_n_<sup>32_f16 arm_fp16 intrinsics. They have the same restrictions and | |
1955 | ;; are implemented in the same way as the neon_vcvth<sup>_nhf patterns. | |
1956 | ||
1957 | ;; Generate an unspec pattern, constraining the registers. | |
1958 | (define_insn "neon_vcvth<sup>_nsi_unspec" | |
1959 | [(set (match_operand:SI 0 "s_register_operand" "=w") | |
1960 | (unspec:SI | |
1961 | [(fix:SI | |
1962 | (fix:SF | |
1963 | (float_extend:SF | |
1964 | (match_operand:HF 1 "s_register_operand" "w")))) | |
1965 | (match_operand:SI 2 "immediate_operand" "i")] | |
1966 | VCVT_SI_US_N))] | |
1967 | "TARGET_VFP_FP16INST" | |
1968 | { | |
d57daa0c | 1969 | arm_const_bounds (operands[2], 1, 33); |
d403b8d4 MW |
1970 | return "vmov.f32\t%0, %1\;vcvt.<sup>%#32.f16\t%0, %0, %2"; |
1971 | } | |
1972 | [(set_attr "conds" "unconditional") | |
1973 | (set_attr "type" "f_cvtf2i")] | |
1974 | ) | |
1975 | ||
1976 | ;; Generate the instruction patterns needed for vcvth_n_f16_s32 neon intrinsics. | |
1977 | (define_expand "neon_vcvth<sup>_nsi" | |
1978 | [(match_operand:SI 0 "s_register_operand") | |
1979 | (unspec:SI | |
1980 | [(match_operand:HF 1 "s_register_operand") | |
1981 | (match_operand:SI 2 "immediate_operand")] | |
1982 | VCVT_SI_US_N)] | |
1983 | "TARGET_VFP_FP16INST" | |
1984 | { | |
1985 | rtx op1 = gen_reg_rtx (SImode); | |
1986 | ||
d57daa0c | 1987 | arm_const_bounds (operands[2], 1, 33); |
d403b8d4 MW |
1988 | emit_insn (gen_neon_vcvth<sup>_nsi_unspec (op1, operands[1], operands[2])); |
1989 | emit_move_insn (operands[0], op1); | |
1990 | DONE; | |
1991 | }) | |
1992 | ||
1993 | (define_insn "neon_vcvt<vcvth_op>h<sup>si" | |
1994 | [(set | |
1995 | (match_operand:SI 0 "s_register_operand" "=w") | |
1996 | (unspec:SI | |
1997 | [(match_operand:HF 1 "s_register_operand" "w")] | |
1998 | VCVT_HF_US))] | |
1999 | "TARGET_VFP_FP16INST" | |
2000 | "vcvt<vcvth_op>.<sup>%#32.f16\t%0, %1" | |
2001 | [(set_attr "conds" "unconditional") | |
2002 | (set_attr "type" "f_cvtf2i")] | |
2003 | ) | |
2004 | ||
7f3d8f56 | 2005 | ;; Store multiple insn used in function prologue. |
9b66ebb1 PB |
2006 | (define_insn "*push_multi_vfp" |
2007 | [(match_parallel 2 "multi_register_push" | |
2008 | [(set (match_operand:BLK 0 "memory_operand" "=m") | |
4e6f5666 | 2009 | (unspec:BLK [(match_operand:DF 1 "vfp_register_operand" "")] |
9b66ebb1 | 2010 | UNSPEC_PUSH_MULT))])] |
c7be0832 | 2011 | "TARGET_32BIT && TARGET_VFP_BASE" |
b27832ed | 2012 | "* return vfp_output_vstmd (operands);" |
75fe7b2f | 2013 | [(set_attr "type" "f_stored")] |
9b66ebb1 PB |
2014 | ) |
2015 | ||
1dd4fe1f KT |
2016 | ;; VRINT round to integral instructions. |
2017 | ;; Invoked for the patterns: btruncsf2, btruncdf2, ceilsf2, ceildf2, | |
2018 | ;; roundsf2, rounddf2, floorsf2, floordf2, nearbyintsf2, nearbyintdf2, | |
2019 | ;; rintsf2, rintdf2. | |
2020 | (define_insn "<vrint_pattern><SDF:mode>2" | |
2021 | [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>") | |
2022 | (unspec:SDF [(match_operand:SDF 1 | |
2023 | "register_operand" "<F_constraint>")] | |
2024 | VRINT))] | |
2f6403f1 | 2025 | "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>" |
1dd4fe1f KT |
2026 | "vrint<vrint_variant>%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1" |
2027 | [(set_attr "predicable" "<vrint_predicable>") | |
fca0efeb KT |
2028 | (set_attr "type" "f_rint<vfp_type>") |
2029 | (set_attr "conds" "<vrint_conds>")] | |
1dd4fe1f | 2030 | ) |
9b66ebb1 | 2031 | |
ababd936 KT |
2032 | ;; Implements the lround, lfloor and lceil optabs. |
2033 | (define_insn "l<vrint_pattern><su_optab><mode>si2" | |
2034 | [(set (match_operand:SI 0 "register_operand" "=t") | |
2035 | (FIXUORS:SI (unspec:SDF | |
2036 | [(match_operand:SDF 1 | |
2037 | "register_operand" "<F_constraint>")] VCVT)))] | |
c8d61ab8 | 2038 | "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>" |
962801c5 | 2039 | "vcvt<vrint_variant>.<su>32.<V_if_elem>\\t%0, %<V_reg>1" |
113c53c3 | 2040 | [(set_attr "conds" "unconditional") |
ababd936 KT |
2041 | (set_attr "type" "f_cvtf2i")] |
2042 | ) | |
2043 | ||
37202071 KT |
2044 | ;; MIN_EXPR and MAX_EXPR eventually map to 'smin' and 'smax' in RTL. |
2045 | ;; The 'smax' and 'smin' RTL standard pattern names do not specify which | |
2046 | ;; operand will be returned when both operands are zero (i.e. they may not | |
2047 | ;; honour signed zeroes), or when either operand is NaN. Therefore GCC | |
2048 | ;; only introduces MIN_EXPR/MAX_EXPR in fast math mode or when not honouring | |
2049 | ;; NaNs. | |
2050 | ||
2051 | (define_insn "smax<mode>3" | |
2052 | [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>") | |
2053 | (smax:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>") | |
2054 | (match_operand:SDF 2 "register_operand" "<F_constraint>")))] | |
2f6403f1 | 2055 | "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>" |
37202071 | 2056 | "vmaxnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" |
fca0efeb KT |
2057 | [(set_attr "type" "f_minmax<vfp_type>") |
2058 | (set_attr "conds" "unconditional")] | |
37202071 KT |
2059 | ) |
2060 | ||
2061 | (define_insn "smin<mode>3" | |
2062 | [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>") | |
2063 | (smin:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>") | |
2064 | (match_operand:SDF 2 "register_operand" "<F_constraint>")))] | |
2f6403f1 | 2065 | "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>" |
37202071 | 2066 | "vminnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" |
fca0efeb KT |
2067 | [(set_attr "type" "f_minmax<vfp_type>") |
2068 | (set_attr "conds" "unconditional")] | |
37202071 KT |
2069 | ) |
2070 | ||
0a18c19f | 2071 | ;; Scalar forms for the IEEE-754 fmax()/fmin() functions |
d403b8d4 MW |
2072 | |
2073 | (define_insn "neon_<fmaxmin_op>hf" | |
2074 | [(set | |
2075 | (match_operand:HF 0 "s_register_operand" "=w") | |
2076 | (unspec:HF | |
2077 | [(match_operand:HF 1 "s_register_operand" "w") | |
2078 | (match_operand:HF 2 "s_register_operand" "w")] | |
2079 | VMAXMINFNM))] | |
2080 | "TARGET_VFP_FP16INST" | |
2081 | "<fmaxmin_op>.f16\t%0, %1, %2" | |
2082 | [(set_attr "conds" "unconditional") | |
2083 | (set_attr "type" "f_minmaxs")] | |
2084 | ) | |
2085 | ||
0a18c19f DS |
2086 | (define_insn "<fmaxmin><mode>3" |
2087 | [(set (match_operand:SDF 0 "s_register_operand" "=<F_constraint>") | |
2088 | (unspec:SDF [(match_operand:SDF 1 "s_register_operand" "<F_constraint>") | |
2089 | (match_operand:SDF 2 "s_register_operand" "<F_constraint>")] | |
2090 | VMAXMINFNM))] | |
2091 | "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>" | |
2092 | "<fmaxmin_op>.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" | |
2093 | [(set_attr "type" "f_minmax<vfp_type>") | |
2094 | (set_attr "conds" "unconditional")] | |
2095 | ) | |
2096 | ||
f10743d3 KV |
2097 | ;; Write Floating-point Status and Control Register. |
2098 | (define_insn "set_fpscr" | |
719c8642 ASDV |
2099 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] |
2100 | VUNSPEC_SET_FPSCR)] | |
c7be0832 | 2101 | "TARGET_VFP_BASE" |
f10743d3 KV |
2102 | "mcr\\tp10, 7, %0, cr1, cr0, 0\\t @SET_FPSCR" |
2103 | [(set_attr "type" "mrs")]) | |
2104 | ||
2105 | ;; Read Floating-point Status and Control Register. | |
2106 | (define_insn "get_fpscr" | |
2107 | [(set (match_operand:SI 0 "register_operand" "=r") | |
719c8642 | 2108 | (unspec_volatile:SI [(const_int 0)] VUNSPEC_GET_FPSCR))] |
c7be0832 | 2109 | "TARGET_VFP_BASE" |
f10743d3 KV |
2110 | "mrc\\tp10, 7, %0, cr1, cr0, 0\\t @GET_FPSCR" |
2111 | [(set_attr "type" "mrs")]) | |
2112 | ||
2113 | ||
9b66ebb1 PB |
2114 | ;; Unimplemented insns: |
2115 | ;; fldm* | |
2116 | ;; fstm* | |
2117 | ;; fmdhr et al (VFPv1) | |
59b9a953 | 2118 | ;; Support for xD (single precision only) variants. |
9b66ebb1 | 2119 | ;; fmrrs, fmsrr |
655b5fc8 | 2120 | |
8d33eae8 TP |
2121 | ;; Load a DF immediate via GPR (where combinations of MOV and MOVT can be used) |
2122 | ;; and then move it into a VFP register. | |
655b5fc8 | 2123 | (define_insn_and_split "no_literal_pool_df_immediate" |
8d33eae8 TP |
2124 | [(set (match_operand:DF 0 "s_register_operand" "=w") |
2125 | (match_operand:DF 1 "const_double_operand" "F")) | |
2126 | (clobber (match_operand:DF 2 "s_register_operand" "=r"))] | |
2127 | "arm_disable_literal_pool | |
2128 | && TARGET_HARD_FLOAT | |
2129 | && !arm_const_double_rtx (operands[1]) | |
2130 | && !(TARGET_VFP_DOUBLE && vfp3_const_double_rtx (operands[1]))" | |
655b5fc8 | 2131 | "#" |
8d33eae8 TP |
2132 | "" |
2133 | [(const_int 0)] | |
2134 | { | |
655b5fc8 | 2135 | long buf[2]; |
8d33eae8 | 2136 | int order = BYTES_BIG_ENDIAN ? 1 : 0; |
655b5fc8 | 2137 | real_to_target (buf, CONST_DOUBLE_REAL_VALUE (operands[1]), DFmode); |
8d33eae8 TP |
2138 | unsigned HOST_WIDE_INT ival = zext_hwi (buf[order], 32); |
2139 | ival |= (zext_hwi (buf[1 - order], 32) << 32); | |
2140 | rtx cst = gen_int_mode (ival, DImode); | |
2141 | emit_move_insn (simplify_gen_subreg (DImode, operands[2], DFmode, 0), cst); | |
2142 | emit_move_insn (operands[0], operands[2]); | |
2143 | DONE; | |
2144 | } | |
2145 | ) | |
655b5fc8 | 2146 | |
8d33eae8 TP |
2147 | ;; Load a SF immediate via GPR (where combinations of MOV and MOVT can be used) |
2148 | ;; and then move it into a VFP register. | |
655b5fc8 | 2149 | (define_insn_and_split "no_literal_pool_sf_immediate" |
8d33eae8 TP |
2150 | [(set (match_operand:SF 0 "s_register_operand" "=t") |
2151 | (match_operand:SF 1 "const_double_operand" "E")) | |
2152 | (clobber (match_operand:SF 2 "s_register_operand" "=r"))] | |
2153 | "arm_disable_literal_pool | |
2154 | && TARGET_HARD_FLOAT | |
2155 | && !vfp3_const_double_rtx (operands[1])" | |
655b5fc8 | 2156 | "#" |
8d33eae8 TP |
2157 | "" |
2158 | [(const_int 0)] | |
2159 | { | |
655b5fc8 AV |
2160 | long buf; |
2161 | real_to_target (&buf, CONST_DOUBLE_REAL_VALUE (operands[1]), SFmode); | |
8d33eae8 TP |
2162 | rtx cst = gen_int_mode (buf, SImode); |
2163 | emit_move_insn (simplify_gen_subreg (SImode, operands[2], SFmode, 0), cst); | |
2164 | emit_move_insn (operands[0], operands[2]); | |
2165 | DONE; | |
2166 | } | |
2167 | ) | |
07b9bfd0 DZ |
2168 | |
2169 | ;; CDE instructions using FPU/MVE S/D registers | |
2170 | ||
2171 | (define_insn "arm_vcx1<mode>" | |
2172 | [(set (match_operand:SIDI 0 "register_operand" "=t") | |
2173 | (unspec:SIDI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
2174 | (match_operand:SI 2 "const_int_vcde1_operand" "i")] | |
2175 | UNSPEC_VCDE))] | |
2176 | "TARGET_CDE && (TARGET_ARM_FP || TARGET_HAVE_MVE)" | |
2177 | "vcx1\\tp%c1, %<V_reg>0, #%c2" | |
2178 | [(set_attr "type" "coproc")] | |
2179 | ) | |
2180 | ||
2181 | (define_insn "arm_vcx1a<mode>" | |
2182 | [(set (match_operand:SIDI 0 "register_operand" "=t") | |
2183 | (unspec:SIDI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
2184 | (match_operand:SIDI 2 "register_operand" "0") | |
2185 | (match_operand:SI 3 "const_int_vcde1_operand" "i")] | |
2186 | UNSPEC_VCDEA))] | |
2187 | "TARGET_CDE && (TARGET_ARM_FP || TARGET_HAVE_MVE)" | |
2188 | "vcx1a\\tp%c1, %<V_reg>0, #%c3" | |
2189 | [(set_attr "type" "coproc")] | |
2190 | ) | |
2191 | ||
2192 | (define_insn "arm_vcx2<mode>" | |
2193 | [(set (match_operand:SIDI 0 "register_operand" "=t") | |
2194 | (unspec:SIDI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
2195 | (match_operand:SIDI 2 "register_operand" "t") | |
2196 | (match_operand:SI 3 "const_int_vcde2_operand" "i")] | |
2197 | UNSPEC_VCDE))] | |
2198 | "TARGET_CDE && (TARGET_ARM_FP || TARGET_HAVE_MVE)" | |
2199 | "vcx2\\tp%c1, %<V_reg>0, %<V_reg>2, #%c3" | |
2200 | [(set_attr "type" "coproc")] | |
2201 | ) | |
2202 | ||
2203 | (define_insn "arm_vcx2a<mode>" | |
2204 | [(set (match_operand:SIDI 0 "register_operand" "=t") | |
2205 | (unspec:SIDI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
2206 | (match_operand:SIDI 2 "register_operand" "0") | |
2207 | (match_operand:SIDI 3 "register_operand" "t") | |
2208 | (match_operand:SI 4 "const_int_vcde2_operand" "i")] | |
2209 | UNSPEC_VCDEA))] | |
2210 | "TARGET_CDE && (TARGET_ARM_FP || TARGET_HAVE_MVE)" | |
2211 | "vcx2a\\tp%c1, %<V_reg>0, %<V_reg>3, #%c4" | |
2212 | [(set_attr "type" "coproc")] | |
2213 | ) | |
2214 | ||
2215 | (define_insn "arm_vcx3<mode>" | |
2216 | [(set (match_operand:SIDI 0 "register_operand" "=t") | |
2217 | (unspec:SIDI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
2218 | (match_operand:SIDI 2 "register_operand" "t") | |
2219 | (match_operand:SIDI 3 "register_operand" "t") | |
2220 | (match_operand:SI 4 "const_int_vcde3_operand" "i")] | |
2221 | UNSPEC_VCDE))] | |
2222 | "TARGET_CDE && (TARGET_ARM_FP || TARGET_HAVE_MVE)" | |
2223 | "vcx3\\tp%c1, %<V_reg>0, %<V_reg>2, %<V_reg>3, #%c4" | |
2224 | [(set_attr "type" "coproc")] | |
2225 | ) | |
2226 | ||
2227 | (define_insn "arm_vcx3a<mode>" | |
2228 | [(set (match_operand:SIDI 0 "register_operand" "=t") | |
2229 | (unspec:SIDI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
2230 | (match_operand:SIDI 2 "register_operand" "0") | |
2231 | (match_operand:SIDI 3 "register_operand" "t") | |
2232 | (match_operand:SIDI 4 "register_operand" "t") | |
2233 | (match_operand:SI 5 "const_int_vcde3_operand" "i")] | |
2234 | UNSPEC_VCDEA))] | |
2235 | "TARGET_CDE && (TARGET_ARM_FP || TARGET_HAVE_MVE)" | |
2236 | "vcx3a\\tp%c1, %<V_reg>0, %<V_reg>3, %<V_reg>4, #%c5" | |
2237 | [(set_attr "type" "coproc")] | |
2238 | ) |