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config.gcc (with_fpu): Allow --with-fpu=vfp3.
[thirdparty/gcc.git] / gcc / config / arm / vfp.md
CommitLineData
9b66ebb1 1;; ARM VFP coprocessor Machine Description
5b3e6663 2;; Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc.
9b66ebb1
PB		 3;; Written by CodeSourcery, LLC.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published by
9;; the Free Software Foundation; either version 2, or (at your option)
10;; any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but
13;; WITHOUT ANY WARRANTY; without even the implied warranty of
14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15;; General Public License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING. If not, write to the Free
39d14dda
KC		 19;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
20;; 02110-1301, USA. */
9b66ebb1
PB		 21
22;; Additional register numbers
23(define_constants
f1adb0a9 24 [(VFPCC_REGNUM 127)]
9b66ebb1
PB		 25)
26
27;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
28;; Pipeline description
29;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
30
31(define_automaton "vfp11")
32
33;; There are 3 pipelines in the VFP11 unit.
34;;
35;; - A 8-stage FMAC pipeline (7 execute + writeback) with forward from
36;; fourth stage for simple operations.
37;;
38;; - A 5-stage DS pipeline (4 execute + writeback) for divide/sqrt insns.
39;; These insns also uses first execute stage of FMAC pipeline.
40;;
41;; - A 4-stage LS pipeline (execute + 2 memory + writeback) with forward from
42;; second memory stage for loads.
43
44;; We do not model Write-After-Read hazards.
59b9a953
KH		 45;; We do not do write scheduling with the arm core, so it is only necessary
46;; to model the first stage of each pipeline
9b66ebb1 47;; ??? Need to model LS pipeline properly for load/store multiple?
59b9a953 48;; We do not model fmstat properly. This could be done by modeling pipelines
9b66ebb1
PB		 49;; properly and defining an absence set between a dummy fmstat unit and all
50;; other vfp units.
51
52(define_cpu_unit "fmac" "vfp11")
53
54(define_cpu_unit "ds" "vfp11")
55
56(define_cpu_unit "vfp_ls" "vfp11")
57
75fe7b2f
RE		 58(define_cpu_unit "fmstat" "vfp11")
59
60(exclusion_set "fmac,ds" "fmstat")
61
9b66ebb1 62;; The VFP "type" attributes differ from those used in the FPA model.
112cdef5 63;; ffarith Fast floating point insns, e.g. abs, neg, cpy, cmp.
9b66ebb1 64;; farith Most arithmetic insns.
59b9a953 65;; fmul Double precision multiply.
9b66ebb1
PB		 66;; fdivs Single precision sqrt or division.
67;; fdivd Double precision sqrt or division.
75fe7b2f
RE		 68;; f_flag fmstat operation
69;; f_load[sd] Floating point load from memory.
70;; f_store[sd] Floating point store to memory.
9b66ebb1
PB		 71;; f_2_r Transfer vfp to arm reg.
72;; r_2_f Transfer arm to vfp reg.
75fe7b2f 73;; f_cvt Convert floating<->integral
9b66ebb1
PB		 74
75(define_insn_reservation "vfp_ffarith" 4
75fe7b2f 76 (and (eq_attr "generic_vfp" "yes")
9b66ebb1
PB		 77 (eq_attr "type" "ffarith"))
78 "fmac")
79
80(define_insn_reservation "vfp_farith" 8
75fe7b2f
RE		 81 (and (eq_attr "generic_vfp" "yes")
82 (eq_attr "type" "farith,f_cvt"))
9b66ebb1
PB		 83 "fmac")
84
85(define_insn_reservation "vfp_fmul" 9
75fe7b2f 86 (and (eq_attr "generic_vfp" "yes")
9b66ebb1
PB		 87 (eq_attr "type" "fmul"))
88 "fmac*2")
89
90(define_insn_reservation "vfp_fdivs" 19
75fe7b2f 91 (and (eq_attr "generic_vfp" "yes")
9b66ebb1
PB		 92 (eq_attr "type" "fdivs"))
93 "ds*15")
94
95(define_insn_reservation "vfp_fdivd" 33
75fe7b2f 96 (and (eq_attr "generic_vfp" "yes")
9b66ebb1
PB		 97 (eq_attr "type" "fdivd"))
98 "fmac+ds*29")
99
100;; Moves to/from arm regs also use the load/store pipeline.
101(define_insn_reservation "vfp_fload" 4
75fe7b2f
RE		 102 (and (eq_attr "generic_vfp" "yes")
103 (eq_attr "type" "f_loads,f_loadd,r_2_f"))
9b66ebb1
PB		 104 "vfp_ls")
105
106(define_insn_reservation "vfp_fstore" 4
75fe7b2f
RE		 107 (and (eq_attr "generic_vfp" "yes")
108 (eq_attr "type" "f_stores,f_stored,f_2_r"))
9b66ebb1
PB		 109 "vfp_ls")
110
75fe7b2f
RE		 111(define_insn_reservation "vfp_to_cpsr" 4
112 (and (eq_attr "generic_vfp" "yes")
113 (eq_attr "type" "f_flag"))
114 "fmstat,vfp_ls*3")
9b66ebb1
PB		 115
116;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
59b9a953 117;; Insn pattern
9b66ebb1
PB		 118;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
119
120;; SImode moves
121;; ??? For now do not allow loading constants into vfp regs. This causes
59b9a953 122;; problems because small constants get converted into adds.
9b66ebb1 123(define_insn "*arm_movsi_vfp"
f1adb0a9
JB		 124 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r ,m,*t,r,*t,*t, *Uv")
125 (match_operand:SI 1 "general_operand" "rI,K,N,mi,r,r,*t,*t,*Uvi,*t"))]
9b66ebb1
PB		 126 "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT
127 && ( s_register_operand (operands[0], SImode)
128 || s_register_operand (operands[1], SImode))"
5b3e6663
PB		 129 "*
130 switch (which_alternative)
131 {
132 case 0:
133 return \"mov%?\\t%0, %1\";
134 case 1:
135 return \"mvn%?\\t%0, #%B1\";
136 case 2:
137 return \"movw%?\\t%0, %1\";
138 case 3:
139 return \"ldr%?\\t%0, %1\";
140 case 4:
141 return \"str%?\\t%1, %0\";
142 case 5:
143 return \"fmsr%?\\t%0, %1\\t%@ int\";
144 case 6:
145 return \"fmrs%?\\t%0, %1\\t%@ int\";
146 case 7:
147 return \"fcpys%?\\t%0, %1\\t%@ int\";
148 case 8: case 9:
149 return output_move_vfp (operands);
150 default:
151 gcc_unreachable ();
152 }
153 "
154 [(set_attr "predicable" "yes")
155 (set_attr "type" "*,*,*,load1,store1,r_2_f,f_2_r,ffarith,f_loads,f_stores")
156 (set_attr "pool_range" "*,*,*,4096,*,*,*,*,1020,*")
157 (set_attr "neg_pool_range" "*,*,*,4084,*,*,*,*,1008,*")]
158)
159
160(define_insn "*thumb2_movsi_vfp"
f1adb0a9
JB		 161 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*t,r,*t,*t, *Uv")
162 (match_operand:SI 1 "general_operand" "rI,K,N,mi,r,r,*t,*t,*Uvi,*t"))]
5b3e6663
PB		 163 "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT
164 && ( s_register_operand (operands[0], SImode)
165 || s_register_operand (operands[1], SImode))"
166 "*
167 switch (which_alternative)
168 {
169 case 0:
170 return \"mov%?\\t%0, %1\";
171 case 1:
172 return \"mvn%?\\t%0, #%B1\";
173 case 2:
174 return \"movw%?\\t%0, %1\";
175 case 3:
176 return \"ldr%?\\t%0, %1\";
177 case 4:
178 return \"str%?\\t%1, %0\";
179 case 5:
180 return \"fmsr%?\\t%0, %1\\t%@ int\";
181 case 6:
182 return \"fmrs%?\\t%0, %1\\t%@ int\";
183 case 7:
184 return \"fcpys%?\\t%0, %1\\t%@ int\";
185 case 8: case 9:
186 return output_move_vfp (operands);
187 default:
188 gcc_unreachable ();
189 }
190 "
9b66ebb1 191 [(set_attr "predicable" "yes")
5b3e6663
PB		 192 (set_attr "type" "*,*,*,load1,store1,r_2_f,f_2_r,ffarith,f_load,f_store")
193 (set_attr "pool_range" "*,*,*,4096,*,*,*,*,1020,*")
194 (set_attr "neg_pool_range" "*,*,*, 0,*,*,*,*,1008,*")]
9b66ebb1
PB		 195)
196
197
198;; DImode moves
199
200(define_insn "*arm_movdi_vfp"
fdd695fd
PB		 201 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv")
202 (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))]
d5b6e637
PB		 203 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
204 && ( register_operand (operands[0], DImode)
205 || register_operand (operands[1], DImode))"
9b66ebb1
PB		 206 "*
207 switch (which_alternative)
208 {
9b901d50
RE		 209 case 0:
210 return \"#\";
211 case 1:
212 case 2:
213 return output_move_double (operands);
9b66ebb1 214 case 3:
94634f14 215 return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
9b66ebb1 216 case 4:
94634f14 217 return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
9b66ebb1
PB		 218 case 5:
219 return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
5b3e6663
PB		 220 case 6: case 7:
221 return output_move_vfp (operands);
9b66ebb1 222 default:
e6d29d15 223 gcc_unreachable ();
9b66ebb1
PB		 224 }
225 "
75fe7b2f 226 [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarith,f_loadd,f_stored")
9b66ebb1
PB		 227 (set_attr "length" "8,8,8,4,4,4,4,4")
228 (set_attr "pool_range" "*,1020,*,*,*,*,1020,*")
229 (set_attr "neg_pool_range" "*,1008,*,*,*,*,1008,*")]
230)
231
5b3e6663
PB		 232(define_insn "*thumb2_movdi_vfp"
233 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv")
234 (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))]
235 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
236 "*
237 switch (which_alternative)
238 {
239 case 0: case 1: case 2:
240 return (output_move_double (operands));
241 case 3:
242 return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
243 case 4:
244 return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
245 case 5:
246 return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
247 case 6: case 7:
248 return output_move_vfp (operands);
249 default:
250 abort ();
251 }
252 "
253 [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarith,f_load,f_store")
254 (set_attr "length" "8,8,8,4,4,4,4,4")
255 (set_attr "pool_range" "*,4096,*,*,*,*,1020,*")
256 (set_attr "neg_pool_range" "*, 0,*,*,*,*,1008,*")]
257)
258
9b66ebb1
PB		 259
260;; SFmode moves
221b2a64
PB		 261;; Disparage the w<->r cases because reloading an invalid address is
262;; preferable to loading the value via integer registers.
9b66ebb1
PB		 263
264(define_insn "*movsf_vfp"
f1adb0a9
JB		 265 [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t ,t ,Uv,r ,m,t,r")
266 (match_operand:SF 1 "general_operand" " ?r,t,Dv,UvE,t, mE,r,t,r"))]
9b66ebb1
PB		 267 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
268 && ( s_register_operand (operands[0], SFmode)
269 || s_register_operand (operands[1], SFmode))"
5b3e6663
PB		 270 "*
271 switch (which_alternative)
272 {
273 case 0:
274 return \"fmsr%?\\t%0, %1\";
275 case 1:
276 return \"fmrs%?\\t%0, %1\";
f1adb0a9
JB		 277 case 2:
278 return \"fconsts%?\\t%0, #%G1\";
279 case 3: case 4:
5b3e6663 280 return output_move_vfp (operands);
5b3e6663 281 case 5:
f1adb0a9 282 return \"ldr%?\\t%0, %1\\t%@ float\";
5b3e6663 283 case 6:
f1adb0a9 284 return \"str%?\\t%1, %0\\t%@ float\";
5b3e6663 285 case 7:
f1adb0a9
JB		 286 return \"fcpys%?\\t%0, %1\";
287 case 8:
5b3e6663
PB		 288 return \"mov%?\\t%0, %1\\t%@ float\";
289 default:
290 gcc_unreachable ();
291 }
292 "
9b66ebb1 293 [(set_attr "predicable" "yes")
f1adb0a9
JB		 294 (set_attr "type"
295 "r_2_f,f_2_r,farith,f_loads,f_stores,load1,store1,ffarith,*")
296 (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
297 (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")]
9b66ebb1
PB		 298)
299
5b3e6663 300(define_insn "*thumb2_movsf_vfp"
f1adb0a9
JB		 301 [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t, t ,Uv,r ,m,t,r")
302 (match_operand:SF 1 "general_operand" " ?r,t,Dv,UvE,t, mE,r,t,r"))]
5b3e6663
PB		 303 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
304 && ( s_register_operand (operands[0], SFmode)
305 || s_register_operand (operands[1], SFmode))"
306 "*
307 switch (which_alternative)
308 {
309 case 0:
310 return \"fmsr%?\\t%0, %1\";
311 case 1:
312 return \"fmrs%?\\t%0, %1\";
f1adb0a9
JB		 313 case 2:
314 return \"fconsts%?\\t%0, #%G1\";
315 case 3: case 4:
5b3e6663 316 return output_move_vfp (operands);
5b3e6663 317 case 5:
f1adb0a9 318 return \"ldr%?\\t%0, %1\\t%@ float\";
5b3e6663 319 case 6:
f1adb0a9 320 return \"str%?\\t%1, %0\\t%@ float\";
5b3e6663 321 case 7:
f1adb0a9
JB		 322 return \"fcpys%?\\t%0, %1\";
323 case 8:
5b3e6663
PB		 324 return \"mov%?\\t%0, %1\\t%@ float\";
325 default:
326 gcc_unreachable ();
327 }
328 "
329 [(set_attr "predicable" "yes")
f1adb0a9
JB		 330 (set_attr "type"
331 "r_2_f,f_2_r,farith,f_load,f_store,load1,store1,ffarith,*")
332 (set_attr "pool_range" "*,*,*,1020,*,4092,*,*,*")
333 (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
5b3e6663
PB		 334)
335
9b66ebb1
PB		 336
337;; DFmode moves
338
339(define_insn "*movdf_vfp"
f1adb0a9
JB		 340 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r")
341 (match_operand:DF 1 "soft_df_operand" " ?r,w,Dv,mF,r,UvF,w, w,r"))]
d5b6e637
PB		 342 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
343 && ( register_operand (operands[0], DFmode)
344 || register_operand (operands[1], DFmode))"
9b66ebb1
PB		 345 "*
346 {
347 switch (which_alternative)
348 {
349 case 0:
350 return \"fmdrr%?\\t%P0, %Q1, %R1\";
351 case 1:
352 return \"fmrrd%?\\t%Q0, %R0, %P1\";
f1adb0a9
JB		 353 case 2:
354 return \"fconstd%?\\t%P0, #%G1\";
355 case 3: case 4:
9b66ebb1 356 return output_move_double (operands);
f1adb0a9 357 case 5: case 6:
5b3e6663 358 return output_move_vfp (operands);
9b901d50 359 case 7:
f1adb0a9
JB		 360 return \"fcpyd%?\\t%P0, %P1\";
361 case 8:
9b901d50 362 return \"#\";
9b66ebb1 363 default:
e6d29d15 364 gcc_unreachable ();
9b66ebb1
PB		 365 }
366 }
367 "
f1adb0a9
JB		 368 [(set_attr "type"
369 "r_2_f,f_2_r,farith,f_loadd,f_stored,load2,store2,ffarith,*")
370 (set_attr "length" "4,4,4,8,8,4,4,4,8")
371 (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*")
372 (set_attr "neg_pool_range" "*,*,*,1008,*,1008,*,*,*")]
9b66ebb1
PB		 373)
374
5b3e6663 375(define_insn "*thumb2_movdf_vfp"
f1adb0a9
JB		 376 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r")
377 (match_operand:DF 1 "soft_df_operand" " ?r,w,Dv,mF,r,UvF,w, w,r"))]
5b3e6663
PB		 378 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
379 "*
380 {
381 switch (which_alternative)
382 {
383 case 0:
384 return \"fmdrr%?\\t%P0, %Q1, %R1\";
385 case 1:
386 return \"fmrrd%?\\t%Q0, %R0, %P1\";
f1adb0a9
JB		 387 case 2:
388 return \"fconstd%?\\t%P0, #%G1\";
389 case 3: case 4: case 8:
5b3e6663 390 return output_move_double (operands);
f1adb0a9 391 case 5: case 6:
5b3e6663 392 return output_move_vfp (operands);
f1adb0a9 393 case 7:
5b3e6663
PB		 394 return \"fcpyd%?\\t%P0, %P1\";
395 default:
396 abort ();
397 }
398 }
399 "
f1adb0a9
JB		 400 [(set_attr "type"
401 "r_2_f,f_2_r,farith,load2,store2,f_load,f_store,ffarith,*")
402 (set_attr "length" "4,4,4,8,8,4,4,4,8")
403 (set_attr "pool_range" "*,*,*,4096,*,1020,*,*,*")
404 (set_attr "neg_pool_range" "*,*,*,0,*,1008,*,*,*")]
5b3e6663
PB		 405)
406
9b66ebb1
PB		 407
408;; Conditional move patterns
409
410(define_insn "*movsfcc_vfp"
f1adb0a9 411 [(set (match_operand:SF 0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
9b66ebb1
PB		 412 (if_then_else:SF
413 (match_operator 3 "arm_comparison_operator"
414 [(match_operand 4 "cc_register" "") (const_int 0)])
f1adb0a9
JB		 415 (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
416 (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
9b66ebb1
PB		 417 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
418 "@
419 fcpys%D3\\t%0, %2
420 fcpys%d3\\t%0, %1
421 fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
422 fmsr%D3\\t%0, %2
423 fmsr%d3\\t%0, %1
424 fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
425 fmrs%D3\\t%0, %2
426 fmrs%d3\\t%0, %1
427 fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
428 [(set_attr "conds" "use")
429 (set_attr "length" "4,4,8,4,4,8,4,4,8")
430 (set_attr "type" "ffarith,ffarith,ffarith,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
431)
432
5b3e6663 433(define_insn "*thumb2_movsfcc_vfp"
f1adb0a9 434 [(set (match_operand:SF 0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
5b3e6663
PB		 435 (if_then_else:SF
436 (match_operator 3 "arm_comparison_operator"
437 [(match_operand 4 "cc_register" "") (const_int 0)])
f1adb0a9
JB		 438 (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
439 (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
5b3e6663
PB		 440 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
441 "@
442 it\\t%D3\;fcpys%D3\\t%0, %2
443 it\\t%d3\;fcpys%d3\\t%0, %1
444 ite\\t%D3\;fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
445 it\\t%D3\;fmsr%D3\\t%0, %2
446 it\\t%d3\;fmsr%d3\\t%0, %1
447 ite\\t%D3\;fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
448 it\\t%D3\;fmrs%D3\\t%0, %2
449 it\\t%d3\;fmrs%d3\\t%0, %1
450 ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
451 [(set_attr "conds" "use")
452 (set_attr "length" "6,6,10,6,6,10,6,6,10")
453 (set_attr "type" "ffarith,ffarith,ffarith,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
454)
455
9b66ebb1
PB		 456(define_insn "*movdfcc_vfp"
457 [(set (match_operand:DF 0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
458 (if_then_else:DF
459 (match_operator 3 "arm_comparison_operator"
460 [(match_operand 4 "cc_register" "") (const_int 0)])
461 (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
462 (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
463 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
464 "@
465 fcpyd%D3\\t%P0, %P2
466 fcpyd%d3\\t%P0, %P1
467 fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
468 fmdrr%D3\\t%P0, %Q2, %R2
469 fmdrr%d3\\t%P0, %Q1, %R1
470 fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
471 fmrrd%D3\\t%Q0, %R0, %P2
472 fmrrd%d3\\t%Q0, %R0, %P1
473 fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
474 [(set_attr "conds" "use")
475 (set_attr "length" "4,4,8,4,4,8,4,4,8")
476 (set_attr "type" "ffarith,ffarith,ffarith,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
477)
478
5b3e6663
PB		 479(define_insn "*thumb2_movdfcc_vfp"
480 [(set (match_operand:DF 0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
481 (if_then_else:DF
482 (match_operator 3 "arm_comparison_operator"
483 [(match_operand 4 "cc_register" "") (const_int 0)])
484 (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
485 (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
486 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
487 "@
488 it\\t%D3\;fcpyd%D3\\t%P0, %P2
489 it\\t%d3\;fcpyd%d3\\t%P0, %P1
490 ite\\t%D3\;fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
491 it\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2
492 it\t%d3\;fmdrr%d3\\t%P0, %Q1, %R1
493 ite\\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
494 it\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2
495 it\t%d3\;fmrrd%d3\\t%Q0, %R0, %P1
496 ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
497 [(set_attr "conds" "use")
498 (set_attr "length" "6,6,10,6,6,10,6,6,10")
499 (set_attr "type" "ffarith,ffarith,ffarith,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
500)
501
9b66ebb1
PB		 502
503;; Sign manipulation functions
504
505(define_insn "*abssf2_vfp"
f1adb0a9
JB		 506 [(set (match_operand:SF 0 "s_register_operand" "=t")
507 (abs:SF (match_operand:SF 1 "s_register_operand" "t")))]
5b3e6663 508 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 509 "fabss%?\\t%0, %1"
510 [(set_attr "predicable" "yes")
511 (set_attr "type" "ffarith")]
512)
513
514(define_insn "*absdf2_vfp"
515 [(set (match_operand:DF 0 "s_register_operand" "=w")
516 (abs:DF (match_operand:DF 1 "s_register_operand" "w")))]
5b3e6663 517 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 518 "fabsd%?\\t%P0, %P1"
519 [(set_attr "predicable" "yes")
520 (set_attr "type" "ffarith")]
521)
522
523(define_insn "*negsf2_vfp"
f1adb0a9
JB		 524 [(set (match_operand:SF 0 "s_register_operand" "=t,?r")
525 (neg:SF (match_operand:SF 1 "s_register_operand" "t,r")))]
5b3e6663 526 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
81632f11
RE		 527 "@
528 fnegs%?\\t%0, %1
529 eor%?\\t%0, %1, #-2147483648"
9b66ebb1
PB		 530 [(set_attr "predicable" "yes")
531 (set_attr "type" "ffarith")]
532)
533
81632f11
RE		 534(define_insn_and_split "*negdf2_vfp"
535 [(set (match_operand:DF 0 "s_register_operand" "=w,?r,?r")
536 (neg:DF (match_operand:DF 1 "s_register_operand" "w,0,r")))]
5b3e6663 537 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
81632f11
RE		 538 "@
539 fnegd%?\\t%P0, %P1
540 #
541 #"
5b3e6663 542 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && reload_completed
81632f11
RE		 543 && arm_general_register_operand (operands[0], DFmode)"
544 [(set (match_dup 0) (match_dup 1))]
545 "
546 if (REGNO (operands[0]) == REGNO (operands[1]))
547 {
548 operands[0] = gen_highpart (SImode, operands[0]);
549 operands[1] = gen_rtx_XOR (SImode, operands[0], GEN_INT (0x80000000));
550 }
551 else
552 {
553 rtx in_hi, in_lo, out_hi, out_lo;
554
555 in_hi = gen_rtx_XOR (SImode, gen_highpart (SImode, operands[1]),
556 GEN_INT (0x80000000));
557 in_lo = gen_lowpart (SImode, operands[1]);
558 out_hi = gen_highpart (SImode, operands[0]);
559 out_lo = gen_lowpart (SImode, operands[0]);
560
561 if (REGNO (in_lo) == REGNO (out_hi))
562 {
563 emit_insn (gen_rtx_SET (SImode, out_lo, in_lo));
564 operands[0] = out_hi;
565 operands[1] = in_hi;
566 }
567 else
568 {
569 emit_insn (gen_rtx_SET (SImode, out_hi, in_hi));
570 operands[0] = out_lo;
571 operands[1] = in_lo;
572 }
573 }
574 "
9b66ebb1 575 [(set_attr "predicable" "yes")
81632f11 576 (set_attr "length" "4,4,8")
9b66ebb1
PB		 577 (set_attr "type" "ffarith")]
578)
579
580
581;; Arithmetic insns
582
583(define_insn "*addsf3_vfp"
f1adb0a9
JB		 584 [(set (match_operand:SF 0 "s_register_operand" "=t")
585 (plus:SF (match_operand:SF 1 "s_register_operand" "t")
586 (match_operand:SF 2 "s_register_operand" "t")))]
5b3e6663 587 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 588 "fadds%?\\t%0, %1, %2"
589 [(set_attr "predicable" "yes")
590 (set_attr "type" "farith")]
591)
592
593(define_insn "*adddf3_vfp"
594 [(set (match_operand:DF 0 "s_register_operand" "=w")
595 (plus:DF (match_operand:DF 1 "s_register_operand" "w")
596 (match_operand:DF 2 "s_register_operand" "w")))]
5b3e6663 597 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 598 "faddd%?\\t%P0, %P1, %P2"
599 [(set_attr "predicable" "yes")
600 (set_attr "type" "farith")]
601)
602
603
604(define_insn "*subsf3_vfp"
f1adb0a9
JB		 605 [(set (match_operand:SF 0 "s_register_operand" "=t")
606 (minus:SF (match_operand:SF 1 "s_register_operand" "t")
607 (match_operand:SF 2 "s_register_operand" "t")))]
5b3e6663 608 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 609 "fsubs%?\\t%0, %1, %2"
610 [(set_attr "predicable" "yes")
611 (set_attr "type" "farith")]
612)
613
614(define_insn "*subdf3_vfp"
615 [(set (match_operand:DF 0 "s_register_operand" "=w")
616 (minus:DF (match_operand:DF 1 "s_register_operand" "w")
617 (match_operand:DF 2 "s_register_operand" "w")))]
5b3e6663 618 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 619 "fsubd%?\\t%P0, %P1, %P2"
620 [(set_attr "predicable" "yes")
621 (set_attr "type" "farith")]
622)
623
624
625;; Division insns
626
627(define_insn "*divsf3_vfp"
f1adb0a9
JB		 628 [(set (match_operand:SF 0 "s_register_operand" "+t")
629 (div:SF (match_operand:SF 1 "s_register_operand" "t")
630 (match_operand:SF 2 "s_register_operand" "t")))]
5b3e6663 631 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 632 "fdivs%?\\t%0, %1, %2"
633 [(set_attr "predicable" "yes")
634 (set_attr "type" "fdivs")]
635)
636
637(define_insn "*divdf3_vfp"
638 [(set (match_operand:DF 0 "s_register_operand" "+w")
639 (div:DF (match_operand:DF 1 "s_register_operand" "w")
640 (match_operand:DF 2 "s_register_operand" "w")))]
5b3e6663 641 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 642 "fdivd%?\\t%P0, %P1, %P2"
643 [(set_attr "predicable" "yes")
644 (set_attr "type" "fdivd")]
645)
646
647
648;; Multiplication insns
649
650(define_insn "*mulsf3_vfp"
f1adb0a9
JB		 651 [(set (match_operand:SF 0 "s_register_operand" "+t")
652 (mult:SF (match_operand:SF 1 "s_register_operand" "t")
653 (match_operand:SF 2 "s_register_operand" "t")))]
5b3e6663 654 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 655 "fmuls%?\\t%0, %1, %2"
656 [(set_attr "predicable" "yes")
657 (set_attr "type" "farith")]
658)
659
660(define_insn "*muldf3_vfp"
661 [(set (match_operand:DF 0 "s_register_operand" "+w")
662 (mult:DF (match_operand:DF 1 "s_register_operand" "w")
663 (match_operand:DF 2 "s_register_operand" "w")))]
5b3e6663 664 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 665 "fmuld%?\\t%P0, %P1, %P2"
666 [(set_attr "predicable" "yes")
667 (set_attr "type" "fmul")]
668)
669
670
671(define_insn "*mulsf3negsf_vfp"
f1adb0a9
JB		 672 [(set (match_operand:SF 0 "s_register_operand" "+t")
673 (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
674 (match_operand:SF 2 "s_register_operand" "t")))]
5b3e6663 675 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 676 "fnmuls%?\\t%0, %1, %2"
677 [(set_attr "predicable" "yes")
678 (set_attr "type" "farith")]
679)
680
681(define_insn "*muldf3negdf_vfp"
682 [(set (match_operand:DF 0 "s_register_operand" "+w")
683 (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
684 (match_operand:DF 2 "s_register_operand" "w")))]
5b3e6663 685 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 686 "fnmuld%?\\t%P0, %P1, %P2"
687 [(set_attr "predicable" "yes")
688 (set_attr "type" "fmul")]
689)
690
691
692;; Multiply-accumulate insns
693
694;; 0 = 1 * 2 + 0
695(define_insn "*mulsf3addsf_vfp"
f1adb0a9
JB		 696 [(set (match_operand:SF 0 "s_register_operand" "=t")
697 (plus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
698 (match_operand:SF 3 "s_register_operand" "t"))
9b66ebb1 699 (match_operand:SF 1 "s_register_operand" "0")))]
5b3e6663 700 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 701 "fmacs%?\\t%0, %2, %3"
702 [(set_attr "predicable" "yes")
703 (set_attr "type" "farith")]
704)
705
706(define_insn "*muldf3adddf_vfp"
707 [(set (match_operand:DF 0 "s_register_operand" "=w")
708 (plus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
709 (match_operand:DF 3 "s_register_operand" "w"))
710 (match_operand:DF 1 "s_register_operand" "0")))]
5b3e6663 711 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 712 "fmacd%?\\t%P0, %P2, %P3"
713 [(set_attr "predicable" "yes")
714 (set_attr "type" "fmul")]
715)
716
717;; 0 = 1 * 2 - 0
718(define_insn "*mulsf3subsf_vfp"
f1adb0a9
JB		 719 [(set (match_operand:SF 0 "s_register_operand" "=t")
720 (minus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
721 (match_operand:SF 3 "s_register_operand" "t"))
9b66ebb1 722 (match_operand:SF 1 "s_register_operand" "0")))]
5b3e6663 723 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 724 "fmscs%?\\t%0, %2, %3"
725 [(set_attr "predicable" "yes")
726 (set_attr "type" "farith")]
727)
728
729(define_insn "*muldf3subdf_vfp"
730 [(set (match_operand:DF 0 "s_register_operand" "=w")
731 (minus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
732 (match_operand:DF 3 "s_register_operand" "w"))
733 (match_operand:DF 1 "s_register_operand" "0")))]
5b3e6663 734 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 735 "fmscd%?\\t%P0, %P2, %P3"
736 [(set_attr "predicable" "yes")
737 (set_attr "type" "fmul")]
738)
739
740;; 0 = -(1 * 2) + 0
741(define_insn "*mulsf3negsfaddsf_vfp"
f1adb0a9 742 [(set (match_operand:SF 0 "s_register_operand" "=t")
9b66ebb1 743 (minus:SF (match_operand:SF 1 "s_register_operand" "0")
f1adb0a9
JB		 744 (mult:SF (match_operand:SF 2 "s_register_operand" "t")
745 (match_operand:SF 3 "s_register_operand" "t"))))]
5b3e6663 746 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 747 "fnmacs%?\\t%0, %2, %3"
748 [(set_attr "predicable" "yes")
749 (set_attr "type" "farith")]
750)
751
752(define_insn "*fmuldf3negdfadddf_vfp"
753 [(set (match_operand:DF 0 "s_register_operand" "=w")
754 (minus:DF (match_operand:DF 1 "s_register_operand" "0")
755 (mult:DF (match_operand:DF 2 "s_register_operand" "w")
756 (match_operand:DF 3 "s_register_operand" "w"))))]
5b3e6663 757 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 758 "fnmacd%?\\t%P0, %P2, %P3"
759 [(set_attr "predicable" "yes")
760 (set_attr "type" "fmul")]
761)
762
763
764;; 0 = -(1 * 2) - 0
765(define_insn "*mulsf3negsfsubsf_vfp"
f1adb0a9 766 [(set (match_operand:SF 0 "s_register_operand" "=t")
9b66ebb1 767 (minus:SF (mult:SF
f1adb0a9
JB		 768 (neg:SF (match_operand:SF 2 "s_register_operand" "t"))
769 (match_operand:SF 3 "s_register_operand" "t"))
9b66ebb1 770 (match_operand:SF 1 "s_register_operand" "0")))]
5b3e6663 771 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 772 "fnmscs%?\\t%0, %2, %3"
773 [(set_attr "predicable" "yes")
774 (set_attr "type" "farith")]
775)
776
777(define_insn "*muldf3negdfsubdf_vfp"
778 [(set (match_operand:DF 0 "s_register_operand" "=w")
779 (minus:DF (mult:DF
780 (neg:DF (match_operand:DF 2 "s_register_operand" "w"))
781 (match_operand:DF 3 "s_register_operand" "w"))
782 (match_operand:DF 1 "s_register_operand" "0")))]
5b3e6663 783 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 784 "fnmscd%?\\t%P0, %P2, %P3"
785 [(set_attr "predicable" "yes")
786 (set_attr "type" "fmul")]
787)
788
789
790;; Conversion routines
791
792(define_insn "*extendsfdf2_vfp"
793 [(set (match_operand:DF 0 "s_register_operand" "=w")
f1adb0a9 794 (float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))]
5b3e6663 795 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 796 "fcvtds%?\\t%P0, %1"
797 [(set_attr "predicable" "yes")
75fe7b2f 798 (set_attr "type" "f_cvt")]
9b66ebb1
PB		 799)
800
801(define_insn "*truncdfsf2_vfp"
f1adb0a9 802 [(set (match_operand:SF 0 "s_register_operand" "=t")
9b66ebb1 803 (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))]
5b3e6663 804 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 805 "fcvtsd%?\\t%0, %P1"
806 [(set_attr "predicable" "yes")
75fe7b2f 807 (set_attr "type" "f_cvt")]
9b66ebb1
PB		 808)
809
810(define_insn "*truncsisf2_vfp"
f1adb0a9
JB		 811 [(set (match_operand:SI 0 "s_register_operand" "=t")
812 (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
5b3e6663 813 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 814 "ftosizs%?\\t%0, %1"
815 [(set_attr "predicable" "yes")
75fe7b2f 816 (set_attr "type" "f_cvt")]
9b66ebb1
PB		 817)
818
819(define_insn "*truncsidf2_vfp"
f1adb0a9 820 [(set (match_operand:SI 0 "s_register_operand" "=t")
9b66ebb1 821 (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))]
5b3e6663 822 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 823 "ftosizd%?\\t%0, %P1"
824 [(set_attr "predicable" "yes")
75fe7b2f 825 (set_attr "type" "f_cvt")]
9b66ebb1
PB		 826)
827
6f6c1f6d
PB		 828
829(define_insn "fixuns_truncsfsi2"
f1adb0a9
JB		 830 [(set (match_operand:SI 0 "s_register_operand" "=t")
831 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
5b3e6663 832 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
6f6c1f6d
PB		 833 "ftouizs%?\\t%0, %1"
834 [(set_attr "predicable" "yes")
75fe7b2f 835 (set_attr "type" "f_cvt")]
6f6c1f6d
PB		 836)
837
838(define_insn "fixuns_truncdfsi2"
f1adb0a9
JB		 839 [(set (match_operand:SI 0 "s_register_operand" "=t")
840 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))]
5b3e6663 841 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
6f6c1f6d
PB		 842 "ftouizd%?\\t%0, %P1"
843 [(set_attr "predicable" "yes")
75fe7b2f 844 (set_attr "type" "f_cvt")]
6f6c1f6d
PB		 845)
846
847
9b66ebb1 848(define_insn "*floatsisf2_vfp"
f1adb0a9
JB		 849 [(set (match_operand:SF 0 "s_register_operand" "=t")
850 (float:SF (match_operand:SI 1 "s_register_operand" "t")))]
5b3e6663 851 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 852 "fsitos%?\\t%0, %1"
853 [(set_attr "predicable" "yes")
75fe7b2f 854 (set_attr "type" "f_cvt")]
9b66ebb1
PB		 855)
856
857(define_insn "*floatsidf2_vfp"
858 [(set (match_operand:DF 0 "s_register_operand" "=w")
f1adb0a9 859 (float:DF (match_operand:SI 1 "s_register_operand" "t")))]
5b3e6663 860 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 861 "fsitod%?\\t%P0, %1"
862 [(set_attr "predicable" "yes")
75fe7b2f 863 (set_attr "type" "f_cvt")]
9b66ebb1
PB		 864)
865
866
6f6c1f6d 867(define_insn "floatunssisf2"
f1adb0a9
JB		 868 [(set (match_operand:SF 0 "s_register_operand" "=t")
869 (unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))]
5b3e6663 870 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
6f6c1f6d
PB		 871 "fuitos%?\\t%0, %1"
872 [(set_attr "predicable" "yes")
75fe7b2f 873 (set_attr "type" "f_cvt")]
6f6c1f6d
PB		 874)
875
876(define_insn "floatunssidf2"
877 [(set (match_operand:DF 0 "s_register_operand" "=w")
f1adb0a9 878 (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))]
5b3e6663 879 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
6f6c1f6d
PB		 880 "fuitod%?\\t%P0, %1"
881 [(set_attr "predicable" "yes")
75fe7b2f 882 (set_attr "type" "f_cvt")]
6f6c1f6d
PB		 883)
884
885
9b66ebb1
PB		 886;; Sqrt insns.
887
888(define_insn "*sqrtsf2_vfp"
f1adb0a9
JB		 889 [(set (match_operand:SF 0 "s_register_operand" "=t")
890 (sqrt:SF (match_operand:SF 1 "s_register_operand" "t")))]
5b3e6663 891 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 892 "fsqrts%?\\t%0, %1"
893 [(set_attr "predicable" "yes")
894 (set_attr "type" "fdivs")]
895)
896
897(define_insn "*sqrtdf2_vfp"
898 [(set (match_operand:DF 0 "s_register_operand" "=w")
899 (sqrt:DF (match_operand:DF 1 "s_register_operand" "w")))]
5b3e6663 900 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 901 "fsqrtd%?\\t%P0, %P1"
902 [(set_attr "predicable" "yes")
903 (set_attr "type" "fdivd")]
904)
905
906
907;; Patterns to split/copy vfp condition flags.
908
909(define_insn "*movcc_vfp"
910 [(set (reg CC_REGNUM)
911 (reg VFPCC_REGNUM))]
5b3e6663 912 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 913 "fmstat%?"
914 [(set_attr "conds" "set")
75fe7b2f 915 (set_attr "type" "f_flag")]
9b66ebb1
PB		 916)
917
918(define_insn_and_split "*cmpsf_split_vfp"
919 [(set (reg:CCFP CC_REGNUM)
f1adb0a9
JB		 920 (compare:CCFP (match_operand:SF 0 "s_register_operand" "t")
921 (match_operand:SF 1 "vfp_compare_operand" "tG")))]
5b3e6663 922 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1 923 "#"
5b3e6663 924 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 925 [(set (reg:CCFP VFPCC_REGNUM)
926 (compare:CCFP (match_dup 0)
927 (match_dup 1)))
928 (set (reg:CCFP CC_REGNUM)
929 (reg:CCFP VFPCC_REGNUM))]
930 ""
931)
932
933(define_insn_and_split "*cmpsf_trap_split_vfp"
934 [(set (reg:CCFPE CC_REGNUM)
f1adb0a9
JB		 935 (compare:CCFPE (match_operand:SF 0 "s_register_operand" "t")
936 (match_operand:SF 1 "vfp_compare_operand" "tG")))]
5b3e6663 937 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1 938 "#"
5b3e6663 939 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 940 [(set (reg:CCFPE VFPCC_REGNUM)
941 (compare:CCFPE (match_dup 0)
942 (match_dup 1)))
943 (set (reg:CCFPE CC_REGNUM)
944 (reg:CCFPE VFPCC_REGNUM))]
945 ""
946)
947
948(define_insn_and_split "*cmpdf_split_vfp"
949 [(set (reg:CCFP CC_REGNUM)
950 (compare:CCFP (match_operand:DF 0 "s_register_operand" "w")
951 (match_operand:DF 1 "vfp_compare_operand" "wG")))]
5b3e6663 952 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1 953 "#"
5b3e6663 954 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 955 [(set (reg:CCFP VFPCC_REGNUM)
956 (compare:CCFP (match_dup 0)
957 (match_dup 1)))
958 (set (reg:CCFP CC_REGNUM)
959 (reg:CCFPE VFPCC_REGNUM))]
960 ""
961)
962
963(define_insn_and_split "*cmpdf_trap_split_vfp"
964 [(set (reg:CCFPE CC_REGNUM)
965 (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w")
966 (match_operand:DF 1 "vfp_compare_operand" "wG")))]
5b3e6663 967 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1 968 "#"
5b3e6663 969 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 970 [(set (reg:CCFPE VFPCC_REGNUM)
971 (compare:CCFPE (match_dup 0)
972 (match_dup 1)))
973 (set (reg:CCFPE CC_REGNUM)
974 (reg:CCFPE VFPCC_REGNUM))]
975 ""
976)
977
978
979;; Comparison patterns
980
981(define_insn "*cmpsf_vfp"
982 [(set (reg:CCFP VFPCC_REGNUM)
f1adb0a9
JB		 983 (compare:CCFP (match_operand:SF 0 "s_register_operand" "t,t")
984 (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
5b3e6663 985 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 986 "@
987 fcmps%?\\t%0, %1
988 fcmpzs%?\\t%0"
989 [(set_attr "predicable" "yes")
990 (set_attr "type" "ffarith")]
991)
992
993(define_insn "*cmpsf_trap_vfp"
994 [(set (reg:CCFPE VFPCC_REGNUM)
f1adb0a9
JB		 995 (compare:CCFPE (match_operand:SF 0 "s_register_operand" "t,t")
996 (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
5b3e6663 997 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 998 "@
999 fcmpes%?\\t%0, %1
1000 fcmpezs%?\\t%0"
1001 [(set_attr "predicable" "yes")
1002 (set_attr "type" "ffarith")]
1003)
1004
1005(define_insn "*cmpdf_vfp"
1006 [(set (reg:CCFP VFPCC_REGNUM)
1007 (compare:CCFP (match_operand:DF 0 "s_register_operand" "w,w")
1008 (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
5b3e6663 1009 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 1010 "@
1011 fcmpd%?\\t%P0, %P1
1012 fcmpzd%?\\t%P0"
1013 [(set_attr "predicable" "yes")
1014 (set_attr "type" "ffarith")]
1015)
1016
1017(define_insn "*cmpdf_trap_vfp"
1018 [(set (reg:CCFPE VFPCC_REGNUM)
1019 (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w,w")
1020 (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
5b3e6663 1021 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
9b66ebb1
PB		 1022 "@
1023 fcmped%?\\t%P0, %P1
1024 fcmpezd%?\\t%P0"
1025 [(set_attr "predicable" "yes")
1026 (set_attr "type" "ffarith")]
1027)
1028
1029
1030;; Store multiple insn used in function prologue.
1031
1032(define_insn "*push_multi_vfp"
1033 [(match_parallel 2 "multi_register_push"
1034 [(set (match_operand:BLK 0 "memory_operand" "=m")
1035 (unspec:BLK [(match_operand:DF 1 "s_register_operand" "w")]
1036 UNSPEC_PUSH_MULT))])]
5b3e6663 1037 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
8edfc4cc 1038 "* return vfp_output_fstmd (operands);"
75fe7b2f 1039 [(set_attr "type" "f_stored")]
9b66ebb1
PB		 1040)
1041
1042
1043;; Unimplemented insns:
1044;; fldm*
1045;; fstm*
1046;; fmdhr et al (VFPv1)
59b9a953 1047;; Support for xD (single precision only) variants.
9b66ebb1 1048;; fmrrs, fmsrr
Mirror of https://gcc.gnu.org/git/gcc.git