]>
Commit | Line | Data |
---|---|---|
1dbb006a | 1 | /* Definitions of types that are used to store AVR architecture and |
2 | device information. | |
fbd26352 | 3 | Copyright (C) 2012-2019 Free Software Foundation, Inc. |
1dbb006a | 4 | Contributed by Georg-Johann Lay (avr@gjlay.de) |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GCC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
21 | ||
c0d7a1d0 | 22 | #ifndef AVR_ARCH_H |
23 | #define AVR_ARCH_H | |
1dbb006a | 24 | |
f0aa7fe2 | 25 | #define AVR_MMCU_DEFAULT "avr2" |
26 | ||
1dbb006a | 27 | /* This enum supplies indices into the avr_arch_types[] table below. */ |
28 | ||
f0aa7fe2 | 29 | enum avr_arch_id |
1dbb006a | 30 | { |
31 | ARCH_UNKNOWN, | |
32 | ARCH_AVR1, | |
33 | ARCH_AVR2, | |
34 | ARCH_AVR25, | |
35 | ARCH_AVR3, | |
36 | ARCH_AVR31, | |
37 | ARCH_AVR35, | |
38 | ARCH_AVR4, | |
39 | ARCH_AVR5, | |
40 | ARCH_AVR51, | |
41 | ARCH_AVR6, | |
b4e6d2e2 | 42 | ARCH_AVRTINY, |
1dbb006a | 43 | ARCH_AVRXMEGA2, |
02bfce13 | 44 | ARCH_AVRXMEGA3, |
1dbb006a | 45 | ARCH_AVRXMEGA4, |
46 | ARCH_AVRXMEGA5, | |
47 | ARCH_AVRXMEGA6, | |
48 | ARCH_AVRXMEGA7 | |
49 | }; | |
50 | ||
51 | ||
52 | /* Architecture-specific properties. */ | |
53 | ||
ce544647 | 54 | typedef struct |
1dbb006a | 55 | { |
56 | /* Assembler only. */ | |
57 | int asm_only; | |
58 | ||
59 | /* Core have 'MUL*' instructions. */ | |
60 | int have_mul; | |
61 | ||
62 | /* Core have 'CALL' and 'JMP' instructions. */ | |
63 | int have_jmp_call; | |
64 | ||
65 | /* Core have 'MOVW' and 'LPM Rx,Z' instructions. */ | |
66 | int have_movw_lpmx; | |
67 | ||
68 | /* Core have 'ELPM' instructions. */ | |
69 | int have_elpm; | |
70 | ||
71 | /* Core have 'ELPM Rx,Z' instructions. */ | |
72 | int have_elpmx; | |
73 | ||
74 | /* Core have 'EICALL' and 'EIJMP' instructions. */ | |
75 | int have_eijmp_eicall; | |
76 | ||
77 | /* This is an XMEGA core. */ | |
78 | int xmega_p; | |
79 | ||
80 | /* This core has the RAMPD special function register | |
81 | and thus also the RAMPX, RAMPY and RAMPZ registers. */ | |
82 | int have_rampd; | |
0dff9558 | 83 | |
b4e6d2e2 | 84 | /* This is a TINY core. */ |
85 | int tiny_p; | |
86 | ||
1dbb006a | 87 | /* Default start of data section address for architecture. */ |
88 | int default_data_section_start; | |
89 | ||
02bfce13 | 90 | /* Offset where flash memory is seen in RAM address range or 0. */ |
91 | int flash_pm_offset; | |
92 | ||
1dbb006a | 93 | /* Offset between SFR address and RAM address: |
94 | SFR-address = RAM-address - sfr_offset */ | |
95 | int sfr_offset; | |
96 | ||
97 | /* Architecture id to built-in define __AVR_ARCH__ (NULL -> no macro) */ | |
98 | const char *const macro; | |
0dff9558 | 99 | |
1dbb006a | 100 | /* Architecture name. */ |
f0aa7fe2 | 101 | const char *const name; |
ce544647 | 102 | } avr_arch_t; |
1dbb006a | 103 | |
104 | ||
105 | /* Device-specific properties. */ | |
106 | ||
ce544647 | 107 | typedef struct |
1dbb006a | 108 | { |
109 | /* Device name. */ | |
110 | const char *const name; | |
0dff9558 | 111 | |
1dbb006a | 112 | /* Index in avr_arch_types[]. */ |
f0aa7fe2 | 113 | enum avr_arch_id arch_id; |
0dff9558 | 114 | |
976c7653 | 115 | /* device specific feature */ |
116 | int dev_attribute; | |
117 | ||
1dbb006a | 118 | /* Must lie outside user's namespace. NULL == no macro. */ |
119 | const char *const macro; | |
0dff9558 | 120 | |
1dbb006a | 121 | /* Start of data section. */ |
122 | int data_section_start; | |
0dff9558 | 123 | |
d86b94f3 | 124 | /* Start of text section. */ |
125 | int text_section_start; | |
126 | ||
0effb377 | 127 | /* Flash size in bytes. */ |
128 | int flash_size; | |
ce544647 | 129 | } avr_mcu_t; |
1dbb006a | 130 | |
976c7653 | 131 | /* AVR device specific features. |
132 | ||
133 | AVR_ISA_RMW | |
134 | Only few avr devices have Read-Modify-Write (RMW) instructions | |
135 | (XCH, LAC, LAS and LAT) | |
136 | ||
137 | AVR_SHORT_SP | |
138 | Stack Pointer has only 8 bit width. | |
139 | The device / multilib has an 8-bit stack pointer (no SPH). | |
140 | ||
141 | AVR_ERRATA_SKIP | |
142 | Some AVR devices have a core erratum when skipping a 2-word instruction. | |
143 | Skip instructions are: SBRC, SBRS, SBIC, SBIS, CPSE. | |
144 | Problems will occur with return address is IRQ executes during the | |
145 | skip sequence. | |
146 | ||
147 | A support ticket from Atmel returned the following information: | |
148 | ||
149 | Subject: (ATTicket:644469) On AVR skip-bug core Erratum | |
150 | From: avr@atmel.com Date: 2011-07-27 | |
151 | (Please keep the subject when replying to this mail) | |
152 | ||
153 | This errata exists only in AT90S8515 and ATmega103 devices. | |
154 | ||
155 | For information please refer the following respective errata links | |
156 | http://www.atmel.com/dyn/resources/prod_documents/doc2494.pdf | |
02bfce13 | 157 | http://www.atmel.com/dyn/resources/prod_documents/doc1436.pdf |
158 | ||
159 | AVR_ISA_RCALL | |
160 | Always use RJMP / RCALL and assume JMP / CALL are not available. | |
161 | This affects multilib selection via specs generation and -mshort-calls. | |
162 | Even if a device like ATtiny417 from avrxmega3 supports JMP / CALL, we | |
163 | assume these instructions are not available and we set the built-in | |
164 | macro __AVR_HAVE_JMP_CALL__ accordingly. This macro is used to | |
165 | determine a rough estimate of flash size in libgcc, and AVR-LibC uses | |
166 | this macro to determine vector sizes. */ | |
976c7653 | 167 | |
168 | enum avr_device_specific_features | |
169 | { | |
170 | AVR_ISA_NONE, | |
171 | AVR_ISA_RMW = 0x1, /* device has RMW instructions. */ | |
172 | AVR_SHORT_SP = 0x2, /* Stack Pointer has 8 bits width. */ | |
3f1786fa | 173 | AVR_ERRATA_SKIP = 0x4, /* device has a core erratum. */ |
02bfce13 | 174 | AVR_ISA_LDS = 0x8, /* whether LDS / STS is valid for all data in static |
3f1786fa | 175 | storage. Only useful for reduced Tiny. */ |
02bfce13 | 176 | AVR_ISA_RCALL = 0x10 /* Use RJMP / RCALL even though JMP / CALL |
177 | are available (-mshort-calls). */ | |
976c7653 | 178 | }; |
179 | ||
1dbb006a | 180 | /* Map architecture to its texinfo string. */ |
181 | ||
ce544647 | 182 | typedef struct |
1dbb006a | 183 | { |
184 | /* Architecture ID. */ | |
f0aa7fe2 | 185 | enum avr_arch_id arch_id; |
1dbb006a | 186 | |
2fbe7a32 | 187 | /* textinfo source to describe the architecture. */ |
1dbb006a | 188 | const char *texinfo; |
ce544647 | 189 | } avr_arch_info_t; |
1dbb006a | 190 | |
191 | /* Preprocessor macros to define depending on MCU type. */ | |
192 | ||
ce544647 | 193 | extern const avr_arch_t avr_arch_types[]; |
f0aa7fe2 | 194 | extern const avr_arch_t *avr_arch; |
ce544647 | 195 | |
196 | extern const avr_mcu_t avr_mcu_types[]; | |
f0aa7fe2 | 197 | |
f0aa7fe2 | 198 | extern void avr_inform_core_architectures (void); |
c0d7a1d0 | 199 | |
200 | #endif /* AVR_ARCH_H */ |