]>
Commit | Line | Data |
---|---|---|
fe24f256 | 1 | /* The Blackfin code generation auxiliary output file. |
fba5dd52 | 2 | Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010, 2011 |
7cf0dbf3 | 3 | Free Software Foundation, Inc. |
9e6a0967 | 4 | Contributed by Analog Devices. |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify it | |
9 | under the terms of the GNU General Public License as published | |
038d1e19 | 10 | by the Free Software Foundation; either version 3, or (at your |
9e6a0967 | 11 | option) any later version. |
12 | ||
13 | GCC is distributed in the hope that it will be useful, but WITHOUT | |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
038d1e19 | 19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
9e6a0967 | 21 | |
22 | #include "config.h" | |
23 | #include "system.h" | |
24 | #include "coretypes.h" | |
25 | #include "tm.h" | |
26 | #include "rtl.h" | |
27 | #include "regs.h" | |
28 | #include "hard-reg-set.h" | |
9e6a0967 | 29 | #include "insn-config.h" |
b00f0d99 | 30 | #include "insn-codes.h" |
9e6a0967 | 31 | #include "conditions.h" |
32 | #include "insn-flags.h" | |
33 | #include "output.h" | |
34 | #include "insn-attr.h" | |
35 | #include "tree.h" | |
36 | #include "flags.h" | |
37 | #include "except.h" | |
38 | #include "function.h" | |
39 | #include "input.h" | |
40 | #include "target.h" | |
41 | #include "target-def.h" | |
42 | #include "expr.h" | |
0b205f4c | 43 | #include "diagnostic-core.h" |
9e6a0967 | 44 | #include "recog.h" |
f9edc33d | 45 | #include "optabs.h" |
9e6a0967 | 46 | #include "ggc.h" |
47 | #include "integrate.h" | |
70d893c7 | 48 | #include "cgraph.h" |
684389d2 | 49 | #include "langhooks.h" |
9e6a0967 | 50 | #include "bfin-protos.h" |
51 | #include "tm-preds.h" | |
87943377 | 52 | #include "tm-constrs.h" |
9e6a0967 | 53 | #include "gt-bfin.h" |
3c1905a4 | 54 | #include "basic-block.h" |
917c4036 | 55 | #include "cfglayout.h" |
48df5a7f | 56 | #include "timevar.h" |
d18119ae | 57 | #include "df.h" |
95f13934 | 58 | #include "sel-sched.h" |
fba5dd52 | 59 | #include "opts.h" |
3c1905a4 | 60 | |
61 | /* A C structure for machine-specific, per-function data. | |
62 | This is added to the cfun structure. */ | |
fb1e4f4a | 63 | struct GTY(()) machine_function |
3c1905a4 | 64 | { |
4cf41453 | 65 | /* Set if we are notified by the doloop pass that a hardware loop |
66 | was created. */ | |
3c1905a4 | 67 | int has_hardware_loops; |
4bb5cea5 | 68 | |
4cf41453 | 69 | /* Set if we create a memcpy pattern that uses loop registers. */ |
70 | int has_loopreg_clobber; | |
3c1905a4 | 71 | }; |
9e6a0967 | 72 | |
9e6a0967 | 73 | /* RTX for condition code flag register and RETS register */ |
74 | extern GTY(()) rtx bfin_cc_rtx; | |
75 | extern GTY(()) rtx bfin_rets_rtx; | |
76 | rtx bfin_cc_rtx, bfin_rets_rtx; | |
77 | ||
78 | int max_arg_registers = 0; | |
79 | ||
80 | /* Arrays used when emitting register names. */ | |
81 | const char *short_reg_names[] = SHORT_REGISTER_NAMES; | |
82 | const char *high_reg_names[] = HIGH_REGISTER_NAMES; | |
83 | const char *dregs_pair_names[] = DREGS_PAIR_NAMES; | |
84 | const char *byte_reg_names[] = BYTE_REGISTER_NAMES; | |
85 | ||
86 | static int arg_regs[] = FUNCTION_ARG_REGISTERS; | |
4bb5cea5 | 87 | static int ret_regs[] = FUNCTION_RETURN_REGISTERS; |
9e6a0967 | 88 | |
0fead507 | 89 | int splitting_for_sched, splitting_loops; |
48df5a7f | 90 | |
9e6a0967 | 91 | static void |
92 | bfin_globalize_label (FILE *stream, const char *name) | |
93 | { | |
94 | fputs (".global ", stream); | |
95 | assemble_name (stream, name); | |
96 | fputc (';',stream); | |
97 | fputc ('\n',stream); | |
98 | } | |
99 | ||
100 | static void | |
101 | output_file_start (void) | |
102 | { | |
103 | FILE *file = asm_out_file; | |
104 | int i; | |
105 | ||
106 | fprintf (file, ".file \"%s\";\n", input_filename); | |
107 | ||
108 | for (i = 0; arg_regs[i] >= 0; i++) | |
109 | ; | |
110 | max_arg_registers = i; /* how many arg reg used */ | |
111 | } | |
112 | ||
9e6a0967 | 113 | /* Examine machine-dependent attributes of function type FUNTYPE and return its |
114 | type. See the definition of E_FUNKIND. */ | |
115 | ||
a9f1838b | 116 | static e_funkind |
117 | funkind (const_tree funtype) | |
9e6a0967 | 118 | { |
119 | tree attrs = TYPE_ATTRIBUTES (funtype); | |
120 | if (lookup_attribute ("interrupt_handler", attrs)) | |
121 | return INTERRUPT_HANDLER; | |
122 | else if (lookup_attribute ("exception_handler", attrs)) | |
123 | return EXCPT_HANDLER; | |
124 | else if (lookup_attribute ("nmi_handler", attrs)) | |
125 | return NMI_HANDLER; | |
126 | else | |
127 | return SUBROUTINE; | |
128 | } | |
129 | \f | |
b90ce3c3 | 130 | /* Legitimize PIC addresses. If the address is already position-independent, |
131 | we return ORIG. Newly generated position-independent addresses go into a | |
132 | reg. This is REG if nonzero, otherwise we allocate register(s) as | |
133 | necessary. PICREG is the register holding the pointer to the PIC offset | |
134 | table. */ | |
135 | ||
55be0e32 | 136 | static rtx |
b90ce3c3 | 137 | legitimize_pic_address (rtx orig, rtx reg, rtx picreg) |
138 | { | |
139 | rtx addr = orig; | |
8deb3959 | 140 | rtx new_rtx = orig; |
b90ce3c3 | 141 | |
142 | if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF) | |
143 | { | |
e80283bd | 144 | int unspec; |
145 | rtx tmp; | |
146 | ||
147 | if (TARGET_ID_SHARED_LIBRARY) | |
148 | unspec = UNSPEC_MOVE_PIC; | |
149 | else if (GET_CODE (addr) == SYMBOL_REF | |
150 | && SYMBOL_REF_FUNCTION_P (addr)) | |
151 | unspec = UNSPEC_FUNCDESC_GOT17M4; | |
b90ce3c3 | 152 | else |
e80283bd | 153 | unspec = UNSPEC_MOVE_FDPIC; |
154 | ||
155 | if (reg == 0) | |
b90ce3c3 | 156 | { |
e1ba4a27 | 157 | gcc_assert (can_create_pseudo_p ()); |
e80283bd | 158 | reg = gen_reg_rtx (Pmode); |
b90ce3c3 | 159 | } |
e80283bd | 160 | |
161 | tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), unspec); | |
8deb3959 | 162 | new_rtx = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, picreg, tmp)); |
e80283bd | 163 | |
8deb3959 | 164 | emit_move_insn (reg, new_rtx); |
b90ce3c3 | 165 | if (picreg == pic_offset_table_rtx) |
18d50ae6 | 166 | crtl->uses_pic_offset_table = 1; |
b90ce3c3 | 167 | return reg; |
168 | } | |
169 | ||
170 | else if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS) | |
171 | { | |
172 | rtx base; | |
173 | ||
174 | if (GET_CODE (addr) == CONST) | |
175 | { | |
176 | addr = XEXP (addr, 0); | |
177 | gcc_assert (GET_CODE (addr) == PLUS); | |
178 | } | |
179 | ||
180 | if (XEXP (addr, 0) == picreg) | |
181 | return orig; | |
182 | ||
183 | if (reg == 0) | |
184 | { | |
e1ba4a27 | 185 | gcc_assert (can_create_pseudo_p ()); |
b90ce3c3 | 186 | reg = gen_reg_rtx (Pmode); |
187 | } | |
188 | ||
189 | base = legitimize_pic_address (XEXP (addr, 0), reg, picreg); | |
190 | addr = legitimize_pic_address (XEXP (addr, 1), | |
191 | base == reg ? NULL_RTX : reg, | |
192 | picreg); | |
193 | ||
194 | if (GET_CODE (addr) == CONST_INT) | |
195 | { | |
196 | gcc_assert (! reload_in_progress && ! reload_completed); | |
197 | addr = force_reg (Pmode, addr); | |
198 | } | |
199 | ||
200 | if (GET_CODE (addr) == PLUS && CONSTANT_P (XEXP (addr, 1))) | |
201 | { | |
202 | base = gen_rtx_PLUS (Pmode, base, XEXP (addr, 0)); | |
203 | addr = XEXP (addr, 1); | |
204 | } | |
205 | ||
206 | return gen_rtx_PLUS (Pmode, base, addr); | |
207 | } | |
208 | ||
8deb3959 | 209 | return new_rtx; |
b90ce3c3 | 210 | } |
211 | \f | |
9e6a0967 | 212 | /* Stack frame layout. */ |
213 | ||
29b085dc | 214 | /* For a given REGNO, determine whether it must be saved in the function |
215 | prologue. IS_INTHANDLER specifies whether we're generating a normal | |
216 | prologue or an interrupt/exception one. */ | |
217 | static bool | |
218 | must_save_p (bool is_inthandler, unsigned regno) | |
9e6a0967 | 219 | { |
29b085dc | 220 | if (D_REGNO_P (regno)) |
9e6a0967 | 221 | { |
29b085dc | 222 | bool is_eh_return_reg = false; |
18d50ae6 | 223 | if (crtl->calls_eh_return) |
9e6a0967 | 224 | { |
225 | unsigned j; | |
226 | for (j = 0; ; j++) | |
227 | { | |
228 | unsigned test = EH_RETURN_DATA_REGNO (j); | |
229 | if (test == INVALID_REGNUM) | |
230 | break; | |
29b085dc | 231 | if (test == regno) |
232 | is_eh_return_reg = true; | |
9e6a0967 | 233 | } |
234 | } | |
235 | ||
29b085dc | 236 | return (is_eh_return_reg |
237 | || (df_regs_ever_live_p (regno) | |
238 | && !fixed_regs[regno] | |
239 | && (is_inthandler || !call_used_regs[regno]))); | |
9e6a0967 | 240 | } |
29b085dc | 241 | else if (P_REGNO_P (regno)) |
242 | { | |
243 | return ((df_regs_ever_live_p (regno) | |
244 | && !fixed_regs[regno] | |
245 | && (is_inthandler || !call_used_regs[regno])) | |
b43b7954 | 246 | || (is_inthandler |
247 | && (ENABLE_WA_05000283 || ENABLE_WA_05000315) | |
248 | && regno == REG_P5) | |
29b085dc | 249 | || (!TARGET_FDPIC |
250 | && regno == PIC_OFFSET_TABLE_REGNUM | |
18d50ae6 | 251 | && (crtl->uses_pic_offset_table |
29b085dc | 252 | || (TARGET_ID_SHARED_LIBRARY && !current_function_is_leaf)))); |
253 | } | |
254 | else | |
255 | return ((is_inthandler || !call_used_regs[regno]) | |
256 | && (df_regs_ever_live_p (regno) | |
257 | || (!leaf_function_p () && call_used_regs[regno]))); | |
258 | ||
259 | } | |
260 | ||
261 | /* Compute the number of DREGS to save with a push_multiple operation. | |
262 | This could include registers that aren't modified in the function, | |
263 | since push_multiple only takes a range of registers. | |
264 | If IS_INTHANDLER, then everything that is live must be saved, even | |
265 | if normally call-clobbered. | |
266 | If CONSECUTIVE, return the number of registers we can save in one | |
267 | instruction with a push/pop multiple instruction. */ | |
268 | ||
269 | static int | |
270 | n_dregs_to_save (bool is_inthandler, bool consecutive) | |
271 | { | |
272 | int count = 0; | |
273 | unsigned i; | |
274 | ||
275 | for (i = REG_R7 + 1; i-- != REG_R0;) | |
276 | { | |
277 | if (must_save_p (is_inthandler, i)) | |
278 | count++; | |
279 | else if (consecutive) | |
280 | return count; | |
281 | } | |
282 | return count; | |
9e6a0967 | 283 | } |
284 | ||
285 | /* Like n_dregs_to_save, but compute number of PREGS to save. */ | |
286 | ||
287 | static int | |
29b085dc | 288 | n_pregs_to_save (bool is_inthandler, bool consecutive) |
9e6a0967 | 289 | { |
29b085dc | 290 | int count = 0; |
9e6a0967 | 291 | unsigned i; |
292 | ||
29b085dc | 293 | for (i = REG_P5 + 1; i-- != REG_P0;) |
294 | if (must_save_p (is_inthandler, i)) | |
295 | count++; | |
296 | else if (consecutive) | |
297 | return count; | |
298 | return count; | |
9e6a0967 | 299 | } |
300 | ||
301 | /* Determine if we are going to save the frame pointer in the prologue. */ | |
302 | ||
303 | static bool | |
304 | must_save_fp_p (void) | |
305 | { | |
4bb5cea5 | 306 | return df_regs_ever_live_p (REG_FP); |
307 | } | |
308 | ||
309 | /* Determine if we are going to save the RETS register. */ | |
310 | static bool | |
311 | must_save_rets_p (void) | |
312 | { | |
313 | return df_regs_ever_live_p (REG_RETS); | |
9e6a0967 | 314 | } |
315 | ||
316 | static bool | |
317 | stack_frame_needed_p (void) | |
318 | { | |
319 | /* EH return puts a new return address into the frame using an | |
320 | address relative to the frame pointer. */ | |
18d50ae6 | 321 | if (crtl->calls_eh_return) |
9e6a0967 | 322 | return true; |
323 | return frame_pointer_needed; | |
324 | } | |
325 | ||
326 | /* Emit code to save registers in the prologue. SAVEALL is nonzero if we | |
327 | must save all registers; this is used for interrupt handlers. | |
345458f3 | 328 | SPREG contains (reg:SI REG_SP). IS_INTHANDLER is true if we're doing |
329 | this for an interrupt (or exception) handler. */ | |
9e6a0967 | 330 | |
331 | static void | |
345458f3 | 332 | expand_prologue_reg_save (rtx spreg, int saveall, bool is_inthandler) |
9e6a0967 | 333 | { |
49569132 | 334 | rtx predec1 = gen_rtx_PRE_DEC (SImode, spreg); |
335 | rtx predec = gen_rtx_MEM (SImode, predec1); | |
29b085dc | 336 | int ndregs = saveall ? 8 : n_dregs_to_save (is_inthandler, false); |
337 | int npregs = saveall ? 6 : n_pregs_to_save (is_inthandler, false); | |
338 | int ndregs_consec = saveall ? 8 : n_dregs_to_save (is_inthandler, true); | |
339 | int npregs_consec = saveall ? 6 : n_pregs_to_save (is_inthandler, true); | |
340 | int dregno, pregno; | |
341 | int total_consec = ndregs_consec + npregs_consec; | |
342 | int i, d_to_save; | |
9e6a0967 | 343 | |
49569132 | 344 | if (saveall || is_inthandler) |
345 | { | |
29b085dc | 346 | rtx insn = emit_move_insn (predec, gen_rtx_REG (SImode, REG_ASTAT)); |
4cf41453 | 347 | |
49569132 | 348 | RTX_FRAME_RELATED_P (insn) = 1; |
b43b7954 | 349 | for (dregno = REG_LT0; dregno <= REG_LB1; dregno++) |
350 | if (! current_function_is_leaf | |
351 | || cfun->machine->has_hardware_loops | |
352 | || cfun->machine->has_loopreg_clobber | |
353 | || (ENABLE_WA_05000257 | |
354 | && (dregno == REG_LC0 || dregno == REG_LC1))) | |
4cf41453 | 355 | { |
356 | insn = emit_move_insn (predec, gen_rtx_REG (SImode, dregno)); | |
357 | RTX_FRAME_RELATED_P (insn) = 1; | |
358 | } | |
49569132 | 359 | } |
360 | ||
29b085dc | 361 | if (total_consec != 0) |
362 | { | |
363 | rtx insn; | |
364 | rtx val = GEN_INT (-total_consec * 4); | |
365 | rtx pat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_consec + 2)); | |
366 | ||
367 | XVECEXP (pat, 0, 0) = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, val), | |
368 | UNSPEC_PUSH_MULTIPLE); | |
369 | XVECEXP (pat, 0, total_consec + 1) = gen_rtx_SET (VOIDmode, spreg, | |
370 | gen_rtx_PLUS (Pmode, | |
371 | spreg, | |
372 | val)); | |
373 | RTX_FRAME_RELATED_P (XVECEXP (pat, 0, total_consec + 1)) = 1; | |
374 | d_to_save = ndregs_consec; | |
375 | dregno = REG_R7 + 1 - ndregs_consec; | |
376 | pregno = REG_P5 + 1 - npregs_consec; | |
377 | for (i = 0; i < total_consec; i++) | |
378 | { | |
379 | rtx memref = gen_rtx_MEM (word_mode, | |
380 | gen_rtx_PLUS (Pmode, spreg, | |
381 | GEN_INT (- i * 4 - 4))); | |
382 | rtx subpat; | |
383 | if (d_to_save > 0) | |
384 | { | |
385 | subpat = gen_rtx_SET (VOIDmode, memref, gen_rtx_REG (word_mode, | |
386 | dregno++)); | |
387 | d_to_save--; | |
388 | } | |
389 | else | |
390 | { | |
391 | subpat = gen_rtx_SET (VOIDmode, memref, gen_rtx_REG (word_mode, | |
392 | pregno++)); | |
393 | } | |
394 | XVECEXP (pat, 0, i + 1) = subpat; | |
395 | RTX_FRAME_RELATED_P (subpat) = 1; | |
396 | } | |
397 | insn = emit_insn (pat); | |
398 | RTX_FRAME_RELATED_P (insn) = 1; | |
399 | } | |
9e6a0967 | 400 | |
29b085dc | 401 | for (dregno = REG_R0; ndregs != ndregs_consec; dregno++) |
9e6a0967 | 402 | { |
29b085dc | 403 | if (must_save_p (is_inthandler, dregno)) |
9e6a0967 | 404 | { |
29b085dc | 405 | rtx insn = emit_move_insn (predec, gen_rtx_REG (word_mode, dregno)); |
406 | RTX_FRAME_RELATED_P (insn) = 1; | |
9e6a0967 | 407 | ndregs--; |
408 | } | |
29b085dc | 409 | } |
410 | for (pregno = REG_P0; npregs != npregs_consec; pregno++) | |
411 | { | |
412 | if (must_save_p (is_inthandler, pregno)) | |
9e6a0967 | 413 | { |
29b085dc | 414 | rtx insn = emit_move_insn (predec, gen_rtx_REG (word_mode, pregno)); |
415 | RTX_FRAME_RELATED_P (insn) = 1; | |
416 | npregs--; | |
9e6a0967 | 417 | } |
9e6a0967 | 418 | } |
49569132 | 419 | for (i = REG_P7 + 1; i < REG_CC; i++) |
420 | if (saveall | |
421 | || (is_inthandler | |
422 | && (df_regs_ever_live_p (i) | |
423 | || (!leaf_function_p () && call_used_regs[i])))) | |
424 | { | |
29b085dc | 425 | rtx insn; |
49569132 | 426 | if (i == REG_A0 || i == REG_A1) |
427 | insn = emit_move_insn (gen_rtx_MEM (PDImode, predec1), | |
428 | gen_rtx_REG (PDImode, i)); | |
429 | else | |
430 | insn = emit_move_insn (predec, gen_rtx_REG (SImode, i)); | |
431 | RTX_FRAME_RELATED_P (insn) = 1; | |
432 | } | |
9e6a0967 | 433 | } |
434 | ||
435 | /* Emit code to restore registers in the epilogue. SAVEALL is nonzero if we | |
436 | must save all registers; this is used for interrupt handlers. | |
345458f3 | 437 | SPREG contains (reg:SI REG_SP). IS_INTHANDLER is true if we're doing |
438 | this for an interrupt (or exception) handler. */ | |
9e6a0967 | 439 | |
440 | static void | |
345458f3 | 441 | expand_epilogue_reg_restore (rtx spreg, bool saveall, bool is_inthandler) |
9e6a0967 | 442 | { |
49569132 | 443 | rtx postinc1 = gen_rtx_POST_INC (SImode, spreg); |
444 | rtx postinc = gen_rtx_MEM (SImode, postinc1); | |
445 | ||
29b085dc | 446 | int ndregs = saveall ? 8 : n_dregs_to_save (is_inthandler, false); |
447 | int npregs = saveall ? 6 : n_pregs_to_save (is_inthandler, false); | |
448 | int ndregs_consec = saveall ? 8 : n_dregs_to_save (is_inthandler, true); | |
449 | int npregs_consec = saveall ? 6 : n_pregs_to_save (is_inthandler, true); | |
450 | int total_consec = ndregs_consec + npregs_consec; | |
9e6a0967 | 451 | int i, regno; |
29b085dc | 452 | rtx insn; |
9e6a0967 | 453 | |
49569132 | 454 | /* A slightly crude technique to stop flow from trying to delete "dead" |
455 | insns. */ | |
456 | MEM_VOLATILE_P (postinc) = 1; | |
457 | ||
458 | for (i = REG_CC - 1; i > REG_P7; i--) | |
459 | if (saveall | |
460 | || (is_inthandler | |
461 | && (df_regs_ever_live_p (i) | |
462 | || (!leaf_function_p () && call_used_regs[i])))) | |
463 | { | |
464 | if (i == REG_A0 || i == REG_A1) | |
465 | { | |
466 | rtx mem = gen_rtx_MEM (PDImode, postinc1); | |
467 | MEM_VOLATILE_P (mem) = 1; | |
468 | emit_move_insn (gen_rtx_REG (PDImode, i), mem); | |
469 | } | |
470 | else | |
471 | emit_move_insn (gen_rtx_REG (SImode, i), postinc); | |
472 | } | |
473 | ||
29b085dc | 474 | regno = REG_P5 - npregs_consec; |
475 | for (; npregs != npregs_consec; regno--) | |
9e6a0967 | 476 | { |
29b085dc | 477 | if (must_save_p (is_inthandler, regno)) |
9e6a0967 | 478 | { |
29b085dc | 479 | emit_move_insn (gen_rtx_REG (word_mode, regno), postinc); |
480 | npregs--; | |
9e6a0967 | 481 | } |
482 | } | |
29b085dc | 483 | regno = REG_R7 - ndregs_consec; |
484 | for (; ndregs != ndregs_consec; regno--) | |
485 | { | |
486 | if (must_save_p (is_inthandler, regno)) | |
487 | { | |
488 | emit_move_insn (gen_rtx_REG (word_mode, regno), postinc); | |
489 | ndregs--; | |
490 | } | |
491 | } | |
492 | ||
493 | if (total_consec != 0) | |
494 | { | |
495 | rtx pat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_consec + 1)); | |
496 | XVECEXP (pat, 0, 0) | |
497 | = gen_rtx_SET (VOIDmode, spreg, | |
498 | gen_rtx_PLUS (Pmode, spreg, | |
499 | GEN_INT (total_consec * 4))); | |
500 | ||
501 | if (npregs_consec > 0) | |
502 | regno = REG_P5 + 1; | |
503 | else | |
504 | regno = REG_R7 + 1; | |
9e6a0967 | 505 | |
29b085dc | 506 | for (i = 0; i < total_consec; i++) |
507 | { | |
508 | rtx addr = (i > 0 | |
509 | ? gen_rtx_PLUS (Pmode, spreg, GEN_INT (i * 4)) | |
510 | : spreg); | |
511 | rtx memref = gen_rtx_MEM (word_mode, addr); | |
512 | ||
513 | regno--; | |
514 | XVECEXP (pat, 0, i + 1) | |
515 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (word_mode, regno), memref); | |
516 | ||
517 | if (npregs_consec > 0) | |
518 | { | |
519 | if (--npregs_consec == 0) | |
520 | regno = REG_R7 + 1; | |
521 | } | |
522 | } | |
49569132 | 523 | |
29b085dc | 524 | insn = emit_insn (pat); |
525 | RTX_FRAME_RELATED_P (insn) = 1; | |
526 | } | |
49569132 | 527 | if (saveall || is_inthandler) |
4cf41453 | 528 | { |
b43b7954 | 529 | for (regno = REG_LB1; regno >= REG_LT0; regno--) |
530 | if (! current_function_is_leaf | |
531 | || cfun->machine->has_hardware_loops | |
532 | || cfun->machine->has_loopreg_clobber | |
533 | || (ENABLE_WA_05000257 && (regno == REG_LC0 || regno == REG_LC1))) | |
4cf41453 | 534 | emit_move_insn (gen_rtx_REG (SImode, regno), postinc); |
535 | ||
536 | emit_move_insn (gen_rtx_REG (SImode, REG_ASTAT), postinc); | |
537 | } | |
9e6a0967 | 538 | } |
539 | ||
540 | /* Perform any needed actions needed for a function that is receiving a | |
541 | variable number of arguments. | |
542 | ||
543 | CUM is as above. | |
544 | ||
545 | MODE and TYPE are the mode and type of the current parameter. | |
546 | ||
547 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
548 | that must be pushed by the prolog to pretend that our caller pushed | |
549 | it. | |
550 | ||
551 | Normally, this macro will push all remaining incoming registers on the | |
552 | stack and set PRETEND_SIZE to the length of the registers pushed. | |
553 | ||
554 | Blackfin specific : | |
555 | - VDSP C compiler manual (our ABI) says that a variable args function | |
556 | should save the R0, R1 and R2 registers in the stack. | |
557 | - The caller will always leave space on the stack for the | |
558 | arguments that are passed in registers, so we dont have | |
559 | to leave any extra space. | |
560 | - now, the vastart pointer can access all arguments from the stack. */ | |
561 | ||
562 | static void | |
563 | setup_incoming_varargs (CUMULATIVE_ARGS *cum, | |
564 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
565 | tree type ATTRIBUTE_UNUSED, int *pretend_size, | |
566 | int no_rtl) | |
567 | { | |
568 | rtx mem; | |
569 | int i; | |
570 | ||
571 | if (no_rtl) | |
572 | return; | |
573 | ||
574 | /* The move for named arguments will be generated automatically by the | |
575 | compiler. We need to generate the move rtx for the unnamed arguments | |
fe24f256 | 576 | if they are in the first 3 words. We assume at least 1 named argument |
9e6a0967 | 577 | exists, so we never generate [ARGP] = R0 here. */ |
578 | ||
579 | for (i = cum->words + 1; i < max_arg_registers; i++) | |
580 | { | |
581 | mem = gen_rtx_MEM (Pmode, | |
582 | plus_constant (arg_pointer_rtx, (i * UNITS_PER_WORD))); | |
583 | emit_move_insn (mem, gen_rtx_REG (Pmode, i)); | |
584 | } | |
585 | ||
586 | *pretend_size = 0; | |
587 | } | |
588 | ||
589 | /* Value should be nonzero if functions must have frame pointers. | |
590 | Zero means the frame pointer need not be set up (and parms may | |
591 | be accessed via the stack pointer) in functions that seem suitable. */ | |
592 | ||
5a1c68c3 | 593 | static bool |
9e6a0967 | 594 | bfin_frame_pointer_required (void) |
595 | { | |
596 | e_funkind fkind = funkind (TREE_TYPE (current_function_decl)); | |
597 | ||
598 | if (fkind != SUBROUTINE) | |
5a1c68c3 | 599 | return true; |
9e6a0967 | 600 | |
3ce7ff97 | 601 | /* We turn on -fomit-frame-pointer if -momit-leaf-frame-pointer is used, |
9e6a0967 | 602 | so we have to override it for non-leaf functions. */ |
603 | if (TARGET_OMIT_LEAF_FRAME_POINTER && ! current_function_is_leaf) | |
5a1c68c3 | 604 | return true; |
9e6a0967 | 605 | |
5a1c68c3 | 606 | return false; |
9e6a0967 | 607 | } |
608 | ||
609 | /* Return the number of registers pushed during the prologue. */ | |
610 | ||
611 | static int | |
612 | n_regs_saved_by_prologue (void) | |
613 | { | |
614 | e_funkind fkind = funkind (TREE_TYPE (current_function_decl)); | |
345458f3 | 615 | bool is_inthandler = fkind != SUBROUTINE; |
616 | tree attrs = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl)); | |
617 | bool all = (lookup_attribute ("saveall", attrs) != NULL_TREE | |
618 | || (is_inthandler && !current_function_is_leaf)); | |
29b085dc | 619 | int ndregs = all ? 8 : n_dregs_to_save (is_inthandler, false); |
620 | int npregs = all ? 6 : n_pregs_to_save (is_inthandler, false); | |
345458f3 | 621 | int n = ndregs + npregs; |
49569132 | 622 | int i; |
9e6a0967 | 623 | |
345458f3 | 624 | if (all || stack_frame_needed_p ()) |
9e6a0967 | 625 | n += 2; |
626 | else | |
627 | { | |
628 | if (must_save_fp_p ()) | |
629 | n++; | |
4bb5cea5 | 630 | if (must_save_rets_p ()) |
9e6a0967 | 631 | n++; |
632 | } | |
633 | ||
49569132 | 634 | if (fkind != SUBROUTINE || all) |
4cf41453 | 635 | { |
636 | /* Increment once for ASTAT. */ | |
637 | n++; | |
638 | if (! current_function_is_leaf | |
639 | || cfun->machine->has_hardware_loops | |
640 | || cfun->machine->has_loopreg_clobber) | |
641 | { | |
642 | n += 6; | |
643 | } | |
644 | } | |
49569132 | 645 | |
9e6a0967 | 646 | if (fkind != SUBROUTINE) |
647 | { | |
9e6a0967 | 648 | /* RETE/X/N. */ |
649 | if (lookup_attribute ("nesting", attrs)) | |
650 | n++; | |
9e6a0967 | 651 | } |
49569132 | 652 | |
653 | for (i = REG_P7 + 1; i < REG_CC; i++) | |
654 | if (all | |
655 | || (fkind != SUBROUTINE | |
656 | && (df_regs_ever_live_p (i) | |
657 | || (!leaf_function_p () && call_used_regs[i])))) | |
658 | n += i == REG_A0 || i == REG_A1 ? 2 : 1; | |
659 | ||
9e6a0967 | 660 | return n; |
661 | } | |
662 | ||
cd90919d | 663 | /* Given FROM and TO register numbers, say whether this elimination is |
664 | allowed. Frame pointer elimination is automatically handled. | |
665 | ||
666 | All other eliminations are valid. */ | |
667 | ||
668 | static bool | |
669 | bfin_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) | |
670 | { | |
671 | return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true); | |
672 | } | |
673 | ||
9e6a0967 | 674 | /* Return the offset between two registers, one to be eliminated, and the other |
675 | its replacement, at the start of a routine. */ | |
676 | ||
677 | HOST_WIDE_INT | |
678 | bfin_initial_elimination_offset (int from, int to) | |
679 | { | |
680 | HOST_WIDE_INT offset = 0; | |
681 | ||
682 | if (from == ARG_POINTER_REGNUM) | |
683 | offset = n_regs_saved_by_prologue () * 4; | |
684 | ||
685 | if (to == STACK_POINTER_REGNUM) | |
686 | { | |
abe32cce | 687 | if (crtl->outgoing_args_size >= FIXED_STACK_AREA) |
688 | offset += crtl->outgoing_args_size; | |
689 | else if (crtl->outgoing_args_size) | |
9e6a0967 | 690 | offset += FIXED_STACK_AREA; |
691 | ||
692 | offset += get_frame_size (); | |
693 | } | |
694 | ||
695 | return offset; | |
696 | } | |
697 | ||
698 | /* Emit code to load a constant CONSTANT into register REG; setting | |
b90ce3c3 | 699 | RTX_FRAME_RELATED_P on all insns we generate if RELATED is true. |
700 | Make sure that the insns we generate need not be split. */ | |
9e6a0967 | 701 | |
702 | static void | |
b90ce3c3 | 703 | frame_related_constant_load (rtx reg, HOST_WIDE_INT constant, bool related) |
9e6a0967 | 704 | { |
705 | rtx insn; | |
706 | rtx cst = GEN_INT (constant); | |
707 | ||
708 | if (constant >= -32768 && constant < 65536) | |
709 | insn = emit_move_insn (reg, cst); | |
710 | else | |
711 | { | |
712 | /* We don't call split_load_immediate here, since dwarf2out.c can get | |
713 | confused about some of the more clever sequences it can generate. */ | |
714 | insn = emit_insn (gen_movsi_high (reg, cst)); | |
b90ce3c3 | 715 | if (related) |
716 | RTX_FRAME_RELATED_P (insn) = 1; | |
9e6a0967 | 717 | insn = emit_insn (gen_movsi_low (reg, reg, cst)); |
718 | } | |
b90ce3c3 | 719 | if (related) |
720 | RTX_FRAME_RELATED_P (insn) = 1; | |
9e6a0967 | 721 | } |
722 | ||
a35b82b9 | 723 | /* Generate efficient code to add a value to a P register. |
724 | Set RTX_FRAME_RELATED_P on the generated insns if FRAME is nonzero. | |
725 | EPILOGUE_P is zero if this function is called for prologue, | |
726 | otherwise it's nonzero. And it's less than zero if this is for | |
727 | sibcall epilogue. */ | |
9e6a0967 | 728 | |
729 | static void | |
a35b82b9 | 730 | add_to_reg (rtx reg, HOST_WIDE_INT value, int frame, int epilogue_p) |
9e6a0967 | 731 | { |
732 | if (value == 0) | |
733 | return; | |
734 | ||
735 | /* Choose whether to use a sequence using a temporary register, or | |
905ea169 | 736 | a sequence with multiple adds. We can add a signed 7-bit value |
9e6a0967 | 737 | in one instruction. */ |
738 | if (value > 120 || value < -120) | |
739 | { | |
a35b82b9 | 740 | rtx tmpreg; |
741 | rtx tmpreg2; | |
9e6a0967 | 742 | rtx insn; |
743 | ||
a35b82b9 | 744 | tmpreg2 = NULL_RTX; |
745 | ||
746 | /* For prologue or normal epilogue, P1 can be safely used | |
747 | as the temporary register. For sibcall epilogue, we try to find | |
748 | a call used P register, which will be restored in epilogue. | |
749 | If we cannot find such a P register, we have to use one I register | |
750 | to help us. */ | |
751 | ||
752 | if (epilogue_p >= 0) | |
753 | tmpreg = gen_rtx_REG (SImode, REG_P1); | |
754 | else | |
755 | { | |
756 | int i; | |
757 | for (i = REG_P0; i <= REG_P5; i++) | |
d18119ae | 758 | if ((df_regs_ever_live_p (i) && ! call_used_regs[i]) |
a35b82b9 | 759 | || (!TARGET_FDPIC |
760 | && i == PIC_OFFSET_TABLE_REGNUM | |
18d50ae6 | 761 | && (crtl->uses_pic_offset_table |
a35b82b9 | 762 | || (TARGET_ID_SHARED_LIBRARY |
763 | && ! current_function_is_leaf)))) | |
764 | break; | |
765 | if (i <= REG_P5) | |
766 | tmpreg = gen_rtx_REG (SImode, i); | |
767 | else | |
768 | { | |
769 | tmpreg = gen_rtx_REG (SImode, REG_P1); | |
770 | tmpreg2 = gen_rtx_REG (SImode, REG_I0); | |
771 | emit_move_insn (tmpreg2, tmpreg); | |
772 | } | |
773 | } | |
774 | ||
9e6a0967 | 775 | if (frame) |
b90ce3c3 | 776 | frame_related_constant_load (tmpreg, value, TRUE); |
9e6a0967 | 777 | else |
6295e560 | 778 | insn = emit_move_insn (tmpreg, GEN_INT (value)); |
9e6a0967 | 779 | |
6295e560 | 780 | insn = emit_insn (gen_addsi3 (reg, reg, tmpreg)); |
9e6a0967 | 781 | if (frame) |
782 | RTX_FRAME_RELATED_P (insn) = 1; | |
a35b82b9 | 783 | |
784 | if (tmpreg2 != NULL_RTX) | |
785 | emit_move_insn (tmpreg, tmpreg2); | |
9e6a0967 | 786 | } |
787 | else | |
788 | do | |
789 | { | |
790 | int size = value; | |
791 | rtx insn; | |
792 | ||
793 | if (size > 60) | |
794 | size = 60; | |
795 | else if (size < -60) | |
796 | /* We could use -62, but that would leave the stack unaligned, so | |
797 | it's no good. */ | |
798 | size = -60; | |
799 | ||
6295e560 | 800 | insn = emit_insn (gen_addsi3 (reg, reg, GEN_INT (size))); |
9e6a0967 | 801 | if (frame) |
802 | RTX_FRAME_RELATED_P (insn) = 1; | |
803 | value -= size; | |
804 | } | |
805 | while (value != 0); | |
806 | } | |
807 | ||
808 | /* Generate a LINK insn for a frame sized FRAME_SIZE. If this constant | |
809 | is too large, generate a sequence of insns that has the same effect. | |
810 | SPREG contains (reg:SI REG_SP). */ | |
811 | ||
812 | static void | |
813 | emit_link_insn (rtx spreg, HOST_WIDE_INT frame_size) | |
814 | { | |
815 | HOST_WIDE_INT link_size = frame_size; | |
816 | rtx insn; | |
817 | int i; | |
818 | ||
819 | if (link_size > 262140) | |
820 | link_size = 262140; | |
821 | ||
822 | /* Use a LINK insn with as big a constant as possible, then subtract | |
823 | any remaining size from the SP. */ | |
824 | insn = emit_insn (gen_link (GEN_INT (-8 - link_size))); | |
825 | RTX_FRAME_RELATED_P (insn) = 1; | |
826 | ||
827 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) | |
828 | { | |
829 | rtx set = XVECEXP (PATTERN (insn), 0, i); | |
2115ae11 | 830 | gcc_assert (GET_CODE (set) == SET); |
9e6a0967 | 831 | RTX_FRAME_RELATED_P (set) = 1; |
832 | } | |
833 | ||
834 | frame_size -= link_size; | |
835 | ||
836 | if (frame_size > 0) | |
837 | { | |
838 | /* Must use a call-clobbered PREG that isn't the static chain. */ | |
839 | rtx tmpreg = gen_rtx_REG (Pmode, REG_P1); | |
840 | ||
b90ce3c3 | 841 | frame_related_constant_load (tmpreg, -frame_size, TRUE); |
9e6a0967 | 842 | insn = emit_insn (gen_addsi3 (spreg, spreg, tmpreg)); |
843 | RTX_FRAME_RELATED_P (insn) = 1; | |
844 | } | |
845 | } | |
846 | ||
847 | /* Return the number of bytes we must reserve for outgoing arguments | |
848 | in the current function's stack frame. */ | |
849 | ||
850 | static HOST_WIDE_INT | |
851 | arg_area_size (void) | |
852 | { | |
abe32cce | 853 | if (crtl->outgoing_args_size) |
9e6a0967 | 854 | { |
abe32cce | 855 | if (crtl->outgoing_args_size >= FIXED_STACK_AREA) |
856 | return crtl->outgoing_args_size; | |
9e6a0967 | 857 | else |
858 | return FIXED_STACK_AREA; | |
859 | } | |
860 | return 0; | |
861 | } | |
862 | ||
345458f3 | 863 | /* Save RETS and FP, and allocate a stack frame. ALL is true if the |
864 | function must save all its registers (true only for certain interrupt | |
865 | handlers). */ | |
9e6a0967 | 866 | |
867 | static void | |
345458f3 | 868 | do_link (rtx spreg, HOST_WIDE_INT frame_size, bool all) |
9e6a0967 | 869 | { |
870 | frame_size += arg_area_size (); | |
871 | ||
4bb5cea5 | 872 | if (all |
873 | || stack_frame_needed_p () | |
874 | || (must_save_rets_p () && must_save_fp_p ())) | |
9e6a0967 | 875 | emit_link_insn (spreg, frame_size); |
876 | else | |
877 | { | |
4bb5cea5 | 878 | if (must_save_rets_p ()) |
9e6a0967 | 879 | { |
880 | rtx pat = gen_movsi (gen_rtx_MEM (Pmode, | |
881 | gen_rtx_PRE_DEC (Pmode, spreg)), | |
882 | bfin_rets_rtx); | |
883 | rtx insn = emit_insn (pat); | |
884 | RTX_FRAME_RELATED_P (insn) = 1; | |
885 | } | |
886 | if (must_save_fp_p ()) | |
887 | { | |
888 | rtx pat = gen_movsi (gen_rtx_MEM (Pmode, | |
889 | gen_rtx_PRE_DEC (Pmode, spreg)), | |
890 | gen_rtx_REG (Pmode, REG_FP)); | |
891 | rtx insn = emit_insn (pat); | |
892 | RTX_FRAME_RELATED_P (insn) = 1; | |
893 | } | |
a35b82b9 | 894 | add_to_reg (spreg, -frame_size, 1, 0); |
9e6a0967 | 895 | } |
896 | } | |
897 | ||
a35b82b9 | 898 | /* Like do_link, but used for epilogues to deallocate the stack frame. |
899 | EPILOGUE_P is zero if this function is called for prologue, | |
900 | otherwise it's nonzero. And it's less than zero if this is for | |
901 | sibcall epilogue. */ | |
9e6a0967 | 902 | |
903 | static void | |
a35b82b9 | 904 | do_unlink (rtx spreg, HOST_WIDE_INT frame_size, bool all, int epilogue_p) |
9e6a0967 | 905 | { |
906 | frame_size += arg_area_size (); | |
907 | ||
4bb5cea5 | 908 | if (stack_frame_needed_p ()) |
9e6a0967 | 909 | emit_insn (gen_unlink ()); |
910 | else | |
911 | { | |
912 | rtx postinc = gen_rtx_MEM (Pmode, gen_rtx_POST_INC (Pmode, spreg)); | |
913 | ||
a35b82b9 | 914 | add_to_reg (spreg, frame_size, 0, epilogue_p); |
4bb5cea5 | 915 | if (all || must_save_fp_p ()) |
9e6a0967 | 916 | { |
917 | rtx fpreg = gen_rtx_REG (Pmode, REG_FP); | |
918 | emit_move_insn (fpreg, postinc); | |
18b42941 | 919 | emit_use (fpreg); |
9e6a0967 | 920 | } |
4bb5cea5 | 921 | if (all || must_save_rets_p ()) |
9e6a0967 | 922 | { |
923 | emit_move_insn (bfin_rets_rtx, postinc); | |
18b42941 | 924 | emit_use (bfin_rets_rtx); |
9e6a0967 | 925 | } |
926 | } | |
927 | } | |
928 | ||
929 | /* Generate a prologue suitable for a function of kind FKIND. This is | |
930 | called for interrupt and exception handler prologues. | |
931 | SPREG contains (reg:SI REG_SP). */ | |
932 | ||
933 | static void | |
49569132 | 934 | expand_interrupt_handler_prologue (rtx spreg, e_funkind fkind, bool all) |
9e6a0967 | 935 | { |
9e6a0967 | 936 | HOST_WIDE_INT frame_size = get_frame_size (); |
937 | rtx predec1 = gen_rtx_PRE_DEC (SImode, spreg); | |
938 | rtx predec = gen_rtx_MEM (SImode, predec1); | |
939 | rtx insn; | |
940 | tree attrs = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl)); | |
9e6a0967 | 941 | tree kspisusp = lookup_attribute ("kspisusp", attrs); |
942 | ||
943 | if (kspisusp) | |
944 | { | |
945 | insn = emit_move_insn (spreg, gen_rtx_REG (Pmode, REG_USP)); | |
946 | RTX_FRAME_RELATED_P (insn) = 1; | |
947 | } | |
948 | ||
949 | /* We need space on the stack in case we need to save the argument | |
950 | registers. */ | |
951 | if (fkind == EXCPT_HANDLER) | |
952 | { | |
953 | insn = emit_insn (gen_addsi3 (spreg, spreg, GEN_INT (-12))); | |
954 | RTX_FRAME_RELATED_P (insn) = 1; | |
955 | } | |
956 | ||
345458f3 | 957 | /* If we're calling other functions, they won't save their call-clobbered |
958 | registers, so we must save everything here. */ | |
959 | if (!current_function_is_leaf) | |
960 | all = true; | |
961 | expand_prologue_reg_save (spreg, all, true); | |
9e6a0967 | 962 | |
b43b7954 | 963 | if (ENABLE_WA_05000283 || ENABLE_WA_05000315) |
964 | { | |
965 | rtx chipid = GEN_INT (trunc_int_for_mode (0xFFC00014, SImode)); | |
966 | rtx p5reg = gen_rtx_REG (Pmode, REG_P5); | |
967 | emit_insn (gen_movbi (bfin_cc_rtx, const1_rtx)); | |
968 | emit_insn (gen_movsi_high (p5reg, chipid)); | |
969 | emit_insn (gen_movsi_low (p5reg, p5reg, chipid)); | |
970 | emit_insn (gen_dummy_load (p5reg, bfin_cc_rtx)); | |
971 | } | |
972 | ||
9e6a0967 | 973 | if (lookup_attribute ("nesting", attrs)) |
974 | { | |
4bb5cea5 | 975 | rtx srcreg = gen_rtx_REG (Pmode, ret_regs[fkind]); |
9e6a0967 | 976 | insn = emit_move_insn (predec, srcreg); |
977 | RTX_FRAME_RELATED_P (insn) = 1; | |
978 | } | |
979 | ||
345458f3 | 980 | do_link (spreg, frame_size, all); |
9e6a0967 | 981 | |
982 | if (fkind == EXCPT_HANDLER) | |
983 | { | |
984 | rtx r0reg = gen_rtx_REG (SImode, REG_R0); | |
985 | rtx r1reg = gen_rtx_REG (SImode, REG_R1); | |
986 | rtx r2reg = gen_rtx_REG (SImode, REG_R2); | |
9e6a0967 | 987 | |
95f13934 | 988 | emit_move_insn (r0reg, gen_rtx_REG (SImode, REG_SEQSTAT)); |
989 | emit_insn (gen_ashrsi3 (r0reg, r0reg, GEN_INT (26))); | |
990 | emit_insn (gen_ashlsi3 (r0reg, r0reg, GEN_INT (26))); | |
991 | emit_move_insn (r1reg, spreg); | |
992 | emit_move_insn (r2reg, gen_rtx_REG (Pmode, REG_FP)); | |
993 | emit_insn (gen_addsi3 (r2reg, r2reg, GEN_INT (8))); | |
9e6a0967 | 994 | } |
995 | } | |
996 | ||
997 | /* Generate an epilogue suitable for a function of kind FKIND. This is | |
998 | called for interrupt and exception handler epilogues. | |
999 | SPREG contains (reg:SI REG_SP). */ | |
1000 | ||
1001 | static void | |
49569132 | 1002 | expand_interrupt_handler_epilogue (rtx spreg, e_funkind fkind, bool all) |
9e6a0967 | 1003 | { |
49569132 | 1004 | tree attrs = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl)); |
9e6a0967 | 1005 | rtx postinc1 = gen_rtx_POST_INC (SImode, spreg); |
1006 | rtx postinc = gen_rtx_MEM (SImode, postinc1); | |
9e6a0967 | 1007 | |
1008 | /* A slightly crude technique to stop flow from trying to delete "dead" | |
1009 | insns. */ | |
1010 | MEM_VOLATILE_P (postinc) = 1; | |
1011 | ||
a35b82b9 | 1012 | do_unlink (spreg, get_frame_size (), all, 1); |
9e6a0967 | 1013 | |
1014 | if (lookup_attribute ("nesting", attrs)) | |
1015 | { | |
4bb5cea5 | 1016 | rtx srcreg = gen_rtx_REG (Pmode, ret_regs[fkind]); |
9e6a0967 | 1017 | emit_move_insn (srcreg, postinc); |
1018 | } | |
1019 | ||
345458f3 | 1020 | /* If we're calling other functions, they won't save their call-clobbered |
1021 | registers, so we must save (and restore) everything here. */ | |
1022 | if (!current_function_is_leaf) | |
1023 | all = true; | |
1024 | ||
345458f3 | 1025 | expand_epilogue_reg_restore (spreg, all, true); |
9e6a0967 | 1026 | |
9e6a0967 | 1027 | /* Deallocate any space we left on the stack in case we needed to save the |
1028 | argument registers. */ | |
1029 | if (fkind == EXCPT_HANDLER) | |
1030 | emit_insn (gen_addsi3 (spreg, spreg, GEN_INT (12))); | |
1031 | ||
4bb5cea5 | 1032 | emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, ret_regs[fkind]))); |
9e6a0967 | 1033 | } |
1034 | ||
b90ce3c3 | 1035 | /* Used while emitting the prologue to generate code to load the correct value |
1036 | into the PIC register, which is passed in DEST. */ | |
1037 | ||
70d893c7 | 1038 | static rtx |
b90ce3c3 | 1039 | bfin_load_pic_reg (rtx dest) |
1040 | { | |
70d893c7 | 1041 | struct cgraph_local_info *i = NULL; |
95f13934 | 1042 | rtx addr; |
70d893c7 | 1043 | |
6329636b | 1044 | i = cgraph_local_info (current_function_decl); |
70d893c7 | 1045 | |
1046 | /* Functions local to the translation unit don't need to reload the | |
1047 | pic reg, since the caller always passes a usable one. */ | |
1048 | if (i && i->local) | |
1049 | return pic_offset_table_rtx; | |
b90ce3c3 | 1050 | |
33c9a3e7 | 1051 | if (global_options_set.x_bfin_library_id) |
b90ce3c3 | 1052 | addr = plus_constant (pic_offset_table_rtx, -4 - bfin_library_id * 4); |
1053 | else | |
1054 | addr = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, | |
1055 | gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
1056 | UNSPEC_LIBRARY_OFFSET)); | |
95f13934 | 1057 | emit_insn (gen_movsi (dest, gen_rtx_MEM (Pmode, addr))); |
70d893c7 | 1058 | return dest; |
b90ce3c3 | 1059 | } |
1060 | ||
9e6a0967 | 1061 | /* Generate RTL for the prologue of the current function. */ |
1062 | ||
1063 | void | |
1064 | bfin_expand_prologue (void) | |
1065 | { | |
9e6a0967 | 1066 | HOST_WIDE_INT frame_size = get_frame_size (); |
1067 | rtx spreg = gen_rtx_REG (Pmode, REG_SP); | |
1068 | e_funkind fkind = funkind (TREE_TYPE (current_function_decl)); | |
b90ce3c3 | 1069 | rtx pic_reg_loaded = NULL_RTX; |
49569132 | 1070 | tree attrs = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl)); |
1071 | bool all = lookup_attribute ("saveall", attrs) != NULL_TREE; | |
9e6a0967 | 1072 | |
1073 | if (fkind != SUBROUTINE) | |
1074 | { | |
49569132 | 1075 | expand_interrupt_handler_prologue (spreg, fkind, all); |
9e6a0967 | 1076 | return; |
1077 | } | |
1078 | ||
18d50ae6 | 1079 | if (crtl->limit_stack |
14a75278 | 1080 | || (TARGET_STACK_CHECK_L1 |
1081 | && !DECL_NO_LIMIT_STACK (current_function_decl))) | |
b90ce3c3 | 1082 | { |
1083 | HOST_WIDE_INT offset | |
1084 | = bfin_initial_elimination_offset (ARG_POINTER_REGNUM, | |
1085 | STACK_POINTER_REGNUM); | |
18d50ae6 | 1086 | rtx lim = crtl->limit_stack ? stack_limit_rtx : NULL_RTX; |
6d8651b5 | 1087 | rtx tmp = gen_rtx_REG (Pmode, REG_R3); |
6295e560 | 1088 | rtx p2reg = gen_rtx_REG (Pmode, REG_P2); |
b90ce3c3 | 1089 | |
6d8651b5 | 1090 | emit_move_insn (tmp, p2reg); |
6295e560 | 1091 | if (!lim) |
1092 | { | |
6295e560 | 1093 | emit_move_insn (p2reg, gen_int_mode (0xFFB00000, SImode)); |
1094 | emit_move_insn (p2reg, gen_rtx_MEM (Pmode, p2reg)); | |
1095 | lim = p2reg; | |
1096 | } | |
b90ce3c3 | 1097 | if (GET_CODE (lim) == SYMBOL_REF) |
1098 | { | |
b90ce3c3 | 1099 | if (TARGET_ID_SHARED_LIBRARY) |
1100 | { | |
1101 | rtx p1reg = gen_rtx_REG (Pmode, REG_P1); | |
b90ce3c3 | 1102 | rtx val; |
70d893c7 | 1103 | pic_reg_loaded = bfin_load_pic_reg (p2reg); |
1104 | val = legitimize_pic_address (stack_limit_rtx, p1reg, | |
1105 | pic_reg_loaded); | |
b90ce3c3 | 1106 | emit_move_insn (p1reg, val); |
1107 | frame_related_constant_load (p2reg, offset, FALSE); | |
1108 | emit_insn (gen_addsi3 (p2reg, p2reg, p1reg)); | |
1109 | lim = p2reg; | |
1110 | } | |
1111 | else | |
1112 | { | |
6295e560 | 1113 | rtx limit = plus_constant (lim, offset); |
b90ce3c3 | 1114 | emit_move_insn (p2reg, limit); |
1115 | lim = p2reg; | |
1116 | } | |
1117 | } | |
6295e560 | 1118 | else |
1119 | { | |
1120 | if (lim != p2reg) | |
1121 | emit_move_insn (p2reg, lim); | |
a35b82b9 | 1122 | add_to_reg (p2reg, offset, 0, 0); |
6295e560 | 1123 | lim = p2reg; |
1124 | } | |
b90ce3c3 | 1125 | emit_insn (gen_compare_lt (bfin_cc_rtx, spreg, lim)); |
1126 | emit_insn (gen_trapifcc ()); | |
6d8651b5 | 1127 | emit_move_insn (p2reg, tmp); |
b90ce3c3 | 1128 | } |
49569132 | 1129 | expand_prologue_reg_save (spreg, all, false); |
9e6a0967 | 1130 | |
0c3f2f8a | 1131 | do_link (spreg, frame_size, all); |
9e6a0967 | 1132 | |
1133 | if (TARGET_ID_SHARED_LIBRARY | |
40831b00 | 1134 | && !TARGET_SEP_DATA |
18d50ae6 | 1135 | && (crtl->uses_pic_offset_table |
9e6a0967 | 1136 | || !current_function_is_leaf)) |
b90ce3c3 | 1137 | bfin_load_pic_reg (pic_offset_table_rtx); |
9e6a0967 | 1138 | } |
1139 | ||
1140 | /* Generate RTL for the epilogue of the current function. NEED_RETURN is zero | |
1141 | if this is for a sibcall. EH_RETURN is nonzero if we're expanding an | |
a35b82b9 | 1142 | eh_return pattern. SIBCALL_P is true if this is a sibcall epilogue, |
1143 | false otherwise. */ | |
9e6a0967 | 1144 | |
1145 | void | |
a35b82b9 | 1146 | bfin_expand_epilogue (int need_return, int eh_return, bool sibcall_p) |
9e6a0967 | 1147 | { |
1148 | rtx spreg = gen_rtx_REG (Pmode, REG_SP); | |
1149 | e_funkind fkind = funkind (TREE_TYPE (current_function_decl)); | |
a35b82b9 | 1150 | int e = sibcall_p ? -1 : 1; |
49569132 | 1151 | tree attrs = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl)); |
1152 | bool all = lookup_attribute ("saveall", attrs) != NULL_TREE; | |
9e6a0967 | 1153 | |
1154 | if (fkind != SUBROUTINE) | |
1155 | { | |
49569132 | 1156 | expand_interrupt_handler_epilogue (spreg, fkind, all); |
9e6a0967 | 1157 | return; |
1158 | } | |
1159 | ||
0c3f2f8a | 1160 | do_unlink (spreg, get_frame_size (), all, e); |
9e6a0967 | 1161 | |
49569132 | 1162 | expand_epilogue_reg_restore (spreg, all, false); |
9e6a0967 | 1163 | |
1164 | /* Omit the return insn if this is for a sibcall. */ | |
1165 | if (! need_return) | |
1166 | return; | |
1167 | ||
1168 | if (eh_return) | |
1169 | emit_insn (gen_addsi3 (spreg, spreg, gen_rtx_REG (Pmode, REG_P2))); | |
1170 | ||
4bb5cea5 | 1171 | emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, REG_RETS))); |
9e6a0967 | 1172 | } |
1173 | \f | |
1174 | /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */ | |
1175 | ||
1176 | int | |
1177 | bfin_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, | |
1178 | unsigned int new_reg) | |
1179 | { | |
1180 | /* Interrupt functions can only use registers that have already been | |
1181 | saved by the prologue, even if they would normally be | |
1182 | call-clobbered. */ | |
1183 | ||
1184 | if (funkind (TREE_TYPE (current_function_decl)) != SUBROUTINE | |
3072d30e | 1185 | && !df_regs_ever_live_p (new_reg)) |
9e6a0967 | 1186 | return 0; |
1187 | ||
1188 | return 1; | |
1189 | } | |
1190 | ||
08d2cf2d | 1191 | /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */ |
1192 | static void | |
1193 | bfin_extra_live_on_entry (bitmap regs) | |
1194 | { | |
1195 | if (TARGET_FDPIC) | |
1196 | bitmap_set_bit (regs, FDPIC_REGNO); | |
1197 | } | |
1198 | ||
9e6a0967 | 1199 | /* Return the value of the return address for the frame COUNT steps up |
1200 | from the current frame, after the prologue. | |
1201 | We punt for everything but the current frame by returning const0_rtx. */ | |
1202 | ||
1203 | rtx | |
1204 | bfin_return_addr_rtx (int count) | |
1205 | { | |
1206 | if (count != 0) | |
1207 | return const0_rtx; | |
1208 | ||
1209 | return get_hard_reg_initial_val (Pmode, REG_RETS); | |
1210 | } | |
1211 | ||
6833eae4 | 1212 | static rtx |
1213 | bfin_delegitimize_address (rtx orig_x) | |
1214 | { | |
2b8e874f | 1215 | rtx x = orig_x; |
6833eae4 | 1216 | |
1217 | if (GET_CODE (x) != MEM) | |
1218 | return orig_x; | |
1219 | ||
1220 | x = XEXP (x, 0); | |
1221 | if (GET_CODE (x) == PLUS | |
1222 | && GET_CODE (XEXP (x, 1)) == UNSPEC | |
1223 | && XINT (XEXP (x, 1), 1) == UNSPEC_MOVE_PIC | |
1224 | && GET_CODE (XEXP (x, 0)) == REG | |
1225 | && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM) | |
1226 | return XVECEXP (XEXP (x, 1), 0, 0); | |
1227 | ||
1228 | return orig_x; | |
1229 | } | |
1230 | ||
9e6a0967 | 1231 | /* This predicate is used to compute the length of a load/store insn. |
1232 | OP is a MEM rtx, we return nonzero if its addressing mode requires a | |
905ea169 | 1233 | 32-bit instruction. */ |
9e6a0967 | 1234 | |
1235 | int | |
1236 | effective_address_32bit_p (rtx op, enum machine_mode mode) | |
1237 | { | |
1238 | HOST_WIDE_INT offset; | |
1239 | ||
1240 | mode = GET_MODE (op); | |
1241 | op = XEXP (op, 0); | |
1242 | ||
9e6a0967 | 1243 | if (GET_CODE (op) != PLUS) |
2115ae11 | 1244 | { |
1245 | gcc_assert (REG_P (op) || GET_CODE (op) == POST_INC | |
1246 | || GET_CODE (op) == PRE_DEC || GET_CODE (op) == POST_DEC); | |
1247 | return 0; | |
1248 | } | |
9e6a0967 | 1249 | |
4c359296 | 1250 | if (GET_CODE (XEXP (op, 1)) == UNSPEC) |
1251 | return 1; | |
1252 | ||
9e6a0967 | 1253 | offset = INTVAL (XEXP (op, 1)); |
1254 | ||
905ea169 | 1255 | /* All byte loads use a 16-bit offset. */ |
9e6a0967 | 1256 | if (GET_MODE_SIZE (mode) == 1) |
1257 | return 1; | |
1258 | ||
1259 | if (GET_MODE_SIZE (mode) == 4) | |
1260 | { | |
1261 | /* Frame pointer relative loads can use a negative offset, all others | |
1262 | are restricted to a small positive one. */ | |
1263 | if (XEXP (op, 0) == frame_pointer_rtx) | |
1264 | return offset < -128 || offset > 60; | |
1265 | return offset < 0 || offset > 60; | |
1266 | } | |
1267 | ||
1268 | /* Must be HImode now. */ | |
1269 | return offset < 0 || offset > 30; | |
1270 | } | |
1271 | ||
00cb30dc | 1272 | /* Returns true if X is a memory reference using an I register. */ |
1273 | bool | |
1274 | bfin_dsp_memref_p (rtx x) | |
1275 | { | |
1276 | if (! MEM_P (x)) | |
1277 | return false; | |
1278 | x = XEXP (x, 0); | |
1279 | if (GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_INC | |
1280 | || GET_CODE (x) == POST_DEC || GET_CODE (x) == PRE_DEC) | |
1281 | x = XEXP (x, 0); | |
1282 | return IREG_P (x); | |
1283 | } | |
1284 | ||
9e6a0967 | 1285 | /* Return cost of the memory address ADDR. |
1286 | All addressing modes are equally cheap on the Blackfin. */ | |
1287 | ||
1288 | static int | |
f529eb25 | 1289 | bfin_address_cost (rtx addr ATTRIBUTE_UNUSED, bool speed ATTRIBUTE_UNUSED) |
9e6a0967 | 1290 | { |
1291 | return 1; | |
1292 | } | |
1293 | ||
1294 | /* Subroutine of print_operand; used to print a memory reference X to FILE. */ | |
1295 | ||
1296 | void | |
1297 | print_address_operand (FILE *file, rtx x) | |
1298 | { | |
9e6a0967 | 1299 | switch (GET_CODE (x)) |
1300 | { | |
1301 | case PLUS: | |
1302 | output_address (XEXP (x, 0)); | |
1303 | fprintf (file, "+"); | |
1304 | output_address (XEXP (x, 1)); | |
1305 | break; | |
1306 | ||
1307 | case PRE_DEC: | |
1308 | fprintf (file, "--"); | |
1309 | output_address (XEXP (x, 0)); | |
1310 | break; | |
1311 | case POST_INC: | |
1312 | output_address (XEXP (x, 0)); | |
1313 | fprintf (file, "++"); | |
1314 | break; | |
1315 | case POST_DEC: | |
1316 | output_address (XEXP (x, 0)); | |
1317 | fprintf (file, "--"); | |
1318 | break; | |
1319 | ||
1320 | default: | |
2115ae11 | 1321 | gcc_assert (GET_CODE (x) != MEM); |
9e6a0967 | 1322 | print_operand (file, x, 0); |
2115ae11 | 1323 | break; |
9e6a0967 | 1324 | } |
1325 | } | |
1326 | ||
1327 | /* Adding intp DImode support by Tony | |
1328 | * -- Q: (low word) | |
1329 | * -- R: (high word) | |
1330 | */ | |
1331 | ||
1332 | void | |
1333 | print_operand (FILE *file, rtx x, char code) | |
1334 | { | |
48df5a7f | 1335 | enum machine_mode mode; |
1336 | ||
1337 | if (code == '!') | |
1338 | { | |
1339 | if (GET_MODE (current_output_insn) == SImode) | |
1340 | fprintf (file, " ||"); | |
1341 | else | |
1342 | fprintf (file, ";"); | |
1343 | return; | |
1344 | } | |
1345 | ||
1346 | mode = GET_MODE (x); | |
9e6a0967 | 1347 | |
1348 | switch (code) | |
1349 | { | |
1350 | case 'j': | |
1351 | switch (GET_CODE (x)) | |
1352 | { | |
1353 | case EQ: | |
1354 | fprintf (file, "e"); | |
1355 | break; | |
1356 | case NE: | |
1357 | fprintf (file, "ne"); | |
1358 | break; | |
1359 | case GT: | |
1360 | fprintf (file, "g"); | |
1361 | break; | |
1362 | case LT: | |
1363 | fprintf (file, "l"); | |
1364 | break; | |
1365 | case GE: | |
1366 | fprintf (file, "ge"); | |
1367 | break; | |
1368 | case LE: | |
1369 | fprintf (file, "le"); | |
1370 | break; | |
1371 | case GTU: | |
1372 | fprintf (file, "g"); | |
1373 | break; | |
1374 | case LTU: | |
1375 | fprintf (file, "l"); | |
1376 | break; | |
1377 | case GEU: | |
1378 | fprintf (file, "ge"); | |
1379 | break; | |
1380 | case LEU: | |
1381 | fprintf (file, "le"); | |
1382 | break; | |
1383 | default: | |
1384 | output_operand_lossage ("invalid %%j value"); | |
1385 | } | |
1386 | break; | |
1387 | ||
1388 | case 'J': /* reverse logic */ | |
1389 | switch (GET_CODE(x)) | |
1390 | { | |
1391 | case EQ: | |
1392 | fprintf (file, "ne"); | |
1393 | break; | |
1394 | case NE: | |
1395 | fprintf (file, "e"); | |
1396 | break; | |
1397 | case GT: | |
1398 | fprintf (file, "le"); | |
1399 | break; | |
1400 | case LT: | |
1401 | fprintf (file, "ge"); | |
1402 | break; | |
1403 | case GE: | |
1404 | fprintf (file, "l"); | |
1405 | break; | |
1406 | case LE: | |
1407 | fprintf (file, "g"); | |
1408 | break; | |
1409 | case GTU: | |
1410 | fprintf (file, "le"); | |
1411 | break; | |
1412 | case LTU: | |
1413 | fprintf (file, "ge"); | |
1414 | break; | |
1415 | case GEU: | |
1416 | fprintf (file, "l"); | |
1417 | break; | |
1418 | case LEU: | |
1419 | fprintf (file, "g"); | |
1420 | break; | |
1421 | default: | |
1422 | output_operand_lossage ("invalid %%J value"); | |
1423 | } | |
1424 | break; | |
1425 | ||
1426 | default: | |
1427 | switch (GET_CODE (x)) | |
1428 | { | |
1429 | case REG: | |
1430 | if (code == 'h') | |
1431 | { | |
108988a0 | 1432 | if (REGNO (x) < 32) |
1433 | fprintf (file, "%s", short_reg_names[REGNO (x)]); | |
1434 | else | |
1435 | output_operand_lossage ("invalid operand for code '%c'", code); | |
9e6a0967 | 1436 | } |
1437 | else if (code == 'd') | |
1438 | { | |
108988a0 | 1439 | if (REGNO (x) < 32) |
1440 | fprintf (file, "%s", high_reg_names[REGNO (x)]); | |
1441 | else | |
1442 | output_operand_lossage ("invalid operand for code '%c'", code); | |
9e6a0967 | 1443 | } |
1444 | else if (code == 'w') | |
1445 | { | |
108988a0 | 1446 | if (REGNO (x) == REG_A0 || REGNO (x) == REG_A1) |
1447 | fprintf (file, "%s.w", reg_names[REGNO (x)]); | |
1448 | else | |
1449 | output_operand_lossage ("invalid operand for code '%c'", code); | |
9e6a0967 | 1450 | } |
1451 | else if (code == 'x') | |
1452 | { | |
108988a0 | 1453 | if (REGNO (x) == REG_A0 || REGNO (x) == REG_A1) |
1454 | fprintf (file, "%s.x", reg_names[REGNO (x)]); | |
1455 | else | |
1456 | output_operand_lossage ("invalid operand for code '%c'", code); | |
9e6a0967 | 1457 | } |
a4317a50 | 1458 | else if (code == 'v') |
1459 | { | |
1460 | if (REGNO (x) == REG_A0) | |
1461 | fprintf (file, "AV0"); | |
1462 | else if (REGNO (x) == REG_A1) | |
1463 | fprintf (file, "AV1"); | |
1464 | else | |
1465 | output_operand_lossage ("invalid operand for code '%c'", code); | |
1466 | } | |
9e6a0967 | 1467 | else if (code == 'D') |
1468 | { | |
108988a0 | 1469 | if (D_REGNO_P (REGNO (x))) |
1470 | fprintf (file, "%s", dregs_pair_names[REGNO (x)]); | |
1471 | else | |
1472 | output_operand_lossage ("invalid operand for code '%c'", code); | |
9e6a0967 | 1473 | } |
1474 | else if (code == 'H') | |
1475 | { | |
108988a0 | 1476 | if ((mode == DImode || mode == DFmode) && REG_P (x)) |
1477 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); | |
1478 | else | |
1479 | output_operand_lossage ("invalid operand for code '%c'", code); | |
9e6a0967 | 1480 | } |
1481 | else if (code == 'T') | |
1482 | { | |
108988a0 | 1483 | if (D_REGNO_P (REGNO (x))) |
1484 | fprintf (file, "%s", byte_reg_names[REGNO (x)]); | |
1485 | else | |
1486 | output_operand_lossage ("invalid operand for code '%c'", code); | |
9e6a0967 | 1487 | } |
1488 | else | |
1489 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
1490 | break; | |
1491 | ||
1492 | case MEM: | |
1493 | fputc ('[', file); | |
1494 | x = XEXP (x,0); | |
1495 | print_address_operand (file, x); | |
1496 | fputc (']', file); | |
1497 | break; | |
1498 | ||
1499 | case CONST_INT: | |
0bdbecff | 1500 | if (code == 'M') |
1501 | { | |
1502 | switch (INTVAL (x)) | |
1503 | { | |
1504 | case MACFLAG_NONE: | |
1505 | break; | |
1506 | case MACFLAG_FU: | |
1507 | fputs ("(FU)", file); | |
1508 | break; | |
1509 | case MACFLAG_T: | |
1510 | fputs ("(T)", file); | |
1511 | break; | |
1512 | case MACFLAG_TFU: | |
1513 | fputs ("(TFU)", file); | |
1514 | break; | |
1515 | case MACFLAG_W32: | |
1516 | fputs ("(W32)", file); | |
1517 | break; | |
1518 | case MACFLAG_IS: | |
1519 | fputs ("(IS)", file); | |
1520 | break; | |
1521 | case MACFLAG_IU: | |
1522 | fputs ("(IU)", file); | |
1523 | break; | |
1524 | case MACFLAG_IH: | |
1525 | fputs ("(IH)", file); | |
1526 | break; | |
1527 | case MACFLAG_M: | |
1528 | fputs ("(M)", file); | |
1529 | break; | |
9422b03b | 1530 | case MACFLAG_IS_M: |
1531 | fputs ("(IS,M)", file); | |
1532 | break; | |
0bdbecff | 1533 | case MACFLAG_ISS2: |
1534 | fputs ("(ISS2)", file); | |
1535 | break; | |
1536 | case MACFLAG_S2RND: | |
1537 | fputs ("(S2RND)", file); | |
1538 | break; | |
1539 | default: | |
1540 | gcc_unreachable (); | |
1541 | } | |
1542 | break; | |
1543 | } | |
1544 | else if (code == 'b') | |
1545 | { | |
1546 | if (INTVAL (x) == 0) | |
1547 | fputs ("+=", file); | |
1548 | else if (INTVAL (x) == 1) | |
1549 | fputs ("-=", file); | |
1550 | else | |
1551 | gcc_unreachable (); | |
1552 | break; | |
1553 | } | |
9e6a0967 | 1554 | /* Moves to half registers with d or h modifiers always use unsigned |
1555 | constants. */ | |
0bdbecff | 1556 | else if (code == 'd') |
9e6a0967 | 1557 | x = GEN_INT ((INTVAL (x) >> 16) & 0xffff); |
1558 | else if (code == 'h') | |
1559 | x = GEN_INT (INTVAL (x) & 0xffff); | |
5af6d8d8 | 1560 | else if (code == 'N') |
1561 | x = GEN_INT (-INTVAL (x)); | |
9e6a0967 | 1562 | else if (code == 'X') |
1563 | x = GEN_INT (exact_log2 (0xffffffff & INTVAL (x))); | |
1564 | else if (code == 'Y') | |
1565 | x = GEN_INT (exact_log2 (0xffffffff & ~INTVAL (x))); | |
1566 | else if (code == 'Z') | |
1567 | /* Used for LINK insns. */ | |
1568 | x = GEN_INT (-8 - INTVAL (x)); | |
1569 | ||
1570 | /* fall through */ | |
1571 | ||
1572 | case SYMBOL_REF: | |
1573 | output_addr_const (file, x); | |
9e6a0967 | 1574 | break; |
1575 | ||
1576 | case CONST_DOUBLE: | |
1577 | output_operand_lossage ("invalid const_double operand"); | |
1578 | break; | |
1579 | ||
1580 | case UNSPEC: | |
2115ae11 | 1581 | switch (XINT (x, 1)) |
9e6a0967 | 1582 | { |
2115ae11 | 1583 | case UNSPEC_MOVE_PIC: |
9e6a0967 | 1584 | output_addr_const (file, XVECEXP (x, 0, 0)); |
1585 | fprintf (file, "@GOT"); | |
2115ae11 | 1586 | break; |
1587 | ||
55be0e32 | 1588 | case UNSPEC_MOVE_FDPIC: |
1589 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1590 | fprintf (file, "@GOT17M4"); | |
1591 | break; | |
1592 | ||
1593 | case UNSPEC_FUNCDESC_GOT17M4: | |
1594 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1595 | fprintf (file, "@FUNCDESC_GOT17M4"); | |
1596 | break; | |
1597 | ||
2115ae11 | 1598 | case UNSPEC_LIBRARY_OFFSET: |
1599 | fprintf (file, "_current_shared_library_p5_offset_"); | |
1600 | break; | |
1601 | ||
1602 | default: | |
1603 | gcc_unreachable (); | |
9e6a0967 | 1604 | } |
9e6a0967 | 1605 | break; |
1606 | ||
1607 | default: | |
1608 | output_addr_const (file, x); | |
1609 | } | |
1610 | } | |
1611 | } | |
1612 | \f | |
1613 | /* Argument support functions. */ | |
1614 | ||
1615 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1616 | for a call to a function whose data type is FNTYPE. | |
1617 | For a library call, FNTYPE is 0. | |
1618 | VDSP C Compiler manual, our ABI says that | |
1619 | first 3 words of arguments will use R0, R1 and R2. | |
1620 | */ | |
1621 | ||
1622 | void | |
7b6ef6dd | 1623 | init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, |
9e6a0967 | 1624 | rtx libname ATTRIBUTE_UNUSED) |
1625 | { | |
1626 | static CUMULATIVE_ARGS zero_cum; | |
1627 | ||
1628 | *cum = zero_cum; | |
1629 | ||
1630 | /* Set up the number of registers to use for passing arguments. */ | |
1631 | ||
1632 | cum->nregs = max_arg_registers; | |
1633 | cum->arg_regs = arg_regs; | |
1634 | ||
7b6ef6dd | 1635 | cum->call_cookie = CALL_NORMAL; |
1636 | /* Check for a longcall attribute. */ | |
1637 | if (fntype && lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))) | |
1638 | cum->call_cookie |= CALL_SHORT; | |
1639 | else if (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))) | |
1640 | cum->call_cookie |= CALL_LONG; | |
1641 | ||
9e6a0967 | 1642 | return; |
1643 | } | |
1644 | ||
1645 | /* Update the data in CUM to advance over an argument | |
1646 | of mode MODE and data type TYPE. | |
1647 | (TYPE is null for libcalls where that information may not be available.) */ | |
1648 | ||
d8882c2e | 1649 | static void |
1650 | bfin_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
1651 | const_tree type, bool named ATTRIBUTE_UNUSED) | |
9e6a0967 | 1652 | { |
1653 | int count, bytes, words; | |
1654 | ||
1655 | bytes = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); | |
1656 | words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
1657 | ||
1658 | cum->words += words; | |
1659 | cum->nregs -= words; | |
1660 | ||
1661 | if (cum->nregs <= 0) | |
1662 | { | |
1663 | cum->nregs = 0; | |
1664 | cum->arg_regs = NULL; | |
1665 | } | |
1666 | else | |
1667 | { | |
1668 | for (count = 1; count <= words; count++) | |
1669 | cum->arg_regs++; | |
1670 | } | |
1671 | ||
1672 | return; | |
1673 | } | |
1674 | ||
1675 | /* Define where to put the arguments to a function. | |
1676 | Value is zero to push the argument on the stack, | |
1677 | or a hard register in which to store the argument. | |
1678 | ||
1679 | MODE is the argument's machine mode. | |
1680 | TYPE is the data type of the argument (as a tree). | |
1681 | This is null for libcalls where that information may | |
1682 | not be available. | |
1683 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1684 | the preceding args and about the function being called. | |
1685 | NAMED is nonzero if this argument is a named parameter | |
1686 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1687 | ||
d8882c2e | 1688 | static rtx |
1689 | bfin_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
1690 | const_tree type, bool named ATTRIBUTE_UNUSED) | |
9e6a0967 | 1691 | { |
1692 | int bytes | |
1693 | = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); | |
1694 | ||
7b6ef6dd | 1695 | if (mode == VOIDmode) |
1696 | /* Compute operand 2 of the call insn. */ | |
1697 | return GEN_INT (cum->call_cookie); | |
1698 | ||
9e6a0967 | 1699 | if (bytes == -1) |
1700 | return NULL_RTX; | |
1701 | ||
1702 | if (cum->nregs) | |
1703 | return gen_rtx_REG (mode, *(cum->arg_regs)); | |
1704 | ||
1705 | return NULL_RTX; | |
1706 | } | |
1707 | ||
1708 | /* For an arg passed partly in registers and partly in memory, | |
1709 | this is the number of bytes passed in registers. | |
1710 | For args passed entirely in registers or entirely in memory, zero. | |
1711 | ||
1712 | Refer VDSP C Compiler manual, our ABI. | |
85694bac | 1713 | First 3 words are in registers. So, if an argument is larger |
9e6a0967 | 1714 | than the registers available, it will span the register and |
1715 | stack. */ | |
1716 | ||
1717 | static int | |
1718 | bfin_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
1719 | tree type ATTRIBUTE_UNUSED, | |
1720 | bool named ATTRIBUTE_UNUSED) | |
1721 | { | |
1722 | int bytes | |
1723 | = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); | |
1724 | int bytes_left = cum->nregs * UNITS_PER_WORD; | |
1725 | ||
1726 | if (bytes == -1) | |
1727 | return 0; | |
1728 | ||
1729 | if (bytes_left == 0) | |
1730 | return 0; | |
1731 | if (bytes > bytes_left) | |
1732 | return bytes_left; | |
1733 | return 0; | |
1734 | } | |
1735 | ||
1736 | /* Variable sized types are passed by reference. */ | |
1737 | ||
1738 | static bool | |
1739 | bfin_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, | |
1740 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
fb80456a | 1741 | const_tree type, bool named ATTRIBUTE_UNUSED) |
9e6a0967 | 1742 | { |
1743 | return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST; | |
1744 | } | |
1745 | ||
1746 | /* Decide whether a type should be returned in memory (true) | |
1747 | or in a register (false). This is called by the macro | |
22c61100 | 1748 | TARGET_RETURN_IN_MEMORY. */ |
9e6a0967 | 1749 | |
0a619688 | 1750 | static bool |
22c61100 | 1751 | bfin_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
9e6a0967 | 1752 | { |
8683c45f | 1753 | int size = int_size_in_bytes (type); |
1754 | return size > 2 * UNITS_PER_WORD || size == -1; | |
9e6a0967 | 1755 | } |
1756 | ||
1757 | /* Register in which address to store a structure value | |
1758 | is passed to a function. */ | |
1759 | static rtx | |
1760 | bfin_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
1761 | int incoming ATTRIBUTE_UNUSED) | |
1762 | { | |
1763 | return gen_rtx_REG (Pmode, REG_P0); | |
1764 | } | |
1765 | ||
1766 | /* Return true when register may be used to pass function parameters. */ | |
1767 | ||
1768 | bool | |
1769 | function_arg_regno_p (int n) | |
1770 | { | |
1771 | int i; | |
1772 | for (i = 0; arg_regs[i] != -1; i++) | |
1773 | if (n == arg_regs[i]) | |
1774 | return true; | |
1775 | return false; | |
1776 | } | |
1777 | ||
1778 | /* Returns 1 if OP contains a symbol reference */ | |
1779 | ||
1780 | int | |
1781 | symbolic_reference_mentioned_p (rtx op) | |
1782 | { | |
1783 | register const char *fmt; | |
1784 | register int i; | |
1785 | ||
1786 | if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF) | |
1787 | return 1; | |
1788 | ||
1789 | fmt = GET_RTX_FORMAT (GET_CODE (op)); | |
1790 | for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--) | |
1791 | { | |
1792 | if (fmt[i] == 'E') | |
1793 | { | |
1794 | register int j; | |
1795 | ||
1796 | for (j = XVECLEN (op, i) - 1; j >= 0; j--) | |
1797 | if (symbolic_reference_mentioned_p (XVECEXP (op, i, j))) | |
1798 | return 1; | |
1799 | } | |
1800 | ||
1801 | else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i))) | |
1802 | return 1; | |
1803 | } | |
1804 | ||
1805 | return 0; | |
1806 | } | |
1807 | ||
1808 | /* Decide whether we can make a sibling call to a function. DECL is the | |
1809 | declaration of the function being targeted by the call and EXP is the | |
1810 | CALL_EXPR representing the call. */ | |
1811 | ||
1812 | static bool | |
1813 | bfin_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED, | |
1814 | tree exp ATTRIBUTE_UNUSED) | |
1815 | { | |
6329636b | 1816 | struct cgraph_local_info *this_func, *called_func; |
345458f3 | 1817 | e_funkind fkind = funkind (TREE_TYPE (current_function_decl)); |
f9ecc035 | 1818 | if (fkind != SUBROUTINE) |
1819 | return false; | |
1820 | if (!TARGET_ID_SHARED_LIBRARY || TARGET_SEP_DATA) | |
1821 | return true; | |
1822 | ||
1823 | /* When compiling for ID shared libraries, can't sibcall a local function | |
1824 | from a non-local function, because the local function thinks it does | |
1825 | not need to reload P5 in the prologue, but the sibcall wil pop P5 in the | |
1826 | sibcall epilogue, and we end up with the wrong value in P5. */ | |
1827 | ||
e5f223f4 | 1828 | if (!decl) |
1829 | /* Not enough information. */ | |
1830 | return false; | |
f9ecc035 | 1831 | |
6329636b | 1832 | this_func = cgraph_local_info (current_function_decl); |
1833 | called_func = cgraph_local_info (decl); | |
f0090234 | 1834 | if (!called_func) |
1835 | return false; | |
6329636b | 1836 | return !called_func->local || this_func->local; |
9e6a0967 | 1837 | } |
1838 | \f | |
eeae9f72 | 1839 | /* Write a template for a trampoline to F. */ |
1840 | ||
1841 | static void | |
1842 | bfin_asm_trampoline_template (FILE *f) | |
1843 | { | |
1844 | if (TARGET_FDPIC) | |
1845 | { | |
1846 | fprintf (f, "\t.dd\t0x00000000\n"); /* 0 */ | |
1847 | fprintf (f, "\t.dd\t0x00000000\n"); /* 0 */ | |
1848 | fprintf (f, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ | |
1849 | fprintf (f, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ | |
1850 | fprintf (f, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ | |
1851 | fprintf (f, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ | |
1852 | fprintf (f, "\t.dw\t0xac4b\n"); /* p3 = [p1 + 4] */ | |
1853 | fprintf (f, "\t.dw\t0x9149\n"); /* p1 = [p1] */ | |
1854 | fprintf (f, "\t.dw\t0x0051\n"); /* jump (p1)*/ | |
1855 | } | |
1856 | else | |
1857 | { | |
1858 | fprintf (f, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ | |
1859 | fprintf (f, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ | |
1860 | fprintf (f, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ | |
1861 | fprintf (f, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ | |
1862 | fprintf (f, "\t.dw\t0x0051\n"); /* jump (p1)*/ | |
1863 | } | |
1864 | } | |
1865 | ||
9e6a0967 | 1866 | /* Emit RTL insns to initialize the variable parts of a trampoline at |
eeae9f72 | 1867 | M_TRAMP. FNDECL is the target function. CHAIN_VALUE is an RTX for |
1868 | the static chain value for the function. */ | |
9e6a0967 | 1869 | |
eeae9f72 | 1870 | static void |
1871 | bfin_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
9e6a0967 | 1872 | { |
eeae9f72 | 1873 | rtx t1 = copy_to_reg (XEXP (DECL_RTL (fndecl), 0)); |
1874 | rtx t2 = copy_to_reg (chain_value); | |
1875 | rtx mem; | |
55be0e32 | 1876 | int i = 0; |
1877 | ||
eeae9f72 | 1878 | emit_block_move (m_tramp, assemble_trampoline_template (), |
1879 | GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); | |
1880 | ||
55be0e32 | 1881 | if (TARGET_FDPIC) |
1882 | { | |
eeae9f72 | 1883 | rtx a = force_reg (Pmode, plus_constant (XEXP (m_tramp, 0), 8)); |
1884 | mem = adjust_address (m_tramp, Pmode, 0); | |
1885 | emit_move_insn (mem, a); | |
55be0e32 | 1886 | i = 8; |
1887 | } | |
9e6a0967 | 1888 | |
eeae9f72 | 1889 | mem = adjust_address (m_tramp, HImode, i + 2); |
1890 | emit_move_insn (mem, gen_lowpart (HImode, t1)); | |
9e6a0967 | 1891 | emit_insn (gen_ashrsi3 (t1, t1, GEN_INT (16))); |
eeae9f72 | 1892 | mem = adjust_address (m_tramp, HImode, i + 6); |
1893 | emit_move_insn (mem, gen_lowpart (HImode, t1)); | |
9e6a0967 | 1894 | |
eeae9f72 | 1895 | mem = adjust_address (m_tramp, HImode, i + 10); |
1896 | emit_move_insn (mem, gen_lowpart (HImode, t2)); | |
9e6a0967 | 1897 | emit_insn (gen_ashrsi3 (t2, t2, GEN_INT (16))); |
eeae9f72 | 1898 | mem = adjust_address (m_tramp, HImode, i + 14); |
1899 | emit_move_insn (mem, gen_lowpart (HImode, t2)); | |
9e6a0967 | 1900 | } |
1901 | ||
9e6a0967 | 1902 | /* Emit insns to move operands[1] into operands[0]. */ |
1903 | ||
1904 | void | |
1905 | emit_pic_move (rtx *operands, enum machine_mode mode ATTRIBUTE_UNUSED) | |
1906 | { | |
1907 | rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); | |
1908 | ||
55be0e32 | 1909 | gcc_assert (!TARGET_FDPIC || !(reload_in_progress || reload_completed)); |
9e6a0967 | 1910 | if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1])) |
1911 | operands[1] = force_reg (SImode, operands[1]); | |
1912 | else | |
b90ce3c3 | 1913 | operands[1] = legitimize_pic_address (operands[1], temp, |
55be0e32 | 1914 | TARGET_FDPIC ? OUR_FDPIC_REG |
1915 | : pic_offset_table_rtx); | |
9e6a0967 | 1916 | } |
1917 | ||
cf63c743 | 1918 | /* Expand a move operation in mode MODE. The operands are in OPERANDS. |
1919 | Returns true if no further code must be generated, false if the caller | |
1920 | should generate an insn to move OPERANDS[1] to OPERANDS[0]. */ | |
9e6a0967 | 1921 | |
cf63c743 | 1922 | bool |
9e6a0967 | 1923 | expand_move (rtx *operands, enum machine_mode mode) |
1924 | { | |
55be0e32 | 1925 | rtx op = operands[1]; |
1926 | if ((TARGET_ID_SHARED_LIBRARY || TARGET_FDPIC) | |
1927 | && SYMBOLIC_CONST (op)) | |
9e6a0967 | 1928 | emit_pic_move (operands, mode); |
cf63c743 | 1929 | else if (mode == SImode && GET_CODE (op) == CONST |
1930 | && GET_CODE (XEXP (op, 0)) == PLUS | |
1931 | && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF | |
ca316360 | 1932 | && !targetm.legitimate_constant_p (mode, op)) |
cf63c743 | 1933 | { |
1934 | rtx dest = operands[0]; | |
1935 | rtx op0, op1; | |
1936 | gcc_assert (!reload_in_progress && !reload_completed); | |
1937 | op = XEXP (op, 0); | |
1938 | op0 = force_reg (mode, XEXP (op, 0)); | |
1939 | op1 = XEXP (op, 1); | |
1940 | if (!insn_data[CODE_FOR_addsi3].operand[2].predicate (op1, mode)) | |
1941 | op1 = force_reg (mode, op1); | |
1942 | if (GET_CODE (dest) == MEM) | |
1943 | dest = gen_reg_rtx (mode); | |
1944 | emit_insn (gen_addsi3 (dest, op0, op1)); | |
1945 | if (dest == operands[0]) | |
1946 | return true; | |
1947 | operands[1] = dest; | |
1948 | } | |
9e6a0967 | 1949 | /* Don't generate memory->memory or constant->memory moves, go through a |
1950 | register */ | |
1951 | else if ((reload_in_progress | reload_completed) == 0 | |
1952 | && GET_CODE (operands[0]) == MEM | |
1953 | && GET_CODE (operands[1]) != REG) | |
1954 | operands[1] = force_reg (mode, operands[1]); | |
cf63c743 | 1955 | return false; |
9e6a0967 | 1956 | } |
1957 | \f | |
1958 | /* Split one or more DImode RTL references into pairs of SImode | |
1959 | references. The RTL can be REG, offsettable MEM, integer constant, or | |
1960 | CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to | |
1961 | split and "num" is its length. lo_half and hi_half are output arrays | |
1962 | that parallel "operands". */ | |
1963 | ||
1964 | void | |
1965 | split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[]) | |
1966 | { | |
1967 | while (num--) | |
1968 | { | |
1969 | rtx op = operands[num]; | |
1970 | ||
1971 | /* simplify_subreg refuse to split volatile memory addresses, | |
1972 | but we still have to handle it. */ | |
1973 | if (GET_CODE (op) == MEM) | |
1974 | { | |
1975 | lo_half[num] = adjust_address (op, SImode, 0); | |
1976 | hi_half[num] = adjust_address (op, SImode, 4); | |
1977 | } | |
1978 | else | |
1979 | { | |
1980 | lo_half[num] = simplify_gen_subreg (SImode, op, | |
1981 | GET_MODE (op) == VOIDmode | |
1982 | ? DImode : GET_MODE (op), 0); | |
1983 | hi_half[num] = simplify_gen_subreg (SImode, op, | |
1984 | GET_MODE (op) == VOIDmode | |
1985 | ? DImode : GET_MODE (op), 4); | |
1986 | } | |
1987 | } | |
1988 | } | |
1989 | \f | |
7b6ef6dd | 1990 | bool |
1991 | bfin_longcall_p (rtx op, int call_cookie) | |
1992 | { | |
1993 | gcc_assert (GET_CODE (op) == SYMBOL_REF); | |
e29b2b97 | 1994 | if (SYMBOL_REF_WEAK (op)) |
1995 | return 1; | |
7b6ef6dd | 1996 | if (call_cookie & CALL_SHORT) |
1997 | return 0; | |
1998 | if (call_cookie & CALL_LONG) | |
1999 | return 1; | |
2000 | if (TARGET_LONG_CALLS) | |
2001 | return 1; | |
2002 | return 0; | |
2003 | } | |
2004 | ||
9e6a0967 | 2005 | /* Expand a call instruction. FNADDR is the call target, RETVAL the return value. |
7b6ef6dd | 2006 | COOKIE is a CONST_INT holding the call_cookie prepared init_cumulative_args. |
9e6a0967 | 2007 | SIBCALL is nonzero if this is a sibling call. */ |
2008 | ||
2009 | void | |
7b6ef6dd | 2010 | bfin_expand_call (rtx retval, rtx fnaddr, rtx callarg1, rtx cookie, int sibcall) |
9e6a0967 | 2011 | { |
2012 | rtx use = NULL, call; | |
7b6ef6dd | 2013 | rtx callee = XEXP (fnaddr, 0); |
4bb5cea5 | 2014 | int nelts = 3; |
55be0e32 | 2015 | rtx pat; |
2016 | rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REGNO); | |
4bb5cea5 | 2017 | rtx retsreg = gen_rtx_REG (Pmode, REG_RETS); |
55be0e32 | 2018 | int n; |
7b6ef6dd | 2019 | |
2020 | /* In an untyped call, we can get NULL for operand 2. */ | |
2021 | if (cookie == NULL_RTX) | |
2022 | cookie = const0_rtx; | |
9e6a0967 | 2023 | |
2024 | /* Static functions and indirect calls don't need the pic register. */ | |
55be0e32 | 2025 | if (!TARGET_FDPIC && flag_pic |
7b6ef6dd | 2026 | && GET_CODE (callee) == SYMBOL_REF |
2027 | && !SYMBOL_REF_LOCAL_P (callee)) | |
9e6a0967 | 2028 | use_reg (&use, pic_offset_table_rtx); |
2029 | ||
55be0e32 | 2030 | if (TARGET_FDPIC) |
2031 | { | |
aba5356f | 2032 | int caller_in_sram, callee_in_sram; |
fc8aef7f | 2033 | |
aba5356f | 2034 | /* 0 is not in sram, 1 is in L1 sram, 2 is in L2 sram. */ |
2035 | caller_in_sram = callee_in_sram = 0; | |
fc8aef7f | 2036 | |
2037 | if (lookup_attribute ("l1_text", | |
2038 | DECL_ATTRIBUTES (cfun->decl)) != NULL_TREE) | |
aba5356f | 2039 | caller_in_sram = 1; |
2040 | else if (lookup_attribute ("l2", | |
2041 | DECL_ATTRIBUTES (cfun->decl)) != NULL_TREE) | |
2042 | caller_in_sram = 2; | |
fc8aef7f | 2043 | |
2044 | if (GET_CODE (callee) == SYMBOL_REF | |
aba5356f | 2045 | && SYMBOL_REF_DECL (callee) && DECL_P (SYMBOL_REF_DECL (callee))) |
2046 | { | |
2047 | if (lookup_attribute | |
2048 | ("l1_text", | |
2049 | DECL_ATTRIBUTES (SYMBOL_REF_DECL (callee))) != NULL_TREE) | |
2050 | callee_in_sram = 1; | |
2051 | else if (lookup_attribute | |
2052 | ("l2", | |
2053 | DECL_ATTRIBUTES (SYMBOL_REF_DECL (callee))) != NULL_TREE) | |
2054 | callee_in_sram = 2; | |
2055 | } | |
fc8aef7f | 2056 | |
55be0e32 | 2057 | if (GET_CODE (callee) != SYMBOL_REF |
f4ec07e4 | 2058 | || bfin_longcall_p (callee, INTVAL (cookie)) |
2059 | || (GET_CODE (callee) == SYMBOL_REF | |
2060 | && !SYMBOL_REF_LOCAL_P (callee) | |
fc8aef7f | 2061 | && TARGET_INLINE_PLT) |
aba5356f | 2062 | || caller_in_sram != callee_in_sram |
2063 | || (caller_in_sram && callee_in_sram | |
fc8aef7f | 2064 | && (GET_CODE (callee) != SYMBOL_REF |
2065 | || !SYMBOL_REF_LOCAL_P (callee)))) | |
55be0e32 | 2066 | { |
2067 | rtx addr = callee; | |
2068 | if (! address_operand (addr, Pmode)) | |
2069 | addr = force_reg (Pmode, addr); | |
2070 | ||
2071 | fnaddr = gen_reg_rtx (SImode); | |
2072 | emit_insn (gen_load_funcdescsi (fnaddr, addr)); | |
2073 | fnaddr = gen_rtx_MEM (Pmode, fnaddr); | |
2074 | ||
2075 | picreg = gen_reg_rtx (SImode); | |
2076 | emit_insn (gen_load_funcdescsi (picreg, | |
2077 | plus_constant (addr, 4))); | |
2078 | } | |
2079 | ||
2080 | nelts++; | |
2081 | } | |
2082 | else if ((!register_no_elim_operand (callee, Pmode) | |
2083 | && GET_CODE (callee) != SYMBOL_REF) | |
2084 | || (GET_CODE (callee) == SYMBOL_REF | |
40831b00 | 2085 | && ((TARGET_ID_SHARED_LIBRARY && !TARGET_LEAF_ID_SHARED_LIBRARY) |
55be0e32 | 2086 | || bfin_longcall_p (callee, INTVAL (cookie))))) |
9e6a0967 | 2087 | { |
7b6ef6dd | 2088 | callee = copy_to_mode_reg (Pmode, callee); |
2089 | fnaddr = gen_rtx_MEM (Pmode, callee); | |
9e6a0967 | 2090 | } |
2091 | call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1); | |
2092 | ||
2093 | if (retval) | |
2094 | call = gen_rtx_SET (VOIDmode, retval, call); | |
7b6ef6dd | 2095 | |
55be0e32 | 2096 | pat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nelts)); |
2097 | n = 0; | |
2098 | XVECEXP (pat, 0, n++) = call; | |
2099 | if (TARGET_FDPIC) | |
2100 | XVECEXP (pat, 0, n++) = gen_rtx_USE (VOIDmode, picreg); | |
2101 | XVECEXP (pat, 0, n++) = gen_rtx_USE (VOIDmode, cookie); | |
9e6a0967 | 2102 | if (sibcall) |
1a860023 | 2103 | XVECEXP (pat, 0, n++) = ret_rtx; |
4bb5cea5 | 2104 | else |
2105 | XVECEXP (pat, 0, n++) = gen_rtx_CLOBBER (VOIDmode, retsreg); | |
7b6ef6dd | 2106 | call = emit_call_insn (pat); |
9e6a0967 | 2107 | if (use) |
2108 | CALL_INSN_FUNCTION_USAGE (call) = use; | |
2109 | } | |
2110 | \f | |
2111 | /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */ | |
2112 | ||
2113 | int | |
2114 | hard_regno_mode_ok (int regno, enum machine_mode mode) | |
2115 | { | |
2116 | /* Allow only dregs to store value of mode HI or QI */ | |
8deb3959 | 2117 | enum reg_class rclass = REGNO_REG_CLASS (regno); |
9e6a0967 | 2118 | |
2119 | if (mode == CCmode) | |
2120 | return 0; | |
2121 | ||
2122 | if (mode == V2HImode) | |
2123 | return D_REGNO_P (regno); | |
8deb3959 | 2124 | if (rclass == CCREGS) |
9e6a0967 | 2125 | return mode == BImode; |
0bdbecff | 2126 | if (mode == PDImode || mode == V2PDImode) |
9e6a0967 | 2127 | return regno == REG_A0 || regno == REG_A1; |
cd36b2c0 | 2128 | |
905ea169 | 2129 | /* Allow all normal 32-bit regs, except REG_M3, in case regclass ever comes |
cd36b2c0 | 2130 | up with a bad register class (such as ALL_REGS) for DImode. */ |
2131 | if (mode == DImode) | |
2132 | return regno < REG_M3; | |
2133 | ||
9e6a0967 | 2134 | if (mode == SImode |
2135 | && TEST_HARD_REG_BIT (reg_class_contents[PROLOGUE_REGS], regno)) | |
2136 | return 1; | |
cd36b2c0 | 2137 | |
9e6a0967 | 2138 | return TEST_HARD_REG_BIT (reg_class_contents[MOST_REGS], regno); |
2139 | } | |
2140 | ||
2141 | /* Implements target hook vector_mode_supported_p. */ | |
2142 | ||
2143 | static bool | |
2144 | bfin_vector_mode_supported_p (enum machine_mode mode) | |
2145 | { | |
2146 | return mode == V2HImode; | |
2147 | } | |
2148 | ||
2149 | /* Return the cost of moving data from a register in class CLASS1 to | |
2150 | one in class CLASS2. A cost of 2 is the default. */ | |
2151 | ||
2152 | int | |
cd36b2c0 | 2153 | bfin_register_move_cost (enum machine_mode mode, |
9e6a0967 | 2154 | enum reg_class class1, enum reg_class class2) |
2155 | { | |
622e3203 | 2156 | /* These need secondary reloads, so they're more expensive. */ |
101deac5 | 2157 | if ((class1 == CCREGS && !reg_class_subset_p (class2, DREGS)) |
2158 | || (class2 == CCREGS && !reg_class_subset_p (class1, DREGS))) | |
622e3203 | 2159 | return 4; |
2160 | ||
9e6a0967 | 2161 | /* If optimizing for size, always prefer reg-reg over reg-memory moves. */ |
2162 | if (optimize_size) | |
2163 | return 2; | |
2164 | ||
cd36b2c0 | 2165 | if (GET_MODE_CLASS (mode) == MODE_INT) |
2166 | { | |
2167 | /* Discourage trying to use the accumulators. */ | |
2168 | if (TEST_HARD_REG_BIT (reg_class_contents[class1], REG_A0) | |
2169 | || TEST_HARD_REG_BIT (reg_class_contents[class1], REG_A1) | |
2170 | || TEST_HARD_REG_BIT (reg_class_contents[class2], REG_A0) | |
2171 | || TEST_HARD_REG_BIT (reg_class_contents[class2], REG_A1)) | |
2172 | return 20; | |
2173 | } | |
9e6a0967 | 2174 | return 2; |
2175 | } | |
2176 | ||
2177 | /* Return the cost of moving data of mode M between a | |
2178 | register and memory. A value of 2 is the default; this cost is | |
2179 | relative to those in `REGISTER_MOVE_COST'. | |
2180 | ||
2181 | ??? In theory L1 memory has single-cycle latency. We should add a switch | |
2182 | that tells the compiler whether we expect to use only L1 memory for the | |
2183 | program; it'll make the costs more accurate. */ | |
2184 | ||
2185 | int | |
2186 | bfin_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, | |
8deb3959 | 2187 | enum reg_class rclass, |
9e6a0967 | 2188 | int in ATTRIBUTE_UNUSED) |
2189 | { | |
2190 | /* Make memory accesses slightly more expensive than any register-register | |
2191 | move. Also, penalize non-DP registers, since they need secondary | |
2192 | reloads to load and store. */ | |
8deb3959 | 2193 | if (! reg_class_subset_p (rclass, DPREGS)) |
9e6a0967 | 2194 | return 10; |
2195 | ||
2196 | return 8; | |
2197 | } | |
2198 | ||
2199 | /* Inform reload about cases where moving X with a mode MODE to a register in | |
8deb3959 | 2200 | RCLASS requires an extra scratch register. Return the class needed for the |
9e6a0967 | 2201 | scratch register. */ |
2202 | ||
964229b7 | 2203 | static reg_class_t |
2204 | bfin_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, | |
e99611da | 2205 | enum machine_mode mode, secondary_reload_info *sri) |
9e6a0967 | 2206 | { |
2207 | /* If we have HImode or QImode, we can only use DREGS as secondary registers; | |
2208 | in most other cases we can also use PREGS. */ | |
2209 | enum reg_class default_class = GET_MODE_SIZE (mode) >= 4 ? DPREGS : DREGS; | |
2210 | enum reg_class x_class = NO_REGS; | |
2211 | enum rtx_code code = GET_CODE (x); | |
964229b7 | 2212 | enum reg_class rclass = (enum reg_class) rclass_i; |
9e6a0967 | 2213 | |
2214 | if (code == SUBREG) | |
2215 | x = SUBREG_REG (x), code = GET_CODE (x); | |
2216 | if (REG_P (x)) | |
2217 | { | |
2218 | int regno = REGNO (x); | |
2219 | if (regno >= FIRST_PSEUDO_REGISTER) | |
2220 | regno = reg_renumber[regno]; | |
2221 | ||
2222 | if (regno == -1) | |
2223 | code = MEM; | |
2224 | else | |
2225 | x_class = REGNO_REG_CLASS (regno); | |
2226 | } | |
2227 | ||
2228 | /* We can be asked to reload (plus (FP) (large_constant)) into a DREG. | |
2229 | This happens as a side effect of register elimination, and we need | |
2230 | a scratch register to do it. */ | |
2231 | if (fp_plus_const_operand (x, mode)) | |
2232 | { | |
2233 | rtx op2 = XEXP (x, 1); | |
87943377 | 2234 | int large_constant_p = ! satisfies_constraint_Ks7 (op2); |
9e6a0967 | 2235 | |
8deb3959 | 2236 | if (rclass == PREGS || rclass == PREGS_CLOBBERED) |
9e6a0967 | 2237 | return NO_REGS; |
2238 | /* If destination is a DREG, we can do this without a scratch register | |
2239 | if the constant is valid for an add instruction. */ | |
8deb3959 | 2240 | if ((rclass == DREGS || rclass == DPREGS) |
88eaee2d | 2241 | && ! large_constant_p) |
2242 | return NO_REGS; | |
9e6a0967 | 2243 | /* Reloading to anything other than a DREG? Use a PREG scratch |
2244 | register. */ | |
88eaee2d | 2245 | sri->icode = CODE_FOR_reload_insi; |
2246 | return NO_REGS; | |
9e6a0967 | 2247 | } |
2248 | ||
2249 | /* Data can usually be moved freely between registers of most classes. | |
2250 | AREGS are an exception; they can only move to or from another register | |
2251 | in AREGS or one in DREGS. They can also be assigned the constant 0. */ | |
9422b03b | 2252 | if (x_class == AREGS || x_class == EVEN_AREGS || x_class == ODD_AREGS) |
8deb3959 | 2253 | return (rclass == DREGS || rclass == AREGS || rclass == EVEN_AREGS |
2254 | || rclass == ODD_AREGS | |
9422b03b | 2255 | ? NO_REGS : DREGS); |
9e6a0967 | 2256 | |
8deb3959 | 2257 | if (rclass == AREGS || rclass == EVEN_AREGS || rclass == ODD_AREGS) |
9e6a0967 | 2258 | { |
e99611da | 2259 | if (code == MEM) |
2260 | { | |
2261 | sri->icode = in_p ? CODE_FOR_reload_inpdi : CODE_FOR_reload_outpdi; | |
2262 | return NO_REGS; | |
2263 | } | |
2264 | ||
9e6a0967 | 2265 | if (x != const0_rtx && x_class != DREGS) |
e99611da | 2266 | { |
2267 | return DREGS; | |
2268 | } | |
9e6a0967 | 2269 | else |
2270 | return NO_REGS; | |
2271 | } | |
2272 | ||
2273 | /* CCREGS can only be moved from/to DREGS. */ | |
8deb3959 | 2274 | if (rclass == CCREGS && x_class != DREGS) |
9e6a0967 | 2275 | return DREGS; |
8deb3959 | 2276 | if (x_class == CCREGS && rclass != DREGS) |
9e6a0967 | 2277 | return DREGS; |
622e3203 | 2278 | |
9e6a0967 | 2279 | /* All registers other than AREGS can load arbitrary constants. The only |
2280 | case that remains is MEM. */ | |
2281 | if (code == MEM) | |
8deb3959 | 2282 | if (! reg_class_subset_p (rclass, default_class)) |
9e6a0967 | 2283 | return default_class; |
e99611da | 2284 | |
9e6a0967 | 2285 | return NO_REGS; |
2286 | } | |
877af69b | 2287 | |
2288 | /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */ | |
2289 | ||
2290 | static bool | |
2291 | bfin_class_likely_spilled_p (reg_class_t rclass) | |
2292 | { | |
2293 | switch (rclass) | |
2294 | { | |
2295 | case PREGS_CLOBBERED: | |
2296 | case PROLOGUE_REGS: | |
2297 | case P0REGS: | |
2298 | case D0REGS: | |
2299 | case D1REGS: | |
2300 | case D2REGS: | |
2301 | case CCREGS: | |
2302 | return true; | |
2303 | ||
2304 | default: | |
2305 | break; | |
2306 | } | |
2307 | ||
2308 | return false; | |
2309 | } | |
9e6a0967 | 2310 | \f |
3c1905a4 | 2311 | static struct machine_function * |
2312 | bfin_init_machine_status (void) | |
2313 | { | |
ba72912a | 2314 | return ggc_alloc_cleared_machine_function (); |
3c1905a4 | 2315 | } |
2316 | ||
4c834714 | 2317 | /* Implement the TARGET_OPTION_OVERRIDE hook. */ |
9e6a0967 | 2318 | |
4c834714 | 2319 | static void |
2320 | bfin_option_override (void) | |
9e6a0967 | 2321 | { |
cfef164f | 2322 | /* If processor type is not specified, enable all workarounds. */ |
2323 | if (bfin_cpu_type == BFIN_CPU_UNKNOWN) | |
2324 | { | |
2325 | int i; | |
2326 | ||
2327 | for (i = 0; bfin_cpus[i].name != NULL; i++) | |
2328 | bfin_workarounds |= bfin_cpus[i].workarounds; | |
2329 | ||
2330 | bfin_si_revision = 0xffff; | |
2331 | } | |
2332 | ||
709b2de5 | 2333 | if (bfin_csync_anomaly == 1) |
2334 | bfin_workarounds |= WA_SPECULATIVE_SYNCS; | |
2335 | else if (bfin_csync_anomaly == 0) | |
2336 | bfin_workarounds &= ~WA_SPECULATIVE_SYNCS; | |
2337 | ||
2338 | if (bfin_specld_anomaly == 1) | |
2339 | bfin_workarounds |= WA_SPECULATIVE_LOADS; | |
2340 | else if (bfin_specld_anomaly == 0) | |
2341 | bfin_workarounds &= ~WA_SPECULATIVE_LOADS; | |
2342 | ||
9e6a0967 | 2343 | if (TARGET_OMIT_LEAF_FRAME_POINTER) |
2344 | flag_omit_frame_pointer = 1; | |
2345 | ||
a581fd25 | 2346 | #ifdef SUBTARGET_FDPIC_NOT_SUPPORTED |
2347 | if (TARGET_FDPIC) | |
2348 | error ("-mfdpic is not supported, please use a bfin-linux-uclibc target"); | |
2349 | #endif | |
2350 | ||
9e6a0967 | 2351 | /* Library identification */ |
33c9a3e7 | 2352 | if (global_options_set.x_bfin_library_id && ! TARGET_ID_SHARED_LIBRARY) |
f2a5d439 | 2353 | error ("-mshared-library-id= specified without -mid-shared-library"); |
9e6a0967 | 2354 | |
274c4c98 | 2355 | if (stack_limit_rtx && TARGET_FDPIC) |
2356 | { | |
2357 | warning (0, "-fstack-limit- options are ignored with -mfdpic; use -mstack-check-l1"); | |
2358 | stack_limit_rtx = NULL_RTX; | |
2359 | } | |
2360 | ||
6295e560 | 2361 | if (stack_limit_rtx && TARGET_STACK_CHECK_L1) |
bf776685 | 2362 | error ("can%'t use multiple stack checking methods together"); |
6295e560 | 2363 | |
55be0e32 | 2364 | if (TARGET_ID_SHARED_LIBRARY && TARGET_FDPIC) |
bf776685 | 2365 | error ("ID shared libraries and FD-PIC mode can%'t be used together"); |
55be0e32 | 2366 | |
40831b00 | 2367 | /* Don't allow the user to specify -mid-shared-library and -msep-data |
2368 | together, as it makes little sense from a user's point of view... */ | |
2369 | if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY) | |
2370 | error ("cannot specify both -msep-data and -mid-shared-library"); | |
2371 | /* ... internally, however, it's nearly the same. */ | |
2372 | if (TARGET_SEP_DATA) | |
2373 | target_flags |= MASK_ID_SHARED_LIBRARY | MASK_LEAF_ID_SHARED_LIBRARY; | |
2374 | ||
ced0033c | 2375 | if (TARGET_ID_SHARED_LIBRARY && flag_pic == 0) |
2376 | flag_pic = 1; | |
2377 | ||
55be0e32 | 2378 | /* There is no single unaligned SI op for PIC code. Sometimes we |
2379 | need to use ".4byte" and sometimes we need to use ".picptr". | |
2380 | See bfin_assemble_integer for details. */ | |
2381 | if (TARGET_FDPIC) | |
2382 | targetm.asm_out.unaligned_op.si = 0; | |
2383 | ||
2384 | /* Silently turn off flag_pic if not doing FDPIC or ID shared libraries, | |
2385 | since we don't support it and it'll just break. */ | |
2386 | if (flag_pic && !TARGET_FDPIC && !TARGET_ID_SHARED_LIBRARY) | |
2387 | flag_pic = 0; | |
2388 | ||
cfef164f | 2389 | if (TARGET_MULTICORE && bfin_cpu_type != BFIN_CPU_BF561) |
2390 | error ("-mmulticore can only be used with BF561"); | |
2391 | ||
2392 | if (TARGET_COREA && !TARGET_MULTICORE) | |
2393 | error ("-mcorea should be used with -mmulticore"); | |
2394 | ||
2395 | if (TARGET_COREB && !TARGET_MULTICORE) | |
2396 | error ("-mcoreb should be used with -mmulticore"); | |
2397 | ||
2398 | if (TARGET_COREA && TARGET_COREB) | |
bf776685 | 2399 | error ("-mcorea and -mcoreb can%'t be used together"); |
cfef164f | 2400 | |
9e6a0967 | 2401 | flag_schedule_insns = 0; |
3c1905a4 | 2402 | |
2403 | init_machine_status = bfin_init_machine_status; | |
9e6a0967 | 2404 | } |
2405 | ||
b03ddc8f | 2406 | /* Return the destination address of BRANCH. |
2407 | We need to use this instead of get_attr_length, because the | |
2408 | cbranch_with_nops pattern conservatively sets its length to 6, and | |
2409 | we still prefer to use shorter sequences. */ | |
9e6a0967 | 2410 | |
2411 | static int | |
2412 | branch_dest (rtx branch) | |
2413 | { | |
2414 | rtx dest; | |
2415 | int dest_uid; | |
2416 | rtx pat = PATTERN (branch); | |
2417 | if (GET_CODE (pat) == PARALLEL) | |
2418 | pat = XVECEXP (pat, 0, 0); | |
2419 | dest = SET_SRC (pat); | |
2420 | if (GET_CODE (dest) == IF_THEN_ELSE) | |
2421 | dest = XEXP (dest, 1); | |
2422 | dest = XEXP (dest, 0); | |
2423 | dest_uid = INSN_UID (dest); | |
2424 | return INSN_ADDRESSES (dest_uid); | |
2425 | } | |
2426 | ||
2427 | /* Return nonzero if INSN is annotated with a REG_BR_PROB note that indicates | |
2428 | it's a branch that's predicted taken. */ | |
2429 | ||
2430 | static int | |
2431 | cbranch_predicted_taken_p (rtx insn) | |
2432 | { | |
2433 | rtx x = find_reg_note (insn, REG_BR_PROB, 0); | |
2434 | ||
2435 | if (x) | |
2436 | { | |
2437 | int pred_val = INTVAL (XEXP (x, 0)); | |
2438 | ||
2439 | return pred_val >= REG_BR_PROB_BASE / 2; | |
2440 | } | |
2441 | ||
2442 | return 0; | |
2443 | } | |
2444 | ||
2445 | /* Templates for use by asm_conditional_branch. */ | |
2446 | ||
2447 | static const char *ccbranch_templates[][3] = { | |
2448 | { "if !cc jump %3;", "if cc jump 4 (bp); jump.s %3;", "if cc jump 6 (bp); jump.l %3;" }, | |
2449 | { "if cc jump %3;", "if !cc jump 4 (bp); jump.s %3;", "if !cc jump 6 (bp); jump.l %3;" }, | |
2450 | { "if !cc jump %3 (bp);", "if cc jump 4; jump.s %3;", "if cc jump 6; jump.l %3;" }, | |
2451 | { "if cc jump %3 (bp);", "if !cc jump 4; jump.s %3;", "if !cc jump 6; jump.l %3;" }, | |
2452 | }; | |
2453 | ||
2454 | /* Output INSN, which is a conditional branch instruction with operands | |
2455 | OPERANDS. | |
2456 | ||
2457 | We deal with the various forms of conditional branches that can be generated | |
2458 | by bfin_reorg to prevent the hardware from doing speculative loads, by | |
2459 | - emitting a sufficient number of nops, if N_NOPS is nonzero, or | |
2460 | - always emitting the branch as predicted taken, if PREDICT_TAKEN is true. | |
2461 | Either of these is only necessary if the branch is short, otherwise the | |
2462 | template we use ends in an unconditional jump which flushes the pipeline | |
2463 | anyway. */ | |
2464 | ||
2465 | void | |
2466 | asm_conditional_branch (rtx insn, rtx *operands, int n_nops, int predict_taken) | |
2467 | { | |
2468 | int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn)); | |
2469 | /* Note : offset for instructions like if cc jmp; jump.[sl] offset | |
2470 | is to be taken from start of if cc rather than jump. | |
2471 | Range for jump.s is (-4094, 4096) instead of (-4096, 4094) | |
2472 | */ | |
2473 | int len = (offset >= -1024 && offset <= 1022 ? 0 | |
2474 | : offset >= -4094 && offset <= 4096 ? 1 | |
2475 | : 2); | |
2476 | int bp = predict_taken && len == 0 ? 1 : cbranch_predicted_taken_p (insn); | |
2477 | int idx = (bp << 1) | (GET_CODE (operands[0]) == EQ ? BRF : BRT); | |
2478 | output_asm_insn (ccbranch_templates[idx][len], operands); | |
2115ae11 | 2479 | gcc_assert (n_nops == 0 || !bp); |
9e6a0967 | 2480 | if (len == 0) |
2481 | while (n_nops-- > 0) | |
2482 | output_asm_insn ("nop;", NULL); | |
2483 | } | |
2484 | ||
2485 | /* Emit rtl for a comparison operation CMP in mode MODE. Operands have been | |
2486 | stored in bfin_compare_op0 and bfin_compare_op1 already. */ | |
2487 | ||
2488 | rtx | |
2489 | bfin_gen_compare (rtx cmp, enum machine_mode mode ATTRIBUTE_UNUSED) | |
2490 | { | |
2491 | enum rtx_code code1, code2; | |
74f4459c | 2492 | rtx op0 = XEXP (cmp, 0), op1 = XEXP (cmp, 1); |
9e6a0967 | 2493 | rtx tem = bfin_cc_rtx; |
2494 | enum rtx_code code = GET_CODE (cmp); | |
2495 | ||
2496 | /* If we have a BImode input, then we already have a compare result, and | |
2497 | do not need to emit another comparison. */ | |
2498 | if (GET_MODE (op0) == BImode) | |
2499 | { | |
2115ae11 | 2500 | gcc_assert ((code == NE || code == EQ) && op1 == const0_rtx); |
2501 | tem = op0, code2 = code; | |
9e6a0967 | 2502 | } |
2503 | else | |
2504 | { | |
2505 | switch (code) { | |
2506 | /* bfin has these conditions */ | |
2507 | case EQ: | |
2508 | case LT: | |
2509 | case LE: | |
2510 | case LEU: | |
2511 | case LTU: | |
2512 | code1 = code; | |
2513 | code2 = NE; | |
2514 | break; | |
2515 | default: | |
2516 | code1 = reverse_condition (code); | |
2517 | code2 = EQ; | |
2518 | break; | |
2519 | } | |
74f4459c | 2520 | emit_insn (gen_rtx_SET (VOIDmode, tem, |
9e6a0967 | 2521 | gen_rtx_fmt_ee (code1, BImode, op0, op1))); |
2522 | } | |
2523 | ||
2524 | return gen_rtx_fmt_ee (code2, BImode, tem, CONST0_RTX (BImode)); | |
2525 | } | |
2526 | \f | |
2527 | /* Return nonzero iff C has exactly one bit set if it is interpreted | |
905ea169 | 2528 | as a 32-bit constant. */ |
9e6a0967 | 2529 | |
2530 | int | |
2531 | log2constp (unsigned HOST_WIDE_INT c) | |
2532 | { | |
2533 | c &= 0xFFFFFFFF; | |
2534 | return c != 0 && (c & (c-1)) == 0; | |
2535 | } | |
2536 | ||
2537 | /* Returns the number of consecutive least significant zeros in the binary | |
2538 | representation of *V. | |
2539 | We modify *V to contain the original value arithmetically shifted right by | |
2540 | the number of zeroes. */ | |
2541 | ||
2542 | static int | |
2543 | shiftr_zero (HOST_WIDE_INT *v) | |
2544 | { | |
2545 | unsigned HOST_WIDE_INT tmp = *v; | |
2546 | unsigned HOST_WIDE_INT sgn; | |
2547 | int n = 0; | |
2548 | ||
2549 | if (tmp == 0) | |
2550 | return 0; | |
2551 | ||
2552 | sgn = tmp & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)); | |
2553 | while ((tmp & 0x1) == 0 && n <= 32) | |
2554 | { | |
2555 | tmp = (tmp >> 1) | sgn; | |
2556 | n++; | |
2557 | } | |
2558 | *v = tmp; | |
2559 | return n; | |
2560 | } | |
2561 | ||
2562 | /* After reload, split the load of an immediate constant. OPERANDS are the | |
2563 | operands of the movsi_insn pattern which we are splitting. We return | |
2564 | nonzero if we emitted a sequence to load the constant, zero if we emitted | |
2565 | nothing because we want to use the splitter's default sequence. */ | |
2566 | ||
2567 | int | |
2568 | split_load_immediate (rtx operands[]) | |
2569 | { | |
2570 | HOST_WIDE_INT val = INTVAL (operands[1]); | |
2571 | HOST_WIDE_INT tmp; | |
2572 | HOST_WIDE_INT shifted = val; | |
2573 | HOST_WIDE_INT shifted_compl = ~val; | |
2574 | int num_zero = shiftr_zero (&shifted); | |
2575 | int num_compl_zero = shiftr_zero (&shifted_compl); | |
2576 | unsigned int regno = REGNO (operands[0]); | |
9e6a0967 | 2577 | |
2578 | /* This case takes care of single-bit set/clear constants, which we could | |
2579 | also implement with BITSET/BITCLR. */ | |
2580 | if (num_zero | |
2581 | && shifted >= -32768 && shifted < 65536 | |
2582 | && (D_REGNO_P (regno) | |
2583 | || (regno >= REG_P0 && regno <= REG_P7 && num_zero <= 2))) | |
2584 | { | |
2585 | emit_insn (gen_movsi (operands[0], GEN_INT (shifted))); | |
2586 | emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (num_zero))); | |
2587 | return 1; | |
2588 | } | |
2589 | ||
2590 | tmp = val & 0xFFFF; | |
2591 | tmp |= -(tmp & 0x8000); | |
2592 | ||
2593 | /* If high word has one bit set or clear, try to use a bit operation. */ | |
2594 | if (D_REGNO_P (regno)) | |
2595 | { | |
2596 | if (log2constp (val & 0xFFFF0000)) | |
2597 | { | |
2598 | emit_insn (gen_movsi (operands[0], GEN_INT (val & 0xFFFF))); | |
2599 | emit_insn (gen_iorsi3 (operands[0], operands[0], GEN_INT (val & 0xFFFF0000))); | |
2600 | return 1; | |
2601 | } | |
2602 | else if (log2constp (val | 0xFFFF) && (val & 0x8000) != 0) | |
2603 | { | |
2604 | emit_insn (gen_movsi (operands[0], GEN_INT (tmp))); | |
2605 | emit_insn (gen_andsi3 (operands[0], operands[0], GEN_INT (val | 0xFFFF))); | |
2606 | } | |
2607 | } | |
2608 | ||
2609 | if (D_REGNO_P (regno)) | |
2610 | { | |
87943377 | 2611 | if (tmp >= -64 && tmp <= 63) |
9e6a0967 | 2612 | { |
2613 | emit_insn (gen_movsi (operands[0], GEN_INT (tmp))); | |
2614 | emit_insn (gen_movstricthi_high (operands[0], GEN_INT (val & -65536))); | |
2615 | return 1; | |
2616 | } | |
2617 | ||
2618 | if ((val & 0xFFFF0000) == 0) | |
2619 | { | |
2620 | emit_insn (gen_movsi (operands[0], const0_rtx)); | |
2621 | emit_insn (gen_movsi_low (operands[0], operands[0], operands[1])); | |
2622 | return 1; | |
2623 | } | |
2624 | ||
2625 | if ((val & 0xFFFF0000) == 0xFFFF0000) | |
2626 | { | |
2627 | emit_insn (gen_movsi (operands[0], constm1_rtx)); | |
2628 | emit_insn (gen_movsi_low (operands[0], operands[0], operands[1])); | |
2629 | return 1; | |
2630 | } | |
2631 | } | |
2632 | ||
2633 | /* Need DREGs for the remaining case. */ | |
2634 | if (regno > REG_R7) | |
2635 | return 0; | |
2636 | ||
2637 | if (optimize_size | |
87943377 | 2638 | && num_compl_zero && shifted_compl >= -64 && shifted_compl <= 63) |
9e6a0967 | 2639 | { |
2640 | /* If optimizing for size, generate a sequence that has more instructions | |
2641 | but is shorter. */ | |
2642 | emit_insn (gen_movsi (operands[0], GEN_INT (shifted_compl))); | |
2643 | emit_insn (gen_ashlsi3 (operands[0], operands[0], | |
2644 | GEN_INT (num_compl_zero))); | |
2645 | emit_insn (gen_one_cmplsi2 (operands[0], operands[0])); | |
2646 | return 1; | |
2647 | } | |
2648 | return 0; | |
2649 | } | |
2650 | \f | |
2651 | /* Return true if the legitimate memory address for a memory operand of mode | |
2652 | MODE. Return false if not. */ | |
2653 | ||
2654 | static bool | |
2655 | bfin_valid_add (enum machine_mode mode, HOST_WIDE_INT value) | |
2656 | { | |
2657 | unsigned HOST_WIDE_INT v = value > 0 ? value : -value; | |
2658 | int sz = GET_MODE_SIZE (mode); | |
2659 | int shift = sz == 1 ? 0 : sz == 2 ? 1 : 2; | |
2660 | /* The usual offsettable_memref machinery doesn't work so well for this | |
2661 | port, so we deal with the problem here. */ | |
351ae60b | 2662 | if (value > 0 && sz == 8) |
2663 | v += 4; | |
2664 | return (v & ~(0x7fff << shift)) == 0; | |
9e6a0967 | 2665 | } |
2666 | ||
2667 | static bool | |
00cb30dc | 2668 | bfin_valid_reg_p (unsigned int regno, int strict, enum machine_mode mode, |
2669 | enum rtx_code outer_code) | |
9e6a0967 | 2670 | { |
00cb30dc | 2671 | if (strict) |
2672 | return REGNO_OK_FOR_BASE_STRICT_P (regno, mode, outer_code, SCRATCH); | |
2673 | else | |
2674 | return REGNO_OK_FOR_BASE_NONSTRICT_P (regno, mode, outer_code, SCRATCH); | |
9e6a0967 | 2675 | } |
2676 | ||
fd50b071 | 2677 | /* Recognize an RTL expression that is a valid memory address for an |
2678 | instruction. The MODE argument is the machine mode for the MEM expression | |
2679 | that wants to use this address. | |
2680 | ||
2681 | Blackfin addressing modes are as follows: | |
2682 | ||
2683 | [preg] | |
2684 | [preg + imm16] | |
2685 | ||
2686 | B [ Preg + uimm15 ] | |
2687 | W [ Preg + uimm16m2 ] | |
2688 | [ Preg + uimm17m4 ] | |
2689 | ||
2690 | [preg++] | |
2691 | [preg--] | |
2692 | [--sp] | |
2693 | */ | |
2694 | ||
2695 | static bool | |
2696 | bfin_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) | |
9e6a0967 | 2697 | { |
2698 | switch (GET_CODE (x)) { | |
2699 | case REG: | |
00cb30dc | 2700 | if (bfin_valid_reg_p (REGNO (x), strict, mode, MEM)) |
9e6a0967 | 2701 | return true; |
2702 | break; | |
2703 | case PLUS: | |
2704 | if (REG_P (XEXP (x, 0)) | |
00cb30dc | 2705 | && bfin_valid_reg_p (REGNO (XEXP (x, 0)), strict, mode, PLUS) |
8f5efc80 | 2706 | && ((GET_CODE (XEXP (x, 1)) == UNSPEC && mode == SImode) |
9e6a0967 | 2707 | || (GET_CODE (XEXP (x, 1)) == CONST_INT |
2708 | && bfin_valid_add (mode, INTVAL (XEXP (x, 1)))))) | |
2709 | return true; | |
2710 | break; | |
2711 | case POST_INC: | |
2712 | case POST_DEC: | |
2713 | if (LEGITIMATE_MODE_FOR_AUTOINC_P (mode) | |
2714 | && REG_P (XEXP (x, 0)) | |
00cb30dc | 2715 | && bfin_valid_reg_p (REGNO (XEXP (x, 0)), strict, mode, POST_INC)) |
9e6a0967 | 2716 | return true; |
2717 | case PRE_DEC: | |
2718 | if (LEGITIMATE_MODE_FOR_AUTOINC_P (mode) | |
2719 | && XEXP (x, 0) == stack_pointer_rtx | |
2720 | && REG_P (XEXP (x, 0)) | |
00cb30dc | 2721 | && bfin_valid_reg_p (REGNO (XEXP (x, 0)), strict, mode, PRE_DEC)) |
9e6a0967 | 2722 | return true; |
2723 | break; | |
2724 | default: | |
2725 | break; | |
2726 | } | |
2727 | return false; | |
2728 | } | |
2729 | ||
cf63c743 | 2730 | /* Decide whether we can force certain constants to memory. If we |
2731 | decide we can't, the caller should be able to cope with it in | |
2732 | another way. */ | |
2733 | ||
2734 | static bool | |
7d7d7bd2 | 2735 | bfin_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, |
2736 | rtx x ATTRIBUTE_UNUSED) | |
cf63c743 | 2737 | { |
2738 | /* We have only one class of non-legitimate constants, and our movsi | |
2739 | expander knows how to handle them. Dropping these constants into the | |
2740 | data section would only shift the problem - we'd still get relocs | |
2741 | outside the object, in the data section rather than the text section. */ | |
2742 | return true; | |
2743 | } | |
2744 | ||
2745 | /* Ensure that for any constant of the form symbol + offset, the offset | |
2746 | remains within the object. Any other constants are ok. | |
2747 | This ensures that flat binaries never have to deal with relocations | |
2748 | crossing section boundaries. */ | |
2749 | ||
ca316360 | 2750 | static bool |
2751 | bfin_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) | |
cf63c743 | 2752 | { |
2753 | rtx sym; | |
2754 | HOST_WIDE_INT offset; | |
2755 | ||
2756 | if (GET_CODE (x) != CONST) | |
2757 | return true; | |
2758 | ||
2759 | x = XEXP (x, 0); | |
2760 | gcc_assert (GET_CODE (x) == PLUS); | |
2761 | ||
2762 | sym = XEXP (x, 0); | |
2763 | x = XEXP (x, 1); | |
2764 | if (GET_CODE (sym) != SYMBOL_REF | |
2765 | || GET_CODE (x) != CONST_INT) | |
2766 | return true; | |
2767 | offset = INTVAL (x); | |
2768 | ||
2769 | if (SYMBOL_REF_DECL (sym) == 0) | |
2770 | return true; | |
2771 | if (offset < 0 | |
2772 | || offset >= int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (sym)))) | |
2773 | return false; | |
2774 | ||
2775 | return true; | |
2776 | } | |
2777 | ||
9e6a0967 | 2778 | static bool |
95f13934 | 2779 | bfin_rtx_costs (rtx x, int code_i, int outer_code_i, int *total, bool speed) |
9e6a0967 | 2780 | { |
95f13934 | 2781 | enum rtx_code code = (enum rtx_code) code_i; |
2782 | enum rtx_code outer_code = (enum rtx_code) outer_code_i; | |
9e6a0967 | 2783 | int cost2 = COSTS_N_INSNS (1); |
f84f5dae | 2784 | rtx op0, op1; |
9e6a0967 | 2785 | |
2786 | switch (code) | |
2787 | { | |
2788 | case CONST_INT: | |
2789 | if (outer_code == SET || outer_code == PLUS) | |
87943377 | 2790 | *total = satisfies_constraint_Ks7 (x) ? 0 : cost2; |
9e6a0967 | 2791 | else if (outer_code == AND) |
2792 | *total = log2constp (~INTVAL (x)) ? 0 : cost2; | |
2793 | else if (outer_code == LE || outer_code == LT || outer_code == EQ) | |
2794 | *total = (INTVAL (x) >= -4 && INTVAL (x) <= 3) ? 0 : cost2; | |
2795 | else if (outer_code == LEU || outer_code == LTU) | |
2796 | *total = (INTVAL (x) >= 0 && INTVAL (x) <= 7) ? 0 : cost2; | |
2797 | else if (outer_code == MULT) | |
2798 | *total = (INTVAL (x) == 2 || INTVAL (x) == 4) ? 0 : cost2; | |
2799 | else if (outer_code == ASHIFT && (INTVAL (x) == 1 || INTVAL (x) == 2)) | |
2800 | *total = 0; | |
2801 | else if (outer_code == ASHIFT || outer_code == ASHIFTRT | |
2802 | || outer_code == LSHIFTRT) | |
2803 | *total = (INTVAL (x) >= 0 && INTVAL (x) <= 31) ? 0 : cost2; | |
2804 | else if (outer_code == IOR || outer_code == XOR) | |
2805 | *total = (INTVAL (x) & (INTVAL (x) - 1)) == 0 ? 0 : cost2; | |
2806 | else | |
2807 | *total = cost2; | |
2808 | return true; | |
2809 | ||
2810 | case CONST: | |
2811 | case LABEL_REF: | |
2812 | case SYMBOL_REF: | |
2813 | case CONST_DOUBLE: | |
2814 | *total = COSTS_N_INSNS (2); | |
2815 | return true; | |
2816 | ||
2817 | case PLUS: | |
f84f5dae | 2818 | op0 = XEXP (x, 0); |
2819 | op1 = XEXP (x, 1); | |
2820 | if (GET_MODE (x) == SImode) | |
9e6a0967 | 2821 | { |
f84f5dae | 2822 | if (GET_CODE (op0) == MULT |
2823 | && GET_CODE (XEXP (op0, 1)) == CONST_INT) | |
9e6a0967 | 2824 | { |
f84f5dae | 2825 | HOST_WIDE_INT val = INTVAL (XEXP (op0, 1)); |
9e6a0967 | 2826 | if (val == 2 || val == 4) |
2827 | { | |
2828 | *total = cost2; | |
f529eb25 | 2829 | *total += rtx_cost (XEXP (op0, 0), outer_code, speed); |
2830 | *total += rtx_cost (op1, outer_code, speed); | |
9e6a0967 | 2831 | return true; |
2832 | } | |
2833 | } | |
f84f5dae | 2834 | *total = cost2; |
2835 | if (GET_CODE (op0) != REG | |
2836 | && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG)) | |
f529eb25 | 2837 | *total += rtx_cost (op0, SET, speed); |
f84f5dae | 2838 | #if 0 /* We'd like to do this for accuracy, but it biases the loop optimizer |
2839 | towards creating too many induction variables. */ | |
2840 | if (!reg_or_7bit_operand (op1, SImode)) | |
f529eb25 | 2841 | *total += rtx_cost (op1, SET, speed); |
f84f5dae | 2842 | #endif |
9e6a0967 | 2843 | } |
f84f5dae | 2844 | else if (GET_MODE (x) == DImode) |
2845 | { | |
2846 | *total = 6 * cost2; | |
2847 | if (GET_CODE (op1) != CONST_INT | |
87943377 | 2848 | || !satisfies_constraint_Ks7 (op1)) |
f529eb25 | 2849 | *total += rtx_cost (op1, PLUS, speed); |
f84f5dae | 2850 | if (GET_CODE (op0) != REG |
2851 | && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG)) | |
f529eb25 | 2852 | *total += rtx_cost (op0, PLUS, speed); |
f84f5dae | 2853 | } |
2854 | return true; | |
9e6a0967 | 2855 | |
2856 | case MINUS: | |
f84f5dae | 2857 | if (GET_MODE (x) == DImode) |
2858 | *total = 6 * cost2; | |
2859 | else | |
2860 | *total = cost2; | |
2861 | return true; | |
2862 | ||
9e6a0967 | 2863 | case ASHIFT: |
2864 | case ASHIFTRT: | |
2865 | case LSHIFTRT: | |
2866 | if (GET_MODE (x) == DImode) | |
2867 | *total = 6 * cost2; | |
f84f5dae | 2868 | else |
2869 | *total = cost2; | |
2870 | ||
2871 | op0 = XEXP (x, 0); | |
2872 | op1 = XEXP (x, 1); | |
2873 | if (GET_CODE (op0) != REG | |
2874 | && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG)) | |
f529eb25 | 2875 | *total += rtx_cost (op0, code, speed); |
f84f5dae | 2876 | |
2877 | return true; | |
9e6a0967 | 2878 | |
9e6a0967 | 2879 | case IOR: |
f84f5dae | 2880 | case AND: |
9e6a0967 | 2881 | case XOR: |
f84f5dae | 2882 | op0 = XEXP (x, 0); |
2883 | op1 = XEXP (x, 1); | |
2884 | ||
2885 | /* Handle special cases of IOR: rotates, ALIGN insns, movstricthi_high. */ | |
2886 | if (code == IOR) | |
2887 | { | |
2888 | if ((GET_CODE (op0) == LSHIFTRT && GET_CODE (op1) == ASHIFT) | |
2889 | || (GET_CODE (op0) == ASHIFT && GET_CODE (op1) == ZERO_EXTEND) | |
2890 | || (GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT) | |
2891 | || (GET_CODE (op0) == AND && GET_CODE (op1) == CONST_INT)) | |
2892 | { | |
2893 | *total = cost2; | |
2894 | return true; | |
2895 | } | |
2896 | } | |
2897 | ||
2898 | if (GET_CODE (op0) != REG | |
2899 | && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG)) | |
f529eb25 | 2900 | *total += rtx_cost (op0, code, speed); |
f84f5dae | 2901 | |
9e6a0967 | 2902 | if (GET_MODE (x) == DImode) |
f84f5dae | 2903 | { |
2904 | *total = 2 * cost2; | |
2905 | return true; | |
2906 | } | |
2907 | *total = cost2; | |
2908 | if (GET_MODE (x) != SImode) | |
2909 | return true; | |
2910 | ||
2911 | if (code == AND) | |
2912 | { | |
2913 | if (! rhs_andsi3_operand (XEXP (x, 1), SImode)) | |
f529eb25 | 2914 | *total += rtx_cost (XEXP (x, 1), code, speed); |
f84f5dae | 2915 | } |
2916 | else | |
2917 | { | |
2918 | if (! regorlog2_operand (XEXP (x, 1), SImode)) | |
f529eb25 | 2919 | *total += rtx_cost (XEXP (x, 1), code, speed); |
f84f5dae | 2920 | } |
2921 | ||
2922 | return true; | |
2923 | ||
2924 | case ZERO_EXTRACT: | |
2925 | case SIGN_EXTRACT: | |
2926 | if (outer_code == SET | |
2927 | && XEXP (x, 1) == const1_rtx | |
2928 | && GET_CODE (XEXP (x, 2)) == CONST_INT) | |
2929 | { | |
2930 | *total = 2 * cost2; | |
2931 | return true; | |
2932 | } | |
2933 | /* fall through */ | |
2934 | ||
2935 | case SIGN_EXTEND: | |
2936 | case ZERO_EXTEND: | |
2937 | *total = cost2; | |
2938 | return true; | |
9e6a0967 | 2939 | |
2940 | case MULT: | |
f84f5dae | 2941 | { |
2942 | op0 = XEXP (x, 0); | |
2943 | op1 = XEXP (x, 1); | |
2944 | if (GET_CODE (op0) == GET_CODE (op1) | |
2945 | && (GET_CODE (op0) == ZERO_EXTEND | |
2946 | || GET_CODE (op0) == SIGN_EXTEND)) | |
2947 | { | |
2948 | *total = COSTS_N_INSNS (1); | |
2949 | op0 = XEXP (op0, 0); | |
2950 | op1 = XEXP (op1, 0); | |
2951 | } | |
f529eb25 | 2952 | else if (!speed) |
f84f5dae | 2953 | *total = COSTS_N_INSNS (1); |
2954 | else | |
2955 | *total = COSTS_N_INSNS (3); | |
2956 | ||
2957 | if (GET_CODE (op0) != REG | |
2958 | && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG)) | |
f529eb25 | 2959 | *total += rtx_cost (op0, MULT, speed); |
f84f5dae | 2960 | if (GET_CODE (op1) != REG |
2961 | && (GET_CODE (op1) != SUBREG || GET_CODE (SUBREG_REG (op1)) != REG)) | |
f529eb25 | 2962 | *total += rtx_cost (op1, MULT, speed); |
f84f5dae | 2963 | } |
2964 | return true; | |
9e6a0967 | 2965 | |
ff7e43ad | 2966 | case UDIV: |
2967 | case UMOD: | |
2968 | *total = COSTS_N_INSNS (32); | |
2969 | return true; | |
2970 | ||
f9edc33d | 2971 | case VEC_CONCAT: |
2972 | case VEC_SELECT: | |
2973 | if (outer_code == SET) | |
2974 | *total = cost2; | |
2975 | return true; | |
2976 | ||
9e6a0967 | 2977 | default: |
2978 | return false; | |
2979 | } | |
2980 | } | |
9e6a0967 | 2981 | \f |
2982 | /* Used for communication between {push,pop}_multiple_operation (which | |
2983 | we use not only as a predicate) and the corresponding output functions. */ | |
2984 | static int first_preg_to_save, first_dreg_to_save; | |
0d65fac2 | 2985 | static int n_regs_to_save; |
9e6a0967 | 2986 | |
2987 | int | |
2988 | push_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
2989 | { | |
2990 | int lastdreg = 8, lastpreg = 6; | |
2991 | int i, group; | |
2992 | ||
2993 | first_preg_to_save = lastpreg; | |
2994 | first_dreg_to_save = lastdreg; | |
2995 | for (i = 1, group = 0; i < XVECLEN (op, 0) - 1; i++) | |
2996 | { | |
2997 | rtx t = XVECEXP (op, 0, i); | |
2998 | rtx src, dest; | |
2999 | int regno; | |
3000 | ||
3001 | if (GET_CODE (t) != SET) | |
3002 | return 0; | |
3003 | ||
3004 | src = SET_SRC (t); | |
3005 | dest = SET_DEST (t); | |
3006 | if (GET_CODE (dest) != MEM || ! REG_P (src)) | |
3007 | return 0; | |
3008 | dest = XEXP (dest, 0); | |
3009 | if (GET_CODE (dest) != PLUS | |
3010 | || ! REG_P (XEXP (dest, 0)) | |
3011 | || REGNO (XEXP (dest, 0)) != REG_SP | |
3012 | || GET_CODE (XEXP (dest, 1)) != CONST_INT | |
3013 | || INTVAL (XEXP (dest, 1)) != -i * 4) | |
3014 | return 0; | |
3015 | ||
3016 | regno = REGNO (src); | |
3017 | if (group == 0) | |
3018 | { | |
3019 | if (D_REGNO_P (regno)) | |
3020 | { | |
3021 | group = 1; | |
3022 | first_dreg_to_save = lastdreg = regno - REG_R0; | |
3023 | } | |
3024 | else if (regno >= REG_P0 && regno <= REG_P7) | |
3025 | { | |
3026 | group = 2; | |
3027 | first_preg_to_save = lastpreg = regno - REG_P0; | |
3028 | } | |
3029 | else | |
3030 | return 0; | |
3031 | ||
3032 | continue; | |
3033 | } | |
3034 | ||
3035 | if (group == 1) | |
3036 | { | |
3037 | if (regno >= REG_P0 && regno <= REG_P7) | |
3038 | { | |
3039 | group = 2; | |
3040 | first_preg_to_save = lastpreg = regno - REG_P0; | |
3041 | } | |
3042 | else if (regno != REG_R0 + lastdreg + 1) | |
3043 | return 0; | |
3044 | else | |
3045 | lastdreg++; | |
3046 | } | |
3047 | else if (group == 2) | |
3048 | { | |
3049 | if (regno != REG_P0 + lastpreg + 1) | |
3050 | return 0; | |
3051 | lastpreg++; | |
3052 | } | |
3053 | } | |
0d65fac2 | 3054 | n_regs_to_save = 8 - first_dreg_to_save + 6 - first_preg_to_save; |
9e6a0967 | 3055 | return 1; |
3056 | } | |
3057 | ||
3058 | int | |
3059 | pop_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
3060 | { | |
3061 | int lastdreg = 8, lastpreg = 6; | |
3062 | int i, group; | |
3063 | ||
3064 | for (i = 1, group = 0; i < XVECLEN (op, 0); i++) | |
3065 | { | |
3066 | rtx t = XVECEXP (op, 0, i); | |
3067 | rtx src, dest; | |
3068 | int regno; | |
3069 | ||
3070 | if (GET_CODE (t) != SET) | |
3071 | return 0; | |
3072 | ||
3073 | src = SET_SRC (t); | |
3074 | dest = SET_DEST (t); | |
3075 | if (GET_CODE (src) != MEM || ! REG_P (dest)) | |
3076 | return 0; | |
3077 | src = XEXP (src, 0); | |
3078 | ||
3079 | if (i == 1) | |
3080 | { | |
3081 | if (! REG_P (src) || REGNO (src) != REG_SP) | |
3082 | return 0; | |
3083 | } | |
3084 | else if (GET_CODE (src) != PLUS | |
3085 | || ! REG_P (XEXP (src, 0)) | |
3086 | || REGNO (XEXP (src, 0)) != REG_SP | |
3087 | || GET_CODE (XEXP (src, 1)) != CONST_INT | |
3088 | || INTVAL (XEXP (src, 1)) != (i - 1) * 4) | |
3089 | return 0; | |
3090 | ||
3091 | regno = REGNO (dest); | |
3092 | if (group == 0) | |
3093 | { | |
3094 | if (regno == REG_R7) | |
3095 | { | |
3096 | group = 1; | |
3097 | lastdreg = 7; | |
3098 | } | |
3099 | else if (regno != REG_P0 + lastpreg - 1) | |
3100 | return 0; | |
3101 | else | |
3102 | lastpreg--; | |
3103 | } | |
3104 | else if (group == 1) | |
3105 | { | |
3106 | if (regno != REG_R0 + lastdreg - 1) | |
3107 | return 0; | |
3108 | else | |
3109 | lastdreg--; | |
3110 | } | |
3111 | } | |
3112 | first_dreg_to_save = lastdreg; | |
3113 | first_preg_to_save = lastpreg; | |
0d65fac2 | 3114 | n_regs_to_save = 8 - first_dreg_to_save + 6 - first_preg_to_save; |
9e6a0967 | 3115 | return 1; |
3116 | } | |
3117 | ||
3118 | /* Emit assembly code for one multi-register push described by INSN, with | |
3119 | operands in OPERANDS. */ | |
3120 | ||
3121 | void | |
3122 | output_push_multiple (rtx insn, rtx *operands) | |
3123 | { | |
3124 | char buf[80]; | |
2115ae11 | 3125 | int ok; |
3126 | ||
9e6a0967 | 3127 | /* Validate the insn again, and compute first_[dp]reg_to_save. */ |
2115ae11 | 3128 | ok = push_multiple_operation (PATTERN (insn), VOIDmode); |
3129 | gcc_assert (ok); | |
3130 | ||
9e6a0967 | 3131 | if (first_dreg_to_save == 8) |
3132 | sprintf (buf, "[--sp] = ( p5:%d );\n", first_preg_to_save); | |
3133 | else if (first_preg_to_save == 6) | |
3134 | sprintf (buf, "[--sp] = ( r7:%d );\n", first_dreg_to_save); | |
3135 | else | |
2115ae11 | 3136 | sprintf (buf, "[--sp] = ( r7:%d, p5:%d );\n", |
3137 | first_dreg_to_save, first_preg_to_save); | |
9e6a0967 | 3138 | |
3139 | output_asm_insn (buf, operands); | |
3140 | } | |
3141 | ||
3142 | /* Emit assembly code for one multi-register pop described by INSN, with | |
3143 | operands in OPERANDS. */ | |
3144 | ||
3145 | void | |
3146 | output_pop_multiple (rtx insn, rtx *operands) | |
3147 | { | |
3148 | char buf[80]; | |
2115ae11 | 3149 | int ok; |
3150 | ||
9e6a0967 | 3151 | /* Validate the insn again, and compute first_[dp]reg_to_save. */ |
2115ae11 | 3152 | ok = pop_multiple_operation (PATTERN (insn), VOIDmode); |
3153 | gcc_assert (ok); | |
9e6a0967 | 3154 | |
3155 | if (first_dreg_to_save == 8) | |
3156 | sprintf (buf, "( p5:%d ) = [sp++];\n", first_preg_to_save); | |
3157 | else if (first_preg_to_save == 6) | |
3158 | sprintf (buf, "( r7:%d ) = [sp++];\n", first_dreg_to_save); | |
3159 | else | |
2115ae11 | 3160 | sprintf (buf, "( r7:%d, p5:%d ) = [sp++];\n", |
3161 | first_dreg_to_save, first_preg_to_save); | |
9e6a0967 | 3162 | |
3163 | output_asm_insn (buf, operands); | |
3164 | } | |
3165 | ||
3166 | /* Adjust DST and SRC by OFFSET bytes, and generate one move in mode MODE. */ | |
3167 | ||
3168 | static void | |
a92178b8 | 3169 | single_move_for_movmem (rtx dst, rtx src, enum machine_mode mode, HOST_WIDE_INT offset) |
9e6a0967 | 3170 | { |
3171 | rtx scratch = gen_reg_rtx (mode); | |
3172 | rtx srcmem, dstmem; | |
3173 | ||
3174 | srcmem = adjust_address_nv (src, mode, offset); | |
3175 | dstmem = adjust_address_nv (dst, mode, offset); | |
3176 | emit_move_insn (scratch, srcmem); | |
3177 | emit_move_insn (dstmem, scratch); | |
3178 | } | |
3179 | ||
3180 | /* Expand a string move operation of COUNT_EXP bytes from SRC to DST, with | |
3181 | alignment ALIGN_EXP. Return true if successful, false if we should fall | |
3182 | back on a different method. */ | |
3183 | ||
3184 | bool | |
a92178b8 | 3185 | bfin_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp) |
9e6a0967 | 3186 | { |
3187 | rtx srcreg, destreg, countreg; | |
3188 | HOST_WIDE_INT align = 0; | |
3189 | unsigned HOST_WIDE_INT count = 0; | |
3190 | ||
3191 | if (GET_CODE (align_exp) == CONST_INT) | |
3192 | align = INTVAL (align_exp); | |
3193 | if (GET_CODE (count_exp) == CONST_INT) | |
3194 | { | |
3195 | count = INTVAL (count_exp); | |
3196 | #if 0 | |
3197 | if (!TARGET_INLINE_ALL_STRINGOPS && count > 64) | |
3198 | return false; | |
3199 | #endif | |
3200 | } | |
3201 | ||
3202 | /* If optimizing for size, only do single copies inline. */ | |
3203 | if (optimize_size) | |
3204 | { | |
3205 | if (count == 2 && align < 2) | |
3206 | return false; | |
3207 | if (count == 4 && align < 4) | |
3208 | return false; | |
3209 | if (count != 1 && count != 2 && count != 4) | |
3210 | return false; | |
3211 | } | |
3212 | if (align < 2 && count != 1) | |
3213 | return false; | |
3214 | ||
3215 | destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0)); | |
3216 | if (destreg != XEXP (dst, 0)) | |
3217 | dst = replace_equiv_address_nv (dst, destreg); | |
3218 | srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0)); | |
3219 | if (srcreg != XEXP (src, 0)) | |
3220 | src = replace_equiv_address_nv (src, srcreg); | |
3221 | ||
3222 | if (count != 0 && align >= 2) | |
3223 | { | |
3224 | unsigned HOST_WIDE_INT offset = 0; | |
3225 | ||
3226 | if (align >= 4) | |
3227 | { | |
3228 | if ((count & ~3) == 4) | |
3229 | { | |
a92178b8 | 3230 | single_move_for_movmem (dst, src, SImode, offset); |
9e6a0967 | 3231 | offset = 4; |
3232 | } | |
3233 | else if (count & ~3) | |
3234 | { | |
3235 | HOST_WIDE_INT new_count = ((count >> 2) & 0x3fffffff) - 1; | |
3236 | countreg = copy_to_mode_reg (Pmode, GEN_INT (new_count)); | |
3237 | ||
3238 | emit_insn (gen_rep_movsi (destreg, srcreg, countreg, destreg, srcreg)); | |
4cf41453 | 3239 | cfun->machine->has_loopreg_clobber = true; |
9e6a0967 | 3240 | } |
488493c5 | 3241 | if (count & 2) |
3242 | { | |
a92178b8 | 3243 | single_move_for_movmem (dst, src, HImode, offset); |
488493c5 | 3244 | offset += 2; |
3245 | } | |
9e6a0967 | 3246 | } |
3247 | else | |
3248 | { | |
3249 | if ((count & ~1) == 2) | |
3250 | { | |
a92178b8 | 3251 | single_move_for_movmem (dst, src, HImode, offset); |
9e6a0967 | 3252 | offset = 2; |
3253 | } | |
3254 | else if (count & ~1) | |
3255 | { | |
3256 | HOST_WIDE_INT new_count = ((count >> 1) & 0x7fffffff) - 1; | |
3257 | countreg = copy_to_mode_reg (Pmode, GEN_INT (new_count)); | |
3258 | ||
3259 | emit_insn (gen_rep_movhi (destreg, srcreg, countreg, destreg, srcreg)); | |
4cf41453 | 3260 | cfun->machine->has_loopreg_clobber = true; |
9e6a0967 | 3261 | } |
3262 | } | |
9e6a0967 | 3263 | if (count & 1) |
3264 | { | |
a92178b8 | 3265 | single_move_for_movmem (dst, src, QImode, offset); |
9e6a0967 | 3266 | } |
3267 | return true; | |
3268 | } | |
3269 | return false; | |
3270 | } | |
9e6a0967 | 3271 | \f |
23285403 | 3272 | /* Compute the alignment for a local variable. |
3273 | TYPE is the data type, and ALIGN is the alignment that | |
3274 | the object would ordinarily have. The value of this macro is used | |
3275 | instead of that alignment to align the object. */ | |
3276 | ||
95f13934 | 3277 | unsigned |
3278 | bfin_local_alignment (tree type, unsigned align) | |
23285403 | 3279 | { |
3280 | /* Increasing alignment for (relatively) big types allows the builtin | |
3281 | memcpy can use 32 bit loads/stores. */ | |
3282 | if (TYPE_SIZE (type) | |
3283 | && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
3284 | && (TREE_INT_CST_LOW (TYPE_SIZE (type)) > 8 | |
3285 | || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 32) | |
3286 | return 32; | |
3287 | return align; | |
3288 | } | |
3289 | \f | |
9aa0222b | 3290 | /* Implement TARGET_SCHED_ISSUE_RATE. */ |
3291 | ||
3292 | static int | |
3293 | bfin_issue_rate (void) | |
3294 | { | |
3295 | return 3; | |
3296 | } | |
3297 | ||
9e6a0967 | 3298 | static int |
3299 | bfin_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) | |
3300 | { | |
95f13934 | 3301 | enum attr_type dep_insn_type; |
9e6a0967 | 3302 | int dep_insn_code_number; |
3303 | ||
3304 | /* Anti and output dependencies have zero cost. */ | |
3305 | if (REG_NOTE_KIND (link) != 0) | |
3306 | return 0; | |
3307 | ||
3308 | dep_insn_code_number = recog_memoized (dep_insn); | |
3309 | ||
3310 | /* If we can't recognize the insns, we can't really do anything. */ | |
3311 | if (dep_insn_code_number < 0 || recog_memoized (insn) < 0) | |
3312 | return cost; | |
3313 | ||
9e6a0967 | 3314 | dep_insn_type = get_attr_type (dep_insn); |
3315 | ||
3316 | if (dep_insn_type == TYPE_MOVE || dep_insn_type == TYPE_MCLD) | |
3317 | { | |
3318 | rtx pat = PATTERN (dep_insn); | |
95f13934 | 3319 | rtx dest, src; |
3320 | ||
4694534a | 3321 | if (GET_CODE (pat) == PARALLEL) |
3322 | pat = XVECEXP (pat, 0, 0); | |
95f13934 | 3323 | dest = SET_DEST (pat); |
3324 | src = SET_SRC (pat); | |
4c359296 | 3325 | if (! ADDRESS_REGNO_P (REGNO (dest)) |
3326 | || ! (MEM_P (src) || D_REGNO_P (REGNO (src)))) | |
9e6a0967 | 3327 | return cost; |
3328 | return cost + (dep_insn_type == TYPE_MOVE ? 4 : 3); | |
3329 | } | |
3330 | ||
3331 | return cost; | |
3332 | } | |
462ce619 | 3333 | \f |
3334 | /* This function acts like NEXT_INSN, but is aware of three-insn bundles and | |
3335 | skips all subsequent parallel instructions if INSN is the start of such | |
3336 | a group. */ | |
3337 | static rtx | |
3338 | find_next_insn_start (rtx insn) | |
3339 | { | |
3340 | if (GET_MODE (insn) == SImode) | |
3341 | { | |
3342 | while (GET_MODE (insn) != QImode) | |
3343 | insn = NEXT_INSN (insn); | |
3344 | } | |
3345 | return NEXT_INSN (insn); | |
3346 | } | |
3c1905a4 | 3347 | |
462ce619 | 3348 | /* This function acts like PREV_INSN, but is aware of three-insn bundles and |
3349 | skips all subsequent parallel instructions if INSN is the start of such | |
3350 | a group. */ | |
3351 | static rtx | |
3352 | find_prev_insn_start (rtx insn) | |
3353 | { | |
3354 | insn = PREV_INSN (insn); | |
3355 | gcc_assert (GET_MODE (insn) != SImode); | |
3356 | if (GET_MODE (insn) == QImode) | |
3357 | { | |
3358 | while (GET_MODE (PREV_INSN (insn)) == SImode) | |
3359 | insn = PREV_INSN (insn); | |
3360 | } | |
3361 | return insn; | |
3362 | } | |
3c1905a4 | 3363 | \f |
3364 | /* Increment the counter for the number of loop instructions in the | |
3365 | current function. */ | |
3366 | ||
3367 | void | |
3368 | bfin_hardware_loop (void) | |
3369 | { | |
3370 | cfun->machine->has_hardware_loops++; | |
3371 | } | |
3372 | ||
1a4340cd | 3373 | /* Maximum loop nesting depth. */ |
3c1905a4 | 3374 | #define MAX_LOOP_DEPTH 2 |
3375 | ||
1a4340cd | 3376 | /* Maximum size of a loop. */ |
b6cf30ce | 3377 | #define MAX_LOOP_LENGTH 2042 |
3c1905a4 | 3378 | |
917c4036 | 3379 | /* Maximum distance of the LSETUP instruction from the loop start. */ |
3380 | #define MAX_LSETUP_DISTANCE 30 | |
3381 | ||
3c1905a4 | 3382 | /* We need to keep a vector of loops */ |
95f13934 | 3383 | typedef struct loop_info_d *loop_info; |
3c1905a4 | 3384 | DEF_VEC_P (loop_info); |
3385 | DEF_VEC_ALLOC_P (loop_info,heap); | |
3386 | ||
3387 | /* Information about a loop we have found (or are in the process of | |
3388 | finding). */ | |
95f13934 | 3389 | struct GTY (()) loop_info_d |
3c1905a4 | 3390 | { |
3391 | /* loop number, for dumps */ | |
3392 | int loop_no; | |
3393 | ||
917c4036 | 3394 | /* All edges that jump into and out of the loop. */ |
3395 | VEC(edge,gc) *incoming; | |
3396 | ||
3397 | /* We can handle two cases: all incoming edges have the same destination | |
3398 | block, or all incoming edges have the same source block. These two | |
3399 | members are set to the common source or destination we found, or NULL | |
3400 | if different blocks were found. If both are NULL the loop can't be | |
3401 | optimized. */ | |
3402 | basic_block incoming_src; | |
3403 | basic_block incoming_dest; | |
3c1905a4 | 3404 | |
3405 | /* First block in the loop. This is the one branched to by the loop_end | |
3406 | insn. */ | |
3407 | basic_block head; | |
3408 | ||
3409 | /* Last block in the loop (the one with the loop_end insn). */ | |
3410 | basic_block tail; | |
3411 | ||
3412 | /* The successor block of the loop. This is the one the loop_end insn | |
3413 | falls into. */ | |
3414 | basic_block successor; | |
3415 | ||
3416 | /* The last instruction in the tail. */ | |
3417 | rtx last_insn; | |
3418 | ||
3419 | /* The loop_end insn. */ | |
3420 | rtx loop_end; | |
3421 | ||
3422 | /* The iteration register. */ | |
3423 | rtx iter_reg; | |
3424 | ||
3c1905a4 | 3425 | /* The new label placed at the beginning of the loop. */ |
3426 | rtx start_label; | |
3427 | ||
3428 | /* The new label placed at the end of the loop. */ | |
3429 | rtx end_label; | |
3430 | ||
3431 | /* The length of the loop. */ | |
3432 | int length; | |
3433 | ||
e82f36f5 | 3434 | /* The nesting depth of the loop. */ |
3c1905a4 | 3435 | int depth; |
3436 | ||
e82f36f5 | 3437 | /* Nonzero if we can't optimize this loop. */ |
3438 | int bad; | |
3439 | ||
3c1905a4 | 3440 | /* True if we have visited this loop. */ |
3441 | int visited; | |
3442 | ||
3443 | /* True if this loop body clobbers any of LC0, LT0, or LB0. */ | |
3444 | int clobber_loop0; | |
3445 | ||
3446 | /* True if this loop body clobbers any of LC1, LT1, or LB1. */ | |
3447 | int clobber_loop1; | |
3448 | ||
3449 | /* Next loop in the graph. */ | |
95f13934 | 3450 | struct loop_info_d *next; |
3c1905a4 | 3451 | |
3452 | /* Immediate outer loop of this loop. */ | |
95f13934 | 3453 | struct loop_info_d *outer; |
3c1905a4 | 3454 | |
e82f36f5 | 3455 | /* Vector of blocks only within the loop, including those within |
3456 | inner loops. */ | |
3c1905a4 | 3457 | VEC (basic_block,heap) *blocks; |
3458 | ||
e82f36f5 | 3459 | /* Same information in a bitmap. */ |
3460 | bitmap block_bitmap; | |
3461 | ||
3c1905a4 | 3462 | /* Vector of inner loops within this loop */ |
3463 | VEC (loop_info,heap) *loops; | |
3464 | }; | |
3465 | ||
3c1905a4 | 3466 | static void |
3467 | bfin_dump_loops (loop_info loops) | |
3468 | { | |
3469 | loop_info loop; | |
3470 | ||
3471 | for (loop = loops; loop; loop = loop->next) | |
3472 | { | |
3473 | loop_info i; | |
3474 | basic_block b; | |
3475 | unsigned ix; | |
3476 | ||
3477 | fprintf (dump_file, ";; loop %d: ", loop->loop_no); | |
e82f36f5 | 3478 | if (loop->bad) |
3479 | fprintf (dump_file, "(bad) "); | |
3c1905a4 | 3480 | fprintf (dump_file, "{head:%d, depth:%d}", loop->head->index, loop->depth); |
3481 | ||
3482 | fprintf (dump_file, " blocks: [ "); | |
48148244 | 3483 | FOR_EACH_VEC_ELT (basic_block, loop->blocks, ix, b) |
3c1905a4 | 3484 | fprintf (dump_file, "%d ", b->index); |
3485 | fprintf (dump_file, "] "); | |
3486 | ||
3487 | fprintf (dump_file, " inner loops: [ "); | |
48148244 | 3488 | FOR_EACH_VEC_ELT (loop_info, loop->loops, ix, i) |
3c1905a4 | 3489 | fprintf (dump_file, "%d ", i->loop_no); |
3490 | fprintf (dump_file, "]\n"); | |
3491 | } | |
3492 | fprintf (dump_file, "\n"); | |
3493 | } | |
3494 | ||
3495 | /* Scan the blocks of LOOP (and its inferiors) looking for basic block | |
3496 | BB. Return true, if we find it. */ | |
3497 | ||
3498 | static bool | |
3499 | bfin_bb_in_loop (loop_info loop, basic_block bb) | |
3500 | { | |
e82f36f5 | 3501 | return bitmap_bit_p (loop->block_bitmap, bb->index); |
3c1905a4 | 3502 | } |
3503 | ||
3504 | /* Scan the blocks of LOOP (and its inferiors) looking for uses of | |
3505 | REG. Return true, if we find any. Don't count the loop's loop_end | |
3506 | insn if it matches LOOP_END. */ | |
3507 | ||
3508 | static bool | |
3509 | bfin_scan_loop (loop_info loop, rtx reg, rtx loop_end) | |
3510 | { | |
3511 | unsigned ix; | |
3c1905a4 | 3512 | basic_block bb; |
3513 | ||
48148244 | 3514 | FOR_EACH_VEC_ELT (basic_block, loop->blocks, ix, bb) |
3c1905a4 | 3515 | { |
3516 | rtx insn; | |
3517 | ||
3518 | for (insn = BB_HEAD (bb); | |
3519 | insn != NEXT_INSN (BB_END (bb)); | |
3520 | insn = NEXT_INSN (insn)) | |
3521 | { | |
3522 | if (!INSN_P (insn)) | |
3523 | continue; | |
3524 | if (insn == loop_end) | |
3525 | continue; | |
3526 | if (reg_mentioned_p (reg, PATTERN (insn))) | |
3527 | return true; | |
3528 | } | |
3529 | } | |
3c1905a4 | 3530 | return false; |
3531 | } | |
3532 | ||
917c4036 | 3533 | /* Estimate the length of INSN conservatively. */ |
3534 | ||
3535 | static int | |
3536 | length_for_loop (rtx insn) | |
3537 | { | |
3538 | int length = 0; | |
3539 | if (JUMP_P (insn) && any_condjump_p (insn) && !optimize_size) | |
3540 | { | |
709b2de5 | 3541 | if (ENABLE_WA_SPECULATIVE_SYNCS) |
917c4036 | 3542 | length = 8; |
709b2de5 | 3543 | else if (ENABLE_WA_SPECULATIVE_LOADS) |
917c4036 | 3544 | length = 6; |
3545 | } | |
3546 | else if (LABEL_P (insn)) | |
3547 | { | |
709b2de5 | 3548 | if (ENABLE_WA_SPECULATIVE_SYNCS) |
917c4036 | 3549 | length = 4; |
3550 | } | |
3551 | ||
b83e063e | 3552 | if (NONDEBUG_INSN_P (insn)) |
917c4036 | 3553 | length += get_attr_length (insn); |
3554 | ||
3555 | return length; | |
3556 | } | |
3557 | ||
3c1905a4 | 3558 | /* Optimize LOOP. */ |
3559 | ||
3560 | static void | |
3561 | bfin_optimize_loop (loop_info loop) | |
3562 | { | |
3563 | basic_block bb; | |
e82f36f5 | 3564 | loop_info inner; |
0fead507 | 3565 | rtx insn, last_insn; |
3c1905a4 | 3566 | rtx loop_init, start_label, end_label; |
3567 | rtx reg_lc0, reg_lc1, reg_lt0, reg_lt1, reg_lb0, reg_lb1; | |
8c7abb6c | 3568 | rtx iter_reg, scratchreg, scratch_init, scratch_init_insn; |
3c1905a4 | 3569 | rtx lc_reg, lt_reg, lb_reg; |
917c4036 | 3570 | rtx seq, seq_end; |
3c1905a4 | 3571 | int length; |
3572 | unsigned ix; | |
3573 | int inner_depth = 0; | |
3c1905a4 | 3574 | |
3575 | if (loop->visited) | |
3576 | return; | |
3577 | ||
3578 | loop->visited = 1; | |
3579 | ||
e82f36f5 | 3580 | if (loop->bad) |
3c1905a4 | 3581 | { |
3582 | if (dump_file) | |
3583 | fprintf (dump_file, ";; loop %d bad when found\n", loop->loop_no); | |
3584 | goto bad_loop; | |
3585 | } | |
3586 | ||
e82f36f5 | 3587 | /* Every loop contains in its list of inner loops every loop nested inside |
3588 | it, even if there are intermediate loops. This works because we're doing | |
3589 | a depth-first search here and never visit a loop more than once. */ | |
48148244 | 3590 | FOR_EACH_VEC_ELT (loop_info, loop->loops, ix, inner) |
3c1905a4 | 3591 | { |
e82f36f5 | 3592 | bfin_optimize_loop (inner); |
3c1905a4 | 3593 | |
e82f36f5 | 3594 | if (!inner->bad && inner_depth < inner->depth) |
3595 | { | |
3596 | inner_depth = inner->depth; | |
3c1905a4 | 3597 | |
e82f36f5 | 3598 | loop->clobber_loop0 |= inner->clobber_loop0; |
3599 | loop->clobber_loop1 |= inner->clobber_loop1; | |
3600 | } | |
3c1905a4 | 3601 | } |
3602 | ||
e82f36f5 | 3603 | loop->depth = inner_depth + 1; |
3604 | if (loop->depth > MAX_LOOP_DEPTH) | |
3c1905a4 | 3605 | { |
3606 | if (dump_file) | |
e82f36f5 | 3607 | fprintf (dump_file, ";; loop %d too deep\n", loop->loop_no); |
3c1905a4 | 3608 | goto bad_loop; |
3609 | } | |
3610 | ||
3611 | /* Get the loop iteration register. */ | |
3612 | iter_reg = loop->iter_reg; | |
3613 | ||
0fead507 | 3614 | if (!REG_P (iter_reg)) |
3c1905a4 | 3615 | { |
3616 | if (dump_file) | |
0fead507 | 3617 | fprintf (dump_file, ";; loop %d iteration count not in a register\n", |
3c1905a4 | 3618 | loop->loop_no); |
3619 | goto bad_loop; | |
3620 | } | |
0fead507 | 3621 | scratchreg = NULL_RTX; |
8c7abb6c | 3622 | scratch_init = iter_reg; |
3623 | scratch_init_insn = NULL_RTX; | |
0fead507 | 3624 | if (!PREG_P (iter_reg) && loop->incoming_src) |
3625 | { | |
8c7abb6c | 3626 | basic_block bb_in = loop->incoming_src; |
0fead507 | 3627 | int i; |
3628 | for (i = REG_P0; i <= REG_P5; i++) | |
3629 | if ((df_regs_ever_live_p (i) | |
3630 | || (funkind (TREE_TYPE (current_function_decl)) == SUBROUTINE | |
3631 | && call_used_regs[i])) | |
8c7abb6c | 3632 | && !REGNO_REG_SET_P (df_get_live_out (bb_in), i)) |
0fead507 | 3633 | { |
3634 | scratchreg = gen_rtx_REG (SImode, i); | |
3635 | break; | |
3636 | } | |
8c7abb6c | 3637 | for (insn = BB_END (bb_in); insn != BB_HEAD (bb_in); |
3638 | insn = PREV_INSN (insn)) | |
3639 | { | |
3640 | rtx set; | |
3641 | if (NOTE_P (insn) || BARRIER_P (insn)) | |
3642 | continue; | |
3643 | set = single_set (insn); | |
3644 | if (set && rtx_equal_p (SET_DEST (set), iter_reg)) | |
3645 | { | |
3646 | if (CONSTANT_P (SET_SRC (set))) | |
3647 | { | |
3648 | scratch_init = SET_SRC (set); | |
3649 | scratch_init_insn = insn; | |
3650 | } | |
3651 | break; | |
3652 | } | |
3653 | else if (reg_mentioned_p (iter_reg, PATTERN (insn))) | |
3654 | break; | |
3655 | } | |
0fead507 | 3656 | } |
3c1905a4 | 3657 | |
917c4036 | 3658 | if (loop->incoming_src) |
3659 | { | |
3660 | /* Make sure the predecessor is before the loop start label, as required by | |
3661 | the LSETUP instruction. */ | |
3662 | length = 0; | |
1fd36c3a | 3663 | insn = BB_END (loop->incoming_src); |
3664 | /* If we have to insert the LSETUP before a jump, count that jump in the | |
3665 | length. */ | |
3666 | if (VEC_length (edge, loop->incoming) > 1 | |
3667 | || !(VEC_last (edge, loop->incoming)->flags & EDGE_FALLTHRU)) | |
3668 | { | |
3669 | gcc_assert (JUMP_P (insn)); | |
3670 | insn = PREV_INSN (insn); | |
3671 | } | |
3672 | ||
3673 | for (; insn && insn != loop->start_label; insn = NEXT_INSN (insn)) | |
917c4036 | 3674 | length += length_for_loop (insn); |
0fead507 | 3675 | |
917c4036 | 3676 | if (!insn) |
3677 | { | |
3678 | if (dump_file) | |
3679 | fprintf (dump_file, ";; loop %d lsetup not before loop_start\n", | |
3680 | loop->loop_no); | |
3681 | goto bad_loop; | |
3682 | } | |
3683 | ||
0fead507 | 3684 | /* Account for the pop of a scratch register where necessary. */ |
3685 | if (!PREG_P (iter_reg) && scratchreg == NULL_RTX | |
3686 | && ENABLE_WA_LOAD_LCREGS) | |
3687 | length += 2; | |
3688 | ||
917c4036 | 3689 | if (length > MAX_LSETUP_DISTANCE) |
3690 | { | |
3691 | if (dump_file) | |
3692 | fprintf (dump_file, ";; loop %d lsetup too far away\n", loop->loop_no); | |
3693 | goto bad_loop; | |
3694 | } | |
3695 | } | |
3696 | ||
3c1905a4 | 3697 | /* Check if start_label appears before loop_end and calculate the |
3698 | offset between them. We calculate the length of instructions | |
3699 | conservatively. */ | |
3700 | length = 0; | |
3701 | for (insn = loop->start_label; | |
3702 | insn && insn != loop->loop_end; | |
3703 | insn = NEXT_INSN (insn)) | |
917c4036 | 3704 | length += length_for_loop (insn); |
3c1905a4 | 3705 | |
3706 | if (!insn) | |
3707 | { | |
3708 | if (dump_file) | |
3709 | fprintf (dump_file, ";; loop %d start_label not before loop_end\n", | |
3710 | loop->loop_no); | |
3711 | goto bad_loop; | |
3712 | } | |
3713 | ||
3714 | loop->length = length; | |
3715 | if (loop->length > MAX_LOOP_LENGTH) | |
3716 | { | |
3717 | if (dump_file) | |
3718 | fprintf (dump_file, ";; loop %d too long\n", loop->loop_no); | |
3719 | goto bad_loop; | |
3720 | } | |
3721 | ||
3722 | /* Scan all the blocks to make sure they don't use iter_reg. */ | |
3723 | if (bfin_scan_loop (loop, iter_reg, loop->loop_end)) | |
3724 | { | |
3725 | if (dump_file) | |
3726 | fprintf (dump_file, ";; loop %d uses iterator\n", loop->loop_no); | |
3727 | goto bad_loop; | |
3728 | } | |
3729 | ||
3730 | /* Scan all the insns to see if the loop body clobber | |
3731 | any hardware loop registers. */ | |
3732 | ||
3733 | reg_lc0 = gen_rtx_REG (SImode, REG_LC0); | |
3734 | reg_lc1 = gen_rtx_REG (SImode, REG_LC1); | |
3735 | reg_lt0 = gen_rtx_REG (SImode, REG_LT0); | |
3736 | reg_lt1 = gen_rtx_REG (SImode, REG_LT1); | |
3737 | reg_lb0 = gen_rtx_REG (SImode, REG_LB0); | |
3738 | reg_lb1 = gen_rtx_REG (SImode, REG_LB1); | |
3739 | ||
48148244 | 3740 | FOR_EACH_VEC_ELT (basic_block, loop->blocks, ix, bb) |
3c1905a4 | 3741 | { |
3742 | rtx insn; | |
3743 | ||
3744 | for (insn = BB_HEAD (bb); | |
3745 | insn != NEXT_INSN (BB_END (bb)); | |
3746 | insn = NEXT_INSN (insn)) | |
3747 | { | |
3748 | if (!INSN_P (insn)) | |
3749 | continue; | |
3750 | ||
3751 | if (reg_set_p (reg_lc0, insn) | |
3752 | || reg_set_p (reg_lt0, insn) | |
3753 | || reg_set_p (reg_lb0, insn)) | |
3754 | loop->clobber_loop0 = 1; | |
3755 | ||
3756 | if (reg_set_p (reg_lc1, insn) | |
3757 | || reg_set_p (reg_lt1, insn) | |
3758 | || reg_set_p (reg_lb1, insn)) | |
3759 | loop->clobber_loop1 |= 1; | |
3760 | } | |
3761 | } | |
3762 | ||
3763 | if ((loop->clobber_loop0 && loop->clobber_loop1) | |
3764 | || (loop->depth == MAX_LOOP_DEPTH && loop->clobber_loop0)) | |
3765 | { | |
3766 | loop->depth = MAX_LOOP_DEPTH + 1; | |
3767 | if (dump_file) | |
3768 | fprintf (dump_file, ";; loop %d no loop reg available\n", | |
3769 | loop->loop_no); | |
3770 | goto bad_loop; | |
3771 | } | |
3772 | ||
3773 | /* There should be an instruction before the loop_end instruction | |
3774 | in the same basic block. And the instruction must not be | |
3775 | - JUMP | |
3776 | - CONDITIONAL BRANCH | |
3777 | - CALL | |
3778 | - CSYNC | |
3779 | - SSYNC | |
3780 | - Returns (RTS, RTN, etc.) */ | |
3781 | ||
3782 | bb = loop->tail; | |
462ce619 | 3783 | last_insn = find_prev_insn_start (loop->loop_end); |
3c1905a4 | 3784 | |
3785 | while (1) | |
3786 | { | |
462ce619 | 3787 | for (; last_insn != BB_HEAD (bb); |
3788 | last_insn = find_prev_insn_start (last_insn)) | |
b83e063e | 3789 | if (NONDEBUG_INSN_P (last_insn)) |
3c1905a4 | 3790 | break; |
3791 | ||
462ce619 | 3792 | if (last_insn != BB_HEAD (bb)) |
3c1905a4 | 3793 | break; |
3794 | ||
3795 | if (single_pred_p (bb) | |
82adee25 | 3796 | && single_pred_edge (bb)->flags & EDGE_FALLTHRU |
3c1905a4 | 3797 | && single_pred (bb) != ENTRY_BLOCK_PTR) |
3798 | { | |
3799 | bb = single_pred (bb); | |
3800 | last_insn = BB_END (bb); | |
3801 | continue; | |
3802 | } | |
3803 | else | |
3804 | { | |
3805 | last_insn = NULL_RTX; | |
3806 | break; | |
3807 | } | |
3808 | } | |
3809 | ||
3810 | if (!last_insn) | |
3811 | { | |
3812 | if (dump_file) | |
3813 | fprintf (dump_file, ";; loop %d has no last instruction\n", | |
3814 | loop->loop_no); | |
3815 | goto bad_loop; | |
3816 | } | |
3817 | ||
2a21643e | 3818 | if (JUMP_P (last_insn) && !any_condjump_p (last_insn)) |
3c1905a4 | 3819 | { |
2a21643e | 3820 | if (dump_file) |
3821 | fprintf (dump_file, ";; loop %d has bad last instruction\n", | |
3822 | loop->loop_no); | |
3823 | goto bad_loop; | |
3824 | } | |
3825 | /* In all other cases, try to replace a bad last insn with a nop. */ | |
3826 | else if (JUMP_P (last_insn) | |
3827 | || CALL_P (last_insn) | |
3828 | || get_attr_type (last_insn) == TYPE_SYNC | |
3829 | || get_attr_type (last_insn) == TYPE_CALL | |
3830 | || get_attr_seq_insns (last_insn) == SEQ_INSNS_MULTI | |
3831 | || recog_memoized (last_insn) == CODE_FOR_return_internal | |
3832 | || GET_CODE (PATTERN (last_insn)) == ASM_INPUT | |
3833 | || asm_noperands (PATTERN (last_insn)) >= 0) | |
3834 | { | |
3835 | if (loop->length + 2 > MAX_LOOP_LENGTH) | |
3c1905a4 | 3836 | { |
3837 | if (dump_file) | |
2a21643e | 3838 | fprintf (dump_file, ";; loop %d too long\n", loop->loop_no); |
3c1905a4 | 3839 | goto bad_loop; |
3840 | } | |
3c1905a4 | 3841 | if (dump_file) |
2a21643e | 3842 | fprintf (dump_file, ";; loop %d has bad last insn; replace with nop\n", |
3c1905a4 | 3843 | loop->loop_no); |
3c1905a4 | 3844 | |
2a21643e | 3845 | last_insn = emit_insn_after (gen_forced_nop (), last_insn); |
3c1905a4 | 3846 | } |
3847 | ||
3848 | loop->last_insn = last_insn; | |
3849 | ||
3850 | /* The loop is good for replacement. */ | |
3851 | start_label = loop->start_label; | |
3852 | end_label = gen_label_rtx (); | |
3853 | iter_reg = loop->iter_reg; | |
3854 | ||
3855 | if (loop->depth == 1 && !loop->clobber_loop1) | |
3856 | { | |
3857 | lc_reg = reg_lc1; | |
3858 | lt_reg = reg_lt1; | |
3859 | lb_reg = reg_lb1; | |
3860 | loop->clobber_loop1 = 1; | |
3861 | } | |
3862 | else | |
3863 | { | |
3864 | lc_reg = reg_lc0; | |
3865 | lt_reg = reg_lt0; | |
3866 | lb_reg = reg_lb0; | |
3867 | loop->clobber_loop0 = 1; | |
3868 | } | |
3869 | ||
0fead507 | 3870 | loop->end_label = end_label; |
3871 | ||
3872 | /* Create a sequence containing the loop setup. */ | |
3873 | start_sequence (); | |
3874 | ||
3875 | /* LSETUP only accepts P registers. If we have one, we can use it, | |
3876 | otherwise there are several ways of working around the problem. | |
3877 | If we're not affected by anomaly 312, we can load the LC register | |
3878 | from any iteration register, and use LSETUP without initialization. | |
3879 | If we've found a P scratch register that's not live here, we can | |
3880 | instead copy the iter_reg into that and use an initializing LSETUP. | |
3881 | If all else fails, push and pop P0 and use it as a scratch. */ | |
3882 | if (P_REGNO_P (REGNO (iter_reg))) | |
3883 | { | |
3884 | loop_init = gen_lsetup_with_autoinit (lt_reg, start_label, | |
3885 | lb_reg, end_label, | |
3886 | lc_reg, iter_reg); | |
3887 | seq_end = emit_insn (loop_init); | |
3888 | } | |
3889 | else if (!ENABLE_WA_LOAD_LCREGS && DPREG_P (iter_reg)) | |
3c1905a4 | 3890 | { |
0fead507 | 3891 | emit_insn (gen_movsi (lc_reg, iter_reg)); |
3c1905a4 | 3892 | loop_init = gen_lsetup_without_autoinit (lt_reg, start_label, |
3893 | lb_reg, end_label, | |
3894 | lc_reg); | |
0fead507 | 3895 | seq_end = emit_insn (loop_init); |
3c1905a4 | 3896 | } |
0fead507 | 3897 | else if (scratchreg != NULL_RTX) |
3c1905a4 | 3898 | { |
8c7abb6c | 3899 | emit_insn (gen_movsi (scratchreg, scratch_init)); |
3c1905a4 | 3900 | loop_init = gen_lsetup_with_autoinit (lt_reg, start_label, |
3901 | lb_reg, end_label, | |
0fead507 | 3902 | lc_reg, scratchreg); |
3903 | seq_end = emit_insn (loop_init); | |
8c7abb6c | 3904 | if (scratch_init_insn != NULL_RTX) |
3905 | delete_insn (scratch_init_insn); | |
3c1905a4 | 3906 | } |
3907 | else | |
0fead507 | 3908 | { |
3909 | rtx p0reg = gen_rtx_REG (SImode, REG_P0); | |
3910 | rtx push = gen_frame_mem (SImode, | |
3911 | gen_rtx_PRE_DEC (SImode, stack_pointer_rtx)); | |
3912 | rtx pop = gen_frame_mem (SImode, | |
3913 | gen_rtx_POST_INC (SImode, stack_pointer_rtx)); | |
3914 | emit_insn (gen_movsi (push, p0reg)); | |
8c7abb6c | 3915 | emit_insn (gen_movsi (p0reg, scratch_init)); |
0fead507 | 3916 | loop_init = gen_lsetup_with_autoinit (lt_reg, start_label, |
3917 | lb_reg, end_label, | |
3918 | lc_reg, p0reg); | |
3919 | emit_insn (loop_init); | |
3920 | seq_end = emit_insn (gen_movsi (p0reg, pop)); | |
8c7abb6c | 3921 | if (scratch_init_insn != NULL_RTX) |
3922 | delete_insn (scratch_init_insn); | |
0fead507 | 3923 | } |
3c1905a4 | 3924 | |
3925 | if (dump_file) | |
3926 | { | |
3927 | fprintf (dump_file, ";; replacing loop %d initializer with\n", | |
3928 | loop->loop_no); | |
0fead507 | 3929 | print_rtl_single (dump_file, loop_init); |
3c1905a4 | 3930 | fprintf (dump_file, ";; replacing loop %d terminator with\n", |
3931 | loop->loop_no); | |
3932 | print_rtl_single (dump_file, loop->loop_end); | |
3933 | } | |
3934 | ||
b4e5c32d | 3935 | /* If the loop isn't entered at the top, also create a jump to the entry |
3936 | point. */ | |
3937 | if (!loop->incoming_src && loop->head != loop->incoming_dest) | |
3938 | { | |
3939 | rtx label = BB_HEAD (loop->incoming_dest); | |
3940 | /* If we're jumping to the final basic block in the loop, and there's | |
3941 | only one cheap instruction before the end (typically an increment of | |
3942 | an induction variable), we can just emit a copy here instead of a | |
3943 | jump. */ | |
3944 | if (loop->incoming_dest == loop->tail | |
3945 | && next_real_insn (label) == last_insn | |
3946 | && asm_noperands (last_insn) < 0 | |
3947 | && GET_CODE (PATTERN (last_insn)) == SET) | |
3948 | { | |
3949 | seq_end = emit_insn (copy_rtx (PATTERN (last_insn))); | |
3950 | } | |
3951 | else | |
4132c07c | 3952 | { |
3953 | emit_jump_insn (gen_jump (label)); | |
3954 | seq_end = emit_barrier (); | |
3955 | } | |
b4e5c32d | 3956 | } |
3957 | ||
3c1905a4 | 3958 | seq = get_insns (); |
3959 | end_sequence (); | |
3960 | ||
917c4036 | 3961 | if (loop->incoming_src) |
3962 | { | |
3963 | rtx prev = BB_END (loop->incoming_src); | |
3964 | if (VEC_length (edge, loop->incoming) > 1 | |
3965 | || !(VEC_last (edge, loop->incoming)->flags & EDGE_FALLTHRU)) | |
3966 | { | |
3967 | gcc_assert (JUMP_P (prev)); | |
3968 | prev = PREV_INSN (prev); | |
3969 | } | |
3970 | emit_insn_after (seq, prev); | |
3971 | } | |
3972 | else | |
3973 | { | |
3974 | basic_block new_bb; | |
3975 | edge e; | |
3976 | edge_iterator ei; | |
b4e5c32d | 3977 | |
3978 | #ifdef ENABLE_CHECKING | |
917c4036 | 3979 | if (loop->head != loop->incoming_dest) |
3980 | { | |
b4e5c32d | 3981 | /* We aren't entering the loop at the top. Since we've established |
3982 | that the loop is entered only at one point, this means there | |
3983 | can't be fallthru edges into the head. Any such fallthru edges | |
3984 | would become invalid when we insert the new block, so verify | |
3985 | that this does not in fact happen. */ | |
917c4036 | 3986 | FOR_EACH_EDGE (e, ei, loop->head->preds) |
b4e5c32d | 3987 | gcc_assert (!(e->flags & EDGE_FALLTHRU)); |
917c4036 | 3988 | } |
b4e5c32d | 3989 | #endif |
917c4036 | 3990 | |
3991 | emit_insn_before (seq, BB_HEAD (loop->head)); | |
3992 | seq = emit_label_before (gen_label_rtx (), seq); | |
3c1905a4 | 3993 | |
917c4036 | 3994 | new_bb = create_basic_block (seq, seq_end, loop->head->prev_bb); |
3995 | FOR_EACH_EDGE (e, ei, loop->incoming) | |
3996 | { | |
3997 | if (!(e->flags & EDGE_FALLTHRU) | |
3998 | || e->dest != loop->head) | |
3999 | redirect_edge_and_branch_force (e, new_bb); | |
4000 | else | |
4001 | redirect_edge_succ (e, new_bb); | |
4002 | } | |
4132c07c | 4003 | e = make_edge (new_bb, loop->head, 0); |
917c4036 | 4004 | } |
2a21643e | 4005 | |
917c4036 | 4006 | delete_insn (loop->loop_end); |
3c1905a4 | 4007 | /* Insert the loop end label before the last instruction of the loop. */ |
4008 | emit_label_before (loop->end_label, loop->last_insn); | |
4009 | ||
4010 | return; | |
4011 | ||
917c4036 | 4012 | bad_loop: |
3c1905a4 | 4013 | |
4014 | if (dump_file) | |
4015 | fprintf (dump_file, ";; loop %d is bad\n", loop->loop_no); | |
4016 | ||
e82f36f5 | 4017 | loop->bad = 1; |
3c1905a4 | 4018 | |
4019 | if (DPREG_P (loop->iter_reg)) | |
4020 | { | |
4021 | /* If loop->iter_reg is a DREG or PREG, we can split it here | |
4022 | without scratch register. */ | |
74f4459c | 4023 | rtx insn, test; |
3c1905a4 | 4024 | |
4025 | emit_insn_before (gen_addsi3 (loop->iter_reg, | |
4026 | loop->iter_reg, | |
4027 | constm1_rtx), | |
4028 | loop->loop_end); | |
4029 | ||
74f4459c | 4030 | test = gen_rtx_NE (VOIDmode, loop->iter_reg, const0_rtx); |
4031 | insn = emit_jump_insn_before (gen_cbranchsi4 (test, | |
4032 | loop->iter_reg, const0_rtx, | |
4033 | loop->start_label), | |
3c1905a4 | 4034 | loop->loop_end); |
4035 | ||
4036 | JUMP_LABEL (insn) = loop->start_label; | |
4037 | LABEL_NUSES (loop->start_label)++; | |
4038 | delete_insn (loop->loop_end); | |
4039 | } | |
4040 | } | |
4041 | ||
e82f36f5 | 4042 | /* Called from bfin_reorg_loops when a potential loop end is found. LOOP is |
4043 | a newly set up structure describing the loop, it is this function's | |
4044 | responsibility to fill most of it. TAIL_BB and TAIL_INSN point to the | |
4045 | loop_end insn and its enclosing basic block. */ | |
4046 | ||
4047 | static void | |
4048 | bfin_discover_loop (loop_info loop, basic_block tail_bb, rtx tail_insn) | |
4049 | { | |
4050 | unsigned dwork = 0; | |
4051 | basic_block bb; | |
4052 | VEC (basic_block,heap) *works = VEC_alloc (basic_block,heap,20); | |
4053 | ||
4054 | loop->tail = tail_bb; | |
4055 | loop->head = BRANCH_EDGE (tail_bb)->dest; | |
4056 | loop->successor = FALLTHRU_EDGE (tail_bb)->dest; | |
e82f36f5 | 4057 | loop->loop_end = tail_insn; |
4058 | loop->last_insn = NULL_RTX; | |
4059 | loop->iter_reg = SET_DEST (XVECEXP (PATTERN (tail_insn), 0, 1)); | |
4060 | loop->depth = loop->length = 0; | |
4061 | loop->visited = 0; | |
4062 | loop->clobber_loop0 = loop->clobber_loop1 = 0; | |
4063 | loop->outer = NULL; | |
4064 | loop->loops = NULL; | |
917c4036 | 4065 | loop->incoming = VEC_alloc (edge, gc, 2); |
e82f36f5 | 4066 | loop->start_label = XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (tail_insn), 0, 0)), 1), 0); |
4067 | loop->end_label = NULL_RTX; | |
4068 | loop->bad = 0; | |
4069 | ||
4070 | VEC_safe_push (basic_block, heap, works, loop->head); | |
4071 | ||
4072 | while (VEC_iterate (basic_block, works, dwork++, bb)) | |
4073 | { | |
4074 | edge e; | |
4075 | edge_iterator ei; | |
4076 | if (bb == EXIT_BLOCK_PTR) | |
4077 | { | |
4078 | /* We've reached the exit block. The loop must be bad. */ | |
4079 | if (dump_file) | |
4080 | fprintf (dump_file, | |
4081 | ";; Loop is bad - reached exit block while scanning\n"); | |
4082 | loop->bad = 1; | |
4083 | break; | |
4084 | } | |
4085 | ||
6ef9bbe0 | 4086 | if (!bitmap_set_bit (loop->block_bitmap, bb->index)) |
e82f36f5 | 4087 | continue; |
4088 | ||
4089 | /* We've not seen this block before. Add it to the loop's | |
4090 | list and then add each successor to the work list. */ | |
4091 | ||
4092 | VEC_safe_push (basic_block, heap, loop->blocks, bb); | |
e82f36f5 | 4093 | |
4094 | if (bb != tail_bb) | |
4095 | { | |
4096 | FOR_EACH_EDGE (e, ei, bb->succs) | |
4097 | { | |
4098 | basic_block succ = EDGE_SUCC (bb, ei.index)->dest; | |
d18119ae | 4099 | if (!REGNO_REG_SET_P (df_get_live_in (succ), |
e82f36f5 | 4100 | REGNO (loop->iter_reg))) |
4101 | continue; | |
4102 | if (!VEC_space (basic_block, works, 1)) | |
4103 | { | |
4104 | if (dwork) | |
4105 | { | |
4106 | VEC_block_remove (basic_block, works, 0, dwork); | |
4107 | dwork = 0; | |
4108 | } | |
4109 | else | |
4110 | VEC_reserve (basic_block, heap, works, 1); | |
4111 | } | |
4112 | VEC_quick_push (basic_block, works, succ); | |
4113 | } | |
4114 | } | |
4115 | } | |
4116 | ||
917c4036 | 4117 | /* Find the predecessor, and make sure nothing else jumps into this loop. */ |
e82f36f5 | 4118 | if (!loop->bad) |
4119 | { | |
917c4036 | 4120 | int pass, retry; |
48148244 | 4121 | FOR_EACH_VEC_ELT (basic_block, loop->blocks, dwork, bb) |
e82f36f5 | 4122 | { |
917c4036 | 4123 | edge e; |
4124 | edge_iterator ei; | |
4125 | FOR_EACH_EDGE (e, ei, bb->preds) | |
4126 | { | |
4127 | basic_block pred = e->src; | |
4128 | ||
4129 | if (!bfin_bb_in_loop (loop, pred)) | |
4130 | { | |
4131 | if (dump_file) | |
4132 | fprintf (dump_file, ";; Loop %d: incoming edge %d -> %d\n", | |
4133 | loop->loop_no, pred->index, | |
4134 | e->dest->index); | |
4135 | VEC_safe_push (edge, gc, loop->incoming, e); | |
4136 | } | |
4137 | } | |
e82f36f5 | 4138 | } |
4139 | ||
917c4036 | 4140 | for (pass = 0, retry = 1; retry && pass < 2; pass++) |
e82f36f5 | 4141 | { |
917c4036 | 4142 | edge e; |
4143 | edge_iterator ei; | |
4144 | bool first = true; | |
4145 | retry = 0; | |
4146 | ||
4147 | FOR_EACH_EDGE (e, ei, loop->incoming) | |
4148 | { | |
4149 | if (first) | |
4150 | { | |
4151 | loop->incoming_src = e->src; | |
4152 | loop->incoming_dest = e->dest; | |
4153 | first = false; | |
4154 | } | |
4155 | else | |
4156 | { | |
4157 | if (e->dest != loop->incoming_dest) | |
4158 | loop->incoming_dest = NULL; | |
4159 | if (e->src != loop->incoming_src) | |
4160 | loop->incoming_src = NULL; | |
4161 | } | |
4162 | if (loop->incoming_src == NULL && loop->incoming_dest == NULL) | |
4163 | { | |
4164 | if (pass == 0) | |
4165 | { | |
4166 | if (dump_file) | |
4167 | fprintf (dump_file, | |
4168 | ";; retrying loop %d with forwarder blocks\n", | |
4169 | loop->loop_no); | |
4170 | retry = 1; | |
4171 | break; | |
4172 | } | |
4173 | loop->bad = 1; | |
4174 | if (dump_file) | |
4175 | fprintf (dump_file, | |
4176 | ";; can't find suitable entry for loop %d\n", | |
4177 | loop->loop_no); | |
4178 | goto out; | |
4179 | } | |
4180 | } | |
4181 | if (retry) | |
4182 | { | |
4183 | retry = 0; | |
4184 | FOR_EACH_EDGE (e, ei, loop->incoming) | |
4185 | { | |
4186 | if (forwarder_block_p (e->src)) | |
4187 | { | |
4188 | edge e2; | |
4189 | edge_iterator ei2; | |
4190 | ||
4191 | if (dump_file) | |
4192 | fprintf (dump_file, | |
4193 | ";; Adding forwarder block %d to loop %d and retrying\n", | |
4194 | e->src->index, loop->loop_no); | |
4195 | VEC_safe_push (basic_block, heap, loop->blocks, e->src); | |
4196 | bitmap_set_bit (loop->block_bitmap, e->src->index); | |
4197 | FOR_EACH_EDGE (e2, ei2, e->src->preds) | |
4198 | VEC_safe_push (edge, gc, loop->incoming, e2); | |
4199 | VEC_unordered_remove (edge, loop->incoming, ei.index); | |
4200 | retry = 1; | |
4201 | break; | |
4202 | } | |
4203 | } | |
05f566a9 | 4204 | if (!retry) |
4205 | { | |
4206 | if (dump_file) | |
4207 | fprintf (dump_file, ";; No forwarder blocks found\n"); | |
4208 | loop->bad = 1; | |
4209 | } | |
917c4036 | 4210 | } |
e82f36f5 | 4211 | } |
4212 | } | |
4213 | ||
917c4036 | 4214 | out: |
e82f36f5 | 4215 | VEC_free (basic_block, heap, works); |
4216 | } | |
4217 | ||
917c4036 | 4218 | /* Analyze the structure of the loops in the current function. Use STACK |
4219 | for bitmap allocations. Returns all the valid candidates for hardware | |
4220 | loops found in this function. */ | |
4221 | static loop_info | |
4222 | bfin_discover_loops (bitmap_obstack *stack, FILE *dump_file) | |
3c1905a4 | 4223 | { |
3c1905a4 | 4224 | loop_info loops = NULL; |
4225 | loop_info loop; | |
917c4036 | 4226 | basic_block bb; |
4227 | bitmap tmp_bitmap; | |
3c1905a4 | 4228 | int nloops = 0; |
e82f36f5 | 4229 | |
3c1905a4 | 4230 | /* Find all the possible loop tails. This means searching for every |
4231 | loop_end instruction. For each one found, create a loop_info | |
4232 | structure and add the head block to the work list. */ | |
4233 | FOR_EACH_BB (bb) | |
4234 | { | |
4235 | rtx tail = BB_END (bb); | |
4236 | ||
4237 | while (GET_CODE (tail) == NOTE) | |
4238 | tail = PREV_INSN (tail); | |
4239 | ||
4240 | bb->aux = NULL; | |
e82f36f5 | 4241 | |
7196637a | 4242 | if (INSN_P (tail) && recog_memoized (tail) == CODE_FOR_loop_end) |
3c1905a4 | 4243 | { |
d4cae31e | 4244 | rtx insn; |
3c1905a4 | 4245 | /* A possible loop end */ |
4246 | ||
d4cae31e | 4247 | /* There's a degenerate case we can handle - an empty loop consisting |
4248 | of only a back branch. Handle that by deleting the branch. */ | |
4249 | insn = BB_HEAD (BRANCH_EDGE (bb)->dest); | |
4250 | if (next_real_insn (insn) == tail) | |
4251 | { | |
4252 | if (dump_file) | |
4253 | { | |
4254 | fprintf (dump_file, ";; degenerate loop ending at\n"); | |
4255 | print_rtl_single (dump_file, tail); | |
4256 | } | |
4257 | delete_insn_and_edges (tail); | |
4258 | continue; | |
4259 | } | |
4260 | ||
95f13934 | 4261 | loop = XNEW (struct loop_info_d); |
3c1905a4 | 4262 | loop->next = loops; |
4263 | loops = loop; | |
3c1905a4 | 4264 | loop->loop_no = nloops++; |
e82f36f5 | 4265 | loop->blocks = VEC_alloc (basic_block, heap, 20); |
917c4036 | 4266 | loop->block_bitmap = BITMAP_ALLOC (stack); |
3c1905a4 | 4267 | bb->aux = loop; |
4268 | ||
4269 | if (dump_file) | |
4270 | { | |
4271 | fprintf (dump_file, ";; potential loop %d ending at\n", | |
4272 | loop->loop_no); | |
4273 | print_rtl_single (dump_file, tail); | |
4274 | } | |
e82f36f5 | 4275 | |
4276 | bfin_discover_loop (loop, bb, tail); | |
3c1905a4 | 4277 | } |
4278 | } | |
4279 | ||
917c4036 | 4280 | tmp_bitmap = BITMAP_ALLOC (stack); |
e82f36f5 | 4281 | /* Compute loop nestings. */ |
4282 | for (loop = loops; loop; loop = loop->next) | |
4283 | { | |
4284 | loop_info other; | |
4285 | if (loop->bad) | |
4286 | continue; | |
4287 | ||
4288 | for (other = loop->next; other; other = other->next) | |
3c1905a4 | 4289 | { |
e82f36f5 | 4290 | if (other->bad) |
4291 | continue; | |
4292 | ||
4293 | bitmap_and (tmp_bitmap, other->block_bitmap, loop->block_bitmap); | |
4294 | if (bitmap_empty_p (tmp_bitmap)) | |
4295 | continue; | |
4296 | if (bitmap_equal_p (tmp_bitmap, other->block_bitmap)) | |
3c1905a4 | 4297 | { |
e82f36f5 | 4298 | other->outer = loop; |
4299 | VEC_safe_push (loop_info, heap, loop->loops, other); | |
4300 | } | |
4301 | else if (bitmap_equal_p (tmp_bitmap, loop->block_bitmap)) | |
4302 | { | |
4303 | loop->outer = other; | |
4304 | VEC_safe_push (loop_info, heap, other->loops, loop); | |
3c1905a4 | 4305 | } |
3c1905a4 | 4306 | else |
4307 | { | |
917c4036 | 4308 | if (dump_file) |
4309 | fprintf (dump_file, | |
4310 | ";; can't find suitable nesting for loops %d and %d\n", | |
4311 | loop->loop_no, other->loop_no); | |
e82f36f5 | 4312 | loop->bad = other->bad = 1; |
3c1905a4 | 4313 | } |
4314 | } | |
4315 | } | |
e82f36f5 | 4316 | BITMAP_FREE (tmp_bitmap); |
3c1905a4 | 4317 | |
917c4036 | 4318 | return loops; |
4319 | } | |
4320 | ||
4321 | /* Free up the loop structures in LOOPS. */ | |
4322 | static void | |
4323 | free_loops (loop_info loops) | |
4324 | { | |
4325 | while (loops) | |
4326 | { | |
4327 | loop_info loop = loops; | |
4328 | loops = loop->next; | |
4329 | VEC_free (loop_info, heap, loop->loops); | |
4330 | VEC_free (basic_block, heap, loop->blocks); | |
4331 | BITMAP_FREE (loop->block_bitmap); | |
4332 | XDELETE (loop); | |
4333 | } | |
4334 | } | |
4335 | ||
ec1773c6 | 4336 | #define BB_AUX_INDEX(BB) ((intptr_t)(BB)->aux) |
917c4036 | 4337 | |
4338 | /* The taken-branch edge from the loop end can actually go forward. Since the | |
4339 | Blackfin's LSETUP instruction requires that the loop end be after the loop | |
4340 | start, try to reorder a loop's basic blocks when we find such a case. */ | |
4341 | static void | |
4342 | bfin_reorder_loops (loop_info loops, FILE *dump_file) | |
4343 | { | |
4344 | basic_block bb; | |
4345 | loop_info loop; | |
4346 | ||
4347 | FOR_EACH_BB (bb) | |
4348 | bb->aux = NULL; | |
d18119ae | 4349 | cfg_layout_initialize (0); |
917c4036 | 4350 | |
4351 | for (loop = loops; loop; loop = loop->next) | |
4352 | { | |
ec1773c6 | 4353 | intptr_t index; |
917c4036 | 4354 | basic_block bb; |
4355 | edge e; | |
4356 | edge_iterator ei; | |
4357 | ||
4358 | if (loop->bad) | |
4359 | continue; | |
4360 | ||
4361 | /* Recreate an index for basic blocks that represents their order. */ | |
4362 | for (bb = ENTRY_BLOCK_PTR->next_bb, index = 0; | |
4363 | bb != EXIT_BLOCK_PTR; | |
4364 | bb = bb->next_bb, index++) | |
4365 | bb->aux = (PTR) index; | |
4366 | ||
4367 | if (BB_AUX_INDEX (loop->head) < BB_AUX_INDEX (loop->tail)) | |
4368 | continue; | |
4369 | ||
4370 | FOR_EACH_EDGE (e, ei, loop->head->succs) | |
4371 | { | |
4372 | if (bitmap_bit_p (loop->block_bitmap, e->dest->index) | |
4373 | && BB_AUX_INDEX (e->dest) < BB_AUX_INDEX (loop->tail)) | |
4374 | { | |
4375 | basic_block start_bb = e->dest; | |
4376 | basic_block start_prev_bb = start_bb->prev_bb; | |
4377 | ||
4378 | if (dump_file) | |
4379 | fprintf (dump_file, ";; Moving block %d before block %d\n", | |
4380 | loop->head->index, start_bb->index); | |
4381 | loop->head->prev_bb->next_bb = loop->head->next_bb; | |
4382 | loop->head->next_bb->prev_bb = loop->head->prev_bb; | |
4383 | ||
4384 | loop->head->prev_bb = start_prev_bb; | |
4385 | loop->head->next_bb = start_bb; | |
4386 | start_prev_bb->next_bb = start_bb->prev_bb = loop->head; | |
4387 | break; | |
4388 | } | |
4389 | } | |
4390 | loops = loops->next; | |
4391 | } | |
4392 | ||
4393 | FOR_EACH_BB (bb) | |
4394 | { | |
4395 | if (bb->next_bb != EXIT_BLOCK_PTR) | |
4396 | bb->aux = bb->next_bb; | |
4397 | else | |
4398 | bb->aux = NULL; | |
4399 | } | |
4400 | cfg_layout_finalize (); | |
d18119ae | 4401 | df_analyze (); |
917c4036 | 4402 | } |
4403 | ||
4404 | /* Run from machine_dependent_reorg, this pass looks for doloop_end insns | |
4405 | and tries to rewrite the RTL of these loops so that proper Blackfin | |
4406 | hardware loops are generated. */ | |
4407 | ||
4408 | static void | |
4409 | bfin_reorg_loops (FILE *dump_file) | |
4410 | { | |
4411 | loop_info loops = NULL; | |
4412 | loop_info loop; | |
4413 | basic_block bb; | |
4414 | bitmap_obstack stack; | |
4415 | ||
4416 | bitmap_obstack_initialize (&stack); | |
4417 | ||
4418 | if (dump_file) | |
4419 | fprintf (dump_file, ";; Find loops, first pass\n\n"); | |
4420 | ||
4421 | loops = bfin_discover_loops (&stack, dump_file); | |
4422 | ||
4423 | if (dump_file) | |
4424 | bfin_dump_loops (loops); | |
4425 | ||
4426 | bfin_reorder_loops (loops, dump_file); | |
4427 | free_loops (loops); | |
4428 | ||
4429 | if (dump_file) | |
4430 | fprintf (dump_file, ";; Find loops, second pass\n\n"); | |
4431 | ||
4432 | loops = bfin_discover_loops (&stack, dump_file); | |
3c1905a4 | 4433 | if (dump_file) |
4434 | { | |
4435 | fprintf (dump_file, ";; All loops found:\n\n"); | |
4436 | bfin_dump_loops (loops); | |
4437 | } | |
0fead507 | 4438 | |
3c1905a4 | 4439 | /* Now apply the optimizations. */ |
4440 | for (loop = loops; loop; loop = loop->next) | |
4441 | bfin_optimize_loop (loop); | |
4442 | ||
4443 | if (dump_file) | |
4444 | { | |
4445 | fprintf (dump_file, ";; After hardware loops optimization:\n\n"); | |
4446 | bfin_dump_loops (loops); | |
4447 | } | |
4448 | ||
917c4036 | 4449 | free_loops (loops); |
3c1905a4 | 4450 | |
4451 | if (dump_file) | |
4452 | print_rtl (dump_file, get_insns ()); | |
48df5a7f | 4453 | |
4454 | FOR_EACH_BB (bb) | |
4455 | bb->aux = NULL; | |
0fead507 | 4456 | |
4457 | splitting_loops = 1; | |
4458 | FOR_EACH_BB (bb) | |
4459 | { | |
4460 | rtx insn = BB_END (bb); | |
4461 | if (!JUMP_P (insn)) | |
4462 | continue; | |
4463 | ||
4464 | try_split (PATTERN (insn), insn, 1); | |
4465 | } | |
4466 | splitting_loops = 0; | |
3c1905a4 | 4467 | } |
48df5a7f | 4468 | \f |
4469 | /* Possibly generate a SEQUENCE out of three insns found in SLOT. | |
4470 | Returns true if we modified the insn chain, false otherwise. */ | |
4471 | static bool | |
4472 | gen_one_bundle (rtx slot[3]) | |
4473 | { | |
48df5a7f | 4474 | gcc_assert (slot[1] != NULL_RTX); |
4475 | ||
73c69c85 | 4476 | /* Don't add extra NOPs if optimizing for size. */ |
4477 | if (optimize_size | |
4478 | && (slot[0] == NULL_RTX || slot[2] == NULL_RTX)) | |
4479 | return false; | |
4480 | ||
48df5a7f | 4481 | /* Verify that we really can do the multi-issue. */ |
4482 | if (slot[0]) | |
4483 | { | |
4484 | rtx t = NEXT_INSN (slot[0]); | |
4485 | while (t != slot[1]) | |
4486 | { | |
4487 | if (GET_CODE (t) != NOTE | |
ad4583d9 | 4488 | || NOTE_KIND (t) != NOTE_INSN_DELETED) |
48df5a7f | 4489 | return false; |
4490 | t = NEXT_INSN (t); | |
4491 | } | |
4492 | } | |
4493 | if (slot[2]) | |
4494 | { | |
4495 | rtx t = NEXT_INSN (slot[1]); | |
4496 | while (t != slot[2]) | |
4497 | { | |
4498 | if (GET_CODE (t) != NOTE | |
ad4583d9 | 4499 | || NOTE_KIND (t) != NOTE_INSN_DELETED) |
48df5a7f | 4500 | return false; |
4501 | t = NEXT_INSN (t); | |
4502 | } | |
4503 | } | |
4504 | ||
4505 | if (slot[0] == NULL_RTX) | |
d18119ae | 4506 | { |
4507 | slot[0] = emit_insn_before (gen_mnop (), slot[1]); | |
4508 | df_insn_rescan (slot[0]); | |
4509 | } | |
48df5a7f | 4510 | if (slot[2] == NULL_RTX) |
d18119ae | 4511 | { |
4512 | slot[2] = emit_insn_after (gen_forced_nop (), slot[1]); | |
4513 | df_insn_rescan (slot[2]); | |
4514 | } | |
48df5a7f | 4515 | |
4516 | /* Avoid line number information being printed inside one bundle. */ | |
4517 | if (INSN_LOCATOR (slot[1]) | |
4518 | && INSN_LOCATOR (slot[1]) != INSN_LOCATOR (slot[0])) | |
4519 | INSN_LOCATOR (slot[1]) = INSN_LOCATOR (slot[0]); | |
4520 | if (INSN_LOCATOR (slot[2]) | |
4521 | && INSN_LOCATOR (slot[2]) != INSN_LOCATOR (slot[0])) | |
4522 | INSN_LOCATOR (slot[2]) = INSN_LOCATOR (slot[0]); | |
4523 | ||
4524 | /* Terminate them with "|| " instead of ";" in the output. */ | |
4525 | PUT_MODE (slot[0], SImode); | |
4526 | PUT_MODE (slot[1], SImode); | |
d18119ae | 4527 | /* Terminate the bundle, for the benefit of reorder_var_tracking_notes. */ |
4528 | PUT_MODE (slot[2], QImode); | |
48df5a7f | 4529 | return true; |
4530 | } | |
4531 | ||
4532 | /* Go through all insns, and use the information generated during scheduling | |
4533 | to generate SEQUENCEs to represent bundles of instructions issued | |
4534 | simultaneously. */ | |
4535 | ||
4536 | static void | |
4537 | bfin_gen_bundles (void) | |
4538 | { | |
4539 | basic_block bb; | |
4540 | FOR_EACH_BB (bb) | |
4541 | { | |
4542 | rtx insn, next; | |
4543 | rtx slot[3]; | |
4544 | int n_filled = 0; | |
4545 | ||
4546 | slot[0] = slot[1] = slot[2] = NULL_RTX; | |
4547 | for (insn = BB_HEAD (bb);; insn = next) | |
4548 | { | |
4549 | int at_end; | |
80e585b2 | 4550 | rtx delete_this = NULL_RTX; |
4551 | ||
b83e063e | 4552 | if (NONDEBUG_INSN_P (insn)) |
48df5a7f | 4553 | { |
80e585b2 | 4554 | enum attr_type type = get_attr_type (insn); |
4555 | ||
4556 | if (type == TYPE_STALL) | |
4557 | { | |
4558 | gcc_assert (n_filled == 0); | |
4559 | delete_this = insn; | |
4560 | } | |
48df5a7f | 4561 | else |
80e585b2 | 4562 | { |
6ed2288f | 4563 | if (type == TYPE_DSP32 || type == TYPE_DSP32SHIFTIMM) |
80e585b2 | 4564 | slot[0] = insn; |
4565 | else if (slot[1] == NULL_RTX) | |
4566 | slot[1] = insn; | |
4567 | else | |
4568 | slot[2] = insn; | |
4569 | n_filled++; | |
4570 | } | |
48df5a7f | 4571 | } |
4572 | ||
4573 | next = NEXT_INSN (insn); | |
4574 | while (next && insn != BB_END (bb) | |
4575 | && !(INSN_P (next) | |
4576 | && GET_CODE (PATTERN (next)) != USE | |
4577 | && GET_CODE (PATTERN (next)) != CLOBBER)) | |
4578 | { | |
4579 | insn = next; | |
4580 | next = NEXT_INSN (insn); | |
4581 | } | |
3c1905a4 | 4582 | |
48df5a7f | 4583 | /* BB_END can change due to emitting extra NOPs, so check here. */ |
4584 | at_end = insn == BB_END (bb); | |
80e585b2 | 4585 | if (delete_this == NULL_RTX && (at_end || GET_MODE (next) == TImode)) |
48df5a7f | 4586 | { |
4587 | if ((n_filled < 2 | |
4588 | || !gen_one_bundle (slot)) | |
4589 | && slot[0] != NULL_RTX) | |
4590 | { | |
4591 | rtx pat = PATTERN (slot[0]); | |
4592 | if (GET_CODE (pat) == SET | |
4593 | && GET_CODE (SET_SRC (pat)) == UNSPEC | |
4594 | && XINT (SET_SRC (pat), 1) == UNSPEC_32BIT) | |
4595 | { | |
4596 | SET_SRC (pat) = XVECEXP (SET_SRC (pat), 0, 0); | |
4597 | INSN_CODE (slot[0]) = -1; | |
d18119ae | 4598 | df_insn_rescan (slot[0]); |
48df5a7f | 4599 | } |
4600 | } | |
4601 | n_filled = 0; | |
4602 | slot[0] = slot[1] = slot[2] = NULL_RTX; | |
4603 | } | |
80e585b2 | 4604 | if (delete_this != NULL_RTX) |
4605 | delete_insn (delete_this); | |
48df5a7f | 4606 | if (at_end) |
4607 | break; | |
4608 | } | |
4609 | } | |
4610 | } | |
d18119ae | 4611 | |
4612 | /* Ensure that no var tracking notes are emitted in the middle of a | |
4613 | three-instruction bundle. */ | |
4614 | ||
4615 | static void | |
4616 | reorder_var_tracking_notes (void) | |
4617 | { | |
4618 | basic_block bb; | |
4619 | FOR_EACH_BB (bb) | |
4620 | { | |
4621 | rtx insn, next; | |
4622 | rtx queue = NULL_RTX; | |
4623 | bool in_bundle = false; | |
4624 | ||
4625 | for (insn = BB_HEAD (bb); insn != BB_END (bb); insn = next) | |
4626 | { | |
4627 | next = NEXT_INSN (insn); | |
4628 | ||
4629 | if (INSN_P (insn)) | |
4630 | { | |
4631 | /* Emit queued up notes at the last instruction of a bundle. */ | |
4632 | if (GET_MODE (insn) == QImode) | |
4633 | { | |
4634 | while (queue) | |
4635 | { | |
4636 | rtx next_queue = PREV_INSN (queue); | |
4637 | PREV_INSN (NEXT_INSN (insn)) = queue; | |
4638 | NEXT_INSN (queue) = NEXT_INSN (insn); | |
4639 | NEXT_INSN (insn) = queue; | |
4640 | PREV_INSN (queue) = insn; | |
4641 | queue = next_queue; | |
4642 | } | |
4643 | in_bundle = false; | |
4644 | } | |
4645 | else if (GET_MODE (insn) == SImode) | |
4646 | in_bundle = true; | |
4647 | } | |
4648 | else if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_VAR_LOCATION) | |
4649 | { | |
4650 | if (in_bundle) | |
4651 | { | |
4652 | rtx prev = PREV_INSN (insn); | |
4653 | PREV_INSN (next) = prev; | |
4654 | NEXT_INSN (prev) = next; | |
4655 | ||
4656 | PREV_INSN (insn) = queue; | |
4657 | queue = insn; | |
4658 | } | |
4659 | } | |
4660 | } | |
4661 | } | |
4662 | } | |
9e6a0967 | 4663 | \f |
0d65fac2 | 4664 | /* On some silicon revisions, functions shorter than a certain number of cycles |
4665 | can cause unpredictable behaviour. Work around this by adding NOPs as | |
4666 | needed. */ | |
4667 | static void | |
4668 | workaround_rts_anomaly (void) | |
4669 | { | |
4670 | rtx insn, first_insn = NULL_RTX; | |
4671 | int cycles = 4; | |
4672 | ||
4673 | if (! ENABLE_WA_RETS) | |
4674 | return; | |
4675 | ||
4676 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
4677 | { | |
4678 | rtx pat; | |
4679 | ||
4680 | if (BARRIER_P (insn)) | |
4681 | return; | |
4682 | ||
4683 | if (NOTE_P (insn) || LABEL_P (insn)) | |
4684 | continue; | |
4685 | ||
4686 | if (first_insn == NULL_RTX) | |
4687 | first_insn = insn; | |
4688 | pat = PATTERN (insn); | |
4689 | if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER | |
4690 | || GET_CODE (pat) == ASM_INPUT || GET_CODE (pat) == ADDR_VEC | |
4691 | || GET_CODE (pat) == ADDR_DIFF_VEC || asm_noperands (pat) >= 0) | |
4692 | continue; | |
4693 | ||
4694 | if (CALL_P (insn)) | |
4695 | return; | |
4696 | ||
4697 | if (JUMP_P (insn)) | |
4698 | { | |
4699 | if (recog_memoized (insn) == CODE_FOR_return_internal) | |
4700 | break; | |
4701 | ||
4702 | /* Nothing to worry about for direct jumps. */ | |
4703 | if (!any_condjump_p (insn)) | |
4704 | return; | |
4705 | if (cycles <= 1) | |
4706 | return; | |
4707 | cycles--; | |
4708 | } | |
4709 | else if (INSN_P (insn)) | |
4710 | { | |
4711 | rtx pat = PATTERN (insn); | |
4712 | int this_cycles = 1; | |
4713 | ||
4714 | if (GET_CODE (pat) == PARALLEL) | |
4715 | { | |
4716 | if (push_multiple_operation (pat, VOIDmode) | |
4717 | || pop_multiple_operation (pat, VOIDmode)) | |
4718 | this_cycles = n_regs_to_save; | |
4719 | } | |
4720 | else | |
4721 | { | |
95f13934 | 4722 | int icode = recog_memoized (insn); |
4723 | ||
0d65fac2 | 4724 | if (icode == CODE_FOR_link) |
4725 | this_cycles = 4; | |
4726 | else if (icode == CODE_FOR_unlink) | |
4727 | this_cycles = 3; | |
4728 | else if (icode == CODE_FOR_mulsi3) | |
4729 | this_cycles = 5; | |
4730 | } | |
4731 | if (this_cycles >= cycles) | |
4732 | return; | |
4733 | ||
4734 | cycles -= this_cycles; | |
4735 | } | |
4736 | } | |
4737 | while (cycles > 0) | |
4738 | { | |
4739 | emit_insn_before (gen_nop (), first_insn); | |
4740 | cycles--; | |
4741 | } | |
4742 | } | |
4743 | ||
48df5a7f | 4744 | /* Return an insn type for INSN that can be used by the caller for anomaly |
4745 | workarounds. This differs from plain get_attr_type in that it handles | |
4746 | SEQUENCEs. */ | |
4747 | ||
4748 | static enum attr_type | |
4749 | type_for_anomaly (rtx insn) | |
4750 | { | |
4751 | rtx pat = PATTERN (insn); | |
4752 | if (GET_CODE (pat) == SEQUENCE) | |
4753 | { | |
4754 | enum attr_type t; | |
4755 | t = get_attr_type (XVECEXP (pat, 0, 1)); | |
4756 | if (t == TYPE_MCLD) | |
4757 | return t; | |
4758 | t = get_attr_type (XVECEXP (pat, 0, 2)); | |
4759 | if (t == TYPE_MCLD) | |
4760 | return t; | |
4761 | return TYPE_MCST; | |
4762 | } | |
4763 | else | |
4764 | return get_attr_type (insn); | |
4765 | } | |
4766 | ||
e36d8ec6 | 4767 | /* Return true iff the address found in MEM is based on the register |
4768 | NP_REG and optionally has a positive offset. */ | |
48df5a7f | 4769 | static bool |
e36d8ec6 | 4770 | harmless_null_pointer_p (rtx mem, int np_reg) |
48df5a7f | 4771 | { |
e36d8ec6 | 4772 | mem = XEXP (mem, 0); |
4773 | if (GET_CODE (mem) == POST_INC || GET_CODE (mem) == POST_DEC) | |
4774 | mem = XEXP (mem, 0); | |
95f13934 | 4775 | if (REG_P (mem) && (int) REGNO (mem) == np_reg) |
e36d8ec6 | 4776 | return true; |
4777 | if (GET_CODE (mem) == PLUS | |
95f13934 | 4778 | && REG_P (XEXP (mem, 0)) && (int) REGNO (XEXP (mem, 0)) == np_reg) |
48df5a7f | 4779 | { |
e36d8ec6 | 4780 | mem = XEXP (mem, 1); |
4781 | if (GET_CODE (mem) == CONST_INT && INTVAL (mem) > 0) | |
48df5a7f | 4782 | return true; |
48df5a7f | 4783 | } |
e36d8ec6 | 4784 | return false; |
4785 | } | |
4786 | ||
4787 | /* Return nonzero if INSN contains any loads that may trap. */ | |
4788 | ||
4789 | static bool | |
4790 | trapping_loads_p (rtx insn, int np_reg, bool after_np_branch) | |
4791 | { | |
e36d8ec6 | 4792 | rtx mem = SET_SRC (single_set (insn)); |
4793 | ||
4794 | if (!after_np_branch) | |
4795 | np_reg = -1; | |
4796 | return ((np_reg == -1 || !harmless_null_pointer_p (mem, np_reg)) | |
4797 | && may_trap_p (mem)); | |
48df5a7f | 4798 | } |
4799 | ||
771ce05e | 4800 | /* Return INSN if it is of TYPE_MCLD. Alternatively, if INSN is the start of |
4801 | a three-insn bundle, see if one of them is a load and return that if so. | |
4802 | Return NULL_RTX if the insn does not contain loads. */ | |
4803 | static rtx | |
4804 | find_load (rtx insn) | |
4805 | { | |
b83e063e | 4806 | if (!NONDEBUG_INSN_P (insn)) |
4807 | return NULL_RTX; | |
771ce05e | 4808 | if (get_attr_type (insn) == TYPE_MCLD) |
4809 | return insn; | |
4810 | if (GET_MODE (insn) != SImode) | |
4811 | return NULL_RTX; | |
4812 | do { | |
4813 | insn = NEXT_INSN (insn); | |
4814 | if ((GET_MODE (insn) == SImode || GET_MODE (insn) == QImode) | |
4815 | && get_attr_type (insn) == TYPE_MCLD) | |
4816 | return insn; | |
4817 | } while (GET_MODE (insn) != QImode); | |
4818 | return NULL_RTX; | |
4819 | } | |
4820 | ||
7f242caa | 4821 | /* Determine whether PAT is an indirect call pattern. */ |
4822 | static bool | |
4823 | indirect_call_p (rtx pat) | |
4824 | { | |
4825 | if (GET_CODE (pat) == PARALLEL) | |
4826 | pat = XVECEXP (pat, 0, 0); | |
4827 | if (GET_CODE (pat) == SET) | |
4828 | pat = SET_SRC (pat); | |
4829 | gcc_assert (GET_CODE (pat) == CALL); | |
4830 | pat = XEXP (pat, 0); | |
4831 | gcc_assert (GET_CODE (pat) == MEM); | |
4832 | pat = XEXP (pat, 0); | |
4833 | ||
4834 | return REG_P (pat); | |
4835 | } | |
4836 | ||
e36d8ec6 | 4837 | /* During workaround_speculation, track whether we're in the shadow of a |
4838 | conditional branch that tests a P register for NULL. If so, we can omit | |
4839 | emitting NOPs if we see a load from that P register, since a speculative | |
4840 | access at address 0 isn't a problem, and the load is executed in all other | |
4841 | cases anyway. | |
4842 | Global for communication with note_np_check_stores through note_stores. | |
4843 | */ | |
4844 | int np_check_regno = -1; | |
4845 | bool np_after_branch = false; | |
4846 | ||
4847 | /* Subroutine of workaround_speculation, called through note_stores. */ | |
4848 | static void | |
95f13934 | 4849 | note_np_check_stores (rtx x, const_rtx pat ATTRIBUTE_UNUSED, |
4850 | void *data ATTRIBUTE_UNUSED) | |
e36d8ec6 | 4851 | { |
95f13934 | 4852 | if (REG_P (x) && (REGNO (x) == REG_CC || (int) REGNO (x) == np_check_regno)) |
e36d8ec6 | 4853 | np_check_regno = -1; |
4854 | } | |
4855 | ||
9e6a0967 | 4856 | static void |
0d65fac2 | 4857 | workaround_speculation (void) |
9e6a0967 | 4858 | { |
771ce05e | 4859 | rtx insn, next; |
4860 | rtx last_condjump = NULL_RTX; | |
9e6a0967 | 4861 | int cycles_since_jump = INT_MAX; |
cedee41a | 4862 | int delay_added = 0; |
9e6a0967 | 4863 | |
7f242caa | 4864 | if (! ENABLE_WA_SPECULATIVE_LOADS && ! ENABLE_WA_SPECULATIVE_SYNCS |
4865 | && ! ENABLE_WA_INDIRECT_CALLS) | |
9e6a0967 | 4866 | return; |
4867 | ||
b00f0d99 | 4868 | /* First pass: find predicted-false branches; if something after them |
4869 | needs nops, insert them or change the branch to predict true. */ | |
771ce05e | 4870 | for (insn = get_insns (); insn; insn = next) |
9e6a0967 | 4871 | { |
4872 | rtx pat; | |
cedee41a | 4873 | int delay_needed = 0; |
9e6a0967 | 4874 | |
771ce05e | 4875 | next = find_next_insn_start (insn); |
4876 | ||
e36d8ec6 | 4877 | if (NOTE_P (insn) || BARRIER_P (insn)) |
9e6a0967 | 4878 | continue; |
4879 | ||
e36d8ec6 | 4880 | if (LABEL_P (insn)) |
4881 | { | |
4882 | np_check_regno = -1; | |
4883 | continue; | |
4884 | } | |
4885 | ||
9e6a0967 | 4886 | pat = PATTERN (insn); |
4887 | if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER | |
e36d8ec6 | 4888 | || GET_CODE (pat) == ADDR_VEC || GET_CODE (pat) == ADDR_DIFF_VEC) |
9e6a0967 | 4889 | continue; |
e36d8ec6 | 4890 | |
4891 | if (GET_CODE (pat) == ASM_INPUT || asm_noperands (pat) >= 0) | |
4892 | { | |
4893 | np_check_regno = -1; | |
4894 | continue; | |
4895 | } | |
9e6a0967 | 4896 | |
4897 | if (JUMP_P (insn)) | |
4898 | { | |
e36d8ec6 | 4899 | /* Is this a condjump based on a null pointer comparison we saw |
4900 | earlier? */ | |
4901 | if (np_check_regno != -1 | |
4902 | && recog_memoized (insn) == CODE_FOR_cbranchbi4) | |
4903 | { | |
4904 | rtx op = XEXP (SET_SRC (PATTERN (insn)), 0); | |
4905 | gcc_assert (GET_CODE (op) == EQ || GET_CODE (op) == NE); | |
4906 | if (GET_CODE (op) == NE) | |
4907 | np_after_branch = true; | |
4908 | } | |
9e6a0967 | 4909 | if (any_condjump_p (insn) |
4910 | && ! cbranch_predicted_taken_p (insn)) | |
4911 | { | |
4912 | last_condjump = insn; | |
cedee41a | 4913 | delay_added = 0; |
9e6a0967 | 4914 | cycles_since_jump = 0; |
4915 | } | |
4916 | else | |
4917 | cycles_since_jump = INT_MAX; | |
4918 | } | |
7f242caa | 4919 | else if (CALL_P (insn)) |
4920 | { | |
e36d8ec6 | 4921 | np_check_regno = -1; |
7f242caa | 4922 | if (cycles_since_jump < INT_MAX) |
4923 | cycles_since_jump++; | |
4924 | if (indirect_call_p (pat) && ENABLE_WA_INDIRECT_CALLS) | |
4925 | { | |
4926 | delay_needed = 3; | |
4927 | } | |
4928 | } | |
b83e063e | 4929 | else if (NONDEBUG_INSN_P (insn)) |
9e6a0967 | 4930 | { |
771ce05e | 4931 | rtx load_insn = find_load (insn); |
48df5a7f | 4932 | enum attr_type type = type_for_anomaly (insn); |
cedee41a | 4933 | |
9e6a0967 | 4934 | if (cycles_since_jump < INT_MAX) |
4935 | cycles_since_jump++; | |
4936 | ||
e36d8ec6 | 4937 | /* Detect a comparison of a P register with zero. If we later |
4938 | see a condjump based on it, we have found a null pointer | |
4939 | check. */ | |
4940 | if (recog_memoized (insn) == CODE_FOR_compare_eq) | |
4941 | { | |
4942 | rtx src = SET_SRC (PATTERN (insn)); | |
4943 | if (REG_P (XEXP (src, 0)) | |
4944 | && P_REGNO_P (REGNO (XEXP (src, 0))) | |
4945 | && XEXP (src, 1) == const0_rtx) | |
4946 | { | |
4947 | np_check_regno = REGNO (XEXP (src, 0)); | |
4948 | np_after_branch = false; | |
4949 | } | |
4950 | else | |
4951 | np_check_regno = -1; | |
4952 | } | |
4953 | ||
709b2de5 | 4954 | if (load_insn && ENABLE_WA_SPECULATIVE_LOADS) |
b00f0d99 | 4955 | { |
e36d8ec6 | 4956 | if (trapping_loads_p (load_insn, np_check_regno, |
4957 | np_after_branch)) | |
cedee41a | 4958 | delay_needed = 4; |
b00f0d99 | 4959 | } |
709b2de5 | 4960 | else if (type == TYPE_SYNC && ENABLE_WA_SPECULATIVE_SYNCS) |
cedee41a | 4961 | delay_needed = 3; |
e36d8ec6 | 4962 | |
4963 | /* See if we need to forget about a null pointer comparison | |
4964 | we found earlier. */ | |
4965 | if (recog_memoized (insn) != CODE_FOR_compare_eq) | |
4966 | { | |
4967 | note_stores (PATTERN (insn), note_np_check_stores, NULL); | |
4968 | if (np_check_regno != -1) | |
4969 | { | |
4970 | if (find_regno_note (insn, REG_INC, np_check_regno)) | |
4971 | np_check_regno = -1; | |
4972 | } | |
4973 | } | |
4974 | ||
cedee41a | 4975 | } |
b00f0d99 | 4976 | |
cedee41a | 4977 | if (delay_needed > cycles_since_jump |
4978 | && (delay_needed - cycles_since_jump) > delay_added) | |
4979 | { | |
4980 | rtx pat1; | |
4981 | int num_clobbers; | |
4982 | rtx *op = recog_data.operand; | |
9e6a0967 | 4983 | |
cedee41a | 4984 | delay_needed -= cycles_since_jump; |
b00f0d99 | 4985 | |
cedee41a | 4986 | extract_insn (last_condjump); |
4987 | if (optimize_size) | |
4988 | { | |
4989 | pat1 = gen_cbranch_predicted_taken (op[0], op[1], op[2], | |
4990 | op[3]); | |
4991 | cycles_since_jump = INT_MAX; | |
4992 | } | |
4993 | else | |
4994 | { | |
4995 | /* Do not adjust cycles_since_jump in this case, so that | |
4996 | we'll increase the number of NOPs for a subsequent insn | |
4997 | if necessary. */ | |
4998 | pat1 = gen_cbranch_with_nops (op[0], op[1], op[2], op[3], | |
4999 | GEN_INT (delay_needed)); | |
5000 | delay_added = delay_needed; | |
b00f0d99 | 5001 | } |
cedee41a | 5002 | PATTERN (last_condjump) = pat1; |
5003 | INSN_CODE (last_condjump) = recog (pat1, insn, &num_clobbers); | |
5004 | } | |
5005 | if (CALL_P (insn)) | |
5006 | { | |
5007 | cycles_since_jump = INT_MAX; | |
5008 | delay_added = 0; | |
b00f0d99 | 5009 | } |
5010 | } | |
cedee41a | 5011 | |
b00f0d99 | 5012 | /* Second pass: for predicted-true branches, see if anything at the |
5013 | branch destination needs extra nops. */ | |
b00f0d99 | 5014 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
5015 | { | |
0d65fac2 | 5016 | int cycles_since_jump; |
b00f0d99 | 5017 | if (JUMP_P (insn) |
5018 | && any_condjump_p (insn) | |
5019 | && (INSN_CODE (insn) == CODE_FOR_cbranch_predicted_taken | |
5020 | || cbranch_predicted_taken_p (insn))) | |
5021 | { | |
5022 | rtx target = JUMP_LABEL (insn); | |
5023 | rtx label = target; | |
cedee41a | 5024 | rtx next_tgt; |
5025 | ||
b00f0d99 | 5026 | cycles_since_jump = 0; |
cedee41a | 5027 | for (; target && cycles_since_jump < 3; target = next_tgt) |
b00f0d99 | 5028 | { |
5029 | rtx pat; | |
5030 | ||
cedee41a | 5031 | next_tgt = find_next_insn_start (target); |
5032 | ||
b00f0d99 | 5033 | if (NOTE_P (target) || BARRIER_P (target) || LABEL_P (target)) |
5034 | continue; | |
5035 | ||
5036 | pat = PATTERN (target); | |
5037 | if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER | |
5038 | || GET_CODE (pat) == ASM_INPUT || GET_CODE (pat) == ADDR_VEC | |
5039 | || GET_CODE (pat) == ADDR_DIFF_VEC || asm_noperands (pat) >= 0) | |
5040 | continue; | |
5041 | ||
b83e063e | 5042 | if (NONDEBUG_INSN_P (target)) |
b00f0d99 | 5043 | { |
cedee41a | 5044 | rtx load_insn = find_load (target); |
48df5a7f | 5045 | enum attr_type type = type_for_anomaly (target); |
b00f0d99 | 5046 | int delay_needed = 0; |
5047 | if (cycles_since_jump < INT_MAX) | |
5048 | cycles_since_jump++; | |
5049 | ||
cedee41a | 5050 | if (load_insn && ENABLE_WA_SPECULATIVE_LOADS) |
5051 | { | |
e36d8ec6 | 5052 | if (trapping_loads_p (load_insn, -1, false)) |
cedee41a | 5053 | delay_needed = 2; |
5054 | } | |
5055 | else if (type == TYPE_SYNC && ENABLE_WA_SPECULATIVE_SYNCS) | |
b00f0d99 | 5056 | delay_needed = 2; |
5057 | ||
5058 | if (delay_needed > cycles_since_jump) | |
5059 | { | |
5060 | rtx prev = prev_real_insn (label); | |
5061 | delay_needed -= cycles_since_jump; | |
5062 | if (dump_file) | |
5063 | fprintf (dump_file, "Adding %d nops after %d\n", | |
5064 | delay_needed, INSN_UID (label)); | |
5065 | if (JUMP_P (prev) | |
5066 | && INSN_CODE (prev) == CODE_FOR_cbranch_with_nops) | |
5067 | { | |
5068 | rtx x; | |
5069 | HOST_WIDE_INT v; | |
5070 | ||
5071 | if (dump_file) | |
5072 | fprintf (dump_file, | |
5073 | "Reducing nops on insn %d.\n", | |
5074 | INSN_UID (prev)); | |
5075 | x = PATTERN (prev); | |
5076 | x = XVECEXP (x, 0, 1); | |
5077 | v = INTVAL (XVECEXP (x, 0, 0)) - delay_needed; | |
5078 | XVECEXP (x, 0, 0) = GEN_INT (v); | |
5079 | } | |
5080 | while (delay_needed-- > 0) | |
5081 | emit_insn_after (gen_nop (), label); | |
5082 | break; | |
5083 | } | |
5084 | } | |
9e6a0967 | 5085 | } |
5086 | } | |
5087 | } | |
0d65fac2 | 5088 | } |
5089 | ||
80e585b2 | 5090 | /* Called just before the final scheduling pass. If we need to insert NOPs |
5091 | later on to work around speculative loads, insert special placeholder | |
5092 | insns that cause loads to be delayed for as many cycles as necessary | |
5093 | (and possible). This reduces the number of NOPs we need to add. | |
5094 | The dummy insns we generate are later removed by bfin_gen_bundles. */ | |
5095 | static void | |
5096 | add_sched_insns_for_speculation (void) | |
5097 | { | |
5098 | rtx insn; | |
5099 | ||
5100 | if (! ENABLE_WA_SPECULATIVE_LOADS && ! ENABLE_WA_SPECULATIVE_SYNCS | |
5101 | && ! ENABLE_WA_INDIRECT_CALLS) | |
5102 | return; | |
5103 | ||
5104 | /* First pass: find predicted-false branches; if something after them | |
5105 | needs nops, insert them or change the branch to predict true. */ | |
5106 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
5107 | { | |
5108 | rtx pat; | |
5109 | ||
5110 | if (NOTE_P (insn) || BARRIER_P (insn) || LABEL_P (insn)) | |
5111 | continue; | |
5112 | ||
5113 | pat = PATTERN (insn); | |
5114 | if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER | |
5115 | || GET_CODE (pat) == ASM_INPUT || GET_CODE (pat) == ADDR_VEC | |
5116 | || GET_CODE (pat) == ADDR_DIFF_VEC || asm_noperands (pat) >= 0) | |
5117 | continue; | |
5118 | ||
5119 | if (JUMP_P (insn)) | |
5120 | { | |
5121 | if (any_condjump_p (insn) | |
5122 | && !cbranch_predicted_taken_p (insn)) | |
5123 | { | |
5124 | rtx n = next_real_insn (insn); | |
5125 | emit_insn_before (gen_stall (GEN_INT (3)), n); | |
5126 | } | |
5127 | } | |
5128 | } | |
5129 | ||
5130 | /* Second pass: for predicted-true branches, see if anything at the | |
5131 | branch destination needs extra nops. */ | |
5132 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
5133 | { | |
5134 | if (JUMP_P (insn) | |
5135 | && any_condjump_p (insn) | |
5136 | && (cbranch_predicted_taken_p (insn))) | |
5137 | { | |
5138 | rtx target = JUMP_LABEL (insn); | |
5139 | rtx next = next_real_insn (target); | |
5140 | ||
5141 | if (GET_CODE (PATTERN (next)) == UNSPEC_VOLATILE | |
5142 | && get_attr_type (next) == TYPE_STALL) | |
5143 | continue; | |
5144 | emit_insn_before (gen_stall (GEN_INT (1)), next); | |
5145 | } | |
5146 | } | |
5147 | } | |
5148 | ||
0d65fac2 | 5149 | /* We use the machine specific reorg pass for emitting CSYNC instructions |
5150 | after conditional branches as needed. | |
5151 | ||
5152 | The Blackfin is unusual in that a code sequence like | |
5153 | if cc jump label | |
5154 | r0 = (p0) | |
5155 | may speculatively perform the load even if the condition isn't true. This | |
5156 | happens for a branch that is predicted not taken, because the pipeline | |
5157 | isn't flushed or stalled, so the early stages of the following instructions, | |
5158 | which perform the memory reference, are allowed to execute before the | |
5159 | jump condition is evaluated. | |
5160 | Therefore, we must insert additional instructions in all places where this | |
5161 | could lead to incorrect behavior. The manual recommends CSYNC, while | |
5162 | VDSP seems to use NOPs (even though its corresponding compiler option is | |
5163 | named CSYNC). | |
5164 | ||
5165 | When optimizing for speed, we emit NOPs, which seems faster than a CSYNC. | |
5166 | When optimizing for size, we turn the branch into a predicted taken one. | |
5167 | This may be slower due to mispredicts, but saves code size. */ | |
5168 | ||
5169 | static void | |
5170 | bfin_reorg (void) | |
5171 | { | |
5172 | /* We are freeing block_for_insn in the toplev to keep compatibility | |
5173 | with old MDEP_REORGS that are not CFG based. Recompute it now. */ | |
5174 | compute_bb_for_insn (); | |
5175 | ||
8a42230a | 5176 | if (flag_schedule_insns_after_reload) |
0d65fac2 | 5177 | { |
5178 | splitting_for_sched = 1; | |
5179 | split_all_insns (); | |
5180 | splitting_for_sched = 0; | |
5181 | ||
80e585b2 | 5182 | add_sched_insns_for_speculation (); |
5183 | ||
0d65fac2 | 5184 | timevar_push (TV_SCHED2); |
f5a15437 | 5185 | if (flag_selective_scheduling2 |
5186 | && !maybe_skip_selective_scheduling ()) | |
5187 | run_selective_scheduling (); | |
5188 | else | |
5189 | schedule_insns (); | |
0d65fac2 | 5190 | timevar_pop (TV_SCHED2); |
5191 | ||
5192 | /* Examine the schedule and insert nops as necessary for 64-bit parallel | |
5193 | instructions. */ | |
5194 | bfin_gen_bundles (); | |
5195 | } | |
5196 | ||
5197 | df_analyze (); | |
5198 | ||
5199 | /* Doloop optimization */ | |
5200 | if (cfun->machine->has_hardware_loops) | |
5201 | bfin_reorg_loops (dump_file); | |
5202 | ||
5203 | workaround_speculation (); | |
48df5a7f | 5204 | |
8a42230a | 5205 | if (flag_var_tracking) |
48df5a7f | 5206 | { |
5207 | timevar_push (TV_VAR_TRACKING); | |
5208 | variable_tracking_main (); | |
d18119ae | 5209 | reorder_var_tracking_notes (); |
48df5a7f | 5210 | timevar_pop (TV_VAR_TRACKING); |
5211 | } | |
0d65fac2 | 5212 | |
314966f4 | 5213 | df_finish_pass (false); |
0d65fac2 | 5214 | |
5215 | workaround_rts_anomaly (); | |
9e6a0967 | 5216 | } |
5217 | \f | |
5218 | /* Handle interrupt_handler, exception_handler and nmi_handler function | |
5219 | attributes; arguments as in struct attribute_spec.handler. */ | |
5220 | ||
5221 | static tree | |
5222 | handle_int_attribute (tree *node, tree name, | |
5223 | tree args ATTRIBUTE_UNUSED, | |
5224 | int flags ATTRIBUTE_UNUSED, | |
5225 | bool *no_add_attrs) | |
5226 | { | |
5227 | tree x = *node; | |
5228 | if (TREE_CODE (x) == FUNCTION_DECL) | |
5229 | x = TREE_TYPE (x); | |
5230 | ||
5231 | if (TREE_CODE (x) != FUNCTION_TYPE) | |
5232 | { | |
67a779df | 5233 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
5234 | name); | |
9e6a0967 | 5235 | *no_add_attrs = true; |
5236 | } | |
5237 | else if (funkind (x) != SUBROUTINE) | |
5238 | error ("multiple function type attributes specified"); | |
5239 | ||
5240 | return NULL_TREE; | |
5241 | } | |
5242 | ||
5243 | /* Return 0 if the attributes for two types are incompatible, 1 if they | |
5244 | are compatible, and 2 if they are nearly compatible (which causes a | |
5245 | warning to be generated). */ | |
5246 | ||
5247 | static int | |
a9f1838b | 5248 | bfin_comp_type_attributes (const_tree type1, const_tree type2) |
9e6a0967 | 5249 | { |
5250 | e_funkind kind1, kind2; | |
5251 | ||
5252 | if (TREE_CODE (type1) != FUNCTION_TYPE) | |
5253 | return 1; | |
5254 | ||
5255 | kind1 = funkind (type1); | |
5256 | kind2 = funkind (type2); | |
5257 | ||
5258 | if (kind1 != kind2) | |
5259 | return 0; | |
5260 | ||
5261 | /* Check for mismatched modifiers */ | |
5262 | if (!lookup_attribute ("nesting", TYPE_ATTRIBUTES (type1)) | |
5263 | != !lookup_attribute ("nesting", TYPE_ATTRIBUTES (type2))) | |
5264 | return 0; | |
5265 | ||
5266 | if (!lookup_attribute ("saveall", TYPE_ATTRIBUTES (type1)) | |
5267 | != !lookup_attribute ("saveall", TYPE_ATTRIBUTES (type2))) | |
5268 | return 0; | |
5269 | ||
5270 | if (!lookup_attribute ("kspisusp", TYPE_ATTRIBUTES (type1)) | |
5271 | != !lookup_attribute ("kspisusp", TYPE_ATTRIBUTES (type2))) | |
5272 | return 0; | |
5273 | ||
7b6ef6dd | 5274 | if (!lookup_attribute ("longcall", TYPE_ATTRIBUTES (type1)) |
5275 | != !lookup_attribute ("longcall", TYPE_ATTRIBUTES (type2))) | |
5276 | return 0; | |
5277 | ||
9e6a0967 | 5278 | return 1; |
5279 | } | |
5280 | ||
7b6ef6dd | 5281 | /* Handle a "longcall" or "shortcall" attribute; arguments as in |
5282 | struct attribute_spec.handler. */ | |
5283 | ||
5284 | static tree | |
5285 | bfin_handle_longcall_attribute (tree *node, tree name, | |
5286 | tree args ATTRIBUTE_UNUSED, | |
5287 | int flags ATTRIBUTE_UNUSED, | |
5288 | bool *no_add_attrs) | |
5289 | { | |
5290 | if (TREE_CODE (*node) != FUNCTION_TYPE | |
5291 | && TREE_CODE (*node) != FIELD_DECL | |
5292 | && TREE_CODE (*node) != TYPE_DECL) | |
5293 | { | |
67a779df | 5294 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
5295 | name); | |
7b6ef6dd | 5296 | *no_add_attrs = true; |
5297 | } | |
5298 | ||
5299 | if ((strcmp (IDENTIFIER_POINTER (name), "longcall") == 0 | |
5300 | && lookup_attribute ("shortcall", TYPE_ATTRIBUTES (*node))) | |
5301 | || (strcmp (IDENTIFIER_POINTER (name), "shortcall") == 0 | |
5302 | && lookup_attribute ("longcall", TYPE_ATTRIBUTES (*node)))) | |
5303 | { | |
5304 | warning (OPT_Wattributes, | |
bf776685 | 5305 | "can%'t apply both longcall and shortcall attributes to the same function"); |
7b6ef6dd | 5306 | *no_add_attrs = true; |
5307 | } | |
5308 | ||
5309 | return NULL_TREE; | |
5310 | } | |
5311 | ||
fc8aef7f | 5312 | /* Handle a "l1_text" attribute; arguments as in |
5313 | struct attribute_spec.handler. */ | |
5314 | ||
5315 | static tree | |
5316 | bfin_handle_l1_text_attribute (tree *node, tree name, tree ARG_UNUSED (args), | |
5317 | int ARG_UNUSED (flags), bool *no_add_attrs) | |
5318 | { | |
5319 | tree decl = *node; | |
5320 | ||
5321 | if (TREE_CODE (decl) != FUNCTION_DECL) | |
5322 | { | |
67a779df | 5323 | error ("%qE attribute only applies to functions", |
5324 | name); | |
fc8aef7f | 5325 | *no_add_attrs = true; |
5326 | } | |
5327 | ||
5328 | /* The decl may have already been given a section attribute | |
5329 | from a previous declaration. Ensure they match. */ | |
5330 | else if (DECL_SECTION_NAME (decl) != NULL_TREE | |
5331 | && strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl)), | |
5332 | ".l1.text") != 0) | |
5333 | { | |
5334 | error ("section of %q+D conflicts with previous declaration", | |
5335 | decl); | |
5336 | *no_add_attrs = true; | |
5337 | } | |
5338 | else | |
5339 | DECL_SECTION_NAME (decl) = build_string (9, ".l1.text"); | |
5340 | ||
5341 | return NULL_TREE; | |
5342 | } | |
5343 | ||
5344 | /* Handle a "l1_data", "l1_data_A" or "l1_data_B" attribute; | |
5345 | arguments as in struct attribute_spec.handler. */ | |
5346 | ||
5347 | static tree | |
5348 | bfin_handle_l1_data_attribute (tree *node, tree name, tree ARG_UNUSED (args), | |
5349 | int ARG_UNUSED (flags), bool *no_add_attrs) | |
5350 | { | |
5351 | tree decl = *node; | |
5352 | ||
5353 | if (TREE_CODE (decl) != VAR_DECL) | |
5354 | { | |
67a779df | 5355 | error ("%qE attribute only applies to variables", |
5356 | name); | |
fc8aef7f | 5357 | *no_add_attrs = true; |
5358 | } | |
5359 | else if (current_function_decl != NULL_TREE | |
5360 | && !TREE_STATIC (decl)) | |
5361 | { | |
67a779df | 5362 | error ("%qE attribute cannot be specified for local variables", |
5363 | name); | |
fc8aef7f | 5364 | *no_add_attrs = true; |
5365 | } | |
5366 | else | |
5367 | { | |
5368 | const char *section_name; | |
5369 | ||
5370 | if (strcmp (IDENTIFIER_POINTER (name), "l1_data") == 0) | |
5371 | section_name = ".l1.data"; | |
5372 | else if (strcmp (IDENTIFIER_POINTER (name), "l1_data_A") == 0) | |
5373 | section_name = ".l1.data.A"; | |
5374 | else if (strcmp (IDENTIFIER_POINTER (name), "l1_data_B") == 0) | |
5375 | section_name = ".l1.data.B"; | |
5376 | else | |
5377 | gcc_unreachable (); | |
5378 | ||
5379 | /* The decl may have already been given a section attribute | |
5380 | from a previous declaration. Ensure they match. */ | |
5381 | if (DECL_SECTION_NAME (decl) != NULL_TREE | |
5382 | && strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl)), | |
5383 | section_name) != 0) | |
5384 | { | |
5385 | error ("section of %q+D conflicts with previous declaration", | |
5386 | decl); | |
5387 | *no_add_attrs = true; | |
5388 | } | |
5389 | else | |
5390 | DECL_SECTION_NAME (decl) | |
5391 | = build_string (strlen (section_name) + 1, section_name); | |
5392 | } | |
5393 | ||
5394 | return NULL_TREE; | |
5395 | } | |
5396 | ||
aba5356f | 5397 | /* Handle a "l2" attribute; arguments as in struct attribute_spec.handler. */ |
5398 | ||
5399 | static tree | |
5400 | bfin_handle_l2_attribute (tree *node, tree ARG_UNUSED (name), | |
5401 | tree ARG_UNUSED (args), int ARG_UNUSED (flags), | |
5402 | bool *no_add_attrs) | |
5403 | { | |
5404 | tree decl = *node; | |
5405 | ||
5406 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
5407 | { | |
5408 | if (DECL_SECTION_NAME (decl) != NULL_TREE | |
5409 | && strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl)), | |
5410 | ".l2.text") != 0) | |
5411 | { | |
5412 | error ("section of %q+D conflicts with previous declaration", | |
5413 | decl); | |
5414 | *no_add_attrs = true; | |
5415 | } | |
5416 | else | |
5417 | DECL_SECTION_NAME (decl) = build_string (9, ".l2.text"); | |
5418 | } | |
5419 | else if (TREE_CODE (decl) == VAR_DECL) | |
5420 | { | |
5421 | if (DECL_SECTION_NAME (decl) != NULL_TREE | |
5422 | && strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl)), | |
5423 | ".l2.data") != 0) | |
5424 | { | |
5425 | error ("section of %q+D conflicts with previous declaration", | |
5426 | decl); | |
5427 | *no_add_attrs = true; | |
5428 | } | |
5429 | else | |
5430 | DECL_SECTION_NAME (decl) = build_string (9, ".l2.data"); | |
5431 | } | |
5432 | ||
5433 | return NULL_TREE; | |
5434 | } | |
5435 | ||
9e6a0967 | 5436 | /* Table of valid machine attributes. */ |
cd819d2f | 5437 | static const struct attribute_spec bfin_attribute_table[] = |
9e6a0967 | 5438 | { |
ac86af5d | 5439 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler, |
5440 | affects_type_identity } */ | |
5441 | { "interrupt_handler", 0, 0, false, true, true, handle_int_attribute, | |
5442 | false }, | |
5443 | { "exception_handler", 0, 0, false, true, true, handle_int_attribute, | |
5444 | false }, | |
5445 | { "nmi_handler", 0, 0, false, true, true, handle_int_attribute, false }, | |
5446 | { "nesting", 0, 0, false, true, true, NULL, false }, | |
5447 | { "kspisusp", 0, 0, false, true, true, NULL, false }, | |
5448 | { "saveall", 0, 0, false, true, true, NULL, false }, | |
5449 | { "longcall", 0, 0, false, true, true, bfin_handle_longcall_attribute, | |
5450 | false }, | |
5451 | { "shortcall", 0, 0, false, true, true, bfin_handle_longcall_attribute, | |
5452 | false }, | |
5453 | { "l1_text", 0, 0, true, false, false, bfin_handle_l1_text_attribute, | |
5454 | false }, | |
5455 | { "l1_data", 0, 0, true, false, false, bfin_handle_l1_data_attribute, | |
5456 | false }, | |
5457 | { "l1_data_A", 0, 0, true, false, false, bfin_handle_l1_data_attribute, | |
5458 | false }, | |
5459 | { "l1_data_B", 0, 0, true, false, false, bfin_handle_l1_data_attribute, | |
5460 | false }, | |
5461 | { "l2", 0, 0, true, false, false, bfin_handle_l2_attribute, false }, | |
5462 | { NULL, 0, 0, false, false, false, NULL, false } | |
9e6a0967 | 5463 | }; |
5464 | \f | |
55be0e32 | 5465 | /* Implementation of TARGET_ASM_INTEGER. When using FD-PIC, we need to |
5466 | tell the assembler to generate pointers to function descriptors in | |
5467 | some cases. */ | |
5468 | ||
5469 | static bool | |
5470 | bfin_assemble_integer (rtx value, unsigned int size, int aligned_p) | |
5471 | { | |
5472 | if (TARGET_FDPIC && size == UNITS_PER_WORD) | |
5473 | { | |
5474 | if (GET_CODE (value) == SYMBOL_REF | |
5475 | && SYMBOL_REF_FUNCTION_P (value)) | |
5476 | { | |
5477 | fputs ("\t.picptr\tfuncdesc(", asm_out_file); | |
5478 | output_addr_const (asm_out_file, value); | |
5479 | fputs (")\n", asm_out_file); | |
5480 | return true; | |
5481 | } | |
5482 | if (!aligned_p) | |
5483 | { | |
5484 | /* We've set the unaligned SI op to NULL, so we always have to | |
5485 | handle the unaligned case here. */ | |
5486 | assemble_integer_with_op ("\t.4byte\t", value); | |
5487 | return true; | |
5488 | } | |
5489 | } | |
5490 | return default_assemble_integer (value, size, aligned_p); | |
5491 | } | |
5492 | \f | |
9e6a0967 | 5493 | /* Output the assembler code for a thunk function. THUNK_DECL is the |
5494 | declaration for the thunk function itself, FUNCTION is the decl for | |
5495 | the target function. DELTA is an immediate constant offset to be | |
5496 | added to THIS. If VCALL_OFFSET is nonzero, the word at | |
5497 | *(*this + vcall_offset) should be added to THIS. */ | |
5498 | ||
5499 | static void | |
5500 | bfin_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED, | |
5501 | tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta, | |
5502 | HOST_WIDE_INT vcall_offset, tree function) | |
5503 | { | |
5504 | rtx xops[3]; | |
5505 | /* The this parameter is passed as the first argument. */ | |
8deb3959 | 5506 | rtx this_rtx = gen_rtx_REG (Pmode, REG_R0); |
9e6a0967 | 5507 | |
5508 | /* Adjust the this parameter by a fixed constant. */ | |
5509 | if (delta) | |
5510 | { | |
8deb3959 | 5511 | xops[1] = this_rtx; |
9e6a0967 | 5512 | if (delta >= -64 && delta <= 63) |
5513 | { | |
5514 | xops[0] = GEN_INT (delta); | |
5515 | output_asm_insn ("%1 += %0;", xops); | |
5516 | } | |
5517 | else if (delta >= -128 && delta < -64) | |
5518 | { | |
5519 | xops[0] = GEN_INT (delta + 64); | |
5520 | output_asm_insn ("%1 += -64; %1 += %0;", xops); | |
5521 | } | |
5522 | else if (delta > 63 && delta <= 126) | |
5523 | { | |
5524 | xops[0] = GEN_INT (delta - 63); | |
5525 | output_asm_insn ("%1 += 63; %1 += %0;", xops); | |
5526 | } | |
5527 | else | |
5528 | { | |
5529 | xops[0] = GEN_INT (delta); | |
5530 | output_asm_insn ("r3.l = %h0; r3.h = %d0; %1 = %1 + r3;", xops); | |
5531 | } | |
5532 | } | |
5533 | ||
5534 | /* Adjust the this parameter by a value stored in the vtable. */ | |
5535 | if (vcall_offset) | |
5536 | { | |
5537 | rtx p2tmp = gen_rtx_REG (Pmode, REG_P2); | |
7943de3b | 5538 | rtx tmp = gen_rtx_REG (Pmode, REG_R3); |
9e6a0967 | 5539 | |
5540 | xops[1] = tmp; | |
5541 | xops[2] = p2tmp; | |
5542 | output_asm_insn ("%2 = r0; %2 = [%2];", xops); | |
5543 | ||
5544 | /* Adjust the this parameter. */ | |
5545 | xops[0] = gen_rtx_MEM (Pmode, plus_constant (p2tmp, vcall_offset)); | |
5546 | if (!memory_operand (xops[0], Pmode)) | |
5547 | { | |
5548 | rtx tmp2 = gen_rtx_REG (Pmode, REG_P1); | |
5549 | xops[0] = GEN_INT (vcall_offset); | |
5550 | xops[1] = tmp2; | |
5551 | output_asm_insn ("%h1 = %h0; %d1 = %d0; %2 = %2 + %1", xops); | |
5552 | xops[0] = gen_rtx_MEM (Pmode, p2tmp); | |
5553 | } | |
8deb3959 | 5554 | xops[2] = this_rtx; |
9e6a0967 | 5555 | output_asm_insn ("%1 = %0; %2 = %2 + %1;", xops); |
5556 | } | |
5557 | ||
5558 | xops[0] = XEXP (DECL_RTL (function), 0); | |
5559 | if (1 || !flag_pic || (*targetm.binds_local_p) (function)) | |
5560 | output_asm_insn ("jump.l\t%P0", xops); | |
5561 | } | |
5562 | \f | |
6e6ce962 | 5563 | /* Codes for all the Blackfin builtins. */ |
5564 | enum bfin_builtins | |
5565 | { | |
5566 | BFIN_BUILTIN_CSYNC, | |
5567 | BFIN_BUILTIN_SSYNC, | |
44395948 | 5568 | BFIN_BUILTIN_ONES, |
f9edc33d | 5569 | BFIN_BUILTIN_COMPOSE_2X16, |
5570 | BFIN_BUILTIN_EXTRACTLO, | |
5571 | BFIN_BUILTIN_EXTRACTHI, | |
5572 | ||
5573 | BFIN_BUILTIN_SSADD_2X16, | |
5574 | BFIN_BUILTIN_SSSUB_2X16, | |
5575 | BFIN_BUILTIN_SSADDSUB_2X16, | |
5576 | BFIN_BUILTIN_SSSUBADD_2X16, | |
5577 | BFIN_BUILTIN_MULT_2X16, | |
5578 | BFIN_BUILTIN_MULTR_2X16, | |
5579 | BFIN_BUILTIN_NEG_2X16, | |
5580 | BFIN_BUILTIN_ABS_2X16, | |
5581 | BFIN_BUILTIN_MIN_2X16, | |
5582 | BFIN_BUILTIN_MAX_2X16, | |
5583 | ||
5584 | BFIN_BUILTIN_SSADD_1X16, | |
5585 | BFIN_BUILTIN_SSSUB_1X16, | |
5586 | BFIN_BUILTIN_MULT_1X16, | |
5587 | BFIN_BUILTIN_MULTR_1X16, | |
5588 | BFIN_BUILTIN_NORM_1X16, | |
5589 | BFIN_BUILTIN_NEG_1X16, | |
5590 | BFIN_BUILTIN_ABS_1X16, | |
5591 | BFIN_BUILTIN_MIN_1X16, | |
5592 | BFIN_BUILTIN_MAX_1X16, | |
5593 | ||
a4317a50 | 5594 | BFIN_BUILTIN_SUM_2X16, |
f9edc33d | 5595 | BFIN_BUILTIN_DIFFHL_2X16, |
5596 | BFIN_BUILTIN_DIFFLH_2X16, | |
5597 | ||
5598 | BFIN_BUILTIN_SSADD_1X32, | |
5599 | BFIN_BUILTIN_SSSUB_1X32, | |
5600 | BFIN_BUILTIN_NORM_1X32, | |
a4317a50 | 5601 | BFIN_BUILTIN_ROUND_1X32, |
f9edc33d | 5602 | BFIN_BUILTIN_NEG_1X32, |
a4317a50 | 5603 | BFIN_BUILTIN_ABS_1X32, |
f9edc33d | 5604 | BFIN_BUILTIN_MIN_1X32, |
5605 | BFIN_BUILTIN_MAX_1X32, | |
5606 | BFIN_BUILTIN_MULT_1X32, | |
a4317a50 | 5607 | BFIN_BUILTIN_MULT_1X32X32, |
5608 | BFIN_BUILTIN_MULT_1X32X32NS, | |
f9edc33d | 5609 | |
5610 | BFIN_BUILTIN_MULHISILL, | |
5611 | BFIN_BUILTIN_MULHISILH, | |
5612 | BFIN_BUILTIN_MULHISIHL, | |
5613 | BFIN_BUILTIN_MULHISIHH, | |
5614 | ||
5615 | BFIN_BUILTIN_LSHIFT_1X16, | |
5616 | BFIN_BUILTIN_LSHIFT_2X16, | |
5617 | BFIN_BUILTIN_SSASHIFT_1X16, | |
5618 | BFIN_BUILTIN_SSASHIFT_2X16, | |
a4317a50 | 5619 | BFIN_BUILTIN_SSASHIFT_1X32, |
f9edc33d | 5620 | |
5621 | BFIN_BUILTIN_CPLX_MUL_16, | |
5622 | BFIN_BUILTIN_CPLX_MAC_16, | |
5623 | BFIN_BUILTIN_CPLX_MSU_16, | |
5624 | ||
44395948 | 5625 | BFIN_BUILTIN_CPLX_MUL_16_S40, |
5626 | BFIN_BUILTIN_CPLX_MAC_16_S40, | |
5627 | BFIN_BUILTIN_CPLX_MSU_16_S40, | |
5628 | ||
5629 | BFIN_BUILTIN_CPLX_SQU, | |
5630 | ||
16f1c0ab | 5631 | BFIN_BUILTIN_LOADBYTES, |
5632 | ||
6e6ce962 | 5633 | BFIN_BUILTIN_MAX |
5634 | }; | |
5635 | ||
684389d2 | 5636 | #define def_builtin(NAME, TYPE, CODE) \ |
5637 | do { \ | |
54be5d7e | 5638 | add_builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \ |
5639 | NULL, NULL_TREE); \ | |
e43914a7 | 5640 | } while (0) |
5641 | ||
5642 | /* Set up all builtin functions for this target. */ | |
5643 | static void | |
5644 | bfin_init_builtins (void) | |
5645 | { | |
f9edc33d | 5646 | tree V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode); |
e43914a7 | 5647 | tree void_ftype_void |
9989d11e | 5648 | = build_function_type_list (void_type_node, NULL_TREE); |
f9edc33d | 5649 | tree short_ftype_short |
5650 | = build_function_type_list (short_integer_type_node, short_integer_type_node, | |
5651 | NULL_TREE); | |
5652 | tree short_ftype_int_int | |
5653 | = build_function_type_list (short_integer_type_node, integer_type_node, | |
5654 | integer_type_node, NULL_TREE); | |
5655 | tree int_ftype_int_int | |
5656 | = build_function_type_list (integer_type_node, integer_type_node, | |
5657 | integer_type_node, NULL_TREE); | |
5658 | tree int_ftype_int | |
5659 | = build_function_type_list (integer_type_node, integer_type_node, | |
5660 | NULL_TREE); | |
5661 | tree short_ftype_int | |
5662 | = build_function_type_list (short_integer_type_node, integer_type_node, | |
5663 | NULL_TREE); | |
5664 | tree int_ftype_v2hi_v2hi | |
5665 | = build_function_type_list (integer_type_node, V2HI_type_node, | |
5666 | V2HI_type_node, NULL_TREE); | |
5667 | tree v2hi_ftype_v2hi_v2hi | |
5668 | = build_function_type_list (V2HI_type_node, V2HI_type_node, | |
5669 | V2HI_type_node, NULL_TREE); | |
5670 | tree v2hi_ftype_v2hi_v2hi_v2hi | |
5671 | = build_function_type_list (V2HI_type_node, V2HI_type_node, | |
5672 | V2HI_type_node, V2HI_type_node, NULL_TREE); | |
5673 | tree v2hi_ftype_int_int | |
5674 | = build_function_type_list (V2HI_type_node, integer_type_node, | |
5675 | integer_type_node, NULL_TREE); | |
5676 | tree v2hi_ftype_v2hi_int | |
5677 | = build_function_type_list (V2HI_type_node, V2HI_type_node, | |
5678 | integer_type_node, NULL_TREE); | |
5679 | tree int_ftype_short_short | |
5680 | = build_function_type_list (integer_type_node, short_integer_type_node, | |
5681 | short_integer_type_node, NULL_TREE); | |
5682 | tree v2hi_ftype_v2hi | |
5683 | = build_function_type_list (V2HI_type_node, V2HI_type_node, NULL_TREE); | |
5684 | tree short_ftype_v2hi | |
5685 | = build_function_type_list (short_integer_type_node, V2HI_type_node, | |
5686 | NULL_TREE); | |
16f1c0ab | 5687 | tree int_ftype_pint |
5688 | = build_function_type_list (integer_type_node, | |
5689 | build_pointer_type (integer_type_node), | |
5690 | NULL_TREE); | |
5691 | ||
e43914a7 | 5692 | /* Add the remaining MMX insns with somewhat more complicated types. */ |
5693 | def_builtin ("__builtin_bfin_csync", void_ftype_void, BFIN_BUILTIN_CSYNC); | |
5694 | def_builtin ("__builtin_bfin_ssync", void_ftype_void, BFIN_BUILTIN_SSYNC); | |
f9edc33d | 5695 | |
44395948 | 5696 | def_builtin ("__builtin_bfin_ones", short_ftype_int, BFIN_BUILTIN_ONES); |
5697 | ||
f9edc33d | 5698 | def_builtin ("__builtin_bfin_compose_2x16", v2hi_ftype_int_int, |
5699 | BFIN_BUILTIN_COMPOSE_2X16); | |
5700 | def_builtin ("__builtin_bfin_extract_hi", short_ftype_v2hi, | |
5701 | BFIN_BUILTIN_EXTRACTHI); | |
5702 | def_builtin ("__builtin_bfin_extract_lo", short_ftype_v2hi, | |
5703 | BFIN_BUILTIN_EXTRACTLO); | |
5704 | ||
5705 | def_builtin ("__builtin_bfin_min_fr2x16", v2hi_ftype_v2hi_v2hi, | |
5706 | BFIN_BUILTIN_MIN_2X16); | |
5707 | def_builtin ("__builtin_bfin_max_fr2x16", v2hi_ftype_v2hi_v2hi, | |
5708 | BFIN_BUILTIN_MAX_2X16); | |
5709 | ||
5710 | def_builtin ("__builtin_bfin_add_fr2x16", v2hi_ftype_v2hi_v2hi, | |
5711 | BFIN_BUILTIN_SSADD_2X16); | |
5712 | def_builtin ("__builtin_bfin_sub_fr2x16", v2hi_ftype_v2hi_v2hi, | |
5713 | BFIN_BUILTIN_SSSUB_2X16); | |
5714 | def_builtin ("__builtin_bfin_dspaddsubsat", v2hi_ftype_v2hi_v2hi, | |
5715 | BFIN_BUILTIN_SSADDSUB_2X16); | |
5716 | def_builtin ("__builtin_bfin_dspsubaddsat", v2hi_ftype_v2hi_v2hi, | |
5717 | BFIN_BUILTIN_SSSUBADD_2X16); | |
5718 | def_builtin ("__builtin_bfin_mult_fr2x16", v2hi_ftype_v2hi_v2hi, | |
5719 | BFIN_BUILTIN_MULT_2X16); | |
5720 | def_builtin ("__builtin_bfin_multr_fr2x16", v2hi_ftype_v2hi_v2hi, | |
5721 | BFIN_BUILTIN_MULTR_2X16); | |
5722 | def_builtin ("__builtin_bfin_negate_fr2x16", v2hi_ftype_v2hi, | |
5723 | BFIN_BUILTIN_NEG_2X16); | |
5724 | def_builtin ("__builtin_bfin_abs_fr2x16", v2hi_ftype_v2hi, | |
5725 | BFIN_BUILTIN_ABS_2X16); | |
5726 | ||
44395948 | 5727 | def_builtin ("__builtin_bfin_min_fr1x16", short_ftype_int_int, |
5728 | BFIN_BUILTIN_MIN_1X16); | |
5729 | def_builtin ("__builtin_bfin_max_fr1x16", short_ftype_int_int, | |
5730 | BFIN_BUILTIN_MAX_1X16); | |
5731 | ||
f9edc33d | 5732 | def_builtin ("__builtin_bfin_add_fr1x16", short_ftype_int_int, |
5733 | BFIN_BUILTIN_SSADD_1X16); | |
5734 | def_builtin ("__builtin_bfin_sub_fr1x16", short_ftype_int_int, | |
5735 | BFIN_BUILTIN_SSSUB_1X16); | |
5736 | def_builtin ("__builtin_bfin_mult_fr1x16", short_ftype_int_int, | |
5737 | BFIN_BUILTIN_MULT_1X16); | |
5738 | def_builtin ("__builtin_bfin_multr_fr1x16", short_ftype_int_int, | |
5739 | BFIN_BUILTIN_MULTR_1X16); | |
5740 | def_builtin ("__builtin_bfin_negate_fr1x16", short_ftype_short, | |
5741 | BFIN_BUILTIN_NEG_1X16); | |
5742 | def_builtin ("__builtin_bfin_abs_fr1x16", short_ftype_short, | |
5743 | BFIN_BUILTIN_ABS_1X16); | |
5744 | def_builtin ("__builtin_bfin_norm_fr1x16", short_ftype_int, | |
5745 | BFIN_BUILTIN_NORM_1X16); | |
5746 | ||
a4317a50 | 5747 | def_builtin ("__builtin_bfin_sum_fr2x16", short_ftype_v2hi, |
5748 | BFIN_BUILTIN_SUM_2X16); | |
f9edc33d | 5749 | def_builtin ("__builtin_bfin_diff_hl_fr2x16", short_ftype_v2hi, |
5750 | BFIN_BUILTIN_DIFFHL_2X16); | |
5751 | def_builtin ("__builtin_bfin_diff_lh_fr2x16", short_ftype_v2hi, | |
5752 | BFIN_BUILTIN_DIFFLH_2X16); | |
5753 | ||
5754 | def_builtin ("__builtin_bfin_mulhisill", int_ftype_v2hi_v2hi, | |
5755 | BFIN_BUILTIN_MULHISILL); | |
5756 | def_builtin ("__builtin_bfin_mulhisihl", int_ftype_v2hi_v2hi, | |
5757 | BFIN_BUILTIN_MULHISIHL); | |
5758 | def_builtin ("__builtin_bfin_mulhisilh", int_ftype_v2hi_v2hi, | |
5759 | BFIN_BUILTIN_MULHISILH); | |
5760 | def_builtin ("__builtin_bfin_mulhisihh", int_ftype_v2hi_v2hi, | |
5761 | BFIN_BUILTIN_MULHISIHH); | |
5762 | ||
44395948 | 5763 | def_builtin ("__builtin_bfin_min_fr1x32", int_ftype_int_int, |
5764 | BFIN_BUILTIN_MIN_1X32); | |
5765 | def_builtin ("__builtin_bfin_max_fr1x32", int_ftype_int_int, | |
5766 | BFIN_BUILTIN_MAX_1X32); | |
5767 | ||
f9edc33d | 5768 | def_builtin ("__builtin_bfin_add_fr1x32", int_ftype_int_int, |
5769 | BFIN_BUILTIN_SSADD_1X32); | |
5770 | def_builtin ("__builtin_bfin_sub_fr1x32", int_ftype_int_int, | |
5771 | BFIN_BUILTIN_SSSUB_1X32); | |
5772 | def_builtin ("__builtin_bfin_negate_fr1x32", int_ftype_int, | |
5773 | BFIN_BUILTIN_NEG_1X32); | |
a4317a50 | 5774 | def_builtin ("__builtin_bfin_abs_fr1x32", int_ftype_int, |
5775 | BFIN_BUILTIN_ABS_1X32); | |
f9edc33d | 5776 | def_builtin ("__builtin_bfin_norm_fr1x32", short_ftype_int, |
5777 | BFIN_BUILTIN_NORM_1X32); | |
a4317a50 | 5778 | def_builtin ("__builtin_bfin_round_fr1x32", short_ftype_int, |
5779 | BFIN_BUILTIN_ROUND_1X32); | |
f9edc33d | 5780 | def_builtin ("__builtin_bfin_mult_fr1x32", int_ftype_short_short, |
5781 | BFIN_BUILTIN_MULT_1X32); | |
a4317a50 | 5782 | def_builtin ("__builtin_bfin_mult_fr1x32x32", int_ftype_int_int, |
5783 | BFIN_BUILTIN_MULT_1X32X32); | |
5784 | def_builtin ("__builtin_bfin_mult_fr1x32x32NS", int_ftype_int_int, | |
5785 | BFIN_BUILTIN_MULT_1X32X32NS); | |
f9edc33d | 5786 | |
5787 | /* Shifts. */ | |
5788 | def_builtin ("__builtin_bfin_shl_fr1x16", short_ftype_int_int, | |
5789 | BFIN_BUILTIN_SSASHIFT_1X16); | |
5790 | def_builtin ("__builtin_bfin_shl_fr2x16", v2hi_ftype_v2hi_int, | |
5791 | BFIN_BUILTIN_SSASHIFT_2X16); | |
5792 | def_builtin ("__builtin_bfin_lshl_fr1x16", short_ftype_int_int, | |
5793 | BFIN_BUILTIN_LSHIFT_1X16); | |
5794 | def_builtin ("__builtin_bfin_lshl_fr2x16", v2hi_ftype_v2hi_int, | |
5795 | BFIN_BUILTIN_LSHIFT_2X16); | |
a4317a50 | 5796 | def_builtin ("__builtin_bfin_shl_fr1x32", int_ftype_int_int, |
5797 | BFIN_BUILTIN_SSASHIFT_1X32); | |
f9edc33d | 5798 | |
5799 | /* Complex numbers. */ | |
44395948 | 5800 | def_builtin ("__builtin_bfin_cmplx_add", v2hi_ftype_v2hi_v2hi, |
5801 | BFIN_BUILTIN_SSADD_2X16); | |
5802 | def_builtin ("__builtin_bfin_cmplx_sub", v2hi_ftype_v2hi_v2hi, | |
5803 | BFIN_BUILTIN_SSSUB_2X16); | |
f9edc33d | 5804 | def_builtin ("__builtin_bfin_cmplx_mul", v2hi_ftype_v2hi_v2hi, |
5805 | BFIN_BUILTIN_CPLX_MUL_16); | |
5806 | def_builtin ("__builtin_bfin_cmplx_mac", v2hi_ftype_v2hi_v2hi_v2hi, | |
5807 | BFIN_BUILTIN_CPLX_MAC_16); | |
5808 | def_builtin ("__builtin_bfin_cmplx_msu", v2hi_ftype_v2hi_v2hi_v2hi, | |
5809 | BFIN_BUILTIN_CPLX_MSU_16); | |
44395948 | 5810 | def_builtin ("__builtin_bfin_cmplx_mul_s40", v2hi_ftype_v2hi_v2hi, |
5811 | BFIN_BUILTIN_CPLX_MUL_16_S40); | |
5812 | def_builtin ("__builtin_bfin_cmplx_mac_s40", v2hi_ftype_v2hi_v2hi_v2hi, | |
5813 | BFIN_BUILTIN_CPLX_MAC_16_S40); | |
5814 | def_builtin ("__builtin_bfin_cmplx_msu_s40", v2hi_ftype_v2hi_v2hi_v2hi, | |
5815 | BFIN_BUILTIN_CPLX_MSU_16_S40); | |
5816 | def_builtin ("__builtin_bfin_csqu_fr16", v2hi_ftype_v2hi, | |
5817 | BFIN_BUILTIN_CPLX_SQU); | |
16f1c0ab | 5818 | |
5819 | /* "Unaligned" load. */ | |
5820 | def_builtin ("__builtin_bfin_loadbytes", int_ftype_pint, | |
5821 | BFIN_BUILTIN_LOADBYTES); | |
5822 | ||
f9edc33d | 5823 | } |
5824 | ||
5825 | ||
5826 | struct builtin_description | |
5827 | { | |
5828 | const enum insn_code icode; | |
5829 | const char *const name; | |
5830 | const enum bfin_builtins code; | |
5831 | int macflag; | |
5832 | }; | |
5833 | ||
5834 | static const struct builtin_description bdesc_2arg[] = | |
5835 | { | |
5836 | { CODE_FOR_composev2hi, "__builtin_bfin_compose_2x16", BFIN_BUILTIN_COMPOSE_2X16, -1 }, | |
5837 | ||
5838 | { CODE_FOR_ssashiftv2hi3, "__builtin_bfin_shl_fr2x16", BFIN_BUILTIN_SSASHIFT_2X16, -1 }, | |
5839 | { CODE_FOR_ssashifthi3, "__builtin_bfin_shl_fr1x16", BFIN_BUILTIN_SSASHIFT_1X16, -1 }, | |
5840 | { CODE_FOR_lshiftv2hi3, "__builtin_bfin_lshl_fr2x16", BFIN_BUILTIN_LSHIFT_2X16, -1 }, | |
5841 | { CODE_FOR_lshifthi3, "__builtin_bfin_lshl_fr1x16", BFIN_BUILTIN_LSHIFT_1X16, -1 }, | |
a4317a50 | 5842 | { CODE_FOR_ssashiftsi3, "__builtin_bfin_shl_fr1x32", BFIN_BUILTIN_SSASHIFT_1X32, -1 }, |
f9edc33d | 5843 | |
5844 | { CODE_FOR_sminhi3, "__builtin_bfin_min_fr1x16", BFIN_BUILTIN_MIN_1X16, -1 }, | |
5845 | { CODE_FOR_smaxhi3, "__builtin_bfin_max_fr1x16", BFIN_BUILTIN_MAX_1X16, -1 }, | |
5846 | { CODE_FOR_ssaddhi3, "__builtin_bfin_add_fr1x16", BFIN_BUILTIN_SSADD_1X16, -1 }, | |
5847 | { CODE_FOR_sssubhi3, "__builtin_bfin_sub_fr1x16", BFIN_BUILTIN_SSSUB_1X16, -1 }, | |
5848 | ||
5849 | { CODE_FOR_sminsi3, "__builtin_bfin_min_fr1x32", BFIN_BUILTIN_MIN_1X32, -1 }, | |
5850 | { CODE_FOR_smaxsi3, "__builtin_bfin_max_fr1x32", BFIN_BUILTIN_MAX_1X32, -1 }, | |
5851 | { CODE_FOR_ssaddsi3, "__builtin_bfin_add_fr1x32", BFIN_BUILTIN_SSADD_1X32, -1 }, | |
5852 | { CODE_FOR_sssubsi3, "__builtin_bfin_sub_fr1x32", BFIN_BUILTIN_SSSUB_1X32, -1 }, | |
5853 | ||
5854 | { CODE_FOR_sminv2hi3, "__builtin_bfin_min_fr2x16", BFIN_BUILTIN_MIN_2X16, -1 }, | |
5855 | { CODE_FOR_smaxv2hi3, "__builtin_bfin_max_fr2x16", BFIN_BUILTIN_MAX_2X16, -1 }, | |
5856 | { CODE_FOR_ssaddv2hi3, "__builtin_bfin_add_fr2x16", BFIN_BUILTIN_SSADD_2X16, -1 }, | |
5857 | { CODE_FOR_sssubv2hi3, "__builtin_bfin_sub_fr2x16", BFIN_BUILTIN_SSSUB_2X16, -1 }, | |
5858 | { CODE_FOR_ssaddsubv2hi3, "__builtin_bfin_dspaddsubsat", BFIN_BUILTIN_SSADDSUB_2X16, -1 }, | |
5859 | { CODE_FOR_sssubaddv2hi3, "__builtin_bfin_dspsubaddsat", BFIN_BUILTIN_SSSUBADD_2X16, -1 }, | |
5860 | ||
5861 | { CODE_FOR_flag_mulhisi, "__builtin_bfin_mult_fr1x32", BFIN_BUILTIN_MULT_1X32, MACFLAG_NONE }, | |
5862 | { CODE_FOR_flag_mulhi, "__builtin_bfin_mult_fr1x16", BFIN_BUILTIN_MULT_1X16, MACFLAG_T }, | |
5863 | { CODE_FOR_flag_mulhi, "__builtin_bfin_multr_fr1x16", BFIN_BUILTIN_MULTR_1X16, MACFLAG_NONE }, | |
5864 | { CODE_FOR_flag_mulv2hi, "__builtin_bfin_mult_fr2x16", BFIN_BUILTIN_MULT_2X16, MACFLAG_T }, | |
4fe1a599 | 5865 | { CODE_FOR_flag_mulv2hi, "__builtin_bfin_multr_fr2x16", BFIN_BUILTIN_MULTR_2X16, MACFLAG_NONE }, |
5866 | ||
5867 | { CODE_FOR_mulhisi_ll, "__builtin_bfin_mulhisill", BFIN_BUILTIN_MULHISILL, -1 }, | |
5868 | { CODE_FOR_mulhisi_lh, "__builtin_bfin_mulhisilh", BFIN_BUILTIN_MULHISILH, -1 }, | |
5869 | { CODE_FOR_mulhisi_hl, "__builtin_bfin_mulhisihl", BFIN_BUILTIN_MULHISIHL, -1 }, | |
5870 | { CODE_FOR_mulhisi_hh, "__builtin_bfin_mulhisihh", BFIN_BUILTIN_MULHISIHH, -1 } | |
5871 | ||
f9edc33d | 5872 | }; |
5873 | ||
5874 | static const struct builtin_description bdesc_1arg[] = | |
5875 | { | |
16f1c0ab | 5876 | { CODE_FOR_loadbytes, "__builtin_bfin_loadbytes", BFIN_BUILTIN_LOADBYTES, 0 }, |
5877 | ||
44395948 | 5878 | { CODE_FOR_ones, "__builtin_bfin_ones", BFIN_BUILTIN_ONES, 0 }, |
5879 | ||
f9edc33d | 5880 | { CODE_FOR_signbitshi2, "__builtin_bfin_norm_fr1x16", BFIN_BUILTIN_NORM_1X16, 0 }, |
5881 | { CODE_FOR_ssneghi2, "__builtin_bfin_negate_fr1x16", BFIN_BUILTIN_NEG_1X16, 0 }, | |
5882 | { CODE_FOR_abshi2, "__builtin_bfin_abs_fr1x16", BFIN_BUILTIN_ABS_1X16, 0 }, | |
5883 | ||
5884 | { CODE_FOR_signbitssi2, "__builtin_bfin_norm_fr1x32", BFIN_BUILTIN_NORM_1X32, 0 }, | |
a4317a50 | 5885 | { CODE_FOR_ssroundsi2, "__builtin_bfin_round_fr1x32", BFIN_BUILTIN_ROUND_1X32, 0 }, |
f9edc33d | 5886 | { CODE_FOR_ssnegsi2, "__builtin_bfin_negate_fr1x32", BFIN_BUILTIN_NEG_1X32, 0 }, |
a4317a50 | 5887 | { CODE_FOR_ssabssi2, "__builtin_bfin_abs_fr1x32", BFIN_BUILTIN_ABS_1X32, 0 }, |
f9edc33d | 5888 | |
5889 | { CODE_FOR_movv2hi_hi_low, "__builtin_bfin_extract_lo", BFIN_BUILTIN_EXTRACTLO, 0 }, | |
5890 | { CODE_FOR_movv2hi_hi_high, "__builtin_bfin_extract_hi", BFIN_BUILTIN_EXTRACTHI, 0 }, | |
5891 | { CODE_FOR_ssnegv2hi2, "__builtin_bfin_negate_fr2x16", BFIN_BUILTIN_NEG_2X16, 0 }, | |
a4317a50 | 5892 | { CODE_FOR_ssabsv2hi2, "__builtin_bfin_abs_fr2x16", BFIN_BUILTIN_ABS_2X16, 0 } |
f9edc33d | 5893 | }; |
5894 | ||
5895 | /* Errors in the source file can cause expand_expr to return const0_rtx | |
5896 | where we expect a vector. To avoid crashing, use one of the vector | |
5897 | clear instructions. */ | |
5898 | static rtx | |
5899 | safe_vector_operand (rtx x, enum machine_mode mode) | |
5900 | { | |
5901 | if (x != const0_rtx) | |
5902 | return x; | |
5903 | x = gen_reg_rtx (SImode); | |
5904 | ||
5905 | emit_insn (gen_movsi (x, CONST0_RTX (SImode))); | |
5906 | return gen_lowpart (mode, x); | |
5907 | } | |
5908 | ||
5909 | /* Subroutine of bfin_expand_builtin to take care of binop insns. MACFLAG is -1 | |
5910 | if this is a normal binary op, or one of the MACFLAG_xxx constants. */ | |
5911 | ||
5912 | static rtx | |
c2f47e15 | 5913 | bfin_expand_binop_builtin (enum insn_code icode, tree exp, rtx target, |
f9edc33d | 5914 | int macflag) |
5915 | { | |
5916 | rtx pat; | |
c2f47e15 | 5917 | tree arg0 = CALL_EXPR_ARG (exp, 0); |
5918 | tree arg1 = CALL_EXPR_ARG (exp, 1); | |
95f13934 | 5919 | rtx op0 = expand_normal (arg0); |
5920 | rtx op1 = expand_normal (arg1); | |
f9edc33d | 5921 | enum machine_mode op0mode = GET_MODE (op0); |
5922 | enum machine_mode op1mode = GET_MODE (op1); | |
5923 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
5924 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
5925 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
5926 | ||
5927 | if (VECTOR_MODE_P (mode0)) | |
5928 | op0 = safe_vector_operand (op0, mode0); | |
5929 | if (VECTOR_MODE_P (mode1)) | |
5930 | op1 = safe_vector_operand (op1, mode1); | |
5931 | ||
5932 | if (! target | |
5933 | || GET_MODE (target) != tmode | |
5934 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5935 | target = gen_reg_rtx (tmode); | |
5936 | ||
5937 | if ((op0mode == SImode || op0mode == VOIDmode) && mode0 == HImode) | |
5938 | { | |
5939 | op0mode = HImode; | |
5940 | op0 = gen_lowpart (HImode, op0); | |
5941 | } | |
5942 | if ((op1mode == SImode || op1mode == VOIDmode) && mode1 == HImode) | |
5943 | { | |
5944 | op1mode = HImode; | |
5945 | op1 = gen_lowpart (HImode, op1); | |
5946 | } | |
5947 | /* In case the insn wants input operands in modes different from | |
5948 | the result, abort. */ | |
5949 | gcc_assert ((op0mode == mode0 || op0mode == VOIDmode) | |
5950 | && (op1mode == mode1 || op1mode == VOIDmode)); | |
5951 | ||
5952 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5953 | op0 = copy_to_mode_reg (mode0, op0); | |
5954 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
5955 | op1 = copy_to_mode_reg (mode1, op1); | |
5956 | ||
5957 | if (macflag == -1) | |
5958 | pat = GEN_FCN (icode) (target, op0, op1); | |
5959 | else | |
5960 | pat = GEN_FCN (icode) (target, op0, op1, GEN_INT (macflag)); | |
5961 | if (! pat) | |
5962 | return 0; | |
5963 | ||
5964 | emit_insn (pat); | |
5965 | return target; | |
5966 | } | |
5967 | ||
5968 | /* Subroutine of bfin_expand_builtin to take care of unop insns. */ | |
5969 | ||
5970 | static rtx | |
c2f47e15 | 5971 | bfin_expand_unop_builtin (enum insn_code icode, tree exp, |
f9edc33d | 5972 | rtx target) |
5973 | { | |
5974 | rtx pat; | |
c2f47e15 | 5975 | tree arg0 = CALL_EXPR_ARG (exp, 0); |
95f13934 | 5976 | rtx op0 = expand_normal (arg0); |
f9edc33d | 5977 | enum machine_mode op0mode = GET_MODE (op0); |
5978 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
5979 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
5980 | ||
5981 | if (! target | |
5982 | || GET_MODE (target) != tmode | |
5983 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5984 | target = gen_reg_rtx (tmode); | |
5985 | ||
5986 | if (VECTOR_MODE_P (mode0)) | |
5987 | op0 = safe_vector_operand (op0, mode0); | |
5988 | ||
5989 | if (op0mode == SImode && mode0 == HImode) | |
5990 | { | |
5991 | op0mode = HImode; | |
5992 | op0 = gen_lowpart (HImode, op0); | |
5993 | } | |
5994 | gcc_assert (op0mode == mode0 || op0mode == VOIDmode); | |
5995 | ||
5996 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5997 | op0 = copy_to_mode_reg (mode0, op0); | |
5998 | ||
5999 | pat = GEN_FCN (icode) (target, op0); | |
6000 | if (! pat) | |
6001 | return 0; | |
6002 | emit_insn (pat); | |
6003 | return target; | |
e43914a7 | 6004 | } |
6005 | ||
6006 | /* Expand an expression EXP that calls a built-in function, | |
6007 | with result going to TARGET if that's convenient | |
6008 | (and in mode MODE if that's convenient). | |
6009 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
6010 | IGNORE is nonzero if the value is to be ignored. */ | |
6011 | ||
6012 | static rtx | |
6013 | bfin_expand_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, | |
6014 | rtx subtarget ATTRIBUTE_UNUSED, | |
6015 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
6016 | int ignore ATTRIBUTE_UNUSED) | |
6017 | { | |
f9edc33d | 6018 | size_t i; |
6019 | enum insn_code icode; | |
6020 | const struct builtin_description *d; | |
c2f47e15 | 6021 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
e43914a7 | 6022 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
f9edc33d | 6023 | tree arg0, arg1, arg2; |
a4317a50 | 6024 | rtx op0, op1, op2, accvec, pat, tmp1, tmp2, a0reg, a1reg; |
f9edc33d | 6025 | enum machine_mode tmode, mode0; |
e43914a7 | 6026 | |
6027 | switch (fcode) | |
6028 | { | |
6029 | case BFIN_BUILTIN_CSYNC: | |
6030 | emit_insn (gen_csync ()); | |
6031 | return 0; | |
6032 | case BFIN_BUILTIN_SSYNC: | |
6033 | emit_insn (gen_ssync ()); | |
6034 | return 0; | |
6035 | ||
f9edc33d | 6036 | case BFIN_BUILTIN_DIFFHL_2X16: |
6037 | case BFIN_BUILTIN_DIFFLH_2X16: | |
a4317a50 | 6038 | case BFIN_BUILTIN_SUM_2X16: |
c2f47e15 | 6039 | arg0 = CALL_EXPR_ARG (exp, 0); |
95f13934 | 6040 | op0 = expand_normal (arg0); |
a4317a50 | 6041 | icode = (fcode == BFIN_BUILTIN_DIFFHL_2X16 ? CODE_FOR_subhilov2hi3 |
6042 | : fcode == BFIN_BUILTIN_DIFFLH_2X16 ? CODE_FOR_sublohiv2hi3 | |
6043 | : CODE_FOR_ssaddhilov2hi3); | |
f9edc33d | 6044 | tmode = insn_data[icode].operand[0].mode; |
6045 | mode0 = insn_data[icode].operand[1].mode; | |
6046 | ||
6047 | if (! target | |
6048 | || GET_MODE (target) != tmode | |
6049 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6050 | target = gen_reg_rtx (tmode); | |
6051 | ||
6052 | if (VECTOR_MODE_P (mode0)) | |
6053 | op0 = safe_vector_operand (op0, mode0); | |
6054 | ||
6055 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6056 | op0 = copy_to_mode_reg (mode0, op0); | |
6057 | ||
6058 | pat = GEN_FCN (icode) (target, op0, op0); | |
6059 | if (! pat) | |
6060 | return 0; | |
6061 | emit_insn (pat); | |
6062 | return target; | |
6063 | ||
a4317a50 | 6064 | case BFIN_BUILTIN_MULT_1X32X32: |
6065 | case BFIN_BUILTIN_MULT_1X32X32NS: | |
6066 | arg0 = CALL_EXPR_ARG (exp, 0); | |
6067 | arg1 = CALL_EXPR_ARG (exp, 1); | |
95f13934 | 6068 | op0 = expand_normal (arg0); |
6069 | op1 = expand_normal (arg1); | |
a4317a50 | 6070 | if (! target |
6071 | || !register_operand (target, SImode)) | |
6072 | target = gen_reg_rtx (SImode); | |
3deb3527 | 6073 | if (! register_operand (op0, SImode)) |
6074 | op0 = copy_to_mode_reg (SImode, op0); | |
6075 | if (! register_operand (op1, SImode)) | |
6076 | op1 = copy_to_mode_reg (SImode, op1); | |
a4317a50 | 6077 | |
6078 | a1reg = gen_rtx_REG (PDImode, REG_A1); | |
6079 | a0reg = gen_rtx_REG (PDImode, REG_A0); | |
6080 | tmp1 = gen_lowpart (V2HImode, op0); | |
6081 | tmp2 = gen_lowpart (V2HImode, op1); | |
6082 | emit_insn (gen_flag_macinit1hi (a1reg, | |
6083 | gen_lowpart (HImode, op0), | |
6084 | gen_lowpart (HImode, op1), | |
6085 | GEN_INT (MACFLAG_FU))); | |
6086 | emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16))); | |
6087 | ||
6088 | if (fcode == BFIN_BUILTIN_MULT_1X32X32) | |
6089 | emit_insn (gen_flag_mul_macv2hi_parts_acconly (a0reg, a1reg, tmp1, tmp2, | |
6090 | const1_rtx, const1_rtx, | |
6091 | const1_rtx, const0_rtx, a1reg, | |
6092 | const0_rtx, GEN_INT (MACFLAG_NONE), | |
6093 | GEN_INT (MACFLAG_M))); | |
6094 | else | |
6095 | { | |
6096 | /* For saturating multiplication, there's exactly one special case | |
6097 | to be handled: multiplying the smallest negative value with | |
6098 | itself. Due to shift correction in fractional multiplies, this | |
6099 | can overflow. Iff this happens, OP2 will contain 1, which, when | |
6100 | added in 32 bits to the smallest negative, wraps to the largest | |
6101 | positive, which is the result we want. */ | |
6102 | op2 = gen_reg_rtx (V2HImode); | |
6103 | emit_insn (gen_packv2hi (op2, tmp1, tmp2, const0_rtx, const0_rtx)); | |
6104 | emit_insn (gen_movsibi (gen_rtx_REG (BImode, REG_CC), | |
6105 | gen_lowpart (SImode, op2))); | |
6106 | emit_insn (gen_flag_mul_macv2hi_parts_acconly_andcc0 (a0reg, a1reg, tmp1, tmp2, | |
6107 | const1_rtx, const1_rtx, | |
6108 | const1_rtx, const0_rtx, a1reg, | |
6109 | const0_rtx, GEN_INT (MACFLAG_NONE), | |
6110 | GEN_INT (MACFLAG_M))); | |
6111 | op2 = gen_reg_rtx (SImode); | |
6112 | emit_insn (gen_movbisi (op2, gen_rtx_REG (BImode, REG_CC))); | |
6113 | } | |
6114 | emit_insn (gen_flag_machi_parts_acconly (a1reg, tmp2, tmp1, | |
6115 | const1_rtx, const0_rtx, | |
6116 | a1reg, const0_rtx, GEN_INT (MACFLAG_M))); | |
6117 | emit_insn (gen_ashrpdi3 (a1reg, a1reg, GEN_INT (15))); | |
6118 | emit_insn (gen_sum_of_accumulators (target, a0reg, a0reg, a1reg)); | |
6119 | if (fcode == BFIN_BUILTIN_MULT_1X32X32NS) | |
6120 | emit_insn (gen_addsi3 (target, target, op2)); | |
6121 | return target; | |
6122 | ||
f9edc33d | 6123 | case BFIN_BUILTIN_CPLX_MUL_16: |
44395948 | 6124 | case BFIN_BUILTIN_CPLX_MUL_16_S40: |
c2f47e15 | 6125 | arg0 = CALL_EXPR_ARG (exp, 0); |
6126 | arg1 = CALL_EXPR_ARG (exp, 1); | |
95f13934 | 6127 | op0 = expand_normal (arg0); |
6128 | op1 = expand_normal (arg1); | |
f9edc33d | 6129 | accvec = gen_reg_rtx (V2PDImode); |
3deb3527 | 6130 | icode = CODE_FOR_flag_macv2hi_parts; |
95f13934 | 6131 | tmode = insn_data[icode].operand[0].mode; |
f9edc33d | 6132 | |
6133 | if (! target | |
6134 | || GET_MODE (target) != V2HImode | |
6135 | || ! (*insn_data[icode].operand[0].predicate) (target, V2HImode)) | |
6136 | target = gen_reg_rtx (tmode); | |
6137 | if (! register_operand (op0, GET_MODE (op0))) | |
6138 | op0 = copy_to_mode_reg (GET_MODE (op0), op0); | |
6139 | if (! register_operand (op1, GET_MODE (op1))) | |
6140 | op1 = copy_to_mode_reg (GET_MODE (op1), op1); | |
6141 | ||
44395948 | 6142 | if (fcode == BFIN_BUILTIN_CPLX_MUL_16) |
6143 | emit_insn (gen_flag_macinit1v2hi_parts (accvec, op0, op1, const0_rtx, | |
6144 | const0_rtx, const0_rtx, | |
6145 | const1_rtx, GEN_INT (MACFLAG_W32))); | |
6146 | else | |
6147 | emit_insn (gen_flag_macinit1v2hi_parts (accvec, op0, op1, const0_rtx, | |
6148 | const0_rtx, const0_rtx, | |
6149 | const1_rtx, GEN_INT (MACFLAG_NONE))); | |
f9edc33d | 6150 | emit_insn (gen_flag_macv2hi_parts (target, op0, op1, const1_rtx, |
6151 | const1_rtx, const1_rtx, | |
6152 | const0_rtx, accvec, const1_rtx, const0_rtx, | |
6153 | GEN_INT (MACFLAG_NONE), accvec)); | |
6154 | ||
6155 | return target; | |
6156 | ||
6157 | case BFIN_BUILTIN_CPLX_MAC_16: | |
6158 | case BFIN_BUILTIN_CPLX_MSU_16: | |
44395948 | 6159 | case BFIN_BUILTIN_CPLX_MAC_16_S40: |
6160 | case BFIN_BUILTIN_CPLX_MSU_16_S40: | |
c2f47e15 | 6161 | arg0 = CALL_EXPR_ARG (exp, 0); |
6162 | arg1 = CALL_EXPR_ARG (exp, 1); | |
6163 | arg2 = CALL_EXPR_ARG (exp, 2); | |
95f13934 | 6164 | op0 = expand_normal (arg0); |
6165 | op1 = expand_normal (arg1); | |
6166 | op2 = expand_normal (arg2); | |
f9edc33d | 6167 | accvec = gen_reg_rtx (V2PDImode); |
3deb3527 | 6168 | icode = CODE_FOR_flag_macv2hi_parts; |
95f13934 | 6169 | tmode = insn_data[icode].operand[0].mode; |
f9edc33d | 6170 | |
6171 | if (! target | |
6172 | || GET_MODE (target) != V2HImode | |
6173 | || ! (*insn_data[icode].operand[0].predicate) (target, V2HImode)) | |
6174 | target = gen_reg_rtx (tmode); | |
f9edc33d | 6175 | if (! register_operand (op1, GET_MODE (op1))) |
6176 | op1 = copy_to_mode_reg (GET_MODE (op1), op1); | |
121e4cf5 | 6177 | if (! register_operand (op2, GET_MODE (op2))) |
6178 | op2 = copy_to_mode_reg (GET_MODE (op2), op2); | |
f9edc33d | 6179 | |
6180 | tmp1 = gen_reg_rtx (SImode); | |
6181 | tmp2 = gen_reg_rtx (SImode); | |
121e4cf5 | 6182 | emit_insn (gen_ashlsi3 (tmp1, gen_lowpart (SImode, op0), GEN_INT (16))); |
6183 | emit_move_insn (tmp2, gen_lowpart (SImode, op0)); | |
f9edc33d | 6184 | emit_insn (gen_movstricthi_1 (gen_lowpart (HImode, tmp2), const0_rtx)); |
6185 | emit_insn (gen_load_accumulator_pair (accvec, tmp1, tmp2)); | |
44395948 | 6186 | if (fcode == BFIN_BUILTIN_CPLX_MAC_16 |
6187 | || fcode == BFIN_BUILTIN_CPLX_MSU_16) | |
6188 | emit_insn (gen_flag_macv2hi_parts_acconly (accvec, op1, op2, const0_rtx, | |
6189 | const0_rtx, const0_rtx, | |
6190 | const1_rtx, accvec, const0_rtx, | |
6191 | const0_rtx, | |
6192 | GEN_INT (MACFLAG_W32))); | |
6193 | else | |
6194 | emit_insn (gen_flag_macv2hi_parts_acconly (accvec, op1, op2, const0_rtx, | |
6195 | const0_rtx, const0_rtx, | |
6196 | const1_rtx, accvec, const0_rtx, | |
6197 | const0_rtx, | |
6198 | GEN_INT (MACFLAG_NONE))); | |
6199 | if (fcode == BFIN_BUILTIN_CPLX_MAC_16 | |
6200 | || fcode == BFIN_BUILTIN_CPLX_MAC_16_S40) | |
6201 | { | |
6202 | tmp1 = const1_rtx; | |
6203 | tmp2 = const0_rtx; | |
6204 | } | |
6205 | else | |
6206 | { | |
6207 | tmp1 = const0_rtx; | |
6208 | tmp2 = const1_rtx; | |
6209 | } | |
121e4cf5 | 6210 | emit_insn (gen_flag_macv2hi_parts (target, op1, op2, const1_rtx, |
f9edc33d | 6211 | const1_rtx, const1_rtx, |
6212 | const0_rtx, accvec, tmp1, tmp2, | |
6213 | GEN_INT (MACFLAG_NONE), accvec)); | |
6214 | ||
6215 | return target; | |
6216 | ||
44395948 | 6217 | case BFIN_BUILTIN_CPLX_SQU: |
6218 | arg0 = CALL_EXPR_ARG (exp, 0); | |
95f13934 | 6219 | op0 = expand_normal (arg0); |
44395948 | 6220 | accvec = gen_reg_rtx (V2PDImode); |
6221 | icode = CODE_FOR_flag_mulv2hi; | |
6222 | tmp1 = gen_reg_rtx (V2HImode); | |
6223 | tmp2 = gen_reg_rtx (V2HImode); | |
6224 | ||
6225 | if (! target | |
6226 | || GET_MODE (target) != V2HImode | |
6227 | || ! (*insn_data[icode].operand[0].predicate) (target, V2HImode)) | |
6228 | target = gen_reg_rtx (V2HImode); | |
6229 | if (! register_operand (op0, GET_MODE (op0))) | |
6230 | op0 = copy_to_mode_reg (GET_MODE (op0), op0); | |
6231 | ||
6232 | emit_insn (gen_flag_mulv2hi (tmp1, op0, op0, GEN_INT (MACFLAG_NONE))); | |
6233 | ||
901bfd0a | 6234 | emit_insn (gen_flag_mulhi_parts (gen_lowpart (HImode, tmp2), op0, op0, |
44395948 | 6235 | const0_rtx, const1_rtx, |
6236 | GEN_INT (MACFLAG_NONE))); | |
6237 | ||
901bfd0a | 6238 | emit_insn (gen_ssaddhi3_high_parts (target, tmp2, tmp2, tmp2, const0_rtx, |
6239 | const0_rtx)); | |
6240 | emit_insn (gen_sssubhi3_low_parts (target, target, tmp1, tmp1, | |
6241 | const0_rtx, const1_rtx)); | |
44395948 | 6242 | |
6243 | return target; | |
6244 | ||
e43914a7 | 6245 | default: |
f9edc33d | 6246 | break; |
e43914a7 | 6247 | } |
f9edc33d | 6248 | |
6249 | for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) | |
6250 | if (d->code == fcode) | |
c2f47e15 | 6251 | return bfin_expand_binop_builtin (d->icode, exp, target, |
f9edc33d | 6252 | d->macflag); |
6253 | ||
6254 | for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++) | |
6255 | if (d->code == fcode) | |
c2f47e15 | 6256 | return bfin_expand_unop_builtin (d->icode, exp, target); |
f9edc33d | 6257 | |
6258 | gcc_unreachable (); | |
e43914a7 | 6259 | } |
b2d7ede1 | 6260 | |
6261 | static void | |
6262 | bfin_conditional_register_usage (void) | |
6263 | { | |
6264 | /* initialize condition code flag register rtx */ | |
6265 | bfin_cc_rtx = gen_rtx_REG (BImode, REG_CC); | |
6266 | bfin_rets_rtx = gen_rtx_REG (Pmode, REG_RETS); | |
6267 | if (TARGET_FDPIC) | |
6268 | call_used_regs[FDPIC_REGNO] = 1; | |
6269 | if (!TARGET_FDPIC && flag_pic) | |
6270 | { | |
6271 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; | |
6272 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; | |
6273 | } | |
6274 | } | |
e43914a7 | 6275 | \f |
6276 | #undef TARGET_INIT_BUILTINS | |
6277 | #define TARGET_INIT_BUILTINS bfin_init_builtins | |
6278 | ||
6279 | #undef TARGET_EXPAND_BUILTIN | |
6280 | #define TARGET_EXPAND_BUILTIN bfin_expand_builtin | |
6281 | ||
9e6a0967 | 6282 | #undef TARGET_ASM_GLOBALIZE_LABEL |
6283 | #define TARGET_ASM_GLOBALIZE_LABEL bfin_globalize_label | |
6284 | ||
6285 | #undef TARGET_ASM_FILE_START | |
6286 | #define TARGET_ASM_FILE_START output_file_start | |
6287 | ||
6288 | #undef TARGET_ATTRIBUTE_TABLE | |
6289 | #define TARGET_ATTRIBUTE_TABLE bfin_attribute_table | |
6290 | ||
6291 | #undef TARGET_COMP_TYPE_ATTRIBUTES | |
6292 | #define TARGET_COMP_TYPE_ATTRIBUTES bfin_comp_type_attributes | |
6293 | ||
6294 | #undef TARGET_RTX_COSTS | |
6295 | #define TARGET_RTX_COSTS bfin_rtx_costs | |
6296 | ||
6297 | #undef TARGET_ADDRESS_COST | |
6298 | #define TARGET_ADDRESS_COST bfin_address_cost | |
6299 | ||
55be0e32 | 6300 | #undef TARGET_ASM_INTEGER |
6301 | #define TARGET_ASM_INTEGER bfin_assemble_integer | |
6302 | ||
9e6a0967 | 6303 | #undef TARGET_MACHINE_DEPENDENT_REORG |
6304 | #define TARGET_MACHINE_DEPENDENT_REORG bfin_reorg | |
6305 | ||
6306 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL | |
6307 | #define TARGET_FUNCTION_OK_FOR_SIBCALL bfin_function_ok_for_sibcall | |
6308 | ||
6309 | #undef TARGET_ASM_OUTPUT_MI_THUNK | |
6310 | #define TARGET_ASM_OUTPUT_MI_THUNK bfin_output_mi_thunk | |
6311 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
a9f1838b | 6312 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true |
9e6a0967 | 6313 | |
6314 | #undef TARGET_SCHED_ADJUST_COST | |
6315 | #define TARGET_SCHED_ADJUST_COST bfin_adjust_cost | |
6316 | ||
9aa0222b | 6317 | #undef TARGET_SCHED_ISSUE_RATE |
6318 | #define TARGET_SCHED_ISSUE_RATE bfin_issue_rate | |
6319 | ||
3b2411a8 | 6320 | #undef TARGET_PROMOTE_FUNCTION_MODE |
6321 | #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote | |
9e6a0967 | 6322 | |
6323 | #undef TARGET_ARG_PARTIAL_BYTES | |
6324 | #define TARGET_ARG_PARTIAL_BYTES bfin_arg_partial_bytes | |
6325 | ||
d8882c2e | 6326 | #undef TARGET_FUNCTION_ARG |
6327 | #define TARGET_FUNCTION_ARG bfin_function_arg | |
6328 | ||
6329 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
6330 | #define TARGET_FUNCTION_ARG_ADVANCE bfin_function_arg_advance | |
6331 | ||
9e6a0967 | 6332 | #undef TARGET_PASS_BY_REFERENCE |
6333 | #define TARGET_PASS_BY_REFERENCE bfin_pass_by_reference | |
6334 | ||
6335 | #undef TARGET_SETUP_INCOMING_VARARGS | |
6336 | #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs | |
6337 | ||
6338 | #undef TARGET_STRUCT_VALUE_RTX | |
6339 | #define TARGET_STRUCT_VALUE_RTX bfin_struct_value_rtx | |
6340 | ||
6341 | #undef TARGET_VECTOR_MODE_SUPPORTED_P | |
6342 | #define TARGET_VECTOR_MODE_SUPPORTED_P bfin_vector_mode_supported_p | |
6343 | ||
4c834714 | 6344 | #undef TARGET_OPTION_OVERRIDE |
6345 | #define TARGET_OPTION_OVERRIDE bfin_option_override | |
6346 | ||
88eaee2d | 6347 | #undef TARGET_SECONDARY_RELOAD |
6348 | #define TARGET_SECONDARY_RELOAD bfin_secondary_reload | |
6349 | ||
877af69b | 6350 | #undef TARGET_CLASS_LIKELY_SPILLED_P |
6351 | #define TARGET_CLASS_LIKELY_SPILLED_P bfin_class_likely_spilled_p | |
6352 | ||
6833eae4 | 6353 | #undef TARGET_DELEGITIMIZE_ADDRESS |
6354 | #define TARGET_DELEGITIMIZE_ADDRESS bfin_delegitimize_address | |
6355 | ||
ca316360 | 6356 | #undef TARGET_LEGITIMATE_CONSTANT_P |
6357 | #define TARGET_LEGITIMATE_CONSTANT_P bfin_legitimate_constant_p | |
6358 | ||
cf63c743 | 6359 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
6360 | #define TARGET_CANNOT_FORCE_CONST_MEM bfin_cannot_force_const_mem | |
6361 | ||
0a619688 | 6362 | #undef TARGET_RETURN_IN_MEMORY |
6363 | #define TARGET_RETURN_IN_MEMORY bfin_return_in_memory | |
6364 | ||
fd50b071 | 6365 | #undef TARGET_LEGITIMATE_ADDRESS_P |
6366 | #define TARGET_LEGITIMATE_ADDRESS_P bfin_legitimate_address_p | |
6367 | ||
5a1c68c3 | 6368 | #undef TARGET_FRAME_POINTER_REQUIRED |
6369 | #define TARGET_FRAME_POINTER_REQUIRED bfin_frame_pointer_required | |
6370 | ||
cd90919d | 6371 | #undef TARGET_CAN_ELIMINATE |
6372 | #define TARGET_CAN_ELIMINATE bfin_can_eliminate | |
6373 | ||
b2d7ede1 | 6374 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
6375 | #define TARGET_CONDITIONAL_REGISTER_USAGE bfin_conditional_register_usage | |
6376 | ||
eeae9f72 | 6377 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE |
6378 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE bfin_asm_trampoline_template | |
6379 | #undef TARGET_TRAMPOLINE_INIT | |
6380 | #define TARGET_TRAMPOLINE_INIT bfin_trampoline_init | |
6381 | ||
08d2cf2d | 6382 | #undef TARGET_EXTRA_LIVE_ON_ENTRY |
6383 | #define TARGET_EXTRA_LIVE_ON_ENTRY bfin_extra_live_on_entry | |
6384 | ||
8a42230a | 6385 | /* Passes after sched2 can break the helpful TImode annotations that |
6386 | haifa-sched puts on every insn. Just do scheduling in reorg. */ | |
6387 | #undef TARGET_DELAY_SCHED2 | |
6388 | #define TARGET_DELAY_SCHED2 true | |
6389 | ||
6390 | /* Variable tracking should be run after all optimizations which | |
6391 | change order of insns. It also needs a valid CFG. */ | |
6392 | #undef TARGET_DELAY_VARTRACK | |
6393 | #define TARGET_DELAY_VARTRACK true | |
6394 | ||
9e6a0967 | 6395 | struct gcc_target targetm = TARGET_INITIALIZER; |