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fe24f256 | 1 | /* The Blackfin code generation auxiliary output file. |
27bedcb4 | 2 | Copyright (C) 2005, 2006, 2007, 2008 Free Software Foundation, Inc. |
9e6a0967 | 3 | Contributed by Analog Devices. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it | |
8 | under the terms of the GNU General Public License as published | |
038d1e19 | 9 | by the Free Software Foundation; either version 3, or (at your |
9e6a0967 | 10 | option) any later version. |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
038d1e19 | 18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
9e6a0967 | 20 | |
21 | #include "config.h" | |
22 | #include "system.h" | |
23 | #include "coretypes.h" | |
24 | #include "tm.h" | |
25 | #include "rtl.h" | |
26 | #include "regs.h" | |
27 | #include "hard-reg-set.h" | |
28 | #include "real.h" | |
29 | #include "insn-config.h" | |
b00f0d99 | 30 | #include "insn-codes.h" |
9e6a0967 | 31 | #include "conditions.h" |
32 | #include "insn-flags.h" | |
33 | #include "output.h" | |
34 | #include "insn-attr.h" | |
35 | #include "tree.h" | |
36 | #include "flags.h" | |
37 | #include "except.h" | |
38 | #include "function.h" | |
39 | #include "input.h" | |
40 | #include "target.h" | |
41 | #include "target-def.h" | |
42 | #include "expr.h" | |
43 | #include "toplev.h" | |
44 | #include "recog.h" | |
f9edc33d | 45 | #include "optabs.h" |
9e6a0967 | 46 | #include "ggc.h" |
47 | #include "integrate.h" | |
70d893c7 | 48 | #include "cgraph.h" |
684389d2 | 49 | #include "langhooks.h" |
9e6a0967 | 50 | #include "bfin-protos.h" |
51 | #include "tm-preds.h" | |
87943377 | 52 | #include "tm-constrs.h" |
9e6a0967 | 53 | #include "gt-bfin.h" |
3c1905a4 | 54 | #include "basic-block.h" |
917c4036 | 55 | #include "cfglayout.h" |
48df5a7f | 56 | #include "timevar.h" |
d18119ae | 57 | #include "df.h" |
3c1905a4 | 58 | |
59 | /* A C structure for machine-specific, per-function data. | |
60 | This is added to the cfun structure. */ | |
61 | struct machine_function GTY(()) | |
62 | { | |
63 | int has_hardware_loops; | |
64 | }; | |
9e6a0967 | 65 | |
66 | /* Test and compare insns in bfin.md store the information needed to | |
67 | generate branch and scc insns here. */ | |
68 | rtx bfin_compare_op0, bfin_compare_op1; | |
69 | ||
70 | /* RTX for condition code flag register and RETS register */ | |
71 | extern GTY(()) rtx bfin_cc_rtx; | |
72 | extern GTY(()) rtx bfin_rets_rtx; | |
73 | rtx bfin_cc_rtx, bfin_rets_rtx; | |
74 | ||
75 | int max_arg_registers = 0; | |
76 | ||
77 | /* Arrays used when emitting register names. */ | |
78 | const char *short_reg_names[] = SHORT_REGISTER_NAMES; | |
79 | const char *high_reg_names[] = HIGH_REGISTER_NAMES; | |
80 | const char *dregs_pair_names[] = DREGS_PAIR_NAMES; | |
81 | const char *byte_reg_names[] = BYTE_REGISTER_NAMES; | |
82 | ||
83 | static int arg_regs[] = FUNCTION_ARG_REGISTERS; | |
84 | ||
354bd282 | 85 | /* Nonzero if -mshared-library-id was given. */ |
86 | static int bfin_lib_id_given; | |
9e6a0967 | 87 | |
48df5a7f | 88 | /* Nonzero if -fschedule-insns2 was given. We override it and |
89 | call the scheduler ourselves during reorg. */ | |
90 | static int bfin_flag_schedule_insns2; | |
91 | ||
92 | /* Determines whether we run variable tracking in machine dependent | |
93 | reorganization. */ | |
94 | static int bfin_flag_var_tracking; | |
95 | ||
c9ddd413 | 96 | /* -mcpu support */ |
cfef164f | 97 | bfin_cpu_t bfin_cpu_type = BFIN_CPU_UNKNOWN; |
c9ddd413 | 98 | |
709b2de5 | 99 | /* -msi-revision support. There are three special values: |
100 | -1 -msi-revision=none. | |
101 | 0xffff -msi-revision=any. */ | |
102 | int bfin_si_revision; | |
103 | ||
104 | /* The workarounds enabled */ | |
105 | unsigned int bfin_workarounds = 0; | |
106 | ||
107 | struct bfin_cpu | |
108 | { | |
109 | const char *name; | |
110 | bfin_cpu_t type; | |
111 | int si_revision; | |
112 | unsigned int workarounds; | |
113 | }; | |
114 | ||
115 | struct bfin_cpu bfin_cpus[] = | |
116 | { | |
1dd743ee | 117 | {"bf522", BFIN_CPU_BF522, 0x0001, |
118 | WA_SPECULATIVE_LOADS | WA_RETS}, | |
709b2de5 | 119 | {"bf522", BFIN_CPU_BF522, 0x0000, |
f5c2bcb7 | 120 | WA_SPECULATIVE_LOADS | WA_RETS}, |
709b2de5 | 121 | |
1dd743ee | 122 | {"bf523", BFIN_CPU_BF523, 0x0001, |
123 | WA_SPECULATIVE_LOADS | WA_RETS}, | |
27bedcb4 | 124 | {"bf523", BFIN_CPU_BF523, 0x0000, |
f5c2bcb7 | 125 | WA_SPECULATIVE_LOADS | WA_RETS}, |
27bedcb4 | 126 | |
1dd743ee | 127 | {"bf524", BFIN_CPU_BF524, 0x0001, |
128 | WA_SPECULATIVE_LOADS | WA_RETS}, | |
27bedcb4 | 129 | {"bf524", BFIN_CPU_BF524, 0x0000, |
f5c2bcb7 | 130 | WA_SPECULATIVE_LOADS | WA_RETS}, |
27bedcb4 | 131 | |
1dd743ee | 132 | {"bf525", BFIN_CPU_BF525, 0x0001, |
133 | WA_SPECULATIVE_LOADS | WA_RETS}, | |
709b2de5 | 134 | {"bf525", BFIN_CPU_BF525, 0x0000, |
f5c2bcb7 | 135 | WA_SPECULATIVE_LOADS | WA_RETS}, |
709b2de5 | 136 | |
1dd743ee | 137 | {"bf526", BFIN_CPU_BF526, 0x0001, |
138 | WA_SPECULATIVE_LOADS | WA_RETS}, | |
27bedcb4 | 139 | {"bf526", BFIN_CPU_BF526, 0x0000, |
f5c2bcb7 | 140 | WA_SPECULATIVE_LOADS | WA_RETS}, |
27bedcb4 | 141 | |
1dd743ee | 142 | {"bf527", BFIN_CPU_BF527, 0x0001, |
143 | WA_SPECULATIVE_LOADS | WA_RETS}, | |
709b2de5 | 144 | {"bf527", BFIN_CPU_BF527, 0x0000, |
f5c2bcb7 | 145 | WA_SPECULATIVE_LOADS | WA_RETS}, |
709b2de5 | 146 | |
147 | {"bf531", BFIN_CPU_BF531, 0x0005, | |
f5c2bcb7 | 148 | WA_SPECULATIVE_LOADS | WA_RETS}, |
709b2de5 | 149 | {"bf531", BFIN_CPU_BF531, 0x0004, |
f5c2bcb7 | 150 | WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS}, |
709b2de5 | 151 | {"bf531", BFIN_CPU_BF531, 0x0003, |
f5c2bcb7 | 152 | WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS}, |
709b2de5 | 153 | |
154 | {"bf532", BFIN_CPU_BF532, 0x0005, | |
f5c2bcb7 | 155 | WA_SPECULATIVE_LOADS | WA_RETS}, |
709b2de5 | 156 | {"bf532", BFIN_CPU_BF532, 0x0004, |
f5c2bcb7 | 157 | WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS}, |
709b2de5 | 158 | {"bf532", BFIN_CPU_BF532, 0x0003, |
f5c2bcb7 | 159 | WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS}, |
709b2de5 | 160 | |
161 | {"bf533", BFIN_CPU_BF533, 0x0005, | |
f5c2bcb7 | 162 | WA_SPECULATIVE_LOADS | WA_RETS}, |
709b2de5 | 163 | {"bf533", BFIN_CPU_BF533, 0x0004, |
f5c2bcb7 | 164 | WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS}, |
709b2de5 | 165 | {"bf533", BFIN_CPU_BF533, 0x0003, |
f5c2bcb7 | 166 | WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS}, |
709b2de5 | 167 | |
168 | {"bf534", BFIN_CPU_BF534, 0x0003, | |
f5c2bcb7 | 169 | WA_SPECULATIVE_LOADS | WA_RETS}, |
709b2de5 | 170 | {"bf534", BFIN_CPU_BF534, 0x0002, |
f5c2bcb7 | 171 | WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS}, |
709b2de5 | 172 | {"bf534", BFIN_CPU_BF534, 0x0001, |
f5c2bcb7 | 173 | WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS}, |
709b2de5 | 174 | |
175 | {"bf536", BFIN_CPU_BF536, 0x0003, | |
f5c2bcb7 | 176 | WA_SPECULATIVE_LOADS | WA_RETS}, |
709b2de5 | 177 | {"bf536", BFIN_CPU_BF536, 0x0002, |
f5c2bcb7 | 178 | WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS}, |
709b2de5 | 179 | {"bf536", BFIN_CPU_BF536, 0x0001, |
f5c2bcb7 | 180 | WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS}, |
709b2de5 | 181 | |
182 | {"bf537", BFIN_CPU_BF537, 0x0003, | |
f5c2bcb7 | 183 | WA_SPECULATIVE_LOADS | WA_RETS}, |
709b2de5 | 184 | {"bf537", BFIN_CPU_BF537, 0x0002, |
f5c2bcb7 | 185 | WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS}, |
709b2de5 | 186 | {"bf537", BFIN_CPU_BF537, 0x0001, |
f5c2bcb7 | 187 | WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS}, |
709b2de5 | 188 | |
189 | {"bf538", BFIN_CPU_BF538, 0x0004, | |
f5c2bcb7 | 190 | WA_SPECULATIVE_LOADS | WA_RETS}, |
709b2de5 | 191 | {"bf538", BFIN_CPU_BF538, 0x0003, |
f5c2bcb7 | 192 | WA_SPECULATIVE_LOADS | WA_RETS}, |
1dd743ee | 193 | {"bf538", BFIN_CPU_BF538, 0x0002, |
194 | WA_SPECULATIVE_LOADS | WA_RETS}, | |
709b2de5 | 195 | |
196 | {"bf539", BFIN_CPU_BF539, 0x0004, | |
f5c2bcb7 | 197 | WA_SPECULATIVE_LOADS | WA_RETS}, |
709b2de5 | 198 | {"bf539", BFIN_CPU_BF539, 0x0003, |
f5c2bcb7 | 199 | WA_SPECULATIVE_LOADS | WA_RETS}, |
709b2de5 | 200 | {"bf539", BFIN_CPU_BF539, 0x0002, |
f5c2bcb7 | 201 | WA_SPECULATIVE_LOADS | WA_RETS}, |
709b2de5 | 202 | |
1dd743ee | 203 | {"bf542", BFIN_CPU_BF542, 0x0001, |
204 | WA_SPECULATIVE_LOADS | WA_RETS}, | |
709b2de5 | 205 | {"bf542", BFIN_CPU_BF542, 0x0000, |
f5c2bcb7 | 206 | WA_SPECULATIVE_LOADS | WA_RETS}, |
709b2de5 | 207 | |
1dd743ee | 208 | {"bf544", BFIN_CPU_BF544, 0x0001, |
209 | WA_SPECULATIVE_LOADS | WA_RETS}, | |
709b2de5 | 210 | {"bf544", BFIN_CPU_BF544, 0x0000, |
f5c2bcb7 | 211 | WA_SPECULATIVE_LOADS | WA_RETS}, |
709b2de5 | 212 | |
1dd743ee | 213 | {"bf547", BFIN_CPU_BF547, 0x0001, |
214 | WA_SPECULATIVE_LOADS | WA_RETS}, | |
27bedcb4 | 215 | {"bf547", BFIN_CPU_BF547, 0x0000, |
f5c2bcb7 | 216 | WA_SPECULATIVE_LOADS | WA_RETS}, |
27bedcb4 | 217 | |
1dd743ee | 218 | {"bf548", BFIN_CPU_BF548, 0x0001, |
219 | WA_SPECULATIVE_LOADS | WA_RETS}, | |
709b2de5 | 220 | {"bf548", BFIN_CPU_BF548, 0x0000, |
f5c2bcb7 | 221 | WA_SPECULATIVE_LOADS | WA_RETS}, |
709b2de5 | 222 | |
1dd743ee | 223 | {"bf549", BFIN_CPU_BF549, 0x0001, |
224 | WA_SPECULATIVE_LOADS | WA_RETS}, | |
709b2de5 | 225 | {"bf549", BFIN_CPU_BF549, 0x0000, |
f5c2bcb7 | 226 | WA_SPECULATIVE_LOADS | WA_RETS}, |
709b2de5 | 227 | |
f5c2bcb7 | 228 | {"bf561", BFIN_CPU_BF561, 0x0005, WA_RETS}, |
709b2de5 | 229 | {"bf561", BFIN_CPU_BF561, 0x0003, |
f5c2bcb7 | 230 | WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS}, |
709b2de5 | 231 | {"bf561", BFIN_CPU_BF561, 0x0002, |
f5c2bcb7 | 232 | WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS}, |
709b2de5 | 233 | |
234 | {NULL, 0, 0, 0} | |
235 | }; | |
236 | ||
48df5a7f | 237 | int splitting_for_sched; |
238 | ||
9e6a0967 | 239 | static void |
240 | bfin_globalize_label (FILE *stream, const char *name) | |
241 | { | |
242 | fputs (".global ", stream); | |
243 | assemble_name (stream, name); | |
244 | fputc (';',stream); | |
245 | fputc ('\n',stream); | |
246 | } | |
247 | ||
248 | static void | |
249 | output_file_start (void) | |
250 | { | |
251 | FILE *file = asm_out_file; | |
252 | int i; | |
253 | ||
48df5a7f | 254 | /* Variable tracking should be run after all optimizations which change order |
255 | of insns. It also needs a valid CFG. This can't be done in | |
25d323e6 | 256 | override_options, because flag_var_tracking is finalized after |
48df5a7f | 257 | that. */ |
258 | bfin_flag_var_tracking = flag_var_tracking; | |
259 | flag_var_tracking = 0; | |
260 | ||
9e6a0967 | 261 | fprintf (file, ".file \"%s\";\n", input_filename); |
262 | ||
263 | for (i = 0; arg_regs[i] >= 0; i++) | |
264 | ; | |
265 | max_arg_registers = i; /* how many arg reg used */ | |
266 | } | |
267 | ||
268 | /* Called early in the compilation to conditionally modify | |
269 | fixed_regs/call_used_regs. */ | |
270 | ||
271 | void | |
272 | conditional_register_usage (void) | |
273 | { | |
274 | /* initialize condition code flag register rtx */ | |
275 | bfin_cc_rtx = gen_rtx_REG (BImode, REG_CC); | |
276 | bfin_rets_rtx = gen_rtx_REG (Pmode, REG_RETS); | |
277 | } | |
278 | ||
279 | /* Examine machine-dependent attributes of function type FUNTYPE and return its | |
280 | type. See the definition of E_FUNKIND. */ | |
281 | ||
a9f1838b | 282 | static e_funkind |
283 | funkind (const_tree funtype) | |
9e6a0967 | 284 | { |
285 | tree attrs = TYPE_ATTRIBUTES (funtype); | |
286 | if (lookup_attribute ("interrupt_handler", attrs)) | |
287 | return INTERRUPT_HANDLER; | |
288 | else if (lookup_attribute ("exception_handler", attrs)) | |
289 | return EXCPT_HANDLER; | |
290 | else if (lookup_attribute ("nmi_handler", attrs)) | |
291 | return NMI_HANDLER; | |
292 | else | |
293 | return SUBROUTINE; | |
294 | } | |
295 | \f | |
b90ce3c3 | 296 | /* Legitimize PIC addresses. If the address is already position-independent, |
297 | we return ORIG. Newly generated position-independent addresses go into a | |
298 | reg. This is REG if nonzero, otherwise we allocate register(s) as | |
299 | necessary. PICREG is the register holding the pointer to the PIC offset | |
300 | table. */ | |
301 | ||
55be0e32 | 302 | static rtx |
b90ce3c3 | 303 | legitimize_pic_address (rtx orig, rtx reg, rtx picreg) |
304 | { | |
305 | rtx addr = orig; | |
8deb3959 | 306 | rtx new_rtx = orig; |
b90ce3c3 | 307 | |
308 | if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF) | |
309 | { | |
e80283bd | 310 | int unspec; |
311 | rtx tmp; | |
312 | ||
313 | if (TARGET_ID_SHARED_LIBRARY) | |
314 | unspec = UNSPEC_MOVE_PIC; | |
315 | else if (GET_CODE (addr) == SYMBOL_REF | |
316 | && SYMBOL_REF_FUNCTION_P (addr)) | |
317 | unspec = UNSPEC_FUNCDESC_GOT17M4; | |
b90ce3c3 | 318 | else |
e80283bd | 319 | unspec = UNSPEC_MOVE_FDPIC; |
320 | ||
321 | if (reg == 0) | |
b90ce3c3 | 322 | { |
e1ba4a27 | 323 | gcc_assert (can_create_pseudo_p ()); |
e80283bd | 324 | reg = gen_reg_rtx (Pmode); |
b90ce3c3 | 325 | } |
e80283bd | 326 | |
327 | tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), unspec); | |
8deb3959 | 328 | new_rtx = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, picreg, tmp)); |
e80283bd | 329 | |
8deb3959 | 330 | emit_move_insn (reg, new_rtx); |
b90ce3c3 | 331 | if (picreg == pic_offset_table_rtx) |
18d50ae6 | 332 | crtl->uses_pic_offset_table = 1; |
b90ce3c3 | 333 | return reg; |
334 | } | |
335 | ||
336 | else if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS) | |
337 | { | |
338 | rtx base; | |
339 | ||
340 | if (GET_CODE (addr) == CONST) | |
341 | { | |
342 | addr = XEXP (addr, 0); | |
343 | gcc_assert (GET_CODE (addr) == PLUS); | |
344 | } | |
345 | ||
346 | if (XEXP (addr, 0) == picreg) | |
347 | return orig; | |
348 | ||
349 | if (reg == 0) | |
350 | { | |
e1ba4a27 | 351 | gcc_assert (can_create_pseudo_p ()); |
b90ce3c3 | 352 | reg = gen_reg_rtx (Pmode); |
353 | } | |
354 | ||
355 | base = legitimize_pic_address (XEXP (addr, 0), reg, picreg); | |
356 | addr = legitimize_pic_address (XEXP (addr, 1), | |
357 | base == reg ? NULL_RTX : reg, | |
358 | picreg); | |
359 | ||
360 | if (GET_CODE (addr) == CONST_INT) | |
361 | { | |
362 | gcc_assert (! reload_in_progress && ! reload_completed); | |
363 | addr = force_reg (Pmode, addr); | |
364 | } | |
365 | ||
366 | if (GET_CODE (addr) == PLUS && CONSTANT_P (XEXP (addr, 1))) | |
367 | { | |
368 | base = gen_rtx_PLUS (Pmode, base, XEXP (addr, 0)); | |
369 | addr = XEXP (addr, 1); | |
370 | } | |
371 | ||
372 | return gen_rtx_PLUS (Pmode, base, addr); | |
373 | } | |
374 | ||
8deb3959 | 375 | return new_rtx; |
b90ce3c3 | 376 | } |
377 | \f | |
9e6a0967 | 378 | /* Stack frame layout. */ |
379 | ||
29b085dc | 380 | /* For a given REGNO, determine whether it must be saved in the function |
381 | prologue. IS_INTHANDLER specifies whether we're generating a normal | |
382 | prologue or an interrupt/exception one. */ | |
383 | static bool | |
384 | must_save_p (bool is_inthandler, unsigned regno) | |
9e6a0967 | 385 | { |
29b085dc | 386 | if (D_REGNO_P (regno)) |
9e6a0967 | 387 | { |
29b085dc | 388 | bool is_eh_return_reg = false; |
18d50ae6 | 389 | if (crtl->calls_eh_return) |
9e6a0967 | 390 | { |
391 | unsigned j; | |
392 | for (j = 0; ; j++) | |
393 | { | |
394 | unsigned test = EH_RETURN_DATA_REGNO (j); | |
395 | if (test == INVALID_REGNUM) | |
396 | break; | |
29b085dc | 397 | if (test == regno) |
398 | is_eh_return_reg = true; | |
9e6a0967 | 399 | } |
400 | } | |
401 | ||
29b085dc | 402 | return (is_eh_return_reg |
403 | || (df_regs_ever_live_p (regno) | |
404 | && !fixed_regs[regno] | |
405 | && (is_inthandler || !call_used_regs[regno]))); | |
9e6a0967 | 406 | } |
29b085dc | 407 | else if (P_REGNO_P (regno)) |
408 | { | |
409 | return ((df_regs_ever_live_p (regno) | |
410 | && !fixed_regs[regno] | |
411 | && (is_inthandler || !call_used_regs[regno])) | |
412 | || (!TARGET_FDPIC | |
413 | && regno == PIC_OFFSET_TABLE_REGNUM | |
18d50ae6 | 414 | && (crtl->uses_pic_offset_table |
29b085dc | 415 | || (TARGET_ID_SHARED_LIBRARY && !current_function_is_leaf)))); |
416 | } | |
417 | else | |
418 | return ((is_inthandler || !call_used_regs[regno]) | |
419 | && (df_regs_ever_live_p (regno) | |
420 | || (!leaf_function_p () && call_used_regs[regno]))); | |
421 | ||
422 | } | |
423 | ||
424 | /* Compute the number of DREGS to save with a push_multiple operation. | |
425 | This could include registers that aren't modified in the function, | |
426 | since push_multiple only takes a range of registers. | |
427 | If IS_INTHANDLER, then everything that is live must be saved, even | |
428 | if normally call-clobbered. | |
429 | If CONSECUTIVE, return the number of registers we can save in one | |
430 | instruction with a push/pop multiple instruction. */ | |
431 | ||
432 | static int | |
433 | n_dregs_to_save (bool is_inthandler, bool consecutive) | |
434 | { | |
435 | int count = 0; | |
436 | unsigned i; | |
437 | ||
438 | for (i = REG_R7 + 1; i-- != REG_R0;) | |
439 | { | |
440 | if (must_save_p (is_inthandler, i)) | |
441 | count++; | |
442 | else if (consecutive) | |
443 | return count; | |
444 | } | |
445 | return count; | |
9e6a0967 | 446 | } |
447 | ||
448 | /* Like n_dregs_to_save, but compute number of PREGS to save. */ | |
449 | ||
450 | static int | |
29b085dc | 451 | n_pregs_to_save (bool is_inthandler, bool consecutive) |
9e6a0967 | 452 | { |
29b085dc | 453 | int count = 0; |
9e6a0967 | 454 | unsigned i; |
455 | ||
29b085dc | 456 | for (i = REG_P5 + 1; i-- != REG_P0;) |
457 | if (must_save_p (is_inthandler, i)) | |
458 | count++; | |
459 | else if (consecutive) | |
460 | return count; | |
461 | return count; | |
9e6a0967 | 462 | } |
463 | ||
464 | /* Determine if we are going to save the frame pointer in the prologue. */ | |
465 | ||
466 | static bool | |
467 | must_save_fp_p (void) | |
468 | { | |
3072d30e | 469 | return frame_pointer_needed || df_regs_ever_live_p (REG_FP); |
9e6a0967 | 470 | } |
471 | ||
472 | static bool | |
473 | stack_frame_needed_p (void) | |
474 | { | |
475 | /* EH return puts a new return address into the frame using an | |
476 | address relative to the frame pointer. */ | |
18d50ae6 | 477 | if (crtl->calls_eh_return) |
9e6a0967 | 478 | return true; |
479 | return frame_pointer_needed; | |
480 | } | |
481 | ||
482 | /* Emit code to save registers in the prologue. SAVEALL is nonzero if we | |
483 | must save all registers; this is used for interrupt handlers. | |
345458f3 | 484 | SPREG contains (reg:SI REG_SP). IS_INTHANDLER is true if we're doing |
485 | this for an interrupt (or exception) handler. */ | |
9e6a0967 | 486 | |
487 | static void | |
345458f3 | 488 | expand_prologue_reg_save (rtx spreg, int saveall, bool is_inthandler) |
9e6a0967 | 489 | { |
49569132 | 490 | rtx predec1 = gen_rtx_PRE_DEC (SImode, spreg); |
491 | rtx predec = gen_rtx_MEM (SImode, predec1); | |
29b085dc | 492 | int ndregs = saveall ? 8 : n_dregs_to_save (is_inthandler, false); |
493 | int npregs = saveall ? 6 : n_pregs_to_save (is_inthandler, false); | |
494 | int ndregs_consec = saveall ? 8 : n_dregs_to_save (is_inthandler, true); | |
495 | int npregs_consec = saveall ? 6 : n_pregs_to_save (is_inthandler, true); | |
496 | int dregno, pregno; | |
497 | int total_consec = ndregs_consec + npregs_consec; | |
498 | int i, d_to_save; | |
9e6a0967 | 499 | |
49569132 | 500 | if (saveall || is_inthandler) |
501 | { | |
29b085dc | 502 | rtx insn = emit_move_insn (predec, gen_rtx_REG (SImode, REG_ASTAT)); |
49569132 | 503 | RTX_FRAME_RELATED_P (insn) = 1; |
504 | } | |
505 | ||
29b085dc | 506 | if (total_consec != 0) |
507 | { | |
508 | rtx insn; | |
509 | rtx val = GEN_INT (-total_consec * 4); | |
510 | rtx pat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_consec + 2)); | |
511 | ||
512 | XVECEXP (pat, 0, 0) = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, val), | |
513 | UNSPEC_PUSH_MULTIPLE); | |
514 | XVECEXP (pat, 0, total_consec + 1) = gen_rtx_SET (VOIDmode, spreg, | |
515 | gen_rtx_PLUS (Pmode, | |
516 | spreg, | |
517 | val)); | |
518 | RTX_FRAME_RELATED_P (XVECEXP (pat, 0, total_consec + 1)) = 1; | |
519 | d_to_save = ndregs_consec; | |
520 | dregno = REG_R7 + 1 - ndregs_consec; | |
521 | pregno = REG_P5 + 1 - npregs_consec; | |
522 | for (i = 0; i < total_consec; i++) | |
523 | { | |
524 | rtx memref = gen_rtx_MEM (word_mode, | |
525 | gen_rtx_PLUS (Pmode, spreg, | |
526 | GEN_INT (- i * 4 - 4))); | |
527 | rtx subpat; | |
528 | if (d_to_save > 0) | |
529 | { | |
530 | subpat = gen_rtx_SET (VOIDmode, memref, gen_rtx_REG (word_mode, | |
531 | dregno++)); | |
532 | d_to_save--; | |
533 | } | |
534 | else | |
535 | { | |
536 | subpat = gen_rtx_SET (VOIDmode, memref, gen_rtx_REG (word_mode, | |
537 | pregno++)); | |
538 | } | |
539 | XVECEXP (pat, 0, i + 1) = subpat; | |
540 | RTX_FRAME_RELATED_P (subpat) = 1; | |
541 | } | |
542 | insn = emit_insn (pat); | |
543 | RTX_FRAME_RELATED_P (insn) = 1; | |
544 | } | |
9e6a0967 | 545 | |
29b085dc | 546 | for (dregno = REG_R0; ndregs != ndregs_consec; dregno++) |
9e6a0967 | 547 | { |
29b085dc | 548 | if (must_save_p (is_inthandler, dregno)) |
9e6a0967 | 549 | { |
29b085dc | 550 | rtx insn = emit_move_insn (predec, gen_rtx_REG (word_mode, dregno)); |
551 | RTX_FRAME_RELATED_P (insn) = 1; | |
9e6a0967 | 552 | ndregs--; |
553 | } | |
29b085dc | 554 | } |
555 | for (pregno = REG_P0; npregs != npregs_consec; pregno++) | |
556 | { | |
557 | if (must_save_p (is_inthandler, pregno)) | |
9e6a0967 | 558 | { |
29b085dc | 559 | rtx insn = emit_move_insn (predec, gen_rtx_REG (word_mode, pregno)); |
560 | RTX_FRAME_RELATED_P (insn) = 1; | |
561 | npregs--; | |
9e6a0967 | 562 | } |
9e6a0967 | 563 | } |
49569132 | 564 | for (i = REG_P7 + 1; i < REG_CC; i++) |
565 | if (saveall | |
566 | || (is_inthandler | |
567 | && (df_regs_ever_live_p (i) | |
568 | || (!leaf_function_p () && call_used_regs[i])))) | |
569 | { | |
29b085dc | 570 | rtx insn; |
49569132 | 571 | if (i == REG_A0 || i == REG_A1) |
572 | insn = emit_move_insn (gen_rtx_MEM (PDImode, predec1), | |
573 | gen_rtx_REG (PDImode, i)); | |
574 | else | |
575 | insn = emit_move_insn (predec, gen_rtx_REG (SImode, i)); | |
576 | RTX_FRAME_RELATED_P (insn) = 1; | |
577 | } | |
9e6a0967 | 578 | } |
579 | ||
580 | /* Emit code to restore registers in the epilogue. SAVEALL is nonzero if we | |
581 | must save all registers; this is used for interrupt handlers. | |
345458f3 | 582 | SPREG contains (reg:SI REG_SP). IS_INTHANDLER is true if we're doing |
583 | this for an interrupt (or exception) handler. */ | |
9e6a0967 | 584 | |
585 | static void | |
345458f3 | 586 | expand_epilogue_reg_restore (rtx spreg, bool saveall, bool is_inthandler) |
9e6a0967 | 587 | { |
49569132 | 588 | rtx postinc1 = gen_rtx_POST_INC (SImode, spreg); |
589 | rtx postinc = gen_rtx_MEM (SImode, postinc1); | |
590 | ||
29b085dc | 591 | int ndregs = saveall ? 8 : n_dregs_to_save (is_inthandler, false); |
592 | int npregs = saveall ? 6 : n_pregs_to_save (is_inthandler, false); | |
593 | int ndregs_consec = saveall ? 8 : n_dregs_to_save (is_inthandler, true); | |
594 | int npregs_consec = saveall ? 6 : n_pregs_to_save (is_inthandler, true); | |
595 | int total_consec = ndregs_consec + npregs_consec; | |
9e6a0967 | 596 | int i, regno; |
29b085dc | 597 | rtx insn; |
9e6a0967 | 598 | |
49569132 | 599 | /* A slightly crude technique to stop flow from trying to delete "dead" |
600 | insns. */ | |
601 | MEM_VOLATILE_P (postinc) = 1; | |
602 | ||
603 | for (i = REG_CC - 1; i > REG_P7; i--) | |
604 | if (saveall | |
605 | || (is_inthandler | |
606 | && (df_regs_ever_live_p (i) | |
607 | || (!leaf_function_p () && call_used_regs[i])))) | |
608 | { | |
609 | if (i == REG_A0 || i == REG_A1) | |
610 | { | |
611 | rtx mem = gen_rtx_MEM (PDImode, postinc1); | |
612 | MEM_VOLATILE_P (mem) = 1; | |
613 | emit_move_insn (gen_rtx_REG (PDImode, i), mem); | |
614 | } | |
615 | else | |
616 | emit_move_insn (gen_rtx_REG (SImode, i), postinc); | |
617 | } | |
618 | ||
29b085dc | 619 | regno = REG_P5 - npregs_consec; |
620 | for (; npregs != npregs_consec; regno--) | |
9e6a0967 | 621 | { |
29b085dc | 622 | if (must_save_p (is_inthandler, regno)) |
9e6a0967 | 623 | { |
29b085dc | 624 | emit_move_insn (gen_rtx_REG (word_mode, regno), postinc); |
625 | npregs--; | |
9e6a0967 | 626 | } |
627 | } | |
29b085dc | 628 | regno = REG_R7 - ndregs_consec; |
629 | for (; ndregs != ndregs_consec; regno--) | |
630 | { | |
631 | if (must_save_p (is_inthandler, regno)) | |
632 | { | |
633 | emit_move_insn (gen_rtx_REG (word_mode, regno), postinc); | |
634 | ndregs--; | |
635 | } | |
636 | } | |
637 | ||
638 | if (total_consec != 0) | |
639 | { | |
640 | rtx pat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_consec + 1)); | |
641 | XVECEXP (pat, 0, 0) | |
642 | = gen_rtx_SET (VOIDmode, spreg, | |
643 | gen_rtx_PLUS (Pmode, spreg, | |
644 | GEN_INT (total_consec * 4))); | |
645 | ||
646 | if (npregs_consec > 0) | |
647 | regno = REG_P5 + 1; | |
648 | else | |
649 | regno = REG_R7 + 1; | |
9e6a0967 | 650 | |
29b085dc | 651 | for (i = 0; i < total_consec; i++) |
652 | { | |
653 | rtx addr = (i > 0 | |
654 | ? gen_rtx_PLUS (Pmode, spreg, GEN_INT (i * 4)) | |
655 | : spreg); | |
656 | rtx memref = gen_rtx_MEM (word_mode, addr); | |
657 | ||
658 | regno--; | |
659 | XVECEXP (pat, 0, i + 1) | |
660 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (word_mode, regno), memref); | |
661 | ||
662 | if (npregs_consec > 0) | |
663 | { | |
664 | if (--npregs_consec == 0) | |
665 | regno = REG_R7 + 1; | |
666 | } | |
667 | } | |
49569132 | 668 | |
29b085dc | 669 | insn = emit_insn (pat); |
670 | RTX_FRAME_RELATED_P (insn) = 1; | |
671 | } | |
49569132 | 672 | if (saveall || is_inthandler) |
673 | emit_move_insn (gen_rtx_REG (SImode, REG_ASTAT), postinc); | |
9e6a0967 | 674 | } |
675 | ||
676 | /* Perform any needed actions needed for a function that is receiving a | |
677 | variable number of arguments. | |
678 | ||
679 | CUM is as above. | |
680 | ||
681 | MODE and TYPE are the mode and type of the current parameter. | |
682 | ||
683 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
684 | that must be pushed by the prolog to pretend that our caller pushed | |
685 | it. | |
686 | ||
687 | Normally, this macro will push all remaining incoming registers on the | |
688 | stack and set PRETEND_SIZE to the length of the registers pushed. | |
689 | ||
690 | Blackfin specific : | |
691 | - VDSP C compiler manual (our ABI) says that a variable args function | |
692 | should save the R0, R1 and R2 registers in the stack. | |
693 | - The caller will always leave space on the stack for the | |
694 | arguments that are passed in registers, so we dont have | |
695 | to leave any extra space. | |
696 | - now, the vastart pointer can access all arguments from the stack. */ | |
697 | ||
698 | static void | |
699 | setup_incoming_varargs (CUMULATIVE_ARGS *cum, | |
700 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
701 | tree type ATTRIBUTE_UNUSED, int *pretend_size, | |
702 | int no_rtl) | |
703 | { | |
704 | rtx mem; | |
705 | int i; | |
706 | ||
707 | if (no_rtl) | |
708 | return; | |
709 | ||
710 | /* The move for named arguments will be generated automatically by the | |
711 | compiler. We need to generate the move rtx for the unnamed arguments | |
fe24f256 | 712 | if they are in the first 3 words. We assume at least 1 named argument |
9e6a0967 | 713 | exists, so we never generate [ARGP] = R0 here. */ |
714 | ||
715 | for (i = cum->words + 1; i < max_arg_registers; i++) | |
716 | { | |
717 | mem = gen_rtx_MEM (Pmode, | |
718 | plus_constant (arg_pointer_rtx, (i * UNITS_PER_WORD))); | |
719 | emit_move_insn (mem, gen_rtx_REG (Pmode, i)); | |
720 | } | |
721 | ||
722 | *pretend_size = 0; | |
723 | } | |
724 | ||
725 | /* Value should be nonzero if functions must have frame pointers. | |
726 | Zero means the frame pointer need not be set up (and parms may | |
727 | be accessed via the stack pointer) in functions that seem suitable. */ | |
728 | ||
729 | int | |
730 | bfin_frame_pointer_required (void) | |
731 | { | |
732 | e_funkind fkind = funkind (TREE_TYPE (current_function_decl)); | |
733 | ||
734 | if (fkind != SUBROUTINE) | |
735 | return 1; | |
736 | ||
3ce7ff97 | 737 | /* We turn on -fomit-frame-pointer if -momit-leaf-frame-pointer is used, |
9e6a0967 | 738 | so we have to override it for non-leaf functions. */ |
739 | if (TARGET_OMIT_LEAF_FRAME_POINTER && ! current_function_is_leaf) | |
740 | return 1; | |
741 | ||
742 | return 0; | |
743 | } | |
744 | ||
745 | /* Return the number of registers pushed during the prologue. */ | |
746 | ||
747 | static int | |
748 | n_regs_saved_by_prologue (void) | |
749 | { | |
750 | e_funkind fkind = funkind (TREE_TYPE (current_function_decl)); | |
345458f3 | 751 | bool is_inthandler = fkind != SUBROUTINE; |
752 | tree attrs = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl)); | |
753 | bool all = (lookup_attribute ("saveall", attrs) != NULL_TREE | |
754 | || (is_inthandler && !current_function_is_leaf)); | |
29b085dc | 755 | int ndregs = all ? 8 : n_dregs_to_save (is_inthandler, false); |
756 | int npregs = all ? 6 : n_pregs_to_save (is_inthandler, false); | |
345458f3 | 757 | int n = ndregs + npregs; |
49569132 | 758 | int i; |
9e6a0967 | 759 | |
345458f3 | 760 | if (all || stack_frame_needed_p ()) |
9e6a0967 | 761 | /* We use a LINK instruction in this case. */ |
762 | n += 2; | |
763 | else | |
764 | { | |
765 | if (must_save_fp_p ()) | |
766 | n++; | |
767 | if (! current_function_is_leaf) | |
768 | n++; | |
769 | } | |
770 | ||
49569132 | 771 | if (fkind != SUBROUTINE || all) |
772 | /* Increment once for ASTAT. */ | |
773 | n++; | |
774 | ||
9e6a0967 | 775 | if (fkind != SUBROUTINE) |
776 | { | |
9e6a0967 | 777 | /* RETE/X/N. */ |
778 | if (lookup_attribute ("nesting", attrs)) | |
779 | n++; | |
9e6a0967 | 780 | } |
49569132 | 781 | |
782 | for (i = REG_P7 + 1; i < REG_CC; i++) | |
783 | if (all | |
784 | || (fkind != SUBROUTINE | |
785 | && (df_regs_ever_live_p (i) | |
786 | || (!leaf_function_p () && call_used_regs[i])))) | |
787 | n += i == REG_A0 || i == REG_A1 ? 2 : 1; | |
788 | ||
9e6a0967 | 789 | return n; |
790 | } | |
791 | ||
792 | /* Return the offset between two registers, one to be eliminated, and the other | |
793 | its replacement, at the start of a routine. */ | |
794 | ||
795 | HOST_WIDE_INT | |
796 | bfin_initial_elimination_offset (int from, int to) | |
797 | { | |
798 | HOST_WIDE_INT offset = 0; | |
799 | ||
800 | if (from == ARG_POINTER_REGNUM) | |
801 | offset = n_regs_saved_by_prologue () * 4; | |
802 | ||
803 | if (to == STACK_POINTER_REGNUM) | |
804 | { | |
abe32cce | 805 | if (crtl->outgoing_args_size >= FIXED_STACK_AREA) |
806 | offset += crtl->outgoing_args_size; | |
807 | else if (crtl->outgoing_args_size) | |
9e6a0967 | 808 | offset += FIXED_STACK_AREA; |
809 | ||
810 | offset += get_frame_size (); | |
811 | } | |
812 | ||
813 | return offset; | |
814 | } | |
815 | ||
816 | /* Emit code to load a constant CONSTANT into register REG; setting | |
b90ce3c3 | 817 | RTX_FRAME_RELATED_P on all insns we generate if RELATED is true. |
818 | Make sure that the insns we generate need not be split. */ | |
9e6a0967 | 819 | |
820 | static void | |
b90ce3c3 | 821 | frame_related_constant_load (rtx reg, HOST_WIDE_INT constant, bool related) |
9e6a0967 | 822 | { |
823 | rtx insn; | |
824 | rtx cst = GEN_INT (constant); | |
825 | ||
826 | if (constant >= -32768 && constant < 65536) | |
827 | insn = emit_move_insn (reg, cst); | |
828 | else | |
829 | { | |
830 | /* We don't call split_load_immediate here, since dwarf2out.c can get | |
831 | confused about some of the more clever sequences it can generate. */ | |
832 | insn = emit_insn (gen_movsi_high (reg, cst)); | |
b90ce3c3 | 833 | if (related) |
834 | RTX_FRAME_RELATED_P (insn) = 1; | |
9e6a0967 | 835 | insn = emit_insn (gen_movsi_low (reg, reg, cst)); |
836 | } | |
b90ce3c3 | 837 | if (related) |
838 | RTX_FRAME_RELATED_P (insn) = 1; | |
9e6a0967 | 839 | } |
840 | ||
a35b82b9 | 841 | /* Generate efficient code to add a value to a P register. |
842 | Set RTX_FRAME_RELATED_P on the generated insns if FRAME is nonzero. | |
843 | EPILOGUE_P is zero if this function is called for prologue, | |
844 | otherwise it's nonzero. And it's less than zero if this is for | |
845 | sibcall epilogue. */ | |
9e6a0967 | 846 | |
847 | static void | |
a35b82b9 | 848 | add_to_reg (rtx reg, HOST_WIDE_INT value, int frame, int epilogue_p) |
9e6a0967 | 849 | { |
850 | if (value == 0) | |
851 | return; | |
852 | ||
853 | /* Choose whether to use a sequence using a temporary register, or | |
905ea169 | 854 | a sequence with multiple adds. We can add a signed 7-bit value |
9e6a0967 | 855 | in one instruction. */ |
856 | if (value > 120 || value < -120) | |
857 | { | |
a35b82b9 | 858 | rtx tmpreg; |
859 | rtx tmpreg2; | |
9e6a0967 | 860 | rtx insn; |
861 | ||
a35b82b9 | 862 | tmpreg2 = NULL_RTX; |
863 | ||
864 | /* For prologue or normal epilogue, P1 can be safely used | |
865 | as the temporary register. For sibcall epilogue, we try to find | |
866 | a call used P register, which will be restored in epilogue. | |
867 | If we cannot find such a P register, we have to use one I register | |
868 | to help us. */ | |
869 | ||
870 | if (epilogue_p >= 0) | |
871 | tmpreg = gen_rtx_REG (SImode, REG_P1); | |
872 | else | |
873 | { | |
874 | int i; | |
875 | for (i = REG_P0; i <= REG_P5; i++) | |
d18119ae | 876 | if ((df_regs_ever_live_p (i) && ! call_used_regs[i]) |
a35b82b9 | 877 | || (!TARGET_FDPIC |
878 | && i == PIC_OFFSET_TABLE_REGNUM | |
18d50ae6 | 879 | && (crtl->uses_pic_offset_table |
a35b82b9 | 880 | || (TARGET_ID_SHARED_LIBRARY |
881 | && ! current_function_is_leaf)))) | |
882 | break; | |
883 | if (i <= REG_P5) | |
884 | tmpreg = gen_rtx_REG (SImode, i); | |
885 | else | |
886 | { | |
887 | tmpreg = gen_rtx_REG (SImode, REG_P1); | |
888 | tmpreg2 = gen_rtx_REG (SImode, REG_I0); | |
889 | emit_move_insn (tmpreg2, tmpreg); | |
890 | } | |
891 | } | |
892 | ||
9e6a0967 | 893 | if (frame) |
b90ce3c3 | 894 | frame_related_constant_load (tmpreg, value, TRUE); |
9e6a0967 | 895 | else |
6295e560 | 896 | insn = emit_move_insn (tmpreg, GEN_INT (value)); |
9e6a0967 | 897 | |
6295e560 | 898 | insn = emit_insn (gen_addsi3 (reg, reg, tmpreg)); |
9e6a0967 | 899 | if (frame) |
900 | RTX_FRAME_RELATED_P (insn) = 1; | |
a35b82b9 | 901 | |
902 | if (tmpreg2 != NULL_RTX) | |
903 | emit_move_insn (tmpreg, tmpreg2); | |
9e6a0967 | 904 | } |
905 | else | |
906 | do | |
907 | { | |
908 | int size = value; | |
909 | rtx insn; | |
910 | ||
911 | if (size > 60) | |
912 | size = 60; | |
913 | else if (size < -60) | |
914 | /* We could use -62, but that would leave the stack unaligned, so | |
915 | it's no good. */ | |
916 | size = -60; | |
917 | ||
6295e560 | 918 | insn = emit_insn (gen_addsi3 (reg, reg, GEN_INT (size))); |
9e6a0967 | 919 | if (frame) |
920 | RTX_FRAME_RELATED_P (insn) = 1; | |
921 | value -= size; | |
922 | } | |
923 | while (value != 0); | |
924 | } | |
925 | ||
926 | /* Generate a LINK insn for a frame sized FRAME_SIZE. If this constant | |
927 | is too large, generate a sequence of insns that has the same effect. | |
928 | SPREG contains (reg:SI REG_SP). */ | |
929 | ||
930 | static void | |
931 | emit_link_insn (rtx spreg, HOST_WIDE_INT frame_size) | |
932 | { | |
933 | HOST_WIDE_INT link_size = frame_size; | |
934 | rtx insn; | |
935 | int i; | |
936 | ||
937 | if (link_size > 262140) | |
938 | link_size = 262140; | |
939 | ||
940 | /* Use a LINK insn with as big a constant as possible, then subtract | |
941 | any remaining size from the SP. */ | |
942 | insn = emit_insn (gen_link (GEN_INT (-8 - link_size))); | |
943 | RTX_FRAME_RELATED_P (insn) = 1; | |
944 | ||
945 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) | |
946 | { | |
947 | rtx set = XVECEXP (PATTERN (insn), 0, i); | |
2115ae11 | 948 | gcc_assert (GET_CODE (set) == SET); |
9e6a0967 | 949 | RTX_FRAME_RELATED_P (set) = 1; |
950 | } | |
951 | ||
952 | frame_size -= link_size; | |
953 | ||
954 | if (frame_size > 0) | |
955 | { | |
956 | /* Must use a call-clobbered PREG that isn't the static chain. */ | |
957 | rtx tmpreg = gen_rtx_REG (Pmode, REG_P1); | |
958 | ||
b90ce3c3 | 959 | frame_related_constant_load (tmpreg, -frame_size, TRUE); |
9e6a0967 | 960 | insn = emit_insn (gen_addsi3 (spreg, spreg, tmpreg)); |
961 | RTX_FRAME_RELATED_P (insn) = 1; | |
962 | } | |
963 | } | |
964 | ||
965 | /* Return the number of bytes we must reserve for outgoing arguments | |
966 | in the current function's stack frame. */ | |
967 | ||
968 | static HOST_WIDE_INT | |
969 | arg_area_size (void) | |
970 | { | |
abe32cce | 971 | if (crtl->outgoing_args_size) |
9e6a0967 | 972 | { |
abe32cce | 973 | if (crtl->outgoing_args_size >= FIXED_STACK_AREA) |
974 | return crtl->outgoing_args_size; | |
9e6a0967 | 975 | else |
976 | return FIXED_STACK_AREA; | |
977 | } | |
978 | return 0; | |
979 | } | |
980 | ||
345458f3 | 981 | /* Save RETS and FP, and allocate a stack frame. ALL is true if the |
982 | function must save all its registers (true only for certain interrupt | |
983 | handlers). */ | |
9e6a0967 | 984 | |
985 | static void | |
345458f3 | 986 | do_link (rtx spreg, HOST_WIDE_INT frame_size, bool all) |
9e6a0967 | 987 | { |
988 | frame_size += arg_area_size (); | |
989 | ||
345458f3 | 990 | if (all || stack_frame_needed_p () |
9e6a0967 | 991 | || (must_save_fp_p () && ! current_function_is_leaf)) |
992 | emit_link_insn (spreg, frame_size); | |
993 | else | |
994 | { | |
995 | if (! current_function_is_leaf) | |
996 | { | |
997 | rtx pat = gen_movsi (gen_rtx_MEM (Pmode, | |
998 | gen_rtx_PRE_DEC (Pmode, spreg)), | |
999 | bfin_rets_rtx); | |
1000 | rtx insn = emit_insn (pat); | |
1001 | RTX_FRAME_RELATED_P (insn) = 1; | |
1002 | } | |
1003 | if (must_save_fp_p ()) | |
1004 | { | |
1005 | rtx pat = gen_movsi (gen_rtx_MEM (Pmode, | |
1006 | gen_rtx_PRE_DEC (Pmode, spreg)), | |
1007 | gen_rtx_REG (Pmode, REG_FP)); | |
1008 | rtx insn = emit_insn (pat); | |
1009 | RTX_FRAME_RELATED_P (insn) = 1; | |
1010 | } | |
a35b82b9 | 1011 | add_to_reg (spreg, -frame_size, 1, 0); |
9e6a0967 | 1012 | } |
1013 | } | |
1014 | ||
a35b82b9 | 1015 | /* Like do_link, but used for epilogues to deallocate the stack frame. |
1016 | EPILOGUE_P is zero if this function is called for prologue, | |
1017 | otherwise it's nonzero. And it's less than zero if this is for | |
1018 | sibcall epilogue. */ | |
9e6a0967 | 1019 | |
1020 | static void | |
a35b82b9 | 1021 | do_unlink (rtx spreg, HOST_WIDE_INT frame_size, bool all, int epilogue_p) |
9e6a0967 | 1022 | { |
1023 | frame_size += arg_area_size (); | |
1024 | ||
345458f3 | 1025 | if (all || stack_frame_needed_p ()) |
9e6a0967 | 1026 | emit_insn (gen_unlink ()); |
1027 | else | |
1028 | { | |
1029 | rtx postinc = gen_rtx_MEM (Pmode, gen_rtx_POST_INC (Pmode, spreg)); | |
1030 | ||
a35b82b9 | 1031 | add_to_reg (spreg, frame_size, 0, epilogue_p); |
9e6a0967 | 1032 | if (must_save_fp_p ()) |
1033 | { | |
1034 | rtx fpreg = gen_rtx_REG (Pmode, REG_FP); | |
1035 | emit_move_insn (fpreg, postinc); | |
18b42941 | 1036 | emit_use (fpreg); |
9e6a0967 | 1037 | } |
1038 | if (! current_function_is_leaf) | |
1039 | { | |
1040 | emit_move_insn (bfin_rets_rtx, postinc); | |
18b42941 | 1041 | emit_use (bfin_rets_rtx); |
9e6a0967 | 1042 | } |
1043 | } | |
1044 | } | |
1045 | ||
1046 | /* Generate a prologue suitable for a function of kind FKIND. This is | |
1047 | called for interrupt and exception handler prologues. | |
1048 | SPREG contains (reg:SI REG_SP). */ | |
1049 | ||
1050 | static void | |
49569132 | 1051 | expand_interrupt_handler_prologue (rtx spreg, e_funkind fkind, bool all) |
9e6a0967 | 1052 | { |
9e6a0967 | 1053 | HOST_WIDE_INT frame_size = get_frame_size (); |
1054 | rtx predec1 = gen_rtx_PRE_DEC (SImode, spreg); | |
1055 | rtx predec = gen_rtx_MEM (SImode, predec1); | |
1056 | rtx insn; | |
1057 | tree attrs = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl)); | |
9e6a0967 | 1058 | tree kspisusp = lookup_attribute ("kspisusp", attrs); |
1059 | ||
1060 | if (kspisusp) | |
1061 | { | |
1062 | insn = emit_move_insn (spreg, gen_rtx_REG (Pmode, REG_USP)); | |
1063 | RTX_FRAME_RELATED_P (insn) = 1; | |
1064 | } | |
1065 | ||
1066 | /* We need space on the stack in case we need to save the argument | |
1067 | registers. */ | |
1068 | if (fkind == EXCPT_HANDLER) | |
1069 | { | |
1070 | insn = emit_insn (gen_addsi3 (spreg, spreg, GEN_INT (-12))); | |
1071 | RTX_FRAME_RELATED_P (insn) = 1; | |
1072 | } | |
1073 | ||
345458f3 | 1074 | /* If we're calling other functions, they won't save their call-clobbered |
1075 | registers, so we must save everything here. */ | |
1076 | if (!current_function_is_leaf) | |
1077 | all = true; | |
1078 | expand_prologue_reg_save (spreg, all, true); | |
9e6a0967 | 1079 | |
9e6a0967 | 1080 | if (lookup_attribute ("nesting", attrs)) |
1081 | { | |
1082 | rtx srcreg = gen_rtx_REG (Pmode, (fkind == EXCPT_HANDLER ? REG_RETX | |
1083 | : fkind == NMI_HANDLER ? REG_RETN | |
1084 | : REG_RETI)); | |
1085 | insn = emit_move_insn (predec, srcreg); | |
1086 | RTX_FRAME_RELATED_P (insn) = 1; | |
1087 | } | |
1088 | ||
345458f3 | 1089 | do_link (spreg, frame_size, all); |
9e6a0967 | 1090 | |
1091 | if (fkind == EXCPT_HANDLER) | |
1092 | { | |
1093 | rtx r0reg = gen_rtx_REG (SImode, REG_R0); | |
1094 | rtx r1reg = gen_rtx_REG (SImode, REG_R1); | |
1095 | rtx r2reg = gen_rtx_REG (SImode, REG_R2); | |
1096 | rtx insn; | |
1097 | ||
1098 | insn = emit_move_insn (r0reg, gen_rtx_REG (SImode, REG_SEQSTAT)); | |
9e6a0967 | 1099 | insn = emit_insn (gen_ashrsi3 (r0reg, r0reg, GEN_INT (26))); |
9e6a0967 | 1100 | insn = emit_insn (gen_ashlsi3 (r0reg, r0reg, GEN_INT (26))); |
9e6a0967 | 1101 | insn = emit_move_insn (r1reg, spreg); |
9e6a0967 | 1102 | insn = emit_move_insn (r2reg, gen_rtx_REG (Pmode, REG_FP)); |
9e6a0967 | 1103 | insn = emit_insn (gen_addsi3 (r2reg, r2reg, GEN_INT (8))); |
9e6a0967 | 1104 | } |
1105 | } | |
1106 | ||
1107 | /* Generate an epilogue suitable for a function of kind FKIND. This is | |
1108 | called for interrupt and exception handler epilogues. | |
1109 | SPREG contains (reg:SI REG_SP). */ | |
1110 | ||
1111 | static void | |
49569132 | 1112 | expand_interrupt_handler_epilogue (rtx spreg, e_funkind fkind, bool all) |
9e6a0967 | 1113 | { |
49569132 | 1114 | tree attrs = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl)); |
9e6a0967 | 1115 | rtx postinc1 = gen_rtx_POST_INC (SImode, spreg); |
1116 | rtx postinc = gen_rtx_MEM (SImode, postinc1); | |
9e6a0967 | 1117 | |
1118 | /* A slightly crude technique to stop flow from trying to delete "dead" | |
1119 | insns. */ | |
1120 | MEM_VOLATILE_P (postinc) = 1; | |
1121 | ||
a35b82b9 | 1122 | do_unlink (spreg, get_frame_size (), all, 1); |
9e6a0967 | 1123 | |
1124 | if (lookup_attribute ("nesting", attrs)) | |
1125 | { | |
1126 | rtx srcreg = gen_rtx_REG (Pmode, (fkind == EXCPT_HANDLER ? REG_RETX | |
1127 | : fkind == NMI_HANDLER ? REG_RETN | |
1128 | : REG_RETI)); | |
1129 | emit_move_insn (srcreg, postinc); | |
1130 | } | |
1131 | ||
345458f3 | 1132 | /* If we're calling other functions, they won't save their call-clobbered |
1133 | registers, so we must save (and restore) everything here. */ | |
1134 | if (!current_function_is_leaf) | |
1135 | all = true; | |
1136 | ||
345458f3 | 1137 | expand_epilogue_reg_restore (spreg, all, true); |
9e6a0967 | 1138 | |
9e6a0967 | 1139 | /* Deallocate any space we left on the stack in case we needed to save the |
1140 | argument registers. */ | |
1141 | if (fkind == EXCPT_HANDLER) | |
1142 | emit_insn (gen_addsi3 (spreg, spreg, GEN_INT (12))); | |
1143 | ||
1144 | emit_jump_insn (gen_return_internal (GEN_INT (fkind))); | |
1145 | } | |
1146 | ||
b90ce3c3 | 1147 | /* Used while emitting the prologue to generate code to load the correct value |
1148 | into the PIC register, which is passed in DEST. */ | |
1149 | ||
70d893c7 | 1150 | static rtx |
b90ce3c3 | 1151 | bfin_load_pic_reg (rtx dest) |
1152 | { | |
70d893c7 | 1153 | struct cgraph_local_info *i = NULL; |
b90ce3c3 | 1154 | rtx addr, insn; |
70d893c7 | 1155 | |
6329636b | 1156 | i = cgraph_local_info (current_function_decl); |
70d893c7 | 1157 | |
1158 | /* Functions local to the translation unit don't need to reload the | |
1159 | pic reg, since the caller always passes a usable one. */ | |
1160 | if (i && i->local) | |
1161 | return pic_offset_table_rtx; | |
b90ce3c3 | 1162 | |
1163 | if (bfin_lib_id_given) | |
1164 | addr = plus_constant (pic_offset_table_rtx, -4 - bfin_library_id * 4); | |
1165 | else | |
1166 | addr = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, | |
1167 | gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
1168 | UNSPEC_LIBRARY_OFFSET)); | |
1169 | insn = emit_insn (gen_movsi (dest, gen_rtx_MEM (Pmode, addr))); | |
70d893c7 | 1170 | return dest; |
b90ce3c3 | 1171 | } |
1172 | ||
9e6a0967 | 1173 | /* Generate RTL for the prologue of the current function. */ |
1174 | ||
1175 | void | |
1176 | bfin_expand_prologue (void) | |
1177 | { | |
9e6a0967 | 1178 | HOST_WIDE_INT frame_size = get_frame_size (); |
1179 | rtx spreg = gen_rtx_REG (Pmode, REG_SP); | |
1180 | e_funkind fkind = funkind (TREE_TYPE (current_function_decl)); | |
b90ce3c3 | 1181 | rtx pic_reg_loaded = NULL_RTX; |
49569132 | 1182 | tree attrs = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl)); |
1183 | bool all = lookup_attribute ("saveall", attrs) != NULL_TREE; | |
9e6a0967 | 1184 | |
1185 | if (fkind != SUBROUTINE) | |
1186 | { | |
49569132 | 1187 | expand_interrupt_handler_prologue (spreg, fkind, all); |
9e6a0967 | 1188 | return; |
1189 | } | |
1190 | ||
18d50ae6 | 1191 | if (crtl->limit_stack |
14a75278 | 1192 | || (TARGET_STACK_CHECK_L1 |
1193 | && !DECL_NO_LIMIT_STACK (current_function_decl))) | |
b90ce3c3 | 1194 | { |
1195 | HOST_WIDE_INT offset | |
1196 | = bfin_initial_elimination_offset (ARG_POINTER_REGNUM, | |
1197 | STACK_POINTER_REGNUM); | |
18d50ae6 | 1198 | rtx lim = crtl->limit_stack ? stack_limit_rtx : NULL_RTX; |
6295e560 | 1199 | rtx p2reg = gen_rtx_REG (Pmode, REG_P2); |
b90ce3c3 | 1200 | |
6295e560 | 1201 | if (!lim) |
1202 | { | |
6295e560 | 1203 | emit_move_insn (p2reg, gen_int_mode (0xFFB00000, SImode)); |
1204 | emit_move_insn (p2reg, gen_rtx_MEM (Pmode, p2reg)); | |
1205 | lim = p2reg; | |
1206 | } | |
b90ce3c3 | 1207 | if (GET_CODE (lim) == SYMBOL_REF) |
1208 | { | |
b90ce3c3 | 1209 | if (TARGET_ID_SHARED_LIBRARY) |
1210 | { | |
1211 | rtx p1reg = gen_rtx_REG (Pmode, REG_P1); | |
b90ce3c3 | 1212 | rtx val; |
70d893c7 | 1213 | pic_reg_loaded = bfin_load_pic_reg (p2reg); |
1214 | val = legitimize_pic_address (stack_limit_rtx, p1reg, | |
1215 | pic_reg_loaded); | |
b90ce3c3 | 1216 | emit_move_insn (p1reg, val); |
1217 | frame_related_constant_load (p2reg, offset, FALSE); | |
1218 | emit_insn (gen_addsi3 (p2reg, p2reg, p1reg)); | |
1219 | lim = p2reg; | |
1220 | } | |
1221 | else | |
1222 | { | |
6295e560 | 1223 | rtx limit = plus_constant (lim, offset); |
b90ce3c3 | 1224 | emit_move_insn (p2reg, limit); |
1225 | lim = p2reg; | |
1226 | } | |
1227 | } | |
6295e560 | 1228 | else |
1229 | { | |
1230 | if (lim != p2reg) | |
1231 | emit_move_insn (p2reg, lim); | |
a35b82b9 | 1232 | add_to_reg (p2reg, offset, 0, 0); |
6295e560 | 1233 | lim = p2reg; |
1234 | } | |
b90ce3c3 | 1235 | emit_insn (gen_compare_lt (bfin_cc_rtx, spreg, lim)); |
1236 | emit_insn (gen_trapifcc ()); | |
1237 | } | |
49569132 | 1238 | expand_prologue_reg_save (spreg, all, false); |
9e6a0967 | 1239 | |
345458f3 | 1240 | do_link (spreg, frame_size, false); |
9e6a0967 | 1241 | |
1242 | if (TARGET_ID_SHARED_LIBRARY | |
40831b00 | 1243 | && !TARGET_SEP_DATA |
18d50ae6 | 1244 | && (crtl->uses_pic_offset_table |
9e6a0967 | 1245 | || !current_function_is_leaf)) |
b90ce3c3 | 1246 | bfin_load_pic_reg (pic_offset_table_rtx); |
9e6a0967 | 1247 | } |
1248 | ||
1249 | /* Generate RTL for the epilogue of the current function. NEED_RETURN is zero | |
1250 | if this is for a sibcall. EH_RETURN is nonzero if we're expanding an | |
a35b82b9 | 1251 | eh_return pattern. SIBCALL_P is true if this is a sibcall epilogue, |
1252 | false otherwise. */ | |
9e6a0967 | 1253 | |
1254 | void | |
a35b82b9 | 1255 | bfin_expand_epilogue (int need_return, int eh_return, bool sibcall_p) |
9e6a0967 | 1256 | { |
1257 | rtx spreg = gen_rtx_REG (Pmode, REG_SP); | |
1258 | e_funkind fkind = funkind (TREE_TYPE (current_function_decl)); | |
a35b82b9 | 1259 | int e = sibcall_p ? -1 : 1; |
49569132 | 1260 | tree attrs = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl)); |
1261 | bool all = lookup_attribute ("saveall", attrs) != NULL_TREE; | |
9e6a0967 | 1262 | |
1263 | if (fkind != SUBROUTINE) | |
1264 | { | |
49569132 | 1265 | expand_interrupt_handler_epilogue (spreg, fkind, all); |
9e6a0967 | 1266 | return; |
1267 | } | |
1268 | ||
a35b82b9 | 1269 | do_unlink (spreg, get_frame_size (), false, e); |
9e6a0967 | 1270 | |
49569132 | 1271 | expand_epilogue_reg_restore (spreg, all, false); |
9e6a0967 | 1272 | |
1273 | /* Omit the return insn if this is for a sibcall. */ | |
1274 | if (! need_return) | |
1275 | return; | |
1276 | ||
1277 | if (eh_return) | |
1278 | emit_insn (gen_addsi3 (spreg, spreg, gen_rtx_REG (Pmode, REG_P2))); | |
1279 | ||
1280 | emit_jump_insn (gen_return_internal (GEN_INT (SUBROUTINE))); | |
1281 | } | |
1282 | \f | |
1283 | /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */ | |
1284 | ||
1285 | int | |
1286 | bfin_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, | |
1287 | unsigned int new_reg) | |
1288 | { | |
1289 | /* Interrupt functions can only use registers that have already been | |
1290 | saved by the prologue, even if they would normally be | |
1291 | call-clobbered. */ | |
1292 | ||
1293 | if (funkind (TREE_TYPE (current_function_decl)) != SUBROUTINE | |
3072d30e | 1294 | && !df_regs_ever_live_p (new_reg)) |
9e6a0967 | 1295 | return 0; |
1296 | ||
1297 | return 1; | |
1298 | } | |
1299 | ||
1300 | /* Return the value of the return address for the frame COUNT steps up | |
1301 | from the current frame, after the prologue. | |
1302 | We punt for everything but the current frame by returning const0_rtx. */ | |
1303 | ||
1304 | rtx | |
1305 | bfin_return_addr_rtx (int count) | |
1306 | { | |
1307 | if (count != 0) | |
1308 | return const0_rtx; | |
1309 | ||
1310 | return get_hard_reg_initial_val (Pmode, REG_RETS); | |
1311 | } | |
1312 | ||
1313 | /* Try machine-dependent ways of modifying an illegitimate address X | |
1314 | to be legitimate. If we find one, return the new, valid address, | |
1315 | otherwise return NULL_RTX. | |
1316 | ||
1317 | OLDX is the address as it was before break_out_memory_refs was called. | |
1318 | In some cases it is useful to look at this to decide what needs to be done. | |
1319 | ||
1320 | MODE is the mode of the memory reference. */ | |
1321 | ||
1322 | rtx | |
1323 | legitimize_address (rtx x ATTRIBUTE_UNUSED, rtx oldx ATTRIBUTE_UNUSED, | |
1324 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
1325 | { | |
1326 | return NULL_RTX; | |
1327 | } | |
1328 | ||
6833eae4 | 1329 | static rtx |
1330 | bfin_delegitimize_address (rtx orig_x) | |
1331 | { | |
2b8e874f | 1332 | rtx x = orig_x; |
6833eae4 | 1333 | |
1334 | if (GET_CODE (x) != MEM) | |
1335 | return orig_x; | |
1336 | ||
1337 | x = XEXP (x, 0); | |
1338 | if (GET_CODE (x) == PLUS | |
1339 | && GET_CODE (XEXP (x, 1)) == UNSPEC | |
1340 | && XINT (XEXP (x, 1), 1) == UNSPEC_MOVE_PIC | |
1341 | && GET_CODE (XEXP (x, 0)) == REG | |
1342 | && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM) | |
1343 | return XVECEXP (XEXP (x, 1), 0, 0); | |
1344 | ||
1345 | return orig_x; | |
1346 | } | |
1347 | ||
9e6a0967 | 1348 | /* This predicate is used to compute the length of a load/store insn. |
1349 | OP is a MEM rtx, we return nonzero if its addressing mode requires a | |
905ea169 | 1350 | 32-bit instruction. */ |
9e6a0967 | 1351 | |
1352 | int | |
1353 | effective_address_32bit_p (rtx op, enum machine_mode mode) | |
1354 | { | |
1355 | HOST_WIDE_INT offset; | |
1356 | ||
1357 | mode = GET_MODE (op); | |
1358 | op = XEXP (op, 0); | |
1359 | ||
9e6a0967 | 1360 | if (GET_CODE (op) != PLUS) |
2115ae11 | 1361 | { |
1362 | gcc_assert (REG_P (op) || GET_CODE (op) == POST_INC | |
1363 | || GET_CODE (op) == PRE_DEC || GET_CODE (op) == POST_DEC); | |
1364 | return 0; | |
1365 | } | |
9e6a0967 | 1366 | |
4c359296 | 1367 | if (GET_CODE (XEXP (op, 1)) == UNSPEC) |
1368 | return 1; | |
1369 | ||
9e6a0967 | 1370 | offset = INTVAL (XEXP (op, 1)); |
1371 | ||
905ea169 | 1372 | /* All byte loads use a 16-bit offset. */ |
9e6a0967 | 1373 | if (GET_MODE_SIZE (mode) == 1) |
1374 | return 1; | |
1375 | ||
1376 | if (GET_MODE_SIZE (mode) == 4) | |
1377 | { | |
1378 | /* Frame pointer relative loads can use a negative offset, all others | |
1379 | are restricted to a small positive one. */ | |
1380 | if (XEXP (op, 0) == frame_pointer_rtx) | |
1381 | return offset < -128 || offset > 60; | |
1382 | return offset < 0 || offset > 60; | |
1383 | } | |
1384 | ||
1385 | /* Must be HImode now. */ | |
1386 | return offset < 0 || offset > 30; | |
1387 | } | |
1388 | ||
00cb30dc | 1389 | /* Returns true if X is a memory reference using an I register. */ |
1390 | bool | |
1391 | bfin_dsp_memref_p (rtx x) | |
1392 | { | |
1393 | if (! MEM_P (x)) | |
1394 | return false; | |
1395 | x = XEXP (x, 0); | |
1396 | if (GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_INC | |
1397 | || GET_CODE (x) == POST_DEC || GET_CODE (x) == PRE_DEC) | |
1398 | x = XEXP (x, 0); | |
1399 | return IREG_P (x); | |
1400 | } | |
1401 | ||
9e6a0967 | 1402 | /* Return cost of the memory address ADDR. |
1403 | All addressing modes are equally cheap on the Blackfin. */ | |
1404 | ||
1405 | static int | |
f529eb25 | 1406 | bfin_address_cost (rtx addr ATTRIBUTE_UNUSED, bool speed ATTRIBUTE_UNUSED) |
9e6a0967 | 1407 | { |
1408 | return 1; | |
1409 | } | |
1410 | ||
1411 | /* Subroutine of print_operand; used to print a memory reference X to FILE. */ | |
1412 | ||
1413 | void | |
1414 | print_address_operand (FILE *file, rtx x) | |
1415 | { | |
9e6a0967 | 1416 | switch (GET_CODE (x)) |
1417 | { | |
1418 | case PLUS: | |
1419 | output_address (XEXP (x, 0)); | |
1420 | fprintf (file, "+"); | |
1421 | output_address (XEXP (x, 1)); | |
1422 | break; | |
1423 | ||
1424 | case PRE_DEC: | |
1425 | fprintf (file, "--"); | |
1426 | output_address (XEXP (x, 0)); | |
1427 | break; | |
1428 | case POST_INC: | |
1429 | output_address (XEXP (x, 0)); | |
1430 | fprintf (file, "++"); | |
1431 | break; | |
1432 | case POST_DEC: | |
1433 | output_address (XEXP (x, 0)); | |
1434 | fprintf (file, "--"); | |
1435 | break; | |
1436 | ||
1437 | default: | |
2115ae11 | 1438 | gcc_assert (GET_CODE (x) != MEM); |
9e6a0967 | 1439 | print_operand (file, x, 0); |
2115ae11 | 1440 | break; |
9e6a0967 | 1441 | } |
1442 | } | |
1443 | ||
1444 | /* Adding intp DImode support by Tony | |
1445 | * -- Q: (low word) | |
1446 | * -- R: (high word) | |
1447 | */ | |
1448 | ||
1449 | void | |
1450 | print_operand (FILE *file, rtx x, char code) | |
1451 | { | |
48df5a7f | 1452 | enum machine_mode mode; |
1453 | ||
1454 | if (code == '!') | |
1455 | { | |
1456 | if (GET_MODE (current_output_insn) == SImode) | |
1457 | fprintf (file, " ||"); | |
1458 | else | |
1459 | fprintf (file, ";"); | |
1460 | return; | |
1461 | } | |
1462 | ||
1463 | mode = GET_MODE (x); | |
9e6a0967 | 1464 | |
1465 | switch (code) | |
1466 | { | |
1467 | case 'j': | |
1468 | switch (GET_CODE (x)) | |
1469 | { | |
1470 | case EQ: | |
1471 | fprintf (file, "e"); | |
1472 | break; | |
1473 | case NE: | |
1474 | fprintf (file, "ne"); | |
1475 | break; | |
1476 | case GT: | |
1477 | fprintf (file, "g"); | |
1478 | break; | |
1479 | case LT: | |
1480 | fprintf (file, "l"); | |
1481 | break; | |
1482 | case GE: | |
1483 | fprintf (file, "ge"); | |
1484 | break; | |
1485 | case LE: | |
1486 | fprintf (file, "le"); | |
1487 | break; | |
1488 | case GTU: | |
1489 | fprintf (file, "g"); | |
1490 | break; | |
1491 | case LTU: | |
1492 | fprintf (file, "l"); | |
1493 | break; | |
1494 | case GEU: | |
1495 | fprintf (file, "ge"); | |
1496 | break; | |
1497 | case LEU: | |
1498 | fprintf (file, "le"); | |
1499 | break; | |
1500 | default: | |
1501 | output_operand_lossage ("invalid %%j value"); | |
1502 | } | |
1503 | break; | |
1504 | ||
1505 | case 'J': /* reverse logic */ | |
1506 | switch (GET_CODE(x)) | |
1507 | { | |
1508 | case EQ: | |
1509 | fprintf (file, "ne"); | |
1510 | break; | |
1511 | case NE: | |
1512 | fprintf (file, "e"); | |
1513 | break; | |
1514 | case GT: | |
1515 | fprintf (file, "le"); | |
1516 | break; | |
1517 | case LT: | |
1518 | fprintf (file, "ge"); | |
1519 | break; | |
1520 | case GE: | |
1521 | fprintf (file, "l"); | |
1522 | break; | |
1523 | case LE: | |
1524 | fprintf (file, "g"); | |
1525 | break; | |
1526 | case GTU: | |
1527 | fprintf (file, "le"); | |
1528 | break; | |
1529 | case LTU: | |
1530 | fprintf (file, "ge"); | |
1531 | break; | |
1532 | case GEU: | |
1533 | fprintf (file, "l"); | |
1534 | break; | |
1535 | case LEU: | |
1536 | fprintf (file, "g"); | |
1537 | break; | |
1538 | default: | |
1539 | output_operand_lossage ("invalid %%J value"); | |
1540 | } | |
1541 | break; | |
1542 | ||
1543 | default: | |
1544 | switch (GET_CODE (x)) | |
1545 | { | |
1546 | case REG: | |
1547 | if (code == 'h') | |
1548 | { | |
108988a0 | 1549 | if (REGNO (x) < 32) |
1550 | fprintf (file, "%s", short_reg_names[REGNO (x)]); | |
1551 | else | |
1552 | output_operand_lossage ("invalid operand for code '%c'", code); | |
9e6a0967 | 1553 | } |
1554 | else if (code == 'd') | |
1555 | { | |
108988a0 | 1556 | if (REGNO (x) < 32) |
1557 | fprintf (file, "%s", high_reg_names[REGNO (x)]); | |
1558 | else | |
1559 | output_operand_lossage ("invalid operand for code '%c'", code); | |
9e6a0967 | 1560 | } |
1561 | else if (code == 'w') | |
1562 | { | |
108988a0 | 1563 | if (REGNO (x) == REG_A0 || REGNO (x) == REG_A1) |
1564 | fprintf (file, "%s.w", reg_names[REGNO (x)]); | |
1565 | else | |
1566 | output_operand_lossage ("invalid operand for code '%c'", code); | |
9e6a0967 | 1567 | } |
1568 | else if (code == 'x') | |
1569 | { | |
108988a0 | 1570 | if (REGNO (x) == REG_A0 || REGNO (x) == REG_A1) |
1571 | fprintf (file, "%s.x", reg_names[REGNO (x)]); | |
1572 | else | |
1573 | output_operand_lossage ("invalid operand for code '%c'", code); | |
9e6a0967 | 1574 | } |
a4317a50 | 1575 | else if (code == 'v') |
1576 | { | |
1577 | if (REGNO (x) == REG_A0) | |
1578 | fprintf (file, "AV0"); | |
1579 | else if (REGNO (x) == REG_A1) | |
1580 | fprintf (file, "AV1"); | |
1581 | else | |
1582 | output_operand_lossage ("invalid operand for code '%c'", code); | |
1583 | } | |
9e6a0967 | 1584 | else if (code == 'D') |
1585 | { | |
108988a0 | 1586 | if (D_REGNO_P (REGNO (x))) |
1587 | fprintf (file, "%s", dregs_pair_names[REGNO (x)]); | |
1588 | else | |
1589 | output_operand_lossage ("invalid operand for code '%c'", code); | |
9e6a0967 | 1590 | } |
1591 | else if (code == 'H') | |
1592 | { | |
108988a0 | 1593 | if ((mode == DImode || mode == DFmode) && REG_P (x)) |
1594 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); | |
1595 | else | |
1596 | output_operand_lossage ("invalid operand for code '%c'", code); | |
9e6a0967 | 1597 | } |
1598 | else if (code == 'T') | |
1599 | { | |
108988a0 | 1600 | if (D_REGNO_P (REGNO (x))) |
1601 | fprintf (file, "%s", byte_reg_names[REGNO (x)]); | |
1602 | else | |
1603 | output_operand_lossage ("invalid operand for code '%c'", code); | |
9e6a0967 | 1604 | } |
1605 | else | |
1606 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
1607 | break; | |
1608 | ||
1609 | case MEM: | |
1610 | fputc ('[', file); | |
1611 | x = XEXP (x,0); | |
1612 | print_address_operand (file, x); | |
1613 | fputc (']', file); | |
1614 | break; | |
1615 | ||
1616 | case CONST_INT: | |
0bdbecff | 1617 | if (code == 'M') |
1618 | { | |
1619 | switch (INTVAL (x)) | |
1620 | { | |
1621 | case MACFLAG_NONE: | |
1622 | break; | |
1623 | case MACFLAG_FU: | |
1624 | fputs ("(FU)", file); | |
1625 | break; | |
1626 | case MACFLAG_T: | |
1627 | fputs ("(T)", file); | |
1628 | break; | |
1629 | case MACFLAG_TFU: | |
1630 | fputs ("(TFU)", file); | |
1631 | break; | |
1632 | case MACFLAG_W32: | |
1633 | fputs ("(W32)", file); | |
1634 | break; | |
1635 | case MACFLAG_IS: | |
1636 | fputs ("(IS)", file); | |
1637 | break; | |
1638 | case MACFLAG_IU: | |
1639 | fputs ("(IU)", file); | |
1640 | break; | |
1641 | case MACFLAG_IH: | |
1642 | fputs ("(IH)", file); | |
1643 | break; | |
1644 | case MACFLAG_M: | |
1645 | fputs ("(M)", file); | |
1646 | break; | |
9422b03b | 1647 | case MACFLAG_IS_M: |
1648 | fputs ("(IS,M)", file); | |
1649 | break; | |
0bdbecff | 1650 | case MACFLAG_ISS2: |
1651 | fputs ("(ISS2)", file); | |
1652 | break; | |
1653 | case MACFLAG_S2RND: | |
1654 | fputs ("(S2RND)", file); | |
1655 | break; | |
1656 | default: | |
1657 | gcc_unreachable (); | |
1658 | } | |
1659 | break; | |
1660 | } | |
1661 | else if (code == 'b') | |
1662 | { | |
1663 | if (INTVAL (x) == 0) | |
1664 | fputs ("+=", file); | |
1665 | else if (INTVAL (x) == 1) | |
1666 | fputs ("-=", file); | |
1667 | else | |
1668 | gcc_unreachable (); | |
1669 | break; | |
1670 | } | |
9e6a0967 | 1671 | /* Moves to half registers with d or h modifiers always use unsigned |
1672 | constants. */ | |
0bdbecff | 1673 | else if (code == 'd') |
9e6a0967 | 1674 | x = GEN_INT ((INTVAL (x) >> 16) & 0xffff); |
1675 | else if (code == 'h') | |
1676 | x = GEN_INT (INTVAL (x) & 0xffff); | |
5af6d8d8 | 1677 | else if (code == 'N') |
1678 | x = GEN_INT (-INTVAL (x)); | |
9e6a0967 | 1679 | else if (code == 'X') |
1680 | x = GEN_INT (exact_log2 (0xffffffff & INTVAL (x))); | |
1681 | else if (code == 'Y') | |
1682 | x = GEN_INT (exact_log2 (0xffffffff & ~INTVAL (x))); | |
1683 | else if (code == 'Z') | |
1684 | /* Used for LINK insns. */ | |
1685 | x = GEN_INT (-8 - INTVAL (x)); | |
1686 | ||
1687 | /* fall through */ | |
1688 | ||
1689 | case SYMBOL_REF: | |
1690 | output_addr_const (file, x); | |
9e6a0967 | 1691 | break; |
1692 | ||
1693 | case CONST_DOUBLE: | |
1694 | output_operand_lossage ("invalid const_double operand"); | |
1695 | break; | |
1696 | ||
1697 | case UNSPEC: | |
2115ae11 | 1698 | switch (XINT (x, 1)) |
9e6a0967 | 1699 | { |
2115ae11 | 1700 | case UNSPEC_MOVE_PIC: |
9e6a0967 | 1701 | output_addr_const (file, XVECEXP (x, 0, 0)); |
1702 | fprintf (file, "@GOT"); | |
2115ae11 | 1703 | break; |
1704 | ||
55be0e32 | 1705 | case UNSPEC_MOVE_FDPIC: |
1706 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1707 | fprintf (file, "@GOT17M4"); | |
1708 | break; | |
1709 | ||
1710 | case UNSPEC_FUNCDESC_GOT17M4: | |
1711 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1712 | fprintf (file, "@FUNCDESC_GOT17M4"); | |
1713 | break; | |
1714 | ||
2115ae11 | 1715 | case UNSPEC_LIBRARY_OFFSET: |
1716 | fprintf (file, "_current_shared_library_p5_offset_"); | |
1717 | break; | |
1718 | ||
1719 | default: | |
1720 | gcc_unreachable (); | |
9e6a0967 | 1721 | } |
9e6a0967 | 1722 | break; |
1723 | ||
1724 | default: | |
1725 | output_addr_const (file, x); | |
1726 | } | |
1727 | } | |
1728 | } | |
1729 | \f | |
1730 | /* Argument support functions. */ | |
1731 | ||
1732 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1733 | for a call to a function whose data type is FNTYPE. | |
1734 | For a library call, FNTYPE is 0. | |
1735 | VDSP C Compiler manual, our ABI says that | |
1736 | first 3 words of arguments will use R0, R1 and R2. | |
1737 | */ | |
1738 | ||
1739 | void | |
7b6ef6dd | 1740 | init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, |
9e6a0967 | 1741 | rtx libname ATTRIBUTE_UNUSED) |
1742 | { | |
1743 | static CUMULATIVE_ARGS zero_cum; | |
1744 | ||
1745 | *cum = zero_cum; | |
1746 | ||
1747 | /* Set up the number of registers to use for passing arguments. */ | |
1748 | ||
1749 | cum->nregs = max_arg_registers; | |
1750 | cum->arg_regs = arg_regs; | |
1751 | ||
7b6ef6dd | 1752 | cum->call_cookie = CALL_NORMAL; |
1753 | /* Check for a longcall attribute. */ | |
1754 | if (fntype && lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))) | |
1755 | cum->call_cookie |= CALL_SHORT; | |
1756 | else if (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))) | |
1757 | cum->call_cookie |= CALL_LONG; | |
1758 | ||
9e6a0967 | 1759 | return; |
1760 | } | |
1761 | ||
1762 | /* Update the data in CUM to advance over an argument | |
1763 | of mode MODE and data type TYPE. | |
1764 | (TYPE is null for libcalls where that information may not be available.) */ | |
1765 | ||
1766 | void | |
1767 | function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, | |
1768 | int named ATTRIBUTE_UNUSED) | |
1769 | { | |
1770 | int count, bytes, words; | |
1771 | ||
1772 | bytes = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); | |
1773 | words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
1774 | ||
1775 | cum->words += words; | |
1776 | cum->nregs -= words; | |
1777 | ||
1778 | if (cum->nregs <= 0) | |
1779 | { | |
1780 | cum->nregs = 0; | |
1781 | cum->arg_regs = NULL; | |
1782 | } | |
1783 | else | |
1784 | { | |
1785 | for (count = 1; count <= words; count++) | |
1786 | cum->arg_regs++; | |
1787 | } | |
1788 | ||
1789 | return; | |
1790 | } | |
1791 | ||
1792 | /* Define where to put the arguments to a function. | |
1793 | Value is zero to push the argument on the stack, | |
1794 | or a hard register in which to store the argument. | |
1795 | ||
1796 | MODE is the argument's machine mode. | |
1797 | TYPE is the data type of the argument (as a tree). | |
1798 | This is null for libcalls where that information may | |
1799 | not be available. | |
1800 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1801 | the preceding args and about the function being called. | |
1802 | NAMED is nonzero if this argument is a named parameter | |
1803 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1804 | ||
1805 | struct rtx_def * | |
1806 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, | |
1807 | int named ATTRIBUTE_UNUSED) | |
1808 | { | |
1809 | int bytes | |
1810 | = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); | |
1811 | ||
7b6ef6dd | 1812 | if (mode == VOIDmode) |
1813 | /* Compute operand 2 of the call insn. */ | |
1814 | return GEN_INT (cum->call_cookie); | |
1815 | ||
9e6a0967 | 1816 | if (bytes == -1) |
1817 | return NULL_RTX; | |
1818 | ||
1819 | if (cum->nregs) | |
1820 | return gen_rtx_REG (mode, *(cum->arg_regs)); | |
1821 | ||
1822 | return NULL_RTX; | |
1823 | } | |
1824 | ||
1825 | /* For an arg passed partly in registers and partly in memory, | |
1826 | this is the number of bytes passed in registers. | |
1827 | For args passed entirely in registers or entirely in memory, zero. | |
1828 | ||
1829 | Refer VDSP C Compiler manual, our ABI. | |
85694bac | 1830 | First 3 words are in registers. So, if an argument is larger |
9e6a0967 | 1831 | than the registers available, it will span the register and |
1832 | stack. */ | |
1833 | ||
1834 | static int | |
1835 | bfin_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
1836 | tree type ATTRIBUTE_UNUSED, | |
1837 | bool named ATTRIBUTE_UNUSED) | |
1838 | { | |
1839 | int bytes | |
1840 | = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); | |
1841 | int bytes_left = cum->nregs * UNITS_PER_WORD; | |
1842 | ||
1843 | if (bytes == -1) | |
1844 | return 0; | |
1845 | ||
1846 | if (bytes_left == 0) | |
1847 | return 0; | |
1848 | if (bytes > bytes_left) | |
1849 | return bytes_left; | |
1850 | return 0; | |
1851 | } | |
1852 | ||
1853 | /* Variable sized types are passed by reference. */ | |
1854 | ||
1855 | static bool | |
1856 | bfin_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, | |
1857 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
fb80456a | 1858 | const_tree type, bool named ATTRIBUTE_UNUSED) |
9e6a0967 | 1859 | { |
1860 | return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST; | |
1861 | } | |
1862 | ||
1863 | /* Decide whether a type should be returned in memory (true) | |
1864 | or in a register (false). This is called by the macro | |
22c61100 | 1865 | TARGET_RETURN_IN_MEMORY. */ |
9e6a0967 | 1866 | |
0a619688 | 1867 | static bool |
22c61100 | 1868 | bfin_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
9e6a0967 | 1869 | { |
8683c45f | 1870 | int size = int_size_in_bytes (type); |
1871 | return size > 2 * UNITS_PER_WORD || size == -1; | |
9e6a0967 | 1872 | } |
1873 | ||
1874 | /* Register in which address to store a structure value | |
1875 | is passed to a function. */ | |
1876 | static rtx | |
1877 | bfin_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
1878 | int incoming ATTRIBUTE_UNUSED) | |
1879 | { | |
1880 | return gen_rtx_REG (Pmode, REG_P0); | |
1881 | } | |
1882 | ||
1883 | /* Return true when register may be used to pass function parameters. */ | |
1884 | ||
1885 | bool | |
1886 | function_arg_regno_p (int n) | |
1887 | { | |
1888 | int i; | |
1889 | for (i = 0; arg_regs[i] != -1; i++) | |
1890 | if (n == arg_regs[i]) | |
1891 | return true; | |
1892 | return false; | |
1893 | } | |
1894 | ||
1895 | /* Returns 1 if OP contains a symbol reference */ | |
1896 | ||
1897 | int | |
1898 | symbolic_reference_mentioned_p (rtx op) | |
1899 | { | |
1900 | register const char *fmt; | |
1901 | register int i; | |
1902 | ||
1903 | if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF) | |
1904 | return 1; | |
1905 | ||
1906 | fmt = GET_RTX_FORMAT (GET_CODE (op)); | |
1907 | for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--) | |
1908 | { | |
1909 | if (fmt[i] == 'E') | |
1910 | { | |
1911 | register int j; | |
1912 | ||
1913 | for (j = XVECLEN (op, i) - 1; j >= 0; j--) | |
1914 | if (symbolic_reference_mentioned_p (XVECEXP (op, i, j))) | |
1915 | return 1; | |
1916 | } | |
1917 | ||
1918 | else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i))) | |
1919 | return 1; | |
1920 | } | |
1921 | ||
1922 | return 0; | |
1923 | } | |
1924 | ||
1925 | /* Decide whether we can make a sibling call to a function. DECL is the | |
1926 | declaration of the function being targeted by the call and EXP is the | |
1927 | CALL_EXPR representing the call. */ | |
1928 | ||
1929 | static bool | |
1930 | bfin_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED, | |
1931 | tree exp ATTRIBUTE_UNUSED) | |
1932 | { | |
6329636b | 1933 | struct cgraph_local_info *this_func, *called_func; |
345458f3 | 1934 | e_funkind fkind = funkind (TREE_TYPE (current_function_decl)); |
f9ecc035 | 1935 | if (fkind != SUBROUTINE) |
1936 | return false; | |
1937 | if (!TARGET_ID_SHARED_LIBRARY || TARGET_SEP_DATA) | |
1938 | return true; | |
1939 | ||
1940 | /* When compiling for ID shared libraries, can't sibcall a local function | |
1941 | from a non-local function, because the local function thinks it does | |
1942 | not need to reload P5 in the prologue, but the sibcall wil pop P5 in the | |
1943 | sibcall epilogue, and we end up with the wrong value in P5. */ | |
1944 | ||
e5f223f4 | 1945 | if (!decl) |
1946 | /* Not enough information. */ | |
1947 | return false; | |
f9ecc035 | 1948 | |
6329636b | 1949 | this_func = cgraph_local_info (current_function_decl); |
1950 | called_func = cgraph_local_info (decl); | |
1951 | return !called_func->local || this_func->local; | |
9e6a0967 | 1952 | } |
1953 | \f | |
1954 | /* Emit RTL insns to initialize the variable parts of a trampoline at | |
1955 | TRAMP. FNADDR is an RTX for the address of the function's pure | |
1956 | code. CXT is an RTX for the static chain value for the function. */ | |
1957 | ||
1958 | void | |
2b8e874f | 1959 | initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt) |
9e6a0967 | 1960 | { |
1961 | rtx t1 = copy_to_reg (fnaddr); | |
1962 | rtx t2 = copy_to_reg (cxt); | |
1963 | rtx addr; | |
55be0e32 | 1964 | int i = 0; |
1965 | ||
1966 | if (TARGET_FDPIC) | |
1967 | { | |
1968 | rtx a = memory_address (Pmode, plus_constant (tramp, 8)); | |
1969 | addr = memory_address (Pmode, tramp); | |
1970 | emit_move_insn (gen_rtx_MEM (SImode, addr), a); | |
1971 | i = 8; | |
1972 | } | |
9e6a0967 | 1973 | |
55be0e32 | 1974 | addr = memory_address (Pmode, plus_constant (tramp, i + 2)); |
9e6a0967 | 1975 | emit_move_insn (gen_rtx_MEM (HImode, addr), gen_lowpart (HImode, t1)); |
1976 | emit_insn (gen_ashrsi3 (t1, t1, GEN_INT (16))); | |
55be0e32 | 1977 | addr = memory_address (Pmode, plus_constant (tramp, i + 6)); |
9e6a0967 | 1978 | emit_move_insn (gen_rtx_MEM (HImode, addr), gen_lowpart (HImode, t1)); |
1979 | ||
55be0e32 | 1980 | addr = memory_address (Pmode, plus_constant (tramp, i + 10)); |
9e6a0967 | 1981 | emit_move_insn (gen_rtx_MEM (HImode, addr), gen_lowpart (HImode, t2)); |
1982 | emit_insn (gen_ashrsi3 (t2, t2, GEN_INT (16))); | |
55be0e32 | 1983 | addr = memory_address (Pmode, plus_constant (tramp, i + 14)); |
9e6a0967 | 1984 | emit_move_insn (gen_rtx_MEM (HImode, addr), gen_lowpart (HImode, t2)); |
1985 | } | |
1986 | ||
9e6a0967 | 1987 | /* Emit insns to move operands[1] into operands[0]. */ |
1988 | ||
1989 | void | |
1990 | emit_pic_move (rtx *operands, enum machine_mode mode ATTRIBUTE_UNUSED) | |
1991 | { | |
1992 | rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); | |
1993 | ||
55be0e32 | 1994 | gcc_assert (!TARGET_FDPIC || !(reload_in_progress || reload_completed)); |
9e6a0967 | 1995 | if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1])) |
1996 | operands[1] = force_reg (SImode, operands[1]); | |
1997 | else | |
b90ce3c3 | 1998 | operands[1] = legitimize_pic_address (operands[1], temp, |
55be0e32 | 1999 | TARGET_FDPIC ? OUR_FDPIC_REG |
2000 | : pic_offset_table_rtx); | |
9e6a0967 | 2001 | } |
2002 | ||
cf63c743 | 2003 | /* Expand a move operation in mode MODE. The operands are in OPERANDS. |
2004 | Returns true if no further code must be generated, false if the caller | |
2005 | should generate an insn to move OPERANDS[1] to OPERANDS[0]. */ | |
9e6a0967 | 2006 | |
cf63c743 | 2007 | bool |
9e6a0967 | 2008 | expand_move (rtx *operands, enum machine_mode mode) |
2009 | { | |
55be0e32 | 2010 | rtx op = operands[1]; |
2011 | if ((TARGET_ID_SHARED_LIBRARY || TARGET_FDPIC) | |
2012 | && SYMBOLIC_CONST (op)) | |
9e6a0967 | 2013 | emit_pic_move (operands, mode); |
cf63c743 | 2014 | else if (mode == SImode && GET_CODE (op) == CONST |
2015 | && GET_CODE (XEXP (op, 0)) == PLUS | |
2016 | && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF | |
2017 | && !bfin_legitimate_constant_p (op)) | |
2018 | { | |
2019 | rtx dest = operands[0]; | |
2020 | rtx op0, op1; | |
2021 | gcc_assert (!reload_in_progress && !reload_completed); | |
2022 | op = XEXP (op, 0); | |
2023 | op0 = force_reg (mode, XEXP (op, 0)); | |
2024 | op1 = XEXP (op, 1); | |
2025 | if (!insn_data[CODE_FOR_addsi3].operand[2].predicate (op1, mode)) | |
2026 | op1 = force_reg (mode, op1); | |
2027 | if (GET_CODE (dest) == MEM) | |
2028 | dest = gen_reg_rtx (mode); | |
2029 | emit_insn (gen_addsi3 (dest, op0, op1)); | |
2030 | if (dest == operands[0]) | |
2031 | return true; | |
2032 | operands[1] = dest; | |
2033 | } | |
9e6a0967 | 2034 | /* Don't generate memory->memory or constant->memory moves, go through a |
2035 | register */ | |
2036 | else if ((reload_in_progress | reload_completed) == 0 | |
2037 | && GET_CODE (operands[0]) == MEM | |
2038 | && GET_CODE (operands[1]) != REG) | |
2039 | operands[1] = force_reg (mode, operands[1]); | |
cf63c743 | 2040 | return false; |
9e6a0967 | 2041 | } |
2042 | \f | |
2043 | /* Split one or more DImode RTL references into pairs of SImode | |
2044 | references. The RTL can be REG, offsettable MEM, integer constant, or | |
2045 | CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to | |
2046 | split and "num" is its length. lo_half and hi_half are output arrays | |
2047 | that parallel "operands". */ | |
2048 | ||
2049 | void | |
2050 | split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[]) | |
2051 | { | |
2052 | while (num--) | |
2053 | { | |
2054 | rtx op = operands[num]; | |
2055 | ||
2056 | /* simplify_subreg refuse to split volatile memory addresses, | |
2057 | but we still have to handle it. */ | |
2058 | if (GET_CODE (op) == MEM) | |
2059 | { | |
2060 | lo_half[num] = adjust_address (op, SImode, 0); | |
2061 | hi_half[num] = adjust_address (op, SImode, 4); | |
2062 | } | |
2063 | else | |
2064 | { | |
2065 | lo_half[num] = simplify_gen_subreg (SImode, op, | |
2066 | GET_MODE (op) == VOIDmode | |
2067 | ? DImode : GET_MODE (op), 0); | |
2068 | hi_half[num] = simplify_gen_subreg (SImode, op, | |
2069 | GET_MODE (op) == VOIDmode | |
2070 | ? DImode : GET_MODE (op), 4); | |
2071 | } | |
2072 | } | |
2073 | } | |
2074 | \f | |
7b6ef6dd | 2075 | bool |
2076 | bfin_longcall_p (rtx op, int call_cookie) | |
2077 | { | |
2078 | gcc_assert (GET_CODE (op) == SYMBOL_REF); | |
2079 | if (call_cookie & CALL_SHORT) | |
2080 | return 0; | |
2081 | if (call_cookie & CALL_LONG) | |
2082 | return 1; | |
2083 | if (TARGET_LONG_CALLS) | |
2084 | return 1; | |
2085 | return 0; | |
2086 | } | |
2087 | ||
9e6a0967 | 2088 | /* Expand a call instruction. FNADDR is the call target, RETVAL the return value. |
7b6ef6dd | 2089 | COOKIE is a CONST_INT holding the call_cookie prepared init_cumulative_args. |
9e6a0967 | 2090 | SIBCALL is nonzero if this is a sibling call. */ |
2091 | ||
2092 | void | |
7b6ef6dd | 2093 | bfin_expand_call (rtx retval, rtx fnaddr, rtx callarg1, rtx cookie, int sibcall) |
9e6a0967 | 2094 | { |
2095 | rtx use = NULL, call; | |
7b6ef6dd | 2096 | rtx callee = XEXP (fnaddr, 0); |
55be0e32 | 2097 | int nelts = 2 + !!sibcall; |
2098 | rtx pat; | |
2099 | rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REGNO); | |
2100 | int n; | |
7b6ef6dd | 2101 | |
2102 | /* In an untyped call, we can get NULL for operand 2. */ | |
2103 | if (cookie == NULL_RTX) | |
2104 | cookie = const0_rtx; | |
9e6a0967 | 2105 | |
2106 | /* Static functions and indirect calls don't need the pic register. */ | |
55be0e32 | 2107 | if (!TARGET_FDPIC && flag_pic |
7b6ef6dd | 2108 | && GET_CODE (callee) == SYMBOL_REF |
2109 | && !SYMBOL_REF_LOCAL_P (callee)) | |
9e6a0967 | 2110 | use_reg (&use, pic_offset_table_rtx); |
2111 | ||
55be0e32 | 2112 | if (TARGET_FDPIC) |
2113 | { | |
fc8aef7f | 2114 | int caller_has_l1_text, callee_has_l1_text; |
2115 | ||
2116 | caller_has_l1_text = callee_has_l1_text = 0; | |
2117 | ||
2118 | if (lookup_attribute ("l1_text", | |
2119 | DECL_ATTRIBUTES (cfun->decl)) != NULL_TREE) | |
2120 | caller_has_l1_text = 1; | |
2121 | ||
2122 | if (GET_CODE (callee) == SYMBOL_REF | |
2123 | && SYMBOL_REF_DECL (callee) && DECL_P (SYMBOL_REF_DECL (callee)) | |
2124 | && lookup_attribute | |
2125 | ("l1_text", | |
2126 | DECL_ATTRIBUTES (SYMBOL_REF_DECL (callee))) != NULL_TREE) | |
2127 | callee_has_l1_text = 1; | |
2128 | ||
55be0e32 | 2129 | if (GET_CODE (callee) != SYMBOL_REF |
f4ec07e4 | 2130 | || bfin_longcall_p (callee, INTVAL (cookie)) |
2131 | || (GET_CODE (callee) == SYMBOL_REF | |
2132 | && !SYMBOL_REF_LOCAL_P (callee) | |
fc8aef7f | 2133 | && TARGET_INLINE_PLT) |
2134 | || caller_has_l1_text != callee_has_l1_text | |
2135 | || (caller_has_l1_text && callee_has_l1_text | |
2136 | && (GET_CODE (callee) != SYMBOL_REF | |
2137 | || !SYMBOL_REF_LOCAL_P (callee)))) | |
55be0e32 | 2138 | { |
2139 | rtx addr = callee; | |
2140 | if (! address_operand (addr, Pmode)) | |
2141 | addr = force_reg (Pmode, addr); | |
2142 | ||
2143 | fnaddr = gen_reg_rtx (SImode); | |
2144 | emit_insn (gen_load_funcdescsi (fnaddr, addr)); | |
2145 | fnaddr = gen_rtx_MEM (Pmode, fnaddr); | |
2146 | ||
2147 | picreg = gen_reg_rtx (SImode); | |
2148 | emit_insn (gen_load_funcdescsi (picreg, | |
2149 | plus_constant (addr, 4))); | |
2150 | } | |
2151 | ||
2152 | nelts++; | |
2153 | } | |
2154 | else if ((!register_no_elim_operand (callee, Pmode) | |
2155 | && GET_CODE (callee) != SYMBOL_REF) | |
2156 | || (GET_CODE (callee) == SYMBOL_REF | |
40831b00 | 2157 | && ((TARGET_ID_SHARED_LIBRARY && !TARGET_LEAF_ID_SHARED_LIBRARY) |
55be0e32 | 2158 | || bfin_longcall_p (callee, INTVAL (cookie))))) |
9e6a0967 | 2159 | { |
7b6ef6dd | 2160 | callee = copy_to_mode_reg (Pmode, callee); |
2161 | fnaddr = gen_rtx_MEM (Pmode, callee); | |
9e6a0967 | 2162 | } |
2163 | call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1); | |
2164 | ||
2165 | if (retval) | |
2166 | call = gen_rtx_SET (VOIDmode, retval, call); | |
7b6ef6dd | 2167 | |
55be0e32 | 2168 | pat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nelts)); |
2169 | n = 0; | |
2170 | XVECEXP (pat, 0, n++) = call; | |
2171 | if (TARGET_FDPIC) | |
2172 | XVECEXP (pat, 0, n++) = gen_rtx_USE (VOIDmode, picreg); | |
2173 | XVECEXP (pat, 0, n++) = gen_rtx_USE (VOIDmode, cookie); | |
9e6a0967 | 2174 | if (sibcall) |
55be0e32 | 2175 | XVECEXP (pat, 0, n++) = gen_rtx_RETURN (VOIDmode); |
7b6ef6dd | 2176 | call = emit_call_insn (pat); |
9e6a0967 | 2177 | if (use) |
2178 | CALL_INSN_FUNCTION_USAGE (call) = use; | |
2179 | } | |
2180 | \f | |
2181 | /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */ | |
2182 | ||
2183 | int | |
2184 | hard_regno_mode_ok (int regno, enum machine_mode mode) | |
2185 | { | |
2186 | /* Allow only dregs to store value of mode HI or QI */ | |
8deb3959 | 2187 | enum reg_class rclass = REGNO_REG_CLASS (regno); |
9e6a0967 | 2188 | |
2189 | if (mode == CCmode) | |
2190 | return 0; | |
2191 | ||
2192 | if (mode == V2HImode) | |
2193 | return D_REGNO_P (regno); | |
8deb3959 | 2194 | if (rclass == CCREGS) |
9e6a0967 | 2195 | return mode == BImode; |
0bdbecff | 2196 | if (mode == PDImode || mode == V2PDImode) |
9e6a0967 | 2197 | return regno == REG_A0 || regno == REG_A1; |
cd36b2c0 | 2198 | |
905ea169 | 2199 | /* Allow all normal 32-bit regs, except REG_M3, in case regclass ever comes |
cd36b2c0 | 2200 | up with a bad register class (such as ALL_REGS) for DImode. */ |
2201 | if (mode == DImode) | |
2202 | return regno < REG_M3; | |
2203 | ||
9e6a0967 | 2204 | if (mode == SImode |
2205 | && TEST_HARD_REG_BIT (reg_class_contents[PROLOGUE_REGS], regno)) | |
2206 | return 1; | |
cd36b2c0 | 2207 | |
9e6a0967 | 2208 | return TEST_HARD_REG_BIT (reg_class_contents[MOST_REGS], regno); |
2209 | } | |
2210 | ||
2211 | /* Implements target hook vector_mode_supported_p. */ | |
2212 | ||
2213 | static bool | |
2214 | bfin_vector_mode_supported_p (enum machine_mode mode) | |
2215 | { | |
2216 | return mode == V2HImode; | |
2217 | } | |
2218 | ||
2219 | /* Return the cost of moving data from a register in class CLASS1 to | |
2220 | one in class CLASS2. A cost of 2 is the default. */ | |
2221 | ||
2222 | int | |
cd36b2c0 | 2223 | bfin_register_move_cost (enum machine_mode mode, |
9e6a0967 | 2224 | enum reg_class class1, enum reg_class class2) |
2225 | { | |
622e3203 | 2226 | /* These need secondary reloads, so they're more expensive. */ |
2227 | if ((class1 == CCREGS && class2 != DREGS) | |
2228 | || (class1 != DREGS && class2 == CCREGS)) | |
2229 | return 4; | |
2230 | ||
9e6a0967 | 2231 | /* If optimizing for size, always prefer reg-reg over reg-memory moves. */ |
2232 | if (optimize_size) | |
2233 | return 2; | |
2234 | ||
2235 | /* There are some stalls involved when moving from a DREG to a different | |
2236 | class reg, and using the value in one of the following instructions. | |
2237 | Attempt to model this by slightly discouraging such moves. */ | |
2238 | if (class1 == DREGS && class2 != DREGS) | |
2239 | return 2 * 2; | |
2240 | ||
cd36b2c0 | 2241 | if (GET_MODE_CLASS (mode) == MODE_INT) |
2242 | { | |
2243 | /* Discourage trying to use the accumulators. */ | |
2244 | if (TEST_HARD_REG_BIT (reg_class_contents[class1], REG_A0) | |
2245 | || TEST_HARD_REG_BIT (reg_class_contents[class1], REG_A1) | |
2246 | || TEST_HARD_REG_BIT (reg_class_contents[class2], REG_A0) | |
2247 | || TEST_HARD_REG_BIT (reg_class_contents[class2], REG_A1)) | |
2248 | return 20; | |
2249 | } | |
9e6a0967 | 2250 | return 2; |
2251 | } | |
2252 | ||
2253 | /* Return the cost of moving data of mode M between a | |
2254 | register and memory. A value of 2 is the default; this cost is | |
2255 | relative to those in `REGISTER_MOVE_COST'. | |
2256 | ||
2257 | ??? In theory L1 memory has single-cycle latency. We should add a switch | |
2258 | that tells the compiler whether we expect to use only L1 memory for the | |
2259 | program; it'll make the costs more accurate. */ | |
2260 | ||
2261 | int | |
2262 | bfin_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, | |
8deb3959 | 2263 | enum reg_class rclass, |
9e6a0967 | 2264 | int in ATTRIBUTE_UNUSED) |
2265 | { | |
2266 | /* Make memory accesses slightly more expensive than any register-register | |
2267 | move. Also, penalize non-DP registers, since they need secondary | |
2268 | reloads to load and store. */ | |
8deb3959 | 2269 | if (! reg_class_subset_p (rclass, DPREGS)) |
9e6a0967 | 2270 | return 10; |
2271 | ||
2272 | return 8; | |
2273 | } | |
2274 | ||
2275 | /* Inform reload about cases where moving X with a mode MODE to a register in | |
8deb3959 | 2276 | RCLASS requires an extra scratch register. Return the class needed for the |
9e6a0967 | 2277 | scratch register. */ |
2278 | ||
88eaee2d | 2279 | static enum reg_class |
8deb3959 | 2280 | bfin_secondary_reload (bool in_p, rtx x, enum reg_class rclass, |
e99611da | 2281 | enum machine_mode mode, secondary_reload_info *sri) |
9e6a0967 | 2282 | { |
2283 | /* If we have HImode or QImode, we can only use DREGS as secondary registers; | |
2284 | in most other cases we can also use PREGS. */ | |
2285 | enum reg_class default_class = GET_MODE_SIZE (mode) >= 4 ? DPREGS : DREGS; | |
2286 | enum reg_class x_class = NO_REGS; | |
2287 | enum rtx_code code = GET_CODE (x); | |
2288 | ||
2289 | if (code == SUBREG) | |
2290 | x = SUBREG_REG (x), code = GET_CODE (x); | |
2291 | if (REG_P (x)) | |
2292 | { | |
2293 | int regno = REGNO (x); | |
2294 | if (regno >= FIRST_PSEUDO_REGISTER) | |
2295 | regno = reg_renumber[regno]; | |
2296 | ||
2297 | if (regno == -1) | |
2298 | code = MEM; | |
2299 | else | |
2300 | x_class = REGNO_REG_CLASS (regno); | |
2301 | } | |
2302 | ||
2303 | /* We can be asked to reload (plus (FP) (large_constant)) into a DREG. | |
2304 | This happens as a side effect of register elimination, and we need | |
2305 | a scratch register to do it. */ | |
2306 | if (fp_plus_const_operand (x, mode)) | |
2307 | { | |
2308 | rtx op2 = XEXP (x, 1); | |
87943377 | 2309 | int large_constant_p = ! satisfies_constraint_Ks7 (op2); |
9e6a0967 | 2310 | |
8deb3959 | 2311 | if (rclass == PREGS || rclass == PREGS_CLOBBERED) |
9e6a0967 | 2312 | return NO_REGS; |
2313 | /* If destination is a DREG, we can do this without a scratch register | |
2314 | if the constant is valid for an add instruction. */ | |
8deb3959 | 2315 | if ((rclass == DREGS || rclass == DPREGS) |
88eaee2d | 2316 | && ! large_constant_p) |
2317 | return NO_REGS; | |
9e6a0967 | 2318 | /* Reloading to anything other than a DREG? Use a PREG scratch |
2319 | register. */ | |
88eaee2d | 2320 | sri->icode = CODE_FOR_reload_insi; |
2321 | return NO_REGS; | |
9e6a0967 | 2322 | } |
2323 | ||
2324 | /* Data can usually be moved freely between registers of most classes. | |
2325 | AREGS are an exception; they can only move to or from another register | |
2326 | in AREGS or one in DREGS. They can also be assigned the constant 0. */ | |
9422b03b | 2327 | if (x_class == AREGS || x_class == EVEN_AREGS || x_class == ODD_AREGS) |
8deb3959 | 2328 | return (rclass == DREGS || rclass == AREGS || rclass == EVEN_AREGS |
2329 | || rclass == ODD_AREGS | |
9422b03b | 2330 | ? NO_REGS : DREGS); |
9e6a0967 | 2331 | |
8deb3959 | 2332 | if (rclass == AREGS || rclass == EVEN_AREGS || rclass == ODD_AREGS) |
9e6a0967 | 2333 | { |
e99611da | 2334 | if (code == MEM) |
2335 | { | |
2336 | sri->icode = in_p ? CODE_FOR_reload_inpdi : CODE_FOR_reload_outpdi; | |
2337 | return NO_REGS; | |
2338 | } | |
2339 | ||
9e6a0967 | 2340 | if (x != const0_rtx && x_class != DREGS) |
e99611da | 2341 | { |
2342 | return DREGS; | |
2343 | } | |
9e6a0967 | 2344 | else |
2345 | return NO_REGS; | |
2346 | } | |
2347 | ||
2348 | /* CCREGS can only be moved from/to DREGS. */ | |
8deb3959 | 2349 | if (rclass == CCREGS && x_class != DREGS) |
9e6a0967 | 2350 | return DREGS; |
8deb3959 | 2351 | if (x_class == CCREGS && rclass != DREGS) |
9e6a0967 | 2352 | return DREGS; |
622e3203 | 2353 | |
9e6a0967 | 2354 | /* All registers other than AREGS can load arbitrary constants. The only |
2355 | case that remains is MEM. */ | |
2356 | if (code == MEM) | |
8deb3959 | 2357 | if (! reg_class_subset_p (rclass, default_class)) |
9e6a0967 | 2358 | return default_class; |
e99611da | 2359 | |
9e6a0967 | 2360 | return NO_REGS; |
2361 | } | |
9e6a0967 | 2362 | \f |
f2a5d439 | 2363 | /* Implement TARGET_HANDLE_OPTION. */ |
2364 | ||
2365 | static bool | |
2366 | bfin_handle_option (size_t code, const char *arg, int value) | |
2367 | { | |
2368 | switch (code) | |
2369 | { | |
2370 | case OPT_mshared_library_id_: | |
2371 | if (value > MAX_LIBRARY_ID) | |
2372 | error ("-mshared-library-id=%s is not between 0 and %d", | |
2373 | arg, MAX_LIBRARY_ID); | |
354bd282 | 2374 | bfin_lib_id_given = 1; |
f2a5d439 | 2375 | return true; |
2376 | ||
c9ddd413 | 2377 | case OPT_mcpu_: |
709b2de5 | 2378 | { |
2379 | const char *p, *q; | |
2380 | int i; | |
2381 | ||
2382 | i = 0; | |
2383 | while ((p = bfin_cpus[i].name) != NULL) | |
2384 | { | |
2385 | if (strncmp (arg, p, strlen (p)) == 0) | |
2386 | break; | |
2387 | i++; | |
2388 | } | |
2389 | ||
2390 | if (p == NULL) | |
2391 | { | |
2392 | error ("-mcpu=%s is not valid", arg); | |
2393 | return false; | |
2394 | } | |
2395 | ||
2396 | bfin_cpu_type = bfin_cpus[i].type; | |
2397 | ||
2398 | q = arg + strlen (p); | |
2399 | ||
2400 | if (*q == '\0') | |
2401 | { | |
2402 | bfin_si_revision = bfin_cpus[i].si_revision; | |
2403 | bfin_workarounds |= bfin_cpus[i].workarounds; | |
2404 | } | |
2405 | else if (strcmp (q, "-none") == 0) | |
2406 | bfin_si_revision = -1; | |
2407 | else if (strcmp (q, "-any") == 0) | |
2408 | { | |
2409 | bfin_si_revision = 0xffff; | |
2410 | while (bfin_cpus[i].type == bfin_cpu_type) | |
2411 | { | |
2412 | bfin_workarounds |= bfin_cpus[i].workarounds; | |
2413 | i++; | |
2414 | } | |
2415 | } | |
2416 | else | |
2417 | { | |
2418 | unsigned int si_major, si_minor; | |
2419 | int rev_len, n; | |
2420 | ||
2421 | rev_len = strlen (q); | |
2422 | ||
2423 | if (sscanf (q, "-%u.%u%n", &si_major, &si_minor, &n) != 2 | |
2424 | || n != rev_len | |
2425 | || si_major > 0xff || si_minor > 0xff) | |
2426 | { | |
2427 | invalid_silicon_revision: | |
2428 | error ("-mcpu=%s has invalid silicon revision", arg); | |
2429 | return false; | |
2430 | } | |
2431 | ||
2432 | bfin_si_revision = (si_major << 8) | si_minor; | |
2433 | ||
2434 | while (bfin_cpus[i].type == bfin_cpu_type | |
2435 | && bfin_cpus[i].si_revision != bfin_si_revision) | |
2436 | i++; | |
2437 | ||
2438 | if (bfin_cpus[i].type != bfin_cpu_type) | |
2439 | goto invalid_silicon_revision; | |
2440 | ||
2441 | bfin_workarounds |= bfin_cpus[i].workarounds; | |
2442 | } | |
2443 | ||
709b2de5 | 2444 | return true; |
2445 | } | |
c9ddd413 | 2446 | |
f2a5d439 | 2447 | default: |
2448 | return true; | |
2449 | } | |
2450 | } | |
2451 | ||
3c1905a4 | 2452 | static struct machine_function * |
2453 | bfin_init_machine_status (void) | |
2454 | { | |
2455 | struct machine_function *f; | |
2456 | ||
225ab426 | 2457 | f = GGC_CNEW (struct machine_function); |
3c1905a4 | 2458 | |
2459 | return f; | |
2460 | } | |
2461 | ||
9e6a0967 | 2462 | /* Implement the macro OVERRIDE_OPTIONS. */ |
2463 | ||
2464 | void | |
2465 | override_options (void) | |
2466 | { | |
cfef164f | 2467 | /* If processor type is not specified, enable all workarounds. */ |
2468 | if (bfin_cpu_type == BFIN_CPU_UNKNOWN) | |
2469 | { | |
2470 | int i; | |
2471 | ||
2472 | for (i = 0; bfin_cpus[i].name != NULL; i++) | |
2473 | bfin_workarounds |= bfin_cpus[i].workarounds; | |
2474 | ||
2475 | bfin_si_revision = 0xffff; | |
2476 | } | |
2477 | ||
709b2de5 | 2478 | if (bfin_csync_anomaly == 1) |
2479 | bfin_workarounds |= WA_SPECULATIVE_SYNCS; | |
2480 | else if (bfin_csync_anomaly == 0) | |
2481 | bfin_workarounds &= ~WA_SPECULATIVE_SYNCS; | |
2482 | ||
2483 | if (bfin_specld_anomaly == 1) | |
2484 | bfin_workarounds |= WA_SPECULATIVE_LOADS; | |
2485 | else if (bfin_specld_anomaly == 0) | |
2486 | bfin_workarounds &= ~WA_SPECULATIVE_LOADS; | |
2487 | ||
9e6a0967 | 2488 | if (TARGET_OMIT_LEAF_FRAME_POINTER) |
2489 | flag_omit_frame_pointer = 1; | |
2490 | ||
2491 | /* Library identification */ | |
f2a5d439 | 2492 | if (bfin_lib_id_given && ! TARGET_ID_SHARED_LIBRARY) |
2493 | error ("-mshared-library-id= specified without -mid-shared-library"); | |
9e6a0967 | 2494 | |
6295e560 | 2495 | if (stack_limit_rtx && TARGET_STACK_CHECK_L1) |
2496 | error ("Can't use multiple stack checking methods together."); | |
2497 | ||
55be0e32 | 2498 | if (TARGET_ID_SHARED_LIBRARY && TARGET_FDPIC) |
6295e560 | 2499 | error ("ID shared libraries and FD-PIC mode can't be used together."); |
55be0e32 | 2500 | |
40831b00 | 2501 | /* Don't allow the user to specify -mid-shared-library and -msep-data |
2502 | together, as it makes little sense from a user's point of view... */ | |
2503 | if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY) | |
2504 | error ("cannot specify both -msep-data and -mid-shared-library"); | |
2505 | /* ... internally, however, it's nearly the same. */ | |
2506 | if (TARGET_SEP_DATA) | |
2507 | target_flags |= MASK_ID_SHARED_LIBRARY | MASK_LEAF_ID_SHARED_LIBRARY; | |
2508 | ||
ced0033c | 2509 | if (TARGET_ID_SHARED_LIBRARY && flag_pic == 0) |
2510 | flag_pic = 1; | |
2511 | ||
55be0e32 | 2512 | /* There is no single unaligned SI op for PIC code. Sometimes we |
2513 | need to use ".4byte" and sometimes we need to use ".picptr". | |
2514 | See bfin_assemble_integer for details. */ | |
2515 | if (TARGET_FDPIC) | |
2516 | targetm.asm_out.unaligned_op.si = 0; | |
2517 | ||
2518 | /* Silently turn off flag_pic if not doing FDPIC or ID shared libraries, | |
2519 | since we don't support it and it'll just break. */ | |
2520 | if (flag_pic && !TARGET_FDPIC && !TARGET_ID_SHARED_LIBRARY) | |
2521 | flag_pic = 0; | |
2522 | ||
cfef164f | 2523 | if (TARGET_MULTICORE && bfin_cpu_type != BFIN_CPU_BF561) |
2524 | error ("-mmulticore can only be used with BF561"); | |
2525 | ||
2526 | if (TARGET_COREA && !TARGET_MULTICORE) | |
2527 | error ("-mcorea should be used with -mmulticore"); | |
2528 | ||
2529 | if (TARGET_COREB && !TARGET_MULTICORE) | |
2530 | error ("-mcoreb should be used with -mmulticore"); | |
2531 | ||
2532 | if (TARGET_COREA && TARGET_COREB) | |
2533 | error ("-mcorea and -mcoreb can't be used together"); | |
2534 | ||
9e6a0967 | 2535 | flag_schedule_insns = 0; |
3c1905a4 | 2536 | |
48df5a7f | 2537 | /* Passes after sched2 can break the helpful TImode annotations that |
2538 | haifa-sched puts on every insn. Just do scheduling in reorg. */ | |
2539 | bfin_flag_schedule_insns2 = flag_schedule_insns_after_reload; | |
2540 | flag_schedule_insns_after_reload = 0; | |
2541 | ||
3c1905a4 | 2542 | init_machine_status = bfin_init_machine_status; |
9e6a0967 | 2543 | } |
2544 | ||
b03ddc8f | 2545 | /* Return the destination address of BRANCH. |
2546 | We need to use this instead of get_attr_length, because the | |
2547 | cbranch_with_nops pattern conservatively sets its length to 6, and | |
2548 | we still prefer to use shorter sequences. */ | |
9e6a0967 | 2549 | |
2550 | static int | |
2551 | branch_dest (rtx branch) | |
2552 | { | |
2553 | rtx dest; | |
2554 | int dest_uid; | |
2555 | rtx pat = PATTERN (branch); | |
2556 | if (GET_CODE (pat) == PARALLEL) | |
2557 | pat = XVECEXP (pat, 0, 0); | |
2558 | dest = SET_SRC (pat); | |
2559 | if (GET_CODE (dest) == IF_THEN_ELSE) | |
2560 | dest = XEXP (dest, 1); | |
2561 | dest = XEXP (dest, 0); | |
2562 | dest_uid = INSN_UID (dest); | |
2563 | return INSN_ADDRESSES (dest_uid); | |
2564 | } | |
2565 | ||
2566 | /* Return nonzero if INSN is annotated with a REG_BR_PROB note that indicates | |
2567 | it's a branch that's predicted taken. */ | |
2568 | ||
2569 | static int | |
2570 | cbranch_predicted_taken_p (rtx insn) | |
2571 | { | |
2572 | rtx x = find_reg_note (insn, REG_BR_PROB, 0); | |
2573 | ||
2574 | if (x) | |
2575 | { | |
2576 | int pred_val = INTVAL (XEXP (x, 0)); | |
2577 | ||
2578 | return pred_val >= REG_BR_PROB_BASE / 2; | |
2579 | } | |
2580 | ||
2581 | return 0; | |
2582 | } | |
2583 | ||
2584 | /* Templates for use by asm_conditional_branch. */ | |
2585 | ||
2586 | static const char *ccbranch_templates[][3] = { | |
2587 | { "if !cc jump %3;", "if cc jump 4 (bp); jump.s %3;", "if cc jump 6 (bp); jump.l %3;" }, | |
2588 | { "if cc jump %3;", "if !cc jump 4 (bp); jump.s %3;", "if !cc jump 6 (bp); jump.l %3;" }, | |
2589 | { "if !cc jump %3 (bp);", "if cc jump 4; jump.s %3;", "if cc jump 6; jump.l %3;" }, | |
2590 | { "if cc jump %3 (bp);", "if !cc jump 4; jump.s %3;", "if !cc jump 6; jump.l %3;" }, | |
2591 | }; | |
2592 | ||
2593 | /* Output INSN, which is a conditional branch instruction with operands | |
2594 | OPERANDS. | |
2595 | ||
2596 | We deal with the various forms of conditional branches that can be generated | |
2597 | by bfin_reorg to prevent the hardware from doing speculative loads, by | |
2598 | - emitting a sufficient number of nops, if N_NOPS is nonzero, or | |
2599 | - always emitting the branch as predicted taken, if PREDICT_TAKEN is true. | |
2600 | Either of these is only necessary if the branch is short, otherwise the | |
2601 | template we use ends in an unconditional jump which flushes the pipeline | |
2602 | anyway. */ | |
2603 | ||
2604 | void | |
2605 | asm_conditional_branch (rtx insn, rtx *operands, int n_nops, int predict_taken) | |
2606 | { | |
2607 | int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn)); | |
2608 | /* Note : offset for instructions like if cc jmp; jump.[sl] offset | |
2609 | is to be taken from start of if cc rather than jump. | |
2610 | Range for jump.s is (-4094, 4096) instead of (-4096, 4094) | |
2611 | */ | |
2612 | int len = (offset >= -1024 && offset <= 1022 ? 0 | |
2613 | : offset >= -4094 && offset <= 4096 ? 1 | |
2614 | : 2); | |
2615 | int bp = predict_taken && len == 0 ? 1 : cbranch_predicted_taken_p (insn); | |
2616 | int idx = (bp << 1) | (GET_CODE (operands[0]) == EQ ? BRF : BRT); | |
2617 | output_asm_insn (ccbranch_templates[idx][len], operands); | |
2115ae11 | 2618 | gcc_assert (n_nops == 0 || !bp); |
9e6a0967 | 2619 | if (len == 0) |
2620 | while (n_nops-- > 0) | |
2621 | output_asm_insn ("nop;", NULL); | |
2622 | } | |
2623 | ||
2624 | /* Emit rtl for a comparison operation CMP in mode MODE. Operands have been | |
2625 | stored in bfin_compare_op0 and bfin_compare_op1 already. */ | |
2626 | ||
2627 | rtx | |
2628 | bfin_gen_compare (rtx cmp, enum machine_mode mode ATTRIBUTE_UNUSED) | |
2629 | { | |
2630 | enum rtx_code code1, code2; | |
2631 | rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1; | |
2632 | rtx tem = bfin_cc_rtx; | |
2633 | enum rtx_code code = GET_CODE (cmp); | |
2634 | ||
2635 | /* If we have a BImode input, then we already have a compare result, and | |
2636 | do not need to emit another comparison. */ | |
2637 | if (GET_MODE (op0) == BImode) | |
2638 | { | |
2115ae11 | 2639 | gcc_assert ((code == NE || code == EQ) && op1 == const0_rtx); |
2640 | tem = op0, code2 = code; | |
9e6a0967 | 2641 | } |
2642 | else | |
2643 | { | |
2644 | switch (code) { | |
2645 | /* bfin has these conditions */ | |
2646 | case EQ: | |
2647 | case LT: | |
2648 | case LE: | |
2649 | case LEU: | |
2650 | case LTU: | |
2651 | code1 = code; | |
2652 | code2 = NE; | |
2653 | break; | |
2654 | default: | |
2655 | code1 = reverse_condition (code); | |
2656 | code2 = EQ; | |
2657 | break; | |
2658 | } | |
2659 | emit_insn (gen_rtx_SET (BImode, tem, | |
2660 | gen_rtx_fmt_ee (code1, BImode, op0, op1))); | |
2661 | } | |
2662 | ||
2663 | return gen_rtx_fmt_ee (code2, BImode, tem, CONST0_RTX (BImode)); | |
2664 | } | |
2665 | \f | |
2666 | /* Return nonzero iff C has exactly one bit set if it is interpreted | |
905ea169 | 2667 | as a 32-bit constant. */ |
9e6a0967 | 2668 | |
2669 | int | |
2670 | log2constp (unsigned HOST_WIDE_INT c) | |
2671 | { | |
2672 | c &= 0xFFFFFFFF; | |
2673 | return c != 0 && (c & (c-1)) == 0; | |
2674 | } | |
2675 | ||
2676 | /* Returns the number of consecutive least significant zeros in the binary | |
2677 | representation of *V. | |
2678 | We modify *V to contain the original value arithmetically shifted right by | |
2679 | the number of zeroes. */ | |
2680 | ||
2681 | static int | |
2682 | shiftr_zero (HOST_WIDE_INT *v) | |
2683 | { | |
2684 | unsigned HOST_WIDE_INT tmp = *v; | |
2685 | unsigned HOST_WIDE_INT sgn; | |
2686 | int n = 0; | |
2687 | ||
2688 | if (tmp == 0) | |
2689 | return 0; | |
2690 | ||
2691 | sgn = tmp & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)); | |
2692 | while ((tmp & 0x1) == 0 && n <= 32) | |
2693 | { | |
2694 | tmp = (tmp >> 1) | sgn; | |
2695 | n++; | |
2696 | } | |
2697 | *v = tmp; | |
2698 | return n; | |
2699 | } | |
2700 | ||
2701 | /* After reload, split the load of an immediate constant. OPERANDS are the | |
2702 | operands of the movsi_insn pattern which we are splitting. We return | |
2703 | nonzero if we emitted a sequence to load the constant, zero if we emitted | |
2704 | nothing because we want to use the splitter's default sequence. */ | |
2705 | ||
2706 | int | |
2707 | split_load_immediate (rtx operands[]) | |
2708 | { | |
2709 | HOST_WIDE_INT val = INTVAL (operands[1]); | |
2710 | HOST_WIDE_INT tmp; | |
2711 | HOST_WIDE_INT shifted = val; | |
2712 | HOST_WIDE_INT shifted_compl = ~val; | |
2713 | int num_zero = shiftr_zero (&shifted); | |
2714 | int num_compl_zero = shiftr_zero (&shifted_compl); | |
2715 | unsigned int regno = REGNO (operands[0]); | |
9e6a0967 | 2716 | |
2717 | /* This case takes care of single-bit set/clear constants, which we could | |
2718 | also implement with BITSET/BITCLR. */ | |
2719 | if (num_zero | |
2720 | && shifted >= -32768 && shifted < 65536 | |
2721 | && (D_REGNO_P (regno) | |
2722 | || (regno >= REG_P0 && regno <= REG_P7 && num_zero <= 2))) | |
2723 | { | |
2724 | emit_insn (gen_movsi (operands[0], GEN_INT (shifted))); | |
2725 | emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (num_zero))); | |
2726 | return 1; | |
2727 | } | |
2728 | ||
2729 | tmp = val & 0xFFFF; | |
2730 | tmp |= -(tmp & 0x8000); | |
2731 | ||
2732 | /* If high word has one bit set or clear, try to use a bit operation. */ | |
2733 | if (D_REGNO_P (regno)) | |
2734 | { | |
2735 | if (log2constp (val & 0xFFFF0000)) | |
2736 | { | |
2737 | emit_insn (gen_movsi (operands[0], GEN_INT (val & 0xFFFF))); | |
2738 | emit_insn (gen_iorsi3 (operands[0], operands[0], GEN_INT (val & 0xFFFF0000))); | |
2739 | return 1; | |
2740 | } | |
2741 | else if (log2constp (val | 0xFFFF) && (val & 0x8000) != 0) | |
2742 | { | |
2743 | emit_insn (gen_movsi (operands[0], GEN_INT (tmp))); | |
2744 | emit_insn (gen_andsi3 (operands[0], operands[0], GEN_INT (val | 0xFFFF))); | |
2745 | } | |
2746 | } | |
2747 | ||
2748 | if (D_REGNO_P (regno)) | |
2749 | { | |
87943377 | 2750 | if (tmp >= -64 && tmp <= 63) |
9e6a0967 | 2751 | { |
2752 | emit_insn (gen_movsi (operands[0], GEN_INT (tmp))); | |
2753 | emit_insn (gen_movstricthi_high (operands[0], GEN_INT (val & -65536))); | |
2754 | return 1; | |
2755 | } | |
2756 | ||
2757 | if ((val & 0xFFFF0000) == 0) | |
2758 | { | |
2759 | emit_insn (gen_movsi (operands[0], const0_rtx)); | |
2760 | emit_insn (gen_movsi_low (operands[0], operands[0], operands[1])); | |
2761 | return 1; | |
2762 | } | |
2763 | ||
2764 | if ((val & 0xFFFF0000) == 0xFFFF0000) | |
2765 | { | |
2766 | emit_insn (gen_movsi (operands[0], constm1_rtx)); | |
2767 | emit_insn (gen_movsi_low (operands[0], operands[0], operands[1])); | |
2768 | return 1; | |
2769 | } | |
2770 | } | |
2771 | ||
2772 | /* Need DREGs for the remaining case. */ | |
2773 | if (regno > REG_R7) | |
2774 | return 0; | |
2775 | ||
2776 | if (optimize_size | |
87943377 | 2777 | && num_compl_zero && shifted_compl >= -64 && shifted_compl <= 63) |
9e6a0967 | 2778 | { |
2779 | /* If optimizing for size, generate a sequence that has more instructions | |
2780 | but is shorter. */ | |
2781 | emit_insn (gen_movsi (operands[0], GEN_INT (shifted_compl))); | |
2782 | emit_insn (gen_ashlsi3 (operands[0], operands[0], | |
2783 | GEN_INT (num_compl_zero))); | |
2784 | emit_insn (gen_one_cmplsi2 (operands[0], operands[0])); | |
2785 | return 1; | |
2786 | } | |
2787 | return 0; | |
2788 | } | |
2789 | \f | |
2790 | /* Return true if the legitimate memory address for a memory operand of mode | |
2791 | MODE. Return false if not. */ | |
2792 | ||
2793 | static bool | |
2794 | bfin_valid_add (enum machine_mode mode, HOST_WIDE_INT value) | |
2795 | { | |
2796 | unsigned HOST_WIDE_INT v = value > 0 ? value : -value; | |
2797 | int sz = GET_MODE_SIZE (mode); | |
2798 | int shift = sz == 1 ? 0 : sz == 2 ? 1 : 2; | |
2799 | /* The usual offsettable_memref machinery doesn't work so well for this | |
2800 | port, so we deal with the problem here. */ | |
351ae60b | 2801 | if (value > 0 && sz == 8) |
2802 | v += 4; | |
2803 | return (v & ~(0x7fff << shift)) == 0; | |
9e6a0967 | 2804 | } |
2805 | ||
2806 | static bool | |
00cb30dc | 2807 | bfin_valid_reg_p (unsigned int regno, int strict, enum machine_mode mode, |
2808 | enum rtx_code outer_code) | |
9e6a0967 | 2809 | { |
00cb30dc | 2810 | if (strict) |
2811 | return REGNO_OK_FOR_BASE_STRICT_P (regno, mode, outer_code, SCRATCH); | |
2812 | else | |
2813 | return REGNO_OK_FOR_BASE_NONSTRICT_P (regno, mode, outer_code, SCRATCH); | |
9e6a0967 | 2814 | } |
2815 | ||
2816 | bool | |
2817 | bfin_legitimate_address_p (enum machine_mode mode, rtx x, int strict) | |
2818 | { | |
2819 | switch (GET_CODE (x)) { | |
2820 | case REG: | |
00cb30dc | 2821 | if (bfin_valid_reg_p (REGNO (x), strict, mode, MEM)) |
9e6a0967 | 2822 | return true; |
2823 | break; | |
2824 | case PLUS: | |
2825 | if (REG_P (XEXP (x, 0)) | |
00cb30dc | 2826 | && bfin_valid_reg_p (REGNO (XEXP (x, 0)), strict, mode, PLUS) |
8f5efc80 | 2827 | && ((GET_CODE (XEXP (x, 1)) == UNSPEC && mode == SImode) |
9e6a0967 | 2828 | || (GET_CODE (XEXP (x, 1)) == CONST_INT |
2829 | && bfin_valid_add (mode, INTVAL (XEXP (x, 1)))))) | |
2830 | return true; | |
2831 | break; | |
2832 | case POST_INC: | |
2833 | case POST_DEC: | |
2834 | if (LEGITIMATE_MODE_FOR_AUTOINC_P (mode) | |
2835 | && REG_P (XEXP (x, 0)) | |
00cb30dc | 2836 | && bfin_valid_reg_p (REGNO (XEXP (x, 0)), strict, mode, POST_INC)) |
9e6a0967 | 2837 | return true; |
2838 | case PRE_DEC: | |
2839 | if (LEGITIMATE_MODE_FOR_AUTOINC_P (mode) | |
2840 | && XEXP (x, 0) == stack_pointer_rtx | |
2841 | && REG_P (XEXP (x, 0)) | |
00cb30dc | 2842 | && bfin_valid_reg_p (REGNO (XEXP (x, 0)), strict, mode, PRE_DEC)) |
9e6a0967 | 2843 | return true; |
2844 | break; | |
2845 | default: | |
2846 | break; | |
2847 | } | |
2848 | return false; | |
2849 | } | |
2850 | ||
cf63c743 | 2851 | /* Decide whether we can force certain constants to memory. If we |
2852 | decide we can't, the caller should be able to cope with it in | |
2853 | another way. */ | |
2854 | ||
2855 | static bool | |
2856 | bfin_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED) | |
2857 | { | |
2858 | /* We have only one class of non-legitimate constants, and our movsi | |
2859 | expander knows how to handle them. Dropping these constants into the | |
2860 | data section would only shift the problem - we'd still get relocs | |
2861 | outside the object, in the data section rather than the text section. */ | |
2862 | return true; | |
2863 | } | |
2864 | ||
2865 | /* Ensure that for any constant of the form symbol + offset, the offset | |
2866 | remains within the object. Any other constants are ok. | |
2867 | This ensures that flat binaries never have to deal with relocations | |
2868 | crossing section boundaries. */ | |
2869 | ||
2870 | bool | |
2871 | bfin_legitimate_constant_p (rtx x) | |
2872 | { | |
2873 | rtx sym; | |
2874 | HOST_WIDE_INT offset; | |
2875 | ||
2876 | if (GET_CODE (x) != CONST) | |
2877 | return true; | |
2878 | ||
2879 | x = XEXP (x, 0); | |
2880 | gcc_assert (GET_CODE (x) == PLUS); | |
2881 | ||
2882 | sym = XEXP (x, 0); | |
2883 | x = XEXP (x, 1); | |
2884 | if (GET_CODE (sym) != SYMBOL_REF | |
2885 | || GET_CODE (x) != CONST_INT) | |
2886 | return true; | |
2887 | offset = INTVAL (x); | |
2888 | ||
2889 | if (SYMBOL_REF_DECL (sym) == 0) | |
2890 | return true; | |
2891 | if (offset < 0 | |
2892 | || offset >= int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (sym)))) | |
2893 | return false; | |
2894 | ||
2895 | return true; | |
2896 | } | |
2897 | ||
9e6a0967 | 2898 | static bool |
f529eb25 | 2899 | bfin_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed) |
9e6a0967 | 2900 | { |
2901 | int cost2 = COSTS_N_INSNS (1); | |
f84f5dae | 2902 | rtx op0, op1; |
9e6a0967 | 2903 | |
2904 | switch (code) | |
2905 | { | |
2906 | case CONST_INT: | |
2907 | if (outer_code == SET || outer_code == PLUS) | |
87943377 | 2908 | *total = satisfies_constraint_Ks7 (x) ? 0 : cost2; |
9e6a0967 | 2909 | else if (outer_code == AND) |
2910 | *total = log2constp (~INTVAL (x)) ? 0 : cost2; | |
2911 | else if (outer_code == LE || outer_code == LT || outer_code == EQ) | |
2912 | *total = (INTVAL (x) >= -4 && INTVAL (x) <= 3) ? 0 : cost2; | |
2913 | else if (outer_code == LEU || outer_code == LTU) | |
2914 | *total = (INTVAL (x) >= 0 && INTVAL (x) <= 7) ? 0 : cost2; | |
2915 | else if (outer_code == MULT) | |
2916 | *total = (INTVAL (x) == 2 || INTVAL (x) == 4) ? 0 : cost2; | |
2917 | else if (outer_code == ASHIFT && (INTVAL (x) == 1 || INTVAL (x) == 2)) | |
2918 | *total = 0; | |
2919 | else if (outer_code == ASHIFT || outer_code == ASHIFTRT | |
2920 | || outer_code == LSHIFTRT) | |
2921 | *total = (INTVAL (x) >= 0 && INTVAL (x) <= 31) ? 0 : cost2; | |
2922 | else if (outer_code == IOR || outer_code == XOR) | |
2923 | *total = (INTVAL (x) & (INTVAL (x) - 1)) == 0 ? 0 : cost2; | |
2924 | else | |
2925 | *total = cost2; | |
2926 | return true; | |
2927 | ||
2928 | case CONST: | |
2929 | case LABEL_REF: | |
2930 | case SYMBOL_REF: | |
2931 | case CONST_DOUBLE: | |
2932 | *total = COSTS_N_INSNS (2); | |
2933 | return true; | |
2934 | ||
2935 | case PLUS: | |
f84f5dae | 2936 | op0 = XEXP (x, 0); |
2937 | op1 = XEXP (x, 1); | |
2938 | if (GET_MODE (x) == SImode) | |
9e6a0967 | 2939 | { |
f84f5dae | 2940 | if (GET_CODE (op0) == MULT |
2941 | && GET_CODE (XEXP (op0, 1)) == CONST_INT) | |
9e6a0967 | 2942 | { |
f84f5dae | 2943 | HOST_WIDE_INT val = INTVAL (XEXP (op0, 1)); |
9e6a0967 | 2944 | if (val == 2 || val == 4) |
2945 | { | |
2946 | *total = cost2; | |
f529eb25 | 2947 | *total += rtx_cost (XEXP (op0, 0), outer_code, speed); |
2948 | *total += rtx_cost (op1, outer_code, speed); | |
9e6a0967 | 2949 | return true; |
2950 | } | |
2951 | } | |
f84f5dae | 2952 | *total = cost2; |
2953 | if (GET_CODE (op0) != REG | |
2954 | && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG)) | |
f529eb25 | 2955 | *total += rtx_cost (op0, SET, speed); |
f84f5dae | 2956 | #if 0 /* We'd like to do this for accuracy, but it biases the loop optimizer |
2957 | towards creating too many induction variables. */ | |
2958 | if (!reg_or_7bit_operand (op1, SImode)) | |
f529eb25 | 2959 | *total += rtx_cost (op1, SET, speed); |
f84f5dae | 2960 | #endif |
9e6a0967 | 2961 | } |
f84f5dae | 2962 | else if (GET_MODE (x) == DImode) |
2963 | { | |
2964 | *total = 6 * cost2; | |
2965 | if (GET_CODE (op1) != CONST_INT | |
87943377 | 2966 | || !satisfies_constraint_Ks7 (op1)) |
f529eb25 | 2967 | *total += rtx_cost (op1, PLUS, speed); |
f84f5dae | 2968 | if (GET_CODE (op0) != REG |
2969 | && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG)) | |
f529eb25 | 2970 | *total += rtx_cost (op0, PLUS, speed); |
f84f5dae | 2971 | } |
2972 | return true; | |
9e6a0967 | 2973 | |
2974 | case MINUS: | |
f84f5dae | 2975 | if (GET_MODE (x) == DImode) |
2976 | *total = 6 * cost2; | |
2977 | else | |
2978 | *total = cost2; | |
2979 | return true; | |
2980 | ||
9e6a0967 | 2981 | case ASHIFT: |
2982 | case ASHIFTRT: | |
2983 | case LSHIFTRT: | |
2984 | if (GET_MODE (x) == DImode) | |
2985 | *total = 6 * cost2; | |
f84f5dae | 2986 | else |
2987 | *total = cost2; | |
2988 | ||
2989 | op0 = XEXP (x, 0); | |
2990 | op1 = XEXP (x, 1); | |
2991 | if (GET_CODE (op0) != REG | |
2992 | && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG)) | |
f529eb25 | 2993 | *total += rtx_cost (op0, code, speed); |
f84f5dae | 2994 | |
2995 | return true; | |
9e6a0967 | 2996 | |
9e6a0967 | 2997 | case IOR: |
f84f5dae | 2998 | case AND: |
9e6a0967 | 2999 | case XOR: |
f84f5dae | 3000 | op0 = XEXP (x, 0); |
3001 | op1 = XEXP (x, 1); | |
3002 | ||
3003 | /* Handle special cases of IOR: rotates, ALIGN insns, movstricthi_high. */ | |
3004 | if (code == IOR) | |
3005 | { | |
3006 | if ((GET_CODE (op0) == LSHIFTRT && GET_CODE (op1) == ASHIFT) | |
3007 | || (GET_CODE (op0) == ASHIFT && GET_CODE (op1) == ZERO_EXTEND) | |
3008 | || (GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT) | |
3009 | || (GET_CODE (op0) == AND && GET_CODE (op1) == CONST_INT)) | |
3010 | { | |
3011 | *total = cost2; | |
3012 | return true; | |
3013 | } | |
3014 | } | |
3015 | ||
3016 | if (GET_CODE (op0) != REG | |
3017 | && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG)) | |
f529eb25 | 3018 | *total += rtx_cost (op0, code, speed); |
f84f5dae | 3019 | |
9e6a0967 | 3020 | if (GET_MODE (x) == DImode) |
f84f5dae | 3021 | { |
3022 | *total = 2 * cost2; | |
3023 | return true; | |
3024 | } | |
3025 | *total = cost2; | |
3026 | if (GET_MODE (x) != SImode) | |
3027 | return true; | |
3028 | ||
3029 | if (code == AND) | |
3030 | { | |
3031 | if (! rhs_andsi3_operand (XEXP (x, 1), SImode)) | |
f529eb25 | 3032 | *total += rtx_cost (XEXP (x, 1), code, speed); |
f84f5dae | 3033 | } |
3034 | else | |
3035 | { | |
3036 | if (! regorlog2_operand (XEXP (x, 1), SImode)) | |
f529eb25 | 3037 | *total += rtx_cost (XEXP (x, 1), code, speed); |
f84f5dae | 3038 | } |
3039 | ||
3040 | return true; | |
3041 | ||
3042 | case ZERO_EXTRACT: | |
3043 | case SIGN_EXTRACT: | |
3044 | if (outer_code == SET | |
3045 | && XEXP (x, 1) == const1_rtx | |
3046 | && GET_CODE (XEXP (x, 2)) == CONST_INT) | |
3047 | { | |
3048 | *total = 2 * cost2; | |
3049 | return true; | |
3050 | } | |
3051 | /* fall through */ | |
3052 | ||
3053 | case SIGN_EXTEND: | |
3054 | case ZERO_EXTEND: | |
3055 | *total = cost2; | |
3056 | return true; | |
9e6a0967 | 3057 | |
3058 | case MULT: | |
f84f5dae | 3059 | { |
3060 | op0 = XEXP (x, 0); | |
3061 | op1 = XEXP (x, 1); | |
3062 | if (GET_CODE (op0) == GET_CODE (op1) | |
3063 | && (GET_CODE (op0) == ZERO_EXTEND | |
3064 | || GET_CODE (op0) == SIGN_EXTEND)) | |
3065 | { | |
3066 | *total = COSTS_N_INSNS (1); | |
3067 | op0 = XEXP (op0, 0); | |
3068 | op1 = XEXP (op1, 0); | |
3069 | } | |
f529eb25 | 3070 | else if (!speed) |
f84f5dae | 3071 | *total = COSTS_N_INSNS (1); |
3072 | else | |
3073 | *total = COSTS_N_INSNS (3); | |
3074 | ||
3075 | if (GET_CODE (op0) != REG | |
3076 | && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG)) | |
f529eb25 | 3077 | *total += rtx_cost (op0, MULT, speed); |
f84f5dae | 3078 | if (GET_CODE (op1) != REG |
3079 | && (GET_CODE (op1) != SUBREG || GET_CODE (SUBREG_REG (op1)) != REG)) | |
f529eb25 | 3080 | *total += rtx_cost (op1, MULT, speed); |
f84f5dae | 3081 | } |
3082 | return true; | |
9e6a0967 | 3083 | |
ff7e43ad | 3084 | case UDIV: |
3085 | case UMOD: | |
3086 | *total = COSTS_N_INSNS (32); | |
3087 | return true; | |
3088 | ||
f9edc33d | 3089 | case VEC_CONCAT: |
3090 | case VEC_SELECT: | |
3091 | if (outer_code == SET) | |
3092 | *total = cost2; | |
3093 | return true; | |
3094 | ||
9e6a0967 | 3095 | default: |
3096 | return false; | |
3097 | } | |
3098 | } | |
9e6a0967 | 3099 | \f |
3100 | /* Used for communication between {push,pop}_multiple_operation (which | |
3101 | we use not only as a predicate) and the corresponding output functions. */ | |
3102 | static int first_preg_to_save, first_dreg_to_save; | |
3103 | ||
3104 | int | |
3105 | push_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
3106 | { | |
3107 | int lastdreg = 8, lastpreg = 6; | |
3108 | int i, group; | |
3109 | ||
3110 | first_preg_to_save = lastpreg; | |
3111 | first_dreg_to_save = lastdreg; | |
3112 | for (i = 1, group = 0; i < XVECLEN (op, 0) - 1; i++) | |
3113 | { | |
3114 | rtx t = XVECEXP (op, 0, i); | |
3115 | rtx src, dest; | |
3116 | int regno; | |
3117 | ||
3118 | if (GET_CODE (t) != SET) | |
3119 | return 0; | |
3120 | ||
3121 | src = SET_SRC (t); | |
3122 | dest = SET_DEST (t); | |
3123 | if (GET_CODE (dest) != MEM || ! REG_P (src)) | |
3124 | return 0; | |
3125 | dest = XEXP (dest, 0); | |
3126 | if (GET_CODE (dest) != PLUS | |
3127 | || ! REG_P (XEXP (dest, 0)) | |
3128 | || REGNO (XEXP (dest, 0)) != REG_SP | |
3129 | || GET_CODE (XEXP (dest, 1)) != CONST_INT | |
3130 | || INTVAL (XEXP (dest, 1)) != -i * 4) | |
3131 | return 0; | |
3132 | ||
3133 | regno = REGNO (src); | |
3134 | if (group == 0) | |
3135 | { | |
3136 | if (D_REGNO_P (regno)) | |
3137 | { | |
3138 | group = 1; | |
3139 | first_dreg_to_save = lastdreg = regno - REG_R0; | |
3140 | } | |
3141 | else if (regno >= REG_P0 && regno <= REG_P7) | |
3142 | { | |
3143 | group = 2; | |
3144 | first_preg_to_save = lastpreg = regno - REG_P0; | |
3145 | } | |
3146 | else | |
3147 | return 0; | |
3148 | ||
3149 | continue; | |
3150 | } | |
3151 | ||
3152 | if (group == 1) | |
3153 | { | |
3154 | if (regno >= REG_P0 && regno <= REG_P7) | |
3155 | { | |
3156 | group = 2; | |
3157 | first_preg_to_save = lastpreg = regno - REG_P0; | |
3158 | } | |
3159 | else if (regno != REG_R0 + lastdreg + 1) | |
3160 | return 0; | |
3161 | else | |
3162 | lastdreg++; | |
3163 | } | |
3164 | else if (group == 2) | |
3165 | { | |
3166 | if (regno != REG_P0 + lastpreg + 1) | |
3167 | return 0; | |
3168 | lastpreg++; | |
3169 | } | |
3170 | } | |
3171 | return 1; | |
3172 | } | |
3173 | ||
3174 | int | |
3175 | pop_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
3176 | { | |
3177 | int lastdreg = 8, lastpreg = 6; | |
3178 | int i, group; | |
3179 | ||
3180 | for (i = 1, group = 0; i < XVECLEN (op, 0); i++) | |
3181 | { | |
3182 | rtx t = XVECEXP (op, 0, i); | |
3183 | rtx src, dest; | |
3184 | int regno; | |
3185 | ||
3186 | if (GET_CODE (t) != SET) | |
3187 | return 0; | |
3188 | ||
3189 | src = SET_SRC (t); | |
3190 | dest = SET_DEST (t); | |
3191 | if (GET_CODE (src) != MEM || ! REG_P (dest)) | |
3192 | return 0; | |
3193 | src = XEXP (src, 0); | |
3194 | ||
3195 | if (i == 1) | |
3196 | { | |
3197 | if (! REG_P (src) || REGNO (src) != REG_SP) | |
3198 | return 0; | |
3199 | } | |
3200 | else if (GET_CODE (src) != PLUS | |
3201 | || ! REG_P (XEXP (src, 0)) | |
3202 | || REGNO (XEXP (src, 0)) != REG_SP | |
3203 | || GET_CODE (XEXP (src, 1)) != CONST_INT | |
3204 | || INTVAL (XEXP (src, 1)) != (i - 1) * 4) | |
3205 | return 0; | |
3206 | ||
3207 | regno = REGNO (dest); | |
3208 | if (group == 0) | |
3209 | { | |
3210 | if (regno == REG_R7) | |
3211 | { | |
3212 | group = 1; | |
3213 | lastdreg = 7; | |
3214 | } | |
3215 | else if (regno != REG_P0 + lastpreg - 1) | |
3216 | return 0; | |
3217 | else | |
3218 | lastpreg--; | |
3219 | } | |
3220 | else if (group == 1) | |
3221 | { | |
3222 | if (regno != REG_R0 + lastdreg - 1) | |
3223 | return 0; | |
3224 | else | |
3225 | lastdreg--; | |
3226 | } | |
3227 | } | |
3228 | first_dreg_to_save = lastdreg; | |
3229 | first_preg_to_save = lastpreg; | |
3230 | return 1; | |
3231 | } | |
3232 | ||
3233 | /* Emit assembly code for one multi-register push described by INSN, with | |
3234 | operands in OPERANDS. */ | |
3235 | ||
3236 | void | |
3237 | output_push_multiple (rtx insn, rtx *operands) | |
3238 | { | |
3239 | char buf[80]; | |
2115ae11 | 3240 | int ok; |
3241 | ||
9e6a0967 | 3242 | /* Validate the insn again, and compute first_[dp]reg_to_save. */ |
2115ae11 | 3243 | ok = push_multiple_operation (PATTERN (insn), VOIDmode); |
3244 | gcc_assert (ok); | |
3245 | ||
9e6a0967 | 3246 | if (first_dreg_to_save == 8) |
3247 | sprintf (buf, "[--sp] = ( p5:%d );\n", first_preg_to_save); | |
3248 | else if (first_preg_to_save == 6) | |
3249 | sprintf (buf, "[--sp] = ( r7:%d );\n", first_dreg_to_save); | |
3250 | else | |
2115ae11 | 3251 | sprintf (buf, "[--sp] = ( r7:%d, p5:%d );\n", |
3252 | first_dreg_to_save, first_preg_to_save); | |
9e6a0967 | 3253 | |
3254 | output_asm_insn (buf, operands); | |
3255 | } | |
3256 | ||
3257 | /* Emit assembly code for one multi-register pop described by INSN, with | |
3258 | operands in OPERANDS. */ | |
3259 | ||
3260 | void | |
3261 | output_pop_multiple (rtx insn, rtx *operands) | |
3262 | { | |
3263 | char buf[80]; | |
2115ae11 | 3264 | int ok; |
3265 | ||
9e6a0967 | 3266 | /* Validate the insn again, and compute first_[dp]reg_to_save. */ |
2115ae11 | 3267 | ok = pop_multiple_operation (PATTERN (insn), VOIDmode); |
3268 | gcc_assert (ok); | |
9e6a0967 | 3269 | |
3270 | if (first_dreg_to_save == 8) | |
3271 | sprintf (buf, "( p5:%d ) = [sp++];\n", first_preg_to_save); | |
3272 | else if (first_preg_to_save == 6) | |
3273 | sprintf (buf, "( r7:%d ) = [sp++];\n", first_dreg_to_save); | |
3274 | else | |
2115ae11 | 3275 | sprintf (buf, "( r7:%d, p5:%d ) = [sp++];\n", |
3276 | first_dreg_to_save, first_preg_to_save); | |
9e6a0967 | 3277 | |
3278 | output_asm_insn (buf, operands); | |
3279 | } | |
3280 | ||
3281 | /* Adjust DST and SRC by OFFSET bytes, and generate one move in mode MODE. */ | |
3282 | ||
3283 | static void | |
a92178b8 | 3284 | single_move_for_movmem (rtx dst, rtx src, enum machine_mode mode, HOST_WIDE_INT offset) |
9e6a0967 | 3285 | { |
3286 | rtx scratch = gen_reg_rtx (mode); | |
3287 | rtx srcmem, dstmem; | |
3288 | ||
3289 | srcmem = adjust_address_nv (src, mode, offset); | |
3290 | dstmem = adjust_address_nv (dst, mode, offset); | |
3291 | emit_move_insn (scratch, srcmem); | |
3292 | emit_move_insn (dstmem, scratch); | |
3293 | } | |
3294 | ||
3295 | /* Expand a string move operation of COUNT_EXP bytes from SRC to DST, with | |
3296 | alignment ALIGN_EXP. Return true if successful, false if we should fall | |
3297 | back on a different method. */ | |
3298 | ||
3299 | bool | |
a92178b8 | 3300 | bfin_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp) |
9e6a0967 | 3301 | { |
3302 | rtx srcreg, destreg, countreg; | |
3303 | HOST_WIDE_INT align = 0; | |
3304 | unsigned HOST_WIDE_INT count = 0; | |
3305 | ||
3306 | if (GET_CODE (align_exp) == CONST_INT) | |
3307 | align = INTVAL (align_exp); | |
3308 | if (GET_CODE (count_exp) == CONST_INT) | |
3309 | { | |
3310 | count = INTVAL (count_exp); | |
3311 | #if 0 | |
3312 | if (!TARGET_INLINE_ALL_STRINGOPS && count > 64) | |
3313 | return false; | |
3314 | #endif | |
3315 | } | |
3316 | ||
3317 | /* If optimizing for size, only do single copies inline. */ | |
3318 | if (optimize_size) | |
3319 | { | |
3320 | if (count == 2 && align < 2) | |
3321 | return false; | |
3322 | if (count == 4 && align < 4) | |
3323 | return false; | |
3324 | if (count != 1 && count != 2 && count != 4) | |
3325 | return false; | |
3326 | } | |
3327 | if (align < 2 && count != 1) | |
3328 | return false; | |
3329 | ||
3330 | destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0)); | |
3331 | if (destreg != XEXP (dst, 0)) | |
3332 | dst = replace_equiv_address_nv (dst, destreg); | |
3333 | srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0)); | |
3334 | if (srcreg != XEXP (src, 0)) | |
3335 | src = replace_equiv_address_nv (src, srcreg); | |
3336 | ||
3337 | if (count != 0 && align >= 2) | |
3338 | { | |
3339 | unsigned HOST_WIDE_INT offset = 0; | |
3340 | ||
3341 | if (align >= 4) | |
3342 | { | |
3343 | if ((count & ~3) == 4) | |
3344 | { | |
a92178b8 | 3345 | single_move_for_movmem (dst, src, SImode, offset); |
9e6a0967 | 3346 | offset = 4; |
3347 | } | |
3348 | else if (count & ~3) | |
3349 | { | |
3350 | HOST_WIDE_INT new_count = ((count >> 2) & 0x3fffffff) - 1; | |
3351 | countreg = copy_to_mode_reg (Pmode, GEN_INT (new_count)); | |
3352 | ||
3353 | emit_insn (gen_rep_movsi (destreg, srcreg, countreg, destreg, srcreg)); | |
3354 | } | |
488493c5 | 3355 | if (count & 2) |
3356 | { | |
a92178b8 | 3357 | single_move_for_movmem (dst, src, HImode, offset); |
488493c5 | 3358 | offset += 2; |
3359 | } | |
9e6a0967 | 3360 | } |
3361 | else | |
3362 | { | |
3363 | if ((count & ~1) == 2) | |
3364 | { | |
a92178b8 | 3365 | single_move_for_movmem (dst, src, HImode, offset); |
9e6a0967 | 3366 | offset = 2; |
3367 | } | |
3368 | else if (count & ~1) | |
3369 | { | |
3370 | HOST_WIDE_INT new_count = ((count >> 1) & 0x7fffffff) - 1; | |
3371 | countreg = copy_to_mode_reg (Pmode, GEN_INT (new_count)); | |
3372 | ||
3373 | emit_insn (gen_rep_movhi (destreg, srcreg, countreg, destreg, srcreg)); | |
3374 | } | |
3375 | } | |
9e6a0967 | 3376 | if (count & 1) |
3377 | { | |
a92178b8 | 3378 | single_move_for_movmem (dst, src, QImode, offset); |
9e6a0967 | 3379 | } |
3380 | return true; | |
3381 | } | |
3382 | return false; | |
3383 | } | |
9e6a0967 | 3384 | \f |
23285403 | 3385 | /* Compute the alignment for a local variable. |
3386 | TYPE is the data type, and ALIGN is the alignment that | |
3387 | the object would ordinarily have. The value of this macro is used | |
3388 | instead of that alignment to align the object. */ | |
3389 | ||
3390 | int | |
3391 | bfin_local_alignment (tree type, int align) | |
3392 | { | |
3393 | /* Increasing alignment for (relatively) big types allows the builtin | |
3394 | memcpy can use 32 bit loads/stores. */ | |
3395 | if (TYPE_SIZE (type) | |
3396 | && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
3397 | && (TREE_INT_CST_LOW (TYPE_SIZE (type)) > 8 | |
3398 | || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 32) | |
3399 | return 32; | |
3400 | return align; | |
3401 | } | |
3402 | \f | |
9aa0222b | 3403 | /* Implement TARGET_SCHED_ISSUE_RATE. */ |
3404 | ||
3405 | static int | |
3406 | bfin_issue_rate (void) | |
3407 | { | |
3408 | return 3; | |
3409 | } | |
3410 | ||
9e6a0967 | 3411 | static int |
3412 | bfin_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) | |
3413 | { | |
3414 | enum attr_type insn_type, dep_insn_type; | |
3415 | int dep_insn_code_number; | |
3416 | ||
3417 | /* Anti and output dependencies have zero cost. */ | |
3418 | if (REG_NOTE_KIND (link) != 0) | |
3419 | return 0; | |
3420 | ||
3421 | dep_insn_code_number = recog_memoized (dep_insn); | |
3422 | ||
3423 | /* If we can't recognize the insns, we can't really do anything. */ | |
3424 | if (dep_insn_code_number < 0 || recog_memoized (insn) < 0) | |
3425 | return cost; | |
3426 | ||
3427 | insn_type = get_attr_type (insn); | |
3428 | dep_insn_type = get_attr_type (dep_insn); | |
3429 | ||
3430 | if (dep_insn_type == TYPE_MOVE || dep_insn_type == TYPE_MCLD) | |
3431 | { | |
3432 | rtx pat = PATTERN (dep_insn); | |
4694534a | 3433 | if (GET_CODE (pat) == PARALLEL) |
3434 | pat = XVECEXP (pat, 0, 0); | |
9e6a0967 | 3435 | rtx dest = SET_DEST (pat); |
3436 | rtx src = SET_SRC (pat); | |
4c359296 | 3437 | if (! ADDRESS_REGNO_P (REGNO (dest)) |
3438 | || ! (MEM_P (src) || D_REGNO_P (REGNO (src)))) | |
9e6a0967 | 3439 | return cost; |
3440 | return cost + (dep_insn_type == TYPE_MOVE ? 4 : 3); | |
3441 | } | |
3442 | ||
3443 | return cost; | |
3444 | } | |
3c1905a4 | 3445 | |
3446 | \f | |
3447 | /* Increment the counter for the number of loop instructions in the | |
3448 | current function. */ | |
3449 | ||
3450 | void | |
3451 | bfin_hardware_loop (void) | |
3452 | { | |
3453 | cfun->machine->has_hardware_loops++; | |
3454 | } | |
3455 | ||
1a4340cd | 3456 | /* Maximum loop nesting depth. */ |
3c1905a4 | 3457 | #define MAX_LOOP_DEPTH 2 |
3458 | ||
1a4340cd | 3459 | /* Maximum size of a loop. */ |
b6cf30ce | 3460 | #define MAX_LOOP_LENGTH 2042 |
3c1905a4 | 3461 | |
917c4036 | 3462 | /* Maximum distance of the LSETUP instruction from the loop start. */ |
3463 | #define MAX_LSETUP_DISTANCE 30 | |
3464 | ||
3c1905a4 | 3465 | /* We need to keep a vector of loops */ |
3466 | typedef struct loop_info *loop_info; | |
3467 | DEF_VEC_P (loop_info); | |
3468 | DEF_VEC_ALLOC_P (loop_info,heap); | |
3469 | ||
3470 | /* Information about a loop we have found (or are in the process of | |
3471 | finding). */ | |
3472 | struct loop_info GTY (()) | |
3473 | { | |
3474 | /* loop number, for dumps */ | |
3475 | int loop_no; | |
3476 | ||
917c4036 | 3477 | /* All edges that jump into and out of the loop. */ |
3478 | VEC(edge,gc) *incoming; | |
3479 | ||
3480 | /* We can handle two cases: all incoming edges have the same destination | |
3481 | block, or all incoming edges have the same source block. These two | |
3482 | members are set to the common source or destination we found, or NULL | |
3483 | if different blocks were found. If both are NULL the loop can't be | |
3484 | optimized. */ | |
3485 | basic_block incoming_src; | |
3486 | basic_block incoming_dest; | |
3c1905a4 | 3487 | |
3488 | /* First block in the loop. This is the one branched to by the loop_end | |
3489 | insn. */ | |
3490 | basic_block head; | |
3491 | ||
3492 | /* Last block in the loop (the one with the loop_end insn). */ | |
3493 | basic_block tail; | |
3494 | ||
3495 | /* The successor block of the loop. This is the one the loop_end insn | |
3496 | falls into. */ | |
3497 | basic_block successor; | |
3498 | ||
3499 | /* The last instruction in the tail. */ | |
3500 | rtx last_insn; | |
3501 | ||
3502 | /* The loop_end insn. */ | |
3503 | rtx loop_end; | |
3504 | ||
3505 | /* The iteration register. */ | |
3506 | rtx iter_reg; | |
3507 | ||
3508 | /* The new initialization insn. */ | |
3509 | rtx init; | |
3510 | ||
3511 | /* The new initialization instruction. */ | |
3512 | rtx loop_init; | |
3513 | ||
3514 | /* The new label placed at the beginning of the loop. */ | |
3515 | rtx start_label; | |
3516 | ||
3517 | /* The new label placed at the end of the loop. */ | |
3518 | rtx end_label; | |
3519 | ||
3520 | /* The length of the loop. */ | |
3521 | int length; | |
3522 | ||
e82f36f5 | 3523 | /* The nesting depth of the loop. */ |
3c1905a4 | 3524 | int depth; |
3525 | ||
e82f36f5 | 3526 | /* Nonzero if we can't optimize this loop. */ |
3527 | int bad; | |
3528 | ||
3c1905a4 | 3529 | /* True if we have visited this loop. */ |
3530 | int visited; | |
3531 | ||
3532 | /* True if this loop body clobbers any of LC0, LT0, or LB0. */ | |
3533 | int clobber_loop0; | |
3534 | ||
3535 | /* True if this loop body clobbers any of LC1, LT1, or LB1. */ | |
3536 | int clobber_loop1; | |
3537 | ||
3538 | /* Next loop in the graph. */ | |
3539 | struct loop_info *next; | |
3540 | ||
3541 | /* Immediate outer loop of this loop. */ | |
3542 | struct loop_info *outer; | |
3543 | ||
e82f36f5 | 3544 | /* Vector of blocks only within the loop, including those within |
3545 | inner loops. */ | |
3c1905a4 | 3546 | VEC (basic_block,heap) *blocks; |
3547 | ||
e82f36f5 | 3548 | /* Same information in a bitmap. */ |
3549 | bitmap block_bitmap; | |
3550 | ||
3c1905a4 | 3551 | /* Vector of inner loops within this loop */ |
3552 | VEC (loop_info,heap) *loops; | |
3553 | }; | |
3554 | ||
3c1905a4 | 3555 | static void |
3556 | bfin_dump_loops (loop_info loops) | |
3557 | { | |
3558 | loop_info loop; | |
3559 | ||
3560 | for (loop = loops; loop; loop = loop->next) | |
3561 | { | |
3562 | loop_info i; | |
3563 | basic_block b; | |
3564 | unsigned ix; | |
3565 | ||
3566 | fprintf (dump_file, ";; loop %d: ", loop->loop_no); | |
e82f36f5 | 3567 | if (loop->bad) |
3568 | fprintf (dump_file, "(bad) "); | |
3c1905a4 | 3569 | fprintf (dump_file, "{head:%d, depth:%d}", loop->head->index, loop->depth); |
3570 | ||
3571 | fprintf (dump_file, " blocks: [ "); | |
3572 | for (ix = 0; VEC_iterate (basic_block, loop->blocks, ix, b); ix++) | |
3573 | fprintf (dump_file, "%d ", b->index); | |
3574 | fprintf (dump_file, "] "); | |
3575 | ||
3576 | fprintf (dump_file, " inner loops: [ "); | |
3577 | for (ix = 0; VEC_iterate (loop_info, loop->loops, ix, i); ix++) | |
3578 | fprintf (dump_file, "%d ", i->loop_no); | |
3579 | fprintf (dump_file, "]\n"); | |
3580 | } | |
3581 | fprintf (dump_file, "\n"); | |
3582 | } | |
3583 | ||
3584 | /* Scan the blocks of LOOP (and its inferiors) looking for basic block | |
3585 | BB. Return true, if we find it. */ | |
3586 | ||
3587 | static bool | |
3588 | bfin_bb_in_loop (loop_info loop, basic_block bb) | |
3589 | { | |
e82f36f5 | 3590 | return bitmap_bit_p (loop->block_bitmap, bb->index); |
3c1905a4 | 3591 | } |
3592 | ||
3593 | /* Scan the blocks of LOOP (and its inferiors) looking for uses of | |
3594 | REG. Return true, if we find any. Don't count the loop's loop_end | |
3595 | insn if it matches LOOP_END. */ | |
3596 | ||
3597 | static bool | |
3598 | bfin_scan_loop (loop_info loop, rtx reg, rtx loop_end) | |
3599 | { | |
3600 | unsigned ix; | |
3c1905a4 | 3601 | basic_block bb; |
3602 | ||
3603 | for (ix = 0; VEC_iterate (basic_block, loop->blocks, ix, bb); ix++) | |
3604 | { | |
3605 | rtx insn; | |
3606 | ||
3607 | for (insn = BB_HEAD (bb); | |
3608 | insn != NEXT_INSN (BB_END (bb)); | |
3609 | insn = NEXT_INSN (insn)) | |
3610 | { | |
3611 | if (!INSN_P (insn)) | |
3612 | continue; | |
3613 | if (insn == loop_end) | |
3614 | continue; | |
3615 | if (reg_mentioned_p (reg, PATTERN (insn))) | |
3616 | return true; | |
3617 | } | |
3618 | } | |
3c1905a4 | 3619 | return false; |
3620 | } | |
3621 | ||
917c4036 | 3622 | /* Estimate the length of INSN conservatively. */ |
3623 | ||
3624 | static int | |
3625 | length_for_loop (rtx insn) | |
3626 | { | |
3627 | int length = 0; | |
3628 | if (JUMP_P (insn) && any_condjump_p (insn) && !optimize_size) | |
3629 | { | |
709b2de5 | 3630 | if (ENABLE_WA_SPECULATIVE_SYNCS) |
917c4036 | 3631 | length = 8; |
709b2de5 | 3632 | else if (ENABLE_WA_SPECULATIVE_LOADS) |
917c4036 | 3633 | length = 6; |
3634 | } | |
3635 | else if (LABEL_P (insn)) | |
3636 | { | |
709b2de5 | 3637 | if (ENABLE_WA_SPECULATIVE_SYNCS) |
917c4036 | 3638 | length = 4; |
3639 | } | |
3640 | ||
3641 | if (INSN_P (insn)) | |
3642 | length += get_attr_length (insn); | |
3643 | ||
3644 | return length; | |
3645 | } | |
3646 | ||
3c1905a4 | 3647 | /* Optimize LOOP. */ |
3648 | ||
3649 | static void | |
3650 | bfin_optimize_loop (loop_info loop) | |
3651 | { | |
3652 | basic_block bb; | |
e82f36f5 | 3653 | loop_info inner; |
3c1905a4 | 3654 | rtx insn, init_insn, last_insn, nop_insn; |
3655 | rtx loop_init, start_label, end_label; | |
3656 | rtx reg_lc0, reg_lc1, reg_lt0, reg_lt1, reg_lb0, reg_lb1; | |
3657 | rtx iter_reg; | |
3658 | rtx lc_reg, lt_reg, lb_reg; | |
917c4036 | 3659 | rtx seq, seq_end; |
3c1905a4 | 3660 | int length; |
3661 | unsigned ix; | |
3662 | int inner_depth = 0; | |
3c1905a4 | 3663 | |
3664 | if (loop->visited) | |
3665 | return; | |
3666 | ||
3667 | loop->visited = 1; | |
3668 | ||
e82f36f5 | 3669 | if (loop->bad) |
3c1905a4 | 3670 | { |
3671 | if (dump_file) | |
3672 | fprintf (dump_file, ";; loop %d bad when found\n", loop->loop_no); | |
3673 | goto bad_loop; | |
3674 | } | |
3675 | ||
e82f36f5 | 3676 | /* Every loop contains in its list of inner loops every loop nested inside |
3677 | it, even if there are intermediate loops. This works because we're doing | |
3678 | a depth-first search here and never visit a loop more than once. */ | |
3679 | for (ix = 0; VEC_iterate (loop_info, loop->loops, ix, inner); ix++) | |
3c1905a4 | 3680 | { |
e82f36f5 | 3681 | bfin_optimize_loop (inner); |
3c1905a4 | 3682 | |
e82f36f5 | 3683 | if (!inner->bad && inner_depth < inner->depth) |
3684 | { | |
3685 | inner_depth = inner->depth; | |
3c1905a4 | 3686 | |
e82f36f5 | 3687 | loop->clobber_loop0 |= inner->clobber_loop0; |
3688 | loop->clobber_loop1 |= inner->clobber_loop1; | |
3689 | } | |
3c1905a4 | 3690 | } |
3691 | ||
e82f36f5 | 3692 | loop->depth = inner_depth + 1; |
3693 | if (loop->depth > MAX_LOOP_DEPTH) | |
3c1905a4 | 3694 | { |
3695 | if (dump_file) | |
e82f36f5 | 3696 | fprintf (dump_file, ";; loop %d too deep\n", loop->loop_no); |
3c1905a4 | 3697 | goto bad_loop; |
3698 | } | |
3699 | ||
3700 | /* Get the loop iteration register. */ | |
3701 | iter_reg = loop->iter_reg; | |
3702 | ||
3703 | if (!DPREG_P (iter_reg)) | |
3704 | { | |
3705 | if (dump_file) | |
3706 | fprintf (dump_file, ";; loop %d iteration count NOT in PREG or DREG\n", | |
3707 | loop->loop_no); | |
3708 | goto bad_loop; | |
3709 | } | |
3710 | ||
917c4036 | 3711 | if (loop->incoming_src) |
3712 | { | |
3713 | /* Make sure the predecessor is before the loop start label, as required by | |
3714 | the LSETUP instruction. */ | |
3715 | length = 0; | |
3716 | for (insn = BB_END (loop->incoming_src); | |
3717 | insn && insn != loop->start_label; | |
3718 | insn = NEXT_INSN (insn)) | |
3719 | length += length_for_loop (insn); | |
3720 | ||
3721 | if (!insn) | |
3722 | { | |
3723 | if (dump_file) | |
3724 | fprintf (dump_file, ";; loop %d lsetup not before loop_start\n", | |
3725 | loop->loop_no); | |
3726 | goto bad_loop; | |
3727 | } | |
3728 | ||
3729 | if (length > MAX_LSETUP_DISTANCE) | |
3730 | { | |
3731 | if (dump_file) | |
3732 | fprintf (dump_file, ";; loop %d lsetup too far away\n", loop->loop_no); | |
3733 | goto bad_loop; | |
3734 | } | |
3735 | } | |
3736 | ||
3c1905a4 | 3737 | /* Check if start_label appears before loop_end and calculate the |
3738 | offset between them. We calculate the length of instructions | |
3739 | conservatively. */ | |
3740 | length = 0; | |
3741 | for (insn = loop->start_label; | |
3742 | insn && insn != loop->loop_end; | |
3743 | insn = NEXT_INSN (insn)) | |
917c4036 | 3744 | length += length_for_loop (insn); |
3c1905a4 | 3745 | |
3746 | if (!insn) | |
3747 | { | |
3748 | if (dump_file) | |
3749 | fprintf (dump_file, ";; loop %d start_label not before loop_end\n", | |
3750 | loop->loop_no); | |
3751 | goto bad_loop; | |
3752 | } | |
3753 | ||
3754 | loop->length = length; | |
3755 | if (loop->length > MAX_LOOP_LENGTH) | |
3756 | { | |
3757 | if (dump_file) | |
3758 | fprintf (dump_file, ";; loop %d too long\n", loop->loop_no); | |
3759 | goto bad_loop; | |
3760 | } | |
3761 | ||
3762 | /* Scan all the blocks to make sure they don't use iter_reg. */ | |
3763 | if (bfin_scan_loop (loop, iter_reg, loop->loop_end)) | |
3764 | { | |
3765 | if (dump_file) | |
3766 | fprintf (dump_file, ";; loop %d uses iterator\n", loop->loop_no); | |
3767 | goto bad_loop; | |
3768 | } | |
3769 | ||
3770 | /* Scan all the insns to see if the loop body clobber | |
3771 | any hardware loop registers. */ | |
3772 | ||
3773 | reg_lc0 = gen_rtx_REG (SImode, REG_LC0); | |
3774 | reg_lc1 = gen_rtx_REG (SImode, REG_LC1); | |
3775 | reg_lt0 = gen_rtx_REG (SImode, REG_LT0); | |
3776 | reg_lt1 = gen_rtx_REG (SImode, REG_LT1); | |
3777 | reg_lb0 = gen_rtx_REG (SImode, REG_LB0); | |
3778 | reg_lb1 = gen_rtx_REG (SImode, REG_LB1); | |
3779 | ||
3780 | for (ix = 0; VEC_iterate (basic_block, loop->blocks, ix, bb); ix++) | |
3781 | { | |
3782 | rtx insn; | |
3783 | ||
3784 | for (insn = BB_HEAD (bb); | |
3785 | insn != NEXT_INSN (BB_END (bb)); | |
3786 | insn = NEXT_INSN (insn)) | |
3787 | { | |
3788 | if (!INSN_P (insn)) | |
3789 | continue; | |
3790 | ||
3791 | if (reg_set_p (reg_lc0, insn) | |
3792 | || reg_set_p (reg_lt0, insn) | |
3793 | || reg_set_p (reg_lb0, insn)) | |
3794 | loop->clobber_loop0 = 1; | |
3795 | ||
3796 | if (reg_set_p (reg_lc1, insn) | |
3797 | || reg_set_p (reg_lt1, insn) | |
3798 | || reg_set_p (reg_lb1, insn)) | |
3799 | loop->clobber_loop1 |= 1; | |
3800 | } | |
3801 | } | |
3802 | ||
3803 | if ((loop->clobber_loop0 && loop->clobber_loop1) | |
3804 | || (loop->depth == MAX_LOOP_DEPTH && loop->clobber_loop0)) | |
3805 | { | |
3806 | loop->depth = MAX_LOOP_DEPTH + 1; | |
3807 | if (dump_file) | |
3808 | fprintf (dump_file, ";; loop %d no loop reg available\n", | |
3809 | loop->loop_no); | |
3810 | goto bad_loop; | |
3811 | } | |
3812 | ||
3813 | /* There should be an instruction before the loop_end instruction | |
3814 | in the same basic block. And the instruction must not be | |
3815 | - JUMP | |
3816 | - CONDITIONAL BRANCH | |
3817 | - CALL | |
3818 | - CSYNC | |
3819 | - SSYNC | |
3820 | - Returns (RTS, RTN, etc.) */ | |
3821 | ||
3822 | bb = loop->tail; | |
3823 | last_insn = PREV_INSN (loop->loop_end); | |
3824 | ||
3825 | while (1) | |
3826 | { | |
3827 | for (; last_insn != PREV_INSN (BB_HEAD (bb)); | |
3828 | last_insn = PREV_INSN (last_insn)) | |
3829 | if (INSN_P (last_insn)) | |
3830 | break; | |
3831 | ||
3832 | if (last_insn != PREV_INSN (BB_HEAD (bb))) | |
3833 | break; | |
3834 | ||
3835 | if (single_pred_p (bb) | |
3836 | && single_pred (bb) != ENTRY_BLOCK_PTR) | |
3837 | { | |
3838 | bb = single_pred (bb); | |
3839 | last_insn = BB_END (bb); | |
3840 | continue; | |
3841 | } | |
3842 | else | |
3843 | { | |
3844 | last_insn = NULL_RTX; | |
3845 | break; | |
3846 | } | |
3847 | } | |
3848 | ||
3849 | if (!last_insn) | |
3850 | { | |
3851 | if (dump_file) | |
3852 | fprintf (dump_file, ";; loop %d has no last instruction\n", | |
3853 | loop->loop_no); | |
3854 | goto bad_loop; | |
3855 | } | |
3856 | ||
3857 | if (JUMP_P (last_insn)) | |
3858 | { | |
225ab426 | 3859 | loop_info inner = (loop_info) bb->aux; |
3c1905a4 | 3860 | if (inner |
3861 | && inner->outer == loop | |
3862 | && inner->loop_end == last_insn | |
3863 | && inner->depth == 1) | |
3864 | /* This jump_insn is the exact loop_end of an inner loop | |
3865 | and to be optimized away. So use the inner's last_insn. */ | |
3866 | last_insn = inner->last_insn; | |
3867 | else | |
3868 | { | |
3869 | if (dump_file) | |
3870 | fprintf (dump_file, ";; loop %d has bad last instruction\n", | |
3871 | loop->loop_no); | |
3872 | goto bad_loop; | |
3873 | } | |
3874 | } | |
3875 | else if (CALL_P (last_insn) | |
48df5a7f | 3876 | || (GET_CODE (PATTERN (last_insn)) != SEQUENCE |
3877 | && get_attr_type (last_insn) == TYPE_SYNC) | |
3c1905a4 | 3878 | || recog_memoized (last_insn) == CODE_FOR_return_internal) |
3879 | { | |
3880 | if (dump_file) | |
3881 | fprintf (dump_file, ";; loop %d has bad last instruction\n", | |
3882 | loop->loop_no); | |
3883 | goto bad_loop; | |
3884 | } | |
3885 | ||
3886 | if (GET_CODE (PATTERN (last_insn)) == ASM_INPUT | |
3887 | || asm_noperands (PATTERN (last_insn)) >= 0 | |
48df5a7f | 3888 | || (GET_CODE (PATTERN (last_insn)) != SEQUENCE |
3889 | && get_attr_seq_insns (last_insn) == SEQ_INSNS_MULTI)) | |
3c1905a4 | 3890 | { |
3891 | nop_insn = emit_insn_after (gen_nop (), last_insn); | |
3892 | last_insn = nop_insn; | |
3893 | } | |
3894 | ||
3895 | loop->last_insn = last_insn; | |
3896 | ||
3897 | /* The loop is good for replacement. */ | |
3898 | start_label = loop->start_label; | |
3899 | end_label = gen_label_rtx (); | |
3900 | iter_reg = loop->iter_reg; | |
3901 | ||
3902 | if (loop->depth == 1 && !loop->clobber_loop1) | |
3903 | { | |
3904 | lc_reg = reg_lc1; | |
3905 | lt_reg = reg_lt1; | |
3906 | lb_reg = reg_lb1; | |
3907 | loop->clobber_loop1 = 1; | |
3908 | } | |
3909 | else | |
3910 | { | |
3911 | lc_reg = reg_lc0; | |
3912 | lt_reg = reg_lt0; | |
3913 | lb_reg = reg_lb0; | |
3914 | loop->clobber_loop0 = 1; | |
3915 | } | |
3916 | ||
3917 | /* If iter_reg is a DREG, we need generate an instruction to load | |
3918 | the loop count into LC register. */ | |
3919 | if (D_REGNO_P (REGNO (iter_reg))) | |
3920 | { | |
3921 | init_insn = gen_movsi (lc_reg, iter_reg); | |
3922 | loop_init = gen_lsetup_without_autoinit (lt_reg, start_label, | |
3923 | lb_reg, end_label, | |
3924 | lc_reg); | |
3925 | } | |
3926 | else if (P_REGNO_P (REGNO (iter_reg))) | |
3927 | { | |
3928 | init_insn = NULL_RTX; | |
3929 | loop_init = gen_lsetup_with_autoinit (lt_reg, start_label, | |
3930 | lb_reg, end_label, | |
3931 | lc_reg, iter_reg); | |
3932 | } | |
3933 | else | |
3934 | gcc_unreachable (); | |
3935 | ||
3936 | loop->init = init_insn; | |
3937 | loop->end_label = end_label; | |
3938 | loop->loop_init = loop_init; | |
3939 | ||
3940 | if (dump_file) | |
3941 | { | |
3942 | fprintf (dump_file, ";; replacing loop %d initializer with\n", | |
3943 | loop->loop_no); | |
3944 | print_rtl_single (dump_file, loop->loop_init); | |
3945 | fprintf (dump_file, ";; replacing loop %d terminator with\n", | |
3946 | loop->loop_no); | |
3947 | print_rtl_single (dump_file, loop->loop_end); | |
3948 | } | |
3949 | ||
3950 | start_sequence (); | |
3951 | ||
3952 | if (loop->init != NULL_RTX) | |
3953 | emit_insn (loop->init); | |
917c4036 | 3954 | seq_end = emit_insn (loop->loop_init); |
3c1905a4 | 3955 | |
3956 | seq = get_insns (); | |
3957 | end_sequence (); | |
3958 | ||
917c4036 | 3959 | if (loop->incoming_src) |
3960 | { | |
3961 | rtx prev = BB_END (loop->incoming_src); | |
3962 | if (VEC_length (edge, loop->incoming) > 1 | |
3963 | || !(VEC_last (edge, loop->incoming)->flags & EDGE_FALLTHRU)) | |
3964 | { | |
3965 | gcc_assert (JUMP_P (prev)); | |
3966 | prev = PREV_INSN (prev); | |
3967 | } | |
3968 | emit_insn_after (seq, prev); | |
3969 | } | |
3970 | else | |
3971 | { | |
3972 | basic_block new_bb; | |
3973 | edge e; | |
3974 | edge_iterator ei; | |
3975 | ||
3976 | if (loop->head != loop->incoming_dest) | |
3977 | { | |
3978 | FOR_EACH_EDGE (e, ei, loop->head->preds) | |
3979 | { | |
3980 | if (e->flags & EDGE_FALLTHRU) | |
3981 | { | |
3982 | rtx newjump = gen_jump (loop->start_label); | |
3983 | emit_insn_before (newjump, BB_HEAD (loop->head)); | |
3984 | new_bb = create_basic_block (newjump, newjump, loop->head->prev_bb); | |
3985 | gcc_assert (new_bb = loop->head->prev_bb); | |
3986 | break; | |
3987 | } | |
3988 | } | |
3989 | } | |
3990 | ||
3991 | emit_insn_before (seq, BB_HEAD (loop->head)); | |
3992 | seq = emit_label_before (gen_label_rtx (), seq); | |
3c1905a4 | 3993 | |
917c4036 | 3994 | new_bb = create_basic_block (seq, seq_end, loop->head->prev_bb); |
3995 | FOR_EACH_EDGE (e, ei, loop->incoming) | |
3996 | { | |
3997 | if (!(e->flags & EDGE_FALLTHRU) | |
3998 | || e->dest != loop->head) | |
3999 | redirect_edge_and_branch_force (e, new_bb); | |
4000 | else | |
4001 | redirect_edge_succ (e, new_bb); | |
4002 | } | |
4003 | } | |
4004 | ||
4005 | delete_insn (loop->loop_end); | |
3c1905a4 | 4006 | /* Insert the loop end label before the last instruction of the loop. */ |
4007 | emit_label_before (loop->end_label, loop->last_insn); | |
4008 | ||
4009 | return; | |
4010 | ||
917c4036 | 4011 | bad_loop: |
3c1905a4 | 4012 | |
4013 | if (dump_file) | |
4014 | fprintf (dump_file, ";; loop %d is bad\n", loop->loop_no); | |
4015 | ||
e82f36f5 | 4016 | loop->bad = 1; |
3c1905a4 | 4017 | |
4018 | if (DPREG_P (loop->iter_reg)) | |
4019 | { | |
4020 | /* If loop->iter_reg is a DREG or PREG, we can split it here | |
4021 | without scratch register. */ | |
4022 | rtx insn; | |
4023 | ||
4024 | emit_insn_before (gen_addsi3 (loop->iter_reg, | |
4025 | loop->iter_reg, | |
4026 | constm1_rtx), | |
4027 | loop->loop_end); | |
4028 | ||
4029 | emit_insn_before (gen_cmpsi (loop->iter_reg, const0_rtx), | |
4030 | loop->loop_end); | |
4031 | ||
4032 | insn = emit_jump_insn_before (gen_bne (loop->start_label), | |
4033 | loop->loop_end); | |
4034 | ||
4035 | JUMP_LABEL (insn) = loop->start_label; | |
4036 | LABEL_NUSES (loop->start_label)++; | |
4037 | delete_insn (loop->loop_end); | |
4038 | } | |
4039 | } | |
4040 | ||
e82f36f5 | 4041 | /* Called from bfin_reorg_loops when a potential loop end is found. LOOP is |
4042 | a newly set up structure describing the loop, it is this function's | |
4043 | responsibility to fill most of it. TAIL_BB and TAIL_INSN point to the | |
4044 | loop_end insn and its enclosing basic block. */ | |
4045 | ||
4046 | static void | |
4047 | bfin_discover_loop (loop_info loop, basic_block tail_bb, rtx tail_insn) | |
4048 | { | |
4049 | unsigned dwork = 0; | |
4050 | basic_block bb; | |
4051 | VEC (basic_block,heap) *works = VEC_alloc (basic_block,heap,20); | |
4052 | ||
4053 | loop->tail = tail_bb; | |
4054 | loop->head = BRANCH_EDGE (tail_bb)->dest; | |
4055 | loop->successor = FALLTHRU_EDGE (tail_bb)->dest; | |
e82f36f5 | 4056 | loop->loop_end = tail_insn; |
4057 | loop->last_insn = NULL_RTX; | |
4058 | loop->iter_reg = SET_DEST (XVECEXP (PATTERN (tail_insn), 0, 1)); | |
4059 | loop->depth = loop->length = 0; | |
4060 | loop->visited = 0; | |
4061 | loop->clobber_loop0 = loop->clobber_loop1 = 0; | |
4062 | loop->outer = NULL; | |
4063 | loop->loops = NULL; | |
917c4036 | 4064 | loop->incoming = VEC_alloc (edge, gc, 2); |
e82f36f5 | 4065 | loop->init = loop->loop_init = NULL_RTX; |
4066 | loop->start_label = XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (tail_insn), 0, 0)), 1), 0); | |
4067 | loop->end_label = NULL_RTX; | |
4068 | loop->bad = 0; | |
4069 | ||
4070 | VEC_safe_push (basic_block, heap, works, loop->head); | |
4071 | ||
4072 | while (VEC_iterate (basic_block, works, dwork++, bb)) | |
4073 | { | |
4074 | edge e; | |
4075 | edge_iterator ei; | |
4076 | if (bb == EXIT_BLOCK_PTR) | |
4077 | { | |
4078 | /* We've reached the exit block. The loop must be bad. */ | |
4079 | if (dump_file) | |
4080 | fprintf (dump_file, | |
4081 | ";; Loop is bad - reached exit block while scanning\n"); | |
4082 | loop->bad = 1; | |
4083 | break; | |
4084 | } | |
4085 | ||
4086 | if (bitmap_bit_p (loop->block_bitmap, bb->index)) | |
4087 | continue; | |
4088 | ||
4089 | /* We've not seen this block before. Add it to the loop's | |
4090 | list and then add each successor to the work list. */ | |
4091 | ||
4092 | VEC_safe_push (basic_block, heap, loop->blocks, bb); | |
4093 | bitmap_set_bit (loop->block_bitmap, bb->index); | |
4094 | ||
4095 | if (bb != tail_bb) | |
4096 | { | |
4097 | FOR_EACH_EDGE (e, ei, bb->succs) | |
4098 | { | |
4099 | basic_block succ = EDGE_SUCC (bb, ei.index)->dest; | |
d18119ae | 4100 | if (!REGNO_REG_SET_P (df_get_live_in (succ), |
e82f36f5 | 4101 | REGNO (loop->iter_reg))) |
4102 | continue; | |
4103 | if (!VEC_space (basic_block, works, 1)) | |
4104 | { | |
4105 | if (dwork) | |
4106 | { | |
4107 | VEC_block_remove (basic_block, works, 0, dwork); | |
4108 | dwork = 0; | |
4109 | } | |
4110 | else | |
4111 | VEC_reserve (basic_block, heap, works, 1); | |
4112 | } | |
4113 | VEC_quick_push (basic_block, works, succ); | |
4114 | } | |
4115 | } | |
4116 | } | |
4117 | ||
917c4036 | 4118 | /* Find the predecessor, and make sure nothing else jumps into this loop. */ |
e82f36f5 | 4119 | if (!loop->bad) |
4120 | { | |
917c4036 | 4121 | int pass, retry; |
4122 | for (dwork = 0; VEC_iterate (basic_block, loop->blocks, dwork, bb); dwork++) | |
e82f36f5 | 4123 | { |
917c4036 | 4124 | edge e; |
4125 | edge_iterator ei; | |
4126 | FOR_EACH_EDGE (e, ei, bb->preds) | |
4127 | { | |
4128 | basic_block pred = e->src; | |
4129 | ||
4130 | if (!bfin_bb_in_loop (loop, pred)) | |
4131 | { | |
4132 | if (dump_file) | |
4133 | fprintf (dump_file, ";; Loop %d: incoming edge %d -> %d\n", | |
4134 | loop->loop_no, pred->index, | |
4135 | e->dest->index); | |
4136 | VEC_safe_push (edge, gc, loop->incoming, e); | |
4137 | } | |
4138 | } | |
e82f36f5 | 4139 | } |
4140 | ||
917c4036 | 4141 | for (pass = 0, retry = 1; retry && pass < 2; pass++) |
e82f36f5 | 4142 | { |
917c4036 | 4143 | edge e; |
4144 | edge_iterator ei; | |
4145 | bool first = true; | |
4146 | retry = 0; | |
4147 | ||
4148 | FOR_EACH_EDGE (e, ei, loop->incoming) | |
4149 | { | |
4150 | if (first) | |
4151 | { | |
4152 | loop->incoming_src = e->src; | |
4153 | loop->incoming_dest = e->dest; | |
4154 | first = false; | |
4155 | } | |
4156 | else | |
4157 | { | |
4158 | if (e->dest != loop->incoming_dest) | |
4159 | loop->incoming_dest = NULL; | |
4160 | if (e->src != loop->incoming_src) | |
4161 | loop->incoming_src = NULL; | |
4162 | } | |
4163 | if (loop->incoming_src == NULL && loop->incoming_dest == NULL) | |
4164 | { | |
4165 | if (pass == 0) | |
4166 | { | |
4167 | if (dump_file) | |
4168 | fprintf (dump_file, | |
4169 | ";; retrying loop %d with forwarder blocks\n", | |
4170 | loop->loop_no); | |
4171 | retry = 1; | |
4172 | break; | |
4173 | } | |
4174 | loop->bad = 1; | |
4175 | if (dump_file) | |
4176 | fprintf (dump_file, | |
4177 | ";; can't find suitable entry for loop %d\n", | |
4178 | loop->loop_no); | |
4179 | goto out; | |
4180 | } | |
4181 | } | |
4182 | if (retry) | |
4183 | { | |
4184 | retry = 0; | |
4185 | FOR_EACH_EDGE (e, ei, loop->incoming) | |
4186 | { | |
4187 | if (forwarder_block_p (e->src)) | |
4188 | { | |
4189 | edge e2; | |
4190 | edge_iterator ei2; | |
4191 | ||
4192 | if (dump_file) | |
4193 | fprintf (dump_file, | |
4194 | ";; Adding forwarder block %d to loop %d and retrying\n", | |
4195 | e->src->index, loop->loop_no); | |
4196 | VEC_safe_push (basic_block, heap, loop->blocks, e->src); | |
4197 | bitmap_set_bit (loop->block_bitmap, e->src->index); | |
4198 | FOR_EACH_EDGE (e2, ei2, e->src->preds) | |
4199 | VEC_safe_push (edge, gc, loop->incoming, e2); | |
4200 | VEC_unordered_remove (edge, loop->incoming, ei.index); | |
4201 | retry = 1; | |
4202 | break; | |
4203 | } | |
4204 | } | |
4205 | } | |
e82f36f5 | 4206 | } |
4207 | } | |
4208 | ||
917c4036 | 4209 | out: |
e82f36f5 | 4210 | VEC_free (basic_block, heap, works); |
4211 | } | |
4212 | ||
917c4036 | 4213 | /* Analyze the structure of the loops in the current function. Use STACK |
4214 | for bitmap allocations. Returns all the valid candidates for hardware | |
4215 | loops found in this function. */ | |
4216 | static loop_info | |
4217 | bfin_discover_loops (bitmap_obstack *stack, FILE *dump_file) | |
3c1905a4 | 4218 | { |
3c1905a4 | 4219 | loop_info loops = NULL; |
4220 | loop_info loop; | |
917c4036 | 4221 | basic_block bb; |
4222 | bitmap tmp_bitmap; | |
3c1905a4 | 4223 | int nloops = 0; |
e82f36f5 | 4224 | |
3c1905a4 | 4225 | /* Find all the possible loop tails. This means searching for every |
4226 | loop_end instruction. For each one found, create a loop_info | |
4227 | structure and add the head block to the work list. */ | |
4228 | FOR_EACH_BB (bb) | |
4229 | { | |
4230 | rtx tail = BB_END (bb); | |
4231 | ||
4232 | while (GET_CODE (tail) == NOTE) | |
4233 | tail = PREV_INSN (tail); | |
4234 | ||
4235 | bb->aux = NULL; | |
e82f36f5 | 4236 | |
7196637a | 4237 | if (INSN_P (tail) && recog_memoized (tail) == CODE_FOR_loop_end) |
3c1905a4 | 4238 | { |
d4cae31e | 4239 | rtx insn; |
3c1905a4 | 4240 | /* A possible loop end */ |
4241 | ||
d4cae31e | 4242 | /* There's a degenerate case we can handle - an empty loop consisting |
4243 | of only a back branch. Handle that by deleting the branch. */ | |
4244 | insn = BB_HEAD (BRANCH_EDGE (bb)->dest); | |
4245 | if (next_real_insn (insn) == tail) | |
4246 | { | |
4247 | if (dump_file) | |
4248 | { | |
4249 | fprintf (dump_file, ";; degenerate loop ending at\n"); | |
4250 | print_rtl_single (dump_file, tail); | |
4251 | } | |
4252 | delete_insn_and_edges (tail); | |
4253 | continue; | |
4254 | } | |
4255 | ||
3c1905a4 | 4256 | loop = XNEW (struct loop_info); |
4257 | loop->next = loops; | |
4258 | loops = loop; | |
3c1905a4 | 4259 | loop->loop_no = nloops++; |
e82f36f5 | 4260 | loop->blocks = VEC_alloc (basic_block, heap, 20); |
917c4036 | 4261 | loop->block_bitmap = BITMAP_ALLOC (stack); |
3c1905a4 | 4262 | bb->aux = loop; |
4263 | ||
4264 | if (dump_file) | |
4265 | { | |
4266 | fprintf (dump_file, ";; potential loop %d ending at\n", | |
4267 | loop->loop_no); | |
4268 | print_rtl_single (dump_file, tail); | |
4269 | } | |
e82f36f5 | 4270 | |
4271 | bfin_discover_loop (loop, bb, tail); | |
3c1905a4 | 4272 | } |
4273 | } | |
4274 | ||
917c4036 | 4275 | tmp_bitmap = BITMAP_ALLOC (stack); |
e82f36f5 | 4276 | /* Compute loop nestings. */ |
4277 | for (loop = loops; loop; loop = loop->next) | |
4278 | { | |
4279 | loop_info other; | |
4280 | if (loop->bad) | |
4281 | continue; | |
4282 | ||
4283 | for (other = loop->next; other; other = other->next) | |
3c1905a4 | 4284 | { |
e82f36f5 | 4285 | if (other->bad) |
4286 | continue; | |
4287 | ||
4288 | bitmap_and (tmp_bitmap, other->block_bitmap, loop->block_bitmap); | |
4289 | if (bitmap_empty_p (tmp_bitmap)) | |
4290 | continue; | |
4291 | if (bitmap_equal_p (tmp_bitmap, other->block_bitmap)) | |
3c1905a4 | 4292 | { |
e82f36f5 | 4293 | other->outer = loop; |
4294 | VEC_safe_push (loop_info, heap, loop->loops, other); | |
4295 | } | |
4296 | else if (bitmap_equal_p (tmp_bitmap, loop->block_bitmap)) | |
4297 | { | |
4298 | loop->outer = other; | |
4299 | VEC_safe_push (loop_info, heap, other->loops, loop); | |
3c1905a4 | 4300 | } |
3c1905a4 | 4301 | else |
4302 | { | |
917c4036 | 4303 | if (dump_file) |
4304 | fprintf (dump_file, | |
4305 | ";; can't find suitable nesting for loops %d and %d\n", | |
4306 | loop->loop_no, other->loop_no); | |
e82f36f5 | 4307 | loop->bad = other->bad = 1; |
3c1905a4 | 4308 | } |
4309 | } | |
4310 | } | |
e82f36f5 | 4311 | BITMAP_FREE (tmp_bitmap); |
3c1905a4 | 4312 | |
917c4036 | 4313 | return loops; |
4314 | } | |
4315 | ||
4316 | /* Free up the loop structures in LOOPS. */ | |
4317 | static void | |
4318 | free_loops (loop_info loops) | |
4319 | { | |
4320 | while (loops) | |
4321 | { | |
4322 | loop_info loop = loops; | |
4323 | loops = loop->next; | |
4324 | VEC_free (loop_info, heap, loop->loops); | |
4325 | VEC_free (basic_block, heap, loop->blocks); | |
4326 | BITMAP_FREE (loop->block_bitmap); | |
4327 | XDELETE (loop); | |
4328 | } | |
4329 | } | |
4330 | ||
4331 | #define BB_AUX_INDEX(BB) ((unsigned)(BB)->aux) | |
4332 | ||
4333 | /* The taken-branch edge from the loop end can actually go forward. Since the | |
4334 | Blackfin's LSETUP instruction requires that the loop end be after the loop | |
4335 | start, try to reorder a loop's basic blocks when we find such a case. */ | |
4336 | static void | |
4337 | bfin_reorder_loops (loop_info loops, FILE *dump_file) | |
4338 | { | |
4339 | basic_block bb; | |
4340 | loop_info loop; | |
4341 | ||
4342 | FOR_EACH_BB (bb) | |
4343 | bb->aux = NULL; | |
d18119ae | 4344 | cfg_layout_initialize (0); |
917c4036 | 4345 | |
4346 | for (loop = loops; loop; loop = loop->next) | |
4347 | { | |
4348 | unsigned index; | |
4349 | basic_block bb; | |
4350 | edge e; | |
4351 | edge_iterator ei; | |
4352 | ||
4353 | if (loop->bad) | |
4354 | continue; | |
4355 | ||
4356 | /* Recreate an index for basic blocks that represents their order. */ | |
4357 | for (bb = ENTRY_BLOCK_PTR->next_bb, index = 0; | |
4358 | bb != EXIT_BLOCK_PTR; | |
4359 | bb = bb->next_bb, index++) | |
4360 | bb->aux = (PTR) index; | |
4361 | ||
4362 | if (BB_AUX_INDEX (loop->head) < BB_AUX_INDEX (loop->tail)) | |
4363 | continue; | |
4364 | ||
4365 | FOR_EACH_EDGE (e, ei, loop->head->succs) | |
4366 | { | |
4367 | if (bitmap_bit_p (loop->block_bitmap, e->dest->index) | |
4368 | && BB_AUX_INDEX (e->dest) < BB_AUX_INDEX (loop->tail)) | |
4369 | { | |
4370 | basic_block start_bb = e->dest; | |
4371 | basic_block start_prev_bb = start_bb->prev_bb; | |
4372 | ||
4373 | if (dump_file) | |
4374 | fprintf (dump_file, ";; Moving block %d before block %d\n", | |
4375 | loop->head->index, start_bb->index); | |
4376 | loop->head->prev_bb->next_bb = loop->head->next_bb; | |
4377 | loop->head->next_bb->prev_bb = loop->head->prev_bb; | |
4378 | ||
4379 | loop->head->prev_bb = start_prev_bb; | |
4380 | loop->head->next_bb = start_bb; | |
4381 | start_prev_bb->next_bb = start_bb->prev_bb = loop->head; | |
4382 | break; | |
4383 | } | |
4384 | } | |
4385 | loops = loops->next; | |
4386 | } | |
4387 | ||
4388 | FOR_EACH_BB (bb) | |
4389 | { | |
4390 | if (bb->next_bb != EXIT_BLOCK_PTR) | |
4391 | bb->aux = bb->next_bb; | |
4392 | else | |
4393 | bb->aux = NULL; | |
4394 | } | |
4395 | cfg_layout_finalize (); | |
d18119ae | 4396 | df_analyze (); |
917c4036 | 4397 | } |
4398 | ||
4399 | /* Run from machine_dependent_reorg, this pass looks for doloop_end insns | |
4400 | and tries to rewrite the RTL of these loops so that proper Blackfin | |
4401 | hardware loops are generated. */ | |
4402 | ||
4403 | static void | |
4404 | bfin_reorg_loops (FILE *dump_file) | |
4405 | { | |
4406 | loop_info loops = NULL; | |
4407 | loop_info loop; | |
4408 | basic_block bb; | |
4409 | bitmap_obstack stack; | |
4410 | ||
4411 | bitmap_obstack_initialize (&stack); | |
4412 | ||
4413 | if (dump_file) | |
4414 | fprintf (dump_file, ";; Find loops, first pass\n\n"); | |
4415 | ||
4416 | loops = bfin_discover_loops (&stack, dump_file); | |
4417 | ||
4418 | if (dump_file) | |
4419 | bfin_dump_loops (loops); | |
4420 | ||
4421 | bfin_reorder_loops (loops, dump_file); | |
4422 | free_loops (loops); | |
4423 | ||
4424 | if (dump_file) | |
4425 | fprintf (dump_file, ";; Find loops, second pass\n\n"); | |
4426 | ||
4427 | loops = bfin_discover_loops (&stack, dump_file); | |
3c1905a4 | 4428 | if (dump_file) |
4429 | { | |
4430 | fprintf (dump_file, ";; All loops found:\n\n"); | |
4431 | bfin_dump_loops (loops); | |
4432 | } | |
4433 | ||
4434 | /* Now apply the optimizations. */ | |
4435 | for (loop = loops; loop; loop = loop->next) | |
4436 | bfin_optimize_loop (loop); | |
4437 | ||
4438 | if (dump_file) | |
4439 | { | |
4440 | fprintf (dump_file, ";; After hardware loops optimization:\n\n"); | |
4441 | bfin_dump_loops (loops); | |
4442 | } | |
4443 | ||
917c4036 | 4444 | free_loops (loops); |
3c1905a4 | 4445 | |
4446 | if (dump_file) | |
4447 | print_rtl (dump_file, get_insns ()); | |
48df5a7f | 4448 | |
4449 | FOR_EACH_BB (bb) | |
4450 | bb->aux = NULL; | |
3c1905a4 | 4451 | } |
48df5a7f | 4452 | \f |
4453 | /* Possibly generate a SEQUENCE out of three insns found in SLOT. | |
4454 | Returns true if we modified the insn chain, false otherwise. */ | |
4455 | static bool | |
4456 | gen_one_bundle (rtx slot[3]) | |
4457 | { | |
48df5a7f | 4458 | gcc_assert (slot[1] != NULL_RTX); |
4459 | ||
73c69c85 | 4460 | /* Don't add extra NOPs if optimizing for size. */ |
4461 | if (optimize_size | |
4462 | && (slot[0] == NULL_RTX || slot[2] == NULL_RTX)) | |
4463 | return false; | |
4464 | ||
48df5a7f | 4465 | /* Verify that we really can do the multi-issue. */ |
4466 | if (slot[0]) | |
4467 | { | |
4468 | rtx t = NEXT_INSN (slot[0]); | |
4469 | while (t != slot[1]) | |
4470 | { | |
4471 | if (GET_CODE (t) != NOTE | |
ad4583d9 | 4472 | || NOTE_KIND (t) != NOTE_INSN_DELETED) |
48df5a7f | 4473 | return false; |
4474 | t = NEXT_INSN (t); | |
4475 | } | |
4476 | } | |
4477 | if (slot[2]) | |
4478 | { | |
4479 | rtx t = NEXT_INSN (slot[1]); | |
4480 | while (t != slot[2]) | |
4481 | { | |
4482 | if (GET_CODE (t) != NOTE | |
ad4583d9 | 4483 | || NOTE_KIND (t) != NOTE_INSN_DELETED) |
48df5a7f | 4484 | return false; |
4485 | t = NEXT_INSN (t); | |
4486 | } | |
4487 | } | |
4488 | ||
4489 | if (slot[0] == NULL_RTX) | |
d18119ae | 4490 | { |
4491 | slot[0] = emit_insn_before (gen_mnop (), slot[1]); | |
4492 | df_insn_rescan (slot[0]); | |
4493 | } | |
48df5a7f | 4494 | if (slot[2] == NULL_RTX) |
d18119ae | 4495 | { |
4496 | slot[2] = emit_insn_after (gen_forced_nop (), slot[1]); | |
4497 | df_insn_rescan (slot[2]); | |
4498 | } | |
48df5a7f | 4499 | |
4500 | /* Avoid line number information being printed inside one bundle. */ | |
4501 | if (INSN_LOCATOR (slot[1]) | |
4502 | && INSN_LOCATOR (slot[1]) != INSN_LOCATOR (slot[0])) | |
4503 | INSN_LOCATOR (slot[1]) = INSN_LOCATOR (slot[0]); | |
4504 | if (INSN_LOCATOR (slot[2]) | |
4505 | && INSN_LOCATOR (slot[2]) != INSN_LOCATOR (slot[0])) | |
4506 | INSN_LOCATOR (slot[2]) = INSN_LOCATOR (slot[0]); | |
4507 | ||
4508 | /* Terminate them with "|| " instead of ";" in the output. */ | |
4509 | PUT_MODE (slot[0], SImode); | |
4510 | PUT_MODE (slot[1], SImode); | |
d18119ae | 4511 | /* Terminate the bundle, for the benefit of reorder_var_tracking_notes. */ |
4512 | PUT_MODE (slot[2], QImode); | |
48df5a7f | 4513 | return true; |
4514 | } | |
4515 | ||
4516 | /* Go through all insns, and use the information generated during scheduling | |
4517 | to generate SEQUENCEs to represent bundles of instructions issued | |
4518 | simultaneously. */ | |
4519 | ||
4520 | static void | |
4521 | bfin_gen_bundles (void) | |
4522 | { | |
4523 | basic_block bb; | |
4524 | FOR_EACH_BB (bb) | |
4525 | { | |
4526 | rtx insn, next; | |
4527 | rtx slot[3]; | |
4528 | int n_filled = 0; | |
4529 | ||
4530 | slot[0] = slot[1] = slot[2] = NULL_RTX; | |
4531 | for (insn = BB_HEAD (bb);; insn = next) | |
4532 | { | |
4533 | int at_end; | |
4534 | if (INSN_P (insn)) | |
4535 | { | |
4536 | if (get_attr_type (insn) == TYPE_DSP32) | |
4537 | slot[0] = insn; | |
4538 | else if (slot[1] == NULL_RTX) | |
4539 | slot[1] = insn; | |
4540 | else | |
4541 | slot[2] = insn; | |
4542 | n_filled++; | |
4543 | } | |
4544 | ||
4545 | next = NEXT_INSN (insn); | |
4546 | while (next && insn != BB_END (bb) | |
4547 | && !(INSN_P (next) | |
4548 | && GET_CODE (PATTERN (next)) != USE | |
4549 | && GET_CODE (PATTERN (next)) != CLOBBER)) | |
4550 | { | |
4551 | insn = next; | |
4552 | next = NEXT_INSN (insn); | |
4553 | } | |
3c1905a4 | 4554 | |
48df5a7f | 4555 | /* BB_END can change due to emitting extra NOPs, so check here. */ |
4556 | at_end = insn == BB_END (bb); | |
4557 | if (at_end || GET_MODE (next) == TImode) | |
4558 | { | |
4559 | if ((n_filled < 2 | |
4560 | || !gen_one_bundle (slot)) | |
4561 | && slot[0] != NULL_RTX) | |
4562 | { | |
4563 | rtx pat = PATTERN (slot[0]); | |
4564 | if (GET_CODE (pat) == SET | |
4565 | && GET_CODE (SET_SRC (pat)) == UNSPEC | |
4566 | && XINT (SET_SRC (pat), 1) == UNSPEC_32BIT) | |
4567 | { | |
4568 | SET_SRC (pat) = XVECEXP (SET_SRC (pat), 0, 0); | |
4569 | INSN_CODE (slot[0]) = -1; | |
d18119ae | 4570 | df_insn_rescan (slot[0]); |
48df5a7f | 4571 | } |
4572 | } | |
4573 | n_filled = 0; | |
4574 | slot[0] = slot[1] = slot[2] = NULL_RTX; | |
4575 | } | |
4576 | if (at_end) | |
4577 | break; | |
4578 | } | |
4579 | } | |
4580 | } | |
d18119ae | 4581 | |
4582 | /* Ensure that no var tracking notes are emitted in the middle of a | |
4583 | three-instruction bundle. */ | |
4584 | ||
4585 | static void | |
4586 | reorder_var_tracking_notes (void) | |
4587 | { | |
4588 | basic_block bb; | |
4589 | FOR_EACH_BB (bb) | |
4590 | { | |
4591 | rtx insn, next; | |
4592 | rtx queue = NULL_RTX; | |
4593 | bool in_bundle = false; | |
4594 | ||
4595 | for (insn = BB_HEAD (bb); insn != BB_END (bb); insn = next) | |
4596 | { | |
4597 | next = NEXT_INSN (insn); | |
4598 | ||
4599 | if (INSN_P (insn)) | |
4600 | { | |
4601 | /* Emit queued up notes at the last instruction of a bundle. */ | |
4602 | if (GET_MODE (insn) == QImode) | |
4603 | { | |
4604 | while (queue) | |
4605 | { | |
4606 | rtx next_queue = PREV_INSN (queue); | |
4607 | PREV_INSN (NEXT_INSN (insn)) = queue; | |
4608 | NEXT_INSN (queue) = NEXT_INSN (insn); | |
4609 | NEXT_INSN (insn) = queue; | |
4610 | PREV_INSN (queue) = insn; | |
4611 | queue = next_queue; | |
4612 | } | |
4613 | in_bundle = false; | |
4614 | } | |
4615 | else if (GET_MODE (insn) == SImode) | |
4616 | in_bundle = true; | |
4617 | } | |
4618 | else if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_VAR_LOCATION) | |
4619 | { | |
4620 | if (in_bundle) | |
4621 | { | |
4622 | rtx prev = PREV_INSN (insn); | |
4623 | PREV_INSN (next) = prev; | |
4624 | NEXT_INSN (prev) = next; | |
4625 | ||
4626 | PREV_INSN (insn) = queue; | |
4627 | queue = insn; | |
4628 | } | |
4629 | } | |
4630 | } | |
4631 | } | |
4632 | } | |
9e6a0967 | 4633 | \f |
48df5a7f | 4634 | /* Return an insn type for INSN that can be used by the caller for anomaly |
4635 | workarounds. This differs from plain get_attr_type in that it handles | |
4636 | SEQUENCEs. */ | |
4637 | ||
4638 | static enum attr_type | |
4639 | type_for_anomaly (rtx insn) | |
4640 | { | |
4641 | rtx pat = PATTERN (insn); | |
4642 | if (GET_CODE (pat) == SEQUENCE) | |
4643 | { | |
4644 | enum attr_type t; | |
4645 | t = get_attr_type (XVECEXP (pat, 0, 1)); | |
4646 | if (t == TYPE_MCLD) | |
4647 | return t; | |
4648 | t = get_attr_type (XVECEXP (pat, 0, 2)); | |
4649 | if (t == TYPE_MCLD) | |
4650 | return t; | |
4651 | return TYPE_MCST; | |
4652 | } | |
4653 | else | |
4654 | return get_attr_type (insn); | |
4655 | } | |
4656 | ||
4657 | /* Return nonzero if INSN contains any loads that may trap. It handles | |
4658 | SEQUENCEs correctly. */ | |
4659 | ||
4660 | static bool | |
4661 | trapping_loads_p (rtx insn) | |
4662 | { | |
4663 | rtx pat = PATTERN (insn); | |
4664 | if (GET_CODE (pat) == SEQUENCE) | |
4665 | { | |
4666 | enum attr_type t; | |
4667 | t = get_attr_type (XVECEXP (pat, 0, 1)); | |
4c359296 | 4668 | if (t == TYPE_MCLD |
4669 | && may_trap_p (SET_SRC (PATTERN (XVECEXP (pat, 0, 1))))) | |
48df5a7f | 4670 | return true; |
4671 | t = get_attr_type (XVECEXP (pat, 0, 2)); | |
4c359296 | 4672 | if (t == TYPE_MCLD |
4673 | && may_trap_p (SET_SRC (PATTERN (XVECEXP (pat, 0, 2))))) | |
48df5a7f | 4674 | return true; |
4675 | return false; | |
4676 | } | |
4677 | else | |
4678 | return may_trap_p (SET_SRC (single_set (insn))); | |
4679 | } | |
4680 | ||
771ce05e | 4681 | /* This function acts like NEXT_INSN, but is aware of three-insn bundles and |
4682 | skips all subsequent parallel instructions if INSN is the start of such | |
4683 | a group. */ | |
4684 | static rtx | |
4685 | find_next_insn_start (rtx insn) | |
4686 | { | |
4687 | if (GET_MODE (insn) == SImode) | |
4688 | { | |
4689 | while (GET_MODE (insn) != QImode) | |
4690 | insn = NEXT_INSN (insn); | |
4691 | } | |
4692 | return NEXT_INSN (insn); | |
4693 | } | |
4694 | ||
4695 | /* Return INSN if it is of TYPE_MCLD. Alternatively, if INSN is the start of | |
4696 | a three-insn bundle, see if one of them is a load and return that if so. | |
4697 | Return NULL_RTX if the insn does not contain loads. */ | |
4698 | static rtx | |
4699 | find_load (rtx insn) | |
4700 | { | |
4701 | if (get_attr_type (insn) == TYPE_MCLD) | |
4702 | return insn; | |
4703 | if (GET_MODE (insn) != SImode) | |
4704 | return NULL_RTX; | |
4705 | do { | |
4706 | insn = NEXT_INSN (insn); | |
4707 | if ((GET_MODE (insn) == SImode || GET_MODE (insn) == QImode) | |
4708 | && get_attr_type (insn) == TYPE_MCLD) | |
4709 | return insn; | |
4710 | } while (GET_MODE (insn) != QImode); | |
4711 | return NULL_RTX; | |
4712 | } | |
4713 | ||
9e6a0967 | 4714 | /* We use the machine specific reorg pass for emitting CSYNC instructions |
4715 | after conditional branches as needed. | |
4716 | ||
4717 | The Blackfin is unusual in that a code sequence like | |
4718 | if cc jump label | |
4719 | r0 = (p0) | |
4720 | may speculatively perform the load even if the condition isn't true. This | |
4721 | happens for a branch that is predicted not taken, because the pipeline | |
4722 | isn't flushed or stalled, so the early stages of the following instructions, | |
4723 | which perform the memory reference, are allowed to execute before the | |
4724 | jump condition is evaluated. | |
4725 | Therefore, we must insert additional instructions in all places where this | |
442e3cb9 | 4726 | could lead to incorrect behavior. The manual recommends CSYNC, while |
9e6a0967 | 4727 | VDSP seems to use NOPs (even though its corresponding compiler option is |
4728 | named CSYNC). | |
4729 | ||
4730 | When optimizing for speed, we emit NOPs, which seems faster than a CSYNC. | |
4731 | When optimizing for size, we turn the branch into a predicted taken one. | |
4732 | This may be slower due to mispredicts, but saves code size. */ | |
4733 | ||
4734 | static void | |
4735 | bfin_reorg (void) | |
4736 | { | |
771ce05e | 4737 | rtx insn, next; |
4738 | rtx last_condjump = NULL_RTX; | |
9e6a0967 | 4739 | int cycles_since_jump = INT_MAX; |
4740 | ||
48df5a7f | 4741 | /* We are freeing block_for_insn in the toplev to keep compatibility |
4742 | with old MDEP_REORGS that are not CFG based. Recompute it now. */ | |
4743 | compute_bb_for_insn (); | |
4744 | ||
4745 | if (bfin_flag_schedule_insns2) | |
4746 | { | |
4747 | splitting_for_sched = 1; | |
d18119ae | 4748 | split_all_insns (); |
48df5a7f | 4749 | splitting_for_sched = 0; |
4750 | ||
48df5a7f | 4751 | timevar_push (TV_SCHED2); |
4752 | schedule_insns (); | |
4753 | timevar_pop (TV_SCHED2); | |
4754 | ||
905ea169 | 4755 | /* Examine the schedule and insert nops as necessary for 64-bit parallel |
48df5a7f | 4756 | instructions. */ |
4757 | bfin_gen_bundles (); | |
4758 | } | |
4759 | ||
d18119ae | 4760 | df_analyze (); |
4761 | ||
3c1905a4 | 4762 | /* Doloop optimization */ |
4763 | if (cfun->machine->has_hardware_loops) | |
4764 | bfin_reorg_loops (dump_file); | |
4765 | ||
709b2de5 | 4766 | if (! ENABLE_WA_SPECULATIVE_LOADS && ! ENABLE_WA_SPECULATIVE_SYNCS) |
9e6a0967 | 4767 | return; |
4768 | ||
b00f0d99 | 4769 | /* First pass: find predicted-false branches; if something after them |
4770 | needs nops, insert them or change the branch to predict true. */ | |
771ce05e | 4771 | for (insn = get_insns (); insn; insn = next) |
9e6a0967 | 4772 | { |
4773 | rtx pat; | |
4774 | ||
771ce05e | 4775 | next = find_next_insn_start (insn); |
4776 | ||
9e6a0967 | 4777 | if (NOTE_P (insn) || BARRIER_P (insn) || LABEL_P (insn)) |
4778 | continue; | |
4779 | ||
4780 | pat = PATTERN (insn); | |
4781 | if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER | |
4782 | || GET_CODE (pat) == ASM_INPUT || GET_CODE (pat) == ADDR_VEC | |
4783 | || GET_CODE (pat) == ADDR_DIFF_VEC || asm_noperands (pat) >= 0) | |
4784 | continue; | |
4785 | ||
4786 | if (JUMP_P (insn)) | |
4787 | { | |
4788 | if (any_condjump_p (insn) | |
4789 | && ! cbranch_predicted_taken_p (insn)) | |
4790 | { | |
4791 | last_condjump = insn; | |
4792 | cycles_since_jump = 0; | |
4793 | } | |
4794 | else | |
4795 | cycles_since_jump = INT_MAX; | |
4796 | } | |
4797 | else if (INSN_P (insn)) | |
4798 | { | |
771ce05e | 4799 | rtx load_insn = find_load (insn); |
48df5a7f | 4800 | enum attr_type type = type_for_anomaly (insn); |
b00f0d99 | 4801 | int delay_needed = 0; |
9e6a0967 | 4802 | if (cycles_since_jump < INT_MAX) |
4803 | cycles_since_jump++; | |
4804 | ||
709b2de5 | 4805 | if (load_insn && ENABLE_WA_SPECULATIVE_LOADS) |
b00f0d99 | 4806 | { |
771ce05e | 4807 | if (trapping_loads_p (load_insn)) |
b00f0d99 | 4808 | delay_needed = 3; |
4809 | } | |
709b2de5 | 4810 | else if (type == TYPE_SYNC && ENABLE_WA_SPECULATIVE_SYNCS) |
b00f0d99 | 4811 | delay_needed = 4; |
4812 | ||
4813 | if (delay_needed > cycles_since_jump) | |
9e6a0967 | 4814 | { |
4815 | rtx pat; | |
b00f0d99 | 4816 | int num_clobbers; |
4817 | rtx *op = recog_data.operand; | |
9e6a0967 | 4818 | |
b00f0d99 | 4819 | delay_needed -= cycles_since_jump; |
4820 | ||
4821 | extract_insn (last_condjump); | |
4822 | if (optimize_size) | |
9e6a0967 | 4823 | { |
b00f0d99 | 4824 | pat = gen_cbranch_predicted_taken (op[0], op[1], op[2], |
4825 | op[3]); | |
9e6a0967 | 4826 | cycles_since_jump = INT_MAX; |
4827 | } | |
b00f0d99 | 4828 | else |
4829 | /* Do not adjust cycles_since_jump in this case, so that | |
4830 | we'll increase the number of NOPs for a subsequent insn | |
4831 | if necessary. */ | |
4832 | pat = gen_cbranch_with_nops (op[0], op[1], op[2], op[3], | |
4833 | GEN_INT (delay_needed)); | |
4834 | PATTERN (last_condjump) = pat; | |
4835 | INSN_CODE (last_condjump) = recog (pat, insn, &num_clobbers); | |
4836 | } | |
4837 | } | |
4838 | } | |
4839 | /* Second pass: for predicted-true branches, see if anything at the | |
4840 | branch destination needs extra nops. */ | |
709b2de5 | 4841 | if (! ENABLE_WA_SPECULATIVE_SYNCS) |
b00f0d99 | 4842 | return; |
4843 | ||
f5c2bcb7 | 4844 | if (! ENABLE_WA_RETS) |
4845 | return; | |
4846 | ||
b00f0d99 | 4847 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
4848 | { | |
4849 | if (JUMP_P (insn) | |
4850 | && any_condjump_p (insn) | |
4851 | && (INSN_CODE (insn) == CODE_FOR_cbranch_predicted_taken | |
4852 | || cbranch_predicted_taken_p (insn))) | |
4853 | { | |
4854 | rtx target = JUMP_LABEL (insn); | |
4855 | rtx label = target; | |
4856 | cycles_since_jump = 0; | |
4857 | for (; target && cycles_since_jump < 3; target = NEXT_INSN (target)) | |
4858 | { | |
4859 | rtx pat; | |
4860 | ||
4861 | if (NOTE_P (target) || BARRIER_P (target) || LABEL_P (target)) | |
4862 | continue; | |
4863 | ||
4864 | pat = PATTERN (target); | |
4865 | if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER | |
4866 | || GET_CODE (pat) == ASM_INPUT || GET_CODE (pat) == ADDR_VEC | |
4867 | || GET_CODE (pat) == ADDR_DIFF_VEC || asm_noperands (pat) >= 0) | |
4868 | continue; | |
4869 | ||
4870 | if (INSN_P (target)) | |
4871 | { | |
48df5a7f | 4872 | enum attr_type type = type_for_anomaly (target); |
b00f0d99 | 4873 | int delay_needed = 0; |
4874 | if (cycles_since_jump < INT_MAX) | |
4875 | cycles_since_jump++; | |
4876 | ||
709b2de5 | 4877 | if (type == TYPE_SYNC && ENABLE_WA_SPECULATIVE_SYNCS) |
b00f0d99 | 4878 | delay_needed = 2; |
4879 | ||
4880 | if (delay_needed > cycles_since_jump) | |
4881 | { | |
4882 | rtx prev = prev_real_insn (label); | |
4883 | delay_needed -= cycles_since_jump; | |
4884 | if (dump_file) | |
4885 | fprintf (dump_file, "Adding %d nops after %d\n", | |
4886 | delay_needed, INSN_UID (label)); | |
4887 | if (JUMP_P (prev) | |
4888 | && INSN_CODE (prev) == CODE_FOR_cbranch_with_nops) | |
4889 | { | |
4890 | rtx x; | |
4891 | HOST_WIDE_INT v; | |
4892 | ||
4893 | if (dump_file) | |
4894 | fprintf (dump_file, | |
4895 | "Reducing nops on insn %d.\n", | |
4896 | INSN_UID (prev)); | |
4897 | x = PATTERN (prev); | |
4898 | x = XVECEXP (x, 0, 1); | |
4899 | v = INTVAL (XVECEXP (x, 0, 0)) - delay_needed; | |
4900 | XVECEXP (x, 0, 0) = GEN_INT (v); | |
4901 | } | |
4902 | while (delay_needed-- > 0) | |
4903 | emit_insn_after (gen_nop (), label); | |
4904 | break; | |
4905 | } | |
4906 | } | |
9e6a0967 | 4907 | } |
4908 | } | |
4909 | } | |
48df5a7f | 4910 | |
4911 | if (bfin_flag_var_tracking) | |
4912 | { | |
4913 | timevar_push (TV_VAR_TRACKING); | |
4914 | variable_tracking_main (); | |
d18119ae | 4915 | reorder_var_tracking_notes (); |
48df5a7f | 4916 | timevar_pop (TV_VAR_TRACKING); |
4917 | } | |
314966f4 | 4918 | df_finish_pass (false); |
9e6a0967 | 4919 | } |
4920 | \f | |
4921 | /* Handle interrupt_handler, exception_handler and nmi_handler function | |
4922 | attributes; arguments as in struct attribute_spec.handler. */ | |
4923 | ||
4924 | static tree | |
4925 | handle_int_attribute (tree *node, tree name, | |
4926 | tree args ATTRIBUTE_UNUSED, | |
4927 | int flags ATTRIBUTE_UNUSED, | |
4928 | bool *no_add_attrs) | |
4929 | { | |
4930 | tree x = *node; | |
4931 | if (TREE_CODE (x) == FUNCTION_DECL) | |
4932 | x = TREE_TYPE (x); | |
4933 | ||
4934 | if (TREE_CODE (x) != FUNCTION_TYPE) | |
4935 | { | |
9b2d6d13 | 4936 | warning (OPT_Wattributes, "%qs attribute only applies to functions", |
9e6a0967 | 4937 | IDENTIFIER_POINTER (name)); |
4938 | *no_add_attrs = true; | |
4939 | } | |
4940 | else if (funkind (x) != SUBROUTINE) | |
4941 | error ("multiple function type attributes specified"); | |
4942 | ||
4943 | return NULL_TREE; | |
4944 | } | |
4945 | ||
4946 | /* Return 0 if the attributes for two types are incompatible, 1 if they | |
4947 | are compatible, and 2 if they are nearly compatible (which causes a | |
4948 | warning to be generated). */ | |
4949 | ||
4950 | static int | |
a9f1838b | 4951 | bfin_comp_type_attributes (const_tree type1, const_tree type2) |
9e6a0967 | 4952 | { |
4953 | e_funkind kind1, kind2; | |
4954 | ||
4955 | if (TREE_CODE (type1) != FUNCTION_TYPE) | |
4956 | return 1; | |
4957 | ||
4958 | kind1 = funkind (type1); | |
4959 | kind2 = funkind (type2); | |
4960 | ||
4961 | if (kind1 != kind2) | |
4962 | return 0; | |
4963 | ||
4964 | /* Check for mismatched modifiers */ | |
4965 | if (!lookup_attribute ("nesting", TYPE_ATTRIBUTES (type1)) | |
4966 | != !lookup_attribute ("nesting", TYPE_ATTRIBUTES (type2))) | |
4967 | return 0; | |
4968 | ||
4969 | if (!lookup_attribute ("saveall", TYPE_ATTRIBUTES (type1)) | |
4970 | != !lookup_attribute ("saveall", TYPE_ATTRIBUTES (type2))) | |
4971 | return 0; | |
4972 | ||
4973 | if (!lookup_attribute ("kspisusp", TYPE_ATTRIBUTES (type1)) | |
4974 | != !lookup_attribute ("kspisusp", TYPE_ATTRIBUTES (type2))) | |
4975 | return 0; | |
4976 | ||
7b6ef6dd | 4977 | if (!lookup_attribute ("longcall", TYPE_ATTRIBUTES (type1)) |
4978 | != !lookup_attribute ("longcall", TYPE_ATTRIBUTES (type2))) | |
4979 | return 0; | |
4980 | ||
9e6a0967 | 4981 | return 1; |
4982 | } | |
4983 | ||
7b6ef6dd | 4984 | /* Handle a "longcall" or "shortcall" attribute; arguments as in |
4985 | struct attribute_spec.handler. */ | |
4986 | ||
4987 | static tree | |
4988 | bfin_handle_longcall_attribute (tree *node, tree name, | |
4989 | tree args ATTRIBUTE_UNUSED, | |
4990 | int flags ATTRIBUTE_UNUSED, | |
4991 | bool *no_add_attrs) | |
4992 | { | |
4993 | if (TREE_CODE (*node) != FUNCTION_TYPE | |
4994 | && TREE_CODE (*node) != FIELD_DECL | |
4995 | && TREE_CODE (*node) != TYPE_DECL) | |
4996 | { | |
4997 | warning (OPT_Wattributes, "`%s' attribute only applies to functions", | |
4998 | IDENTIFIER_POINTER (name)); | |
4999 | *no_add_attrs = true; | |
5000 | } | |
5001 | ||
5002 | if ((strcmp (IDENTIFIER_POINTER (name), "longcall") == 0 | |
5003 | && lookup_attribute ("shortcall", TYPE_ATTRIBUTES (*node))) | |
5004 | || (strcmp (IDENTIFIER_POINTER (name), "shortcall") == 0 | |
5005 | && lookup_attribute ("longcall", TYPE_ATTRIBUTES (*node)))) | |
5006 | { | |
5007 | warning (OPT_Wattributes, | |
5008 | "can't apply both longcall and shortcall attributes to the same function"); | |
5009 | *no_add_attrs = true; | |
5010 | } | |
5011 | ||
5012 | return NULL_TREE; | |
5013 | } | |
5014 | ||
fc8aef7f | 5015 | /* Handle a "l1_text" attribute; arguments as in |
5016 | struct attribute_spec.handler. */ | |
5017 | ||
5018 | static tree | |
5019 | bfin_handle_l1_text_attribute (tree *node, tree name, tree ARG_UNUSED (args), | |
5020 | int ARG_UNUSED (flags), bool *no_add_attrs) | |
5021 | { | |
5022 | tree decl = *node; | |
5023 | ||
5024 | if (TREE_CODE (decl) != FUNCTION_DECL) | |
5025 | { | |
5026 | error ("`%s' attribute only applies to functions", | |
5027 | IDENTIFIER_POINTER (name)); | |
5028 | *no_add_attrs = true; | |
5029 | } | |
5030 | ||
5031 | /* The decl may have already been given a section attribute | |
5032 | from a previous declaration. Ensure they match. */ | |
5033 | else if (DECL_SECTION_NAME (decl) != NULL_TREE | |
5034 | && strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl)), | |
5035 | ".l1.text") != 0) | |
5036 | { | |
5037 | error ("section of %q+D conflicts with previous declaration", | |
5038 | decl); | |
5039 | *no_add_attrs = true; | |
5040 | } | |
5041 | else | |
5042 | DECL_SECTION_NAME (decl) = build_string (9, ".l1.text"); | |
5043 | ||
5044 | return NULL_TREE; | |
5045 | } | |
5046 | ||
5047 | /* Handle a "l1_data", "l1_data_A" or "l1_data_B" attribute; | |
5048 | arguments as in struct attribute_spec.handler. */ | |
5049 | ||
5050 | static tree | |
5051 | bfin_handle_l1_data_attribute (tree *node, tree name, tree ARG_UNUSED (args), | |
5052 | int ARG_UNUSED (flags), bool *no_add_attrs) | |
5053 | { | |
5054 | tree decl = *node; | |
5055 | ||
5056 | if (TREE_CODE (decl) != VAR_DECL) | |
5057 | { | |
5058 | error ("`%s' attribute only applies to variables", | |
5059 | IDENTIFIER_POINTER (name)); | |
5060 | *no_add_attrs = true; | |
5061 | } | |
5062 | else if (current_function_decl != NULL_TREE | |
5063 | && !TREE_STATIC (decl)) | |
5064 | { | |
5065 | error ("`%s' attribute cannot be specified for local variables", | |
5066 | IDENTIFIER_POINTER (name)); | |
5067 | *no_add_attrs = true; | |
5068 | } | |
5069 | else | |
5070 | { | |
5071 | const char *section_name; | |
5072 | ||
5073 | if (strcmp (IDENTIFIER_POINTER (name), "l1_data") == 0) | |
5074 | section_name = ".l1.data"; | |
5075 | else if (strcmp (IDENTIFIER_POINTER (name), "l1_data_A") == 0) | |
5076 | section_name = ".l1.data.A"; | |
5077 | else if (strcmp (IDENTIFIER_POINTER (name), "l1_data_B") == 0) | |
5078 | section_name = ".l1.data.B"; | |
5079 | else | |
5080 | gcc_unreachable (); | |
5081 | ||
5082 | /* The decl may have already been given a section attribute | |
5083 | from a previous declaration. Ensure they match. */ | |
5084 | if (DECL_SECTION_NAME (decl) != NULL_TREE | |
5085 | && strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl)), | |
5086 | section_name) != 0) | |
5087 | { | |
5088 | error ("section of %q+D conflicts with previous declaration", | |
5089 | decl); | |
5090 | *no_add_attrs = true; | |
5091 | } | |
5092 | else | |
5093 | DECL_SECTION_NAME (decl) | |
5094 | = build_string (strlen (section_name) + 1, section_name); | |
5095 | } | |
5096 | ||
5097 | return NULL_TREE; | |
5098 | } | |
5099 | ||
9e6a0967 | 5100 | /* Table of valid machine attributes. */ |
5101 | const struct attribute_spec bfin_attribute_table[] = | |
5102 | { | |
5103 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ | |
5104 | { "interrupt_handler", 0, 0, false, true, true, handle_int_attribute }, | |
5105 | { "exception_handler", 0, 0, false, true, true, handle_int_attribute }, | |
5106 | { "nmi_handler", 0, 0, false, true, true, handle_int_attribute }, | |
5107 | { "nesting", 0, 0, false, true, true, NULL }, | |
5108 | { "kspisusp", 0, 0, false, true, true, NULL }, | |
5109 | { "saveall", 0, 0, false, true, true, NULL }, | |
7b6ef6dd | 5110 | { "longcall", 0, 0, false, true, true, bfin_handle_longcall_attribute }, |
5111 | { "shortcall", 0, 0, false, true, true, bfin_handle_longcall_attribute }, | |
fc8aef7f | 5112 | { "l1_text", 0, 0, true, false, false, bfin_handle_l1_text_attribute }, |
5113 | { "l1_data", 0, 0, true, false, false, bfin_handle_l1_data_attribute }, | |
5114 | { "l1_data_A", 0, 0, true, false, false, bfin_handle_l1_data_attribute }, | |
5115 | { "l1_data_B", 0, 0, true, false, false, bfin_handle_l1_data_attribute }, | |
9e6a0967 | 5116 | { NULL, 0, 0, false, false, false, NULL } |
5117 | }; | |
5118 | \f | |
55be0e32 | 5119 | /* Implementation of TARGET_ASM_INTEGER. When using FD-PIC, we need to |
5120 | tell the assembler to generate pointers to function descriptors in | |
5121 | some cases. */ | |
5122 | ||
5123 | static bool | |
5124 | bfin_assemble_integer (rtx value, unsigned int size, int aligned_p) | |
5125 | { | |
5126 | if (TARGET_FDPIC && size == UNITS_PER_WORD) | |
5127 | { | |
5128 | if (GET_CODE (value) == SYMBOL_REF | |
5129 | && SYMBOL_REF_FUNCTION_P (value)) | |
5130 | { | |
5131 | fputs ("\t.picptr\tfuncdesc(", asm_out_file); | |
5132 | output_addr_const (asm_out_file, value); | |
5133 | fputs (")\n", asm_out_file); | |
5134 | return true; | |
5135 | } | |
5136 | if (!aligned_p) | |
5137 | { | |
5138 | /* We've set the unaligned SI op to NULL, so we always have to | |
5139 | handle the unaligned case here. */ | |
5140 | assemble_integer_with_op ("\t.4byte\t", value); | |
5141 | return true; | |
5142 | } | |
5143 | } | |
5144 | return default_assemble_integer (value, size, aligned_p); | |
5145 | } | |
5146 | \f | |
9e6a0967 | 5147 | /* Output the assembler code for a thunk function. THUNK_DECL is the |
5148 | declaration for the thunk function itself, FUNCTION is the decl for | |
5149 | the target function. DELTA is an immediate constant offset to be | |
5150 | added to THIS. If VCALL_OFFSET is nonzero, the word at | |
5151 | *(*this + vcall_offset) should be added to THIS. */ | |
5152 | ||
5153 | static void | |
5154 | bfin_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED, | |
5155 | tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta, | |
5156 | HOST_WIDE_INT vcall_offset, tree function) | |
5157 | { | |
5158 | rtx xops[3]; | |
5159 | /* The this parameter is passed as the first argument. */ | |
8deb3959 | 5160 | rtx this_rtx = gen_rtx_REG (Pmode, REG_R0); |
9e6a0967 | 5161 | |
5162 | /* Adjust the this parameter by a fixed constant. */ | |
5163 | if (delta) | |
5164 | { | |
8deb3959 | 5165 | xops[1] = this_rtx; |
9e6a0967 | 5166 | if (delta >= -64 && delta <= 63) |
5167 | { | |
5168 | xops[0] = GEN_INT (delta); | |
5169 | output_asm_insn ("%1 += %0;", xops); | |
5170 | } | |
5171 | else if (delta >= -128 && delta < -64) | |
5172 | { | |
5173 | xops[0] = GEN_INT (delta + 64); | |
5174 | output_asm_insn ("%1 += -64; %1 += %0;", xops); | |
5175 | } | |
5176 | else if (delta > 63 && delta <= 126) | |
5177 | { | |
5178 | xops[0] = GEN_INT (delta - 63); | |
5179 | output_asm_insn ("%1 += 63; %1 += %0;", xops); | |
5180 | } | |
5181 | else | |
5182 | { | |
5183 | xops[0] = GEN_INT (delta); | |
5184 | output_asm_insn ("r3.l = %h0; r3.h = %d0; %1 = %1 + r3;", xops); | |
5185 | } | |
5186 | } | |
5187 | ||
5188 | /* Adjust the this parameter by a value stored in the vtable. */ | |
5189 | if (vcall_offset) | |
5190 | { | |
5191 | rtx p2tmp = gen_rtx_REG (Pmode, REG_P2); | |
7943de3b | 5192 | rtx tmp = gen_rtx_REG (Pmode, REG_R3); |
9e6a0967 | 5193 | |
5194 | xops[1] = tmp; | |
5195 | xops[2] = p2tmp; | |
5196 | output_asm_insn ("%2 = r0; %2 = [%2];", xops); | |
5197 | ||
5198 | /* Adjust the this parameter. */ | |
5199 | xops[0] = gen_rtx_MEM (Pmode, plus_constant (p2tmp, vcall_offset)); | |
5200 | if (!memory_operand (xops[0], Pmode)) | |
5201 | { | |
5202 | rtx tmp2 = gen_rtx_REG (Pmode, REG_P1); | |
5203 | xops[0] = GEN_INT (vcall_offset); | |
5204 | xops[1] = tmp2; | |
5205 | output_asm_insn ("%h1 = %h0; %d1 = %d0; %2 = %2 + %1", xops); | |
5206 | xops[0] = gen_rtx_MEM (Pmode, p2tmp); | |
5207 | } | |
8deb3959 | 5208 | xops[2] = this_rtx; |
9e6a0967 | 5209 | output_asm_insn ("%1 = %0; %2 = %2 + %1;", xops); |
5210 | } | |
5211 | ||
5212 | xops[0] = XEXP (DECL_RTL (function), 0); | |
5213 | if (1 || !flag_pic || (*targetm.binds_local_p) (function)) | |
5214 | output_asm_insn ("jump.l\t%P0", xops); | |
5215 | } | |
5216 | \f | |
6e6ce962 | 5217 | /* Codes for all the Blackfin builtins. */ |
5218 | enum bfin_builtins | |
5219 | { | |
5220 | BFIN_BUILTIN_CSYNC, | |
5221 | BFIN_BUILTIN_SSYNC, | |
44395948 | 5222 | BFIN_BUILTIN_ONES, |
f9edc33d | 5223 | BFIN_BUILTIN_COMPOSE_2X16, |
5224 | BFIN_BUILTIN_EXTRACTLO, | |
5225 | BFIN_BUILTIN_EXTRACTHI, | |
5226 | ||
5227 | BFIN_BUILTIN_SSADD_2X16, | |
5228 | BFIN_BUILTIN_SSSUB_2X16, | |
5229 | BFIN_BUILTIN_SSADDSUB_2X16, | |
5230 | BFIN_BUILTIN_SSSUBADD_2X16, | |
5231 | BFIN_BUILTIN_MULT_2X16, | |
5232 | BFIN_BUILTIN_MULTR_2X16, | |
5233 | BFIN_BUILTIN_NEG_2X16, | |
5234 | BFIN_BUILTIN_ABS_2X16, | |
5235 | BFIN_BUILTIN_MIN_2X16, | |
5236 | BFIN_BUILTIN_MAX_2X16, | |
5237 | ||
5238 | BFIN_BUILTIN_SSADD_1X16, | |
5239 | BFIN_BUILTIN_SSSUB_1X16, | |
5240 | BFIN_BUILTIN_MULT_1X16, | |
5241 | BFIN_BUILTIN_MULTR_1X16, | |
5242 | BFIN_BUILTIN_NORM_1X16, | |
5243 | BFIN_BUILTIN_NEG_1X16, | |
5244 | BFIN_BUILTIN_ABS_1X16, | |
5245 | BFIN_BUILTIN_MIN_1X16, | |
5246 | BFIN_BUILTIN_MAX_1X16, | |
5247 | ||
a4317a50 | 5248 | BFIN_BUILTIN_SUM_2X16, |
f9edc33d | 5249 | BFIN_BUILTIN_DIFFHL_2X16, |
5250 | BFIN_BUILTIN_DIFFLH_2X16, | |
5251 | ||
5252 | BFIN_BUILTIN_SSADD_1X32, | |
5253 | BFIN_BUILTIN_SSSUB_1X32, | |
5254 | BFIN_BUILTIN_NORM_1X32, | |
a4317a50 | 5255 | BFIN_BUILTIN_ROUND_1X32, |
f9edc33d | 5256 | BFIN_BUILTIN_NEG_1X32, |
a4317a50 | 5257 | BFIN_BUILTIN_ABS_1X32, |
f9edc33d | 5258 | BFIN_BUILTIN_MIN_1X32, |
5259 | BFIN_BUILTIN_MAX_1X32, | |
5260 | BFIN_BUILTIN_MULT_1X32, | |
a4317a50 | 5261 | BFIN_BUILTIN_MULT_1X32X32, |
5262 | BFIN_BUILTIN_MULT_1X32X32NS, | |
f9edc33d | 5263 | |
5264 | BFIN_BUILTIN_MULHISILL, | |
5265 | BFIN_BUILTIN_MULHISILH, | |
5266 | BFIN_BUILTIN_MULHISIHL, | |
5267 | BFIN_BUILTIN_MULHISIHH, | |
5268 | ||
5269 | BFIN_BUILTIN_LSHIFT_1X16, | |
5270 | BFIN_BUILTIN_LSHIFT_2X16, | |
5271 | BFIN_BUILTIN_SSASHIFT_1X16, | |
5272 | BFIN_BUILTIN_SSASHIFT_2X16, | |
a4317a50 | 5273 | BFIN_BUILTIN_SSASHIFT_1X32, |
f9edc33d | 5274 | |
5275 | BFIN_BUILTIN_CPLX_MUL_16, | |
5276 | BFIN_BUILTIN_CPLX_MAC_16, | |
5277 | BFIN_BUILTIN_CPLX_MSU_16, | |
5278 | ||
44395948 | 5279 | BFIN_BUILTIN_CPLX_MUL_16_S40, |
5280 | BFIN_BUILTIN_CPLX_MAC_16_S40, | |
5281 | BFIN_BUILTIN_CPLX_MSU_16_S40, | |
5282 | ||
5283 | BFIN_BUILTIN_CPLX_SQU, | |
5284 | ||
16f1c0ab | 5285 | BFIN_BUILTIN_LOADBYTES, |
5286 | ||
6e6ce962 | 5287 | BFIN_BUILTIN_MAX |
5288 | }; | |
5289 | ||
684389d2 | 5290 | #define def_builtin(NAME, TYPE, CODE) \ |
5291 | do { \ | |
54be5d7e | 5292 | add_builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \ |
5293 | NULL, NULL_TREE); \ | |
e43914a7 | 5294 | } while (0) |
5295 | ||
5296 | /* Set up all builtin functions for this target. */ | |
5297 | static void | |
5298 | bfin_init_builtins (void) | |
5299 | { | |
f9edc33d | 5300 | tree V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode); |
e43914a7 | 5301 | tree void_ftype_void |
5302 | = build_function_type (void_type_node, void_list_node); | |
f9edc33d | 5303 | tree short_ftype_short |
5304 | = build_function_type_list (short_integer_type_node, short_integer_type_node, | |
5305 | NULL_TREE); | |
5306 | tree short_ftype_int_int | |
5307 | = build_function_type_list (short_integer_type_node, integer_type_node, | |
5308 | integer_type_node, NULL_TREE); | |
5309 | tree int_ftype_int_int | |
5310 | = build_function_type_list (integer_type_node, integer_type_node, | |
5311 | integer_type_node, NULL_TREE); | |
5312 | tree int_ftype_int | |
5313 | = build_function_type_list (integer_type_node, integer_type_node, | |
5314 | NULL_TREE); | |
5315 | tree short_ftype_int | |
5316 | = build_function_type_list (short_integer_type_node, integer_type_node, | |
5317 | NULL_TREE); | |
5318 | tree int_ftype_v2hi_v2hi | |
5319 | = build_function_type_list (integer_type_node, V2HI_type_node, | |
5320 | V2HI_type_node, NULL_TREE); | |
5321 | tree v2hi_ftype_v2hi_v2hi | |
5322 | = build_function_type_list (V2HI_type_node, V2HI_type_node, | |
5323 | V2HI_type_node, NULL_TREE); | |
5324 | tree v2hi_ftype_v2hi_v2hi_v2hi | |
5325 | = build_function_type_list (V2HI_type_node, V2HI_type_node, | |
5326 | V2HI_type_node, V2HI_type_node, NULL_TREE); | |
5327 | tree v2hi_ftype_int_int | |
5328 | = build_function_type_list (V2HI_type_node, integer_type_node, | |
5329 | integer_type_node, NULL_TREE); | |
5330 | tree v2hi_ftype_v2hi_int | |
5331 | = build_function_type_list (V2HI_type_node, V2HI_type_node, | |
5332 | integer_type_node, NULL_TREE); | |
5333 | tree int_ftype_short_short | |
5334 | = build_function_type_list (integer_type_node, short_integer_type_node, | |
5335 | short_integer_type_node, NULL_TREE); | |
5336 | tree v2hi_ftype_v2hi | |
5337 | = build_function_type_list (V2HI_type_node, V2HI_type_node, NULL_TREE); | |
5338 | tree short_ftype_v2hi | |
5339 | = build_function_type_list (short_integer_type_node, V2HI_type_node, | |
5340 | NULL_TREE); | |
16f1c0ab | 5341 | tree int_ftype_pint |
5342 | = build_function_type_list (integer_type_node, | |
5343 | build_pointer_type (integer_type_node), | |
5344 | NULL_TREE); | |
5345 | ||
e43914a7 | 5346 | /* Add the remaining MMX insns with somewhat more complicated types. */ |
5347 | def_builtin ("__builtin_bfin_csync", void_ftype_void, BFIN_BUILTIN_CSYNC); | |
5348 | def_builtin ("__builtin_bfin_ssync", void_ftype_void, BFIN_BUILTIN_SSYNC); | |
f9edc33d | 5349 | |
44395948 | 5350 | def_builtin ("__builtin_bfin_ones", short_ftype_int, BFIN_BUILTIN_ONES); |
5351 | ||
f9edc33d | 5352 | def_builtin ("__builtin_bfin_compose_2x16", v2hi_ftype_int_int, |
5353 | BFIN_BUILTIN_COMPOSE_2X16); | |
5354 | def_builtin ("__builtin_bfin_extract_hi", short_ftype_v2hi, | |
5355 | BFIN_BUILTIN_EXTRACTHI); | |
5356 | def_builtin ("__builtin_bfin_extract_lo", short_ftype_v2hi, | |
5357 | BFIN_BUILTIN_EXTRACTLO); | |
5358 | ||
5359 | def_builtin ("__builtin_bfin_min_fr2x16", v2hi_ftype_v2hi_v2hi, | |
5360 | BFIN_BUILTIN_MIN_2X16); | |
5361 | def_builtin ("__builtin_bfin_max_fr2x16", v2hi_ftype_v2hi_v2hi, | |
5362 | BFIN_BUILTIN_MAX_2X16); | |
5363 | ||
5364 | def_builtin ("__builtin_bfin_add_fr2x16", v2hi_ftype_v2hi_v2hi, | |
5365 | BFIN_BUILTIN_SSADD_2X16); | |
5366 | def_builtin ("__builtin_bfin_sub_fr2x16", v2hi_ftype_v2hi_v2hi, | |
5367 | BFIN_BUILTIN_SSSUB_2X16); | |
5368 | def_builtin ("__builtin_bfin_dspaddsubsat", v2hi_ftype_v2hi_v2hi, | |
5369 | BFIN_BUILTIN_SSADDSUB_2X16); | |
5370 | def_builtin ("__builtin_bfin_dspsubaddsat", v2hi_ftype_v2hi_v2hi, | |
5371 | BFIN_BUILTIN_SSSUBADD_2X16); | |
5372 | def_builtin ("__builtin_bfin_mult_fr2x16", v2hi_ftype_v2hi_v2hi, | |
5373 | BFIN_BUILTIN_MULT_2X16); | |
5374 | def_builtin ("__builtin_bfin_multr_fr2x16", v2hi_ftype_v2hi_v2hi, | |
5375 | BFIN_BUILTIN_MULTR_2X16); | |
5376 | def_builtin ("__builtin_bfin_negate_fr2x16", v2hi_ftype_v2hi, | |
5377 | BFIN_BUILTIN_NEG_2X16); | |
5378 | def_builtin ("__builtin_bfin_abs_fr2x16", v2hi_ftype_v2hi, | |
5379 | BFIN_BUILTIN_ABS_2X16); | |
5380 | ||
44395948 | 5381 | def_builtin ("__builtin_bfin_min_fr1x16", short_ftype_int_int, |
5382 | BFIN_BUILTIN_MIN_1X16); | |
5383 | def_builtin ("__builtin_bfin_max_fr1x16", short_ftype_int_int, | |
5384 | BFIN_BUILTIN_MAX_1X16); | |
5385 | ||
f9edc33d | 5386 | def_builtin ("__builtin_bfin_add_fr1x16", short_ftype_int_int, |
5387 | BFIN_BUILTIN_SSADD_1X16); | |
5388 | def_builtin ("__builtin_bfin_sub_fr1x16", short_ftype_int_int, | |
5389 | BFIN_BUILTIN_SSSUB_1X16); | |
5390 | def_builtin ("__builtin_bfin_mult_fr1x16", short_ftype_int_int, | |
5391 | BFIN_BUILTIN_MULT_1X16); | |
5392 | def_builtin ("__builtin_bfin_multr_fr1x16", short_ftype_int_int, | |
5393 | BFIN_BUILTIN_MULTR_1X16); | |
5394 | def_builtin ("__builtin_bfin_negate_fr1x16", short_ftype_short, | |
5395 | BFIN_BUILTIN_NEG_1X16); | |
5396 | def_builtin ("__builtin_bfin_abs_fr1x16", short_ftype_short, | |
5397 | BFIN_BUILTIN_ABS_1X16); | |
5398 | def_builtin ("__builtin_bfin_norm_fr1x16", short_ftype_int, | |
5399 | BFIN_BUILTIN_NORM_1X16); | |
5400 | ||
a4317a50 | 5401 | def_builtin ("__builtin_bfin_sum_fr2x16", short_ftype_v2hi, |
5402 | BFIN_BUILTIN_SUM_2X16); | |
f9edc33d | 5403 | def_builtin ("__builtin_bfin_diff_hl_fr2x16", short_ftype_v2hi, |
5404 | BFIN_BUILTIN_DIFFHL_2X16); | |
5405 | def_builtin ("__builtin_bfin_diff_lh_fr2x16", short_ftype_v2hi, | |
5406 | BFIN_BUILTIN_DIFFLH_2X16); | |
5407 | ||
5408 | def_builtin ("__builtin_bfin_mulhisill", int_ftype_v2hi_v2hi, | |
5409 | BFIN_BUILTIN_MULHISILL); | |
5410 | def_builtin ("__builtin_bfin_mulhisihl", int_ftype_v2hi_v2hi, | |
5411 | BFIN_BUILTIN_MULHISIHL); | |
5412 | def_builtin ("__builtin_bfin_mulhisilh", int_ftype_v2hi_v2hi, | |
5413 | BFIN_BUILTIN_MULHISILH); | |
5414 | def_builtin ("__builtin_bfin_mulhisihh", int_ftype_v2hi_v2hi, | |
5415 | BFIN_BUILTIN_MULHISIHH); | |
5416 | ||
44395948 | 5417 | def_builtin ("__builtin_bfin_min_fr1x32", int_ftype_int_int, |
5418 | BFIN_BUILTIN_MIN_1X32); | |
5419 | def_builtin ("__builtin_bfin_max_fr1x32", int_ftype_int_int, | |
5420 | BFIN_BUILTIN_MAX_1X32); | |
5421 | ||
f9edc33d | 5422 | def_builtin ("__builtin_bfin_add_fr1x32", int_ftype_int_int, |
5423 | BFIN_BUILTIN_SSADD_1X32); | |
5424 | def_builtin ("__builtin_bfin_sub_fr1x32", int_ftype_int_int, | |
5425 | BFIN_BUILTIN_SSSUB_1X32); | |
5426 | def_builtin ("__builtin_bfin_negate_fr1x32", int_ftype_int, | |
5427 | BFIN_BUILTIN_NEG_1X32); | |
a4317a50 | 5428 | def_builtin ("__builtin_bfin_abs_fr1x32", int_ftype_int, |
5429 | BFIN_BUILTIN_ABS_1X32); | |
f9edc33d | 5430 | def_builtin ("__builtin_bfin_norm_fr1x32", short_ftype_int, |
5431 | BFIN_BUILTIN_NORM_1X32); | |
a4317a50 | 5432 | def_builtin ("__builtin_bfin_round_fr1x32", short_ftype_int, |
5433 | BFIN_BUILTIN_ROUND_1X32); | |
f9edc33d | 5434 | def_builtin ("__builtin_bfin_mult_fr1x32", int_ftype_short_short, |
5435 | BFIN_BUILTIN_MULT_1X32); | |
a4317a50 | 5436 | def_builtin ("__builtin_bfin_mult_fr1x32x32", int_ftype_int_int, |
5437 | BFIN_BUILTIN_MULT_1X32X32); | |
5438 | def_builtin ("__builtin_bfin_mult_fr1x32x32NS", int_ftype_int_int, | |
5439 | BFIN_BUILTIN_MULT_1X32X32NS); | |
f9edc33d | 5440 | |
5441 | /* Shifts. */ | |
5442 | def_builtin ("__builtin_bfin_shl_fr1x16", short_ftype_int_int, | |
5443 | BFIN_BUILTIN_SSASHIFT_1X16); | |
5444 | def_builtin ("__builtin_bfin_shl_fr2x16", v2hi_ftype_v2hi_int, | |
5445 | BFIN_BUILTIN_SSASHIFT_2X16); | |
5446 | def_builtin ("__builtin_bfin_lshl_fr1x16", short_ftype_int_int, | |
5447 | BFIN_BUILTIN_LSHIFT_1X16); | |
5448 | def_builtin ("__builtin_bfin_lshl_fr2x16", v2hi_ftype_v2hi_int, | |
5449 | BFIN_BUILTIN_LSHIFT_2X16); | |
a4317a50 | 5450 | def_builtin ("__builtin_bfin_shl_fr1x32", int_ftype_int_int, |
5451 | BFIN_BUILTIN_SSASHIFT_1X32); | |
f9edc33d | 5452 | |
5453 | /* Complex numbers. */ | |
44395948 | 5454 | def_builtin ("__builtin_bfin_cmplx_add", v2hi_ftype_v2hi_v2hi, |
5455 | BFIN_BUILTIN_SSADD_2X16); | |
5456 | def_builtin ("__builtin_bfin_cmplx_sub", v2hi_ftype_v2hi_v2hi, | |
5457 | BFIN_BUILTIN_SSSUB_2X16); | |
f9edc33d | 5458 | def_builtin ("__builtin_bfin_cmplx_mul", v2hi_ftype_v2hi_v2hi, |
5459 | BFIN_BUILTIN_CPLX_MUL_16); | |
5460 | def_builtin ("__builtin_bfin_cmplx_mac", v2hi_ftype_v2hi_v2hi_v2hi, | |
5461 | BFIN_BUILTIN_CPLX_MAC_16); | |
5462 | def_builtin ("__builtin_bfin_cmplx_msu", v2hi_ftype_v2hi_v2hi_v2hi, | |
5463 | BFIN_BUILTIN_CPLX_MSU_16); | |
44395948 | 5464 | def_builtin ("__builtin_bfin_cmplx_mul_s40", v2hi_ftype_v2hi_v2hi, |
5465 | BFIN_BUILTIN_CPLX_MUL_16_S40); | |
5466 | def_builtin ("__builtin_bfin_cmplx_mac_s40", v2hi_ftype_v2hi_v2hi_v2hi, | |
5467 | BFIN_BUILTIN_CPLX_MAC_16_S40); | |
5468 | def_builtin ("__builtin_bfin_cmplx_msu_s40", v2hi_ftype_v2hi_v2hi_v2hi, | |
5469 | BFIN_BUILTIN_CPLX_MSU_16_S40); | |
5470 | def_builtin ("__builtin_bfin_csqu_fr16", v2hi_ftype_v2hi, | |
5471 | BFIN_BUILTIN_CPLX_SQU); | |
16f1c0ab | 5472 | |
5473 | /* "Unaligned" load. */ | |
5474 | def_builtin ("__builtin_bfin_loadbytes", int_ftype_pint, | |
5475 | BFIN_BUILTIN_LOADBYTES); | |
5476 | ||
f9edc33d | 5477 | } |
5478 | ||
5479 | ||
5480 | struct builtin_description | |
5481 | { | |
5482 | const enum insn_code icode; | |
5483 | const char *const name; | |
5484 | const enum bfin_builtins code; | |
5485 | int macflag; | |
5486 | }; | |
5487 | ||
5488 | static const struct builtin_description bdesc_2arg[] = | |
5489 | { | |
5490 | { CODE_FOR_composev2hi, "__builtin_bfin_compose_2x16", BFIN_BUILTIN_COMPOSE_2X16, -1 }, | |
5491 | ||
5492 | { CODE_FOR_ssashiftv2hi3, "__builtin_bfin_shl_fr2x16", BFIN_BUILTIN_SSASHIFT_2X16, -1 }, | |
5493 | { CODE_FOR_ssashifthi3, "__builtin_bfin_shl_fr1x16", BFIN_BUILTIN_SSASHIFT_1X16, -1 }, | |
5494 | { CODE_FOR_lshiftv2hi3, "__builtin_bfin_lshl_fr2x16", BFIN_BUILTIN_LSHIFT_2X16, -1 }, | |
5495 | { CODE_FOR_lshifthi3, "__builtin_bfin_lshl_fr1x16", BFIN_BUILTIN_LSHIFT_1X16, -1 }, | |
a4317a50 | 5496 | { CODE_FOR_ssashiftsi3, "__builtin_bfin_shl_fr1x32", BFIN_BUILTIN_SSASHIFT_1X32, -1 }, |
f9edc33d | 5497 | |
5498 | { CODE_FOR_sminhi3, "__builtin_bfin_min_fr1x16", BFIN_BUILTIN_MIN_1X16, -1 }, | |
5499 | { CODE_FOR_smaxhi3, "__builtin_bfin_max_fr1x16", BFIN_BUILTIN_MAX_1X16, -1 }, | |
5500 | { CODE_FOR_ssaddhi3, "__builtin_bfin_add_fr1x16", BFIN_BUILTIN_SSADD_1X16, -1 }, | |
5501 | { CODE_FOR_sssubhi3, "__builtin_bfin_sub_fr1x16", BFIN_BUILTIN_SSSUB_1X16, -1 }, | |
5502 | ||
5503 | { CODE_FOR_sminsi3, "__builtin_bfin_min_fr1x32", BFIN_BUILTIN_MIN_1X32, -1 }, | |
5504 | { CODE_FOR_smaxsi3, "__builtin_bfin_max_fr1x32", BFIN_BUILTIN_MAX_1X32, -1 }, | |
5505 | { CODE_FOR_ssaddsi3, "__builtin_bfin_add_fr1x32", BFIN_BUILTIN_SSADD_1X32, -1 }, | |
5506 | { CODE_FOR_sssubsi3, "__builtin_bfin_sub_fr1x32", BFIN_BUILTIN_SSSUB_1X32, -1 }, | |
5507 | ||
5508 | { CODE_FOR_sminv2hi3, "__builtin_bfin_min_fr2x16", BFIN_BUILTIN_MIN_2X16, -1 }, | |
5509 | { CODE_FOR_smaxv2hi3, "__builtin_bfin_max_fr2x16", BFIN_BUILTIN_MAX_2X16, -1 }, | |
5510 | { CODE_FOR_ssaddv2hi3, "__builtin_bfin_add_fr2x16", BFIN_BUILTIN_SSADD_2X16, -1 }, | |
5511 | { CODE_FOR_sssubv2hi3, "__builtin_bfin_sub_fr2x16", BFIN_BUILTIN_SSSUB_2X16, -1 }, | |
5512 | { CODE_FOR_ssaddsubv2hi3, "__builtin_bfin_dspaddsubsat", BFIN_BUILTIN_SSADDSUB_2X16, -1 }, | |
5513 | { CODE_FOR_sssubaddv2hi3, "__builtin_bfin_dspsubaddsat", BFIN_BUILTIN_SSSUBADD_2X16, -1 }, | |
5514 | ||
5515 | { CODE_FOR_flag_mulhisi, "__builtin_bfin_mult_fr1x32", BFIN_BUILTIN_MULT_1X32, MACFLAG_NONE }, | |
5516 | { CODE_FOR_flag_mulhi, "__builtin_bfin_mult_fr1x16", BFIN_BUILTIN_MULT_1X16, MACFLAG_T }, | |
5517 | { CODE_FOR_flag_mulhi, "__builtin_bfin_multr_fr1x16", BFIN_BUILTIN_MULTR_1X16, MACFLAG_NONE }, | |
5518 | { CODE_FOR_flag_mulv2hi, "__builtin_bfin_mult_fr2x16", BFIN_BUILTIN_MULT_2X16, MACFLAG_T }, | |
5519 | { CODE_FOR_flag_mulv2hi, "__builtin_bfin_multr_fr2x16", BFIN_BUILTIN_MULTR_2X16, MACFLAG_NONE } | |
5520 | }; | |
5521 | ||
5522 | static const struct builtin_description bdesc_1arg[] = | |
5523 | { | |
16f1c0ab | 5524 | { CODE_FOR_loadbytes, "__builtin_bfin_loadbytes", BFIN_BUILTIN_LOADBYTES, 0 }, |
5525 | ||
44395948 | 5526 | { CODE_FOR_ones, "__builtin_bfin_ones", BFIN_BUILTIN_ONES, 0 }, |
5527 | ||
f9edc33d | 5528 | { CODE_FOR_signbitshi2, "__builtin_bfin_norm_fr1x16", BFIN_BUILTIN_NORM_1X16, 0 }, |
5529 | { CODE_FOR_ssneghi2, "__builtin_bfin_negate_fr1x16", BFIN_BUILTIN_NEG_1X16, 0 }, | |
5530 | { CODE_FOR_abshi2, "__builtin_bfin_abs_fr1x16", BFIN_BUILTIN_ABS_1X16, 0 }, | |
5531 | ||
5532 | { CODE_FOR_signbitssi2, "__builtin_bfin_norm_fr1x32", BFIN_BUILTIN_NORM_1X32, 0 }, | |
a4317a50 | 5533 | { CODE_FOR_ssroundsi2, "__builtin_bfin_round_fr1x32", BFIN_BUILTIN_ROUND_1X32, 0 }, |
f9edc33d | 5534 | { CODE_FOR_ssnegsi2, "__builtin_bfin_negate_fr1x32", BFIN_BUILTIN_NEG_1X32, 0 }, |
a4317a50 | 5535 | { CODE_FOR_ssabssi2, "__builtin_bfin_abs_fr1x32", BFIN_BUILTIN_ABS_1X32, 0 }, |
f9edc33d | 5536 | |
5537 | { CODE_FOR_movv2hi_hi_low, "__builtin_bfin_extract_lo", BFIN_BUILTIN_EXTRACTLO, 0 }, | |
5538 | { CODE_FOR_movv2hi_hi_high, "__builtin_bfin_extract_hi", BFIN_BUILTIN_EXTRACTHI, 0 }, | |
5539 | { CODE_FOR_ssnegv2hi2, "__builtin_bfin_negate_fr2x16", BFIN_BUILTIN_NEG_2X16, 0 }, | |
a4317a50 | 5540 | { CODE_FOR_ssabsv2hi2, "__builtin_bfin_abs_fr2x16", BFIN_BUILTIN_ABS_2X16, 0 } |
f9edc33d | 5541 | }; |
5542 | ||
5543 | /* Errors in the source file can cause expand_expr to return const0_rtx | |
5544 | where we expect a vector. To avoid crashing, use one of the vector | |
5545 | clear instructions. */ | |
5546 | static rtx | |
5547 | safe_vector_operand (rtx x, enum machine_mode mode) | |
5548 | { | |
5549 | if (x != const0_rtx) | |
5550 | return x; | |
5551 | x = gen_reg_rtx (SImode); | |
5552 | ||
5553 | emit_insn (gen_movsi (x, CONST0_RTX (SImode))); | |
5554 | return gen_lowpart (mode, x); | |
5555 | } | |
5556 | ||
5557 | /* Subroutine of bfin_expand_builtin to take care of binop insns. MACFLAG is -1 | |
5558 | if this is a normal binary op, or one of the MACFLAG_xxx constants. */ | |
5559 | ||
5560 | static rtx | |
c2f47e15 | 5561 | bfin_expand_binop_builtin (enum insn_code icode, tree exp, rtx target, |
f9edc33d | 5562 | int macflag) |
5563 | { | |
5564 | rtx pat; | |
c2f47e15 | 5565 | tree arg0 = CALL_EXPR_ARG (exp, 0); |
5566 | tree arg1 = CALL_EXPR_ARG (exp, 1); | |
f9edc33d | 5567 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); |
5568 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
5569 | enum machine_mode op0mode = GET_MODE (op0); | |
5570 | enum machine_mode op1mode = GET_MODE (op1); | |
5571 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
5572 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
5573 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
5574 | ||
5575 | if (VECTOR_MODE_P (mode0)) | |
5576 | op0 = safe_vector_operand (op0, mode0); | |
5577 | if (VECTOR_MODE_P (mode1)) | |
5578 | op1 = safe_vector_operand (op1, mode1); | |
5579 | ||
5580 | if (! target | |
5581 | || GET_MODE (target) != tmode | |
5582 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5583 | target = gen_reg_rtx (tmode); | |
5584 | ||
5585 | if ((op0mode == SImode || op0mode == VOIDmode) && mode0 == HImode) | |
5586 | { | |
5587 | op0mode = HImode; | |
5588 | op0 = gen_lowpart (HImode, op0); | |
5589 | } | |
5590 | if ((op1mode == SImode || op1mode == VOIDmode) && mode1 == HImode) | |
5591 | { | |
5592 | op1mode = HImode; | |
5593 | op1 = gen_lowpart (HImode, op1); | |
5594 | } | |
5595 | /* In case the insn wants input operands in modes different from | |
5596 | the result, abort. */ | |
5597 | gcc_assert ((op0mode == mode0 || op0mode == VOIDmode) | |
5598 | && (op1mode == mode1 || op1mode == VOIDmode)); | |
5599 | ||
5600 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5601 | op0 = copy_to_mode_reg (mode0, op0); | |
5602 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
5603 | op1 = copy_to_mode_reg (mode1, op1); | |
5604 | ||
5605 | if (macflag == -1) | |
5606 | pat = GEN_FCN (icode) (target, op0, op1); | |
5607 | else | |
5608 | pat = GEN_FCN (icode) (target, op0, op1, GEN_INT (macflag)); | |
5609 | if (! pat) | |
5610 | return 0; | |
5611 | ||
5612 | emit_insn (pat); | |
5613 | return target; | |
5614 | } | |
5615 | ||
5616 | /* Subroutine of bfin_expand_builtin to take care of unop insns. */ | |
5617 | ||
5618 | static rtx | |
c2f47e15 | 5619 | bfin_expand_unop_builtin (enum insn_code icode, tree exp, |
f9edc33d | 5620 | rtx target) |
5621 | { | |
5622 | rtx pat; | |
c2f47e15 | 5623 | tree arg0 = CALL_EXPR_ARG (exp, 0); |
f9edc33d | 5624 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); |
5625 | enum machine_mode op0mode = GET_MODE (op0); | |
5626 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
5627 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
5628 | ||
5629 | if (! target | |
5630 | || GET_MODE (target) != tmode | |
5631 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5632 | target = gen_reg_rtx (tmode); | |
5633 | ||
5634 | if (VECTOR_MODE_P (mode0)) | |
5635 | op0 = safe_vector_operand (op0, mode0); | |
5636 | ||
5637 | if (op0mode == SImode && mode0 == HImode) | |
5638 | { | |
5639 | op0mode = HImode; | |
5640 | op0 = gen_lowpart (HImode, op0); | |
5641 | } | |
5642 | gcc_assert (op0mode == mode0 || op0mode == VOIDmode); | |
5643 | ||
5644 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5645 | op0 = copy_to_mode_reg (mode0, op0); | |
5646 | ||
5647 | pat = GEN_FCN (icode) (target, op0); | |
5648 | if (! pat) | |
5649 | return 0; | |
5650 | emit_insn (pat); | |
5651 | return target; | |
e43914a7 | 5652 | } |
5653 | ||
5654 | /* Expand an expression EXP that calls a built-in function, | |
5655 | with result going to TARGET if that's convenient | |
5656 | (and in mode MODE if that's convenient). | |
5657 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
5658 | IGNORE is nonzero if the value is to be ignored. */ | |
5659 | ||
5660 | static rtx | |
5661 | bfin_expand_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, | |
5662 | rtx subtarget ATTRIBUTE_UNUSED, | |
5663 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
5664 | int ignore ATTRIBUTE_UNUSED) | |
5665 | { | |
f9edc33d | 5666 | size_t i; |
5667 | enum insn_code icode; | |
5668 | const struct builtin_description *d; | |
c2f47e15 | 5669 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
e43914a7 | 5670 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
f9edc33d | 5671 | tree arg0, arg1, arg2; |
a4317a50 | 5672 | rtx op0, op1, op2, accvec, pat, tmp1, tmp2, a0reg, a1reg; |
f9edc33d | 5673 | enum machine_mode tmode, mode0; |
e43914a7 | 5674 | |
5675 | switch (fcode) | |
5676 | { | |
5677 | case BFIN_BUILTIN_CSYNC: | |
5678 | emit_insn (gen_csync ()); | |
5679 | return 0; | |
5680 | case BFIN_BUILTIN_SSYNC: | |
5681 | emit_insn (gen_ssync ()); | |
5682 | return 0; | |
5683 | ||
f9edc33d | 5684 | case BFIN_BUILTIN_DIFFHL_2X16: |
5685 | case BFIN_BUILTIN_DIFFLH_2X16: | |
a4317a50 | 5686 | case BFIN_BUILTIN_SUM_2X16: |
c2f47e15 | 5687 | arg0 = CALL_EXPR_ARG (exp, 0); |
f9edc33d | 5688 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); |
a4317a50 | 5689 | icode = (fcode == BFIN_BUILTIN_DIFFHL_2X16 ? CODE_FOR_subhilov2hi3 |
5690 | : fcode == BFIN_BUILTIN_DIFFLH_2X16 ? CODE_FOR_sublohiv2hi3 | |
5691 | : CODE_FOR_ssaddhilov2hi3); | |
f9edc33d | 5692 | tmode = insn_data[icode].operand[0].mode; |
5693 | mode0 = insn_data[icode].operand[1].mode; | |
5694 | ||
5695 | if (! target | |
5696 | || GET_MODE (target) != tmode | |
5697 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5698 | target = gen_reg_rtx (tmode); | |
5699 | ||
5700 | if (VECTOR_MODE_P (mode0)) | |
5701 | op0 = safe_vector_operand (op0, mode0); | |
5702 | ||
5703 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5704 | op0 = copy_to_mode_reg (mode0, op0); | |
5705 | ||
5706 | pat = GEN_FCN (icode) (target, op0, op0); | |
5707 | if (! pat) | |
5708 | return 0; | |
5709 | emit_insn (pat); | |
5710 | return target; | |
5711 | ||
a4317a50 | 5712 | case BFIN_BUILTIN_MULT_1X32X32: |
5713 | case BFIN_BUILTIN_MULT_1X32X32NS: | |
5714 | arg0 = CALL_EXPR_ARG (exp, 0); | |
5715 | arg1 = CALL_EXPR_ARG (exp, 1); | |
5716 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5717 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
5718 | if (! target | |
5719 | || !register_operand (target, SImode)) | |
5720 | target = gen_reg_rtx (SImode); | |
5721 | ||
5722 | a1reg = gen_rtx_REG (PDImode, REG_A1); | |
5723 | a0reg = gen_rtx_REG (PDImode, REG_A0); | |
5724 | tmp1 = gen_lowpart (V2HImode, op0); | |
5725 | tmp2 = gen_lowpart (V2HImode, op1); | |
5726 | emit_insn (gen_flag_macinit1hi (a1reg, | |
5727 | gen_lowpart (HImode, op0), | |
5728 | gen_lowpart (HImode, op1), | |
5729 | GEN_INT (MACFLAG_FU))); | |
5730 | emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16))); | |
5731 | ||
5732 | if (fcode == BFIN_BUILTIN_MULT_1X32X32) | |
5733 | emit_insn (gen_flag_mul_macv2hi_parts_acconly (a0reg, a1reg, tmp1, tmp2, | |
5734 | const1_rtx, const1_rtx, | |
5735 | const1_rtx, const0_rtx, a1reg, | |
5736 | const0_rtx, GEN_INT (MACFLAG_NONE), | |
5737 | GEN_INT (MACFLAG_M))); | |
5738 | else | |
5739 | { | |
5740 | /* For saturating multiplication, there's exactly one special case | |
5741 | to be handled: multiplying the smallest negative value with | |
5742 | itself. Due to shift correction in fractional multiplies, this | |
5743 | can overflow. Iff this happens, OP2 will contain 1, which, when | |
5744 | added in 32 bits to the smallest negative, wraps to the largest | |
5745 | positive, which is the result we want. */ | |
5746 | op2 = gen_reg_rtx (V2HImode); | |
5747 | emit_insn (gen_packv2hi (op2, tmp1, tmp2, const0_rtx, const0_rtx)); | |
5748 | emit_insn (gen_movsibi (gen_rtx_REG (BImode, REG_CC), | |
5749 | gen_lowpart (SImode, op2))); | |
5750 | emit_insn (gen_flag_mul_macv2hi_parts_acconly_andcc0 (a0reg, a1reg, tmp1, tmp2, | |
5751 | const1_rtx, const1_rtx, | |
5752 | const1_rtx, const0_rtx, a1reg, | |
5753 | const0_rtx, GEN_INT (MACFLAG_NONE), | |
5754 | GEN_INT (MACFLAG_M))); | |
5755 | op2 = gen_reg_rtx (SImode); | |
5756 | emit_insn (gen_movbisi (op2, gen_rtx_REG (BImode, REG_CC))); | |
5757 | } | |
5758 | emit_insn (gen_flag_machi_parts_acconly (a1reg, tmp2, tmp1, | |
5759 | const1_rtx, const0_rtx, | |
5760 | a1reg, const0_rtx, GEN_INT (MACFLAG_M))); | |
5761 | emit_insn (gen_ashrpdi3 (a1reg, a1reg, GEN_INT (15))); | |
5762 | emit_insn (gen_sum_of_accumulators (target, a0reg, a0reg, a1reg)); | |
5763 | if (fcode == BFIN_BUILTIN_MULT_1X32X32NS) | |
5764 | emit_insn (gen_addsi3 (target, target, op2)); | |
5765 | return target; | |
5766 | ||
f9edc33d | 5767 | case BFIN_BUILTIN_CPLX_MUL_16: |
44395948 | 5768 | case BFIN_BUILTIN_CPLX_MUL_16_S40: |
c2f47e15 | 5769 | arg0 = CALL_EXPR_ARG (exp, 0); |
5770 | arg1 = CALL_EXPR_ARG (exp, 1); | |
f9edc33d | 5771 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); |
5772 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
5773 | accvec = gen_reg_rtx (V2PDImode); | |
5774 | ||
5775 | if (! target | |
5776 | || GET_MODE (target) != V2HImode | |
5777 | || ! (*insn_data[icode].operand[0].predicate) (target, V2HImode)) | |
5778 | target = gen_reg_rtx (tmode); | |
5779 | if (! register_operand (op0, GET_MODE (op0))) | |
5780 | op0 = copy_to_mode_reg (GET_MODE (op0), op0); | |
5781 | if (! register_operand (op1, GET_MODE (op1))) | |
5782 | op1 = copy_to_mode_reg (GET_MODE (op1), op1); | |
5783 | ||
44395948 | 5784 | if (fcode == BFIN_BUILTIN_CPLX_MUL_16) |
5785 | emit_insn (gen_flag_macinit1v2hi_parts (accvec, op0, op1, const0_rtx, | |
5786 | const0_rtx, const0_rtx, | |
5787 | const1_rtx, GEN_INT (MACFLAG_W32))); | |
5788 | else | |
5789 | emit_insn (gen_flag_macinit1v2hi_parts (accvec, op0, op1, const0_rtx, | |
5790 | const0_rtx, const0_rtx, | |
5791 | const1_rtx, GEN_INT (MACFLAG_NONE))); | |
f9edc33d | 5792 | emit_insn (gen_flag_macv2hi_parts (target, op0, op1, const1_rtx, |
5793 | const1_rtx, const1_rtx, | |
5794 | const0_rtx, accvec, const1_rtx, const0_rtx, | |
5795 | GEN_INT (MACFLAG_NONE), accvec)); | |
5796 | ||
5797 | return target; | |
5798 | ||
5799 | case BFIN_BUILTIN_CPLX_MAC_16: | |
5800 | case BFIN_BUILTIN_CPLX_MSU_16: | |
44395948 | 5801 | case BFIN_BUILTIN_CPLX_MAC_16_S40: |
5802 | case BFIN_BUILTIN_CPLX_MSU_16_S40: | |
c2f47e15 | 5803 | arg0 = CALL_EXPR_ARG (exp, 0); |
5804 | arg1 = CALL_EXPR_ARG (exp, 1); | |
5805 | arg2 = CALL_EXPR_ARG (exp, 2); | |
f9edc33d | 5806 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); |
5807 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
5808 | op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
5809 | accvec = gen_reg_rtx (V2PDImode); | |
5810 | ||
5811 | if (! target | |
5812 | || GET_MODE (target) != V2HImode | |
5813 | || ! (*insn_data[icode].operand[0].predicate) (target, V2HImode)) | |
5814 | target = gen_reg_rtx (tmode); | |
f9edc33d | 5815 | if (! register_operand (op1, GET_MODE (op1))) |
5816 | op1 = copy_to_mode_reg (GET_MODE (op1), op1); | |
121e4cf5 | 5817 | if (! register_operand (op2, GET_MODE (op2))) |
5818 | op2 = copy_to_mode_reg (GET_MODE (op2), op2); | |
f9edc33d | 5819 | |
5820 | tmp1 = gen_reg_rtx (SImode); | |
5821 | tmp2 = gen_reg_rtx (SImode); | |
121e4cf5 | 5822 | emit_insn (gen_ashlsi3 (tmp1, gen_lowpart (SImode, op0), GEN_INT (16))); |
5823 | emit_move_insn (tmp2, gen_lowpart (SImode, op0)); | |
f9edc33d | 5824 | emit_insn (gen_movstricthi_1 (gen_lowpart (HImode, tmp2), const0_rtx)); |
5825 | emit_insn (gen_load_accumulator_pair (accvec, tmp1, tmp2)); | |
44395948 | 5826 | if (fcode == BFIN_BUILTIN_CPLX_MAC_16 |
5827 | || fcode == BFIN_BUILTIN_CPLX_MSU_16) | |
5828 | emit_insn (gen_flag_macv2hi_parts_acconly (accvec, op1, op2, const0_rtx, | |
5829 | const0_rtx, const0_rtx, | |
5830 | const1_rtx, accvec, const0_rtx, | |
5831 | const0_rtx, | |
5832 | GEN_INT (MACFLAG_W32))); | |
5833 | else | |
5834 | emit_insn (gen_flag_macv2hi_parts_acconly (accvec, op1, op2, const0_rtx, | |
5835 | const0_rtx, const0_rtx, | |
5836 | const1_rtx, accvec, const0_rtx, | |
5837 | const0_rtx, | |
5838 | GEN_INT (MACFLAG_NONE))); | |
5839 | if (fcode == BFIN_BUILTIN_CPLX_MAC_16 | |
5840 | || fcode == BFIN_BUILTIN_CPLX_MAC_16_S40) | |
5841 | { | |
5842 | tmp1 = const1_rtx; | |
5843 | tmp2 = const0_rtx; | |
5844 | } | |
5845 | else | |
5846 | { | |
5847 | tmp1 = const0_rtx; | |
5848 | tmp2 = const1_rtx; | |
5849 | } | |
121e4cf5 | 5850 | emit_insn (gen_flag_macv2hi_parts (target, op1, op2, const1_rtx, |
f9edc33d | 5851 | const1_rtx, const1_rtx, |
5852 | const0_rtx, accvec, tmp1, tmp2, | |
5853 | GEN_INT (MACFLAG_NONE), accvec)); | |
5854 | ||
5855 | return target; | |
5856 | ||
44395948 | 5857 | case BFIN_BUILTIN_CPLX_SQU: |
5858 | arg0 = CALL_EXPR_ARG (exp, 0); | |
5859 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5860 | accvec = gen_reg_rtx (V2PDImode); | |
5861 | icode = CODE_FOR_flag_mulv2hi; | |
5862 | tmp1 = gen_reg_rtx (V2HImode); | |
5863 | tmp2 = gen_reg_rtx (V2HImode); | |
5864 | ||
5865 | if (! target | |
5866 | || GET_MODE (target) != V2HImode | |
5867 | || ! (*insn_data[icode].operand[0].predicate) (target, V2HImode)) | |
5868 | target = gen_reg_rtx (V2HImode); | |
5869 | if (! register_operand (op0, GET_MODE (op0))) | |
5870 | op0 = copy_to_mode_reg (GET_MODE (op0), op0); | |
5871 | ||
5872 | emit_insn (gen_flag_mulv2hi (tmp1, op0, op0, GEN_INT (MACFLAG_NONE))); | |
5873 | ||
5874 | emit_insn (gen_flag_mulhi_parts (tmp2, op0, op0, const0_rtx, | |
5875 | const0_rtx, const1_rtx, | |
5876 | GEN_INT (MACFLAG_NONE))); | |
5877 | ||
5878 | emit_insn (gen_ssaddhi3_parts (target, tmp2, tmp2, const1_rtx, | |
5879 | const0_rtx, const0_rtx)); | |
5880 | ||
5881 | emit_insn (gen_sssubhi3_parts (target, tmp1, tmp1, const0_rtx, | |
5882 | const0_rtx, const1_rtx)); | |
5883 | ||
5884 | return target; | |
5885 | ||
e43914a7 | 5886 | default: |
f9edc33d | 5887 | break; |
e43914a7 | 5888 | } |
f9edc33d | 5889 | |
5890 | for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) | |
5891 | if (d->code == fcode) | |
c2f47e15 | 5892 | return bfin_expand_binop_builtin (d->icode, exp, target, |
f9edc33d | 5893 | d->macflag); |
5894 | ||
5895 | for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++) | |
5896 | if (d->code == fcode) | |
c2f47e15 | 5897 | return bfin_expand_unop_builtin (d->icode, exp, target); |
f9edc33d | 5898 | |
5899 | gcc_unreachable (); | |
e43914a7 | 5900 | } |
5901 | \f | |
5902 | #undef TARGET_INIT_BUILTINS | |
5903 | #define TARGET_INIT_BUILTINS bfin_init_builtins | |
5904 | ||
5905 | #undef TARGET_EXPAND_BUILTIN | |
5906 | #define TARGET_EXPAND_BUILTIN bfin_expand_builtin | |
5907 | ||
9e6a0967 | 5908 | #undef TARGET_ASM_GLOBALIZE_LABEL |
5909 | #define TARGET_ASM_GLOBALIZE_LABEL bfin_globalize_label | |
5910 | ||
5911 | #undef TARGET_ASM_FILE_START | |
5912 | #define TARGET_ASM_FILE_START output_file_start | |
5913 | ||
5914 | #undef TARGET_ATTRIBUTE_TABLE | |
5915 | #define TARGET_ATTRIBUTE_TABLE bfin_attribute_table | |
5916 | ||
5917 | #undef TARGET_COMP_TYPE_ATTRIBUTES | |
5918 | #define TARGET_COMP_TYPE_ATTRIBUTES bfin_comp_type_attributes | |
5919 | ||
5920 | #undef TARGET_RTX_COSTS | |
5921 | #define TARGET_RTX_COSTS bfin_rtx_costs | |
5922 | ||
5923 | #undef TARGET_ADDRESS_COST | |
5924 | #define TARGET_ADDRESS_COST bfin_address_cost | |
5925 | ||
55be0e32 | 5926 | #undef TARGET_ASM_INTEGER |
5927 | #define TARGET_ASM_INTEGER bfin_assemble_integer | |
5928 | ||
9e6a0967 | 5929 | #undef TARGET_MACHINE_DEPENDENT_REORG |
5930 | #define TARGET_MACHINE_DEPENDENT_REORG bfin_reorg | |
5931 | ||
5932 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL | |
5933 | #define TARGET_FUNCTION_OK_FOR_SIBCALL bfin_function_ok_for_sibcall | |
5934 | ||
5935 | #undef TARGET_ASM_OUTPUT_MI_THUNK | |
5936 | #define TARGET_ASM_OUTPUT_MI_THUNK bfin_output_mi_thunk | |
5937 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
a9f1838b | 5938 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true |
9e6a0967 | 5939 | |
5940 | #undef TARGET_SCHED_ADJUST_COST | |
5941 | #define TARGET_SCHED_ADJUST_COST bfin_adjust_cost | |
5942 | ||
9aa0222b | 5943 | #undef TARGET_SCHED_ISSUE_RATE |
5944 | #define TARGET_SCHED_ISSUE_RATE bfin_issue_rate | |
5945 | ||
9e6a0967 | 5946 | #undef TARGET_PROMOTE_PROTOTYPES |
fb80456a | 5947 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true |
9e6a0967 | 5948 | #undef TARGET_PROMOTE_FUNCTION_ARGS |
fb80456a | 5949 | #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true |
9e6a0967 | 5950 | #undef TARGET_PROMOTE_FUNCTION_RETURN |
fb80456a | 5951 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true |
9e6a0967 | 5952 | |
5953 | #undef TARGET_ARG_PARTIAL_BYTES | |
5954 | #define TARGET_ARG_PARTIAL_BYTES bfin_arg_partial_bytes | |
5955 | ||
5956 | #undef TARGET_PASS_BY_REFERENCE | |
5957 | #define TARGET_PASS_BY_REFERENCE bfin_pass_by_reference | |
5958 | ||
5959 | #undef TARGET_SETUP_INCOMING_VARARGS | |
5960 | #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs | |
5961 | ||
5962 | #undef TARGET_STRUCT_VALUE_RTX | |
5963 | #define TARGET_STRUCT_VALUE_RTX bfin_struct_value_rtx | |
5964 | ||
5965 | #undef TARGET_VECTOR_MODE_SUPPORTED_P | |
5966 | #define TARGET_VECTOR_MODE_SUPPORTED_P bfin_vector_mode_supported_p | |
5967 | ||
f2a5d439 | 5968 | #undef TARGET_HANDLE_OPTION |
5969 | #define TARGET_HANDLE_OPTION bfin_handle_option | |
5970 | ||
b00f0d99 | 5971 | #undef TARGET_DEFAULT_TARGET_FLAGS |
5972 | #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT | |
5973 | ||
88eaee2d | 5974 | #undef TARGET_SECONDARY_RELOAD |
5975 | #define TARGET_SECONDARY_RELOAD bfin_secondary_reload | |
5976 | ||
6833eae4 | 5977 | #undef TARGET_DELEGITIMIZE_ADDRESS |
5978 | #define TARGET_DELEGITIMIZE_ADDRESS bfin_delegitimize_address | |
5979 | ||
cf63c743 | 5980 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
5981 | #define TARGET_CANNOT_FORCE_CONST_MEM bfin_cannot_force_const_mem | |
5982 | ||
0a619688 | 5983 | #undef TARGET_RETURN_IN_MEMORY |
5984 | #define TARGET_RETURN_IN_MEMORY bfin_return_in_memory | |
5985 | ||
9e6a0967 | 5986 | struct gcc_target targetm = TARGET_INITIALIZER; |