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0d4a78eb | 1 | /* Definitions for the Blackfin port. |
64882649 | 2 | Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc. |
0d4a78eb BS |
3 | Contributed by Analog Devices. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it | |
8 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | by the Free Software Foundation; either version 3, or (at your |
0d4a78eb BS |
10 | option) any later version. |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
0d4a78eb BS |
20 | |
21 | #ifndef _BFIN_CONFIG | |
22 | #define _BFIN_CONFIG | |
23 | ||
24 | #define OBJECT_FORMAT_ELF | |
25 | ||
26 | #define BRT 1 | |
27 | #define BRF 0 | |
28 | ||
29 | /* Print subsidiary information on the compiler version in use. */ | |
30 | #define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)") | |
31 | ||
32 | /* Run-time compilation parameters selecting different hardware subsets. */ | |
33 | ||
34 | extern int target_flags; | |
35 | ||
9d3f9aa3 BS |
36 | #ifndef DEFAULT_CPU_TYPE |
37 | #define DEFAULT_CPU_TYPE BFIN_CPU_BF532 | |
38 | #endif | |
39 | ||
0d4a78eb BS |
40 | /* Predefinition in the preprocessor for this target machine */ |
41 | #ifndef TARGET_CPU_CPP_BUILTINS | |
ea2382be JZ |
42 | #define TARGET_CPU_CPP_BUILTINS() \ |
43 | do \ | |
44 | { \ | |
45 | builtin_define_std ("bfin"); \ | |
46 | builtin_define_std ("BFIN"); \ | |
42da70b7 | 47 | builtin_define ("__ADSPBLACKFIN__"); \ |
9d3f9aa3 BS |
48 | builtin_define ("__ADSPLPBLACKFIN__"); \ |
49 | \ | |
50 | switch (bfin_cpu_type) \ | |
51 | { \ | |
ea2382be JZ |
52 | case BFIN_CPU_BF522: \ |
53 | builtin_define ("__ADSPBF522__"); \ | |
54 | builtin_define ("__ADSPBF52x__"); \ | |
55 | break; \ | |
64882649 BS |
56 | case BFIN_CPU_BF523: \ |
57 | builtin_define ("__ADSPBF523__"); \ | |
58 | builtin_define ("__ADSPBF52x__"); \ | |
59 | break; \ | |
60 | case BFIN_CPU_BF524: \ | |
61 | builtin_define ("__ADSPBF524__"); \ | |
62 | builtin_define ("__ADSPBF52x__"); \ | |
63 | break; \ | |
ea2382be JZ |
64 | case BFIN_CPU_BF525: \ |
65 | builtin_define ("__ADSPBF525__"); \ | |
66 | builtin_define ("__ADSPBF52x__"); \ | |
67 | break; \ | |
64882649 BS |
68 | case BFIN_CPU_BF526: \ |
69 | builtin_define ("__ADSPBF526__"); \ | |
70 | builtin_define ("__ADSPBF52x__"); \ | |
71 | break; \ | |
ea2382be JZ |
72 | case BFIN_CPU_BF527: \ |
73 | builtin_define ("__ADSPBF527__"); \ | |
74 | builtin_define ("__ADSPBF52x__"); \ | |
75 | break; \ | |
9d3f9aa3 BS |
76 | case BFIN_CPU_BF531: \ |
77 | builtin_define ("__ADSPBF531__"); \ | |
78 | break; \ | |
79 | case BFIN_CPU_BF532: \ | |
80 | builtin_define ("__ADSPBF532__"); \ | |
81 | break; \ | |
82 | case BFIN_CPU_BF533: \ | |
83 | builtin_define ("__ADSPBF533__"); \ | |
84 | break; \ | |
28f601ff JZ |
85 | case BFIN_CPU_BF534: \ |
86 | builtin_define ("__ADSPBF534__"); \ | |
87 | break; \ | |
88 | case BFIN_CPU_BF536: \ | |
89 | builtin_define ("__ADSPBF536__"); \ | |
90 | break; \ | |
9d3f9aa3 BS |
91 | case BFIN_CPU_BF537: \ |
92 | builtin_define ("__ADSPBF537__"); \ | |
93 | break; \ | |
ea2382be JZ |
94 | case BFIN_CPU_BF538: \ |
95 | builtin_define ("__ADSPBF538__"); \ | |
96 | break; \ | |
97 | case BFIN_CPU_BF539: \ | |
98 | builtin_define ("__ADSPBF539__"); \ | |
99 | break; \ | |
100 | case BFIN_CPU_BF542: \ | |
101 | builtin_define ("__ADSPBF542__"); \ | |
102 | builtin_define ("__ADSPBF54x__"); \ | |
103 | break; \ | |
104 | case BFIN_CPU_BF544: \ | |
105 | builtin_define ("__ADSPBF544__"); \ | |
106 | builtin_define ("__ADSPBF54x__"); \ | |
107 | break; \ | |
108 | case BFIN_CPU_BF548: \ | |
109 | builtin_define ("__ADSPBF548__"); \ | |
110 | builtin_define ("__ADSPBF54x__"); \ | |
111 | break; \ | |
64882649 BS |
112 | case BFIN_CPU_BF547: \ |
113 | builtin_define ("__ADSPBF547__"); \ | |
114 | builtin_define ("__ADSPBF54x__"); \ | |
115 | break; \ | |
ea2382be JZ |
116 | case BFIN_CPU_BF549: \ |
117 | builtin_define ("__ADSPBF549__"); \ | |
118 | builtin_define ("__ADSPBF54x__"); \ | |
119 | break; \ | |
28f601ff JZ |
120 | case BFIN_CPU_BF561: \ |
121 | builtin_define ("__ADSPBF561__"); \ | |
122 | break; \ | |
9d3f9aa3 BS |
123 | } \ |
124 | \ | |
ea2382be JZ |
125 | if (bfin_si_revision != -1) \ |
126 | { \ | |
127 | /* space of 0xnnnn and a NUL */ \ | |
128 | char *buf = alloca (7); \ | |
129 | \ | |
130 | sprintf (buf, "0x%04x", bfin_si_revision); \ | |
131 | builtin_define_with_value ("__SILICON_REVISION__", buf, 0); \ | |
132 | } \ | |
133 | \ | |
134 | if (bfin_workarounds) \ | |
135 | builtin_define ("__WORKAROUNDS_ENABLED"); \ | |
136 | if (ENABLE_WA_SPECULATIVE_LOADS) \ | |
137 | builtin_define ("__WORKAROUND_SPECULATIVE_LOADS"); \ | |
138 | if (ENABLE_WA_SPECULATIVE_SYNCS) \ | |
139 | builtin_define ("__WORKAROUND_SPECULATIVE_SYNCS"); \ | |
140 | \ | |
6614f9f5 | 141 | if (TARGET_FDPIC) \ |
f13488c0 BS |
142 | { \ |
143 | builtin_define ("__BFIN_FDPIC__"); \ | |
144 | builtin_define ("__FDPIC__"); \ | |
145 | } \ | |
ea2382be JZ |
146 | if (TARGET_ID_SHARED_LIBRARY \ |
147 | && !TARGET_SEP_DATA) \ | |
4af990cd | 148 | builtin_define ("__ID_SHARED_LIB__"); \ |
ae80f469 JZ |
149 | if (flag_no_builtin) \ |
150 | builtin_define ("__NO_BUILTIN"); \ | |
ea2382be | 151 | } \ |
0d4a78eb BS |
152 | while (0) |
153 | #endif | |
154 | ||
6614f9f5 | 155 | #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\ |
ea2382be | 156 | %{!mcpu=*:-mcpu=bf532} \ |
93147119 | 157 | %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \ |
6614f9f5 BS |
158 | %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\ |
159 | %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \ | |
160 | " | |
161 | #ifndef SUBTARGET_DRIVER_SELF_SPECS | |
162 | # define SUBTARGET_DRIVER_SELF_SPECS | |
163 | #endif | |
164 | ||
2c117a21 JZ |
165 | #define LINK_GCC_C_SEQUENCE_SPEC "\ |
166 | %{mfast-fp:-lbffastfp} %G %L %{mfast-fp:-lbffastfp} %G \ | |
167 | " | |
6614f9f5 BS |
168 | |
169 | /* A C string constant that tells the GCC driver program options to pass to | |
170 | the assembler. It can also specify how to translate options you give to GNU | |
171 | CC into options for GCC to pass to the assembler. See the file `sun3.h' | |
172 | for an example of this. | |
173 | ||
174 | Do not define this macro if it does not need to do anything. | |
175 | ||
176 | Defined in svr4.h. */ | |
177 | #undef ASM_SPEC | |
178 | #define ASM_SPEC "\ | |
179 | %{G*} %{v} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} \ | |
180 | %{mno-fdpic:-mnopic} %{mfdpic}" | |
181 | ||
182 | #define LINK_SPEC "\ | |
183 | %{h*} %{v:-V} \ | |
184 | %{b} \ | |
185 | %{mfdpic:-melf32bfinfd -z text} \ | |
186 | %{static:-dn -Bstatic} \ | |
187 | %{shared:-G -Bdynamic} \ | |
188 | %{symbolic:-Bsymbolic} \ | |
189 | %{G*} \ | |
190 | %{YP,*} \ | |
191 | %{Qy:} %{!Qn:-Qy} \ | |
192 | -init __init -fini __fini " | |
193 | ||
0d4a78eb BS |
194 | /* Generate DSP instructions, like DSP halfword loads */ |
195 | #define TARGET_DSP (1) | |
196 | ||
ea2382be | 197 | #define TARGET_DEFAULT 0 |
0d4a78eb | 198 | |
0d4a78eb BS |
199 | /* Maximum number of library ids we permit */ |
200 | #define MAX_LIBRARY_ID 255 | |
201 | ||
202 | extern const char *bfin_library_id_string; | |
203 | ||
204 | /* Sometimes certain combinations of command options do not make | |
205 | sense on a particular target machine. You can define a macro | |
206 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
207 | defined, is executed once just after all the command options have | |
208 | been parsed. | |
209 | ||
210 | Don't use this macro to turn on various extra optimizations for | |
211 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
212 | ||
213 | #define OVERRIDE_OPTIONS override_options () | |
214 | ||
215 | #define FUNCTION_MODE SImode | |
216 | #define Pmode SImode | |
217 | ||
218 | /* store-condition-codes instructions store 0 for false | |
219 | This is the value stored for true. */ | |
220 | #define STORE_FLAG_VALUE 1 | |
221 | ||
222 | /* Define this if pushing a word on the stack | |
223 | makes the stack pointer a smaller address. */ | |
224 | #define STACK_GROWS_DOWNWARD | |
225 | ||
226 | #define STACK_PUSH_CODE PRE_DEC | |
227 | ||
a4d05547 | 228 | /* Define this to nonzero if the nominal address of the stack frame |
0d4a78eb BS |
229 | is at the high-address end of the local variables; |
230 | that is, each additional local variable allocated | |
231 | goes at a more negative offset in the frame. */ | |
f62c8a5c | 232 | #define FRAME_GROWS_DOWNWARD 1 |
0d4a78eb BS |
233 | |
234 | /* We define a dummy ARGP register; the parameters start at offset 0 from | |
235 | it. */ | |
236 | #define FIRST_PARM_OFFSET(DECL) 0 | |
237 | ||
238 | /* Offset within stack frame to start allocating local variables at. | |
239 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
240 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
241 | of the first local allocated. */ | |
242 | #define STARTING_FRAME_OFFSET 0 | |
243 | ||
244 | /* Register to use for pushing function arguments. */ | |
245 | #define STACK_POINTER_REGNUM REG_P6 | |
246 | ||
247 | /* Base register for access to local variables of the function. */ | |
248 | #define FRAME_POINTER_REGNUM REG_P7 | |
249 | ||
250 | /* A dummy register that will be eliminated to either FP or SP. */ | |
251 | #define ARG_POINTER_REGNUM REG_ARGP | |
252 | ||
253 | /* `PIC_OFFSET_TABLE_REGNUM' | |
254 | The register number of the register used to address a table of | |
255 | static data addresses in memory. In some cases this register is | |
256 | defined by a processor's "application binary interface" (ABI). | |
257 | When this macro is defined, RTL is generated for this register | |
258 | once, as with the stack pointer and frame pointer registers. If | |
259 | this macro is not defined, it is up to the machine-dependent files | |
260 | to allocate such a register (if necessary). */ | |
261 | #define PIC_OFFSET_TABLE_REGNUM (REG_P5) | |
262 | ||
6614f9f5 BS |
263 | #define FDPIC_FPTR_REGNO REG_P1 |
264 | #define FDPIC_REGNO REG_P3 | |
265 | #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO) | |
266 | ||
0d4a78eb BS |
267 | /* A static chain register for nested functions. We need to use a |
268 | call-clobbered register for this. */ | |
269 | #define STATIC_CHAIN_REGNUM REG_P2 | |
270 | ||
271 | /* Define this if functions should assume that stack space has been | |
272 | allocated for arguments even when their values are passed in | |
273 | registers. | |
274 | ||
275 | The value of this macro is the size, in bytes, of the area reserved for | |
276 | arguments passed in registers. | |
277 | ||
278 | This space can either be allocated by the caller or be a part of the | |
279 | machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' | |
280 | says which. */ | |
281 | #define FIXED_STACK_AREA 12 | |
282 | #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA | |
283 | ||
284 | /* Define this if the above stack space is to be considered part of the | |
285 | * space allocated by the caller. */ | |
ac294f0b | 286 | #define OUTGOING_REG_PARM_STACK_SPACE 1 |
0d4a78eb BS |
287 | |
288 | /* Define this if the maximum size of all the outgoing args is to be | |
289 | accumulated and pushed during the prologue. The amount can be | |
290 | found in the variable current_function_outgoing_args_size. */ | |
291 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
292 | ||
293 | /* Value should be nonzero if functions must have frame pointers. | |
294 | Zero means the frame pointer need not be set up (and parms | |
295 | may be accessed via the stack pointer) in functions that seem suitable. | |
296 | This is computed in `reload', in reload1.c. | |
297 | */ | |
298 | #define FRAME_POINTER_REQUIRED (bfin_frame_pointer_required ()) | |
299 | ||
0d4a78eb BS |
300 | /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */ |
301 | ||
520c62ad BS |
302 | /* If defined, a C expression to compute the alignment for a local |
303 | variable. TYPE is the data type, and ALIGN is the alignment that | |
304 | the object would ordinarily have. The value of this macro is used | |
305 | instead of that alignment to align the object. | |
306 | ||
307 | If this macro is not defined, then ALIGN is used. | |
308 | ||
309 | One use of this macro is to increase alignment of medium-size | |
310 | data to make it all fit in fewer cache lines. */ | |
311 | ||
312 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN)) | |
313 | ||
0d4a78eb BS |
314 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
315 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
316 | (TREE_CODE (EXP) == STRING_CST \ | |
317 | && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
318 | ||
6614f9f5 | 319 | #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18) |
0d4a78eb | 320 | #define TRAMPOLINE_TEMPLATE(FILE) \ |
6614f9f5 BS |
321 | if (TARGET_FDPIC) \ |
322 | { \ | |
323 | fprintf(FILE, "\t.dd\t0x00000000\n"); /* 0 */ \ | |
324 | fprintf(FILE, "\t.dd\t0x00000000\n"); /* 0 */ \ | |
325 | fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \ | |
326 | fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ \ | |
327 | fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ \ | |
328 | fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ \ | |
329 | fprintf(FILE, "\t.dw\t0xac4b\n"); /* p3 = [p1 + 4] */ \ | |
330 | fprintf(FILE, "\t.dw\t0x9149\n"); /* p1 = [p1] */ \ | |
331 | fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ \ | |
332 | } \ | |
333 | else \ | |
334 | { \ | |
335 | fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \ | |
336 | fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ \ | |
337 | fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ \ | |
338 | fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ \ | |
339 | fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ \ | |
340 | } | |
0d4a78eb BS |
341 | |
342 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
343 | initialize_trampoline (TRAMP, FNADDR, CXT) | |
344 | \f | |
345 | /* Definitions for register eliminations. | |
346 | ||
347 | This is an array of structures. Each structure initializes one pair | |
348 | of eliminable registers. The "from" register number is given first, | |
349 | followed by "to". Eliminations of the same "from" register are listed | |
350 | in order of preference. | |
351 | ||
352 | There are two registers that can always be eliminated on the i386. | |
353 | The frame pointer and the arg pointer can be replaced by either the | |
354 | hard frame pointer or to the stack pointer, depending upon the | |
355 | circumstances. The hard frame pointer is not used before reload and | |
356 | so it is not eligible for elimination. */ | |
357 | ||
358 | #define ELIMINABLE_REGS \ | |
359 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
360 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ | |
361 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \ | |
362 | ||
363 | /* Given FROM and TO register numbers, say whether this elimination is | |
364 | allowed. Frame pointer elimination is automatically handled. | |
365 | ||
366 | All other eliminations are valid. */ | |
367 | ||
368 | #define CAN_ELIMINATE(FROM, TO) \ | |
369 | ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) | |
370 | ||
371 | /* Define the offset between two registers, one to be eliminated, and the other | |
372 | its replacement, at the start of a routine. */ | |
373 | ||
374 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
375 | ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO))) | |
376 | \f | |
377 | /* This processor has | |
378 | 8 data register for doing arithmetic | |
379 | 8 pointer register for doing addressing, including | |
380 | 1 stack pointer P6 | |
381 | 1 frame pointer P7 | |
382 | 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3) | |
383 | 1 condition code flag register CC | |
384 | 5 return address registers RETS/I/X/N/E | |
385 | 1 arithmetic status register (ASTAT). */ | |
386 | ||
b03149e1 | 387 | #define FIRST_PSEUDO_REGISTER 50 |
0d4a78eb | 388 | |
0d4a78eb | 389 | #define D_REGNO_P(X) ((X) <= REG_R7) |
c4963a0a | 390 | #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7) |
b03149e1 JZ |
391 | #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3) |
392 | #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X)) | |
393 | #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3) | |
394 | #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X))) | |
395 | #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X))) | |
396 | #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X))) | |
397 | #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X))) | |
0d4a78eb BS |
398 | |
399 | #define REGISTER_NAMES { \ | |
400 | "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \ | |
401 | "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \ | |
df259245 JZ |
402 | "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \ |
403 | "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \ | |
0d4a78eb BS |
404 | "A0", "A1", \ |
405 | "CC", \ | |
406 | "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \ | |
b03149e1 JZ |
407 | "ARGP", \ |
408 | "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \ | |
0d4a78eb BS |
409 | } |
410 | ||
411 | #define SHORT_REGISTER_NAMES { \ | |
412 | "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \ | |
413 | "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \ | |
df259245 JZ |
414 | "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \ |
415 | "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", } | |
0d4a78eb BS |
416 | |
417 | #define HIGH_REGISTER_NAMES { \ | |
418 | "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \ | |
419 | "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \ | |
df259245 JZ |
420 | "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \ |
421 | "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", } | |
0d4a78eb BS |
422 | |
423 | #define DREGS_PAIR_NAMES { \ | |
424 | "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, } | |
425 | ||
426 | #define BYTE_REGISTER_NAMES { \ | |
427 | "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", } | |
428 | ||
429 | ||
430 | /* 1 for registers that have pervasive standard uses | |
431 | and are not available for the register allocator. */ | |
432 | ||
433 | #define FIXED_REGISTERS \ | |
434 | /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \ | |
435 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ | |
df259245 JZ |
436 | /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \ |
437 | 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \ | |
b03149e1 JZ |
438 | /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \ |
439 | 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
440 | /*lb0/1 */ \ | |
441 | 1, 1 \ | |
0d4a78eb BS |
442 | } |
443 | ||
444 | /* 1 for registers not available across function calls. | |
445 | These must include the FIXED_REGISTERS and also any | |
446 | registers that can be used without being saved. | |
447 | The latter must include the registers where values are returned | |
448 | and the register where structure-value addresses are passed. | |
449 | Aside from that, you can include as many other registers as you like. */ | |
450 | ||
451 | #define CALL_USED_REGISTERS \ | |
452 | /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \ | |
453 | { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \ | |
df259245 | 454 | /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \ |
0d4a78eb | 455 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
b03149e1 JZ |
456 | /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \ |
457 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
458 | /*lb0/1 */ \ | |
459 | 1, 1 \ | |
0d4a78eb BS |
460 | } |
461 | ||
462 | /* Order in which to allocate registers. Each register must be | |
463 | listed once, even those in FIXED_REGISTERS. List frame pointer | |
464 | late and fixed registers last. Note that, in general, we prefer | |
465 | registers listed in CALL_USED_REGISTERS, keeping the others | |
466 | available for storage of persistent values. */ | |
467 | ||
468 | #define REG_ALLOC_ORDER \ | |
469 | { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \ | |
470 | REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \ | |
471 | REG_A0, REG_A1, \ | |
df259245 JZ |
472 | REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \ |
473 | REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \ | |
0d4a78eb BS |
474 | REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \ |
475 | REG_ASTAT, REG_SEQSTAT, REG_USP, \ | |
b03149e1 JZ |
476 | REG_CC, REG_ARGP, \ |
477 | REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \ | |
0d4a78eb BS |
478 | } |
479 | ||
480 | /* Macro to conditionally modify fixed_regs/call_used_regs. */ | |
481 | #define CONDITIONAL_REGISTER_USAGE \ | |
482 | { \ | |
483 | conditional_register_usage(); \ | |
6614f9f5 BS |
484 | if (TARGET_FDPIC) \ |
485 | call_used_regs[FDPIC_REGNO] = 1; \ | |
486 | if (!TARGET_FDPIC && flag_pic) \ | |
0d4a78eb BS |
487 | { \ |
488 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
489 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
490 | } \ | |
491 | } | |
492 | ||
493 | /* Define the classes of registers for register constraints in the | |
494 | machine description. Also define ranges of constants. | |
495 | ||
496 | One of the classes must always be named ALL_REGS and include all hard regs. | |
497 | If there is more than one class, another class must be named NO_REGS | |
498 | and contain no registers. | |
499 | ||
500 | The name GENERAL_REGS must be the name of a class (or an alias for | |
501 | another name such as ALL_REGS). This is the class of registers | |
502 | that is allowed by "g" or "r" in a register constraint. | |
503 | Also, registers outside this class are allocated only when | |
504 | instructions express preferences for them. | |
505 | ||
506 | The classes must be numbered in nondecreasing order; that is, | |
507 | a larger-numbered class must never be contained completely | |
508 | in a smaller-numbered class. | |
509 | ||
510 | For any two classes, it is very desirable that there be another | |
511 | class that represents their union. */ | |
512 | ||
513 | ||
514 | enum reg_class | |
515 | { | |
516 | NO_REGS, | |
517 | IREGS, | |
518 | BREGS, | |
519 | LREGS, | |
520 | MREGS, | |
f652d14b | 521 | CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */ |
0d4a78eb BS |
522 | DAGREGS, |
523 | EVEN_AREGS, | |
524 | ODD_AREGS, | |
525 | AREGS, | |
526 | CCREGS, | |
527 | EVEN_DREGS, | |
528 | ODD_DREGS, | |
2889abed BS |
529 | D0REGS, |
530 | D1REGS, | |
531 | D2REGS, | |
532 | D3REGS, | |
533 | D4REGS, | |
534 | D5REGS, | |
535 | D6REGS, | |
536 | D7REGS, | |
0d4a78eb | 537 | DREGS, |
03848bd0 | 538 | P0REGS, |
6614f9f5 BS |
539 | FDPIC_REGS, |
540 | FDPIC_FPTR_REGS, | |
0d4a78eb BS |
541 | PREGS_CLOBBERED, |
542 | PREGS, | |
c4963a0a | 543 | IPREGS, |
0d4a78eb BS |
544 | DPREGS, |
545 | MOST_REGS, | |
b03149e1 JZ |
546 | LT_REGS, |
547 | LC_REGS, | |
548 | LB_REGS, | |
0d4a78eb BS |
549 | PROLOGUE_REGS, |
550 | NON_A_CC_REGS, | |
551 | ALL_REGS, LIM_REG_CLASSES | |
552 | }; | |
553 | ||
554 | #define N_REG_CLASSES ((int)LIM_REG_CLASSES) | |
555 | ||
556 | #define GENERAL_REGS DPREGS | |
557 | ||
558 | /* Give names of register classes as strings for dump file. */ | |
559 | ||
560 | #define REG_CLASS_NAMES \ | |
561 | { "NO_REGS", \ | |
562 | "IREGS", \ | |
563 | "BREGS", \ | |
564 | "LREGS", \ | |
565 | "MREGS", \ | |
566 | "CIRCREGS", \ | |
567 | "DAGREGS", \ | |
568 | "EVEN_AREGS", \ | |
569 | "ODD_AREGS", \ | |
570 | "AREGS", \ | |
571 | "CCREGS", \ | |
572 | "EVEN_DREGS", \ | |
573 | "ODD_DREGS", \ | |
2889abed BS |
574 | "D0REGS", \ |
575 | "D1REGS", \ | |
576 | "D2REGS", \ | |
577 | "D3REGS", \ | |
578 | "D4REGS", \ | |
579 | "D5REGS", \ | |
580 | "D6REGS", \ | |
581 | "D7REGS", \ | |
0d4a78eb | 582 | "DREGS", \ |
03848bd0 | 583 | "P0REGS", \ |
6614f9f5 BS |
584 | "FDPIC_REGS", \ |
585 | "FDPIC_FPTR_REGS", \ | |
0d4a78eb BS |
586 | "PREGS_CLOBBERED", \ |
587 | "PREGS", \ | |
c4963a0a | 588 | "IPREGS", \ |
0d4a78eb BS |
589 | "DPREGS", \ |
590 | "MOST_REGS", \ | |
b03149e1 JZ |
591 | "LT_REGS", \ |
592 | "LC_REGS", \ | |
593 | "LB_REGS", \ | |
0d4a78eb BS |
594 | "PROLOGUE_REGS", \ |
595 | "NON_A_CC_REGS", \ | |
596 | "ALL_REGS" } | |
597 | ||
598 | /* An initializer containing the contents of the register classes, as integers | |
599 | which are bit masks. The Nth integer specifies the contents of class N. | |
600 | The way the integer MASK is interpreted is that register R is in the class | |
601 | if `MASK & (1 << R)' is 1. | |
602 | ||
603 | When the machine has more than 32 registers, an integer does not suffice. | |
604 | Then the integers are replaced by sub-initializers, braced groupings | |
605 | containing several integers. Each sub-initializer must be suitable as an | |
606 | initializer for the type `HARD_REG_SET' which is defined in | |
607 | `hard-reg-set.h'. */ | |
608 | ||
609 | /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use | |
610 | MOST_REGS as the union of DPREGS and DAGREGS. */ | |
611 | ||
612 | #define REG_CLASS_CONTENTS \ | |
613 | /* 31 - 0 63-32 */ \ | |
614 | { { 0x00000000, 0 }, /* NO_REGS */ \ | |
df259245 JZ |
615 | { 0x000f0000, 0 }, /* IREGS */ \ |
616 | { 0x00f00000, 0 }, /* BREGS */ \ | |
617 | { 0x0f000000, 0 }, /* LREGS */ \ | |
0d4a78eb BS |
618 | { 0xf0000000, 0 }, /* MREGS */ \ |
619 | { 0x0fff0000, 0 }, /* CIRCREGS */ \ | |
620 | { 0xffff0000, 0 }, /* DAGREGS */ \ | |
621 | { 0x00000000, 0x1 }, /* EVEN_AREGS */ \ | |
622 | { 0x00000000, 0x2 }, /* ODD_AREGS */ \ | |
623 | { 0x00000000, 0x3 }, /* AREGS */ \ | |
624 | { 0x00000000, 0x4 }, /* CCREGS */ \ | |
625 | { 0x00000055, 0 }, /* EVEN_DREGS */ \ | |
626 | { 0x000000aa, 0 }, /* ODD_DREGS */ \ | |
2889abed BS |
627 | { 0x00000001, 0 }, /* D0REGS */ \ |
628 | { 0x00000002, 0 }, /* D1REGS */ \ | |
629 | { 0x00000004, 0 }, /* D2REGS */ \ | |
630 | { 0x00000008, 0 }, /* D3REGS */ \ | |
631 | { 0x00000010, 0 }, /* D4REGS */ \ | |
632 | { 0x00000020, 0 }, /* D5REGS */ \ | |
633 | { 0x00000040, 0 }, /* D6REGS */ \ | |
634 | { 0x00000080, 0 }, /* D7REGS */ \ | |
0d4a78eb | 635 | { 0x000000ff, 0 }, /* DREGS */ \ |
03848bd0 | 636 | { 0x00000100, 0x000 }, /* P0REGS */ \ |
6614f9f5 BS |
637 | { 0x00000800, 0x000 }, /* FDPIC_REGS */ \ |
638 | { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \ | |
0d4a78eb BS |
639 | { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \ |
640 | { 0x0000ff00, 0x800 }, /* PREGS */ \ | |
c4963a0a | 641 | { 0x000fff00, 0x800 }, /* IPREGS */ \ |
0d4a78eb BS |
642 | { 0x0000ffff, 0x800 }, /* DPREGS */ \ |
643 | { 0xffffffff, 0x800 }, /* MOST_REGS */\ | |
b03149e1 JZ |
644 | { 0x00000000, 0x3000 }, /* LT_REGS */\ |
645 | { 0x00000000, 0xc000 }, /* LC_REGS */\ | |
646 | { 0x00000000, 0x30000 }, /* LB_REGS */\ | |
647 | { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\ | |
648 | { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\ | |
649 | { 0xffffffff, 0x3ffff }} /* ALL_REGS */ | |
0d4a78eb | 650 | |
c4963a0a BS |
651 | #define IREG_POSSIBLE_P(OUTER) \ |
652 | ((OUTER) == POST_INC || (OUTER) == PRE_INC \ | |
653 | || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \ | |
654 | || (OUTER) == MEM || (OUTER) == ADDRESS) | |
655 | ||
656 | #define MODE_CODE_BASE_REG_CLASS(MODE, OUTER, INDEX) \ | |
657 | ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS) | |
658 | ||
0d4a78eb BS |
659 | #define INDEX_REG_CLASS PREGS |
660 | ||
c4963a0a BS |
661 | #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \ |
662 | (P_REGNO_P (X) || (X) == REG_ARGP \ | |
663 | || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \ | |
664 | && I_REGNO_P (X))) | |
665 | ||
666 | #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \ | |
667 | ((X) >= FIRST_PSEUDO_REGISTER \ | |
668 | || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)) | |
0d4a78eb BS |
669 | |
670 | #ifdef REG_OK_STRICT | |
c4963a0a BS |
671 | #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \ |
672 | REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX) | |
0d4a78eb | 673 | #else |
c4963a0a BS |
674 | #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \ |
675 | REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX) | |
0d4a78eb BS |
676 | #endif |
677 | ||
0d4a78eb BS |
678 | #define REGNO_OK_FOR_INDEX_P(X) 0 |
679 | ||
680 | /* Get reg_class from a letter such as appears in the machine description. */ | |
681 | ||
2889abed | 682 | #define REG_CLASS_FROM_CONSTRAINT(LETTER, STR) \ |
0d4a78eb | 683 | ((LETTER) == 'a' ? PREGS : \ |
6614f9f5 BS |
684 | (LETTER) == 'Z' ? FDPIC_REGS : \ |
685 | (LETTER) == 'Y' ? FDPIC_FPTR_REGS : \ | |
0d4a78eb BS |
686 | (LETTER) == 'd' ? DREGS : \ |
687 | (LETTER) == 'z' ? PREGS_CLOBBERED : \ | |
688 | (LETTER) == 'D' ? EVEN_DREGS : \ | |
689 | (LETTER) == 'W' ? ODD_DREGS : \ | |
690 | (LETTER) == 'e' ? AREGS : \ | |
691 | (LETTER) == 'A' ? EVEN_AREGS : \ | |
692 | (LETTER) == 'B' ? ODD_AREGS : \ | |
693 | (LETTER) == 'b' ? IREGS : \ | |
a9c46998 | 694 | (LETTER) == 'v' ? BREGS : \ |
0d4a78eb BS |
695 | (LETTER) == 'f' ? MREGS : \ |
696 | (LETTER) == 'c' ? CIRCREGS : \ | |
697 | (LETTER) == 'C' ? CCREGS : \ | |
b03149e1 JZ |
698 | (LETTER) == 't' ? LT_REGS : \ |
699 | (LETTER) == 'k' ? LC_REGS : \ | |
a9c46998 | 700 | (LETTER) == 'u' ? LB_REGS : \ |
0d4a78eb BS |
701 | (LETTER) == 'x' ? MOST_REGS : \ |
702 | (LETTER) == 'y' ? PROLOGUE_REGS : \ | |
703 | (LETTER) == 'w' ? NON_A_CC_REGS : \ | |
2889abed BS |
704 | (LETTER) == 'q' \ |
705 | ? ((STR)[1] == '0' ? D0REGS \ | |
706 | : (STR)[1] == '1' ? D1REGS \ | |
707 | : (STR)[1] == '2' ? D2REGS \ | |
708 | : (STR)[1] == '3' ? D3REGS \ | |
709 | : (STR)[1] == '4' ? D4REGS \ | |
710 | : (STR)[1] == '5' ? D5REGS \ | |
711 | : (STR)[1] == '6' ? D6REGS \ | |
712 | : (STR)[1] == '7' ? D7REGS \ | |
03848bd0 | 713 | : (STR)[1] == 'A' ? P0REGS \ |
2889abed | 714 | : NO_REGS) : \ |
0d4a78eb BS |
715 | NO_REGS) |
716 | ||
717 | /* The same information, inverted: | |
718 | Return the class number of the smallest class containing | |
719 | reg number REGNO. This could be a conditional expression | |
720 | or could index an array. */ | |
721 | ||
722 | #define REGNO_REG_CLASS(REGNO) \ | |
2889abed BS |
723 | ((REGNO) == REG_R0 ? D0REGS \ |
724 | : (REGNO) == REG_R1 ? D1REGS \ | |
725 | : (REGNO) == REG_R2 ? D2REGS \ | |
726 | : (REGNO) == REG_R3 ? D3REGS \ | |
727 | : (REGNO) == REG_R4 ? D4REGS \ | |
728 | : (REGNO) == REG_R5 ? D5REGS \ | |
729 | : (REGNO) == REG_R6 ? D6REGS \ | |
730 | : (REGNO) == REG_R7 ? D7REGS \ | |
03848bd0 | 731 | : (REGNO) == REG_P0 ? P0REGS \ |
0d4a78eb | 732 | : (REGNO) < REG_I0 ? PREGS \ |
c4963a0a | 733 | : (REGNO) == REG_ARGP ? PREGS \ |
0d4a78eb BS |
734 | : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \ |
735 | : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \ | |
736 | : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \ | |
737 | : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \ | |
738 | : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \ | |
b03149e1 JZ |
739 | : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \ |
740 | : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \ | |
741 | : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \ | |
0d4a78eb BS |
742 | : (REGNO) == REG_CC ? CCREGS \ |
743 | : (REGNO) >= REG_RETS ? PROLOGUE_REGS \ | |
744 | : NO_REGS) | |
745 | ||
746 | /* When defined, the compiler allows registers explicitly used in the | |
747 | rtl to be used as spill registers but prevents the compiler from | |
748 | extending the lifetime of these registers. */ | |
749 | #define SMALL_REGISTER_CLASSES 1 | |
750 | ||
751 | #define CLASS_LIKELY_SPILLED_P(CLASS) \ | |
752 | ((CLASS) == PREGS_CLOBBERED \ | |
753 | || (CLASS) == PROLOGUE_REGS \ | |
03848bd0 | 754 | || (CLASS) == P0REGS \ |
2889abed BS |
755 | || (CLASS) == D0REGS \ |
756 | || (CLASS) == D1REGS \ | |
757 | || (CLASS) == D2REGS \ | |
0d4a78eb BS |
758 | || (CLASS) == CCREGS) |
759 | ||
760 | /* Do not allow to store a value in REG_CC for any mode */ | |
761 | /* Do not allow to store value in pregs if mode is not SI*/ | |
762 | #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE)) | |
763 | ||
764 | /* Return the maximum number of consecutive registers | |
765 | needed to represent mode MODE in a register of class CLASS. */ | |
75d8b2d0 BS |
766 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
767 | ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \ | |
768 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
0d4a78eb BS |
769 | |
770 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
75d8b2d0 BS |
771 | ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \ |
772 | : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \ | |
773 | : CLASS_MAX_NREGS (GENERAL_REGS, MODE)) | |
0d4a78eb BS |
774 | |
775 | /* A C expression that is nonzero if hard register TO can be | |
776 | considered for use as a rename register for FROM register */ | |
777 | #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO) | |
778 | ||
779 | /* A C expression that is nonzero if it is desirable to choose | |
780 | register allocation so as to avoid move instructions between a | |
781 | value of mode MODE1 and a value of mode MODE2. | |
782 | ||
783 | If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, | |
784 | MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1, | |
785 | MODE2)' must be zero. */ | |
4d4f2837 BS |
786 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
787 | ((MODE1) == (MODE2) \ | |
788 | || ((GET_MODE_CLASS (MODE1) == MODE_INT \ | |
789 | || GET_MODE_CLASS (MODE1) == MODE_FLOAT) \ | |
790 | && (GET_MODE_CLASS (MODE2) == MODE_INT \ | |
791 | || GET_MODE_CLASS (MODE2) == MODE_FLOAT) \ | |
792 | && (MODE1) != BImode && (MODE2) != BImode \ | |
793 | && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \ | |
794 | && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)) | |
0d4a78eb BS |
795 | |
796 | /* `PREFERRED_RELOAD_CLASS (X, CLASS)' | |
797 | A C expression that places additional restrictions on the register | |
798 | class to use when it is necessary to copy value X into a register | |
799 | in class CLASS. The value is a register class; perhaps CLASS, or | |
800 | perhaps another, smaller class. */ | |
aeffb4b5 BS |
801 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ |
802 | (GET_CODE (X) == POST_INC \ | |
803 | || GET_CODE (X) == POST_DEC \ | |
804 | || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS)) | |
0d4a78eb | 805 | |
0d4a78eb BS |
806 | /* Function Calling Conventions. */ |
807 | ||
808 | /* The type of the current function; normal functions are of type | |
809 | SUBROUTINE. */ | |
810 | typedef enum { | |
811 | SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER | |
812 | } e_funkind; | |
813 | ||
814 | #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 } | |
815 | ||
6d459e2b BS |
816 | /* Flags for the call/call_value rtl operations set up by function_arg */ |
817 | #define CALL_NORMAL 0x00000000 /* no special processing */ | |
818 | #define CALL_LONG 0x00000001 /* always call indirect */ | |
819 | #define CALL_SHORT 0x00000002 /* always call by symbol */ | |
820 | ||
0d4a78eb BS |
821 | typedef struct { |
822 | int words; /* # words passed so far */ | |
823 | int nregs; /* # registers available for passing */ | |
824 | int *arg_regs; /* array of register -1 terminated */ | |
6d459e2b | 825 | int call_cookie; /* Do special things for this call */ |
0d4a78eb BS |
826 | } CUMULATIVE_ARGS; |
827 | ||
828 | /* Define where to put the arguments to a function. | |
829 | Value is zero to push the argument on the stack, | |
830 | or a hard register in which to store the argument. | |
831 | ||
832 | MODE is the argument's machine mode. | |
833 | TYPE is the data type of the argument (as a tree). | |
834 | This is null for libcalls where that information may | |
835 | not be available. | |
836 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
837 | the preceding args and about the function being called. | |
838 | NAMED is nonzero if this argument is a named parameter | |
839 | (otherwise it is an extra parameter matching an ellipsis). */ | |
840 | ||
841 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
842 | (function_arg (&CUM, MODE, TYPE, NAMED)) | |
843 | ||
844 | #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO) | |
845 | ||
846 | ||
847 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
848 | for a call to a function whose data type is FNTYPE. | |
849 | For a library call, FNTYPE is 0. */ | |
850 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \ | |
851 | (init_cumulative_args (&CUM, FNTYPE, LIBNAME)) | |
852 | ||
853 | /* Update the data in CUM to advance over an argument | |
854 | of mode MODE and data type TYPE. | |
855 | (TYPE is null for libcalls where that information may not be available.) */ | |
856 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
857 | (function_arg_advance (&CUM, MODE, TYPE, NAMED)) | |
858 | ||
859 | #define RETURN_POPS_ARGS(FDECL, FUNTYPE, STKSIZE) 0 | |
860 | ||
861 | /* Define how to find the value returned by a function. | |
862 | VALTYPE is the data type of the value (as a tree). | |
863 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
864 | otherwise, FUNC is 0. | |
865 | */ | |
866 | ||
867 | #define VALUE_REGNO(MODE) (REG_R0) | |
868 | ||
869 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
870 | gen_rtx_REG (TYPE_MODE (VALTYPE), \ | |
871 | VALUE_REGNO(TYPE_MODE(VALTYPE))) | |
872 | ||
873 | /* Define how to find the value returned by a library function | |
874 | assuming the value has mode MODE. */ | |
875 | ||
876 | #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE)) | |
877 | ||
878 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0) | |
879 | ||
880 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
881 | #define RETURN_IN_MEMORY(TYPE) bfin_return_in_memory(TYPE) | |
882 | ||
883 | /* Before the prologue, the return address is in the RETS register. */ | |
884 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS) | |
885 | ||
886 | #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT) | |
887 | ||
888 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS) | |
889 | ||
890 | /* Call instructions don't modify the stack pointer on the Blackfin. */ | |
891 | #define INCOMING_FRAME_SP_OFFSET 0 | |
892 | ||
893 | /* Describe how we implement __builtin_eh_return. */ | |
894 | #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) | |
895 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2) | |
896 | #define EH_RETURN_HANDLER_RTX \ | |
1ca950ca | 897 | gen_frame_mem (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD)) |
0d4a78eb BS |
898 | |
899 | /* Addressing Modes */ | |
900 | ||
901 | /* Recognize any constant value that is a valid address. */ | |
902 | #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X)) | |
903 | ||
904 | /* Nonzero if the constant value X is a legitimate general operand. | |
905 | symbol_ref are not legitimate and will be put into constant pool. | |
906 | See force_const_mem(). | |
907 | If -mno-pool, all constants are legitimate. | |
908 | */ | |
d6f6753e | 909 | #define LEGITIMATE_CONSTANT_P(X) bfin_legitimate_constant_p (X) |
0d4a78eb BS |
910 | |
911 | /* A number, the maximum number of registers that can appear in a | |
912 | valid memory address. Note that it is up to you to specify a | |
913 | value equal to the maximum number that `GO_IF_LEGITIMATE_ADDRESS' | |
914 | would ever accept. */ | |
915 | #define MAX_REGS_PER_ADDRESS 1 | |
916 | ||
917 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
918 | that is a valid memory address for an instruction. | |
919 | The MODE argument is the machine mode for the MEM expression | |
920 | that wants to use this address. | |
921 | ||
922 | Blackfin addressing modes are as follows: | |
923 | ||
924 | [preg] | |
925 | [preg + imm16] | |
926 | ||
927 | B [ Preg + uimm15 ] | |
928 | W [ Preg + uimm16m2 ] | |
929 | [ Preg + uimm17m4 ] | |
930 | ||
931 | [preg++] | |
932 | [preg--] | |
933 | [--sp] | |
934 | */ | |
935 | ||
936 | #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \ | |
937 | (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode) | |
938 | ||
939 | #ifdef REG_OK_STRICT | |
940 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ | |
941 | do { \ | |
942 | if (bfin_legitimate_address_p (MODE, X, 1)) \ | |
943 | goto WIN; \ | |
944 | } while (0); | |
945 | #else | |
946 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ | |
947 | do { \ | |
948 | if (bfin_legitimate_address_p (MODE, X, 0)) \ | |
949 | goto WIN; \ | |
950 | } while (0); | |
951 | #endif | |
952 | ||
953 | /* Try machine-dependent ways of modifying an illegitimate address | |
954 | to be legitimate. If we find one, return the new, valid address. | |
955 | This macro is used in only one place: `memory_address' in explow.c. | |
956 | ||
957 | OLDX is the address as it was before break_out_memory_refs was called. | |
958 | In some cases it is useful to look at this to decide what needs to be done. | |
959 | ||
960 | MODE and WIN are passed so that this macro can use | |
961 | GO_IF_LEGITIMATE_ADDRESS. | |
962 | ||
963 | It is always safe for this macro to do nothing. It exists to recognize | |
964 | opportunities to optimize the output. | |
965 | */ | |
966 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
967 | do { \ | |
968 | rtx _q = legitimize_address(X, OLDX, MODE); \ | |
969 | if (_q) { X = _q; goto WIN; } \ | |
970 | } while (0) | |
971 | ||
972 | #define HAVE_POST_INCREMENT 1 | |
973 | #define HAVE_POST_DECREMENT 1 | |
974 | #define HAVE_PRE_DECREMENT 1 | |
975 | ||
976 | /* `LEGITIMATE_PIC_OPERAND_P (X)' | |
977 | A C expression that is nonzero if X is a legitimate immediate | |
978 | operand on the target machine when generating position independent | |
979 | code. You can assume that X satisfies `CONSTANT_P', so you need | |
980 | not check this. You can also assume FLAG_PIC is true, so you need | |
981 | not check it either. You need not define this macro if all | |
982 | constants (including `SYMBOL_REF') can be immediate operands when | |
983 | generating position independent code. */ | |
984 | #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X) | |
985 | ||
986 | #define SYMBOLIC_CONST(X) \ | |
987 | (GET_CODE (X) == SYMBOL_REF \ | |
988 | || GET_CODE (X) == LABEL_REF \ | |
989 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
990 | ||
991 | /* | |
992 | A C statement or compound statement with a conditional `goto | |
993 | LABEL;' executed if memory address X (an RTX) can have different | |
994 | meanings depending on the machine mode of the memory reference it | |
995 | is used for or if the address is valid for some modes but not | |
996 | others. | |
997 | ||
998 | Autoincrement and autodecrement addresses typically have | |
999 | mode-dependent effects because the amount of the increment or | |
1000 | decrement is the size of the operand being addressed. Some | |
1001 | machines have other mode-dependent addresses. Many RISC machines | |
1002 | have no mode-dependent addresses. | |
1003 | ||
1004 | You may assume that ADDR is a valid address for the machine. | |
1005 | */ | |
b9a76028 | 1006 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) |
0d4a78eb BS |
1007 | |
1008 | #define NOTICE_UPDATE_CC(EXPR, INSN) 0 | |
1009 | ||
1010 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1011 | is done just by pretending it is already truncated. */ | |
1012 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1013 | ||
1014 | /* Max number of bytes we can move from memory to memory | |
1015 | in one reasonably fast instruction. */ | |
1016 | #define MOVE_MAX UNITS_PER_WORD | |
1017 | ||
b548a9c2 BS |
1018 | /* If a memory-to-memory move would take MOVE_RATIO or more simple |
1019 | move-instruction pairs, we will do a movmem or libcall instead. */ | |
1020 | ||
1021 | #define MOVE_RATIO 5 | |
0d4a78eb BS |
1022 | |
1023 | /* STORAGE LAYOUT: target machine storage layout | |
1024 | Define this macro as a C expression which is nonzero if accessing | |
1025 | less than a word of memory (i.e. a `char' or a `short') is no | |
1026 | faster than accessing a word of memory, i.e., if such access | |
1027 | require more than one instruction or if there is no difference in | |
1028 | cost between byte and (aligned) word loads. | |
1029 | ||
1030 | When this macro is not defined, the compiler will access a field by | |
1031 | finding the smallest containing object; when it is defined, a | |
1032 | fullword load will be used if alignment permits. Unless bytes | |
1033 | accesses are faster than word accesses, using word accesses is | |
1034 | preferable since it may eliminate subsequent memory access if | |
1035 | subsequent accesses occur to other fields in the same word of the | |
1036 | structure, but to different bytes. */ | |
1037 | #define SLOW_BYTE_ACCESS 0 | |
1038 | #define SLOW_SHORT_ACCESS 0 | |
1039 | ||
1040 | /* Define this if most significant bit is lowest numbered | |
1041 | in instructions that operate on numbered bit-fields. */ | |
1042 | #define BITS_BIG_ENDIAN 0 | |
1043 | ||
1044 | /* Define this if most significant byte of a word is the lowest numbered. | |
1045 | We can't access bytes but if we could we would in the Big Endian order. */ | |
1046 | #define BYTES_BIG_ENDIAN 0 | |
1047 | ||
1048 | /* Define this if most significant word of a multiword number is numbered. */ | |
1049 | #define WORDS_BIG_ENDIAN 0 | |
1050 | ||
1051 | /* number of bits in an addressable storage unit */ | |
1052 | #define BITS_PER_UNIT 8 | |
1053 | ||
1054 | /* Width in bits of a "word", which is the contents of a machine register. | |
1055 | Note that this is not necessarily the width of data type `int'; | |
1056 | if using 16-bit ints on a 68000, this would still be 32. | |
1057 | But on a machine with 16-bit registers, this would be 16. */ | |
1058 | #define BITS_PER_WORD 32 | |
1059 | ||
1060 | /* Width of a word, in units (bytes). */ | |
1061 | #define UNITS_PER_WORD 4 | |
1062 | ||
0d4a78eb BS |
1063 | /* Width in bits of a pointer. |
1064 | See also the macro `Pmode1' defined below. */ | |
1065 | #define POINTER_SIZE 32 | |
1066 | ||
1067 | /* Allocation boundary (in *bits*) for storing pointers in memory. */ | |
1068 | #define POINTER_BOUNDARY 32 | |
1069 | ||
1070 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
1071 | #define PARM_BOUNDARY 32 | |
1072 | ||
1073 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
1074 | #define STACK_BOUNDARY 32 | |
1075 | ||
1076 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
1077 | #define FUNCTION_BOUNDARY 32 | |
1078 | ||
1079 | /* Alignment of field after `int : 0' in a structure. */ | |
1080 | #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD | |
1081 | ||
1082 | /* No data type wants to be aligned rounder than this. */ | |
1083 | #define BIGGEST_ALIGNMENT 32 | |
1084 | ||
1085 | /* Define this if move instructions will actually fail to work | |
1086 | when given unaligned data. */ | |
1087 | #define STRICT_ALIGNMENT 1 | |
1088 | ||
1089 | /* (shell-command "rm c-decl.o stor-layout.o") | |
1090 | * never define PCC_BITFIELD_TYPE_MATTERS | |
1091 | * really cause some alignment problem | |
1092 | */ | |
1093 | ||
1094 | #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \ | |
1095 | BITS_PER_UNIT) | |
1096 | ||
1097 | #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \ | |
1098 | BITS_PER_UNIT) | |
1099 | ||
1100 | ||
1101 | /* what is the 'type' of size_t */ | |
1102 | #define SIZE_TYPE "long unsigned int" | |
1103 | ||
1104 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
1105 | #define DEFAULT_SIGNED_CHAR 1 | |
1106 | #define FLOAT_TYPE_SIZE BITS_PER_WORD | |
1107 | #define SHORT_TYPE_SIZE 16 | |
1108 | #define CHAR_TYPE_SIZE 8 | |
1109 | #define INT_TYPE_SIZE 32 | |
1110 | #define LONG_TYPE_SIZE 32 | |
1111 | #define LONG_LONG_TYPE_SIZE 64 | |
1112 | ||
1113 | /* Note: Fix this to depend on target switch. -- lev */ | |
1114 | ||
1115 | /* Note: Try to implement double and force long double. -- tonyko | |
1116 | * #define __DOUBLES_ARE_FLOATS__ | |
1117 | * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE | |
1118 | * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE | |
1119 | * #define DOUBLES_ARE_FLOATS 1 | |
1120 | */ | |
1121 | ||
1122 | #define DOUBLE_TYPE_SIZE 64 | |
1123 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
1124 | ||
1125 | /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)' | |
1126 | A macro to update M and UNSIGNEDP when an object whose type is | |
1127 | TYPE and which has the specified mode and signedness is to be | |
1128 | stored in a register. This macro is only called when TYPE is a | |
1129 | scalar type. | |
1130 | ||
1131 | On most RISC machines, which only have operations that operate on | |
1132 | a full register, define this macro to set M to `word_mode' if M is | |
1133 | an integer mode narrower than `BITS_PER_WORD'. In most cases, | |
1134 | only integer modes should be widened because wider-precision | |
1135 | floating-point operations are usually more expensive than their | |
1136 | narrower counterparts. | |
1137 | ||
1138 | For most machines, the macro definition does not change UNSIGNEDP. | |
1139 | However, some machines, have instructions that preferentially | |
1140 | handle either signed or unsigned quantities of certain modes. For | |
1141 | example, on the DEC Alpha, 32-bit loads from memory and 32-bit add | |
1142 | instructions sign-extend the result to 64 bits. On such machines, | |
1143 | set UNSIGNEDP according to which kind of extension is more | |
1144 | efficient. | |
1145 | ||
1146 | Do not define this macro if it would never modify M.*/ | |
1147 | ||
1148 | #define BFIN_PROMOTE_MODE_P(MODE) \ | |
1149 | (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \ | |
1150 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) | |
1151 | ||
1152 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
1153 | if (BFIN_PROMOTE_MODE_P(MODE)) \ | |
1154 | { \ | |
1155 | if (MODE == QImode) \ | |
1156 | UNSIGNEDP = 1; \ | |
1157 | else if (MODE == HImode) \ | |
1158 | UNSIGNEDP = 0; \ | |
1159 | (MODE) = SImode; \ | |
1160 | } | |
1161 | ||
1162 | /* Describing Relative Costs of Operations */ | |
1163 | ||
1164 | /* Do not put function addr into constant pool */ | |
1165 | #define NO_FUNCTION_CSE 1 | |
1166 | ||
1167 | /* A C expression for the cost of moving data from a register in class FROM to | |
1168 | one in class TO. The classes are expressed using the enumeration values | |
1169 | such as `GENERAL_REGS'. A value of 2 is the default; other values are | |
1170 | interpreted relative to that. | |
1171 | ||
1172 | It is not required that the cost always equal 2 when FROM is the same as TO; | |
1173 | on some machines it is expensive to move between registers if they are not | |
1174 | general registers. */ | |
1175 | ||
1176 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ | |
1177 | bfin_register_move_cost ((MODE), (CLASS1), (CLASS2)) | |
1178 | ||
1179 | /* A C expression for the cost of moving data of mode M between a | |
1180 | register and memory. A value of 2 is the default; this cost is | |
1181 | relative to those in `REGISTER_MOVE_COST'. | |
1182 | ||
1183 | If moving between registers and memory is more expensive than | |
1184 | between two registers, you should define this macro to express the | |
1185 | relative cost. */ | |
1186 | ||
1187 | #define MEMORY_MOVE_COST(MODE, CLASS, IN) \ | |
1188 | bfin_memory_move_cost ((MODE), (CLASS), (IN)) | |
1189 | ||
1190 | /* Specify the machine mode that this machine uses | |
1191 | for the index in the tablejump instruction. */ | |
1192 | #define CASE_VECTOR_MODE SImode | |
1193 | ||
1194 | #define JUMP_TABLES_IN_TEXT_SECTION flag_pic | |
1195 | ||
1196 | /* Define if operations between registers always perform the operation | |
1197 | on the full register even if a narrower mode is specified. | |
1198 | #define WORD_REGISTER_OPERATIONS | |
1199 | */ | |
1200 | ||
1201 | #define CONST_18UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 262140) | |
1202 | #define CONST_16BIT_IMM_P(VALUE) ((VALUE) >= -32768 && (VALUE) <= 32767) | |
1203 | #define CONST_16UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 65535) | |
1204 | #define CONST_7BIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 63) | |
1205 | #define CONST_7NBIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 0) | |
1206 | #define CONST_5UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 31) | |
1207 | #define CONST_4BIT_IMM_P(VALUE) ((VALUE) >= -8 && (VALUE) <= 7) | |
1208 | #define CONST_4UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 15) | |
1209 | #define CONST_3BIT_IMM_P(VALUE) ((VALUE) >= -4 && (VALUE) <= 3) | |
1210 | #define CONST_3UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 7) | |
1211 | ||
1212 | #define CONSTRAINT_LEN(C, STR) \ | |
2889abed | 1213 | ((C) == 'P' || (C) == 'M' || (C) == 'N' || (C) == 'q' ? 2 \ |
0d4a78eb BS |
1214 | : (C) == 'K' ? 3 \ |
1215 | : DEFAULT_CONSTRAINT_LEN ((C), (STR))) | |
1216 | ||
1217 | #define CONST_OK_FOR_P(VALUE, STR) \ | |
1218 | ((STR)[1] == '0' ? (VALUE) == 0 \ | |
1219 | : (STR)[1] == '1' ? (VALUE) == 1 \ | |
1220 | : (STR)[1] == '2' ? (VALUE) == 2 \ | |
1221 | : (STR)[1] == '3' ? (VALUE) == 3 \ | |
1222 | : (STR)[1] == '4' ? (VALUE) == 4 \ | |
3efd5670 BS |
1223 | : (STR)[1] == 'A' ? (VALUE) != MACFLAG_M && (VALUE) != MACFLAG_IS_M \ |
1224 | : (STR)[1] == 'B' ? (VALUE) == MACFLAG_M || (VALUE) == MACFLAG_IS_M \ | |
0d4a78eb BS |
1225 | : 0) |
1226 | ||
1227 | #define CONST_OK_FOR_K(VALUE, STR) \ | |
1228 | ((STR)[1] == 'u' \ | |
1229 | ? ((STR)[2] == '3' ? CONST_3UBIT_IMM_P (VALUE) \ | |
1230 | : (STR)[2] == '4' ? CONST_4UBIT_IMM_P (VALUE) \ | |
1231 | : (STR)[2] == '5' ? CONST_5UBIT_IMM_P (VALUE) \ | |
1232 | : (STR)[2] == 'h' ? CONST_16UBIT_IMM_P (VALUE) \ | |
1233 | : 0) \ | |
1234 | : (STR)[1] == 's' \ | |
1235 | ? ((STR)[2] == '3' ? CONST_3BIT_IMM_P (VALUE) \ | |
1236 | : (STR)[2] == '4' ? CONST_4BIT_IMM_P (VALUE) \ | |
1237 | : (STR)[2] == '7' ? CONST_7BIT_IMM_P (VALUE) \ | |
1238 | : (STR)[2] == 'h' ? CONST_16BIT_IMM_P (VALUE) \ | |
1239 | : 0) \ | |
1240 | : (STR)[1] == 'n' \ | |
1241 | ? ((STR)[2] == '7' ? CONST_7NBIT_IMM_P (VALUE) \ | |
1242 | : 0) \ | |
d4e85050 BS |
1243 | : (STR)[1] == 'N' \ |
1244 | ? ((STR)[2] == '7' ? CONST_7BIT_IMM_P (-(VALUE)) \ | |
1245 | : 0) \ | |
0d4a78eb BS |
1246 | : 0) |
1247 | ||
1248 | #define CONST_OK_FOR_M(VALUE, STR) \ | |
1249 | ((STR)[1] == '1' ? (VALUE) == 255 \ | |
1250 | : (STR)[1] == '2' ? (VALUE) == 65535 \ | |
1251 | : 0) | |
1252 | ||
1253 | /* The letters I, J, K, L and M in a register constraint string | |
1254 | can be used to stand for particular ranges of immediate operands. | |
1255 | This macro defines what the ranges are. | |
1256 | C is the letter, and VALUE is a constant value. | |
1257 | Return 1 if VALUE is in the range specified by C. | |
1258 | ||
1259 | bfin constant operands are as follows | |
1260 | ||
1261 | J 2**N 5bit imm scaled | |
1262 | Ks7 -64 .. 63 signed 7bit imm | |
1263 | Ku5 0..31 unsigned 5bit imm | |
1264 | Ks4 -8 .. 7 signed 4bit imm | |
1265 | Ks3 -4 .. 3 signed 3bit imm | |
1266 | Ku3 0 .. 7 unsigned 3bit imm | |
1267 | Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n | |
1268 | */ | |
1269 | #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \ | |
1270 | ((C) == 'J' ? (log2constp (VALUE)) \ | |
1271 | : (C) == 'K' ? CONST_OK_FOR_K (VALUE, STR) \ | |
1272 | : (C) == 'L' ? log2constp (~(VALUE)) \ | |
1273 | : (C) == 'M' ? CONST_OK_FOR_M (VALUE, STR) \ | |
1274 | : (C) == 'P' ? CONST_OK_FOR_P (VALUE, STR) \ | |
1275 | : 0) | |
1276 | ||
1277 | /*Constant Output Formats */ | |
1278 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
1279 | ((C) == 'H' ? 1 : 0) | |
1280 | ||
1281 | #define EXTRA_CONSTRAINT(VALUE, D) \ | |
1282 | ((D) == 'Q' ? GET_CODE (VALUE) == SYMBOL_REF : 0) | |
1283 | ||
3efd5670 BS |
1284 | /* Evaluates to true if A and B are mac flags that can be used |
1285 | together in a single multiply insn. That is the case if they are | |
1286 | both the same flag not involving M, or if one is a combination of | |
1287 | the other with M. */ | |
1288 | #define MACFLAGS_MATCH_P(A, B) \ | |
1289 | ((A) == (B) \ | |
1290 | || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \ | |
1291 | || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \ | |
1292 | || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \ | |
1293 | || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS)) | |
1294 | ||
0d4a78eb BS |
1295 | /* Switch into a generic section. */ |
1296 | #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section | |
1297 | ||
1298 | #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE) | |
1299 | #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX) | |
1300 | ||
1301 | typedef enum sections { | |
1302 | CODE_DIR, | |
1303 | DATA_DIR, | |
1304 | LAST_SECT_NM | |
1305 | } SECT_ENUM_T; | |
1306 | ||
1307 | typedef enum directives { | |
1308 | LONG_CONST_DIR, | |
1309 | SHORT_CONST_DIR, | |
1310 | BYTE_CONST_DIR, | |
1311 | SPACE_DIR, | |
1312 | INIT_DIR, | |
1313 | LAST_DIR_NM | |
1314 | } DIR_ENUM_T; | |
1315 | ||
980d8882 BS |
1316 | #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \ |
1317 | ((C) == ';' \ | |
1318 | || ((C) == '|' && (STR)[1] == '|')) | |
1319 | ||
0d4a78eb BS |
1320 | #define TEXT_SECTION_ASM_OP ".text;" |
1321 | #define DATA_SECTION_ASM_OP ".data;" | |
1322 | ||
1323 | #define ASM_APP_ON "" | |
1324 | #define ASM_APP_OFF "" | |
1325 | ||
1326 | #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \ | |
1327 | do { fputs (".global ", FILE); \ | |
1328 | assemble_name (FILE, NAME); \ | |
1329 | fputc (';',FILE); \ | |
1330 | fputc ('\n',FILE); \ | |
1331 | } while (0) | |
1332 | ||
1333 | #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ | |
1334 | do { \ | |
1335 | fputs (".type ", FILE); \ | |
1336 | assemble_name (FILE, NAME); \ | |
1337 | fputs (", STT_FUNC", FILE); \ | |
1338 | fputc (';',FILE); \ | |
1339 | fputc ('\n',FILE); \ | |
1340 | ASM_OUTPUT_LABEL(FILE, NAME); \ | |
1341 | } while (0) | |
1342 | ||
1343 | #define ASM_OUTPUT_LABEL(FILE, NAME) \ | |
1344 | do { assemble_name (FILE, NAME); \ | |
1345 | fputs (":\n",FILE); \ | |
1346 | } while (0) | |
1347 | ||
1348 | #define ASM_OUTPUT_LABELREF(FILE,NAME) \ | |
1349 | do { fprintf (FILE, "_%s", NAME); \ | |
1350 | } while (0) | |
1351 | ||
0d4a78eb BS |
1352 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ |
1353 | do { char __buf[256]; \ | |
1354 | fprintf (FILE, "\t.dd\t"); \ | |
1355 | ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ | |
1356 | assemble_name (FILE, __buf); \ | |
1357 | fputc (';', FILE); \ | |
1358 | fputc ('\n', FILE); \ | |
1359 | } while (0) | |
1360 | ||
1361 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
1362 | MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) | |
1363 | ||
1364 | #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ | |
1365 | do { \ | |
1366 | char __buf[256]; \ | |
1367 | fprintf (FILE, "\t.dd\t"); \ | |
1368 | ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ | |
1369 | assemble_name (FILE, __buf); \ | |
1370 | fputs (" - ", FILE); \ | |
1371 | ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \ | |
1372 | assemble_name (FILE, __buf); \ | |
1373 | fputc (';', FILE); \ | |
1374 | fputc ('\n', FILE); \ | |
1375 | } while (0) | |
1376 | ||
1377 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
21956c07 BS |
1378 | do { \ |
1379 | if ((LOG) != 0) \ | |
1380 | fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \ | |
0d4a78eb BS |
1381 | } while (0) |
1382 | ||
1383 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
1384 | do { \ | |
1385 | asm_output_skip (FILE, SIZE); \ | |
1386 | } while (0) | |
1387 | ||
1388 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ | |
1389 | do { \ | |
d6b5193b | 1390 | switch_to_section (data_section); \ |
0d4a78eb BS |
1391 | if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \ |
1392 | ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \ | |
1393 | ASM_OUTPUT_LABEL (FILE, NAME); \ | |
1394 | fprintf (FILE, "%s %ld;\n", ASM_SPACE, \ | |
1395 | (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \ | |
1396 | } while (0) | |
1397 | ||
1398 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
1399 | do { \ | |
1400 | ASM_GLOBALIZE_LABEL1(FILE,NAME); \ | |
1401 | ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0) | |
1402 | ||
1403 | #define ASM_COMMENT_START "//" | |
1404 | ||
56014148 JZ |
1405 | #define FUNCTION_PROFILER(FILE, LABELNO) \ |
1406 | do { \ | |
1407 | fprintf (FILE, "\tCALL __mcount;\n"); \ | |
0d4a78eb BS |
1408 | } while(0) |
1409 | ||
56014148 JZ |
1410 | #undef NO_PROFILE_COUNTERS |
1411 | #define NO_PROFILE_COUNTERS 1 | |
1412 | ||
0d4a78eb BS |
1413 | #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO]) |
1414 | #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO]) | |
1415 | ||
1416 | extern struct rtx_def *bfin_compare_op0, *bfin_compare_op1; | |
1417 | extern struct rtx_def *bfin_cc_rtx, *bfin_rets_rtx; | |
1418 | ||
1419 | /* This works for GAS and some other assemblers. */ | |
1420 | #define SET_ASM_OP ".set " | |
1421 | ||
0d4a78eb BS |
1422 | /* DBX register number for a given compiler register number */ |
1423 | #define DBX_REGISTER_NUMBER(REGNO) (REGNO) | |
1424 | ||
1425 | #define SIZE_ASM_OP "\t.size\t" | |
1426 | ||
bbbc206e BS |
1427 | extern int splitting_for_sched; |
1428 | ||
1429 | #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!') | |
1430 | ||
0d4a78eb | 1431 | #endif /* _BFIN_CONFIG */ |