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1 | /* Definitions for the Blackfin port. |
2 | Copyright (C) 2005 Free Software Foundation, Inc. | |
3 | Contributed by Analog Devices. | |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it | |
8 | under the terms of the GNU General Public License as published | |
9 | by the Free Software Foundation; either version 2, or (at your | |
10 | option) any later version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING. If not, write to | |
39d14dda KC |
19 | the Free Software Foundation, 51 Franklin Street, Fifth Floor, |
20 | Boston, MA 02110-1301, USA. */ | |
0d4a78eb BS |
21 | |
22 | #ifndef _BFIN_CONFIG | |
23 | #define _BFIN_CONFIG | |
24 | ||
25 | #define OBJECT_FORMAT_ELF | |
26 | ||
27 | #define BRT 1 | |
28 | #define BRF 0 | |
29 | ||
30 | /* Print subsidiary information on the compiler version in use. */ | |
31 | #define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)") | |
32 | ||
33 | /* Run-time compilation parameters selecting different hardware subsets. */ | |
34 | ||
35 | extern int target_flags; | |
36 | ||
37 | /* Predefinition in the preprocessor for this target machine */ | |
38 | #ifndef TARGET_CPU_CPP_BUILTINS | |
39 | #define TARGET_CPU_CPP_BUILTINS() \ | |
40 | do \ | |
41 | { \ | |
42 | builtin_define ("bfin"); \ | |
43 | builtin_define ("BFIN"); \ | |
44 | } \ | |
45 | while (0) | |
46 | #endif | |
47 | ||
48 | /* Generate DSP instructions, like DSP halfword loads */ | |
49 | #define TARGET_DSP (1) | |
50 | ||
3fb192d2 | 51 | #define TARGET_DEFAULT (MASK_SPECLD_ANOMALY | MASK_CSYNC_ANOMALY) |
0d4a78eb | 52 | |
0d4a78eb BS |
53 | /* Maximum number of library ids we permit */ |
54 | #define MAX_LIBRARY_ID 255 | |
55 | ||
56 | extern const char *bfin_library_id_string; | |
57 | ||
58 | /* Sometimes certain combinations of command options do not make | |
59 | sense on a particular target machine. You can define a macro | |
60 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
61 | defined, is executed once just after all the command options have | |
62 | been parsed. | |
63 | ||
64 | Don't use this macro to turn on various extra optimizations for | |
65 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
66 | ||
67 | #define OVERRIDE_OPTIONS override_options () | |
68 | ||
69 | #define FUNCTION_MODE SImode | |
70 | #define Pmode SImode | |
71 | ||
72 | /* store-condition-codes instructions store 0 for false | |
73 | This is the value stored for true. */ | |
74 | #define STORE_FLAG_VALUE 1 | |
75 | ||
76 | /* Define this if pushing a word on the stack | |
77 | makes the stack pointer a smaller address. */ | |
78 | #define STACK_GROWS_DOWNWARD | |
79 | ||
80 | #define STACK_PUSH_CODE PRE_DEC | |
81 | ||
a4d05547 | 82 | /* Define this to nonzero if the nominal address of the stack frame |
0d4a78eb BS |
83 | is at the high-address end of the local variables; |
84 | that is, each additional local variable allocated | |
85 | goes at a more negative offset in the frame. */ | |
f62c8a5c | 86 | #define FRAME_GROWS_DOWNWARD 1 |
0d4a78eb BS |
87 | |
88 | /* We define a dummy ARGP register; the parameters start at offset 0 from | |
89 | it. */ | |
90 | #define FIRST_PARM_OFFSET(DECL) 0 | |
91 | ||
92 | /* Offset within stack frame to start allocating local variables at. | |
93 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
94 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
95 | of the first local allocated. */ | |
96 | #define STARTING_FRAME_OFFSET 0 | |
97 | ||
98 | /* Register to use for pushing function arguments. */ | |
99 | #define STACK_POINTER_REGNUM REG_P6 | |
100 | ||
101 | /* Base register for access to local variables of the function. */ | |
102 | #define FRAME_POINTER_REGNUM REG_P7 | |
103 | ||
104 | /* A dummy register that will be eliminated to either FP or SP. */ | |
105 | #define ARG_POINTER_REGNUM REG_ARGP | |
106 | ||
107 | /* `PIC_OFFSET_TABLE_REGNUM' | |
108 | The register number of the register used to address a table of | |
109 | static data addresses in memory. In some cases this register is | |
110 | defined by a processor's "application binary interface" (ABI). | |
111 | When this macro is defined, RTL is generated for this register | |
112 | once, as with the stack pointer and frame pointer registers. If | |
113 | this macro is not defined, it is up to the machine-dependent files | |
114 | to allocate such a register (if necessary). */ | |
115 | #define PIC_OFFSET_TABLE_REGNUM (REG_P5) | |
116 | ||
117 | /* A static chain register for nested functions. We need to use a | |
118 | call-clobbered register for this. */ | |
119 | #define STATIC_CHAIN_REGNUM REG_P2 | |
120 | ||
121 | /* Define this if functions should assume that stack space has been | |
122 | allocated for arguments even when their values are passed in | |
123 | registers. | |
124 | ||
125 | The value of this macro is the size, in bytes, of the area reserved for | |
126 | arguments passed in registers. | |
127 | ||
128 | This space can either be allocated by the caller or be a part of the | |
129 | machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' | |
130 | says which. */ | |
131 | #define FIXED_STACK_AREA 12 | |
132 | #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA | |
133 | ||
134 | /* Define this if the above stack space is to be considered part of the | |
135 | * space allocated by the caller. */ | |
136 | #define OUTGOING_REG_PARM_STACK_SPACE | |
137 | ||
138 | /* Define this if the maximum size of all the outgoing args is to be | |
139 | accumulated and pushed during the prologue. The amount can be | |
140 | found in the variable current_function_outgoing_args_size. */ | |
141 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
142 | ||
143 | /* Value should be nonzero if functions must have frame pointers. | |
144 | Zero means the frame pointer need not be set up (and parms | |
145 | may be accessed via the stack pointer) in functions that seem suitable. | |
146 | This is computed in `reload', in reload1.c. | |
147 | */ | |
148 | #define FRAME_POINTER_REQUIRED (bfin_frame_pointer_required ()) | |
149 | ||
150 | #define PARM_BOUNDRY 32 | |
151 | ||
152 | #define STACK_BOUNDRY 32 | |
153 | ||
154 | /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */ | |
155 | ||
156 | /* Make strings word-aligned so strcpy from constants will be faster. */ | |
157 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
158 | (TREE_CODE (EXP) == STRING_CST \ | |
159 | && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
160 | ||
161 | #define TRAMPOLINE_SIZE 18 | |
162 | #define TRAMPOLINE_TEMPLATE(FILE) \ | |
163 | fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \ | |
164 | fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */; \ | |
165 | fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */; \ | |
166 | fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */; \ | |
167 | fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ | |
168 | ||
169 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
170 | initialize_trampoline (TRAMP, FNADDR, CXT) | |
171 | \f | |
172 | /* Definitions for register eliminations. | |
173 | ||
174 | This is an array of structures. Each structure initializes one pair | |
175 | of eliminable registers. The "from" register number is given first, | |
176 | followed by "to". Eliminations of the same "from" register are listed | |
177 | in order of preference. | |
178 | ||
179 | There are two registers that can always be eliminated on the i386. | |
180 | The frame pointer and the arg pointer can be replaced by either the | |
181 | hard frame pointer or to the stack pointer, depending upon the | |
182 | circumstances. The hard frame pointer is not used before reload and | |
183 | so it is not eligible for elimination. */ | |
184 | ||
185 | #define ELIMINABLE_REGS \ | |
186 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
187 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ | |
188 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \ | |
189 | ||
190 | /* Given FROM and TO register numbers, say whether this elimination is | |
191 | allowed. Frame pointer elimination is automatically handled. | |
192 | ||
193 | All other eliminations are valid. */ | |
194 | ||
195 | #define CAN_ELIMINATE(FROM, TO) \ | |
196 | ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) | |
197 | ||
198 | /* Define the offset between two registers, one to be eliminated, and the other | |
199 | its replacement, at the start of a routine. */ | |
200 | ||
201 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
202 | ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO))) | |
203 | \f | |
204 | /* This processor has | |
205 | 8 data register for doing arithmetic | |
206 | 8 pointer register for doing addressing, including | |
207 | 1 stack pointer P6 | |
208 | 1 frame pointer P7 | |
209 | 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3) | |
210 | 1 condition code flag register CC | |
211 | 5 return address registers RETS/I/X/N/E | |
212 | 1 arithmetic status register (ASTAT). */ | |
213 | ||
214 | #define FIRST_PSEUDO_REGISTER 44 | |
215 | ||
216 | #define PREG_P(X) (REG_P (X) && REGNO (X) >= REG_P0 && REGNO (X) <= REG_P7) | |
217 | #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3) | |
218 | #define D_REGNO_P(X) ((X) <= REG_R7) | |
219 | ||
220 | #define REGISTER_NAMES { \ | |
221 | "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \ | |
222 | "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \ | |
223 | "I0", "B0", "L0", "I1", "B1", "L1", "I2", "B2", \ | |
224 | "L2", "I3", "B3", "L3", "M0", "M1", "M2", "M3", \ | |
225 | "A0", "A1", \ | |
226 | "CC", \ | |
227 | "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \ | |
228 | "ARGP" \ | |
229 | } | |
230 | ||
231 | #define SHORT_REGISTER_NAMES { \ | |
232 | "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \ | |
233 | "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \ | |
234 | "I0.L", "B0.L", "L0.L", "I1.L", "B1.L", "L1.L", "I2.L", "B2.L", \ | |
235 | "L2.L", "I3.L", "B3.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", } | |
236 | ||
237 | #define HIGH_REGISTER_NAMES { \ | |
238 | "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \ | |
239 | "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \ | |
240 | "I0.H", "B0.H", "L0.H", "I1.H", "B1.H", "L1.H", "I2.H", "B2.H", \ | |
241 | "L2.H", "I3.H", "B3.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", } | |
242 | ||
243 | #define DREGS_PAIR_NAMES { \ | |
244 | "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, } | |
245 | ||
246 | #define BYTE_REGISTER_NAMES { \ | |
247 | "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", } | |
248 | ||
249 | ||
250 | /* 1 for registers that have pervasive standard uses | |
251 | and are not available for the register allocator. */ | |
252 | ||
253 | #define FIXED_REGISTERS \ | |
254 | /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \ | |
255 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ | |
256 | /*i0 b0 l0 i1 b1 l1 i2 b2 l2 i3 b3 l3 m0 m1 m2 m3 */ \ | |
257 | 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, \ | |
258 | /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp */ \ | |
259 | 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ | |
260 | } | |
261 | ||
262 | /* 1 for registers not available across function calls. | |
263 | These must include the FIXED_REGISTERS and also any | |
264 | registers that can be used without being saved. | |
265 | The latter must include the registers where values are returned | |
266 | and the register where structure-value addresses are passed. | |
267 | Aside from that, you can include as many other registers as you like. */ | |
268 | ||
269 | #define CALL_USED_REGISTERS \ | |
270 | /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \ | |
271 | { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \ | |
272 | /*i0 b0 l0 i1 b1 l1 i2 b2 l2 i3 b3 l3 m0 m1 m2 m3 */ \ | |
273 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
274 | /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp */ \ | |
275 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ | |
276 | } | |
277 | ||
278 | /* Order in which to allocate registers. Each register must be | |
279 | listed once, even those in FIXED_REGISTERS. List frame pointer | |
280 | late and fixed registers last. Note that, in general, we prefer | |
281 | registers listed in CALL_USED_REGISTERS, keeping the others | |
282 | available for storage of persistent values. */ | |
283 | ||
284 | #define REG_ALLOC_ORDER \ | |
285 | { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \ | |
286 | REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \ | |
287 | REG_A0, REG_A1, \ | |
288 | REG_I0, REG_B0, REG_L0, REG_I1, REG_B1, REG_L1, REG_I2, REG_B2, \ | |
289 | REG_L2, REG_I3, REG_B3, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \ | |
290 | REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \ | |
291 | REG_ASTAT, REG_SEQSTAT, REG_USP, \ | |
292 | REG_CC, REG_ARGP \ | |
293 | } | |
294 | ||
295 | /* Macro to conditionally modify fixed_regs/call_used_regs. */ | |
296 | #define CONDITIONAL_REGISTER_USAGE \ | |
297 | { \ | |
298 | conditional_register_usage(); \ | |
299 | if (flag_pic) \ | |
300 | { \ | |
301 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
302 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
303 | } \ | |
304 | } | |
305 | ||
306 | /* Define the classes of registers for register constraints in the | |
307 | machine description. Also define ranges of constants. | |
308 | ||
309 | One of the classes must always be named ALL_REGS and include all hard regs. | |
310 | If there is more than one class, another class must be named NO_REGS | |
311 | and contain no registers. | |
312 | ||
313 | The name GENERAL_REGS must be the name of a class (or an alias for | |
314 | another name such as ALL_REGS). This is the class of registers | |
315 | that is allowed by "g" or "r" in a register constraint. | |
316 | Also, registers outside this class are allocated only when | |
317 | instructions express preferences for them. | |
318 | ||
319 | The classes must be numbered in nondecreasing order; that is, | |
320 | a larger-numbered class must never be contained completely | |
321 | in a smaller-numbered class. | |
322 | ||
323 | For any two classes, it is very desirable that there be another | |
324 | class that represents their union. */ | |
325 | ||
326 | ||
327 | enum reg_class | |
328 | { | |
329 | NO_REGS, | |
330 | IREGS, | |
331 | BREGS, | |
332 | LREGS, | |
333 | MREGS, | |
f652d14b | 334 | CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */ |
0d4a78eb BS |
335 | DAGREGS, |
336 | EVEN_AREGS, | |
337 | ODD_AREGS, | |
338 | AREGS, | |
339 | CCREGS, | |
340 | EVEN_DREGS, | |
341 | ODD_DREGS, | |
342 | DREGS, | |
343 | PREGS_CLOBBERED, | |
344 | PREGS, | |
345 | DPREGS, | |
346 | MOST_REGS, | |
347 | PROLOGUE_REGS, | |
348 | NON_A_CC_REGS, | |
349 | ALL_REGS, LIM_REG_CLASSES | |
350 | }; | |
351 | ||
352 | #define N_REG_CLASSES ((int)LIM_REG_CLASSES) | |
353 | ||
354 | #define GENERAL_REGS DPREGS | |
355 | ||
356 | /* Give names of register classes as strings for dump file. */ | |
357 | ||
358 | #define REG_CLASS_NAMES \ | |
359 | { "NO_REGS", \ | |
360 | "IREGS", \ | |
361 | "BREGS", \ | |
362 | "LREGS", \ | |
363 | "MREGS", \ | |
364 | "CIRCREGS", \ | |
365 | "DAGREGS", \ | |
366 | "EVEN_AREGS", \ | |
367 | "ODD_AREGS", \ | |
368 | "AREGS", \ | |
369 | "CCREGS", \ | |
370 | "EVEN_DREGS", \ | |
371 | "ODD_DREGS", \ | |
372 | "DREGS", \ | |
373 | "PREGS_CLOBBERED", \ | |
374 | "PREGS", \ | |
375 | "DPREGS", \ | |
376 | "MOST_REGS", \ | |
377 | "PROLOGUE_REGS", \ | |
378 | "NON_A_CC_REGS", \ | |
379 | "ALL_REGS" } | |
380 | ||
381 | /* An initializer containing the contents of the register classes, as integers | |
382 | which are bit masks. The Nth integer specifies the contents of class N. | |
383 | The way the integer MASK is interpreted is that register R is in the class | |
384 | if `MASK & (1 << R)' is 1. | |
385 | ||
386 | When the machine has more than 32 registers, an integer does not suffice. | |
387 | Then the integers are replaced by sub-initializers, braced groupings | |
388 | containing several integers. Each sub-initializer must be suitable as an | |
389 | initializer for the type `HARD_REG_SET' which is defined in | |
390 | `hard-reg-set.h'. */ | |
391 | ||
392 | /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use | |
393 | MOST_REGS as the union of DPREGS and DAGREGS. */ | |
394 | ||
395 | #define REG_CLASS_CONTENTS \ | |
396 | /* 31 - 0 63-32 */ \ | |
397 | { { 0x00000000, 0 }, /* NO_REGS */ \ | |
398 | { 0x02490000, 0 }, /* IREGS */ \ | |
399 | { 0x04920000, 0 }, /* BREGS */ \ | |
400 | { 0x09240000, 0 }, /* LREGS */ \ | |
401 | { 0xf0000000, 0 }, /* MREGS */ \ | |
402 | { 0x0fff0000, 0 }, /* CIRCREGS */ \ | |
403 | { 0xffff0000, 0 }, /* DAGREGS */ \ | |
404 | { 0x00000000, 0x1 }, /* EVEN_AREGS */ \ | |
405 | { 0x00000000, 0x2 }, /* ODD_AREGS */ \ | |
406 | { 0x00000000, 0x3 }, /* AREGS */ \ | |
407 | { 0x00000000, 0x4 }, /* CCREGS */ \ | |
408 | { 0x00000055, 0 }, /* EVEN_DREGS */ \ | |
409 | { 0x000000aa, 0 }, /* ODD_DREGS */ \ | |
410 | { 0x000000ff, 0 }, /* DREGS */ \ | |
411 | { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \ | |
412 | { 0x0000ff00, 0x800 }, /* PREGS */ \ | |
413 | { 0x0000ffff, 0x800 }, /* DPREGS */ \ | |
414 | { 0xffffffff, 0x800 }, /* MOST_REGS */\ | |
415 | { 0x00000000, 0x7f8 }, /* PROLOGUE_REGS */\ | |
416 | { 0xffffffff, 0xff8 }, /* NON_A_CC_REGS */\ | |
417 | { 0xffffffff, 0xfff }} /* ALL_REGS */ | |
418 | ||
419 | #define BASE_REG_CLASS PREGS | |
420 | #define INDEX_REG_CLASS PREGS | |
421 | ||
422 | #define REGNO_OK_FOR_BASE_STRICT_P(X) (REGNO_REG_CLASS (X) == BASE_REG_CLASS) | |
423 | #define REGNO_OK_FOR_BASE_NONSTRICT_P(X) \ | |
424 | (((X) >= FIRST_PSEUDO_REGISTER) || REGNO_REG_CLASS (X) == BASE_REG_CLASS) | |
425 | ||
426 | #ifdef REG_OK_STRICT | |
427 | #define REGNO_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_STRICT_P (X) | |
428 | #else | |
429 | #define REGNO_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_NONSTRICT_P (X) | |
430 | #endif | |
431 | ||
432 | #define REG_OK_FOR_BASE_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X))) | |
433 | #define REG_OK_FOR_INDEX_P(X) 0 | |
434 | #define REGNO_OK_FOR_INDEX_P(X) 0 | |
435 | ||
436 | /* Get reg_class from a letter such as appears in the machine description. */ | |
437 | ||
438 | #define REG_CLASS_FROM_LETTER(LETTER) \ | |
439 | ((LETTER) == 'a' ? PREGS : \ | |
440 | (LETTER) == 'd' ? DREGS : \ | |
441 | (LETTER) == 'z' ? PREGS_CLOBBERED : \ | |
442 | (LETTER) == 'D' ? EVEN_DREGS : \ | |
443 | (LETTER) == 'W' ? ODD_DREGS : \ | |
444 | (LETTER) == 'e' ? AREGS : \ | |
445 | (LETTER) == 'A' ? EVEN_AREGS : \ | |
446 | (LETTER) == 'B' ? ODD_AREGS : \ | |
447 | (LETTER) == 'b' ? IREGS : \ | |
448 | (LETTER) == 'B' ? BREGS : \ | |
449 | (LETTER) == 'f' ? MREGS : \ | |
450 | (LETTER) == 'c' ? CIRCREGS : \ | |
451 | (LETTER) == 'C' ? CCREGS : \ | |
452 | (LETTER) == 'x' ? MOST_REGS : \ | |
453 | (LETTER) == 'y' ? PROLOGUE_REGS : \ | |
454 | (LETTER) == 'w' ? NON_A_CC_REGS : \ | |
455 | NO_REGS) | |
456 | ||
457 | /* The same information, inverted: | |
458 | Return the class number of the smallest class containing | |
459 | reg number REGNO. This could be a conditional expression | |
460 | or could index an array. */ | |
461 | ||
462 | #define REGNO_REG_CLASS(REGNO) \ | |
463 | ((REGNO) < REG_P0 ? DREGS \ | |
464 | : (REGNO) < REG_I0 ? PREGS \ | |
465 | : (REGNO) == REG_ARGP ? BASE_REG_CLASS \ | |
466 | : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \ | |
467 | : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \ | |
468 | : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \ | |
469 | : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \ | |
470 | : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \ | |
471 | : (REGNO) == REG_CC ? CCREGS \ | |
472 | : (REGNO) >= REG_RETS ? PROLOGUE_REGS \ | |
473 | : NO_REGS) | |
474 | ||
475 | /* When defined, the compiler allows registers explicitly used in the | |
476 | rtl to be used as spill registers but prevents the compiler from | |
477 | extending the lifetime of these registers. */ | |
478 | #define SMALL_REGISTER_CLASSES 1 | |
479 | ||
480 | #define CLASS_LIKELY_SPILLED_P(CLASS) \ | |
481 | ((CLASS) == PREGS_CLOBBERED \ | |
482 | || (CLASS) == PROLOGUE_REGS \ | |
483 | || (CLASS) == CCREGS) | |
484 | ||
485 | /* Do not allow to store a value in REG_CC for any mode */ | |
486 | /* Do not allow to store value in pregs if mode is not SI*/ | |
487 | #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE)) | |
488 | ||
489 | /* Return the maximum number of consecutive registers | |
490 | needed to represent mode MODE in a register of class CLASS. */ | |
491 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
492 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
493 | ||
494 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
495 | ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) \ | |
496 | ? 1 : CLASS_MAX_NREGS (GENERAL_REGS, MODE)) | |
497 | ||
498 | /* A C expression that is nonzero if hard register TO can be | |
499 | considered for use as a rename register for FROM register */ | |
500 | #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO) | |
501 | ||
502 | /* A C expression that is nonzero if it is desirable to choose | |
503 | register allocation so as to avoid move instructions between a | |
504 | value of mode MODE1 and a value of mode MODE2. | |
505 | ||
506 | If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, | |
507 | MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1, | |
508 | MODE2)' must be zero. */ | |
509 | #define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) == (MODE2)) | |
510 | ||
511 | /* `PREFERRED_RELOAD_CLASS (X, CLASS)' | |
512 | A C expression that places additional restrictions on the register | |
513 | class to use when it is necessary to copy value X into a register | |
514 | in class CLASS. The value is a register class; perhaps CLASS, or | |
515 | perhaps another, smaller class. */ | |
516 | #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS) | |
517 | ||
518 | #define SECONDARY_OUTPUT_RELOAD_CLASS(class,mode,x) \ | |
519 | secondary_output_reload_class(class,mode,x) | |
520 | #define SECONDARY_INPUT_RELOAD_CLASS(class,mode,x) \ | |
521 | secondary_input_reload_class(class,mode,x) | |
522 | ||
523 | /* Function Calling Conventions. */ | |
524 | ||
525 | /* The type of the current function; normal functions are of type | |
526 | SUBROUTINE. */ | |
527 | typedef enum { | |
528 | SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER | |
529 | } e_funkind; | |
530 | ||
531 | #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 } | |
532 | ||
6d459e2b BS |
533 | /* Flags for the call/call_value rtl operations set up by function_arg */ |
534 | #define CALL_NORMAL 0x00000000 /* no special processing */ | |
535 | #define CALL_LONG 0x00000001 /* always call indirect */ | |
536 | #define CALL_SHORT 0x00000002 /* always call by symbol */ | |
537 | ||
0d4a78eb BS |
538 | typedef struct { |
539 | int words; /* # words passed so far */ | |
540 | int nregs; /* # registers available for passing */ | |
541 | int *arg_regs; /* array of register -1 terminated */ | |
6d459e2b | 542 | int call_cookie; /* Do special things for this call */ |
0d4a78eb BS |
543 | } CUMULATIVE_ARGS; |
544 | ||
545 | /* Define where to put the arguments to a function. | |
546 | Value is zero to push the argument on the stack, | |
547 | or a hard register in which to store the argument. | |
548 | ||
549 | MODE is the argument's machine mode. | |
550 | TYPE is the data type of the argument (as a tree). | |
551 | This is null for libcalls where that information may | |
552 | not be available. | |
553 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
554 | the preceding args and about the function being called. | |
555 | NAMED is nonzero if this argument is a named parameter | |
556 | (otherwise it is an extra parameter matching an ellipsis). */ | |
557 | ||
558 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
559 | (function_arg (&CUM, MODE, TYPE, NAMED)) | |
560 | ||
561 | #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO) | |
562 | ||
563 | ||
564 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
565 | for a call to a function whose data type is FNTYPE. | |
566 | For a library call, FNTYPE is 0. */ | |
567 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \ | |
568 | (init_cumulative_args (&CUM, FNTYPE, LIBNAME)) | |
569 | ||
570 | /* Update the data in CUM to advance over an argument | |
571 | of mode MODE and data type TYPE. | |
572 | (TYPE is null for libcalls where that information may not be available.) */ | |
573 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
574 | (function_arg_advance (&CUM, MODE, TYPE, NAMED)) | |
575 | ||
576 | #define RETURN_POPS_ARGS(FDECL, FUNTYPE, STKSIZE) 0 | |
577 | ||
578 | /* Define how to find the value returned by a function. | |
579 | VALTYPE is the data type of the value (as a tree). | |
580 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
581 | otherwise, FUNC is 0. | |
582 | */ | |
583 | ||
584 | #define VALUE_REGNO(MODE) (REG_R0) | |
585 | ||
586 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
587 | gen_rtx_REG (TYPE_MODE (VALTYPE), \ | |
588 | VALUE_REGNO(TYPE_MODE(VALTYPE))) | |
589 | ||
590 | /* Define how to find the value returned by a library function | |
591 | assuming the value has mode MODE. */ | |
592 | ||
593 | #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE)) | |
594 | ||
595 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0) | |
596 | ||
597 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
598 | #define RETURN_IN_MEMORY(TYPE) bfin_return_in_memory(TYPE) | |
599 | ||
600 | /* Before the prologue, the return address is in the RETS register. */ | |
601 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS) | |
602 | ||
603 | #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT) | |
604 | ||
605 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS) | |
606 | ||
607 | /* Call instructions don't modify the stack pointer on the Blackfin. */ | |
608 | #define INCOMING_FRAME_SP_OFFSET 0 | |
609 | ||
610 | /* Describe how we implement __builtin_eh_return. */ | |
611 | #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) | |
612 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2) | |
613 | #define EH_RETURN_HANDLER_RTX \ | |
614 | gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD)) | |
615 | ||
616 | /* Addressing Modes */ | |
617 | ||
618 | /* Recognize any constant value that is a valid address. */ | |
619 | #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X)) | |
620 | ||
621 | /* Nonzero if the constant value X is a legitimate general operand. | |
622 | symbol_ref are not legitimate and will be put into constant pool. | |
623 | See force_const_mem(). | |
624 | If -mno-pool, all constants are legitimate. | |
625 | */ | |
626 | #define LEGITIMATE_CONSTANT_P(x) 1 | |
627 | ||
628 | /* A number, the maximum number of registers that can appear in a | |
629 | valid memory address. Note that it is up to you to specify a | |
630 | value equal to the maximum number that `GO_IF_LEGITIMATE_ADDRESS' | |
631 | would ever accept. */ | |
632 | #define MAX_REGS_PER_ADDRESS 1 | |
633 | ||
634 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
635 | that is a valid memory address for an instruction. | |
636 | The MODE argument is the machine mode for the MEM expression | |
637 | that wants to use this address. | |
638 | ||
639 | Blackfin addressing modes are as follows: | |
640 | ||
641 | [preg] | |
642 | [preg + imm16] | |
643 | ||
644 | B [ Preg + uimm15 ] | |
645 | W [ Preg + uimm16m2 ] | |
646 | [ Preg + uimm17m4 ] | |
647 | ||
648 | [preg++] | |
649 | [preg--] | |
650 | [--sp] | |
651 | */ | |
652 | ||
653 | #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \ | |
654 | (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode) | |
655 | ||
656 | #ifdef REG_OK_STRICT | |
657 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ | |
658 | do { \ | |
659 | if (bfin_legitimate_address_p (MODE, X, 1)) \ | |
660 | goto WIN; \ | |
661 | } while (0); | |
662 | #else | |
663 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ | |
664 | do { \ | |
665 | if (bfin_legitimate_address_p (MODE, X, 0)) \ | |
666 | goto WIN; \ | |
667 | } while (0); | |
668 | #endif | |
669 | ||
670 | /* Try machine-dependent ways of modifying an illegitimate address | |
671 | to be legitimate. If we find one, return the new, valid address. | |
672 | This macro is used in only one place: `memory_address' in explow.c. | |
673 | ||
674 | OLDX is the address as it was before break_out_memory_refs was called. | |
675 | In some cases it is useful to look at this to decide what needs to be done. | |
676 | ||
677 | MODE and WIN are passed so that this macro can use | |
678 | GO_IF_LEGITIMATE_ADDRESS. | |
679 | ||
680 | It is always safe for this macro to do nothing. It exists to recognize | |
681 | opportunities to optimize the output. | |
682 | */ | |
683 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
684 | do { \ | |
685 | rtx _q = legitimize_address(X, OLDX, MODE); \ | |
686 | if (_q) { X = _q; goto WIN; } \ | |
687 | } while (0) | |
688 | ||
689 | #define HAVE_POST_INCREMENT 1 | |
690 | #define HAVE_POST_DECREMENT 1 | |
691 | #define HAVE_PRE_DECREMENT 1 | |
692 | ||
693 | /* `LEGITIMATE_PIC_OPERAND_P (X)' | |
694 | A C expression that is nonzero if X is a legitimate immediate | |
695 | operand on the target machine when generating position independent | |
696 | code. You can assume that X satisfies `CONSTANT_P', so you need | |
697 | not check this. You can also assume FLAG_PIC is true, so you need | |
698 | not check it either. You need not define this macro if all | |
699 | constants (including `SYMBOL_REF') can be immediate operands when | |
700 | generating position independent code. */ | |
701 | #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X) | |
702 | ||
703 | #define SYMBOLIC_CONST(X) \ | |
704 | (GET_CODE (X) == SYMBOL_REF \ | |
705 | || GET_CODE (X) == LABEL_REF \ | |
706 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
707 | ||
708 | /* | |
709 | A C statement or compound statement with a conditional `goto | |
710 | LABEL;' executed if memory address X (an RTX) can have different | |
711 | meanings depending on the machine mode of the memory reference it | |
712 | is used for or if the address is valid for some modes but not | |
713 | others. | |
714 | ||
715 | Autoincrement and autodecrement addresses typically have | |
716 | mode-dependent effects because the amount of the increment or | |
717 | decrement is the size of the operand being addressed. Some | |
718 | machines have other mode-dependent addresses. Many RISC machines | |
719 | have no mode-dependent addresses. | |
720 | ||
721 | You may assume that ADDR is a valid address for the machine. | |
722 | */ | |
723 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
724 | do { \ | |
725 | if (GET_CODE (ADDR) == POST_INC \ | |
726 | || GET_CODE (ADDR) == POST_DEC \ | |
727 | || GET_CODE (ADDR) == PRE_DEC) \ | |
728 | goto LABEL; \ | |
729 | } while (0) | |
730 | ||
731 | #define NOTICE_UPDATE_CC(EXPR, INSN) 0 | |
732 | ||
733 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
734 | is done just by pretending it is already truncated. */ | |
735 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
736 | ||
737 | /* Max number of bytes we can move from memory to memory | |
738 | in one reasonably fast instruction. */ | |
739 | #define MOVE_MAX UNITS_PER_WORD | |
740 | ||
741 | ||
742 | /* STORAGE LAYOUT: target machine storage layout | |
743 | Define this macro as a C expression which is nonzero if accessing | |
744 | less than a word of memory (i.e. a `char' or a `short') is no | |
745 | faster than accessing a word of memory, i.e., if such access | |
746 | require more than one instruction or if there is no difference in | |
747 | cost between byte and (aligned) word loads. | |
748 | ||
749 | When this macro is not defined, the compiler will access a field by | |
750 | finding the smallest containing object; when it is defined, a | |
751 | fullword load will be used if alignment permits. Unless bytes | |
752 | accesses are faster than word accesses, using word accesses is | |
753 | preferable since it may eliminate subsequent memory access if | |
754 | subsequent accesses occur to other fields in the same word of the | |
755 | structure, but to different bytes. */ | |
756 | #define SLOW_BYTE_ACCESS 0 | |
757 | #define SLOW_SHORT_ACCESS 0 | |
758 | ||
759 | /* Define this if most significant bit is lowest numbered | |
760 | in instructions that operate on numbered bit-fields. */ | |
761 | #define BITS_BIG_ENDIAN 0 | |
762 | ||
763 | /* Define this if most significant byte of a word is the lowest numbered. | |
764 | We can't access bytes but if we could we would in the Big Endian order. */ | |
765 | #define BYTES_BIG_ENDIAN 0 | |
766 | ||
767 | /* Define this if most significant word of a multiword number is numbered. */ | |
768 | #define WORDS_BIG_ENDIAN 0 | |
769 | ||
770 | /* number of bits in an addressable storage unit */ | |
771 | #define BITS_PER_UNIT 8 | |
772 | ||
773 | /* Width in bits of a "word", which is the contents of a machine register. | |
774 | Note that this is not necessarily the width of data type `int'; | |
775 | if using 16-bit ints on a 68000, this would still be 32. | |
776 | But on a machine with 16-bit registers, this would be 16. */ | |
777 | #define BITS_PER_WORD 32 | |
778 | ||
779 | /* Width of a word, in units (bytes). */ | |
780 | #define UNITS_PER_WORD 4 | |
781 | ||
0d4a78eb BS |
782 | /* Width in bits of a pointer. |
783 | See also the macro `Pmode1' defined below. */ | |
784 | #define POINTER_SIZE 32 | |
785 | ||
786 | /* Allocation boundary (in *bits*) for storing pointers in memory. */ | |
787 | #define POINTER_BOUNDARY 32 | |
788 | ||
789 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
790 | #define PARM_BOUNDARY 32 | |
791 | ||
792 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
793 | #define STACK_BOUNDARY 32 | |
794 | ||
795 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
796 | #define FUNCTION_BOUNDARY 32 | |
797 | ||
798 | /* Alignment of field after `int : 0' in a structure. */ | |
799 | #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD | |
800 | ||
801 | /* No data type wants to be aligned rounder than this. */ | |
802 | #define BIGGEST_ALIGNMENT 32 | |
803 | ||
804 | /* Define this if move instructions will actually fail to work | |
805 | when given unaligned data. */ | |
806 | #define STRICT_ALIGNMENT 1 | |
807 | ||
808 | /* (shell-command "rm c-decl.o stor-layout.o") | |
809 | * never define PCC_BITFIELD_TYPE_MATTERS | |
810 | * really cause some alignment problem | |
811 | */ | |
812 | ||
813 | #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \ | |
814 | BITS_PER_UNIT) | |
815 | ||
816 | #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \ | |
817 | BITS_PER_UNIT) | |
818 | ||
819 | ||
820 | /* what is the 'type' of size_t */ | |
821 | #define SIZE_TYPE "long unsigned int" | |
822 | ||
823 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
824 | #define DEFAULT_SIGNED_CHAR 1 | |
825 | #define FLOAT_TYPE_SIZE BITS_PER_WORD | |
826 | #define SHORT_TYPE_SIZE 16 | |
827 | #define CHAR_TYPE_SIZE 8 | |
828 | #define INT_TYPE_SIZE 32 | |
829 | #define LONG_TYPE_SIZE 32 | |
830 | #define LONG_LONG_TYPE_SIZE 64 | |
831 | ||
832 | /* Note: Fix this to depend on target switch. -- lev */ | |
833 | ||
834 | /* Note: Try to implement double and force long double. -- tonyko | |
835 | * #define __DOUBLES_ARE_FLOATS__ | |
836 | * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE | |
837 | * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE | |
838 | * #define DOUBLES_ARE_FLOATS 1 | |
839 | */ | |
840 | ||
841 | #define DOUBLE_TYPE_SIZE 64 | |
842 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
843 | ||
844 | /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)' | |
845 | A macro to update M and UNSIGNEDP when an object whose type is | |
846 | TYPE and which has the specified mode and signedness is to be | |
847 | stored in a register. This macro is only called when TYPE is a | |
848 | scalar type. | |
849 | ||
850 | On most RISC machines, which only have operations that operate on | |
851 | a full register, define this macro to set M to `word_mode' if M is | |
852 | an integer mode narrower than `BITS_PER_WORD'. In most cases, | |
853 | only integer modes should be widened because wider-precision | |
854 | floating-point operations are usually more expensive than their | |
855 | narrower counterparts. | |
856 | ||
857 | For most machines, the macro definition does not change UNSIGNEDP. | |
858 | However, some machines, have instructions that preferentially | |
859 | handle either signed or unsigned quantities of certain modes. For | |
860 | example, on the DEC Alpha, 32-bit loads from memory and 32-bit add | |
861 | instructions sign-extend the result to 64 bits. On such machines, | |
862 | set UNSIGNEDP according to which kind of extension is more | |
863 | efficient. | |
864 | ||
865 | Do not define this macro if it would never modify M.*/ | |
866 | ||
867 | #define BFIN_PROMOTE_MODE_P(MODE) \ | |
868 | (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \ | |
869 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) | |
870 | ||
871 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
872 | if (BFIN_PROMOTE_MODE_P(MODE)) \ | |
873 | { \ | |
874 | if (MODE == QImode) \ | |
875 | UNSIGNEDP = 1; \ | |
876 | else if (MODE == HImode) \ | |
877 | UNSIGNEDP = 0; \ | |
878 | (MODE) = SImode; \ | |
879 | } | |
880 | ||
881 | /* Describing Relative Costs of Operations */ | |
882 | ||
883 | /* Do not put function addr into constant pool */ | |
884 | #define NO_FUNCTION_CSE 1 | |
885 | ||
886 | /* A C expression for the cost of moving data from a register in class FROM to | |
887 | one in class TO. The classes are expressed using the enumeration values | |
888 | such as `GENERAL_REGS'. A value of 2 is the default; other values are | |
889 | interpreted relative to that. | |
890 | ||
891 | It is not required that the cost always equal 2 when FROM is the same as TO; | |
892 | on some machines it is expensive to move between registers if they are not | |
893 | general registers. */ | |
894 | ||
895 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ | |
896 | bfin_register_move_cost ((MODE), (CLASS1), (CLASS2)) | |
897 | ||
898 | /* A C expression for the cost of moving data of mode M between a | |
899 | register and memory. A value of 2 is the default; this cost is | |
900 | relative to those in `REGISTER_MOVE_COST'. | |
901 | ||
902 | If moving between registers and memory is more expensive than | |
903 | between two registers, you should define this macro to express the | |
904 | relative cost. */ | |
905 | ||
906 | #define MEMORY_MOVE_COST(MODE, CLASS, IN) \ | |
907 | bfin_memory_move_cost ((MODE), (CLASS), (IN)) | |
908 | ||
909 | /* Specify the machine mode that this machine uses | |
910 | for the index in the tablejump instruction. */ | |
911 | #define CASE_VECTOR_MODE SImode | |
912 | ||
913 | #define JUMP_TABLES_IN_TEXT_SECTION flag_pic | |
914 | ||
915 | /* Define if operations between registers always perform the operation | |
916 | on the full register even if a narrower mode is specified. | |
917 | #define WORD_REGISTER_OPERATIONS | |
918 | */ | |
919 | ||
920 | #define CONST_18UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 262140) | |
921 | #define CONST_16BIT_IMM_P(VALUE) ((VALUE) >= -32768 && (VALUE) <= 32767) | |
922 | #define CONST_16UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 65535) | |
923 | #define CONST_7BIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 63) | |
924 | #define CONST_7NBIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 0) | |
925 | #define CONST_5UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 31) | |
926 | #define CONST_4BIT_IMM_P(VALUE) ((VALUE) >= -8 && (VALUE) <= 7) | |
927 | #define CONST_4UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 15) | |
928 | #define CONST_3BIT_IMM_P(VALUE) ((VALUE) >= -4 && (VALUE) <= 3) | |
929 | #define CONST_3UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 7) | |
930 | ||
931 | #define CONSTRAINT_LEN(C, STR) \ | |
932 | ((C) == 'P' || (C) == 'M' || (C) == 'N' ? 2 \ | |
933 | : (C) == 'K' ? 3 \ | |
934 | : DEFAULT_CONSTRAINT_LEN ((C), (STR))) | |
935 | ||
936 | #define CONST_OK_FOR_P(VALUE, STR) \ | |
937 | ((STR)[1] == '0' ? (VALUE) == 0 \ | |
938 | : (STR)[1] == '1' ? (VALUE) == 1 \ | |
939 | : (STR)[1] == '2' ? (VALUE) == 2 \ | |
940 | : (STR)[1] == '3' ? (VALUE) == 3 \ | |
941 | : (STR)[1] == '4' ? (VALUE) == 4 \ | |
942 | : 0) | |
943 | ||
944 | #define CONST_OK_FOR_K(VALUE, STR) \ | |
945 | ((STR)[1] == 'u' \ | |
946 | ? ((STR)[2] == '3' ? CONST_3UBIT_IMM_P (VALUE) \ | |
947 | : (STR)[2] == '4' ? CONST_4UBIT_IMM_P (VALUE) \ | |
948 | : (STR)[2] == '5' ? CONST_5UBIT_IMM_P (VALUE) \ | |
949 | : (STR)[2] == 'h' ? CONST_16UBIT_IMM_P (VALUE) \ | |
950 | : 0) \ | |
951 | : (STR)[1] == 's' \ | |
952 | ? ((STR)[2] == '3' ? CONST_3BIT_IMM_P (VALUE) \ | |
953 | : (STR)[2] == '4' ? CONST_4BIT_IMM_P (VALUE) \ | |
954 | : (STR)[2] == '7' ? CONST_7BIT_IMM_P (VALUE) \ | |
955 | : (STR)[2] == 'h' ? CONST_16BIT_IMM_P (VALUE) \ | |
956 | : 0) \ | |
957 | : (STR)[1] == 'n' \ | |
958 | ? ((STR)[2] == '7' ? CONST_7NBIT_IMM_P (VALUE) \ | |
959 | : 0) \ | |
960 | : 0) | |
961 | ||
962 | #define CONST_OK_FOR_M(VALUE, STR) \ | |
963 | ((STR)[1] == '1' ? (VALUE) == 255 \ | |
964 | : (STR)[1] == '2' ? (VALUE) == 65535 \ | |
965 | : 0) | |
966 | ||
967 | /* The letters I, J, K, L and M in a register constraint string | |
968 | can be used to stand for particular ranges of immediate operands. | |
969 | This macro defines what the ranges are. | |
970 | C is the letter, and VALUE is a constant value. | |
971 | Return 1 if VALUE is in the range specified by C. | |
972 | ||
973 | bfin constant operands are as follows | |
974 | ||
975 | J 2**N 5bit imm scaled | |
976 | Ks7 -64 .. 63 signed 7bit imm | |
977 | Ku5 0..31 unsigned 5bit imm | |
978 | Ks4 -8 .. 7 signed 4bit imm | |
979 | Ks3 -4 .. 3 signed 3bit imm | |
980 | Ku3 0 .. 7 unsigned 3bit imm | |
981 | Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n | |
982 | */ | |
983 | #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \ | |
984 | ((C) == 'J' ? (log2constp (VALUE)) \ | |
985 | : (C) == 'K' ? CONST_OK_FOR_K (VALUE, STR) \ | |
986 | : (C) == 'L' ? log2constp (~(VALUE)) \ | |
987 | : (C) == 'M' ? CONST_OK_FOR_M (VALUE, STR) \ | |
988 | : (C) == 'P' ? CONST_OK_FOR_P (VALUE, STR) \ | |
989 | : 0) | |
990 | ||
991 | /*Constant Output Formats */ | |
992 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
993 | ((C) == 'H' ? 1 : 0) | |
994 | ||
995 | #define EXTRA_CONSTRAINT(VALUE, D) \ | |
996 | ((D) == 'Q' ? GET_CODE (VALUE) == SYMBOL_REF : 0) | |
997 | ||
0d4a78eb BS |
998 | /* Switch into a generic section. */ |
999 | #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section | |
1000 | ||
1001 | #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE) | |
1002 | #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX) | |
1003 | ||
1004 | typedef enum sections { | |
1005 | CODE_DIR, | |
1006 | DATA_DIR, | |
1007 | LAST_SECT_NM | |
1008 | } SECT_ENUM_T; | |
1009 | ||
1010 | typedef enum directives { | |
1011 | LONG_CONST_DIR, | |
1012 | SHORT_CONST_DIR, | |
1013 | BYTE_CONST_DIR, | |
1014 | SPACE_DIR, | |
1015 | INIT_DIR, | |
1016 | LAST_DIR_NM | |
1017 | } DIR_ENUM_T; | |
1018 | ||
1019 | #define TEXT_SECTION_ASM_OP ".text;" | |
1020 | #define DATA_SECTION_ASM_OP ".data;" | |
1021 | ||
1022 | #define ASM_APP_ON "" | |
1023 | #define ASM_APP_OFF "" | |
1024 | ||
1025 | #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \ | |
1026 | do { fputs (".global ", FILE); \ | |
1027 | assemble_name (FILE, NAME); \ | |
1028 | fputc (';',FILE); \ | |
1029 | fputc ('\n',FILE); \ | |
1030 | } while (0) | |
1031 | ||
1032 | #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ | |
1033 | do { \ | |
1034 | fputs (".type ", FILE); \ | |
1035 | assemble_name (FILE, NAME); \ | |
1036 | fputs (", STT_FUNC", FILE); \ | |
1037 | fputc (';',FILE); \ | |
1038 | fputc ('\n',FILE); \ | |
1039 | ASM_OUTPUT_LABEL(FILE, NAME); \ | |
1040 | } while (0) | |
1041 | ||
1042 | #define ASM_OUTPUT_LABEL(FILE, NAME) \ | |
1043 | do { assemble_name (FILE, NAME); \ | |
1044 | fputs (":\n",FILE); \ | |
1045 | } while (0) | |
1046 | ||
1047 | #define ASM_OUTPUT_LABELREF(FILE,NAME) \ | |
1048 | do { fprintf (FILE, "_%s", NAME); \ | |
1049 | } while (0) | |
1050 | ||
1051 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
1052 | do { \ | |
1053 | int len = strlen (NAME); \ | |
1054 | char *temp = (char *) alloca (len + 4); \ | |
1055 | temp[0] = 'L'; \ | |
1056 | temp[1] = '_'; \ | |
1057 | strcpy (&temp[2], (NAME)); \ | |
1058 | temp[len + 2] = '_'; \ | |
1059 | temp[len + 3] = 0; \ | |
1060 | (OUTPUT) = (char *) alloca (strlen (NAME) + 13); \ | |
1061 | sprintf (OUTPUT, "_%s$%d", temp, LABELNO); \ | |
1062 | } while (0) | |
1063 | ||
1064 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
1065 | do { char __buf[256]; \ | |
1066 | fprintf (FILE, "\t.dd\t"); \ | |
1067 | ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ | |
1068 | assemble_name (FILE, __buf); \ | |
1069 | fputc (';', FILE); \ | |
1070 | fputc ('\n', FILE); \ | |
1071 | } while (0) | |
1072 | ||
1073 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
1074 | MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) | |
1075 | ||
1076 | #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ | |
1077 | do { \ | |
1078 | char __buf[256]; \ | |
1079 | fprintf (FILE, "\t.dd\t"); \ | |
1080 | ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ | |
1081 | assemble_name (FILE, __buf); \ | |
1082 | fputs (" - ", FILE); \ | |
1083 | ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \ | |
1084 | assemble_name (FILE, __buf); \ | |
1085 | fputc (';', FILE); \ | |
1086 | fputc ('\n', FILE); \ | |
1087 | } while (0) | |
1088 | ||
1089 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
21956c07 BS |
1090 | do { \ |
1091 | if ((LOG) != 0) \ | |
1092 | fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \ | |
0d4a78eb BS |
1093 | } while (0) |
1094 | ||
1095 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
1096 | do { \ | |
1097 | asm_output_skip (FILE, SIZE); \ | |
1098 | } while (0) | |
1099 | ||
1100 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ | |
1101 | do { \ | |
1102 | data_section(); \ | |
1103 | if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \ | |
1104 | ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \ | |
1105 | ASM_OUTPUT_LABEL (FILE, NAME); \ | |
1106 | fprintf (FILE, "%s %ld;\n", ASM_SPACE, \ | |
1107 | (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \ | |
1108 | } while (0) | |
1109 | ||
1110 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
1111 | do { \ | |
1112 | ASM_GLOBALIZE_LABEL1(FILE,NAME); \ | |
1113 | ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0) | |
1114 | ||
1115 | #define ASM_COMMENT_START "//" | |
1116 | ||
1117 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
1118 | do {\ | |
1119 | fprintf (FILE, "\tP1.l =LP$%d; P1.h =LP$%d; call mcount;\n", \ | |
1120 | LABELNO, LABELNO);\ | |
1121 | } while(0) | |
1122 | ||
1123 | #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO]) | |
1124 | #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO]) | |
1125 | ||
1126 | extern struct rtx_def *bfin_compare_op0, *bfin_compare_op1; | |
1127 | extern struct rtx_def *bfin_cc_rtx, *bfin_rets_rtx; | |
1128 | ||
1129 | /* This works for GAS and some other assemblers. */ | |
1130 | #define SET_ASM_OP ".set " | |
1131 | ||
1132 | /* Don't know how to order these. UNALIGNED_WORD_ASM_OP is in | |
1133 | dwarf2.out. */ | |
1134 | #define UNALIGNED_WORD_ASM_OP ".4byte" | |
1135 | ||
1136 | /* DBX register number for a given compiler register number */ | |
1137 | #define DBX_REGISTER_NUMBER(REGNO) (REGNO) | |
1138 | ||
1139 | #define SIZE_ASM_OP "\t.size\t" | |
1140 | ||
1141 | #endif /* _BFIN_CONFIG */ |