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0d4a78eb | 1 | /* Definitions for the Blackfin port. |
85ec4feb | 2 | Copyright (C) 2005-2018 Free Software Foundation, Inc. |
0d4a78eb BS |
3 | Contributed by Analog Devices. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it | |
8 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | by the Free Software Foundation; either version 3, or (at your |
0d4a78eb BS |
10 | option) any later version. |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
0d4a78eb BS |
20 | |
21 | #ifndef _BFIN_CONFIG | |
22 | #define _BFIN_CONFIG | |
23 | ||
bbd399cf JM |
24 | #ifndef BFIN_OPTS_H |
25 | #include "config/bfin/bfin-opts.h" | |
26 | #endif | |
27 | ||
0d4a78eb BS |
28 | #define OBJECT_FORMAT_ELF |
29 | ||
30 | #define BRT 1 | |
31 | #define BRF 0 | |
32 | ||
0d4a78eb BS |
33 | /* Predefinition in the preprocessor for this target machine */ |
34 | #ifndef TARGET_CPU_CPP_BUILTINS | |
ea2382be JZ |
35 | #define TARGET_CPU_CPP_BUILTINS() \ |
36 | do \ | |
37 | { \ | |
38 | builtin_define_std ("bfin"); \ | |
39 | builtin_define_std ("BFIN"); \ | |
42da70b7 | 40 | builtin_define ("__ADSPBLACKFIN__"); \ |
9d3f9aa3 BS |
41 | builtin_define ("__ADSPLPBLACKFIN__"); \ |
42 | \ | |
43 | switch (bfin_cpu_type) \ | |
44 | { \ | |
0828c47b BRF |
45 | case BFIN_CPU_UNKNOWN: \ |
46 | break; \ | |
318b3009 BS |
47 | case BFIN_CPU_BF512: \ |
48 | builtin_define ("__ADSPBF512__"); \ | |
49 | builtin_define ("__ADSPBF51x__"); \ | |
50 | break; \ | |
51 | case BFIN_CPU_BF514: \ | |
52 | builtin_define ("__ADSPBF514__"); \ | |
53 | builtin_define ("__ADSPBF51x__"); \ | |
54 | break; \ | |
55 | case BFIN_CPU_BF516: \ | |
56 | builtin_define ("__ADSPBF516__"); \ | |
57 | builtin_define ("__ADSPBF51x__"); \ | |
58 | break; \ | |
59 | case BFIN_CPU_BF518: \ | |
60 | builtin_define ("__ADSPBF518__"); \ | |
61 | builtin_define ("__ADSPBF51x__"); \ | |
62 | break; \ | |
ea2382be JZ |
63 | case BFIN_CPU_BF522: \ |
64 | builtin_define ("__ADSPBF522__"); \ | |
65 | builtin_define ("__ADSPBF52x__"); \ | |
66 | break; \ | |
64882649 BS |
67 | case BFIN_CPU_BF523: \ |
68 | builtin_define ("__ADSPBF523__"); \ | |
69 | builtin_define ("__ADSPBF52x__"); \ | |
70 | break; \ | |
71 | case BFIN_CPU_BF524: \ | |
72 | builtin_define ("__ADSPBF524__"); \ | |
73 | builtin_define ("__ADSPBF52x__"); \ | |
74 | break; \ | |
ea2382be JZ |
75 | case BFIN_CPU_BF525: \ |
76 | builtin_define ("__ADSPBF525__"); \ | |
77 | builtin_define ("__ADSPBF52x__"); \ | |
78 | break; \ | |
64882649 BS |
79 | case BFIN_CPU_BF526: \ |
80 | builtin_define ("__ADSPBF526__"); \ | |
81 | builtin_define ("__ADSPBF52x__"); \ | |
82 | break; \ | |
ea2382be JZ |
83 | case BFIN_CPU_BF527: \ |
84 | builtin_define ("__ADSPBF527__"); \ | |
85 | builtin_define ("__ADSPBF52x__"); \ | |
86 | break; \ | |
9d3f9aa3 BS |
87 | case BFIN_CPU_BF531: \ |
88 | builtin_define ("__ADSPBF531__"); \ | |
89 | break; \ | |
90 | case BFIN_CPU_BF532: \ | |
91 | builtin_define ("__ADSPBF532__"); \ | |
92 | break; \ | |
93 | case BFIN_CPU_BF533: \ | |
94 | builtin_define ("__ADSPBF533__"); \ | |
95 | break; \ | |
28f601ff JZ |
96 | case BFIN_CPU_BF534: \ |
97 | builtin_define ("__ADSPBF534__"); \ | |
98 | break; \ | |
99 | case BFIN_CPU_BF536: \ | |
100 | builtin_define ("__ADSPBF536__"); \ | |
101 | break; \ | |
9d3f9aa3 BS |
102 | case BFIN_CPU_BF537: \ |
103 | builtin_define ("__ADSPBF537__"); \ | |
104 | break; \ | |
ea2382be JZ |
105 | case BFIN_CPU_BF538: \ |
106 | builtin_define ("__ADSPBF538__"); \ | |
107 | break; \ | |
108 | case BFIN_CPU_BF539: \ | |
109 | builtin_define ("__ADSPBF539__"); \ | |
110 | break; \ | |
5254cd50 BS |
111 | case BFIN_CPU_BF542M: \ |
112 | builtin_define ("__ADSPBF542M__"); \ | |
a563e6e9 | 113 | /* FALLTHRU */ \ |
ea2382be JZ |
114 | case BFIN_CPU_BF542: \ |
115 | builtin_define ("__ADSPBF542__"); \ | |
116 | builtin_define ("__ADSPBF54x__"); \ | |
117 | break; \ | |
5254cd50 BS |
118 | case BFIN_CPU_BF544M: \ |
119 | builtin_define ("__ADSPBF544M__"); \ | |
a563e6e9 | 120 | /* FALLTHRU */ \ |
ea2382be JZ |
121 | case BFIN_CPU_BF544: \ |
122 | builtin_define ("__ADSPBF544__"); \ | |
123 | builtin_define ("__ADSPBF54x__"); \ | |
124 | break; \ | |
5254cd50 BS |
125 | case BFIN_CPU_BF547M: \ |
126 | builtin_define ("__ADSPBF547M__"); \ | |
a563e6e9 | 127 | /* FALLTHRU */ \ |
64882649 BS |
128 | case BFIN_CPU_BF547: \ |
129 | builtin_define ("__ADSPBF547__"); \ | |
130 | builtin_define ("__ADSPBF54x__"); \ | |
131 | break; \ | |
5254cd50 BS |
132 | case BFIN_CPU_BF548M: \ |
133 | builtin_define ("__ADSPBF548M__"); \ | |
a563e6e9 | 134 | /* FALLTHRU */ \ |
5254cd50 BS |
135 | case BFIN_CPU_BF548: \ |
136 | builtin_define ("__ADSPBF548__"); \ | |
137 | builtin_define ("__ADSPBF54x__"); \ | |
138 | break; \ | |
139 | case BFIN_CPU_BF549M: \ | |
140 | builtin_define ("__ADSPBF549M__"); \ | |
a563e6e9 | 141 | /* FALLTHRU */ \ |
ea2382be JZ |
142 | case BFIN_CPU_BF549: \ |
143 | builtin_define ("__ADSPBF549__"); \ | |
144 | builtin_define ("__ADSPBF54x__"); \ | |
145 | break; \ | |
28f601ff JZ |
146 | case BFIN_CPU_BF561: \ |
147 | builtin_define ("__ADSPBF561__"); \ | |
148 | break; \ | |
033b0805 SH |
149 | case BFIN_CPU_BF592: \ |
150 | builtin_define ("__ADSPBF592__"); \ | |
151 | builtin_define ("__ADSPBF59x__"); \ | |
152 | break; \ | |
9d3f9aa3 BS |
153 | } \ |
154 | \ | |
ea2382be JZ |
155 | if (bfin_si_revision != -1) \ |
156 | { \ | |
157 | /* space of 0xnnnn and a NUL */ \ | |
5ead67f6 | 158 | char *buf = XALLOCAVEC (char, 7); \ |
ea2382be JZ |
159 | \ |
160 | sprintf (buf, "0x%04x", bfin_si_revision); \ | |
161 | builtin_define_with_value ("__SILICON_REVISION__", buf, 0); \ | |
162 | } \ | |
163 | \ | |
164 | if (bfin_workarounds) \ | |
165 | builtin_define ("__WORKAROUNDS_ENABLED"); \ | |
166 | if (ENABLE_WA_SPECULATIVE_LOADS) \ | |
167 | builtin_define ("__WORKAROUND_SPECULATIVE_LOADS"); \ | |
168 | if (ENABLE_WA_SPECULATIVE_SYNCS) \ | |
169 | builtin_define ("__WORKAROUND_SPECULATIVE_SYNCS"); \ | |
c2d54fdf | 170 | if (ENABLE_WA_INDIRECT_CALLS) \ |
bf85bc3d | 171 | builtin_define ("__WORKAROUND_INDIRECT_CALLS"); \ |
2643f14e | 172 | if (ENABLE_WA_RETS) \ |
bf85bc3d | 173 | builtin_define ("__WORKAROUND_RETS"); \ |
ea2382be | 174 | \ |
6614f9f5 | 175 | if (TARGET_FDPIC) \ |
f13488c0 BS |
176 | { \ |
177 | builtin_define ("__BFIN_FDPIC__"); \ | |
178 | builtin_define ("__FDPIC__"); \ | |
179 | } \ | |
ea2382be JZ |
180 | if (TARGET_ID_SHARED_LIBRARY \ |
181 | && !TARGET_SEP_DATA) \ | |
4af990cd | 182 | builtin_define ("__ID_SHARED_LIB__"); \ |
ae80f469 JZ |
183 | if (flag_no_builtin) \ |
184 | builtin_define ("__NO_BUILTIN"); \ | |
16869606 BS |
185 | if (TARGET_MULTICORE) \ |
186 | builtin_define ("__BFIN_MULTICORE"); \ | |
187 | if (TARGET_COREA) \ | |
188 | builtin_define ("__BFIN_COREA"); \ | |
189 | if (TARGET_COREB) \ | |
190 | builtin_define ("__BFIN_COREB"); \ | |
191 | if (TARGET_SDRAM) \ | |
192 | builtin_define ("__BFIN_SDRAM"); \ | |
ea2382be | 193 | } \ |
0d4a78eb BS |
194 | while (0) |
195 | #endif | |
196 | ||
6614f9f5 | 197 | #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\ |
93147119 | 198 | %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \ |
6614f9f5 BS |
199 | %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\ |
200 | %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \ | |
201 | " | |
202 | #ifndef SUBTARGET_DRIVER_SELF_SPECS | |
203 | # define SUBTARGET_DRIVER_SELF_SPECS | |
204 | #endif | |
205 | ||
2c117a21 | 206 | #define LINK_GCC_C_SEQUENCE_SPEC "\ |
f37866e8 | 207 | %{mfast-fp:-lbffastfp} %G %{!nolibc:%L} %{mfast-fp:-lbffastfp} %G \ |
2c117a21 | 208 | " |
6614f9f5 | 209 | |
6614f9f5 BS |
210 | #undef ASM_SPEC |
211 | #define ASM_SPEC "\ | |
6614f9f5 BS |
212 | %{mno-fdpic:-mnopic} %{mfdpic}" |
213 | ||
214 | #define LINK_SPEC "\ | |
215 | %{h*} %{v:-V} \ | |
6614f9f5 BS |
216 | %{mfdpic:-melf32bfinfd -z text} \ |
217 | %{static:-dn -Bstatic} \ | |
218 | %{shared:-G -Bdynamic} \ | |
219 | %{symbolic:-Bsymbolic} \ | |
6614f9f5 BS |
220 | -init __init -fini __fini " |
221 | ||
0d4a78eb BS |
222 | /* Generate DSP instructions, like DSP halfword loads */ |
223 | #define TARGET_DSP (1) | |
224 | ||
ea2382be | 225 | #define TARGET_DEFAULT 0 |
0d4a78eb | 226 | |
0d4a78eb BS |
227 | /* Maximum number of library ids we permit */ |
228 | #define MAX_LIBRARY_ID 255 | |
229 | ||
230 | extern const char *bfin_library_id_string; | |
231 | ||
0d4a78eb BS |
232 | #define FUNCTION_MODE SImode |
233 | #define Pmode SImode | |
234 | ||
235 | /* store-condition-codes instructions store 0 for false | |
236 | This is the value stored for true. */ | |
237 | #define STORE_FLAG_VALUE 1 | |
238 | ||
239 | /* Define this if pushing a word on the stack | |
240 | makes the stack pointer a smaller address. */ | |
62f9f30b | 241 | #define STACK_GROWS_DOWNWARD 1 |
0d4a78eb BS |
242 | |
243 | #define STACK_PUSH_CODE PRE_DEC | |
244 | ||
a4d05547 | 245 | /* Define this to nonzero if the nominal address of the stack frame |
0d4a78eb BS |
246 | is at the high-address end of the local variables; |
247 | that is, each additional local variable allocated | |
248 | goes at a more negative offset in the frame. */ | |
f62c8a5c | 249 | #define FRAME_GROWS_DOWNWARD 1 |
0d4a78eb BS |
250 | |
251 | /* We define a dummy ARGP register; the parameters start at offset 0 from | |
252 | it. */ | |
253 | #define FIRST_PARM_OFFSET(DECL) 0 | |
254 | ||
0d4a78eb BS |
255 | /* Register to use for pushing function arguments. */ |
256 | #define STACK_POINTER_REGNUM REG_P6 | |
257 | ||
258 | /* Base register for access to local variables of the function. */ | |
259 | #define FRAME_POINTER_REGNUM REG_P7 | |
260 | ||
261 | /* A dummy register that will be eliminated to either FP or SP. */ | |
262 | #define ARG_POINTER_REGNUM REG_ARGP | |
263 | ||
264 | /* `PIC_OFFSET_TABLE_REGNUM' | |
265 | The register number of the register used to address a table of | |
266 | static data addresses in memory. In some cases this register is | |
267 | defined by a processor's "application binary interface" (ABI). | |
268 | When this macro is defined, RTL is generated for this register | |
269 | once, as with the stack pointer and frame pointer registers. If | |
270 | this macro is not defined, it is up to the machine-dependent files | |
271 | to allocate such a register (if necessary). */ | |
272 | #define PIC_OFFSET_TABLE_REGNUM (REG_P5) | |
273 | ||
6614f9f5 BS |
274 | #define FDPIC_FPTR_REGNO REG_P1 |
275 | #define FDPIC_REGNO REG_P3 | |
276 | #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO) | |
277 | ||
0d4a78eb BS |
278 | /* A static chain register for nested functions. We need to use a |
279 | call-clobbered register for this. */ | |
280 | #define STATIC_CHAIN_REGNUM REG_P2 | |
281 | ||
282 | /* Define this if functions should assume that stack space has been | |
283 | allocated for arguments even when their values are passed in | |
284 | registers. | |
285 | ||
286 | The value of this macro is the size, in bytes, of the area reserved for | |
287 | arguments passed in registers. | |
288 | ||
289 | This space can either be allocated by the caller or be a part of the | |
290 | machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' | |
291 | says which. */ | |
292 | #define FIXED_STACK_AREA 12 | |
293 | #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA | |
294 | ||
295 | /* Define this if the above stack space is to be considered part of the | |
296 | * space allocated by the caller. */ | |
81464b2c | 297 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 |
0d4a78eb BS |
298 | |
299 | /* Define this if the maximum size of all the outgoing args is to be | |
300 | accumulated and pushed during the prologue. The amount can be | |
38173d38 | 301 | found in the variable crtl->outgoing_args_size. */ |
0d4a78eb BS |
302 | #define ACCUMULATE_OUTGOING_ARGS 1 |
303 | ||
0d4a78eb BS |
304 | /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */ |
305 | ||
520c62ad BS |
306 | /* If defined, a C expression to compute the alignment for a local |
307 | variable. TYPE is the data type, and ALIGN is the alignment that | |
308 | the object would ordinarily have. The value of this macro is used | |
309 | instead of that alignment to align the object. | |
310 | ||
311 | If this macro is not defined, then ALIGN is used. | |
312 | ||
313 | One use of this macro is to increase alignment of medium-size | |
314 | data to make it all fit in fewer cache lines. */ | |
315 | ||
316 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN)) | |
317 | ||
6614f9f5 | 318 | #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18) |
0d4a78eb BS |
319 | \f |
320 | /* Definitions for register eliminations. | |
321 | ||
322 | This is an array of structures. Each structure initializes one pair | |
323 | of eliminable registers. The "from" register number is given first, | |
324 | followed by "to". Eliminations of the same "from" register are listed | |
325 | in order of preference. | |
326 | ||
327 | There are two registers that can always be eliminated on the i386. | |
328 | The frame pointer and the arg pointer can be replaced by either the | |
329 | hard frame pointer or to the stack pointer, depending upon the | |
330 | circumstances. The hard frame pointer is not used before reload and | |
331 | so it is not eligible for elimination. */ | |
332 | ||
333 | #define ELIMINABLE_REGS \ | |
334 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
335 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ | |
336 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \ | |
337 | ||
0d4a78eb BS |
338 | /* Define the offset between two registers, one to be eliminated, and the other |
339 | its replacement, at the start of a routine. */ | |
340 | ||
341 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
342 | ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO))) | |
343 | \f | |
344 | /* This processor has | |
345 | 8 data register for doing arithmetic | |
346 | 8 pointer register for doing addressing, including | |
347 | 1 stack pointer P6 | |
348 | 1 frame pointer P7 | |
349 | 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3) | |
350 | 1 condition code flag register CC | |
351 | 5 return address registers RETS/I/X/N/E | |
352 | 1 arithmetic status register (ASTAT). */ | |
353 | ||
b03149e1 | 354 | #define FIRST_PSEUDO_REGISTER 50 |
0d4a78eb | 355 | |
0d4a78eb | 356 | #define D_REGNO_P(X) ((X) <= REG_R7) |
c4963a0a | 357 | #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7) |
b03149e1 JZ |
358 | #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3) |
359 | #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X)) | |
360 | #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3) | |
361 | #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X))) | |
362 | #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X))) | |
363 | #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X))) | |
364 | #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X))) | |
0d4a78eb BS |
365 | |
366 | #define REGISTER_NAMES { \ | |
367 | "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \ | |
368 | "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \ | |
df259245 JZ |
369 | "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \ |
370 | "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \ | |
0d4a78eb BS |
371 | "A0", "A1", \ |
372 | "CC", \ | |
373 | "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \ | |
b03149e1 JZ |
374 | "ARGP", \ |
375 | "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \ | |
0d4a78eb BS |
376 | } |
377 | ||
378 | #define SHORT_REGISTER_NAMES { \ | |
379 | "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \ | |
380 | "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \ | |
df259245 JZ |
381 | "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \ |
382 | "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", } | |
0d4a78eb BS |
383 | |
384 | #define HIGH_REGISTER_NAMES { \ | |
385 | "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \ | |
386 | "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \ | |
df259245 JZ |
387 | "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \ |
388 | "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", } | |
0d4a78eb BS |
389 | |
390 | #define DREGS_PAIR_NAMES { \ | |
391 | "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, } | |
392 | ||
393 | #define BYTE_REGISTER_NAMES { \ | |
394 | "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", } | |
395 | ||
396 | ||
397 | /* 1 for registers that have pervasive standard uses | |
398 | and are not available for the register allocator. */ | |
399 | ||
400 | #define FIXED_REGISTERS \ | |
401 | /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \ | |
402 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ | |
df259245 JZ |
403 | /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \ |
404 | 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \ | |
b03149e1 JZ |
405 | /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \ |
406 | 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
407 | /*lb0/1 */ \ | |
408 | 1, 1 \ | |
0d4a78eb BS |
409 | } |
410 | ||
411 | /* 1 for registers not available across function calls. | |
412 | These must include the FIXED_REGISTERS and also any | |
413 | registers that can be used without being saved. | |
414 | The latter must include the registers where values are returned | |
415 | and the register where structure-value addresses are passed. | |
416 | Aside from that, you can include as many other registers as you like. */ | |
417 | ||
418 | #define CALL_USED_REGISTERS \ | |
419 | /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \ | |
420 | { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \ | |
df259245 | 421 | /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \ |
0d4a78eb | 422 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
b03149e1 JZ |
423 | /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \ |
424 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
425 | /*lb0/1 */ \ | |
426 | 1, 1 \ | |
0d4a78eb BS |
427 | } |
428 | ||
429 | /* Order in which to allocate registers. Each register must be | |
430 | listed once, even those in FIXED_REGISTERS. List frame pointer | |
431 | late and fixed registers last. Note that, in general, we prefer | |
432 | registers listed in CALL_USED_REGISTERS, keeping the others | |
433 | available for storage of persistent values. */ | |
434 | ||
435 | #define REG_ALLOC_ORDER \ | |
436 | { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \ | |
437 | REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \ | |
438 | REG_A0, REG_A1, \ | |
df259245 JZ |
439 | REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \ |
440 | REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \ | |
0d4a78eb BS |
441 | REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \ |
442 | REG_ASTAT, REG_SEQSTAT, REG_USP, \ | |
b03149e1 JZ |
443 | REG_CC, REG_ARGP, \ |
444 | REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \ | |
0d4a78eb BS |
445 | } |
446 | ||
0d4a78eb BS |
447 | /* Define the classes of registers for register constraints in the |
448 | machine description. Also define ranges of constants. | |
449 | ||
450 | One of the classes must always be named ALL_REGS and include all hard regs. | |
451 | If there is more than one class, another class must be named NO_REGS | |
452 | and contain no registers. | |
453 | ||
454 | The name GENERAL_REGS must be the name of a class (or an alias for | |
455 | another name such as ALL_REGS). This is the class of registers | |
456 | that is allowed by "g" or "r" in a register constraint. | |
457 | Also, registers outside this class are allocated only when | |
458 | instructions express preferences for them. | |
459 | ||
460 | The classes must be numbered in nondecreasing order; that is, | |
461 | a larger-numbered class must never be contained completely | |
462 | in a smaller-numbered class. | |
463 | ||
464 | For any two classes, it is very desirable that there be another | |
465 | class that represents their union. */ | |
466 | ||
467 | ||
468 | enum reg_class | |
469 | { | |
470 | NO_REGS, | |
471 | IREGS, | |
472 | BREGS, | |
473 | LREGS, | |
474 | MREGS, | |
f652d14b | 475 | CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */ |
0d4a78eb BS |
476 | DAGREGS, |
477 | EVEN_AREGS, | |
478 | ODD_AREGS, | |
479 | AREGS, | |
480 | CCREGS, | |
481 | EVEN_DREGS, | |
482 | ODD_DREGS, | |
2889abed BS |
483 | D0REGS, |
484 | D1REGS, | |
485 | D2REGS, | |
486 | D3REGS, | |
487 | D4REGS, | |
488 | D5REGS, | |
489 | D6REGS, | |
490 | D7REGS, | |
0d4a78eb | 491 | DREGS, |
03848bd0 | 492 | P0REGS, |
6614f9f5 BS |
493 | FDPIC_REGS, |
494 | FDPIC_FPTR_REGS, | |
0d4a78eb BS |
495 | PREGS_CLOBBERED, |
496 | PREGS, | |
c4963a0a | 497 | IPREGS, |
0d4a78eb BS |
498 | DPREGS, |
499 | MOST_REGS, | |
b03149e1 JZ |
500 | LT_REGS, |
501 | LC_REGS, | |
502 | LB_REGS, | |
0d4a78eb BS |
503 | PROLOGUE_REGS, |
504 | NON_A_CC_REGS, | |
505 | ALL_REGS, LIM_REG_CLASSES | |
506 | }; | |
507 | ||
508 | #define N_REG_CLASSES ((int)LIM_REG_CLASSES) | |
509 | ||
510 | #define GENERAL_REGS DPREGS | |
511 | ||
512 | /* Give names of register classes as strings for dump file. */ | |
513 | ||
514 | #define REG_CLASS_NAMES \ | |
515 | { "NO_REGS", \ | |
516 | "IREGS", \ | |
517 | "BREGS", \ | |
518 | "LREGS", \ | |
519 | "MREGS", \ | |
520 | "CIRCREGS", \ | |
521 | "DAGREGS", \ | |
522 | "EVEN_AREGS", \ | |
523 | "ODD_AREGS", \ | |
524 | "AREGS", \ | |
525 | "CCREGS", \ | |
526 | "EVEN_DREGS", \ | |
527 | "ODD_DREGS", \ | |
2889abed BS |
528 | "D0REGS", \ |
529 | "D1REGS", \ | |
530 | "D2REGS", \ | |
531 | "D3REGS", \ | |
532 | "D4REGS", \ | |
533 | "D5REGS", \ | |
534 | "D6REGS", \ | |
535 | "D7REGS", \ | |
0d4a78eb | 536 | "DREGS", \ |
03848bd0 | 537 | "P0REGS", \ |
6614f9f5 BS |
538 | "FDPIC_REGS", \ |
539 | "FDPIC_FPTR_REGS", \ | |
0d4a78eb BS |
540 | "PREGS_CLOBBERED", \ |
541 | "PREGS", \ | |
c4963a0a | 542 | "IPREGS", \ |
0d4a78eb BS |
543 | "DPREGS", \ |
544 | "MOST_REGS", \ | |
b03149e1 JZ |
545 | "LT_REGS", \ |
546 | "LC_REGS", \ | |
547 | "LB_REGS", \ | |
0d4a78eb BS |
548 | "PROLOGUE_REGS", \ |
549 | "NON_A_CC_REGS", \ | |
550 | "ALL_REGS" } | |
551 | ||
552 | /* An initializer containing the contents of the register classes, as integers | |
553 | which are bit masks. The Nth integer specifies the contents of class N. | |
554 | The way the integer MASK is interpreted is that register R is in the class | |
555 | if `MASK & (1 << R)' is 1. | |
556 | ||
557 | When the machine has more than 32 registers, an integer does not suffice. | |
558 | Then the integers are replaced by sub-initializers, braced groupings | |
559 | containing several integers. Each sub-initializer must be suitable as an | |
560 | initializer for the type `HARD_REG_SET' which is defined in | |
561 | `hard-reg-set.h'. */ | |
562 | ||
563 | /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use | |
564 | MOST_REGS as the union of DPREGS and DAGREGS. */ | |
565 | ||
566 | #define REG_CLASS_CONTENTS \ | |
567 | /* 31 - 0 63-32 */ \ | |
568 | { { 0x00000000, 0 }, /* NO_REGS */ \ | |
df259245 JZ |
569 | { 0x000f0000, 0 }, /* IREGS */ \ |
570 | { 0x00f00000, 0 }, /* BREGS */ \ | |
571 | { 0x0f000000, 0 }, /* LREGS */ \ | |
0d4a78eb BS |
572 | { 0xf0000000, 0 }, /* MREGS */ \ |
573 | { 0x0fff0000, 0 }, /* CIRCREGS */ \ | |
574 | { 0xffff0000, 0 }, /* DAGREGS */ \ | |
575 | { 0x00000000, 0x1 }, /* EVEN_AREGS */ \ | |
576 | { 0x00000000, 0x2 }, /* ODD_AREGS */ \ | |
577 | { 0x00000000, 0x3 }, /* AREGS */ \ | |
578 | { 0x00000000, 0x4 }, /* CCREGS */ \ | |
579 | { 0x00000055, 0 }, /* EVEN_DREGS */ \ | |
580 | { 0x000000aa, 0 }, /* ODD_DREGS */ \ | |
2889abed BS |
581 | { 0x00000001, 0 }, /* D0REGS */ \ |
582 | { 0x00000002, 0 }, /* D1REGS */ \ | |
583 | { 0x00000004, 0 }, /* D2REGS */ \ | |
584 | { 0x00000008, 0 }, /* D3REGS */ \ | |
585 | { 0x00000010, 0 }, /* D4REGS */ \ | |
586 | { 0x00000020, 0 }, /* D5REGS */ \ | |
587 | { 0x00000040, 0 }, /* D6REGS */ \ | |
588 | { 0x00000080, 0 }, /* D7REGS */ \ | |
0d4a78eb | 589 | { 0x000000ff, 0 }, /* DREGS */ \ |
03848bd0 | 590 | { 0x00000100, 0x000 }, /* P0REGS */ \ |
6614f9f5 BS |
591 | { 0x00000800, 0x000 }, /* FDPIC_REGS */ \ |
592 | { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \ | |
0d4a78eb BS |
593 | { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \ |
594 | { 0x0000ff00, 0x800 }, /* PREGS */ \ | |
c4963a0a | 595 | { 0x000fff00, 0x800 }, /* IPREGS */ \ |
0d4a78eb BS |
596 | { 0x0000ffff, 0x800 }, /* DPREGS */ \ |
597 | { 0xffffffff, 0x800 }, /* MOST_REGS */\ | |
b03149e1 JZ |
598 | { 0x00000000, 0x3000 }, /* LT_REGS */\ |
599 | { 0x00000000, 0xc000 }, /* LC_REGS */\ | |
600 | { 0x00000000, 0x30000 }, /* LB_REGS */\ | |
601 | { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\ | |
602 | { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\ | |
603 | { 0xffffffff, 0x3ffff }} /* ALL_REGS */ | |
0d4a78eb | 604 | |
c4963a0a BS |
605 | #define IREG_POSSIBLE_P(OUTER) \ |
606 | ((OUTER) == POST_INC || (OUTER) == PRE_INC \ | |
607 | || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \ | |
608 | || (OUTER) == MEM || (OUTER) == ADDRESS) | |
609 | ||
86fc3d06 | 610 | #define MODE_CODE_BASE_REG_CLASS(MODE, AS, OUTER, INDEX) \ |
c4963a0a BS |
611 | ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS) |
612 | ||
0d4a78eb BS |
613 | #define INDEX_REG_CLASS PREGS |
614 | ||
c4963a0a BS |
615 | #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \ |
616 | (P_REGNO_P (X) || (X) == REG_ARGP \ | |
617 | || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \ | |
618 | && I_REGNO_P (X))) | |
619 | ||
620 | #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \ | |
621 | ((X) >= FIRST_PSEUDO_REGISTER \ | |
622 | || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)) | |
0d4a78eb BS |
623 | |
624 | #ifdef REG_OK_STRICT | |
86fc3d06 | 625 | #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, AS, OUTER, INDEX) \ |
c4963a0a | 626 | REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX) |
0d4a78eb | 627 | #else |
86fc3d06 | 628 | #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, AS, OUTER, INDEX) \ |
c4963a0a | 629 | REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX) |
0d4a78eb BS |
630 | #endif |
631 | ||
0d4a78eb BS |
632 | #define REGNO_OK_FOR_INDEX_P(X) 0 |
633 | ||
0d4a78eb BS |
634 | /* The same information, inverted: |
635 | Return the class number of the smallest class containing | |
636 | reg number REGNO. This could be a conditional expression | |
637 | or could index an array. */ | |
638 | ||
639 | #define REGNO_REG_CLASS(REGNO) \ | |
2889abed BS |
640 | ((REGNO) == REG_R0 ? D0REGS \ |
641 | : (REGNO) == REG_R1 ? D1REGS \ | |
642 | : (REGNO) == REG_R2 ? D2REGS \ | |
643 | : (REGNO) == REG_R3 ? D3REGS \ | |
644 | : (REGNO) == REG_R4 ? D4REGS \ | |
645 | : (REGNO) == REG_R5 ? D5REGS \ | |
646 | : (REGNO) == REG_R6 ? D6REGS \ | |
647 | : (REGNO) == REG_R7 ? D7REGS \ | |
03848bd0 | 648 | : (REGNO) == REG_P0 ? P0REGS \ |
0d4a78eb | 649 | : (REGNO) < REG_I0 ? PREGS \ |
c4963a0a | 650 | : (REGNO) == REG_ARGP ? PREGS \ |
0d4a78eb BS |
651 | : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \ |
652 | : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \ | |
653 | : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \ | |
654 | : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \ | |
655 | : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \ | |
b03149e1 JZ |
656 | : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \ |
657 | : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \ | |
658 | : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \ | |
0d4a78eb BS |
659 | : (REGNO) == REG_CC ? CCREGS \ |
660 | : (REGNO) >= REG_RETS ? PROLOGUE_REGS \ | |
661 | : NO_REGS) | |
662 | ||
42db504c SB |
663 | /* When this hook returns true for MODE, the compiler allows |
664 | registers explicitly used in the rtl to be used as spill registers | |
665 | but prevents the compiler from extending the lifetime of these | |
666 | registers. */ | |
667 | #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true | |
0d4a78eb | 668 | |
0d4a78eb BS |
669 | /* Return the maximum number of consecutive registers |
670 | needed to represent mode MODE in a register of class CLASS. */ | |
75d8b2d0 BS |
671 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
672 | ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \ | |
673 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
0d4a78eb | 674 | |
0d4a78eb BS |
675 | /* A C expression that is nonzero if hard register TO can be |
676 | considered for use as a rename register for FROM register */ | |
677 | #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO) | |
678 | ||
0d4a78eb BS |
679 | /* `PREFERRED_RELOAD_CLASS (X, CLASS)' |
680 | A C expression that places additional restrictions on the register | |
681 | class to use when it is necessary to copy value X into a register | |
682 | in class CLASS. The value is a register class; perhaps CLASS, or | |
683 | perhaps another, smaller class. */ | |
aeffb4b5 BS |
684 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ |
685 | (GET_CODE (X) == POST_INC \ | |
686 | || GET_CODE (X) == POST_DEC \ | |
687 | || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS)) | |
0d4a78eb | 688 | |
0d4a78eb BS |
689 | /* Function Calling Conventions. */ |
690 | ||
691 | /* The type of the current function; normal functions are of type | |
692 | SUBROUTINE. */ | |
693 | typedef enum { | |
694 | SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER | |
695 | } e_funkind; | |
9840d30a | 696 | #define FUNCTION_RETURN_REGISTERS { REG_RETS, REG_RETI, REG_RETX, REG_RETN } |
0d4a78eb BS |
697 | |
698 | #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 } | |
699 | ||
6d459e2b BS |
700 | /* Flags for the call/call_value rtl operations set up by function_arg */ |
701 | #define CALL_NORMAL 0x00000000 /* no special processing */ | |
702 | #define CALL_LONG 0x00000001 /* always call indirect */ | |
703 | #define CALL_SHORT 0x00000002 /* always call by symbol */ | |
704 | ||
0d4a78eb BS |
705 | typedef struct { |
706 | int words; /* # words passed so far */ | |
707 | int nregs; /* # registers available for passing */ | |
708 | int *arg_regs; /* array of register -1 terminated */ | |
6d459e2b | 709 | int call_cookie; /* Do special things for this call */ |
0d4a78eb BS |
710 | } CUMULATIVE_ARGS; |
711 | ||
0d4a78eb BS |
712 | #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO) |
713 | ||
714 | ||
715 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
716 | for a call to a function whose data type is FNTYPE. | |
717 | For a library call, FNTYPE is 0. */ | |
718 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \ | |
719 | (init_cumulative_args (&CUM, FNTYPE, LIBNAME)) | |
720 | ||
0d4a78eb BS |
721 | /* Define how to find the value returned by a function. |
722 | VALTYPE is the data type of the value (as a tree). | |
723 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
724 | otherwise, FUNC is 0. | |
725 | */ | |
726 | ||
727 | #define VALUE_REGNO(MODE) (REG_R0) | |
728 | ||
729 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
730 | gen_rtx_REG (TYPE_MODE (VALTYPE), \ | |
731 | VALUE_REGNO(TYPE_MODE(VALTYPE))) | |
732 | ||
733 | /* Define how to find the value returned by a library function | |
734 | assuming the value has mode MODE. */ | |
735 | ||
736 | #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE)) | |
737 | ||
738 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0) | |
739 | ||
740 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
0d4a78eb BS |
741 | |
742 | /* Before the prologue, the return address is in the RETS register. */ | |
743 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS) | |
744 | ||
745 | #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT) | |
746 | ||
747 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS) | |
748 | ||
749 | /* Call instructions don't modify the stack pointer on the Blackfin. */ | |
750 | #define INCOMING_FRAME_SP_OFFSET 0 | |
751 | ||
752 | /* Describe how we implement __builtin_eh_return. */ | |
753 | #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) | |
754 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2) | |
755 | #define EH_RETURN_HANDLER_RTX \ | |
0a81f074 RS |
756 | gen_frame_mem (Pmode, plus_constant (Pmode, frame_pointer_rtx, \ |
757 | UNITS_PER_WORD)) | |
0d4a78eb BS |
758 | |
759 | /* Addressing Modes */ | |
760 | ||
0d4a78eb BS |
761 | /* A number, the maximum number of registers that can appear in a |
762 | valid memory address. Note that it is up to you to specify a | |
331d9186 | 763 | value equal to the maximum number that `TARGET_LEGITIMATE_ADDRESS_P' |
0d4a78eb BS |
764 | would ever accept. */ |
765 | #define MAX_REGS_PER_ADDRESS 1 | |
766 | ||
0d4a78eb BS |
767 | #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \ |
768 | (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode) | |
769 | ||
0d4a78eb BS |
770 | #define HAVE_POST_INCREMENT 1 |
771 | #define HAVE_POST_DECREMENT 1 | |
772 | #define HAVE_PRE_DECREMENT 1 | |
773 | ||
774 | /* `LEGITIMATE_PIC_OPERAND_P (X)' | |
775 | A C expression that is nonzero if X is a legitimate immediate | |
776 | operand on the target machine when generating position independent | |
777 | code. You can assume that X satisfies `CONSTANT_P', so you need | |
778 | not check this. You can also assume FLAG_PIC is true, so you need | |
779 | not check it either. You need not define this macro if all | |
780 | constants (including `SYMBOL_REF') can be immediate operands when | |
781 | generating position independent code. */ | |
782 | #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X) | |
783 | ||
784 | #define SYMBOLIC_CONST(X) \ | |
785 | (GET_CODE (X) == SYMBOL_REF \ | |
786 | || GET_CODE (X) == LABEL_REF \ | |
787 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
788 | ||
0d4a78eb BS |
789 | #define NOTICE_UPDATE_CC(EXPR, INSN) 0 |
790 | ||
0d4a78eb BS |
791 | /* Max number of bytes we can move from memory to memory |
792 | in one reasonably fast instruction. */ | |
793 | #define MOVE_MAX UNITS_PER_WORD | |
794 | ||
b548a9c2 BS |
795 | /* If a memory-to-memory move would take MOVE_RATIO or more simple |
796 | move-instruction pairs, we will do a movmem or libcall instead. */ | |
797 | ||
e04ad03d | 798 | #define MOVE_RATIO(speed) 5 |
0d4a78eb BS |
799 | |
800 | /* STORAGE LAYOUT: target machine storage layout | |
801 | Define this macro as a C expression which is nonzero if accessing | |
802 | less than a word of memory (i.e. a `char' or a `short') is no | |
803 | faster than accessing a word of memory, i.e., if such access | |
804 | require more than one instruction or if there is no difference in | |
805 | cost between byte and (aligned) word loads. | |
806 | ||
807 | When this macro is not defined, the compiler will access a field by | |
808 | finding the smallest containing object; when it is defined, a | |
809 | fullword load will be used if alignment permits. Unless bytes | |
810 | accesses are faster than word accesses, using word accesses is | |
811 | preferable since it may eliminate subsequent memory access if | |
812 | subsequent accesses occur to other fields in the same word of the | |
813 | structure, but to different bytes. */ | |
814 | #define SLOW_BYTE_ACCESS 0 | |
815 | #define SLOW_SHORT_ACCESS 0 | |
816 | ||
817 | /* Define this if most significant bit is lowest numbered | |
818 | in instructions that operate on numbered bit-fields. */ | |
819 | #define BITS_BIG_ENDIAN 0 | |
820 | ||
821 | /* Define this if most significant byte of a word is the lowest numbered. | |
822 | We can't access bytes but if we could we would in the Big Endian order. */ | |
823 | #define BYTES_BIG_ENDIAN 0 | |
824 | ||
825 | /* Define this if most significant word of a multiword number is numbered. */ | |
826 | #define WORDS_BIG_ENDIAN 0 | |
827 | ||
0d4a78eb BS |
828 | /* Width in bits of a "word", which is the contents of a machine register. |
829 | Note that this is not necessarily the width of data type `int'; | |
830 | if using 16-bit ints on a 68000, this would still be 32. | |
831 | But on a machine with 16-bit registers, this would be 16. */ | |
832 | #define BITS_PER_WORD 32 | |
833 | ||
834 | /* Width of a word, in units (bytes). */ | |
835 | #define UNITS_PER_WORD 4 | |
836 | ||
0d4a78eb BS |
837 | /* Width in bits of a pointer. |
838 | See also the macro `Pmode1' defined below. */ | |
839 | #define POINTER_SIZE 32 | |
840 | ||
841 | /* Allocation boundary (in *bits*) for storing pointers in memory. */ | |
842 | #define POINTER_BOUNDARY 32 | |
843 | ||
844 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
845 | #define PARM_BOUNDARY 32 | |
846 | ||
847 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
848 | #define STACK_BOUNDARY 32 | |
849 | ||
850 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
851 | #define FUNCTION_BOUNDARY 32 | |
852 | ||
853 | /* Alignment of field after `int : 0' in a structure. */ | |
854 | #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD | |
855 | ||
856 | /* No data type wants to be aligned rounder than this. */ | |
857 | #define BIGGEST_ALIGNMENT 32 | |
858 | ||
859 | /* Define this if move instructions will actually fail to work | |
860 | when given unaligned data. */ | |
861 | #define STRICT_ALIGNMENT 1 | |
862 | ||
863 | /* (shell-command "rm c-decl.o stor-layout.o") | |
864 | * never define PCC_BITFIELD_TYPE_MATTERS | |
865 | * really cause some alignment problem | |
866 | */ | |
867 | ||
868 | #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \ | |
869 | BITS_PER_UNIT) | |
870 | ||
871 | #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \ | |
872 | BITS_PER_UNIT) | |
873 | ||
874 | ||
875 | /* what is the 'type' of size_t */ | |
876 | #define SIZE_TYPE "long unsigned int" | |
877 | ||
878 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
879 | #define DEFAULT_SIGNED_CHAR 1 | |
880 | #define FLOAT_TYPE_SIZE BITS_PER_WORD | |
881 | #define SHORT_TYPE_SIZE 16 | |
882 | #define CHAR_TYPE_SIZE 8 | |
883 | #define INT_TYPE_SIZE 32 | |
884 | #define LONG_TYPE_SIZE 32 | |
885 | #define LONG_LONG_TYPE_SIZE 64 | |
886 | ||
887 | /* Note: Fix this to depend on target switch. -- lev */ | |
888 | ||
889 | /* Note: Try to implement double and force long double. -- tonyko | |
890 | * #define __DOUBLES_ARE_FLOATS__ | |
891 | * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE | |
892 | * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE | |
893 | * #define DOUBLES_ARE_FLOATS 1 | |
894 | */ | |
895 | ||
896 | #define DOUBLE_TYPE_SIZE 64 | |
897 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
898 | ||
899 | /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)' | |
900 | A macro to update M and UNSIGNEDP when an object whose type is | |
901 | TYPE and which has the specified mode and signedness is to be | |
902 | stored in a register. This macro is only called when TYPE is a | |
903 | scalar type. | |
904 | ||
905 | On most RISC machines, which only have operations that operate on | |
906 | a full register, define this macro to set M to `word_mode' if M is | |
907 | an integer mode narrower than `BITS_PER_WORD'. In most cases, | |
908 | only integer modes should be widened because wider-precision | |
909 | floating-point operations are usually more expensive than their | |
910 | narrower counterparts. | |
911 | ||
912 | For most machines, the macro definition does not change UNSIGNEDP. | |
913 | However, some machines, have instructions that preferentially | |
914 | handle either signed or unsigned quantities of certain modes. For | |
915 | example, on the DEC Alpha, 32-bit loads from memory and 32-bit add | |
916 | instructions sign-extend the result to 64 bits. On such machines, | |
917 | set UNSIGNEDP according to which kind of extension is more | |
918 | efficient. | |
919 | ||
920 | Do not define this macro if it would never modify M.*/ | |
921 | ||
922 | #define BFIN_PROMOTE_MODE_P(MODE) \ | |
923 | (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \ | |
924 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) | |
925 | ||
926 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
927 | if (BFIN_PROMOTE_MODE_P(MODE)) \ | |
928 | { \ | |
929 | if (MODE == QImode) \ | |
930 | UNSIGNEDP = 1; \ | |
931 | else if (MODE == HImode) \ | |
932 | UNSIGNEDP = 0; \ | |
933 | (MODE) = SImode; \ | |
934 | } | |
935 | ||
936 | /* Describing Relative Costs of Operations */ | |
937 | ||
938 | /* Do not put function addr into constant pool */ | |
939 | #define NO_FUNCTION_CSE 1 | |
940 | ||
0d4a78eb BS |
941 | /* Specify the machine mode that this machine uses |
942 | for the index in the tablejump instruction. */ | |
943 | #define CASE_VECTOR_MODE SImode | |
944 | ||
945 | #define JUMP_TABLES_IN_TEXT_SECTION flag_pic | |
946 | ||
947 | /* Define if operations between registers always perform the operation | |
948 | on the full register even if a narrower mode is specified. | |
9e11bfef | 949 | #define WORD_REGISTER_OPERATIONS 1 |
0d4a78eb BS |
950 | */ |
951 | ||
3efd5670 BS |
952 | /* Evaluates to true if A and B are mac flags that can be used |
953 | together in a single multiply insn. That is the case if they are | |
954 | both the same flag not involving M, or if one is a combination of | |
955 | the other with M. */ | |
956 | #define MACFLAGS_MATCH_P(A, B) \ | |
957 | ((A) == (B) \ | |
958 | || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \ | |
959 | || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \ | |
960 | || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \ | |
961 | || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS)) | |
962 | ||
0d4a78eb BS |
963 | /* Switch into a generic section. */ |
964 | #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section | |
965 | ||
966 | #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE) | |
967 | #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX) | |
968 | ||
969 | typedef enum sections { | |
970 | CODE_DIR, | |
971 | DATA_DIR, | |
972 | LAST_SECT_NM | |
973 | } SECT_ENUM_T; | |
974 | ||
975 | typedef enum directives { | |
976 | LONG_CONST_DIR, | |
977 | SHORT_CONST_DIR, | |
978 | BYTE_CONST_DIR, | |
979 | SPACE_DIR, | |
980 | INIT_DIR, | |
981 | LAST_DIR_NM | |
982 | } DIR_ENUM_T; | |
983 | ||
980d8882 BS |
984 | #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \ |
985 | ((C) == ';' \ | |
986 | || ((C) == '|' && (STR)[1] == '|')) | |
987 | ||
0d4a78eb BS |
988 | #define TEXT_SECTION_ASM_OP ".text;" |
989 | #define DATA_SECTION_ASM_OP ".data;" | |
990 | ||
991 | #define ASM_APP_ON "" | |
992 | #define ASM_APP_OFF "" | |
993 | ||
994 | #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \ | |
995 | do { fputs (".global ", FILE); \ | |
996 | assemble_name (FILE, NAME); \ | |
997 | fputc (';',FILE); \ | |
998 | fputc ('\n',FILE); \ | |
999 | } while (0) | |
1000 | ||
1001 | #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ | |
1002 | do { \ | |
1003 | fputs (".type ", FILE); \ | |
1004 | assemble_name (FILE, NAME); \ | |
1005 | fputs (", STT_FUNC", FILE); \ | |
1006 | fputc (';',FILE); \ | |
1007 | fputc ('\n',FILE); \ | |
1008 | ASM_OUTPUT_LABEL(FILE, NAME); \ | |
1009 | } while (0) | |
1010 | ||
1011 | #define ASM_OUTPUT_LABEL(FILE, NAME) \ | |
1012 | do { assemble_name (FILE, NAME); \ | |
1013 | fputs (":\n",FILE); \ | |
1014 | } while (0) | |
1015 | ||
1016 | #define ASM_OUTPUT_LABELREF(FILE,NAME) \ | |
1017 | do { fprintf (FILE, "_%s", NAME); \ | |
1018 | } while (0) | |
1019 | ||
0d4a78eb BS |
1020 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ |
1021 | do { char __buf[256]; \ | |
1022 | fprintf (FILE, "\t.dd\t"); \ | |
1023 | ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ | |
1024 | assemble_name (FILE, __buf); \ | |
1025 | fputc (';', FILE); \ | |
1026 | fputc ('\n', FILE); \ | |
1027 | } while (0) | |
1028 | ||
1029 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
1030 | MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) | |
1031 | ||
1032 | #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ | |
1033 | do { \ | |
1034 | char __buf[256]; \ | |
1035 | fprintf (FILE, "\t.dd\t"); \ | |
1036 | ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ | |
1037 | assemble_name (FILE, __buf); \ | |
1038 | fputs (" - ", FILE); \ | |
1039 | ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \ | |
1040 | assemble_name (FILE, __buf); \ | |
1041 | fputc (';', FILE); \ | |
1042 | fputc ('\n', FILE); \ | |
1043 | } while (0) | |
1044 | ||
1045 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
21956c07 BS |
1046 | do { \ |
1047 | if ((LOG) != 0) \ | |
1048 | fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \ | |
0d4a78eb BS |
1049 | } while (0) |
1050 | ||
1051 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
1052 | do { \ | |
1053 | asm_output_skip (FILE, SIZE); \ | |
1054 | } while (0) | |
1055 | ||
1056 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ | |
1057 | do { \ | |
d6b5193b | 1058 | switch_to_section (data_section); \ |
0d4a78eb BS |
1059 | if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \ |
1060 | ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \ | |
1061 | ASM_OUTPUT_LABEL (FILE, NAME); \ | |
1062 | fprintf (FILE, "%s %ld;\n", ASM_SPACE, \ | |
1063 | (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \ | |
1064 | } while (0) | |
1065 | ||
1066 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
1067 | do { \ | |
1068 | ASM_GLOBALIZE_LABEL1(FILE,NAME); \ | |
1069 | ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0) | |
1070 | ||
1071 | #define ASM_COMMENT_START "//" | |
1072 | ||
420ccc84 | 1073 | #define PROFILE_BEFORE_PROLOGUE |
56014148 JZ |
1074 | #define FUNCTION_PROFILER(FILE, LABELNO) \ |
1075 | do { \ | |
420ccc84 SH |
1076 | fprintf (FILE, "\t[--SP] = RETS;\n"); \ |
1077 | if (TARGET_LONG_CALLS) \ | |
1078 | { \ | |
1079 | fprintf (FILE, "\tP2.h = __mcount;\n"); \ | |
1080 | fprintf (FILE, "\tP2.l = __mcount;\n"); \ | |
1081 | fprintf (FILE, "\tCALL (P2);\n"); \ | |
1082 | } \ | |
1083 | else \ | |
1084 | fprintf (FILE, "\tCALL __mcount;\n"); \ | |
1085 | fprintf (FILE, "\tRETS = [SP++];\n"); \ | |
0d4a78eb BS |
1086 | } while(0) |
1087 | ||
56014148 JZ |
1088 | #undef NO_PROFILE_COUNTERS |
1089 | #define NO_PROFILE_COUNTERS 1 | |
1090 | ||
420ccc84 SH |
1091 | #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "\t[--SP] = %s;\n", reg_names[REGNO]) |
1092 | #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "\t%s = [SP++];\n", reg_names[REGNO]) | |
0d4a78eb | 1093 | |
984514ac | 1094 | extern rtx bfin_cc_rtx, bfin_rets_rtx; |
0d4a78eb BS |
1095 | |
1096 | /* This works for GAS and some other assemblers. */ | |
1097 | #define SET_ASM_OP ".set " | |
1098 | ||
0d4a78eb BS |
1099 | /* DBX register number for a given compiler register number */ |
1100 | #define DBX_REGISTER_NUMBER(REGNO) (REGNO) | |
1101 | ||
1102 | #define SIZE_ASM_OP "\t.size\t" | |
1103 | ||
97a988bc | 1104 | extern int splitting_for_sched, splitting_loops; |
bbbc206e BS |
1105 | |
1106 | #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!') | |
1107 | ||
9840d30a BS |
1108 | #ifndef TARGET_SUPPORTS_SYNC_CALLS |
1109 | #define TARGET_SUPPORTS_SYNC_CALLS 0 | |
1110 | #endif | |
1111 | ||
677f3fa8 JM |
1112 | struct bfin_cpu |
1113 | { | |
1114 | const char *name; | |
1115 | bfin_cpu_t type; | |
1116 | int si_revision; | |
1117 | unsigned int workarounds; | |
1118 | }; | |
1119 | ||
1120 | extern const struct bfin_cpu bfin_cpus[]; | |
1121 | ||
0d4a78eb | 1122 | #endif /* _BFIN_CONFIG */ |