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0d4a78eb | 1 | ;;- Machine description for Blackfin for GNU compiler |
d1e082c2 | 2 | ;; Copyright (C) 2005-2013 Free Software Foundation, Inc. |
0d4a78eb BS |
3 | ;; Contributed by Analog Devices. |
4 | ||
5 | ;; This file is part of GCC. | |
6 | ||
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | ;; by the Free Software Foundation; either version 3, or (at your |
0d4a78eb BS |
10 | ;; option) any later version. |
11 | ||
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | ;; along with GCC; see the file COPYING3. If not see |
19 | ;; <http://www.gnu.org/licenses/>. | |
0d4a78eb BS |
20 | |
21 | ; operand punctuation marks: | |
22 | ; | |
23 | ; X -- integer value printed as log2 | |
24 | ; Y -- integer value printed as log2(~value) - for bitclear | |
25 | ; h -- print half word register, low part | |
26 | ; d -- print half word register, high part | |
27 | ; D -- print operand as dregs pairs | |
28 | ; w -- print operand as accumulator register word (a0w, a1w) | |
29 | ; H -- high part of double mode operand | |
30 | ; T -- byte register representation Oct. 02 2001 | |
31 | ||
32 | ; constant operand classes | |
33 | ; | |
34 | ; J 2**N 5bit imm scaled | |
35 | ; Ks7 -64 .. 63 signed 7bit imm | |
36 | ; Ku5 0..31 unsigned 5bit imm | |
37 | ; Ks4 -8 .. 7 signed 4bit imm | |
38 | ; Ks3 -4 .. 3 signed 3bit imm | |
39 | ; Ku3 0 .. 7 unsigned 3bit imm | |
40 | ; Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n | |
41 | ; | |
42 | ; register operands | |
43 | ; d (r0..r7) | |
44 | ; a (p0..p5,fp,sp) | |
45 | ; e (a0, a1) | |
46 | ; b (i0..i3) | |
47 | ; f (m0..m3) | |
a9c46998 JZ |
48 | ; v (b0..b3) |
49 | ; c (i0..i3,m0..m3) CIRCREGS | |
50 | ; C (CC) CCREGS | |
b03149e1 JZ |
51 | ; t (lt0,lt1) |
52 | ; k (lc0,lc1) | |
a9c46998 | 53 | ; u (lb0,lb1) |
0d4a78eb BS |
54 | ; |
55 | ||
56 | ;; Define constants for hard registers. | |
57 | ||
58 | (define_constants | |
59 | [(REG_R0 0) | |
60 | (REG_R1 1) | |
61 | (REG_R2 2) | |
62 | (REG_R3 3) | |
63 | (REG_R4 4) | |
64 | (REG_R5 5) | |
65 | (REG_R6 6) | |
66 | (REG_R7 7) | |
67 | ||
68 | (REG_P0 8) | |
69 | (REG_P1 9) | |
70 | (REG_P2 10) | |
71 | (REG_P3 11) | |
72 | (REG_P4 12) | |
73 | (REG_P5 13) | |
74 | (REG_P6 14) | |
75 | (REG_P7 15) | |
76 | ||
77 | (REG_SP 14) | |
78 | (REG_FP 15) | |
79 | ||
80 | (REG_I0 16) | |
df259245 JZ |
81 | (REG_I1 17) |
82 | (REG_I2 18) | |
83 | (REG_I3 19) | |
84 | ||
85 | (REG_B0 20) | |
86 | (REG_B1 21) | |
87 | (REG_B2 22) | |
88 | (REG_B3 23) | |
89 | ||
90 | (REG_L0 24) | |
91 | (REG_L1 25) | |
92 | (REG_L2 26) | |
0d4a78eb BS |
93 | (REG_L3 27) |
94 | ||
95 | (REG_M0 28) | |
96 | (REG_M1 29) | |
97 | (REG_M2 30) | |
98 | (REG_M3 31) | |
99 | ||
100 | (REG_A0 32) | |
101 | (REG_A1 33) | |
102 | ||
103 | (REG_CC 34) | |
104 | (REG_RETS 35) | |
105 | (REG_RETI 36) | |
106 | (REG_RETX 37) | |
107 | (REG_RETN 38) | |
108 | (REG_RETE 39) | |
109 | ||
110 | (REG_ASTAT 40) | |
111 | (REG_SEQSTAT 41) | |
112 | (REG_USP 42) | |
113 | ||
b03149e1 JZ |
114 | (REG_ARGP 43) |
115 | ||
116 | (REG_LT0 44) | |
117 | (REG_LT1 45) | |
118 | (REG_LC0 46) | |
119 | (REG_LC1 47) | |
120 | (REG_LB0 48) | |
121 | (REG_LB1 49)]) | |
0d4a78eb BS |
122 | |
123 | ;; Constants used in UNSPECs and UNSPEC_VOLATILEs. | |
124 | ||
125 | (define_constants | |
126 | [(UNSPEC_CBRANCH_TAKEN 0) | |
127 | (UNSPEC_CBRANCH_NOPS 1) | |
128 | (UNSPEC_RETURN 2) | |
129 | (UNSPEC_MOVE_PIC 3) | |
130 | (UNSPEC_LIBRARY_OFFSET 4) | |
75d8b2d0 BS |
131 | (UNSPEC_PUSH_MULTIPLE 5) |
132 | ;; Multiply or MAC with extra CONST_INT operand specifying the macflag | |
133 | (UNSPEC_MUL_WITH_FLAG 6) | |
6614f9f5 BS |
134 | (UNSPEC_MAC_WITH_FLAG 7) |
135 | (UNSPEC_MOVE_FDPIC 8) | |
b03149e1 | 136 | (UNSPEC_FUNCDESC_GOT17M4 9) |
bbbc206e | 137 | (UNSPEC_LSETUP_END 10) |
942fd98f | 138 | ;; Distinguish a 32-bit version of an insn from a 16-bit version. |
b18e284e | 139 | (UNSPEC_32BIT 11) |
1d7d5ac4 | 140 | (UNSPEC_NOP 12) |
9840d30a BS |
141 | (UNSPEC_ONES 13) |
142 | (UNSPEC_ATOMIC 14)]) | |
0d4a78eb BS |
143 | |
144 | (define_constants | |
cd9c1ca8 | 145 | [(UNSPEC_VOLATILE_CSYNC 1) |
6614f9f5 | 146 | (UNSPEC_VOLATILE_SSYNC 2) |
1ca950ca | 147 | (UNSPEC_VOLATILE_LOAD_FUNCDESC 3) |
669eeb28 | 148 | (UNSPEC_VOLATILE_STORE_EH_HANDLER 4) |
c7cb1555 BS |
149 | (UNSPEC_VOLATILE_DUMMY 5) |
150 | (UNSPEC_VOLATILE_STALL 6)]) | |
0d4a78eb | 151 | |
75d8b2d0 BS |
152 | (define_constants |
153 | [(MACFLAG_NONE 0) | |
154 | (MACFLAG_T 1) | |
155 | (MACFLAG_FU 2) | |
156 | (MACFLAG_TFU 3) | |
157 | (MACFLAG_IS 4) | |
158 | (MACFLAG_IU 5) | |
159 | (MACFLAG_W32 6) | |
160 | (MACFLAG_M 7) | |
3efd5670 BS |
161 | (MACFLAG_IS_M 8) |
162 | (MACFLAG_S2RND 9) | |
163 | (MACFLAG_ISS2 10) | |
164 | (MACFLAG_IH 11)]) | |
75d8b2d0 | 165 | |
0d4a78eb | 166 | (define_attr "type" |
b3187e24 | 167 | "move,movcc,mvi,mcld,mcst,dsp32,dsp32shiftimm,mult,alu0,shft,brcc,br,call,misc,sync,compare,dummy,stall" |
0d4a78eb BS |
168 | (const_string "misc")) |
169 | ||
c7cb1555 | 170 | (define_attr "addrtype" "32bit,preg,spreg,ireg" |
36662eb1 | 171 | (cond [(and (eq_attr "type" "mcld") |
b3187e24 | 172 | (and (match_operand 0 "dp_register_operand" "") |
36662eb1 BS |
173 | (match_operand 1 "mem_p_address_operand" ""))) |
174 | (const_string "preg") | |
c7cb1555 | 175 | (and (eq_attr "type" "mcld") |
b3187e24 | 176 | (and (match_operand 0 "dp_register_operand" "") |
c7cb1555 BS |
177 | (match_operand 1 "mem_spfp_address_operand" ""))) |
178 | (const_string "spreg") | |
36662eb1 | 179 | (and (eq_attr "type" "mcld") |
b3187e24 | 180 | (and (match_operand 0 "dp_register_operand" "") |
36662eb1 BS |
181 | (match_operand 1 "mem_i_address_operand" ""))) |
182 | (const_string "ireg") | |
183 | (and (eq_attr "type" "mcst") | |
b3187e24 | 184 | (and (match_operand 1 "dp_register_operand" "") |
36662eb1 BS |
185 | (match_operand 0 "mem_p_address_operand" ""))) |
186 | (const_string "preg") | |
c7cb1555 | 187 | (and (eq_attr "type" "mcst") |
b3187e24 | 188 | (and (match_operand 1 "dp_register_operand" "") |
c7cb1555 BS |
189 | (match_operand 0 "mem_spfp_address_operand" ""))) |
190 | (const_string "spreg") | |
36662eb1 | 191 | (and (eq_attr "type" "mcst") |
b3187e24 | 192 | (and (match_operand 1 "dp_register_operand" "") |
36662eb1 BS |
193 | (match_operand 0 "mem_i_address_operand" ""))) |
194 | (const_string "ireg")] | |
195 | (const_string "32bit"))) | |
196 | ||
b3187e24 BS |
197 | (define_attr "storereg" "preg,other" |
198 | (cond [(and (eq_attr "type" "mcst") | |
199 | (match_operand 1 "p_register_operand" "")) | |
200 | (const_string "preg")] | |
201 | (const_string "other"))) | |
202 | ||
0d4a78eb BS |
203 | ;; Scheduling definitions |
204 | ||
205 | (define_automaton "bfin") | |
206 | ||
36662eb1 BS |
207 | (define_cpu_unit "slot0" "bfin") |
208 | (define_cpu_unit "slot1" "bfin") | |
209 | (define_cpu_unit "slot2" "bfin") | |
210 | ||
211 | ;; Three units used to enforce parallel issue restrictions: | |
942fd98f | 212 | ;; only one of the 16-bit slots can use a P register in an address, |
36662eb1 BS |
213 | ;; and only one them can be a store. |
214 | (define_cpu_unit "store" "bfin") | |
215 | (define_cpu_unit "pregs" "bfin") | |
216 | ||
c7cb1555 BS |
217 | ;; A dummy unit used to delay scheduling of loads after a conditional |
218 | ;; branch. | |
219 | (define_cpu_unit "load" "bfin") | |
220 | ||
b3187e24 BS |
221 | ;; A logical unit used to work around anomaly 05000074. |
222 | (define_cpu_unit "anomaly_05000074" "bfin") | |
223 | ||
36662eb1 | 224 | (define_reservation "core" "slot0+slot1+slot2") |
0d4a78eb BS |
225 | |
226 | (define_insn_reservation "alu" 1 | |
96f46444 | 227 | (eq_attr "type" "move,movcc,mvi,alu0,shft,brcc,br,call,misc,sync,compare") |
0d4a78eb BS |
228 | "core") |
229 | ||
230 | (define_insn_reservation "imul" 3 | |
231 | (eq_attr "type" "mult") | |
232 | "core*3") | |
233 | ||
36662eb1 BS |
234 | (define_insn_reservation "dsp32" 1 |
235 | (eq_attr "type" "dsp32") | |
236 | "slot0") | |
237 | ||
b3187e24 BS |
238 | (define_insn_reservation "dsp32shiftimm" 1 |
239 | (and (eq_attr "type" "dsp32shiftimm") | |
dd02d5ef | 240 | (not (match_test "ENABLE_WA_05000074"))) |
b3187e24 BS |
241 | "slot0") |
242 | ||
243 | (define_insn_reservation "dsp32shiftimm_anomaly_05000074" 1 | |
244 | (and (eq_attr "type" "dsp32shiftimm") | |
dd02d5ef | 245 | (match_test "ENABLE_WA_05000074")) |
b3187e24 BS |
246 | "slot0+anomaly_05000074") |
247 | ||
36662eb1 BS |
248 | (define_insn_reservation "load32" 1 |
249 | (and (not (eq_attr "seq_insns" "multi")) | |
250 | (and (eq_attr "type" "mcld") (eq_attr "addrtype" "32bit"))) | |
c7cb1555 | 251 | "core+load") |
36662eb1 BS |
252 | |
253 | (define_insn_reservation "loadp" 1 | |
254 | (and (not (eq_attr "seq_insns" "multi")) | |
255 | (and (eq_attr "type" "mcld") (eq_attr "addrtype" "preg"))) | |
b3187e24 | 256 | "slot1+pregs+load") |
c7cb1555 BS |
257 | |
258 | (define_insn_reservation "loadsp" 1 | |
259 | (and (not (eq_attr "seq_insns" "multi")) | |
260 | (and (eq_attr "type" "mcld") (eq_attr "addrtype" "spreg"))) | |
b3187e24 | 261 | "slot1+pregs") |
36662eb1 BS |
262 | |
263 | (define_insn_reservation "loadi" 1 | |
264 | (and (not (eq_attr "seq_insns" "multi")) | |
265 | (and (eq_attr "type" "mcld") (eq_attr "addrtype" "ireg"))) | |
c7cb1555 | 266 | "(slot1|slot2)+load") |
36662eb1 BS |
267 | |
268 | (define_insn_reservation "store32" 1 | |
269 | (and (not (eq_attr "seq_insns" "multi")) | |
270 | (and (eq_attr "type" "mcst") (eq_attr "addrtype" "32bit"))) | |
0d4a78eb BS |
271 | "core") |
272 | ||
36662eb1 | 273 | (define_insn_reservation "storep" 1 |
b3187e24 BS |
274 | (and (and (not (eq_attr "seq_insns" "multi")) |
275 | (and (eq_attr "type" "mcst") | |
276 | (ior (eq_attr "addrtype" "preg") | |
277 | (eq_attr "addrtype" "spreg")))) | |
dd02d5ef | 278 | (ior (not (match_test "ENABLE_WA_05000074")) |
b3187e24 BS |
279 | (eq_attr "storereg" "other"))) |
280 | "slot1+pregs+store") | |
281 | ||
282 | (define_insn_reservation "storep_anomaly_05000074" 1 | |
283 | (and (and (not (eq_attr "seq_insns" "multi")) | |
284 | (and (eq_attr "type" "mcst") | |
285 | (ior (eq_attr "addrtype" "preg") | |
286 | (eq_attr "addrtype" "spreg")))) | |
dd02d5ef | 287 | (and (match_test "ENABLE_WA_05000074") |
b3187e24 BS |
288 | (eq_attr "storereg" "preg"))) |
289 | "slot1+anomaly_05000074+pregs+store") | |
36662eb1 BS |
290 | |
291 | (define_insn_reservation "storei" 1 | |
b3187e24 BS |
292 | (and (and (not (eq_attr "seq_insns" "multi")) |
293 | (and (eq_attr "type" "mcst") (eq_attr "addrtype" "ireg"))) | |
dd02d5ef | 294 | (ior (not (match_test "ENABLE_WA_05000074")) |
b3187e24 | 295 | (eq_attr "storereg" "other"))) |
36662eb1 BS |
296 | "(slot1|slot2)+store") |
297 | ||
b3187e24 BS |
298 | (define_insn_reservation "storei_anomaly_05000074" 1 |
299 | (and (and (not (eq_attr "seq_insns" "multi")) | |
300 | (and (eq_attr "type" "mcst") (eq_attr "addrtype" "ireg"))) | |
dd02d5ef | 301 | (and (match_test "ENABLE_WA_05000074") |
b3187e24 BS |
302 | (eq_attr "storereg" "preg"))) |
303 | "((slot1+anomaly_05000074)|slot2)+store") | |
304 | ||
36662eb1 BS |
305 | (define_insn_reservation "multi" 2 |
306 | (eq_attr "seq_insns" "multi") | |
307 | "core") | |
308 | ||
c7cb1555 BS |
309 | (define_insn_reservation "load_stall1" 1 |
310 | (and (eq_attr "type" "stall") | |
311 | (match_operand 0 "const1_operand" "")) | |
312 | "core+load*2") | |
313 | ||
314 | (define_insn_reservation "load_stall3" 1 | |
315 | (and (eq_attr "type" "stall") | |
316 | (match_operand 0 "const3_operand" "")) | |
317 | "core+load*4") | |
318 | ||
36662eb1 BS |
319 | (absence_set "slot0" "slot1,slot2") |
320 | (absence_set "slot1" "slot2") | |
321 | ||
0d4a78eb BS |
322 | ;; Make sure genautomata knows about the maximum latency that can be produced |
323 | ;; by the adjust_cost function. | |
324 | (define_insn_reservation "dummy" 5 | |
36662eb1 | 325 | (eq_attr "type" "dummy") |
0d4a78eb BS |
326 | "core") |
327 | \f | |
328 | ;; Operand and operator predicates | |
329 | ||
330 | (include "predicates.md") | |
9fdd7520 | 331 | (include "constraints.md") |
0d4a78eb BS |
332 | \f |
333 | ;;; FRIO branches have been optimized for code density | |
334 | ;;; this comes at a slight cost of complexity when | |
335 | ;;; a compiler needs to generate branches in the general | |
336 | ;;; case. In order to generate the correct branching | |
337 | ;;; mechanisms the compiler needs keep track of instruction | |
338 | ;;; lengths. The follow table describes how to count instructions | |
339 | ;;; for the FRIO architecture. | |
340 | ;;; | |
341 | ;;; unconditional br are 12-bit imm pcrelative branches *2 | |
342 | ;;; conditional br are 10-bit imm pcrelative branches *2 | |
343 | ;;; brcc 10-bit: | |
344 | ;;; 1024 10-bit imm *2 is 2048 (-1024..1022) | |
345 | ;;; br 12-bit : | |
346 | ;;; 4096 12-bit imm *2 is 8192 (-4096..4094) | |
347 | ;;; NOTE : For brcc we generate instructions such as | |
348 | ;;; if cc jmp; jump.[sl] offset | |
349 | ;;; offset of jump.[sl] is from the jump instruction but | |
350 | ;;; gcc calculates length from the if cc jmp instruction | |
a2391c6a JZ |
351 | ;;; furthermore gcc takes the end address of the branch instruction |
352 | ;;; as (pc) for a forward branch | |
353 | ;;; hence our range is (-4094, 4092) instead of (-4096, 4094) for a br | |
0d4a78eb BS |
354 | ;;; |
355 | ;;; The way the (pc) rtx works in these calculations is somewhat odd; | |
356 | ;;; for backward branches it's the address of the current instruction, | |
357 | ;;; for forward branches it's the previously known address of the following | |
358 | ;;; instruction - we have to take this into account by reducing the range | |
359 | ;;; for a forward branch. | |
360 | ||
361 | ;; Lengths for type "mvi" insns are always defined by the instructions | |
362 | ;; themselves. | |
363 | (define_attr "length" "" | |
364 | (cond [(eq_attr "type" "mcld") | |
365 | (if_then_else (match_operand 1 "effective_address_32bit_p" "") | |
366 | (const_int 4) (const_int 2)) | |
367 | ||
368 | (eq_attr "type" "mcst") | |
369 | (if_then_else (match_operand 0 "effective_address_32bit_p" "") | |
370 | (const_int 4) (const_int 2)) | |
371 | ||
372 | (eq_attr "type" "move") (const_int 2) | |
373 | ||
374 | (eq_attr "type" "dsp32") (const_int 4) | |
b3187e24 | 375 | (eq_attr "type" "dsp32shiftimm") (const_int 4) |
0d4a78eb BS |
376 | (eq_attr "type" "call") (const_int 4) |
377 | ||
378 | (eq_attr "type" "br") | |
379 | (if_then_else (and | |
380 | (le (minus (match_dup 0) (pc)) (const_int 4092)) | |
381 | (ge (minus (match_dup 0) (pc)) (const_int -4096))) | |
382 | (const_int 2) | |
383 | (const_int 4)) | |
384 | ||
385 | (eq_attr "type" "brcc") | |
386 | (cond [(and | |
387 | (le (minus (match_dup 3) (pc)) (const_int 1020)) | |
388 | (ge (minus (match_dup 3) (pc)) (const_int -1024))) | |
389 | (const_int 2) | |
390 | (and | |
a2391c6a | 391 | (le (minus (match_dup 3) (pc)) (const_int 4092)) |
0d4a78eb BS |
392 | (ge (minus (match_dup 3) (pc)) (const_int -4094))) |
393 | (const_int 4)] | |
394 | (const_int 6)) | |
395 | ] | |
396 | ||
397 | (const_int 2))) | |
398 | ||
b03149e1 JZ |
399 | ;; Classify the insns into those that are one instruction and those that |
400 | ;; are more than one in sequence. | |
401 | (define_attr "seq_insns" "single,multi" | |
402 | (const_string "single")) | |
403 | ||
4ceb4242 BS |
404 | ;; Describe a user's asm statement. |
405 | (define_asm_attributes | |
406 | [(set_attr "type" "misc") | |
407 | (set_attr "seq_insns" "multi") | |
408 | (set_attr "length" "4")]) | |
409 | ||
0d4a78eb BS |
410 | ;; Conditional moves |
411 | ||
265b1d82 SH |
412 | (define_mode_iterator CCMOV [QI HI SI]) |
413 | ||
414 | (define_expand "mov<mode>cc" | |
415 | [(set (match_operand:CCMOV 0 "register_operand" "") | |
416 | (if_then_else:CCMOV (match_operand 1 "comparison_operator" "") | |
417 | (match_operand:CCMOV 2 "register_operand" "") | |
418 | (match_operand:CCMOV 3 "register_operand" "")))] | |
0d4a78eb BS |
419 | "" |
420 | { | |
265b1d82 | 421 | operands[1] = bfin_gen_compare (operands[1], <MODE>mode); |
0d4a78eb BS |
422 | }) |
423 | ||
265b1d82 SH |
424 | (define_insn "*mov<mode>cc_insn1" |
425 | [(set (match_operand:CCMOV 0 "register_operand" "=da,da,da") | |
426 | (if_then_else:CCMOV | |
4729dc92 | 427 | (eq:BI (match_operand:BI 3 "register_operand" "C,C,C") |
0d4a78eb | 428 | (const_int 0)) |
265b1d82 SH |
429 | (match_operand:CCMOV 1 "register_operand" "da,0,da") |
430 | (match_operand:CCMOV 2 "register_operand" "0,da,da")))] | |
0d4a78eb BS |
431 | "" |
432 | "@ | |
265b1d82 SH |
433 | if !cc %0 = %1; |
434 | if cc %0 = %2; | |
435 | if !cc %0 = %1; if cc %0 = %2;" | |
0d4a78eb | 436 | [(set_attr "length" "2,2,4") |
96f46444 | 437 | (set_attr "type" "movcc") |
b03149e1 | 438 | (set_attr "seq_insns" "*,*,multi")]) |
0d4a78eb | 439 | |
265b1d82 SH |
440 | (define_insn "*mov<mode>cc_insn2" |
441 | [(set (match_operand:CCMOV 0 "register_operand" "=da,da,da") | |
442 | (if_then_else:CCMOV | |
4729dc92 | 443 | (ne:BI (match_operand:BI 3 "register_operand" "C,C,C") |
0d4a78eb | 444 | (const_int 0)) |
265b1d82 SH |
445 | (match_operand:CCMOV 1 "register_operand" "0,da,da") |
446 | (match_operand:CCMOV 2 "register_operand" "da,0,da")))] | |
0d4a78eb BS |
447 | "" |
448 | "@ | |
265b1d82 SH |
449 | if !cc %0 = %2; |
450 | if cc %0 = %1; | |
451 | if cc %0 = %1; if !cc %0 = %2;" | |
0d4a78eb | 452 | [(set_attr "length" "2,2,4") |
96f46444 | 453 | (set_attr "type" "movcc") |
b03149e1 | 454 | (set_attr "seq_insns" "*,*,multi")]) |
0d4a78eb BS |
455 | |
456 | ;; Insns to load HIGH and LO_SUM | |
457 | ||
458 | (define_insn "movsi_high" | |
459 | [(set (match_operand:SI 0 "register_operand" "=x") | |
460 | (high:SI (match_operand:SI 1 "immediate_operand" "i")))] | |
461 | "reload_completed" | |
462 | "%d0 = %d1;" | |
463 | [(set_attr "type" "mvi") | |
464 | (set_attr "length" "4")]) | |
465 | ||
466 | (define_insn "movstricthi_high" | |
467 | [(set (match_operand:SI 0 "register_operand" "+x") | |
468 | (ior:SI (and:SI (match_dup 0) (const_int 65535)) | |
469 | (match_operand:SI 1 "immediate_operand" "i")))] | |
470 | "reload_completed" | |
471 | "%d0 = %d1;" | |
472 | [(set_attr "type" "mvi") | |
473 | (set_attr "length" "4")]) | |
474 | ||
475 | (define_insn "movsi_low" | |
476 | [(set (match_operand:SI 0 "register_operand" "=x") | |
477 | (lo_sum:SI (match_operand:SI 1 "register_operand" "0") | |
478 | (match_operand:SI 2 "immediate_operand" "i")))] | |
479 | "reload_completed" | |
480 | "%h0 = %h2;" | |
481 | [(set_attr "type" "mvi") | |
482 | (set_attr "length" "4")]) | |
483 | ||
484 | (define_insn "movsi_high_pic" | |
485 | [(set (match_operand:SI 0 "register_operand" "=x") | |
486 | (high:SI (unspec:SI [(match_operand:SI 1 "" "")] | |
487 | UNSPEC_MOVE_PIC)))] | |
488 | "" | |
489 | "%d0 = %1@GOT_LOW;" | |
490 | [(set_attr "type" "mvi") | |
491 | (set_attr "length" "4")]) | |
492 | ||
493 | (define_insn "movsi_low_pic" | |
494 | [(set (match_operand:SI 0 "register_operand" "=x") | |
495 | (lo_sum:SI (match_operand:SI 1 "register_operand" "0") | |
496 | (unspec:SI [(match_operand:SI 2 "" "")] | |
497 | UNSPEC_MOVE_PIC)))] | |
498 | "" | |
499 | "%h0 = %h2@GOT_HIGH;" | |
500 | [(set_attr "type" "mvi") | |
501 | (set_attr "length" "4")]) | |
502 | ||
503 | ;;; Move instructions | |
504 | ||
505 | (define_insn_and_split "movdi_insn" | |
506 | [(set (match_operand:DI 0 "nonimmediate_operand" "=x,mx,r") | |
507 | (match_operand:DI 1 "general_operand" "iFx,r,mx"))] | |
0ea80eb6 | 508 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG" |
0d4a78eb BS |
509 | "#" |
510 | "reload_completed" | |
511 | [(set (match_dup 2) (match_dup 3)) | |
512 | (set (match_dup 4) (match_dup 5))] | |
513 | { | |
514 | rtx lo_half[2], hi_half[2]; | |
515 | split_di (operands, 2, lo_half, hi_half); | |
516 | ||
517 | if (reg_overlap_mentioned_p (lo_half[0], hi_half[1])) | |
518 | { | |
519 | operands[2] = hi_half[0]; | |
520 | operands[3] = hi_half[1]; | |
521 | operands[4] = lo_half[0]; | |
522 | operands[5] = lo_half[1]; | |
523 | } | |
524 | else | |
525 | { | |
526 | operands[2] = lo_half[0]; | |
527 | operands[3] = lo_half[1]; | |
528 | operands[4] = hi_half[0]; | |
529 | operands[5] = hi_half[1]; | |
530 | } | |
531 | }) | |
532 | ||
533 | (define_insn "movbi" | |
669eeb28 BS |
534 | [(set (match_operand:BI 0 "nonimmediate_operand" "=x,x,d,md,C,d,C,P1") |
535 | (match_operand:BI 1 "general_operand" "x,xKs3,md,d,d,C,P0,P1"))] | |
0d4a78eb BS |
536 | |
537 | "" | |
538 | "@ | |
539 | %0 = %1; | |
540 | %0 = %1 (X); | |
bbbc206e | 541 | %0 = B %1 (Z)%! |
4729dc92 | 542 | B %0 = %1; |
0d4a78eb | 543 | CC = %1; |
49373252 | 544 | %0 = CC; |
669eeb28 BS |
545 | CC = R0 < R0; |
546 | CC = R0 == R0;" | |
547 | [(set_attr "type" "move,mvi,mcld,mcst,compare,compare,compare,compare") | |
548 | (set_attr "length" "2,2,*,*,2,2,2,2") | |
549 | (set_attr "seq_insns" "*,*,*,*,*,*,*,*")]) | |
0d4a78eb BS |
550 | |
551 | (define_insn "movpdi" | |
552 | [(set (match_operand:PDI 0 "nonimmediate_operand" "=e,<,e") | |
553 | (match_operand:PDI 1 "general_operand" " e,e,>"))] | |
554 | "" | |
555 | "@ | |
556 | %0 = %1; | |
557 | %0 = %x1; %0 = %w1; | |
558 | %w0 = %1; %x0 = %1;" | |
b03149e1 JZ |
559 | [(set_attr "type" "move,mcst,mcld") |
560 | (set_attr "seq_insns" "*,multi,multi")]) | |
0d4a78eb | 561 | |
75d8b2d0 BS |
562 | (define_insn "load_accumulator" |
563 | [(set (match_operand:PDI 0 "register_operand" "=e") | |
564 | (sign_extend:PDI (match_operand:SI 1 "register_operand" "d")))] | |
565 | "" | |
566 | "%0 = %1;" | |
567 | [(set_attr "type" "move")]) | |
568 | ||
569 | (define_insn_and_split "load_accumulator_pair" | |
570 | [(set (match_operand:V2PDI 0 "register_operand" "=e") | |
571 | (sign_extend:V2PDI (vec_concat:V2SI | |
572 | (match_operand:SI 1 "register_operand" "d") | |
573 | (match_operand:SI 2 "register_operand" "d"))))] | |
574 | "" | |
575 | "#" | |
576 | "reload_completed" | |
577 | [(set (match_dup 3) (sign_extend:PDI (match_dup 1))) | |
578 | (set (match_dup 4) (sign_extend:PDI (match_dup 2)))] | |
579 | { | |
580 | operands[3] = gen_rtx_REG (PDImode, REGNO (operands[0])); | |
581 | operands[4] = gen_rtx_REG (PDImode, REGNO (operands[0]) + 1); | |
582 | }) | |
583 | ||
0d4a78eb BS |
584 | (define_insn "*pushsi_insn" |
585 | [(set (mem:SI (pre_dec:SI (reg:SI REG_SP))) | |
586 | (match_operand:SI 0 "register_operand" "xy"))] | |
587 | "" | |
588 | "[--SP] = %0;" | |
589 | [(set_attr "type" "mcst") | |
35e3ced9 | 590 | (set_attr "addrtype" "32bit") |
0d4a78eb BS |
591 | (set_attr "length" "2")]) |
592 | ||
593 | (define_insn "*popsi_insn" | |
35e3ced9 | 594 | [(set (match_operand:SI 0 "register_operand" "=d,xy") |
0d4a78eb BS |
595 | (mem:SI (post_inc:SI (reg:SI REG_SP))))] |
596 | "" | |
bbbc206e | 597 | "%0 = [SP++]%!" |
0d4a78eb | 598 | [(set_attr "type" "mcld") |
35e3ced9 | 599 | (set_attr "addrtype" "preg,32bit") |
0d4a78eb BS |
600 | (set_attr "length" "2")]) |
601 | ||
602 | ;; The first alternative is used to make reload choose a limited register | |
603 | ;; class when faced with a movsi_insn that had its input operand replaced | |
604 | ;; with a PLUS. We generally require fewer secondary reloads this way. | |
0d4a78eb | 605 | |
b03149e1 | 606 | (define_insn "*movsi_insn" |
97a988bc BS |
607 | [(set (match_operand:SI 0 "nonimmediate_operand" "=da,x,da,y,da,x,x,x,da,mr") |
608 | (match_operand:SI 1 "general_operand" "da,x,y,da,xKs7,xKsh,xKuh,ix,mr,da"))] | |
0ea80eb6 | 609 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG" |
b03149e1 | 610 | "@ |
97a988bc BS |
611 | %0 = %1; |
612 | %0 = %1; | |
0d4a78eb BS |
613 | %0 = %1; |
614 | %0 = %1; | |
615 | %0 = %1 (X); | |
616 | %0 = %1 (X); | |
617 | %0 = %1 (Z); | |
618 | # | |
bbbc206e BS |
619 | %0 = %1%! |
620 | %0 = %1%!" | |
97a988bc BS |
621 | [(set_attr "type" "move,move,move,move,mvi,mvi,mvi,*,mcld,mcst") |
622 | (set_attr "length" "2,2,2,2,2,4,4,*,*,*")]) | |
0d4a78eb | 623 | |
bbbc206e BS |
624 | (define_insn "*movsi_insn32" |
625 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
626 | (unspec:SI [(match_operand:SI 1 "nonmemory_operand" "d,P0")] UNSPEC_32BIT))] | |
627 | "" | |
628 | "@ | |
629 | %0 = ROT %1 BY 0%! | |
630 | %0 = %0 -|- %0%!" | |
b3187e24 | 631 | [(set_attr "type" "dsp32shiftimm,dsp32")]) |
bbbc206e BS |
632 | |
633 | (define_split | |
634 | [(set (match_operand:SI 0 "d_register_operand" "") | |
635 | (const_int 0))] | |
636 | "splitting_for_sched && !optimize_size" | |
637 | [(set (match_dup 0) (unspec:SI [(const_int 0)] UNSPEC_32BIT))]) | |
638 | ||
639 | (define_split | |
640 | [(set (match_operand:SI 0 "d_register_operand" "") | |
641 | (match_operand:SI 1 "d_register_operand" ""))] | |
642 | "splitting_for_sched && !optimize_size" | |
643 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_32BIT))]) | |
644 | ||
75d8b2d0 BS |
645 | (define_insn_and_split "*movv2hi_insn" |
646 | [(set (match_operand:V2HI 0 "nonimmediate_operand" "=da,da,d,dm") | |
647 | (match_operand:V2HI 1 "general_operand" "i,di,md,d"))] | |
0d4a78eb | 648 | |
0ea80eb6 | 649 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG" |
75d8b2d0 BS |
650 | "@ |
651 | # | |
652 | %0 = %1; | |
bbbc206e BS |
653 | %0 = %1%! |
654 | %0 = %1%!" | |
75d8b2d0 BS |
655 | "reload_completed && GET_CODE (operands[1]) == CONST_VECTOR" |
656 | [(set (match_dup 0) (high:SI (match_dup 2))) | |
657 | (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 3)))] | |
658 | { | |
659 | HOST_WIDE_INT intval = INTVAL (XVECEXP (operands[1], 0, 1)) << 16; | |
660 | intval |= INTVAL (XVECEXP (operands[1], 0, 0)) & 0xFFFF; | |
554006bd | 661 | |
75d8b2d0 BS |
662 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[0])); |
663 | operands[2] = operands[3] = GEN_INT (trunc_int_for_mode (intval, SImode)); | |
664 | } | |
665 | [(set_attr "type" "move,move,mcld,mcst") | |
666 | (set_attr "length" "2,2,*,*")]) | |
0d4a78eb BS |
667 | |
668 | (define_insn "*movhi_insn" | |
669 | [(set (match_operand:HI 0 "nonimmediate_operand" "=x,da,x,d,mr") | |
670 | (match_operand:HI 1 "general_operand" "x,xKs7,xKsh,mr,d"))] | |
0ea80eb6 | 671 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG" |
c4963a0a BS |
672 | { |
673 | static const char *templates[] = { | |
674 | "%0 = %1;", | |
675 | "%0 = %1 (X);", | |
676 | "%0 = %1 (X);", | |
bbbc206e BS |
677 | "%0 = W %1 (X)%!", |
678 | "W %0 = %1%!", | |
679 | "%h0 = W %1%!", | |
680 | "W %0 = %h1%!" | |
c4963a0a BS |
681 | }; |
682 | int alt = which_alternative; | |
683 | rtx mem = (MEM_P (operands[0]) ? operands[0] | |
684 | : MEM_P (operands[1]) ? operands[1] : NULL_RTX); | |
685 | if (mem && bfin_dsp_memref_p (mem)) | |
686 | alt += 2; | |
687 | return templates[alt]; | |
688 | } | |
0d4a78eb BS |
689 | [(set_attr "type" "move,mvi,mvi,mcld,mcst") |
690 | (set_attr "length" "2,2,4,*,*")]) | |
691 | ||
692 | (define_insn "*movqi_insn" | |
693 | [(set (match_operand:QI 0 "nonimmediate_operand" "=x,da,x,d,mr") | |
694 | (match_operand:QI 1 "general_operand" "x,xKs7,xKsh,mr,d"))] | |
0ea80eb6 | 695 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG" |
0d4a78eb BS |
696 | "@ |
697 | %0 = %1; | |
698 | %0 = %1 (X); | |
699 | %0 = %1 (X); | |
bbbc206e BS |
700 | %0 = B %1 (X)%! |
701 | B %0 = %1%!" | |
0d4a78eb BS |
702 | [(set_attr "type" "move,mvi,mvi,mcld,mcst") |
703 | (set_attr "length" "2,2,4,*,*")]) | |
704 | ||
705 | (define_insn "*movsf_insn" | |
706 | [(set (match_operand:SF 0 "nonimmediate_operand" "=x,x,da,mr") | |
707 | (match_operand:SF 1 "general_operand" "x,Fx,mr,da"))] | |
0ea80eb6 | 708 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG" |
0d4a78eb BS |
709 | "@ |
710 | %0 = %1; | |
711 | # | |
bbbc206e BS |
712 | %0 = %1%! |
713 | %0 = %1%!" | |
0d4a78eb BS |
714 | [(set_attr "type" "move,*,mcld,mcst")]) |
715 | ||
716 | (define_insn_and_split "movdf_insn" | |
717 | [(set (match_operand:DF 0 "nonimmediate_operand" "=x,mx,r") | |
718 | (match_operand:DF 1 "general_operand" "iFx,r,mx"))] | |
0ea80eb6 | 719 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG" |
0d4a78eb BS |
720 | "#" |
721 | "reload_completed" | |
722 | [(set (match_dup 2) (match_dup 3)) | |
723 | (set (match_dup 4) (match_dup 5))] | |
724 | { | |
725 | rtx lo_half[2], hi_half[2]; | |
726 | split_di (operands, 2, lo_half, hi_half); | |
727 | ||
728 | if (reg_overlap_mentioned_p (lo_half[0], hi_half[1])) | |
729 | { | |
730 | operands[2] = hi_half[0]; | |
731 | operands[3] = hi_half[1]; | |
732 | operands[4] = lo_half[0]; | |
733 | operands[5] = lo_half[1]; | |
734 | } | |
735 | else | |
736 | { | |
737 | operands[2] = lo_half[0]; | |
738 | operands[3] = lo_half[1]; | |
739 | operands[4] = hi_half[0]; | |
740 | operands[5] = hi_half[1]; | |
741 | } | |
742 | }) | |
743 | ||
75d8b2d0 BS |
744 | ;; Storing halfwords. |
745 | (define_insn "*movsi_insv" | |
746 | [(set (zero_extract:SI (match_operand 0 "register_operand" "+d,x") | |
747 | (const_int 16) | |
748 | (const_int 16)) | |
749 | (match_operand:SI 1 "nonmemory_operand" "d,n"))] | |
750 | "" | |
751 | "@ | |
bbbc206e | 752 | %d0 = %h1 << 0%! |
75d8b2d0 | 753 | %d0 = %1;" |
b3187e24 | 754 | [(set_attr "type" "dsp32shiftimm,mvi")]) |
75d8b2d0 BS |
755 | |
756 | (define_expand "insv" | |
757 | [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "") | |
758 | (match_operand:SI 1 "immediate_operand" "") | |
759 | (match_operand:SI 2 "immediate_operand" "")) | |
760 | (match_operand:SI 3 "nonmemory_operand" ""))] | |
761 | "" | |
762 | { | |
763 | if (INTVAL (operands[1]) != 16 || INTVAL (operands[2]) != 16) | |
764 | FAIL; | |
765 | ||
766 | /* From mips.md: insert_bit_field doesn't verify that our source | |
767 | matches the predicate, so check it again here. */ | |
768 | if (! register_operand (operands[0], VOIDmode)) | |
769 | FAIL; | |
770 | }) | |
771 | ||
0d4a78eb BS |
772 | ;; This is the main "hook" for PIC code. When generating |
773 | ;; PIC, movsi is responsible for determining when the source address | |
774 | ;; needs PIC relocation and appropriately calling legitimize_pic_address | |
775 | ;; to perform the actual relocation. | |
776 | ||
777 | (define_expand "movsi" | |
778 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
779 | (match_operand:SI 1 "general_operand" ""))] | |
780 | "" | |
d6f6753e BS |
781 | { |
782 | if (expand_move (operands, SImode)) | |
783 | DONE; | |
784 | }) | |
0d4a78eb BS |
785 | |
786 | (define_expand "movv2hi" | |
787 | [(set (match_operand:V2HI 0 "nonimmediate_operand" "") | |
788 | (match_operand:V2HI 1 "general_operand" ""))] | |
789 | "" | |
790 | "expand_move (operands, V2HImode);") | |
791 | ||
792 | (define_expand "movdi" | |
793 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
794 | (match_operand:DI 1 "general_operand" ""))] | |
795 | "" | |
796 | "expand_move (operands, DImode);") | |
797 | ||
798 | (define_expand "movsf" | |
799 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
800 | (match_operand:SF 1 "general_operand" ""))] | |
801 | "" | |
802 | "expand_move (operands, SFmode);") | |
803 | ||
804 | (define_expand "movdf" | |
805 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
806 | (match_operand:DF 1 "general_operand" ""))] | |
807 | "" | |
808 | "expand_move (operands, DFmode);") | |
809 | ||
810 | (define_expand "movhi" | |
811 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
812 | (match_operand:HI 1 "general_operand" ""))] | |
813 | "" | |
814 | "expand_move (operands, HImode);") | |
815 | ||
816 | (define_expand "movqi" | |
817 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
818 | (match_operand:QI 1 "general_operand" ""))] | |
819 | "" | |
820 | " expand_move (operands, QImode); ") | |
821 | ||
822 | ;; Some define_splits to break up SI/SFmode loads of immediate constants. | |
823 | ||
824 | (define_split | |
825 | [(set (match_operand:SI 0 "register_operand" "") | |
826 | (match_operand:SI 1 "symbolic_or_const_operand" ""))] | |
827 | "reload_completed | |
828 | /* Always split symbolic operands; split integer constants that are | |
829 | too large for a single instruction. */ | |
830 | && (GET_CODE (operands[1]) != CONST_INT | |
831 | || (INTVAL (operands[1]) < -32768 | |
832 | || INTVAL (operands[1]) >= 65536 | |
833 | || (INTVAL (operands[1]) >= 32768 && PREG_P (operands[0]))))" | |
834 | [(set (match_dup 0) (high:SI (match_dup 1))) | |
835 | (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 1)))] | |
836 | { | |
837 | if (GET_CODE (operands[1]) == CONST_INT | |
838 | && split_load_immediate (operands)) | |
839 | DONE; | |
840 | /* ??? Do something about TARGET_LOW_64K. */ | |
841 | }) | |
842 | ||
843 | (define_split | |
844 | [(set (match_operand:SF 0 "register_operand" "") | |
845 | (match_operand:SF 1 "immediate_operand" ""))] | |
846 | "reload_completed" | |
847 | [(set (match_dup 2) (high:SI (match_dup 3))) | |
848 | (set (match_dup 2) (lo_sum:SI (match_dup 2) (match_dup 3)))] | |
849 | { | |
850 | long values; | |
851 | REAL_VALUE_TYPE value; | |
852 | ||
3b9dd769 | 853 | gcc_assert (GET_CODE (operands[1]) == CONST_DOUBLE); |
0d4a78eb BS |
854 | |
855 | REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]); | |
856 | REAL_VALUE_TO_TARGET_SINGLE (value, values); | |
857 | ||
858 | operands[2] = gen_rtx_REG (SImode, true_regnum (operands[0])); | |
859 | operands[3] = GEN_INT (trunc_int_for_mode (values, SImode)); | |
860 | if (values >= -32768 && values < 65536) | |
861 | { | |
862 | emit_move_insn (operands[2], operands[3]); | |
863 | DONE; | |
864 | } | |
865 | if (split_load_immediate (operands + 2)) | |
866 | DONE; | |
867 | }) | |
868 | ||
869 | ;; Sadly, this can't be a proper named movstrict pattern, since the compiler | |
870 | ;; expects to be able to use registers for operand 1. | |
871 | ;; Note that the asm instruction is defined by the manual to take an unsigned | |
872 | ;; constant, but it doesn't matter to the assembler, and the compiler only | |
873 | ;; deals with sign-extended constants. Hence "Ksh". | |
75d8b2d0 | 874 | (define_insn "movstricthi_1" |
0d4a78eb BS |
875 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+x")) |
876 | (match_operand:HI 1 "immediate_operand" "Ksh"))] | |
877 | "" | |
878 | "%h0 = %1;" | |
879 | [(set_attr "type" "mvi") | |
880 | (set_attr "length" "4")]) | |
881 | ||
882 | ;; Sign and zero extensions | |
883 | ||
c4963a0a | 884 | (define_insn_and_split "extendhisi2" |
0d4a78eb BS |
885 | [(set (match_operand:SI 0 "register_operand" "=d, d") |
886 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))] | |
887 | "" | |
888 | "@ | |
889 | %0 = %h1 (X); | |
bbbc206e | 890 | %0 = W %h1 (X)%!" |
c4963a0a BS |
891 | "reload_completed && bfin_dsp_memref_p (operands[1])" |
892 | [(set (match_dup 2) (match_dup 1)) | |
893 | (set (match_dup 0) (sign_extend:SI (match_dup 2)))] | |
894 | { | |
895 | operands[2] = gen_lowpart (HImode, operands[0]); | |
896 | } | |
0d4a78eb BS |
897 | [(set_attr "type" "alu0,mcld")]) |
898 | ||
c4963a0a | 899 | (define_insn_and_split "zero_extendhisi2" |
0d4a78eb BS |
900 | [(set (match_operand:SI 0 "register_operand" "=d, d") |
901 | (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))] | |
902 | "" | |
903 | "@ | |
904 | %0 = %h1 (Z); | |
bbbc206e | 905 | %0 = W %h1 (Z)%!" |
c4963a0a BS |
906 | "reload_completed && bfin_dsp_memref_p (operands[1])" |
907 | [(set (match_dup 2) (match_dup 1)) | |
908 | (set (match_dup 0) (zero_extend:SI (match_dup 2)))] | |
909 | { | |
910 | operands[2] = gen_lowpart (HImode, operands[0]); | |
911 | } | |
0d4a78eb BS |
912 | [(set_attr "type" "alu0,mcld")]) |
913 | ||
914 | (define_insn "zero_extendbisi2" | |
915 | [(set (match_operand:SI 0 "register_operand" "=d") | |
916 | (zero_extend:SI (match_operand:BI 1 "nonimmediate_operand" "C")))] | |
917 | "" | |
918 | "%0 = %1;" | |
919 | [(set_attr "type" "compare")]) | |
920 | ||
921 | (define_insn "extendqihi2" | |
922 | [(set (match_operand:HI 0 "register_operand" "=d, d") | |
923 | (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] | |
924 | "" | |
925 | "@ | |
bbbc206e | 926 | %0 = B %1 (X)%! |
0d4a78eb BS |
927 | %0 = %T1 (X);" |
928 | [(set_attr "type" "mcld,alu0")]) | |
929 | ||
930 | (define_insn "extendqisi2" | |
931 | [(set (match_operand:SI 0 "register_operand" "=d, d") | |
932 | (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] | |
933 | "" | |
934 | "@ | |
bbbc206e | 935 | %0 = B %1 (X)%! |
0d4a78eb BS |
936 | %0 = %T1 (X);" |
937 | [(set_attr "type" "mcld,alu0")]) | |
938 | ||
939 | ||
940 | (define_insn "zero_extendqihi2" | |
941 | [(set (match_operand:HI 0 "register_operand" "=d, d") | |
942 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] | |
943 | "" | |
944 | "@ | |
bbbc206e | 945 | %0 = B %1 (Z)%! |
0d4a78eb BS |
946 | %0 = %T1 (Z);" |
947 | [(set_attr "type" "mcld,alu0")]) | |
948 | ||
949 | ||
950 | (define_insn "zero_extendqisi2" | |
951 | [(set (match_operand:SI 0 "register_operand" "=d, d") | |
952 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] | |
953 | "" | |
954 | "@ | |
bbbc206e | 955 | %0 = B %1 (Z)%! |
0d4a78eb BS |
956 | %0 = %T1 (Z);" |
957 | [(set_attr "type" "mcld,alu0")]) | |
958 | ||
959 | ;; DImode logical operations | |
960 | ||
3abcb3a7 | 961 | (define_code_iterator any_logical [and ior xor]) |
0d4a78eb BS |
962 | (define_code_attr optab [(and "and") |
963 | (ior "ior") | |
964 | (xor "xor")]) | |
965 | (define_code_attr op [(and "&") | |
966 | (ior "|") | |
967 | (xor "^")]) | |
968 | (define_code_attr high_result [(and "0") | |
969 | (ior "%H1") | |
970 | (xor "%H1")]) | |
971 | ||
e4fae5f7 BS |
972 | ;; Keep this pattern around to avoid generating NO_CONFLICT blocks. |
973 | (define_expand "<optab>di3" | |
0d4a78eb BS |
974 | [(set (match_operand:DI 0 "register_operand" "=d") |
975 | (any_logical:DI (match_operand:DI 1 "register_operand" "0") | |
e4fae5f7 | 976 | (match_operand:DI 2 "general_operand" "d")))] |
0d4a78eb | 977 | "" |
0d4a78eb | 978 | { |
e4fae5f7 BS |
979 | rtx hi_half[3], lo_half[3]; |
980 | enum insn_code icode = CODE_FOR_<optab>si3; | |
981 | if (!reg_overlap_mentioned_p (operands[0], operands[1]) | |
982 | && !reg_overlap_mentioned_p (operands[0], operands[2])) | |
c41c1387 | 983 | emit_clobber (operands[0]); |
e4fae5f7 BS |
984 | split_di (operands, 3, lo_half, hi_half); |
985 | if (!(*insn_data[icode].operand[2].predicate) (lo_half[2], SImode)) | |
986 | lo_half[2] = force_reg (SImode, lo_half[2]); | |
987 | emit_insn (GEN_FCN (icode) (lo_half[0], lo_half[1], lo_half[2])); | |
988 | if (!(*insn_data[icode].operand[2].predicate) (hi_half[2], SImode)) | |
989 | hi_half[2] = force_reg (SImode, hi_half[2]); | |
990 | emit_insn (GEN_FCN (icode) (hi_half[0], hi_half[1], hi_half[2])); | |
991 | DONE; | |
0d4a78eb BS |
992 | }) |
993 | ||
994 | (define_insn "zero_extendqidi2" | |
995 | [(set (match_operand:DI 0 "register_operand" "=d") | |
996 | (zero_extend:DI (match_operand:QI 1 "register_operand" "d")))] | |
997 | "" | |
998 | "%0 = %T1 (Z);\\n\\t%H0 = 0;" | |
b03149e1 JZ |
999 | [(set_attr "length" "4") |
1000 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
1001 | |
1002 | (define_insn "zero_extendhidi2" | |
1003 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1004 | (zero_extend:DI (match_operand:HI 1 "register_operand" "d")))] | |
1005 | "" | |
1006 | "%0 = %h1 (Z);\\n\\t%H0 = 0;" | |
b03149e1 JZ |
1007 | [(set_attr "length" "4") |
1008 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
1009 | |
1010 | (define_insn_and_split "extendsidi2" | |
1011 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1012 | (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))] | |
1013 | "" | |
1014 | "#" | |
1015 | "reload_completed" | |
1016 | [(set (match_dup 3) (match_dup 1)) | |
1017 | (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))] | |
1018 | { | |
1019 | split_di (operands, 1, operands + 2, operands + 3); | |
1020 | if (REGNO (operands[0]) != REGNO (operands[1])) | |
1021 | emit_move_insn (operands[2], operands[1]); | |
1022 | }) | |
1023 | ||
1024 | (define_insn_and_split "extendqidi2" | |
1025 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1026 | (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))] | |
1027 | "" | |
1028 | "#" | |
1029 | "reload_completed" | |
1030 | [(set (match_dup 2) (sign_extend:SI (match_dup 1))) | |
1031 | (set (match_dup 3) (sign_extend:SI (match_dup 1))) | |
1032 | (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))] | |
1033 | { | |
1034 | split_di (operands, 1, operands + 2, operands + 3); | |
1035 | }) | |
1036 | ||
1037 | (define_insn_and_split "extendhidi2" | |
1038 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1039 | (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))] | |
1040 | "" | |
1041 | "#" | |
1042 | "reload_completed" | |
1043 | [(set (match_dup 2) (sign_extend:SI (match_dup 1))) | |
1044 | (set (match_dup 3) (sign_extend:SI (match_dup 1))) | |
1045 | (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))] | |
1046 | { | |
1047 | split_di (operands, 1, operands + 2, operands + 3); | |
1048 | }) | |
1049 | ||
1050 | ;; DImode arithmetic operations | |
1051 | ||
2889abed BS |
1052 | (define_insn "add_with_carry" |
1053 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
e4fae5f7 | 1054 | (plus:SI (match_operand:SI 1 "register_operand" "%0,d") |
2889abed | 1055 | (match_operand:SI 2 "nonmemory_operand" "Ks7,d"))) |
e4fae5f7 BS |
1056 | (set (match_operand:BI 3 "register_operand" "=C,C") |
1057 | (ltu:BI (not:SI (match_dup 1)) (match_dup 2)))] | |
2889abed BS |
1058 | "" |
1059 | "@ | |
e4fae5f7 BS |
1060 | %0 += %2; cc = ac0; |
1061 | %0 = %1 + %2; cc = ac0;" | |
2889abed | 1062 | [(set_attr "type" "alu0") |
e4fae5f7 | 1063 | (set_attr "length" "4") |
2889abed BS |
1064 | (set_attr "seq_insns" "multi")]) |
1065 | ||
e4fae5f7 BS |
1066 | (define_insn "sub_with_carry" |
1067 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1068 | (minus:SI (match_operand:SI 1 "register_operand" "%d") | |
1069 | (match_operand:SI 2 "nonmemory_operand" "d"))) | |
1070 | (set (match_operand:BI 3 "register_operand" "=C") | |
1071 | (leu:BI (match_dup 2) (match_dup 1)))] | |
0d4a78eb | 1072 | "" |
e4fae5f7 | 1073 | "%0 = %1 - %2; cc = ac0;" |
0d4a78eb | 1074 | [(set_attr "type" "alu0") |
e4fae5f7 | 1075 | (set_attr "length" "4") |
b03149e1 | 1076 | (set_attr "seq_insns" "multi")]) |
0d4a78eb | 1077 | |
e4fae5f7 BS |
1078 | (define_expand "adddi3" |
1079 | [(set (match_operand:DI 0 "register_operand" "") | |
1080 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
1081 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
1082 | (clobber (match_scratch:SI 3 "")) | |
0d4a78eb BS |
1083 | (clobber (reg:CC 34))] |
1084 | "" | |
e4fae5f7 BS |
1085 | { |
1086 | rtx xops[8]; | |
1087 | xops[0] = gen_lowpart (SImode, operands[0]); | |
1088 | xops[1] = simplify_gen_subreg (SImode, operands[0], DImode, 4); | |
1089 | xops[2] = gen_lowpart (SImode, operands[1]); | |
1090 | xops[3] = simplify_gen_subreg (SImode, operands[1], DImode, 4); | |
1091 | xops[4] = gen_lowpart (SImode, operands[2]); | |
1092 | xops[5] = simplify_gen_subreg (SImode, operands[2], DImode, 4); | |
1093 | xops[6] = gen_reg_rtx (SImode); | |
1094 | xops[7] = gen_rtx_REG (BImode, REG_CC); | |
1095 | if (!register_operand (xops[4], SImode) | |
1096 | && (GET_CODE (xops[4]) != CONST_INT | |
9fdd7520 | 1097 | || !satisfies_constraint_Ks7 (xops[4]))) |
e4fae5f7 BS |
1098 | xops[4] = force_reg (SImode, xops[4]); |
1099 | if (!reg_overlap_mentioned_p (operands[0], operands[1]) | |
1100 | && !reg_overlap_mentioned_p (operands[0], operands[2])) | |
c41c1387 | 1101 | emit_clobber (operands[0]); |
e4fae5f7 BS |
1102 | emit_insn (gen_add_with_carry (xops[0], xops[2], xops[4], xops[7])); |
1103 | emit_insn (gen_movbisi (xops[6], xops[7])); | |
1104 | if (!register_operand (xops[5], SImode) | |
1105 | && (GET_CODE (xops[5]) != CONST_INT | |
9fdd7520 | 1106 | || !satisfies_constraint_Ks7 (xops[5]))) |
e4fae5f7 BS |
1107 | xops[5] = force_reg (SImode, xops[5]); |
1108 | if (xops[5] != const0_rtx) | |
1109 | emit_insn (gen_addsi3 (xops[1], xops[3], xops[5])); | |
1110 | else | |
1111 | emit_move_insn (xops[1], xops[3]); | |
1112 | emit_insn (gen_addsi3 (xops[1], xops[1], xops[6])); | |
1113 | DONE; | |
1114 | }) | |
0d4a78eb | 1115 | |
e4fae5f7 BS |
1116 | (define_expand "subdi3" |
1117 | [(set (match_operand:DI 0 "register_operand" "") | |
1118 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
1119 | (match_operand:DI 2 "register_operand" ""))) | |
0d4a78eb BS |
1120 | (clobber (reg:CC 34))] |
1121 | "" | |
e4fae5f7 BS |
1122 | { |
1123 | rtx xops[8]; | |
1124 | xops[0] = gen_lowpart (SImode, operands[0]); | |
1125 | xops[1] = simplify_gen_subreg (SImode, operands[0], DImode, 4); | |
1126 | xops[2] = gen_lowpart (SImode, operands[1]); | |
1127 | xops[3] = simplify_gen_subreg (SImode, operands[1], DImode, 4); | |
1128 | xops[4] = gen_lowpart (SImode, operands[2]); | |
1129 | xops[5] = simplify_gen_subreg (SImode, operands[2], DImode, 4); | |
1130 | xops[6] = gen_reg_rtx (SImode); | |
1131 | xops[7] = gen_rtx_REG (BImode, REG_CC); | |
1132 | if (!reg_overlap_mentioned_p (operands[0], operands[1]) | |
1133 | && !reg_overlap_mentioned_p (operands[0], operands[2])) | |
c41c1387 | 1134 | emit_clobber (operands[0]); |
e4fae5f7 BS |
1135 | emit_insn (gen_sub_with_carry (xops[0], xops[2], xops[4], xops[7])); |
1136 | emit_insn (gen_notbi (xops[7], xops[7])); | |
1137 | emit_insn (gen_movbisi (xops[6], xops[7])); | |
1138 | emit_insn (gen_subsi3 (xops[1], xops[3], xops[5])); | |
1139 | emit_insn (gen_subsi3 (xops[1], xops[1], xops[6])); | |
1140 | DONE; | |
1141 | }) | |
0d4a78eb BS |
1142 | |
1143 | ;; Combined shift/add instructions | |
1144 | ||
1145 | (define_insn "" | |
1146 | [(set (match_operand:SI 0 "register_operand" "=a,d") | |
1147 | (ashift:SI (plus:SI (match_operand:SI 1 "register_operand" "%0,0") | |
1148 | (match_operand:SI 2 "register_operand" "a,d")) | |
1149 | (match_operand:SI 3 "pos_scale_operand" "P1P2,P1P2")))] | |
1150 | "" | |
1151 | "%0 = (%0 + %2) << %3;" /* "shadd %0,%2,%3;" */ | |
1152 | [(set_attr "type" "alu0")]) | |
1153 | ||
1154 | (define_insn "" | |
1155 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1156 | (plus:SI (match_operand:SI 1 "register_operand" "a") | |
1157 | (mult:SI (match_operand:SI 2 "register_operand" "a") | |
1158 | (match_operand:SI 3 "scale_by_operand" "i"))))] | |
1159 | "" | |
1160 | "%0 = %1 + (%2 << %X3);" | |
1161 | [(set_attr "type" "alu0")]) | |
1162 | ||
1163 | (define_insn "" | |
1164 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1165 | (plus:SI (match_operand:SI 1 "register_operand" "a") | |
1166 | (ashift:SI (match_operand:SI 2 "register_operand" "a") | |
1167 | (match_operand:SI 3 "pos_scale_operand" "i"))))] | |
1168 | "" | |
1169 | "%0 = %1 + (%2 << %3);" | |
1170 | [(set_attr "type" "alu0")]) | |
1171 | ||
1172 | (define_insn "" | |
1173 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1174 | (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "a") | |
1175 | (match_operand:SI 2 "scale_by_operand" "i")) | |
1176 | (match_operand:SI 3 "register_operand" "a")))] | |
1177 | "" | |
1178 | "%0 = %3 + (%1 << %X2);" | |
1179 | [(set_attr "type" "alu0")]) | |
1180 | ||
1181 | (define_insn "" | |
1182 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1183 | (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "a") | |
1184 | (match_operand:SI 2 "pos_scale_operand" "i")) | |
1185 | (match_operand:SI 3 "register_operand" "a")))] | |
1186 | "" | |
1187 | "%0 = %3 + (%1 << %2);" | |
1188 | [(set_attr "type" "alu0")]) | |
1189 | ||
1190 | (define_insn "mulhisi3" | |
1191 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1192 | (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%d")) | |
1193 | (sign_extend:SI (match_operand:HI 2 "register_operand" "d"))))] | |
1194 | "" | |
bbbc206e | 1195 | "%0 = %h1 * %h2 (IS)%!" |
0d4a78eb BS |
1196 | [(set_attr "type" "dsp32")]) |
1197 | ||
1198 | (define_insn "umulhisi3" | |
1199 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1200 | (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%d")) | |
1201 | (zero_extend:SI (match_operand:HI 2 "register_operand" "d"))))] | |
1202 | "" | |
bbbc206e | 1203 | "%0 = %h1 * %h2 (FU)%!" |
0d4a78eb BS |
1204 | [(set_attr "type" "dsp32")]) |
1205 | ||
8b44057d BS |
1206 | (define_insn "usmulhisi3" |
1207 | [(set (match_operand:SI 0 "register_operand" "=W") | |
1208 | (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "W")) | |
1209 | (sign_extend:SI (match_operand:HI 2 "register_operand" "W"))))] | |
1210 | "" | |
bbbc206e | 1211 | "%0 = %h2 * %h1 (IS,M)%!" |
8b44057d BS |
1212 | [(set_attr "type" "dsp32")]) |
1213 | ||
9b19b026 SH |
1214 | ;; The alternative involving IREGS requires that the corresponding L register |
1215 | ;; is zero. | |
0d4a78eb BS |
1216 | |
1217 | (define_insn "addsi3" | |
9b19b026 SH |
1218 | [(set (match_operand:SI 0 "register_operand" "=ad,a,d,b") |
1219 | (plus:SI (match_operand:SI 1 "register_operand" "%0, a,d,0") | |
1220 | (match_operand:SI 2 "reg_or_7bit_operand" "Ks7, a,d,fP2P4")))] | |
0d4a78eb BS |
1221 | "" |
1222 | "@ | |
1223 | %0 += %2; | |
1224 | %0 = %1 + %2; | |
9b19b026 SH |
1225 | %0 = %1 + %2; |
1226 | %0 += %2;" | |
0d4a78eb | 1227 | [(set_attr "type" "alu0") |
9b19b026 | 1228 | (set_attr "length" "2,2,2,2")]) |
0d4a78eb | 1229 | |
75d8b2d0 BS |
1230 | (define_insn "ssaddsi3" |
1231 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1232 | (ss_plus:SI (match_operand:SI 1 "register_operand" "d") | |
1233 | (match_operand:SI 2 "register_operand" "d")))] | |
1234 | "" | |
bbbc206e | 1235 | "%0 = %1 + %2 (S)%!" |
75d8b2d0 BS |
1236 | [(set_attr "type" "dsp32")]) |
1237 | ||
d4e85050 | 1238 | (define_insn "subsi3" |
0d4a78eb BS |
1239 | [(set (match_operand:SI 0 "register_operand" "=da,d,a") |
1240 | (minus:SI (match_operand:SI 1 "register_operand" "0,d,0") | |
d4e85050 BS |
1241 | (match_operand:SI 2 "reg_or_neg7bit_operand" "KN7,d,a")))] |
1242 | "" | |
0d4a78eb BS |
1243 | { |
1244 | static const char *const strings_subsi3[] = { | |
1245 | "%0 += -%2;", | |
1246 | "%0 = %1 - %2;", | |
1247 | "%0 -= %2;", | |
1248 | }; | |
1249 | ||
1250 | if (CONSTANT_P (operands[2]) && INTVAL (operands[2]) < 0) { | |
1251 | rtx tmp_op = operands[2]; | |
1252 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
1253 | output_asm_insn ("%0 += %2;", operands); | |
1254 | operands[2] = tmp_op; | |
1255 | return ""; | |
1256 | } | |
1257 | ||
1258 | return strings_subsi3[which_alternative]; | |
1259 | } | |
1260 | [(set_attr "type" "alu0")]) | |
1261 | ||
75d8b2d0 BS |
1262 | (define_insn "sssubsi3" |
1263 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1264 | (ss_minus:SI (match_operand:SI 1 "register_operand" "d") | |
1265 | (match_operand:SI 2 "register_operand" "d")))] | |
1266 | "" | |
bbbc206e | 1267 | "%0 = %1 - %2 (S)%!" |
75d8b2d0 BS |
1268 | [(set_attr "type" "dsp32")]) |
1269 | ||
3efd5670 BS |
1270 | ;; Accumulator addition |
1271 | ||
314f9913 BS |
1272 | (define_insn "addpdi3" |
1273 | [(set (match_operand:PDI 0 "register_operand" "=A") | |
1274 | (ss_plus:PDI (match_operand:PDI 1 "register_operand" "%0") | |
1275 | (match_operand:PDI 2 "nonmemory_operand" "B")))] | |
1276 | "" | |
1277 | "A0 += A1%!" | |
1278 | [(set_attr "type" "dsp32")]) | |
1279 | ||
3efd5670 BS |
1280 | (define_insn "sum_of_accumulators" |
1281 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1282 | (ss_truncate:SI | |
1283 | (ss_plus:PDI (match_operand:PDI 2 "register_operand" "1") | |
1284 | (match_operand:PDI 3 "register_operand" "B")))) | |
1285 | (set (match_operand:PDI 1 "register_operand" "=A") | |
1286 | (ss_plus:PDI (match_dup 2) (match_dup 3)))] | |
1287 | "" | |
1288 | "%0 = (A0 += A1)%!" | |
1289 | [(set_attr "type" "dsp32")]) | |
1290 | ||
314f9913 BS |
1291 | (define_insn "us_truncpdisi2" |
1292 | [(set (match_operand:SI 0 "register_operand" "=D,W") | |
1293 | (us_truncate:SI (match_operand:PDI 1 "register_operand" "A,B")))] | |
1294 | "" | |
1295 | "%0 = %1 (FU)%!" | |
1296 | [(set_attr "type" "dsp32")]) | |
1297 | ||
0d4a78eb BS |
1298 | ;; Bit test instructions |
1299 | ||
1300 | (define_insn "*not_bittst" | |
4729dc92 | 1301 | [(set (match_operand:BI 0 "register_operand" "=C") |
0d4a78eb BS |
1302 | (eq:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d") |
1303 | (const_int 1) | |
1304 | (match_operand:SI 2 "immediate_operand" "Ku5")) | |
1305 | (const_int 0)))] | |
1306 | "" | |
1307 | "cc = !BITTST (%1,%2);" | |
1308 | [(set_attr "type" "alu0")]) | |
1309 | ||
1310 | (define_insn "*bittst" | |
4729dc92 | 1311 | [(set (match_operand:BI 0 "register_operand" "=C") |
0d4a78eb BS |
1312 | (ne:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d") |
1313 | (const_int 1) | |
1314 | (match_operand:SI 2 "immediate_operand" "Ku5")) | |
1315 | (const_int 0)))] | |
1316 | "" | |
1317 | "cc = BITTST (%1,%2);" | |
1318 | [(set_attr "type" "alu0")]) | |
1319 | ||
1320 | (define_insn_and_split "*bit_extract" | |
1321 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1322 | (zero_extract:SI (match_operand:SI 1 "register_operand" "d") | |
1323 | (const_int 1) | |
1324 | (match_operand:SI 2 "immediate_operand" "Ku5"))) | |
1325 | (clobber (reg:BI REG_CC))] | |
1326 | "" | |
1327 | "#" | |
1328 | "" | |
1329 | [(set (reg:BI REG_CC) | |
1330 | (ne:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2)) | |
1331 | (const_int 0))) | |
1332 | (set (match_dup 0) | |
1333 | (ne:SI (reg:BI REG_CC) (const_int 0)))]) | |
1334 | ||
1335 | (define_insn_and_split "*not_bit_extract" | |
1336 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1337 | (zero_extract:SI (not:SI (match_operand:SI 1 "register_operand" "d")) | |
1338 | (const_int 1) | |
1339 | (match_operand:SI 2 "immediate_operand" "Ku5"))) | |
1340 | (clobber (reg:BI REG_CC))] | |
1341 | "" | |
1342 | "#" | |
1343 | "" | |
1344 | [(set (reg:BI REG_CC) | |
1345 | (eq:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2)) | |
1346 | (const_int 0))) | |
1347 | (set (match_dup 0) | |
1348 | (ne:SI (reg:BI REG_CC) (const_int 0)))]) | |
1349 | ||
1350 | (define_insn "*andsi_insn" | |
1351 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") | |
1352 | (and:SI (match_operand:SI 1 "register_operand" "%0,d,d,d") | |
1353 | (match_operand:SI 2 "rhs_andsi3_operand" "L,M1,M2,d")))] | |
1354 | "" | |
1355 | "@ | |
1356 | BITCLR (%0,%Y2); | |
1357 | %0 = %T1 (Z); | |
1358 | %0 = %h1 (Z); | |
1359 | %0 = %1 & %2;" | |
1360 | [(set_attr "type" "alu0")]) | |
1361 | ||
1362 | (define_expand "andsi3" | |
1363 | [(set (match_operand:SI 0 "register_operand" "") | |
1364 | (and:SI (match_operand:SI 1 "register_operand" "") | |
1365 | (match_operand:SI 2 "general_operand" "")))] | |
1366 | "" | |
1367 | { | |
1368 | if (highbits_operand (operands[2], SImode)) | |
1369 | { | |
1370 | operands[2] = GEN_INT (exact_log2 (-INTVAL (operands[2]))); | |
1371 | emit_insn (gen_ashrsi3 (operands[0], operands[1], operands[2])); | |
1372 | emit_insn (gen_ashlsi3 (operands[0], operands[0], operands[2])); | |
1373 | DONE; | |
1374 | } | |
1375 | if (! rhs_andsi3_operand (operands[2], SImode)) | |
1376 | operands[2] = force_reg (SImode, operands[2]); | |
1377 | }) | |
1378 | ||
1379 | (define_insn "iorsi3" | |
1380 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1381 | (ior:SI (match_operand:SI 1 "register_operand" "%0,d") | |
1382 | (match_operand:SI 2 "regorlog2_operand" "J,d")))] | |
1383 | "" | |
1384 | "@ | |
1385 | BITSET (%0, %X2); | |
1386 | %0 = %1 | %2;" | |
1387 | [(set_attr "type" "alu0")]) | |
1388 | ||
1389 | (define_insn "xorsi3" | |
1390 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1391 | (xor:SI (match_operand:SI 1 "register_operand" "%0,d") | |
1392 | (match_operand:SI 2 "regorlog2_operand" "J,d")))] | |
1393 | "" | |
1394 | "@ | |
1395 | BITTGL (%0, %X2); | |
1396 | %0 = %1 ^ %2;" | |
1397 | [(set_attr "type" "alu0")]) | |
1398 | ||
1d7d5ac4 BS |
1399 | (define_insn "ones" |
1400 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1401 | (unspec:HI [(match_operand:SI 1 "register_operand" "d")] | |
1402 | UNSPEC_ONES))] | |
1403 | "" | |
1404 | "%h0 = ONES %1;" | |
1405 | [(set_attr "type" "alu0")]) | |
1406 | ||
0d4a78eb BS |
1407 | (define_insn "smaxsi3" |
1408 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1409 | (smax:SI (match_operand:SI 1 "register_operand" "d") | |
1410 | (match_operand:SI 2 "register_operand" "d")))] | |
1411 | "" | |
bbbc206e | 1412 | "%0 = max(%1,%2)%!" |
0d4a78eb BS |
1413 | [(set_attr "type" "dsp32")]) |
1414 | ||
1415 | (define_insn "sminsi3" | |
1416 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1417 | (smin:SI (match_operand:SI 1 "register_operand" "d") | |
1418 | (match_operand:SI 2 "register_operand" "d")))] | |
1419 | "" | |
bbbc206e | 1420 | "%0 = min(%1,%2)%!" |
0d4a78eb BS |
1421 | [(set_attr "type" "dsp32")]) |
1422 | ||
1423 | (define_insn "abssi2" | |
1424 | [(set (match_operand:SI 0 "register_operand" "=d") | |
75d8b2d0 | 1425 | (abs:SI (match_operand:SI 1 "register_operand" "d")))] |
0d4a78eb | 1426 | "" |
bbbc206e | 1427 | "%0 = abs %1%!" |
0d4a78eb BS |
1428 | [(set_attr "type" "dsp32")]) |
1429 | ||
26c5953d BS |
1430 | (define_insn "ssabssi2" |
1431 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1432 | (ss_abs:SI (match_operand:SI 1 "register_operand" "d")))] | |
1433 | "" | |
1434 | "%0 = abs %1%!" | |
1435 | [(set_attr "type" "dsp32")]) | |
1436 | ||
0d4a78eb BS |
1437 | (define_insn "negsi2" |
1438 | [(set (match_operand:SI 0 "register_operand" "=d") | |
75d8b2d0 | 1439 | (neg:SI (match_operand:SI 1 "register_operand" "d")))] |
0d4a78eb | 1440 | "" |
75d8b2d0 | 1441 | "%0 = -%1;" |
0d4a78eb BS |
1442 | [(set_attr "type" "alu0")]) |
1443 | ||
75d8b2d0 BS |
1444 | (define_insn "ssnegsi2" |
1445 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1446 | (ss_neg:SI (match_operand:SI 1 "register_operand" "d")))] | |
1447 | "" | |
bbbc206e | 1448 | "%0 = -%1 (S)%!" |
75d8b2d0 BS |
1449 | [(set_attr "type" "dsp32")]) |
1450 | ||
0d4a78eb BS |
1451 | (define_insn "one_cmplsi2" |
1452 | [(set (match_operand:SI 0 "register_operand" "=d") | |
75d8b2d0 | 1453 | (not:SI (match_operand:SI 1 "register_operand" "d")))] |
0d4a78eb | 1454 | "" |
75d8b2d0 | 1455 | "%0 = ~%1;" |
0d4a78eb BS |
1456 | [(set_attr "type" "alu0")]) |
1457 | ||
3801c801 BS |
1458 | (define_expand "clrsbsi2" |
1459 | [(set (match_dup 2) | |
e2f00837 | 1460 | (truncate:HI (clrsb:SI (match_operand:SI 1 "register_operand" "d")))) |
3801c801 BS |
1461 | (set (match_operand:SI 0 "register_operand") |
1462 | (zero_extend:SI (match_dup 2)))] | |
1463 | "" | |
1464 | { | |
1465 | operands[2] = gen_reg_rtx (HImode); | |
1466 | }) | |
1467 | ||
75d8b2d0 BS |
1468 | (define_insn "signbitssi2" |
1469 | [(set (match_operand:HI 0 "register_operand" "=d") | |
e2f00837 | 1470 | (truncate:HI (clrsb:SI (match_operand:SI 1 "register_operand" "d"))))] |
75d8b2d0 | 1471 | "" |
bbbc206e | 1472 | "%h0 = signbits %1%!" |
75d8b2d0 BS |
1473 | [(set_attr "type" "dsp32")]) |
1474 | ||
26c5953d BS |
1475 | (define_insn "ssroundsi2" |
1476 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1477 | (truncate:HI | |
1478 | (lshiftrt:SI (ss_plus:SI (match_operand:SI 1 "register_operand" "d") | |
1479 | (const_int 32768)) | |
1480 | (const_int 16))))] | |
1481 | "" | |
1482 | "%h0 = %1 (RND)%!" | |
1483 | [(set_attr "type" "dsp32")]) | |
1484 | ||
75d8b2d0 BS |
1485 | (define_insn "smaxhi3" |
1486 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1487 | (smax:HI (match_operand:HI 1 "register_operand" "d") | |
1488 | (match_operand:HI 2 "register_operand" "d")))] | |
1489 | "" | |
bbbc206e | 1490 | "%0 = max(%1,%2) (V)%!" |
75d8b2d0 BS |
1491 | [(set_attr "type" "dsp32")]) |
1492 | ||
1493 | (define_insn "sminhi3" | |
1494 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1495 | (smin:HI (match_operand:HI 1 "register_operand" "d") | |
1496 | (match_operand:HI 2 "register_operand" "d")))] | |
1497 | "" | |
bbbc206e | 1498 | "%0 = min(%1,%2) (V)%!" |
75d8b2d0 BS |
1499 | [(set_attr "type" "dsp32")]) |
1500 | ||
1501 | (define_insn "abshi2" | |
1502 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1503 | (abs:HI (match_operand:HI 1 "register_operand" "d")))] | |
1504 | "" | |
bbbc206e | 1505 | "%0 = abs %1 (V)%!" |
75d8b2d0 BS |
1506 | [(set_attr "type" "dsp32")]) |
1507 | ||
1508 | (define_insn "neghi2" | |
1509 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1510 | (neg:HI (match_operand:HI 1 "register_operand" "d")))] | |
1511 | "" | |
1512 | "%0 = -%1;" | |
bbbc206e | 1513 | [(set_attr "type" "alu0")]) |
75d8b2d0 BS |
1514 | |
1515 | (define_insn "ssneghi2" | |
1516 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1517 | (ss_neg:HI (match_operand:HI 1 "register_operand" "d")))] | |
1518 | "" | |
bbbc206e | 1519 | "%0 = -%1 (V)%!" |
75d8b2d0 BS |
1520 | [(set_attr "type" "dsp32")]) |
1521 | ||
3801c801 | 1522 | (define_insn "clrsbhi2" |
75d8b2d0 | 1523 | [(set (match_operand:HI 0 "register_operand" "=d") |
3801c801 | 1524 | (clrsb:HI (match_operand:HI 1 "register_operand" "d")))] |
75d8b2d0 | 1525 | "" |
bbbc206e | 1526 | "%h0 = signbits %h1%!" |
75d8b2d0 BS |
1527 | [(set_attr "type" "dsp32")]) |
1528 | ||
0d4a78eb BS |
1529 | (define_insn "mulsi3" |
1530 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1531 | (mult:SI (match_operand:SI 1 "register_operand" "%0") | |
1532 | (match_operand:SI 2 "register_operand" "d")))] | |
1533 | "" | |
75d8b2d0 | 1534 | "%0 *= %2;" |
0d4a78eb BS |
1535 | [(set_attr "type" "mult")]) |
1536 | ||
01e7cd6e | 1537 | (define_expand "umulsi3_highpart" |
3fbee523 BS |
1538 | [(parallel |
1539 | [(set (match_operand:SI 0 "register_operand" "") | |
1540 | (truncate:SI | |
1541 | (lshiftrt:DI | |
1542 | (mult:DI (zero_extend:DI | |
1543 | (match_operand:SI 1 "nonimmediate_operand" "")) | |
1544 | (zero_extend:DI | |
1545 | (match_operand:SI 2 "register_operand" ""))) | |
1546 | (const_int 32)))) | |
1547 | (clobber (reg:PDI REG_A0)) | |
1548 | (clobber (reg:PDI REG_A1))])] | |
01e7cd6e BS |
1549 | "" |
1550 | { | |
3fbee523 BS |
1551 | if (!optimize_size) |
1552 | { | |
1553 | rtx a1reg = gen_rtx_REG (PDImode, REG_A1); | |
1554 | rtx a0reg = gen_rtx_REG (PDImode, REG_A0); | |
1555 | emit_insn (gen_flag_macinit1hi (a1reg, | |
1556 | gen_lowpart (HImode, operands[1]), | |
1557 | gen_lowpart (HImode, operands[2]), | |
1558 | GEN_INT (MACFLAG_FU))); | |
1559 | emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16))); | |
1560 | emit_insn (gen_flag_mul_macv2hi_parts_acconly (a0reg, a1reg, | |
1561 | gen_lowpart (V2HImode, operands[1]), | |
1562 | gen_lowpart (V2HImode, operands[2]), | |
1563 | const1_rtx, const1_rtx, | |
1564 | const1_rtx, const0_rtx, a1reg, | |
1565 | const0_rtx, GEN_INT (MACFLAG_FU), | |
1566 | GEN_INT (MACFLAG_FU))); | |
1567 | emit_insn (gen_flag_machi_parts_acconly (a1reg, | |
1568 | gen_lowpart (V2HImode, operands[2]), | |
1569 | gen_lowpart (V2HImode, operands[1]), | |
1570 | const1_rtx, const0_rtx, | |
1571 | a1reg, const0_rtx, GEN_INT (MACFLAG_FU))); | |
1572 | emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16))); | |
314f9913 BS |
1573 | emit_insn (gen_addpdi3 (a0reg, a0reg, a1reg)); |
1574 | emit_insn (gen_us_truncpdisi2 (operands[0], a0reg)); | |
3fbee523 BS |
1575 | } |
1576 | else | |
1577 | { | |
1578 | rtx umulsi3_highpart_libfunc | |
1579 | = init_one_libfunc ("__umulsi3_highpart"); | |
01e7cd6e | 1580 | |
3fbee523 BS |
1581 | emit_library_call_value (umulsi3_highpart_libfunc, |
1582 | operands[0], LCT_NORMAL, SImode, | |
1583 | 2, operands[1], SImode, operands[2], SImode); | |
1584 | } | |
01e7cd6e BS |
1585 | DONE; |
1586 | }) | |
1587 | ||
1588 | (define_expand "smulsi3_highpart" | |
3fbee523 BS |
1589 | [(parallel |
1590 | [(set (match_operand:SI 0 "register_operand" "") | |
1591 | (truncate:SI | |
1592 | (lshiftrt:DI | |
1593 | (mult:DI (sign_extend:DI | |
1594 | (match_operand:SI 1 "nonimmediate_operand" "")) | |
1595 | (sign_extend:DI | |
1596 | (match_operand:SI 2 "register_operand" ""))) | |
1597 | (const_int 32)))) | |
1598 | (clobber (reg:PDI REG_A0)) | |
1599 | (clobber (reg:PDI REG_A1))])] | |
01e7cd6e BS |
1600 | "" |
1601 | { | |
3fbee523 BS |
1602 | if (!optimize_size) |
1603 | { | |
1604 | rtx a1reg = gen_rtx_REG (PDImode, REG_A1); | |
1605 | rtx a0reg = gen_rtx_REG (PDImode, REG_A0); | |
1606 | emit_insn (gen_flag_macinit1hi (a1reg, | |
1607 | gen_lowpart (HImode, operands[1]), | |
1608 | gen_lowpart (HImode, operands[2]), | |
1609 | GEN_INT (MACFLAG_FU))); | |
1610 | emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16))); | |
1611 | emit_insn (gen_flag_mul_macv2hi_parts_acconly (a0reg, a1reg, | |
1612 | gen_lowpart (V2HImode, operands[1]), | |
1613 | gen_lowpart (V2HImode, operands[2]), | |
1614 | const1_rtx, const1_rtx, | |
1615 | const1_rtx, const0_rtx, a1reg, | |
1616 | const0_rtx, GEN_INT (MACFLAG_IS), | |
1617 | GEN_INT (MACFLAG_IS_M))); | |
1618 | emit_insn (gen_flag_machi_parts_acconly (a1reg, | |
1619 | gen_lowpart (V2HImode, operands[2]), | |
1620 | gen_lowpart (V2HImode, operands[1]), | |
1621 | const1_rtx, const0_rtx, | |
1622 | a1reg, const0_rtx, GEN_INT (MACFLAG_IS_M))); | |
1623 | emit_insn (gen_ashrpdi3 (a1reg, a1reg, GEN_INT (16))); | |
1624 | emit_insn (gen_sum_of_accumulators (operands[0], a0reg, a0reg, a1reg)); | |
1625 | } | |
1626 | else | |
1627 | { | |
1628 | rtx smulsi3_highpart_libfunc | |
1629 | = init_one_libfunc ("__smulsi3_highpart"); | |
01e7cd6e | 1630 | |
3fbee523 BS |
1631 | emit_library_call_value (smulsi3_highpart_libfunc, |
1632 | operands[0], LCT_NORMAL, SImode, | |
1633 | 2, operands[1], SImode, operands[2], SImode); | |
1634 | } | |
01e7cd6e BS |
1635 | DONE; |
1636 | }) | |
1637 | ||
0d4a78eb BS |
1638 | (define_expand "ashlsi3" |
1639 | [(set (match_operand:SI 0 "register_operand" "") | |
1640 | (ashift:SI (match_operand:SI 1 "register_operand" "") | |
1641 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
1642 | "" | |
1643 | { | |
1644 | if (GET_CODE (operands[2]) == CONST_INT | |
1645 | && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) | |
1646 | { | |
1647 | emit_insn (gen_movsi (operands[0], const0_rtx)); | |
1648 | DONE; | |
1649 | } | |
1650 | }) | |
1651 | ||
1652 | (define_insn_and_split "*ashlsi3_insn" | |
bbbc206e BS |
1653 | [(set (match_operand:SI 0 "register_operand" "=d,d,a,a,a") |
1654 | (ashift:SI (match_operand:SI 1 "register_operand" "0,d,a,a,a") | |
1655 | (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5,P1,P2,?P3P4")))] | |
0d4a78eb BS |
1656 | "" |
1657 | "@ | |
1658 | %0 <<= %2; | |
bbbc206e | 1659 | %0 = %1 << %2%! |
0d4a78eb BS |
1660 | %0 = %1 + %1; |
1661 | %0 = %1 << %2; | |
1662 | #" | |
1663 | "PREG_P (operands[0]) && INTVAL (operands[2]) > 2" | |
1664 | [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 2))) | |
1665 | (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))] | |
1666 | "operands[3] = GEN_INT (INTVAL (operands[2]) - 2);" | |
b3187e24 | 1667 | [(set_attr "type" "shft,dsp32shiftimm,shft,shft,*")]) |
0d4a78eb BS |
1668 | |
1669 | (define_insn "ashrsi3" | |
bbbc206e BS |
1670 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
1671 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d") | |
1672 | (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5")))] | |
0d4a78eb | 1673 | "" |
bbbc206e BS |
1674 | "@ |
1675 | %0 >>>= %2; | |
1676 | %0 = %1 >>> %2%!" | |
b3187e24 | 1677 | [(set_attr "type" "shft,dsp32shiftimm")]) |
0d4a78eb | 1678 | |
97130915 BS |
1679 | (define_insn "rotl16" |
1680 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1681 | (rotate:SI (match_operand:SI 1 "register_operand" "d") | |
1682 | (const_int 16)))] | |
1683 | "" | |
1684 | "%0 = PACK (%h1, %d1)%!" | |
1685 | [(set_attr "type" "dsp32")]) | |
1686 | ||
1687 | (define_expand "rotlsi3" | |
1688 | [(set (match_operand:SI 0 "register_operand" "") | |
1689 | (rotate:SI (match_operand:SI 1 "register_operand" "") | |
9f111209 | 1690 | (match_operand:SI 2 "const_int_operand" "")))] |
97130915 BS |
1691 | "" |
1692 | { | |
9f111209 | 1693 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 16) |
97130915 BS |
1694 | FAIL; |
1695 | }) | |
1696 | ||
1697 | (define_expand "rotrsi3" | |
1698 | [(set (match_operand:SI 0 "register_operand" "") | |
1699 | (rotatert:SI (match_operand:SI 1 "register_operand" "") | |
9f111209 | 1700 | (match_operand:SI 2 "const_int_operand" "")))] |
97130915 BS |
1701 | "" |
1702 | { | |
9f111209 | 1703 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 16) |
97130915 BS |
1704 | FAIL; |
1705 | emit_insn (gen_rotl16 (operands[0], operands[1])); | |
1706 | DONE; | |
1707 | }) | |
1708 | ||
1709 | ||
49373252 BS |
1710 | (define_insn "ror_one" |
1711 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1712 | (ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") (const_int 1)) | |
1713 | (ashift:SI (zero_extend:SI (reg:BI REG_CC)) (const_int 31)))) | |
1714 | (set (reg:BI REG_CC) | |
1715 | (zero_extract:BI (match_dup 1) (const_int 1) (const_int 0)))] | |
1716 | "" | |
bbbc206e | 1717 | "%0 = ROT %1 BY -1%!" |
b3187e24 | 1718 | [(set_attr "type" "dsp32shiftimm")]) |
49373252 BS |
1719 | |
1720 | (define_insn "rol_one" | |
1721 | [(set (match_operand:SI 0 "register_operand" "+d") | |
1722 | (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") (const_int 1)) | |
1723 | (zero_extend:SI (reg:BI REG_CC)))) | |
1724 | (set (reg:BI REG_CC) | |
1725 | (zero_extract:BI (match_dup 1) (const_int 31) (const_int 0)))] | |
1726 | "" | |
bbbc206e | 1727 | "%0 = ROT %1 BY 1%!" |
b3187e24 | 1728 | [(set_attr "type" "dsp32shiftimm")]) |
49373252 BS |
1729 | |
1730 | (define_expand "lshrdi3" | |
1731 | [(set (match_operand:DI 0 "register_operand" "") | |
1732 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
1733 | (match_operand:DI 2 "general_operand" "")))] | |
1734 | "" | |
1735 | { | |
1736 | rtx lo_half[2], hi_half[2]; | |
1737 | ||
1738 | if (operands[2] != const1_rtx) | |
1739 | FAIL; | |
1740 | if (! rtx_equal_p (operands[0], operands[1])) | |
1741 | emit_move_insn (operands[0], operands[1]); | |
1742 | ||
1743 | split_di (operands, 2, lo_half, hi_half); | |
1744 | ||
1745 | emit_move_insn (bfin_cc_rtx, const0_rtx); | |
1746 | emit_insn (gen_ror_one (hi_half[0], hi_half[0])); | |
1747 | emit_insn (gen_ror_one (lo_half[0], lo_half[0])); | |
1748 | DONE; | |
1749 | }) | |
1750 | ||
1751 | (define_expand "ashrdi3" | |
1752 | [(set (match_operand:DI 0 "register_operand" "") | |
1753 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
1754 | (match_operand:DI 2 "general_operand" "")))] | |
1755 | "" | |
1756 | { | |
1757 | rtx lo_half[2], hi_half[2]; | |
1758 | ||
1759 | if (operands[2] != const1_rtx) | |
1760 | FAIL; | |
1761 | if (! rtx_equal_p (operands[0], operands[1])) | |
1762 | emit_move_insn (operands[0], operands[1]); | |
1763 | ||
1764 | split_di (operands, 2, lo_half, hi_half); | |
1765 | ||
1766 | emit_insn (gen_compare_lt (gen_rtx_REG (BImode, REG_CC), | |
1767 | hi_half[1], const0_rtx)); | |
1768 | emit_insn (gen_ror_one (hi_half[0], hi_half[0])); | |
1769 | emit_insn (gen_ror_one (lo_half[0], lo_half[0])); | |
1770 | DONE; | |
1771 | }) | |
1772 | ||
1773 | (define_expand "ashldi3" | |
1774 | [(set (match_operand:DI 0 "register_operand" "") | |
1775 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
1776 | (match_operand:DI 2 "general_operand" "")))] | |
1777 | "" | |
1778 | { | |
1779 | rtx lo_half[2], hi_half[2]; | |
1780 | ||
1781 | if (operands[2] != const1_rtx) | |
1782 | FAIL; | |
1783 | if (! rtx_equal_p (operands[0], operands[1])) | |
1784 | emit_move_insn (operands[0], operands[1]); | |
1785 | ||
1786 | split_di (operands, 2, lo_half, hi_half); | |
1787 | ||
1788 | emit_move_insn (bfin_cc_rtx, const0_rtx); | |
1789 | emit_insn (gen_rol_one (lo_half[0], lo_half[0])); | |
1790 | emit_insn (gen_rol_one (hi_half[0], hi_half[0])); | |
1791 | DONE; | |
1792 | }) | |
1793 | ||
0d4a78eb | 1794 | (define_insn "lshrsi3" |
bbbc206e BS |
1795 | [(set (match_operand:SI 0 "register_operand" "=d,d,a") |
1796 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,d,a") | |
1797 | (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5,P1P2")))] | |
0d4a78eb BS |
1798 | "" |
1799 | "@ | |
1800 | %0 >>= %2; | |
bbbc206e | 1801 | %0 = %1 >> %2%! |
0d4a78eb | 1802 | %0 = %1 >> %2;" |
b3187e24 | 1803 | [(set_attr "type" "shft,dsp32shiftimm,shft")]) |
0d4a78eb | 1804 | |
3efd5670 BS |
1805 | (define_insn "lshrpdi3" |
1806 | [(set (match_operand:PDI 0 "register_operand" "=e") | |
1807 | (lshiftrt:PDI (match_operand:PDI 1 "register_operand" "0") | |
1808 | (match_operand:SI 2 "nonmemory_operand" "Ku5")))] | |
1809 | "" | |
1810 | "%0 = %1 >> %2%!" | |
b3187e24 | 1811 | [(set_attr "type" "dsp32shiftimm")]) |
3efd5670 BS |
1812 | |
1813 | (define_insn "ashrpdi3" | |
1814 | [(set (match_operand:PDI 0 "register_operand" "=e") | |
1815 | (ashiftrt:PDI (match_operand:PDI 1 "register_operand" "0") | |
1816 | (match_operand:SI 2 "nonmemory_operand" "Ku5")))] | |
1817 | "" | |
1818 | "%0 = %1 >>> %2%!" | |
b3187e24 | 1819 | [(set_attr "type" "dsp32shiftimm")]) |
3efd5670 | 1820 | |
0d4a78eb BS |
1821 | ;; A pattern to reload the equivalent of |
1822 | ;; (set (Dreg) (plus (FP) (large_constant))) | |
1823 | ;; or | |
1824 | ;; (set (dagreg) (plus (FP) (arbitrary_constant))) | |
1825 | ;; using a scratch register | |
1826 | (define_expand "reload_insi" | |
1827 | [(parallel [(set (match_operand:SI 0 "register_operand" "=w") | |
1828 | (match_operand:SI 1 "fp_plus_const_operand" "")) | |
1829 | (clobber (match_operand:SI 2 "register_operand" "=&a"))])] | |
1830 | "" | |
1831 | { | |
1832 | rtx fp_op = XEXP (operands[1], 0); | |
1833 | rtx const_op = XEXP (operands[1], 1); | |
1834 | rtx primary = operands[0]; | |
1835 | rtx scratch = operands[2]; | |
1836 | ||
1837 | emit_move_insn (scratch, const_op); | |
1838 | emit_insn (gen_addsi3 (scratch, scratch, fp_op)); | |
1839 | emit_move_insn (primary, scratch); | |
1840 | DONE; | |
1841 | }) | |
1842 | ||
6c1c1dfa BS |
1843 | (define_mode_iterator AREG [PDI V2PDI]) |
1844 | ||
1845 | (define_insn "reload_in<mode>" | |
1846 | [(set (match_operand:AREG 0 "register_operand" "=e") | |
1847 | (match_operand:AREG 1 "memory_operand" "m")) | |
6ed44ca1 BS |
1848 | (clobber (match_operand:SI 2 "register_operand" "=d"))] |
1849 | "" | |
1850 | { | |
1851 | rtx xops[4]; | |
1852 | xops[0] = operands[0]; | |
1853 | xops[1] = operands[2]; | |
1854 | split_di (operands + 1, 1, xops + 2, xops + 3); | |
1855 | output_asm_insn ("%1 = %2;", xops); | |
1856 | output_asm_insn ("%w0 = %1;", xops); | |
1857 | output_asm_insn ("%1 = %3;", xops); | |
1858 | output_asm_insn ("%x0 = %1;", xops); | |
1859 | return ""; | |
1860 | } | |
1861 | [(set_attr "seq_insns" "multi") | |
1862 | (set_attr "type" "mcld") | |
1863 | (set_attr "length" "12")]) | |
1864 | ||
6c1c1dfa BS |
1865 | (define_insn "reload_out<mode>" |
1866 | [(set (match_operand:AREG 0 "memory_operand" "=m") | |
1867 | (match_operand:AREG 1 "register_operand" "e")) | |
6ed44ca1 BS |
1868 | (clobber (match_operand:SI 2 "register_operand" "=d"))] |
1869 | "" | |
1870 | { | |
1871 | rtx xops[4]; | |
1872 | xops[0] = operands[1]; | |
1873 | xops[1] = operands[2]; | |
1874 | split_di (operands, 1, xops + 2, xops + 3); | |
1875 | output_asm_insn ("%1 = %w0;", xops); | |
1876 | output_asm_insn ("%2 = %1;", xops); | |
1877 | output_asm_insn ("%1 = %x0;", xops); | |
1878 | output_asm_insn ("%3 = %1;", xops); | |
1879 | return ""; | |
1880 | } | |
1881 | [(set_attr "seq_insns" "multi") | |
1882 | (set_attr "type" "mcld") | |
1883 | (set_attr "length" "12")]) | |
1884 | ||
0d4a78eb BS |
1885 | ;; Jump instructions |
1886 | ||
1887 | (define_insn "jump" | |
1888 | [(set (pc) | |
1889 | (label_ref (match_operand 0 "" "")))] | |
1890 | "" | |
1891 | { | |
1892 | if (get_attr_length (insn) == 2) | |
1893 | return "jump.s %0;"; | |
1894 | else | |
1895 | return "jump.l %0;"; | |
1896 | } | |
1897 | [(set_attr "type" "br")]) | |
1898 | ||
1899 | (define_insn "indirect_jump" | |
1900 | [(set (pc) | |
1901 | (match_operand:SI 0 "register_operand" "a"))] | |
1902 | "" | |
1903 | "jump (%0);" | |
1904 | [(set_attr "type" "misc")]) | |
1905 | ||
1906 | (define_expand "tablejump" | |
1907 | [(parallel [(set (pc) (match_operand:SI 0 "register_operand" "a")) | |
1908 | (use (label_ref (match_operand 1 "" "")))])] | |
1909 | "" | |
1910 | { | |
1911 | /* In PIC mode, the table entries are stored PC relative. | |
1912 | Convert the relative address to an absolute address. */ | |
1913 | if (flag_pic) | |
1914 | { | |
1915 | rtx op1 = gen_rtx_LABEL_REF (Pmode, operands[1]); | |
1916 | ||
1917 | operands[0] = expand_simple_binop (Pmode, PLUS, operands[0], | |
1918 | op1, NULL_RTX, 0, OPTAB_DIRECT); | |
1919 | } | |
1920 | }) | |
1921 | ||
1922 | (define_insn "*tablejump_internal" | |
1923 | [(set (pc) (match_operand:SI 0 "register_operand" "a")) | |
1924 | (use (label_ref (match_operand 1 "" "")))] | |
1925 | "" | |
1926 | "jump (%0);" | |
1927 | [(set_attr "type" "misc")]) | |
1928 | ||
b03149e1 JZ |
1929 | ;; Hardware loop |
1930 | ||
1931 | ; operand 0 is the loop count pseudo register | |
1932 | ; operand 1 is the number of loop iterations or 0 if it is unknown | |
1933 | ; operand 2 is the maximum number of loop iterations | |
1934 | ; operand 3 is the number of levels of enclosed loops | |
1935 | ; operand 4 is the label to jump to at the top of the loop | |
2407343c | 1936 | ; operand 5 indicates if the loop is entered at the top |
b03149e1 JZ |
1937 | (define_expand "doloop_end" |
1938 | [(parallel [(set (pc) (if_then_else | |
1939 | (ne (match_operand:SI 0 "" "") | |
1940 | (const_int 1)) | |
1941 | (label_ref (match_operand 4 "" "")) | |
1942 | (pc))) | |
1943 | (set (match_dup 0) | |
1944 | (plus:SI (match_dup 0) | |
1945 | (const_int -1))) | |
1946 | (unspec [(const_int 0)] UNSPEC_LSETUP_END) | |
2407343c | 1947 | (clobber (match_operand 5 ""))])] ; match_scratch |
b03149e1 | 1948 | "" |
0a8f8c45 | 1949 | { |
9b02a95e BS |
1950 | /* The loop optimizer doesn't check the predicates... */ |
1951 | if (GET_MODE (operands[0]) != SImode) | |
1952 | FAIL; | |
0a8f8c45 BS |
1953 | /* Due to limitations in the hardware (an initial loop count of 0 |
1954 | does not loop 2^32 times) we must avoid to generate a hardware | |
1955 | loops when we cannot rule out this case. */ | |
0a8f8c45 BS |
1956 | if (!flag_unsafe_loop_optimizations |
1957 | && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 0xFFFFFFFF) | |
1958 | FAIL; | |
1959 | bfin_hardware_loop (); | |
2407343c | 1960 | operands[5] = gen_rtx_SCRATCH (SImode); |
0a8f8c45 | 1961 | }) |
b03149e1 JZ |
1962 | |
1963 | (define_insn "loop_end" | |
1964 | [(set (pc) | |
36019c19 | 1965 | (if_then_else (ne (match_operand:SI 2 "nonimmediate_operand" "0,0,0") |
b03149e1 JZ |
1966 | (const_int 1)) |
1967 | (label_ref (match_operand 1 "" "")) | |
1968 | (pc))) | |
36019c19 SH |
1969 | (set (match_operand:SI 0 "nonimmediate_operand" "=a*d,*b*v*f,m") |
1970 | (plus (match_dup 2) | |
b03149e1 JZ |
1971 | (const_int -1))) |
1972 | (unspec [(const_int 0)] UNSPEC_LSETUP_END) | |
36019c19 | 1973 | (clobber (match_scratch:SI 3 "=X,&r,&r"))] |
b03149e1 JZ |
1974 | "" |
1975 | "@ | |
1976 | /* loop end %0 %l1 */ | |
1977 | # | |
1978 | #" | |
1979 | [(set_attr "length" "6,10,14")]) | |
1980 | ||
1981 | (define_split | |
1982 | [(set (pc) | |
1983 | (if_then_else (ne (match_operand:SI 0 "nondp_reg_or_memory_operand" "") | |
1984 | (const_int 1)) | |
1985 | (label_ref (match_operand 1 "" "")) | |
1986 | (pc))) | |
1987 | (set (match_dup 0) | |
1988 | (plus (match_dup 0) | |
1989 | (const_int -1))) | |
1990 | (unspec [(const_int 0)] UNSPEC_LSETUP_END) | |
1991 | (clobber (match_scratch:SI 2 "=&r"))] | |
9d9c740d | 1992 | "memory_operand (operands[0], SImode) || splitting_loops" |
b03149e1 JZ |
1993 | [(set (match_dup 2) (match_dup 0)) |
1994 | (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
1995 | (set (match_dup 0) (match_dup 2)) | |
1996 | (set (reg:BI REG_CC) (eq:BI (match_dup 2) (const_int 0))) | |
1997 | (set (pc) | |
1998 | (if_then_else (eq (reg:BI REG_CC) | |
1999 | (const_int 0)) | |
2000 | (label_ref (match_dup 1)) | |
2001 | (pc)))] | |
2002 | "") | |
2003 | ||
2004 | (define_insn "lsetup_with_autoinit" | |
2005 | [(set (match_operand:SI 0 "lt_register_operand" "=t") | |
2006 | (label_ref (match_operand 1 "" ""))) | |
a9c46998 | 2007 | (set (match_operand:SI 2 "lb_register_operand" "=u") |
b03149e1 JZ |
2008 | (label_ref (match_operand 3 "" ""))) |
2009 | (set (match_operand:SI 4 "lc_register_operand" "=k") | |
2010 | (match_operand:SI 5 "register_operand" "a"))] | |
2011 | "" | |
2012 | "LSETUP (%1, %3) %4 = %5;" | |
2013 | [(set_attr "length" "4")]) | |
2014 | ||
2015 | (define_insn "lsetup_without_autoinit" | |
2016 | [(set (match_operand:SI 0 "lt_register_operand" "=t") | |
2017 | (label_ref (match_operand 1 "" ""))) | |
a9c46998 | 2018 | (set (match_operand:SI 2 "lb_register_operand" "=u") |
b03149e1 JZ |
2019 | (label_ref (match_operand 3 "" ""))) |
2020 | (use (match_operand:SI 4 "lc_register_operand" "k"))] | |
2021 | "" | |
2022 | "LSETUP (%1, %3) %4;" | |
2023 | [(set_attr "length" "4")]) | |
2024 | ||
0d4a78eb BS |
2025 | ;; Call instructions.. |
2026 | ||
6614f9f5 BS |
2027 | ;; The explicit MEM inside the UNSPEC prevents the compiler from moving |
2028 | ;; the load before a branch after a NULL test, or before a store that | |
2029 | ;; initializes a function descriptor. | |
2030 | ||
2031 | (define_insn_and_split "load_funcdescsi" | |
2032 | [(set (match_operand:SI 0 "register_operand" "=a") | |
2033 | (unspec_volatile:SI [(mem:SI (match_operand:SI 1 "address_operand" "p"))] | |
2034 | UNSPEC_VOLATILE_LOAD_FUNCDESC))] | |
2035 | "" | |
2036 | "#" | |
2037 | "reload_completed" | |
2038 | [(set (match_dup 0) (mem:SI (match_dup 1)))]) | |
2039 | ||
0d4a78eb | 2040 | (define_expand "call" |
6d459e2b BS |
2041 | [(parallel [(call (match_operand:SI 0 "" "") |
2042 | (match_operand 1 "" "")) | |
2043 | (use (match_operand 2 "" ""))])] | |
0d4a78eb | 2044 | "" |
6d459e2b BS |
2045 | { |
2046 | bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 0); | |
2047 | DONE; | |
2048 | }) | |
0d4a78eb BS |
2049 | |
2050 | (define_expand "sibcall" | |
2051 | [(parallel [(call (match_operand:SI 0 "" "") | |
2052 | (match_operand 1 "" "")) | |
6d459e2b | 2053 | (use (match_operand 2 "" "")) |
0d4a78eb BS |
2054 | (return)])] |
2055 | "" | |
6d459e2b BS |
2056 | { |
2057 | bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 1); | |
2058 | DONE; | |
2059 | }) | |
0d4a78eb BS |
2060 | |
2061 | (define_expand "call_value" | |
6d459e2b BS |
2062 | [(parallel [(set (match_operand 0 "register_operand" "") |
2063 | (call (match_operand:SI 1 "" "") | |
2064 | (match_operand 2 "" ""))) | |
2065 | (use (match_operand 3 "" ""))])] | |
0d4a78eb | 2066 | "" |
6d459e2b BS |
2067 | { |
2068 | bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 0); | |
2069 | DONE; | |
2070 | }) | |
0d4a78eb BS |
2071 | |
2072 | (define_expand "sibcall_value" | |
2073 | [(parallel [(set (match_operand 0 "register_operand" "") | |
2074 | (call (match_operand:SI 1 "" "") | |
2075 | (match_operand 2 "" ""))) | |
6d459e2b | 2076 | (use (match_operand 3 "" "")) |
0d4a78eb BS |
2077 | (return)])] |
2078 | "" | |
6d459e2b BS |
2079 | { |
2080 | bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 1); | |
2081 | DONE; | |
2082 | }) | |
0d4a78eb | 2083 | |
6614f9f5 BS |
2084 | (define_insn "*call_symbol_fdpic" |
2085 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q")) | |
2086 | (match_operand 1 "general_operand" "g")) | |
2087 | (use (match_operand:SI 2 "register_operand" "Z")) | |
9840d30a BS |
2088 | (use (match_operand 3 "" "")) |
2089 | (clobber (reg:SI REG_RETS))] | |
6614f9f5 BS |
2090 | "! SIBLING_CALL_P (insn) |
2091 | && GET_CODE (operands[0]) == SYMBOL_REF | |
2092 | && !bfin_longcall_p (operands[0], INTVAL (operands[3]))" | |
2093 | "call %0;" | |
2094 | [(set_attr "type" "call") | |
2095 | (set_attr "length" "4")]) | |
2096 | ||
2097 | (define_insn "*sibcall_symbol_fdpic" | |
2098 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q")) | |
2099 | (match_operand 1 "general_operand" "g")) | |
2100 | (use (match_operand:SI 2 "register_operand" "Z")) | |
2101 | (use (match_operand 3 "" "")) | |
2102 | (return)] | |
2103 | "SIBLING_CALL_P (insn) | |
2104 | && GET_CODE (operands[0]) == SYMBOL_REF | |
2105 | && !bfin_longcall_p (operands[0], INTVAL (operands[3]))" | |
2106 | "jump.l %0;" | |
2107 | [(set_attr "type" "br") | |
2108 | (set_attr "length" "4")]) | |
2109 | ||
2110 | (define_insn "*call_value_symbol_fdpic" | |
2111 | [(set (match_operand 0 "register_operand" "=d") | |
2112 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q")) | |
2113 | (match_operand 2 "general_operand" "g"))) | |
2114 | (use (match_operand:SI 3 "register_operand" "Z")) | |
9840d30a BS |
2115 | (use (match_operand 4 "" "")) |
2116 | (clobber (reg:SI REG_RETS))] | |
6614f9f5 BS |
2117 | "! SIBLING_CALL_P (insn) |
2118 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2119 | && !bfin_longcall_p (operands[1], INTVAL (operands[4]))" | |
2120 | "call %1;" | |
2121 | [(set_attr "type" "call") | |
2122 | (set_attr "length" "4")]) | |
2123 | ||
2124 | (define_insn "*sibcall_value_symbol_fdpic" | |
2125 | [(set (match_operand 0 "register_operand" "=d") | |
2126 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q")) | |
2127 | (match_operand 2 "general_operand" "g"))) | |
2128 | (use (match_operand:SI 3 "register_operand" "Z")) | |
2129 | (use (match_operand 4 "" "")) | |
2130 | (return)] | |
2131 | "SIBLING_CALL_P (insn) | |
2132 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2133 | && !bfin_longcall_p (operands[1], INTVAL (operands[4]))" | |
2134 | "jump.l %1;" | |
2135 | [(set_attr "type" "br") | |
2136 | (set_attr "length" "4")]) | |
2137 | ||
2138 | (define_insn "*call_insn_fdpic" | |
2139 | [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y")) | |
2140 | (match_operand 1 "general_operand" "g")) | |
2141 | (use (match_operand:SI 2 "register_operand" "Z")) | |
9840d30a BS |
2142 | (use (match_operand 3 "" "")) |
2143 | (clobber (reg:SI REG_RETS))] | |
6614f9f5 BS |
2144 | "! SIBLING_CALL_P (insn)" |
2145 | "call (%0);" | |
2146 | [(set_attr "type" "call") | |
2147 | (set_attr "length" "2")]) | |
2148 | ||
2149 | (define_insn "*sibcall_insn_fdpic" | |
2150 | [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y")) | |
2151 | (match_operand 1 "general_operand" "g")) | |
2152 | (use (match_operand:SI 2 "register_operand" "Z")) | |
2153 | (use (match_operand 3 "" "")) | |
2154 | (return)] | |
2155 | "SIBLING_CALL_P (insn)" | |
2156 | "jump (%0);" | |
2157 | [(set_attr "type" "br") | |
2158 | (set_attr "length" "2")]) | |
2159 | ||
2160 | (define_insn "*call_value_insn_fdpic" | |
2161 | [(set (match_operand 0 "register_operand" "=d") | |
2162 | (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y")) | |
2163 | (match_operand 2 "general_operand" "g"))) | |
2164 | (use (match_operand:SI 3 "register_operand" "Z")) | |
9840d30a BS |
2165 | (use (match_operand 4 "" "")) |
2166 | (clobber (reg:SI REG_RETS))] | |
6614f9f5 BS |
2167 | "! SIBLING_CALL_P (insn)" |
2168 | "call (%1);" | |
2169 | [(set_attr "type" "call") | |
2170 | (set_attr "length" "2")]) | |
2171 | ||
2172 | (define_insn "*sibcall_value_insn_fdpic" | |
2173 | [(set (match_operand 0 "register_operand" "=d") | |
2174 | (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y")) | |
2175 | (match_operand 2 "general_operand" "g"))) | |
2176 | (use (match_operand:SI 3 "register_operand" "Z")) | |
2177 | (use (match_operand 4 "" "")) | |
2178 | (return)] | |
2179 | "SIBLING_CALL_P (insn)" | |
2180 | "jump (%1);" | |
2181 | [(set_attr "type" "br") | |
2182 | (set_attr "length" "2")]) | |
2183 | ||
6d459e2b BS |
2184 | (define_insn "*call_symbol" |
2185 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q")) | |
2186 | (match_operand 1 "general_operand" "g")) | |
9840d30a BS |
2187 | (use (match_operand 2 "" "")) |
2188 | (clobber (reg:SI REG_RETS))] | |
0d4a78eb | 2189 | "! SIBLING_CALL_P (insn) |
93147119 | 2190 | && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY) |
6d459e2b BS |
2191 | && GET_CODE (operands[0]) == SYMBOL_REF |
2192 | && !bfin_longcall_p (operands[0], INTVAL (operands[2]))" | |
96c30d2a | 2193 | "call %0;" |
0d4a78eb | 2194 | [(set_attr "type" "call") |
6d459e2b | 2195 | (set_attr "length" "4")]) |
0d4a78eb | 2196 | |
6d459e2b BS |
2197 | (define_insn "*sibcall_symbol" |
2198 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q")) | |
2199 | (match_operand 1 "general_operand" "g")) | |
2200 | (use (match_operand 2 "" "")) | |
0d4a78eb BS |
2201 | (return)] |
2202 | "SIBLING_CALL_P (insn) | |
93147119 | 2203 | && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY) |
6d459e2b BS |
2204 | && GET_CODE (operands[0]) == SYMBOL_REF |
2205 | && !bfin_longcall_p (operands[0], INTVAL (operands[2]))" | |
96c30d2a | 2206 | "jump.l %0;" |
0d4a78eb | 2207 | [(set_attr "type" "br") |
6d459e2b | 2208 | (set_attr "length" "4")]) |
0d4a78eb | 2209 | |
6d459e2b BS |
2210 | (define_insn "*call_value_symbol" |
2211 | [(set (match_operand 0 "register_operand" "=d") | |
2212 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q")) | |
2213 | (match_operand 2 "general_operand" "g"))) | |
9840d30a BS |
2214 | (use (match_operand 3 "" "")) |
2215 | (clobber (reg:SI REG_RETS))] | |
0d4a78eb | 2216 | "! SIBLING_CALL_P (insn) |
93147119 | 2217 | && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY) |
6d459e2b BS |
2218 | && GET_CODE (operands[1]) == SYMBOL_REF |
2219 | && !bfin_longcall_p (operands[1], INTVAL (operands[3]))" | |
96c30d2a | 2220 | "call %1;" |
0d4a78eb | 2221 | [(set_attr "type" "call") |
6d459e2b | 2222 | (set_attr "length" "4")]) |
0d4a78eb | 2223 | |
6d459e2b BS |
2224 | (define_insn "*sibcall_value_symbol" |
2225 | [(set (match_operand 0 "register_operand" "=d") | |
2226 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q")) | |
2227 | (match_operand 2 "general_operand" "g"))) | |
2228 | (use (match_operand 3 "" "")) | |
0d4a78eb BS |
2229 | (return)] |
2230 | "SIBLING_CALL_P (insn) | |
93147119 | 2231 | && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY) |
6d459e2b BS |
2232 | && GET_CODE (operands[1]) == SYMBOL_REF |
2233 | && !bfin_longcall_p (operands[1], INTVAL (operands[3]))" | |
96c30d2a | 2234 | "jump.l %1;" |
6d459e2b BS |
2235 | [(set_attr "type" "br") |
2236 | (set_attr "length" "4")]) | |
2237 | ||
2238 | (define_insn "*call_insn" | |
2239 | [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "a")) | |
2240 | (match_operand 1 "general_operand" "g")) | |
9840d30a BS |
2241 | (use (match_operand 2 "" "")) |
2242 | (clobber (reg:SI REG_RETS))] | |
6d459e2b BS |
2243 | "! SIBLING_CALL_P (insn)" |
2244 | "call (%0);" | |
2245 | [(set_attr "type" "call") | |
2246 | (set_attr "length" "2")]) | |
2247 | ||
2248 | (define_insn "*sibcall_insn" | |
2249 | [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "z")) | |
2250 | (match_operand 1 "general_operand" "g")) | |
2251 | (use (match_operand 2 "" "")) | |
2252 | (return)] | |
2253 | "SIBLING_CALL_P (insn)" | |
2254 | "jump (%0);" | |
2255 | [(set_attr "type" "br") | |
2256 | (set_attr "length" "2")]) | |
2257 | ||
2258 | (define_insn "*call_value_insn" | |
2259 | [(set (match_operand 0 "register_operand" "=d") | |
2260 | (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "a")) | |
2261 | (match_operand 2 "general_operand" "g"))) | |
9840d30a BS |
2262 | (use (match_operand 3 "" "")) |
2263 | (clobber (reg:SI REG_RETS))] | |
6d459e2b BS |
2264 | "! SIBLING_CALL_P (insn)" |
2265 | "call (%1);" | |
2266 | [(set_attr "type" "call") | |
2267 | (set_attr "length" "2")]) | |
2268 | ||
2269 | (define_insn "*sibcall_value_insn" | |
2270 | [(set (match_operand 0 "register_operand" "=d") | |
2271 | (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "z")) | |
2272 | (match_operand 2 "general_operand" "g"))) | |
2273 | (use (match_operand 3 "" "")) | |
2274 | (return)] | |
2275 | "SIBLING_CALL_P (insn)" | |
2276 | "jump (%1);" | |
0d4a78eb | 2277 | [(set_attr "type" "br") |
6d459e2b | 2278 | (set_attr "length" "2")]) |
0d4a78eb BS |
2279 | |
2280 | ;; Block move patterns | |
2281 | ||
2282 | ;; We cheat. This copies one more word than operand 2 indicates. | |
2283 | ||
2284 | (define_insn "rep_movsi" | |
2285 | [(set (match_operand:SI 0 "register_operand" "=&a") | |
2286 | (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0") | |
2287 | (ashift:SI (match_operand:SI 2 "register_operand" "a") | |
2288 | (const_int 2))) | |
2289 | (const_int 4))) | |
2290 | (set (match_operand:SI 1 "register_operand" "=&b") | |
2291 | (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1") | |
2292 | (ashift:SI (match_dup 2) (const_int 2))) | |
2293 | (const_int 4))) | |
2294 | (set (mem:BLK (match_dup 3)) | |
2295 | (mem:BLK (match_dup 4))) | |
2296 | (use (match_dup 2)) | |
b03149e1 JZ |
2297 | (clobber (match_scratch:HI 5 "=&d")) |
2298 | (clobber (reg:SI REG_LT1)) | |
2299 | (clobber (reg:SI REG_LC1)) | |
2300 | (clobber (reg:SI REG_LB1))] | |
0d4a78eb | 2301 | "" |
51a641fd | 2302 | "%5 = [%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || [%3++] = %5 || %5 = [%4++]; [%3++] = %5;" |
0d4a78eb | 2303 | [(set_attr "type" "misc") |
b03149e1 JZ |
2304 | (set_attr "length" "16") |
2305 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
2306 | |
2307 | (define_insn "rep_movhi" | |
2308 | [(set (match_operand:SI 0 "register_operand" "=&a") | |
2309 | (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0") | |
2310 | (ashift:SI (match_operand:SI 2 "register_operand" "a") | |
2311 | (const_int 1))) | |
2312 | (const_int 2))) | |
2313 | (set (match_operand:SI 1 "register_operand" "=&b") | |
2314 | (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1") | |
2315 | (ashift:SI (match_dup 2) (const_int 1))) | |
2316 | (const_int 2))) | |
2317 | (set (mem:BLK (match_dup 3)) | |
2318 | (mem:BLK (match_dup 4))) | |
2319 | (use (match_dup 2)) | |
b03149e1 JZ |
2320 | (clobber (match_scratch:HI 5 "=&d")) |
2321 | (clobber (reg:SI REG_LT1)) | |
2322 | (clobber (reg:SI REG_LC1)) | |
2323 | (clobber (reg:SI REG_LB1))] | |
0d4a78eb | 2324 | "" |
51a641fd | 2325 | "%h5 = W[%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || W [%3++] = %5 || %h5 = W [%4++]; W [%3++] = %5;" |
0d4a78eb | 2326 | [(set_attr "type" "misc") |
b03149e1 JZ |
2327 | (set_attr "length" "16") |
2328 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb | 2329 | |
144f8315 | 2330 | (define_expand "movmemsi" |
0d4a78eb BS |
2331 | [(match_operand:BLK 0 "general_operand" "") |
2332 | (match_operand:BLK 1 "general_operand" "") | |
2333 | (match_operand:SI 2 "const_int_operand" "") | |
2334 | (match_operand:SI 3 "const_int_operand" "")] | |
2335 | "" | |
2336 | { | |
144f8315 | 2337 | if (bfin_expand_movmem (operands[0], operands[1], operands[2], operands[3])) |
0d4a78eb BS |
2338 | DONE; |
2339 | FAIL; | |
2340 | }) | |
2341 | ||
2342 | ;; Conditional branch patterns | |
2343 | ;; The Blackfin has only few condition codes: eq, lt, lte, ltu, leu | |
2344 | ||
49373252 | 2345 | (define_insn "compare_eq" |
4729dc92 | 2346 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2347 | (eq:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2348 | (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] |
0d4a78eb BS |
2349 | "" |
2350 | "cc =%1==%2;" | |
2351 | [(set_attr "type" "compare")]) | |
2352 | ||
49373252 | 2353 | (define_insn "compare_ne" |
4729dc92 | 2354 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2355 | (ne:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2356 | (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] |
0d4a78eb BS |
2357 | "0" |
2358 | "cc =%1!=%2;" | |
2359 | [(set_attr "type" "compare")]) | |
2360 | ||
49373252 | 2361 | (define_insn "compare_lt" |
4729dc92 | 2362 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2363 | (lt:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2364 | (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] |
0d4a78eb BS |
2365 | "" |
2366 | "cc =%1<%2;" | |
2367 | [(set_attr "type" "compare")]) | |
2368 | ||
49373252 | 2369 | (define_insn "compare_le" |
4729dc92 | 2370 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2371 | (le:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2372 | (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] |
0d4a78eb BS |
2373 | "" |
2374 | "cc =%1<=%2;" | |
2375 | [(set_attr "type" "compare")]) | |
2376 | ||
49373252 | 2377 | (define_insn "compare_leu" |
4729dc92 | 2378 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2379 | (leu:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2380 | (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))] |
0d4a78eb BS |
2381 | "" |
2382 | "cc =%1<=%2 (iu);" | |
2383 | [(set_attr "type" "compare")]) | |
2384 | ||
49373252 | 2385 | (define_insn "compare_ltu" |
4729dc92 | 2386 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2387 | (ltu:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2388 | (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))] |
0d4a78eb BS |
2389 | "" |
2390 | "cc =%1<%2 (iu);" | |
2391 | [(set_attr "type" "compare")]) | |
2392 | ||
26c5953d BS |
2393 | ;; Same as above, but and CC with the overflow bit generated by the first |
2394 | ;; multiplication. | |
2395 | (define_insn "flag_mul_macv2hi_parts_acconly_andcc0" | |
2396 | [(set (match_operand:PDI 0 "register_operand" "=B,e,e") | |
2397 | (unspec:PDI [(vec_select:HI | |
2398 | (match_operand:V2HI 2 "register_operand" "d,d,d") | |
2399 | (parallel [(match_operand 4 "const01_operand" "P0P1,P0P1,P0P1")])) | |
2400 | (vec_select:HI | |
2401 | (match_operand:V2HI 3 "register_operand" "d,d,d") | |
2402 | (parallel [(match_operand 6 "const01_operand" "P0P1,P0P1,P0P1")])) | |
2403 | (match_operand 10 "const_int_operand" "PB,PA,PA")] | |
2404 | UNSPEC_MUL_WITH_FLAG)) | |
2405 | (set (match_operand:PDI 1 "register_operand" "=B,e,e") | |
2406 | (unspec:PDI [(vec_select:HI | |
2407 | (match_dup 2) | |
2408 | (parallel [(match_operand 5 "const01_operand" "P0P1,P0P1,P0P1")])) | |
2409 | (vec_select:HI | |
2410 | (match_dup 3) | |
2411 | (parallel [(match_operand 7 "const01_operand" "P0P1,P0P1,P0P1")])) | |
2412 | (match_operand:PDI 8 "register_operand" "1,1,1") | |
2413 | (match_operand 9 "const01_operand" "P0P1,P0P1,P0P1") | |
2414 | (match_operand 11 "const_int_operand" "PA,PB,PA")] | |
2415 | UNSPEC_MAC_WITH_FLAG)) | |
2416 | (set (reg:BI REG_CC) | |
2417 | (and:BI (reg:BI REG_CC) | |
2418 | (unspec:BI [(vec_select:HI (match_dup 2) (parallel [(match_dup 4)])) | |
2419 | (vec_select:HI (match_dup 3) (parallel [(match_dup 6)])) | |
2420 | (match_dup 10)] | |
2421 | UNSPEC_MUL_WITH_FLAG)))] | |
2422 | "MACFLAGS_MATCH_P (INTVAL (operands[10]), INTVAL (operands[11]))" | |
2423 | { | |
2424 | rtx xops[6]; | |
2425 | const char *templates[] = { | |
2426 | "%0 = %h2 * %h3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;", | |
2427 | "%0 = %d2 * %h3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;", | |
2428 | "%0 = %h2 * %h3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;", | |
2429 | "%0 = %d2 * %h3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;", | |
2430 | "%0 = %h2 * %d3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;", | |
2431 | "%0 = %d2 * %d3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;", | |
2432 | "%0 = %h2 * %d3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;", | |
2433 | "%0 = %d2 * %d3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;", | |
2434 | "%0 = %h2 * %h3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;", | |
2435 | "%0 = %d2 * %h3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;", | |
2436 | "%0 = %h2 * %h3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;", | |
2437 | "%0 = %d2 * %h3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;", | |
2438 | "%0 = %h2 * %d3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;", | |
2439 | "%0 = %d2 * %d3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;", | |
2440 | "%0 = %h2 * %d3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;", | |
2441 | "%0 = %d2 * %d3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;" }; | |
2442 | int alt = (INTVAL (operands[4]) + (INTVAL (operands[5]) << 1) | |
2443 | + (INTVAL (operands[6]) << 2) + (INTVAL (operands[7]) << 3)); | |
2444 | xops[0] = operands[0]; | |
2445 | xops[1] = operands[1]; | |
2446 | xops[2] = operands[2]; | |
2447 | xops[3] = operands[3]; | |
2448 | xops[4] = operands[9]; | |
2449 | xops[5] = which_alternative == 0 ? operands[10] : operands[11]; | |
2450 | output_asm_insn (templates[alt], xops); | |
2451 | return ""; | |
2452 | } | |
2453 | [(set_attr "type" "misc") | |
2454 | (set_attr "length" "6") | |
2455 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb | 2456 | |
f90b7a5a PB |
2457 | (define_expand "cbranchsi4" |
2458 | [(set (pc) | |
2459 | (if_then_else (match_operator 0 "ordered_comparison_operator" | |
2460 | [(match_operand:SI 1 "register_operand" "") | |
2461 | (match_operand:SI 2 "reg_or_const_int_operand" "")]) | |
2462 | (label_ref (match_operand 3 "" "")) | |
2463 | (pc)))] | |
0d4a78eb BS |
2464 | "" |
2465 | { | |
f90b7a5a PB |
2466 | rtx bi_compare = bfin_gen_compare (operands[0], SImode); |
2467 | emit_jump_insn (gen_cbranchbi4 (bi_compare, bfin_cc_rtx, CONST0_RTX (BImode), | |
2468 | operands[3])); | |
2469 | DONE; | |
0d4a78eb BS |
2470 | }) |
2471 | ||
2472 | (define_insn "cbranchbi4" | |
2473 | [(set (pc) | |
2474 | (if_then_else | |
f90b7a5a | 2475 | (match_operator 0 "bfin_bimode_comparison_operator" |
4729dc92 | 2476 | [(match_operand:BI 1 "register_operand" "C") |
0d4a78eb BS |
2477 | (match_operand:BI 2 "immediate_operand" "P0")]) |
2478 | (label_ref (match_operand 3 "" "")) | |
2479 | (pc)))] | |
2480 | "" | |
2481 | { | |
2482 | asm_conditional_branch (insn, operands, 0, 0); | |
2483 | return ""; | |
2484 | } | |
2485 | [(set_attr "type" "brcc")]) | |
2486 | ||
2487 | ;; Special cbranch patterns to deal with the speculative load problem - see | |
2488 | ;; bfin_reorg for details. | |
2489 | ||
2490 | (define_insn "cbranch_predicted_taken" | |
2491 | [(set (pc) | |
2492 | (if_then_else | |
f90b7a5a | 2493 | (match_operator 0 "bfin_bimode_comparison_operator" |
4729dc92 | 2494 | [(match_operand:BI 1 "register_operand" "C") |
0d4a78eb BS |
2495 | (match_operand:BI 2 "immediate_operand" "P0")]) |
2496 | (label_ref (match_operand 3 "" "")) | |
2497 | (pc))) | |
2498 | (unspec [(const_int 0)] UNSPEC_CBRANCH_TAKEN)] | |
2499 | "" | |
2500 | { | |
2501 | asm_conditional_branch (insn, operands, 0, 1); | |
2502 | return ""; | |
2503 | } | |
2504 | [(set_attr "type" "brcc")]) | |
2505 | ||
2506 | (define_insn "cbranch_with_nops" | |
2507 | [(set (pc) | |
2508 | (if_then_else | |
f90b7a5a | 2509 | (match_operator 0 "bfin_bimode_comparison_operator" |
4729dc92 | 2510 | [(match_operand:BI 1 "register_operand" "C") |
0d4a78eb BS |
2511 | (match_operand:BI 2 "immediate_operand" "P0")]) |
2512 | (label_ref (match_operand 3 "" "")) | |
2513 | (pc))) | |
2514 | (unspec [(match_operand 4 "immediate_operand" "")] UNSPEC_CBRANCH_NOPS)] | |
2515 | "reload_completed" | |
2516 | { | |
2517 | asm_conditional_branch (insn, operands, INTVAL (operands[4]), 0); | |
2518 | return ""; | |
2519 | } | |
2520 | [(set_attr "type" "brcc") | |
90cbba02 | 2521 | (set_attr "length" "8")]) |
0d4a78eb | 2522 | |
f90b7a5a | 2523 | ;; setcc insns. |
0d4a78eb | 2524 | |
f90b7a5a PB |
2525 | (define_expand "cstorebi4" |
2526 | [(set (match_dup 4) | |
2527 | (match_operator:BI 1 "bfin_bimode_comparison_operator" | |
2528 | [(match_operand:BI 2 "register_operand" "") | |
2529 | (match_operand:BI 3 "reg_or_const_int_operand" "")])) | |
0d4a78eb | 2530 | (set (match_operand:SI 0 "register_operand" "") |
f90b7a5a | 2531 | (ne:SI (match_dup 4) (const_int 0)))] |
0d4a78eb BS |
2532 | "" |
2533 | { | |
f90b7a5a PB |
2534 | /* It could be expanded as a movbisi instruction, but the portable |
2535 | alternative produces better code. */ | |
2536 | if (GET_CODE (operands[1]) == NE) | |
2537 | FAIL; | |
0d4a78eb | 2538 | |
f90b7a5a | 2539 | operands[4] = bfin_cc_rtx; |
0d4a78eb BS |
2540 | }) |
2541 | ||
f90b7a5a PB |
2542 | (define_expand "cstoresi4" |
2543 | [(set (match_operand:SI 0 "register_operand") | |
2544 | (match_operator:SI 1 "ordered_comparison_operator" | |
2545 | [(match_operand:SI 2 "register_operand" "") | |
2546 | (match_operand:SI 3 "reg_or_const_int_operand" "")]))] | |
0d4a78eb BS |
2547 | "" |
2548 | { | |
f90b7a5a | 2549 | rtx bi_compare, test; |
0d4a78eb | 2550 | |
f90b7a5a PB |
2551 | if (!bfin_direct_comparison_operator (operands[1], SImode)) |
2552 | { | |
2553 | if (!register_operand (operands[3], SImode) | |
2554 | || GET_CODE (operands[1]) == NE) | |
2555 | FAIL; | |
2556 | test = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])), | |
2557 | SImode, operands[3], operands[2]); | |
2558 | } | |
2559 | else | |
2560 | test = operands[1]; | |
2561 | ||
2562 | bi_compare = bfin_gen_compare (test, SImode); | |
2563 | gcc_assert (GET_CODE (bi_compare) == NE); | |
2564 | emit_insn (gen_movbisi (operands[0], bfin_cc_rtx)); | |
2565 | DONE; | |
0d4a78eb BS |
2566 | }) |
2567 | ||
2568 | (define_insn "nop" | |
2569 | [(const_int 0)] | |
2570 | "" | |
2571 | "nop;") | |
2572 | ||
b18e284e BS |
2573 | ;; A nop which stays there when emitted. |
2574 | (define_insn "forced_nop" | |
2575 | [(unspec [(const_int 0)] UNSPEC_NOP)] | |
2576 | "" | |
2577 | "nop;") | |
2578 | ||
bbbc206e BS |
2579 | (define_insn "mnop" |
2580 | [(unspec [(const_int 0)] UNSPEC_32BIT)] | |
2581 | "" | |
2582 | "mnop%!" | |
2583 | [(set_attr "type" "dsp32")]) | |
2584 | ||
0d4a78eb BS |
2585 | ;;;;;;;;;;;;;;;;;;;; CC2dreg ;;;;;;;;;;;;;;;;;;;;;;;;; |
2586 | (define_insn "movsibi" | |
4729dc92 | 2587 | [(set (match_operand:BI 0 "register_operand" "=C") |
0d4a78eb BS |
2588 | (ne:BI (match_operand:SI 1 "register_operand" "d") |
2589 | (const_int 0)))] | |
2590 | "" | |
2591 | "CC = %1;" | |
2592 | [(set_attr "length" "2")]) | |
2593 | ||
f90b7a5a | 2594 | (define_insn_and_split "movbisi" |
0d4a78eb | 2595 | [(set (match_operand:SI 0 "register_operand" "=d") |
4729dc92 | 2596 | (ne:SI (match_operand:BI 1 "register_operand" "C") |
0d4a78eb BS |
2597 | (const_int 0)))] |
2598 | "" | |
f90b7a5a PB |
2599 | "#" |
2600 | "" | |
2601 | [(set (match_operand:SI 0 "register_operand" "") | |
2602 | (zero_extend:SI (match_operand:BI 1 "register_operand" "")))] | |
2603 | "") | |
0d4a78eb | 2604 | |
e4fae5f7 | 2605 | (define_insn "notbi" |
4729dc92 BS |
2606 | [(set (match_operand:BI 0 "register_operand" "=C") |
2607 | (eq:BI (match_operand:BI 1 "register_operand" " 0") | |
0d4a78eb BS |
2608 | (const_int 0)))] |
2609 | "" | |
2610 | "%0 = ! %0;" /* NOT CC;" */ | |
2611 | [(set_attr "type" "compare")]) | |
2612 | ||
2613 | ;; Vector and DSP insns | |
2614 | ||
2615 | (define_insn "" | |
2616 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2617 | (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") | |
2618 | (const_int 24)) | |
2619 | (lshiftrt:SI (match_operand:SI 2 "register_operand" "d") | |
2620 | (const_int 8))))] | |
2621 | "" | |
bbbc206e | 2622 | "%0 = ALIGN8(%1, %2)%!" |
0d4a78eb BS |
2623 | [(set_attr "type" "dsp32")]) |
2624 | ||
2625 | (define_insn "" | |
2626 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2627 | (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") | |
2628 | (const_int 16)) | |
2629 | (lshiftrt:SI (match_operand:SI 2 "register_operand" "d") | |
2630 | (const_int 16))))] | |
2631 | "" | |
bbbc206e | 2632 | "%0 = ALIGN16(%1, %2)%!" |
0d4a78eb BS |
2633 | [(set_attr "type" "dsp32")]) |
2634 | ||
2635 | (define_insn "" | |
2636 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2637 | (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") | |
2638 | (const_int 8)) | |
2639 | (lshiftrt:SI (match_operand:SI 2 "register_operand" "d") | |
2640 | (const_int 24))))] | |
2641 | "" | |
bbbc206e | 2642 | "%0 = ALIGN24(%1, %2)%!" |
0d4a78eb BS |
2643 | [(set_attr "type" "dsp32")]) |
2644 | ||
2645 | ;; Prologue and epilogue. | |
2646 | ||
2647 | (define_expand "prologue" | |
2648 | [(const_int 1)] | |
2649 | "" | |
2650 | "bfin_expand_prologue (); DONE;") | |
2651 | ||
2652 | (define_expand "epilogue" | |
2653 | [(const_int 1)] | |
2654 | "" | |
1f9e4ca1 | 2655 | "bfin_expand_epilogue (1, 0, 0); DONE;") |
0d4a78eb BS |
2656 | |
2657 | (define_expand "sibcall_epilogue" | |
2658 | [(const_int 1)] | |
2659 | "" | |
1f9e4ca1 | 2660 | "bfin_expand_epilogue (0, 0, 1); DONE;") |
0d4a78eb BS |
2661 | |
2662 | (define_expand "eh_return" | |
cd9c1ca8 | 2663 | [(use (match_operand:SI 0 "register_operand" ""))] |
0d4a78eb BS |
2664 | "" |
2665 | { | |
1ca950ca | 2666 | emit_insn (gen_eh_store_handler (EH_RETURN_HANDLER_RTX, operands[0])); |
1e96b1c3 | 2667 | emit_jump_insn (gen_eh_return_internal ()); |
0d4a78eb | 2668 | emit_barrier (); |
4193ce73 | 2669 | DONE; |
0d4a78eb BS |
2670 | }) |
2671 | ||
1ca950ca BS |
2672 | (define_insn "eh_store_handler" |
2673 | [(unspec_volatile [(match_operand:SI 1 "register_operand" "da")] | |
2674 | UNSPEC_VOLATILE_STORE_EH_HANDLER) | |
2675 | (clobber (match_operand:SI 0 "memory_operand" "=m"))] | |
2676 | "" | |
2677 | "%0 = %1%!" | |
2678 | [(set_attr "type" "mcst")]) | |
2679 | ||
0d4a78eb | 2680 | (define_insn_and_split "eh_return_internal" |
cd9c1ca8 | 2681 | [(eh_return)] |
0d4a78eb BS |
2682 | "" |
2683 | "#" | |
cd9c1ca8 | 2684 | "epilogue_completed" |
0d4a78eb | 2685 | [(const_int 1)] |
1f9e4ca1 | 2686 | "bfin_expand_epilogue (1, 1, 0); DONE;") |
0d4a78eb BS |
2687 | |
2688 | (define_insn "link" | |
2689 | [(set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -4))) (reg:SI REG_RETS)) | |
2690 | (set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -8))) (reg:SI REG_FP)) | |
2691 | (set (reg:SI REG_FP) | |
2692 | (plus:SI (reg:SI REG_SP) (const_int -8))) | |
2693 | (set (reg:SI REG_SP) | |
2694 | (plus:SI (reg:SI REG_SP) (match_operand:SI 0 "immediate_operand" "i")))] | |
2695 | "" | |
2696 | "LINK %Z0;" | |
2697 | [(set_attr "length" "4")]) | |
2698 | ||
2699 | (define_insn "unlink" | |
2700 | [(set (reg:SI REG_FP) (mem:SI (reg:SI REG_FP))) | |
2701 | (set (reg:SI REG_RETS) (mem:SI (plus:SI (reg:SI REG_FP) (const_int 4)))) | |
2702 | (set (reg:SI REG_SP) (plus:SI (reg:SI REG_FP) (const_int 8)))] | |
2703 | "" | |
2704 | "UNLINK;" | |
2705 | [(set_attr "length" "4")]) | |
2706 | ||
2707 | ;; This pattern is slightly clumsy. The stack adjust must be the final SET in | |
2708 | ;; the pattern, otherwise dwarf2out becomes very confused about which reg goes | |
2709 | ;; where on the stack, since it goes through all elements of the parallel in | |
2710 | ;; sequence. | |
2711 | (define_insn "push_multiple" | |
2712 | [(match_parallel 0 "push_multiple_operation" | |
2713 | [(unspec [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_PUSH_MULTIPLE)])] | |
2714 | "" | |
2715 | { | |
2716 | output_push_multiple (insn, operands); | |
2717 | return ""; | |
2718 | }) | |
2719 | ||
2720 | (define_insn "pop_multiple" | |
2721 | [(match_parallel 0 "pop_multiple_operation" | |
2722 | [(set (reg:SI REG_SP) | |
2723 | (plus:SI (reg:SI REG_SP) (match_operand:SI 1 "immediate_operand" "i")))])] | |
2724 | "" | |
2725 | { | |
2726 | output_pop_multiple (insn, operands); | |
2727 | return ""; | |
2728 | }) | |
2729 | ||
2730 | (define_insn "return_internal" | |
2731 | [(return) | |
9840d30a | 2732 | (use (match_operand 0 "register_operand" ""))] |
0d4a78eb BS |
2733 | "reload_completed" |
2734 | { | |
9840d30a | 2735 | switch (REGNO (operands[0])) |
0d4a78eb | 2736 | { |
9840d30a | 2737 | case REG_RETX: |
0d4a78eb | 2738 | return "rtx;"; |
9840d30a | 2739 | case REG_RETN: |
0d4a78eb | 2740 | return "rtn;"; |
9840d30a | 2741 | case REG_RETI: |
0d4a78eb | 2742 | return "rti;"; |
9840d30a | 2743 | case REG_RETS: |
0d4a78eb BS |
2744 | return "rts;"; |
2745 | } | |
2746 | gcc_unreachable (); | |
2747 | }) | |
2748 | ||
c7cb1555 BS |
2749 | ;; When used at a location where CC contains 1, causes a speculative load |
2750 | ;; that is later cancelled. This is used for certain workarounds in | |
2751 | ;; interrupt handler prologues. | |
669eeb28 BS |
2752 | (define_insn "dummy_load" |
2753 | [(unspec_volatile [(match_operand 0 "register_operand" "a") | |
2754 | (match_operand 1 "register_operand" "C")] | |
2755 | UNSPEC_VOLATILE_DUMMY)] | |
2756 | "" | |
2757 | "if cc jump 4;\n\tr7 = [%0];" | |
2758 | [(set_attr "type" "misc") | |
2759 | (set_attr "length" "4") | |
2760 | (set_attr "seq_insns" "multi")]) | |
2761 | ||
c7cb1555 BS |
2762 | ;; A placeholder insn inserted before the final scheduling pass. It is used |
2763 | ;; to improve scheduling of loads when workarounds for speculative loads are | |
2764 | ;; needed, by not placing them in the first few cycles after a conditional | |
2765 | ;; branch. | |
2766 | (define_insn "stall" | |
2767 | [(unspec_volatile [(match_operand 0 "const_int_operand" "P1P3")] | |
2768 | UNSPEC_VOLATILE_STALL)] | |
2769 | "" | |
2770 | "" | |
2771 | [(set_attr "type" "stall")]) | |
2772 | ||
5fcead21 BS |
2773 | (define_insn "csync" |
2774 | [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_CSYNC)] | |
2775 | "" | |
2776 | "csync;" | |
3fb192d2 | 2777 | [(set_attr "type" "sync")]) |
5fcead21 BS |
2778 | |
2779 | (define_insn "ssync" | |
2780 | [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_SSYNC)] | |
2781 | "" | |
2782 | "ssync;" | |
3fb192d2 | 2783 | [(set_attr "type" "sync")]) |
5fcead21 | 2784 | |
3d33a056 JZ |
2785 | (define_insn "trap" |
2786 | [(trap_if (const_int 1) (const_int 3))] | |
2787 | "" | |
2788 | "excpt 3;" | |
2789 | [(set_attr "type" "misc") | |
2790 | (set_attr "length" "2")]) | |
2791 | ||
09350e36 BS |
2792 | (define_insn "trapifcc" |
2793 | [(trap_if (reg:BI REG_CC) (const_int 3))] | |
2794 | "" | |
2795 | "if !cc jump 4 (bp); excpt 3;" | |
2796 | [(set_attr "type" "misc") | |
b03149e1 JZ |
2797 | (set_attr "length" "4") |
2798 | (set_attr "seq_insns" "multi")]) | |
09350e36 | 2799 | |
0d4a78eb BS |
2800 | ;;; Vector instructions |
2801 | ||
75d8b2d0 BS |
2802 | ;; First, all sorts of move variants |
2803 | ||
75d8b2d0 BS |
2804 | (define_insn "movhiv2hi_low" |
2805 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2806 | (vec_concat:V2HI | |
2807 | (match_operand:HI 2 "register_operand" "d") | |
2808 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
2809 | (parallel [(const_int 1)]))))] | |
2810 | "" | |
bbbc206e | 2811 | "%h0 = %h2 << 0%!" |
b3187e24 | 2812 | [(set_attr "type" "dsp32shiftimm")]) |
75d8b2d0 BS |
2813 | |
2814 | (define_insn "movhiv2hi_high" | |
2815 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2816 | (vec_concat:V2HI | |
2817 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
2818 | (parallel [(const_int 0)])) | |
2819 | (match_operand:HI 2 "register_operand" "d")))] | |
2820 | "" | |
bbbc206e | 2821 | "%d0 = %h2 << 0%!" |
b3187e24 | 2822 | [(set_attr "type" "dsp32shiftimm")]) |
75d8b2d0 BS |
2823 | |
2824 | ;; No earlyclobber on alternative two since our sequence ought to be safe. | |
2825 | ;; The order of operands is intentional to match the VDSP builtin (high word | |
2826 | ;; is passed first). | |
2827 | (define_insn_and_split "composev2hi" | |
2828 | [(set (match_operand:V2HI 0 "register_operand" "=d,d") | |
2829 | (vec_concat:V2HI (match_operand:HI 2 "register_operand" "0,d") | |
2830 | (match_operand:HI 1 "register_operand" "d,d")))] | |
2831 | "" | |
2832 | "@ | |
23cf1526 | 2833 | %d0 = %h1 << 0%! |
75d8b2d0 BS |
2834 | #" |
2835 | "reload_completed" | |
2836 | [(set (match_dup 0) | |
2837 | (vec_concat:V2HI | |
2838 | (vec_select:HI (match_dup 0) (parallel [(const_int 0)])) | |
23cf1526 | 2839 | (match_dup 1))) |
75d8b2d0 BS |
2840 | (set (match_dup 0) |
2841 | (vec_concat:V2HI | |
23cf1526 | 2842 | (match_dup 2) |
75d8b2d0 BS |
2843 | (vec_select:HI (match_dup 0) (parallel [(const_int 1)]))))] |
2844 | "" | |
b3187e24 | 2845 | [(set_attr "type" "dsp32shiftimm")]) |
75d8b2d0 BS |
2846 | |
2847 | ; Like composev2hi, but operating on elements of V2HI vectors. | |
2848 | ; Useful on its own, and as a combiner bridge for the multiply and | |
2849 | ; mac patterns. | |
2850 | (define_insn "packv2hi" | |
2d3649b2 | 2851 | [(set (match_operand:V2HI 0 "register_operand" "=d,d,d,d,d,d,d,d") |
75d8b2d0 | 2852 | (vec_concat:V2HI (vec_select:HI |
2d3649b2 BS |
2853 | (match_operand:V2HI 1 "register_operand" "0,0,d,d,d,d,d,d") |
2854 | (parallel [(match_operand 3 "const01_operand" "P0,P0,P0,P1,P0,P1,P0,P1")])) | |
75d8b2d0 | 2855 | (vec_select:HI |
2d3649b2 BS |
2856 | (match_operand:V2HI 2 "register_operand" "d,d,0,0,d,d,d,d") |
2857 | (parallel [(match_operand 4 "const01_operand" "P0,P1,P1,P1,P0,P0,P1,P1")]))))] | |
75d8b2d0 BS |
2858 | "" |
2859 | "@ | |
2d3649b2 BS |
2860 | %d0 = %h2 << 0%! |
2861 | %d0 = %d2 << 0%! | |
2862 | %h0 = %h1 << 0%! | |
2863 | %h0 = %d1 << 0%! | |
bbbc206e BS |
2864 | %0 = PACK (%h2,%h1)%! |
2865 | %0 = PACK (%h2,%d1)%! | |
2866 | %0 = PACK (%d2,%h1)%! | |
2867 | %0 = PACK (%d2,%d1)%!" | |
b3187e24 | 2868 | [(set_attr "type" "dsp32shiftimm,dsp32shiftimm,dsp32shiftimm,dsp32shiftimm,dsp32,dsp32,dsp32,dsp32")]) |
75d8b2d0 BS |
2869 | |
2870 | (define_insn "movv2hi_hi" | |
2871 | [(set (match_operand:HI 0 "register_operand" "=d,d,d") | |
2872 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0,d,d") | |
554006bd | 2873 | (parallel [(match_operand 2 "const01_operand" "P0,P0,P1")])))] |
75d8b2d0 BS |
2874 | "" |
2875 | "@ | |
2876 | /* optimized out */ | |
bbbc206e BS |
2877 | %h0 = %h1 << 0%! |
2878 | %h0 = %d1 << 0%!" | |
b3187e24 | 2879 | [(set_attr "type" "dsp32shiftimm")]) |
75d8b2d0 BS |
2880 | |
2881 | (define_expand "movv2hi_hi_low" | |
2882 | [(set (match_operand:HI 0 "register_operand" "") | |
2883 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "") | |
2884 | (parallel [(const_int 0)])))] | |
2885 | "" | |
2886 | "") | |
2887 | ||
2888 | (define_expand "movv2hi_hi_high" | |
2889 | [(set (match_operand:HI 0 "register_operand" "") | |
2890 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "") | |
2891 | (parallel [(const_int 1)])))] | |
2892 | "" | |
2893 | "") | |
2894 | ||
942fd98f | 2895 | ;; Unusual arithmetic operations on 16-bit registers. |
75d8b2d0 | 2896 | |
a0a31d1e BS |
2897 | (define_code_iterator sp_or_sm [ss_plus ss_minus]) |
2898 | (define_code_attr spm_string [(ss_plus "+") (ss_minus "-")]) | |
2899 | (define_code_attr spm_name [(ss_plus "add") (ss_minus "sub")]) | |
2900 | ||
2901 | (define_insn "ss<spm_name>hi3" | |
75d8b2d0 | 2902 | [(set (match_operand:HI 0 "register_operand" "=d") |
a0a31d1e | 2903 | (sp_or_sm:HI (match_operand:HI 1 "register_operand" "d") |
75d8b2d0 BS |
2904 | (match_operand:HI 2 "register_operand" "d")))] |
2905 | "" | |
a0a31d1e | 2906 | "%h0 = %h1 <spm_string> %h2 (S)%!" |
75d8b2d0 BS |
2907 | [(set_attr "type" "dsp32")]) |
2908 | ||
a0a31d1e BS |
2909 | (define_insn "ss<spm_name>hi3_parts" |
2910 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2911 | (sp_or_sm:HI (vec_select:HI | |
2912 | (match_operand:V2HI 1 "register_operand" "d") | |
2913 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) | |
2914 | (vec_select:HI | |
2915 | (match_operand:V2HI 2 "register_operand" "d") | |
2916 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))))] | |
2917 | "" | |
1d7d5ac4 BS |
2918 | { |
2919 | const char *templates[] = { | |
a0a31d1e BS |
2920 | "%h0 = %h1 <spm_string> %h2 (S)%!", |
2921 | "%h0 = %d1 <spm_string> %h2 (S)%!", | |
2922 | "%h0 = %h1 <spm_string> %d2 (S)%!", | |
2923 | "%h0 = %d1 <spm_string> %d2 (S)%!" }; | |
2924 | int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1); | |
1d7d5ac4 BS |
2925 | return templates[alt]; |
2926 | } | |
2927 | [(set_attr "type" "dsp32")]) | |
2928 | ||
a0a31d1e BS |
2929 | (define_insn "ss<spm_name>hi3_low_parts" |
2930 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2931 | (vec_concat:V2HI | |
2932 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
2933 | (parallel [(const_int 0)])) | |
2934 | (sp_or_sm:HI (vec_select:HI | |
2935 | (match_operand:V2HI 2 "register_operand" "d") | |
2936 | (parallel [(match_operand 4 "const01_operand" "P0P1")])) | |
2937 | (vec_select:HI | |
2938 | (match_operand:V2HI 3 "register_operand" "d") | |
2939 | (parallel [(match_operand 5 "const01_operand" "P0P1")])))))] | |
2940 | "" | |
1d7d5ac4 BS |
2941 | { |
2942 | const char *templates[] = { | |
a0a31d1e BS |
2943 | "%h0 = %h2 <spm_string> %h3 (S)%!", |
2944 | "%h0 = %d2 <spm_string> %h3 (S)%!", | |
2945 | "%h0 = %h2 <spm_string> %d3 (S)%!", | |
2946 | "%h0 = %d2 <spm_string> %d3 (S)%!" }; | |
2947 | int alt = INTVAL (operands[4]) + (INTVAL (operands[5]) << 1); | |
1d7d5ac4 BS |
2948 | return templates[alt]; |
2949 | } | |
2950 | [(set_attr "type" "dsp32")]) | |
2951 | ||
a0a31d1e BS |
2952 | (define_insn "ss<spm_name>hi3_high_parts" |
2953 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2954 | (vec_concat:V2HI | |
2955 | (sp_or_sm:HI (vec_select:HI | |
2956 | (match_operand:V2HI 2 "register_operand" "d") | |
2957 | (parallel [(match_operand 4 "const01_operand" "P0P1")])) | |
2958 | (vec_select:HI | |
2959 | (match_operand:V2HI 3 "register_operand" "d") | |
2960 | (parallel [(match_operand 5 "const01_operand" "P0P1")]))) | |
2961 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
2962 | (parallel [(const_int 1)]))))] | |
2963 | "" | |
2964 | { | |
2965 | const char *templates[] = { | |
2966 | "%d0 = %h2 <spm_string> %h3 (S)%!", | |
2967 | "%d0 = %d2 <spm_string> %h3 (S)%!", | |
2968 | "%d0 = %h2 <spm_string> %d3 (S)%!", | |
2969 | "%d0 = %d2 <spm_string> %d3 (S)%!" }; | |
2970 | int alt = INTVAL (operands[4]) + (INTVAL (operands[5]) << 1); | |
2971 | return templates[alt]; | |
2972 | } | |
75d8b2d0 BS |
2973 | [(set_attr "type" "dsp32")]) |
2974 | ||
2975 | ;; V2HI vector insns | |
2976 | ||
c9b3f817 | 2977 | (define_insn "addv2hi3" |
0d4a78eb BS |
2978 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
2979 | (plus:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
2980 | (match_operand:V2HI 2 "register_operand" "d")))] | |
2981 | "" | |
bbbc206e | 2982 | "%0 = %1 +|+ %2%!" |
0d4a78eb BS |
2983 | [(set_attr "type" "dsp32")]) |
2984 | ||
75d8b2d0 BS |
2985 | (define_insn "ssaddv2hi3" |
2986 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2987 | (ss_plus:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
2988 | (match_operand:V2HI 2 "register_operand" "d")))] | |
2989 | "" | |
bbbc206e | 2990 | "%0 = %1 +|+ %2 (S)%!" |
75d8b2d0 BS |
2991 | [(set_attr "type" "dsp32")]) |
2992 | ||
c9b3f817 | 2993 | (define_insn "subv2hi3" |
0d4a78eb BS |
2994 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
2995 | (minus:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
2996 | (match_operand:V2HI 2 "register_operand" "d")))] | |
2997 | "" | |
bbbc206e | 2998 | "%0 = %1 -|- %2%!" |
0d4a78eb BS |
2999 | [(set_attr "type" "dsp32")]) |
3000 | ||
75d8b2d0 BS |
3001 | (define_insn "sssubv2hi3" |
3002 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3003 | (ss_minus:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
3004 | (match_operand:V2HI 2 "register_operand" "d")))] | |
3005 | "" | |
bbbc206e | 3006 | "%0 = %1 -|- %2 (S)%!" |
75d8b2d0 BS |
3007 | [(set_attr "type" "dsp32")]) |
3008 | ||
3009 | (define_insn "addsubv2hi3" | |
3010 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3011 | (vec_concat:V2HI | |
3012 | (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3013 | (parallel [(const_int 0)])) | |
3014 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3015 | (parallel [(const_int 0)]))) | |
3016 | (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])) | |
3017 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3018 | "" | |
bbbc206e | 3019 | "%0 = %1 +|- %2%!" |
75d8b2d0 BS |
3020 | [(set_attr "type" "dsp32")]) |
3021 | ||
3022 | (define_insn "subaddv2hi3" | |
3023 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3024 | (vec_concat:V2HI | |
3025 | (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3026 | (parallel [(const_int 0)])) | |
3027 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3028 | (parallel [(const_int 0)]))) | |
3029 | (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])) | |
3030 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3031 | "" | |
bbbc206e | 3032 | "%0 = %1 -|+ %2%!" |
75d8b2d0 BS |
3033 | [(set_attr "type" "dsp32")]) |
3034 | ||
3035 | (define_insn "ssaddsubv2hi3" | |
3036 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3037 | (vec_concat:V2HI | |
3038 | (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3039 | (parallel [(const_int 0)])) | |
3040 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3041 | (parallel [(const_int 0)]))) | |
3042 | (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])) | |
3043 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3044 | "" | |
bbbc206e | 3045 | "%0 = %1 +|- %2 (S)%!" |
75d8b2d0 BS |
3046 | [(set_attr "type" "dsp32")]) |
3047 | ||
3048 | (define_insn "sssubaddv2hi3" | |
3049 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3050 | (vec_concat:V2HI | |
3051 | (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3052 | (parallel [(const_int 0)])) | |
3053 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3054 | (parallel [(const_int 0)]))) | |
3055 | (ss_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])) | |
3056 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3057 | "" | |
bbbc206e | 3058 | "%0 = %1 -|+ %2 (S)%!" |
75d8b2d0 BS |
3059 | [(set_attr "type" "dsp32")]) |
3060 | ||
3061 | (define_insn "sublohiv2hi3" | |
3062 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3063 | (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3064 | (parallel [(const_int 1)])) | |
3065 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3066 | (parallel [(const_int 0)]))))] | |
3067 | "" | |
bbbc206e | 3068 | "%h0 = %d1 - %h2%!" |
75d8b2d0 BS |
3069 | [(set_attr "type" "dsp32")]) |
3070 | ||
3071 | (define_insn "subhilov2hi3" | |
3072 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3073 | (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3074 | (parallel [(const_int 0)])) | |
3075 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3076 | (parallel [(const_int 1)]))))] | |
3077 | "" | |
bbbc206e | 3078 | "%h0 = %h1 - %d2%!" |
75d8b2d0 BS |
3079 | [(set_attr "type" "dsp32")]) |
3080 | ||
3081 | (define_insn "sssublohiv2hi3" | |
3082 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3083 | (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3084 | (parallel [(const_int 1)])) | |
3085 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3086 | (parallel [(const_int 0)]))))] | |
3087 | "" | |
bbbc206e | 3088 | "%h0 = %d1 - %h2 (S)%!" |
75d8b2d0 BS |
3089 | [(set_attr "type" "dsp32")]) |
3090 | ||
3091 | (define_insn "sssubhilov2hi3" | |
3092 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3093 | (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3094 | (parallel [(const_int 0)])) | |
3095 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3096 | (parallel [(const_int 1)]))))] | |
3097 | "" | |
bbbc206e | 3098 | "%h0 = %h1 - %d2 (S)%!" |
75d8b2d0 BS |
3099 | [(set_attr "type" "dsp32")]) |
3100 | ||
3101 | (define_insn "addlohiv2hi3" | |
3102 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3103 | (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3104 | (parallel [(const_int 1)])) | |
3105 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3106 | (parallel [(const_int 0)]))))] | |
3107 | "" | |
bbbc206e | 3108 | "%h0 = %d1 + %h2%!" |
75d8b2d0 BS |
3109 | [(set_attr "type" "dsp32")]) |
3110 | ||
3111 | (define_insn "addhilov2hi3" | |
3112 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3113 | (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3114 | (parallel [(const_int 0)])) | |
3115 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3116 | (parallel [(const_int 1)]))))] | |
3117 | "" | |
bbbc206e | 3118 | "%h0 = %h1 + %d2%!" |
75d8b2d0 BS |
3119 | [(set_attr "type" "dsp32")]) |
3120 | ||
3121 | (define_insn "ssaddlohiv2hi3" | |
3122 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3123 | (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3124 | (parallel [(const_int 1)])) | |
3125 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3126 | (parallel [(const_int 0)]))))] | |
3127 | "" | |
bbbc206e | 3128 | "%h0 = %d1 + %h2 (S)%!" |
75d8b2d0 BS |
3129 | [(set_attr "type" "dsp32")]) |
3130 | ||
3131 | (define_insn "ssaddhilov2hi3" | |
3132 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3133 | (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3134 | (parallel [(const_int 0)])) | |
3135 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3136 | (parallel [(const_int 1)]))))] | |
3137 | "" | |
bbbc206e | 3138 | "%h0 = %h1 + %d2 (S)%!" |
75d8b2d0 BS |
3139 | [(set_attr "type" "dsp32")]) |
3140 | ||
c9b3f817 | 3141 | (define_insn "sminv2hi3" |
0d4a78eb BS |
3142 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
3143 | (smin:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
3144 | (match_operand:V2HI 2 "register_operand" "d")))] | |
3145 | "" | |
bbbc206e | 3146 | "%0 = MIN (%1, %2) (V)%!" |
0d4a78eb BS |
3147 | [(set_attr "type" "dsp32")]) |
3148 | ||
c9b3f817 | 3149 | (define_insn "smaxv2hi3" |
0d4a78eb BS |
3150 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
3151 | (smax:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
3152 | (match_operand:V2HI 2 "register_operand" "d")))] | |
3153 | "" | |
bbbc206e | 3154 | "%0 = MAX (%1, %2) (V)%!" |
0d4a78eb BS |
3155 | [(set_attr "type" "dsp32")]) |
3156 | ||
75d8b2d0 BS |
3157 | ;; Multiplications. |
3158 | ||
3159 | ;; The Blackfin allows a lot of different options, and we need many patterns to | |
3160 | ;; cover most of the hardware's abilities. | |
3161 | ;; There are a few simple patterns using MULT rtx codes, but most of them use | |
3162 | ;; an unspec with a const_int operand that determines which flag to use in the | |
3163 | ;; instruction. | |
3164 | ;; There are variants for single and parallel multiplications. | |
942fd98f | 3165 | ;; There are variants which just use 16-bit lowparts as inputs, and variants |
75d8b2d0 BS |
3166 | ;; which allow the user to choose just which halves to use as input values. |
3167 | ;; There are variants which set D registers, variants which set accumulators, | |
3168 | ;; variants which set both, some of them optionally using the accumulators as | |
3169 | ;; inputs for multiply-accumulate operations. | |
3170 | ||
3171 | (define_insn "flag_mulhi" | |
3172 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3173 | (unspec:HI [(match_operand:HI 1 "register_operand" "d") | |
3174 | (match_operand:HI 2 "register_operand" "d") | |
3175 | (match_operand 3 "const_int_operand" "n")] | |
3176 | UNSPEC_MUL_WITH_FLAG))] | |
3177 | "" | |
bbbc206e | 3178 | "%h0 = %h1 * %h2 %M3%!" |
75d8b2d0 BS |
3179 | [(set_attr "type" "dsp32")]) |
3180 | ||
1d7d5ac4 | 3181 | (define_insn "flag_mulhi_parts" |
a0a31d1e | 3182 | [(set (match_operand:HI 0 "register_operand" "=d") |
1d7d5ac4 BS |
3183 | (unspec:HI [(vec_select:HI |
3184 | (match_operand:V2HI 1 "register_operand" "d") | |
a0a31d1e | 3185 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
1d7d5ac4 BS |
3186 | (vec_select:HI |
3187 | (match_operand:V2HI 2 "register_operand" "d") | |
a0a31d1e BS |
3188 | (parallel [(match_operand 4 "const01_operand" "P0P1")])) |
3189 | (match_operand 5 "const_int_operand" "n")] | |
1d7d5ac4 BS |
3190 | UNSPEC_MUL_WITH_FLAG))] |
3191 | "" | |
3192 | { | |
3193 | const char *templates[] = { | |
a0a31d1e BS |
3194 | "%h0 = %h1 * %h2 %M5%!", |
3195 | "%h0 = %d1 * %h2 %M5%!", | |
3196 | "%h0 = %h1 * %d2 %M5%!", | |
3197 | "%h0 = %d1 * %d2 %M5%!" }; | |
3198 | int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1); | |
1d7d5ac4 BS |
3199 | return templates[alt]; |
3200 | } | |
3201 | [(set_attr "type" "dsp32")]) | |
3202 | ||
75d8b2d0 BS |
3203 | (define_insn "flag_mulhisi" |
3204 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3205 | (unspec:SI [(match_operand:HI 1 "register_operand" "d") | |
3206 | (match_operand:HI 2 "register_operand" "d") | |
3207 | (match_operand 3 "const_int_operand" "n")] | |
3208 | UNSPEC_MUL_WITH_FLAG))] | |
3209 | "" | |
bbbc206e | 3210 | "%0 = %h1 * %h2 %M3%!" |
75d8b2d0 BS |
3211 | [(set_attr "type" "dsp32")]) |
3212 | ||
3213 | (define_insn "flag_mulhisi_parts" | |
3214 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3215 | (unspec:SI [(vec_select:HI | |
3216 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3217 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3218 | (vec_select:HI |
3219 | (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3220 | (parallel [(match_operand 4 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3221 | (match_operand 5 "const_int_operand" "n")] |
3222 | UNSPEC_MUL_WITH_FLAG))] | |
3223 | "" | |
3224 | { | |
3225 | const char *templates[] = { | |
bbbc206e BS |
3226 | "%0 = %h1 * %h2 %M5%!", |
3227 | "%0 = %d1 * %h2 %M5%!", | |
3228 | "%0 = %h1 * %d2 %M5%!", | |
3229 | "%0 = %d1 * %d2 %M5%!" }; | |
75d8b2d0 BS |
3230 | int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1); |
3231 | return templates[alt]; | |
3232 | } | |
3233 | [(set_attr "type" "dsp32")]) | |
3234 | ||
3efd5670 BS |
3235 | ;; Three alternatives here to cover all possible allocations: |
3236 | ;; 0. mac flag is usable only for accumulator 1 - use A1 and odd DREG | |
3237 | ;; 1. mac flag is usable for accumulator 0 - use A0 and even DREG | |
3238 | ;; 2. mac flag is usable in any accumulator - use A1 and odd DREG | |
3239 | ;; Other patterns which don't have a DREG destination can collapse cases | |
3240 | ;; 1 and 2 into one. | |
75d8b2d0 | 3241 | (define_insn "flag_machi" |
3efd5670 BS |
3242 | [(set (match_operand:HI 0 "register_operand" "=W,D,W") |
3243 | (unspec:HI [(match_operand:HI 2 "register_operand" "d,d,d") | |
3244 | (match_operand:HI 3 "register_operand" "d,d,d") | |
3245 | (match_operand 4 "register_operand" "1,1,1") | |
3246 | (match_operand 5 "const01_operand" "P0P1,P0P1,P0P1") | |
3247 | (match_operand 6 "const_int_operand" "PB,PA,PA")] | |
75d8b2d0 | 3248 | UNSPEC_MAC_WITH_FLAG)) |
3efd5670 | 3249 | (set (match_operand:PDI 1 "register_operand" "=B,A,B") |
75d8b2d0 BS |
3250 | (unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3) |
3251 | (match_dup 4) (match_dup 5)] | |
3252 | UNSPEC_MAC_WITH_FLAG))] | |
3253 | "" | |
3efd5670 | 3254 | "%h0 = (%1 %b5 %h2 * %h3) %M6%!" |
75d8b2d0 BS |
3255 | [(set_attr "type" "dsp32")]) |
3256 | ||
3257 | (define_insn "flag_machi_acconly" | |
3efd5670 BS |
3258 | [(set (match_operand:PDI 0 "register_operand" "=B,e") |
3259 | (unspec:PDI [(match_operand:HI 1 "register_operand" "d,d") | |
3260 | (match_operand:HI 2 "register_operand" "d,d") | |
3261 | (match_operand 3 "register_operand" "0,0") | |
3262 | (match_operand 4 "const01_operand" "P0P1,P0P1") | |
3263 | (match_operand 5 "const_int_operand" "PB,PA")] | |
75d8b2d0 BS |
3264 | UNSPEC_MAC_WITH_FLAG))] |
3265 | "" | |
3efd5670 BS |
3266 | "%0 %b4 %h1 * %h2 %M5%!" |
3267 | [(set_attr "type" "dsp32")]) | |
3268 | ||
3269 | (define_insn "flag_machi_parts_acconly" | |
3270 | [(set (match_operand:PDI 0 "register_operand" "=B,e") | |
3271 | (unspec:PDI [(vec_select:HI | |
3272 | (match_operand:V2HI 1 "register_operand" "d,d") | |
3273 | (parallel [(match_operand 3 "const01_operand" "P0P1,P0P1")])) | |
3274 | (vec_select:HI | |
3275 | (match_operand:V2HI 2 "register_operand" "d,d") | |
3276 | (parallel [(match_operand 4 "const01_operand" "P0P1,P0P1")])) | |
3277 | (match_operand:PDI 5 "register_operand" "0,0") | |
3278 | (match_operand 6 "const01_operand" "P0P1,P0P1") | |
3279 | (match_operand 7 "const_int_operand" "PB,PA")] | |
3280 | UNSPEC_MAC_WITH_FLAG))] | |
3281 | "" | |
3282 | { | |
3283 | const char *templates[] = { | |
3284 | "%0 %b6 %h1 * %h2 %M7%!", | |
3285 | "%0 %b6 %d1 * %h2 %M7%!", | |
3286 | "%0 %b6 %h1 * %d2 %M7%!", | |
3287 | "%0 %b6 %d1 * %d2 %M7%!" | |
3288 | }; | |
3289 | int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1); | |
3290 | return templates[alt]; | |
3291 | } | |
75d8b2d0 BS |
3292 | [(set_attr "type" "dsp32")]) |
3293 | ||
3294 | (define_insn "flag_macinithi" | |
3efd5670 BS |
3295 | [(set (match_operand:HI 0 "register_operand" "=W,D,W") |
3296 | (unspec:HI [(match_operand:HI 1 "register_operand" "d,d,d") | |
3297 | (match_operand:HI 2 "register_operand" "d,d,d") | |
3298 | (match_operand 3 "const_int_operand" "PB,PA,PA")] | |
75d8b2d0 | 3299 | UNSPEC_MAC_WITH_FLAG)) |
3efd5670 | 3300 | (set (match_operand:PDI 4 "register_operand" "=B,A,B") |
75d8b2d0 BS |
3301 | (unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3)] |
3302 | UNSPEC_MAC_WITH_FLAG))] | |
3303 | "" | |
3efd5670 | 3304 | "%h0 = (%4 = %h1 * %h2) %M3%!" |
75d8b2d0 BS |
3305 | [(set_attr "type" "dsp32")]) |
3306 | ||
3307 | (define_insn "flag_macinit1hi" | |
3efd5670 BS |
3308 | [(set (match_operand:PDI 0 "register_operand" "=B,e") |
3309 | (unspec:PDI [(match_operand:HI 1 "register_operand" "d,d") | |
3310 | (match_operand:HI 2 "register_operand" "d,d") | |
3311 | (match_operand 3 "const_int_operand" "PB,PA")] | |
75d8b2d0 BS |
3312 | UNSPEC_MAC_WITH_FLAG))] |
3313 | "" | |
bbbc206e | 3314 | "%0 = %h1 * %h2 %M3%!" |
75d8b2d0 BS |
3315 | [(set_attr "type" "dsp32")]) |
3316 | ||
c9b3f817 | 3317 | (define_insn "mulv2hi3" |
0d4a78eb BS |
3318 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
3319 | (mult:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
3320 | (match_operand:V2HI 2 "register_operand" "d")))] | |
3321 | "" | |
bbbc206e | 3322 | "%h0 = %h1 * %h2, %d0 = %d1 * %d2 (IS)%!" |
0d4a78eb BS |
3323 | [(set_attr "type" "dsp32")]) |
3324 | ||
75d8b2d0 BS |
3325 | (define_insn "flag_mulv2hi" |
3326 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3327 | (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d") | |
3328 | (match_operand:V2HI 2 "register_operand" "d") | |
3329 | (match_operand 3 "const_int_operand" "n")] | |
3330 | UNSPEC_MUL_WITH_FLAG))] | |
3331 | "" | |
bbbc206e | 3332 | "%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M3%!" |
75d8b2d0 BS |
3333 | [(set_attr "type" "dsp32")]) |
3334 | ||
3335 | (define_insn "flag_mulv2hi_parts" | |
3336 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3337 | (unspec:V2HI [(vec_concat:V2HI | |
3338 | (vec_select:HI | |
3339 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3340 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3341 | (vec_select:HI |
3342 | (match_dup 1) | |
554006bd | 3343 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3344 | (vec_concat:V2HI |
3345 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3346 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3347 | (vec_select:HI (match_dup 2) |
554006bd | 3348 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3349 | (match_operand 7 "const_int_operand" "n")] |
3350 | UNSPEC_MUL_WITH_FLAG))] | |
3351 | "" | |
3352 | { | |
3353 | const char *templates[] = { | |
bbbc206e BS |
3354 | "%h0 = %h1 * %h2, %d0 = %h1 * %h2 %M7%!", |
3355 | "%h0 = %d1 * %h2, %d0 = %h1 * %h2 %M7%!", | |
3356 | "%h0 = %h1 * %h2, %d0 = %d1 * %h2 %M7%!", | |
3357 | "%h0 = %d1 * %h2, %d0 = %d1 * %h2 %M7%!", | |
3358 | "%h0 = %h1 * %d2, %d0 = %h1 * %h2 %M7%!", | |
3359 | "%h0 = %d1 * %d2, %d0 = %h1 * %h2 %M7%!", | |
3360 | "%h0 = %h1 * %d2, %d0 = %d1 * %h2 %M7%!", | |
3361 | "%h0 = %d1 * %d2, %d0 = %d1 * %h2 %M7%!", | |
3362 | "%h0 = %h1 * %h2, %d0 = %h1 * %d2 %M7%!", | |
3363 | "%h0 = %d1 * %h2, %d0 = %h1 * %d2 %M7%!", | |
3364 | "%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M7%!", | |
3365 | "%h0 = %d1 * %h2, %d0 = %d1 * %d2 %M7%!", | |
3366 | "%h0 = %h1 * %d2, %d0 = %h1 * %d2 %M7%!", | |
3367 | "%h0 = %d1 * %d2, %d0 = %h1 * %d2 %M7%!", | |
3368 | "%h0 = %h1 * %d2, %d0 = %d1 * %d2 %M7%!", | |
3369 | "%h0 = %d1 * %d2, %d0 = %d1 * %d2 %M7%!" }; | |
75d8b2d0 BS |
3370 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3371 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3372 | return templates[alt]; | |
3373 | } | |
3374 | [(set_attr "type" "dsp32")]) | |
3375 | ||
3376 | ;; A slightly complicated pattern. | |
3377 | ;; Operand 0 is the halfword output; operand 11 is the accumulator output | |
3378 | ;; Halfword inputs are operands 1 and 2; operands 3, 4, 5 and 6 specify which | |
3379 | ;; parts of these 2x16 bit registers to use. | |
3380 | ;; Operand 7 is the accumulator input. | |
3381 | ;; Operands 8/9 specify whether low/high parts are mac (0) or msu (1) | |
3382 | ;; Operand 10 is the macflag to be used. | |
3383 | (define_insn "flag_macv2hi_parts" | |
3384 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3385 | (unspec:V2HI [(vec_concat:V2HI | |
3386 | (vec_select:HI | |
3387 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3388 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3389 | (vec_select:HI |
3390 | (match_dup 1) | |
554006bd | 3391 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3392 | (vec_concat:V2HI |
3393 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3394 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3395 | (vec_select:HI (match_dup 2) |
554006bd | 3396 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3397 | (match_operand:V2PDI 7 "register_operand" "e") |
3398 | (match_operand 8 "const01_operand" "P0P1") | |
3399 | (match_operand 9 "const01_operand" "P0P1") | |
3400 | (match_operand 10 "const_int_operand" "n")] | |
3401 | UNSPEC_MAC_WITH_FLAG)) | |
3402 | (set (match_operand:V2PDI 11 "register_operand" "=e") | |
3403 | (unspec:V2PDI [(vec_concat:V2HI | |
3404 | (vec_select:HI (match_dup 1) (parallel [(match_dup 3)])) | |
3405 | (vec_select:HI (match_dup 1) (parallel [(match_dup 4)]))) | |
3406 | (vec_concat:V2HI | |
3407 | (vec_select:HI (match_dup 2) (parallel [(match_dup 5)])) | |
3408 | (vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))) | |
3409 | (match_dup 7) (match_dup 8) (match_dup 9) (match_dup 10)] | |
3410 | UNSPEC_MAC_WITH_FLAG))] | |
3411 | "" | |
3412 | { | |
3413 | const char *templates[] = { | |
bbbc206e BS |
3414 | "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10%!", |
3415 | "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10%!", | |
3416 | "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10%!", | |
3417 | "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10%!", | |
3418 | "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10%!", | |
3419 | "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10%!", | |
3420 | "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10%!", | |
3421 | "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10%!", | |
3422 | "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10%!", | |
3423 | "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10%!", | |
3424 | "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10%!", | |
3425 | "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10%!", | |
3426 | "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10%!", | |
3427 | "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10%!", | |
3428 | "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10%!", | |
3429 | "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10%!" }; | |
75d8b2d0 BS |
3430 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3431 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3432 | return templates[alt]; | |
3433 | } | |
3434 | [(set_attr "type" "dsp32")]) | |
3435 | ||
3436 | (define_insn "flag_macv2hi_parts_acconly" | |
3437 | [(set (match_operand:V2PDI 0 "register_operand" "=e") | |
3438 | (unspec:V2PDI [(vec_concat:V2HI | |
3439 | (vec_select:HI | |
3440 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3441 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3442 | (vec_select:HI |
3443 | (match_dup 1) | |
554006bd | 3444 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3445 | (vec_concat:V2HI |
3446 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3447 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3448 | (vec_select:HI (match_dup 2) |
554006bd | 3449 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3450 | (match_operand:V2PDI 7 "register_operand" "e") |
3451 | (match_operand 8 "const01_operand" "P0P1") | |
3452 | (match_operand 9 "const01_operand" "P0P1") | |
3453 | (match_operand 10 "const_int_operand" "n")] | |
3454 | UNSPEC_MAC_WITH_FLAG))] | |
3455 | "" | |
3456 | { | |
3457 | const char *templates[] = { | |
bbbc206e BS |
3458 | "A0 %b8 %h1 * %h2, A1 %b9 %h1 * %h2 %M10%!", |
3459 | "A0 %b8 %d1 * %h2, A1 %b9 %h1 * %h2 %M10%!", | |
3460 | "A0 %b8 %h1 * %h2, A1 %b9 %d1 * %h2 %M10%!", | |
3461 | "A0 %b8 %d1 * %h2, A1 %b9 %d1 * %h2 %M10%!", | |
3462 | "A0 %b8 %h1 * %d2, A1 %b9 %h1 * %h2 %M10%!", | |
3463 | "A0 %b8 %d1 * %d2, A1 %b9 %h1 * %h2 %M10%!", | |
3464 | "A0 %b8 %h1 * %d2, A1 %b9 %d1 * %h2 %M10%!", | |
3465 | "A0 %b8 %d1 * %d2, A1 %b9 %d1 * %h2 %M10%!", | |
3466 | "A0 %b8 %h1 * %h2, A1 %b9 %h1 * %d2 %M10%!", | |
3467 | "A0 %b8 %d1 * %h2, A1 %b9 %h1 * %d2 %M10%!", | |
3468 | "A0 %b8 %h1 * %h2, A1 %b9 %d1 * %d2 %M10%!", | |
3469 | "A0 %b8 %d1 * %h2, A1 %b9 %d1 * %d2 %M10%!", | |
3470 | "A0 %b8 %h1 * %d2, A1 %b9 %h1 * %d2 %M10%!", | |
3471 | "A0 %b8 %d1 * %d2, A1 %b9 %h1 * %d2 %M10%!", | |
3472 | "A0 %b8 %h1 * %d2, A1 %b9 %d1 * %d2 %M10%!", | |
3473 | "A0 %b8 %d1 * %d2, A1 %b9 %d1 * %d2 %M10%!" }; | |
75d8b2d0 BS |
3474 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3475 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3476 | return templates[alt]; | |
3477 | } | |
3478 | [(set_attr "type" "dsp32")]) | |
3479 | ||
3480 | ;; Same as above, but initializing the accumulators and therefore a couple fewer | |
3481 | ;; necessary operands. | |
3482 | (define_insn "flag_macinitv2hi_parts" | |
0d4a78eb | 3483 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
75d8b2d0 BS |
3484 | (unspec:V2HI [(vec_concat:V2HI |
3485 | (vec_select:HI | |
3486 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3487 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3488 | (vec_select:HI |
3489 | (match_dup 1) | |
554006bd | 3490 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3491 | (vec_concat:V2HI |
3492 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3493 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3494 | (vec_select:HI (match_dup 2) |
554006bd | 3495 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3496 | (match_operand 7 "const_int_operand" "n")] |
3497 | UNSPEC_MAC_WITH_FLAG)) | |
3498 | (set (match_operand:V2PDI 8 "register_operand" "=e") | |
3499 | (unspec:V2PDI [(vec_concat:V2HI | |
3500 | (vec_select:HI (match_dup 1) (parallel [(match_dup 3)])) | |
3501 | (vec_select:HI (match_dup 1) (parallel [(match_dup 4)]))) | |
3502 | (vec_concat:V2HI | |
3503 | (vec_select:HI (match_dup 2) (parallel [(match_dup 5)])) | |
3504 | (vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))) | |
3505 | (match_dup 7)] | |
3506 | UNSPEC_MAC_WITH_FLAG))] | |
3507 | "" | |
3508 | { | |
3509 | const char *templates[] = { | |
bbbc206e BS |
3510 | "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %h2) %M7%!", |
3511 | "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %h2) %M7%!", | |
3512 | "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %h2) %M7%!", | |
3513 | "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %h2) %M7%!", | |
3514 | "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %h2) %M7%!", | |
3515 | "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %h2) %M7%!", | |
3516 | "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %h2) %M7%!", | |
3517 | "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %h2) %M7%!", | |
3518 | "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %d2) %M7%!", | |
3519 | "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %d2) %M7%!", | |
3520 | "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %d2) %M7%!", | |
3521 | "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %d2) %M7%!", | |
3522 | "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %d2) %M7%!", | |
3523 | "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %d2) %M7%!", | |
3524 | "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %d2) %M7%!", | |
3525 | "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %d2) %M7%!" }; | |
75d8b2d0 BS |
3526 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3527 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3528 | return templates[alt]; | |
3529 | } | |
3530 | [(set_attr "type" "dsp32")]) | |
3531 | ||
3532 | (define_insn "flag_macinit1v2hi_parts" | |
3533 | [(set (match_operand:V2PDI 0 "register_operand" "=e") | |
3534 | (unspec:V2PDI [(vec_concat:V2HI | |
3535 | (vec_select:HI | |
3536 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3537 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3538 | (vec_select:HI |
3539 | (match_dup 1) | |
554006bd | 3540 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3541 | (vec_concat:V2HI |
3542 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3543 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3544 | (vec_select:HI (match_dup 2) |
554006bd | 3545 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3546 | (match_operand 7 "const_int_operand" "n")] |
3547 | UNSPEC_MAC_WITH_FLAG))] | |
3548 | "" | |
3549 | { | |
3550 | const char *templates[] = { | |
bbbc206e BS |
3551 | "A0 = %h1 * %h2, A1 = %h1 * %h2 %M7%!", |
3552 | "A0 = %d1 * %h2, A1 = %h1 * %h2 %M7%!", | |
3553 | "A0 = %h1 * %h2, A1 = %d1 * %h2 %M7%!", | |
3554 | "A0 = %d1 * %h2, A1 = %d1 * %h2 %M7%!", | |
3555 | "A0 = %h1 * %d2, A1 = %h1 * %h2 %M7%!", | |
3556 | "A0 = %d1 * %d2, A1 = %h1 * %h2 %M7%!", | |
3557 | "A0 = %h1 * %d2, A1 = %d1 * %h2 %M7%!", | |
3558 | "A0 = %d1 * %d2, A1 = %d1 * %h2 %M7%!", | |
3559 | "A0 = %h1 * %h2, A1 = %h1 * %d2 %M7%!", | |
3560 | "A0 = %d1 * %h2, A1 = %h1 * %d2 %M7%!", | |
3561 | "A0 = %h1 * %h2, A1 = %d1 * %d2 %M7%!", | |
3562 | "A0 = %d1 * %h2, A1 = %d1 * %d2 %M7%!", | |
3563 | "A0 = %h1 * %d2, A1 = %h1 * %d2 %M7%!", | |
3564 | "A0 = %d1 * %d2, A1 = %h1 * %d2 %M7%!", | |
3565 | "A0 = %h1 * %d2, A1 = %d1 * %d2 %M7%!", | |
3566 | "A0 = %d1 * %d2, A1 = %d1 * %d2 %M7%!" }; | |
75d8b2d0 BS |
3567 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3568 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3569 | return templates[alt]; | |
3570 | } | |
3571 | [(set_attr "type" "dsp32")]) | |
3572 | ||
3efd5670 BS |
3573 | ;; A mixture of multiply and multiply-accumulate for when we only want to |
3574 | ;; initialize one part. | |
3575 | (define_insn "flag_mul_macv2hi_parts_acconly" | |
3576 | [(set (match_operand:PDI 0 "register_operand" "=B,e,e") | |
3577 | (unspec:PDI [(vec_select:HI | |
3578 | (match_operand:V2HI 2 "register_operand" "d,d,d") | |
3579 | (parallel [(match_operand 4 "const01_operand" "P0P1,P0P1,P0P1")])) | |
3580 | (vec_select:HI | |
3581 | (match_operand:V2HI 3 "register_operand" "d,d,d") | |
3582 | (parallel [(match_operand 6 "const01_operand" "P0P1,P0P1,P0P1")])) | |
3583 | (match_operand 10 "const_int_operand" "PB,PA,PA")] | |
3584 | UNSPEC_MUL_WITH_FLAG)) | |
3585 | (set (match_operand:PDI 1 "register_operand" "=B,e,e") | |
3586 | (unspec:PDI [(vec_select:HI | |
3587 | (match_dup 2) | |
3588 | (parallel [(match_operand 5 "const01_operand" "P0P1,P0P1,P0P1")])) | |
3589 | (vec_select:HI | |
3590 | (match_dup 3) | |
3591 | (parallel [(match_operand 7 "const01_operand" "P0P1,P0P1,P0P1")])) | |
3592 | (match_operand:PDI 8 "register_operand" "1,1,1") | |
3593 | (match_operand 9 "const01_operand" "P0P1,P0P1,P0P1") | |
3594 | (match_operand 11 "const_int_operand" "PA,PB,PA")] | |
3595 | UNSPEC_MAC_WITH_FLAG))] | |
3596 | "MACFLAGS_MATCH_P (INTVAL (operands[10]), INTVAL (operands[11]))" | |
3597 | { | |
3598 | rtx xops[6]; | |
3599 | const char *templates[] = { | |
3600 | "%0 = %h2 * %h3, %1 %b4 %h2 * %h3 %M5%!", | |
3601 | "%0 = %d2 * %h3, %1 %b4 %h2 * %h3 %M5%!", | |
3602 | "%0 = %h2 * %h3, %1 %b4 %d2 * %h3 %M5%!", | |
3603 | "%0 = %d2 * %h3, %1 %b4 %d2 * %h3 %M5%!", | |
3604 | "%0 = %h2 * %d3, %1 %b4 %h2 * %h3 %M5%!", | |
3605 | "%0 = %d2 * %d3, %1 %b4 %h2 * %h3 %M5%!", | |
3606 | "%0 = %h2 * %d3, %1 %b4 %d2 * %h3 %M5%!", | |
3607 | "%0 = %d2 * %d3, %1 %b4 %d2 * %h3 %M5%!", | |
3608 | "%0 = %h2 * %h3, %1 %b4 %h2 * %d3 %M5%!", | |
3609 | "%0 = %d2 * %h3, %1 %b4 %h2 * %d3 %M5%!", | |
3610 | "%0 = %h2 * %h3, %1 %b4 %d2 * %d3 %M5%!", | |
3611 | "%0 = %d2 * %h3, %1 %b4 %d2 * %d3 %M5%!", | |
3612 | "%0 = %h2 * %d3, %1 %b4 %h2 * %d3 %M5%!", | |
3613 | "%0 = %d2 * %d3, %1 %b4 %h2 * %d3 %M5%!", | |
3614 | "%0 = %h2 * %d3, %1 %b4 %d2 * %d3 %M5%!", | |
3615 | "%0 = %d2 * %d3, %1 %b4 %d2 * %d3 %M5%!" }; | |
3616 | int alt = (INTVAL (operands[4]) + (INTVAL (operands[5]) << 1) | |
3617 | + (INTVAL (operands[6]) << 2) + (INTVAL (operands[7]) << 3)); | |
3618 | xops[0] = operands[0]; | |
3619 | xops[1] = operands[1]; | |
3620 | xops[2] = operands[2]; | |
3621 | xops[3] = operands[3]; | |
3622 | xops[4] = operands[9]; | |
3623 | xops[5] = which_alternative == 0 ? operands[10] : operands[11]; | |
3624 | output_asm_insn (templates[alt], xops); | |
3625 | return ""; | |
3626 | } | |
3627 | [(set_attr "type" "dsp32")]) | |
3628 | ||
3629 | ||
3abcb3a7 | 3630 | (define_code_iterator s_or_u [sign_extend zero_extend]) |
2889abed BS |
3631 | (define_code_attr su_optab [(sign_extend "mul") |
3632 | (zero_extend "umul")]) | |
3633 | (define_code_attr su_modifier [(sign_extend "IS") | |
3634 | (zero_extend "FU")]) | |
3635 | ||
3636 | (define_insn "<su_optab>hisi_ll" | |
75d8b2d0 | 3637 | [(set (match_operand:SI 0 "register_operand" "=d") |
2889abed | 3638 | (mult:SI (s_or_u:SI |
75d8b2d0 BS |
3639 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d") |
3640 | (parallel [(const_int 0)]))) | |
2889abed | 3641 | (s_or_u:SI |
75d8b2d0 BS |
3642 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") |
3643 | (parallel [(const_int 0)])))))] | |
3644 | "" | |
2889abed | 3645 | "%0 = %h1 * %h2 (<su_modifier>)%!" |
75d8b2d0 BS |
3646 | [(set_attr "type" "dsp32")]) |
3647 | ||
2889abed | 3648 | (define_insn "<su_optab>hisi_lh" |
75d8b2d0 | 3649 | [(set (match_operand:SI 0 "register_operand" "=d") |
2889abed BS |
3650 | (mult:SI (s_or_u:SI |
3651 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
75d8b2d0 | 3652 | (parallel [(const_int 0)]))) |
2889abed | 3653 | (s_or_u:SI |
75d8b2d0 BS |
3654 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") |
3655 | (parallel [(const_int 1)])))))] | |
3656 | "" | |
2889abed | 3657 | "%0 = %h1 * %d2 (<su_modifier>)%!" |
75d8b2d0 BS |
3658 | [(set_attr "type" "dsp32")]) |
3659 | ||
2889abed | 3660 | (define_insn "<su_optab>hisi_hl" |
75d8b2d0 | 3661 | [(set (match_operand:SI 0 "register_operand" "=d") |
2889abed BS |
3662 | (mult:SI (s_or_u:SI |
3663 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3664 | (parallel [(const_int 1)]))) | |
3665 | (s_or_u:SI | |
3666 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3667 | (parallel [(const_int 0)])))))] | |
3668 | "" | |
3669 | "%0 = %d1 * %h2 (<su_modifier>)%!" | |
3670 | [(set_attr "type" "dsp32")]) | |
3671 | ||
3672 | (define_insn "<su_optab>hisi_hh" | |
3673 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3674 | (mult:SI (s_or_u:SI | |
75d8b2d0 BS |
3675 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d") |
3676 | (parallel [(const_int 1)]))) | |
2889abed BS |
3677 | (s_or_u:SI |
3678 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3679 | (parallel [(const_int 1)])))))] | |
3680 | "" | |
3681 | "%0 = %d1 * %d2 (<su_modifier>)%!" | |
3682 | [(set_attr "type" "dsp32")]) | |
3683 | ||
3684 | ;; Additional variants for signed * unsigned multiply. | |
3685 | ||
3686 | (define_insn "usmulhisi_ull" | |
3687 | [(set (match_operand:SI 0 "register_operand" "=W") | |
3688 | (mult:SI (zero_extend:SI | |
3689 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d") | |
3690 | (parallel [(const_int 0)]))) | |
75d8b2d0 BS |
3691 | (sign_extend:SI |
3692 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3693 | (parallel [(const_int 0)])))))] | |
3694 | "" | |
2889abed | 3695 | "%0 = %h2 * %h1 (IS,M)%!" |
75d8b2d0 BS |
3696 | [(set_attr "type" "dsp32")]) |
3697 | ||
2889abed BS |
3698 | (define_insn "usmulhisi_ulh" |
3699 | [(set (match_operand:SI 0 "register_operand" "=W") | |
3700 | (mult:SI (zero_extend:SI | |
3701 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3702 | (parallel [(const_int 0)]))) | |
3703 | (sign_extend:SI | |
3704 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3705 | (parallel [(const_int 1)])))))] | |
3706 | "" | |
3707 | "%0 = %d2 * %h1 (IS,M)%!" | |
3708 | [(set_attr "type" "dsp32")]) | |
3709 | ||
3710 | (define_insn "usmulhisi_uhl" | |
3711 | [(set (match_operand:SI 0 "register_operand" "=W") | |
3712 | (mult:SI (zero_extend:SI | |
3713 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3714 | (parallel [(const_int 1)]))) | |
3715 | (sign_extend:SI | |
3716 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3717 | (parallel [(const_int 0)])))))] | |
3718 | "" | |
3719 | "%0 = %h2 * %d1 (IS,M)%!" | |
3720 | [(set_attr "type" "dsp32")]) | |
3721 | ||
3722 | (define_insn "usmulhisi_uhh" | |
3723 | [(set (match_operand:SI 0 "register_operand" "=W") | |
3724 | (mult:SI (zero_extend:SI | |
75d8b2d0 BS |
3725 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d") |
3726 | (parallel [(const_int 1)]))) | |
3727 | (sign_extend:SI | |
3728 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3729 | (parallel [(const_int 1)])))))] | |
3730 | "" | |
2889abed BS |
3731 | "%0 = %d2 * %d1 (IS,M)%!" |
3732 | [(set_attr "type" "dsp32")]) | |
3733 | ||
3734 | ;; Parallel versions of these operations. First, normal signed or unsigned | |
3735 | ;; multiplies. | |
3736 | ||
3737 | (define_insn "<su_optab>hisi_ll_lh" | |
3738 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3739 | (mult:SI (s_or_u:SI | |
3740 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3741 | (parallel [(const_int 0)]))) | |
3742 | (s_or_u:SI | |
3743 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3744 | (parallel [(const_int 0)]))))) | |
3745 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3746 | (mult:SI (s_or_u:SI | |
3747 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3748 | (s_or_u:SI | |
3749 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3750 | "" | |
3751 | "%0 = %h1 * %h2, %3 = %h1 * %d2 (<su_modifier>)%!" | |
3752 | [(set_attr "type" "dsp32")]) | |
3753 | ||
3754 | (define_insn "<su_optab>hisi_ll_hl" | |
3755 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3756 | (mult:SI (s_or_u:SI | |
3757 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3758 | (parallel [(const_int 0)]))) | |
3759 | (s_or_u:SI | |
3760 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3761 | (parallel [(const_int 0)]))))) | |
3762 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3763 | (mult:SI (s_or_u:SI | |
3764 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3765 | (s_or_u:SI | |
3766 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3767 | "" | |
3768 | "%0 = %h1 * %h2, %3 = %d1 * %h2 (<su_modifier>)%!" | |
3769 | [(set_attr "type" "dsp32")]) | |
3770 | ||
3771 | (define_insn "<su_optab>hisi_ll_hh" | |
3772 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3773 | (mult:SI (s_or_u:SI | |
3774 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3775 | (parallel [(const_int 0)]))) | |
3776 | (s_or_u:SI | |
3777 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3778 | (parallel [(const_int 0)]))))) | |
3779 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3780 | (mult:SI (s_or_u:SI | |
3781 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3782 | (s_or_u:SI | |
3783 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3784 | "" | |
3785 | "%0 = %h1 * %h2, %3 = %d1 * %d2 (<su_modifier>)%!" | |
3786 | [(set_attr "type" "dsp32")]) | |
3787 | ||
3788 | (define_insn "<su_optab>hisi_lh_hl" | |
3789 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3790 | (mult:SI (s_or_u:SI | |
3791 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3792 | (parallel [(const_int 0)]))) | |
3793 | (s_or_u:SI | |
3794 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3795 | (parallel [(const_int 1)]))))) | |
3796 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3797 | (mult:SI (s_or_u:SI | |
3798 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3799 | (s_or_u:SI | |
3800 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3801 | "" | |
3802 | "%0 = %h1 * %d2, %3 = %d1 * %h2 (<su_modifier>)%!" | |
3803 | [(set_attr "type" "dsp32")]) | |
3804 | ||
3805 | (define_insn "<su_optab>hisi_lh_hh" | |
3806 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3807 | (mult:SI (s_or_u:SI | |
3808 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3809 | (parallel [(const_int 0)]))) | |
3810 | (s_or_u:SI | |
3811 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3812 | (parallel [(const_int 1)]))))) | |
3813 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3814 | (mult:SI (s_or_u:SI | |
3815 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3816 | (s_or_u:SI | |
3817 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3818 | "" | |
3819 | "%0 = %h1 * %d2, %3 = %d1 * %d2 (<su_modifier>)%!" | |
3820 | [(set_attr "type" "dsp32")]) | |
3821 | ||
3822 | (define_insn "<su_optab>hisi_hl_hh" | |
3823 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3824 | (mult:SI (s_or_u:SI | |
3825 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3826 | (parallel [(const_int 1)]))) | |
3827 | (s_or_u:SI | |
3828 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3829 | (parallel [(const_int 0)]))))) | |
3830 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3831 | (mult:SI (s_or_u:SI | |
3832 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3833 | (s_or_u:SI | |
3834 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3835 | "" | |
3836 | "%0 = %d1 * %h2, %3 = %d1 * %d2 (<su_modifier>)%!" | |
3837 | [(set_attr "type" "dsp32")]) | |
3838 | ||
3839 | ;; Special signed * unsigned variants. | |
3840 | ||
3841 | (define_insn "usmulhisi_ll_lul" | |
3842 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3843 | (mult:SI (sign_extend:SI | |
3844 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3845 | (parallel [(const_int 0)]))) | |
3846 | (sign_extend:SI | |
3847 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3848 | (parallel [(const_int 0)]))))) | |
3849 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3850 | (mult:SI (sign_extend:SI | |
3851 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3852 | (zero_extend:SI | |
3853 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3854 | "" | |
3855 | "%0 = %h1 * %h2, %3 = %h1 * %h2 (IS,M)%!" | |
3856 | [(set_attr "type" "dsp32")]) | |
3857 | ||
3858 | (define_insn "usmulhisi_ll_luh" | |
3859 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3860 | (mult:SI (sign_extend:SI | |
3861 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3862 | (parallel [(const_int 0)]))) | |
3863 | (sign_extend:SI | |
3864 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3865 | (parallel [(const_int 0)]))))) | |
3866 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3867 | (mult:SI (sign_extend:SI | |
3868 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3869 | (zero_extend:SI | |
3870 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3871 | "" | |
3872 | "%0 = %h1 * %h2, %3 = %h1 * %d2 (IS,M)%!" | |
3873 | [(set_attr "type" "dsp32")]) | |
3874 | ||
3875 | (define_insn "usmulhisi_ll_hul" | |
3876 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3877 | (mult:SI (sign_extend:SI | |
3878 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3879 | (parallel [(const_int 0)]))) | |
3880 | (sign_extend:SI | |
3881 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3882 | (parallel [(const_int 0)]))))) | |
3883 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3884 | (mult:SI (sign_extend:SI | |
3885 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3886 | (zero_extend:SI | |
3887 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3888 | "" | |
3889 | "%0 = %h1 * %h2, %3 = %d1 * %h2 (IS,M)%!" | |
3890 | [(set_attr "type" "dsp32")]) | |
3891 | ||
3892 | (define_insn "usmulhisi_ll_huh" | |
3893 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3894 | (mult:SI (sign_extend:SI | |
3895 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3896 | (parallel [(const_int 0)]))) | |
3897 | (sign_extend:SI | |
3898 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3899 | (parallel [(const_int 0)]))))) | |
3900 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3901 | (mult:SI (sign_extend:SI | |
3902 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3903 | (zero_extend:SI | |
3904 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3905 | "" | |
3906 | "%0 = %h1 * %h2, %3 = %d1 * %d2 (IS,M)%!" | |
3907 | [(set_attr "type" "dsp32")]) | |
3908 | ||
3909 | (define_insn "usmulhisi_lh_lul" | |
3910 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3911 | (mult:SI (sign_extend:SI | |
3912 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3913 | (parallel [(const_int 0)]))) | |
3914 | (sign_extend:SI | |
3915 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3916 | (parallel [(const_int 1)]))))) | |
3917 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3918 | (mult:SI (sign_extend:SI | |
3919 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3920 | (zero_extend:SI | |
3921 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3922 | "" | |
3923 | "%0 = %h1 * %d2, %3 = %h1 * %h2 (IS,M)%!" | |
3924 | [(set_attr "type" "dsp32")]) | |
3925 | ||
3926 | (define_insn "usmulhisi_lh_luh" | |
3927 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3928 | (mult:SI (sign_extend:SI | |
3929 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3930 | (parallel [(const_int 0)]))) | |
3931 | (sign_extend:SI | |
3932 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3933 | (parallel [(const_int 1)]))))) | |
3934 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3935 | (mult:SI (sign_extend:SI | |
3936 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3937 | (zero_extend:SI | |
3938 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3939 | "" | |
3940 | "%0 = %h1 * %d2, %3 = %h1 * %d2 (IS,M)%!" | |
3941 | [(set_attr "type" "dsp32")]) | |
3942 | ||
3943 | (define_insn "usmulhisi_lh_hul" | |
3944 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3945 | (mult:SI (sign_extend:SI | |
3946 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3947 | (parallel [(const_int 0)]))) | |
3948 | (sign_extend:SI | |
3949 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3950 | (parallel [(const_int 1)]))))) | |
3951 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3952 | (mult:SI (sign_extend:SI | |
3953 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3954 | (zero_extend:SI | |
3955 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3956 | "" | |
3957 | "%0 = %h1 * %d2, %3 = %d1 * %h2 (IS,M)%!" | |
3958 | [(set_attr "type" "dsp32")]) | |
3959 | ||
3960 | (define_insn "usmulhisi_lh_huh" | |
3961 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3962 | (mult:SI (sign_extend:SI | |
3963 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3964 | (parallel [(const_int 0)]))) | |
3965 | (sign_extend:SI | |
3966 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3967 | (parallel [(const_int 1)]))))) | |
3968 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3969 | (mult:SI (sign_extend:SI | |
3970 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3971 | (zero_extend:SI | |
3972 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3973 | "" | |
3974 | "%0 = %h1 * %d2, %3 = %d1 * %d2 (IS,M)%!" | |
3975 | [(set_attr "type" "dsp32")]) | |
3976 | ||
3977 | (define_insn "usmulhisi_hl_lul" | |
3978 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3979 | (mult:SI (sign_extend:SI | |
3980 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3981 | (parallel [(const_int 1)]))) | |
3982 | (sign_extend:SI | |
3983 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3984 | (parallel [(const_int 0)]))))) | |
3985 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3986 | (mult:SI (sign_extend:SI | |
3987 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3988 | (zero_extend:SI | |
3989 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3990 | "" | |
3991 | "%0 = %d1 * %h2, %3 = %h1 * %h2 (IS,M)%!" | |
3992 | [(set_attr "type" "dsp32")]) | |
3993 | ||
3994 | (define_insn "usmulhisi_hl_luh" | |
3995 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3996 | (mult:SI (sign_extend:SI | |
3997 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3998 | (parallel [(const_int 1)]))) | |
3999 | (sign_extend:SI | |
4000 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4001 | (parallel [(const_int 0)]))))) | |
4002 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4003 | (mult:SI (sign_extend:SI | |
4004 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
4005 | (zero_extend:SI | |
4006 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
4007 | "" | |
4008 | "%0 = %d1 * %h2, %3 = %h1 * %d2 (IS,M)%!" | |
4009 | [(set_attr "type" "dsp32")]) | |
4010 | ||
4011 | (define_insn "usmulhisi_hl_hul" | |
4012 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
4013 | (mult:SI (sign_extend:SI | |
4014 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4015 | (parallel [(const_int 1)]))) | |
4016 | (sign_extend:SI | |
4017 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4018 | (parallel [(const_int 0)]))))) | |
4019 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4020 | (mult:SI (sign_extend:SI | |
4021 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
4022 | (zero_extend:SI | |
4023 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
4024 | "" | |
4025 | "%0 = %d1 * %h2, %3 = %d1 * %h2 (IS,M)%!" | |
4026 | [(set_attr "type" "dsp32")]) | |
4027 | ||
4028 | (define_insn "usmulhisi_hl_huh" | |
4029 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
4030 | (mult:SI (sign_extend:SI | |
4031 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4032 | (parallel [(const_int 1)]))) | |
4033 | (sign_extend:SI | |
4034 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4035 | (parallel [(const_int 0)]))))) | |
4036 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4037 | (mult:SI (sign_extend:SI | |
4038 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
4039 | (zero_extend:SI | |
4040 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
4041 | "" | |
4042 | "%0 = %d1 * %h2, %3 = %d1 * %d2 (IS,M)%!" | |
4043 | [(set_attr "type" "dsp32")]) | |
4044 | ||
4045 | (define_insn "usmulhisi_hh_lul" | |
4046 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
4047 | (mult:SI (sign_extend:SI | |
4048 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4049 | (parallel [(const_int 1)]))) | |
4050 | (sign_extend:SI | |
4051 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4052 | (parallel [(const_int 1)]))))) | |
4053 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4054 | (mult:SI (sign_extend:SI | |
4055 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
4056 | (zero_extend:SI | |
4057 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
4058 | "" | |
4059 | "%0 = %d1 * %d2, %3 = %h1 * %h2 (IS,M)%!" | |
75d8b2d0 BS |
4060 | [(set_attr "type" "dsp32")]) |
4061 | ||
2889abed BS |
4062 | (define_insn "usmulhisi_hh_luh" |
4063 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
4064 | (mult:SI (sign_extend:SI | |
4065 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4066 | (parallel [(const_int 1)]))) | |
4067 | (sign_extend:SI | |
4068 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4069 | (parallel [(const_int 1)]))))) | |
4070 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4071 | (mult:SI (sign_extend:SI | |
4072 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
4073 | (zero_extend:SI | |
4074 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
4075 | "" | |
4076 | "%0 = %d1 * %d2, %3 = %h1 * %d2 (IS,M)%!" | |
4077 | [(set_attr "type" "dsp32")]) | |
4078 | ||
4079 | (define_insn "usmulhisi_hh_hul" | |
4080 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
4081 | (mult:SI (sign_extend:SI | |
4082 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4083 | (parallel [(const_int 1)]))) | |
4084 | (sign_extend:SI | |
4085 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4086 | (parallel [(const_int 1)]))))) | |
4087 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4088 | (mult:SI (sign_extend:SI | |
4089 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
4090 | (zero_extend:SI | |
4091 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
4092 | "" | |
4093 | "%0 = %d1 * %d2, %3 = %d1 * %h2 (IS,M)%!" | |
4094 | [(set_attr "type" "dsp32")]) | |
4095 | ||
4096 | (define_insn "usmulhisi_hh_huh" | |
4097 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
4098 | (mult:SI (sign_extend:SI | |
4099 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4100 | (parallel [(const_int 1)]))) | |
4101 | (sign_extend:SI | |
4102 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4103 | (parallel [(const_int 1)]))))) | |
4104 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4105 | (mult:SI (sign_extend:SI | |
4106 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
4107 | (zero_extend:SI | |
4108 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
4109 | "" | |
4110 | "%0 = %d1 * %d2, %3 = %d1 * %d2 (IS,M)%!" | |
4111 | [(set_attr "type" "dsp32")]) | |
4112 | ||
4113 | ;; Vector neg/abs. | |
4114 | ||
75d8b2d0 BS |
4115 | (define_insn "ssnegv2hi2" |
4116 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
4117 | (ss_neg:V2HI (match_operand:V2HI 1 "register_operand" "d")))] | |
0d4a78eb | 4118 | "" |
bbbc206e | 4119 | "%0 = - %1 (V)%!" |
0d4a78eb BS |
4120 | [(set_attr "type" "dsp32")]) |
4121 | ||
26c5953d | 4122 | (define_insn "ssabsv2hi2" |
0d4a78eb | 4123 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
26c5953d | 4124 | (ss_abs:V2HI (match_operand:V2HI 1 "register_operand" "d")))] |
0d4a78eb | 4125 | "" |
bbbc206e | 4126 | "%0 = ABS %1 (V)%!" |
0d4a78eb BS |
4127 | [(set_attr "type" "dsp32")]) |
4128 | ||
75d8b2d0 BS |
4129 | ;; Shifts. |
4130 | ||
4131 | (define_insn "ssashiftv2hi3" | |
4132 | [(set (match_operand:V2HI 0 "register_operand" "=d,d,d") | |
4133 | (if_then_else:V2HI | |
26c5953d | 4134 | (lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) |
75d8b2d0 BS |
4135 | (ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d") |
4136 | (match_dup 2)) | |
4137 | (ss_ashift:V2HI (match_dup 1) (match_dup 2))))] | |
4138 | "" | |
4139 | "@ | |
329437dd | 4140 | %0 = ASHIFT %1 BY %h2 (V, S)%! |
58f76679 BS |
4141 | %0 = %1 << %2 (V,S)%! |
4142 | %0 = %1 >>> %N2 (V,S)%!" | |
b3187e24 | 4143 | [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")]) |
75d8b2d0 BS |
4144 | |
4145 | (define_insn "ssashifthi3" | |
4146 | [(set (match_operand:HI 0 "register_operand" "=d,d,d") | |
4147 | (if_then_else:HI | |
26c5953d | 4148 | (lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) |
75d8b2d0 BS |
4149 | (ashiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d") |
4150 | (match_dup 2)) | |
4151 | (ss_ashift:HI (match_dup 1) (match_dup 2))))] | |
4152 | "" | |
4153 | "@ | |
329437dd | 4154 | %0 = ASHIFT %1 BY %h2 (V, S)%! |
58f76679 BS |
4155 | %0 = %1 << %2 (V,S)%! |
4156 | %0 = %1 >>> %N2 (V,S)%!" | |
b3187e24 | 4157 | [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")]) |
75d8b2d0 | 4158 | |
26c5953d BS |
4159 | (define_insn "ssashiftsi3" |
4160 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
4161 | (if_then_else:SI | |
4162 | (lt (match_operand:HI 2 "reg_or_const_int_operand" "d,Ku5,Ks5") (const_int 0)) | |
4163 | (ashiftrt:SI (match_operand:HI 1 "register_operand" "d,d,d") | |
4164 | (match_dup 2)) | |
4165 | (ss_ashift:SI (match_dup 1) (match_dup 2))))] | |
4166 | "" | |
4167 | "@ | |
4168 | %0 = ASHIFT %1 BY %h2 (S)%! | |
4169 | %0 = %1 << %2 (S)%! | |
4170 | %0 = %1 >>> %N2 (S)%!" | |
b3187e24 | 4171 | [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")]) |
26c5953d | 4172 | |
75d8b2d0 BS |
4173 | (define_insn "lshiftv2hi3" |
4174 | [(set (match_operand:V2HI 0 "register_operand" "=d,d,d") | |
4175 | (if_then_else:V2HI | |
26c5953d | 4176 | (lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) |
75d8b2d0 BS |
4177 | (lshiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d") |
4178 | (match_dup 2)) | |
4179 | (ashift:V2HI (match_dup 1) (match_dup 2))))] | |
4180 | "" | |
4181 | "@ | |
329437dd | 4182 | %0 = LSHIFT %1 BY %h2 (V)%! |
58f76679 BS |
4183 | %0 = %1 << %2 (V)%! |
4184 | %0 = %1 >> %N2 (V)%!" | |
b3187e24 | 4185 | [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")]) |
75d8b2d0 BS |
4186 | |
4187 | (define_insn "lshifthi3" | |
4188 | [(set (match_operand:HI 0 "register_operand" "=d,d,d") | |
4189 | (if_then_else:HI | |
26c5953d | 4190 | (lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) |
75d8b2d0 BS |
4191 | (lshiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d") |
4192 | (match_dup 2)) | |
4193 | (ashift:HI (match_dup 1) (match_dup 2))))] | |
4194 | "" | |
4195 | "@ | |
329437dd | 4196 | %0 = LSHIFT %1 BY %h2 (V)%! |
58f76679 BS |
4197 | %0 = %1 << %2 (V)%! |
4198 | %0 = %1 >> %N2 (V)%!" | |
b3187e24 | 4199 | [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")]) |
75d8b2d0 | 4200 | |
8fa477f7 BS |
4201 | ;; Load without alignment exception (masking off low bits) |
4202 | ||
4203 | (define_insn "loadbytes" | |
4204 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4205 | (mem:SI (and:SI (match_operand:SI 1 "register_operand" "b") | |
4206 | (const_int -4))))] | |
4207 | "" | |
4208 | "DISALGNEXCPT || %0 = [%1];" | |
4209 | [(set_attr "type" "mcld") | |
4210 | (set_attr "length" "8")]) | |
9840d30a BS |
4211 | |
4212 | (include "sync.md") |