]>
Commit | Line | Data |
---|---|---|
0d4a78eb | 1 | ;;- Machine description for Blackfin for GNU compiler |
818ab71a | 2 | ;; Copyright (C) 2005-2016 Free Software Foundation, Inc. |
0d4a78eb BS |
3 | ;; Contributed by Analog Devices. |
4 | ||
5 | ;; This file is part of GCC. | |
6 | ||
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | ;; by the Free Software Foundation; either version 3, or (at your |
0d4a78eb BS |
10 | ;; option) any later version. |
11 | ||
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | ;; along with GCC; see the file COPYING3. If not see |
19 | ;; <http://www.gnu.org/licenses/>. | |
0d4a78eb BS |
20 | |
21 | ; operand punctuation marks: | |
22 | ; | |
23 | ; X -- integer value printed as log2 | |
24 | ; Y -- integer value printed as log2(~value) - for bitclear | |
25 | ; h -- print half word register, low part | |
26 | ; d -- print half word register, high part | |
27 | ; D -- print operand as dregs pairs | |
28 | ; w -- print operand as accumulator register word (a0w, a1w) | |
29 | ; H -- high part of double mode operand | |
30 | ; T -- byte register representation Oct. 02 2001 | |
31 | ||
32 | ; constant operand classes | |
33 | ; | |
34 | ; J 2**N 5bit imm scaled | |
35 | ; Ks7 -64 .. 63 signed 7bit imm | |
36 | ; Ku5 0..31 unsigned 5bit imm | |
37 | ; Ks4 -8 .. 7 signed 4bit imm | |
38 | ; Ks3 -4 .. 3 signed 3bit imm | |
39 | ; Ku3 0 .. 7 unsigned 3bit imm | |
40 | ; Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n | |
41 | ; | |
42 | ; register operands | |
43 | ; d (r0..r7) | |
44 | ; a (p0..p5,fp,sp) | |
45 | ; e (a0, a1) | |
46 | ; b (i0..i3) | |
47 | ; f (m0..m3) | |
a9c46998 JZ |
48 | ; v (b0..b3) |
49 | ; c (i0..i3,m0..m3) CIRCREGS | |
50 | ; C (CC) CCREGS | |
b03149e1 JZ |
51 | ; t (lt0,lt1) |
52 | ; k (lc0,lc1) | |
a9c46998 | 53 | ; u (lb0,lb1) |
0d4a78eb BS |
54 | ; |
55 | ||
56 | ;; Define constants for hard registers. | |
57 | ||
58 | (define_constants | |
59 | [(REG_R0 0) | |
60 | (REG_R1 1) | |
61 | (REG_R2 2) | |
62 | (REG_R3 3) | |
63 | (REG_R4 4) | |
64 | (REG_R5 5) | |
65 | (REG_R6 6) | |
66 | (REG_R7 7) | |
67 | ||
68 | (REG_P0 8) | |
69 | (REG_P1 9) | |
70 | (REG_P2 10) | |
71 | (REG_P3 11) | |
72 | (REG_P4 12) | |
73 | (REG_P5 13) | |
74 | (REG_P6 14) | |
75 | (REG_P7 15) | |
76 | ||
77 | (REG_SP 14) | |
78 | (REG_FP 15) | |
79 | ||
80 | (REG_I0 16) | |
df259245 JZ |
81 | (REG_I1 17) |
82 | (REG_I2 18) | |
83 | (REG_I3 19) | |
84 | ||
85 | (REG_B0 20) | |
86 | (REG_B1 21) | |
87 | (REG_B2 22) | |
88 | (REG_B3 23) | |
89 | ||
90 | (REG_L0 24) | |
91 | (REG_L1 25) | |
92 | (REG_L2 26) | |
0d4a78eb BS |
93 | (REG_L3 27) |
94 | ||
95 | (REG_M0 28) | |
96 | (REG_M1 29) | |
97 | (REG_M2 30) | |
98 | (REG_M3 31) | |
99 | ||
100 | (REG_A0 32) | |
101 | (REG_A1 33) | |
102 | ||
103 | (REG_CC 34) | |
104 | (REG_RETS 35) | |
105 | (REG_RETI 36) | |
106 | (REG_RETX 37) | |
107 | (REG_RETN 38) | |
108 | (REG_RETE 39) | |
109 | ||
110 | (REG_ASTAT 40) | |
111 | (REG_SEQSTAT 41) | |
112 | (REG_USP 42) | |
113 | ||
b03149e1 JZ |
114 | (REG_ARGP 43) |
115 | ||
116 | (REG_LT0 44) | |
117 | (REG_LT1 45) | |
118 | (REG_LC0 46) | |
119 | (REG_LC1 47) | |
120 | (REG_LB0 48) | |
121 | (REG_LB1 49)]) | |
0d4a78eb BS |
122 | |
123 | ;; Constants used in UNSPECs and UNSPEC_VOLATILEs. | |
124 | ||
125 | (define_constants | |
126 | [(UNSPEC_CBRANCH_TAKEN 0) | |
127 | (UNSPEC_CBRANCH_NOPS 1) | |
128 | (UNSPEC_RETURN 2) | |
129 | (UNSPEC_MOVE_PIC 3) | |
130 | (UNSPEC_LIBRARY_OFFSET 4) | |
75d8b2d0 BS |
131 | (UNSPEC_PUSH_MULTIPLE 5) |
132 | ;; Multiply or MAC with extra CONST_INT operand specifying the macflag | |
133 | (UNSPEC_MUL_WITH_FLAG 6) | |
6614f9f5 BS |
134 | (UNSPEC_MAC_WITH_FLAG 7) |
135 | (UNSPEC_MOVE_FDPIC 8) | |
b03149e1 | 136 | (UNSPEC_FUNCDESC_GOT17M4 9) |
bbbc206e | 137 | (UNSPEC_LSETUP_END 10) |
942fd98f | 138 | ;; Distinguish a 32-bit version of an insn from a 16-bit version. |
b18e284e | 139 | (UNSPEC_32BIT 11) |
1d7d5ac4 | 140 | (UNSPEC_NOP 12) |
9840d30a BS |
141 | (UNSPEC_ONES 13) |
142 | (UNSPEC_ATOMIC 14)]) | |
0d4a78eb BS |
143 | |
144 | (define_constants | |
cd9c1ca8 | 145 | [(UNSPEC_VOLATILE_CSYNC 1) |
6614f9f5 | 146 | (UNSPEC_VOLATILE_SSYNC 2) |
1ca950ca | 147 | (UNSPEC_VOLATILE_LOAD_FUNCDESC 3) |
669eeb28 | 148 | (UNSPEC_VOLATILE_STORE_EH_HANDLER 4) |
c7cb1555 BS |
149 | (UNSPEC_VOLATILE_DUMMY 5) |
150 | (UNSPEC_VOLATILE_STALL 6)]) | |
0d4a78eb | 151 | |
75d8b2d0 BS |
152 | (define_constants |
153 | [(MACFLAG_NONE 0) | |
154 | (MACFLAG_T 1) | |
155 | (MACFLAG_FU 2) | |
156 | (MACFLAG_TFU 3) | |
157 | (MACFLAG_IS 4) | |
158 | (MACFLAG_IU 5) | |
159 | (MACFLAG_W32 6) | |
160 | (MACFLAG_M 7) | |
3efd5670 BS |
161 | (MACFLAG_IS_M 8) |
162 | (MACFLAG_S2RND 9) | |
163 | (MACFLAG_ISS2 10) | |
164 | (MACFLAG_IH 11)]) | |
75d8b2d0 | 165 | |
0d4a78eb | 166 | (define_attr "type" |
b3187e24 | 167 | "move,movcc,mvi,mcld,mcst,dsp32,dsp32shiftimm,mult,alu0,shft,brcc,br,call,misc,sync,compare,dummy,stall" |
0d4a78eb BS |
168 | (const_string "misc")) |
169 | ||
c7cb1555 | 170 | (define_attr "addrtype" "32bit,preg,spreg,ireg" |
36662eb1 | 171 | (cond [(and (eq_attr "type" "mcld") |
b3187e24 | 172 | (and (match_operand 0 "dp_register_operand" "") |
36662eb1 BS |
173 | (match_operand 1 "mem_p_address_operand" ""))) |
174 | (const_string "preg") | |
c7cb1555 | 175 | (and (eq_attr "type" "mcld") |
b3187e24 | 176 | (and (match_operand 0 "dp_register_operand" "") |
c7cb1555 BS |
177 | (match_operand 1 "mem_spfp_address_operand" ""))) |
178 | (const_string "spreg") | |
36662eb1 | 179 | (and (eq_attr "type" "mcld") |
b3187e24 | 180 | (and (match_operand 0 "dp_register_operand" "") |
36662eb1 BS |
181 | (match_operand 1 "mem_i_address_operand" ""))) |
182 | (const_string "ireg") | |
183 | (and (eq_attr "type" "mcst") | |
b3187e24 | 184 | (and (match_operand 1 "dp_register_operand" "") |
36662eb1 BS |
185 | (match_operand 0 "mem_p_address_operand" ""))) |
186 | (const_string "preg") | |
c7cb1555 | 187 | (and (eq_attr "type" "mcst") |
b3187e24 | 188 | (and (match_operand 1 "dp_register_operand" "") |
c7cb1555 BS |
189 | (match_operand 0 "mem_spfp_address_operand" ""))) |
190 | (const_string "spreg") | |
36662eb1 | 191 | (and (eq_attr "type" "mcst") |
b3187e24 | 192 | (and (match_operand 1 "dp_register_operand" "") |
36662eb1 BS |
193 | (match_operand 0 "mem_i_address_operand" ""))) |
194 | (const_string "ireg")] | |
195 | (const_string "32bit"))) | |
196 | ||
b3187e24 BS |
197 | (define_attr "storereg" "preg,other" |
198 | (cond [(and (eq_attr "type" "mcst") | |
199 | (match_operand 1 "p_register_operand" "")) | |
200 | (const_string "preg")] | |
201 | (const_string "other"))) | |
202 | ||
0d4a78eb BS |
203 | ;; Scheduling definitions |
204 | ||
205 | (define_automaton "bfin") | |
206 | ||
36662eb1 BS |
207 | (define_cpu_unit "slot0" "bfin") |
208 | (define_cpu_unit "slot1" "bfin") | |
209 | (define_cpu_unit "slot2" "bfin") | |
210 | ||
211 | ;; Three units used to enforce parallel issue restrictions: | |
942fd98f | 212 | ;; only one of the 16-bit slots can use a P register in an address, |
36662eb1 BS |
213 | ;; and only one them can be a store. |
214 | (define_cpu_unit "store" "bfin") | |
215 | (define_cpu_unit "pregs" "bfin") | |
216 | ||
c7cb1555 BS |
217 | ;; A dummy unit used to delay scheduling of loads after a conditional |
218 | ;; branch. | |
219 | (define_cpu_unit "load" "bfin") | |
220 | ||
b3187e24 BS |
221 | ;; A logical unit used to work around anomaly 05000074. |
222 | (define_cpu_unit "anomaly_05000074" "bfin") | |
223 | ||
36662eb1 | 224 | (define_reservation "core" "slot0+slot1+slot2") |
0d4a78eb BS |
225 | |
226 | (define_insn_reservation "alu" 1 | |
96f46444 | 227 | (eq_attr "type" "move,movcc,mvi,alu0,shft,brcc,br,call,misc,sync,compare") |
0d4a78eb BS |
228 | "core") |
229 | ||
230 | (define_insn_reservation "imul" 3 | |
231 | (eq_attr "type" "mult") | |
232 | "core*3") | |
233 | ||
36662eb1 BS |
234 | (define_insn_reservation "dsp32" 1 |
235 | (eq_attr "type" "dsp32") | |
236 | "slot0") | |
237 | ||
b3187e24 BS |
238 | (define_insn_reservation "dsp32shiftimm" 1 |
239 | (and (eq_attr "type" "dsp32shiftimm") | |
dd02d5ef | 240 | (not (match_test "ENABLE_WA_05000074"))) |
b3187e24 BS |
241 | "slot0") |
242 | ||
243 | (define_insn_reservation "dsp32shiftimm_anomaly_05000074" 1 | |
244 | (and (eq_attr "type" "dsp32shiftimm") | |
dd02d5ef | 245 | (match_test "ENABLE_WA_05000074")) |
b3187e24 BS |
246 | "slot0+anomaly_05000074") |
247 | ||
36662eb1 BS |
248 | (define_insn_reservation "load32" 1 |
249 | (and (not (eq_attr "seq_insns" "multi")) | |
250 | (and (eq_attr "type" "mcld") (eq_attr "addrtype" "32bit"))) | |
c7cb1555 | 251 | "core+load") |
36662eb1 BS |
252 | |
253 | (define_insn_reservation "loadp" 1 | |
254 | (and (not (eq_attr "seq_insns" "multi")) | |
255 | (and (eq_attr "type" "mcld") (eq_attr "addrtype" "preg"))) | |
b3187e24 | 256 | "slot1+pregs+load") |
c7cb1555 BS |
257 | |
258 | (define_insn_reservation "loadsp" 1 | |
259 | (and (not (eq_attr "seq_insns" "multi")) | |
260 | (and (eq_attr "type" "mcld") (eq_attr "addrtype" "spreg"))) | |
b3187e24 | 261 | "slot1+pregs") |
36662eb1 BS |
262 | |
263 | (define_insn_reservation "loadi" 1 | |
264 | (and (not (eq_attr "seq_insns" "multi")) | |
265 | (and (eq_attr "type" "mcld") (eq_attr "addrtype" "ireg"))) | |
c7cb1555 | 266 | "(slot1|slot2)+load") |
36662eb1 BS |
267 | |
268 | (define_insn_reservation "store32" 1 | |
269 | (and (not (eq_attr "seq_insns" "multi")) | |
270 | (and (eq_attr "type" "mcst") (eq_attr "addrtype" "32bit"))) | |
0d4a78eb BS |
271 | "core") |
272 | ||
36662eb1 | 273 | (define_insn_reservation "storep" 1 |
b3187e24 BS |
274 | (and (and (not (eq_attr "seq_insns" "multi")) |
275 | (and (eq_attr "type" "mcst") | |
276 | (ior (eq_attr "addrtype" "preg") | |
277 | (eq_attr "addrtype" "spreg")))) | |
dd02d5ef | 278 | (ior (not (match_test "ENABLE_WA_05000074")) |
b3187e24 BS |
279 | (eq_attr "storereg" "other"))) |
280 | "slot1+pregs+store") | |
281 | ||
282 | (define_insn_reservation "storep_anomaly_05000074" 1 | |
283 | (and (and (not (eq_attr "seq_insns" "multi")) | |
284 | (and (eq_attr "type" "mcst") | |
285 | (ior (eq_attr "addrtype" "preg") | |
286 | (eq_attr "addrtype" "spreg")))) | |
dd02d5ef | 287 | (and (match_test "ENABLE_WA_05000074") |
b3187e24 BS |
288 | (eq_attr "storereg" "preg"))) |
289 | "slot1+anomaly_05000074+pregs+store") | |
36662eb1 BS |
290 | |
291 | (define_insn_reservation "storei" 1 | |
b3187e24 BS |
292 | (and (and (not (eq_attr "seq_insns" "multi")) |
293 | (and (eq_attr "type" "mcst") (eq_attr "addrtype" "ireg"))) | |
dd02d5ef | 294 | (ior (not (match_test "ENABLE_WA_05000074")) |
b3187e24 | 295 | (eq_attr "storereg" "other"))) |
36662eb1 BS |
296 | "(slot1|slot2)+store") |
297 | ||
b3187e24 BS |
298 | (define_insn_reservation "storei_anomaly_05000074" 1 |
299 | (and (and (not (eq_attr "seq_insns" "multi")) | |
300 | (and (eq_attr "type" "mcst") (eq_attr "addrtype" "ireg"))) | |
dd02d5ef | 301 | (and (match_test "ENABLE_WA_05000074") |
b3187e24 BS |
302 | (eq_attr "storereg" "preg"))) |
303 | "((slot1+anomaly_05000074)|slot2)+store") | |
304 | ||
36662eb1 BS |
305 | (define_insn_reservation "multi" 2 |
306 | (eq_attr "seq_insns" "multi") | |
307 | "core") | |
308 | ||
c7cb1555 BS |
309 | (define_insn_reservation "load_stall1" 1 |
310 | (and (eq_attr "type" "stall") | |
311 | (match_operand 0 "const1_operand" "")) | |
312 | "core+load*2") | |
313 | ||
314 | (define_insn_reservation "load_stall3" 1 | |
315 | (and (eq_attr "type" "stall") | |
316 | (match_operand 0 "const3_operand" "")) | |
317 | "core+load*4") | |
318 | ||
36662eb1 BS |
319 | (absence_set "slot0" "slot1,slot2") |
320 | (absence_set "slot1" "slot2") | |
321 | ||
0d4a78eb BS |
322 | ;; Make sure genautomata knows about the maximum latency that can be produced |
323 | ;; by the adjust_cost function. | |
324 | (define_insn_reservation "dummy" 5 | |
36662eb1 | 325 | (eq_attr "type" "dummy") |
0d4a78eb BS |
326 | "core") |
327 | \f | |
328 | ;; Operand and operator predicates | |
329 | ||
330 | (include "predicates.md") | |
9fdd7520 | 331 | (include "constraints.md") |
0d4a78eb BS |
332 | \f |
333 | ;;; FRIO branches have been optimized for code density | |
334 | ;;; this comes at a slight cost of complexity when | |
335 | ;;; a compiler needs to generate branches in the general | |
336 | ;;; case. In order to generate the correct branching | |
337 | ;;; mechanisms the compiler needs keep track of instruction | |
338 | ;;; lengths. The follow table describes how to count instructions | |
339 | ;;; for the FRIO architecture. | |
340 | ;;; | |
341 | ;;; unconditional br are 12-bit imm pcrelative branches *2 | |
342 | ;;; conditional br are 10-bit imm pcrelative branches *2 | |
343 | ;;; brcc 10-bit: | |
344 | ;;; 1024 10-bit imm *2 is 2048 (-1024..1022) | |
345 | ;;; br 12-bit : | |
346 | ;;; 4096 12-bit imm *2 is 8192 (-4096..4094) | |
347 | ;;; NOTE : For brcc we generate instructions such as | |
348 | ;;; if cc jmp; jump.[sl] offset | |
349 | ;;; offset of jump.[sl] is from the jump instruction but | |
350 | ;;; gcc calculates length from the if cc jmp instruction | |
a2391c6a JZ |
351 | ;;; furthermore gcc takes the end address of the branch instruction |
352 | ;;; as (pc) for a forward branch | |
353 | ;;; hence our range is (-4094, 4092) instead of (-4096, 4094) for a br | |
0d4a78eb BS |
354 | ;;; |
355 | ;;; The way the (pc) rtx works in these calculations is somewhat odd; | |
356 | ;;; for backward branches it's the address of the current instruction, | |
357 | ;;; for forward branches it's the previously known address of the following | |
358 | ;;; instruction - we have to take this into account by reducing the range | |
359 | ;;; for a forward branch. | |
360 | ||
361 | ;; Lengths for type "mvi" insns are always defined by the instructions | |
362 | ;; themselves. | |
363 | (define_attr "length" "" | |
364 | (cond [(eq_attr "type" "mcld") | |
365 | (if_then_else (match_operand 1 "effective_address_32bit_p" "") | |
366 | (const_int 4) (const_int 2)) | |
367 | ||
368 | (eq_attr "type" "mcst") | |
369 | (if_then_else (match_operand 0 "effective_address_32bit_p" "") | |
370 | (const_int 4) (const_int 2)) | |
371 | ||
372 | (eq_attr "type" "move") (const_int 2) | |
373 | ||
374 | (eq_attr "type" "dsp32") (const_int 4) | |
b3187e24 | 375 | (eq_attr "type" "dsp32shiftimm") (const_int 4) |
0d4a78eb BS |
376 | (eq_attr "type" "call") (const_int 4) |
377 | ||
378 | (eq_attr "type" "br") | |
379 | (if_then_else (and | |
380 | (le (minus (match_dup 0) (pc)) (const_int 4092)) | |
381 | (ge (minus (match_dup 0) (pc)) (const_int -4096))) | |
382 | (const_int 2) | |
383 | (const_int 4)) | |
384 | ||
385 | (eq_attr "type" "brcc") | |
386 | (cond [(and | |
387 | (le (minus (match_dup 3) (pc)) (const_int 1020)) | |
388 | (ge (minus (match_dup 3) (pc)) (const_int -1024))) | |
389 | (const_int 2) | |
390 | (and | |
a2391c6a | 391 | (le (minus (match_dup 3) (pc)) (const_int 4092)) |
0d4a78eb BS |
392 | (ge (minus (match_dup 3) (pc)) (const_int -4094))) |
393 | (const_int 4)] | |
394 | (const_int 6)) | |
395 | ] | |
396 | ||
397 | (const_int 2))) | |
398 | ||
b03149e1 JZ |
399 | ;; Classify the insns into those that are one instruction and those that |
400 | ;; are more than one in sequence. | |
401 | (define_attr "seq_insns" "single,multi" | |
402 | (const_string "single")) | |
403 | ||
4ceb4242 BS |
404 | ;; Describe a user's asm statement. |
405 | (define_asm_attributes | |
406 | [(set_attr "type" "misc") | |
407 | (set_attr "seq_insns" "multi") | |
408 | (set_attr "length" "4")]) | |
409 | ||
0d4a78eb BS |
410 | ;; Conditional moves |
411 | ||
265b1d82 SH |
412 | (define_mode_iterator CCMOV [QI HI SI]) |
413 | ||
414 | (define_expand "mov<mode>cc" | |
415 | [(set (match_operand:CCMOV 0 "register_operand" "") | |
416 | (if_then_else:CCMOV (match_operand 1 "comparison_operator" "") | |
417 | (match_operand:CCMOV 2 "register_operand" "") | |
418 | (match_operand:CCMOV 3 "register_operand" "")))] | |
0d4a78eb BS |
419 | "" |
420 | { | |
265b1d82 | 421 | operands[1] = bfin_gen_compare (operands[1], <MODE>mode); |
0d4a78eb BS |
422 | }) |
423 | ||
265b1d82 SH |
424 | (define_insn "*mov<mode>cc_insn1" |
425 | [(set (match_operand:CCMOV 0 "register_operand" "=da,da,da") | |
426 | (if_then_else:CCMOV | |
4729dc92 | 427 | (eq:BI (match_operand:BI 3 "register_operand" "C,C,C") |
0d4a78eb | 428 | (const_int 0)) |
265b1d82 SH |
429 | (match_operand:CCMOV 1 "register_operand" "da,0,da") |
430 | (match_operand:CCMOV 2 "register_operand" "0,da,da")))] | |
0d4a78eb BS |
431 | "" |
432 | "@ | |
265b1d82 SH |
433 | if !cc %0 = %1; |
434 | if cc %0 = %2; | |
435 | if !cc %0 = %1; if cc %0 = %2;" | |
0d4a78eb | 436 | [(set_attr "length" "2,2,4") |
96f46444 | 437 | (set_attr "type" "movcc") |
b03149e1 | 438 | (set_attr "seq_insns" "*,*,multi")]) |
0d4a78eb | 439 | |
265b1d82 SH |
440 | (define_insn "*mov<mode>cc_insn2" |
441 | [(set (match_operand:CCMOV 0 "register_operand" "=da,da,da") | |
442 | (if_then_else:CCMOV | |
4729dc92 | 443 | (ne:BI (match_operand:BI 3 "register_operand" "C,C,C") |
0d4a78eb | 444 | (const_int 0)) |
265b1d82 SH |
445 | (match_operand:CCMOV 1 "register_operand" "0,da,da") |
446 | (match_operand:CCMOV 2 "register_operand" "da,0,da")))] | |
0d4a78eb BS |
447 | "" |
448 | "@ | |
265b1d82 SH |
449 | if !cc %0 = %2; |
450 | if cc %0 = %1; | |
451 | if cc %0 = %1; if !cc %0 = %2;" | |
0d4a78eb | 452 | [(set_attr "length" "2,2,4") |
96f46444 | 453 | (set_attr "type" "movcc") |
b03149e1 | 454 | (set_attr "seq_insns" "*,*,multi")]) |
0d4a78eb BS |
455 | |
456 | ;; Insns to load HIGH and LO_SUM | |
457 | ||
458 | (define_insn "movsi_high" | |
459 | [(set (match_operand:SI 0 "register_operand" "=x") | |
460 | (high:SI (match_operand:SI 1 "immediate_operand" "i")))] | |
461 | "reload_completed" | |
462 | "%d0 = %d1;" | |
463 | [(set_attr "type" "mvi") | |
464 | (set_attr "length" "4")]) | |
465 | ||
466 | (define_insn "movstricthi_high" | |
467 | [(set (match_operand:SI 0 "register_operand" "+x") | |
468 | (ior:SI (and:SI (match_dup 0) (const_int 65535)) | |
469 | (match_operand:SI 1 "immediate_operand" "i")))] | |
470 | "reload_completed" | |
471 | "%d0 = %d1;" | |
472 | [(set_attr "type" "mvi") | |
473 | (set_attr "length" "4")]) | |
474 | ||
475 | (define_insn "movsi_low" | |
476 | [(set (match_operand:SI 0 "register_operand" "=x") | |
477 | (lo_sum:SI (match_operand:SI 1 "register_operand" "0") | |
478 | (match_operand:SI 2 "immediate_operand" "i")))] | |
479 | "reload_completed" | |
480 | "%h0 = %h2;" | |
481 | [(set_attr "type" "mvi") | |
482 | (set_attr "length" "4")]) | |
483 | ||
484 | (define_insn "movsi_high_pic" | |
485 | [(set (match_operand:SI 0 "register_operand" "=x") | |
486 | (high:SI (unspec:SI [(match_operand:SI 1 "" "")] | |
487 | UNSPEC_MOVE_PIC)))] | |
488 | "" | |
489 | "%d0 = %1@GOT_LOW;" | |
490 | [(set_attr "type" "mvi") | |
491 | (set_attr "length" "4")]) | |
492 | ||
493 | (define_insn "movsi_low_pic" | |
494 | [(set (match_operand:SI 0 "register_operand" "=x") | |
495 | (lo_sum:SI (match_operand:SI 1 "register_operand" "0") | |
496 | (unspec:SI [(match_operand:SI 2 "" "")] | |
497 | UNSPEC_MOVE_PIC)))] | |
498 | "" | |
499 | "%h0 = %h2@GOT_HIGH;" | |
500 | [(set_attr "type" "mvi") | |
501 | (set_attr "length" "4")]) | |
502 | ||
503 | ;;; Move instructions | |
504 | ||
505 | (define_insn_and_split "movdi_insn" | |
506 | [(set (match_operand:DI 0 "nonimmediate_operand" "=x,mx,r") | |
507 | (match_operand:DI 1 "general_operand" "iFx,r,mx"))] | |
0ea80eb6 | 508 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG" |
0d4a78eb BS |
509 | "#" |
510 | "reload_completed" | |
511 | [(set (match_dup 2) (match_dup 3)) | |
512 | (set (match_dup 4) (match_dup 5))] | |
513 | { | |
514 | rtx lo_half[2], hi_half[2]; | |
515 | split_di (operands, 2, lo_half, hi_half); | |
516 | ||
517 | if (reg_overlap_mentioned_p (lo_half[0], hi_half[1])) | |
518 | { | |
519 | operands[2] = hi_half[0]; | |
520 | operands[3] = hi_half[1]; | |
521 | operands[4] = lo_half[0]; | |
522 | operands[5] = lo_half[1]; | |
523 | } | |
524 | else | |
525 | { | |
526 | operands[2] = lo_half[0]; | |
527 | operands[3] = lo_half[1]; | |
528 | operands[4] = hi_half[0]; | |
529 | operands[5] = hi_half[1]; | |
530 | } | |
531 | }) | |
532 | ||
533 | (define_insn "movbi" | |
669eeb28 BS |
534 | [(set (match_operand:BI 0 "nonimmediate_operand" "=x,x,d,md,C,d,C,P1") |
535 | (match_operand:BI 1 "general_operand" "x,xKs3,md,d,d,C,P0,P1"))] | |
0d4a78eb BS |
536 | |
537 | "" | |
538 | "@ | |
539 | %0 = %1; | |
540 | %0 = %1 (X); | |
bbbc206e | 541 | %0 = B %1 (Z)%! |
4729dc92 | 542 | B %0 = %1; |
0d4a78eb | 543 | CC = %1; |
49373252 | 544 | %0 = CC; |
669eeb28 BS |
545 | CC = R0 < R0; |
546 | CC = R0 == R0;" | |
547 | [(set_attr "type" "move,mvi,mcld,mcst,compare,compare,compare,compare") | |
548 | (set_attr "length" "2,2,*,*,2,2,2,2") | |
549 | (set_attr "seq_insns" "*,*,*,*,*,*,*,*")]) | |
0d4a78eb BS |
550 | |
551 | (define_insn "movpdi" | |
552 | [(set (match_operand:PDI 0 "nonimmediate_operand" "=e,<,e") | |
553 | (match_operand:PDI 1 "general_operand" " e,e,>"))] | |
554 | "" | |
555 | "@ | |
556 | %0 = %1; | |
557 | %0 = %x1; %0 = %w1; | |
558 | %w0 = %1; %x0 = %1;" | |
b03149e1 JZ |
559 | [(set_attr "type" "move,mcst,mcld") |
560 | (set_attr "seq_insns" "*,multi,multi")]) | |
0d4a78eb | 561 | |
75d8b2d0 BS |
562 | (define_insn "load_accumulator" |
563 | [(set (match_operand:PDI 0 "register_operand" "=e") | |
564 | (sign_extend:PDI (match_operand:SI 1 "register_operand" "d")))] | |
565 | "" | |
566 | "%0 = %1;" | |
567 | [(set_attr "type" "move")]) | |
568 | ||
569 | (define_insn_and_split "load_accumulator_pair" | |
570 | [(set (match_operand:V2PDI 0 "register_operand" "=e") | |
571 | (sign_extend:V2PDI (vec_concat:V2SI | |
572 | (match_operand:SI 1 "register_operand" "d") | |
573 | (match_operand:SI 2 "register_operand" "d"))))] | |
574 | "" | |
575 | "#" | |
576 | "reload_completed" | |
577 | [(set (match_dup 3) (sign_extend:PDI (match_dup 1))) | |
578 | (set (match_dup 4) (sign_extend:PDI (match_dup 2)))] | |
579 | { | |
580 | operands[3] = gen_rtx_REG (PDImode, REGNO (operands[0])); | |
581 | operands[4] = gen_rtx_REG (PDImode, REGNO (operands[0]) + 1); | |
582 | }) | |
583 | ||
0d4a78eb BS |
584 | (define_insn "*pushsi_insn" |
585 | [(set (mem:SI (pre_dec:SI (reg:SI REG_SP))) | |
586 | (match_operand:SI 0 "register_operand" "xy"))] | |
587 | "" | |
588 | "[--SP] = %0;" | |
589 | [(set_attr "type" "mcst") | |
35e3ced9 | 590 | (set_attr "addrtype" "32bit") |
0d4a78eb BS |
591 | (set_attr "length" "2")]) |
592 | ||
593 | (define_insn "*popsi_insn" | |
35e3ced9 | 594 | [(set (match_operand:SI 0 "register_operand" "=d,xy") |
0d4a78eb BS |
595 | (mem:SI (post_inc:SI (reg:SI REG_SP))))] |
596 | "" | |
bbbc206e | 597 | "%0 = [SP++]%!" |
0d4a78eb | 598 | [(set_attr "type" "mcld") |
35e3ced9 | 599 | (set_attr "addrtype" "preg,32bit") |
0d4a78eb BS |
600 | (set_attr "length" "2")]) |
601 | ||
602 | ;; The first alternative is used to make reload choose a limited register | |
603 | ;; class when faced with a movsi_insn that had its input operand replaced | |
604 | ;; with a PLUS. We generally require fewer secondary reloads this way. | |
0d4a78eb | 605 | |
b03149e1 | 606 | (define_insn "*movsi_insn" |
97a988bc BS |
607 | [(set (match_operand:SI 0 "nonimmediate_operand" "=da,x,da,y,da,x,x,x,da,mr") |
608 | (match_operand:SI 1 "general_operand" "da,x,y,da,xKs7,xKsh,xKuh,ix,mr,da"))] | |
0ea80eb6 | 609 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG" |
b03149e1 | 610 | "@ |
97a988bc BS |
611 | %0 = %1; |
612 | %0 = %1; | |
0d4a78eb BS |
613 | %0 = %1; |
614 | %0 = %1; | |
615 | %0 = %1 (X); | |
616 | %0 = %1 (X); | |
617 | %0 = %1 (Z); | |
618 | # | |
bbbc206e BS |
619 | %0 = %1%! |
620 | %0 = %1%!" | |
97a988bc BS |
621 | [(set_attr "type" "move,move,move,move,mvi,mvi,mvi,*,mcld,mcst") |
622 | (set_attr "length" "2,2,2,2,2,4,4,*,*,*")]) | |
0d4a78eb | 623 | |
bbbc206e BS |
624 | (define_insn "*movsi_insn32" |
625 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
626 | (unspec:SI [(match_operand:SI 1 "nonmemory_operand" "d,P0")] UNSPEC_32BIT))] | |
627 | "" | |
628 | "@ | |
629 | %0 = ROT %1 BY 0%! | |
630 | %0 = %0 -|- %0%!" | |
b3187e24 | 631 | [(set_attr "type" "dsp32shiftimm,dsp32")]) |
bbbc206e BS |
632 | |
633 | (define_split | |
634 | [(set (match_operand:SI 0 "d_register_operand" "") | |
635 | (const_int 0))] | |
636 | "splitting_for_sched && !optimize_size" | |
637 | [(set (match_dup 0) (unspec:SI [(const_int 0)] UNSPEC_32BIT))]) | |
638 | ||
639 | (define_split | |
640 | [(set (match_operand:SI 0 "d_register_operand" "") | |
641 | (match_operand:SI 1 "d_register_operand" ""))] | |
642 | "splitting_for_sched && !optimize_size" | |
643 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_32BIT))]) | |
644 | ||
75d8b2d0 BS |
645 | (define_insn_and_split "*movv2hi_insn" |
646 | [(set (match_operand:V2HI 0 "nonimmediate_operand" "=da,da,d,dm") | |
647 | (match_operand:V2HI 1 "general_operand" "i,di,md,d"))] | |
0d4a78eb | 648 | |
0ea80eb6 | 649 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG" |
75d8b2d0 BS |
650 | "@ |
651 | # | |
652 | %0 = %1; | |
bbbc206e BS |
653 | %0 = %1%! |
654 | %0 = %1%!" | |
75d8b2d0 BS |
655 | "reload_completed && GET_CODE (operands[1]) == CONST_VECTOR" |
656 | [(set (match_dup 0) (high:SI (match_dup 2))) | |
657 | (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 3)))] | |
658 | { | |
659 | HOST_WIDE_INT intval = INTVAL (XVECEXP (operands[1], 0, 1)) << 16; | |
660 | intval |= INTVAL (XVECEXP (operands[1], 0, 0)) & 0xFFFF; | |
554006bd | 661 | |
75d8b2d0 BS |
662 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[0])); |
663 | operands[2] = operands[3] = GEN_INT (trunc_int_for_mode (intval, SImode)); | |
664 | } | |
665 | [(set_attr "type" "move,move,mcld,mcst") | |
666 | (set_attr "length" "2,2,*,*")]) | |
0d4a78eb BS |
667 | |
668 | (define_insn "*movhi_insn" | |
669 | [(set (match_operand:HI 0 "nonimmediate_operand" "=x,da,x,d,mr") | |
670 | (match_operand:HI 1 "general_operand" "x,xKs7,xKsh,mr,d"))] | |
0ea80eb6 | 671 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG" |
c4963a0a BS |
672 | { |
673 | static const char *templates[] = { | |
674 | "%0 = %1;", | |
675 | "%0 = %1 (X);", | |
676 | "%0 = %1 (X);", | |
bbbc206e BS |
677 | "%0 = W %1 (X)%!", |
678 | "W %0 = %1%!", | |
679 | "%h0 = W %1%!", | |
680 | "W %0 = %h1%!" | |
c4963a0a BS |
681 | }; |
682 | int alt = which_alternative; | |
683 | rtx mem = (MEM_P (operands[0]) ? operands[0] | |
684 | : MEM_P (operands[1]) ? operands[1] : NULL_RTX); | |
685 | if (mem && bfin_dsp_memref_p (mem)) | |
686 | alt += 2; | |
687 | return templates[alt]; | |
688 | } | |
0d4a78eb BS |
689 | [(set_attr "type" "move,mvi,mvi,mcld,mcst") |
690 | (set_attr "length" "2,2,4,*,*")]) | |
691 | ||
692 | (define_insn "*movqi_insn" | |
693 | [(set (match_operand:QI 0 "nonimmediate_operand" "=x,da,x,d,mr") | |
694 | (match_operand:QI 1 "general_operand" "x,xKs7,xKsh,mr,d"))] | |
0ea80eb6 | 695 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG" |
0d4a78eb BS |
696 | "@ |
697 | %0 = %1; | |
698 | %0 = %1 (X); | |
699 | %0 = %1 (X); | |
bbbc206e BS |
700 | %0 = B %1 (X)%! |
701 | B %0 = %1%!" | |
0d4a78eb BS |
702 | [(set_attr "type" "move,mvi,mvi,mcld,mcst") |
703 | (set_attr "length" "2,2,4,*,*")]) | |
704 | ||
705 | (define_insn "*movsf_insn" | |
706 | [(set (match_operand:SF 0 "nonimmediate_operand" "=x,x,da,mr") | |
707 | (match_operand:SF 1 "general_operand" "x,Fx,mr,da"))] | |
0ea80eb6 | 708 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG" |
0d4a78eb BS |
709 | "@ |
710 | %0 = %1; | |
711 | # | |
bbbc206e BS |
712 | %0 = %1%! |
713 | %0 = %1%!" | |
0d4a78eb BS |
714 | [(set_attr "type" "move,*,mcld,mcst")]) |
715 | ||
716 | (define_insn_and_split "movdf_insn" | |
717 | [(set (match_operand:DF 0 "nonimmediate_operand" "=x,mx,r") | |
718 | (match_operand:DF 1 "general_operand" "iFx,r,mx"))] | |
0ea80eb6 | 719 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG" |
0d4a78eb BS |
720 | "#" |
721 | "reload_completed" | |
722 | [(set (match_dup 2) (match_dup 3)) | |
723 | (set (match_dup 4) (match_dup 5))] | |
724 | { | |
725 | rtx lo_half[2], hi_half[2]; | |
726 | split_di (operands, 2, lo_half, hi_half); | |
727 | ||
728 | if (reg_overlap_mentioned_p (lo_half[0], hi_half[1])) | |
729 | { | |
730 | operands[2] = hi_half[0]; | |
731 | operands[3] = hi_half[1]; | |
732 | operands[4] = lo_half[0]; | |
733 | operands[5] = lo_half[1]; | |
734 | } | |
735 | else | |
736 | { | |
737 | operands[2] = lo_half[0]; | |
738 | operands[3] = lo_half[1]; | |
739 | operands[4] = hi_half[0]; | |
740 | operands[5] = hi_half[1]; | |
741 | } | |
742 | }) | |
743 | ||
75d8b2d0 BS |
744 | ;; Storing halfwords. |
745 | (define_insn "*movsi_insv" | |
746 | [(set (zero_extract:SI (match_operand 0 "register_operand" "+d,x") | |
747 | (const_int 16) | |
748 | (const_int 16)) | |
749 | (match_operand:SI 1 "nonmemory_operand" "d,n"))] | |
750 | "" | |
751 | "@ | |
bbbc206e | 752 | %d0 = %h1 << 0%! |
75d8b2d0 | 753 | %d0 = %1;" |
b3187e24 | 754 | [(set_attr "type" "dsp32shiftimm,mvi")]) |
75d8b2d0 BS |
755 | |
756 | (define_expand "insv" | |
757 | [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "") | |
758 | (match_operand:SI 1 "immediate_operand" "") | |
759 | (match_operand:SI 2 "immediate_operand" "")) | |
760 | (match_operand:SI 3 "nonmemory_operand" ""))] | |
761 | "" | |
762 | { | |
763 | if (INTVAL (operands[1]) != 16 || INTVAL (operands[2]) != 16) | |
764 | FAIL; | |
765 | ||
766 | /* From mips.md: insert_bit_field doesn't verify that our source | |
767 | matches the predicate, so check it again here. */ | |
768 | if (! register_operand (operands[0], VOIDmode)) | |
769 | FAIL; | |
770 | }) | |
771 | ||
0d4a78eb BS |
772 | ;; This is the main "hook" for PIC code. When generating |
773 | ;; PIC, movsi is responsible for determining when the source address | |
774 | ;; needs PIC relocation and appropriately calling legitimize_pic_address | |
775 | ;; to perform the actual relocation. | |
776 | ||
777 | (define_expand "movsi" | |
778 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
779 | (match_operand:SI 1 "general_operand" ""))] | |
780 | "" | |
d6f6753e BS |
781 | { |
782 | if (expand_move (operands, SImode)) | |
783 | DONE; | |
784 | }) | |
0d4a78eb BS |
785 | |
786 | (define_expand "movv2hi" | |
787 | [(set (match_operand:V2HI 0 "nonimmediate_operand" "") | |
788 | (match_operand:V2HI 1 "general_operand" ""))] | |
789 | "" | |
790 | "expand_move (operands, V2HImode);") | |
791 | ||
792 | (define_expand "movdi" | |
793 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
794 | (match_operand:DI 1 "general_operand" ""))] | |
795 | "" | |
796 | "expand_move (operands, DImode);") | |
797 | ||
798 | (define_expand "movsf" | |
799 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
800 | (match_operand:SF 1 "general_operand" ""))] | |
801 | "" | |
802 | "expand_move (operands, SFmode);") | |
803 | ||
804 | (define_expand "movdf" | |
805 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
806 | (match_operand:DF 1 "general_operand" ""))] | |
807 | "" | |
808 | "expand_move (operands, DFmode);") | |
809 | ||
810 | (define_expand "movhi" | |
811 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
812 | (match_operand:HI 1 "general_operand" ""))] | |
813 | "" | |
814 | "expand_move (operands, HImode);") | |
815 | ||
816 | (define_expand "movqi" | |
817 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
818 | (match_operand:QI 1 "general_operand" ""))] | |
819 | "" | |
820 | " expand_move (operands, QImode); ") | |
821 | ||
822 | ;; Some define_splits to break up SI/SFmode loads of immediate constants. | |
823 | ||
824 | (define_split | |
825 | [(set (match_operand:SI 0 "register_operand" "") | |
826 | (match_operand:SI 1 "symbolic_or_const_operand" ""))] | |
827 | "reload_completed | |
828 | /* Always split symbolic operands; split integer constants that are | |
829 | too large for a single instruction. */ | |
830 | && (GET_CODE (operands[1]) != CONST_INT | |
831 | || (INTVAL (operands[1]) < -32768 | |
832 | || INTVAL (operands[1]) >= 65536 | |
833 | || (INTVAL (operands[1]) >= 32768 && PREG_P (operands[0]))))" | |
834 | [(set (match_dup 0) (high:SI (match_dup 1))) | |
835 | (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 1)))] | |
836 | { | |
837 | if (GET_CODE (operands[1]) == CONST_INT | |
838 | && split_load_immediate (operands)) | |
839 | DONE; | |
840 | /* ??? Do something about TARGET_LOW_64K. */ | |
841 | }) | |
842 | ||
843 | (define_split | |
844 | [(set (match_operand:SF 0 "register_operand" "") | |
845 | (match_operand:SF 1 "immediate_operand" ""))] | |
846 | "reload_completed" | |
847 | [(set (match_dup 2) (high:SI (match_dup 3))) | |
848 | (set (match_dup 2) (lo_sum:SI (match_dup 2) (match_dup 3)))] | |
849 | { | |
850 | long values; | |
0d4a78eb | 851 | |
3b9dd769 | 852 | gcc_assert (GET_CODE (operands[1]) == CONST_DOUBLE); |
0d4a78eb | 853 | |
34a72c33 | 854 | REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operands[1]), values); |
0d4a78eb BS |
855 | |
856 | operands[2] = gen_rtx_REG (SImode, true_regnum (operands[0])); | |
857 | operands[3] = GEN_INT (trunc_int_for_mode (values, SImode)); | |
858 | if (values >= -32768 && values < 65536) | |
859 | { | |
860 | emit_move_insn (operands[2], operands[3]); | |
861 | DONE; | |
862 | } | |
863 | if (split_load_immediate (operands + 2)) | |
864 | DONE; | |
865 | }) | |
866 | ||
867 | ;; Sadly, this can't be a proper named movstrict pattern, since the compiler | |
868 | ;; expects to be able to use registers for operand 1. | |
869 | ;; Note that the asm instruction is defined by the manual to take an unsigned | |
870 | ;; constant, but it doesn't matter to the assembler, and the compiler only | |
871 | ;; deals with sign-extended constants. Hence "Ksh". | |
75d8b2d0 | 872 | (define_insn "movstricthi_1" |
0d4a78eb BS |
873 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+x")) |
874 | (match_operand:HI 1 "immediate_operand" "Ksh"))] | |
875 | "" | |
876 | "%h0 = %1;" | |
877 | [(set_attr "type" "mvi") | |
878 | (set_attr "length" "4")]) | |
879 | ||
880 | ;; Sign and zero extensions | |
881 | ||
c4963a0a | 882 | (define_insn_and_split "extendhisi2" |
0d4a78eb BS |
883 | [(set (match_operand:SI 0 "register_operand" "=d, d") |
884 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))] | |
885 | "" | |
886 | "@ | |
887 | %0 = %h1 (X); | |
bbbc206e | 888 | %0 = W %h1 (X)%!" |
c4963a0a BS |
889 | "reload_completed && bfin_dsp_memref_p (operands[1])" |
890 | [(set (match_dup 2) (match_dup 1)) | |
891 | (set (match_dup 0) (sign_extend:SI (match_dup 2)))] | |
892 | { | |
893 | operands[2] = gen_lowpart (HImode, operands[0]); | |
894 | } | |
0d4a78eb BS |
895 | [(set_attr "type" "alu0,mcld")]) |
896 | ||
c4963a0a | 897 | (define_insn_and_split "zero_extendhisi2" |
0d4a78eb BS |
898 | [(set (match_operand:SI 0 "register_operand" "=d, d") |
899 | (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))] | |
900 | "" | |
901 | "@ | |
902 | %0 = %h1 (Z); | |
bbbc206e | 903 | %0 = W %h1 (Z)%!" |
c4963a0a BS |
904 | "reload_completed && bfin_dsp_memref_p (operands[1])" |
905 | [(set (match_dup 2) (match_dup 1)) | |
906 | (set (match_dup 0) (zero_extend:SI (match_dup 2)))] | |
907 | { | |
908 | operands[2] = gen_lowpart (HImode, operands[0]); | |
909 | } | |
0d4a78eb BS |
910 | [(set_attr "type" "alu0,mcld")]) |
911 | ||
912 | (define_insn "zero_extendbisi2" | |
913 | [(set (match_operand:SI 0 "register_operand" "=d") | |
914 | (zero_extend:SI (match_operand:BI 1 "nonimmediate_operand" "C")))] | |
915 | "" | |
916 | "%0 = %1;" | |
917 | [(set_attr "type" "compare")]) | |
918 | ||
919 | (define_insn "extendqihi2" | |
920 | [(set (match_operand:HI 0 "register_operand" "=d, d") | |
921 | (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] | |
922 | "" | |
923 | "@ | |
bbbc206e | 924 | %0 = B %1 (X)%! |
0d4a78eb BS |
925 | %0 = %T1 (X);" |
926 | [(set_attr "type" "mcld,alu0")]) | |
927 | ||
928 | (define_insn "extendqisi2" | |
929 | [(set (match_operand:SI 0 "register_operand" "=d, d") | |
930 | (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] | |
931 | "" | |
932 | "@ | |
bbbc206e | 933 | %0 = B %1 (X)%! |
0d4a78eb BS |
934 | %0 = %T1 (X);" |
935 | [(set_attr "type" "mcld,alu0")]) | |
936 | ||
937 | ||
938 | (define_insn "zero_extendqihi2" | |
939 | [(set (match_operand:HI 0 "register_operand" "=d, d") | |
940 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] | |
941 | "" | |
942 | "@ | |
bbbc206e | 943 | %0 = B %1 (Z)%! |
0d4a78eb BS |
944 | %0 = %T1 (Z);" |
945 | [(set_attr "type" "mcld,alu0")]) | |
946 | ||
947 | ||
948 | (define_insn "zero_extendqisi2" | |
949 | [(set (match_operand:SI 0 "register_operand" "=d, d") | |
950 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] | |
951 | "" | |
952 | "@ | |
bbbc206e | 953 | %0 = B %1 (Z)%! |
0d4a78eb BS |
954 | %0 = %T1 (Z);" |
955 | [(set_attr "type" "mcld,alu0")]) | |
956 | ||
957 | ;; DImode logical operations | |
958 | ||
3abcb3a7 | 959 | (define_code_iterator any_logical [and ior xor]) |
0d4a78eb BS |
960 | (define_code_attr optab [(and "and") |
961 | (ior "ior") | |
962 | (xor "xor")]) | |
963 | (define_code_attr op [(and "&") | |
964 | (ior "|") | |
965 | (xor "^")]) | |
966 | (define_code_attr high_result [(and "0") | |
967 | (ior "%H1") | |
968 | (xor "%H1")]) | |
969 | ||
e4fae5f7 BS |
970 | ;; Keep this pattern around to avoid generating NO_CONFLICT blocks. |
971 | (define_expand "<optab>di3" | |
0d4a78eb BS |
972 | [(set (match_operand:DI 0 "register_operand" "=d") |
973 | (any_logical:DI (match_operand:DI 1 "register_operand" "0") | |
e4fae5f7 | 974 | (match_operand:DI 2 "general_operand" "d")))] |
0d4a78eb | 975 | "" |
0d4a78eb | 976 | { |
e4fae5f7 BS |
977 | rtx hi_half[3], lo_half[3]; |
978 | enum insn_code icode = CODE_FOR_<optab>si3; | |
979 | if (!reg_overlap_mentioned_p (operands[0], operands[1]) | |
980 | && !reg_overlap_mentioned_p (operands[0], operands[2])) | |
c41c1387 | 981 | emit_clobber (operands[0]); |
e4fae5f7 BS |
982 | split_di (operands, 3, lo_half, hi_half); |
983 | if (!(*insn_data[icode].operand[2].predicate) (lo_half[2], SImode)) | |
984 | lo_half[2] = force_reg (SImode, lo_half[2]); | |
985 | emit_insn (GEN_FCN (icode) (lo_half[0], lo_half[1], lo_half[2])); | |
986 | if (!(*insn_data[icode].operand[2].predicate) (hi_half[2], SImode)) | |
987 | hi_half[2] = force_reg (SImode, hi_half[2]); | |
988 | emit_insn (GEN_FCN (icode) (hi_half[0], hi_half[1], hi_half[2])); | |
989 | DONE; | |
0d4a78eb BS |
990 | }) |
991 | ||
992 | (define_insn "zero_extendqidi2" | |
993 | [(set (match_operand:DI 0 "register_operand" "=d") | |
994 | (zero_extend:DI (match_operand:QI 1 "register_operand" "d")))] | |
995 | "" | |
996 | "%0 = %T1 (Z);\\n\\t%H0 = 0;" | |
b03149e1 JZ |
997 | [(set_attr "length" "4") |
998 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
999 | |
1000 | (define_insn "zero_extendhidi2" | |
1001 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1002 | (zero_extend:DI (match_operand:HI 1 "register_operand" "d")))] | |
1003 | "" | |
1004 | "%0 = %h1 (Z);\\n\\t%H0 = 0;" | |
b03149e1 JZ |
1005 | [(set_attr "length" "4") |
1006 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
1007 | |
1008 | (define_insn_and_split "extendsidi2" | |
1009 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1010 | (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))] | |
1011 | "" | |
1012 | "#" | |
1013 | "reload_completed" | |
1014 | [(set (match_dup 3) (match_dup 1)) | |
1015 | (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))] | |
1016 | { | |
1017 | split_di (operands, 1, operands + 2, operands + 3); | |
1018 | if (REGNO (operands[0]) != REGNO (operands[1])) | |
1019 | emit_move_insn (operands[2], operands[1]); | |
1020 | }) | |
1021 | ||
1022 | (define_insn_and_split "extendqidi2" | |
1023 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1024 | (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))] | |
1025 | "" | |
1026 | "#" | |
1027 | "reload_completed" | |
1028 | [(set (match_dup 2) (sign_extend:SI (match_dup 1))) | |
1029 | (set (match_dup 3) (sign_extend:SI (match_dup 1))) | |
1030 | (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))] | |
1031 | { | |
1032 | split_di (operands, 1, operands + 2, operands + 3); | |
1033 | }) | |
1034 | ||
1035 | (define_insn_and_split "extendhidi2" | |
1036 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1037 | (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))] | |
1038 | "" | |
1039 | "#" | |
1040 | "reload_completed" | |
1041 | [(set (match_dup 2) (sign_extend:SI (match_dup 1))) | |
1042 | (set (match_dup 3) (sign_extend:SI (match_dup 1))) | |
1043 | (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))] | |
1044 | { | |
1045 | split_di (operands, 1, operands + 2, operands + 3); | |
1046 | }) | |
1047 | ||
1048 | ;; DImode arithmetic operations | |
1049 | ||
2889abed BS |
1050 | (define_insn "add_with_carry" |
1051 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
e4fae5f7 | 1052 | (plus:SI (match_operand:SI 1 "register_operand" "%0,d") |
2889abed | 1053 | (match_operand:SI 2 "nonmemory_operand" "Ks7,d"))) |
e4fae5f7 BS |
1054 | (set (match_operand:BI 3 "register_operand" "=C,C") |
1055 | (ltu:BI (not:SI (match_dup 1)) (match_dup 2)))] | |
2889abed BS |
1056 | "" |
1057 | "@ | |
e4fae5f7 BS |
1058 | %0 += %2; cc = ac0; |
1059 | %0 = %1 + %2; cc = ac0;" | |
2889abed | 1060 | [(set_attr "type" "alu0") |
e4fae5f7 | 1061 | (set_attr "length" "4") |
2889abed BS |
1062 | (set_attr "seq_insns" "multi")]) |
1063 | ||
e4fae5f7 BS |
1064 | (define_insn "sub_with_carry" |
1065 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1066 | (minus:SI (match_operand:SI 1 "register_operand" "%d") | |
1067 | (match_operand:SI 2 "nonmemory_operand" "d"))) | |
1068 | (set (match_operand:BI 3 "register_operand" "=C") | |
1069 | (leu:BI (match_dup 2) (match_dup 1)))] | |
0d4a78eb | 1070 | "" |
e4fae5f7 | 1071 | "%0 = %1 - %2; cc = ac0;" |
0d4a78eb | 1072 | [(set_attr "type" "alu0") |
e4fae5f7 | 1073 | (set_attr "length" "4") |
b03149e1 | 1074 | (set_attr "seq_insns" "multi")]) |
0d4a78eb | 1075 | |
e4fae5f7 BS |
1076 | (define_expand "adddi3" |
1077 | [(set (match_operand:DI 0 "register_operand" "") | |
1078 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
1079 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
1080 | (clobber (match_scratch:SI 3 "")) | |
0d4a78eb BS |
1081 | (clobber (reg:CC 34))] |
1082 | "" | |
e4fae5f7 BS |
1083 | { |
1084 | rtx xops[8]; | |
1085 | xops[0] = gen_lowpart (SImode, operands[0]); | |
1086 | xops[1] = simplify_gen_subreg (SImode, operands[0], DImode, 4); | |
1087 | xops[2] = gen_lowpart (SImode, operands[1]); | |
1088 | xops[3] = simplify_gen_subreg (SImode, operands[1], DImode, 4); | |
1089 | xops[4] = gen_lowpart (SImode, operands[2]); | |
1090 | xops[5] = simplify_gen_subreg (SImode, operands[2], DImode, 4); | |
1091 | xops[6] = gen_reg_rtx (SImode); | |
1092 | xops[7] = gen_rtx_REG (BImode, REG_CC); | |
1093 | if (!register_operand (xops[4], SImode) | |
1094 | && (GET_CODE (xops[4]) != CONST_INT | |
9fdd7520 | 1095 | || !satisfies_constraint_Ks7 (xops[4]))) |
e4fae5f7 BS |
1096 | xops[4] = force_reg (SImode, xops[4]); |
1097 | if (!reg_overlap_mentioned_p (operands[0], operands[1]) | |
1098 | && !reg_overlap_mentioned_p (operands[0], operands[2])) | |
c41c1387 | 1099 | emit_clobber (operands[0]); |
e4fae5f7 BS |
1100 | emit_insn (gen_add_with_carry (xops[0], xops[2], xops[4], xops[7])); |
1101 | emit_insn (gen_movbisi (xops[6], xops[7])); | |
1102 | if (!register_operand (xops[5], SImode) | |
1103 | && (GET_CODE (xops[5]) != CONST_INT | |
9fdd7520 | 1104 | || !satisfies_constraint_Ks7 (xops[5]))) |
e4fae5f7 BS |
1105 | xops[5] = force_reg (SImode, xops[5]); |
1106 | if (xops[5] != const0_rtx) | |
1107 | emit_insn (gen_addsi3 (xops[1], xops[3], xops[5])); | |
1108 | else | |
1109 | emit_move_insn (xops[1], xops[3]); | |
1110 | emit_insn (gen_addsi3 (xops[1], xops[1], xops[6])); | |
1111 | DONE; | |
1112 | }) | |
0d4a78eb | 1113 | |
e4fae5f7 BS |
1114 | (define_expand "subdi3" |
1115 | [(set (match_operand:DI 0 "register_operand" "") | |
1116 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
1117 | (match_operand:DI 2 "register_operand" ""))) | |
0d4a78eb BS |
1118 | (clobber (reg:CC 34))] |
1119 | "" | |
e4fae5f7 BS |
1120 | { |
1121 | rtx xops[8]; | |
1122 | xops[0] = gen_lowpart (SImode, operands[0]); | |
1123 | xops[1] = simplify_gen_subreg (SImode, operands[0], DImode, 4); | |
1124 | xops[2] = gen_lowpart (SImode, operands[1]); | |
1125 | xops[3] = simplify_gen_subreg (SImode, operands[1], DImode, 4); | |
1126 | xops[4] = gen_lowpart (SImode, operands[2]); | |
1127 | xops[5] = simplify_gen_subreg (SImode, operands[2], DImode, 4); | |
1128 | xops[6] = gen_reg_rtx (SImode); | |
1129 | xops[7] = gen_rtx_REG (BImode, REG_CC); | |
1130 | if (!reg_overlap_mentioned_p (operands[0], operands[1]) | |
1131 | && !reg_overlap_mentioned_p (operands[0], operands[2])) | |
c41c1387 | 1132 | emit_clobber (operands[0]); |
e4fae5f7 BS |
1133 | emit_insn (gen_sub_with_carry (xops[0], xops[2], xops[4], xops[7])); |
1134 | emit_insn (gen_notbi (xops[7], xops[7])); | |
1135 | emit_insn (gen_movbisi (xops[6], xops[7])); | |
1136 | emit_insn (gen_subsi3 (xops[1], xops[3], xops[5])); | |
1137 | emit_insn (gen_subsi3 (xops[1], xops[1], xops[6])); | |
1138 | DONE; | |
1139 | }) | |
0d4a78eb BS |
1140 | |
1141 | ;; Combined shift/add instructions | |
1142 | ||
1143 | (define_insn "" | |
1144 | [(set (match_operand:SI 0 "register_operand" "=a,d") | |
1145 | (ashift:SI (plus:SI (match_operand:SI 1 "register_operand" "%0,0") | |
1146 | (match_operand:SI 2 "register_operand" "a,d")) | |
1147 | (match_operand:SI 3 "pos_scale_operand" "P1P2,P1P2")))] | |
1148 | "" | |
1149 | "%0 = (%0 + %2) << %3;" /* "shadd %0,%2,%3;" */ | |
1150 | [(set_attr "type" "alu0")]) | |
1151 | ||
1152 | (define_insn "" | |
1153 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1154 | (plus:SI (match_operand:SI 1 "register_operand" "a") | |
1155 | (mult:SI (match_operand:SI 2 "register_operand" "a") | |
1156 | (match_operand:SI 3 "scale_by_operand" "i"))))] | |
1157 | "" | |
1158 | "%0 = %1 + (%2 << %X3);" | |
1159 | [(set_attr "type" "alu0")]) | |
1160 | ||
1161 | (define_insn "" | |
1162 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1163 | (plus:SI (match_operand:SI 1 "register_operand" "a") | |
1164 | (ashift:SI (match_operand:SI 2 "register_operand" "a") | |
1165 | (match_operand:SI 3 "pos_scale_operand" "i"))))] | |
1166 | "" | |
1167 | "%0 = %1 + (%2 << %3);" | |
1168 | [(set_attr "type" "alu0")]) | |
1169 | ||
1170 | (define_insn "" | |
1171 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1172 | (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "a") | |
1173 | (match_operand:SI 2 "scale_by_operand" "i")) | |
1174 | (match_operand:SI 3 "register_operand" "a")))] | |
1175 | "" | |
1176 | "%0 = %3 + (%1 << %X2);" | |
1177 | [(set_attr "type" "alu0")]) | |
1178 | ||
1179 | (define_insn "" | |
1180 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1181 | (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "a") | |
1182 | (match_operand:SI 2 "pos_scale_operand" "i")) | |
1183 | (match_operand:SI 3 "register_operand" "a")))] | |
1184 | "" | |
1185 | "%0 = %3 + (%1 << %2);" | |
1186 | [(set_attr "type" "alu0")]) | |
1187 | ||
1188 | (define_insn "mulhisi3" | |
1189 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1190 | (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%d")) | |
1191 | (sign_extend:SI (match_operand:HI 2 "register_operand" "d"))))] | |
1192 | "" | |
bbbc206e | 1193 | "%0 = %h1 * %h2 (IS)%!" |
0d4a78eb BS |
1194 | [(set_attr "type" "dsp32")]) |
1195 | ||
1196 | (define_insn "umulhisi3" | |
1197 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1198 | (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%d")) | |
1199 | (zero_extend:SI (match_operand:HI 2 "register_operand" "d"))))] | |
1200 | "" | |
bbbc206e | 1201 | "%0 = %h1 * %h2 (FU)%!" |
0d4a78eb BS |
1202 | [(set_attr "type" "dsp32")]) |
1203 | ||
8b44057d BS |
1204 | (define_insn "usmulhisi3" |
1205 | [(set (match_operand:SI 0 "register_operand" "=W") | |
1206 | (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "W")) | |
1207 | (sign_extend:SI (match_operand:HI 2 "register_operand" "W"))))] | |
1208 | "" | |
bbbc206e | 1209 | "%0 = %h2 * %h1 (IS,M)%!" |
8b44057d BS |
1210 | [(set_attr "type" "dsp32")]) |
1211 | ||
9b19b026 SH |
1212 | ;; The alternative involving IREGS requires that the corresponding L register |
1213 | ;; is zero. | |
0d4a78eb BS |
1214 | |
1215 | (define_insn "addsi3" | |
9b19b026 SH |
1216 | [(set (match_operand:SI 0 "register_operand" "=ad,a,d,b") |
1217 | (plus:SI (match_operand:SI 1 "register_operand" "%0, a,d,0") | |
1218 | (match_operand:SI 2 "reg_or_7bit_operand" "Ks7, a,d,fP2P4")))] | |
0d4a78eb BS |
1219 | "" |
1220 | "@ | |
1221 | %0 += %2; | |
1222 | %0 = %1 + %2; | |
9b19b026 SH |
1223 | %0 = %1 + %2; |
1224 | %0 += %2;" | |
0d4a78eb | 1225 | [(set_attr "type" "alu0") |
9b19b026 | 1226 | (set_attr "length" "2,2,2,2")]) |
0d4a78eb | 1227 | |
75d8b2d0 BS |
1228 | (define_insn "ssaddsi3" |
1229 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1230 | (ss_plus:SI (match_operand:SI 1 "register_operand" "d") | |
1231 | (match_operand:SI 2 "register_operand" "d")))] | |
1232 | "" | |
bbbc206e | 1233 | "%0 = %1 + %2 (S)%!" |
75d8b2d0 BS |
1234 | [(set_attr "type" "dsp32")]) |
1235 | ||
d4e85050 | 1236 | (define_insn "subsi3" |
0d4a78eb BS |
1237 | [(set (match_operand:SI 0 "register_operand" "=da,d,a") |
1238 | (minus:SI (match_operand:SI 1 "register_operand" "0,d,0") | |
d4e85050 BS |
1239 | (match_operand:SI 2 "reg_or_neg7bit_operand" "KN7,d,a")))] |
1240 | "" | |
0d4a78eb BS |
1241 | { |
1242 | static const char *const strings_subsi3[] = { | |
1243 | "%0 += -%2;", | |
1244 | "%0 = %1 - %2;", | |
1245 | "%0 -= %2;", | |
1246 | }; | |
1247 | ||
1248 | if (CONSTANT_P (operands[2]) && INTVAL (operands[2]) < 0) { | |
1249 | rtx tmp_op = operands[2]; | |
1250 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
1251 | output_asm_insn ("%0 += %2;", operands); | |
1252 | operands[2] = tmp_op; | |
1253 | return ""; | |
1254 | } | |
1255 | ||
1256 | return strings_subsi3[which_alternative]; | |
1257 | } | |
1258 | [(set_attr "type" "alu0")]) | |
1259 | ||
75d8b2d0 BS |
1260 | (define_insn "sssubsi3" |
1261 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1262 | (ss_minus:SI (match_operand:SI 1 "register_operand" "d") | |
1263 | (match_operand:SI 2 "register_operand" "d")))] | |
1264 | "" | |
bbbc206e | 1265 | "%0 = %1 - %2 (S)%!" |
75d8b2d0 BS |
1266 | [(set_attr "type" "dsp32")]) |
1267 | ||
3efd5670 BS |
1268 | ;; Accumulator addition |
1269 | ||
314f9913 BS |
1270 | (define_insn "addpdi3" |
1271 | [(set (match_operand:PDI 0 "register_operand" "=A") | |
1272 | (ss_plus:PDI (match_operand:PDI 1 "register_operand" "%0") | |
1273 | (match_operand:PDI 2 "nonmemory_operand" "B")))] | |
1274 | "" | |
1275 | "A0 += A1%!" | |
1276 | [(set_attr "type" "dsp32")]) | |
1277 | ||
3efd5670 BS |
1278 | (define_insn "sum_of_accumulators" |
1279 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1280 | (ss_truncate:SI | |
1281 | (ss_plus:PDI (match_operand:PDI 2 "register_operand" "1") | |
1282 | (match_operand:PDI 3 "register_operand" "B")))) | |
1283 | (set (match_operand:PDI 1 "register_operand" "=A") | |
1284 | (ss_plus:PDI (match_dup 2) (match_dup 3)))] | |
1285 | "" | |
1286 | "%0 = (A0 += A1)%!" | |
1287 | [(set_attr "type" "dsp32")]) | |
1288 | ||
314f9913 BS |
1289 | (define_insn "us_truncpdisi2" |
1290 | [(set (match_operand:SI 0 "register_operand" "=D,W") | |
1291 | (us_truncate:SI (match_operand:PDI 1 "register_operand" "A,B")))] | |
1292 | "" | |
1293 | "%0 = %1 (FU)%!" | |
1294 | [(set_attr "type" "dsp32")]) | |
1295 | ||
0d4a78eb BS |
1296 | ;; Bit test instructions |
1297 | ||
1298 | (define_insn "*not_bittst" | |
4729dc92 | 1299 | [(set (match_operand:BI 0 "register_operand" "=C") |
0d4a78eb BS |
1300 | (eq:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d") |
1301 | (const_int 1) | |
1302 | (match_operand:SI 2 "immediate_operand" "Ku5")) | |
1303 | (const_int 0)))] | |
1304 | "" | |
1305 | "cc = !BITTST (%1,%2);" | |
1306 | [(set_attr "type" "alu0")]) | |
1307 | ||
1308 | (define_insn "*bittst" | |
4729dc92 | 1309 | [(set (match_operand:BI 0 "register_operand" "=C") |
0d4a78eb BS |
1310 | (ne:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d") |
1311 | (const_int 1) | |
1312 | (match_operand:SI 2 "immediate_operand" "Ku5")) | |
1313 | (const_int 0)))] | |
1314 | "" | |
1315 | "cc = BITTST (%1,%2);" | |
1316 | [(set_attr "type" "alu0")]) | |
1317 | ||
1318 | (define_insn_and_split "*bit_extract" | |
1319 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1320 | (zero_extract:SI (match_operand:SI 1 "register_operand" "d") | |
1321 | (const_int 1) | |
1322 | (match_operand:SI 2 "immediate_operand" "Ku5"))) | |
1323 | (clobber (reg:BI REG_CC))] | |
1324 | "" | |
1325 | "#" | |
1326 | "" | |
1327 | [(set (reg:BI REG_CC) | |
1328 | (ne:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2)) | |
1329 | (const_int 0))) | |
1330 | (set (match_dup 0) | |
1331 | (ne:SI (reg:BI REG_CC) (const_int 0)))]) | |
1332 | ||
1333 | (define_insn_and_split "*not_bit_extract" | |
1334 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1335 | (zero_extract:SI (not:SI (match_operand:SI 1 "register_operand" "d")) | |
1336 | (const_int 1) | |
1337 | (match_operand:SI 2 "immediate_operand" "Ku5"))) | |
1338 | (clobber (reg:BI REG_CC))] | |
1339 | "" | |
1340 | "#" | |
1341 | "" | |
1342 | [(set (reg:BI REG_CC) | |
1343 | (eq:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2)) | |
1344 | (const_int 0))) | |
1345 | (set (match_dup 0) | |
1346 | (ne:SI (reg:BI REG_CC) (const_int 0)))]) | |
1347 | ||
1348 | (define_insn "*andsi_insn" | |
1349 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") | |
1350 | (and:SI (match_operand:SI 1 "register_operand" "%0,d,d,d") | |
1351 | (match_operand:SI 2 "rhs_andsi3_operand" "L,M1,M2,d")))] | |
1352 | "" | |
1353 | "@ | |
1354 | BITCLR (%0,%Y2); | |
1355 | %0 = %T1 (Z); | |
1356 | %0 = %h1 (Z); | |
1357 | %0 = %1 & %2;" | |
1358 | [(set_attr "type" "alu0")]) | |
1359 | ||
1360 | (define_expand "andsi3" | |
1361 | [(set (match_operand:SI 0 "register_operand" "") | |
1362 | (and:SI (match_operand:SI 1 "register_operand" "") | |
1363 | (match_operand:SI 2 "general_operand" "")))] | |
1364 | "" | |
1365 | { | |
1366 | if (highbits_operand (operands[2], SImode)) | |
1367 | { | |
1368 | operands[2] = GEN_INT (exact_log2 (-INTVAL (operands[2]))); | |
1369 | emit_insn (gen_ashrsi3 (operands[0], operands[1], operands[2])); | |
1370 | emit_insn (gen_ashlsi3 (operands[0], operands[0], operands[2])); | |
1371 | DONE; | |
1372 | } | |
1373 | if (! rhs_andsi3_operand (operands[2], SImode)) | |
1374 | operands[2] = force_reg (SImode, operands[2]); | |
1375 | }) | |
1376 | ||
1377 | (define_insn "iorsi3" | |
1378 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1379 | (ior:SI (match_operand:SI 1 "register_operand" "%0,d") | |
1380 | (match_operand:SI 2 "regorlog2_operand" "J,d")))] | |
1381 | "" | |
1382 | "@ | |
1383 | BITSET (%0, %X2); | |
1384 | %0 = %1 | %2;" | |
1385 | [(set_attr "type" "alu0")]) | |
1386 | ||
1387 | (define_insn "xorsi3" | |
1388 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1389 | (xor:SI (match_operand:SI 1 "register_operand" "%0,d") | |
1390 | (match_operand:SI 2 "regorlog2_operand" "J,d")))] | |
1391 | "" | |
1392 | "@ | |
1393 | BITTGL (%0, %X2); | |
1394 | %0 = %1 ^ %2;" | |
1395 | [(set_attr "type" "alu0")]) | |
1396 | ||
1d7d5ac4 BS |
1397 | (define_insn "ones" |
1398 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1399 | (unspec:HI [(match_operand:SI 1 "register_operand" "d")] | |
1400 | UNSPEC_ONES))] | |
1401 | "" | |
1402 | "%h0 = ONES %1;" | |
1403 | [(set_attr "type" "alu0")]) | |
1404 | ||
0d4a78eb BS |
1405 | (define_insn "smaxsi3" |
1406 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1407 | (smax:SI (match_operand:SI 1 "register_operand" "d") | |
1408 | (match_operand:SI 2 "register_operand" "d")))] | |
1409 | "" | |
bbbc206e | 1410 | "%0 = max(%1,%2)%!" |
0d4a78eb BS |
1411 | [(set_attr "type" "dsp32")]) |
1412 | ||
1413 | (define_insn "sminsi3" | |
1414 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1415 | (smin:SI (match_operand:SI 1 "register_operand" "d") | |
1416 | (match_operand:SI 2 "register_operand" "d")))] | |
1417 | "" | |
bbbc206e | 1418 | "%0 = min(%1,%2)%!" |
0d4a78eb BS |
1419 | [(set_attr "type" "dsp32")]) |
1420 | ||
1421 | (define_insn "abssi2" | |
1422 | [(set (match_operand:SI 0 "register_operand" "=d") | |
75d8b2d0 | 1423 | (abs:SI (match_operand:SI 1 "register_operand" "d")))] |
0d4a78eb | 1424 | "" |
bbbc206e | 1425 | "%0 = abs %1%!" |
0d4a78eb BS |
1426 | [(set_attr "type" "dsp32")]) |
1427 | ||
26c5953d BS |
1428 | (define_insn "ssabssi2" |
1429 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1430 | (ss_abs:SI (match_operand:SI 1 "register_operand" "d")))] | |
1431 | "" | |
1432 | "%0 = abs %1%!" | |
1433 | [(set_attr "type" "dsp32")]) | |
1434 | ||
0d4a78eb BS |
1435 | (define_insn "negsi2" |
1436 | [(set (match_operand:SI 0 "register_operand" "=d") | |
75d8b2d0 | 1437 | (neg:SI (match_operand:SI 1 "register_operand" "d")))] |
0d4a78eb | 1438 | "" |
75d8b2d0 | 1439 | "%0 = -%1;" |
0d4a78eb BS |
1440 | [(set_attr "type" "alu0")]) |
1441 | ||
75d8b2d0 BS |
1442 | (define_insn "ssnegsi2" |
1443 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1444 | (ss_neg:SI (match_operand:SI 1 "register_operand" "d")))] | |
1445 | "" | |
bbbc206e | 1446 | "%0 = -%1 (S)%!" |
75d8b2d0 BS |
1447 | [(set_attr "type" "dsp32")]) |
1448 | ||
0d4a78eb BS |
1449 | (define_insn "one_cmplsi2" |
1450 | [(set (match_operand:SI 0 "register_operand" "=d") | |
75d8b2d0 | 1451 | (not:SI (match_operand:SI 1 "register_operand" "d")))] |
0d4a78eb | 1452 | "" |
75d8b2d0 | 1453 | "%0 = ~%1;" |
0d4a78eb BS |
1454 | [(set_attr "type" "alu0")]) |
1455 | ||
3801c801 BS |
1456 | (define_expand "clrsbsi2" |
1457 | [(set (match_dup 2) | |
e2f00837 | 1458 | (truncate:HI (clrsb:SI (match_operand:SI 1 "register_operand" "d")))) |
3801c801 BS |
1459 | (set (match_operand:SI 0 "register_operand") |
1460 | (zero_extend:SI (match_dup 2)))] | |
1461 | "" | |
1462 | { | |
1463 | operands[2] = gen_reg_rtx (HImode); | |
1464 | }) | |
1465 | ||
75d8b2d0 BS |
1466 | (define_insn "signbitssi2" |
1467 | [(set (match_operand:HI 0 "register_operand" "=d") | |
e2f00837 | 1468 | (truncate:HI (clrsb:SI (match_operand:SI 1 "register_operand" "d"))))] |
75d8b2d0 | 1469 | "" |
bbbc206e | 1470 | "%h0 = signbits %1%!" |
75d8b2d0 BS |
1471 | [(set_attr "type" "dsp32")]) |
1472 | ||
26c5953d BS |
1473 | (define_insn "ssroundsi2" |
1474 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1475 | (truncate:HI | |
1476 | (lshiftrt:SI (ss_plus:SI (match_operand:SI 1 "register_operand" "d") | |
1477 | (const_int 32768)) | |
1478 | (const_int 16))))] | |
1479 | "" | |
1480 | "%h0 = %1 (RND)%!" | |
1481 | [(set_attr "type" "dsp32")]) | |
1482 | ||
75d8b2d0 BS |
1483 | (define_insn "smaxhi3" |
1484 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1485 | (smax:HI (match_operand:HI 1 "register_operand" "d") | |
1486 | (match_operand:HI 2 "register_operand" "d")))] | |
1487 | "" | |
bbbc206e | 1488 | "%0 = max(%1,%2) (V)%!" |
75d8b2d0 BS |
1489 | [(set_attr "type" "dsp32")]) |
1490 | ||
1491 | (define_insn "sminhi3" | |
1492 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1493 | (smin:HI (match_operand:HI 1 "register_operand" "d") | |
1494 | (match_operand:HI 2 "register_operand" "d")))] | |
1495 | "" | |
bbbc206e | 1496 | "%0 = min(%1,%2) (V)%!" |
75d8b2d0 BS |
1497 | [(set_attr "type" "dsp32")]) |
1498 | ||
1499 | (define_insn "abshi2" | |
1500 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1501 | (abs:HI (match_operand:HI 1 "register_operand" "d")))] | |
1502 | "" | |
bbbc206e | 1503 | "%0 = abs %1 (V)%!" |
75d8b2d0 BS |
1504 | [(set_attr "type" "dsp32")]) |
1505 | ||
1506 | (define_insn "neghi2" | |
1507 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1508 | (neg:HI (match_operand:HI 1 "register_operand" "d")))] | |
1509 | "" | |
1510 | "%0 = -%1;" | |
bbbc206e | 1511 | [(set_attr "type" "alu0")]) |
75d8b2d0 BS |
1512 | |
1513 | (define_insn "ssneghi2" | |
1514 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1515 | (ss_neg:HI (match_operand:HI 1 "register_operand" "d")))] | |
1516 | "" | |
bbbc206e | 1517 | "%0 = -%1 (V)%!" |
75d8b2d0 BS |
1518 | [(set_attr "type" "dsp32")]) |
1519 | ||
3801c801 | 1520 | (define_insn "clrsbhi2" |
75d8b2d0 | 1521 | [(set (match_operand:HI 0 "register_operand" "=d") |
3801c801 | 1522 | (clrsb:HI (match_operand:HI 1 "register_operand" "d")))] |
75d8b2d0 | 1523 | "" |
bbbc206e | 1524 | "%h0 = signbits %h1%!" |
75d8b2d0 BS |
1525 | [(set_attr "type" "dsp32")]) |
1526 | ||
0d4a78eb BS |
1527 | (define_insn "mulsi3" |
1528 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1529 | (mult:SI (match_operand:SI 1 "register_operand" "%0") | |
1530 | (match_operand:SI 2 "register_operand" "d")))] | |
1531 | "" | |
75d8b2d0 | 1532 | "%0 *= %2;" |
0d4a78eb BS |
1533 | [(set_attr "type" "mult")]) |
1534 | ||
01e7cd6e | 1535 | (define_expand "umulsi3_highpart" |
3fbee523 BS |
1536 | [(parallel |
1537 | [(set (match_operand:SI 0 "register_operand" "") | |
1538 | (truncate:SI | |
1539 | (lshiftrt:DI | |
1540 | (mult:DI (zero_extend:DI | |
1541 | (match_operand:SI 1 "nonimmediate_operand" "")) | |
1542 | (zero_extend:DI | |
1543 | (match_operand:SI 2 "register_operand" ""))) | |
1544 | (const_int 32)))) | |
1545 | (clobber (reg:PDI REG_A0)) | |
1546 | (clobber (reg:PDI REG_A1))])] | |
01e7cd6e BS |
1547 | "" |
1548 | { | |
3fbee523 BS |
1549 | if (!optimize_size) |
1550 | { | |
1551 | rtx a1reg = gen_rtx_REG (PDImode, REG_A1); | |
1552 | rtx a0reg = gen_rtx_REG (PDImode, REG_A0); | |
1553 | emit_insn (gen_flag_macinit1hi (a1reg, | |
1554 | gen_lowpart (HImode, operands[1]), | |
1555 | gen_lowpart (HImode, operands[2]), | |
1556 | GEN_INT (MACFLAG_FU))); | |
1557 | emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16))); | |
1558 | emit_insn (gen_flag_mul_macv2hi_parts_acconly (a0reg, a1reg, | |
1559 | gen_lowpart (V2HImode, operands[1]), | |
1560 | gen_lowpart (V2HImode, operands[2]), | |
1561 | const1_rtx, const1_rtx, | |
1562 | const1_rtx, const0_rtx, a1reg, | |
1563 | const0_rtx, GEN_INT (MACFLAG_FU), | |
1564 | GEN_INT (MACFLAG_FU))); | |
1565 | emit_insn (gen_flag_machi_parts_acconly (a1reg, | |
1566 | gen_lowpart (V2HImode, operands[2]), | |
1567 | gen_lowpart (V2HImode, operands[1]), | |
1568 | const1_rtx, const0_rtx, | |
1569 | a1reg, const0_rtx, GEN_INT (MACFLAG_FU))); | |
1570 | emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16))); | |
314f9913 BS |
1571 | emit_insn (gen_addpdi3 (a0reg, a0reg, a1reg)); |
1572 | emit_insn (gen_us_truncpdisi2 (operands[0], a0reg)); | |
3fbee523 BS |
1573 | } |
1574 | else | |
1575 | { | |
1576 | rtx umulsi3_highpart_libfunc | |
1577 | = init_one_libfunc ("__umulsi3_highpart"); | |
01e7cd6e | 1578 | |
3fbee523 BS |
1579 | emit_library_call_value (umulsi3_highpart_libfunc, |
1580 | operands[0], LCT_NORMAL, SImode, | |
1581 | 2, operands[1], SImode, operands[2], SImode); | |
1582 | } | |
01e7cd6e BS |
1583 | DONE; |
1584 | }) | |
1585 | ||
1586 | (define_expand "smulsi3_highpart" | |
3fbee523 BS |
1587 | [(parallel |
1588 | [(set (match_operand:SI 0 "register_operand" "") | |
1589 | (truncate:SI | |
1590 | (lshiftrt:DI | |
1591 | (mult:DI (sign_extend:DI | |
1592 | (match_operand:SI 1 "nonimmediate_operand" "")) | |
1593 | (sign_extend:DI | |
1594 | (match_operand:SI 2 "register_operand" ""))) | |
1595 | (const_int 32)))) | |
1596 | (clobber (reg:PDI REG_A0)) | |
1597 | (clobber (reg:PDI REG_A1))])] | |
01e7cd6e BS |
1598 | "" |
1599 | { | |
3fbee523 BS |
1600 | if (!optimize_size) |
1601 | { | |
1602 | rtx a1reg = gen_rtx_REG (PDImode, REG_A1); | |
1603 | rtx a0reg = gen_rtx_REG (PDImode, REG_A0); | |
1604 | emit_insn (gen_flag_macinit1hi (a1reg, | |
1605 | gen_lowpart (HImode, operands[1]), | |
1606 | gen_lowpart (HImode, operands[2]), | |
1607 | GEN_INT (MACFLAG_FU))); | |
1608 | emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16))); | |
1609 | emit_insn (gen_flag_mul_macv2hi_parts_acconly (a0reg, a1reg, | |
1610 | gen_lowpart (V2HImode, operands[1]), | |
1611 | gen_lowpart (V2HImode, operands[2]), | |
1612 | const1_rtx, const1_rtx, | |
1613 | const1_rtx, const0_rtx, a1reg, | |
1614 | const0_rtx, GEN_INT (MACFLAG_IS), | |
1615 | GEN_INT (MACFLAG_IS_M))); | |
1616 | emit_insn (gen_flag_machi_parts_acconly (a1reg, | |
1617 | gen_lowpart (V2HImode, operands[2]), | |
1618 | gen_lowpart (V2HImode, operands[1]), | |
1619 | const1_rtx, const0_rtx, | |
1620 | a1reg, const0_rtx, GEN_INT (MACFLAG_IS_M))); | |
1621 | emit_insn (gen_ashrpdi3 (a1reg, a1reg, GEN_INT (16))); | |
1622 | emit_insn (gen_sum_of_accumulators (operands[0], a0reg, a0reg, a1reg)); | |
1623 | } | |
1624 | else | |
1625 | { | |
1626 | rtx smulsi3_highpart_libfunc | |
1627 | = init_one_libfunc ("__smulsi3_highpart"); | |
01e7cd6e | 1628 | |
3fbee523 BS |
1629 | emit_library_call_value (smulsi3_highpart_libfunc, |
1630 | operands[0], LCT_NORMAL, SImode, | |
1631 | 2, operands[1], SImode, operands[2], SImode); | |
1632 | } | |
01e7cd6e BS |
1633 | DONE; |
1634 | }) | |
1635 | ||
0d4a78eb BS |
1636 | (define_expand "ashlsi3" |
1637 | [(set (match_operand:SI 0 "register_operand" "") | |
1638 | (ashift:SI (match_operand:SI 1 "register_operand" "") | |
1639 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
1640 | "" | |
1641 | { | |
1642 | if (GET_CODE (operands[2]) == CONST_INT | |
1643 | && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) | |
1644 | { | |
1645 | emit_insn (gen_movsi (operands[0], const0_rtx)); | |
1646 | DONE; | |
1647 | } | |
1648 | }) | |
1649 | ||
1650 | (define_insn_and_split "*ashlsi3_insn" | |
bbbc206e BS |
1651 | [(set (match_operand:SI 0 "register_operand" "=d,d,a,a,a") |
1652 | (ashift:SI (match_operand:SI 1 "register_operand" "0,d,a,a,a") | |
1653 | (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5,P1,P2,?P3P4")))] | |
0d4a78eb BS |
1654 | "" |
1655 | "@ | |
1656 | %0 <<= %2; | |
bbbc206e | 1657 | %0 = %1 << %2%! |
0d4a78eb BS |
1658 | %0 = %1 + %1; |
1659 | %0 = %1 << %2; | |
1660 | #" | |
1661 | "PREG_P (operands[0]) && INTVAL (operands[2]) > 2" | |
1662 | [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 2))) | |
1663 | (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))] | |
1664 | "operands[3] = GEN_INT (INTVAL (operands[2]) - 2);" | |
b3187e24 | 1665 | [(set_attr "type" "shft,dsp32shiftimm,shft,shft,*")]) |
0d4a78eb BS |
1666 | |
1667 | (define_insn "ashrsi3" | |
bbbc206e BS |
1668 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
1669 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d") | |
1670 | (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5")))] | |
0d4a78eb | 1671 | "" |
bbbc206e BS |
1672 | "@ |
1673 | %0 >>>= %2; | |
1674 | %0 = %1 >>> %2%!" | |
b3187e24 | 1675 | [(set_attr "type" "shft,dsp32shiftimm")]) |
0d4a78eb | 1676 | |
97130915 BS |
1677 | (define_insn "rotl16" |
1678 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1679 | (rotate:SI (match_operand:SI 1 "register_operand" "d") | |
1680 | (const_int 16)))] | |
1681 | "" | |
1682 | "%0 = PACK (%h1, %d1)%!" | |
1683 | [(set_attr "type" "dsp32")]) | |
1684 | ||
1685 | (define_expand "rotlsi3" | |
1686 | [(set (match_operand:SI 0 "register_operand" "") | |
1687 | (rotate:SI (match_operand:SI 1 "register_operand" "") | |
9f111209 | 1688 | (match_operand:SI 2 "const_int_operand" "")))] |
97130915 BS |
1689 | "" |
1690 | { | |
9f111209 | 1691 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 16) |
97130915 BS |
1692 | FAIL; |
1693 | }) | |
1694 | ||
1695 | (define_expand "rotrsi3" | |
1696 | [(set (match_operand:SI 0 "register_operand" "") | |
1697 | (rotatert:SI (match_operand:SI 1 "register_operand" "") | |
9f111209 | 1698 | (match_operand:SI 2 "const_int_operand" "")))] |
97130915 BS |
1699 | "" |
1700 | { | |
9f111209 | 1701 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 16) |
97130915 BS |
1702 | FAIL; |
1703 | emit_insn (gen_rotl16 (operands[0], operands[1])); | |
1704 | DONE; | |
1705 | }) | |
1706 | ||
1707 | ||
49373252 BS |
1708 | (define_insn "ror_one" |
1709 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1710 | (ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") (const_int 1)) | |
1711 | (ashift:SI (zero_extend:SI (reg:BI REG_CC)) (const_int 31)))) | |
1712 | (set (reg:BI REG_CC) | |
1713 | (zero_extract:BI (match_dup 1) (const_int 1) (const_int 0)))] | |
1714 | "" | |
bbbc206e | 1715 | "%0 = ROT %1 BY -1%!" |
b3187e24 | 1716 | [(set_attr "type" "dsp32shiftimm")]) |
49373252 BS |
1717 | |
1718 | (define_insn "rol_one" | |
1719 | [(set (match_operand:SI 0 "register_operand" "+d") | |
1720 | (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") (const_int 1)) | |
1721 | (zero_extend:SI (reg:BI REG_CC)))) | |
1722 | (set (reg:BI REG_CC) | |
1723 | (zero_extract:BI (match_dup 1) (const_int 31) (const_int 0)))] | |
1724 | "" | |
bbbc206e | 1725 | "%0 = ROT %1 BY 1%!" |
b3187e24 | 1726 | [(set_attr "type" "dsp32shiftimm")]) |
49373252 BS |
1727 | |
1728 | (define_expand "lshrdi3" | |
1729 | [(set (match_operand:DI 0 "register_operand" "") | |
1730 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
1731 | (match_operand:DI 2 "general_operand" "")))] | |
1732 | "" | |
1733 | { | |
1734 | rtx lo_half[2], hi_half[2]; | |
1735 | ||
1736 | if (operands[2] != const1_rtx) | |
1737 | FAIL; | |
1738 | if (! rtx_equal_p (operands[0], operands[1])) | |
1739 | emit_move_insn (operands[0], operands[1]); | |
1740 | ||
1741 | split_di (operands, 2, lo_half, hi_half); | |
1742 | ||
1743 | emit_move_insn (bfin_cc_rtx, const0_rtx); | |
1744 | emit_insn (gen_ror_one (hi_half[0], hi_half[0])); | |
1745 | emit_insn (gen_ror_one (lo_half[0], lo_half[0])); | |
1746 | DONE; | |
1747 | }) | |
1748 | ||
1749 | (define_expand "ashrdi3" | |
1750 | [(set (match_operand:DI 0 "register_operand" "") | |
1751 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
1752 | (match_operand:DI 2 "general_operand" "")))] | |
1753 | "" | |
1754 | { | |
1755 | rtx lo_half[2], hi_half[2]; | |
1756 | ||
1757 | if (operands[2] != const1_rtx) | |
1758 | FAIL; | |
1759 | if (! rtx_equal_p (operands[0], operands[1])) | |
1760 | emit_move_insn (operands[0], operands[1]); | |
1761 | ||
1762 | split_di (operands, 2, lo_half, hi_half); | |
1763 | ||
1764 | emit_insn (gen_compare_lt (gen_rtx_REG (BImode, REG_CC), | |
1765 | hi_half[1], const0_rtx)); | |
1766 | emit_insn (gen_ror_one (hi_half[0], hi_half[0])); | |
1767 | emit_insn (gen_ror_one (lo_half[0], lo_half[0])); | |
1768 | DONE; | |
1769 | }) | |
1770 | ||
1771 | (define_expand "ashldi3" | |
1772 | [(set (match_operand:DI 0 "register_operand" "") | |
1773 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
1774 | (match_operand:DI 2 "general_operand" "")))] | |
1775 | "" | |
1776 | { | |
1777 | rtx lo_half[2], hi_half[2]; | |
1778 | ||
1779 | if (operands[2] != const1_rtx) | |
1780 | FAIL; | |
1781 | if (! rtx_equal_p (operands[0], operands[1])) | |
1782 | emit_move_insn (operands[0], operands[1]); | |
1783 | ||
1784 | split_di (operands, 2, lo_half, hi_half); | |
1785 | ||
1786 | emit_move_insn (bfin_cc_rtx, const0_rtx); | |
1787 | emit_insn (gen_rol_one (lo_half[0], lo_half[0])); | |
1788 | emit_insn (gen_rol_one (hi_half[0], hi_half[0])); | |
1789 | DONE; | |
1790 | }) | |
1791 | ||
0d4a78eb | 1792 | (define_insn "lshrsi3" |
bbbc206e BS |
1793 | [(set (match_operand:SI 0 "register_operand" "=d,d,a") |
1794 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,d,a") | |
1795 | (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5,P1P2")))] | |
0d4a78eb BS |
1796 | "" |
1797 | "@ | |
1798 | %0 >>= %2; | |
bbbc206e | 1799 | %0 = %1 >> %2%! |
0d4a78eb | 1800 | %0 = %1 >> %2;" |
b3187e24 | 1801 | [(set_attr "type" "shft,dsp32shiftimm,shft")]) |
0d4a78eb | 1802 | |
3efd5670 BS |
1803 | (define_insn "lshrpdi3" |
1804 | [(set (match_operand:PDI 0 "register_operand" "=e") | |
1805 | (lshiftrt:PDI (match_operand:PDI 1 "register_operand" "0") | |
1806 | (match_operand:SI 2 "nonmemory_operand" "Ku5")))] | |
1807 | "" | |
1808 | "%0 = %1 >> %2%!" | |
b3187e24 | 1809 | [(set_attr "type" "dsp32shiftimm")]) |
3efd5670 BS |
1810 | |
1811 | (define_insn "ashrpdi3" | |
1812 | [(set (match_operand:PDI 0 "register_operand" "=e") | |
1813 | (ashiftrt:PDI (match_operand:PDI 1 "register_operand" "0") | |
1814 | (match_operand:SI 2 "nonmemory_operand" "Ku5")))] | |
1815 | "" | |
1816 | "%0 = %1 >>> %2%!" | |
b3187e24 | 1817 | [(set_attr "type" "dsp32shiftimm")]) |
3efd5670 | 1818 | |
0d4a78eb BS |
1819 | ;; A pattern to reload the equivalent of |
1820 | ;; (set (Dreg) (plus (FP) (large_constant))) | |
1821 | ;; or | |
1822 | ;; (set (dagreg) (plus (FP) (arbitrary_constant))) | |
1823 | ;; using a scratch register | |
1824 | (define_expand "reload_insi" | |
1825 | [(parallel [(set (match_operand:SI 0 "register_operand" "=w") | |
1826 | (match_operand:SI 1 "fp_plus_const_operand" "")) | |
1827 | (clobber (match_operand:SI 2 "register_operand" "=&a"))])] | |
1828 | "" | |
1829 | { | |
1830 | rtx fp_op = XEXP (operands[1], 0); | |
1831 | rtx const_op = XEXP (operands[1], 1); | |
1832 | rtx primary = operands[0]; | |
1833 | rtx scratch = operands[2]; | |
1834 | ||
1835 | emit_move_insn (scratch, const_op); | |
1836 | emit_insn (gen_addsi3 (scratch, scratch, fp_op)); | |
1837 | emit_move_insn (primary, scratch); | |
1838 | DONE; | |
1839 | }) | |
1840 | ||
6c1c1dfa BS |
1841 | (define_mode_iterator AREG [PDI V2PDI]) |
1842 | ||
1843 | (define_insn "reload_in<mode>" | |
1844 | [(set (match_operand:AREG 0 "register_operand" "=e") | |
1845 | (match_operand:AREG 1 "memory_operand" "m")) | |
6ed44ca1 BS |
1846 | (clobber (match_operand:SI 2 "register_operand" "=d"))] |
1847 | "" | |
1848 | { | |
1849 | rtx xops[4]; | |
1850 | xops[0] = operands[0]; | |
1851 | xops[1] = operands[2]; | |
1852 | split_di (operands + 1, 1, xops + 2, xops + 3); | |
1853 | output_asm_insn ("%1 = %2;", xops); | |
1854 | output_asm_insn ("%w0 = %1;", xops); | |
1855 | output_asm_insn ("%1 = %3;", xops); | |
1856 | output_asm_insn ("%x0 = %1;", xops); | |
1857 | return ""; | |
1858 | } | |
1859 | [(set_attr "seq_insns" "multi") | |
1860 | (set_attr "type" "mcld") | |
1861 | (set_attr "length" "12")]) | |
1862 | ||
6c1c1dfa BS |
1863 | (define_insn "reload_out<mode>" |
1864 | [(set (match_operand:AREG 0 "memory_operand" "=m") | |
1865 | (match_operand:AREG 1 "register_operand" "e")) | |
6ed44ca1 BS |
1866 | (clobber (match_operand:SI 2 "register_operand" "=d"))] |
1867 | "" | |
1868 | { | |
1869 | rtx xops[4]; | |
1870 | xops[0] = operands[1]; | |
1871 | xops[1] = operands[2]; | |
1872 | split_di (operands, 1, xops + 2, xops + 3); | |
1873 | output_asm_insn ("%1 = %w0;", xops); | |
1874 | output_asm_insn ("%2 = %1;", xops); | |
1875 | output_asm_insn ("%1 = %x0;", xops); | |
1876 | output_asm_insn ("%3 = %1;", xops); | |
1877 | return ""; | |
1878 | } | |
1879 | [(set_attr "seq_insns" "multi") | |
1880 | (set_attr "type" "mcld") | |
1881 | (set_attr "length" "12")]) | |
1882 | ||
0d4a78eb BS |
1883 | ;; Jump instructions |
1884 | ||
1885 | (define_insn "jump" | |
1886 | [(set (pc) | |
1887 | (label_ref (match_operand 0 "" "")))] | |
1888 | "" | |
1889 | { | |
1890 | if (get_attr_length (insn) == 2) | |
1891 | return "jump.s %0;"; | |
1892 | else | |
1893 | return "jump.l %0;"; | |
1894 | } | |
1895 | [(set_attr "type" "br")]) | |
1896 | ||
1897 | (define_insn "indirect_jump" | |
1898 | [(set (pc) | |
1899 | (match_operand:SI 0 "register_operand" "a"))] | |
1900 | "" | |
1901 | "jump (%0);" | |
1902 | [(set_attr "type" "misc")]) | |
1903 | ||
1904 | (define_expand "tablejump" | |
1905 | [(parallel [(set (pc) (match_operand:SI 0 "register_operand" "a")) | |
1906 | (use (label_ref (match_operand 1 "" "")))])] | |
1907 | "" | |
1908 | { | |
1909 | /* In PIC mode, the table entries are stored PC relative. | |
1910 | Convert the relative address to an absolute address. */ | |
1911 | if (flag_pic) | |
1912 | { | |
1913 | rtx op1 = gen_rtx_LABEL_REF (Pmode, operands[1]); | |
1914 | ||
1915 | operands[0] = expand_simple_binop (Pmode, PLUS, operands[0], | |
1916 | op1, NULL_RTX, 0, OPTAB_DIRECT); | |
1917 | } | |
1918 | }) | |
1919 | ||
1920 | (define_insn "*tablejump_internal" | |
1921 | [(set (pc) (match_operand:SI 0 "register_operand" "a")) | |
1922 | (use (label_ref (match_operand 1 "" "")))] | |
1923 | "" | |
1924 | "jump (%0);" | |
1925 | [(set_attr "type" "misc")]) | |
1926 | ||
b03149e1 JZ |
1927 | ;; Hardware loop |
1928 | ||
1929 | ; operand 0 is the loop count pseudo register | |
1d0216c8 | 1930 | ; operand 1 is the label to jump to at the top of the loop |
b03149e1 JZ |
1931 | (define_expand "doloop_end" |
1932 | [(parallel [(set (pc) (if_then_else | |
1933 | (ne (match_operand:SI 0 "" "") | |
1934 | (const_int 1)) | |
1d0216c8 | 1935 | (label_ref (match_operand 1 "" "")) |
b03149e1 JZ |
1936 | (pc))) |
1937 | (set (match_dup 0) | |
1938 | (plus:SI (match_dup 0) | |
1939 | (const_int -1))) | |
1940 | (unspec [(const_int 0)] UNSPEC_LSETUP_END) | |
1d0216c8 | 1941 | (clobber (match_dup 2))])] ; match_scratch |
b03149e1 | 1942 | "" |
0a8f8c45 | 1943 | { |
9b02a95e BS |
1944 | /* The loop optimizer doesn't check the predicates... */ |
1945 | if (GET_MODE (operands[0]) != SImode) | |
1946 | FAIL; | |
0a8f8c45 | 1947 | bfin_hardware_loop (); |
1d0216c8 | 1948 | operands[2] = gen_rtx_SCRATCH (SImode); |
0a8f8c45 | 1949 | }) |
b03149e1 JZ |
1950 | |
1951 | (define_insn "loop_end" | |
1952 | [(set (pc) | |
36019c19 | 1953 | (if_then_else (ne (match_operand:SI 2 "nonimmediate_operand" "0,0,0") |
b03149e1 JZ |
1954 | (const_int 1)) |
1955 | (label_ref (match_operand 1 "" "")) | |
1956 | (pc))) | |
36019c19 SH |
1957 | (set (match_operand:SI 0 "nonimmediate_operand" "=a*d,*b*v*f,m") |
1958 | (plus (match_dup 2) | |
b03149e1 JZ |
1959 | (const_int -1))) |
1960 | (unspec [(const_int 0)] UNSPEC_LSETUP_END) | |
36019c19 | 1961 | (clobber (match_scratch:SI 3 "=X,&r,&r"))] |
b03149e1 JZ |
1962 | "" |
1963 | "@ | |
1964 | /* loop end %0 %l1 */ | |
1965 | # | |
1966 | #" | |
1967 | [(set_attr "length" "6,10,14")]) | |
1968 | ||
1969 | (define_split | |
1970 | [(set (pc) | |
1091cf49 | 1971 | (if_then_else (ne (match_operand:SI 0 "nondp_reg_or_memory_operand") |
b03149e1 | 1972 | (const_int 1)) |
1091cf49 | 1973 | (label_ref (match_operand 1 "")) |
b03149e1 JZ |
1974 | (pc))) |
1975 | (set (match_dup 0) | |
1976 | (plus (match_dup 0) | |
1977 | (const_int -1))) | |
1978 | (unspec [(const_int 0)] UNSPEC_LSETUP_END) | |
1091cf49 | 1979 | (clobber (match_scratch:SI 2))] |
9d9c740d | 1980 | "memory_operand (operands[0], SImode) || splitting_loops" |
b03149e1 JZ |
1981 | [(set (match_dup 2) (match_dup 0)) |
1982 | (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
1983 | (set (match_dup 0) (match_dup 2)) | |
1984 | (set (reg:BI REG_CC) (eq:BI (match_dup 2) (const_int 0))) | |
1985 | (set (pc) | |
1986 | (if_then_else (eq (reg:BI REG_CC) | |
1987 | (const_int 0)) | |
1988 | (label_ref (match_dup 1)) | |
1989 | (pc)))] | |
1990 | "") | |
1991 | ||
1992 | (define_insn "lsetup_with_autoinit" | |
1993 | [(set (match_operand:SI 0 "lt_register_operand" "=t") | |
1994 | (label_ref (match_operand 1 "" ""))) | |
a9c46998 | 1995 | (set (match_operand:SI 2 "lb_register_operand" "=u") |
b03149e1 JZ |
1996 | (label_ref (match_operand 3 "" ""))) |
1997 | (set (match_operand:SI 4 "lc_register_operand" "=k") | |
1998 | (match_operand:SI 5 "register_operand" "a"))] | |
1999 | "" | |
2000 | "LSETUP (%1, %3) %4 = %5;" | |
2001 | [(set_attr "length" "4")]) | |
2002 | ||
2003 | (define_insn "lsetup_without_autoinit" | |
2004 | [(set (match_operand:SI 0 "lt_register_operand" "=t") | |
2005 | (label_ref (match_operand 1 "" ""))) | |
a9c46998 | 2006 | (set (match_operand:SI 2 "lb_register_operand" "=u") |
b03149e1 JZ |
2007 | (label_ref (match_operand 3 "" ""))) |
2008 | (use (match_operand:SI 4 "lc_register_operand" "k"))] | |
2009 | "" | |
2010 | "LSETUP (%1, %3) %4;" | |
2011 | [(set_attr "length" "4")]) | |
2012 | ||
0d4a78eb BS |
2013 | ;; Call instructions.. |
2014 | ||
6614f9f5 BS |
2015 | ;; The explicit MEM inside the UNSPEC prevents the compiler from moving |
2016 | ;; the load before a branch after a NULL test, or before a store that | |
2017 | ;; initializes a function descriptor. | |
2018 | ||
2019 | (define_insn_and_split "load_funcdescsi" | |
2020 | [(set (match_operand:SI 0 "register_operand" "=a") | |
2021 | (unspec_volatile:SI [(mem:SI (match_operand:SI 1 "address_operand" "p"))] | |
2022 | UNSPEC_VOLATILE_LOAD_FUNCDESC))] | |
2023 | "" | |
2024 | "#" | |
2025 | "reload_completed" | |
2026 | [(set (match_dup 0) (mem:SI (match_dup 1)))]) | |
2027 | ||
0d4a78eb | 2028 | (define_expand "call" |
6d459e2b BS |
2029 | [(parallel [(call (match_operand:SI 0 "" "") |
2030 | (match_operand 1 "" "")) | |
2031 | (use (match_operand 2 "" ""))])] | |
0d4a78eb | 2032 | "" |
6d459e2b BS |
2033 | { |
2034 | bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 0); | |
2035 | DONE; | |
2036 | }) | |
0d4a78eb BS |
2037 | |
2038 | (define_expand "sibcall" | |
2039 | [(parallel [(call (match_operand:SI 0 "" "") | |
2040 | (match_operand 1 "" "")) | |
6d459e2b | 2041 | (use (match_operand 2 "" "")) |
0d4a78eb BS |
2042 | (return)])] |
2043 | "" | |
6d459e2b BS |
2044 | { |
2045 | bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 1); | |
2046 | DONE; | |
2047 | }) | |
0d4a78eb BS |
2048 | |
2049 | (define_expand "call_value" | |
6d459e2b BS |
2050 | [(parallel [(set (match_operand 0 "register_operand" "") |
2051 | (call (match_operand:SI 1 "" "") | |
2052 | (match_operand 2 "" ""))) | |
2053 | (use (match_operand 3 "" ""))])] | |
0d4a78eb | 2054 | "" |
6d459e2b BS |
2055 | { |
2056 | bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 0); | |
2057 | DONE; | |
2058 | }) | |
0d4a78eb BS |
2059 | |
2060 | (define_expand "sibcall_value" | |
2061 | [(parallel [(set (match_operand 0 "register_operand" "") | |
2062 | (call (match_operand:SI 1 "" "") | |
2063 | (match_operand 2 "" ""))) | |
6d459e2b | 2064 | (use (match_operand 3 "" "")) |
0d4a78eb BS |
2065 | (return)])] |
2066 | "" | |
6d459e2b BS |
2067 | { |
2068 | bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 1); | |
2069 | DONE; | |
2070 | }) | |
0d4a78eb | 2071 | |
6614f9f5 BS |
2072 | (define_insn "*call_symbol_fdpic" |
2073 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q")) | |
2074 | (match_operand 1 "general_operand" "g")) | |
2075 | (use (match_operand:SI 2 "register_operand" "Z")) | |
9840d30a BS |
2076 | (use (match_operand 3 "" "")) |
2077 | (clobber (reg:SI REG_RETS))] | |
6614f9f5 BS |
2078 | "! SIBLING_CALL_P (insn) |
2079 | && GET_CODE (operands[0]) == SYMBOL_REF | |
2080 | && !bfin_longcall_p (operands[0], INTVAL (operands[3]))" | |
2081 | "call %0;" | |
2082 | [(set_attr "type" "call") | |
2083 | (set_attr "length" "4")]) | |
2084 | ||
2085 | (define_insn "*sibcall_symbol_fdpic" | |
2086 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q")) | |
2087 | (match_operand 1 "general_operand" "g")) | |
2088 | (use (match_operand:SI 2 "register_operand" "Z")) | |
2089 | (use (match_operand 3 "" "")) | |
2090 | (return)] | |
2091 | "SIBLING_CALL_P (insn) | |
2092 | && GET_CODE (operands[0]) == SYMBOL_REF | |
2093 | && !bfin_longcall_p (operands[0], INTVAL (operands[3]))" | |
2094 | "jump.l %0;" | |
2095 | [(set_attr "type" "br") | |
2096 | (set_attr "length" "4")]) | |
2097 | ||
2098 | (define_insn "*call_value_symbol_fdpic" | |
2099 | [(set (match_operand 0 "register_operand" "=d") | |
2100 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q")) | |
2101 | (match_operand 2 "general_operand" "g"))) | |
2102 | (use (match_operand:SI 3 "register_operand" "Z")) | |
9840d30a BS |
2103 | (use (match_operand 4 "" "")) |
2104 | (clobber (reg:SI REG_RETS))] | |
6614f9f5 BS |
2105 | "! SIBLING_CALL_P (insn) |
2106 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2107 | && !bfin_longcall_p (operands[1], INTVAL (operands[4]))" | |
2108 | "call %1;" | |
2109 | [(set_attr "type" "call") | |
2110 | (set_attr "length" "4")]) | |
2111 | ||
2112 | (define_insn "*sibcall_value_symbol_fdpic" | |
2113 | [(set (match_operand 0 "register_operand" "=d") | |
2114 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q")) | |
2115 | (match_operand 2 "general_operand" "g"))) | |
2116 | (use (match_operand:SI 3 "register_operand" "Z")) | |
2117 | (use (match_operand 4 "" "")) | |
2118 | (return)] | |
2119 | "SIBLING_CALL_P (insn) | |
2120 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2121 | && !bfin_longcall_p (operands[1], INTVAL (operands[4]))" | |
2122 | "jump.l %1;" | |
2123 | [(set_attr "type" "br") | |
2124 | (set_attr "length" "4")]) | |
2125 | ||
2126 | (define_insn "*call_insn_fdpic" | |
2127 | [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y")) | |
2128 | (match_operand 1 "general_operand" "g")) | |
2129 | (use (match_operand:SI 2 "register_operand" "Z")) | |
9840d30a BS |
2130 | (use (match_operand 3 "" "")) |
2131 | (clobber (reg:SI REG_RETS))] | |
6614f9f5 BS |
2132 | "! SIBLING_CALL_P (insn)" |
2133 | "call (%0);" | |
2134 | [(set_attr "type" "call") | |
2135 | (set_attr "length" "2")]) | |
2136 | ||
2137 | (define_insn "*sibcall_insn_fdpic" | |
2138 | [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y")) | |
2139 | (match_operand 1 "general_operand" "g")) | |
2140 | (use (match_operand:SI 2 "register_operand" "Z")) | |
2141 | (use (match_operand 3 "" "")) | |
2142 | (return)] | |
2143 | "SIBLING_CALL_P (insn)" | |
2144 | "jump (%0);" | |
2145 | [(set_attr "type" "br") | |
2146 | (set_attr "length" "2")]) | |
2147 | ||
2148 | (define_insn "*call_value_insn_fdpic" | |
2149 | [(set (match_operand 0 "register_operand" "=d") | |
2150 | (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y")) | |
2151 | (match_operand 2 "general_operand" "g"))) | |
2152 | (use (match_operand:SI 3 "register_operand" "Z")) | |
9840d30a BS |
2153 | (use (match_operand 4 "" "")) |
2154 | (clobber (reg:SI REG_RETS))] | |
6614f9f5 BS |
2155 | "! SIBLING_CALL_P (insn)" |
2156 | "call (%1);" | |
2157 | [(set_attr "type" "call") | |
2158 | (set_attr "length" "2")]) | |
2159 | ||
2160 | (define_insn "*sibcall_value_insn_fdpic" | |
2161 | [(set (match_operand 0 "register_operand" "=d") | |
2162 | (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y")) | |
2163 | (match_operand 2 "general_operand" "g"))) | |
2164 | (use (match_operand:SI 3 "register_operand" "Z")) | |
2165 | (use (match_operand 4 "" "")) | |
2166 | (return)] | |
2167 | "SIBLING_CALL_P (insn)" | |
2168 | "jump (%1);" | |
2169 | [(set_attr "type" "br") | |
2170 | (set_attr "length" "2")]) | |
2171 | ||
6d459e2b BS |
2172 | (define_insn "*call_symbol" |
2173 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q")) | |
2174 | (match_operand 1 "general_operand" "g")) | |
9840d30a BS |
2175 | (use (match_operand 2 "" "")) |
2176 | (clobber (reg:SI REG_RETS))] | |
0d4a78eb | 2177 | "! SIBLING_CALL_P (insn) |
93147119 | 2178 | && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY) |
6d459e2b BS |
2179 | && GET_CODE (operands[0]) == SYMBOL_REF |
2180 | && !bfin_longcall_p (operands[0], INTVAL (operands[2]))" | |
96c30d2a | 2181 | "call %0;" |
0d4a78eb | 2182 | [(set_attr "type" "call") |
6d459e2b | 2183 | (set_attr "length" "4")]) |
0d4a78eb | 2184 | |
6d459e2b BS |
2185 | (define_insn "*sibcall_symbol" |
2186 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q")) | |
2187 | (match_operand 1 "general_operand" "g")) | |
2188 | (use (match_operand 2 "" "")) | |
0d4a78eb BS |
2189 | (return)] |
2190 | "SIBLING_CALL_P (insn) | |
93147119 | 2191 | && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY) |
6d459e2b BS |
2192 | && GET_CODE (operands[0]) == SYMBOL_REF |
2193 | && !bfin_longcall_p (operands[0], INTVAL (operands[2]))" | |
96c30d2a | 2194 | "jump.l %0;" |
0d4a78eb | 2195 | [(set_attr "type" "br") |
6d459e2b | 2196 | (set_attr "length" "4")]) |
0d4a78eb | 2197 | |
6d459e2b BS |
2198 | (define_insn "*call_value_symbol" |
2199 | [(set (match_operand 0 "register_operand" "=d") | |
2200 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q")) | |
2201 | (match_operand 2 "general_operand" "g"))) | |
9840d30a BS |
2202 | (use (match_operand 3 "" "")) |
2203 | (clobber (reg:SI REG_RETS))] | |
0d4a78eb | 2204 | "! SIBLING_CALL_P (insn) |
93147119 | 2205 | && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY) |
6d459e2b BS |
2206 | && GET_CODE (operands[1]) == SYMBOL_REF |
2207 | && !bfin_longcall_p (operands[1], INTVAL (operands[3]))" | |
96c30d2a | 2208 | "call %1;" |
0d4a78eb | 2209 | [(set_attr "type" "call") |
6d459e2b | 2210 | (set_attr "length" "4")]) |
0d4a78eb | 2211 | |
6d459e2b BS |
2212 | (define_insn "*sibcall_value_symbol" |
2213 | [(set (match_operand 0 "register_operand" "=d") | |
2214 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q")) | |
2215 | (match_operand 2 "general_operand" "g"))) | |
2216 | (use (match_operand 3 "" "")) | |
0d4a78eb BS |
2217 | (return)] |
2218 | "SIBLING_CALL_P (insn) | |
93147119 | 2219 | && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY) |
6d459e2b BS |
2220 | && GET_CODE (operands[1]) == SYMBOL_REF |
2221 | && !bfin_longcall_p (operands[1], INTVAL (operands[3]))" | |
96c30d2a | 2222 | "jump.l %1;" |
6d459e2b BS |
2223 | [(set_attr "type" "br") |
2224 | (set_attr "length" "4")]) | |
2225 | ||
2226 | (define_insn "*call_insn" | |
2227 | [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "a")) | |
2228 | (match_operand 1 "general_operand" "g")) | |
9840d30a BS |
2229 | (use (match_operand 2 "" "")) |
2230 | (clobber (reg:SI REG_RETS))] | |
6d459e2b BS |
2231 | "! SIBLING_CALL_P (insn)" |
2232 | "call (%0);" | |
2233 | [(set_attr "type" "call") | |
2234 | (set_attr "length" "2")]) | |
2235 | ||
2236 | (define_insn "*sibcall_insn" | |
2237 | [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "z")) | |
2238 | (match_operand 1 "general_operand" "g")) | |
2239 | (use (match_operand 2 "" "")) | |
2240 | (return)] | |
2241 | "SIBLING_CALL_P (insn)" | |
2242 | "jump (%0);" | |
2243 | [(set_attr "type" "br") | |
2244 | (set_attr "length" "2")]) | |
2245 | ||
2246 | (define_insn "*call_value_insn" | |
2247 | [(set (match_operand 0 "register_operand" "=d") | |
2248 | (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "a")) | |
2249 | (match_operand 2 "general_operand" "g"))) | |
9840d30a BS |
2250 | (use (match_operand 3 "" "")) |
2251 | (clobber (reg:SI REG_RETS))] | |
6d459e2b BS |
2252 | "! SIBLING_CALL_P (insn)" |
2253 | "call (%1);" | |
2254 | [(set_attr "type" "call") | |
2255 | (set_attr "length" "2")]) | |
2256 | ||
2257 | (define_insn "*sibcall_value_insn" | |
2258 | [(set (match_operand 0 "register_operand" "=d") | |
2259 | (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "z")) | |
2260 | (match_operand 2 "general_operand" "g"))) | |
2261 | (use (match_operand 3 "" "")) | |
2262 | (return)] | |
2263 | "SIBLING_CALL_P (insn)" | |
2264 | "jump (%1);" | |
0d4a78eb | 2265 | [(set_attr "type" "br") |
6d459e2b | 2266 | (set_attr "length" "2")]) |
0d4a78eb BS |
2267 | |
2268 | ;; Block move patterns | |
2269 | ||
2270 | ;; We cheat. This copies one more word than operand 2 indicates. | |
2271 | ||
2272 | (define_insn "rep_movsi" | |
2273 | [(set (match_operand:SI 0 "register_operand" "=&a") | |
2274 | (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0") | |
2275 | (ashift:SI (match_operand:SI 2 "register_operand" "a") | |
2276 | (const_int 2))) | |
2277 | (const_int 4))) | |
2278 | (set (match_operand:SI 1 "register_operand" "=&b") | |
2279 | (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1") | |
2280 | (ashift:SI (match_dup 2) (const_int 2))) | |
2281 | (const_int 4))) | |
2282 | (set (mem:BLK (match_dup 3)) | |
2283 | (mem:BLK (match_dup 4))) | |
2284 | (use (match_dup 2)) | |
b03149e1 JZ |
2285 | (clobber (match_scratch:HI 5 "=&d")) |
2286 | (clobber (reg:SI REG_LT1)) | |
2287 | (clobber (reg:SI REG_LC1)) | |
2288 | (clobber (reg:SI REG_LB1))] | |
0d4a78eb | 2289 | "" |
51a641fd | 2290 | "%5 = [%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || [%3++] = %5 || %5 = [%4++]; [%3++] = %5;" |
0d4a78eb | 2291 | [(set_attr "type" "misc") |
b03149e1 JZ |
2292 | (set_attr "length" "16") |
2293 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
2294 | |
2295 | (define_insn "rep_movhi" | |
2296 | [(set (match_operand:SI 0 "register_operand" "=&a") | |
2297 | (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0") | |
2298 | (ashift:SI (match_operand:SI 2 "register_operand" "a") | |
2299 | (const_int 1))) | |
2300 | (const_int 2))) | |
2301 | (set (match_operand:SI 1 "register_operand" "=&b") | |
2302 | (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1") | |
2303 | (ashift:SI (match_dup 2) (const_int 1))) | |
2304 | (const_int 2))) | |
2305 | (set (mem:BLK (match_dup 3)) | |
2306 | (mem:BLK (match_dup 4))) | |
2307 | (use (match_dup 2)) | |
b03149e1 JZ |
2308 | (clobber (match_scratch:HI 5 "=&d")) |
2309 | (clobber (reg:SI REG_LT1)) | |
2310 | (clobber (reg:SI REG_LC1)) | |
2311 | (clobber (reg:SI REG_LB1))] | |
0d4a78eb | 2312 | "" |
51a641fd | 2313 | "%h5 = W[%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || W [%3++] = %5 || %h5 = W [%4++]; W [%3++] = %5;" |
0d4a78eb | 2314 | [(set_attr "type" "misc") |
b03149e1 JZ |
2315 | (set_attr "length" "16") |
2316 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb | 2317 | |
144f8315 | 2318 | (define_expand "movmemsi" |
0d4a78eb BS |
2319 | [(match_operand:BLK 0 "general_operand" "") |
2320 | (match_operand:BLK 1 "general_operand" "") | |
2321 | (match_operand:SI 2 "const_int_operand" "") | |
2322 | (match_operand:SI 3 "const_int_operand" "")] | |
2323 | "" | |
2324 | { | |
144f8315 | 2325 | if (bfin_expand_movmem (operands[0], operands[1], operands[2], operands[3])) |
0d4a78eb BS |
2326 | DONE; |
2327 | FAIL; | |
2328 | }) | |
2329 | ||
2330 | ;; Conditional branch patterns | |
2331 | ;; The Blackfin has only few condition codes: eq, lt, lte, ltu, leu | |
2332 | ||
49373252 | 2333 | (define_insn "compare_eq" |
4729dc92 | 2334 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2335 | (eq:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2336 | (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] |
0d4a78eb BS |
2337 | "" |
2338 | "cc =%1==%2;" | |
2339 | [(set_attr "type" "compare")]) | |
2340 | ||
49373252 | 2341 | (define_insn "compare_ne" |
4729dc92 | 2342 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2343 | (ne:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2344 | (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] |
0d4a78eb BS |
2345 | "0" |
2346 | "cc =%1!=%2;" | |
2347 | [(set_attr "type" "compare")]) | |
2348 | ||
49373252 | 2349 | (define_insn "compare_lt" |
4729dc92 | 2350 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2351 | (lt:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2352 | (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] |
0d4a78eb BS |
2353 | "" |
2354 | "cc =%1<%2;" | |
2355 | [(set_attr "type" "compare")]) | |
2356 | ||
49373252 | 2357 | (define_insn "compare_le" |
4729dc92 | 2358 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2359 | (le:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2360 | (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] |
0d4a78eb BS |
2361 | "" |
2362 | "cc =%1<=%2;" | |
2363 | [(set_attr "type" "compare")]) | |
2364 | ||
49373252 | 2365 | (define_insn "compare_leu" |
4729dc92 | 2366 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2367 | (leu:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2368 | (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))] |
0d4a78eb BS |
2369 | "" |
2370 | "cc =%1<=%2 (iu);" | |
2371 | [(set_attr "type" "compare")]) | |
2372 | ||
49373252 | 2373 | (define_insn "compare_ltu" |
4729dc92 | 2374 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2375 | (ltu:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2376 | (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))] |
0d4a78eb BS |
2377 | "" |
2378 | "cc =%1<%2 (iu);" | |
2379 | [(set_attr "type" "compare")]) | |
2380 | ||
26c5953d BS |
2381 | ;; Same as above, but and CC with the overflow bit generated by the first |
2382 | ;; multiplication. | |
2383 | (define_insn "flag_mul_macv2hi_parts_acconly_andcc0" | |
2384 | [(set (match_operand:PDI 0 "register_operand" "=B,e,e") | |
2385 | (unspec:PDI [(vec_select:HI | |
2386 | (match_operand:V2HI 2 "register_operand" "d,d,d") | |
2387 | (parallel [(match_operand 4 "const01_operand" "P0P1,P0P1,P0P1")])) | |
2388 | (vec_select:HI | |
2389 | (match_operand:V2HI 3 "register_operand" "d,d,d") | |
2390 | (parallel [(match_operand 6 "const01_operand" "P0P1,P0P1,P0P1")])) | |
2391 | (match_operand 10 "const_int_operand" "PB,PA,PA")] | |
2392 | UNSPEC_MUL_WITH_FLAG)) | |
2393 | (set (match_operand:PDI 1 "register_operand" "=B,e,e") | |
2394 | (unspec:PDI [(vec_select:HI | |
2395 | (match_dup 2) | |
2396 | (parallel [(match_operand 5 "const01_operand" "P0P1,P0P1,P0P1")])) | |
2397 | (vec_select:HI | |
2398 | (match_dup 3) | |
2399 | (parallel [(match_operand 7 "const01_operand" "P0P1,P0P1,P0P1")])) | |
2400 | (match_operand:PDI 8 "register_operand" "1,1,1") | |
2401 | (match_operand 9 "const01_operand" "P0P1,P0P1,P0P1") | |
2402 | (match_operand 11 "const_int_operand" "PA,PB,PA")] | |
2403 | UNSPEC_MAC_WITH_FLAG)) | |
2404 | (set (reg:BI REG_CC) | |
2405 | (and:BI (reg:BI REG_CC) | |
2406 | (unspec:BI [(vec_select:HI (match_dup 2) (parallel [(match_dup 4)])) | |
2407 | (vec_select:HI (match_dup 3) (parallel [(match_dup 6)])) | |
2408 | (match_dup 10)] | |
2409 | UNSPEC_MUL_WITH_FLAG)))] | |
2410 | "MACFLAGS_MATCH_P (INTVAL (operands[10]), INTVAL (operands[11]))" | |
2411 | { | |
2412 | rtx xops[6]; | |
2413 | const char *templates[] = { | |
2414 | "%0 = %h2 * %h3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;", | |
2415 | "%0 = %d2 * %h3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;", | |
2416 | "%0 = %h2 * %h3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;", | |
2417 | "%0 = %d2 * %h3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;", | |
2418 | "%0 = %h2 * %d3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;", | |
2419 | "%0 = %d2 * %d3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;", | |
2420 | "%0 = %h2 * %d3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;", | |
2421 | "%0 = %d2 * %d3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;", | |
2422 | "%0 = %h2 * %h3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;", | |
2423 | "%0 = %d2 * %h3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;", | |
2424 | "%0 = %h2 * %h3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;", | |
2425 | "%0 = %d2 * %h3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;", | |
2426 | "%0 = %h2 * %d3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;", | |
2427 | "%0 = %d2 * %d3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;", | |
2428 | "%0 = %h2 * %d3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;", | |
2429 | "%0 = %d2 * %d3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;" }; | |
2430 | int alt = (INTVAL (operands[4]) + (INTVAL (operands[5]) << 1) | |
2431 | + (INTVAL (operands[6]) << 2) + (INTVAL (operands[7]) << 3)); | |
2432 | xops[0] = operands[0]; | |
2433 | xops[1] = operands[1]; | |
2434 | xops[2] = operands[2]; | |
2435 | xops[3] = operands[3]; | |
2436 | xops[4] = operands[9]; | |
2437 | xops[5] = which_alternative == 0 ? operands[10] : operands[11]; | |
2438 | output_asm_insn (templates[alt], xops); | |
2439 | return ""; | |
2440 | } | |
2441 | [(set_attr "type" "misc") | |
2442 | (set_attr "length" "6") | |
2443 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb | 2444 | |
f90b7a5a PB |
2445 | (define_expand "cbranchsi4" |
2446 | [(set (pc) | |
2447 | (if_then_else (match_operator 0 "ordered_comparison_operator" | |
2448 | [(match_operand:SI 1 "register_operand" "") | |
2449 | (match_operand:SI 2 "reg_or_const_int_operand" "")]) | |
2450 | (label_ref (match_operand 3 "" "")) | |
2451 | (pc)))] | |
0d4a78eb BS |
2452 | "" |
2453 | { | |
f90b7a5a PB |
2454 | rtx bi_compare = bfin_gen_compare (operands[0], SImode); |
2455 | emit_jump_insn (gen_cbranchbi4 (bi_compare, bfin_cc_rtx, CONST0_RTX (BImode), | |
2456 | operands[3])); | |
2457 | DONE; | |
0d4a78eb BS |
2458 | }) |
2459 | ||
2460 | (define_insn "cbranchbi4" | |
2461 | [(set (pc) | |
2462 | (if_then_else | |
f90b7a5a | 2463 | (match_operator 0 "bfin_bimode_comparison_operator" |
4729dc92 | 2464 | [(match_operand:BI 1 "register_operand" "C") |
0d4a78eb BS |
2465 | (match_operand:BI 2 "immediate_operand" "P0")]) |
2466 | (label_ref (match_operand 3 "" "")) | |
2467 | (pc)))] | |
2468 | "" | |
2469 | { | |
2470 | asm_conditional_branch (insn, operands, 0, 0); | |
2471 | return ""; | |
2472 | } | |
2473 | [(set_attr "type" "brcc")]) | |
2474 | ||
2475 | ;; Special cbranch patterns to deal with the speculative load problem - see | |
2476 | ;; bfin_reorg for details. | |
2477 | ||
2478 | (define_insn "cbranch_predicted_taken" | |
2479 | [(set (pc) | |
2480 | (if_then_else | |
f90b7a5a | 2481 | (match_operator 0 "bfin_bimode_comparison_operator" |
4729dc92 | 2482 | [(match_operand:BI 1 "register_operand" "C") |
0d4a78eb BS |
2483 | (match_operand:BI 2 "immediate_operand" "P0")]) |
2484 | (label_ref (match_operand 3 "" "")) | |
2485 | (pc))) | |
2486 | (unspec [(const_int 0)] UNSPEC_CBRANCH_TAKEN)] | |
2487 | "" | |
2488 | { | |
2489 | asm_conditional_branch (insn, operands, 0, 1); | |
2490 | return ""; | |
2491 | } | |
2492 | [(set_attr "type" "brcc")]) | |
2493 | ||
2494 | (define_insn "cbranch_with_nops" | |
2495 | [(set (pc) | |
2496 | (if_then_else | |
f90b7a5a | 2497 | (match_operator 0 "bfin_bimode_comparison_operator" |
4729dc92 | 2498 | [(match_operand:BI 1 "register_operand" "C") |
0d4a78eb BS |
2499 | (match_operand:BI 2 "immediate_operand" "P0")]) |
2500 | (label_ref (match_operand 3 "" "")) | |
2501 | (pc))) | |
2502 | (unspec [(match_operand 4 "immediate_operand" "")] UNSPEC_CBRANCH_NOPS)] | |
2503 | "reload_completed" | |
2504 | { | |
2505 | asm_conditional_branch (insn, operands, INTVAL (operands[4]), 0); | |
2506 | return ""; | |
2507 | } | |
2508 | [(set_attr "type" "brcc") | |
90cbba02 | 2509 | (set_attr "length" "8")]) |
0d4a78eb | 2510 | |
f90b7a5a | 2511 | ;; setcc insns. |
0d4a78eb | 2512 | |
f90b7a5a PB |
2513 | (define_expand "cstorebi4" |
2514 | [(set (match_dup 4) | |
2515 | (match_operator:BI 1 "bfin_bimode_comparison_operator" | |
2516 | [(match_operand:BI 2 "register_operand" "") | |
2517 | (match_operand:BI 3 "reg_or_const_int_operand" "")])) | |
0d4a78eb | 2518 | (set (match_operand:SI 0 "register_operand" "") |
f90b7a5a | 2519 | (ne:SI (match_dup 4) (const_int 0)))] |
0d4a78eb BS |
2520 | "" |
2521 | { | |
f90b7a5a PB |
2522 | /* It could be expanded as a movbisi instruction, but the portable |
2523 | alternative produces better code. */ | |
2524 | if (GET_CODE (operands[1]) == NE) | |
2525 | FAIL; | |
0d4a78eb | 2526 | |
f90b7a5a | 2527 | operands[4] = bfin_cc_rtx; |
0d4a78eb BS |
2528 | }) |
2529 | ||
f90b7a5a PB |
2530 | (define_expand "cstoresi4" |
2531 | [(set (match_operand:SI 0 "register_operand") | |
2532 | (match_operator:SI 1 "ordered_comparison_operator" | |
2533 | [(match_operand:SI 2 "register_operand" "") | |
2534 | (match_operand:SI 3 "reg_or_const_int_operand" "")]))] | |
0d4a78eb BS |
2535 | "" |
2536 | { | |
f90b7a5a | 2537 | rtx bi_compare, test; |
0d4a78eb | 2538 | |
f90b7a5a PB |
2539 | if (!bfin_direct_comparison_operator (operands[1], SImode)) |
2540 | { | |
2541 | if (!register_operand (operands[3], SImode) | |
2542 | || GET_CODE (operands[1]) == NE) | |
2543 | FAIL; | |
2544 | test = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])), | |
2545 | SImode, operands[3], operands[2]); | |
2546 | } | |
2547 | else | |
2548 | test = operands[1]; | |
2549 | ||
2550 | bi_compare = bfin_gen_compare (test, SImode); | |
2551 | gcc_assert (GET_CODE (bi_compare) == NE); | |
2552 | emit_insn (gen_movbisi (operands[0], bfin_cc_rtx)); | |
2553 | DONE; | |
0d4a78eb BS |
2554 | }) |
2555 | ||
2556 | (define_insn "nop" | |
2557 | [(const_int 0)] | |
2558 | "" | |
2559 | "nop;") | |
2560 | ||
b18e284e BS |
2561 | ;; A nop which stays there when emitted. |
2562 | (define_insn "forced_nop" | |
2563 | [(unspec [(const_int 0)] UNSPEC_NOP)] | |
2564 | "" | |
2565 | "nop;") | |
2566 | ||
bbbc206e BS |
2567 | (define_insn "mnop" |
2568 | [(unspec [(const_int 0)] UNSPEC_32BIT)] | |
2569 | "" | |
2570 | "mnop%!" | |
2571 | [(set_attr "type" "dsp32")]) | |
2572 | ||
0d4a78eb BS |
2573 | ;;;;;;;;;;;;;;;;;;;; CC2dreg ;;;;;;;;;;;;;;;;;;;;;;;;; |
2574 | (define_insn "movsibi" | |
4729dc92 | 2575 | [(set (match_operand:BI 0 "register_operand" "=C") |
0d4a78eb BS |
2576 | (ne:BI (match_operand:SI 1 "register_operand" "d") |
2577 | (const_int 0)))] | |
2578 | "" | |
2579 | "CC = %1;" | |
2580 | [(set_attr "length" "2")]) | |
2581 | ||
f90b7a5a | 2582 | (define_insn_and_split "movbisi" |
0d4a78eb | 2583 | [(set (match_operand:SI 0 "register_operand" "=d") |
4729dc92 | 2584 | (ne:SI (match_operand:BI 1 "register_operand" "C") |
0d4a78eb BS |
2585 | (const_int 0)))] |
2586 | "" | |
f90b7a5a PB |
2587 | "#" |
2588 | "" | |
2589 | [(set (match_operand:SI 0 "register_operand" "") | |
2590 | (zero_extend:SI (match_operand:BI 1 "register_operand" "")))] | |
2591 | "") | |
0d4a78eb | 2592 | |
e4fae5f7 | 2593 | (define_insn "notbi" |
4729dc92 BS |
2594 | [(set (match_operand:BI 0 "register_operand" "=C") |
2595 | (eq:BI (match_operand:BI 1 "register_operand" " 0") | |
0d4a78eb BS |
2596 | (const_int 0)))] |
2597 | "" | |
2598 | "%0 = ! %0;" /* NOT CC;" */ | |
2599 | [(set_attr "type" "compare")]) | |
2600 | ||
2601 | ;; Vector and DSP insns | |
2602 | ||
2603 | (define_insn "" | |
2604 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2605 | (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") | |
2606 | (const_int 24)) | |
2607 | (lshiftrt:SI (match_operand:SI 2 "register_operand" "d") | |
2608 | (const_int 8))))] | |
2609 | "" | |
bbbc206e | 2610 | "%0 = ALIGN8(%1, %2)%!" |
0d4a78eb BS |
2611 | [(set_attr "type" "dsp32")]) |
2612 | ||
2613 | (define_insn "" | |
2614 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2615 | (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") | |
2616 | (const_int 16)) | |
2617 | (lshiftrt:SI (match_operand:SI 2 "register_operand" "d") | |
2618 | (const_int 16))))] | |
2619 | "" | |
bbbc206e | 2620 | "%0 = ALIGN16(%1, %2)%!" |
0d4a78eb BS |
2621 | [(set_attr "type" "dsp32")]) |
2622 | ||
2623 | (define_insn "" | |
2624 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2625 | (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") | |
2626 | (const_int 8)) | |
2627 | (lshiftrt:SI (match_operand:SI 2 "register_operand" "d") | |
2628 | (const_int 24))))] | |
2629 | "" | |
bbbc206e | 2630 | "%0 = ALIGN24(%1, %2)%!" |
0d4a78eb BS |
2631 | [(set_attr "type" "dsp32")]) |
2632 | ||
2633 | ;; Prologue and epilogue. | |
2634 | ||
2635 | (define_expand "prologue" | |
2636 | [(const_int 1)] | |
2637 | "" | |
2638 | "bfin_expand_prologue (); DONE;") | |
2639 | ||
2640 | (define_expand "epilogue" | |
2641 | [(const_int 1)] | |
2642 | "" | |
1f9e4ca1 | 2643 | "bfin_expand_epilogue (1, 0, 0); DONE;") |
0d4a78eb BS |
2644 | |
2645 | (define_expand "sibcall_epilogue" | |
2646 | [(const_int 1)] | |
2647 | "" | |
1f9e4ca1 | 2648 | "bfin_expand_epilogue (0, 0, 1); DONE;") |
0d4a78eb BS |
2649 | |
2650 | (define_expand "eh_return" | |
cd9c1ca8 | 2651 | [(use (match_operand:SI 0 "register_operand" ""))] |
0d4a78eb BS |
2652 | "" |
2653 | { | |
1ca950ca | 2654 | emit_insn (gen_eh_store_handler (EH_RETURN_HANDLER_RTX, operands[0])); |
1e96b1c3 | 2655 | emit_jump_insn (gen_eh_return_internal ()); |
0d4a78eb | 2656 | emit_barrier (); |
4193ce73 | 2657 | DONE; |
0d4a78eb BS |
2658 | }) |
2659 | ||
1ca950ca BS |
2660 | (define_insn "eh_store_handler" |
2661 | [(unspec_volatile [(match_operand:SI 1 "register_operand" "da")] | |
2662 | UNSPEC_VOLATILE_STORE_EH_HANDLER) | |
2663 | (clobber (match_operand:SI 0 "memory_operand" "=m"))] | |
2664 | "" | |
2665 | "%0 = %1%!" | |
2666 | [(set_attr "type" "mcst")]) | |
2667 | ||
0d4a78eb | 2668 | (define_insn_and_split "eh_return_internal" |
cd9c1ca8 | 2669 | [(eh_return)] |
0d4a78eb BS |
2670 | "" |
2671 | "#" | |
cd9c1ca8 | 2672 | "epilogue_completed" |
0d4a78eb | 2673 | [(const_int 1)] |
1f9e4ca1 | 2674 | "bfin_expand_epilogue (1, 1, 0); DONE;") |
0d4a78eb BS |
2675 | |
2676 | (define_insn "link" | |
2677 | [(set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -4))) (reg:SI REG_RETS)) | |
2678 | (set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -8))) (reg:SI REG_FP)) | |
2679 | (set (reg:SI REG_FP) | |
2680 | (plus:SI (reg:SI REG_SP) (const_int -8))) | |
2681 | (set (reg:SI REG_SP) | |
2682 | (plus:SI (reg:SI REG_SP) (match_operand:SI 0 "immediate_operand" "i")))] | |
2683 | "" | |
2684 | "LINK %Z0;" | |
2685 | [(set_attr "length" "4")]) | |
2686 | ||
2687 | (define_insn "unlink" | |
2688 | [(set (reg:SI REG_FP) (mem:SI (reg:SI REG_FP))) | |
2689 | (set (reg:SI REG_RETS) (mem:SI (plus:SI (reg:SI REG_FP) (const_int 4)))) | |
2690 | (set (reg:SI REG_SP) (plus:SI (reg:SI REG_FP) (const_int 8)))] | |
2691 | "" | |
2692 | "UNLINK;" | |
2693 | [(set_attr "length" "4")]) | |
2694 | ||
2695 | ;; This pattern is slightly clumsy. The stack adjust must be the final SET in | |
2696 | ;; the pattern, otherwise dwarf2out becomes very confused about which reg goes | |
2697 | ;; where on the stack, since it goes through all elements of the parallel in | |
2698 | ;; sequence. | |
2699 | (define_insn "push_multiple" | |
2700 | [(match_parallel 0 "push_multiple_operation" | |
2701 | [(unspec [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_PUSH_MULTIPLE)])] | |
2702 | "" | |
2703 | { | |
2704 | output_push_multiple (insn, operands); | |
2705 | return ""; | |
2706 | }) | |
2707 | ||
2708 | (define_insn "pop_multiple" | |
2709 | [(match_parallel 0 "pop_multiple_operation" | |
2710 | [(set (reg:SI REG_SP) | |
2711 | (plus:SI (reg:SI REG_SP) (match_operand:SI 1 "immediate_operand" "i")))])] | |
2712 | "" | |
2713 | { | |
2714 | output_pop_multiple (insn, operands); | |
2715 | return ""; | |
2716 | }) | |
2717 | ||
2718 | (define_insn "return_internal" | |
2719 | [(return) | |
9840d30a | 2720 | (use (match_operand 0 "register_operand" ""))] |
0d4a78eb BS |
2721 | "reload_completed" |
2722 | { | |
9840d30a | 2723 | switch (REGNO (operands[0])) |
0d4a78eb | 2724 | { |
9840d30a | 2725 | case REG_RETX: |
0d4a78eb | 2726 | return "rtx;"; |
9840d30a | 2727 | case REG_RETN: |
0d4a78eb | 2728 | return "rtn;"; |
9840d30a | 2729 | case REG_RETI: |
0d4a78eb | 2730 | return "rti;"; |
9840d30a | 2731 | case REG_RETS: |
0d4a78eb BS |
2732 | return "rts;"; |
2733 | } | |
2734 | gcc_unreachable (); | |
2735 | }) | |
2736 | ||
c7cb1555 BS |
2737 | ;; When used at a location where CC contains 1, causes a speculative load |
2738 | ;; that is later cancelled. This is used for certain workarounds in | |
2739 | ;; interrupt handler prologues. | |
669eeb28 BS |
2740 | (define_insn "dummy_load" |
2741 | [(unspec_volatile [(match_operand 0 "register_operand" "a") | |
2742 | (match_operand 1 "register_operand" "C")] | |
2743 | UNSPEC_VOLATILE_DUMMY)] | |
2744 | "" | |
2745 | "if cc jump 4;\n\tr7 = [%0];" | |
2746 | [(set_attr "type" "misc") | |
2747 | (set_attr "length" "4") | |
2748 | (set_attr "seq_insns" "multi")]) | |
2749 | ||
c7cb1555 BS |
2750 | ;; A placeholder insn inserted before the final scheduling pass. It is used |
2751 | ;; to improve scheduling of loads when workarounds for speculative loads are | |
2752 | ;; needed, by not placing them in the first few cycles after a conditional | |
2753 | ;; branch. | |
2754 | (define_insn "stall" | |
2755 | [(unspec_volatile [(match_operand 0 "const_int_operand" "P1P3")] | |
2756 | UNSPEC_VOLATILE_STALL)] | |
2757 | "" | |
2758 | "" | |
2759 | [(set_attr "type" "stall")]) | |
2760 | ||
5fcead21 BS |
2761 | (define_insn "csync" |
2762 | [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_CSYNC)] | |
2763 | "" | |
2764 | "csync;" | |
3fb192d2 | 2765 | [(set_attr "type" "sync")]) |
5fcead21 BS |
2766 | |
2767 | (define_insn "ssync" | |
2768 | [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_SSYNC)] | |
2769 | "" | |
2770 | "ssync;" | |
3fb192d2 | 2771 | [(set_attr "type" "sync")]) |
5fcead21 | 2772 | |
3d33a056 JZ |
2773 | (define_insn "trap" |
2774 | [(trap_if (const_int 1) (const_int 3))] | |
2775 | "" | |
2776 | "excpt 3;" | |
2777 | [(set_attr "type" "misc") | |
2778 | (set_attr "length" "2")]) | |
2779 | ||
09350e36 BS |
2780 | (define_insn "trapifcc" |
2781 | [(trap_if (reg:BI REG_CC) (const_int 3))] | |
2782 | "" | |
2783 | "if !cc jump 4 (bp); excpt 3;" | |
2784 | [(set_attr "type" "misc") | |
b03149e1 JZ |
2785 | (set_attr "length" "4") |
2786 | (set_attr "seq_insns" "multi")]) | |
09350e36 | 2787 | |
0d4a78eb BS |
2788 | ;;; Vector instructions |
2789 | ||
75d8b2d0 BS |
2790 | ;; First, all sorts of move variants |
2791 | ||
75d8b2d0 BS |
2792 | (define_insn "movhiv2hi_low" |
2793 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2794 | (vec_concat:V2HI | |
2795 | (match_operand:HI 2 "register_operand" "d") | |
2796 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
2797 | (parallel [(const_int 1)]))))] | |
2798 | "" | |
bbbc206e | 2799 | "%h0 = %h2 << 0%!" |
b3187e24 | 2800 | [(set_attr "type" "dsp32shiftimm")]) |
75d8b2d0 BS |
2801 | |
2802 | (define_insn "movhiv2hi_high" | |
2803 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2804 | (vec_concat:V2HI | |
2805 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
2806 | (parallel [(const_int 0)])) | |
2807 | (match_operand:HI 2 "register_operand" "d")))] | |
2808 | "" | |
bbbc206e | 2809 | "%d0 = %h2 << 0%!" |
b3187e24 | 2810 | [(set_attr "type" "dsp32shiftimm")]) |
75d8b2d0 BS |
2811 | |
2812 | ;; No earlyclobber on alternative two since our sequence ought to be safe. | |
2813 | ;; The order of operands is intentional to match the VDSP builtin (high word | |
2814 | ;; is passed first). | |
2815 | (define_insn_and_split "composev2hi" | |
2816 | [(set (match_operand:V2HI 0 "register_operand" "=d,d") | |
2817 | (vec_concat:V2HI (match_operand:HI 2 "register_operand" "0,d") | |
2818 | (match_operand:HI 1 "register_operand" "d,d")))] | |
2819 | "" | |
2820 | "@ | |
23cf1526 | 2821 | %d0 = %h1 << 0%! |
75d8b2d0 BS |
2822 | #" |
2823 | "reload_completed" | |
2824 | [(set (match_dup 0) | |
2825 | (vec_concat:V2HI | |
2826 | (vec_select:HI (match_dup 0) (parallel [(const_int 0)])) | |
23cf1526 | 2827 | (match_dup 1))) |
75d8b2d0 BS |
2828 | (set (match_dup 0) |
2829 | (vec_concat:V2HI | |
23cf1526 | 2830 | (match_dup 2) |
75d8b2d0 BS |
2831 | (vec_select:HI (match_dup 0) (parallel [(const_int 1)]))))] |
2832 | "" | |
b3187e24 | 2833 | [(set_attr "type" "dsp32shiftimm")]) |
75d8b2d0 BS |
2834 | |
2835 | ; Like composev2hi, but operating on elements of V2HI vectors. | |
2836 | ; Useful on its own, and as a combiner bridge for the multiply and | |
2837 | ; mac patterns. | |
2838 | (define_insn "packv2hi" | |
2d3649b2 | 2839 | [(set (match_operand:V2HI 0 "register_operand" "=d,d,d,d,d,d,d,d") |
75d8b2d0 | 2840 | (vec_concat:V2HI (vec_select:HI |
2d3649b2 BS |
2841 | (match_operand:V2HI 1 "register_operand" "0,0,d,d,d,d,d,d") |
2842 | (parallel [(match_operand 3 "const01_operand" "P0,P0,P0,P1,P0,P1,P0,P1")])) | |
75d8b2d0 | 2843 | (vec_select:HI |
2d3649b2 BS |
2844 | (match_operand:V2HI 2 "register_operand" "d,d,0,0,d,d,d,d") |
2845 | (parallel [(match_operand 4 "const01_operand" "P0,P1,P1,P1,P0,P0,P1,P1")]))))] | |
75d8b2d0 BS |
2846 | "" |
2847 | "@ | |
2d3649b2 BS |
2848 | %d0 = %h2 << 0%! |
2849 | %d0 = %d2 << 0%! | |
2850 | %h0 = %h1 << 0%! | |
2851 | %h0 = %d1 << 0%! | |
bbbc206e BS |
2852 | %0 = PACK (%h2,%h1)%! |
2853 | %0 = PACK (%h2,%d1)%! | |
2854 | %0 = PACK (%d2,%h1)%! | |
2855 | %0 = PACK (%d2,%d1)%!" | |
b3187e24 | 2856 | [(set_attr "type" "dsp32shiftimm,dsp32shiftimm,dsp32shiftimm,dsp32shiftimm,dsp32,dsp32,dsp32,dsp32")]) |
75d8b2d0 BS |
2857 | |
2858 | (define_insn "movv2hi_hi" | |
2859 | [(set (match_operand:HI 0 "register_operand" "=d,d,d") | |
2860 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0,d,d") | |
554006bd | 2861 | (parallel [(match_operand 2 "const01_operand" "P0,P0,P1")])))] |
75d8b2d0 BS |
2862 | "" |
2863 | "@ | |
2864 | /* optimized out */ | |
bbbc206e BS |
2865 | %h0 = %h1 << 0%! |
2866 | %h0 = %d1 << 0%!" | |
b3187e24 | 2867 | [(set_attr "type" "dsp32shiftimm")]) |
75d8b2d0 BS |
2868 | |
2869 | (define_expand "movv2hi_hi_low" | |
2870 | [(set (match_operand:HI 0 "register_operand" "") | |
2871 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "") | |
2872 | (parallel [(const_int 0)])))] | |
2873 | "" | |
2874 | "") | |
2875 | ||
2876 | (define_expand "movv2hi_hi_high" | |
2877 | [(set (match_operand:HI 0 "register_operand" "") | |
2878 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "") | |
2879 | (parallel [(const_int 1)])))] | |
2880 | "" | |
2881 | "") | |
2882 | ||
942fd98f | 2883 | ;; Unusual arithmetic operations on 16-bit registers. |
75d8b2d0 | 2884 | |
a0a31d1e BS |
2885 | (define_code_iterator sp_or_sm [ss_plus ss_minus]) |
2886 | (define_code_attr spm_string [(ss_plus "+") (ss_minus "-")]) | |
2887 | (define_code_attr spm_name [(ss_plus "add") (ss_minus "sub")]) | |
2888 | ||
2889 | (define_insn "ss<spm_name>hi3" | |
75d8b2d0 | 2890 | [(set (match_operand:HI 0 "register_operand" "=d") |
a0a31d1e | 2891 | (sp_or_sm:HI (match_operand:HI 1 "register_operand" "d") |
75d8b2d0 BS |
2892 | (match_operand:HI 2 "register_operand" "d")))] |
2893 | "" | |
a0a31d1e | 2894 | "%h0 = %h1 <spm_string> %h2 (S)%!" |
75d8b2d0 BS |
2895 | [(set_attr "type" "dsp32")]) |
2896 | ||
a0a31d1e BS |
2897 | (define_insn "ss<spm_name>hi3_parts" |
2898 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2899 | (sp_or_sm:HI (vec_select:HI | |
2900 | (match_operand:V2HI 1 "register_operand" "d") | |
2901 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) | |
2902 | (vec_select:HI | |
2903 | (match_operand:V2HI 2 "register_operand" "d") | |
2904 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))))] | |
2905 | "" | |
1d7d5ac4 BS |
2906 | { |
2907 | const char *templates[] = { | |
a0a31d1e BS |
2908 | "%h0 = %h1 <spm_string> %h2 (S)%!", |
2909 | "%h0 = %d1 <spm_string> %h2 (S)%!", | |
2910 | "%h0 = %h1 <spm_string> %d2 (S)%!", | |
2911 | "%h0 = %d1 <spm_string> %d2 (S)%!" }; | |
2912 | int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1); | |
1d7d5ac4 BS |
2913 | return templates[alt]; |
2914 | } | |
2915 | [(set_attr "type" "dsp32")]) | |
2916 | ||
a0a31d1e BS |
2917 | (define_insn "ss<spm_name>hi3_low_parts" |
2918 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2919 | (vec_concat:V2HI | |
2920 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
2921 | (parallel [(const_int 0)])) | |
2922 | (sp_or_sm:HI (vec_select:HI | |
2923 | (match_operand:V2HI 2 "register_operand" "d") | |
2924 | (parallel [(match_operand 4 "const01_operand" "P0P1")])) | |
2925 | (vec_select:HI | |
2926 | (match_operand:V2HI 3 "register_operand" "d") | |
2927 | (parallel [(match_operand 5 "const01_operand" "P0P1")])))))] | |
2928 | "" | |
1d7d5ac4 BS |
2929 | { |
2930 | const char *templates[] = { | |
a0a31d1e BS |
2931 | "%h0 = %h2 <spm_string> %h3 (S)%!", |
2932 | "%h0 = %d2 <spm_string> %h3 (S)%!", | |
2933 | "%h0 = %h2 <spm_string> %d3 (S)%!", | |
2934 | "%h0 = %d2 <spm_string> %d3 (S)%!" }; | |
2935 | int alt = INTVAL (operands[4]) + (INTVAL (operands[5]) << 1); | |
1d7d5ac4 BS |
2936 | return templates[alt]; |
2937 | } | |
2938 | [(set_attr "type" "dsp32")]) | |
2939 | ||
a0a31d1e BS |
2940 | (define_insn "ss<spm_name>hi3_high_parts" |
2941 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2942 | (vec_concat:V2HI | |
2943 | (sp_or_sm:HI (vec_select:HI | |
2944 | (match_operand:V2HI 2 "register_operand" "d") | |
2945 | (parallel [(match_operand 4 "const01_operand" "P0P1")])) | |
2946 | (vec_select:HI | |
2947 | (match_operand:V2HI 3 "register_operand" "d") | |
2948 | (parallel [(match_operand 5 "const01_operand" "P0P1")]))) | |
2949 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
2950 | (parallel [(const_int 1)]))))] | |
2951 | "" | |
2952 | { | |
2953 | const char *templates[] = { | |
2954 | "%d0 = %h2 <spm_string> %h3 (S)%!", | |
2955 | "%d0 = %d2 <spm_string> %h3 (S)%!", | |
2956 | "%d0 = %h2 <spm_string> %d3 (S)%!", | |
2957 | "%d0 = %d2 <spm_string> %d3 (S)%!" }; | |
2958 | int alt = INTVAL (operands[4]) + (INTVAL (operands[5]) << 1); | |
2959 | return templates[alt]; | |
2960 | } | |
75d8b2d0 BS |
2961 | [(set_attr "type" "dsp32")]) |
2962 | ||
2963 | ;; V2HI vector insns | |
2964 | ||
c9b3f817 | 2965 | (define_insn "addv2hi3" |
0d4a78eb BS |
2966 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
2967 | (plus:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
2968 | (match_operand:V2HI 2 "register_operand" "d")))] | |
2969 | "" | |
bbbc206e | 2970 | "%0 = %1 +|+ %2%!" |
0d4a78eb BS |
2971 | [(set_attr "type" "dsp32")]) |
2972 | ||
75d8b2d0 BS |
2973 | (define_insn "ssaddv2hi3" |
2974 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2975 | (ss_plus:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
2976 | (match_operand:V2HI 2 "register_operand" "d")))] | |
2977 | "" | |
bbbc206e | 2978 | "%0 = %1 +|+ %2 (S)%!" |
75d8b2d0 BS |
2979 | [(set_attr "type" "dsp32")]) |
2980 | ||
c9b3f817 | 2981 | (define_insn "subv2hi3" |
0d4a78eb BS |
2982 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
2983 | (minus:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
2984 | (match_operand:V2HI 2 "register_operand" "d")))] | |
2985 | "" | |
bbbc206e | 2986 | "%0 = %1 -|- %2%!" |
0d4a78eb BS |
2987 | [(set_attr "type" "dsp32")]) |
2988 | ||
75d8b2d0 BS |
2989 | (define_insn "sssubv2hi3" |
2990 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2991 | (ss_minus:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
2992 | (match_operand:V2HI 2 "register_operand" "d")))] | |
2993 | "" | |
bbbc206e | 2994 | "%0 = %1 -|- %2 (S)%!" |
75d8b2d0 BS |
2995 | [(set_attr "type" "dsp32")]) |
2996 | ||
2997 | (define_insn "addsubv2hi3" | |
2998 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2999 | (vec_concat:V2HI | |
3000 | (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3001 | (parallel [(const_int 0)])) | |
3002 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3003 | (parallel [(const_int 0)]))) | |
3004 | (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])) | |
3005 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3006 | "" | |
bbbc206e | 3007 | "%0 = %1 +|- %2%!" |
75d8b2d0 BS |
3008 | [(set_attr "type" "dsp32")]) |
3009 | ||
3010 | (define_insn "subaddv2hi3" | |
3011 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3012 | (vec_concat:V2HI | |
3013 | (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3014 | (parallel [(const_int 0)])) | |
3015 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3016 | (parallel [(const_int 0)]))) | |
3017 | (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])) | |
3018 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3019 | "" | |
bbbc206e | 3020 | "%0 = %1 -|+ %2%!" |
75d8b2d0 BS |
3021 | [(set_attr "type" "dsp32")]) |
3022 | ||
3023 | (define_insn "ssaddsubv2hi3" | |
3024 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3025 | (vec_concat:V2HI | |
3026 | (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3027 | (parallel [(const_int 0)])) | |
3028 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3029 | (parallel [(const_int 0)]))) | |
3030 | (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])) | |
3031 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3032 | "" | |
bbbc206e | 3033 | "%0 = %1 +|- %2 (S)%!" |
75d8b2d0 BS |
3034 | [(set_attr "type" "dsp32")]) |
3035 | ||
3036 | (define_insn "sssubaddv2hi3" | |
3037 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3038 | (vec_concat:V2HI | |
3039 | (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3040 | (parallel [(const_int 0)])) | |
3041 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3042 | (parallel [(const_int 0)]))) | |
3043 | (ss_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])) | |
3044 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3045 | "" | |
bbbc206e | 3046 | "%0 = %1 -|+ %2 (S)%!" |
75d8b2d0 BS |
3047 | [(set_attr "type" "dsp32")]) |
3048 | ||
3049 | (define_insn "sublohiv2hi3" | |
3050 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3051 | (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3052 | (parallel [(const_int 1)])) | |
3053 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3054 | (parallel [(const_int 0)]))))] | |
3055 | "" | |
bbbc206e | 3056 | "%h0 = %d1 - %h2%!" |
75d8b2d0 BS |
3057 | [(set_attr "type" "dsp32")]) |
3058 | ||
3059 | (define_insn "subhilov2hi3" | |
3060 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3061 | (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3062 | (parallel [(const_int 0)])) | |
3063 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3064 | (parallel [(const_int 1)]))))] | |
3065 | "" | |
bbbc206e | 3066 | "%h0 = %h1 - %d2%!" |
75d8b2d0 BS |
3067 | [(set_attr "type" "dsp32")]) |
3068 | ||
3069 | (define_insn "sssublohiv2hi3" | |
3070 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3071 | (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3072 | (parallel [(const_int 1)])) | |
3073 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3074 | (parallel [(const_int 0)]))))] | |
3075 | "" | |
bbbc206e | 3076 | "%h0 = %d1 - %h2 (S)%!" |
75d8b2d0 BS |
3077 | [(set_attr "type" "dsp32")]) |
3078 | ||
3079 | (define_insn "sssubhilov2hi3" | |
3080 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3081 | (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3082 | (parallel [(const_int 0)])) | |
3083 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3084 | (parallel [(const_int 1)]))))] | |
3085 | "" | |
bbbc206e | 3086 | "%h0 = %h1 - %d2 (S)%!" |
75d8b2d0 BS |
3087 | [(set_attr "type" "dsp32")]) |
3088 | ||
3089 | (define_insn "addlohiv2hi3" | |
3090 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3091 | (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3092 | (parallel [(const_int 1)])) | |
3093 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3094 | (parallel [(const_int 0)]))))] | |
3095 | "" | |
bbbc206e | 3096 | "%h0 = %d1 + %h2%!" |
75d8b2d0 BS |
3097 | [(set_attr "type" "dsp32")]) |
3098 | ||
3099 | (define_insn "addhilov2hi3" | |
3100 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3101 | (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3102 | (parallel [(const_int 0)])) | |
3103 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3104 | (parallel [(const_int 1)]))))] | |
3105 | "" | |
bbbc206e | 3106 | "%h0 = %h1 + %d2%!" |
75d8b2d0 BS |
3107 | [(set_attr "type" "dsp32")]) |
3108 | ||
3109 | (define_insn "ssaddlohiv2hi3" | |
3110 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3111 | (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3112 | (parallel [(const_int 1)])) | |
3113 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3114 | (parallel [(const_int 0)]))))] | |
3115 | "" | |
bbbc206e | 3116 | "%h0 = %d1 + %h2 (S)%!" |
75d8b2d0 BS |
3117 | [(set_attr "type" "dsp32")]) |
3118 | ||
3119 | (define_insn "ssaddhilov2hi3" | |
3120 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3121 | (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3122 | (parallel [(const_int 0)])) | |
3123 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3124 | (parallel [(const_int 1)]))))] | |
3125 | "" | |
bbbc206e | 3126 | "%h0 = %h1 + %d2 (S)%!" |
75d8b2d0 BS |
3127 | [(set_attr "type" "dsp32")]) |
3128 | ||
c9b3f817 | 3129 | (define_insn "sminv2hi3" |
0d4a78eb BS |
3130 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
3131 | (smin:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
3132 | (match_operand:V2HI 2 "register_operand" "d")))] | |
3133 | "" | |
bbbc206e | 3134 | "%0 = MIN (%1, %2) (V)%!" |
0d4a78eb BS |
3135 | [(set_attr "type" "dsp32")]) |
3136 | ||
c9b3f817 | 3137 | (define_insn "smaxv2hi3" |
0d4a78eb BS |
3138 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
3139 | (smax:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
3140 | (match_operand:V2HI 2 "register_operand" "d")))] | |
3141 | "" | |
bbbc206e | 3142 | "%0 = MAX (%1, %2) (V)%!" |
0d4a78eb BS |
3143 | [(set_attr "type" "dsp32")]) |
3144 | ||
75d8b2d0 BS |
3145 | ;; Multiplications. |
3146 | ||
3147 | ;; The Blackfin allows a lot of different options, and we need many patterns to | |
3148 | ;; cover most of the hardware's abilities. | |
3149 | ;; There are a few simple patterns using MULT rtx codes, but most of them use | |
3150 | ;; an unspec with a const_int operand that determines which flag to use in the | |
3151 | ;; instruction. | |
3152 | ;; There are variants for single and parallel multiplications. | |
942fd98f | 3153 | ;; There are variants which just use 16-bit lowparts as inputs, and variants |
75d8b2d0 BS |
3154 | ;; which allow the user to choose just which halves to use as input values. |
3155 | ;; There are variants which set D registers, variants which set accumulators, | |
3156 | ;; variants which set both, some of them optionally using the accumulators as | |
3157 | ;; inputs for multiply-accumulate operations. | |
3158 | ||
3159 | (define_insn "flag_mulhi" | |
3160 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3161 | (unspec:HI [(match_operand:HI 1 "register_operand" "d") | |
3162 | (match_operand:HI 2 "register_operand" "d") | |
3163 | (match_operand 3 "const_int_operand" "n")] | |
3164 | UNSPEC_MUL_WITH_FLAG))] | |
3165 | "" | |
bbbc206e | 3166 | "%h0 = %h1 * %h2 %M3%!" |
75d8b2d0 BS |
3167 | [(set_attr "type" "dsp32")]) |
3168 | ||
1d7d5ac4 | 3169 | (define_insn "flag_mulhi_parts" |
a0a31d1e | 3170 | [(set (match_operand:HI 0 "register_operand" "=d") |
1d7d5ac4 BS |
3171 | (unspec:HI [(vec_select:HI |
3172 | (match_operand:V2HI 1 "register_operand" "d") | |
a0a31d1e | 3173 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
1d7d5ac4 BS |
3174 | (vec_select:HI |
3175 | (match_operand:V2HI 2 "register_operand" "d") | |
a0a31d1e BS |
3176 | (parallel [(match_operand 4 "const01_operand" "P0P1")])) |
3177 | (match_operand 5 "const_int_operand" "n")] | |
1d7d5ac4 BS |
3178 | UNSPEC_MUL_WITH_FLAG))] |
3179 | "" | |
3180 | { | |
3181 | const char *templates[] = { | |
a0a31d1e BS |
3182 | "%h0 = %h1 * %h2 %M5%!", |
3183 | "%h0 = %d1 * %h2 %M5%!", | |
3184 | "%h0 = %h1 * %d2 %M5%!", | |
3185 | "%h0 = %d1 * %d2 %M5%!" }; | |
3186 | int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1); | |
1d7d5ac4 BS |
3187 | return templates[alt]; |
3188 | } | |
3189 | [(set_attr "type" "dsp32")]) | |
3190 | ||
75d8b2d0 BS |
3191 | (define_insn "flag_mulhisi" |
3192 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3193 | (unspec:SI [(match_operand:HI 1 "register_operand" "d") | |
3194 | (match_operand:HI 2 "register_operand" "d") | |
3195 | (match_operand 3 "const_int_operand" "n")] | |
3196 | UNSPEC_MUL_WITH_FLAG))] | |
3197 | "" | |
bbbc206e | 3198 | "%0 = %h1 * %h2 %M3%!" |
75d8b2d0 BS |
3199 | [(set_attr "type" "dsp32")]) |
3200 | ||
3201 | (define_insn "flag_mulhisi_parts" | |
3202 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3203 | (unspec:SI [(vec_select:HI | |
3204 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3205 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3206 | (vec_select:HI |
3207 | (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3208 | (parallel [(match_operand 4 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3209 | (match_operand 5 "const_int_operand" "n")] |
3210 | UNSPEC_MUL_WITH_FLAG))] | |
3211 | "" | |
3212 | { | |
3213 | const char *templates[] = { | |
bbbc206e BS |
3214 | "%0 = %h1 * %h2 %M5%!", |
3215 | "%0 = %d1 * %h2 %M5%!", | |
3216 | "%0 = %h1 * %d2 %M5%!", | |
3217 | "%0 = %d1 * %d2 %M5%!" }; | |
75d8b2d0 BS |
3218 | int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1); |
3219 | return templates[alt]; | |
3220 | } | |
3221 | [(set_attr "type" "dsp32")]) | |
3222 | ||
3efd5670 BS |
3223 | ;; Three alternatives here to cover all possible allocations: |
3224 | ;; 0. mac flag is usable only for accumulator 1 - use A1 and odd DREG | |
3225 | ;; 1. mac flag is usable for accumulator 0 - use A0 and even DREG | |
3226 | ;; 2. mac flag is usable in any accumulator - use A1 and odd DREG | |
3227 | ;; Other patterns which don't have a DREG destination can collapse cases | |
3228 | ;; 1 and 2 into one. | |
75d8b2d0 | 3229 | (define_insn "flag_machi" |
3efd5670 BS |
3230 | [(set (match_operand:HI 0 "register_operand" "=W,D,W") |
3231 | (unspec:HI [(match_operand:HI 2 "register_operand" "d,d,d") | |
3232 | (match_operand:HI 3 "register_operand" "d,d,d") | |
3233 | (match_operand 4 "register_operand" "1,1,1") | |
3234 | (match_operand 5 "const01_operand" "P0P1,P0P1,P0P1") | |
3235 | (match_operand 6 "const_int_operand" "PB,PA,PA")] | |
75d8b2d0 | 3236 | UNSPEC_MAC_WITH_FLAG)) |
3efd5670 | 3237 | (set (match_operand:PDI 1 "register_operand" "=B,A,B") |
75d8b2d0 BS |
3238 | (unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3) |
3239 | (match_dup 4) (match_dup 5)] | |
3240 | UNSPEC_MAC_WITH_FLAG))] | |
3241 | "" | |
3efd5670 | 3242 | "%h0 = (%1 %b5 %h2 * %h3) %M6%!" |
75d8b2d0 BS |
3243 | [(set_attr "type" "dsp32")]) |
3244 | ||
3245 | (define_insn "flag_machi_acconly" | |
3efd5670 BS |
3246 | [(set (match_operand:PDI 0 "register_operand" "=B,e") |
3247 | (unspec:PDI [(match_operand:HI 1 "register_operand" "d,d") | |
3248 | (match_operand:HI 2 "register_operand" "d,d") | |
3249 | (match_operand 3 "register_operand" "0,0") | |
3250 | (match_operand 4 "const01_operand" "P0P1,P0P1") | |
3251 | (match_operand 5 "const_int_operand" "PB,PA")] | |
75d8b2d0 BS |
3252 | UNSPEC_MAC_WITH_FLAG))] |
3253 | "" | |
3efd5670 BS |
3254 | "%0 %b4 %h1 * %h2 %M5%!" |
3255 | [(set_attr "type" "dsp32")]) | |
3256 | ||
3257 | (define_insn "flag_machi_parts_acconly" | |
3258 | [(set (match_operand:PDI 0 "register_operand" "=B,e") | |
3259 | (unspec:PDI [(vec_select:HI | |
3260 | (match_operand:V2HI 1 "register_operand" "d,d") | |
3261 | (parallel [(match_operand 3 "const01_operand" "P0P1,P0P1")])) | |
3262 | (vec_select:HI | |
3263 | (match_operand:V2HI 2 "register_operand" "d,d") | |
3264 | (parallel [(match_operand 4 "const01_operand" "P0P1,P0P1")])) | |
3265 | (match_operand:PDI 5 "register_operand" "0,0") | |
3266 | (match_operand 6 "const01_operand" "P0P1,P0P1") | |
3267 | (match_operand 7 "const_int_operand" "PB,PA")] | |
3268 | UNSPEC_MAC_WITH_FLAG))] | |
3269 | "" | |
3270 | { | |
3271 | const char *templates[] = { | |
3272 | "%0 %b6 %h1 * %h2 %M7%!", | |
3273 | "%0 %b6 %d1 * %h2 %M7%!", | |
3274 | "%0 %b6 %h1 * %d2 %M7%!", | |
3275 | "%0 %b6 %d1 * %d2 %M7%!" | |
3276 | }; | |
3277 | int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1); | |
3278 | return templates[alt]; | |
3279 | } | |
75d8b2d0 BS |
3280 | [(set_attr "type" "dsp32")]) |
3281 | ||
3282 | (define_insn "flag_macinithi" | |
3efd5670 BS |
3283 | [(set (match_operand:HI 0 "register_operand" "=W,D,W") |
3284 | (unspec:HI [(match_operand:HI 1 "register_operand" "d,d,d") | |
3285 | (match_operand:HI 2 "register_operand" "d,d,d") | |
3286 | (match_operand 3 "const_int_operand" "PB,PA,PA")] | |
75d8b2d0 | 3287 | UNSPEC_MAC_WITH_FLAG)) |
3efd5670 | 3288 | (set (match_operand:PDI 4 "register_operand" "=B,A,B") |
75d8b2d0 BS |
3289 | (unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3)] |
3290 | UNSPEC_MAC_WITH_FLAG))] | |
3291 | "" | |
3efd5670 | 3292 | "%h0 = (%4 = %h1 * %h2) %M3%!" |
75d8b2d0 BS |
3293 | [(set_attr "type" "dsp32")]) |
3294 | ||
3295 | (define_insn "flag_macinit1hi" | |
3efd5670 BS |
3296 | [(set (match_operand:PDI 0 "register_operand" "=B,e") |
3297 | (unspec:PDI [(match_operand:HI 1 "register_operand" "d,d") | |
3298 | (match_operand:HI 2 "register_operand" "d,d") | |
3299 | (match_operand 3 "const_int_operand" "PB,PA")] | |
75d8b2d0 BS |
3300 | UNSPEC_MAC_WITH_FLAG))] |
3301 | "" | |
bbbc206e | 3302 | "%0 = %h1 * %h2 %M3%!" |
75d8b2d0 BS |
3303 | [(set_attr "type" "dsp32")]) |
3304 | ||
c9b3f817 | 3305 | (define_insn "mulv2hi3" |
0d4a78eb BS |
3306 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
3307 | (mult:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
3308 | (match_operand:V2HI 2 "register_operand" "d")))] | |
3309 | "" | |
bbbc206e | 3310 | "%h0 = %h1 * %h2, %d0 = %d1 * %d2 (IS)%!" |
0d4a78eb BS |
3311 | [(set_attr "type" "dsp32")]) |
3312 | ||
75d8b2d0 BS |
3313 | (define_insn "flag_mulv2hi" |
3314 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3315 | (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d") | |
3316 | (match_operand:V2HI 2 "register_operand" "d") | |
3317 | (match_operand 3 "const_int_operand" "n")] | |
3318 | UNSPEC_MUL_WITH_FLAG))] | |
3319 | "" | |
bbbc206e | 3320 | "%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M3%!" |
75d8b2d0 BS |
3321 | [(set_attr "type" "dsp32")]) |
3322 | ||
3323 | (define_insn "flag_mulv2hi_parts" | |
3324 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3325 | (unspec:V2HI [(vec_concat:V2HI | |
3326 | (vec_select:HI | |
3327 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3328 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3329 | (vec_select:HI |
3330 | (match_dup 1) | |
554006bd | 3331 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3332 | (vec_concat:V2HI |
3333 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3334 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3335 | (vec_select:HI (match_dup 2) |
554006bd | 3336 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3337 | (match_operand 7 "const_int_operand" "n")] |
3338 | UNSPEC_MUL_WITH_FLAG))] | |
3339 | "" | |
3340 | { | |
3341 | const char *templates[] = { | |
bbbc206e BS |
3342 | "%h0 = %h1 * %h2, %d0 = %h1 * %h2 %M7%!", |
3343 | "%h0 = %d1 * %h2, %d0 = %h1 * %h2 %M7%!", | |
3344 | "%h0 = %h1 * %h2, %d0 = %d1 * %h2 %M7%!", | |
3345 | "%h0 = %d1 * %h2, %d0 = %d1 * %h2 %M7%!", | |
3346 | "%h0 = %h1 * %d2, %d0 = %h1 * %h2 %M7%!", | |
3347 | "%h0 = %d1 * %d2, %d0 = %h1 * %h2 %M7%!", | |
3348 | "%h0 = %h1 * %d2, %d0 = %d1 * %h2 %M7%!", | |
3349 | "%h0 = %d1 * %d2, %d0 = %d1 * %h2 %M7%!", | |
3350 | "%h0 = %h1 * %h2, %d0 = %h1 * %d2 %M7%!", | |
3351 | "%h0 = %d1 * %h2, %d0 = %h1 * %d2 %M7%!", | |
3352 | "%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M7%!", | |
3353 | "%h0 = %d1 * %h2, %d0 = %d1 * %d2 %M7%!", | |
3354 | "%h0 = %h1 * %d2, %d0 = %h1 * %d2 %M7%!", | |
3355 | "%h0 = %d1 * %d2, %d0 = %h1 * %d2 %M7%!", | |
3356 | "%h0 = %h1 * %d2, %d0 = %d1 * %d2 %M7%!", | |
3357 | "%h0 = %d1 * %d2, %d0 = %d1 * %d2 %M7%!" }; | |
75d8b2d0 BS |
3358 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3359 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3360 | return templates[alt]; | |
3361 | } | |
3362 | [(set_attr "type" "dsp32")]) | |
3363 | ||
3364 | ;; A slightly complicated pattern. | |
3365 | ;; Operand 0 is the halfword output; operand 11 is the accumulator output | |
3366 | ;; Halfword inputs are operands 1 and 2; operands 3, 4, 5 and 6 specify which | |
3367 | ;; parts of these 2x16 bit registers to use. | |
3368 | ;; Operand 7 is the accumulator input. | |
3369 | ;; Operands 8/9 specify whether low/high parts are mac (0) or msu (1) | |
3370 | ;; Operand 10 is the macflag to be used. | |
3371 | (define_insn "flag_macv2hi_parts" | |
3372 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3373 | (unspec:V2HI [(vec_concat:V2HI | |
3374 | (vec_select:HI | |
3375 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3376 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3377 | (vec_select:HI |
3378 | (match_dup 1) | |
554006bd | 3379 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3380 | (vec_concat:V2HI |
3381 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3382 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3383 | (vec_select:HI (match_dup 2) |
554006bd | 3384 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3385 | (match_operand:V2PDI 7 "register_operand" "e") |
3386 | (match_operand 8 "const01_operand" "P0P1") | |
3387 | (match_operand 9 "const01_operand" "P0P1") | |
3388 | (match_operand 10 "const_int_operand" "n")] | |
3389 | UNSPEC_MAC_WITH_FLAG)) | |
3390 | (set (match_operand:V2PDI 11 "register_operand" "=e") | |
3391 | (unspec:V2PDI [(vec_concat:V2HI | |
3392 | (vec_select:HI (match_dup 1) (parallel [(match_dup 3)])) | |
3393 | (vec_select:HI (match_dup 1) (parallel [(match_dup 4)]))) | |
3394 | (vec_concat:V2HI | |
3395 | (vec_select:HI (match_dup 2) (parallel [(match_dup 5)])) | |
3396 | (vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))) | |
3397 | (match_dup 7) (match_dup 8) (match_dup 9) (match_dup 10)] | |
3398 | UNSPEC_MAC_WITH_FLAG))] | |
3399 | "" | |
3400 | { | |
3401 | const char *templates[] = { | |
bbbc206e BS |
3402 | "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10%!", |
3403 | "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10%!", | |
3404 | "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10%!", | |
3405 | "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10%!", | |
3406 | "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10%!", | |
3407 | "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10%!", | |
3408 | "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10%!", | |
3409 | "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10%!", | |
3410 | "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10%!", | |
3411 | "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10%!", | |
3412 | "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10%!", | |
3413 | "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10%!", | |
3414 | "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10%!", | |
3415 | "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10%!", | |
3416 | "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10%!", | |
3417 | "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10%!" }; | |
75d8b2d0 BS |
3418 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3419 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3420 | return templates[alt]; | |
3421 | } | |
3422 | [(set_attr "type" "dsp32")]) | |
3423 | ||
3424 | (define_insn "flag_macv2hi_parts_acconly" | |
3425 | [(set (match_operand:V2PDI 0 "register_operand" "=e") | |
3426 | (unspec:V2PDI [(vec_concat:V2HI | |
3427 | (vec_select:HI | |
3428 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3429 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3430 | (vec_select:HI |
3431 | (match_dup 1) | |
554006bd | 3432 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3433 | (vec_concat:V2HI |
3434 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3435 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3436 | (vec_select:HI (match_dup 2) |
554006bd | 3437 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3438 | (match_operand:V2PDI 7 "register_operand" "e") |
3439 | (match_operand 8 "const01_operand" "P0P1") | |
3440 | (match_operand 9 "const01_operand" "P0P1") | |
3441 | (match_operand 10 "const_int_operand" "n")] | |
3442 | UNSPEC_MAC_WITH_FLAG))] | |
3443 | "" | |
3444 | { | |
3445 | const char *templates[] = { | |
bbbc206e BS |
3446 | "A0 %b8 %h1 * %h2, A1 %b9 %h1 * %h2 %M10%!", |
3447 | "A0 %b8 %d1 * %h2, A1 %b9 %h1 * %h2 %M10%!", | |
3448 | "A0 %b8 %h1 * %h2, A1 %b9 %d1 * %h2 %M10%!", | |
3449 | "A0 %b8 %d1 * %h2, A1 %b9 %d1 * %h2 %M10%!", | |
3450 | "A0 %b8 %h1 * %d2, A1 %b9 %h1 * %h2 %M10%!", | |
3451 | "A0 %b8 %d1 * %d2, A1 %b9 %h1 * %h2 %M10%!", | |
3452 | "A0 %b8 %h1 * %d2, A1 %b9 %d1 * %h2 %M10%!", | |
3453 | "A0 %b8 %d1 * %d2, A1 %b9 %d1 * %h2 %M10%!", | |
3454 | "A0 %b8 %h1 * %h2, A1 %b9 %h1 * %d2 %M10%!", | |
3455 | "A0 %b8 %d1 * %h2, A1 %b9 %h1 * %d2 %M10%!", | |
3456 | "A0 %b8 %h1 * %h2, A1 %b9 %d1 * %d2 %M10%!", | |
3457 | "A0 %b8 %d1 * %h2, A1 %b9 %d1 * %d2 %M10%!", | |
3458 | "A0 %b8 %h1 * %d2, A1 %b9 %h1 * %d2 %M10%!", | |
3459 | "A0 %b8 %d1 * %d2, A1 %b9 %h1 * %d2 %M10%!", | |
3460 | "A0 %b8 %h1 * %d2, A1 %b9 %d1 * %d2 %M10%!", | |
3461 | "A0 %b8 %d1 * %d2, A1 %b9 %d1 * %d2 %M10%!" }; | |
75d8b2d0 BS |
3462 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3463 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3464 | return templates[alt]; | |
3465 | } | |
3466 | [(set_attr "type" "dsp32")]) | |
3467 | ||
3468 | ;; Same as above, but initializing the accumulators and therefore a couple fewer | |
3469 | ;; necessary operands. | |
3470 | (define_insn "flag_macinitv2hi_parts" | |
0d4a78eb | 3471 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
75d8b2d0 BS |
3472 | (unspec:V2HI [(vec_concat:V2HI |
3473 | (vec_select:HI | |
3474 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3475 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3476 | (vec_select:HI |
3477 | (match_dup 1) | |
554006bd | 3478 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3479 | (vec_concat:V2HI |
3480 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3481 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3482 | (vec_select:HI (match_dup 2) |
554006bd | 3483 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3484 | (match_operand 7 "const_int_operand" "n")] |
3485 | UNSPEC_MAC_WITH_FLAG)) | |
3486 | (set (match_operand:V2PDI 8 "register_operand" "=e") | |
3487 | (unspec:V2PDI [(vec_concat:V2HI | |
3488 | (vec_select:HI (match_dup 1) (parallel [(match_dup 3)])) | |
3489 | (vec_select:HI (match_dup 1) (parallel [(match_dup 4)]))) | |
3490 | (vec_concat:V2HI | |
3491 | (vec_select:HI (match_dup 2) (parallel [(match_dup 5)])) | |
3492 | (vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))) | |
3493 | (match_dup 7)] | |
3494 | UNSPEC_MAC_WITH_FLAG))] | |
3495 | "" | |
3496 | { | |
3497 | const char *templates[] = { | |
bbbc206e BS |
3498 | "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %h2) %M7%!", |
3499 | "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %h2) %M7%!", | |
3500 | "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %h2) %M7%!", | |
3501 | "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %h2) %M7%!", | |
3502 | "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %h2) %M7%!", | |
3503 | "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %h2) %M7%!", | |
3504 | "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %h2) %M7%!", | |
3505 | "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %h2) %M7%!", | |
3506 | "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %d2) %M7%!", | |
3507 | "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %d2) %M7%!", | |
3508 | "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %d2) %M7%!", | |
3509 | "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %d2) %M7%!", | |
3510 | "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %d2) %M7%!", | |
3511 | "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %d2) %M7%!", | |
3512 | "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %d2) %M7%!", | |
3513 | "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %d2) %M7%!" }; | |
75d8b2d0 BS |
3514 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3515 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3516 | return templates[alt]; | |
3517 | } | |
3518 | [(set_attr "type" "dsp32")]) | |
3519 | ||
3520 | (define_insn "flag_macinit1v2hi_parts" | |
3521 | [(set (match_operand:V2PDI 0 "register_operand" "=e") | |
3522 | (unspec:V2PDI [(vec_concat:V2HI | |
3523 | (vec_select:HI | |
3524 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3525 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3526 | (vec_select:HI |
3527 | (match_dup 1) | |
554006bd | 3528 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3529 | (vec_concat:V2HI |
3530 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3531 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3532 | (vec_select:HI (match_dup 2) |
554006bd | 3533 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3534 | (match_operand 7 "const_int_operand" "n")] |
3535 | UNSPEC_MAC_WITH_FLAG))] | |
3536 | "" | |
3537 | { | |
3538 | const char *templates[] = { | |
bbbc206e BS |
3539 | "A0 = %h1 * %h2, A1 = %h1 * %h2 %M7%!", |
3540 | "A0 = %d1 * %h2, A1 = %h1 * %h2 %M7%!", | |
3541 | "A0 = %h1 * %h2, A1 = %d1 * %h2 %M7%!", | |
3542 | "A0 = %d1 * %h2, A1 = %d1 * %h2 %M7%!", | |
3543 | "A0 = %h1 * %d2, A1 = %h1 * %h2 %M7%!", | |
3544 | "A0 = %d1 * %d2, A1 = %h1 * %h2 %M7%!", | |
3545 | "A0 = %h1 * %d2, A1 = %d1 * %h2 %M7%!", | |
3546 | "A0 = %d1 * %d2, A1 = %d1 * %h2 %M7%!", | |
3547 | "A0 = %h1 * %h2, A1 = %h1 * %d2 %M7%!", | |
3548 | "A0 = %d1 * %h2, A1 = %h1 * %d2 %M7%!", | |
3549 | "A0 = %h1 * %h2, A1 = %d1 * %d2 %M7%!", | |
3550 | "A0 = %d1 * %h2, A1 = %d1 * %d2 %M7%!", | |
3551 | "A0 = %h1 * %d2, A1 = %h1 * %d2 %M7%!", | |
3552 | "A0 = %d1 * %d2, A1 = %h1 * %d2 %M7%!", | |
3553 | "A0 = %h1 * %d2, A1 = %d1 * %d2 %M7%!", | |
3554 | "A0 = %d1 * %d2, A1 = %d1 * %d2 %M7%!" }; | |
75d8b2d0 BS |
3555 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3556 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3557 | return templates[alt]; | |
3558 | } | |
3559 | [(set_attr "type" "dsp32")]) | |
3560 | ||
3efd5670 BS |
3561 | ;; A mixture of multiply and multiply-accumulate for when we only want to |
3562 | ;; initialize one part. | |
3563 | (define_insn "flag_mul_macv2hi_parts_acconly" | |
3564 | [(set (match_operand:PDI 0 "register_operand" "=B,e,e") | |
3565 | (unspec:PDI [(vec_select:HI | |
3566 | (match_operand:V2HI 2 "register_operand" "d,d,d") | |
3567 | (parallel [(match_operand 4 "const01_operand" "P0P1,P0P1,P0P1")])) | |
3568 | (vec_select:HI | |
3569 | (match_operand:V2HI 3 "register_operand" "d,d,d") | |
3570 | (parallel [(match_operand 6 "const01_operand" "P0P1,P0P1,P0P1")])) | |
3571 | (match_operand 10 "const_int_operand" "PB,PA,PA")] | |
3572 | UNSPEC_MUL_WITH_FLAG)) | |
3573 | (set (match_operand:PDI 1 "register_operand" "=B,e,e") | |
3574 | (unspec:PDI [(vec_select:HI | |
3575 | (match_dup 2) | |
3576 | (parallel [(match_operand 5 "const01_operand" "P0P1,P0P1,P0P1")])) | |
3577 | (vec_select:HI | |
3578 | (match_dup 3) | |
3579 | (parallel [(match_operand 7 "const01_operand" "P0P1,P0P1,P0P1")])) | |
3580 | (match_operand:PDI 8 "register_operand" "1,1,1") | |
3581 | (match_operand 9 "const01_operand" "P0P1,P0P1,P0P1") | |
3582 | (match_operand 11 "const_int_operand" "PA,PB,PA")] | |
3583 | UNSPEC_MAC_WITH_FLAG))] | |
3584 | "MACFLAGS_MATCH_P (INTVAL (operands[10]), INTVAL (operands[11]))" | |
3585 | { | |
3586 | rtx xops[6]; | |
3587 | const char *templates[] = { | |
3588 | "%0 = %h2 * %h3, %1 %b4 %h2 * %h3 %M5%!", | |
3589 | "%0 = %d2 * %h3, %1 %b4 %h2 * %h3 %M5%!", | |
3590 | "%0 = %h2 * %h3, %1 %b4 %d2 * %h3 %M5%!", | |
3591 | "%0 = %d2 * %h3, %1 %b4 %d2 * %h3 %M5%!", | |
3592 | "%0 = %h2 * %d3, %1 %b4 %h2 * %h3 %M5%!", | |
3593 | "%0 = %d2 * %d3, %1 %b4 %h2 * %h3 %M5%!", | |
3594 | "%0 = %h2 * %d3, %1 %b4 %d2 * %h3 %M5%!", | |
3595 | "%0 = %d2 * %d3, %1 %b4 %d2 * %h3 %M5%!", | |
3596 | "%0 = %h2 * %h3, %1 %b4 %h2 * %d3 %M5%!", | |
3597 | "%0 = %d2 * %h3, %1 %b4 %h2 * %d3 %M5%!", | |
3598 | "%0 = %h2 * %h3, %1 %b4 %d2 * %d3 %M5%!", | |
3599 | "%0 = %d2 * %h3, %1 %b4 %d2 * %d3 %M5%!", | |
3600 | "%0 = %h2 * %d3, %1 %b4 %h2 * %d3 %M5%!", | |
3601 | "%0 = %d2 * %d3, %1 %b4 %h2 * %d3 %M5%!", | |
3602 | "%0 = %h2 * %d3, %1 %b4 %d2 * %d3 %M5%!", | |
3603 | "%0 = %d2 * %d3, %1 %b4 %d2 * %d3 %M5%!" }; | |
3604 | int alt = (INTVAL (operands[4]) + (INTVAL (operands[5]) << 1) | |
3605 | + (INTVAL (operands[6]) << 2) + (INTVAL (operands[7]) << 3)); | |
3606 | xops[0] = operands[0]; | |
3607 | xops[1] = operands[1]; | |
3608 | xops[2] = operands[2]; | |
3609 | xops[3] = operands[3]; | |
3610 | xops[4] = operands[9]; | |
3611 | xops[5] = which_alternative == 0 ? operands[10] : operands[11]; | |
3612 | output_asm_insn (templates[alt], xops); | |
3613 | return ""; | |
3614 | } | |
3615 | [(set_attr "type" "dsp32")]) | |
3616 | ||
3617 | ||
3abcb3a7 | 3618 | (define_code_iterator s_or_u [sign_extend zero_extend]) |
2889abed BS |
3619 | (define_code_attr su_optab [(sign_extend "mul") |
3620 | (zero_extend "umul")]) | |
3621 | (define_code_attr su_modifier [(sign_extend "IS") | |
3622 | (zero_extend "FU")]) | |
3623 | ||
3624 | (define_insn "<su_optab>hisi_ll" | |
75d8b2d0 | 3625 | [(set (match_operand:SI 0 "register_operand" "=d") |
2889abed | 3626 | (mult:SI (s_or_u:SI |
75d8b2d0 BS |
3627 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d") |
3628 | (parallel [(const_int 0)]))) | |
2889abed | 3629 | (s_or_u:SI |
75d8b2d0 BS |
3630 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") |
3631 | (parallel [(const_int 0)])))))] | |
3632 | "" | |
2889abed | 3633 | "%0 = %h1 * %h2 (<su_modifier>)%!" |
75d8b2d0 BS |
3634 | [(set_attr "type" "dsp32")]) |
3635 | ||
2889abed | 3636 | (define_insn "<su_optab>hisi_lh" |
75d8b2d0 | 3637 | [(set (match_operand:SI 0 "register_operand" "=d") |
2889abed BS |
3638 | (mult:SI (s_or_u:SI |
3639 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
75d8b2d0 | 3640 | (parallel [(const_int 0)]))) |
2889abed | 3641 | (s_or_u:SI |
75d8b2d0 BS |
3642 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") |
3643 | (parallel [(const_int 1)])))))] | |
3644 | "" | |
2889abed | 3645 | "%0 = %h1 * %d2 (<su_modifier>)%!" |
75d8b2d0 BS |
3646 | [(set_attr "type" "dsp32")]) |
3647 | ||
2889abed | 3648 | (define_insn "<su_optab>hisi_hl" |
75d8b2d0 | 3649 | [(set (match_operand:SI 0 "register_operand" "=d") |
2889abed BS |
3650 | (mult:SI (s_or_u:SI |
3651 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3652 | (parallel [(const_int 1)]))) | |
3653 | (s_or_u:SI | |
3654 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3655 | (parallel [(const_int 0)])))))] | |
3656 | "" | |
3657 | "%0 = %d1 * %h2 (<su_modifier>)%!" | |
3658 | [(set_attr "type" "dsp32")]) | |
3659 | ||
3660 | (define_insn "<su_optab>hisi_hh" | |
3661 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3662 | (mult:SI (s_or_u:SI | |
75d8b2d0 BS |
3663 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d") |
3664 | (parallel [(const_int 1)]))) | |
2889abed BS |
3665 | (s_or_u:SI |
3666 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3667 | (parallel [(const_int 1)])))))] | |
3668 | "" | |
3669 | "%0 = %d1 * %d2 (<su_modifier>)%!" | |
3670 | [(set_attr "type" "dsp32")]) | |
3671 | ||
3672 | ;; Additional variants for signed * unsigned multiply. | |
3673 | ||
3674 | (define_insn "usmulhisi_ull" | |
3675 | [(set (match_operand:SI 0 "register_operand" "=W") | |
3676 | (mult:SI (zero_extend:SI | |
3677 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d") | |
3678 | (parallel [(const_int 0)]))) | |
75d8b2d0 BS |
3679 | (sign_extend:SI |
3680 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3681 | (parallel [(const_int 0)])))))] | |
3682 | "" | |
2889abed | 3683 | "%0 = %h2 * %h1 (IS,M)%!" |
75d8b2d0 BS |
3684 | [(set_attr "type" "dsp32")]) |
3685 | ||
2889abed BS |
3686 | (define_insn "usmulhisi_ulh" |
3687 | [(set (match_operand:SI 0 "register_operand" "=W") | |
3688 | (mult:SI (zero_extend:SI | |
3689 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3690 | (parallel [(const_int 0)]))) | |
3691 | (sign_extend:SI | |
3692 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3693 | (parallel [(const_int 1)])))))] | |
3694 | "" | |
3695 | "%0 = %d2 * %h1 (IS,M)%!" | |
3696 | [(set_attr "type" "dsp32")]) | |
3697 | ||
3698 | (define_insn "usmulhisi_uhl" | |
3699 | [(set (match_operand:SI 0 "register_operand" "=W") | |
3700 | (mult:SI (zero_extend:SI | |
3701 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3702 | (parallel [(const_int 1)]))) | |
3703 | (sign_extend:SI | |
3704 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3705 | (parallel [(const_int 0)])))))] | |
3706 | "" | |
3707 | "%0 = %h2 * %d1 (IS,M)%!" | |
3708 | [(set_attr "type" "dsp32")]) | |
3709 | ||
3710 | (define_insn "usmulhisi_uhh" | |
3711 | [(set (match_operand:SI 0 "register_operand" "=W") | |
3712 | (mult:SI (zero_extend:SI | |
75d8b2d0 BS |
3713 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d") |
3714 | (parallel [(const_int 1)]))) | |
3715 | (sign_extend:SI | |
3716 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3717 | (parallel [(const_int 1)])))))] | |
3718 | "" | |
2889abed BS |
3719 | "%0 = %d2 * %d1 (IS,M)%!" |
3720 | [(set_attr "type" "dsp32")]) | |
3721 | ||
3722 | ;; Parallel versions of these operations. First, normal signed or unsigned | |
3723 | ;; multiplies. | |
3724 | ||
3725 | (define_insn "<su_optab>hisi_ll_lh" | |
3726 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3727 | (mult:SI (s_or_u:SI | |
3728 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3729 | (parallel [(const_int 0)]))) | |
3730 | (s_or_u:SI | |
3731 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3732 | (parallel [(const_int 0)]))))) | |
3733 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3734 | (mult:SI (s_or_u:SI | |
3735 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3736 | (s_or_u:SI | |
3737 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3738 | "" | |
3739 | "%0 = %h1 * %h2, %3 = %h1 * %d2 (<su_modifier>)%!" | |
3740 | [(set_attr "type" "dsp32")]) | |
3741 | ||
3742 | (define_insn "<su_optab>hisi_ll_hl" | |
3743 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3744 | (mult:SI (s_or_u:SI | |
3745 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3746 | (parallel [(const_int 0)]))) | |
3747 | (s_or_u:SI | |
3748 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3749 | (parallel [(const_int 0)]))))) | |
3750 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3751 | (mult:SI (s_or_u:SI | |
3752 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3753 | (s_or_u:SI | |
3754 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3755 | "" | |
3756 | "%0 = %h1 * %h2, %3 = %d1 * %h2 (<su_modifier>)%!" | |
3757 | [(set_attr "type" "dsp32")]) | |
3758 | ||
3759 | (define_insn "<su_optab>hisi_ll_hh" | |
3760 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3761 | (mult:SI (s_or_u:SI | |
3762 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3763 | (parallel [(const_int 0)]))) | |
3764 | (s_or_u:SI | |
3765 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3766 | (parallel [(const_int 0)]))))) | |
3767 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3768 | (mult:SI (s_or_u:SI | |
3769 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3770 | (s_or_u:SI | |
3771 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3772 | "" | |
3773 | "%0 = %h1 * %h2, %3 = %d1 * %d2 (<su_modifier>)%!" | |
3774 | [(set_attr "type" "dsp32")]) | |
3775 | ||
3776 | (define_insn "<su_optab>hisi_lh_hl" | |
3777 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3778 | (mult:SI (s_or_u:SI | |
3779 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3780 | (parallel [(const_int 0)]))) | |
3781 | (s_or_u:SI | |
3782 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3783 | (parallel [(const_int 1)]))))) | |
3784 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3785 | (mult:SI (s_or_u:SI | |
3786 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3787 | (s_or_u:SI | |
3788 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3789 | "" | |
3790 | "%0 = %h1 * %d2, %3 = %d1 * %h2 (<su_modifier>)%!" | |
3791 | [(set_attr "type" "dsp32")]) | |
3792 | ||
3793 | (define_insn "<su_optab>hisi_lh_hh" | |
3794 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3795 | (mult:SI (s_or_u:SI | |
3796 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3797 | (parallel [(const_int 0)]))) | |
3798 | (s_or_u:SI | |
3799 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3800 | (parallel [(const_int 1)]))))) | |
3801 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3802 | (mult:SI (s_or_u:SI | |
3803 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3804 | (s_or_u:SI | |
3805 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3806 | "" | |
3807 | "%0 = %h1 * %d2, %3 = %d1 * %d2 (<su_modifier>)%!" | |
3808 | [(set_attr "type" "dsp32")]) | |
3809 | ||
3810 | (define_insn "<su_optab>hisi_hl_hh" | |
3811 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3812 | (mult:SI (s_or_u:SI | |
3813 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3814 | (parallel [(const_int 1)]))) | |
3815 | (s_or_u:SI | |
3816 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3817 | (parallel [(const_int 0)]))))) | |
3818 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3819 | (mult:SI (s_or_u:SI | |
3820 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3821 | (s_or_u:SI | |
3822 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3823 | "" | |
3824 | "%0 = %d1 * %h2, %3 = %d1 * %d2 (<su_modifier>)%!" | |
3825 | [(set_attr "type" "dsp32")]) | |
3826 | ||
3827 | ;; Special signed * unsigned variants. | |
3828 | ||
3829 | (define_insn "usmulhisi_ll_lul" | |
3830 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3831 | (mult:SI (sign_extend:SI | |
3832 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3833 | (parallel [(const_int 0)]))) | |
3834 | (sign_extend:SI | |
3835 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3836 | (parallel [(const_int 0)]))))) | |
3837 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3838 | (mult:SI (sign_extend:SI | |
3839 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3840 | (zero_extend:SI | |
3841 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3842 | "" | |
3843 | "%0 = %h1 * %h2, %3 = %h1 * %h2 (IS,M)%!" | |
3844 | [(set_attr "type" "dsp32")]) | |
3845 | ||
3846 | (define_insn "usmulhisi_ll_luh" | |
3847 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3848 | (mult:SI (sign_extend:SI | |
3849 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3850 | (parallel [(const_int 0)]))) | |
3851 | (sign_extend:SI | |
3852 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3853 | (parallel [(const_int 0)]))))) | |
3854 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3855 | (mult:SI (sign_extend:SI | |
3856 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3857 | (zero_extend:SI | |
3858 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3859 | "" | |
3860 | "%0 = %h1 * %h2, %3 = %h1 * %d2 (IS,M)%!" | |
3861 | [(set_attr "type" "dsp32")]) | |
3862 | ||
3863 | (define_insn "usmulhisi_ll_hul" | |
3864 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3865 | (mult:SI (sign_extend:SI | |
3866 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3867 | (parallel [(const_int 0)]))) | |
3868 | (sign_extend:SI | |
3869 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3870 | (parallel [(const_int 0)]))))) | |
3871 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3872 | (mult:SI (sign_extend:SI | |
3873 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3874 | (zero_extend:SI | |
3875 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3876 | "" | |
3877 | "%0 = %h1 * %h2, %3 = %d1 * %h2 (IS,M)%!" | |
3878 | [(set_attr "type" "dsp32")]) | |
3879 | ||
3880 | (define_insn "usmulhisi_ll_huh" | |
3881 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3882 | (mult:SI (sign_extend:SI | |
3883 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3884 | (parallel [(const_int 0)]))) | |
3885 | (sign_extend:SI | |
3886 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3887 | (parallel [(const_int 0)]))))) | |
3888 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3889 | (mult:SI (sign_extend:SI | |
3890 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3891 | (zero_extend:SI | |
3892 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3893 | "" | |
3894 | "%0 = %h1 * %h2, %3 = %d1 * %d2 (IS,M)%!" | |
3895 | [(set_attr "type" "dsp32")]) | |
3896 | ||
3897 | (define_insn "usmulhisi_lh_lul" | |
3898 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3899 | (mult:SI (sign_extend:SI | |
3900 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3901 | (parallel [(const_int 0)]))) | |
3902 | (sign_extend:SI | |
3903 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3904 | (parallel [(const_int 1)]))))) | |
3905 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3906 | (mult:SI (sign_extend:SI | |
3907 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3908 | (zero_extend:SI | |
3909 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3910 | "" | |
3911 | "%0 = %h1 * %d2, %3 = %h1 * %h2 (IS,M)%!" | |
3912 | [(set_attr "type" "dsp32")]) | |
3913 | ||
3914 | (define_insn "usmulhisi_lh_luh" | |
3915 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3916 | (mult:SI (sign_extend:SI | |
3917 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3918 | (parallel [(const_int 0)]))) | |
3919 | (sign_extend:SI | |
3920 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3921 | (parallel [(const_int 1)]))))) | |
3922 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3923 | (mult:SI (sign_extend:SI | |
3924 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3925 | (zero_extend:SI | |
3926 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3927 | "" | |
3928 | "%0 = %h1 * %d2, %3 = %h1 * %d2 (IS,M)%!" | |
3929 | [(set_attr "type" "dsp32")]) | |
3930 | ||
3931 | (define_insn "usmulhisi_lh_hul" | |
3932 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3933 | (mult:SI (sign_extend:SI | |
3934 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3935 | (parallel [(const_int 0)]))) | |
3936 | (sign_extend:SI | |
3937 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3938 | (parallel [(const_int 1)]))))) | |
3939 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3940 | (mult:SI (sign_extend:SI | |
3941 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3942 | (zero_extend:SI | |
3943 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3944 | "" | |
3945 | "%0 = %h1 * %d2, %3 = %d1 * %h2 (IS,M)%!" | |
3946 | [(set_attr "type" "dsp32")]) | |
3947 | ||
3948 | (define_insn "usmulhisi_lh_huh" | |
3949 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3950 | (mult:SI (sign_extend:SI | |
3951 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3952 | (parallel [(const_int 0)]))) | |
3953 | (sign_extend:SI | |
3954 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3955 | (parallel [(const_int 1)]))))) | |
3956 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3957 | (mult:SI (sign_extend:SI | |
3958 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3959 | (zero_extend:SI | |
3960 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3961 | "" | |
3962 | "%0 = %h1 * %d2, %3 = %d1 * %d2 (IS,M)%!" | |
3963 | [(set_attr "type" "dsp32")]) | |
3964 | ||
3965 | (define_insn "usmulhisi_hl_lul" | |
3966 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3967 | (mult:SI (sign_extend:SI | |
3968 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3969 | (parallel [(const_int 1)]))) | |
3970 | (sign_extend:SI | |
3971 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3972 | (parallel [(const_int 0)]))))) | |
3973 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3974 | (mult:SI (sign_extend:SI | |
3975 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3976 | (zero_extend:SI | |
3977 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3978 | "" | |
3979 | "%0 = %d1 * %h2, %3 = %h1 * %h2 (IS,M)%!" | |
3980 | [(set_attr "type" "dsp32")]) | |
3981 | ||
3982 | (define_insn "usmulhisi_hl_luh" | |
3983 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3984 | (mult:SI (sign_extend:SI | |
3985 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3986 | (parallel [(const_int 1)]))) | |
3987 | (sign_extend:SI | |
3988 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3989 | (parallel [(const_int 0)]))))) | |
3990 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3991 | (mult:SI (sign_extend:SI | |
3992 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3993 | (zero_extend:SI | |
3994 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3995 | "" | |
3996 | "%0 = %d1 * %h2, %3 = %h1 * %d2 (IS,M)%!" | |
3997 | [(set_attr "type" "dsp32")]) | |
3998 | ||
3999 | (define_insn "usmulhisi_hl_hul" | |
4000 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
4001 | (mult:SI (sign_extend:SI | |
4002 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4003 | (parallel [(const_int 1)]))) | |
4004 | (sign_extend:SI | |
4005 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4006 | (parallel [(const_int 0)]))))) | |
4007 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4008 | (mult:SI (sign_extend:SI | |
4009 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
4010 | (zero_extend:SI | |
4011 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
4012 | "" | |
4013 | "%0 = %d1 * %h2, %3 = %d1 * %h2 (IS,M)%!" | |
4014 | [(set_attr "type" "dsp32")]) | |
4015 | ||
4016 | (define_insn "usmulhisi_hl_huh" | |
4017 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
4018 | (mult:SI (sign_extend:SI | |
4019 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4020 | (parallel [(const_int 1)]))) | |
4021 | (sign_extend:SI | |
4022 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4023 | (parallel [(const_int 0)]))))) | |
4024 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4025 | (mult:SI (sign_extend:SI | |
4026 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
4027 | (zero_extend:SI | |
4028 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
4029 | "" | |
4030 | "%0 = %d1 * %h2, %3 = %d1 * %d2 (IS,M)%!" | |
4031 | [(set_attr "type" "dsp32")]) | |
4032 | ||
4033 | (define_insn "usmulhisi_hh_lul" | |
4034 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
4035 | (mult:SI (sign_extend:SI | |
4036 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4037 | (parallel [(const_int 1)]))) | |
4038 | (sign_extend:SI | |
4039 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4040 | (parallel [(const_int 1)]))))) | |
4041 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4042 | (mult:SI (sign_extend:SI | |
4043 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
4044 | (zero_extend:SI | |
4045 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
4046 | "" | |
4047 | "%0 = %d1 * %d2, %3 = %h1 * %h2 (IS,M)%!" | |
75d8b2d0 BS |
4048 | [(set_attr "type" "dsp32")]) |
4049 | ||
2889abed BS |
4050 | (define_insn "usmulhisi_hh_luh" |
4051 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
4052 | (mult:SI (sign_extend:SI | |
4053 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4054 | (parallel [(const_int 1)]))) | |
4055 | (sign_extend:SI | |
4056 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4057 | (parallel [(const_int 1)]))))) | |
4058 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4059 | (mult:SI (sign_extend:SI | |
4060 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
4061 | (zero_extend:SI | |
4062 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
4063 | "" | |
4064 | "%0 = %d1 * %d2, %3 = %h1 * %d2 (IS,M)%!" | |
4065 | [(set_attr "type" "dsp32")]) | |
4066 | ||
4067 | (define_insn "usmulhisi_hh_hul" | |
4068 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
4069 | (mult:SI (sign_extend:SI | |
4070 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4071 | (parallel [(const_int 1)]))) | |
4072 | (sign_extend:SI | |
4073 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4074 | (parallel [(const_int 1)]))))) | |
4075 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4076 | (mult:SI (sign_extend:SI | |
4077 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
4078 | (zero_extend:SI | |
4079 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
4080 | "" | |
4081 | "%0 = %d1 * %d2, %3 = %d1 * %h2 (IS,M)%!" | |
4082 | [(set_attr "type" "dsp32")]) | |
4083 | ||
4084 | (define_insn "usmulhisi_hh_huh" | |
4085 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
4086 | (mult:SI (sign_extend:SI | |
4087 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4088 | (parallel [(const_int 1)]))) | |
4089 | (sign_extend:SI | |
4090 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4091 | (parallel [(const_int 1)]))))) | |
4092 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4093 | (mult:SI (sign_extend:SI | |
4094 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
4095 | (zero_extend:SI | |
4096 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
4097 | "" | |
4098 | "%0 = %d1 * %d2, %3 = %d1 * %d2 (IS,M)%!" | |
4099 | [(set_attr "type" "dsp32")]) | |
4100 | ||
4101 | ;; Vector neg/abs. | |
4102 | ||
75d8b2d0 BS |
4103 | (define_insn "ssnegv2hi2" |
4104 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
4105 | (ss_neg:V2HI (match_operand:V2HI 1 "register_operand" "d")))] | |
0d4a78eb | 4106 | "" |
bbbc206e | 4107 | "%0 = - %1 (V)%!" |
0d4a78eb BS |
4108 | [(set_attr "type" "dsp32")]) |
4109 | ||
26c5953d | 4110 | (define_insn "ssabsv2hi2" |
0d4a78eb | 4111 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
26c5953d | 4112 | (ss_abs:V2HI (match_operand:V2HI 1 "register_operand" "d")))] |
0d4a78eb | 4113 | "" |
bbbc206e | 4114 | "%0 = ABS %1 (V)%!" |
0d4a78eb BS |
4115 | [(set_attr "type" "dsp32")]) |
4116 | ||
75d8b2d0 BS |
4117 | ;; Shifts. |
4118 | ||
4119 | (define_insn "ssashiftv2hi3" | |
4120 | [(set (match_operand:V2HI 0 "register_operand" "=d,d,d") | |
4121 | (if_then_else:V2HI | |
26c5953d | 4122 | (lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) |
75d8b2d0 BS |
4123 | (ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d") |
4124 | (match_dup 2)) | |
4125 | (ss_ashift:V2HI (match_dup 1) (match_dup 2))))] | |
4126 | "" | |
4127 | "@ | |
329437dd | 4128 | %0 = ASHIFT %1 BY %h2 (V, S)%! |
58f76679 BS |
4129 | %0 = %1 << %2 (V,S)%! |
4130 | %0 = %1 >>> %N2 (V,S)%!" | |
b3187e24 | 4131 | [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")]) |
75d8b2d0 BS |
4132 | |
4133 | (define_insn "ssashifthi3" | |
4134 | [(set (match_operand:HI 0 "register_operand" "=d,d,d") | |
4135 | (if_then_else:HI | |
26c5953d | 4136 | (lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) |
75d8b2d0 BS |
4137 | (ashiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d") |
4138 | (match_dup 2)) | |
4139 | (ss_ashift:HI (match_dup 1) (match_dup 2))))] | |
4140 | "" | |
4141 | "@ | |
329437dd | 4142 | %0 = ASHIFT %1 BY %h2 (V, S)%! |
58f76679 BS |
4143 | %0 = %1 << %2 (V,S)%! |
4144 | %0 = %1 >>> %N2 (V,S)%!" | |
b3187e24 | 4145 | [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")]) |
75d8b2d0 | 4146 | |
26c5953d BS |
4147 | (define_insn "ssashiftsi3" |
4148 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
4149 | (if_then_else:SI | |
4150 | (lt (match_operand:HI 2 "reg_or_const_int_operand" "d,Ku5,Ks5") (const_int 0)) | |
4151 | (ashiftrt:SI (match_operand:HI 1 "register_operand" "d,d,d") | |
4152 | (match_dup 2)) | |
4153 | (ss_ashift:SI (match_dup 1) (match_dup 2))))] | |
4154 | "" | |
4155 | "@ | |
4156 | %0 = ASHIFT %1 BY %h2 (S)%! | |
4157 | %0 = %1 << %2 (S)%! | |
4158 | %0 = %1 >>> %N2 (S)%!" | |
b3187e24 | 4159 | [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")]) |
26c5953d | 4160 | |
75d8b2d0 BS |
4161 | (define_insn "lshiftv2hi3" |
4162 | [(set (match_operand:V2HI 0 "register_operand" "=d,d,d") | |
4163 | (if_then_else:V2HI | |
26c5953d | 4164 | (lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) |
75d8b2d0 BS |
4165 | (lshiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d") |
4166 | (match_dup 2)) | |
4167 | (ashift:V2HI (match_dup 1) (match_dup 2))))] | |
4168 | "" | |
4169 | "@ | |
329437dd | 4170 | %0 = LSHIFT %1 BY %h2 (V)%! |
58f76679 BS |
4171 | %0 = %1 << %2 (V)%! |
4172 | %0 = %1 >> %N2 (V)%!" | |
b3187e24 | 4173 | [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")]) |
75d8b2d0 BS |
4174 | |
4175 | (define_insn "lshifthi3" | |
4176 | [(set (match_operand:HI 0 "register_operand" "=d,d,d") | |
4177 | (if_then_else:HI | |
26c5953d | 4178 | (lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) |
75d8b2d0 BS |
4179 | (lshiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d") |
4180 | (match_dup 2)) | |
4181 | (ashift:HI (match_dup 1) (match_dup 2))))] | |
4182 | "" | |
4183 | "@ | |
329437dd | 4184 | %0 = LSHIFT %1 BY %h2 (V)%! |
58f76679 BS |
4185 | %0 = %1 << %2 (V)%! |
4186 | %0 = %1 >> %N2 (V)%!" | |
b3187e24 | 4187 | [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")]) |
75d8b2d0 | 4188 | |
8fa477f7 BS |
4189 | ;; Load without alignment exception (masking off low bits) |
4190 | ||
4191 | (define_insn "loadbytes" | |
4192 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4193 | (mem:SI (and:SI (match_operand:SI 1 "register_operand" "b") | |
4194 | (const_int -4))))] | |
4195 | "" | |
4196 | "DISALGNEXCPT || %0 = [%1];" | |
4197 | [(set_attr "type" "mcld") | |
4198 | (set_attr "length" "8")]) | |
9840d30a BS |
4199 | |
4200 | (include "sync.md") |