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0d4a78eb | 1 | ;;- Machine description for Blackfin for GNU compiler |
66647d44 | 2 | ;; Copyright 2005, 2006, 2007, 2008 Free Software Foundation, Inc. |
0d4a78eb BS |
3 | ;; Contributed by Analog Devices. |
4 | ||
5 | ;; This file is part of GCC. | |
6 | ||
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | ;; by the Free Software Foundation; either version 3, or (at your |
0d4a78eb BS |
10 | ;; option) any later version. |
11 | ||
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | ;; along with GCC; see the file COPYING3. If not see |
19 | ;; <http://www.gnu.org/licenses/>. | |
0d4a78eb BS |
20 | |
21 | ; operand punctuation marks: | |
22 | ; | |
23 | ; X -- integer value printed as log2 | |
24 | ; Y -- integer value printed as log2(~value) - for bitclear | |
25 | ; h -- print half word register, low part | |
26 | ; d -- print half word register, high part | |
27 | ; D -- print operand as dregs pairs | |
28 | ; w -- print operand as accumulator register word (a0w, a1w) | |
29 | ; H -- high part of double mode operand | |
30 | ; T -- byte register representation Oct. 02 2001 | |
31 | ||
32 | ; constant operand classes | |
33 | ; | |
34 | ; J 2**N 5bit imm scaled | |
35 | ; Ks7 -64 .. 63 signed 7bit imm | |
36 | ; Ku5 0..31 unsigned 5bit imm | |
37 | ; Ks4 -8 .. 7 signed 4bit imm | |
38 | ; Ks3 -4 .. 3 signed 3bit imm | |
39 | ; Ku3 0 .. 7 unsigned 3bit imm | |
40 | ; Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n | |
41 | ; | |
42 | ; register operands | |
43 | ; d (r0..r7) | |
44 | ; a (p0..p5,fp,sp) | |
45 | ; e (a0, a1) | |
46 | ; b (i0..i3) | |
47 | ; f (m0..m3) | |
a9c46998 JZ |
48 | ; v (b0..b3) |
49 | ; c (i0..i3,m0..m3) CIRCREGS | |
50 | ; C (CC) CCREGS | |
b03149e1 JZ |
51 | ; t (lt0,lt1) |
52 | ; k (lc0,lc1) | |
a9c46998 | 53 | ; u (lb0,lb1) |
0d4a78eb BS |
54 | ; |
55 | ||
56 | ;; Define constants for hard registers. | |
57 | ||
58 | (define_constants | |
59 | [(REG_R0 0) | |
60 | (REG_R1 1) | |
61 | (REG_R2 2) | |
62 | (REG_R3 3) | |
63 | (REG_R4 4) | |
64 | (REG_R5 5) | |
65 | (REG_R6 6) | |
66 | (REG_R7 7) | |
67 | ||
68 | (REG_P0 8) | |
69 | (REG_P1 9) | |
70 | (REG_P2 10) | |
71 | (REG_P3 11) | |
72 | (REG_P4 12) | |
73 | (REG_P5 13) | |
74 | (REG_P6 14) | |
75 | (REG_P7 15) | |
76 | ||
77 | (REG_SP 14) | |
78 | (REG_FP 15) | |
79 | ||
80 | (REG_I0 16) | |
df259245 JZ |
81 | (REG_I1 17) |
82 | (REG_I2 18) | |
83 | (REG_I3 19) | |
84 | ||
85 | (REG_B0 20) | |
86 | (REG_B1 21) | |
87 | (REG_B2 22) | |
88 | (REG_B3 23) | |
89 | ||
90 | (REG_L0 24) | |
91 | (REG_L1 25) | |
92 | (REG_L2 26) | |
0d4a78eb BS |
93 | (REG_L3 27) |
94 | ||
95 | (REG_M0 28) | |
96 | (REG_M1 29) | |
97 | (REG_M2 30) | |
98 | (REG_M3 31) | |
99 | ||
100 | (REG_A0 32) | |
101 | (REG_A1 33) | |
102 | ||
103 | (REG_CC 34) | |
104 | (REG_RETS 35) | |
105 | (REG_RETI 36) | |
106 | (REG_RETX 37) | |
107 | (REG_RETN 38) | |
108 | (REG_RETE 39) | |
109 | ||
110 | (REG_ASTAT 40) | |
111 | (REG_SEQSTAT 41) | |
112 | (REG_USP 42) | |
113 | ||
b03149e1 JZ |
114 | (REG_ARGP 43) |
115 | ||
116 | (REG_LT0 44) | |
117 | (REG_LT1 45) | |
118 | (REG_LC0 46) | |
119 | (REG_LC1 47) | |
120 | (REG_LB0 48) | |
121 | (REG_LB1 49)]) | |
0d4a78eb BS |
122 | |
123 | ;; Constants used in UNSPECs and UNSPEC_VOLATILEs. | |
124 | ||
125 | (define_constants | |
126 | [(UNSPEC_CBRANCH_TAKEN 0) | |
127 | (UNSPEC_CBRANCH_NOPS 1) | |
128 | (UNSPEC_RETURN 2) | |
129 | (UNSPEC_MOVE_PIC 3) | |
130 | (UNSPEC_LIBRARY_OFFSET 4) | |
75d8b2d0 BS |
131 | (UNSPEC_PUSH_MULTIPLE 5) |
132 | ;; Multiply or MAC with extra CONST_INT operand specifying the macflag | |
133 | (UNSPEC_MUL_WITH_FLAG 6) | |
6614f9f5 BS |
134 | (UNSPEC_MAC_WITH_FLAG 7) |
135 | (UNSPEC_MOVE_FDPIC 8) | |
b03149e1 | 136 | (UNSPEC_FUNCDESC_GOT17M4 9) |
bbbc206e | 137 | (UNSPEC_LSETUP_END 10) |
942fd98f | 138 | ;; Distinguish a 32-bit version of an insn from a 16-bit version. |
b18e284e | 139 | (UNSPEC_32BIT 11) |
1d7d5ac4 BS |
140 | (UNSPEC_NOP 12) |
141 | (UNSPEC_ONES 12)]) | |
0d4a78eb BS |
142 | |
143 | (define_constants | |
5fcead21 BS |
144 | [(UNSPEC_VOLATILE_EH_RETURN 0) |
145 | (UNSPEC_VOLATILE_CSYNC 1) | |
6614f9f5 | 146 | (UNSPEC_VOLATILE_SSYNC 2) |
1ca950ca | 147 | (UNSPEC_VOLATILE_LOAD_FUNCDESC 3) |
669eeb28 BS |
148 | (UNSPEC_VOLATILE_STORE_EH_HANDLER 4) |
149 | (UNSPEC_VOLATILE_DUMMY 5)]) | |
0d4a78eb | 150 | |
75d8b2d0 BS |
151 | (define_constants |
152 | [(MACFLAG_NONE 0) | |
153 | (MACFLAG_T 1) | |
154 | (MACFLAG_FU 2) | |
155 | (MACFLAG_TFU 3) | |
156 | (MACFLAG_IS 4) | |
157 | (MACFLAG_IU 5) | |
158 | (MACFLAG_W32 6) | |
159 | (MACFLAG_M 7) | |
3efd5670 BS |
160 | (MACFLAG_IS_M 8) |
161 | (MACFLAG_S2RND 9) | |
162 | (MACFLAG_ISS2 10) | |
163 | (MACFLAG_IH 11)]) | |
75d8b2d0 | 164 | |
0d4a78eb | 165 | (define_attr "type" |
96f46444 | 166 | "move,movcc,mvi,mcld,mcst,dsp32,mult,alu0,shft,brcc,br,call,misc,sync,compare,dummy" |
0d4a78eb BS |
167 | (const_string "misc")) |
168 | ||
36662eb1 BS |
169 | (define_attr "addrtype" "32bit,preg,ireg" |
170 | (cond [(and (eq_attr "type" "mcld") | |
171 | (and (match_operand 0 "d_register_operand" "") | |
172 | (match_operand 1 "mem_p_address_operand" ""))) | |
173 | (const_string "preg") | |
174 | (and (eq_attr "type" "mcld") | |
175 | (and (match_operand 0 "d_register_operand" "") | |
176 | (match_operand 1 "mem_i_address_operand" ""))) | |
177 | (const_string "ireg") | |
178 | (and (eq_attr "type" "mcst") | |
179 | (and (match_operand 1 "d_register_operand" "") | |
180 | (match_operand 0 "mem_p_address_operand" ""))) | |
181 | (const_string "preg") | |
182 | (and (eq_attr "type" "mcst") | |
183 | (and (match_operand 1 "d_register_operand" "") | |
184 | (match_operand 0 "mem_i_address_operand" ""))) | |
185 | (const_string "ireg")] | |
186 | (const_string "32bit"))) | |
187 | ||
0d4a78eb BS |
188 | ;; Scheduling definitions |
189 | ||
190 | (define_automaton "bfin") | |
191 | ||
36662eb1 BS |
192 | (define_cpu_unit "slot0" "bfin") |
193 | (define_cpu_unit "slot1" "bfin") | |
194 | (define_cpu_unit "slot2" "bfin") | |
195 | ||
196 | ;; Three units used to enforce parallel issue restrictions: | |
942fd98f | 197 | ;; only one of the 16-bit slots can use a P register in an address, |
36662eb1 BS |
198 | ;; and only one them can be a store. |
199 | (define_cpu_unit "store" "bfin") | |
200 | (define_cpu_unit "pregs" "bfin") | |
201 | ||
202 | (define_reservation "core" "slot0+slot1+slot2") | |
0d4a78eb BS |
203 | |
204 | (define_insn_reservation "alu" 1 | |
96f46444 | 205 | (eq_attr "type" "move,movcc,mvi,alu0,shft,brcc,br,call,misc,sync,compare") |
0d4a78eb BS |
206 | "core") |
207 | ||
208 | (define_insn_reservation "imul" 3 | |
209 | (eq_attr "type" "mult") | |
210 | "core*3") | |
211 | ||
36662eb1 BS |
212 | (define_insn_reservation "dsp32" 1 |
213 | (eq_attr "type" "dsp32") | |
214 | "slot0") | |
215 | ||
216 | (define_insn_reservation "load32" 1 | |
217 | (and (not (eq_attr "seq_insns" "multi")) | |
218 | (and (eq_attr "type" "mcld") (eq_attr "addrtype" "32bit"))) | |
219 | "core") | |
220 | ||
221 | (define_insn_reservation "loadp" 1 | |
222 | (and (not (eq_attr "seq_insns" "multi")) | |
223 | (and (eq_attr "type" "mcld") (eq_attr "addrtype" "preg"))) | |
224 | "(slot1|slot2)+pregs") | |
225 | ||
226 | (define_insn_reservation "loadi" 1 | |
227 | (and (not (eq_attr "seq_insns" "multi")) | |
228 | (and (eq_attr "type" "mcld") (eq_attr "addrtype" "ireg"))) | |
229 | "(slot1|slot2)") | |
230 | ||
231 | (define_insn_reservation "store32" 1 | |
232 | (and (not (eq_attr "seq_insns" "multi")) | |
233 | (and (eq_attr "type" "mcst") (eq_attr "addrtype" "32bit"))) | |
0d4a78eb BS |
234 | "core") |
235 | ||
36662eb1 BS |
236 | (define_insn_reservation "storep" 1 |
237 | (and (not (eq_attr "seq_insns" "multi")) | |
238 | (and (eq_attr "type" "mcst") (eq_attr "addrtype" "preg"))) | |
239 | "(slot1|slot2)+pregs+store") | |
240 | ||
241 | (define_insn_reservation "storei" 1 | |
242 | (and (not (eq_attr "seq_insns" "multi")) | |
243 | (and (eq_attr "type" "mcst") (eq_attr "addrtype" "ireg"))) | |
244 | "(slot1|slot2)+store") | |
245 | ||
246 | (define_insn_reservation "multi" 2 | |
247 | (eq_attr "seq_insns" "multi") | |
248 | "core") | |
249 | ||
250 | (absence_set "slot0" "slot1,slot2") | |
251 | (absence_set "slot1" "slot2") | |
252 | ||
0d4a78eb BS |
253 | ;; Make sure genautomata knows about the maximum latency that can be produced |
254 | ;; by the adjust_cost function. | |
255 | (define_insn_reservation "dummy" 5 | |
36662eb1 | 256 | (eq_attr "type" "dummy") |
0d4a78eb BS |
257 | "core") |
258 | \f | |
259 | ;; Operand and operator predicates | |
260 | ||
261 | (include "predicates.md") | |
9fdd7520 | 262 | (include "constraints.md") |
0d4a78eb BS |
263 | \f |
264 | ;;; FRIO branches have been optimized for code density | |
265 | ;;; this comes at a slight cost of complexity when | |
266 | ;;; a compiler needs to generate branches in the general | |
267 | ;;; case. In order to generate the correct branching | |
268 | ;;; mechanisms the compiler needs keep track of instruction | |
269 | ;;; lengths. The follow table describes how to count instructions | |
270 | ;;; for the FRIO architecture. | |
271 | ;;; | |
272 | ;;; unconditional br are 12-bit imm pcrelative branches *2 | |
273 | ;;; conditional br are 10-bit imm pcrelative branches *2 | |
274 | ;;; brcc 10-bit: | |
275 | ;;; 1024 10-bit imm *2 is 2048 (-1024..1022) | |
276 | ;;; br 12-bit : | |
277 | ;;; 4096 12-bit imm *2 is 8192 (-4096..4094) | |
278 | ;;; NOTE : For brcc we generate instructions such as | |
279 | ;;; if cc jmp; jump.[sl] offset | |
280 | ;;; offset of jump.[sl] is from the jump instruction but | |
281 | ;;; gcc calculates length from the if cc jmp instruction | |
a2391c6a JZ |
282 | ;;; furthermore gcc takes the end address of the branch instruction |
283 | ;;; as (pc) for a forward branch | |
284 | ;;; hence our range is (-4094, 4092) instead of (-4096, 4094) for a br | |
0d4a78eb BS |
285 | ;;; |
286 | ;;; The way the (pc) rtx works in these calculations is somewhat odd; | |
287 | ;;; for backward branches it's the address of the current instruction, | |
288 | ;;; for forward branches it's the previously known address of the following | |
289 | ;;; instruction - we have to take this into account by reducing the range | |
290 | ;;; for a forward branch. | |
291 | ||
292 | ;; Lengths for type "mvi" insns are always defined by the instructions | |
293 | ;; themselves. | |
294 | (define_attr "length" "" | |
295 | (cond [(eq_attr "type" "mcld") | |
296 | (if_then_else (match_operand 1 "effective_address_32bit_p" "") | |
297 | (const_int 4) (const_int 2)) | |
298 | ||
299 | (eq_attr "type" "mcst") | |
300 | (if_then_else (match_operand 0 "effective_address_32bit_p" "") | |
301 | (const_int 4) (const_int 2)) | |
302 | ||
303 | (eq_attr "type" "move") (const_int 2) | |
304 | ||
305 | (eq_attr "type" "dsp32") (const_int 4) | |
306 | (eq_attr "type" "call") (const_int 4) | |
307 | ||
308 | (eq_attr "type" "br") | |
309 | (if_then_else (and | |
310 | (le (minus (match_dup 0) (pc)) (const_int 4092)) | |
311 | (ge (minus (match_dup 0) (pc)) (const_int -4096))) | |
312 | (const_int 2) | |
313 | (const_int 4)) | |
314 | ||
315 | (eq_attr "type" "brcc") | |
316 | (cond [(and | |
317 | (le (minus (match_dup 3) (pc)) (const_int 1020)) | |
318 | (ge (minus (match_dup 3) (pc)) (const_int -1024))) | |
319 | (const_int 2) | |
320 | (and | |
a2391c6a | 321 | (le (minus (match_dup 3) (pc)) (const_int 4092)) |
0d4a78eb BS |
322 | (ge (minus (match_dup 3) (pc)) (const_int -4094))) |
323 | (const_int 4)] | |
324 | (const_int 6)) | |
325 | ] | |
326 | ||
327 | (const_int 2))) | |
328 | ||
b03149e1 JZ |
329 | ;; Classify the insns into those that are one instruction and those that |
330 | ;; are more than one in sequence. | |
331 | (define_attr "seq_insns" "single,multi" | |
332 | (const_string "single")) | |
333 | ||
4ceb4242 BS |
334 | ;; Describe a user's asm statement. |
335 | (define_asm_attributes | |
336 | [(set_attr "type" "misc") | |
337 | (set_attr "seq_insns" "multi") | |
338 | (set_attr "length" "4")]) | |
339 | ||
0d4a78eb BS |
340 | ;; Conditional moves |
341 | ||
342 | (define_expand "movsicc" | |
343 | [(set (match_operand:SI 0 "register_operand" "") | |
344 | (if_then_else:SI (match_operand 1 "comparison_operator" "") | |
345 | (match_operand:SI 2 "register_operand" "") | |
346 | (match_operand:SI 3 "register_operand" "")))] | |
347 | "" | |
348 | { | |
349 | operands[1] = bfin_gen_compare (operands[1], SImode); | |
350 | }) | |
351 | ||
352 | (define_insn "*movsicc_insn1" | |
353 | [(set (match_operand:SI 0 "register_operand" "=da,da,da") | |
354 | (if_then_else:SI | |
4729dc92 | 355 | (eq:BI (match_operand:BI 3 "register_operand" "C,C,C") |
0d4a78eb BS |
356 | (const_int 0)) |
357 | (match_operand:SI 1 "register_operand" "da,0,da") | |
358 | (match_operand:SI 2 "register_operand" "0,da,da")))] | |
359 | "" | |
360 | "@ | |
361 | if !cc %0 =%1; /* movsicc-1a */ | |
362 | if cc %0 =%2; /* movsicc-1b */ | |
363 | if !cc %0 =%1; if cc %0=%2; /* movsicc-1 */" | |
364 | [(set_attr "length" "2,2,4") | |
96f46444 | 365 | (set_attr "type" "movcc") |
b03149e1 | 366 | (set_attr "seq_insns" "*,*,multi")]) |
0d4a78eb BS |
367 | |
368 | (define_insn "*movsicc_insn2" | |
369 | [(set (match_operand:SI 0 "register_operand" "=da,da,da") | |
370 | (if_then_else:SI | |
4729dc92 | 371 | (ne:BI (match_operand:BI 3 "register_operand" "C,C,C") |
0d4a78eb BS |
372 | (const_int 0)) |
373 | (match_operand:SI 1 "register_operand" "0,da,da") | |
374 | (match_operand:SI 2 "register_operand" "da,0,da")))] | |
375 | "" | |
376 | "@ | |
377 | if !cc %0 =%2; /* movsicc-2b */ | |
378 | if cc %0 =%1; /* movsicc-2a */ | |
379 | if cc %0 =%1; if !cc %0=%2; /* movsicc-1 */" | |
380 | [(set_attr "length" "2,2,4") | |
96f46444 | 381 | (set_attr "type" "movcc") |
b03149e1 | 382 | (set_attr "seq_insns" "*,*,multi")]) |
0d4a78eb BS |
383 | |
384 | ;; Insns to load HIGH and LO_SUM | |
385 | ||
386 | (define_insn "movsi_high" | |
387 | [(set (match_operand:SI 0 "register_operand" "=x") | |
388 | (high:SI (match_operand:SI 1 "immediate_operand" "i")))] | |
389 | "reload_completed" | |
390 | "%d0 = %d1;" | |
391 | [(set_attr "type" "mvi") | |
392 | (set_attr "length" "4")]) | |
393 | ||
394 | (define_insn "movstricthi_high" | |
395 | [(set (match_operand:SI 0 "register_operand" "+x") | |
396 | (ior:SI (and:SI (match_dup 0) (const_int 65535)) | |
397 | (match_operand:SI 1 "immediate_operand" "i")))] | |
398 | "reload_completed" | |
399 | "%d0 = %d1;" | |
400 | [(set_attr "type" "mvi") | |
401 | (set_attr "length" "4")]) | |
402 | ||
403 | (define_insn "movsi_low" | |
404 | [(set (match_operand:SI 0 "register_operand" "=x") | |
405 | (lo_sum:SI (match_operand:SI 1 "register_operand" "0") | |
406 | (match_operand:SI 2 "immediate_operand" "i")))] | |
407 | "reload_completed" | |
408 | "%h0 = %h2;" | |
409 | [(set_attr "type" "mvi") | |
410 | (set_attr "length" "4")]) | |
411 | ||
412 | (define_insn "movsi_high_pic" | |
413 | [(set (match_operand:SI 0 "register_operand" "=x") | |
414 | (high:SI (unspec:SI [(match_operand:SI 1 "" "")] | |
415 | UNSPEC_MOVE_PIC)))] | |
416 | "" | |
417 | "%d0 = %1@GOT_LOW;" | |
418 | [(set_attr "type" "mvi") | |
419 | (set_attr "length" "4")]) | |
420 | ||
421 | (define_insn "movsi_low_pic" | |
422 | [(set (match_operand:SI 0 "register_operand" "=x") | |
423 | (lo_sum:SI (match_operand:SI 1 "register_operand" "0") | |
424 | (unspec:SI [(match_operand:SI 2 "" "")] | |
425 | UNSPEC_MOVE_PIC)))] | |
426 | "" | |
427 | "%h0 = %h2@GOT_HIGH;" | |
428 | [(set_attr "type" "mvi") | |
429 | (set_attr "length" "4")]) | |
430 | ||
431 | ;;; Move instructions | |
432 | ||
433 | (define_insn_and_split "movdi_insn" | |
434 | [(set (match_operand:DI 0 "nonimmediate_operand" "=x,mx,r") | |
435 | (match_operand:DI 1 "general_operand" "iFx,r,mx"))] | |
0ea80eb6 | 436 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG" |
0d4a78eb BS |
437 | "#" |
438 | "reload_completed" | |
439 | [(set (match_dup 2) (match_dup 3)) | |
440 | (set (match_dup 4) (match_dup 5))] | |
441 | { | |
442 | rtx lo_half[2], hi_half[2]; | |
443 | split_di (operands, 2, lo_half, hi_half); | |
444 | ||
445 | if (reg_overlap_mentioned_p (lo_half[0], hi_half[1])) | |
446 | { | |
447 | operands[2] = hi_half[0]; | |
448 | operands[3] = hi_half[1]; | |
449 | operands[4] = lo_half[0]; | |
450 | operands[5] = lo_half[1]; | |
451 | } | |
452 | else | |
453 | { | |
454 | operands[2] = lo_half[0]; | |
455 | operands[3] = lo_half[1]; | |
456 | operands[4] = hi_half[0]; | |
457 | operands[5] = hi_half[1]; | |
458 | } | |
459 | }) | |
460 | ||
461 | (define_insn "movbi" | |
669eeb28 BS |
462 | [(set (match_operand:BI 0 "nonimmediate_operand" "=x,x,d,md,C,d,C,P1") |
463 | (match_operand:BI 1 "general_operand" "x,xKs3,md,d,d,C,P0,P1"))] | |
0d4a78eb BS |
464 | |
465 | "" | |
466 | "@ | |
467 | %0 = %1; | |
468 | %0 = %1 (X); | |
bbbc206e | 469 | %0 = B %1 (Z)%! |
4729dc92 | 470 | B %0 = %1; |
0d4a78eb | 471 | CC = %1; |
49373252 | 472 | %0 = CC; |
669eeb28 BS |
473 | CC = R0 < R0; |
474 | CC = R0 == R0;" | |
475 | [(set_attr "type" "move,mvi,mcld,mcst,compare,compare,compare,compare") | |
476 | (set_attr "length" "2,2,*,*,2,2,2,2") | |
477 | (set_attr "seq_insns" "*,*,*,*,*,*,*,*")]) | |
0d4a78eb BS |
478 | |
479 | (define_insn "movpdi" | |
480 | [(set (match_operand:PDI 0 "nonimmediate_operand" "=e,<,e") | |
481 | (match_operand:PDI 1 "general_operand" " e,e,>"))] | |
482 | "" | |
483 | "@ | |
484 | %0 = %1; | |
485 | %0 = %x1; %0 = %w1; | |
486 | %w0 = %1; %x0 = %1;" | |
b03149e1 JZ |
487 | [(set_attr "type" "move,mcst,mcld") |
488 | (set_attr "seq_insns" "*,multi,multi")]) | |
0d4a78eb | 489 | |
75d8b2d0 BS |
490 | (define_insn "load_accumulator" |
491 | [(set (match_operand:PDI 0 "register_operand" "=e") | |
492 | (sign_extend:PDI (match_operand:SI 1 "register_operand" "d")))] | |
493 | "" | |
494 | "%0 = %1;" | |
495 | [(set_attr "type" "move")]) | |
496 | ||
497 | (define_insn_and_split "load_accumulator_pair" | |
498 | [(set (match_operand:V2PDI 0 "register_operand" "=e") | |
499 | (sign_extend:V2PDI (vec_concat:V2SI | |
500 | (match_operand:SI 1 "register_operand" "d") | |
501 | (match_operand:SI 2 "register_operand" "d"))))] | |
502 | "" | |
503 | "#" | |
504 | "reload_completed" | |
505 | [(set (match_dup 3) (sign_extend:PDI (match_dup 1))) | |
506 | (set (match_dup 4) (sign_extend:PDI (match_dup 2)))] | |
507 | { | |
508 | operands[3] = gen_rtx_REG (PDImode, REGNO (operands[0])); | |
509 | operands[4] = gen_rtx_REG (PDImode, REGNO (operands[0]) + 1); | |
510 | }) | |
511 | ||
0d4a78eb BS |
512 | (define_insn "*pushsi_insn" |
513 | [(set (mem:SI (pre_dec:SI (reg:SI REG_SP))) | |
514 | (match_operand:SI 0 "register_operand" "xy"))] | |
515 | "" | |
516 | "[--SP] = %0;" | |
517 | [(set_attr "type" "mcst") | |
35e3ced9 | 518 | (set_attr "addrtype" "32bit") |
0d4a78eb BS |
519 | (set_attr "length" "2")]) |
520 | ||
521 | (define_insn "*popsi_insn" | |
35e3ced9 | 522 | [(set (match_operand:SI 0 "register_operand" "=d,xy") |
0d4a78eb BS |
523 | (mem:SI (post_inc:SI (reg:SI REG_SP))))] |
524 | "" | |
bbbc206e | 525 | "%0 = [SP++]%!" |
0d4a78eb | 526 | [(set_attr "type" "mcld") |
35e3ced9 | 527 | (set_attr "addrtype" "preg,32bit") |
0d4a78eb BS |
528 | (set_attr "length" "2")]) |
529 | ||
530 | ;; The first alternative is used to make reload choose a limited register | |
531 | ;; class when faced with a movsi_insn that had its input operand replaced | |
532 | ;; with a PLUS. We generally require fewer secondary reloads this way. | |
0d4a78eb | 533 | |
b03149e1 | 534 | (define_insn "*movsi_insn" |
97a988bc BS |
535 | [(set (match_operand:SI 0 "nonimmediate_operand" "=da,x,da,y,da,x,x,x,da,mr") |
536 | (match_operand:SI 1 "general_operand" "da,x,y,da,xKs7,xKsh,xKuh,ix,mr,da"))] | |
0ea80eb6 | 537 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG" |
b03149e1 | 538 | "@ |
97a988bc BS |
539 | %0 = %1; |
540 | %0 = %1; | |
0d4a78eb BS |
541 | %0 = %1; |
542 | %0 = %1; | |
543 | %0 = %1 (X); | |
544 | %0 = %1 (X); | |
545 | %0 = %1 (Z); | |
546 | # | |
bbbc206e BS |
547 | %0 = %1%! |
548 | %0 = %1%!" | |
97a988bc BS |
549 | [(set_attr "type" "move,move,move,move,mvi,mvi,mvi,*,mcld,mcst") |
550 | (set_attr "length" "2,2,2,2,2,4,4,*,*,*")]) | |
0d4a78eb | 551 | |
bbbc206e BS |
552 | (define_insn "*movsi_insn32" |
553 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
554 | (unspec:SI [(match_operand:SI 1 "nonmemory_operand" "d,P0")] UNSPEC_32BIT))] | |
555 | "" | |
556 | "@ | |
557 | %0 = ROT %1 BY 0%! | |
558 | %0 = %0 -|- %0%!" | |
559 | [(set_attr "type" "dsp32")]) | |
560 | ||
561 | (define_split | |
562 | [(set (match_operand:SI 0 "d_register_operand" "") | |
563 | (const_int 0))] | |
564 | "splitting_for_sched && !optimize_size" | |
565 | [(set (match_dup 0) (unspec:SI [(const_int 0)] UNSPEC_32BIT))]) | |
566 | ||
567 | (define_split | |
568 | [(set (match_operand:SI 0 "d_register_operand" "") | |
569 | (match_operand:SI 1 "d_register_operand" ""))] | |
570 | "splitting_for_sched && !optimize_size" | |
571 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_32BIT))]) | |
572 | ||
75d8b2d0 BS |
573 | (define_insn_and_split "*movv2hi_insn" |
574 | [(set (match_operand:V2HI 0 "nonimmediate_operand" "=da,da,d,dm") | |
575 | (match_operand:V2HI 1 "general_operand" "i,di,md,d"))] | |
0d4a78eb | 576 | |
0ea80eb6 | 577 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG" |
75d8b2d0 BS |
578 | "@ |
579 | # | |
580 | %0 = %1; | |
bbbc206e BS |
581 | %0 = %1%! |
582 | %0 = %1%!" | |
75d8b2d0 BS |
583 | "reload_completed && GET_CODE (operands[1]) == CONST_VECTOR" |
584 | [(set (match_dup 0) (high:SI (match_dup 2))) | |
585 | (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 3)))] | |
586 | { | |
587 | HOST_WIDE_INT intval = INTVAL (XVECEXP (operands[1], 0, 1)) << 16; | |
588 | intval |= INTVAL (XVECEXP (operands[1], 0, 0)) & 0xFFFF; | |
554006bd | 589 | |
75d8b2d0 BS |
590 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[0])); |
591 | operands[2] = operands[3] = GEN_INT (trunc_int_for_mode (intval, SImode)); | |
592 | } | |
593 | [(set_attr "type" "move,move,mcld,mcst") | |
594 | (set_attr "length" "2,2,*,*")]) | |
0d4a78eb BS |
595 | |
596 | (define_insn "*movhi_insn" | |
597 | [(set (match_operand:HI 0 "nonimmediate_operand" "=x,da,x,d,mr") | |
598 | (match_operand:HI 1 "general_operand" "x,xKs7,xKsh,mr,d"))] | |
0ea80eb6 | 599 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG" |
c4963a0a BS |
600 | { |
601 | static const char *templates[] = { | |
602 | "%0 = %1;", | |
603 | "%0 = %1 (X);", | |
604 | "%0 = %1 (X);", | |
bbbc206e BS |
605 | "%0 = W %1 (X)%!", |
606 | "W %0 = %1%!", | |
607 | "%h0 = W %1%!", | |
608 | "W %0 = %h1%!" | |
c4963a0a BS |
609 | }; |
610 | int alt = which_alternative; | |
611 | rtx mem = (MEM_P (operands[0]) ? operands[0] | |
612 | : MEM_P (operands[1]) ? operands[1] : NULL_RTX); | |
613 | if (mem && bfin_dsp_memref_p (mem)) | |
614 | alt += 2; | |
615 | return templates[alt]; | |
616 | } | |
0d4a78eb BS |
617 | [(set_attr "type" "move,mvi,mvi,mcld,mcst") |
618 | (set_attr "length" "2,2,4,*,*")]) | |
619 | ||
620 | (define_insn "*movqi_insn" | |
621 | [(set (match_operand:QI 0 "nonimmediate_operand" "=x,da,x,d,mr") | |
622 | (match_operand:QI 1 "general_operand" "x,xKs7,xKsh,mr,d"))] | |
0ea80eb6 | 623 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG" |
0d4a78eb BS |
624 | "@ |
625 | %0 = %1; | |
626 | %0 = %1 (X); | |
627 | %0 = %1 (X); | |
bbbc206e BS |
628 | %0 = B %1 (X)%! |
629 | B %0 = %1%!" | |
0d4a78eb BS |
630 | [(set_attr "type" "move,mvi,mvi,mcld,mcst") |
631 | (set_attr "length" "2,2,4,*,*")]) | |
632 | ||
633 | (define_insn "*movsf_insn" | |
634 | [(set (match_operand:SF 0 "nonimmediate_operand" "=x,x,da,mr") | |
635 | (match_operand:SF 1 "general_operand" "x,Fx,mr,da"))] | |
0ea80eb6 | 636 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG" |
0d4a78eb BS |
637 | "@ |
638 | %0 = %1; | |
639 | # | |
bbbc206e BS |
640 | %0 = %1%! |
641 | %0 = %1%!" | |
0d4a78eb BS |
642 | [(set_attr "type" "move,*,mcld,mcst")]) |
643 | ||
644 | (define_insn_and_split "movdf_insn" | |
645 | [(set (match_operand:DF 0 "nonimmediate_operand" "=x,mx,r") | |
646 | (match_operand:DF 1 "general_operand" "iFx,r,mx"))] | |
0ea80eb6 | 647 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG" |
0d4a78eb BS |
648 | "#" |
649 | "reload_completed" | |
650 | [(set (match_dup 2) (match_dup 3)) | |
651 | (set (match_dup 4) (match_dup 5))] | |
652 | { | |
653 | rtx lo_half[2], hi_half[2]; | |
654 | split_di (operands, 2, lo_half, hi_half); | |
655 | ||
656 | if (reg_overlap_mentioned_p (lo_half[0], hi_half[1])) | |
657 | { | |
658 | operands[2] = hi_half[0]; | |
659 | operands[3] = hi_half[1]; | |
660 | operands[4] = lo_half[0]; | |
661 | operands[5] = lo_half[1]; | |
662 | } | |
663 | else | |
664 | { | |
665 | operands[2] = lo_half[0]; | |
666 | operands[3] = lo_half[1]; | |
667 | operands[4] = hi_half[0]; | |
668 | operands[5] = hi_half[1]; | |
669 | } | |
670 | }) | |
671 | ||
75d8b2d0 BS |
672 | ;; Storing halfwords. |
673 | (define_insn "*movsi_insv" | |
674 | [(set (zero_extract:SI (match_operand 0 "register_operand" "+d,x") | |
675 | (const_int 16) | |
676 | (const_int 16)) | |
677 | (match_operand:SI 1 "nonmemory_operand" "d,n"))] | |
678 | "" | |
679 | "@ | |
bbbc206e | 680 | %d0 = %h1 << 0%! |
75d8b2d0 BS |
681 | %d0 = %1;" |
682 | [(set_attr "type" "dsp32,mvi")]) | |
683 | ||
684 | (define_expand "insv" | |
685 | [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "") | |
686 | (match_operand:SI 1 "immediate_operand" "") | |
687 | (match_operand:SI 2 "immediate_operand" "")) | |
688 | (match_operand:SI 3 "nonmemory_operand" ""))] | |
689 | "" | |
690 | { | |
691 | if (INTVAL (operands[1]) != 16 || INTVAL (operands[2]) != 16) | |
692 | FAIL; | |
693 | ||
694 | /* From mips.md: insert_bit_field doesn't verify that our source | |
695 | matches the predicate, so check it again here. */ | |
696 | if (! register_operand (operands[0], VOIDmode)) | |
697 | FAIL; | |
698 | }) | |
699 | ||
0d4a78eb BS |
700 | ;; This is the main "hook" for PIC code. When generating |
701 | ;; PIC, movsi is responsible for determining when the source address | |
702 | ;; needs PIC relocation and appropriately calling legitimize_pic_address | |
703 | ;; to perform the actual relocation. | |
704 | ||
705 | (define_expand "movsi" | |
706 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
707 | (match_operand:SI 1 "general_operand" ""))] | |
708 | "" | |
d6f6753e BS |
709 | { |
710 | if (expand_move (operands, SImode)) | |
711 | DONE; | |
712 | }) | |
0d4a78eb BS |
713 | |
714 | (define_expand "movv2hi" | |
715 | [(set (match_operand:V2HI 0 "nonimmediate_operand" "") | |
716 | (match_operand:V2HI 1 "general_operand" ""))] | |
717 | "" | |
718 | "expand_move (operands, V2HImode);") | |
719 | ||
720 | (define_expand "movdi" | |
721 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
722 | (match_operand:DI 1 "general_operand" ""))] | |
723 | "" | |
724 | "expand_move (operands, DImode);") | |
725 | ||
726 | (define_expand "movsf" | |
727 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
728 | (match_operand:SF 1 "general_operand" ""))] | |
729 | "" | |
730 | "expand_move (operands, SFmode);") | |
731 | ||
732 | (define_expand "movdf" | |
733 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
734 | (match_operand:DF 1 "general_operand" ""))] | |
735 | "" | |
736 | "expand_move (operands, DFmode);") | |
737 | ||
738 | (define_expand "movhi" | |
739 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
740 | (match_operand:HI 1 "general_operand" ""))] | |
741 | "" | |
742 | "expand_move (operands, HImode);") | |
743 | ||
744 | (define_expand "movqi" | |
745 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
746 | (match_operand:QI 1 "general_operand" ""))] | |
747 | "" | |
748 | " expand_move (operands, QImode); ") | |
749 | ||
750 | ;; Some define_splits to break up SI/SFmode loads of immediate constants. | |
751 | ||
752 | (define_split | |
753 | [(set (match_operand:SI 0 "register_operand" "") | |
754 | (match_operand:SI 1 "symbolic_or_const_operand" ""))] | |
755 | "reload_completed | |
756 | /* Always split symbolic operands; split integer constants that are | |
757 | too large for a single instruction. */ | |
758 | && (GET_CODE (operands[1]) != CONST_INT | |
759 | || (INTVAL (operands[1]) < -32768 | |
760 | || INTVAL (operands[1]) >= 65536 | |
761 | || (INTVAL (operands[1]) >= 32768 && PREG_P (operands[0]))))" | |
762 | [(set (match_dup 0) (high:SI (match_dup 1))) | |
763 | (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 1)))] | |
764 | { | |
765 | if (GET_CODE (operands[1]) == CONST_INT | |
766 | && split_load_immediate (operands)) | |
767 | DONE; | |
768 | /* ??? Do something about TARGET_LOW_64K. */ | |
769 | }) | |
770 | ||
771 | (define_split | |
772 | [(set (match_operand:SF 0 "register_operand" "") | |
773 | (match_operand:SF 1 "immediate_operand" ""))] | |
774 | "reload_completed" | |
775 | [(set (match_dup 2) (high:SI (match_dup 3))) | |
776 | (set (match_dup 2) (lo_sum:SI (match_dup 2) (match_dup 3)))] | |
777 | { | |
778 | long values; | |
779 | REAL_VALUE_TYPE value; | |
780 | ||
3b9dd769 | 781 | gcc_assert (GET_CODE (operands[1]) == CONST_DOUBLE); |
0d4a78eb BS |
782 | |
783 | REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]); | |
784 | REAL_VALUE_TO_TARGET_SINGLE (value, values); | |
785 | ||
786 | operands[2] = gen_rtx_REG (SImode, true_regnum (operands[0])); | |
787 | operands[3] = GEN_INT (trunc_int_for_mode (values, SImode)); | |
788 | if (values >= -32768 && values < 65536) | |
789 | { | |
790 | emit_move_insn (operands[2], operands[3]); | |
791 | DONE; | |
792 | } | |
793 | if (split_load_immediate (operands + 2)) | |
794 | DONE; | |
795 | }) | |
796 | ||
797 | ;; Sadly, this can't be a proper named movstrict pattern, since the compiler | |
798 | ;; expects to be able to use registers for operand 1. | |
799 | ;; Note that the asm instruction is defined by the manual to take an unsigned | |
800 | ;; constant, but it doesn't matter to the assembler, and the compiler only | |
801 | ;; deals with sign-extended constants. Hence "Ksh". | |
75d8b2d0 | 802 | (define_insn "movstricthi_1" |
0d4a78eb BS |
803 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+x")) |
804 | (match_operand:HI 1 "immediate_operand" "Ksh"))] | |
805 | "" | |
806 | "%h0 = %1;" | |
807 | [(set_attr "type" "mvi") | |
808 | (set_attr "length" "4")]) | |
809 | ||
810 | ;; Sign and zero extensions | |
811 | ||
c4963a0a | 812 | (define_insn_and_split "extendhisi2" |
0d4a78eb BS |
813 | [(set (match_operand:SI 0 "register_operand" "=d, d") |
814 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))] | |
815 | "" | |
816 | "@ | |
817 | %0 = %h1 (X); | |
bbbc206e | 818 | %0 = W %h1 (X)%!" |
c4963a0a BS |
819 | "reload_completed && bfin_dsp_memref_p (operands[1])" |
820 | [(set (match_dup 2) (match_dup 1)) | |
821 | (set (match_dup 0) (sign_extend:SI (match_dup 2)))] | |
822 | { | |
823 | operands[2] = gen_lowpart (HImode, operands[0]); | |
824 | } | |
0d4a78eb BS |
825 | [(set_attr "type" "alu0,mcld")]) |
826 | ||
c4963a0a | 827 | (define_insn_and_split "zero_extendhisi2" |
0d4a78eb BS |
828 | [(set (match_operand:SI 0 "register_operand" "=d, d") |
829 | (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))] | |
830 | "" | |
831 | "@ | |
832 | %0 = %h1 (Z); | |
bbbc206e | 833 | %0 = W %h1 (Z)%!" |
c4963a0a BS |
834 | "reload_completed && bfin_dsp_memref_p (operands[1])" |
835 | [(set (match_dup 2) (match_dup 1)) | |
836 | (set (match_dup 0) (zero_extend:SI (match_dup 2)))] | |
837 | { | |
838 | operands[2] = gen_lowpart (HImode, operands[0]); | |
839 | } | |
0d4a78eb BS |
840 | [(set_attr "type" "alu0,mcld")]) |
841 | ||
842 | (define_insn "zero_extendbisi2" | |
843 | [(set (match_operand:SI 0 "register_operand" "=d") | |
844 | (zero_extend:SI (match_operand:BI 1 "nonimmediate_operand" "C")))] | |
845 | "" | |
846 | "%0 = %1;" | |
847 | [(set_attr "type" "compare")]) | |
848 | ||
849 | (define_insn "extendqihi2" | |
850 | [(set (match_operand:HI 0 "register_operand" "=d, d") | |
851 | (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] | |
852 | "" | |
853 | "@ | |
bbbc206e | 854 | %0 = B %1 (X)%! |
0d4a78eb BS |
855 | %0 = %T1 (X);" |
856 | [(set_attr "type" "mcld,alu0")]) | |
857 | ||
858 | (define_insn "extendqisi2" | |
859 | [(set (match_operand:SI 0 "register_operand" "=d, d") | |
860 | (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] | |
861 | "" | |
862 | "@ | |
bbbc206e | 863 | %0 = B %1 (X)%! |
0d4a78eb BS |
864 | %0 = %T1 (X);" |
865 | [(set_attr "type" "mcld,alu0")]) | |
866 | ||
867 | ||
868 | (define_insn "zero_extendqihi2" | |
869 | [(set (match_operand:HI 0 "register_operand" "=d, d") | |
870 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] | |
871 | "" | |
872 | "@ | |
bbbc206e | 873 | %0 = B %1 (Z)%! |
0d4a78eb BS |
874 | %0 = %T1 (Z);" |
875 | [(set_attr "type" "mcld,alu0")]) | |
876 | ||
877 | ||
878 | (define_insn "zero_extendqisi2" | |
879 | [(set (match_operand:SI 0 "register_operand" "=d, d") | |
880 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] | |
881 | "" | |
882 | "@ | |
bbbc206e | 883 | %0 = B %1 (Z)%! |
0d4a78eb BS |
884 | %0 = %T1 (Z);" |
885 | [(set_attr "type" "mcld,alu0")]) | |
886 | ||
887 | ;; DImode logical operations | |
888 | ||
3abcb3a7 | 889 | (define_code_iterator any_logical [and ior xor]) |
0d4a78eb BS |
890 | (define_code_attr optab [(and "and") |
891 | (ior "ior") | |
892 | (xor "xor")]) | |
893 | (define_code_attr op [(and "&") | |
894 | (ior "|") | |
895 | (xor "^")]) | |
896 | (define_code_attr high_result [(and "0") | |
897 | (ior "%H1") | |
898 | (xor "%H1")]) | |
899 | ||
e4fae5f7 BS |
900 | ;; Keep this pattern around to avoid generating NO_CONFLICT blocks. |
901 | (define_expand "<optab>di3" | |
0d4a78eb BS |
902 | [(set (match_operand:DI 0 "register_operand" "=d") |
903 | (any_logical:DI (match_operand:DI 1 "register_operand" "0") | |
e4fae5f7 | 904 | (match_operand:DI 2 "general_operand" "d")))] |
0d4a78eb | 905 | "" |
0d4a78eb | 906 | { |
e4fae5f7 BS |
907 | rtx hi_half[3], lo_half[3]; |
908 | enum insn_code icode = CODE_FOR_<optab>si3; | |
909 | if (!reg_overlap_mentioned_p (operands[0], operands[1]) | |
910 | && !reg_overlap_mentioned_p (operands[0], operands[2])) | |
c41c1387 | 911 | emit_clobber (operands[0]); |
e4fae5f7 BS |
912 | split_di (operands, 3, lo_half, hi_half); |
913 | if (!(*insn_data[icode].operand[2].predicate) (lo_half[2], SImode)) | |
914 | lo_half[2] = force_reg (SImode, lo_half[2]); | |
915 | emit_insn (GEN_FCN (icode) (lo_half[0], lo_half[1], lo_half[2])); | |
916 | if (!(*insn_data[icode].operand[2].predicate) (hi_half[2], SImode)) | |
917 | hi_half[2] = force_reg (SImode, hi_half[2]); | |
918 | emit_insn (GEN_FCN (icode) (hi_half[0], hi_half[1], hi_half[2])); | |
919 | DONE; | |
0d4a78eb BS |
920 | }) |
921 | ||
922 | (define_insn "zero_extendqidi2" | |
923 | [(set (match_operand:DI 0 "register_operand" "=d") | |
924 | (zero_extend:DI (match_operand:QI 1 "register_operand" "d")))] | |
925 | "" | |
926 | "%0 = %T1 (Z);\\n\\t%H0 = 0;" | |
b03149e1 JZ |
927 | [(set_attr "length" "4") |
928 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
929 | |
930 | (define_insn "zero_extendhidi2" | |
931 | [(set (match_operand:DI 0 "register_operand" "=d") | |
932 | (zero_extend:DI (match_operand:HI 1 "register_operand" "d")))] | |
933 | "" | |
934 | "%0 = %h1 (Z);\\n\\t%H0 = 0;" | |
b03149e1 JZ |
935 | [(set_attr "length" "4") |
936 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
937 | |
938 | (define_insn_and_split "extendsidi2" | |
939 | [(set (match_operand:DI 0 "register_operand" "=d") | |
940 | (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))] | |
941 | "" | |
942 | "#" | |
943 | "reload_completed" | |
944 | [(set (match_dup 3) (match_dup 1)) | |
945 | (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))] | |
946 | { | |
947 | split_di (operands, 1, operands + 2, operands + 3); | |
948 | if (REGNO (operands[0]) != REGNO (operands[1])) | |
949 | emit_move_insn (operands[2], operands[1]); | |
950 | }) | |
951 | ||
952 | (define_insn_and_split "extendqidi2" | |
953 | [(set (match_operand:DI 0 "register_operand" "=d") | |
954 | (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))] | |
955 | "" | |
956 | "#" | |
957 | "reload_completed" | |
958 | [(set (match_dup 2) (sign_extend:SI (match_dup 1))) | |
959 | (set (match_dup 3) (sign_extend:SI (match_dup 1))) | |
960 | (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))] | |
961 | { | |
962 | split_di (operands, 1, operands + 2, operands + 3); | |
963 | }) | |
964 | ||
965 | (define_insn_and_split "extendhidi2" | |
966 | [(set (match_operand:DI 0 "register_operand" "=d") | |
967 | (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))] | |
968 | "" | |
969 | "#" | |
970 | "reload_completed" | |
971 | [(set (match_dup 2) (sign_extend:SI (match_dup 1))) | |
972 | (set (match_dup 3) (sign_extend:SI (match_dup 1))) | |
973 | (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))] | |
974 | { | |
975 | split_di (operands, 1, operands + 2, operands + 3); | |
976 | }) | |
977 | ||
978 | ;; DImode arithmetic operations | |
979 | ||
2889abed BS |
980 | (define_insn "add_with_carry" |
981 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
e4fae5f7 | 982 | (plus:SI (match_operand:SI 1 "register_operand" "%0,d") |
2889abed | 983 | (match_operand:SI 2 "nonmemory_operand" "Ks7,d"))) |
e4fae5f7 BS |
984 | (set (match_operand:BI 3 "register_operand" "=C,C") |
985 | (ltu:BI (not:SI (match_dup 1)) (match_dup 2)))] | |
2889abed BS |
986 | "" |
987 | "@ | |
e4fae5f7 BS |
988 | %0 += %2; cc = ac0; |
989 | %0 = %1 + %2; cc = ac0;" | |
2889abed | 990 | [(set_attr "type" "alu0") |
e4fae5f7 | 991 | (set_attr "length" "4") |
2889abed BS |
992 | (set_attr "seq_insns" "multi")]) |
993 | ||
e4fae5f7 BS |
994 | (define_insn "sub_with_carry" |
995 | [(set (match_operand:SI 0 "register_operand" "=d") | |
996 | (minus:SI (match_operand:SI 1 "register_operand" "%d") | |
997 | (match_operand:SI 2 "nonmemory_operand" "d"))) | |
998 | (set (match_operand:BI 3 "register_operand" "=C") | |
999 | (leu:BI (match_dup 2) (match_dup 1)))] | |
0d4a78eb | 1000 | "" |
e4fae5f7 | 1001 | "%0 = %1 - %2; cc = ac0;" |
0d4a78eb | 1002 | [(set_attr "type" "alu0") |
e4fae5f7 | 1003 | (set_attr "length" "4") |
b03149e1 | 1004 | (set_attr "seq_insns" "multi")]) |
0d4a78eb | 1005 | |
e4fae5f7 BS |
1006 | (define_expand "adddi3" |
1007 | [(set (match_operand:DI 0 "register_operand" "") | |
1008 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
1009 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
1010 | (clobber (match_scratch:SI 3 "")) | |
0d4a78eb BS |
1011 | (clobber (reg:CC 34))] |
1012 | "" | |
e4fae5f7 BS |
1013 | { |
1014 | rtx xops[8]; | |
1015 | xops[0] = gen_lowpart (SImode, operands[0]); | |
1016 | xops[1] = simplify_gen_subreg (SImode, operands[0], DImode, 4); | |
1017 | xops[2] = gen_lowpart (SImode, operands[1]); | |
1018 | xops[3] = simplify_gen_subreg (SImode, operands[1], DImode, 4); | |
1019 | xops[4] = gen_lowpart (SImode, operands[2]); | |
1020 | xops[5] = simplify_gen_subreg (SImode, operands[2], DImode, 4); | |
1021 | xops[6] = gen_reg_rtx (SImode); | |
1022 | xops[7] = gen_rtx_REG (BImode, REG_CC); | |
1023 | if (!register_operand (xops[4], SImode) | |
1024 | && (GET_CODE (xops[4]) != CONST_INT | |
9fdd7520 | 1025 | || !satisfies_constraint_Ks7 (xops[4]))) |
e4fae5f7 BS |
1026 | xops[4] = force_reg (SImode, xops[4]); |
1027 | if (!reg_overlap_mentioned_p (operands[0], operands[1]) | |
1028 | && !reg_overlap_mentioned_p (operands[0], operands[2])) | |
c41c1387 | 1029 | emit_clobber (operands[0]); |
e4fae5f7 BS |
1030 | emit_insn (gen_add_with_carry (xops[0], xops[2], xops[4], xops[7])); |
1031 | emit_insn (gen_movbisi (xops[6], xops[7])); | |
1032 | if (!register_operand (xops[5], SImode) | |
1033 | && (GET_CODE (xops[5]) != CONST_INT | |
9fdd7520 | 1034 | || !satisfies_constraint_Ks7 (xops[5]))) |
e4fae5f7 BS |
1035 | xops[5] = force_reg (SImode, xops[5]); |
1036 | if (xops[5] != const0_rtx) | |
1037 | emit_insn (gen_addsi3 (xops[1], xops[3], xops[5])); | |
1038 | else | |
1039 | emit_move_insn (xops[1], xops[3]); | |
1040 | emit_insn (gen_addsi3 (xops[1], xops[1], xops[6])); | |
1041 | DONE; | |
1042 | }) | |
0d4a78eb | 1043 | |
e4fae5f7 BS |
1044 | (define_expand "subdi3" |
1045 | [(set (match_operand:DI 0 "register_operand" "") | |
1046 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
1047 | (match_operand:DI 2 "register_operand" ""))) | |
0d4a78eb BS |
1048 | (clobber (reg:CC 34))] |
1049 | "" | |
e4fae5f7 BS |
1050 | { |
1051 | rtx xops[8]; | |
1052 | xops[0] = gen_lowpart (SImode, operands[0]); | |
1053 | xops[1] = simplify_gen_subreg (SImode, operands[0], DImode, 4); | |
1054 | xops[2] = gen_lowpart (SImode, operands[1]); | |
1055 | xops[3] = simplify_gen_subreg (SImode, operands[1], DImode, 4); | |
1056 | xops[4] = gen_lowpart (SImode, operands[2]); | |
1057 | xops[5] = simplify_gen_subreg (SImode, operands[2], DImode, 4); | |
1058 | xops[6] = gen_reg_rtx (SImode); | |
1059 | xops[7] = gen_rtx_REG (BImode, REG_CC); | |
1060 | if (!reg_overlap_mentioned_p (operands[0], operands[1]) | |
1061 | && !reg_overlap_mentioned_p (operands[0], operands[2])) | |
c41c1387 | 1062 | emit_clobber (operands[0]); |
e4fae5f7 BS |
1063 | emit_insn (gen_sub_with_carry (xops[0], xops[2], xops[4], xops[7])); |
1064 | emit_insn (gen_notbi (xops[7], xops[7])); | |
1065 | emit_insn (gen_movbisi (xops[6], xops[7])); | |
1066 | emit_insn (gen_subsi3 (xops[1], xops[3], xops[5])); | |
1067 | emit_insn (gen_subsi3 (xops[1], xops[1], xops[6])); | |
1068 | DONE; | |
1069 | }) | |
0d4a78eb BS |
1070 | |
1071 | ;; Combined shift/add instructions | |
1072 | ||
1073 | (define_insn "" | |
1074 | [(set (match_operand:SI 0 "register_operand" "=a,d") | |
1075 | (ashift:SI (plus:SI (match_operand:SI 1 "register_operand" "%0,0") | |
1076 | (match_operand:SI 2 "register_operand" "a,d")) | |
1077 | (match_operand:SI 3 "pos_scale_operand" "P1P2,P1P2")))] | |
1078 | "" | |
1079 | "%0 = (%0 + %2) << %3;" /* "shadd %0,%2,%3;" */ | |
1080 | [(set_attr "type" "alu0")]) | |
1081 | ||
1082 | (define_insn "" | |
1083 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1084 | (plus:SI (match_operand:SI 1 "register_operand" "a") | |
1085 | (mult:SI (match_operand:SI 2 "register_operand" "a") | |
1086 | (match_operand:SI 3 "scale_by_operand" "i"))))] | |
1087 | "" | |
1088 | "%0 = %1 + (%2 << %X3);" | |
1089 | [(set_attr "type" "alu0")]) | |
1090 | ||
1091 | (define_insn "" | |
1092 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1093 | (plus:SI (match_operand:SI 1 "register_operand" "a") | |
1094 | (ashift:SI (match_operand:SI 2 "register_operand" "a") | |
1095 | (match_operand:SI 3 "pos_scale_operand" "i"))))] | |
1096 | "" | |
1097 | "%0 = %1 + (%2 << %3);" | |
1098 | [(set_attr "type" "alu0")]) | |
1099 | ||
1100 | (define_insn "" | |
1101 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1102 | (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "a") | |
1103 | (match_operand:SI 2 "scale_by_operand" "i")) | |
1104 | (match_operand:SI 3 "register_operand" "a")))] | |
1105 | "" | |
1106 | "%0 = %3 + (%1 << %X2);" | |
1107 | [(set_attr "type" "alu0")]) | |
1108 | ||
1109 | (define_insn "" | |
1110 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1111 | (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "a") | |
1112 | (match_operand:SI 2 "pos_scale_operand" "i")) | |
1113 | (match_operand:SI 3 "register_operand" "a")))] | |
1114 | "" | |
1115 | "%0 = %3 + (%1 << %2);" | |
1116 | [(set_attr "type" "alu0")]) | |
1117 | ||
1118 | (define_insn "mulhisi3" | |
1119 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1120 | (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%d")) | |
1121 | (sign_extend:SI (match_operand:HI 2 "register_operand" "d"))))] | |
1122 | "" | |
bbbc206e | 1123 | "%0 = %h1 * %h2 (IS)%!" |
0d4a78eb BS |
1124 | [(set_attr "type" "dsp32")]) |
1125 | ||
1126 | (define_insn "umulhisi3" | |
1127 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1128 | (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%d")) | |
1129 | (zero_extend:SI (match_operand:HI 2 "register_operand" "d"))))] | |
1130 | "" | |
bbbc206e | 1131 | "%0 = %h1 * %h2 (FU)%!" |
0d4a78eb BS |
1132 | [(set_attr "type" "dsp32")]) |
1133 | ||
8b44057d BS |
1134 | (define_insn "usmulhisi3" |
1135 | [(set (match_operand:SI 0 "register_operand" "=W") | |
1136 | (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "W")) | |
1137 | (sign_extend:SI (match_operand:HI 2 "register_operand" "W"))))] | |
1138 | "" | |
bbbc206e | 1139 | "%0 = %h2 * %h1 (IS,M)%!" |
8b44057d BS |
1140 | [(set_attr "type" "dsp32")]) |
1141 | ||
0d4a78eb BS |
1142 | ;; The processor also supports ireg += mreg or ireg -= mreg, but these |
1143 | ;; are unusable if we don't ensure that the corresponding lreg is zero. | |
1144 | ;; The same applies to the add/subtract constant versions involving | |
1145 | ;; iregs | |
1146 | ||
1147 | (define_insn "addsi3" | |
1148 | [(set (match_operand:SI 0 "register_operand" "=ad,a,d") | |
1149 | (plus:SI (match_operand:SI 1 "register_operand" "%0, a,d") | |
1150 | (match_operand:SI 2 "reg_or_7bit_operand" "Ks7, a,d")))] | |
1151 | "" | |
1152 | "@ | |
1153 | %0 += %2; | |
1154 | %0 = %1 + %2; | |
1155 | %0 = %1 + %2;" | |
1156 | [(set_attr "type" "alu0") | |
1157 | (set_attr "length" "2,2,2")]) | |
1158 | ||
75d8b2d0 BS |
1159 | (define_insn "ssaddsi3" |
1160 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1161 | (ss_plus:SI (match_operand:SI 1 "register_operand" "d") | |
1162 | (match_operand:SI 2 "register_operand" "d")))] | |
1163 | "" | |
bbbc206e | 1164 | "%0 = %1 + %2 (S)%!" |
75d8b2d0 BS |
1165 | [(set_attr "type" "dsp32")]) |
1166 | ||
d4e85050 | 1167 | (define_insn "subsi3" |
0d4a78eb BS |
1168 | [(set (match_operand:SI 0 "register_operand" "=da,d,a") |
1169 | (minus:SI (match_operand:SI 1 "register_operand" "0,d,0") | |
d4e85050 BS |
1170 | (match_operand:SI 2 "reg_or_neg7bit_operand" "KN7,d,a")))] |
1171 | "" | |
0d4a78eb BS |
1172 | { |
1173 | static const char *const strings_subsi3[] = { | |
1174 | "%0 += -%2;", | |
1175 | "%0 = %1 - %2;", | |
1176 | "%0 -= %2;", | |
1177 | }; | |
1178 | ||
1179 | if (CONSTANT_P (operands[2]) && INTVAL (operands[2]) < 0) { | |
1180 | rtx tmp_op = operands[2]; | |
1181 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
1182 | output_asm_insn ("%0 += %2;", operands); | |
1183 | operands[2] = tmp_op; | |
1184 | return ""; | |
1185 | } | |
1186 | ||
1187 | return strings_subsi3[which_alternative]; | |
1188 | } | |
1189 | [(set_attr "type" "alu0")]) | |
1190 | ||
75d8b2d0 BS |
1191 | (define_insn "sssubsi3" |
1192 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1193 | (ss_minus:SI (match_operand:SI 1 "register_operand" "d") | |
1194 | (match_operand:SI 2 "register_operand" "d")))] | |
1195 | "" | |
bbbc206e | 1196 | "%0 = %1 - %2 (S)%!" |
75d8b2d0 BS |
1197 | [(set_attr "type" "dsp32")]) |
1198 | ||
3efd5670 BS |
1199 | ;; Accumulator addition |
1200 | ||
314f9913 BS |
1201 | (define_insn "addpdi3" |
1202 | [(set (match_operand:PDI 0 "register_operand" "=A") | |
1203 | (ss_plus:PDI (match_operand:PDI 1 "register_operand" "%0") | |
1204 | (match_operand:PDI 2 "nonmemory_operand" "B")))] | |
1205 | "" | |
1206 | "A0 += A1%!" | |
1207 | [(set_attr "type" "dsp32")]) | |
1208 | ||
3efd5670 BS |
1209 | (define_insn "sum_of_accumulators" |
1210 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1211 | (ss_truncate:SI | |
1212 | (ss_plus:PDI (match_operand:PDI 2 "register_operand" "1") | |
1213 | (match_operand:PDI 3 "register_operand" "B")))) | |
1214 | (set (match_operand:PDI 1 "register_operand" "=A") | |
1215 | (ss_plus:PDI (match_dup 2) (match_dup 3)))] | |
1216 | "" | |
1217 | "%0 = (A0 += A1)%!" | |
1218 | [(set_attr "type" "dsp32")]) | |
1219 | ||
314f9913 BS |
1220 | (define_insn "us_truncpdisi2" |
1221 | [(set (match_operand:SI 0 "register_operand" "=D,W") | |
1222 | (us_truncate:SI (match_operand:PDI 1 "register_operand" "A,B")))] | |
1223 | "" | |
1224 | "%0 = %1 (FU)%!" | |
1225 | [(set_attr "type" "dsp32")]) | |
1226 | ||
0d4a78eb BS |
1227 | ;; Bit test instructions |
1228 | ||
1229 | (define_insn "*not_bittst" | |
4729dc92 | 1230 | [(set (match_operand:BI 0 "register_operand" "=C") |
0d4a78eb BS |
1231 | (eq:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d") |
1232 | (const_int 1) | |
1233 | (match_operand:SI 2 "immediate_operand" "Ku5")) | |
1234 | (const_int 0)))] | |
1235 | "" | |
1236 | "cc = !BITTST (%1,%2);" | |
1237 | [(set_attr "type" "alu0")]) | |
1238 | ||
1239 | (define_insn "*bittst" | |
4729dc92 | 1240 | [(set (match_operand:BI 0 "register_operand" "=C") |
0d4a78eb BS |
1241 | (ne:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d") |
1242 | (const_int 1) | |
1243 | (match_operand:SI 2 "immediate_operand" "Ku5")) | |
1244 | (const_int 0)))] | |
1245 | "" | |
1246 | "cc = BITTST (%1,%2);" | |
1247 | [(set_attr "type" "alu0")]) | |
1248 | ||
1249 | (define_insn_and_split "*bit_extract" | |
1250 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1251 | (zero_extract:SI (match_operand:SI 1 "register_operand" "d") | |
1252 | (const_int 1) | |
1253 | (match_operand:SI 2 "immediate_operand" "Ku5"))) | |
1254 | (clobber (reg:BI REG_CC))] | |
1255 | "" | |
1256 | "#" | |
1257 | "" | |
1258 | [(set (reg:BI REG_CC) | |
1259 | (ne:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2)) | |
1260 | (const_int 0))) | |
1261 | (set (match_dup 0) | |
1262 | (ne:SI (reg:BI REG_CC) (const_int 0)))]) | |
1263 | ||
1264 | (define_insn_and_split "*not_bit_extract" | |
1265 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1266 | (zero_extract:SI (not:SI (match_operand:SI 1 "register_operand" "d")) | |
1267 | (const_int 1) | |
1268 | (match_operand:SI 2 "immediate_operand" "Ku5"))) | |
1269 | (clobber (reg:BI REG_CC))] | |
1270 | "" | |
1271 | "#" | |
1272 | "" | |
1273 | [(set (reg:BI REG_CC) | |
1274 | (eq:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2)) | |
1275 | (const_int 0))) | |
1276 | (set (match_dup 0) | |
1277 | (ne:SI (reg:BI REG_CC) (const_int 0)))]) | |
1278 | ||
1279 | (define_insn "*andsi_insn" | |
1280 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") | |
1281 | (and:SI (match_operand:SI 1 "register_operand" "%0,d,d,d") | |
1282 | (match_operand:SI 2 "rhs_andsi3_operand" "L,M1,M2,d")))] | |
1283 | "" | |
1284 | "@ | |
1285 | BITCLR (%0,%Y2); | |
1286 | %0 = %T1 (Z); | |
1287 | %0 = %h1 (Z); | |
1288 | %0 = %1 & %2;" | |
1289 | [(set_attr "type" "alu0")]) | |
1290 | ||
1291 | (define_expand "andsi3" | |
1292 | [(set (match_operand:SI 0 "register_operand" "") | |
1293 | (and:SI (match_operand:SI 1 "register_operand" "") | |
1294 | (match_operand:SI 2 "general_operand" "")))] | |
1295 | "" | |
1296 | { | |
1297 | if (highbits_operand (operands[2], SImode)) | |
1298 | { | |
1299 | operands[2] = GEN_INT (exact_log2 (-INTVAL (operands[2]))); | |
1300 | emit_insn (gen_ashrsi3 (operands[0], operands[1], operands[2])); | |
1301 | emit_insn (gen_ashlsi3 (operands[0], operands[0], operands[2])); | |
1302 | DONE; | |
1303 | } | |
1304 | if (! rhs_andsi3_operand (operands[2], SImode)) | |
1305 | operands[2] = force_reg (SImode, operands[2]); | |
1306 | }) | |
1307 | ||
1308 | (define_insn "iorsi3" | |
1309 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1310 | (ior:SI (match_operand:SI 1 "register_operand" "%0,d") | |
1311 | (match_operand:SI 2 "regorlog2_operand" "J,d")))] | |
1312 | "" | |
1313 | "@ | |
1314 | BITSET (%0, %X2); | |
1315 | %0 = %1 | %2;" | |
1316 | [(set_attr "type" "alu0")]) | |
1317 | ||
1318 | (define_insn "xorsi3" | |
1319 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1320 | (xor:SI (match_operand:SI 1 "register_operand" "%0,d") | |
1321 | (match_operand:SI 2 "regorlog2_operand" "J,d")))] | |
1322 | "" | |
1323 | "@ | |
1324 | BITTGL (%0, %X2); | |
1325 | %0 = %1 ^ %2;" | |
1326 | [(set_attr "type" "alu0")]) | |
1327 | ||
1d7d5ac4 BS |
1328 | (define_insn "ones" |
1329 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1330 | (unspec:HI [(match_operand:SI 1 "register_operand" "d")] | |
1331 | UNSPEC_ONES))] | |
1332 | "" | |
1333 | "%h0 = ONES %1;" | |
1334 | [(set_attr "type" "alu0")]) | |
1335 | ||
0d4a78eb BS |
1336 | (define_insn "smaxsi3" |
1337 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1338 | (smax:SI (match_operand:SI 1 "register_operand" "d") | |
1339 | (match_operand:SI 2 "register_operand" "d")))] | |
1340 | "" | |
bbbc206e | 1341 | "%0 = max(%1,%2)%!" |
0d4a78eb BS |
1342 | [(set_attr "type" "dsp32")]) |
1343 | ||
1344 | (define_insn "sminsi3" | |
1345 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1346 | (smin:SI (match_operand:SI 1 "register_operand" "d") | |
1347 | (match_operand:SI 2 "register_operand" "d")))] | |
1348 | "" | |
bbbc206e | 1349 | "%0 = min(%1,%2)%!" |
0d4a78eb BS |
1350 | [(set_attr "type" "dsp32")]) |
1351 | ||
1352 | (define_insn "abssi2" | |
1353 | [(set (match_operand:SI 0 "register_operand" "=d") | |
75d8b2d0 | 1354 | (abs:SI (match_operand:SI 1 "register_operand" "d")))] |
0d4a78eb | 1355 | "" |
bbbc206e | 1356 | "%0 = abs %1%!" |
0d4a78eb BS |
1357 | [(set_attr "type" "dsp32")]) |
1358 | ||
26c5953d BS |
1359 | (define_insn "ssabssi2" |
1360 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1361 | (ss_abs:SI (match_operand:SI 1 "register_operand" "d")))] | |
1362 | "" | |
1363 | "%0 = abs %1%!" | |
1364 | [(set_attr "type" "dsp32")]) | |
1365 | ||
0d4a78eb BS |
1366 | (define_insn "negsi2" |
1367 | [(set (match_operand:SI 0 "register_operand" "=d") | |
75d8b2d0 | 1368 | (neg:SI (match_operand:SI 1 "register_operand" "d")))] |
0d4a78eb | 1369 | "" |
75d8b2d0 | 1370 | "%0 = -%1;" |
0d4a78eb BS |
1371 | [(set_attr "type" "alu0")]) |
1372 | ||
75d8b2d0 BS |
1373 | (define_insn "ssnegsi2" |
1374 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1375 | (ss_neg:SI (match_operand:SI 1 "register_operand" "d")))] | |
1376 | "" | |
bbbc206e | 1377 | "%0 = -%1 (S)%!" |
75d8b2d0 BS |
1378 | [(set_attr "type" "dsp32")]) |
1379 | ||
0d4a78eb BS |
1380 | (define_insn "one_cmplsi2" |
1381 | [(set (match_operand:SI 0 "register_operand" "=d") | |
75d8b2d0 | 1382 | (not:SI (match_operand:SI 1 "register_operand" "d")))] |
0d4a78eb | 1383 | "" |
75d8b2d0 | 1384 | "%0 = ~%1;" |
0d4a78eb BS |
1385 | [(set_attr "type" "alu0")]) |
1386 | ||
75d8b2d0 BS |
1387 | (define_insn "signbitssi2" |
1388 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1389 | (if_then_else:HI | |
1390 | (lt (match_operand:SI 1 "register_operand" "d") (const_int 0)) | |
1391 | (clz:HI (not:SI (match_dup 1))) | |
1392 | (clz:HI (match_dup 1))))] | |
1393 | "" | |
bbbc206e | 1394 | "%h0 = signbits %1%!" |
75d8b2d0 BS |
1395 | [(set_attr "type" "dsp32")]) |
1396 | ||
26c5953d BS |
1397 | (define_insn "ssroundsi2" |
1398 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1399 | (truncate:HI | |
1400 | (lshiftrt:SI (ss_plus:SI (match_operand:SI 1 "register_operand" "d") | |
1401 | (const_int 32768)) | |
1402 | (const_int 16))))] | |
1403 | "" | |
1404 | "%h0 = %1 (RND)%!" | |
1405 | [(set_attr "type" "dsp32")]) | |
1406 | ||
75d8b2d0 BS |
1407 | (define_insn "smaxhi3" |
1408 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1409 | (smax:HI (match_operand:HI 1 "register_operand" "d") | |
1410 | (match_operand:HI 2 "register_operand" "d")))] | |
1411 | "" | |
bbbc206e | 1412 | "%0 = max(%1,%2) (V)%!" |
75d8b2d0 BS |
1413 | [(set_attr "type" "dsp32")]) |
1414 | ||
1415 | (define_insn "sminhi3" | |
1416 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1417 | (smin:HI (match_operand:HI 1 "register_operand" "d") | |
1418 | (match_operand:HI 2 "register_operand" "d")))] | |
1419 | "" | |
bbbc206e | 1420 | "%0 = min(%1,%2) (V)%!" |
75d8b2d0 BS |
1421 | [(set_attr "type" "dsp32")]) |
1422 | ||
1423 | (define_insn "abshi2" | |
1424 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1425 | (abs:HI (match_operand:HI 1 "register_operand" "d")))] | |
1426 | "" | |
bbbc206e | 1427 | "%0 = abs %1 (V)%!" |
75d8b2d0 BS |
1428 | [(set_attr "type" "dsp32")]) |
1429 | ||
1430 | (define_insn "neghi2" | |
1431 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1432 | (neg:HI (match_operand:HI 1 "register_operand" "d")))] | |
1433 | "" | |
1434 | "%0 = -%1;" | |
bbbc206e | 1435 | [(set_attr "type" "alu0")]) |
75d8b2d0 BS |
1436 | |
1437 | (define_insn "ssneghi2" | |
1438 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1439 | (ss_neg:HI (match_operand:HI 1 "register_operand" "d")))] | |
1440 | "" | |
bbbc206e | 1441 | "%0 = -%1 (V)%!" |
75d8b2d0 BS |
1442 | [(set_attr "type" "dsp32")]) |
1443 | ||
1444 | (define_insn "signbitshi2" | |
1445 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1446 | (if_then_else:HI | |
1447 | (lt (match_operand:HI 1 "register_operand" "d") (const_int 0)) | |
1448 | (clz:HI (not:HI (match_dup 1))) | |
1449 | (clz:HI (match_dup 1))))] | |
1450 | "" | |
bbbc206e | 1451 | "%h0 = signbits %h1%!" |
75d8b2d0 BS |
1452 | [(set_attr "type" "dsp32")]) |
1453 | ||
0d4a78eb BS |
1454 | (define_insn "mulsi3" |
1455 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1456 | (mult:SI (match_operand:SI 1 "register_operand" "%0") | |
1457 | (match_operand:SI 2 "register_operand" "d")))] | |
1458 | "" | |
75d8b2d0 | 1459 | "%0 *= %2;" |
0d4a78eb BS |
1460 | [(set_attr "type" "mult")]) |
1461 | ||
01e7cd6e | 1462 | (define_expand "umulsi3_highpart" |
3fbee523 BS |
1463 | [(parallel |
1464 | [(set (match_operand:SI 0 "register_operand" "") | |
1465 | (truncate:SI | |
1466 | (lshiftrt:DI | |
1467 | (mult:DI (zero_extend:DI | |
1468 | (match_operand:SI 1 "nonimmediate_operand" "")) | |
1469 | (zero_extend:DI | |
1470 | (match_operand:SI 2 "register_operand" ""))) | |
1471 | (const_int 32)))) | |
1472 | (clobber (reg:PDI REG_A0)) | |
1473 | (clobber (reg:PDI REG_A1))])] | |
01e7cd6e BS |
1474 | "" |
1475 | { | |
3fbee523 BS |
1476 | if (!optimize_size) |
1477 | { | |
1478 | rtx a1reg = gen_rtx_REG (PDImode, REG_A1); | |
1479 | rtx a0reg = gen_rtx_REG (PDImode, REG_A0); | |
1480 | emit_insn (gen_flag_macinit1hi (a1reg, | |
1481 | gen_lowpart (HImode, operands[1]), | |
1482 | gen_lowpart (HImode, operands[2]), | |
1483 | GEN_INT (MACFLAG_FU))); | |
1484 | emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16))); | |
1485 | emit_insn (gen_flag_mul_macv2hi_parts_acconly (a0reg, a1reg, | |
1486 | gen_lowpart (V2HImode, operands[1]), | |
1487 | gen_lowpart (V2HImode, operands[2]), | |
1488 | const1_rtx, const1_rtx, | |
1489 | const1_rtx, const0_rtx, a1reg, | |
1490 | const0_rtx, GEN_INT (MACFLAG_FU), | |
1491 | GEN_INT (MACFLAG_FU))); | |
1492 | emit_insn (gen_flag_machi_parts_acconly (a1reg, | |
1493 | gen_lowpart (V2HImode, operands[2]), | |
1494 | gen_lowpart (V2HImode, operands[1]), | |
1495 | const1_rtx, const0_rtx, | |
1496 | a1reg, const0_rtx, GEN_INT (MACFLAG_FU))); | |
1497 | emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16))); | |
314f9913 BS |
1498 | emit_insn (gen_addpdi3 (a0reg, a0reg, a1reg)); |
1499 | emit_insn (gen_us_truncpdisi2 (operands[0], a0reg)); | |
3fbee523 BS |
1500 | } |
1501 | else | |
1502 | { | |
1503 | rtx umulsi3_highpart_libfunc | |
1504 | = init_one_libfunc ("__umulsi3_highpart"); | |
01e7cd6e | 1505 | |
3fbee523 BS |
1506 | emit_library_call_value (umulsi3_highpart_libfunc, |
1507 | operands[0], LCT_NORMAL, SImode, | |
1508 | 2, operands[1], SImode, operands[2], SImode); | |
1509 | } | |
01e7cd6e BS |
1510 | DONE; |
1511 | }) | |
1512 | ||
1513 | (define_expand "smulsi3_highpart" | |
3fbee523 BS |
1514 | [(parallel |
1515 | [(set (match_operand:SI 0 "register_operand" "") | |
1516 | (truncate:SI | |
1517 | (lshiftrt:DI | |
1518 | (mult:DI (sign_extend:DI | |
1519 | (match_operand:SI 1 "nonimmediate_operand" "")) | |
1520 | (sign_extend:DI | |
1521 | (match_operand:SI 2 "register_operand" ""))) | |
1522 | (const_int 32)))) | |
1523 | (clobber (reg:PDI REG_A0)) | |
1524 | (clobber (reg:PDI REG_A1))])] | |
01e7cd6e BS |
1525 | "" |
1526 | { | |
3fbee523 BS |
1527 | if (!optimize_size) |
1528 | { | |
1529 | rtx a1reg = gen_rtx_REG (PDImode, REG_A1); | |
1530 | rtx a0reg = gen_rtx_REG (PDImode, REG_A0); | |
1531 | emit_insn (gen_flag_macinit1hi (a1reg, | |
1532 | gen_lowpart (HImode, operands[1]), | |
1533 | gen_lowpart (HImode, operands[2]), | |
1534 | GEN_INT (MACFLAG_FU))); | |
1535 | emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16))); | |
1536 | emit_insn (gen_flag_mul_macv2hi_parts_acconly (a0reg, a1reg, | |
1537 | gen_lowpart (V2HImode, operands[1]), | |
1538 | gen_lowpart (V2HImode, operands[2]), | |
1539 | const1_rtx, const1_rtx, | |
1540 | const1_rtx, const0_rtx, a1reg, | |
1541 | const0_rtx, GEN_INT (MACFLAG_IS), | |
1542 | GEN_INT (MACFLAG_IS_M))); | |
1543 | emit_insn (gen_flag_machi_parts_acconly (a1reg, | |
1544 | gen_lowpart (V2HImode, operands[2]), | |
1545 | gen_lowpart (V2HImode, operands[1]), | |
1546 | const1_rtx, const0_rtx, | |
1547 | a1reg, const0_rtx, GEN_INT (MACFLAG_IS_M))); | |
1548 | emit_insn (gen_ashrpdi3 (a1reg, a1reg, GEN_INT (16))); | |
1549 | emit_insn (gen_sum_of_accumulators (operands[0], a0reg, a0reg, a1reg)); | |
1550 | } | |
1551 | else | |
1552 | { | |
1553 | rtx smulsi3_highpart_libfunc | |
1554 | = init_one_libfunc ("__smulsi3_highpart"); | |
01e7cd6e | 1555 | |
3fbee523 BS |
1556 | emit_library_call_value (smulsi3_highpart_libfunc, |
1557 | operands[0], LCT_NORMAL, SImode, | |
1558 | 2, operands[1], SImode, operands[2], SImode); | |
1559 | } | |
01e7cd6e BS |
1560 | DONE; |
1561 | }) | |
1562 | ||
0d4a78eb BS |
1563 | (define_expand "ashlsi3" |
1564 | [(set (match_operand:SI 0 "register_operand" "") | |
1565 | (ashift:SI (match_operand:SI 1 "register_operand" "") | |
1566 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
1567 | "" | |
1568 | { | |
1569 | if (GET_CODE (operands[2]) == CONST_INT | |
1570 | && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) | |
1571 | { | |
1572 | emit_insn (gen_movsi (operands[0], const0_rtx)); | |
1573 | DONE; | |
1574 | } | |
1575 | }) | |
1576 | ||
1577 | (define_insn_and_split "*ashlsi3_insn" | |
bbbc206e BS |
1578 | [(set (match_operand:SI 0 "register_operand" "=d,d,a,a,a") |
1579 | (ashift:SI (match_operand:SI 1 "register_operand" "0,d,a,a,a") | |
1580 | (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5,P1,P2,?P3P4")))] | |
0d4a78eb BS |
1581 | "" |
1582 | "@ | |
1583 | %0 <<= %2; | |
bbbc206e | 1584 | %0 = %1 << %2%! |
0d4a78eb BS |
1585 | %0 = %1 + %1; |
1586 | %0 = %1 << %2; | |
1587 | #" | |
1588 | "PREG_P (operands[0]) && INTVAL (operands[2]) > 2" | |
1589 | [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 2))) | |
1590 | (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))] | |
1591 | "operands[3] = GEN_INT (INTVAL (operands[2]) - 2);" | |
bbbc206e | 1592 | [(set_attr "type" "shft,dsp32,shft,shft,*")]) |
0d4a78eb BS |
1593 | |
1594 | (define_insn "ashrsi3" | |
bbbc206e BS |
1595 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
1596 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d") | |
1597 | (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5")))] | |
0d4a78eb | 1598 | "" |
bbbc206e BS |
1599 | "@ |
1600 | %0 >>>= %2; | |
1601 | %0 = %1 >>> %2%!" | |
1602 | [(set_attr "type" "shft,dsp32")]) | |
0d4a78eb | 1603 | |
97130915 BS |
1604 | (define_insn "rotl16" |
1605 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1606 | (rotate:SI (match_operand:SI 1 "register_operand" "d") | |
1607 | (const_int 16)))] | |
1608 | "" | |
1609 | "%0 = PACK (%h1, %d1)%!" | |
1610 | [(set_attr "type" "dsp32")]) | |
1611 | ||
1612 | (define_expand "rotlsi3" | |
1613 | [(set (match_operand:SI 0 "register_operand" "") | |
1614 | (rotate:SI (match_operand:SI 1 "register_operand" "") | |
1615 | (match_operand:SI 2 "immediate_operand" "")))] | |
1616 | "" | |
1617 | { | |
1618 | if (INTVAL (operands[2]) != 16) | |
1619 | FAIL; | |
1620 | }) | |
1621 | ||
1622 | (define_expand "rotrsi3" | |
1623 | [(set (match_operand:SI 0 "register_operand" "") | |
1624 | (rotatert:SI (match_operand:SI 1 "register_operand" "") | |
1625 | (match_operand:SI 2 "immediate_operand" "")))] | |
1626 | "" | |
1627 | { | |
1628 | if (INTVAL (operands[2]) != 16) | |
1629 | FAIL; | |
1630 | emit_insn (gen_rotl16 (operands[0], operands[1])); | |
1631 | DONE; | |
1632 | }) | |
1633 | ||
1634 | ||
49373252 BS |
1635 | (define_insn "ror_one" |
1636 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1637 | (ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") (const_int 1)) | |
1638 | (ashift:SI (zero_extend:SI (reg:BI REG_CC)) (const_int 31)))) | |
1639 | (set (reg:BI REG_CC) | |
1640 | (zero_extract:BI (match_dup 1) (const_int 1) (const_int 0)))] | |
1641 | "" | |
bbbc206e BS |
1642 | "%0 = ROT %1 BY -1%!" |
1643 | [(set_attr "type" "dsp32")]) | |
49373252 BS |
1644 | |
1645 | (define_insn "rol_one" | |
1646 | [(set (match_operand:SI 0 "register_operand" "+d") | |
1647 | (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") (const_int 1)) | |
1648 | (zero_extend:SI (reg:BI REG_CC)))) | |
1649 | (set (reg:BI REG_CC) | |
1650 | (zero_extract:BI (match_dup 1) (const_int 31) (const_int 0)))] | |
1651 | "" | |
bbbc206e BS |
1652 | "%0 = ROT %1 BY 1%!" |
1653 | [(set_attr "type" "dsp32")]) | |
49373252 BS |
1654 | |
1655 | (define_expand "lshrdi3" | |
1656 | [(set (match_operand:DI 0 "register_operand" "") | |
1657 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
1658 | (match_operand:DI 2 "general_operand" "")))] | |
1659 | "" | |
1660 | { | |
1661 | rtx lo_half[2], hi_half[2]; | |
1662 | ||
1663 | if (operands[2] != const1_rtx) | |
1664 | FAIL; | |
1665 | if (! rtx_equal_p (operands[0], operands[1])) | |
1666 | emit_move_insn (operands[0], operands[1]); | |
1667 | ||
1668 | split_di (operands, 2, lo_half, hi_half); | |
1669 | ||
1670 | emit_move_insn (bfin_cc_rtx, const0_rtx); | |
1671 | emit_insn (gen_ror_one (hi_half[0], hi_half[0])); | |
1672 | emit_insn (gen_ror_one (lo_half[0], lo_half[0])); | |
1673 | DONE; | |
1674 | }) | |
1675 | ||
1676 | (define_expand "ashrdi3" | |
1677 | [(set (match_operand:DI 0 "register_operand" "") | |
1678 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
1679 | (match_operand:DI 2 "general_operand" "")))] | |
1680 | "" | |
1681 | { | |
1682 | rtx lo_half[2], hi_half[2]; | |
1683 | ||
1684 | if (operands[2] != const1_rtx) | |
1685 | FAIL; | |
1686 | if (! rtx_equal_p (operands[0], operands[1])) | |
1687 | emit_move_insn (operands[0], operands[1]); | |
1688 | ||
1689 | split_di (operands, 2, lo_half, hi_half); | |
1690 | ||
1691 | emit_insn (gen_compare_lt (gen_rtx_REG (BImode, REG_CC), | |
1692 | hi_half[1], const0_rtx)); | |
1693 | emit_insn (gen_ror_one (hi_half[0], hi_half[0])); | |
1694 | emit_insn (gen_ror_one (lo_half[0], lo_half[0])); | |
1695 | DONE; | |
1696 | }) | |
1697 | ||
1698 | (define_expand "ashldi3" | |
1699 | [(set (match_operand:DI 0 "register_operand" "") | |
1700 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
1701 | (match_operand:DI 2 "general_operand" "")))] | |
1702 | "" | |
1703 | { | |
1704 | rtx lo_half[2], hi_half[2]; | |
1705 | ||
1706 | if (operands[2] != const1_rtx) | |
1707 | FAIL; | |
1708 | if (! rtx_equal_p (operands[0], operands[1])) | |
1709 | emit_move_insn (operands[0], operands[1]); | |
1710 | ||
1711 | split_di (operands, 2, lo_half, hi_half); | |
1712 | ||
1713 | emit_move_insn (bfin_cc_rtx, const0_rtx); | |
1714 | emit_insn (gen_rol_one (lo_half[0], lo_half[0])); | |
1715 | emit_insn (gen_rol_one (hi_half[0], hi_half[0])); | |
1716 | DONE; | |
1717 | }) | |
1718 | ||
0d4a78eb | 1719 | (define_insn "lshrsi3" |
bbbc206e BS |
1720 | [(set (match_operand:SI 0 "register_operand" "=d,d,a") |
1721 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,d,a") | |
1722 | (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5,P1P2")))] | |
0d4a78eb BS |
1723 | "" |
1724 | "@ | |
1725 | %0 >>= %2; | |
bbbc206e | 1726 | %0 = %1 >> %2%! |
0d4a78eb | 1727 | %0 = %1 >> %2;" |
bbbc206e | 1728 | [(set_attr "type" "shft,dsp32,shft")]) |
0d4a78eb | 1729 | |
3efd5670 BS |
1730 | (define_insn "lshrpdi3" |
1731 | [(set (match_operand:PDI 0 "register_operand" "=e") | |
1732 | (lshiftrt:PDI (match_operand:PDI 1 "register_operand" "0") | |
1733 | (match_operand:SI 2 "nonmemory_operand" "Ku5")))] | |
1734 | "" | |
1735 | "%0 = %1 >> %2%!" | |
1736 | [(set_attr "type" "dsp32")]) | |
1737 | ||
1738 | (define_insn "ashrpdi3" | |
1739 | [(set (match_operand:PDI 0 "register_operand" "=e") | |
1740 | (ashiftrt:PDI (match_operand:PDI 1 "register_operand" "0") | |
1741 | (match_operand:SI 2 "nonmemory_operand" "Ku5")))] | |
1742 | "" | |
1743 | "%0 = %1 >>> %2%!" | |
1744 | [(set_attr "type" "dsp32")]) | |
1745 | ||
0d4a78eb BS |
1746 | ;; A pattern to reload the equivalent of |
1747 | ;; (set (Dreg) (plus (FP) (large_constant))) | |
1748 | ;; or | |
1749 | ;; (set (dagreg) (plus (FP) (arbitrary_constant))) | |
1750 | ;; using a scratch register | |
1751 | (define_expand "reload_insi" | |
1752 | [(parallel [(set (match_operand:SI 0 "register_operand" "=w") | |
1753 | (match_operand:SI 1 "fp_plus_const_operand" "")) | |
1754 | (clobber (match_operand:SI 2 "register_operand" "=&a"))])] | |
1755 | "" | |
1756 | { | |
1757 | rtx fp_op = XEXP (operands[1], 0); | |
1758 | rtx const_op = XEXP (operands[1], 1); | |
1759 | rtx primary = operands[0]; | |
1760 | rtx scratch = operands[2]; | |
1761 | ||
1762 | emit_move_insn (scratch, const_op); | |
1763 | emit_insn (gen_addsi3 (scratch, scratch, fp_op)); | |
1764 | emit_move_insn (primary, scratch); | |
1765 | DONE; | |
1766 | }) | |
1767 | ||
6ed44ca1 BS |
1768 | (define_insn "reload_inpdi" |
1769 | [(set (match_operand:PDI 0 "register_operand" "=e") | |
1770 | (match_operand:PDI 1 "memory_operand" "m")) | |
1771 | (clobber (match_operand:SI 2 "register_operand" "=d"))] | |
1772 | "" | |
1773 | { | |
1774 | rtx xops[4]; | |
1775 | xops[0] = operands[0]; | |
1776 | xops[1] = operands[2]; | |
1777 | split_di (operands + 1, 1, xops + 2, xops + 3); | |
1778 | output_asm_insn ("%1 = %2;", xops); | |
1779 | output_asm_insn ("%w0 = %1;", xops); | |
1780 | output_asm_insn ("%1 = %3;", xops); | |
1781 | output_asm_insn ("%x0 = %1;", xops); | |
1782 | return ""; | |
1783 | } | |
1784 | [(set_attr "seq_insns" "multi") | |
1785 | (set_attr "type" "mcld") | |
1786 | (set_attr "length" "12")]) | |
1787 | ||
1788 | (define_insn "reload_outpdi" | |
1789 | [(set (match_operand:PDI 0 "memory_operand" "=m") | |
1790 | (match_operand:PDI 1 "register_operand" "e")) | |
1791 | (clobber (match_operand:SI 2 "register_operand" "=d"))] | |
1792 | "" | |
1793 | { | |
1794 | rtx xops[4]; | |
1795 | xops[0] = operands[1]; | |
1796 | xops[1] = operands[2]; | |
1797 | split_di (operands, 1, xops + 2, xops + 3); | |
1798 | output_asm_insn ("%1 = %w0;", xops); | |
1799 | output_asm_insn ("%2 = %1;", xops); | |
1800 | output_asm_insn ("%1 = %x0;", xops); | |
1801 | output_asm_insn ("%3 = %1;", xops); | |
1802 | return ""; | |
1803 | } | |
1804 | [(set_attr "seq_insns" "multi") | |
1805 | (set_attr "type" "mcld") | |
1806 | (set_attr "length" "12")]) | |
1807 | ||
0d4a78eb BS |
1808 | ;; Jump instructions |
1809 | ||
1810 | (define_insn "jump" | |
1811 | [(set (pc) | |
1812 | (label_ref (match_operand 0 "" "")))] | |
1813 | "" | |
1814 | { | |
1815 | if (get_attr_length (insn) == 2) | |
1816 | return "jump.s %0;"; | |
1817 | else | |
1818 | return "jump.l %0;"; | |
1819 | } | |
1820 | [(set_attr "type" "br")]) | |
1821 | ||
1822 | (define_insn "indirect_jump" | |
1823 | [(set (pc) | |
1824 | (match_operand:SI 0 "register_operand" "a"))] | |
1825 | "" | |
1826 | "jump (%0);" | |
1827 | [(set_attr "type" "misc")]) | |
1828 | ||
1829 | (define_expand "tablejump" | |
1830 | [(parallel [(set (pc) (match_operand:SI 0 "register_operand" "a")) | |
1831 | (use (label_ref (match_operand 1 "" "")))])] | |
1832 | "" | |
1833 | { | |
1834 | /* In PIC mode, the table entries are stored PC relative. | |
1835 | Convert the relative address to an absolute address. */ | |
1836 | if (flag_pic) | |
1837 | { | |
1838 | rtx op1 = gen_rtx_LABEL_REF (Pmode, operands[1]); | |
1839 | ||
1840 | operands[0] = expand_simple_binop (Pmode, PLUS, operands[0], | |
1841 | op1, NULL_RTX, 0, OPTAB_DIRECT); | |
1842 | } | |
1843 | }) | |
1844 | ||
1845 | (define_insn "*tablejump_internal" | |
1846 | [(set (pc) (match_operand:SI 0 "register_operand" "a")) | |
1847 | (use (label_ref (match_operand 1 "" "")))] | |
1848 | "" | |
1849 | "jump (%0);" | |
1850 | [(set_attr "type" "misc")]) | |
1851 | ||
b03149e1 JZ |
1852 | ;; Hardware loop |
1853 | ||
1854 | ; operand 0 is the loop count pseudo register | |
1855 | ; operand 1 is the number of loop iterations or 0 if it is unknown | |
1856 | ; operand 2 is the maximum number of loop iterations | |
1857 | ; operand 3 is the number of levels of enclosed loops | |
1858 | ; operand 4 is the label to jump to at the top of the loop | |
1859 | (define_expand "doloop_end" | |
1860 | [(parallel [(set (pc) (if_then_else | |
1861 | (ne (match_operand:SI 0 "" "") | |
1862 | (const_int 1)) | |
1863 | (label_ref (match_operand 4 "" "")) | |
1864 | (pc))) | |
1865 | (set (match_dup 0) | |
1866 | (plus:SI (match_dup 0) | |
1867 | (const_int -1))) | |
1868 | (unspec [(const_int 0)] UNSPEC_LSETUP_END) | |
1869 | (clobber (match_scratch:SI 5 ""))])] | |
1870 | "" | |
0a8f8c45 | 1871 | { |
9b02a95e BS |
1872 | /* The loop optimizer doesn't check the predicates... */ |
1873 | if (GET_MODE (operands[0]) != SImode) | |
1874 | FAIL; | |
0a8f8c45 BS |
1875 | /* Due to limitations in the hardware (an initial loop count of 0 |
1876 | does not loop 2^32 times) we must avoid to generate a hardware | |
1877 | loops when we cannot rule out this case. */ | |
0a8f8c45 BS |
1878 | if (!flag_unsafe_loop_optimizations |
1879 | && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 0xFFFFFFFF) | |
1880 | FAIL; | |
1881 | bfin_hardware_loop (); | |
1882 | }) | |
b03149e1 JZ |
1883 | |
1884 | (define_insn "loop_end" | |
1885 | [(set (pc) | |
a9c46998 | 1886 | (if_then_else (ne (match_operand:SI 0 "nonimmediate_operand" "+a*d,*b*v*f,m") |
b03149e1 JZ |
1887 | (const_int 1)) |
1888 | (label_ref (match_operand 1 "" "")) | |
1889 | (pc))) | |
1890 | (set (match_dup 0) | |
1891 | (plus (match_dup 0) | |
1892 | (const_int -1))) | |
1893 | (unspec [(const_int 0)] UNSPEC_LSETUP_END) | |
1894 | (clobber (match_scratch:SI 2 "=X,&r,&r"))] | |
1895 | "" | |
1896 | "@ | |
1897 | /* loop end %0 %l1 */ | |
1898 | # | |
1899 | #" | |
1900 | [(set_attr "length" "6,10,14")]) | |
1901 | ||
1902 | (define_split | |
1903 | [(set (pc) | |
1904 | (if_then_else (ne (match_operand:SI 0 "nondp_reg_or_memory_operand" "") | |
1905 | (const_int 1)) | |
1906 | (label_ref (match_operand 1 "" "")) | |
1907 | (pc))) | |
1908 | (set (match_dup 0) | |
1909 | (plus (match_dup 0) | |
1910 | (const_int -1))) | |
1911 | (unspec [(const_int 0)] UNSPEC_LSETUP_END) | |
1912 | (clobber (match_scratch:SI 2 "=&r"))] | |
97a988bc | 1913 | "splitting_loops" |
b03149e1 JZ |
1914 | [(set (match_dup 2) (match_dup 0)) |
1915 | (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
1916 | (set (match_dup 0) (match_dup 2)) | |
1917 | (set (reg:BI REG_CC) (eq:BI (match_dup 2) (const_int 0))) | |
1918 | (set (pc) | |
1919 | (if_then_else (eq (reg:BI REG_CC) | |
1920 | (const_int 0)) | |
1921 | (label_ref (match_dup 1)) | |
1922 | (pc)))] | |
1923 | "") | |
1924 | ||
1925 | (define_insn "lsetup_with_autoinit" | |
1926 | [(set (match_operand:SI 0 "lt_register_operand" "=t") | |
1927 | (label_ref (match_operand 1 "" ""))) | |
a9c46998 | 1928 | (set (match_operand:SI 2 "lb_register_operand" "=u") |
b03149e1 JZ |
1929 | (label_ref (match_operand 3 "" ""))) |
1930 | (set (match_operand:SI 4 "lc_register_operand" "=k") | |
1931 | (match_operand:SI 5 "register_operand" "a"))] | |
1932 | "" | |
1933 | "LSETUP (%1, %3) %4 = %5;" | |
1934 | [(set_attr "length" "4")]) | |
1935 | ||
1936 | (define_insn "lsetup_without_autoinit" | |
1937 | [(set (match_operand:SI 0 "lt_register_operand" "=t") | |
1938 | (label_ref (match_operand 1 "" ""))) | |
a9c46998 | 1939 | (set (match_operand:SI 2 "lb_register_operand" "=u") |
b03149e1 JZ |
1940 | (label_ref (match_operand 3 "" ""))) |
1941 | (use (match_operand:SI 4 "lc_register_operand" "k"))] | |
1942 | "" | |
1943 | "LSETUP (%1, %3) %4;" | |
1944 | [(set_attr "length" "4")]) | |
1945 | ||
0d4a78eb BS |
1946 | ;; Call instructions.. |
1947 | ||
6614f9f5 BS |
1948 | ;; The explicit MEM inside the UNSPEC prevents the compiler from moving |
1949 | ;; the load before a branch after a NULL test, or before a store that | |
1950 | ;; initializes a function descriptor. | |
1951 | ||
1952 | (define_insn_and_split "load_funcdescsi" | |
1953 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1954 | (unspec_volatile:SI [(mem:SI (match_operand:SI 1 "address_operand" "p"))] | |
1955 | UNSPEC_VOLATILE_LOAD_FUNCDESC))] | |
1956 | "" | |
1957 | "#" | |
1958 | "reload_completed" | |
1959 | [(set (match_dup 0) (mem:SI (match_dup 1)))]) | |
1960 | ||
0d4a78eb | 1961 | (define_expand "call" |
6d459e2b BS |
1962 | [(parallel [(call (match_operand:SI 0 "" "") |
1963 | (match_operand 1 "" "")) | |
1964 | (use (match_operand 2 "" ""))])] | |
0d4a78eb | 1965 | "" |
6d459e2b BS |
1966 | { |
1967 | bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 0); | |
1968 | DONE; | |
1969 | }) | |
0d4a78eb BS |
1970 | |
1971 | (define_expand "sibcall" | |
1972 | [(parallel [(call (match_operand:SI 0 "" "") | |
1973 | (match_operand 1 "" "")) | |
6d459e2b | 1974 | (use (match_operand 2 "" "")) |
0d4a78eb BS |
1975 | (return)])] |
1976 | "" | |
6d459e2b BS |
1977 | { |
1978 | bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 1); | |
1979 | DONE; | |
1980 | }) | |
0d4a78eb BS |
1981 | |
1982 | (define_expand "call_value" | |
6d459e2b BS |
1983 | [(parallel [(set (match_operand 0 "register_operand" "") |
1984 | (call (match_operand:SI 1 "" "") | |
1985 | (match_operand 2 "" ""))) | |
1986 | (use (match_operand 3 "" ""))])] | |
0d4a78eb | 1987 | "" |
6d459e2b BS |
1988 | { |
1989 | bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 0); | |
1990 | DONE; | |
1991 | }) | |
0d4a78eb BS |
1992 | |
1993 | (define_expand "sibcall_value" | |
1994 | [(parallel [(set (match_operand 0 "register_operand" "") | |
1995 | (call (match_operand:SI 1 "" "") | |
1996 | (match_operand 2 "" ""))) | |
6d459e2b | 1997 | (use (match_operand 3 "" "")) |
0d4a78eb BS |
1998 | (return)])] |
1999 | "" | |
6d459e2b BS |
2000 | { |
2001 | bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 1); | |
2002 | DONE; | |
2003 | }) | |
0d4a78eb | 2004 | |
6614f9f5 BS |
2005 | (define_insn "*call_symbol_fdpic" |
2006 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q")) | |
2007 | (match_operand 1 "general_operand" "g")) | |
2008 | (use (match_operand:SI 2 "register_operand" "Z")) | |
2009 | (use (match_operand 3 "" ""))] | |
2010 | "! SIBLING_CALL_P (insn) | |
2011 | && GET_CODE (operands[0]) == SYMBOL_REF | |
2012 | && !bfin_longcall_p (operands[0], INTVAL (operands[3]))" | |
2013 | "call %0;" | |
2014 | [(set_attr "type" "call") | |
2015 | (set_attr "length" "4")]) | |
2016 | ||
2017 | (define_insn "*sibcall_symbol_fdpic" | |
2018 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q")) | |
2019 | (match_operand 1 "general_operand" "g")) | |
2020 | (use (match_operand:SI 2 "register_operand" "Z")) | |
2021 | (use (match_operand 3 "" "")) | |
2022 | (return)] | |
2023 | "SIBLING_CALL_P (insn) | |
2024 | && GET_CODE (operands[0]) == SYMBOL_REF | |
2025 | && !bfin_longcall_p (operands[0], INTVAL (operands[3]))" | |
2026 | "jump.l %0;" | |
2027 | [(set_attr "type" "br") | |
2028 | (set_attr "length" "4")]) | |
2029 | ||
2030 | (define_insn "*call_value_symbol_fdpic" | |
2031 | [(set (match_operand 0 "register_operand" "=d") | |
2032 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q")) | |
2033 | (match_operand 2 "general_operand" "g"))) | |
2034 | (use (match_operand:SI 3 "register_operand" "Z")) | |
2035 | (use (match_operand 4 "" ""))] | |
2036 | "! SIBLING_CALL_P (insn) | |
2037 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2038 | && !bfin_longcall_p (operands[1], INTVAL (operands[4]))" | |
2039 | "call %1;" | |
2040 | [(set_attr "type" "call") | |
2041 | (set_attr "length" "4")]) | |
2042 | ||
2043 | (define_insn "*sibcall_value_symbol_fdpic" | |
2044 | [(set (match_operand 0 "register_operand" "=d") | |
2045 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q")) | |
2046 | (match_operand 2 "general_operand" "g"))) | |
2047 | (use (match_operand:SI 3 "register_operand" "Z")) | |
2048 | (use (match_operand 4 "" "")) | |
2049 | (return)] | |
2050 | "SIBLING_CALL_P (insn) | |
2051 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2052 | && !bfin_longcall_p (operands[1], INTVAL (operands[4]))" | |
2053 | "jump.l %1;" | |
2054 | [(set_attr "type" "br") | |
2055 | (set_attr "length" "4")]) | |
2056 | ||
2057 | (define_insn "*call_insn_fdpic" | |
2058 | [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y")) | |
2059 | (match_operand 1 "general_operand" "g")) | |
2060 | (use (match_operand:SI 2 "register_operand" "Z")) | |
2061 | (use (match_operand 3 "" ""))] | |
2062 | "! SIBLING_CALL_P (insn)" | |
2063 | "call (%0);" | |
2064 | [(set_attr "type" "call") | |
2065 | (set_attr "length" "2")]) | |
2066 | ||
2067 | (define_insn "*sibcall_insn_fdpic" | |
2068 | [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y")) | |
2069 | (match_operand 1 "general_operand" "g")) | |
2070 | (use (match_operand:SI 2 "register_operand" "Z")) | |
2071 | (use (match_operand 3 "" "")) | |
2072 | (return)] | |
2073 | "SIBLING_CALL_P (insn)" | |
2074 | "jump (%0);" | |
2075 | [(set_attr "type" "br") | |
2076 | (set_attr "length" "2")]) | |
2077 | ||
2078 | (define_insn "*call_value_insn_fdpic" | |
2079 | [(set (match_operand 0 "register_operand" "=d") | |
2080 | (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y")) | |
2081 | (match_operand 2 "general_operand" "g"))) | |
2082 | (use (match_operand:SI 3 "register_operand" "Z")) | |
2083 | (use (match_operand 4 "" ""))] | |
2084 | "! SIBLING_CALL_P (insn)" | |
2085 | "call (%1);" | |
2086 | [(set_attr "type" "call") | |
2087 | (set_attr "length" "2")]) | |
2088 | ||
2089 | (define_insn "*sibcall_value_insn_fdpic" | |
2090 | [(set (match_operand 0 "register_operand" "=d") | |
2091 | (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y")) | |
2092 | (match_operand 2 "general_operand" "g"))) | |
2093 | (use (match_operand:SI 3 "register_operand" "Z")) | |
2094 | (use (match_operand 4 "" "")) | |
2095 | (return)] | |
2096 | "SIBLING_CALL_P (insn)" | |
2097 | "jump (%1);" | |
2098 | [(set_attr "type" "br") | |
2099 | (set_attr "length" "2")]) | |
2100 | ||
6d459e2b BS |
2101 | (define_insn "*call_symbol" |
2102 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q")) | |
2103 | (match_operand 1 "general_operand" "g")) | |
2104 | (use (match_operand 2 "" ""))] | |
0d4a78eb | 2105 | "! SIBLING_CALL_P (insn) |
93147119 | 2106 | && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY) |
6d459e2b BS |
2107 | && GET_CODE (operands[0]) == SYMBOL_REF |
2108 | && !bfin_longcall_p (operands[0], INTVAL (operands[2]))" | |
96c30d2a | 2109 | "call %0;" |
0d4a78eb | 2110 | [(set_attr "type" "call") |
6d459e2b | 2111 | (set_attr "length" "4")]) |
0d4a78eb | 2112 | |
6d459e2b BS |
2113 | (define_insn "*sibcall_symbol" |
2114 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q")) | |
2115 | (match_operand 1 "general_operand" "g")) | |
2116 | (use (match_operand 2 "" "")) | |
0d4a78eb BS |
2117 | (return)] |
2118 | "SIBLING_CALL_P (insn) | |
93147119 | 2119 | && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY) |
6d459e2b BS |
2120 | && GET_CODE (operands[0]) == SYMBOL_REF |
2121 | && !bfin_longcall_p (operands[0], INTVAL (operands[2]))" | |
96c30d2a | 2122 | "jump.l %0;" |
0d4a78eb | 2123 | [(set_attr "type" "br") |
6d459e2b | 2124 | (set_attr "length" "4")]) |
0d4a78eb | 2125 | |
6d459e2b BS |
2126 | (define_insn "*call_value_symbol" |
2127 | [(set (match_operand 0 "register_operand" "=d") | |
2128 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q")) | |
2129 | (match_operand 2 "general_operand" "g"))) | |
2130 | (use (match_operand 3 "" ""))] | |
0d4a78eb | 2131 | "! SIBLING_CALL_P (insn) |
93147119 | 2132 | && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY) |
6d459e2b BS |
2133 | && GET_CODE (operands[1]) == SYMBOL_REF |
2134 | && !bfin_longcall_p (operands[1], INTVAL (operands[3]))" | |
96c30d2a | 2135 | "call %1;" |
0d4a78eb | 2136 | [(set_attr "type" "call") |
6d459e2b | 2137 | (set_attr "length" "4")]) |
0d4a78eb | 2138 | |
6d459e2b BS |
2139 | (define_insn "*sibcall_value_symbol" |
2140 | [(set (match_operand 0 "register_operand" "=d") | |
2141 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q")) | |
2142 | (match_operand 2 "general_operand" "g"))) | |
2143 | (use (match_operand 3 "" "")) | |
0d4a78eb BS |
2144 | (return)] |
2145 | "SIBLING_CALL_P (insn) | |
93147119 | 2146 | && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY) |
6d459e2b BS |
2147 | && GET_CODE (operands[1]) == SYMBOL_REF |
2148 | && !bfin_longcall_p (operands[1], INTVAL (operands[3]))" | |
96c30d2a | 2149 | "jump.l %1;" |
6d459e2b BS |
2150 | [(set_attr "type" "br") |
2151 | (set_attr "length" "4")]) | |
2152 | ||
2153 | (define_insn "*call_insn" | |
2154 | [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "a")) | |
2155 | (match_operand 1 "general_operand" "g")) | |
2156 | (use (match_operand 2 "" ""))] | |
2157 | "! SIBLING_CALL_P (insn)" | |
2158 | "call (%0);" | |
2159 | [(set_attr "type" "call") | |
2160 | (set_attr "length" "2")]) | |
2161 | ||
2162 | (define_insn "*sibcall_insn" | |
2163 | [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "z")) | |
2164 | (match_operand 1 "general_operand" "g")) | |
2165 | (use (match_operand 2 "" "")) | |
2166 | (return)] | |
2167 | "SIBLING_CALL_P (insn)" | |
2168 | "jump (%0);" | |
2169 | [(set_attr "type" "br") | |
2170 | (set_attr "length" "2")]) | |
2171 | ||
2172 | (define_insn "*call_value_insn" | |
2173 | [(set (match_operand 0 "register_operand" "=d") | |
2174 | (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "a")) | |
2175 | (match_operand 2 "general_operand" "g"))) | |
2176 | (use (match_operand 3 "" ""))] | |
2177 | "! SIBLING_CALL_P (insn)" | |
2178 | "call (%1);" | |
2179 | [(set_attr "type" "call") | |
2180 | (set_attr "length" "2")]) | |
2181 | ||
2182 | (define_insn "*sibcall_value_insn" | |
2183 | [(set (match_operand 0 "register_operand" "=d") | |
2184 | (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "z")) | |
2185 | (match_operand 2 "general_operand" "g"))) | |
2186 | (use (match_operand 3 "" "")) | |
2187 | (return)] | |
2188 | "SIBLING_CALL_P (insn)" | |
2189 | "jump (%1);" | |
0d4a78eb | 2190 | [(set_attr "type" "br") |
6d459e2b | 2191 | (set_attr "length" "2")]) |
0d4a78eb BS |
2192 | |
2193 | ;; Block move patterns | |
2194 | ||
2195 | ;; We cheat. This copies one more word than operand 2 indicates. | |
2196 | ||
2197 | (define_insn "rep_movsi" | |
2198 | [(set (match_operand:SI 0 "register_operand" "=&a") | |
2199 | (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0") | |
2200 | (ashift:SI (match_operand:SI 2 "register_operand" "a") | |
2201 | (const_int 2))) | |
2202 | (const_int 4))) | |
2203 | (set (match_operand:SI 1 "register_operand" "=&b") | |
2204 | (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1") | |
2205 | (ashift:SI (match_dup 2) (const_int 2))) | |
2206 | (const_int 4))) | |
2207 | (set (mem:BLK (match_dup 3)) | |
2208 | (mem:BLK (match_dup 4))) | |
2209 | (use (match_dup 2)) | |
b03149e1 JZ |
2210 | (clobber (match_scratch:HI 5 "=&d")) |
2211 | (clobber (reg:SI REG_LT1)) | |
2212 | (clobber (reg:SI REG_LC1)) | |
2213 | (clobber (reg:SI REG_LB1))] | |
0d4a78eb | 2214 | "" |
51a641fd | 2215 | "%5 = [%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || [%3++] = %5 || %5 = [%4++]; [%3++] = %5;" |
0d4a78eb | 2216 | [(set_attr "type" "misc") |
b03149e1 JZ |
2217 | (set_attr "length" "16") |
2218 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
2219 | |
2220 | (define_insn "rep_movhi" | |
2221 | [(set (match_operand:SI 0 "register_operand" "=&a") | |
2222 | (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0") | |
2223 | (ashift:SI (match_operand:SI 2 "register_operand" "a") | |
2224 | (const_int 1))) | |
2225 | (const_int 2))) | |
2226 | (set (match_operand:SI 1 "register_operand" "=&b") | |
2227 | (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1") | |
2228 | (ashift:SI (match_dup 2) (const_int 1))) | |
2229 | (const_int 2))) | |
2230 | (set (mem:BLK (match_dup 3)) | |
2231 | (mem:BLK (match_dup 4))) | |
2232 | (use (match_dup 2)) | |
b03149e1 JZ |
2233 | (clobber (match_scratch:HI 5 "=&d")) |
2234 | (clobber (reg:SI REG_LT1)) | |
2235 | (clobber (reg:SI REG_LC1)) | |
2236 | (clobber (reg:SI REG_LB1))] | |
0d4a78eb | 2237 | "" |
51a641fd | 2238 | "%h5 = W[%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || W [%3++] = %5 || %h5 = W [%4++]; W [%3++] = %5;" |
0d4a78eb | 2239 | [(set_attr "type" "misc") |
b03149e1 JZ |
2240 | (set_attr "length" "16") |
2241 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb | 2242 | |
144f8315 | 2243 | (define_expand "movmemsi" |
0d4a78eb BS |
2244 | [(match_operand:BLK 0 "general_operand" "") |
2245 | (match_operand:BLK 1 "general_operand" "") | |
2246 | (match_operand:SI 2 "const_int_operand" "") | |
2247 | (match_operand:SI 3 "const_int_operand" "")] | |
2248 | "" | |
2249 | { | |
144f8315 | 2250 | if (bfin_expand_movmem (operands[0], operands[1], operands[2], operands[3])) |
0d4a78eb BS |
2251 | DONE; |
2252 | FAIL; | |
2253 | }) | |
2254 | ||
2255 | ;; Conditional branch patterns | |
2256 | ;; The Blackfin has only few condition codes: eq, lt, lte, ltu, leu | |
2257 | ||
2258 | ;; The only outcome of this pattern is that global variables | |
2259 | ;; bfin_compare_op[01] are set for use in bcond patterns. | |
2260 | ||
2261 | (define_expand "cmpbi" | |
2262 | [(set (cc0) (compare (match_operand:BI 0 "register_operand" "") | |
2263 | (match_operand:BI 1 "immediate_operand" "")))] | |
2264 | "" | |
2265 | { | |
2266 | bfin_compare_op0 = operands[0]; | |
2267 | bfin_compare_op1 = operands[1]; | |
2268 | DONE; | |
2269 | }) | |
2270 | ||
2271 | (define_expand "cmpsi" | |
2272 | [(set (cc0) (compare (match_operand:SI 0 "register_operand" "") | |
7ddcf3d2 | 2273 | (match_operand:SI 1 "reg_or_const_int_operand" "")))] |
0d4a78eb BS |
2274 | "" |
2275 | { | |
2276 | bfin_compare_op0 = operands[0]; | |
2277 | bfin_compare_op1 = operands[1]; | |
2278 | DONE; | |
2279 | }) | |
2280 | ||
49373252 | 2281 | (define_insn "compare_eq" |
4729dc92 | 2282 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2283 | (eq:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2284 | (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] |
0d4a78eb BS |
2285 | "" |
2286 | "cc =%1==%2;" | |
2287 | [(set_attr "type" "compare")]) | |
2288 | ||
49373252 | 2289 | (define_insn "compare_ne" |
4729dc92 | 2290 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2291 | (ne:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2292 | (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] |
0d4a78eb BS |
2293 | "0" |
2294 | "cc =%1!=%2;" | |
2295 | [(set_attr "type" "compare")]) | |
2296 | ||
49373252 | 2297 | (define_insn "compare_lt" |
4729dc92 | 2298 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2299 | (lt:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2300 | (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] |
0d4a78eb BS |
2301 | "" |
2302 | "cc =%1<%2;" | |
2303 | [(set_attr "type" "compare")]) | |
2304 | ||
49373252 | 2305 | (define_insn "compare_le" |
4729dc92 | 2306 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2307 | (le:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2308 | (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] |
0d4a78eb BS |
2309 | "" |
2310 | "cc =%1<=%2;" | |
2311 | [(set_attr "type" "compare")]) | |
2312 | ||
49373252 | 2313 | (define_insn "compare_leu" |
4729dc92 | 2314 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2315 | (leu:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2316 | (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))] |
0d4a78eb BS |
2317 | "" |
2318 | "cc =%1<=%2 (iu);" | |
2319 | [(set_attr "type" "compare")]) | |
2320 | ||
49373252 | 2321 | (define_insn "compare_ltu" |
4729dc92 | 2322 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2323 | (ltu:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2324 | (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))] |
0d4a78eb BS |
2325 | "" |
2326 | "cc =%1<%2 (iu);" | |
2327 | [(set_attr "type" "compare")]) | |
2328 | ||
2329 | (define_expand "beq" | |
2330 | [(set (match_dup 1) (match_dup 2)) | |
2331 | (set (pc) | |
2332 | (if_then_else (match_dup 3) | |
2333 | (label_ref (match_operand 0 "" "")) | |
2334 | (pc)))] | |
2335 | "" | |
2336 | { | |
2337 | rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1; | |
2338 | operands[1] = bfin_cc_rtx; /* hard register: CC */ | |
2339 | operands[2] = gen_rtx_EQ (BImode, op0, op1); | |
2340 | /* If we have a BImode input, then we already have a compare result, and | |
2341 | do not need to emit another comparison. */ | |
2342 | if (GET_MODE (bfin_compare_op0) == BImode) | |
2343 | { | |
3b9dd769 NS |
2344 | gcc_assert (bfin_compare_op1 == const0_rtx); |
2345 | emit_insn (gen_cbranchbi4 (operands[2], op0, op1, operands[0])); | |
2346 | DONE; | |
0d4a78eb BS |
2347 | } |
2348 | ||
2349 | operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx); | |
2350 | }) | |
2351 | ||
2352 | (define_expand "bne" | |
2353 | [(set (match_dup 1) (match_dup 2)) | |
2354 | (set (pc) | |
2355 | (if_then_else (match_dup 3) | |
2356 | (label_ref (match_operand 0 "" "")) | |
2357 | (pc)))] | |
2358 | "" | |
2359 | { | |
2360 | rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1; | |
2361 | /* If we have a BImode input, then we already have a compare result, and | |
2362 | do not need to emit another comparison. */ | |
2363 | if (GET_MODE (bfin_compare_op0) == BImode) | |
2364 | { | |
3b9dd769 NS |
2365 | rtx cmp = gen_rtx_NE (BImode, op0, op1); |
2366 | ||
2367 | gcc_assert (bfin_compare_op1 == const0_rtx); | |
2368 | emit_insn (gen_cbranchbi4 (cmp, op0, op1, operands[0])); | |
2369 | DONE; | |
0d4a78eb BS |
2370 | } |
2371 | ||
2372 | operands[1] = bfin_cc_rtx; /* hard register: CC */ | |
2373 | operands[2] = gen_rtx_EQ (BImode, op0, op1); | |
2374 | operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx); | |
2375 | }) | |
2376 | ||
2377 | (define_expand "bgt" | |
2378 | [(set (match_dup 1) (match_dup 2)) | |
2379 | (set (pc) | |
2380 | (if_then_else (match_dup 3) | |
2381 | (label_ref (match_operand 0 "" "")) | |
2382 | (pc)))] | |
2383 | "" | |
2384 | { | |
2385 | operands[1] = bfin_cc_rtx; | |
2386 | operands[2] = gen_rtx_LE (BImode, bfin_compare_op0, bfin_compare_op1); | |
2387 | operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx); | |
2388 | }) | |
2389 | ||
2390 | (define_expand "bgtu" | |
2391 | [(set (match_dup 1) (match_dup 2)) | |
2392 | (set (pc) | |
2393 | (if_then_else (match_dup 3) | |
2394 | (label_ref (match_operand 0 "" "")) | |
2395 | (pc)))] | |
2396 | "" | |
2397 | { | |
2398 | operands[1] = bfin_cc_rtx; | |
2399 | operands[2] = gen_rtx_LEU (BImode, bfin_compare_op0, bfin_compare_op1); | |
2400 | operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx); | |
2401 | }) | |
2402 | ||
2403 | (define_expand "blt" | |
2404 | [(set (match_dup 1) (match_dup 2)) | |
2405 | (set (pc) | |
2406 | (if_then_else (match_dup 3) | |
2407 | (label_ref (match_operand 0 "" "")) | |
2408 | (pc)))] | |
2409 | "" | |
2410 | { | |
2411 | operands[1] = bfin_cc_rtx; | |
2412 | operands[2] = gen_rtx_LT (BImode, bfin_compare_op0, bfin_compare_op1); | |
2413 | operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx); | |
2414 | }) | |
2415 | ||
2416 | (define_expand "bltu" | |
2417 | [(set (match_dup 1) (match_dup 2)) | |
2418 | (set (pc) | |
2419 | (if_then_else (match_dup 3) | |
2420 | (label_ref (match_operand 0 "" "")) | |
2421 | (pc)))] | |
2422 | "" | |
2423 | { | |
2424 | operands[1] = bfin_cc_rtx; | |
2425 | operands[2] = gen_rtx_LTU (BImode, bfin_compare_op0, bfin_compare_op1); | |
2426 | operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx); | |
2427 | }) | |
2428 | ||
26c5953d BS |
2429 | ;; Same as above, but and CC with the overflow bit generated by the first |
2430 | ;; multiplication. | |
2431 | (define_insn "flag_mul_macv2hi_parts_acconly_andcc0" | |
2432 | [(set (match_operand:PDI 0 "register_operand" "=B,e,e") | |
2433 | (unspec:PDI [(vec_select:HI | |
2434 | (match_operand:V2HI 2 "register_operand" "d,d,d") | |
2435 | (parallel [(match_operand 4 "const01_operand" "P0P1,P0P1,P0P1")])) | |
2436 | (vec_select:HI | |
2437 | (match_operand:V2HI 3 "register_operand" "d,d,d") | |
2438 | (parallel [(match_operand 6 "const01_operand" "P0P1,P0P1,P0P1")])) | |
2439 | (match_operand 10 "const_int_operand" "PB,PA,PA")] | |
2440 | UNSPEC_MUL_WITH_FLAG)) | |
2441 | (set (match_operand:PDI 1 "register_operand" "=B,e,e") | |
2442 | (unspec:PDI [(vec_select:HI | |
2443 | (match_dup 2) | |
2444 | (parallel [(match_operand 5 "const01_operand" "P0P1,P0P1,P0P1")])) | |
2445 | (vec_select:HI | |
2446 | (match_dup 3) | |
2447 | (parallel [(match_operand 7 "const01_operand" "P0P1,P0P1,P0P1")])) | |
2448 | (match_operand:PDI 8 "register_operand" "1,1,1") | |
2449 | (match_operand 9 "const01_operand" "P0P1,P0P1,P0P1") | |
2450 | (match_operand 11 "const_int_operand" "PA,PB,PA")] | |
2451 | UNSPEC_MAC_WITH_FLAG)) | |
2452 | (set (reg:BI REG_CC) | |
2453 | (and:BI (reg:BI REG_CC) | |
2454 | (unspec:BI [(vec_select:HI (match_dup 2) (parallel [(match_dup 4)])) | |
2455 | (vec_select:HI (match_dup 3) (parallel [(match_dup 6)])) | |
2456 | (match_dup 10)] | |
2457 | UNSPEC_MUL_WITH_FLAG)))] | |
2458 | "MACFLAGS_MATCH_P (INTVAL (operands[10]), INTVAL (operands[11]))" | |
2459 | { | |
2460 | rtx xops[6]; | |
2461 | const char *templates[] = { | |
2462 | "%0 = %h2 * %h3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;", | |
2463 | "%0 = %d2 * %h3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;", | |
2464 | "%0 = %h2 * %h3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;", | |
2465 | "%0 = %d2 * %h3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;", | |
2466 | "%0 = %h2 * %d3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;", | |
2467 | "%0 = %d2 * %d3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;", | |
2468 | "%0 = %h2 * %d3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;", | |
2469 | "%0 = %d2 * %d3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;", | |
2470 | "%0 = %h2 * %h3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;", | |
2471 | "%0 = %d2 * %h3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;", | |
2472 | "%0 = %h2 * %h3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;", | |
2473 | "%0 = %d2 * %h3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;", | |
2474 | "%0 = %h2 * %d3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;", | |
2475 | "%0 = %d2 * %d3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;", | |
2476 | "%0 = %h2 * %d3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;", | |
2477 | "%0 = %d2 * %d3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;" }; | |
2478 | int alt = (INTVAL (operands[4]) + (INTVAL (operands[5]) << 1) | |
2479 | + (INTVAL (operands[6]) << 2) + (INTVAL (operands[7]) << 3)); | |
2480 | xops[0] = operands[0]; | |
2481 | xops[1] = operands[1]; | |
2482 | xops[2] = operands[2]; | |
2483 | xops[3] = operands[3]; | |
2484 | xops[4] = operands[9]; | |
2485 | xops[5] = which_alternative == 0 ? operands[10] : operands[11]; | |
2486 | output_asm_insn (templates[alt], xops); | |
2487 | return ""; | |
2488 | } | |
2489 | [(set_attr "type" "misc") | |
2490 | (set_attr "length" "6") | |
2491 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
2492 | |
2493 | (define_expand "bge" | |
2494 | [(set (match_dup 1) (match_dup 2)) | |
2495 | (set (pc) | |
2496 | (if_then_else (match_dup 3) | |
2497 | (label_ref (match_operand 0 "" "")) | |
2498 | (pc)))] | |
2499 | "" | |
2500 | { | |
2501 | operands[1] = bfin_cc_rtx; | |
2502 | operands[2] = gen_rtx_LT (BImode, bfin_compare_op0, bfin_compare_op1); | |
2503 | operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx); | |
2504 | }) | |
2505 | ||
2506 | (define_expand "bgeu" | |
2507 | [(set (match_dup 1) (match_dup 2)) | |
2508 | (set (pc) | |
2509 | (if_then_else (match_dup 3) | |
2510 | (label_ref (match_operand 0 "" "")) | |
2511 | (pc)))] | |
2512 | "" | |
2513 | { | |
2514 | operands[1] = bfin_cc_rtx; | |
2515 | operands[2] = gen_rtx_LTU (BImode, bfin_compare_op0, bfin_compare_op1); | |
2516 | operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx); | |
2517 | }) | |
2518 | ||
2519 | (define_expand "ble" | |
2520 | [(set (match_dup 1) (match_dup 2)) | |
2521 | (set (pc) | |
2522 | (if_then_else (match_dup 3) | |
2523 | (label_ref (match_operand 0 "" "")) | |
2524 | (pc)))] | |
2525 | "" | |
2526 | { | |
2527 | operands[1] = bfin_cc_rtx; | |
2528 | operands[2] = gen_rtx_LE (BImode, bfin_compare_op0, bfin_compare_op1); | |
2529 | operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx); | |
2530 | }) | |
2531 | ||
2532 | (define_expand "bleu" | |
2533 | [(set (match_dup 1) (match_dup 2)) | |
2534 | (set (pc) | |
2535 | (if_then_else (match_dup 3) | |
2536 | (label_ref (match_operand 0 "" "")) | |
2537 | (pc))) | |
2538 | ] | |
2539 | "" | |
2540 | { | |
2541 | operands[1] = bfin_cc_rtx; | |
2542 | operands[2] = gen_rtx_LEU (BImode, bfin_compare_op0, bfin_compare_op1); | |
2543 | operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx); | |
2544 | }) | |
2545 | ||
2546 | (define_insn "cbranchbi4" | |
2547 | [(set (pc) | |
2548 | (if_then_else | |
2549 | (match_operator 0 "bfin_cbranch_operator" | |
4729dc92 | 2550 | [(match_operand:BI 1 "register_operand" "C") |
0d4a78eb BS |
2551 | (match_operand:BI 2 "immediate_operand" "P0")]) |
2552 | (label_ref (match_operand 3 "" "")) | |
2553 | (pc)))] | |
2554 | "" | |
2555 | { | |
2556 | asm_conditional_branch (insn, operands, 0, 0); | |
2557 | return ""; | |
2558 | } | |
2559 | [(set_attr "type" "brcc")]) | |
2560 | ||
2561 | ;; Special cbranch patterns to deal with the speculative load problem - see | |
2562 | ;; bfin_reorg for details. | |
2563 | ||
2564 | (define_insn "cbranch_predicted_taken" | |
2565 | [(set (pc) | |
2566 | (if_then_else | |
2567 | (match_operator 0 "bfin_cbranch_operator" | |
4729dc92 | 2568 | [(match_operand:BI 1 "register_operand" "C") |
0d4a78eb BS |
2569 | (match_operand:BI 2 "immediate_operand" "P0")]) |
2570 | (label_ref (match_operand 3 "" "")) | |
2571 | (pc))) | |
2572 | (unspec [(const_int 0)] UNSPEC_CBRANCH_TAKEN)] | |
2573 | "" | |
2574 | { | |
2575 | asm_conditional_branch (insn, operands, 0, 1); | |
2576 | return ""; | |
2577 | } | |
2578 | [(set_attr "type" "brcc")]) | |
2579 | ||
2580 | (define_insn "cbranch_with_nops" | |
2581 | [(set (pc) | |
2582 | (if_then_else | |
2583 | (match_operator 0 "bfin_cbranch_operator" | |
4729dc92 | 2584 | [(match_operand:BI 1 "register_operand" "C") |
0d4a78eb BS |
2585 | (match_operand:BI 2 "immediate_operand" "P0")]) |
2586 | (label_ref (match_operand 3 "" "")) | |
2587 | (pc))) | |
2588 | (unspec [(match_operand 4 "immediate_operand" "")] UNSPEC_CBRANCH_NOPS)] | |
2589 | "reload_completed" | |
2590 | { | |
2591 | asm_conditional_branch (insn, operands, INTVAL (operands[4]), 0); | |
2592 | return ""; | |
2593 | } | |
2594 | [(set_attr "type" "brcc") | |
90cbba02 | 2595 | (set_attr "length" "8")]) |
0d4a78eb BS |
2596 | |
2597 | ;; setcc insns. */ | |
2598 | (define_expand "seq" | |
2599 | [(set (match_dup 1) (eq:BI (match_dup 2) (match_dup 3))) | |
2600 | (set (match_operand:SI 0 "register_operand" "") | |
2601 | (ne:SI (match_dup 1) (const_int 0)))] | |
2602 | "" | |
2603 | { | |
2604 | operands[2] = bfin_compare_op0; | |
2605 | operands[3] = bfin_compare_op1; | |
2606 | operands[1] = bfin_cc_rtx; | |
2607 | }) | |
2608 | ||
2609 | (define_expand "slt" | |
2610 | [(set (match_dup 1) (lt:BI (match_dup 2) (match_dup 3))) | |
2611 | (set (match_operand:SI 0 "register_operand" "") | |
2612 | (ne:SI (match_dup 1) (const_int 0)))] | |
2613 | "" | |
2614 | { | |
2615 | operands[2] = bfin_compare_op0; | |
2616 | operands[3] = bfin_compare_op1; | |
2617 | operands[1] = bfin_cc_rtx; | |
2618 | }) | |
2619 | ||
2620 | (define_expand "sle" | |
2621 | [(set (match_dup 1) (le:BI (match_dup 2) (match_dup 3))) | |
2622 | (set (match_operand:SI 0 "register_operand" "") | |
2623 | (ne:SI (match_dup 1) (const_int 0)))] | |
2624 | "" | |
2625 | { | |
2626 | operands[2] = bfin_compare_op0; | |
2627 | operands[3] = bfin_compare_op1; | |
2628 | operands[1] = bfin_cc_rtx; | |
2629 | }) | |
2630 | ||
2631 | (define_expand "sltu" | |
2632 | [(set (match_dup 1) (ltu:BI (match_dup 2) (match_dup 3))) | |
2633 | (set (match_operand:SI 0 "register_operand" "") | |
2634 | (ne:SI (match_dup 1) (const_int 0)))] | |
2635 | "" | |
2636 | { | |
2637 | operands[2] = bfin_compare_op0; | |
2638 | operands[3] = bfin_compare_op1; | |
2639 | operands[1] = bfin_cc_rtx; | |
2640 | }) | |
2641 | ||
2642 | (define_expand "sleu" | |
2643 | [(set (match_dup 1) (leu:BI (match_dup 2) (match_dup 3))) | |
2644 | (set (match_operand:SI 0 "register_operand" "") | |
2645 | (ne:SI (match_dup 1) (const_int 0)))] | |
2646 | "" | |
2647 | { | |
2648 | operands[2] = bfin_compare_op0; | |
2649 | operands[3] = bfin_compare_op1; | |
2650 | operands[1] = bfin_cc_rtx; | |
2651 | }) | |
2652 | ||
2653 | (define_insn "nop" | |
2654 | [(const_int 0)] | |
2655 | "" | |
2656 | "nop;") | |
2657 | ||
b18e284e BS |
2658 | ;; A nop which stays there when emitted. |
2659 | (define_insn "forced_nop" | |
2660 | [(unspec [(const_int 0)] UNSPEC_NOP)] | |
2661 | "" | |
2662 | "nop;") | |
2663 | ||
bbbc206e BS |
2664 | (define_insn "mnop" |
2665 | [(unspec [(const_int 0)] UNSPEC_32BIT)] | |
2666 | "" | |
2667 | "mnop%!" | |
2668 | [(set_attr "type" "dsp32")]) | |
2669 | ||
0d4a78eb BS |
2670 | ;;;;;;;;;;;;;;;;;;;; CC2dreg ;;;;;;;;;;;;;;;;;;;;;;;;; |
2671 | (define_insn "movsibi" | |
4729dc92 | 2672 | [(set (match_operand:BI 0 "register_operand" "=C") |
0d4a78eb BS |
2673 | (ne:BI (match_operand:SI 1 "register_operand" "d") |
2674 | (const_int 0)))] | |
2675 | "" | |
2676 | "CC = %1;" | |
2677 | [(set_attr "length" "2")]) | |
2678 | ||
2679 | (define_insn "movbisi" | |
2680 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4729dc92 | 2681 | (ne:SI (match_operand:BI 1 "register_operand" "C") |
0d4a78eb BS |
2682 | (const_int 0)))] |
2683 | "" | |
2684 | "%0 = CC;" | |
2685 | [(set_attr "length" "2")]) | |
2686 | ||
e4fae5f7 | 2687 | (define_insn "notbi" |
4729dc92 BS |
2688 | [(set (match_operand:BI 0 "register_operand" "=C") |
2689 | (eq:BI (match_operand:BI 1 "register_operand" " 0") | |
0d4a78eb BS |
2690 | (const_int 0)))] |
2691 | "" | |
2692 | "%0 = ! %0;" /* NOT CC;" */ | |
2693 | [(set_attr "type" "compare")]) | |
2694 | ||
2695 | ;; Vector and DSP insns | |
2696 | ||
2697 | (define_insn "" | |
2698 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2699 | (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") | |
2700 | (const_int 24)) | |
2701 | (lshiftrt:SI (match_operand:SI 2 "register_operand" "d") | |
2702 | (const_int 8))))] | |
2703 | "" | |
bbbc206e | 2704 | "%0 = ALIGN8(%1, %2)%!" |
0d4a78eb BS |
2705 | [(set_attr "type" "dsp32")]) |
2706 | ||
2707 | (define_insn "" | |
2708 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2709 | (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") | |
2710 | (const_int 16)) | |
2711 | (lshiftrt:SI (match_operand:SI 2 "register_operand" "d") | |
2712 | (const_int 16))))] | |
2713 | "" | |
bbbc206e | 2714 | "%0 = ALIGN16(%1, %2)%!" |
0d4a78eb BS |
2715 | [(set_attr "type" "dsp32")]) |
2716 | ||
2717 | (define_insn "" | |
2718 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2719 | (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") | |
2720 | (const_int 8)) | |
2721 | (lshiftrt:SI (match_operand:SI 2 "register_operand" "d") | |
2722 | (const_int 24))))] | |
2723 | "" | |
bbbc206e | 2724 | "%0 = ALIGN24(%1, %2)%!" |
0d4a78eb BS |
2725 | [(set_attr "type" "dsp32")]) |
2726 | ||
2727 | ;; Prologue and epilogue. | |
2728 | ||
2729 | (define_expand "prologue" | |
2730 | [(const_int 1)] | |
2731 | "" | |
2732 | "bfin_expand_prologue (); DONE;") | |
2733 | ||
2734 | (define_expand "epilogue" | |
2735 | [(const_int 1)] | |
2736 | "" | |
1f9e4ca1 | 2737 | "bfin_expand_epilogue (1, 0, 0); DONE;") |
0d4a78eb BS |
2738 | |
2739 | (define_expand "sibcall_epilogue" | |
2740 | [(const_int 1)] | |
2741 | "" | |
1f9e4ca1 | 2742 | "bfin_expand_epilogue (0, 0, 1); DONE;") |
0d4a78eb BS |
2743 | |
2744 | (define_expand "eh_return" | |
2745 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "")] | |
2746 | UNSPEC_VOLATILE_EH_RETURN)] | |
2747 | "" | |
2748 | { | |
1ca950ca | 2749 | emit_insn (gen_eh_store_handler (EH_RETURN_HANDLER_RTX, operands[0])); |
1e96b1c3 | 2750 | emit_jump_insn (gen_eh_return_internal ()); |
0d4a78eb | 2751 | emit_barrier (); |
4193ce73 | 2752 | DONE; |
0d4a78eb BS |
2753 | }) |
2754 | ||
1ca950ca BS |
2755 | (define_insn "eh_store_handler" |
2756 | [(unspec_volatile [(match_operand:SI 1 "register_operand" "da")] | |
2757 | UNSPEC_VOLATILE_STORE_EH_HANDLER) | |
2758 | (clobber (match_operand:SI 0 "memory_operand" "=m"))] | |
2759 | "" | |
2760 | "%0 = %1%!" | |
2761 | [(set_attr "type" "mcst")]) | |
2762 | ||
0d4a78eb | 2763 | (define_insn_and_split "eh_return_internal" |
1e96b1c3 JZ |
2764 | [(set (pc) |
2765 | (unspec_volatile [(reg:SI REG_P2)] UNSPEC_VOLATILE_EH_RETURN))] | |
0d4a78eb BS |
2766 | "" |
2767 | "#" | |
2768 | "reload_completed" | |
2769 | [(const_int 1)] | |
1f9e4ca1 | 2770 | "bfin_expand_epilogue (1, 1, 0); DONE;") |
0d4a78eb BS |
2771 | |
2772 | (define_insn "link" | |
2773 | [(set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -4))) (reg:SI REG_RETS)) | |
2774 | (set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -8))) (reg:SI REG_FP)) | |
2775 | (set (reg:SI REG_FP) | |
2776 | (plus:SI (reg:SI REG_SP) (const_int -8))) | |
2777 | (set (reg:SI REG_SP) | |
2778 | (plus:SI (reg:SI REG_SP) (match_operand:SI 0 "immediate_operand" "i")))] | |
2779 | "" | |
2780 | "LINK %Z0;" | |
2781 | [(set_attr "length" "4")]) | |
2782 | ||
2783 | (define_insn "unlink" | |
2784 | [(set (reg:SI REG_FP) (mem:SI (reg:SI REG_FP))) | |
2785 | (set (reg:SI REG_RETS) (mem:SI (plus:SI (reg:SI REG_FP) (const_int 4)))) | |
2786 | (set (reg:SI REG_SP) (plus:SI (reg:SI REG_FP) (const_int 8)))] | |
2787 | "" | |
2788 | "UNLINK;" | |
2789 | [(set_attr "length" "4")]) | |
2790 | ||
2791 | ;; This pattern is slightly clumsy. The stack adjust must be the final SET in | |
2792 | ;; the pattern, otherwise dwarf2out becomes very confused about which reg goes | |
2793 | ;; where on the stack, since it goes through all elements of the parallel in | |
2794 | ;; sequence. | |
2795 | (define_insn "push_multiple" | |
2796 | [(match_parallel 0 "push_multiple_operation" | |
2797 | [(unspec [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_PUSH_MULTIPLE)])] | |
2798 | "" | |
2799 | { | |
2800 | output_push_multiple (insn, operands); | |
2801 | return ""; | |
2802 | }) | |
2803 | ||
2804 | (define_insn "pop_multiple" | |
2805 | [(match_parallel 0 "pop_multiple_operation" | |
2806 | [(set (reg:SI REG_SP) | |
2807 | (plus:SI (reg:SI REG_SP) (match_operand:SI 1 "immediate_operand" "i")))])] | |
2808 | "" | |
2809 | { | |
2810 | output_pop_multiple (insn, operands); | |
2811 | return ""; | |
2812 | }) | |
2813 | ||
2814 | (define_insn "return_internal" | |
2815 | [(return) | |
2816 | (unspec [(match_operand 0 "immediate_operand" "i")] UNSPEC_RETURN)] | |
2817 | "reload_completed" | |
2818 | { | |
2819 | switch (INTVAL (operands[0])) | |
2820 | { | |
2821 | case EXCPT_HANDLER: | |
2822 | return "rtx;"; | |
2823 | case NMI_HANDLER: | |
2824 | return "rtn;"; | |
2825 | case INTERRUPT_HANDLER: | |
2826 | return "rti;"; | |
2827 | case SUBROUTINE: | |
2828 | return "rts;"; | |
2829 | } | |
2830 | gcc_unreachable (); | |
2831 | }) | |
2832 | ||
669eeb28 BS |
2833 | (define_insn "dummy_load" |
2834 | [(unspec_volatile [(match_operand 0 "register_operand" "a") | |
2835 | (match_operand 1 "register_operand" "C")] | |
2836 | UNSPEC_VOLATILE_DUMMY)] | |
2837 | "" | |
2838 | "if cc jump 4;\n\tr7 = [%0];" | |
2839 | [(set_attr "type" "misc") | |
2840 | (set_attr "length" "4") | |
2841 | (set_attr "seq_insns" "multi")]) | |
2842 | ||
5fcead21 BS |
2843 | (define_insn "csync" |
2844 | [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_CSYNC)] | |
2845 | "" | |
2846 | "csync;" | |
3fb192d2 | 2847 | [(set_attr "type" "sync")]) |
5fcead21 BS |
2848 | |
2849 | (define_insn "ssync" | |
2850 | [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_SSYNC)] | |
2851 | "" | |
2852 | "ssync;" | |
3fb192d2 | 2853 | [(set_attr "type" "sync")]) |
5fcead21 | 2854 | |
3d33a056 JZ |
2855 | (define_insn "trap" |
2856 | [(trap_if (const_int 1) (const_int 3))] | |
2857 | "" | |
2858 | "excpt 3;" | |
2859 | [(set_attr "type" "misc") | |
2860 | (set_attr "length" "2")]) | |
2861 | ||
09350e36 BS |
2862 | (define_insn "trapifcc" |
2863 | [(trap_if (reg:BI REG_CC) (const_int 3))] | |
2864 | "" | |
2865 | "if !cc jump 4 (bp); excpt 3;" | |
2866 | [(set_attr "type" "misc") | |
b03149e1 JZ |
2867 | (set_attr "length" "4") |
2868 | (set_attr "seq_insns" "multi")]) | |
09350e36 | 2869 | |
0d4a78eb BS |
2870 | ;;; Vector instructions |
2871 | ||
75d8b2d0 BS |
2872 | ;; First, all sorts of move variants |
2873 | ||
75d8b2d0 BS |
2874 | (define_insn "movhiv2hi_low" |
2875 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2876 | (vec_concat:V2HI | |
2877 | (match_operand:HI 2 "register_operand" "d") | |
2878 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
2879 | (parallel [(const_int 1)]))))] | |
2880 | "" | |
bbbc206e | 2881 | "%h0 = %h2 << 0%!" |
75d8b2d0 BS |
2882 | [(set_attr "type" "dsp32")]) |
2883 | ||
2884 | (define_insn "movhiv2hi_high" | |
2885 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2886 | (vec_concat:V2HI | |
2887 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
2888 | (parallel [(const_int 0)])) | |
2889 | (match_operand:HI 2 "register_operand" "d")))] | |
2890 | "" | |
bbbc206e | 2891 | "%d0 = %h2 << 0%!" |
75d8b2d0 BS |
2892 | [(set_attr "type" "dsp32")]) |
2893 | ||
2894 | ;; No earlyclobber on alternative two since our sequence ought to be safe. | |
2895 | ;; The order of operands is intentional to match the VDSP builtin (high word | |
2896 | ;; is passed first). | |
2897 | (define_insn_and_split "composev2hi" | |
2898 | [(set (match_operand:V2HI 0 "register_operand" "=d,d") | |
2899 | (vec_concat:V2HI (match_operand:HI 2 "register_operand" "0,d") | |
2900 | (match_operand:HI 1 "register_operand" "d,d")))] | |
2901 | "" | |
2902 | "@ | |
23cf1526 | 2903 | %d0 = %h1 << 0%! |
75d8b2d0 BS |
2904 | #" |
2905 | "reload_completed" | |
2906 | [(set (match_dup 0) | |
2907 | (vec_concat:V2HI | |
2908 | (vec_select:HI (match_dup 0) (parallel [(const_int 0)])) | |
23cf1526 | 2909 | (match_dup 1))) |
75d8b2d0 BS |
2910 | (set (match_dup 0) |
2911 | (vec_concat:V2HI | |
23cf1526 | 2912 | (match_dup 2) |
75d8b2d0 BS |
2913 | (vec_select:HI (match_dup 0) (parallel [(const_int 1)]))))] |
2914 | "" | |
2915 | [(set_attr "type" "dsp32")]) | |
2916 | ||
2917 | ; Like composev2hi, but operating on elements of V2HI vectors. | |
2918 | ; Useful on its own, and as a combiner bridge for the multiply and | |
2919 | ; mac patterns. | |
2920 | (define_insn "packv2hi" | |
2d3649b2 | 2921 | [(set (match_operand:V2HI 0 "register_operand" "=d,d,d,d,d,d,d,d") |
75d8b2d0 | 2922 | (vec_concat:V2HI (vec_select:HI |
2d3649b2 BS |
2923 | (match_operand:V2HI 1 "register_operand" "0,0,d,d,d,d,d,d") |
2924 | (parallel [(match_operand 3 "const01_operand" "P0,P0,P0,P1,P0,P1,P0,P1")])) | |
75d8b2d0 | 2925 | (vec_select:HI |
2d3649b2 BS |
2926 | (match_operand:V2HI 2 "register_operand" "d,d,0,0,d,d,d,d") |
2927 | (parallel [(match_operand 4 "const01_operand" "P0,P1,P1,P1,P0,P0,P1,P1")]))))] | |
75d8b2d0 BS |
2928 | "" |
2929 | "@ | |
2d3649b2 BS |
2930 | %d0 = %h2 << 0%! |
2931 | %d0 = %d2 << 0%! | |
2932 | %h0 = %h1 << 0%! | |
2933 | %h0 = %d1 << 0%! | |
bbbc206e BS |
2934 | %0 = PACK (%h2,%h1)%! |
2935 | %0 = PACK (%h2,%d1)%! | |
2936 | %0 = PACK (%d2,%h1)%! | |
2937 | %0 = PACK (%d2,%d1)%!" | |
75d8b2d0 BS |
2938 | [(set_attr "type" "dsp32")]) |
2939 | ||
2940 | (define_insn "movv2hi_hi" | |
2941 | [(set (match_operand:HI 0 "register_operand" "=d,d,d") | |
2942 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0,d,d") | |
554006bd | 2943 | (parallel [(match_operand 2 "const01_operand" "P0,P0,P1")])))] |
75d8b2d0 BS |
2944 | "" |
2945 | "@ | |
2946 | /* optimized out */ | |
bbbc206e BS |
2947 | %h0 = %h1 << 0%! |
2948 | %h0 = %d1 << 0%!" | |
75d8b2d0 BS |
2949 | [(set_attr "type" "dsp32")]) |
2950 | ||
2951 | (define_expand "movv2hi_hi_low" | |
2952 | [(set (match_operand:HI 0 "register_operand" "") | |
2953 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "") | |
2954 | (parallel [(const_int 0)])))] | |
2955 | "" | |
2956 | "") | |
2957 | ||
2958 | (define_expand "movv2hi_hi_high" | |
2959 | [(set (match_operand:HI 0 "register_operand" "") | |
2960 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "") | |
2961 | (parallel [(const_int 1)])))] | |
2962 | "" | |
2963 | "") | |
2964 | ||
942fd98f | 2965 | ;; Unusual arithmetic operations on 16-bit registers. |
75d8b2d0 | 2966 | |
a0a31d1e BS |
2967 | (define_code_iterator sp_or_sm [ss_plus ss_minus]) |
2968 | (define_code_attr spm_string [(ss_plus "+") (ss_minus "-")]) | |
2969 | (define_code_attr spm_name [(ss_plus "add") (ss_minus "sub")]) | |
2970 | ||
2971 | (define_insn "ss<spm_name>hi3" | |
75d8b2d0 | 2972 | [(set (match_operand:HI 0 "register_operand" "=d") |
a0a31d1e | 2973 | (sp_or_sm:HI (match_operand:HI 1 "register_operand" "d") |
75d8b2d0 BS |
2974 | (match_operand:HI 2 "register_operand" "d")))] |
2975 | "" | |
a0a31d1e | 2976 | "%h0 = %h1 <spm_string> %h2 (S)%!" |
75d8b2d0 BS |
2977 | [(set_attr "type" "dsp32")]) |
2978 | ||
a0a31d1e BS |
2979 | (define_insn "ss<spm_name>hi3_parts" |
2980 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2981 | (sp_or_sm:HI (vec_select:HI | |
2982 | (match_operand:V2HI 1 "register_operand" "d") | |
2983 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) | |
2984 | (vec_select:HI | |
2985 | (match_operand:V2HI 2 "register_operand" "d") | |
2986 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))))] | |
2987 | "" | |
1d7d5ac4 BS |
2988 | { |
2989 | const char *templates[] = { | |
a0a31d1e BS |
2990 | "%h0 = %h1 <spm_string> %h2 (S)%!", |
2991 | "%h0 = %d1 <spm_string> %h2 (S)%!", | |
2992 | "%h0 = %h1 <spm_string> %d2 (S)%!", | |
2993 | "%h0 = %d1 <spm_string> %d2 (S)%!" }; | |
2994 | int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1); | |
1d7d5ac4 BS |
2995 | return templates[alt]; |
2996 | } | |
2997 | [(set_attr "type" "dsp32")]) | |
2998 | ||
a0a31d1e BS |
2999 | (define_insn "ss<spm_name>hi3_low_parts" |
3000 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3001 | (vec_concat:V2HI | |
3002 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
3003 | (parallel [(const_int 0)])) | |
3004 | (sp_or_sm:HI (vec_select:HI | |
3005 | (match_operand:V2HI 2 "register_operand" "d") | |
3006 | (parallel [(match_operand 4 "const01_operand" "P0P1")])) | |
3007 | (vec_select:HI | |
3008 | (match_operand:V2HI 3 "register_operand" "d") | |
3009 | (parallel [(match_operand 5 "const01_operand" "P0P1")])))))] | |
3010 | "" | |
1d7d5ac4 BS |
3011 | { |
3012 | const char *templates[] = { | |
a0a31d1e BS |
3013 | "%h0 = %h2 <spm_string> %h3 (S)%!", |
3014 | "%h0 = %d2 <spm_string> %h3 (S)%!", | |
3015 | "%h0 = %h2 <spm_string> %d3 (S)%!", | |
3016 | "%h0 = %d2 <spm_string> %d3 (S)%!" }; | |
3017 | int alt = INTVAL (operands[4]) + (INTVAL (operands[5]) << 1); | |
1d7d5ac4 BS |
3018 | return templates[alt]; |
3019 | } | |
3020 | [(set_attr "type" "dsp32")]) | |
3021 | ||
a0a31d1e BS |
3022 | (define_insn "ss<spm_name>hi3_high_parts" |
3023 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3024 | (vec_concat:V2HI | |
3025 | (sp_or_sm:HI (vec_select:HI | |
3026 | (match_operand:V2HI 2 "register_operand" "d") | |
3027 | (parallel [(match_operand 4 "const01_operand" "P0P1")])) | |
3028 | (vec_select:HI | |
3029 | (match_operand:V2HI 3 "register_operand" "d") | |
3030 | (parallel [(match_operand 5 "const01_operand" "P0P1")]))) | |
3031 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
3032 | (parallel [(const_int 1)]))))] | |
3033 | "" | |
3034 | { | |
3035 | const char *templates[] = { | |
3036 | "%d0 = %h2 <spm_string> %h3 (S)%!", | |
3037 | "%d0 = %d2 <spm_string> %h3 (S)%!", | |
3038 | "%d0 = %h2 <spm_string> %d3 (S)%!", | |
3039 | "%d0 = %d2 <spm_string> %d3 (S)%!" }; | |
3040 | int alt = INTVAL (operands[4]) + (INTVAL (operands[5]) << 1); | |
3041 | return templates[alt]; | |
3042 | } | |
75d8b2d0 BS |
3043 | [(set_attr "type" "dsp32")]) |
3044 | ||
3045 | ;; V2HI vector insns | |
3046 | ||
c9b3f817 | 3047 | (define_insn "addv2hi3" |
0d4a78eb BS |
3048 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
3049 | (plus:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
3050 | (match_operand:V2HI 2 "register_operand" "d")))] | |
3051 | "" | |
bbbc206e | 3052 | "%0 = %1 +|+ %2%!" |
0d4a78eb BS |
3053 | [(set_attr "type" "dsp32")]) |
3054 | ||
75d8b2d0 BS |
3055 | (define_insn "ssaddv2hi3" |
3056 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3057 | (ss_plus:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
3058 | (match_operand:V2HI 2 "register_operand" "d")))] | |
3059 | "" | |
bbbc206e | 3060 | "%0 = %1 +|+ %2 (S)%!" |
75d8b2d0 BS |
3061 | [(set_attr "type" "dsp32")]) |
3062 | ||
c9b3f817 | 3063 | (define_insn "subv2hi3" |
0d4a78eb BS |
3064 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
3065 | (minus:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
3066 | (match_operand:V2HI 2 "register_operand" "d")))] | |
3067 | "" | |
bbbc206e | 3068 | "%0 = %1 -|- %2%!" |
0d4a78eb BS |
3069 | [(set_attr "type" "dsp32")]) |
3070 | ||
75d8b2d0 BS |
3071 | (define_insn "sssubv2hi3" |
3072 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3073 | (ss_minus:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
3074 | (match_operand:V2HI 2 "register_operand" "d")))] | |
3075 | "" | |
bbbc206e | 3076 | "%0 = %1 -|- %2 (S)%!" |
75d8b2d0 BS |
3077 | [(set_attr "type" "dsp32")]) |
3078 | ||
3079 | (define_insn "addsubv2hi3" | |
3080 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3081 | (vec_concat:V2HI | |
3082 | (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3083 | (parallel [(const_int 0)])) | |
3084 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3085 | (parallel [(const_int 0)]))) | |
3086 | (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])) | |
3087 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3088 | "" | |
bbbc206e | 3089 | "%0 = %1 +|- %2%!" |
75d8b2d0 BS |
3090 | [(set_attr "type" "dsp32")]) |
3091 | ||
3092 | (define_insn "subaddv2hi3" | |
3093 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3094 | (vec_concat:V2HI | |
3095 | (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3096 | (parallel [(const_int 0)])) | |
3097 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3098 | (parallel [(const_int 0)]))) | |
3099 | (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])) | |
3100 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3101 | "" | |
bbbc206e | 3102 | "%0 = %1 -|+ %2%!" |
75d8b2d0 BS |
3103 | [(set_attr "type" "dsp32")]) |
3104 | ||
3105 | (define_insn "ssaddsubv2hi3" | |
3106 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3107 | (vec_concat:V2HI | |
3108 | (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3109 | (parallel [(const_int 0)])) | |
3110 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3111 | (parallel [(const_int 0)]))) | |
3112 | (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])) | |
3113 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3114 | "" | |
bbbc206e | 3115 | "%0 = %1 +|- %2 (S)%!" |
75d8b2d0 BS |
3116 | [(set_attr "type" "dsp32")]) |
3117 | ||
3118 | (define_insn "sssubaddv2hi3" | |
3119 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3120 | (vec_concat:V2HI | |
3121 | (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3122 | (parallel [(const_int 0)])) | |
3123 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3124 | (parallel [(const_int 0)]))) | |
3125 | (ss_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])) | |
3126 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3127 | "" | |
bbbc206e | 3128 | "%0 = %1 -|+ %2 (S)%!" |
75d8b2d0 BS |
3129 | [(set_attr "type" "dsp32")]) |
3130 | ||
3131 | (define_insn "sublohiv2hi3" | |
3132 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3133 | (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3134 | (parallel [(const_int 1)])) | |
3135 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3136 | (parallel [(const_int 0)]))))] | |
3137 | "" | |
bbbc206e | 3138 | "%h0 = %d1 - %h2%!" |
75d8b2d0 BS |
3139 | [(set_attr "type" "dsp32")]) |
3140 | ||
3141 | (define_insn "subhilov2hi3" | |
3142 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3143 | (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3144 | (parallel [(const_int 0)])) | |
3145 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3146 | (parallel [(const_int 1)]))))] | |
3147 | "" | |
bbbc206e | 3148 | "%h0 = %h1 - %d2%!" |
75d8b2d0 BS |
3149 | [(set_attr "type" "dsp32")]) |
3150 | ||
3151 | (define_insn "sssublohiv2hi3" | |
3152 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3153 | (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3154 | (parallel [(const_int 1)])) | |
3155 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3156 | (parallel [(const_int 0)]))))] | |
3157 | "" | |
bbbc206e | 3158 | "%h0 = %d1 - %h2 (S)%!" |
75d8b2d0 BS |
3159 | [(set_attr "type" "dsp32")]) |
3160 | ||
3161 | (define_insn "sssubhilov2hi3" | |
3162 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3163 | (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3164 | (parallel [(const_int 0)])) | |
3165 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3166 | (parallel [(const_int 1)]))))] | |
3167 | "" | |
bbbc206e | 3168 | "%h0 = %h1 - %d2 (S)%!" |
75d8b2d0 BS |
3169 | [(set_attr "type" "dsp32")]) |
3170 | ||
3171 | (define_insn "addlohiv2hi3" | |
3172 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3173 | (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3174 | (parallel [(const_int 1)])) | |
3175 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3176 | (parallel [(const_int 0)]))))] | |
3177 | "" | |
bbbc206e | 3178 | "%h0 = %d1 + %h2%!" |
75d8b2d0 BS |
3179 | [(set_attr "type" "dsp32")]) |
3180 | ||
3181 | (define_insn "addhilov2hi3" | |
3182 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3183 | (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3184 | (parallel [(const_int 0)])) | |
3185 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3186 | (parallel [(const_int 1)]))))] | |
3187 | "" | |
bbbc206e | 3188 | "%h0 = %h1 + %d2%!" |
75d8b2d0 BS |
3189 | [(set_attr "type" "dsp32")]) |
3190 | ||
3191 | (define_insn "ssaddlohiv2hi3" | |
3192 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3193 | (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3194 | (parallel [(const_int 1)])) | |
3195 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3196 | (parallel [(const_int 0)]))))] | |
3197 | "" | |
bbbc206e | 3198 | "%h0 = %d1 + %h2 (S)%!" |
75d8b2d0 BS |
3199 | [(set_attr "type" "dsp32")]) |
3200 | ||
3201 | (define_insn "ssaddhilov2hi3" | |
3202 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3203 | (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3204 | (parallel [(const_int 0)])) | |
3205 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3206 | (parallel [(const_int 1)]))))] | |
3207 | "" | |
bbbc206e | 3208 | "%h0 = %h1 + %d2 (S)%!" |
75d8b2d0 BS |
3209 | [(set_attr "type" "dsp32")]) |
3210 | ||
c9b3f817 | 3211 | (define_insn "sminv2hi3" |
0d4a78eb BS |
3212 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
3213 | (smin:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
3214 | (match_operand:V2HI 2 "register_operand" "d")))] | |
3215 | "" | |
bbbc206e | 3216 | "%0 = MIN (%1, %2) (V)%!" |
0d4a78eb BS |
3217 | [(set_attr "type" "dsp32")]) |
3218 | ||
c9b3f817 | 3219 | (define_insn "smaxv2hi3" |
0d4a78eb BS |
3220 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
3221 | (smax:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
3222 | (match_operand:V2HI 2 "register_operand" "d")))] | |
3223 | "" | |
bbbc206e | 3224 | "%0 = MAX (%1, %2) (V)%!" |
0d4a78eb BS |
3225 | [(set_attr "type" "dsp32")]) |
3226 | ||
75d8b2d0 BS |
3227 | ;; Multiplications. |
3228 | ||
3229 | ;; The Blackfin allows a lot of different options, and we need many patterns to | |
3230 | ;; cover most of the hardware's abilities. | |
3231 | ;; There are a few simple patterns using MULT rtx codes, but most of them use | |
3232 | ;; an unspec with a const_int operand that determines which flag to use in the | |
3233 | ;; instruction. | |
3234 | ;; There are variants for single and parallel multiplications. | |
942fd98f | 3235 | ;; There are variants which just use 16-bit lowparts as inputs, and variants |
75d8b2d0 BS |
3236 | ;; which allow the user to choose just which halves to use as input values. |
3237 | ;; There are variants which set D registers, variants which set accumulators, | |
3238 | ;; variants which set both, some of them optionally using the accumulators as | |
3239 | ;; inputs for multiply-accumulate operations. | |
3240 | ||
3241 | (define_insn "flag_mulhi" | |
3242 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3243 | (unspec:HI [(match_operand:HI 1 "register_operand" "d") | |
3244 | (match_operand:HI 2 "register_operand" "d") | |
3245 | (match_operand 3 "const_int_operand" "n")] | |
3246 | UNSPEC_MUL_WITH_FLAG))] | |
3247 | "" | |
bbbc206e | 3248 | "%h0 = %h1 * %h2 %M3%!" |
75d8b2d0 BS |
3249 | [(set_attr "type" "dsp32")]) |
3250 | ||
1d7d5ac4 | 3251 | (define_insn "flag_mulhi_parts" |
a0a31d1e | 3252 | [(set (match_operand:HI 0 "register_operand" "=d") |
1d7d5ac4 BS |
3253 | (unspec:HI [(vec_select:HI |
3254 | (match_operand:V2HI 1 "register_operand" "d") | |
a0a31d1e | 3255 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
1d7d5ac4 BS |
3256 | (vec_select:HI |
3257 | (match_operand:V2HI 2 "register_operand" "d") | |
a0a31d1e BS |
3258 | (parallel [(match_operand 4 "const01_operand" "P0P1")])) |
3259 | (match_operand 5 "const_int_operand" "n")] | |
1d7d5ac4 BS |
3260 | UNSPEC_MUL_WITH_FLAG))] |
3261 | "" | |
3262 | { | |
3263 | const char *templates[] = { | |
a0a31d1e BS |
3264 | "%h0 = %h1 * %h2 %M5%!", |
3265 | "%h0 = %d1 * %h2 %M5%!", | |
3266 | "%h0 = %h1 * %d2 %M5%!", | |
3267 | "%h0 = %d1 * %d2 %M5%!" }; | |
3268 | int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1); | |
1d7d5ac4 BS |
3269 | return templates[alt]; |
3270 | } | |
3271 | [(set_attr "type" "dsp32")]) | |
3272 | ||
75d8b2d0 BS |
3273 | (define_insn "flag_mulhisi" |
3274 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3275 | (unspec:SI [(match_operand:HI 1 "register_operand" "d") | |
3276 | (match_operand:HI 2 "register_operand" "d") | |
3277 | (match_operand 3 "const_int_operand" "n")] | |
3278 | UNSPEC_MUL_WITH_FLAG))] | |
3279 | "" | |
bbbc206e | 3280 | "%0 = %h1 * %h2 %M3%!" |
75d8b2d0 BS |
3281 | [(set_attr "type" "dsp32")]) |
3282 | ||
3283 | (define_insn "flag_mulhisi_parts" | |
3284 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3285 | (unspec:SI [(vec_select:HI | |
3286 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3287 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3288 | (vec_select:HI |
3289 | (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3290 | (parallel [(match_operand 4 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3291 | (match_operand 5 "const_int_operand" "n")] |
3292 | UNSPEC_MUL_WITH_FLAG))] | |
3293 | "" | |
3294 | { | |
3295 | const char *templates[] = { | |
bbbc206e BS |
3296 | "%0 = %h1 * %h2 %M5%!", |
3297 | "%0 = %d1 * %h2 %M5%!", | |
3298 | "%0 = %h1 * %d2 %M5%!", | |
3299 | "%0 = %d1 * %d2 %M5%!" }; | |
75d8b2d0 BS |
3300 | int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1); |
3301 | return templates[alt]; | |
3302 | } | |
3303 | [(set_attr "type" "dsp32")]) | |
3304 | ||
3efd5670 BS |
3305 | ;; Three alternatives here to cover all possible allocations: |
3306 | ;; 0. mac flag is usable only for accumulator 1 - use A1 and odd DREG | |
3307 | ;; 1. mac flag is usable for accumulator 0 - use A0 and even DREG | |
3308 | ;; 2. mac flag is usable in any accumulator - use A1 and odd DREG | |
3309 | ;; Other patterns which don't have a DREG destination can collapse cases | |
3310 | ;; 1 and 2 into one. | |
75d8b2d0 | 3311 | (define_insn "flag_machi" |
3efd5670 BS |
3312 | [(set (match_operand:HI 0 "register_operand" "=W,D,W") |
3313 | (unspec:HI [(match_operand:HI 2 "register_operand" "d,d,d") | |
3314 | (match_operand:HI 3 "register_operand" "d,d,d") | |
3315 | (match_operand 4 "register_operand" "1,1,1") | |
3316 | (match_operand 5 "const01_operand" "P0P1,P0P1,P0P1") | |
3317 | (match_operand 6 "const_int_operand" "PB,PA,PA")] | |
75d8b2d0 | 3318 | UNSPEC_MAC_WITH_FLAG)) |
3efd5670 | 3319 | (set (match_operand:PDI 1 "register_operand" "=B,A,B") |
75d8b2d0 BS |
3320 | (unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3) |
3321 | (match_dup 4) (match_dup 5)] | |
3322 | UNSPEC_MAC_WITH_FLAG))] | |
3323 | "" | |
3efd5670 | 3324 | "%h0 = (%1 %b5 %h2 * %h3) %M6%!" |
75d8b2d0 BS |
3325 | [(set_attr "type" "dsp32")]) |
3326 | ||
3327 | (define_insn "flag_machi_acconly" | |
3efd5670 BS |
3328 | [(set (match_operand:PDI 0 "register_operand" "=B,e") |
3329 | (unspec:PDI [(match_operand:HI 1 "register_operand" "d,d") | |
3330 | (match_operand:HI 2 "register_operand" "d,d") | |
3331 | (match_operand 3 "register_operand" "0,0") | |
3332 | (match_operand 4 "const01_operand" "P0P1,P0P1") | |
3333 | (match_operand 5 "const_int_operand" "PB,PA")] | |
75d8b2d0 BS |
3334 | UNSPEC_MAC_WITH_FLAG))] |
3335 | "" | |
3efd5670 BS |
3336 | "%0 %b4 %h1 * %h2 %M5%!" |
3337 | [(set_attr "type" "dsp32")]) | |
3338 | ||
3339 | (define_insn "flag_machi_parts_acconly" | |
3340 | [(set (match_operand:PDI 0 "register_operand" "=B,e") | |
3341 | (unspec:PDI [(vec_select:HI | |
3342 | (match_operand:V2HI 1 "register_operand" "d,d") | |
3343 | (parallel [(match_operand 3 "const01_operand" "P0P1,P0P1")])) | |
3344 | (vec_select:HI | |
3345 | (match_operand:V2HI 2 "register_operand" "d,d") | |
3346 | (parallel [(match_operand 4 "const01_operand" "P0P1,P0P1")])) | |
3347 | (match_operand:PDI 5 "register_operand" "0,0") | |
3348 | (match_operand 6 "const01_operand" "P0P1,P0P1") | |
3349 | (match_operand 7 "const_int_operand" "PB,PA")] | |
3350 | UNSPEC_MAC_WITH_FLAG))] | |
3351 | "" | |
3352 | { | |
3353 | const char *templates[] = { | |
3354 | "%0 %b6 %h1 * %h2 %M7%!", | |
3355 | "%0 %b6 %d1 * %h2 %M7%!", | |
3356 | "%0 %b6 %h1 * %d2 %M7%!", | |
3357 | "%0 %b6 %d1 * %d2 %M7%!" | |
3358 | }; | |
3359 | int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1); | |
3360 | return templates[alt]; | |
3361 | } | |
75d8b2d0 BS |
3362 | [(set_attr "type" "dsp32")]) |
3363 | ||
3364 | (define_insn "flag_macinithi" | |
3efd5670 BS |
3365 | [(set (match_operand:HI 0 "register_operand" "=W,D,W") |
3366 | (unspec:HI [(match_operand:HI 1 "register_operand" "d,d,d") | |
3367 | (match_operand:HI 2 "register_operand" "d,d,d") | |
3368 | (match_operand 3 "const_int_operand" "PB,PA,PA")] | |
75d8b2d0 | 3369 | UNSPEC_MAC_WITH_FLAG)) |
3efd5670 | 3370 | (set (match_operand:PDI 4 "register_operand" "=B,A,B") |
75d8b2d0 BS |
3371 | (unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3)] |
3372 | UNSPEC_MAC_WITH_FLAG))] | |
3373 | "" | |
3efd5670 | 3374 | "%h0 = (%4 = %h1 * %h2) %M3%!" |
75d8b2d0 BS |
3375 | [(set_attr "type" "dsp32")]) |
3376 | ||
3377 | (define_insn "flag_macinit1hi" | |
3efd5670 BS |
3378 | [(set (match_operand:PDI 0 "register_operand" "=B,e") |
3379 | (unspec:PDI [(match_operand:HI 1 "register_operand" "d,d") | |
3380 | (match_operand:HI 2 "register_operand" "d,d") | |
3381 | (match_operand 3 "const_int_operand" "PB,PA")] | |
75d8b2d0 BS |
3382 | UNSPEC_MAC_WITH_FLAG))] |
3383 | "" | |
bbbc206e | 3384 | "%0 = %h1 * %h2 %M3%!" |
75d8b2d0 BS |
3385 | [(set_attr "type" "dsp32")]) |
3386 | ||
c9b3f817 | 3387 | (define_insn "mulv2hi3" |
0d4a78eb BS |
3388 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
3389 | (mult:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
3390 | (match_operand:V2HI 2 "register_operand" "d")))] | |
3391 | "" | |
bbbc206e | 3392 | "%h0 = %h1 * %h2, %d0 = %d1 * %d2 (IS)%!" |
0d4a78eb BS |
3393 | [(set_attr "type" "dsp32")]) |
3394 | ||
75d8b2d0 BS |
3395 | (define_insn "flag_mulv2hi" |
3396 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3397 | (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d") | |
3398 | (match_operand:V2HI 2 "register_operand" "d") | |
3399 | (match_operand 3 "const_int_operand" "n")] | |
3400 | UNSPEC_MUL_WITH_FLAG))] | |
3401 | "" | |
bbbc206e | 3402 | "%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M3%!" |
75d8b2d0 BS |
3403 | [(set_attr "type" "dsp32")]) |
3404 | ||
3405 | (define_insn "flag_mulv2hi_parts" | |
3406 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3407 | (unspec:V2HI [(vec_concat:V2HI | |
3408 | (vec_select:HI | |
3409 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3410 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3411 | (vec_select:HI |
3412 | (match_dup 1) | |
554006bd | 3413 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3414 | (vec_concat:V2HI |
3415 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3416 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3417 | (vec_select:HI (match_dup 2) |
554006bd | 3418 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3419 | (match_operand 7 "const_int_operand" "n")] |
3420 | UNSPEC_MUL_WITH_FLAG))] | |
3421 | "" | |
3422 | { | |
3423 | const char *templates[] = { | |
bbbc206e BS |
3424 | "%h0 = %h1 * %h2, %d0 = %h1 * %h2 %M7%!", |
3425 | "%h0 = %d1 * %h2, %d0 = %h1 * %h2 %M7%!", | |
3426 | "%h0 = %h1 * %h2, %d0 = %d1 * %h2 %M7%!", | |
3427 | "%h0 = %d1 * %h2, %d0 = %d1 * %h2 %M7%!", | |
3428 | "%h0 = %h1 * %d2, %d0 = %h1 * %h2 %M7%!", | |
3429 | "%h0 = %d1 * %d2, %d0 = %h1 * %h2 %M7%!", | |
3430 | "%h0 = %h1 * %d2, %d0 = %d1 * %h2 %M7%!", | |
3431 | "%h0 = %d1 * %d2, %d0 = %d1 * %h2 %M7%!", | |
3432 | "%h0 = %h1 * %h2, %d0 = %h1 * %d2 %M7%!", | |
3433 | "%h0 = %d1 * %h2, %d0 = %h1 * %d2 %M7%!", | |
3434 | "%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M7%!", | |
3435 | "%h0 = %d1 * %h2, %d0 = %d1 * %d2 %M7%!", | |
3436 | "%h0 = %h1 * %d2, %d0 = %h1 * %d2 %M7%!", | |
3437 | "%h0 = %d1 * %d2, %d0 = %h1 * %d2 %M7%!", | |
3438 | "%h0 = %h1 * %d2, %d0 = %d1 * %d2 %M7%!", | |
3439 | "%h0 = %d1 * %d2, %d0 = %d1 * %d2 %M7%!" }; | |
75d8b2d0 BS |
3440 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3441 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3442 | return templates[alt]; | |
3443 | } | |
3444 | [(set_attr "type" "dsp32")]) | |
3445 | ||
3446 | ;; A slightly complicated pattern. | |
3447 | ;; Operand 0 is the halfword output; operand 11 is the accumulator output | |
3448 | ;; Halfword inputs are operands 1 and 2; operands 3, 4, 5 and 6 specify which | |
3449 | ;; parts of these 2x16 bit registers to use. | |
3450 | ;; Operand 7 is the accumulator input. | |
3451 | ;; Operands 8/9 specify whether low/high parts are mac (0) or msu (1) | |
3452 | ;; Operand 10 is the macflag to be used. | |
3453 | (define_insn "flag_macv2hi_parts" | |
3454 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3455 | (unspec:V2HI [(vec_concat:V2HI | |
3456 | (vec_select:HI | |
3457 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3458 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3459 | (vec_select:HI |
3460 | (match_dup 1) | |
554006bd | 3461 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3462 | (vec_concat:V2HI |
3463 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3464 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3465 | (vec_select:HI (match_dup 2) |
554006bd | 3466 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3467 | (match_operand:V2PDI 7 "register_operand" "e") |
3468 | (match_operand 8 "const01_operand" "P0P1") | |
3469 | (match_operand 9 "const01_operand" "P0P1") | |
3470 | (match_operand 10 "const_int_operand" "n")] | |
3471 | UNSPEC_MAC_WITH_FLAG)) | |
3472 | (set (match_operand:V2PDI 11 "register_operand" "=e") | |
3473 | (unspec:V2PDI [(vec_concat:V2HI | |
3474 | (vec_select:HI (match_dup 1) (parallel [(match_dup 3)])) | |
3475 | (vec_select:HI (match_dup 1) (parallel [(match_dup 4)]))) | |
3476 | (vec_concat:V2HI | |
3477 | (vec_select:HI (match_dup 2) (parallel [(match_dup 5)])) | |
3478 | (vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))) | |
3479 | (match_dup 7) (match_dup 8) (match_dup 9) (match_dup 10)] | |
3480 | UNSPEC_MAC_WITH_FLAG))] | |
3481 | "" | |
3482 | { | |
3483 | const char *templates[] = { | |
bbbc206e BS |
3484 | "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10%!", |
3485 | "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10%!", | |
3486 | "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10%!", | |
3487 | "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10%!", | |
3488 | "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10%!", | |
3489 | "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10%!", | |
3490 | "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10%!", | |
3491 | "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10%!", | |
3492 | "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10%!", | |
3493 | "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10%!", | |
3494 | "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10%!", | |
3495 | "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10%!", | |
3496 | "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10%!", | |
3497 | "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10%!", | |
3498 | "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10%!", | |
3499 | "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10%!" }; | |
75d8b2d0 BS |
3500 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3501 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3502 | return templates[alt]; | |
3503 | } | |
3504 | [(set_attr "type" "dsp32")]) | |
3505 | ||
3506 | (define_insn "flag_macv2hi_parts_acconly" | |
3507 | [(set (match_operand:V2PDI 0 "register_operand" "=e") | |
3508 | (unspec:V2PDI [(vec_concat:V2HI | |
3509 | (vec_select:HI | |
3510 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3511 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3512 | (vec_select:HI |
3513 | (match_dup 1) | |
554006bd | 3514 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3515 | (vec_concat:V2HI |
3516 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3517 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3518 | (vec_select:HI (match_dup 2) |
554006bd | 3519 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3520 | (match_operand:V2PDI 7 "register_operand" "e") |
3521 | (match_operand 8 "const01_operand" "P0P1") | |
3522 | (match_operand 9 "const01_operand" "P0P1") | |
3523 | (match_operand 10 "const_int_operand" "n")] | |
3524 | UNSPEC_MAC_WITH_FLAG))] | |
3525 | "" | |
3526 | { | |
3527 | const char *templates[] = { | |
bbbc206e BS |
3528 | "A0 %b8 %h1 * %h2, A1 %b9 %h1 * %h2 %M10%!", |
3529 | "A0 %b8 %d1 * %h2, A1 %b9 %h1 * %h2 %M10%!", | |
3530 | "A0 %b8 %h1 * %h2, A1 %b9 %d1 * %h2 %M10%!", | |
3531 | "A0 %b8 %d1 * %h2, A1 %b9 %d1 * %h2 %M10%!", | |
3532 | "A0 %b8 %h1 * %d2, A1 %b9 %h1 * %h2 %M10%!", | |
3533 | "A0 %b8 %d1 * %d2, A1 %b9 %h1 * %h2 %M10%!", | |
3534 | "A0 %b8 %h1 * %d2, A1 %b9 %d1 * %h2 %M10%!", | |
3535 | "A0 %b8 %d1 * %d2, A1 %b9 %d1 * %h2 %M10%!", | |
3536 | "A0 %b8 %h1 * %h2, A1 %b9 %h1 * %d2 %M10%!", | |
3537 | "A0 %b8 %d1 * %h2, A1 %b9 %h1 * %d2 %M10%!", | |
3538 | "A0 %b8 %h1 * %h2, A1 %b9 %d1 * %d2 %M10%!", | |
3539 | "A0 %b8 %d1 * %h2, A1 %b9 %d1 * %d2 %M10%!", | |
3540 | "A0 %b8 %h1 * %d2, A1 %b9 %h1 * %d2 %M10%!", | |
3541 | "A0 %b8 %d1 * %d2, A1 %b9 %h1 * %d2 %M10%!", | |
3542 | "A0 %b8 %h1 * %d2, A1 %b9 %d1 * %d2 %M10%!", | |
3543 | "A0 %b8 %d1 * %d2, A1 %b9 %d1 * %d2 %M10%!" }; | |
75d8b2d0 BS |
3544 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3545 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3546 | return templates[alt]; | |
3547 | } | |
3548 | [(set_attr "type" "dsp32")]) | |
3549 | ||
3550 | ;; Same as above, but initializing the accumulators and therefore a couple fewer | |
3551 | ;; necessary operands. | |
3552 | (define_insn "flag_macinitv2hi_parts" | |
0d4a78eb | 3553 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
75d8b2d0 BS |
3554 | (unspec:V2HI [(vec_concat:V2HI |
3555 | (vec_select:HI | |
3556 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3557 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3558 | (vec_select:HI |
3559 | (match_dup 1) | |
554006bd | 3560 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3561 | (vec_concat:V2HI |
3562 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3563 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3564 | (vec_select:HI (match_dup 2) |
554006bd | 3565 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3566 | (match_operand 7 "const_int_operand" "n")] |
3567 | UNSPEC_MAC_WITH_FLAG)) | |
3568 | (set (match_operand:V2PDI 8 "register_operand" "=e") | |
3569 | (unspec:V2PDI [(vec_concat:V2HI | |
3570 | (vec_select:HI (match_dup 1) (parallel [(match_dup 3)])) | |
3571 | (vec_select:HI (match_dup 1) (parallel [(match_dup 4)]))) | |
3572 | (vec_concat:V2HI | |
3573 | (vec_select:HI (match_dup 2) (parallel [(match_dup 5)])) | |
3574 | (vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))) | |
3575 | (match_dup 7)] | |
3576 | UNSPEC_MAC_WITH_FLAG))] | |
3577 | "" | |
3578 | { | |
3579 | const char *templates[] = { | |
bbbc206e BS |
3580 | "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %h2) %M7%!", |
3581 | "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %h2) %M7%!", | |
3582 | "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %h2) %M7%!", | |
3583 | "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %h2) %M7%!", | |
3584 | "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %h2) %M7%!", | |
3585 | "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %h2) %M7%!", | |
3586 | "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %h2) %M7%!", | |
3587 | "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %h2) %M7%!", | |
3588 | "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %d2) %M7%!", | |
3589 | "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %d2) %M7%!", | |
3590 | "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %d2) %M7%!", | |
3591 | "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %d2) %M7%!", | |
3592 | "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %d2) %M7%!", | |
3593 | "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %d2) %M7%!", | |
3594 | "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %d2) %M7%!", | |
3595 | "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %d2) %M7%!" }; | |
75d8b2d0 BS |
3596 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3597 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3598 | return templates[alt]; | |
3599 | } | |
3600 | [(set_attr "type" "dsp32")]) | |
3601 | ||
3602 | (define_insn "flag_macinit1v2hi_parts" | |
3603 | [(set (match_operand:V2PDI 0 "register_operand" "=e") | |
3604 | (unspec:V2PDI [(vec_concat:V2HI | |
3605 | (vec_select:HI | |
3606 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3607 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3608 | (vec_select:HI |
3609 | (match_dup 1) | |
554006bd | 3610 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3611 | (vec_concat:V2HI |
3612 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3613 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3614 | (vec_select:HI (match_dup 2) |
554006bd | 3615 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3616 | (match_operand 7 "const_int_operand" "n")] |
3617 | UNSPEC_MAC_WITH_FLAG))] | |
3618 | "" | |
3619 | { | |
3620 | const char *templates[] = { | |
bbbc206e BS |
3621 | "A0 = %h1 * %h2, A1 = %h1 * %h2 %M7%!", |
3622 | "A0 = %d1 * %h2, A1 = %h1 * %h2 %M7%!", | |
3623 | "A0 = %h1 * %h2, A1 = %d1 * %h2 %M7%!", | |
3624 | "A0 = %d1 * %h2, A1 = %d1 * %h2 %M7%!", | |
3625 | "A0 = %h1 * %d2, A1 = %h1 * %h2 %M7%!", | |
3626 | "A0 = %d1 * %d2, A1 = %h1 * %h2 %M7%!", | |
3627 | "A0 = %h1 * %d2, A1 = %d1 * %h2 %M7%!", | |
3628 | "A0 = %d1 * %d2, A1 = %d1 * %h2 %M7%!", | |
3629 | "A0 = %h1 * %h2, A1 = %h1 * %d2 %M7%!", | |
3630 | "A0 = %d1 * %h2, A1 = %h1 * %d2 %M7%!", | |
3631 | "A0 = %h1 * %h2, A1 = %d1 * %d2 %M7%!", | |
3632 | "A0 = %d1 * %h2, A1 = %d1 * %d2 %M7%!", | |
3633 | "A0 = %h1 * %d2, A1 = %h1 * %d2 %M7%!", | |
3634 | "A0 = %d1 * %d2, A1 = %h1 * %d2 %M7%!", | |
3635 | "A0 = %h1 * %d2, A1 = %d1 * %d2 %M7%!", | |
3636 | "A0 = %d1 * %d2, A1 = %d1 * %d2 %M7%!" }; | |
75d8b2d0 BS |
3637 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3638 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3639 | return templates[alt]; | |
3640 | } | |
3641 | [(set_attr "type" "dsp32")]) | |
3642 | ||
3efd5670 BS |
3643 | ;; A mixture of multiply and multiply-accumulate for when we only want to |
3644 | ;; initialize one part. | |
3645 | (define_insn "flag_mul_macv2hi_parts_acconly" | |
3646 | [(set (match_operand:PDI 0 "register_operand" "=B,e,e") | |
3647 | (unspec:PDI [(vec_select:HI | |
3648 | (match_operand:V2HI 2 "register_operand" "d,d,d") | |
3649 | (parallel [(match_operand 4 "const01_operand" "P0P1,P0P1,P0P1")])) | |
3650 | (vec_select:HI | |
3651 | (match_operand:V2HI 3 "register_operand" "d,d,d") | |
3652 | (parallel [(match_operand 6 "const01_operand" "P0P1,P0P1,P0P1")])) | |
3653 | (match_operand 10 "const_int_operand" "PB,PA,PA")] | |
3654 | UNSPEC_MUL_WITH_FLAG)) | |
3655 | (set (match_operand:PDI 1 "register_operand" "=B,e,e") | |
3656 | (unspec:PDI [(vec_select:HI | |
3657 | (match_dup 2) | |
3658 | (parallel [(match_operand 5 "const01_operand" "P0P1,P0P1,P0P1")])) | |
3659 | (vec_select:HI | |
3660 | (match_dup 3) | |
3661 | (parallel [(match_operand 7 "const01_operand" "P0P1,P0P1,P0P1")])) | |
3662 | (match_operand:PDI 8 "register_operand" "1,1,1") | |
3663 | (match_operand 9 "const01_operand" "P0P1,P0P1,P0P1") | |
3664 | (match_operand 11 "const_int_operand" "PA,PB,PA")] | |
3665 | UNSPEC_MAC_WITH_FLAG))] | |
3666 | "MACFLAGS_MATCH_P (INTVAL (operands[10]), INTVAL (operands[11]))" | |
3667 | { | |
3668 | rtx xops[6]; | |
3669 | const char *templates[] = { | |
3670 | "%0 = %h2 * %h3, %1 %b4 %h2 * %h3 %M5%!", | |
3671 | "%0 = %d2 * %h3, %1 %b4 %h2 * %h3 %M5%!", | |
3672 | "%0 = %h2 * %h3, %1 %b4 %d2 * %h3 %M5%!", | |
3673 | "%0 = %d2 * %h3, %1 %b4 %d2 * %h3 %M5%!", | |
3674 | "%0 = %h2 * %d3, %1 %b4 %h2 * %h3 %M5%!", | |
3675 | "%0 = %d2 * %d3, %1 %b4 %h2 * %h3 %M5%!", | |
3676 | "%0 = %h2 * %d3, %1 %b4 %d2 * %h3 %M5%!", | |
3677 | "%0 = %d2 * %d3, %1 %b4 %d2 * %h3 %M5%!", | |
3678 | "%0 = %h2 * %h3, %1 %b4 %h2 * %d3 %M5%!", | |
3679 | "%0 = %d2 * %h3, %1 %b4 %h2 * %d3 %M5%!", | |
3680 | "%0 = %h2 * %h3, %1 %b4 %d2 * %d3 %M5%!", | |
3681 | "%0 = %d2 * %h3, %1 %b4 %d2 * %d3 %M5%!", | |
3682 | "%0 = %h2 * %d3, %1 %b4 %h2 * %d3 %M5%!", | |
3683 | "%0 = %d2 * %d3, %1 %b4 %h2 * %d3 %M5%!", | |
3684 | "%0 = %h2 * %d3, %1 %b4 %d2 * %d3 %M5%!", | |
3685 | "%0 = %d2 * %d3, %1 %b4 %d2 * %d3 %M5%!" }; | |
3686 | int alt = (INTVAL (operands[4]) + (INTVAL (operands[5]) << 1) | |
3687 | + (INTVAL (operands[6]) << 2) + (INTVAL (operands[7]) << 3)); | |
3688 | xops[0] = operands[0]; | |
3689 | xops[1] = operands[1]; | |
3690 | xops[2] = operands[2]; | |
3691 | xops[3] = operands[3]; | |
3692 | xops[4] = operands[9]; | |
3693 | xops[5] = which_alternative == 0 ? operands[10] : operands[11]; | |
3694 | output_asm_insn (templates[alt], xops); | |
3695 | return ""; | |
3696 | } | |
3697 | [(set_attr "type" "dsp32")]) | |
3698 | ||
3699 | ||
3abcb3a7 | 3700 | (define_code_iterator s_or_u [sign_extend zero_extend]) |
2889abed BS |
3701 | (define_code_attr su_optab [(sign_extend "mul") |
3702 | (zero_extend "umul")]) | |
3703 | (define_code_attr su_modifier [(sign_extend "IS") | |
3704 | (zero_extend "FU")]) | |
3705 | ||
3706 | (define_insn "<su_optab>hisi_ll" | |
75d8b2d0 | 3707 | [(set (match_operand:SI 0 "register_operand" "=d") |
2889abed | 3708 | (mult:SI (s_or_u:SI |
75d8b2d0 BS |
3709 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d") |
3710 | (parallel [(const_int 0)]))) | |
2889abed | 3711 | (s_or_u:SI |
75d8b2d0 BS |
3712 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") |
3713 | (parallel [(const_int 0)])))))] | |
3714 | "" | |
2889abed | 3715 | "%0 = %h1 * %h2 (<su_modifier>)%!" |
75d8b2d0 BS |
3716 | [(set_attr "type" "dsp32")]) |
3717 | ||
2889abed | 3718 | (define_insn "<su_optab>hisi_lh" |
75d8b2d0 | 3719 | [(set (match_operand:SI 0 "register_operand" "=d") |
2889abed BS |
3720 | (mult:SI (s_or_u:SI |
3721 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
75d8b2d0 | 3722 | (parallel [(const_int 0)]))) |
2889abed | 3723 | (s_or_u:SI |
75d8b2d0 BS |
3724 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") |
3725 | (parallel [(const_int 1)])))))] | |
3726 | "" | |
2889abed | 3727 | "%0 = %h1 * %d2 (<su_modifier>)%!" |
75d8b2d0 BS |
3728 | [(set_attr "type" "dsp32")]) |
3729 | ||
2889abed | 3730 | (define_insn "<su_optab>hisi_hl" |
75d8b2d0 | 3731 | [(set (match_operand:SI 0 "register_operand" "=d") |
2889abed BS |
3732 | (mult:SI (s_or_u:SI |
3733 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3734 | (parallel [(const_int 1)]))) | |
3735 | (s_or_u:SI | |
3736 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3737 | (parallel [(const_int 0)])))))] | |
3738 | "" | |
3739 | "%0 = %d1 * %h2 (<su_modifier>)%!" | |
3740 | [(set_attr "type" "dsp32")]) | |
3741 | ||
3742 | (define_insn "<su_optab>hisi_hh" | |
3743 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3744 | (mult:SI (s_or_u:SI | |
75d8b2d0 BS |
3745 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d") |
3746 | (parallel [(const_int 1)]))) | |
2889abed BS |
3747 | (s_or_u:SI |
3748 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3749 | (parallel [(const_int 1)])))))] | |
3750 | "" | |
3751 | "%0 = %d1 * %d2 (<su_modifier>)%!" | |
3752 | [(set_attr "type" "dsp32")]) | |
3753 | ||
3754 | ;; Additional variants for signed * unsigned multiply. | |
3755 | ||
3756 | (define_insn "usmulhisi_ull" | |
3757 | [(set (match_operand:SI 0 "register_operand" "=W") | |
3758 | (mult:SI (zero_extend:SI | |
3759 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d") | |
3760 | (parallel [(const_int 0)]))) | |
75d8b2d0 BS |
3761 | (sign_extend:SI |
3762 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3763 | (parallel [(const_int 0)])))))] | |
3764 | "" | |
2889abed | 3765 | "%0 = %h2 * %h1 (IS,M)%!" |
75d8b2d0 BS |
3766 | [(set_attr "type" "dsp32")]) |
3767 | ||
2889abed BS |
3768 | (define_insn "usmulhisi_ulh" |
3769 | [(set (match_operand:SI 0 "register_operand" "=W") | |
3770 | (mult:SI (zero_extend:SI | |
3771 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3772 | (parallel [(const_int 0)]))) | |
3773 | (sign_extend:SI | |
3774 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3775 | (parallel [(const_int 1)])))))] | |
3776 | "" | |
3777 | "%0 = %d2 * %h1 (IS,M)%!" | |
3778 | [(set_attr "type" "dsp32")]) | |
3779 | ||
3780 | (define_insn "usmulhisi_uhl" | |
3781 | [(set (match_operand:SI 0 "register_operand" "=W") | |
3782 | (mult:SI (zero_extend:SI | |
3783 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3784 | (parallel [(const_int 1)]))) | |
3785 | (sign_extend:SI | |
3786 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3787 | (parallel [(const_int 0)])))))] | |
3788 | "" | |
3789 | "%0 = %h2 * %d1 (IS,M)%!" | |
3790 | [(set_attr "type" "dsp32")]) | |
3791 | ||
3792 | (define_insn "usmulhisi_uhh" | |
3793 | [(set (match_operand:SI 0 "register_operand" "=W") | |
3794 | (mult:SI (zero_extend:SI | |
75d8b2d0 BS |
3795 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d") |
3796 | (parallel [(const_int 1)]))) | |
3797 | (sign_extend:SI | |
3798 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3799 | (parallel [(const_int 1)])))))] | |
3800 | "" | |
2889abed BS |
3801 | "%0 = %d2 * %d1 (IS,M)%!" |
3802 | [(set_attr "type" "dsp32")]) | |
3803 | ||
3804 | ;; Parallel versions of these operations. First, normal signed or unsigned | |
3805 | ;; multiplies. | |
3806 | ||
3807 | (define_insn "<su_optab>hisi_ll_lh" | |
3808 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3809 | (mult:SI (s_or_u:SI | |
3810 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3811 | (parallel [(const_int 0)]))) | |
3812 | (s_or_u:SI | |
3813 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3814 | (parallel [(const_int 0)]))))) | |
3815 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3816 | (mult:SI (s_or_u:SI | |
3817 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3818 | (s_or_u:SI | |
3819 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3820 | "" | |
3821 | "%0 = %h1 * %h2, %3 = %h1 * %d2 (<su_modifier>)%!" | |
3822 | [(set_attr "type" "dsp32")]) | |
3823 | ||
3824 | (define_insn "<su_optab>hisi_ll_hl" | |
3825 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3826 | (mult:SI (s_or_u:SI | |
3827 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3828 | (parallel [(const_int 0)]))) | |
3829 | (s_or_u:SI | |
3830 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3831 | (parallel [(const_int 0)]))))) | |
3832 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3833 | (mult:SI (s_or_u:SI | |
3834 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3835 | (s_or_u:SI | |
3836 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3837 | "" | |
3838 | "%0 = %h1 * %h2, %3 = %d1 * %h2 (<su_modifier>)%!" | |
3839 | [(set_attr "type" "dsp32")]) | |
3840 | ||
3841 | (define_insn "<su_optab>hisi_ll_hh" | |
3842 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3843 | (mult:SI (s_or_u:SI | |
3844 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3845 | (parallel [(const_int 0)]))) | |
3846 | (s_or_u:SI | |
3847 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3848 | (parallel [(const_int 0)]))))) | |
3849 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3850 | (mult:SI (s_or_u:SI | |
3851 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3852 | (s_or_u:SI | |
3853 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3854 | "" | |
3855 | "%0 = %h1 * %h2, %3 = %d1 * %d2 (<su_modifier>)%!" | |
3856 | [(set_attr "type" "dsp32")]) | |
3857 | ||
3858 | (define_insn "<su_optab>hisi_lh_hl" | |
3859 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3860 | (mult:SI (s_or_u:SI | |
3861 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3862 | (parallel [(const_int 0)]))) | |
3863 | (s_or_u:SI | |
3864 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3865 | (parallel [(const_int 1)]))))) | |
3866 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3867 | (mult:SI (s_or_u:SI | |
3868 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3869 | (s_or_u:SI | |
3870 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3871 | "" | |
3872 | "%0 = %h1 * %d2, %3 = %d1 * %h2 (<su_modifier>)%!" | |
3873 | [(set_attr "type" "dsp32")]) | |
3874 | ||
3875 | (define_insn "<su_optab>hisi_lh_hh" | |
3876 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3877 | (mult:SI (s_or_u:SI | |
3878 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3879 | (parallel [(const_int 0)]))) | |
3880 | (s_or_u:SI | |
3881 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3882 | (parallel [(const_int 1)]))))) | |
3883 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3884 | (mult:SI (s_or_u:SI | |
3885 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3886 | (s_or_u:SI | |
3887 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3888 | "" | |
3889 | "%0 = %h1 * %d2, %3 = %d1 * %d2 (<su_modifier>)%!" | |
3890 | [(set_attr "type" "dsp32")]) | |
3891 | ||
3892 | (define_insn "<su_optab>hisi_hl_hh" | |
3893 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3894 | (mult:SI (s_or_u:SI | |
3895 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3896 | (parallel [(const_int 1)]))) | |
3897 | (s_or_u:SI | |
3898 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3899 | (parallel [(const_int 0)]))))) | |
3900 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3901 | (mult:SI (s_or_u:SI | |
3902 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3903 | (s_or_u:SI | |
3904 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3905 | "" | |
3906 | "%0 = %d1 * %h2, %3 = %d1 * %d2 (<su_modifier>)%!" | |
3907 | [(set_attr "type" "dsp32")]) | |
3908 | ||
3909 | ;; Special signed * unsigned variants. | |
3910 | ||
3911 | (define_insn "usmulhisi_ll_lul" | |
3912 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3913 | (mult:SI (sign_extend:SI | |
3914 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3915 | (parallel [(const_int 0)]))) | |
3916 | (sign_extend:SI | |
3917 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3918 | (parallel [(const_int 0)]))))) | |
3919 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3920 | (mult:SI (sign_extend:SI | |
3921 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3922 | (zero_extend:SI | |
3923 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3924 | "" | |
3925 | "%0 = %h1 * %h2, %3 = %h1 * %h2 (IS,M)%!" | |
3926 | [(set_attr "type" "dsp32")]) | |
3927 | ||
3928 | (define_insn "usmulhisi_ll_luh" | |
3929 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3930 | (mult:SI (sign_extend:SI | |
3931 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3932 | (parallel [(const_int 0)]))) | |
3933 | (sign_extend:SI | |
3934 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3935 | (parallel [(const_int 0)]))))) | |
3936 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3937 | (mult:SI (sign_extend:SI | |
3938 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3939 | (zero_extend:SI | |
3940 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3941 | "" | |
3942 | "%0 = %h1 * %h2, %3 = %h1 * %d2 (IS,M)%!" | |
3943 | [(set_attr "type" "dsp32")]) | |
3944 | ||
3945 | (define_insn "usmulhisi_ll_hul" | |
3946 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3947 | (mult:SI (sign_extend:SI | |
3948 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3949 | (parallel [(const_int 0)]))) | |
3950 | (sign_extend:SI | |
3951 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3952 | (parallel [(const_int 0)]))))) | |
3953 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3954 | (mult:SI (sign_extend:SI | |
3955 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3956 | (zero_extend:SI | |
3957 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3958 | "" | |
3959 | "%0 = %h1 * %h2, %3 = %d1 * %h2 (IS,M)%!" | |
3960 | [(set_attr "type" "dsp32")]) | |
3961 | ||
3962 | (define_insn "usmulhisi_ll_huh" | |
3963 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3964 | (mult:SI (sign_extend:SI | |
3965 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3966 | (parallel [(const_int 0)]))) | |
3967 | (sign_extend:SI | |
3968 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3969 | (parallel [(const_int 0)]))))) | |
3970 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3971 | (mult:SI (sign_extend:SI | |
3972 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3973 | (zero_extend:SI | |
3974 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3975 | "" | |
3976 | "%0 = %h1 * %h2, %3 = %d1 * %d2 (IS,M)%!" | |
3977 | [(set_attr "type" "dsp32")]) | |
3978 | ||
3979 | (define_insn "usmulhisi_lh_lul" | |
3980 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3981 | (mult:SI (sign_extend:SI | |
3982 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3983 | (parallel [(const_int 0)]))) | |
3984 | (sign_extend:SI | |
3985 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3986 | (parallel [(const_int 1)]))))) | |
3987 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3988 | (mult:SI (sign_extend:SI | |
3989 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3990 | (zero_extend:SI | |
3991 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3992 | "" | |
3993 | "%0 = %h1 * %d2, %3 = %h1 * %h2 (IS,M)%!" | |
3994 | [(set_attr "type" "dsp32")]) | |
3995 | ||
3996 | (define_insn "usmulhisi_lh_luh" | |
3997 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3998 | (mult:SI (sign_extend:SI | |
3999 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4000 | (parallel [(const_int 0)]))) | |
4001 | (sign_extend:SI | |
4002 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4003 | (parallel [(const_int 1)]))))) | |
4004 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4005 | (mult:SI (sign_extend:SI | |
4006 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
4007 | (zero_extend:SI | |
4008 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
4009 | "" | |
4010 | "%0 = %h1 * %d2, %3 = %h1 * %d2 (IS,M)%!" | |
4011 | [(set_attr "type" "dsp32")]) | |
4012 | ||
4013 | (define_insn "usmulhisi_lh_hul" | |
4014 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
4015 | (mult:SI (sign_extend:SI | |
4016 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4017 | (parallel [(const_int 0)]))) | |
4018 | (sign_extend:SI | |
4019 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4020 | (parallel [(const_int 1)]))))) | |
4021 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4022 | (mult:SI (sign_extend:SI | |
4023 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
4024 | (zero_extend:SI | |
4025 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
4026 | "" | |
4027 | "%0 = %h1 * %d2, %3 = %d1 * %h2 (IS,M)%!" | |
4028 | [(set_attr "type" "dsp32")]) | |
4029 | ||
4030 | (define_insn "usmulhisi_lh_huh" | |
4031 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
4032 | (mult:SI (sign_extend:SI | |
4033 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4034 | (parallel [(const_int 0)]))) | |
4035 | (sign_extend:SI | |
4036 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4037 | (parallel [(const_int 1)]))))) | |
4038 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4039 | (mult:SI (sign_extend:SI | |
4040 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
4041 | (zero_extend:SI | |
4042 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
4043 | "" | |
4044 | "%0 = %h1 * %d2, %3 = %d1 * %d2 (IS,M)%!" | |
4045 | [(set_attr "type" "dsp32")]) | |
4046 | ||
4047 | (define_insn "usmulhisi_hl_lul" | |
4048 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
4049 | (mult:SI (sign_extend:SI | |
4050 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4051 | (parallel [(const_int 1)]))) | |
4052 | (sign_extend:SI | |
4053 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4054 | (parallel [(const_int 0)]))))) | |
4055 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4056 | (mult:SI (sign_extend:SI | |
4057 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
4058 | (zero_extend:SI | |
4059 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
4060 | "" | |
4061 | "%0 = %d1 * %h2, %3 = %h1 * %h2 (IS,M)%!" | |
4062 | [(set_attr "type" "dsp32")]) | |
4063 | ||
4064 | (define_insn "usmulhisi_hl_luh" | |
4065 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
4066 | (mult:SI (sign_extend:SI | |
4067 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4068 | (parallel [(const_int 1)]))) | |
4069 | (sign_extend:SI | |
4070 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4071 | (parallel [(const_int 0)]))))) | |
4072 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4073 | (mult:SI (sign_extend:SI | |
4074 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
4075 | (zero_extend:SI | |
4076 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
4077 | "" | |
4078 | "%0 = %d1 * %h2, %3 = %h1 * %d2 (IS,M)%!" | |
4079 | [(set_attr "type" "dsp32")]) | |
4080 | ||
4081 | (define_insn "usmulhisi_hl_hul" | |
4082 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
4083 | (mult:SI (sign_extend:SI | |
4084 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4085 | (parallel [(const_int 1)]))) | |
4086 | (sign_extend:SI | |
4087 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4088 | (parallel [(const_int 0)]))))) | |
4089 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4090 | (mult:SI (sign_extend:SI | |
4091 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
4092 | (zero_extend:SI | |
4093 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
4094 | "" | |
4095 | "%0 = %d1 * %h2, %3 = %d1 * %h2 (IS,M)%!" | |
4096 | [(set_attr "type" "dsp32")]) | |
4097 | ||
4098 | (define_insn "usmulhisi_hl_huh" | |
4099 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
4100 | (mult:SI (sign_extend:SI | |
4101 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4102 | (parallel [(const_int 1)]))) | |
4103 | (sign_extend:SI | |
4104 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4105 | (parallel [(const_int 0)]))))) | |
4106 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4107 | (mult:SI (sign_extend:SI | |
4108 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
4109 | (zero_extend:SI | |
4110 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
4111 | "" | |
4112 | "%0 = %d1 * %h2, %3 = %d1 * %d2 (IS,M)%!" | |
4113 | [(set_attr "type" "dsp32")]) | |
4114 | ||
4115 | (define_insn "usmulhisi_hh_lul" | |
4116 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
4117 | (mult:SI (sign_extend:SI | |
4118 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4119 | (parallel [(const_int 1)]))) | |
4120 | (sign_extend:SI | |
4121 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4122 | (parallel [(const_int 1)]))))) | |
4123 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4124 | (mult:SI (sign_extend:SI | |
4125 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
4126 | (zero_extend:SI | |
4127 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
4128 | "" | |
4129 | "%0 = %d1 * %d2, %3 = %h1 * %h2 (IS,M)%!" | |
75d8b2d0 BS |
4130 | [(set_attr "type" "dsp32")]) |
4131 | ||
2889abed BS |
4132 | (define_insn "usmulhisi_hh_luh" |
4133 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
4134 | (mult:SI (sign_extend:SI | |
4135 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4136 | (parallel [(const_int 1)]))) | |
4137 | (sign_extend:SI | |
4138 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4139 | (parallel [(const_int 1)]))))) | |
4140 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4141 | (mult:SI (sign_extend:SI | |
4142 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
4143 | (zero_extend:SI | |
4144 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
4145 | "" | |
4146 | "%0 = %d1 * %d2, %3 = %h1 * %d2 (IS,M)%!" | |
4147 | [(set_attr "type" "dsp32")]) | |
4148 | ||
4149 | (define_insn "usmulhisi_hh_hul" | |
4150 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
4151 | (mult:SI (sign_extend:SI | |
4152 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4153 | (parallel [(const_int 1)]))) | |
4154 | (sign_extend:SI | |
4155 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4156 | (parallel [(const_int 1)]))))) | |
4157 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4158 | (mult:SI (sign_extend:SI | |
4159 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
4160 | (zero_extend:SI | |
4161 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
4162 | "" | |
4163 | "%0 = %d1 * %d2, %3 = %d1 * %h2 (IS,M)%!" | |
4164 | [(set_attr "type" "dsp32")]) | |
4165 | ||
4166 | (define_insn "usmulhisi_hh_huh" | |
4167 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
4168 | (mult:SI (sign_extend:SI | |
4169 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
4170 | (parallel [(const_int 1)]))) | |
4171 | (sign_extend:SI | |
4172 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
4173 | (parallel [(const_int 1)]))))) | |
4174 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
4175 | (mult:SI (sign_extend:SI | |
4176 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
4177 | (zero_extend:SI | |
4178 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
4179 | "" | |
4180 | "%0 = %d1 * %d2, %3 = %d1 * %d2 (IS,M)%!" | |
4181 | [(set_attr "type" "dsp32")]) | |
4182 | ||
4183 | ;; Vector neg/abs. | |
4184 | ||
75d8b2d0 BS |
4185 | (define_insn "ssnegv2hi2" |
4186 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
4187 | (ss_neg:V2HI (match_operand:V2HI 1 "register_operand" "d")))] | |
0d4a78eb | 4188 | "" |
bbbc206e | 4189 | "%0 = - %1 (V)%!" |
0d4a78eb BS |
4190 | [(set_attr "type" "dsp32")]) |
4191 | ||
26c5953d | 4192 | (define_insn "ssabsv2hi2" |
0d4a78eb | 4193 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
26c5953d | 4194 | (ss_abs:V2HI (match_operand:V2HI 1 "register_operand" "d")))] |
0d4a78eb | 4195 | "" |
bbbc206e | 4196 | "%0 = ABS %1 (V)%!" |
0d4a78eb BS |
4197 | [(set_attr "type" "dsp32")]) |
4198 | ||
75d8b2d0 BS |
4199 | ;; Shifts. |
4200 | ||
4201 | (define_insn "ssashiftv2hi3" | |
4202 | [(set (match_operand:V2HI 0 "register_operand" "=d,d,d") | |
4203 | (if_then_else:V2HI | |
26c5953d | 4204 | (lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) |
75d8b2d0 BS |
4205 | (ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d") |
4206 | (match_dup 2)) | |
4207 | (ss_ashift:V2HI (match_dup 1) (match_dup 2))))] | |
4208 | "" | |
4209 | "@ | |
329437dd | 4210 | %0 = ASHIFT %1 BY %h2 (V, S)%! |
58f76679 BS |
4211 | %0 = %1 << %2 (V,S)%! |
4212 | %0 = %1 >>> %N2 (V,S)%!" | |
75d8b2d0 BS |
4213 | [(set_attr "type" "dsp32")]) |
4214 | ||
4215 | (define_insn "ssashifthi3" | |
4216 | [(set (match_operand:HI 0 "register_operand" "=d,d,d") | |
4217 | (if_then_else:HI | |
26c5953d | 4218 | (lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) |
75d8b2d0 BS |
4219 | (ashiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d") |
4220 | (match_dup 2)) | |
4221 | (ss_ashift:HI (match_dup 1) (match_dup 2))))] | |
4222 | "" | |
4223 | "@ | |
329437dd | 4224 | %0 = ASHIFT %1 BY %h2 (V, S)%! |
58f76679 BS |
4225 | %0 = %1 << %2 (V,S)%! |
4226 | %0 = %1 >>> %N2 (V,S)%!" | |
75d8b2d0 BS |
4227 | [(set_attr "type" "dsp32")]) |
4228 | ||
26c5953d BS |
4229 | (define_insn "ssashiftsi3" |
4230 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
4231 | (if_then_else:SI | |
4232 | (lt (match_operand:HI 2 "reg_or_const_int_operand" "d,Ku5,Ks5") (const_int 0)) | |
4233 | (ashiftrt:SI (match_operand:HI 1 "register_operand" "d,d,d") | |
4234 | (match_dup 2)) | |
4235 | (ss_ashift:SI (match_dup 1) (match_dup 2))))] | |
4236 | "" | |
4237 | "@ | |
4238 | %0 = ASHIFT %1 BY %h2 (S)%! | |
4239 | %0 = %1 << %2 (S)%! | |
4240 | %0 = %1 >>> %N2 (S)%!" | |
4241 | [(set_attr "type" "dsp32")]) | |
4242 | ||
75d8b2d0 BS |
4243 | (define_insn "lshiftv2hi3" |
4244 | [(set (match_operand:V2HI 0 "register_operand" "=d,d,d") | |
4245 | (if_then_else:V2HI | |
26c5953d | 4246 | (lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) |
75d8b2d0 BS |
4247 | (lshiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d") |
4248 | (match_dup 2)) | |
4249 | (ashift:V2HI (match_dup 1) (match_dup 2))))] | |
4250 | "" | |
4251 | "@ | |
329437dd | 4252 | %0 = LSHIFT %1 BY %h2 (V)%! |
58f76679 BS |
4253 | %0 = %1 << %2 (V)%! |
4254 | %0 = %1 >> %N2 (V)%!" | |
75d8b2d0 BS |
4255 | [(set_attr "type" "dsp32")]) |
4256 | ||
4257 | (define_insn "lshifthi3" | |
4258 | [(set (match_operand:HI 0 "register_operand" "=d,d,d") | |
4259 | (if_then_else:HI | |
26c5953d | 4260 | (lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) |
75d8b2d0 BS |
4261 | (lshiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d") |
4262 | (match_dup 2)) | |
4263 | (ashift:HI (match_dup 1) (match_dup 2))))] | |
4264 | "" | |
4265 | "@ | |
329437dd | 4266 | %0 = LSHIFT %1 BY %h2 (V)%! |
58f76679 BS |
4267 | %0 = %1 << %2 (V)%! |
4268 | %0 = %1 >> %N2 (V)%!" | |
75d8b2d0 BS |
4269 | [(set_attr "type" "dsp32")]) |
4270 | ||
8fa477f7 BS |
4271 | ;; Load without alignment exception (masking off low bits) |
4272 | ||
4273 | (define_insn "loadbytes" | |
4274 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4275 | (mem:SI (and:SI (match_operand:SI 1 "register_operand" "b") | |
4276 | (const_int -4))))] | |
4277 | "" | |
4278 | "DISALGNEXCPT || %0 = [%1];" | |
4279 | [(set_attr "type" "mcld") | |
4280 | (set_attr "length" "8")]) |