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0d4a78eb | 1 | ;;- Machine description for Blackfin for GNU compiler |
4729dc92 | 2 | ;; Copyright 2005, 2006 Free Software Foundation, Inc. |
0d4a78eb BS |
3 | ;; Contributed by Analog Devices. |
4 | ||
5 | ;; This file is part of GCC. | |
6 | ||
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
9 | ;; by the Free Software Foundation; either version 2, or (at your | |
10 | ;; option) any later version. | |
11 | ||
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING. If not, write to | |
39d14dda KC |
19 | ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, |
20 | ;; Boston, MA 02110-1301, USA. | |
0d4a78eb BS |
21 | |
22 | ; operand punctuation marks: | |
23 | ; | |
24 | ; X -- integer value printed as log2 | |
25 | ; Y -- integer value printed as log2(~value) - for bitclear | |
26 | ; h -- print half word register, low part | |
27 | ; d -- print half word register, high part | |
28 | ; D -- print operand as dregs pairs | |
29 | ; w -- print operand as accumulator register word (a0w, a1w) | |
30 | ; H -- high part of double mode operand | |
31 | ; T -- byte register representation Oct. 02 2001 | |
32 | ||
33 | ; constant operand classes | |
34 | ; | |
35 | ; J 2**N 5bit imm scaled | |
36 | ; Ks7 -64 .. 63 signed 7bit imm | |
37 | ; Ku5 0..31 unsigned 5bit imm | |
38 | ; Ks4 -8 .. 7 signed 4bit imm | |
39 | ; Ks3 -4 .. 3 signed 3bit imm | |
40 | ; Ku3 0 .. 7 unsigned 3bit imm | |
41 | ; Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n | |
42 | ; | |
43 | ; register operands | |
44 | ; d (r0..r7) | |
45 | ; a (p0..p5,fp,sp) | |
46 | ; e (a0, a1) | |
47 | ; b (i0..i3) | |
48 | ; f (m0..m3) | |
a9c46998 JZ |
49 | ; v (b0..b3) |
50 | ; c (i0..i3,m0..m3) CIRCREGS | |
51 | ; C (CC) CCREGS | |
b03149e1 JZ |
52 | ; t (lt0,lt1) |
53 | ; k (lc0,lc1) | |
a9c46998 | 54 | ; u (lb0,lb1) |
0d4a78eb BS |
55 | ; |
56 | ||
57 | ;; Define constants for hard registers. | |
58 | ||
59 | (define_constants | |
60 | [(REG_R0 0) | |
61 | (REG_R1 1) | |
62 | (REG_R2 2) | |
63 | (REG_R3 3) | |
64 | (REG_R4 4) | |
65 | (REG_R5 5) | |
66 | (REG_R6 6) | |
67 | (REG_R7 7) | |
68 | ||
69 | (REG_P0 8) | |
70 | (REG_P1 9) | |
71 | (REG_P2 10) | |
72 | (REG_P3 11) | |
73 | (REG_P4 12) | |
74 | (REG_P5 13) | |
75 | (REG_P6 14) | |
76 | (REG_P7 15) | |
77 | ||
78 | (REG_SP 14) | |
79 | (REG_FP 15) | |
80 | ||
81 | (REG_I0 16) | |
df259245 JZ |
82 | (REG_I1 17) |
83 | (REG_I2 18) | |
84 | (REG_I3 19) | |
85 | ||
86 | (REG_B0 20) | |
87 | (REG_B1 21) | |
88 | (REG_B2 22) | |
89 | (REG_B3 23) | |
90 | ||
91 | (REG_L0 24) | |
92 | (REG_L1 25) | |
93 | (REG_L2 26) | |
0d4a78eb BS |
94 | (REG_L3 27) |
95 | ||
96 | (REG_M0 28) | |
97 | (REG_M1 29) | |
98 | (REG_M2 30) | |
99 | (REG_M3 31) | |
100 | ||
101 | (REG_A0 32) | |
102 | (REG_A1 33) | |
103 | ||
104 | (REG_CC 34) | |
105 | (REG_RETS 35) | |
106 | (REG_RETI 36) | |
107 | (REG_RETX 37) | |
108 | (REG_RETN 38) | |
109 | (REG_RETE 39) | |
110 | ||
111 | (REG_ASTAT 40) | |
112 | (REG_SEQSTAT 41) | |
113 | (REG_USP 42) | |
114 | ||
b03149e1 JZ |
115 | (REG_ARGP 43) |
116 | ||
117 | (REG_LT0 44) | |
118 | (REG_LT1 45) | |
119 | (REG_LC0 46) | |
120 | (REG_LC1 47) | |
121 | (REG_LB0 48) | |
122 | (REG_LB1 49)]) | |
0d4a78eb BS |
123 | |
124 | ;; Constants used in UNSPECs and UNSPEC_VOLATILEs. | |
125 | ||
126 | (define_constants | |
127 | [(UNSPEC_CBRANCH_TAKEN 0) | |
128 | (UNSPEC_CBRANCH_NOPS 1) | |
129 | (UNSPEC_RETURN 2) | |
130 | (UNSPEC_MOVE_PIC 3) | |
131 | (UNSPEC_LIBRARY_OFFSET 4) | |
75d8b2d0 BS |
132 | (UNSPEC_PUSH_MULTIPLE 5) |
133 | ;; Multiply or MAC with extra CONST_INT operand specifying the macflag | |
134 | (UNSPEC_MUL_WITH_FLAG 6) | |
6614f9f5 BS |
135 | (UNSPEC_MAC_WITH_FLAG 7) |
136 | (UNSPEC_MOVE_FDPIC 8) | |
b03149e1 | 137 | (UNSPEC_FUNCDESC_GOT17M4 9) |
bbbc206e | 138 | (UNSPEC_LSETUP_END 10) |
942fd98f | 139 | ;; Distinguish a 32-bit version of an insn from a 16-bit version. |
bbbc206e | 140 | (UNSPEC_32BIT 11)]) |
0d4a78eb BS |
141 | |
142 | (define_constants | |
5fcead21 BS |
143 | [(UNSPEC_VOLATILE_EH_RETURN 0) |
144 | (UNSPEC_VOLATILE_CSYNC 1) | |
6614f9f5 BS |
145 | (UNSPEC_VOLATILE_SSYNC 2) |
146 | (UNSPEC_VOLATILE_LOAD_FUNCDESC 3)]) | |
0d4a78eb | 147 | |
75d8b2d0 BS |
148 | (define_constants |
149 | [(MACFLAG_NONE 0) | |
150 | (MACFLAG_T 1) | |
151 | (MACFLAG_FU 2) | |
152 | (MACFLAG_TFU 3) | |
153 | (MACFLAG_IS 4) | |
154 | (MACFLAG_IU 5) | |
155 | (MACFLAG_W32 6) | |
156 | (MACFLAG_M 7) | |
157 | (MACFLAG_S2RND 8) | |
158 | (MACFLAG_ISS2 9) | |
159 | (MACFLAG_IH 10)]) | |
160 | ||
0d4a78eb | 161 | (define_attr "type" |
96f46444 | 162 | "move,movcc,mvi,mcld,mcst,dsp32,mult,alu0,shft,brcc,br,call,misc,sync,compare,dummy" |
0d4a78eb BS |
163 | (const_string "misc")) |
164 | ||
36662eb1 BS |
165 | (define_attr "addrtype" "32bit,preg,ireg" |
166 | (cond [(and (eq_attr "type" "mcld") | |
167 | (and (match_operand 0 "d_register_operand" "") | |
168 | (match_operand 1 "mem_p_address_operand" ""))) | |
169 | (const_string "preg") | |
170 | (and (eq_attr "type" "mcld") | |
171 | (and (match_operand 0 "d_register_operand" "") | |
172 | (match_operand 1 "mem_i_address_operand" ""))) | |
173 | (const_string "ireg") | |
174 | (and (eq_attr "type" "mcst") | |
175 | (and (match_operand 1 "d_register_operand" "") | |
176 | (match_operand 0 "mem_p_address_operand" ""))) | |
177 | (const_string "preg") | |
178 | (and (eq_attr "type" "mcst") | |
179 | (and (match_operand 1 "d_register_operand" "") | |
180 | (match_operand 0 "mem_i_address_operand" ""))) | |
181 | (const_string "ireg")] | |
182 | (const_string "32bit"))) | |
183 | ||
0d4a78eb BS |
184 | ;; Scheduling definitions |
185 | ||
186 | (define_automaton "bfin") | |
187 | ||
36662eb1 BS |
188 | (define_cpu_unit "slot0" "bfin") |
189 | (define_cpu_unit "slot1" "bfin") | |
190 | (define_cpu_unit "slot2" "bfin") | |
191 | ||
192 | ;; Three units used to enforce parallel issue restrictions: | |
942fd98f | 193 | ;; only one of the 16-bit slots can use a P register in an address, |
36662eb1 BS |
194 | ;; and only one them can be a store. |
195 | (define_cpu_unit "store" "bfin") | |
196 | (define_cpu_unit "pregs" "bfin") | |
197 | ||
198 | (define_reservation "core" "slot0+slot1+slot2") | |
0d4a78eb BS |
199 | |
200 | (define_insn_reservation "alu" 1 | |
96f46444 | 201 | (eq_attr "type" "move,movcc,mvi,alu0,shft,brcc,br,call,misc,sync,compare") |
0d4a78eb BS |
202 | "core") |
203 | ||
204 | (define_insn_reservation "imul" 3 | |
205 | (eq_attr "type" "mult") | |
206 | "core*3") | |
207 | ||
36662eb1 BS |
208 | (define_insn_reservation "dsp32" 1 |
209 | (eq_attr "type" "dsp32") | |
210 | "slot0") | |
211 | ||
212 | (define_insn_reservation "load32" 1 | |
213 | (and (not (eq_attr "seq_insns" "multi")) | |
214 | (and (eq_attr "type" "mcld") (eq_attr "addrtype" "32bit"))) | |
215 | "core") | |
216 | ||
217 | (define_insn_reservation "loadp" 1 | |
218 | (and (not (eq_attr "seq_insns" "multi")) | |
219 | (and (eq_attr "type" "mcld") (eq_attr "addrtype" "preg"))) | |
220 | "(slot1|slot2)+pregs") | |
221 | ||
222 | (define_insn_reservation "loadi" 1 | |
223 | (and (not (eq_attr "seq_insns" "multi")) | |
224 | (and (eq_attr "type" "mcld") (eq_attr "addrtype" "ireg"))) | |
225 | "(slot1|slot2)") | |
226 | ||
227 | (define_insn_reservation "store32" 1 | |
228 | (and (not (eq_attr "seq_insns" "multi")) | |
229 | (and (eq_attr "type" "mcst") (eq_attr "addrtype" "32bit"))) | |
0d4a78eb BS |
230 | "core") |
231 | ||
36662eb1 BS |
232 | (define_insn_reservation "storep" 1 |
233 | (and (not (eq_attr "seq_insns" "multi")) | |
234 | (and (eq_attr "type" "mcst") (eq_attr "addrtype" "preg"))) | |
235 | "(slot1|slot2)+pregs+store") | |
236 | ||
237 | (define_insn_reservation "storei" 1 | |
238 | (and (not (eq_attr "seq_insns" "multi")) | |
239 | (and (eq_attr "type" "mcst") (eq_attr "addrtype" "ireg"))) | |
240 | "(slot1|slot2)+store") | |
241 | ||
242 | (define_insn_reservation "multi" 2 | |
243 | (eq_attr "seq_insns" "multi") | |
244 | "core") | |
245 | ||
246 | (absence_set "slot0" "slot1,slot2") | |
247 | (absence_set "slot1" "slot2") | |
248 | ||
0d4a78eb BS |
249 | ;; Make sure genautomata knows about the maximum latency that can be produced |
250 | ;; by the adjust_cost function. | |
251 | (define_insn_reservation "dummy" 5 | |
36662eb1 | 252 | (eq_attr "type" "dummy") |
0d4a78eb BS |
253 | "core") |
254 | \f | |
255 | ;; Operand and operator predicates | |
256 | ||
257 | (include "predicates.md") | |
258 | ||
259 | \f | |
260 | ;;; FRIO branches have been optimized for code density | |
261 | ;;; this comes at a slight cost of complexity when | |
262 | ;;; a compiler needs to generate branches in the general | |
263 | ;;; case. In order to generate the correct branching | |
264 | ;;; mechanisms the compiler needs keep track of instruction | |
265 | ;;; lengths. The follow table describes how to count instructions | |
266 | ;;; for the FRIO architecture. | |
267 | ;;; | |
268 | ;;; unconditional br are 12-bit imm pcrelative branches *2 | |
269 | ;;; conditional br are 10-bit imm pcrelative branches *2 | |
270 | ;;; brcc 10-bit: | |
271 | ;;; 1024 10-bit imm *2 is 2048 (-1024..1022) | |
272 | ;;; br 12-bit : | |
273 | ;;; 4096 12-bit imm *2 is 8192 (-4096..4094) | |
274 | ;;; NOTE : For brcc we generate instructions such as | |
275 | ;;; if cc jmp; jump.[sl] offset | |
276 | ;;; offset of jump.[sl] is from the jump instruction but | |
277 | ;;; gcc calculates length from the if cc jmp instruction | |
a2391c6a JZ |
278 | ;;; furthermore gcc takes the end address of the branch instruction |
279 | ;;; as (pc) for a forward branch | |
280 | ;;; hence our range is (-4094, 4092) instead of (-4096, 4094) for a br | |
0d4a78eb BS |
281 | ;;; |
282 | ;;; The way the (pc) rtx works in these calculations is somewhat odd; | |
283 | ;;; for backward branches it's the address of the current instruction, | |
284 | ;;; for forward branches it's the previously known address of the following | |
285 | ;;; instruction - we have to take this into account by reducing the range | |
286 | ;;; for a forward branch. | |
287 | ||
288 | ;; Lengths for type "mvi" insns are always defined by the instructions | |
289 | ;; themselves. | |
290 | (define_attr "length" "" | |
291 | (cond [(eq_attr "type" "mcld") | |
292 | (if_then_else (match_operand 1 "effective_address_32bit_p" "") | |
293 | (const_int 4) (const_int 2)) | |
294 | ||
295 | (eq_attr "type" "mcst") | |
296 | (if_then_else (match_operand 0 "effective_address_32bit_p" "") | |
297 | (const_int 4) (const_int 2)) | |
298 | ||
299 | (eq_attr "type" "move") (const_int 2) | |
300 | ||
301 | (eq_attr "type" "dsp32") (const_int 4) | |
302 | (eq_attr "type" "call") (const_int 4) | |
303 | ||
304 | (eq_attr "type" "br") | |
305 | (if_then_else (and | |
306 | (le (minus (match_dup 0) (pc)) (const_int 4092)) | |
307 | (ge (minus (match_dup 0) (pc)) (const_int -4096))) | |
308 | (const_int 2) | |
309 | (const_int 4)) | |
310 | ||
311 | (eq_attr "type" "brcc") | |
312 | (cond [(and | |
313 | (le (minus (match_dup 3) (pc)) (const_int 1020)) | |
314 | (ge (minus (match_dup 3) (pc)) (const_int -1024))) | |
315 | (const_int 2) | |
316 | (and | |
a2391c6a | 317 | (le (minus (match_dup 3) (pc)) (const_int 4092)) |
0d4a78eb BS |
318 | (ge (minus (match_dup 3) (pc)) (const_int -4094))) |
319 | (const_int 4)] | |
320 | (const_int 6)) | |
321 | ] | |
322 | ||
323 | (const_int 2))) | |
324 | ||
b03149e1 JZ |
325 | ;; Classify the insns into those that are one instruction and those that |
326 | ;; are more than one in sequence. | |
327 | (define_attr "seq_insns" "single,multi" | |
328 | (const_string "single")) | |
329 | ||
0d4a78eb BS |
330 | ;; Conditional moves |
331 | ||
332 | (define_expand "movsicc" | |
333 | [(set (match_operand:SI 0 "register_operand" "") | |
334 | (if_then_else:SI (match_operand 1 "comparison_operator" "") | |
335 | (match_operand:SI 2 "register_operand" "") | |
336 | (match_operand:SI 3 "register_operand" "")))] | |
337 | "" | |
338 | { | |
339 | operands[1] = bfin_gen_compare (operands[1], SImode); | |
340 | }) | |
341 | ||
342 | (define_insn "*movsicc_insn1" | |
343 | [(set (match_operand:SI 0 "register_operand" "=da,da,da") | |
344 | (if_then_else:SI | |
4729dc92 | 345 | (eq:BI (match_operand:BI 3 "register_operand" "C,C,C") |
0d4a78eb BS |
346 | (const_int 0)) |
347 | (match_operand:SI 1 "register_operand" "da,0,da") | |
348 | (match_operand:SI 2 "register_operand" "0,da,da")))] | |
349 | "" | |
350 | "@ | |
351 | if !cc %0 =%1; /* movsicc-1a */ | |
352 | if cc %0 =%2; /* movsicc-1b */ | |
353 | if !cc %0 =%1; if cc %0=%2; /* movsicc-1 */" | |
354 | [(set_attr "length" "2,2,4") | |
96f46444 | 355 | (set_attr "type" "movcc") |
b03149e1 | 356 | (set_attr "seq_insns" "*,*,multi")]) |
0d4a78eb BS |
357 | |
358 | (define_insn "*movsicc_insn2" | |
359 | [(set (match_operand:SI 0 "register_operand" "=da,da,da") | |
360 | (if_then_else:SI | |
4729dc92 | 361 | (ne:BI (match_operand:BI 3 "register_operand" "C,C,C") |
0d4a78eb BS |
362 | (const_int 0)) |
363 | (match_operand:SI 1 "register_operand" "0,da,da") | |
364 | (match_operand:SI 2 "register_operand" "da,0,da")))] | |
365 | "" | |
366 | "@ | |
367 | if !cc %0 =%2; /* movsicc-2b */ | |
368 | if cc %0 =%1; /* movsicc-2a */ | |
369 | if cc %0 =%1; if !cc %0=%2; /* movsicc-1 */" | |
370 | [(set_attr "length" "2,2,4") | |
96f46444 | 371 | (set_attr "type" "movcc") |
b03149e1 | 372 | (set_attr "seq_insns" "*,*,multi")]) |
0d4a78eb BS |
373 | |
374 | ;; Insns to load HIGH and LO_SUM | |
375 | ||
376 | (define_insn "movsi_high" | |
377 | [(set (match_operand:SI 0 "register_operand" "=x") | |
378 | (high:SI (match_operand:SI 1 "immediate_operand" "i")))] | |
379 | "reload_completed" | |
380 | "%d0 = %d1;" | |
381 | [(set_attr "type" "mvi") | |
382 | (set_attr "length" "4")]) | |
383 | ||
384 | (define_insn "movstricthi_high" | |
385 | [(set (match_operand:SI 0 "register_operand" "+x") | |
386 | (ior:SI (and:SI (match_dup 0) (const_int 65535)) | |
387 | (match_operand:SI 1 "immediate_operand" "i")))] | |
388 | "reload_completed" | |
389 | "%d0 = %d1;" | |
390 | [(set_attr "type" "mvi") | |
391 | (set_attr "length" "4")]) | |
392 | ||
393 | (define_insn "movsi_low" | |
394 | [(set (match_operand:SI 0 "register_operand" "=x") | |
395 | (lo_sum:SI (match_operand:SI 1 "register_operand" "0") | |
396 | (match_operand:SI 2 "immediate_operand" "i")))] | |
397 | "reload_completed" | |
398 | "%h0 = %h2;" | |
399 | [(set_attr "type" "mvi") | |
400 | (set_attr "length" "4")]) | |
401 | ||
402 | (define_insn "movsi_high_pic" | |
403 | [(set (match_operand:SI 0 "register_operand" "=x") | |
404 | (high:SI (unspec:SI [(match_operand:SI 1 "" "")] | |
405 | UNSPEC_MOVE_PIC)))] | |
406 | "" | |
407 | "%d0 = %1@GOT_LOW;" | |
408 | [(set_attr "type" "mvi") | |
409 | (set_attr "length" "4")]) | |
410 | ||
411 | (define_insn "movsi_low_pic" | |
412 | [(set (match_operand:SI 0 "register_operand" "=x") | |
413 | (lo_sum:SI (match_operand:SI 1 "register_operand" "0") | |
414 | (unspec:SI [(match_operand:SI 2 "" "")] | |
415 | UNSPEC_MOVE_PIC)))] | |
416 | "" | |
417 | "%h0 = %h2@GOT_HIGH;" | |
418 | [(set_attr "type" "mvi") | |
419 | (set_attr "length" "4")]) | |
420 | ||
421 | ;;; Move instructions | |
422 | ||
423 | (define_insn_and_split "movdi_insn" | |
424 | [(set (match_operand:DI 0 "nonimmediate_operand" "=x,mx,r") | |
425 | (match_operand:DI 1 "general_operand" "iFx,r,mx"))] | |
426 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" | |
427 | "#" | |
428 | "reload_completed" | |
429 | [(set (match_dup 2) (match_dup 3)) | |
430 | (set (match_dup 4) (match_dup 5))] | |
431 | { | |
432 | rtx lo_half[2], hi_half[2]; | |
433 | split_di (operands, 2, lo_half, hi_half); | |
434 | ||
435 | if (reg_overlap_mentioned_p (lo_half[0], hi_half[1])) | |
436 | { | |
437 | operands[2] = hi_half[0]; | |
438 | operands[3] = hi_half[1]; | |
439 | operands[4] = lo_half[0]; | |
440 | operands[5] = lo_half[1]; | |
441 | } | |
442 | else | |
443 | { | |
444 | operands[2] = lo_half[0]; | |
445 | operands[3] = lo_half[1]; | |
446 | operands[4] = hi_half[0]; | |
447 | operands[5] = hi_half[1]; | |
448 | } | |
449 | }) | |
450 | ||
451 | (define_insn "movbi" | |
4729dc92 BS |
452 | [(set (match_operand:BI 0 "nonimmediate_operand" "=x,x,d,md,C,d,C") |
453 | (match_operand:BI 1 "general_operand" "x,xKs3,md,d,d,C,P0"))] | |
0d4a78eb BS |
454 | |
455 | "" | |
456 | "@ | |
457 | %0 = %1; | |
458 | %0 = %1 (X); | |
bbbc206e | 459 | %0 = B %1 (Z)%! |
4729dc92 | 460 | B %0 = %1; |
0d4a78eb | 461 | CC = %1; |
49373252 BS |
462 | %0 = CC; |
463 | R0 = R0 | R0; CC = AC0;" | |
464 | [(set_attr "type" "move,mvi,mcld,mcst,compare,compare,alu0") | |
b03149e1 JZ |
465 | (set_attr "length" "2,2,*,*,2,2,4") |
466 | (set_attr "seq_insns" "*,*,*,*,*,*,multi")]) | |
0d4a78eb BS |
467 | |
468 | (define_insn "movpdi" | |
469 | [(set (match_operand:PDI 0 "nonimmediate_operand" "=e,<,e") | |
470 | (match_operand:PDI 1 "general_operand" " e,e,>"))] | |
471 | "" | |
472 | "@ | |
473 | %0 = %1; | |
474 | %0 = %x1; %0 = %w1; | |
475 | %w0 = %1; %x0 = %1;" | |
b03149e1 JZ |
476 | [(set_attr "type" "move,mcst,mcld") |
477 | (set_attr "seq_insns" "*,multi,multi")]) | |
0d4a78eb | 478 | |
75d8b2d0 BS |
479 | (define_insn "load_accumulator" |
480 | [(set (match_operand:PDI 0 "register_operand" "=e") | |
481 | (sign_extend:PDI (match_operand:SI 1 "register_operand" "d")))] | |
482 | "" | |
483 | "%0 = %1;" | |
484 | [(set_attr "type" "move")]) | |
485 | ||
486 | (define_insn_and_split "load_accumulator_pair" | |
487 | [(set (match_operand:V2PDI 0 "register_operand" "=e") | |
488 | (sign_extend:V2PDI (vec_concat:V2SI | |
489 | (match_operand:SI 1 "register_operand" "d") | |
490 | (match_operand:SI 2 "register_operand" "d"))))] | |
491 | "" | |
492 | "#" | |
493 | "reload_completed" | |
494 | [(set (match_dup 3) (sign_extend:PDI (match_dup 1))) | |
495 | (set (match_dup 4) (sign_extend:PDI (match_dup 2)))] | |
496 | { | |
497 | operands[3] = gen_rtx_REG (PDImode, REGNO (operands[0])); | |
498 | operands[4] = gen_rtx_REG (PDImode, REGNO (operands[0]) + 1); | |
499 | }) | |
500 | ||
0d4a78eb BS |
501 | (define_insn "*pushsi_insn" |
502 | [(set (mem:SI (pre_dec:SI (reg:SI REG_SP))) | |
503 | (match_operand:SI 0 "register_operand" "xy"))] | |
504 | "" | |
505 | "[--SP] = %0;" | |
506 | [(set_attr "type" "mcst") | |
35e3ced9 | 507 | (set_attr "addrtype" "32bit") |
0d4a78eb BS |
508 | (set_attr "length" "2")]) |
509 | ||
510 | (define_insn "*popsi_insn" | |
35e3ced9 | 511 | [(set (match_operand:SI 0 "register_operand" "=d,xy") |
0d4a78eb BS |
512 | (mem:SI (post_inc:SI (reg:SI REG_SP))))] |
513 | "" | |
bbbc206e | 514 | "%0 = [SP++]%!" |
0d4a78eb | 515 | [(set_attr "type" "mcld") |
35e3ced9 | 516 | (set_attr "addrtype" "preg,32bit") |
0d4a78eb BS |
517 | (set_attr "length" "2")]) |
518 | ||
519 | ;; The first alternative is used to make reload choose a limited register | |
520 | ;; class when faced with a movsi_insn that had its input operand replaced | |
521 | ;; with a PLUS. We generally require fewer secondary reloads this way. | |
0d4a78eb | 522 | |
b03149e1 JZ |
523 | (define_insn "*movsi_insn" |
524 | [(set (match_operand:SI 0 "nonimmediate_operand" "=da,x*y,*k,da,da,x,x,x,da,mr") | |
525 | (match_operand:SI 1 "general_operand" "da,x*y,da,*k,xKs7,xKsh,xKuh,ix,mr,da"))] | |
0d4a78eb | 526 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" |
b03149e1 JZ |
527 | "@ |
528 | %0 = %1; | |
529 | %0 = %1; | |
0d4a78eb BS |
530 | %0 = %1; |
531 | %0 = %1; | |
532 | %0 = %1 (X); | |
533 | %0 = %1 (X); | |
534 | %0 = %1 (Z); | |
535 | # | |
bbbc206e BS |
536 | %0 = %1%! |
537 | %0 = %1%!" | |
b03149e1 JZ |
538 | [(set_attr "type" "move,move,move,move,mvi,mvi,mvi,*,mcld,mcst") |
539 | (set_attr "length" "2,2,2,2,2,4,4,*,*,*")]) | |
0d4a78eb | 540 | |
bbbc206e BS |
541 | (define_insn "*movsi_insn32" |
542 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
543 | (unspec:SI [(match_operand:SI 1 "nonmemory_operand" "d,P0")] UNSPEC_32BIT))] | |
544 | "" | |
545 | "@ | |
546 | %0 = ROT %1 BY 0%! | |
547 | %0 = %0 -|- %0%!" | |
548 | [(set_attr "type" "dsp32")]) | |
549 | ||
550 | (define_split | |
551 | [(set (match_operand:SI 0 "d_register_operand" "") | |
552 | (const_int 0))] | |
553 | "splitting_for_sched && !optimize_size" | |
554 | [(set (match_dup 0) (unspec:SI [(const_int 0)] UNSPEC_32BIT))]) | |
555 | ||
556 | (define_split | |
557 | [(set (match_operand:SI 0 "d_register_operand" "") | |
558 | (match_operand:SI 1 "d_register_operand" ""))] | |
559 | "splitting_for_sched && !optimize_size" | |
560 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_32BIT))]) | |
561 | ||
75d8b2d0 BS |
562 | (define_insn_and_split "*movv2hi_insn" |
563 | [(set (match_operand:V2HI 0 "nonimmediate_operand" "=da,da,d,dm") | |
564 | (match_operand:V2HI 1 "general_operand" "i,di,md,d"))] | |
0d4a78eb BS |
565 | |
566 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" | |
75d8b2d0 BS |
567 | "@ |
568 | # | |
569 | %0 = %1; | |
bbbc206e BS |
570 | %0 = %1%! |
571 | %0 = %1%!" | |
75d8b2d0 BS |
572 | "reload_completed && GET_CODE (operands[1]) == CONST_VECTOR" |
573 | [(set (match_dup 0) (high:SI (match_dup 2))) | |
574 | (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 3)))] | |
575 | { | |
576 | HOST_WIDE_INT intval = INTVAL (XVECEXP (operands[1], 0, 1)) << 16; | |
577 | intval |= INTVAL (XVECEXP (operands[1], 0, 0)) & 0xFFFF; | |
554006bd | 578 | |
75d8b2d0 BS |
579 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[0])); |
580 | operands[2] = operands[3] = GEN_INT (trunc_int_for_mode (intval, SImode)); | |
581 | } | |
582 | [(set_attr "type" "move,move,mcld,mcst") | |
583 | (set_attr "length" "2,2,*,*")]) | |
0d4a78eb BS |
584 | |
585 | (define_insn "*movhi_insn" | |
586 | [(set (match_operand:HI 0 "nonimmediate_operand" "=x,da,x,d,mr") | |
587 | (match_operand:HI 1 "general_operand" "x,xKs7,xKsh,mr,d"))] | |
588 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" | |
c4963a0a BS |
589 | { |
590 | static const char *templates[] = { | |
591 | "%0 = %1;", | |
592 | "%0 = %1 (X);", | |
593 | "%0 = %1 (X);", | |
bbbc206e BS |
594 | "%0 = W %1 (X)%!", |
595 | "W %0 = %1%!", | |
596 | "%h0 = W %1%!", | |
597 | "W %0 = %h1%!" | |
c4963a0a BS |
598 | }; |
599 | int alt = which_alternative; | |
600 | rtx mem = (MEM_P (operands[0]) ? operands[0] | |
601 | : MEM_P (operands[1]) ? operands[1] : NULL_RTX); | |
602 | if (mem && bfin_dsp_memref_p (mem)) | |
603 | alt += 2; | |
604 | return templates[alt]; | |
605 | } | |
0d4a78eb BS |
606 | [(set_attr "type" "move,mvi,mvi,mcld,mcst") |
607 | (set_attr "length" "2,2,4,*,*")]) | |
608 | ||
609 | (define_insn "*movqi_insn" | |
610 | [(set (match_operand:QI 0 "nonimmediate_operand" "=x,da,x,d,mr") | |
611 | (match_operand:QI 1 "general_operand" "x,xKs7,xKsh,mr,d"))] | |
612 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" | |
613 | "@ | |
614 | %0 = %1; | |
615 | %0 = %1 (X); | |
616 | %0 = %1 (X); | |
bbbc206e BS |
617 | %0 = B %1 (X)%! |
618 | B %0 = %1%!" | |
0d4a78eb BS |
619 | [(set_attr "type" "move,mvi,mvi,mcld,mcst") |
620 | (set_attr "length" "2,2,4,*,*")]) | |
621 | ||
622 | (define_insn "*movsf_insn" | |
623 | [(set (match_operand:SF 0 "nonimmediate_operand" "=x,x,da,mr") | |
624 | (match_operand:SF 1 "general_operand" "x,Fx,mr,da"))] | |
625 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" | |
626 | "@ | |
627 | %0 = %1; | |
628 | # | |
bbbc206e BS |
629 | %0 = %1%! |
630 | %0 = %1%!" | |
0d4a78eb BS |
631 | [(set_attr "type" "move,*,mcld,mcst")]) |
632 | ||
633 | (define_insn_and_split "movdf_insn" | |
634 | [(set (match_operand:DF 0 "nonimmediate_operand" "=x,mx,r") | |
635 | (match_operand:DF 1 "general_operand" "iFx,r,mx"))] | |
636 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" | |
637 | "#" | |
638 | "reload_completed" | |
639 | [(set (match_dup 2) (match_dup 3)) | |
640 | (set (match_dup 4) (match_dup 5))] | |
641 | { | |
642 | rtx lo_half[2], hi_half[2]; | |
643 | split_di (operands, 2, lo_half, hi_half); | |
644 | ||
645 | if (reg_overlap_mentioned_p (lo_half[0], hi_half[1])) | |
646 | { | |
647 | operands[2] = hi_half[0]; | |
648 | operands[3] = hi_half[1]; | |
649 | operands[4] = lo_half[0]; | |
650 | operands[5] = lo_half[1]; | |
651 | } | |
652 | else | |
653 | { | |
654 | operands[2] = lo_half[0]; | |
655 | operands[3] = lo_half[1]; | |
656 | operands[4] = hi_half[0]; | |
657 | operands[5] = hi_half[1]; | |
658 | } | |
659 | }) | |
660 | ||
75d8b2d0 BS |
661 | ;; Storing halfwords. |
662 | (define_insn "*movsi_insv" | |
663 | [(set (zero_extract:SI (match_operand 0 "register_operand" "+d,x") | |
664 | (const_int 16) | |
665 | (const_int 16)) | |
666 | (match_operand:SI 1 "nonmemory_operand" "d,n"))] | |
667 | "" | |
668 | "@ | |
bbbc206e | 669 | %d0 = %h1 << 0%! |
75d8b2d0 BS |
670 | %d0 = %1;" |
671 | [(set_attr "type" "dsp32,mvi")]) | |
672 | ||
673 | (define_expand "insv" | |
674 | [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "") | |
675 | (match_operand:SI 1 "immediate_operand" "") | |
676 | (match_operand:SI 2 "immediate_operand" "")) | |
677 | (match_operand:SI 3 "nonmemory_operand" ""))] | |
678 | "" | |
679 | { | |
680 | if (INTVAL (operands[1]) != 16 || INTVAL (operands[2]) != 16) | |
681 | FAIL; | |
682 | ||
683 | /* From mips.md: insert_bit_field doesn't verify that our source | |
684 | matches the predicate, so check it again here. */ | |
685 | if (! register_operand (operands[0], VOIDmode)) | |
686 | FAIL; | |
687 | }) | |
688 | ||
0d4a78eb BS |
689 | ;; This is the main "hook" for PIC code. When generating |
690 | ;; PIC, movsi is responsible for determining when the source address | |
691 | ;; needs PIC relocation and appropriately calling legitimize_pic_address | |
692 | ;; to perform the actual relocation. | |
693 | ||
694 | (define_expand "movsi" | |
695 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
696 | (match_operand:SI 1 "general_operand" ""))] | |
697 | "" | |
d6f6753e BS |
698 | { |
699 | if (expand_move (operands, SImode)) | |
700 | DONE; | |
701 | }) | |
0d4a78eb BS |
702 | |
703 | (define_expand "movv2hi" | |
704 | [(set (match_operand:V2HI 0 "nonimmediate_operand" "") | |
705 | (match_operand:V2HI 1 "general_operand" ""))] | |
706 | "" | |
707 | "expand_move (operands, V2HImode);") | |
708 | ||
709 | (define_expand "movdi" | |
710 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
711 | (match_operand:DI 1 "general_operand" ""))] | |
712 | "" | |
713 | "expand_move (operands, DImode);") | |
714 | ||
715 | (define_expand "movsf" | |
716 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
717 | (match_operand:SF 1 "general_operand" ""))] | |
718 | "" | |
719 | "expand_move (operands, SFmode);") | |
720 | ||
721 | (define_expand "movdf" | |
722 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
723 | (match_operand:DF 1 "general_operand" ""))] | |
724 | "" | |
725 | "expand_move (operands, DFmode);") | |
726 | ||
727 | (define_expand "movhi" | |
728 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
729 | (match_operand:HI 1 "general_operand" ""))] | |
730 | "" | |
731 | "expand_move (operands, HImode);") | |
732 | ||
733 | (define_expand "movqi" | |
734 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
735 | (match_operand:QI 1 "general_operand" ""))] | |
736 | "" | |
737 | " expand_move (operands, QImode); ") | |
738 | ||
739 | ;; Some define_splits to break up SI/SFmode loads of immediate constants. | |
740 | ||
741 | (define_split | |
742 | [(set (match_operand:SI 0 "register_operand" "") | |
743 | (match_operand:SI 1 "symbolic_or_const_operand" ""))] | |
744 | "reload_completed | |
745 | /* Always split symbolic operands; split integer constants that are | |
746 | too large for a single instruction. */ | |
747 | && (GET_CODE (operands[1]) != CONST_INT | |
748 | || (INTVAL (operands[1]) < -32768 | |
749 | || INTVAL (operands[1]) >= 65536 | |
750 | || (INTVAL (operands[1]) >= 32768 && PREG_P (operands[0]))))" | |
751 | [(set (match_dup 0) (high:SI (match_dup 1))) | |
752 | (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 1)))] | |
753 | { | |
754 | if (GET_CODE (operands[1]) == CONST_INT | |
755 | && split_load_immediate (operands)) | |
756 | DONE; | |
757 | /* ??? Do something about TARGET_LOW_64K. */ | |
758 | }) | |
759 | ||
760 | (define_split | |
761 | [(set (match_operand:SF 0 "register_operand" "") | |
762 | (match_operand:SF 1 "immediate_operand" ""))] | |
763 | "reload_completed" | |
764 | [(set (match_dup 2) (high:SI (match_dup 3))) | |
765 | (set (match_dup 2) (lo_sum:SI (match_dup 2) (match_dup 3)))] | |
766 | { | |
767 | long values; | |
768 | REAL_VALUE_TYPE value; | |
769 | ||
3b9dd769 | 770 | gcc_assert (GET_CODE (operands[1]) == CONST_DOUBLE); |
0d4a78eb BS |
771 | |
772 | REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]); | |
773 | REAL_VALUE_TO_TARGET_SINGLE (value, values); | |
774 | ||
775 | operands[2] = gen_rtx_REG (SImode, true_regnum (operands[0])); | |
776 | operands[3] = GEN_INT (trunc_int_for_mode (values, SImode)); | |
777 | if (values >= -32768 && values < 65536) | |
778 | { | |
779 | emit_move_insn (operands[2], operands[3]); | |
780 | DONE; | |
781 | } | |
782 | if (split_load_immediate (operands + 2)) | |
783 | DONE; | |
784 | }) | |
785 | ||
786 | ;; Sadly, this can't be a proper named movstrict pattern, since the compiler | |
787 | ;; expects to be able to use registers for operand 1. | |
788 | ;; Note that the asm instruction is defined by the manual to take an unsigned | |
789 | ;; constant, but it doesn't matter to the assembler, and the compiler only | |
790 | ;; deals with sign-extended constants. Hence "Ksh". | |
75d8b2d0 | 791 | (define_insn "movstricthi_1" |
0d4a78eb BS |
792 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+x")) |
793 | (match_operand:HI 1 "immediate_operand" "Ksh"))] | |
794 | "" | |
795 | "%h0 = %1;" | |
796 | [(set_attr "type" "mvi") | |
797 | (set_attr "length" "4")]) | |
798 | ||
799 | ;; Sign and zero extensions | |
800 | ||
c4963a0a | 801 | (define_insn_and_split "extendhisi2" |
0d4a78eb BS |
802 | [(set (match_operand:SI 0 "register_operand" "=d, d") |
803 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))] | |
804 | "" | |
805 | "@ | |
806 | %0 = %h1 (X); | |
bbbc206e | 807 | %0 = W %h1 (X)%!" |
c4963a0a BS |
808 | "reload_completed && bfin_dsp_memref_p (operands[1])" |
809 | [(set (match_dup 2) (match_dup 1)) | |
810 | (set (match_dup 0) (sign_extend:SI (match_dup 2)))] | |
811 | { | |
812 | operands[2] = gen_lowpart (HImode, operands[0]); | |
813 | } | |
0d4a78eb BS |
814 | [(set_attr "type" "alu0,mcld")]) |
815 | ||
c4963a0a | 816 | (define_insn_and_split "zero_extendhisi2" |
0d4a78eb BS |
817 | [(set (match_operand:SI 0 "register_operand" "=d, d") |
818 | (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))] | |
819 | "" | |
820 | "@ | |
821 | %0 = %h1 (Z); | |
bbbc206e | 822 | %0 = W %h1 (Z)%!" |
c4963a0a BS |
823 | "reload_completed && bfin_dsp_memref_p (operands[1])" |
824 | [(set (match_dup 2) (match_dup 1)) | |
825 | (set (match_dup 0) (zero_extend:SI (match_dup 2)))] | |
826 | { | |
827 | operands[2] = gen_lowpart (HImode, operands[0]); | |
828 | } | |
0d4a78eb BS |
829 | [(set_attr "type" "alu0,mcld")]) |
830 | ||
831 | (define_insn "zero_extendbisi2" | |
832 | [(set (match_operand:SI 0 "register_operand" "=d") | |
833 | (zero_extend:SI (match_operand:BI 1 "nonimmediate_operand" "C")))] | |
834 | "" | |
835 | "%0 = %1;" | |
836 | [(set_attr "type" "compare")]) | |
837 | ||
838 | (define_insn "extendqihi2" | |
839 | [(set (match_operand:HI 0 "register_operand" "=d, d") | |
840 | (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] | |
841 | "" | |
842 | "@ | |
bbbc206e | 843 | %0 = B %1 (X)%! |
0d4a78eb BS |
844 | %0 = %T1 (X);" |
845 | [(set_attr "type" "mcld,alu0")]) | |
846 | ||
847 | (define_insn "extendqisi2" | |
848 | [(set (match_operand:SI 0 "register_operand" "=d, d") | |
849 | (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] | |
850 | "" | |
851 | "@ | |
bbbc206e | 852 | %0 = B %1 (X)%! |
0d4a78eb BS |
853 | %0 = %T1 (X);" |
854 | [(set_attr "type" "mcld,alu0")]) | |
855 | ||
856 | ||
857 | (define_insn "zero_extendqihi2" | |
858 | [(set (match_operand:HI 0 "register_operand" "=d, d") | |
859 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] | |
860 | "" | |
861 | "@ | |
bbbc206e | 862 | %0 = B %1 (Z)%! |
0d4a78eb BS |
863 | %0 = %T1 (Z);" |
864 | [(set_attr "type" "mcld,alu0")]) | |
865 | ||
866 | ||
867 | (define_insn "zero_extendqisi2" | |
868 | [(set (match_operand:SI 0 "register_operand" "=d, d") | |
869 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] | |
870 | "" | |
871 | "@ | |
bbbc206e | 872 | %0 = B %1 (Z)%! |
0d4a78eb BS |
873 | %0 = %T1 (Z);" |
874 | [(set_attr "type" "mcld,alu0")]) | |
875 | ||
876 | ;; DImode logical operations | |
877 | ||
878 | (define_code_macro any_logical [and ior xor]) | |
879 | (define_code_attr optab [(and "and") | |
880 | (ior "ior") | |
881 | (xor "xor")]) | |
882 | (define_code_attr op [(and "&") | |
883 | (ior "|") | |
884 | (xor "^")]) | |
885 | (define_code_attr high_result [(and "0") | |
886 | (ior "%H1") | |
887 | (xor "%H1")]) | |
888 | ||
889 | (define_insn "<optab>di3" | |
890 | [(set (match_operand:DI 0 "register_operand" "=d") | |
891 | (any_logical:DI (match_operand:DI 1 "register_operand" "0") | |
892 | (match_operand:DI 2 "register_operand" "d")))] | |
893 | "" | |
894 | "%0 = %1 <op> %2;\\n\\t%H0 = %H1 <op> %H2;" | |
b03149e1 JZ |
895 | [(set_attr "length" "4") |
896 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
897 | |
898 | (define_insn "*<optab>di_zesidi_di" | |
899 | [(set (match_operand:DI 0 "register_operand" "=d") | |
900 | (any_logical:DI (zero_extend:DI | |
901 | (match_operand:SI 2 "register_operand" "d")) | |
902 | (match_operand:DI 1 "register_operand" "d")))] | |
903 | "" | |
904 | "%0 = %1 <op> %2;\\n\\t%H0 = <high_result>;" | |
b03149e1 JZ |
905 | [(set_attr "length" "4") |
906 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
907 | |
908 | (define_insn "*<optab>di_sesdi_di" | |
909 | [(set (match_operand:DI 0 "register_operand" "=d") | |
910 | (any_logical:DI (sign_extend:DI | |
911 | (match_operand:SI 2 "register_operand" "d")) | |
912 | (match_operand:DI 1 "register_operand" "0"))) | |
913 | (clobber (match_scratch:SI 3 "=&d"))] | |
914 | "" | |
915 | "%0 = %1 <op> %2;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %H1 <op> %3;" | |
b03149e1 JZ |
916 | [(set_attr "length" "8") |
917 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
918 | |
919 | (define_insn "negdi2" | |
920 | [(set (match_operand:DI 0 "register_operand" "=d") | |
921 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
922 | (clobber (match_scratch:SI 2 "=&d")) | |
923 | (clobber (reg:CC REG_CC))] | |
924 | "" | |
925 | "%2 = 0; %2 = %2 - %1; cc = ac0; cc = !cc; %2 = cc;\\n\\t%0 = -%1; %H0 = -%H1; %H0 = %H0 - %2;" | |
b03149e1 JZ |
926 | [(set_attr "length" "16") |
927 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
928 | |
929 | (define_insn "one_cmpldi2" | |
930 | [(set (match_operand:DI 0 "register_operand" "=d") | |
931 | (not:DI (match_operand:DI 1 "register_operand" "d")))] | |
932 | "" | |
933 | "%0 = ~%1;\\n\\t%H0 = ~%H1;" | |
b03149e1 JZ |
934 | [(set_attr "length" "4") |
935 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
936 | |
937 | ;; DImode zero and sign extend patterns | |
938 | ||
939 | (define_insn_and_split "zero_extendsidi2" | |
940 | [(set (match_operand:DI 0 "register_operand" "=d") | |
941 | (zero_extend:DI (match_operand:SI 1 "register_operand" "d")))] | |
942 | "" | |
943 | "#" | |
944 | "reload_completed" | |
945 | [(set (match_dup 3) (const_int 0))] | |
946 | { | |
947 | split_di (operands, 1, operands + 2, operands + 3); | |
948 | if (REGNO (operands[0]) != REGNO (operands[1])) | |
949 | emit_move_insn (operands[2], operands[1]); | |
950 | }) | |
951 | ||
952 | (define_insn "zero_extendqidi2" | |
953 | [(set (match_operand:DI 0 "register_operand" "=d") | |
954 | (zero_extend:DI (match_operand:QI 1 "register_operand" "d")))] | |
955 | "" | |
956 | "%0 = %T1 (Z);\\n\\t%H0 = 0;" | |
b03149e1 JZ |
957 | [(set_attr "length" "4") |
958 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
959 | |
960 | (define_insn "zero_extendhidi2" | |
961 | [(set (match_operand:DI 0 "register_operand" "=d") | |
962 | (zero_extend:DI (match_operand:HI 1 "register_operand" "d")))] | |
963 | "" | |
964 | "%0 = %h1 (Z);\\n\\t%H0 = 0;" | |
b03149e1 JZ |
965 | [(set_attr "length" "4") |
966 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
967 | |
968 | (define_insn_and_split "extendsidi2" | |
969 | [(set (match_operand:DI 0 "register_operand" "=d") | |
970 | (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))] | |
971 | "" | |
972 | "#" | |
973 | "reload_completed" | |
974 | [(set (match_dup 3) (match_dup 1)) | |
975 | (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))] | |
976 | { | |
977 | split_di (operands, 1, operands + 2, operands + 3); | |
978 | if (REGNO (operands[0]) != REGNO (operands[1])) | |
979 | emit_move_insn (operands[2], operands[1]); | |
980 | }) | |
981 | ||
982 | (define_insn_and_split "extendqidi2" | |
983 | [(set (match_operand:DI 0 "register_operand" "=d") | |
984 | (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))] | |
985 | "" | |
986 | "#" | |
987 | "reload_completed" | |
988 | [(set (match_dup 2) (sign_extend:SI (match_dup 1))) | |
989 | (set (match_dup 3) (sign_extend:SI (match_dup 1))) | |
990 | (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))] | |
991 | { | |
992 | split_di (operands, 1, operands + 2, operands + 3); | |
993 | }) | |
994 | ||
995 | (define_insn_and_split "extendhidi2" | |
996 | [(set (match_operand:DI 0 "register_operand" "=d") | |
997 | (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))] | |
998 | "" | |
999 | "#" | |
1000 | "reload_completed" | |
1001 | [(set (match_dup 2) (sign_extend:SI (match_dup 1))) | |
1002 | (set (match_dup 3) (sign_extend:SI (match_dup 1))) | |
1003 | (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))] | |
1004 | { | |
1005 | split_di (operands, 1, operands + 2, operands + 3); | |
1006 | }) | |
1007 | ||
1008 | ;; DImode arithmetic operations | |
1009 | ||
1010 | (define_insn "adddi3" | |
1011 | [(set (match_operand:DI 0 "register_operand" "=&d,&d,&d") | |
1012 | (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0") | |
1013 | (match_operand:DI 2 "nonmemory_operand" "Kn7,Ks7,d"))) | |
1014 | (clobber (match_scratch:SI 3 "=&d,&d,&d")) | |
1015 | (clobber (reg:CC 34))] | |
1016 | "" | |
1017 | "@ | |
1018 | %0 += %2; cc = ac0; %3 = cc; %H0 += -1; %H0 = %H0 + %3; | |
1019 | %0 += %2; cc = ac0; %3 = cc; %H0 = %H0 + %3; | |
1020 | %0 = %0 + %2; cc = ac0; %3 = cc; %H0 = %H0 + %H2; %H0 = %H0 + %3;" | |
1021 | [(set_attr "type" "alu0") | |
b03149e1 JZ |
1022 | (set_attr "length" "10,8,10") |
1023 | (set_attr "seq_insns" "multi,multi,multi")]) | |
0d4a78eb BS |
1024 | |
1025 | (define_insn "subdi3" | |
1026 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
1027 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
1028 | (match_operand:DI 2 "register_operand" "d"))) | |
1029 | (clobber (reg:CC 34))] | |
1030 | "" | |
1031 | "%0 = %1-%2;\\n\\tcc = ac0;\\n\\t%H0 = %H1-%H2;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:" | |
b03149e1 JZ |
1032 | [(set_attr "length" "10") |
1033 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
1034 | |
1035 | (define_insn "*subdi_di_zesidi" | |
1036 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1037 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
1038 | (zero_extend:DI | |
1039 | (match_operand:SI 2 "register_operand" "d")))) | |
1040 | (clobber (match_scratch:SI 3 "=&d")) | |
1041 | (clobber (reg:CC 34))] | |
1042 | "" | |
1043 | "%0 = %1 - %2;\\n\\tcc = ac0;\\n\\tcc = ! cc;\\n\\t%3 = cc;\\n\\t%H0 = %H1 - %3;" | |
b03149e1 JZ |
1044 | [(set_attr "length" "10") |
1045 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
1046 | |
1047 | (define_insn "*subdi_zesidi_di" | |
1048 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1049 | (minus:DI (zero_extend:DI | |
1050 | (match_operand:SI 2 "register_operand" "d")) | |
1051 | (match_operand:DI 1 "register_operand" "0"))) | |
1052 | (clobber (match_scratch:SI 3 "=&d")) | |
1053 | (clobber (reg:CC 34))] | |
1054 | "" | |
1055 | "%0 = %2 - %1;\\n\\tcc = ac0;\\n\\tcc = ! cc;\\n\\t%3 = cc;\\n\\t%3 = -%3;\\n\\t%H0 = %3 - %H1" | |
b03149e1 JZ |
1056 | [(set_attr "length" "12") |
1057 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
1058 | |
1059 | (define_insn "*subdi_di_sesidi" | |
1060 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1061 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
1062 | (sign_extend:DI | |
1063 | (match_operand:SI 2 "register_operand" "d")))) | |
1064 | (clobber (match_scratch:SI 3 "=&d")) | |
1065 | (clobber (reg:CC 34))] | |
1066 | "" | |
1067 | "%0 = %1 - %2;\\n\\tcc = ac0;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %H1 - %3;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:" | |
b03149e1 JZ |
1068 | [(set_attr "length" "14") |
1069 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
1070 | |
1071 | (define_insn "*subdi_sesidi_di" | |
1072 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1073 | (minus:DI (sign_extend:DI | |
1074 | (match_operand:SI 2 "register_operand" "d")) | |
1075 | (match_operand:DI 1 "register_operand" "0"))) | |
1076 | (clobber (match_scratch:SI 3 "=&d")) | |
1077 | (clobber (reg:CC 34))] | |
1078 | "" | |
1079 | "%0 = %2 - %1;\\n\\tcc = ac0;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %3 - %H1;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:" | |
b03149e1 JZ |
1080 | [(set_attr "length" "14") |
1081 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
1082 | |
1083 | ;; Combined shift/add instructions | |
1084 | ||
1085 | (define_insn "" | |
1086 | [(set (match_operand:SI 0 "register_operand" "=a,d") | |
1087 | (ashift:SI (plus:SI (match_operand:SI 1 "register_operand" "%0,0") | |
1088 | (match_operand:SI 2 "register_operand" "a,d")) | |
1089 | (match_operand:SI 3 "pos_scale_operand" "P1P2,P1P2")))] | |
1090 | "" | |
1091 | "%0 = (%0 + %2) << %3;" /* "shadd %0,%2,%3;" */ | |
1092 | [(set_attr "type" "alu0")]) | |
1093 | ||
1094 | (define_insn "" | |
1095 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1096 | (plus:SI (match_operand:SI 1 "register_operand" "a") | |
1097 | (mult:SI (match_operand:SI 2 "register_operand" "a") | |
1098 | (match_operand:SI 3 "scale_by_operand" "i"))))] | |
1099 | "" | |
1100 | "%0 = %1 + (%2 << %X3);" | |
1101 | [(set_attr "type" "alu0")]) | |
1102 | ||
1103 | (define_insn "" | |
1104 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1105 | (plus:SI (match_operand:SI 1 "register_operand" "a") | |
1106 | (ashift:SI (match_operand:SI 2 "register_operand" "a") | |
1107 | (match_operand:SI 3 "pos_scale_operand" "i"))))] | |
1108 | "" | |
1109 | "%0 = %1 + (%2 << %3);" | |
1110 | [(set_attr "type" "alu0")]) | |
1111 | ||
1112 | (define_insn "" | |
1113 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1114 | (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "a") | |
1115 | (match_operand:SI 2 "scale_by_operand" "i")) | |
1116 | (match_operand:SI 3 "register_operand" "a")))] | |
1117 | "" | |
1118 | "%0 = %3 + (%1 << %X2);" | |
1119 | [(set_attr "type" "alu0")]) | |
1120 | ||
1121 | (define_insn "" | |
1122 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1123 | (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "a") | |
1124 | (match_operand:SI 2 "pos_scale_operand" "i")) | |
1125 | (match_operand:SI 3 "register_operand" "a")))] | |
1126 | "" | |
1127 | "%0 = %3 + (%1 << %2);" | |
1128 | [(set_attr "type" "alu0")]) | |
1129 | ||
1130 | (define_insn "mulhisi3" | |
1131 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1132 | (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%d")) | |
1133 | (sign_extend:SI (match_operand:HI 2 "register_operand" "d"))))] | |
1134 | "" | |
bbbc206e | 1135 | "%0 = %h1 * %h2 (IS)%!" |
0d4a78eb BS |
1136 | [(set_attr "type" "dsp32")]) |
1137 | ||
1138 | (define_insn "umulhisi3" | |
1139 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1140 | (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%d")) | |
1141 | (zero_extend:SI (match_operand:HI 2 "register_operand" "d"))))] | |
1142 | "" | |
bbbc206e | 1143 | "%0 = %h1 * %h2 (FU)%!" |
0d4a78eb BS |
1144 | [(set_attr "type" "dsp32")]) |
1145 | ||
8b44057d BS |
1146 | (define_insn "usmulhisi3" |
1147 | [(set (match_operand:SI 0 "register_operand" "=W") | |
1148 | (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "W")) | |
1149 | (sign_extend:SI (match_operand:HI 2 "register_operand" "W"))))] | |
1150 | "" | |
bbbc206e | 1151 | "%0 = %h2 * %h1 (IS,M)%!" |
8b44057d BS |
1152 | [(set_attr "type" "dsp32")]) |
1153 | ||
0d4a78eb BS |
1154 | ;; The processor also supports ireg += mreg or ireg -= mreg, but these |
1155 | ;; are unusable if we don't ensure that the corresponding lreg is zero. | |
1156 | ;; The same applies to the add/subtract constant versions involving | |
1157 | ;; iregs | |
1158 | ||
1159 | (define_insn "addsi3" | |
1160 | [(set (match_operand:SI 0 "register_operand" "=ad,a,d") | |
1161 | (plus:SI (match_operand:SI 1 "register_operand" "%0, a,d") | |
1162 | (match_operand:SI 2 "reg_or_7bit_operand" "Ks7, a,d")))] | |
1163 | "" | |
1164 | "@ | |
1165 | %0 += %2; | |
1166 | %0 = %1 + %2; | |
1167 | %0 = %1 + %2;" | |
1168 | [(set_attr "type" "alu0") | |
1169 | (set_attr "length" "2,2,2")]) | |
1170 | ||
75d8b2d0 BS |
1171 | (define_insn "ssaddsi3" |
1172 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1173 | (ss_plus:SI (match_operand:SI 1 "register_operand" "d") | |
1174 | (match_operand:SI 2 "register_operand" "d")))] | |
1175 | "" | |
bbbc206e | 1176 | "%0 = %1 + %2 (S)%!" |
75d8b2d0 BS |
1177 | [(set_attr "type" "dsp32")]) |
1178 | ||
d4e85050 | 1179 | (define_insn "subsi3" |
0d4a78eb BS |
1180 | [(set (match_operand:SI 0 "register_operand" "=da,d,a") |
1181 | (minus:SI (match_operand:SI 1 "register_operand" "0,d,0") | |
d4e85050 BS |
1182 | (match_operand:SI 2 "reg_or_neg7bit_operand" "KN7,d,a")))] |
1183 | "" | |
0d4a78eb BS |
1184 | { |
1185 | static const char *const strings_subsi3[] = { | |
1186 | "%0 += -%2;", | |
1187 | "%0 = %1 - %2;", | |
1188 | "%0 -= %2;", | |
1189 | }; | |
1190 | ||
1191 | if (CONSTANT_P (operands[2]) && INTVAL (operands[2]) < 0) { | |
1192 | rtx tmp_op = operands[2]; | |
1193 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
1194 | output_asm_insn ("%0 += %2;", operands); | |
1195 | operands[2] = tmp_op; | |
1196 | return ""; | |
1197 | } | |
1198 | ||
1199 | return strings_subsi3[which_alternative]; | |
1200 | } | |
1201 | [(set_attr "type" "alu0")]) | |
1202 | ||
75d8b2d0 BS |
1203 | (define_insn "sssubsi3" |
1204 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1205 | (ss_minus:SI (match_operand:SI 1 "register_operand" "d") | |
1206 | (match_operand:SI 2 "register_operand" "d")))] | |
1207 | "" | |
bbbc206e | 1208 | "%0 = %1 - %2 (S)%!" |
75d8b2d0 BS |
1209 | [(set_attr "type" "dsp32")]) |
1210 | ||
0d4a78eb BS |
1211 | ;; Bit test instructions |
1212 | ||
1213 | (define_insn "*not_bittst" | |
4729dc92 | 1214 | [(set (match_operand:BI 0 "register_operand" "=C") |
0d4a78eb BS |
1215 | (eq:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d") |
1216 | (const_int 1) | |
1217 | (match_operand:SI 2 "immediate_operand" "Ku5")) | |
1218 | (const_int 0)))] | |
1219 | "" | |
1220 | "cc = !BITTST (%1,%2);" | |
1221 | [(set_attr "type" "alu0")]) | |
1222 | ||
1223 | (define_insn "*bittst" | |
4729dc92 | 1224 | [(set (match_operand:BI 0 "register_operand" "=C") |
0d4a78eb BS |
1225 | (ne:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d") |
1226 | (const_int 1) | |
1227 | (match_operand:SI 2 "immediate_operand" "Ku5")) | |
1228 | (const_int 0)))] | |
1229 | "" | |
1230 | "cc = BITTST (%1,%2);" | |
1231 | [(set_attr "type" "alu0")]) | |
1232 | ||
1233 | (define_insn_and_split "*bit_extract" | |
1234 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1235 | (zero_extract:SI (match_operand:SI 1 "register_operand" "d") | |
1236 | (const_int 1) | |
1237 | (match_operand:SI 2 "immediate_operand" "Ku5"))) | |
1238 | (clobber (reg:BI REG_CC))] | |
1239 | "" | |
1240 | "#" | |
1241 | "" | |
1242 | [(set (reg:BI REG_CC) | |
1243 | (ne:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2)) | |
1244 | (const_int 0))) | |
1245 | (set (match_dup 0) | |
1246 | (ne:SI (reg:BI REG_CC) (const_int 0)))]) | |
1247 | ||
1248 | (define_insn_and_split "*not_bit_extract" | |
1249 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1250 | (zero_extract:SI (not:SI (match_operand:SI 1 "register_operand" "d")) | |
1251 | (const_int 1) | |
1252 | (match_operand:SI 2 "immediate_operand" "Ku5"))) | |
1253 | (clobber (reg:BI REG_CC))] | |
1254 | "" | |
1255 | "#" | |
1256 | "" | |
1257 | [(set (reg:BI REG_CC) | |
1258 | (eq:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2)) | |
1259 | (const_int 0))) | |
1260 | (set (match_dup 0) | |
1261 | (ne:SI (reg:BI REG_CC) (const_int 0)))]) | |
1262 | ||
1263 | (define_insn "*andsi_insn" | |
1264 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") | |
1265 | (and:SI (match_operand:SI 1 "register_operand" "%0,d,d,d") | |
1266 | (match_operand:SI 2 "rhs_andsi3_operand" "L,M1,M2,d")))] | |
1267 | "" | |
1268 | "@ | |
1269 | BITCLR (%0,%Y2); | |
1270 | %0 = %T1 (Z); | |
1271 | %0 = %h1 (Z); | |
1272 | %0 = %1 & %2;" | |
1273 | [(set_attr "type" "alu0")]) | |
1274 | ||
1275 | (define_expand "andsi3" | |
1276 | [(set (match_operand:SI 0 "register_operand" "") | |
1277 | (and:SI (match_operand:SI 1 "register_operand" "") | |
1278 | (match_operand:SI 2 "general_operand" "")))] | |
1279 | "" | |
1280 | { | |
1281 | if (highbits_operand (operands[2], SImode)) | |
1282 | { | |
1283 | operands[2] = GEN_INT (exact_log2 (-INTVAL (operands[2]))); | |
1284 | emit_insn (gen_ashrsi3 (operands[0], operands[1], operands[2])); | |
1285 | emit_insn (gen_ashlsi3 (operands[0], operands[0], operands[2])); | |
1286 | DONE; | |
1287 | } | |
1288 | if (! rhs_andsi3_operand (operands[2], SImode)) | |
1289 | operands[2] = force_reg (SImode, operands[2]); | |
1290 | }) | |
1291 | ||
1292 | (define_insn "iorsi3" | |
1293 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1294 | (ior:SI (match_operand:SI 1 "register_operand" "%0,d") | |
1295 | (match_operand:SI 2 "regorlog2_operand" "J,d")))] | |
1296 | "" | |
1297 | "@ | |
1298 | BITSET (%0, %X2); | |
1299 | %0 = %1 | %2;" | |
1300 | [(set_attr "type" "alu0")]) | |
1301 | ||
1302 | (define_insn "xorsi3" | |
1303 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1304 | (xor:SI (match_operand:SI 1 "register_operand" "%0,d") | |
1305 | (match_operand:SI 2 "regorlog2_operand" "J,d")))] | |
1306 | "" | |
1307 | "@ | |
1308 | BITTGL (%0, %X2); | |
1309 | %0 = %1 ^ %2;" | |
1310 | [(set_attr "type" "alu0")]) | |
1311 | ||
1312 | (define_insn "smaxsi3" | |
1313 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1314 | (smax:SI (match_operand:SI 1 "register_operand" "d") | |
1315 | (match_operand:SI 2 "register_operand" "d")))] | |
1316 | "" | |
bbbc206e | 1317 | "%0 = max(%1,%2)%!" |
0d4a78eb BS |
1318 | [(set_attr "type" "dsp32")]) |
1319 | ||
1320 | (define_insn "sminsi3" | |
1321 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1322 | (smin:SI (match_operand:SI 1 "register_operand" "d") | |
1323 | (match_operand:SI 2 "register_operand" "d")))] | |
1324 | "" | |
bbbc206e | 1325 | "%0 = min(%1,%2)%!" |
0d4a78eb BS |
1326 | [(set_attr "type" "dsp32")]) |
1327 | ||
1328 | (define_insn "abssi2" | |
1329 | [(set (match_operand:SI 0 "register_operand" "=d") | |
75d8b2d0 | 1330 | (abs:SI (match_operand:SI 1 "register_operand" "d")))] |
0d4a78eb | 1331 | "" |
bbbc206e | 1332 | "%0 = abs %1%!" |
0d4a78eb BS |
1333 | [(set_attr "type" "dsp32")]) |
1334 | ||
0d4a78eb BS |
1335 | (define_insn "negsi2" |
1336 | [(set (match_operand:SI 0 "register_operand" "=d") | |
75d8b2d0 | 1337 | (neg:SI (match_operand:SI 1 "register_operand" "d")))] |
0d4a78eb | 1338 | "" |
75d8b2d0 | 1339 | "%0 = -%1;" |
0d4a78eb BS |
1340 | [(set_attr "type" "alu0")]) |
1341 | ||
75d8b2d0 BS |
1342 | (define_insn "ssnegsi2" |
1343 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1344 | (ss_neg:SI (match_operand:SI 1 "register_operand" "d")))] | |
1345 | "" | |
bbbc206e | 1346 | "%0 = -%1 (S)%!" |
75d8b2d0 BS |
1347 | [(set_attr "type" "dsp32")]) |
1348 | ||
0d4a78eb BS |
1349 | (define_insn "one_cmplsi2" |
1350 | [(set (match_operand:SI 0 "register_operand" "=d") | |
75d8b2d0 | 1351 | (not:SI (match_operand:SI 1 "register_operand" "d")))] |
0d4a78eb | 1352 | "" |
75d8b2d0 | 1353 | "%0 = ~%1;" |
0d4a78eb BS |
1354 | [(set_attr "type" "alu0")]) |
1355 | ||
75d8b2d0 BS |
1356 | (define_insn "signbitssi2" |
1357 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1358 | (if_then_else:HI | |
1359 | (lt (match_operand:SI 1 "register_operand" "d") (const_int 0)) | |
1360 | (clz:HI (not:SI (match_dup 1))) | |
1361 | (clz:HI (match_dup 1))))] | |
1362 | "" | |
bbbc206e | 1363 | "%h0 = signbits %1%!" |
75d8b2d0 BS |
1364 | [(set_attr "type" "dsp32")]) |
1365 | ||
1366 | (define_insn "smaxhi3" | |
1367 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1368 | (smax:HI (match_operand:HI 1 "register_operand" "d") | |
1369 | (match_operand:HI 2 "register_operand" "d")))] | |
1370 | "" | |
bbbc206e | 1371 | "%0 = max(%1,%2) (V)%!" |
75d8b2d0 BS |
1372 | [(set_attr "type" "dsp32")]) |
1373 | ||
1374 | (define_insn "sminhi3" | |
1375 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1376 | (smin:HI (match_operand:HI 1 "register_operand" "d") | |
1377 | (match_operand:HI 2 "register_operand" "d")))] | |
1378 | "" | |
bbbc206e | 1379 | "%0 = min(%1,%2) (V)%!" |
75d8b2d0 BS |
1380 | [(set_attr "type" "dsp32")]) |
1381 | ||
1382 | (define_insn "abshi2" | |
1383 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1384 | (abs:HI (match_operand:HI 1 "register_operand" "d")))] | |
1385 | "" | |
bbbc206e | 1386 | "%0 = abs %1 (V)%!" |
75d8b2d0 BS |
1387 | [(set_attr "type" "dsp32")]) |
1388 | ||
1389 | (define_insn "neghi2" | |
1390 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1391 | (neg:HI (match_operand:HI 1 "register_operand" "d")))] | |
1392 | "" | |
1393 | "%0 = -%1;" | |
bbbc206e | 1394 | [(set_attr "type" "alu0")]) |
75d8b2d0 BS |
1395 | |
1396 | (define_insn "ssneghi2" | |
1397 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1398 | (ss_neg:HI (match_operand:HI 1 "register_operand" "d")))] | |
1399 | "" | |
bbbc206e | 1400 | "%0 = -%1 (V)%!" |
75d8b2d0 BS |
1401 | [(set_attr "type" "dsp32")]) |
1402 | ||
1403 | (define_insn "signbitshi2" | |
1404 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1405 | (if_then_else:HI | |
1406 | (lt (match_operand:HI 1 "register_operand" "d") (const_int 0)) | |
1407 | (clz:HI (not:HI (match_dup 1))) | |
1408 | (clz:HI (match_dup 1))))] | |
1409 | "" | |
bbbc206e | 1410 | "%h0 = signbits %h1%!" |
75d8b2d0 BS |
1411 | [(set_attr "type" "dsp32")]) |
1412 | ||
0d4a78eb BS |
1413 | (define_insn "mulsi3" |
1414 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1415 | (mult:SI (match_operand:SI 1 "register_operand" "%0") | |
1416 | (match_operand:SI 2 "register_operand" "d")))] | |
1417 | "" | |
75d8b2d0 | 1418 | "%0 *= %2;" |
0d4a78eb BS |
1419 | [(set_attr "type" "mult")]) |
1420 | ||
1421 | (define_expand "ashlsi3" | |
1422 | [(set (match_operand:SI 0 "register_operand" "") | |
1423 | (ashift:SI (match_operand:SI 1 "register_operand" "") | |
1424 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
1425 | "" | |
1426 | { | |
1427 | if (GET_CODE (operands[2]) == CONST_INT | |
1428 | && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) | |
1429 | { | |
1430 | emit_insn (gen_movsi (operands[0], const0_rtx)); | |
1431 | DONE; | |
1432 | } | |
1433 | }) | |
1434 | ||
1435 | (define_insn_and_split "*ashlsi3_insn" | |
bbbc206e BS |
1436 | [(set (match_operand:SI 0 "register_operand" "=d,d,a,a,a") |
1437 | (ashift:SI (match_operand:SI 1 "register_operand" "0,d,a,a,a") | |
1438 | (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5,P1,P2,?P3P4")))] | |
0d4a78eb BS |
1439 | "" |
1440 | "@ | |
1441 | %0 <<= %2; | |
bbbc206e | 1442 | %0 = %1 << %2%! |
0d4a78eb BS |
1443 | %0 = %1 + %1; |
1444 | %0 = %1 << %2; | |
1445 | #" | |
1446 | "PREG_P (operands[0]) && INTVAL (operands[2]) > 2" | |
1447 | [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 2))) | |
1448 | (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))] | |
1449 | "operands[3] = GEN_INT (INTVAL (operands[2]) - 2);" | |
bbbc206e | 1450 | [(set_attr "type" "shft,dsp32,shft,shft,*")]) |
0d4a78eb BS |
1451 | |
1452 | (define_insn "ashrsi3" | |
bbbc206e BS |
1453 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
1454 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d") | |
1455 | (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5")))] | |
0d4a78eb | 1456 | "" |
bbbc206e BS |
1457 | "@ |
1458 | %0 >>>= %2; | |
1459 | %0 = %1 >>> %2%!" | |
1460 | [(set_attr "type" "shft,dsp32")]) | |
0d4a78eb | 1461 | |
49373252 BS |
1462 | (define_insn "ror_one" |
1463 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1464 | (ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") (const_int 1)) | |
1465 | (ashift:SI (zero_extend:SI (reg:BI REG_CC)) (const_int 31)))) | |
1466 | (set (reg:BI REG_CC) | |
1467 | (zero_extract:BI (match_dup 1) (const_int 1) (const_int 0)))] | |
1468 | "" | |
bbbc206e BS |
1469 | "%0 = ROT %1 BY -1%!" |
1470 | [(set_attr "type" "dsp32")]) | |
49373252 BS |
1471 | |
1472 | (define_insn "rol_one" | |
1473 | [(set (match_operand:SI 0 "register_operand" "+d") | |
1474 | (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") (const_int 1)) | |
1475 | (zero_extend:SI (reg:BI REG_CC)))) | |
1476 | (set (reg:BI REG_CC) | |
1477 | (zero_extract:BI (match_dup 1) (const_int 31) (const_int 0)))] | |
1478 | "" | |
bbbc206e BS |
1479 | "%0 = ROT %1 BY 1%!" |
1480 | [(set_attr "type" "dsp32")]) | |
49373252 BS |
1481 | |
1482 | (define_expand "lshrdi3" | |
1483 | [(set (match_operand:DI 0 "register_operand" "") | |
1484 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
1485 | (match_operand:DI 2 "general_operand" "")))] | |
1486 | "" | |
1487 | { | |
1488 | rtx lo_half[2], hi_half[2]; | |
1489 | ||
1490 | if (operands[2] != const1_rtx) | |
1491 | FAIL; | |
1492 | if (! rtx_equal_p (operands[0], operands[1])) | |
1493 | emit_move_insn (operands[0], operands[1]); | |
1494 | ||
1495 | split_di (operands, 2, lo_half, hi_half); | |
1496 | ||
1497 | emit_move_insn (bfin_cc_rtx, const0_rtx); | |
1498 | emit_insn (gen_ror_one (hi_half[0], hi_half[0])); | |
1499 | emit_insn (gen_ror_one (lo_half[0], lo_half[0])); | |
1500 | DONE; | |
1501 | }) | |
1502 | ||
1503 | (define_expand "ashrdi3" | |
1504 | [(set (match_operand:DI 0 "register_operand" "") | |
1505 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
1506 | (match_operand:DI 2 "general_operand" "")))] | |
1507 | "" | |
1508 | { | |
1509 | rtx lo_half[2], hi_half[2]; | |
1510 | ||
1511 | if (operands[2] != const1_rtx) | |
1512 | FAIL; | |
1513 | if (! rtx_equal_p (operands[0], operands[1])) | |
1514 | emit_move_insn (operands[0], operands[1]); | |
1515 | ||
1516 | split_di (operands, 2, lo_half, hi_half); | |
1517 | ||
1518 | emit_insn (gen_compare_lt (gen_rtx_REG (BImode, REG_CC), | |
1519 | hi_half[1], const0_rtx)); | |
1520 | emit_insn (gen_ror_one (hi_half[0], hi_half[0])); | |
1521 | emit_insn (gen_ror_one (lo_half[0], lo_half[0])); | |
1522 | DONE; | |
1523 | }) | |
1524 | ||
1525 | (define_expand "ashldi3" | |
1526 | [(set (match_operand:DI 0 "register_operand" "") | |
1527 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
1528 | (match_operand:DI 2 "general_operand" "")))] | |
1529 | "" | |
1530 | { | |
1531 | rtx lo_half[2], hi_half[2]; | |
1532 | ||
1533 | if (operands[2] != const1_rtx) | |
1534 | FAIL; | |
1535 | if (! rtx_equal_p (operands[0], operands[1])) | |
1536 | emit_move_insn (operands[0], operands[1]); | |
1537 | ||
1538 | split_di (operands, 2, lo_half, hi_half); | |
1539 | ||
1540 | emit_move_insn (bfin_cc_rtx, const0_rtx); | |
1541 | emit_insn (gen_rol_one (lo_half[0], lo_half[0])); | |
1542 | emit_insn (gen_rol_one (hi_half[0], hi_half[0])); | |
1543 | DONE; | |
1544 | }) | |
1545 | ||
0d4a78eb | 1546 | (define_insn "lshrsi3" |
bbbc206e BS |
1547 | [(set (match_operand:SI 0 "register_operand" "=d,d,a") |
1548 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,d,a") | |
1549 | (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5,P1P2")))] | |
0d4a78eb BS |
1550 | "" |
1551 | "@ | |
1552 | %0 >>= %2; | |
bbbc206e | 1553 | %0 = %1 >> %2%! |
0d4a78eb | 1554 | %0 = %1 >> %2;" |
bbbc206e | 1555 | [(set_attr "type" "shft,dsp32,shft")]) |
0d4a78eb BS |
1556 | |
1557 | ;; A pattern to reload the equivalent of | |
1558 | ;; (set (Dreg) (plus (FP) (large_constant))) | |
1559 | ;; or | |
1560 | ;; (set (dagreg) (plus (FP) (arbitrary_constant))) | |
1561 | ;; using a scratch register | |
1562 | (define_expand "reload_insi" | |
1563 | [(parallel [(set (match_operand:SI 0 "register_operand" "=w") | |
1564 | (match_operand:SI 1 "fp_plus_const_operand" "")) | |
1565 | (clobber (match_operand:SI 2 "register_operand" "=&a"))])] | |
1566 | "" | |
1567 | { | |
1568 | rtx fp_op = XEXP (operands[1], 0); | |
1569 | rtx const_op = XEXP (operands[1], 1); | |
1570 | rtx primary = operands[0]; | |
1571 | rtx scratch = operands[2]; | |
1572 | ||
1573 | emit_move_insn (scratch, const_op); | |
1574 | emit_insn (gen_addsi3 (scratch, scratch, fp_op)); | |
1575 | emit_move_insn (primary, scratch); | |
1576 | DONE; | |
1577 | }) | |
1578 | ||
1579 | ;; Jump instructions | |
1580 | ||
1581 | (define_insn "jump" | |
1582 | [(set (pc) | |
1583 | (label_ref (match_operand 0 "" "")))] | |
1584 | "" | |
1585 | { | |
1586 | if (get_attr_length (insn) == 2) | |
1587 | return "jump.s %0;"; | |
1588 | else | |
1589 | return "jump.l %0;"; | |
1590 | } | |
1591 | [(set_attr "type" "br")]) | |
1592 | ||
1593 | (define_insn "indirect_jump" | |
1594 | [(set (pc) | |
1595 | (match_operand:SI 0 "register_operand" "a"))] | |
1596 | "" | |
1597 | "jump (%0);" | |
1598 | [(set_attr "type" "misc")]) | |
1599 | ||
1600 | (define_expand "tablejump" | |
1601 | [(parallel [(set (pc) (match_operand:SI 0 "register_operand" "a")) | |
1602 | (use (label_ref (match_operand 1 "" "")))])] | |
1603 | "" | |
1604 | { | |
1605 | /* In PIC mode, the table entries are stored PC relative. | |
1606 | Convert the relative address to an absolute address. */ | |
1607 | if (flag_pic) | |
1608 | { | |
1609 | rtx op1 = gen_rtx_LABEL_REF (Pmode, operands[1]); | |
1610 | ||
1611 | operands[0] = expand_simple_binop (Pmode, PLUS, operands[0], | |
1612 | op1, NULL_RTX, 0, OPTAB_DIRECT); | |
1613 | } | |
1614 | }) | |
1615 | ||
1616 | (define_insn "*tablejump_internal" | |
1617 | [(set (pc) (match_operand:SI 0 "register_operand" "a")) | |
1618 | (use (label_ref (match_operand 1 "" "")))] | |
1619 | "" | |
1620 | "jump (%0);" | |
1621 | [(set_attr "type" "misc")]) | |
1622 | ||
b03149e1 JZ |
1623 | ;; Hardware loop |
1624 | ||
1625 | ; operand 0 is the loop count pseudo register | |
1626 | ; operand 1 is the number of loop iterations or 0 if it is unknown | |
1627 | ; operand 2 is the maximum number of loop iterations | |
1628 | ; operand 3 is the number of levels of enclosed loops | |
1629 | ; operand 4 is the label to jump to at the top of the loop | |
1630 | (define_expand "doloop_end" | |
1631 | [(parallel [(set (pc) (if_then_else | |
1632 | (ne (match_operand:SI 0 "" "") | |
1633 | (const_int 1)) | |
1634 | (label_ref (match_operand 4 "" "")) | |
1635 | (pc))) | |
1636 | (set (match_dup 0) | |
1637 | (plus:SI (match_dup 0) | |
1638 | (const_int -1))) | |
1639 | (unspec [(const_int 0)] UNSPEC_LSETUP_END) | |
1640 | (clobber (match_scratch:SI 5 ""))])] | |
1641 | "" | |
0a8f8c45 | 1642 | { |
9b02a95e BS |
1643 | /* The loop optimizer doesn't check the predicates... */ |
1644 | if (GET_MODE (operands[0]) != SImode) | |
1645 | FAIL; | |
0a8f8c45 BS |
1646 | /* Due to limitations in the hardware (an initial loop count of 0 |
1647 | does not loop 2^32 times) we must avoid to generate a hardware | |
1648 | loops when we cannot rule out this case. */ | |
0a8f8c45 BS |
1649 | if (!flag_unsafe_loop_optimizations |
1650 | && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 0xFFFFFFFF) | |
1651 | FAIL; | |
1652 | bfin_hardware_loop (); | |
1653 | }) | |
b03149e1 JZ |
1654 | |
1655 | (define_insn "loop_end" | |
1656 | [(set (pc) | |
a9c46998 | 1657 | (if_then_else (ne (match_operand:SI 0 "nonimmediate_operand" "+a*d,*b*v*f,m") |
b03149e1 JZ |
1658 | (const_int 1)) |
1659 | (label_ref (match_operand 1 "" "")) | |
1660 | (pc))) | |
1661 | (set (match_dup 0) | |
1662 | (plus (match_dup 0) | |
1663 | (const_int -1))) | |
1664 | (unspec [(const_int 0)] UNSPEC_LSETUP_END) | |
1665 | (clobber (match_scratch:SI 2 "=X,&r,&r"))] | |
1666 | "" | |
1667 | "@ | |
1668 | /* loop end %0 %l1 */ | |
1669 | # | |
1670 | #" | |
1671 | [(set_attr "length" "6,10,14")]) | |
1672 | ||
1673 | (define_split | |
1674 | [(set (pc) | |
1675 | (if_then_else (ne (match_operand:SI 0 "nondp_reg_or_memory_operand" "") | |
1676 | (const_int 1)) | |
1677 | (label_ref (match_operand 1 "" "")) | |
1678 | (pc))) | |
1679 | (set (match_dup 0) | |
1680 | (plus (match_dup 0) | |
1681 | (const_int -1))) | |
1682 | (unspec [(const_int 0)] UNSPEC_LSETUP_END) | |
1683 | (clobber (match_scratch:SI 2 "=&r"))] | |
1684 | "reload_completed" | |
1685 | [(set (match_dup 2) (match_dup 0)) | |
1686 | (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
1687 | (set (match_dup 0) (match_dup 2)) | |
1688 | (set (reg:BI REG_CC) (eq:BI (match_dup 2) (const_int 0))) | |
1689 | (set (pc) | |
1690 | (if_then_else (eq (reg:BI REG_CC) | |
1691 | (const_int 0)) | |
1692 | (label_ref (match_dup 1)) | |
1693 | (pc)))] | |
1694 | "") | |
1695 | ||
1696 | (define_insn "lsetup_with_autoinit" | |
1697 | [(set (match_operand:SI 0 "lt_register_operand" "=t") | |
1698 | (label_ref (match_operand 1 "" ""))) | |
a9c46998 | 1699 | (set (match_operand:SI 2 "lb_register_operand" "=u") |
b03149e1 JZ |
1700 | (label_ref (match_operand 3 "" ""))) |
1701 | (set (match_operand:SI 4 "lc_register_operand" "=k") | |
1702 | (match_operand:SI 5 "register_operand" "a"))] | |
1703 | "" | |
1704 | "LSETUP (%1, %3) %4 = %5;" | |
1705 | [(set_attr "length" "4")]) | |
1706 | ||
1707 | (define_insn "lsetup_without_autoinit" | |
1708 | [(set (match_operand:SI 0 "lt_register_operand" "=t") | |
1709 | (label_ref (match_operand 1 "" ""))) | |
a9c46998 | 1710 | (set (match_operand:SI 2 "lb_register_operand" "=u") |
b03149e1 JZ |
1711 | (label_ref (match_operand 3 "" ""))) |
1712 | (use (match_operand:SI 4 "lc_register_operand" "k"))] | |
1713 | "" | |
1714 | "LSETUP (%1, %3) %4;" | |
1715 | [(set_attr "length" "4")]) | |
1716 | ||
0d4a78eb BS |
1717 | ;; Call instructions.. |
1718 | ||
6614f9f5 BS |
1719 | ;; The explicit MEM inside the UNSPEC prevents the compiler from moving |
1720 | ;; the load before a branch after a NULL test, or before a store that | |
1721 | ;; initializes a function descriptor. | |
1722 | ||
1723 | (define_insn_and_split "load_funcdescsi" | |
1724 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1725 | (unspec_volatile:SI [(mem:SI (match_operand:SI 1 "address_operand" "p"))] | |
1726 | UNSPEC_VOLATILE_LOAD_FUNCDESC))] | |
1727 | "" | |
1728 | "#" | |
1729 | "reload_completed" | |
1730 | [(set (match_dup 0) (mem:SI (match_dup 1)))]) | |
1731 | ||
0d4a78eb | 1732 | (define_expand "call" |
6d459e2b BS |
1733 | [(parallel [(call (match_operand:SI 0 "" "") |
1734 | (match_operand 1 "" "")) | |
1735 | (use (match_operand 2 "" ""))])] | |
0d4a78eb | 1736 | "" |
6d459e2b BS |
1737 | { |
1738 | bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 0); | |
1739 | DONE; | |
1740 | }) | |
0d4a78eb BS |
1741 | |
1742 | (define_expand "sibcall" | |
1743 | [(parallel [(call (match_operand:SI 0 "" "") | |
1744 | (match_operand 1 "" "")) | |
6d459e2b | 1745 | (use (match_operand 2 "" "")) |
0d4a78eb BS |
1746 | (return)])] |
1747 | "" | |
6d459e2b BS |
1748 | { |
1749 | bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 1); | |
1750 | DONE; | |
1751 | }) | |
0d4a78eb BS |
1752 | |
1753 | (define_expand "call_value" | |
6d459e2b BS |
1754 | [(parallel [(set (match_operand 0 "register_operand" "") |
1755 | (call (match_operand:SI 1 "" "") | |
1756 | (match_operand 2 "" ""))) | |
1757 | (use (match_operand 3 "" ""))])] | |
0d4a78eb | 1758 | "" |
6d459e2b BS |
1759 | { |
1760 | bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 0); | |
1761 | DONE; | |
1762 | }) | |
0d4a78eb BS |
1763 | |
1764 | (define_expand "sibcall_value" | |
1765 | [(parallel [(set (match_operand 0 "register_operand" "") | |
1766 | (call (match_operand:SI 1 "" "") | |
1767 | (match_operand 2 "" ""))) | |
6d459e2b | 1768 | (use (match_operand 3 "" "")) |
0d4a78eb BS |
1769 | (return)])] |
1770 | "" | |
6d459e2b BS |
1771 | { |
1772 | bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 1); | |
1773 | DONE; | |
1774 | }) | |
0d4a78eb | 1775 | |
6614f9f5 BS |
1776 | (define_insn "*call_symbol_fdpic" |
1777 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q")) | |
1778 | (match_operand 1 "general_operand" "g")) | |
1779 | (use (match_operand:SI 2 "register_operand" "Z")) | |
1780 | (use (match_operand 3 "" ""))] | |
1781 | "! SIBLING_CALL_P (insn) | |
1782 | && GET_CODE (operands[0]) == SYMBOL_REF | |
1783 | && !bfin_longcall_p (operands[0], INTVAL (operands[3]))" | |
1784 | "call %0;" | |
1785 | [(set_attr "type" "call") | |
1786 | (set_attr "length" "4")]) | |
1787 | ||
1788 | (define_insn "*sibcall_symbol_fdpic" | |
1789 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q")) | |
1790 | (match_operand 1 "general_operand" "g")) | |
1791 | (use (match_operand:SI 2 "register_operand" "Z")) | |
1792 | (use (match_operand 3 "" "")) | |
1793 | (return)] | |
1794 | "SIBLING_CALL_P (insn) | |
1795 | && GET_CODE (operands[0]) == SYMBOL_REF | |
1796 | && !bfin_longcall_p (operands[0], INTVAL (operands[3]))" | |
1797 | "jump.l %0;" | |
1798 | [(set_attr "type" "br") | |
1799 | (set_attr "length" "4")]) | |
1800 | ||
1801 | (define_insn "*call_value_symbol_fdpic" | |
1802 | [(set (match_operand 0 "register_operand" "=d") | |
1803 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q")) | |
1804 | (match_operand 2 "general_operand" "g"))) | |
1805 | (use (match_operand:SI 3 "register_operand" "Z")) | |
1806 | (use (match_operand 4 "" ""))] | |
1807 | "! SIBLING_CALL_P (insn) | |
1808 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1809 | && !bfin_longcall_p (operands[1], INTVAL (operands[4]))" | |
1810 | "call %1;" | |
1811 | [(set_attr "type" "call") | |
1812 | (set_attr "length" "4")]) | |
1813 | ||
1814 | (define_insn "*sibcall_value_symbol_fdpic" | |
1815 | [(set (match_operand 0 "register_operand" "=d") | |
1816 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q")) | |
1817 | (match_operand 2 "general_operand" "g"))) | |
1818 | (use (match_operand:SI 3 "register_operand" "Z")) | |
1819 | (use (match_operand 4 "" "")) | |
1820 | (return)] | |
1821 | "SIBLING_CALL_P (insn) | |
1822 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1823 | && !bfin_longcall_p (operands[1], INTVAL (operands[4]))" | |
1824 | "jump.l %1;" | |
1825 | [(set_attr "type" "br") | |
1826 | (set_attr "length" "4")]) | |
1827 | ||
1828 | (define_insn "*call_insn_fdpic" | |
1829 | [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y")) | |
1830 | (match_operand 1 "general_operand" "g")) | |
1831 | (use (match_operand:SI 2 "register_operand" "Z")) | |
1832 | (use (match_operand 3 "" ""))] | |
1833 | "! SIBLING_CALL_P (insn)" | |
1834 | "call (%0);" | |
1835 | [(set_attr "type" "call") | |
1836 | (set_attr "length" "2")]) | |
1837 | ||
1838 | (define_insn "*sibcall_insn_fdpic" | |
1839 | [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y")) | |
1840 | (match_operand 1 "general_operand" "g")) | |
1841 | (use (match_operand:SI 2 "register_operand" "Z")) | |
1842 | (use (match_operand 3 "" "")) | |
1843 | (return)] | |
1844 | "SIBLING_CALL_P (insn)" | |
1845 | "jump (%0);" | |
1846 | [(set_attr "type" "br") | |
1847 | (set_attr "length" "2")]) | |
1848 | ||
1849 | (define_insn "*call_value_insn_fdpic" | |
1850 | [(set (match_operand 0 "register_operand" "=d") | |
1851 | (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y")) | |
1852 | (match_operand 2 "general_operand" "g"))) | |
1853 | (use (match_operand:SI 3 "register_operand" "Z")) | |
1854 | (use (match_operand 4 "" ""))] | |
1855 | "! SIBLING_CALL_P (insn)" | |
1856 | "call (%1);" | |
1857 | [(set_attr "type" "call") | |
1858 | (set_attr "length" "2")]) | |
1859 | ||
1860 | (define_insn "*sibcall_value_insn_fdpic" | |
1861 | [(set (match_operand 0 "register_operand" "=d") | |
1862 | (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y")) | |
1863 | (match_operand 2 "general_operand" "g"))) | |
1864 | (use (match_operand:SI 3 "register_operand" "Z")) | |
1865 | (use (match_operand 4 "" "")) | |
1866 | (return)] | |
1867 | "SIBLING_CALL_P (insn)" | |
1868 | "jump (%1);" | |
1869 | [(set_attr "type" "br") | |
1870 | (set_attr "length" "2")]) | |
1871 | ||
6d459e2b BS |
1872 | (define_insn "*call_symbol" |
1873 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q")) | |
1874 | (match_operand 1 "general_operand" "g")) | |
1875 | (use (match_operand 2 "" ""))] | |
0d4a78eb | 1876 | "! SIBLING_CALL_P (insn) |
93147119 | 1877 | && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY) |
6d459e2b BS |
1878 | && GET_CODE (operands[0]) == SYMBOL_REF |
1879 | && !bfin_longcall_p (operands[0], INTVAL (operands[2]))" | |
96c30d2a | 1880 | "call %0;" |
0d4a78eb | 1881 | [(set_attr "type" "call") |
6d459e2b | 1882 | (set_attr "length" "4")]) |
0d4a78eb | 1883 | |
6d459e2b BS |
1884 | (define_insn "*sibcall_symbol" |
1885 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q")) | |
1886 | (match_operand 1 "general_operand" "g")) | |
1887 | (use (match_operand 2 "" "")) | |
0d4a78eb BS |
1888 | (return)] |
1889 | "SIBLING_CALL_P (insn) | |
93147119 | 1890 | && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY) |
6d459e2b BS |
1891 | && GET_CODE (operands[0]) == SYMBOL_REF |
1892 | && !bfin_longcall_p (operands[0], INTVAL (operands[2]))" | |
96c30d2a | 1893 | "jump.l %0;" |
0d4a78eb | 1894 | [(set_attr "type" "br") |
6d459e2b | 1895 | (set_attr "length" "4")]) |
0d4a78eb | 1896 | |
6d459e2b BS |
1897 | (define_insn "*call_value_symbol" |
1898 | [(set (match_operand 0 "register_operand" "=d") | |
1899 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q")) | |
1900 | (match_operand 2 "general_operand" "g"))) | |
1901 | (use (match_operand 3 "" ""))] | |
0d4a78eb | 1902 | "! SIBLING_CALL_P (insn) |
93147119 | 1903 | && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY) |
6d459e2b BS |
1904 | && GET_CODE (operands[1]) == SYMBOL_REF |
1905 | && !bfin_longcall_p (operands[1], INTVAL (operands[3]))" | |
96c30d2a | 1906 | "call %1;" |
0d4a78eb | 1907 | [(set_attr "type" "call") |
6d459e2b | 1908 | (set_attr "length" "4")]) |
0d4a78eb | 1909 | |
6d459e2b BS |
1910 | (define_insn "*sibcall_value_symbol" |
1911 | [(set (match_operand 0 "register_operand" "=d") | |
1912 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q")) | |
1913 | (match_operand 2 "general_operand" "g"))) | |
1914 | (use (match_operand 3 "" "")) | |
0d4a78eb BS |
1915 | (return)] |
1916 | "SIBLING_CALL_P (insn) | |
93147119 | 1917 | && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY) |
6d459e2b BS |
1918 | && GET_CODE (operands[1]) == SYMBOL_REF |
1919 | && !bfin_longcall_p (operands[1], INTVAL (operands[3]))" | |
96c30d2a | 1920 | "jump.l %1;" |
6d459e2b BS |
1921 | [(set_attr "type" "br") |
1922 | (set_attr "length" "4")]) | |
1923 | ||
1924 | (define_insn "*call_insn" | |
1925 | [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "a")) | |
1926 | (match_operand 1 "general_operand" "g")) | |
1927 | (use (match_operand 2 "" ""))] | |
1928 | "! SIBLING_CALL_P (insn)" | |
1929 | "call (%0);" | |
1930 | [(set_attr "type" "call") | |
1931 | (set_attr "length" "2")]) | |
1932 | ||
1933 | (define_insn "*sibcall_insn" | |
1934 | [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "z")) | |
1935 | (match_operand 1 "general_operand" "g")) | |
1936 | (use (match_operand 2 "" "")) | |
1937 | (return)] | |
1938 | "SIBLING_CALL_P (insn)" | |
1939 | "jump (%0);" | |
1940 | [(set_attr "type" "br") | |
1941 | (set_attr "length" "2")]) | |
1942 | ||
1943 | (define_insn "*call_value_insn" | |
1944 | [(set (match_operand 0 "register_operand" "=d") | |
1945 | (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "a")) | |
1946 | (match_operand 2 "general_operand" "g"))) | |
1947 | (use (match_operand 3 "" ""))] | |
1948 | "! SIBLING_CALL_P (insn)" | |
1949 | "call (%1);" | |
1950 | [(set_attr "type" "call") | |
1951 | (set_attr "length" "2")]) | |
1952 | ||
1953 | (define_insn "*sibcall_value_insn" | |
1954 | [(set (match_operand 0 "register_operand" "=d") | |
1955 | (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "z")) | |
1956 | (match_operand 2 "general_operand" "g"))) | |
1957 | (use (match_operand 3 "" "")) | |
1958 | (return)] | |
1959 | "SIBLING_CALL_P (insn)" | |
1960 | "jump (%1);" | |
0d4a78eb | 1961 | [(set_attr "type" "br") |
6d459e2b | 1962 | (set_attr "length" "2")]) |
0d4a78eb BS |
1963 | |
1964 | ;; Block move patterns | |
1965 | ||
1966 | ;; We cheat. This copies one more word than operand 2 indicates. | |
1967 | ||
1968 | (define_insn "rep_movsi" | |
1969 | [(set (match_operand:SI 0 "register_operand" "=&a") | |
1970 | (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0") | |
1971 | (ashift:SI (match_operand:SI 2 "register_operand" "a") | |
1972 | (const_int 2))) | |
1973 | (const_int 4))) | |
1974 | (set (match_operand:SI 1 "register_operand" "=&b") | |
1975 | (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1") | |
1976 | (ashift:SI (match_dup 2) (const_int 2))) | |
1977 | (const_int 4))) | |
1978 | (set (mem:BLK (match_dup 3)) | |
1979 | (mem:BLK (match_dup 4))) | |
1980 | (use (match_dup 2)) | |
b03149e1 JZ |
1981 | (clobber (match_scratch:HI 5 "=&d")) |
1982 | (clobber (reg:SI REG_LT1)) | |
1983 | (clobber (reg:SI REG_LC1)) | |
1984 | (clobber (reg:SI REG_LB1))] | |
0d4a78eb | 1985 | "" |
51a641fd | 1986 | "%5 = [%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || [%3++] = %5 || %5 = [%4++]; [%3++] = %5;" |
0d4a78eb | 1987 | [(set_attr "type" "misc") |
b03149e1 JZ |
1988 | (set_attr "length" "16") |
1989 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
1990 | |
1991 | (define_insn "rep_movhi" | |
1992 | [(set (match_operand:SI 0 "register_operand" "=&a") | |
1993 | (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0") | |
1994 | (ashift:SI (match_operand:SI 2 "register_operand" "a") | |
1995 | (const_int 1))) | |
1996 | (const_int 2))) | |
1997 | (set (match_operand:SI 1 "register_operand" "=&b") | |
1998 | (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1") | |
1999 | (ashift:SI (match_dup 2) (const_int 1))) | |
2000 | (const_int 2))) | |
2001 | (set (mem:BLK (match_dup 3)) | |
2002 | (mem:BLK (match_dup 4))) | |
2003 | (use (match_dup 2)) | |
b03149e1 JZ |
2004 | (clobber (match_scratch:HI 5 "=&d")) |
2005 | (clobber (reg:SI REG_LT1)) | |
2006 | (clobber (reg:SI REG_LC1)) | |
2007 | (clobber (reg:SI REG_LB1))] | |
0d4a78eb | 2008 | "" |
51a641fd | 2009 | "%h5 = W[%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || W [%3++] = %5 || %h5 = W [%4++]; W [%3++] = %5;" |
0d4a78eb | 2010 | [(set_attr "type" "misc") |
b03149e1 JZ |
2011 | (set_attr "length" "16") |
2012 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb | 2013 | |
144f8315 | 2014 | (define_expand "movmemsi" |
0d4a78eb BS |
2015 | [(match_operand:BLK 0 "general_operand" "") |
2016 | (match_operand:BLK 1 "general_operand" "") | |
2017 | (match_operand:SI 2 "const_int_operand" "") | |
2018 | (match_operand:SI 3 "const_int_operand" "")] | |
2019 | "" | |
2020 | { | |
144f8315 | 2021 | if (bfin_expand_movmem (operands[0], operands[1], operands[2], operands[3])) |
0d4a78eb BS |
2022 | DONE; |
2023 | FAIL; | |
2024 | }) | |
2025 | ||
2026 | ;; Conditional branch patterns | |
2027 | ;; The Blackfin has only few condition codes: eq, lt, lte, ltu, leu | |
2028 | ||
2029 | ;; The only outcome of this pattern is that global variables | |
2030 | ;; bfin_compare_op[01] are set for use in bcond patterns. | |
2031 | ||
2032 | (define_expand "cmpbi" | |
2033 | [(set (cc0) (compare (match_operand:BI 0 "register_operand" "") | |
2034 | (match_operand:BI 1 "immediate_operand" "")))] | |
2035 | "" | |
2036 | { | |
2037 | bfin_compare_op0 = operands[0]; | |
2038 | bfin_compare_op1 = operands[1]; | |
2039 | DONE; | |
2040 | }) | |
2041 | ||
2042 | (define_expand "cmpsi" | |
2043 | [(set (cc0) (compare (match_operand:SI 0 "register_operand" "") | |
7ddcf3d2 | 2044 | (match_operand:SI 1 "reg_or_const_int_operand" "")))] |
0d4a78eb BS |
2045 | "" |
2046 | { | |
2047 | bfin_compare_op0 = operands[0]; | |
2048 | bfin_compare_op1 = operands[1]; | |
2049 | DONE; | |
2050 | }) | |
2051 | ||
49373252 | 2052 | (define_insn "compare_eq" |
4729dc92 | 2053 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2054 | (eq:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2055 | (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] |
0d4a78eb BS |
2056 | "" |
2057 | "cc =%1==%2;" | |
2058 | [(set_attr "type" "compare")]) | |
2059 | ||
49373252 | 2060 | (define_insn "compare_ne" |
4729dc92 | 2061 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2062 | (ne:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2063 | (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] |
0d4a78eb BS |
2064 | "0" |
2065 | "cc =%1!=%2;" | |
2066 | [(set_attr "type" "compare")]) | |
2067 | ||
49373252 | 2068 | (define_insn "compare_lt" |
4729dc92 | 2069 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2070 | (lt:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2071 | (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] |
0d4a78eb BS |
2072 | "" |
2073 | "cc =%1<%2;" | |
2074 | [(set_attr "type" "compare")]) | |
2075 | ||
49373252 | 2076 | (define_insn "compare_le" |
4729dc92 | 2077 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2078 | (le:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2079 | (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] |
0d4a78eb BS |
2080 | "" |
2081 | "cc =%1<=%2;" | |
2082 | [(set_attr "type" "compare")]) | |
2083 | ||
49373252 | 2084 | (define_insn "compare_leu" |
4729dc92 | 2085 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2086 | (leu:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2087 | (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))] |
0d4a78eb BS |
2088 | "" |
2089 | "cc =%1<=%2 (iu);" | |
2090 | [(set_attr "type" "compare")]) | |
2091 | ||
49373252 | 2092 | (define_insn "compare_ltu" |
4729dc92 | 2093 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2094 | (ltu:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2095 | (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))] |
0d4a78eb BS |
2096 | "" |
2097 | "cc =%1<%2 (iu);" | |
2098 | [(set_attr "type" "compare")]) | |
2099 | ||
2100 | (define_expand "beq" | |
2101 | [(set (match_dup 1) (match_dup 2)) | |
2102 | (set (pc) | |
2103 | (if_then_else (match_dup 3) | |
2104 | (label_ref (match_operand 0 "" "")) | |
2105 | (pc)))] | |
2106 | "" | |
2107 | { | |
2108 | rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1; | |
2109 | operands[1] = bfin_cc_rtx; /* hard register: CC */ | |
2110 | operands[2] = gen_rtx_EQ (BImode, op0, op1); | |
2111 | /* If we have a BImode input, then we already have a compare result, and | |
2112 | do not need to emit another comparison. */ | |
2113 | if (GET_MODE (bfin_compare_op0) == BImode) | |
2114 | { | |
3b9dd769 NS |
2115 | gcc_assert (bfin_compare_op1 == const0_rtx); |
2116 | emit_insn (gen_cbranchbi4 (operands[2], op0, op1, operands[0])); | |
2117 | DONE; | |
0d4a78eb BS |
2118 | } |
2119 | ||
2120 | operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx); | |
2121 | }) | |
2122 | ||
2123 | (define_expand "bne" | |
2124 | [(set (match_dup 1) (match_dup 2)) | |
2125 | (set (pc) | |
2126 | (if_then_else (match_dup 3) | |
2127 | (label_ref (match_operand 0 "" "")) | |
2128 | (pc)))] | |
2129 | "" | |
2130 | { | |
2131 | rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1; | |
2132 | /* If we have a BImode input, then we already have a compare result, and | |
2133 | do not need to emit another comparison. */ | |
2134 | if (GET_MODE (bfin_compare_op0) == BImode) | |
2135 | { | |
3b9dd769 NS |
2136 | rtx cmp = gen_rtx_NE (BImode, op0, op1); |
2137 | ||
2138 | gcc_assert (bfin_compare_op1 == const0_rtx); | |
2139 | emit_insn (gen_cbranchbi4 (cmp, op0, op1, operands[0])); | |
2140 | DONE; | |
0d4a78eb BS |
2141 | } |
2142 | ||
2143 | operands[1] = bfin_cc_rtx; /* hard register: CC */ | |
2144 | operands[2] = gen_rtx_EQ (BImode, op0, op1); | |
2145 | operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx); | |
2146 | }) | |
2147 | ||
2148 | (define_expand "bgt" | |
2149 | [(set (match_dup 1) (match_dup 2)) | |
2150 | (set (pc) | |
2151 | (if_then_else (match_dup 3) | |
2152 | (label_ref (match_operand 0 "" "")) | |
2153 | (pc)))] | |
2154 | "" | |
2155 | { | |
2156 | operands[1] = bfin_cc_rtx; | |
2157 | operands[2] = gen_rtx_LE (BImode, bfin_compare_op0, bfin_compare_op1); | |
2158 | operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx); | |
2159 | }) | |
2160 | ||
2161 | (define_expand "bgtu" | |
2162 | [(set (match_dup 1) (match_dup 2)) | |
2163 | (set (pc) | |
2164 | (if_then_else (match_dup 3) | |
2165 | (label_ref (match_operand 0 "" "")) | |
2166 | (pc)))] | |
2167 | "" | |
2168 | { | |
2169 | operands[1] = bfin_cc_rtx; | |
2170 | operands[2] = gen_rtx_LEU (BImode, bfin_compare_op0, bfin_compare_op1); | |
2171 | operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx); | |
2172 | }) | |
2173 | ||
2174 | (define_expand "blt" | |
2175 | [(set (match_dup 1) (match_dup 2)) | |
2176 | (set (pc) | |
2177 | (if_then_else (match_dup 3) | |
2178 | (label_ref (match_operand 0 "" "")) | |
2179 | (pc)))] | |
2180 | "" | |
2181 | { | |
2182 | operands[1] = bfin_cc_rtx; | |
2183 | operands[2] = gen_rtx_LT (BImode, bfin_compare_op0, bfin_compare_op1); | |
2184 | operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx); | |
2185 | }) | |
2186 | ||
2187 | (define_expand "bltu" | |
2188 | [(set (match_dup 1) (match_dup 2)) | |
2189 | (set (pc) | |
2190 | (if_then_else (match_dup 3) | |
2191 | (label_ref (match_operand 0 "" "")) | |
2192 | (pc)))] | |
2193 | "" | |
2194 | { | |
2195 | operands[1] = bfin_cc_rtx; | |
2196 | operands[2] = gen_rtx_LTU (BImode, bfin_compare_op0, bfin_compare_op1); | |
2197 | operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx); | |
2198 | }) | |
2199 | ||
2200 | ||
2201 | (define_expand "bge" | |
2202 | [(set (match_dup 1) (match_dup 2)) | |
2203 | (set (pc) | |
2204 | (if_then_else (match_dup 3) | |
2205 | (label_ref (match_operand 0 "" "")) | |
2206 | (pc)))] | |
2207 | "" | |
2208 | { | |
2209 | operands[1] = bfin_cc_rtx; | |
2210 | operands[2] = gen_rtx_LT (BImode, bfin_compare_op0, bfin_compare_op1); | |
2211 | operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx); | |
2212 | }) | |
2213 | ||
2214 | (define_expand "bgeu" | |
2215 | [(set (match_dup 1) (match_dup 2)) | |
2216 | (set (pc) | |
2217 | (if_then_else (match_dup 3) | |
2218 | (label_ref (match_operand 0 "" "")) | |
2219 | (pc)))] | |
2220 | "" | |
2221 | { | |
2222 | operands[1] = bfin_cc_rtx; | |
2223 | operands[2] = gen_rtx_LTU (BImode, bfin_compare_op0, bfin_compare_op1); | |
2224 | operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx); | |
2225 | }) | |
2226 | ||
2227 | (define_expand "ble" | |
2228 | [(set (match_dup 1) (match_dup 2)) | |
2229 | (set (pc) | |
2230 | (if_then_else (match_dup 3) | |
2231 | (label_ref (match_operand 0 "" "")) | |
2232 | (pc)))] | |
2233 | "" | |
2234 | { | |
2235 | operands[1] = bfin_cc_rtx; | |
2236 | operands[2] = gen_rtx_LE (BImode, bfin_compare_op0, bfin_compare_op1); | |
2237 | operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx); | |
2238 | }) | |
2239 | ||
2240 | (define_expand "bleu" | |
2241 | [(set (match_dup 1) (match_dup 2)) | |
2242 | (set (pc) | |
2243 | (if_then_else (match_dup 3) | |
2244 | (label_ref (match_operand 0 "" "")) | |
2245 | (pc))) | |
2246 | ] | |
2247 | "" | |
2248 | { | |
2249 | operands[1] = bfin_cc_rtx; | |
2250 | operands[2] = gen_rtx_LEU (BImode, bfin_compare_op0, bfin_compare_op1); | |
2251 | operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx); | |
2252 | }) | |
2253 | ||
2254 | (define_insn "cbranchbi4" | |
2255 | [(set (pc) | |
2256 | (if_then_else | |
2257 | (match_operator 0 "bfin_cbranch_operator" | |
4729dc92 | 2258 | [(match_operand:BI 1 "register_operand" "C") |
0d4a78eb BS |
2259 | (match_operand:BI 2 "immediate_operand" "P0")]) |
2260 | (label_ref (match_operand 3 "" "")) | |
2261 | (pc)))] | |
2262 | "" | |
2263 | { | |
2264 | asm_conditional_branch (insn, operands, 0, 0); | |
2265 | return ""; | |
2266 | } | |
2267 | [(set_attr "type" "brcc")]) | |
2268 | ||
2269 | ;; Special cbranch patterns to deal with the speculative load problem - see | |
2270 | ;; bfin_reorg for details. | |
2271 | ||
2272 | (define_insn "cbranch_predicted_taken" | |
2273 | [(set (pc) | |
2274 | (if_then_else | |
2275 | (match_operator 0 "bfin_cbranch_operator" | |
4729dc92 | 2276 | [(match_operand:BI 1 "register_operand" "C") |
0d4a78eb BS |
2277 | (match_operand:BI 2 "immediate_operand" "P0")]) |
2278 | (label_ref (match_operand 3 "" "")) | |
2279 | (pc))) | |
2280 | (unspec [(const_int 0)] UNSPEC_CBRANCH_TAKEN)] | |
2281 | "" | |
2282 | { | |
2283 | asm_conditional_branch (insn, operands, 0, 1); | |
2284 | return ""; | |
2285 | } | |
2286 | [(set_attr "type" "brcc")]) | |
2287 | ||
2288 | (define_insn "cbranch_with_nops" | |
2289 | [(set (pc) | |
2290 | (if_then_else | |
2291 | (match_operator 0 "bfin_cbranch_operator" | |
4729dc92 | 2292 | [(match_operand:BI 1 "register_operand" "C") |
0d4a78eb BS |
2293 | (match_operand:BI 2 "immediate_operand" "P0")]) |
2294 | (label_ref (match_operand 3 "" "")) | |
2295 | (pc))) | |
2296 | (unspec [(match_operand 4 "immediate_operand" "")] UNSPEC_CBRANCH_NOPS)] | |
2297 | "reload_completed" | |
2298 | { | |
2299 | asm_conditional_branch (insn, operands, INTVAL (operands[4]), 0); | |
2300 | return ""; | |
2301 | } | |
2302 | [(set_attr "type" "brcc") | |
2303 | (set_attr "length" "6")]) | |
2304 | ||
2305 | ;; setcc insns. */ | |
2306 | (define_expand "seq" | |
2307 | [(set (match_dup 1) (eq:BI (match_dup 2) (match_dup 3))) | |
2308 | (set (match_operand:SI 0 "register_operand" "") | |
2309 | (ne:SI (match_dup 1) (const_int 0)))] | |
2310 | "" | |
2311 | { | |
2312 | operands[2] = bfin_compare_op0; | |
2313 | operands[3] = bfin_compare_op1; | |
2314 | operands[1] = bfin_cc_rtx; | |
2315 | }) | |
2316 | ||
2317 | (define_expand "slt" | |
2318 | [(set (match_dup 1) (lt:BI (match_dup 2) (match_dup 3))) | |
2319 | (set (match_operand:SI 0 "register_operand" "") | |
2320 | (ne:SI (match_dup 1) (const_int 0)))] | |
2321 | "" | |
2322 | { | |
2323 | operands[2] = bfin_compare_op0; | |
2324 | operands[3] = bfin_compare_op1; | |
2325 | operands[1] = bfin_cc_rtx; | |
2326 | }) | |
2327 | ||
2328 | (define_expand "sle" | |
2329 | [(set (match_dup 1) (le:BI (match_dup 2) (match_dup 3))) | |
2330 | (set (match_operand:SI 0 "register_operand" "") | |
2331 | (ne:SI (match_dup 1) (const_int 0)))] | |
2332 | "" | |
2333 | { | |
2334 | operands[2] = bfin_compare_op0; | |
2335 | operands[3] = bfin_compare_op1; | |
2336 | operands[1] = bfin_cc_rtx; | |
2337 | }) | |
2338 | ||
2339 | (define_expand "sltu" | |
2340 | [(set (match_dup 1) (ltu:BI (match_dup 2) (match_dup 3))) | |
2341 | (set (match_operand:SI 0 "register_operand" "") | |
2342 | (ne:SI (match_dup 1) (const_int 0)))] | |
2343 | "" | |
2344 | { | |
2345 | operands[2] = bfin_compare_op0; | |
2346 | operands[3] = bfin_compare_op1; | |
2347 | operands[1] = bfin_cc_rtx; | |
2348 | }) | |
2349 | ||
2350 | (define_expand "sleu" | |
2351 | [(set (match_dup 1) (leu:BI (match_dup 2) (match_dup 3))) | |
2352 | (set (match_operand:SI 0 "register_operand" "") | |
2353 | (ne:SI (match_dup 1) (const_int 0)))] | |
2354 | "" | |
2355 | { | |
2356 | operands[2] = bfin_compare_op0; | |
2357 | operands[3] = bfin_compare_op1; | |
2358 | operands[1] = bfin_cc_rtx; | |
2359 | }) | |
2360 | ||
2361 | (define_insn "nop" | |
2362 | [(const_int 0)] | |
2363 | "" | |
2364 | "nop;") | |
2365 | ||
bbbc206e BS |
2366 | (define_insn "mnop" |
2367 | [(unspec [(const_int 0)] UNSPEC_32BIT)] | |
2368 | "" | |
2369 | "mnop%!" | |
2370 | [(set_attr "type" "dsp32")]) | |
2371 | ||
0d4a78eb BS |
2372 | ;;;;;;;;;;;;;;;;;;;; CC2dreg ;;;;;;;;;;;;;;;;;;;;;;;;; |
2373 | (define_insn "movsibi" | |
4729dc92 | 2374 | [(set (match_operand:BI 0 "register_operand" "=C") |
0d4a78eb BS |
2375 | (ne:BI (match_operand:SI 1 "register_operand" "d") |
2376 | (const_int 0)))] | |
2377 | "" | |
2378 | "CC = %1;" | |
2379 | [(set_attr "length" "2")]) | |
2380 | ||
2381 | (define_insn "movbisi" | |
2382 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4729dc92 | 2383 | (ne:SI (match_operand:BI 1 "register_operand" "C") |
0d4a78eb BS |
2384 | (const_int 0)))] |
2385 | "" | |
2386 | "%0 = CC;" | |
2387 | [(set_attr "length" "2")]) | |
2388 | ||
2389 | (define_insn "" | |
4729dc92 BS |
2390 | [(set (match_operand:BI 0 "register_operand" "=C") |
2391 | (eq:BI (match_operand:BI 1 "register_operand" " 0") | |
0d4a78eb BS |
2392 | (const_int 0)))] |
2393 | "" | |
2394 | "%0 = ! %0;" /* NOT CC;" */ | |
2395 | [(set_attr "type" "compare")]) | |
2396 | ||
2397 | ;; Vector and DSP insns | |
2398 | ||
2399 | (define_insn "" | |
2400 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2401 | (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") | |
2402 | (const_int 24)) | |
2403 | (lshiftrt:SI (match_operand:SI 2 "register_operand" "d") | |
2404 | (const_int 8))))] | |
2405 | "" | |
bbbc206e | 2406 | "%0 = ALIGN8(%1, %2)%!" |
0d4a78eb BS |
2407 | [(set_attr "type" "dsp32")]) |
2408 | ||
2409 | (define_insn "" | |
2410 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2411 | (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") | |
2412 | (const_int 16)) | |
2413 | (lshiftrt:SI (match_operand:SI 2 "register_operand" "d") | |
2414 | (const_int 16))))] | |
2415 | "" | |
bbbc206e | 2416 | "%0 = ALIGN16(%1, %2)%!" |
0d4a78eb BS |
2417 | [(set_attr "type" "dsp32")]) |
2418 | ||
2419 | (define_insn "" | |
2420 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2421 | (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") | |
2422 | (const_int 8)) | |
2423 | (lshiftrt:SI (match_operand:SI 2 "register_operand" "d") | |
2424 | (const_int 24))))] | |
2425 | "" | |
bbbc206e | 2426 | "%0 = ALIGN24(%1, %2)%!" |
0d4a78eb BS |
2427 | [(set_attr "type" "dsp32")]) |
2428 | ||
2429 | ;; Prologue and epilogue. | |
2430 | ||
2431 | (define_expand "prologue" | |
2432 | [(const_int 1)] | |
2433 | "" | |
2434 | "bfin_expand_prologue (); DONE;") | |
2435 | ||
2436 | (define_expand "epilogue" | |
2437 | [(const_int 1)] | |
2438 | "" | |
2439 | "bfin_expand_epilogue (1, 0); DONE;") | |
2440 | ||
2441 | (define_expand "sibcall_epilogue" | |
2442 | [(const_int 1)] | |
2443 | "" | |
2444 | "bfin_expand_epilogue (0, 0); DONE;") | |
2445 | ||
2446 | (define_expand "eh_return" | |
2447 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "")] | |
2448 | UNSPEC_VOLATILE_EH_RETURN)] | |
2449 | "" | |
2450 | { | |
2451 | emit_move_insn (EH_RETURN_HANDLER_RTX, operands[0]); | |
1e96b1c3 | 2452 | emit_jump_insn (gen_eh_return_internal ()); |
0d4a78eb | 2453 | emit_barrier (); |
4193ce73 | 2454 | DONE; |
0d4a78eb BS |
2455 | }) |
2456 | ||
2457 | (define_insn_and_split "eh_return_internal" | |
1e96b1c3 JZ |
2458 | [(set (pc) |
2459 | (unspec_volatile [(reg:SI REG_P2)] UNSPEC_VOLATILE_EH_RETURN))] | |
0d4a78eb BS |
2460 | "" |
2461 | "#" | |
2462 | "reload_completed" | |
2463 | [(const_int 1)] | |
2464 | "bfin_expand_epilogue (1, 1); DONE;") | |
2465 | ||
2466 | (define_insn "link" | |
2467 | [(set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -4))) (reg:SI REG_RETS)) | |
2468 | (set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -8))) (reg:SI REG_FP)) | |
2469 | (set (reg:SI REG_FP) | |
2470 | (plus:SI (reg:SI REG_SP) (const_int -8))) | |
2471 | (set (reg:SI REG_SP) | |
2472 | (plus:SI (reg:SI REG_SP) (match_operand:SI 0 "immediate_operand" "i")))] | |
2473 | "" | |
2474 | "LINK %Z0;" | |
2475 | [(set_attr "length" "4")]) | |
2476 | ||
2477 | (define_insn "unlink" | |
2478 | [(set (reg:SI REG_FP) (mem:SI (reg:SI REG_FP))) | |
2479 | (set (reg:SI REG_RETS) (mem:SI (plus:SI (reg:SI REG_FP) (const_int 4)))) | |
2480 | (set (reg:SI REG_SP) (plus:SI (reg:SI REG_FP) (const_int 8)))] | |
2481 | "" | |
2482 | "UNLINK;" | |
2483 | [(set_attr "length" "4")]) | |
2484 | ||
2485 | ;; This pattern is slightly clumsy. The stack adjust must be the final SET in | |
2486 | ;; the pattern, otherwise dwarf2out becomes very confused about which reg goes | |
2487 | ;; where on the stack, since it goes through all elements of the parallel in | |
2488 | ;; sequence. | |
2489 | (define_insn "push_multiple" | |
2490 | [(match_parallel 0 "push_multiple_operation" | |
2491 | [(unspec [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_PUSH_MULTIPLE)])] | |
2492 | "" | |
2493 | { | |
2494 | output_push_multiple (insn, operands); | |
2495 | return ""; | |
2496 | }) | |
2497 | ||
2498 | (define_insn "pop_multiple" | |
2499 | [(match_parallel 0 "pop_multiple_operation" | |
2500 | [(set (reg:SI REG_SP) | |
2501 | (plus:SI (reg:SI REG_SP) (match_operand:SI 1 "immediate_operand" "i")))])] | |
2502 | "" | |
2503 | { | |
2504 | output_pop_multiple (insn, operands); | |
2505 | return ""; | |
2506 | }) | |
2507 | ||
2508 | (define_insn "return_internal" | |
2509 | [(return) | |
2510 | (unspec [(match_operand 0 "immediate_operand" "i")] UNSPEC_RETURN)] | |
2511 | "reload_completed" | |
2512 | { | |
2513 | switch (INTVAL (operands[0])) | |
2514 | { | |
2515 | case EXCPT_HANDLER: | |
2516 | return "rtx;"; | |
2517 | case NMI_HANDLER: | |
2518 | return "rtn;"; | |
2519 | case INTERRUPT_HANDLER: | |
2520 | return "rti;"; | |
2521 | case SUBROUTINE: | |
2522 | return "rts;"; | |
2523 | } | |
2524 | gcc_unreachable (); | |
2525 | }) | |
2526 | ||
5fcead21 BS |
2527 | (define_insn "csync" |
2528 | [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_CSYNC)] | |
2529 | "" | |
2530 | "csync;" | |
3fb192d2 | 2531 | [(set_attr "type" "sync")]) |
5fcead21 BS |
2532 | |
2533 | (define_insn "ssync" | |
2534 | [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_SSYNC)] | |
2535 | "" | |
2536 | "ssync;" | |
3fb192d2 | 2537 | [(set_attr "type" "sync")]) |
5fcead21 | 2538 | |
3d33a056 JZ |
2539 | (define_insn "trap" |
2540 | [(trap_if (const_int 1) (const_int 3))] | |
2541 | "" | |
2542 | "excpt 3;" | |
2543 | [(set_attr "type" "misc") | |
2544 | (set_attr "length" "2")]) | |
2545 | ||
09350e36 BS |
2546 | (define_insn "trapifcc" |
2547 | [(trap_if (reg:BI REG_CC) (const_int 3))] | |
2548 | "" | |
2549 | "if !cc jump 4 (bp); excpt 3;" | |
2550 | [(set_attr "type" "misc") | |
b03149e1 JZ |
2551 | (set_attr "length" "4") |
2552 | (set_attr "seq_insns" "multi")]) | |
09350e36 | 2553 | |
0d4a78eb BS |
2554 | ;;; Vector instructions |
2555 | ||
75d8b2d0 BS |
2556 | ;; First, all sorts of move variants |
2557 | ||
2558 | (define_insn "movhi_low2high" | |
2559 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2560 | (vec_concat:V2HI | |
2561 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
2562 | (parallel [(const_int 0)])) | |
2563 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2564 | (parallel [(const_int 0)]))))] | |
2565 | "" | |
bbbc206e | 2566 | "%d0 = %h2 << 0%!" |
75d8b2d0 BS |
2567 | [(set_attr "type" "dsp32")]) |
2568 | ||
2569 | (define_insn "movhi_high2high" | |
2570 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2571 | (vec_concat:V2HI | |
2572 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
2573 | (parallel [(const_int 0)])) | |
2574 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2575 | (parallel [(const_int 1)]))))] | |
2576 | "" | |
bbbc206e | 2577 | "%d0 = %d2 << 0%!" |
75d8b2d0 BS |
2578 | [(set_attr "type" "dsp32")]) |
2579 | ||
2580 | (define_insn "movhi_low2low" | |
2581 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2582 | (vec_concat:V2HI | |
2583 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2584 | (parallel [(const_int 0)])) | |
2585 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
2586 | (parallel [(const_int 1)]))))] | |
2587 | "" | |
bbbc206e | 2588 | "%h0 = %h2 << 0%!" |
75d8b2d0 BS |
2589 | [(set_attr "type" "dsp32")]) |
2590 | ||
2591 | (define_insn "movhi_high2low" | |
2592 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2593 | (vec_concat:V2HI | |
2594 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2595 | (parallel [(const_int 1)])) | |
2596 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
2597 | (parallel [(const_int 1)]))))] | |
2598 | "" | |
bbbc206e | 2599 | "%h0 = %d2 << 0%!" |
75d8b2d0 BS |
2600 | [(set_attr "type" "dsp32")]) |
2601 | ||
2602 | (define_insn "movhiv2hi_low" | |
2603 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2604 | (vec_concat:V2HI | |
2605 | (match_operand:HI 2 "register_operand" "d") | |
2606 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
2607 | (parallel [(const_int 1)]))))] | |
2608 | "" | |
bbbc206e | 2609 | "%h0 = %h2 << 0%!" |
75d8b2d0 BS |
2610 | [(set_attr "type" "dsp32")]) |
2611 | ||
2612 | (define_insn "movhiv2hi_high" | |
2613 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2614 | (vec_concat:V2HI | |
2615 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
2616 | (parallel [(const_int 0)])) | |
2617 | (match_operand:HI 2 "register_operand" "d")))] | |
2618 | "" | |
bbbc206e | 2619 | "%d0 = %h2 << 0%!" |
75d8b2d0 BS |
2620 | [(set_attr "type" "dsp32")]) |
2621 | ||
2622 | ;; No earlyclobber on alternative two since our sequence ought to be safe. | |
2623 | ;; The order of operands is intentional to match the VDSP builtin (high word | |
2624 | ;; is passed first). | |
2625 | (define_insn_and_split "composev2hi" | |
2626 | [(set (match_operand:V2HI 0 "register_operand" "=d,d") | |
2627 | (vec_concat:V2HI (match_operand:HI 2 "register_operand" "0,d") | |
2628 | (match_operand:HI 1 "register_operand" "d,d")))] | |
2629 | "" | |
2630 | "@ | |
bbbc206e | 2631 | %d0 = %h2 << 0%! |
75d8b2d0 BS |
2632 | #" |
2633 | "reload_completed" | |
2634 | [(set (match_dup 0) | |
2635 | (vec_concat:V2HI | |
2636 | (vec_select:HI (match_dup 0) (parallel [(const_int 0)])) | |
2637 | (match_dup 2))) | |
2638 | (set (match_dup 0) | |
2639 | (vec_concat:V2HI | |
2640 | (match_dup 1) | |
2641 | (vec_select:HI (match_dup 0) (parallel [(const_int 1)]))))] | |
2642 | "" | |
2643 | [(set_attr "type" "dsp32")]) | |
2644 | ||
2645 | ; Like composev2hi, but operating on elements of V2HI vectors. | |
2646 | ; Useful on its own, and as a combiner bridge for the multiply and | |
2647 | ; mac patterns. | |
2648 | (define_insn "packv2hi" | |
2649 | [(set (match_operand:V2HI 0 "register_operand" "=d,d,d,d") | |
2650 | (vec_concat:V2HI (vec_select:HI | |
2651 | (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
2652 | (parallel [(match_operand 3 "const01_operand" "P0,P1,P0,P1")])) | |
2653 | (vec_select:HI | |
2654 | (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
2655 | (parallel [(match_operand 4 "const01_operand" "P0,P0,P1,P1")]))))] | |
2656 | "" | |
2657 | "@ | |
bbbc206e BS |
2658 | %0 = PACK (%h2,%h1)%! |
2659 | %0 = PACK (%h2,%d1)%! | |
2660 | %0 = PACK (%d2,%h1)%! | |
2661 | %0 = PACK (%d2,%d1)%!" | |
75d8b2d0 BS |
2662 | [(set_attr "type" "dsp32")]) |
2663 | ||
2664 | (define_insn "movv2hi_hi" | |
2665 | [(set (match_operand:HI 0 "register_operand" "=d,d,d") | |
2666 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0,d,d") | |
554006bd | 2667 | (parallel [(match_operand 2 "const01_operand" "P0,P0,P1")])))] |
75d8b2d0 BS |
2668 | "" |
2669 | "@ | |
2670 | /* optimized out */ | |
bbbc206e BS |
2671 | %h0 = %h1 << 0%! |
2672 | %h0 = %d1 << 0%!" | |
75d8b2d0 BS |
2673 | [(set_attr "type" "dsp32")]) |
2674 | ||
2675 | (define_expand "movv2hi_hi_low" | |
2676 | [(set (match_operand:HI 0 "register_operand" "") | |
2677 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "") | |
2678 | (parallel [(const_int 0)])))] | |
2679 | "" | |
2680 | "") | |
2681 | ||
2682 | (define_expand "movv2hi_hi_high" | |
2683 | [(set (match_operand:HI 0 "register_operand" "") | |
2684 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "") | |
2685 | (parallel [(const_int 1)])))] | |
2686 | "" | |
2687 | "") | |
2688 | ||
942fd98f | 2689 | ;; Unusual arithmetic operations on 16-bit registers. |
75d8b2d0 BS |
2690 | |
2691 | (define_insn "ssaddhi3" | |
2692 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2693 | (ss_plus:HI (match_operand:HI 1 "register_operand" "d") | |
2694 | (match_operand:HI 2 "register_operand" "d")))] | |
2695 | "" | |
bbbc206e | 2696 | "%h0 = %h1 + %h2 (S)%!" |
75d8b2d0 BS |
2697 | [(set_attr "type" "dsp32")]) |
2698 | ||
2699 | (define_insn "sssubhi3" | |
2700 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2701 | (ss_minus:HI (match_operand:HI 1 "register_operand" "d") | |
2702 | (match_operand:HI 2 "register_operand" "d")))] | |
2703 | "" | |
bbbc206e | 2704 | "%h0 = %h1 - %h2 (S)%!" |
75d8b2d0 BS |
2705 | [(set_attr "type" "dsp32")]) |
2706 | ||
2707 | ;; V2HI vector insns | |
2708 | ||
c9b3f817 | 2709 | (define_insn "addv2hi3" |
0d4a78eb BS |
2710 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
2711 | (plus:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
2712 | (match_operand:V2HI 2 "register_operand" "d")))] | |
2713 | "" | |
bbbc206e | 2714 | "%0 = %1 +|+ %2%!" |
0d4a78eb BS |
2715 | [(set_attr "type" "dsp32")]) |
2716 | ||
75d8b2d0 BS |
2717 | (define_insn "ssaddv2hi3" |
2718 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2719 | (ss_plus:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
2720 | (match_operand:V2HI 2 "register_operand" "d")))] | |
2721 | "" | |
bbbc206e | 2722 | "%0 = %1 +|+ %2 (S)%!" |
75d8b2d0 BS |
2723 | [(set_attr "type" "dsp32")]) |
2724 | ||
c9b3f817 | 2725 | (define_insn "subv2hi3" |
0d4a78eb BS |
2726 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
2727 | (minus:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
2728 | (match_operand:V2HI 2 "register_operand" "d")))] | |
2729 | "" | |
bbbc206e | 2730 | "%0 = %1 -|- %2%!" |
0d4a78eb BS |
2731 | [(set_attr "type" "dsp32")]) |
2732 | ||
75d8b2d0 BS |
2733 | (define_insn "sssubv2hi3" |
2734 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2735 | (ss_minus:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
2736 | (match_operand:V2HI 2 "register_operand" "d")))] | |
2737 | "" | |
bbbc206e | 2738 | "%0 = %1 -|- %2 (S)%!" |
75d8b2d0 BS |
2739 | [(set_attr "type" "dsp32")]) |
2740 | ||
2741 | (define_insn "addsubv2hi3" | |
2742 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2743 | (vec_concat:V2HI | |
2744 | (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2745 | (parallel [(const_int 0)])) | |
2746 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2747 | (parallel [(const_int 0)]))) | |
2748 | (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])) | |
2749 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
2750 | "" | |
bbbc206e | 2751 | "%0 = %1 +|- %2%!" |
75d8b2d0 BS |
2752 | [(set_attr "type" "dsp32")]) |
2753 | ||
2754 | (define_insn "subaddv2hi3" | |
2755 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2756 | (vec_concat:V2HI | |
2757 | (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2758 | (parallel [(const_int 0)])) | |
2759 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2760 | (parallel [(const_int 0)]))) | |
2761 | (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])) | |
2762 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
2763 | "" | |
bbbc206e | 2764 | "%0 = %1 -|+ %2%!" |
75d8b2d0 BS |
2765 | [(set_attr "type" "dsp32")]) |
2766 | ||
2767 | (define_insn "ssaddsubv2hi3" | |
2768 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2769 | (vec_concat:V2HI | |
2770 | (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2771 | (parallel [(const_int 0)])) | |
2772 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2773 | (parallel [(const_int 0)]))) | |
2774 | (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])) | |
2775 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
2776 | "" | |
bbbc206e | 2777 | "%0 = %1 +|- %2 (S)%!" |
75d8b2d0 BS |
2778 | [(set_attr "type" "dsp32")]) |
2779 | ||
2780 | (define_insn "sssubaddv2hi3" | |
2781 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2782 | (vec_concat:V2HI | |
2783 | (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2784 | (parallel [(const_int 0)])) | |
2785 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2786 | (parallel [(const_int 0)]))) | |
2787 | (ss_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])) | |
2788 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
2789 | "" | |
bbbc206e | 2790 | "%0 = %1 -|+ %2 (S)%!" |
75d8b2d0 BS |
2791 | [(set_attr "type" "dsp32")]) |
2792 | ||
2793 | (define_insn "sublohiv2hi3" | |
2794 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2795 | (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2796 | (parallel [(const_int 1)])) | |
2797 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2798 | (parallel [(const_int 0)]))))] | |
2799 | "" | |
bbbc206e | 2800 | "%h0 = %d1 - %h2%!" |
75d8b2d0 BS |
2801 | [(set_attr "type" "dsp32")]) |
2802 | ||
2803 | (define_insn "subhilov2hi3" | |
2804 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2805 | (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2806 | (parallel [(const_int 0)])) | |
2807 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2808 | (parallel [(const_int 1)]))))] | |
2809 | "" | |
bbbc206e | 2810 | "%h0 = %h1 - %d2%!" |
75d8b2d0 BS |
2811 | [(set_attr "type" "dsp32")]) |
2812 | ||
2813 | (define_insn "sssublohiv2hi3" | |
2814 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2815 | (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2816 | (parallel [(const_int 1)])) | |
2817 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2818 | (parallel [(const_int 0)]))))] | |
2819 | "" | |
bbbc206e | 2820 | "%h0 = %d1 - %h2 (S)%!" |
75d8b2d0 BS |
2821 | [(set_attr "type" "dsp32")]) |
2822 | ||
2823 | (define_insn "sssubhilov2hi3" | |
2824 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2825 | (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2826 | (parallel [(const_int 0)])) | |
2827 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2828 | (parallel [(const_int 1)]))))] | |
2829 | "" | |
bbbc206e | 2830 | "%h0 = %h1 - %d2 (S)%!" |
75d8b2d0 BS |
2831 | [(set_attr "type" "dsp32")]) |
2832 | ||
2833 | (define_insn "addlohiv2hi3" | |
2834 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2835 | (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2836 | (parallel [(const_int 1)])) | |
2837 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2838 | (parallel [(const_int 0)]))))] | |
2839 | "" | |
bbbc206e | 2840 | "%h0 = %d1 + %h2%!" |
75d8b2d0 BS |
2841 | [(set_attr "type" "dsp32")]) |
2842 | ||
2843 | (define_insn "addhilov2hi3" | |
2844 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2845 | (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2846 | (parallel [(const_int 0)])) | |
2847 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2848 | (parallel [(const_int 1)]))))] | |
2849 | "" | |
bbbc206e | 2850 | "%h0 = %h1 + %d2%!" |
75d8b2d0 BS |
2851 | [(set_attr "type" "dsp32")]) |
2852 | ||
2853 | (define_insn "ssaddlohiv2hi3" | |
2854 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2855 | (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2856 | (parallel [(const_int 1)])) | |
2857 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2858 | (parallel [(const_int 0)]))))] | |
2859 | "" | |
bbbc206e | 2860 | "%h0 = %d1 + %h2 (S)%!" |
75d8b2d0 BS |
2861 | [(set_attr "type" "dsp32")]) |
2862 | ||
2863 | (define_insn "ssaddhilov2hi3" | |
2864 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2865 | (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2866 | (parallel [(const_int 0)])) | |
2867 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2868 | (parallel [(const_int 1)]))))] | |
2869 | "" | |
bbbc206e | 2870 | "%h0 = %h1 + %d2 (S)%!" |
75d8b2d0 BS |
2871 | [(set_attr "type" "dsp32")]) |
2872 | ||
c9b3f817 | 2873 | (define_insn "sminv2hi3" |
0d4a78eb BS |
2874 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
2875 | (smin:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
2876 | (match_operand:V2HI 2 "register_operand" "d")))] | |
2877 | "" | |
bbbc206e | 2878 | "%0 = MIN (%1, %2) (V)%!" |
0d4a78eb BS |
2879 | [(set_attr "type" "dsp32")]) |
2880 | ||
c9b3f817 | 2881 | (define_insn "smaxv2hi3" |
0d4a78eb BS |
2882 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
2883 | (smax:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
2884 | (match_operand:V2HI 2 "register_operand" "d")))] | |
2885 | "" | |
bbbc206e | 2886 | "%0 = MAX (%1, %2) (V)%!" |
0d4a78eb BS |
2887 | [(set_attr "type" "dsp32")]) |
2888 | ||
75d8b2d0 BS |
2889 | ;; Multiplications. |
2890 | ||
2891 | ;; The Blackfin allows a lot of different options, and we need many patterns to | |
2892 | ;; cover most of the hardware's abilities. | |
2893 | ;; There are a few simple patterns using MULT rtx codes, but most of them use | |
2894 | ;; an unspec with a const_int operand that determines which flag to use in the | |
2895 | ;; instruction. | |
2896 | ;; There are variants for single and parallel multiplications. | |
942fd98f | 2897 | ;; There are variants which just use 16-bit lowparts as inputs, and variants |
75d8b2d0 BS |
2898 | ;; which allow the user to choose just which halves to use as input values. |
2899 | ;; There are variants which set D registers, variants which set accumulators, | |
2900 | ;; variants which set both, some of them optionally using the accumulators as | |
2901 | ;; inputs for multiply-accumulate operations. | |
2902 | ||
2903 | (define_insn "flag_mulhi" | |
2904 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2905 | (unspec:HI [(match_operand:HI 1 "register_operand" "d") | |
2906 | (match_operand:HI 2 "register_operand" "d") | |
2907 | (match_operand 3 "const_int_operand" "n")] | |
2908 | UNSPEC_MUL_WITH_FLAG))] | |
2909 | "" | |
bbbc206e | 2910 | "%h0 = %h1 * %h2 %M3%!" |
75d8b2d0 BS |
2911 | [(set_attr "type" "dsp32")]) |
2912 | ||
2913 | (define_insn "flag_mulhisi" | |
2914 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2915 | (unspec:SI [(match_operand:HI 1 "register_operand" "d") | |
2916 | (match_operand:HI 2 "register_operand" "d") | |
2917 | (match_operand 3 "const_int_operand" "n")] | |
2918 | UNSPEC_MUL_WITH_FLAG))] | |
2919 | "" | |
bbbc206e | 2920 | "%0 = %h1 * %h2 %M3%!" |
75d8b2d0 BS |
2921 | [(set_attr "type" "dsp32")]) |
2922 | ||
2923 | (define_insn "flag_mulhisi_parts" | |
2924 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2925 | (unspec:SI [(vec_select:HI | |
2926 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 2927 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
2928 | (vec_select:HI |
2929 | (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 2930 | (parallel [(match_operand 4 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
2931 | (match_operand 5 "const_int_operand" "n")] |
2932 | UNSPEC_MUL_WITH_FLAG))] | |
2933 | "" | |
2934 | { | |
2935 | const char *templates[] = { | |
bbbc206e BS |
2936 | "%0 = %h1 * %h2 %M5%!", |
2937 | "%0 = %d1 * %h2 %M5%!", | |
2938 | "%0 = %h1 * %d2 %M5%!", | |
2939 | "%0 = %d1 * %d2 %M5%!" }; | |
75d8b2d0 BS |
2940 | int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1); |
2941 | return templates[alt]; | |
2942 | } | |
2943 | [(set_attr "type" "dsp32")]) | |
2944 | ||
2945 | (define_insn "flag_machi" | |
2946 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2947 | (unspec:HI [(match_operand:HI 1 "register_operand" "d") | |
2948 | (match_operand:HI 2 "register_operand" "d") | |
2949 | (match_operand 3 "register_operand" "A") | |
2950 | (match_operand 4 "const01_operand" "P0P1") | |
2951 | (match_operand 5 "const_int_operand" "n")] | |
2952 | UNSPEC_MAC_WITH_FLAG)) | |
2953 | (set (match_operand:PDI 6 "register_operand" "=A") | |
2954 | (unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3) | |
2955 | (match_dup 4) (match_dup 5)] | |
2956 | UNSPEC_MAC_WITH_FLAG))] | |
2957 | "" | |
bbbc206e | 2958 | "%h0 = (A0 %b4 %h1 * %h2) %M6%!" |
75d8b2d0 BS |
2959 | [(set_attr "type" "dsp32")]) |
2960 | ||
2961 | (define_insn "flag_machi_acconly" | |
2962 | [(set (match_operand:PDI 0 "register_operand" "=e") | |
2963 | (unspec:PDI [(match_operand:HI 1 "register_operand" "d") | |
2964 | (match_operand:HI 2 "register_operand" "d") | |
2965 | (match_operand 3 "register_operand" "A") | |
2966 | (match_operand 4 "const01_operand" "P0P1") | |
2967 | (match_operand 5 "const_int_operand" "n")] | |
2968 | UNSPEC_MAC_WITH_FLAG))] | |
2969 | "" | |
bbbc206e | 2970 | "%0 %b4 %h1 * %h2 %M6%!" |
75d8b2d0 BS |
2971 | [(set_attr "type" "dsp32")]) |
2972 | ||
2973 | (define_insn "flag_macinithi" | |
2974 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2975 | (unspec:HI [(match_operand:HI 1 "register_operand" "d") | |
2976 | (match_operand:HI 2 "register_operand" "d") | |
2977 | (match_operand 3 "const_int_operand" "n")] | |
2978 | UNSPEC_MAC_WITH_FLAG)) | |
2979 | (set (match_operand:PDI 4 "register_operand" "=A") | |
2980 | (unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3)] | |
2981 | UNSPEC_MAC_WITH_FLAG))] | |
2982 | "" | |
bbbc206e | 2983 | "%h0 = (A0 = %h1 * %h2) %M3%!" |
75d8b2d0 BS |
2984 | [(set_attr "type" "dsp32")]) |
2985 | ||
2986 | (define_insn "flag_macinit1hi" | |
2987 | [(set (match_operand:PDI 0 "register_operand" "=e") | |
2988 | (unspec:PDI [(match_operand:HI 1 "register_operand" "d") | |
2989 | (match_operand:HI 2 "register_operand" "d") | |
2990 | (match_operand 3 "const_int_operand" "n")] | |
2991 | UNSPEC_MAC_WITH_FLAG))] | |
2992 | "" | |
bbbc206e | 2993 | "%0 = %h1 * %h2 %M3%!" |
75d8b2d0 BS |
2994 | [(set_attr "type" "dsp32")]) |
2995 | ||
c9b3f817 | 2996 | (define_insn "mulv2hi3" |
0d4a78eb BS |
2997 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
2998 | (mult:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
2999 | (match_operand:V2HI 2 "register_operand" "d")))] | |
3000 | "" | |
bbbc206e | 3001 | "%h0 = %h1 * %h2, %d0 = %d1 * %d2 (IS)%!" |
0d4a78eb BS |
3002 | [(set_attr "type" "dsp32")]) |
3003 | ||
75d8b2d0 BS |
3004 | (define_insn "flag_mulv2hi" |
3005 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3006 | (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d") | |
3007 | (match_operand:V2HI 2 "register_operand" "d") | |
3008 | (match_operand 3 "const_int_operand" "n")] | |
3009 | UNSPEC_MUL_WITH_FLAG))] | |
3010 | "" | |
bbbc206e | 3011 | "%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M3%!" |
75d8b2d0 BS |
3012 | [(set_attr "type" "dsp32")]) |
3013 | ||
3014 | (define_insn "flag_mulv2hi_parts" | |
3015 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3016 | (unspec:V2HI [(vec_concat:V2HI | |
3017 | (vec_select:HI | |
3018 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3019 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3020 | (vec_select:HI |
3021 | (match_dup 1) | |
554006bd | 3022 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3023 | (vec_concat:V2HI |
3024 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3025 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3026 | (vec_select:HI (match_dup 2) |
554006bd | 3027 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3028 | (match_operand 7 "const_int_operand" "n")] |
3029 | UNSPEC_MUL_WITH_FLAG))] | |
3030 | "" | |
3031 | { | |
3032 | const char *templates[] = { | |
bbbc206e BS |
3033 | "%h0 = %h1 * %h2, %d0 = %h1 * %h2 %M7%!", |
3034 | "%h0 = %d1 * %h2, %d0 = %h1 * %h2 %M7%!", | |
3035 | "%h0 = %h1 * %h2, %d0 = %d1 * %h2 %M7%!", | |
3036 | "%h0 = %d1 * %h2, %d0 = %d1 * %h2 %M7%!", | |
3037 | "%h0 = %h1 * %d2, %d0 = %h1 * %h2 %M7%!", | |
3038 | "%h0 = %d1 * %d2, %d0 = %h1 * %h2 %M7%!", | |
3039 | "%h0 = %h1 * %d2, %d0 = %d1 * %h2 %M7%!", | |
3040 | "%h0 = %d1 * %d2, %d0 = %d1 * %h2 %M7%!", | |
3041 | "%h0 = %h1 * %h2, %d0 = %h1 * %d2 %M7%!", | |
3042 | "%h0 = %d1 * %h2, %d0 = %h1 * %d2 %M7%!", | |
3043 | "%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M7%!", | |
3044 | "%h0 = %d1 * %h2, %d0 = %d1 * %d2 %M7%!", | |
3045 | "%h0 = %h1 * %d2, %d0 = %h1 * %d2 %M7%!", | |
3046 | "%h0 = %d1 * %d2, %d0 = %h1 * %d2 %M7%!", | |
3047 | "%h0 = %h1 * %d2, %d0 = %d1 * %d2 %M7%!", | |
3048 | "%h0 = %d1 * %d2, %d0 = %d1 * %d2 %M7%!" }; | |
75d8b2d0 BS |
3049 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3050 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3051 | return templates[alt]; | |
3052 | } | |
3053 | [(set_attr "type" "dsp32")]) | |
3054 | ||
3055 | ;; A slightly complicated pattern. | |
3056 | ;; Operand 0 is the halfword output; operand 11 is the accumulator output | |
3057 | ;; Halfword inputs are operands 1 and 2; operands 3, 4, 5 and 6 specify which | |
3058 | ;; parts of these 2x16 bit registers to use. | |
3059 | ;; Operand 7 is the accumulator input. | |
3060 | ;; Operands 8/9 specify whether low/high parts are mac (0) or msu (1) | |
3061 | ;; Operand 10 is the macflag to be used. | |
3062 | (define_insn "flag_macv2hi_parts" | |
3063 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3064 | (unspec:V2HI [(vec_concat:V2HI | |
3065 | (vec_select:HI | |
3066 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3067 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3068 | (vec_select:HI |
3069 | (match_dup 1) | |
554006bd | 3070 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3071 | (vec_concat:V2HI |
3072 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3073 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3074 | (vec_select:HI (match_dup 2) |
554006bd | 3075 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3076 | (match_operand:V2PDI 7 "register_operand" "e") |
3077 | (match_operand 8 "const01_operand" "P0P1") | |
3078 | (match_operand 9 "const01_operand" "P0P1") | |
3079 | (match_operand 10 "const_int_operand" "n")] | |
3080 | UNSPEC_MAC_WITH_FLAG)) | |
3081 | (set (match_operand:V2PDI 11 "register_operand" "=e") | |
3082 | (unspec:V2PDI [(vec_concat:V2HI | |
3083 | (vec_select:HI (match_dup 1) (parallel [(match_dup 3)])) | |
3084 | (vec_select:HI (match_dup 1) (parallel [(match_dup 4)]))) | |
3085 | (vec_concat:V2HI | |
3086 | (vec_select:HI (match_dup 2) (parallel [(match_dup 5)])) | |
3087 | (vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))) | |
3088 | (match_dup 7) (match_dup 8) (match_dup 9) (match_dup 10)] | |
3089 | UNSPEC_MAC_WITH_FLAG))] | |
3090 | "" | |
3091 | { | |
3092 | const char *templates[] = { | |
bbbc206e BS |
3093 | "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10%!", |
3094 | "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10%!", | |
3095 | "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10%!", | |
3096 | "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10%!", | |
3097 | "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10%!", | |
3098 | "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10%!", | |
3099 | "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10%!", | |
3100 | "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10%!", | |
3101 | "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10%!", | |
3102 | "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10%!", | |
3103 | "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10%!", | |
3104 | "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10%!", | |
3105 | "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10%!", | |
3106 | "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10%!", | |
3107 | "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10%!", | |
3108 | "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10%!" }; | |
75d8b2d0 BS |
3109 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3110 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3111 | return templates[alt]; | |
3112 | } | |
3113 | [(set_attr "type" "dsp32")]) | |
3114 | ||
3115 | (define_insn "flag_macv2hi_parts_acconly" | |
3116 | [(set (match_operand:V2PDI 0 "register_operand" "=e") | |
3117 | (unspec:V2PDI [(vec_concat:V2HI | |
3118 | (vec_select:HI | |
3119 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3120 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3121 | (vec_select:HI |
3122 | (match_dup 1) | |
554006bd | 3123 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3124 | (vec_concat:V2HI |
3125 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3126 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3127 | (vec_select:HI (match_dup 2) |
554006bd | 3128 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3129 | (match_operand:V2PDI 7 "register_operand" "e") |
3130 | (match_operand 8 "const01_operand" "P0P1") | |
3131 | (match_operand 9 "const01_operand" "P0P1") | |
3132 | (match_operand 10 "const_int_operand" "n")] | |
3133 | UNSPEC_MAC_WITH_FLAG))] | |
3134 | "" | |
3135 | { | |
3136 | const char *templates[] = { | |
bbbc206e BS |
3137 | "A0 %b8 %h1 * %h2, A1 %b9 %h1 * %h2 %M10%!", |
3138 | "A0 %b8 %d1 * %h2, A1 %b9 %h1 * %h2 %M10%!", | |
3139 | "A0 %b8 %h1 * %h2, A1 %b9 %d1 * %h2 %M10%!", | |
3140 | "A0 %b8 %d1 * %h2, A1 %b9 %d1 * %h2 %M10%!", | |
3141 | "A0 %b8 %h1 * %d2, A1 %b9 %h1 * %h2 %M10%!", | |
3142 | "A0 %b8 %d1 * %d2, A1 %b9 %h1 * %h2 %M10%!", | |
3143 | "A0 %b8 %h1 * %d2, A1 %b9 %d1 * %h2 %M10%!", | |
3144 | "A0 %b8 %d1 * %d2, A1 %b9 %d1 * %h2 %M10%!", | |
3145 | "A0 %b8 %h1 * %h2, A1 %b9 %h1 * %d2 %M10%!", | |
3146 | "A0 %b8 %d1 * %h2, A1 %b9 %h1 * %d2 %M10%!", | |
3147 | "A0 %b8 %h1 * %h2, A1 %b9 %d1 * %d2 %M10%!", | |
3148 | "A0 %b8 %d1 * %h2, A1 %b9 %d1 * %d2 %M10%!", | |
3149 | "A0 %b8 %h1 * %d2, A1 %b9 %h1 * %d2 %M10%!", | |
3150 | "A0 %b8 %d1 * %d2, A1 %b9 %h1 * %d2 %M10%!", | |
3151 | "A0 %b8 %h1 * %d2, A1 %b9 %d1 * %d2 %M10%!", | |
3152 | "A0 %b8 %d1 * %d2, A1 %b9 %d1 * %d2 %M10%!" }; | |
75d8b2d0 BS |
3153 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3154 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3155 | return templates[alt]; | |
3156 | } | |
3157 | [(set_attr "type" "dsp32")]) | |
3158 | ||
3159 | ;; Same as above, but initializing the accumulators and therefore a couple fewer | |
3160 | ;; necessary operands. | |
3161 | (define_insn "flag_macinitv2hi_parts" | |
0d4a78eb | 3162 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
75d8b2d0 BS |
3163 | (unspec:V2HI [(vec_concat:V2HI |
3164 | (vec_select:HI | |
3165 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3166 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3167 | (vec_select:HI |
3168 | (match_dup 1) | |
554006bd | 3169 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3170 | (vec_concat:V2HI |
3171 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3172 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3173 | (vec_select:HI (match_dup 2) |
554006bd | 3174 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3175 | (match_operand 7 "const_int_operand" "n")] |
3176 | UNSPEC_MAC_WITH_FLAG)) | |
3177 | (set (match_operand:V2PDI 8 "register_operand" "=e") | |
3178 | (unspec:V2PDI [(vec_concat:V2HI | |
3179 | (vec_select:HI (match_dup 1) (parallel [(match_dup 3)])) | |
3180 | (vec_select:HI (match_dup 1) (parallel [(match_dup 4)]))) | |
3181 | (vec_concat:V2HI | |
3182 | (vec_select:HI (match_dup 2) (parallel [(match_dup 5)])) | |
3183 | (vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))) | |
3184 | (match_dup 7)] | |
3185 | UNSPEC_MAC_WITH_FLAG))] | |
3186 | "" | |
3187 | { | |
3188 | const char *templates[] = { | |
bbbc206e BS |
3189 | "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %h2) %M7%!", |
3190 | "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %h2) %M7%!", | |
3191 | "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %h2) %M7%!", | |
3192 | "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %h2) %M7%!", | |
3193 | "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %h2) %M7%!", | |
3194 | "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %h2) %M7%!", | |
3195 | "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %h2) %M7%!", | |
3196 | "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %h2) %M7%!", | |
3197 | "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %d2) %M7%!", | |
3198 | "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %d2) %M7%!", | |
3199 | "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %d2) %M7%!", | |
3200 | "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %d2) %M7%!", | |
3201 | "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %d2) %M7%!", | |
3202 | "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %d2) %M7%!", | |
3203 | "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %d2) %M7%!", | |
3204 | "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %d2) %M7%!" }; | |
75d8b2d0 BS |
3205 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3206 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3207 | return templates[alt]; | |
3208 | } | |
3209 | [(set_attr "type" "dsp32")]) | |
3210 | ||
3211 | (define_insn "flag_macinit1v2hi_parts" | |
3212 | [(set (match_operand:V2PDI 0 "register_operand" "=e") | |
3213 | (unspec:V2PDI [(vec_concat:V2HI | |
3214 | (vec_select:HI | |
3215 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3216 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3217 | (vec_select:HI |
3218 | (match_dup 1) | |
554006bd | 3219 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3220 | (vec_concat:V2HI |
3221 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3222 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3223 | (vec_select:HI (match_dup 2) |
554006bd | 3224 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3225 | (match_operand 7 "const_int_operand" "n")] |
3226 | UNSPEC_MAC_WITH_FLAG))] | |
3227 | "" | |
3228 | { | |
3229 | const char *templates[] = { | |
bbbc206e BS |
3230 | "A0 = %h1 * %h2, A1 = %h1 * %h2 %M7%!", |
3231 | "A0 = %d1 * %h2, A1 = %h1 * %h2 %M7%!", | |
3232 | "A0 = %h1 * %h2, A1 = %d1 * %h2 %M7%!", | |
3233 | "A0 = %d1 * %h2, A1 = %d1 * %h2 %M7%!", | |
3234 | "A0 = %h1 * %d2, A1 = %h1 * %h2 %M7%!", | |
3235 | "A0 = %d1 * %d2, A1 = %h1 * %h2 %M7%!", | |
3236 | "A0 = %h1 * %d2, A1 = %d1 * %h2 %M7%!", | |
3237 | "A0 = %d1 * %d2, A1 = %d1 * %h2 %M7%!", | |
3238 | "A0 = %h1 * %h2, A1 = %h1 * %d2 %M7%!", | |
3239 | "A0 = %d1 * %h2, A1 = %h1 * %d2 %M7%!", | |
3240 | "A0 = %h1 * %h2, A1 = %d1 * %d2 %M7%!", | |
3241 | "A0 = %d1 * %h2, A1 = %d1 * %d2 %M7%!", | |
3242 | "A0 = %h1 * %d2, A1 = %h1 * %d2 %M7%!", | |
3243 | "A0 = %d1 * %d2, A1 = %h1 * %d2 %M7%!", | |
3244 | "A0 = %h1 * %d2, A1 = %d1 * %d2 %M7%!", | |
3245 | "A0 = %d1 * %d2, A1 = %d1 * %d2 %M7%!" }; | |
75d8b2d0 BS |
3246 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3247 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3248 | return templates[alt]; | |
3249 | } | |
3250 | [(set_attr "type" "dsp32")]) | |
3251 | ||
3252 | (define_insn "mulhisi_ll" | |
3253 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3254 | (mult:SI (sign_extend:SI | |
3255 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d") | |
3256 | (parallel [(const_int 0)]))) | |
3257 | (sign_extend:SI | |
3258 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3259 | (parallel [(const_int 0)])))))] | |
3260 | "" | |
bbbc206e | 3261 | "%0 = %h1 * %h2 (IS)%!" |
75d8b2d0 BS |
3262 | [(set_attr "type" "dsp32")]) |
3263 | ||
3264 | (define_insn "mulhisi_lh" | |
3265 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3266 | (mult:SI (sign_extend:SI | |
3267 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d") | |
3268 | (parallel [(const_int 0)]))) | |
3269 | (sign_extend:SI | |
3270 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3271 | (parallel [(const_int 1)])))))] | |
3272 | "" | |
bbbc206e | 3273 | "%0 = %h1 * %d2 (IS)%!" |
75d8b2d0 BS |
3274 | [(set_attr "type" "dsp32")]) |
3275 | ||
3276 | (define_insn "mulhisi_hl" | |
3277 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3278 | (mult:SI (sign_extend:SI | |
3279 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d") | |
3280 | (parallel [(const_int 1)]))) | |
3281 | (sign_extend:SI | |
3282 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3283 | (parallel [(const_int 0)])))))] | |
3284 | "" | |
bbbc206e | 3285 | "%0 = %d1 * %h2 (IS)%!" |
75d8b2d0 BS |
3286 | [(set_attr "type" "dsp32")]) |
3287 | ||
3288 | (define_insn "mulhisi_hh" | |
3289 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3290 | (mult:SI (sign_extend:SI | |
3291 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d") | |
3292 | (parallel [(const_int 1)]))) | |
3293 | (sign_extend:SI | |
3294 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3295 | (parallel [(const_int 1)])))))] | |
3296 | "" | |
bbbc206e | 3297 | "%0 = %d1 * %d2 (IS)%!" |
75d8b2d0 BS |
3298 | [(set_attr "type" "dsp32")]) |
3299 | ||
3300 | (define_insn "ssnegv2hi2" | |
3301 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3302 | (ss_neg:V2HI (match_operand:V2HI 1 "register_operand" "d")))] | |
0d4a78eb | 3303 | "" |
bbbc206e | 3304 | "%0 = - %1 (V)%!" |
0d4a78eb BS |
3305 | [(set_attr "type" "dsp32")]) |
3306 | ||
c9b3f817 | 3307 | (define_insn "absv2hi2" |
0d4a78eb BS |
3308 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
3309 | (abs:V2HI (match_operand:V2HI 1 "register_operand" "d")))] | |
3310 | "" | |
bbbc206e | 3311 | "%0 = ABS %1 (V)%!" |
0d4a78eb BS |
3312 | [(set_attr "type" "dsp32")]) |
3313 | ||
75d8b2d0 BS |
3314 | ;; Shifts. |
3315 | ||
3316 | (define_insn "ssashiftv2hi3" | |
3317 | [(set (match_operand:V2HI 0 "register_operand" "=d,d,d") | |
3318 | (if_then_else:V2HI | |
3319 | (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) | |
3320 | (ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d") | |
3321 | (match_dup 2)) | |
3322 | (ss_ashift:V2HI (match_dup 1) (match_dup 2))))] | |
3323 | "" | |
3324 | "@ | |
bbbc206e | 3325 | %0 = ASHIFT %1 BY %2 (V, S)%! |
58f76679 BS |
3326 | %0 = %1 << %2 (V,S)%! |
3327 | %0 = %1 >>> %N2 (V,S)%!" | |
75d8b2d0 BS |
3328 | [(set_attr "type" "dsp32")]) |
3329 | ||
3330 | (define_insn "ssashifthi3" | |
3331 | [(set (match_operand:HI 0 "register_operand" "=d,d,d") | |
3332 | (if_then_else:HI | |
3333 | (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) | |
3334 | (ashiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d") | |
3335 | (match_dup 2)) | |
3336 | (ss_ashift:HI (match_dup 1) (match_dup 2))))] | |
3337 | "" | |
3338 | "@ | |
bbbc206e | 3339 | %0 = ASHIFT %1 BY %2 (V, S)%! |
58f76679 BS |
3340 | %0 = %1 << %2 (V,S)%! |
3341 | %0 = %1 >>> %N2 (V,S)%!" | |
75d8b2d0 BS |
3342 | [(set_attr "type" "dsp32")]) |
3343 | ||
3344 | (define_insn "lshiftv2hi3" | |
3345 | [(set (match_operand:V2HI 0 "register_operand" "=d,d,d") | |
3346 | (if_then_else:V2HI | |
3347 | (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) | |
3348 | (lshiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d") | |
3349 | (match_dup 2)) | |
3350 | (ashift:V2HI (match_dup 1) (match_dup 2))))] | |
3351 | "" | |
3352 | "@ | |
bbbc206e | 3353 | %0 = LSHIFT %1 BY %2 (V)%! |
58f76679 BS |
3354 | %0 = %1 << %2 (V)%! |
3355 | %0 = %1 >> %N2 (V)%!" | |
75d8b2d0 BS |
3356 | [(set_attr "type" "dsp32")]) |
3357 | ||
3358 | (define_insn "lshifthi3" | |
3359 | [(set (match_operand:HI 0 "register_operand" "=d,d,d") | |
3360 | (if_then_else:HI | |
3361 | (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) | |
3362 | (lshiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d") | |
3363 | (match_dup 2)) | |
3364 | (ashift:HI (match_dup 1) (match_dup 2))))] | |
3365 | "" | |
3366 | "@ | |
bbbc206e | 3367 | %0 = LSHIFT %1 BY %2 (V)%! |
58f76679 BS |
3368 | %0 = %1 << %2 (V)%! |
3369 | %0 = %1 >> %N2 (V)%!" | |
75d8b2d0 BS |
3370 | [(set_attr "type" "dsp32")]) |
3371 |