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0d4a78eb | 1 | ;;- Machine description for Blackfin for GNU compiler |
4729dc92 | 2 | ;; Copyright 2005, 2006 Free Software Foundation, Inc. |
0d4a78eb BS |
3 | ;; Contributed by Analog Devices. |
4 | ||
5 | ;; This file is part of GCC. | |
6 | ||
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
9 | ;; by the Free Software Foundation; either version 2, or (at your | |
10 | ;; option) any later version. | |
11 | ||
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING. If not, write to | |
39d14dda KC |
19 | ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, |
20 | ;; Boston, MA 02110-1301, USA. | |
0d4a78eb BS |
21 | |
22 | ; operand punctuation marks: | |
23 | ; | |
24 | ; X -- integer value printed as log2 | |
25 | ; Y -- integer value printed as log2(~value) - for bitclear | |
26 | ; h -- print half word register, low part | |
27 | ; d -- print half word register, high part | |
28 | ; D -- print operand as dregs pairs | |
29 | ; w -- print operand as accumulator register word (a0w, a1w) | |
30 | ; H -- high part of double mode operand | |
31 | ; T -- byte register representation Oct. 02 2001 | |
32 | ||
33 | ; constant operand classes | |
34 | ; | |
35 | ; J 2**N 5bit imm scaled | |
36 | ; Ks7 -64 .. 63 signed 7bit imm | |
37 | ; Ku5 0..31 unsigned 5bit imm | |
38 | ; Ks4 -8 .. 7 signed 4bit imm | |
39 | ; Ks3 -4 .. 3 signed 3bit imm | |
40 | ; Ku3 0 .. 7 unsigned 3bit imm | |
41 | ; Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n | |
42 | ; | |
43 | ; register operands | |
44 | ; d (r0..r7) | |
45 | ; a (p0..p5,fp,sp) | |
46 | ; e (a0, a1) | |
47 | ; b (i0..i3) | |
48 | ; f (m0..m3) | |
a9c46998 JZ |
49 | ; v (b0..b3) |
50 | ; c (i0..i3,m0..m3) CIRCREGS | |
51 | ; C (CC) CCREGS | |
b03149e1 JZ |
52 | ; t (lt0,lt1) |
53 | ; k (lc0,lc1) | |
a9c46998 | 54 | ; u (lb0,lb1) |
0d4a78eb BS |
55 | ; |
56 | ||
57 | ;; Define constants for hard registers. | |
58 | ||
59 | (define_constants | |
60 | [(REG_R0 0) | |
61 | (REG_R1 1) | |
62 | (REG_R2 2) | |
63 | (REG_R3 3) | |
64 | (REG_R4 4) | |
65 | (REG_R5 5) | |
66 | (REG_R6 6) | |
67 | (REG_R7 7) | |
68 | ||
69 | (REG_P0 8) | |
70 | (REG_P1 9) | |
71 | (REG_P2 10) | |
72 | (REG_P3 11) | |
73 | (REG_P4 12) | |
74 | (REG_P5 13) | |
75 | (REG_P6 14) | |
76 | (REG_P7 15) | |
77 | ||
78 | (REG_SP 14) | |
79 | (REG_FP 15) | |
80 | ||
81 | (REG_I0 16) | |
df259245 JZ |
82 | (REG_I1 17) |
83 | (REG_I2 18) | |
84 | (REG_I3 19) | |
85 | ||
86 | (REG_B0 20) | |
87 | (REG_B1 21) | |
88 | (REG_B2 22) | |
89 | (REG_B3 23) | |
90 | ||
91 | (REG_L0 24) | |
92 | (REG_L1 25) | |
93 | (REG_L2 26) | |
0d4a78eb BS |
94 | (REG_L3 27) |
95 | ||
96 | (REG_M0 28) | |
97 | (REG_M1 29) | |
98 | (REG_M2 30) | |
99 | (REG_M3 31) | |
100 | ||
101 | (REG_A0 32) | |
102 | (REG_A1 33) | |
103 | ||
104 | (REG_CC 34) | |
105 | (REG_RETS 35) | |
106 | (REG_RETI 36) | |
107 | (REG_RETX 37) | |
108 | (REG_RETN 38) | |
109 | (REG_RETE 39) | |
110 | ||
111 | (REG_ASTAT 40) | |
112 | (REG_SEQSTAT 41) | |
113 | (REG_USP 42) | |
114 | ||
b03149e1 JZ |
115 | (REG_ARGP 43) |
116 | ||
117 | (REG_LT0 44) | |
118 | (REG_LT1 45) | |
119 | (REG_LC0 46) | |
120 | (REG_LC1 47) | |
121 | (REG_LB0 48) | |
122 | (REG_LB1 49)]) | |
0d4a78eb BS |
123 | |
124 | ;; Constants used in UNSPECs and UNSPEC_VOLATILEs. | |
125 | ||
126 | (define_constants | |
127 | [(UNSPEC_CBRANCH_TAKEN 0) | |
128 | (UNSPEC_CBRANCH_NOPS 1) | |
129 | (UNSPEC_RETURN 2) | |
130 | (UNSPEC_MOVE_PIC 3) | |
131 | (UNSPEC_LIBRARY_OFFSET 4) | |
75d8b2d0 BS |
132 | (UNSPEC_PUSH_MULTIPLE 5) |
133 | ;; Multiply or MAC with extra CONST_INT operand specifying the macflag | |
134 | (UNSPEC_MUL_WITH_FLAG 6) | |
6614f9f5 BS |
135 | (UNSPEC_MAC_WITH_FLAG 7) |
136 | (UNSPEC_MOVE_FDPIC 8) | |
b03149e1 | 137 | (UNSPEC_FUNCDESC_GOT17M4 9) |
bbbc206e | 138 | (UNSPEC_LSETUP_END 10) |
942fd98f | 139 | ;; Distinguish a 32-bit version of an insn from a 16-bit version. |
bbbc206e | 140 | (UNSPEC_32BIT 11)]) |
0d4a78eb BS |
141 | |
142 | (define_constants | |
5fcead21 BS |
143 | [(UNSPEC_VOLATILE_EH_RETURN 0) |
144 | (UNSPEC_VOLATILE_CSYNC 1) | |
6614f9f5 BS |
145 | (UNSPEC_VOLATILE_SSYNC 2) |
146 | (UNSPEC_VOLATILE_LOAD_FUNCDESC 3)]) | |
0d4a78eb | 147 | |
75d8b2d0 BS |
148 | (define_constants |
149 | [(MACFLAG_NONE 0) | |
150 | (MACFLAG_T 1) | |
151 | (MACFLAG_FU 2) | |
152 | (MACFLAG_TFU 3) | |
153 | (MACFLAG_IS 4) | |
154 | (MACFLAG_IU 5) | |
155 | (MACFLAG_W32 6) | |
156 | (MACFLAG_M 7) | |
157 | (MACFLAG_S2RND 8) | |
158 | (MACFLAG_ISS2 9) | |
159 | (MACFLAG_IH 10)]) | |
160 | ||
0d4a78eb | 161 | (define_attr "type" |
96f46444 | 162 | "move,movcc,mvi,mcld,mcst,dsp32,mult,alu0,shft,brcc,br,call,misc,sync,compare,dummy" |
0d4a78eb BS |
163 | (const_string "misc")) |
164 | ||
36662eb1 BS |
165 | (define_attr "addrtype" "32bit,preg,ireg" |
166 | (cond [(and (eq_attr "type" "mcld") | |
167 | (and (match_operand 0 "d_register_operand" "") | |
168 | (match_operand 1 "mem_p_address_operand" ""))) | |
169 | (const_string "preg") | |
170 | (and (eq_attr "type" "mcld") | |
171 | (and (match_operand 0 "d_register_operand" "") | |
172 | (match_operand 1 "mem_i_address_operand" ""))) | |
173 | (const_string "ireg") | |
174 | (and (eq_attr "type" "mcst") | |
175 | (and (match_operand 1 "d_register_operand" "") | |
176 | (match_operand 0 "mem_p_address_operand" ""))) | |
177 | (const_string "preg") | |
178 | (and (eq_attr "type" "mcst") | |
179 | (and (match_operand 1 "d_register_operand" "") | |
180 | (match_operand 0 "mem_i_address_operand" ""))) | |
181 | (const_string "ireg")] | |
182 | (const_string "32bit"))) | |
183 | ||
0d4a78eb BS |
184 | ;; Scheduling definitions |
185 | ||
186 | (define_automaton "bfin") | |
187 | ||
36662eb1 BS |
188 | (define_cpu_unit "slot0" "bfin") |
189 | (define_cpu_unit "slot1" "bfin") | |
190 | (define_cpu_unit "slot2" "bfin") | |
191 | ||
192 | ;; Three units used to enforce parallel issue restrictions: | |
942fd98f | 193 | ;; only one of the 16-bit slots can use a P register in an address, |
36662eb1 BS |
194 | ;; and only one them can be a store. |
195 | (define_cpu_unit "store" "bfin") | |
196 | (define_cpu_unit "pregs" "bfin") | |
197 | ||
198 | (define_reservation "core" "slot0+slot1+slot2") | |
0d4a78eb BS |
199 | |
200 | (define_insn_reservation "alu" 1 | |
96f46444 | 201 | (eq_attr "type" "move,movcc,mvi,alu0,shft,brcc,br,call,misc,sync,compare") |
0d4a78eb BS |
202 | "core") |
203 | ||
204 | (define_insn_reservation "imul" 3 | |
205 | (eq_attr "type" "mult") | |
206 | "core*3") | |
207 | ||
36662eb1 BS |
208 | (define_insn_reservation "dsp32" 1 |
209 | (eq_attr "type" "dsp32") | |
210 | "slot0") | |
211 | ||
212 | (define_insn_reservation "load32" 1 | |
213 | (and (not (eq_attr "seq_insns" "multi")) | |
214 | (and (eq_attr "type" "mcld") (eq_attr "addrtype" "32bit"))) | |
215 | "core") | |
216 | ||
217 | (define_insn_reservation "loadp" 1 | |
218 | (and (not (eq_attr "seq_insns" "multi")) | |
219 | (and (eq_attr "type" "mcld") (eq_attr "addrtype" "preg"))) | |
220 | "(slot1|slot2)+pregs") | |
221 | ||
222 | (define_insn_reservation "loadi" 1 | |
223 | (and (not (eq_attr "seq_insns" "multi")) | |
224 | (and (eq_attr "type" "mcld") (eq_attr "addrtype" "ireg"))) | |
225 | "(slot1|slot2)") | |
226 | ||
227 | (define_insn_reservation "store32" 1 | |
228 | (and (not (eq_attr "seq_insns" "multi")) | |
229 | (and (eq_attr "type" "mcst") (eq_attr "addrtype" "32bit"))) | |
0d4a78eb BS |
230 | "core") |
231 | ||
36662eb1 BS |
232 | (define_insn_reservation "storep" 1 |
233 | (and (not (eq_attr "seq_insns" "multi")) | |
234 | (and (eq_attr "type" "mcst") (eq_attr "addrtype" "preg"))) | |
235 | "(slot1|slot2)+pregs+store") | |
236 | ||
237 | (define_insn_reservation "storei" 1 | |
238 | (and (not (eq_attr "seq_insns" "multi")) | |
239 | (and (eq_attr "type" "mcst") (eq_attr "addrtype" "ireg"))) | |
240 | "(slot1|slot2)+store") | |
241 | ||
242 | (define_insn_reservation "multi" 2 | |
243 | (eq_attr "seq_insns" "multi") | |
244 | "core") | |
245 | ||
246 | (absence_set "slot0" "slot1,slot2") | |
247 | (absence_set "slot1" "slot2") | |
248 | ||
0d4a78eb BS |
249 | ;; Make sure genautomata knows about the maximum latency that can be produced |
250 | ;; by the adjust_cost function. | |
251 | (define_insn_reservation "dummy" 5 | |
36662eb1 | 252 | (eq_attr "type" "dummy") |
0d4a78eb BS |
253 | "core") |
254 | \f | |
255 | ;; Operand and operator predicates | |
256 | ||
257 | (include "predicates.md") | |
258 | ||
259 | \f | |
260 | ;;; FRIO branches have been optimized for code density | |
261 | ;;; this comes at a slight cost of complexity when | |
262 | ;;; a compiler needs to generate branches in the general | |
263 | ;;; case. In order to generate the correct branching | |
264 | ;;; mechanisms the compiler needs keep track of instruction | |
265 | ;;; lengths. The follow table describes how to count instructions | |
266 | ;;; for the FRIO architecture. | |
267 | ;;; | |
268 | ;;; unconditional br are 12-bit imm pcrelative branches *2 | |
269 | ;;; conditional br are 10-bit imm pcrelative branches *2 | |
270 | ;;; brcc 10-bit: | |
271 | ;;; 1024 10-bit imm *2 is 2048 (-1024..1022) | |
272 | ;;; br 12-bit : | |
273 | ;;; 4096 12-bit imm *2 is 8192 (-4096..4094) | |
274 | ;;; NOTE : For brcc we generate instructions such as | |
275 | ;;; if cc jmp; jump.[sl] offset | |
276 | ;;; offset of jump.[sl] is from the jump instruction but | |
277 | ;;; gcc calculates length from the if cc jmp instruction | |
a2391c6a JZ |
278 | ;;; furthermore gcc takes the end address of the branch instruction |
279 | ;;; as (pc) for a forward branch | |
280 | ;;; hence our range is (-4094, 4092) instead of (-4096, 4094) for a br | |
0d4a78eb BS |
281 | ;;; |
282 | ;;; The way the (pc) rtx works in these calculations is somewhat odd; | |
283 | ;;; for backward branches it's the address of the current instruction, | |
284 | ;;; for forward branches it's the previously known address of the following | |
285 | ;;; instruction - we have to take this into account by reducing the range | |
286 | ;;; for a forward branch. | |
287 | ||
288 | ;; Lengths for type "mvi" insns are always defined by the instructions | |
289 | ;; themselves. | |
290 | (define_attr "length" "" | |
291 | (cond [(eq_attr "type" "mcld") | |
292 | (if_then_else (match_operand 1 "effective_address_32bit_p" "") | |
293 | (const_int 4) (const_int 2)) | |
294 | ||
295 | (eq_attr "type" "mcst") | |
296 | (if_then_else (match_operand 0 "effective_address_32bit_p" "") | |
297 | (const_int 4) (const_int 2)) | |
298 | ||
299 | (eq_attr "type" "move") (const_int 2) | |
300 | ||
301 | (eq_attr "type" "dsp32") (const_int 4) | |
302 | (eq_attr "type" "call") (const_int 4) | |
303 | ||
304 | (eq_attr "type" "br") | |
305 | (if_then_else (and | |
306 | (le (minus (match_dup 0) (pc)) (const_int 4092)) | |
307 | (ge (minus (match_dup 0) (pc)) (const_int -4096))) | |
308 | (const_int 2) | |
309 | (const_int 4)) | |
310 | ||
311 | (eq_attr "type" "brcc") | |
312 | (cond [(and | |
313 | (le (minus (match_dup 3) (pc)) (const_int 1020)) | |
314 | (ge (minus (match_dup 3) (pc)) (const_int -1024))) | |
315 | (const_int 2) | |
316 | (and | |
a2391c6a | 317 | (le (minus (match_dup 3) (pc)) (const_int 4092)) |
0d4a78eb BS |
318 | (ge (minus (match_dup 3) (pc)) (const_int -4094))) |
319 | (const_int 4)] | |
320 | (const_int 6)) | |
321 | ] | |
322 | ||
323 | (const_int 2))) | |
324 | ||
b03149e1 JZ |
325 | ;; Classify the insns into those that are one instruction and those that |
326 | ;; are more than one in sequence. | |
327 | (define_attr "seq_insns" "single,multi" | |
328 | (const_string "single")) | |
329 | ||
0d4a78eb BS |
330 | ;; Conditional moves |
331 | ||
332 | (define_expand "movsicc" | |
333 | [(set (match_operand:SI 0 "register_operand" "") | |
334 | (if_then_else:SI (match_operand 1 "comparison_operator" "") | |
335 | (match_operand:SI 2 "register_operand" "") | |
336 | (match_operand:SI 3 "register_operand" "")))] | |
337 | "" | |
338 | { | |
339 | operands[1] = bfin_gen_compare (operands[1], SImode); | |
340 | }) | |
341 | ||
342 | (define_insn "*movsicc_insn1" | |
343 | [(set (match_operand:SI 0 "register_operand" "=da,da,da") | |
344 | (if_then_else:SI | |
4729dc92 | 345 | (eq:BI (match_operand:BI 3 "register_operand" "C,C,C") |
0d4a78eb BS |
346 | (const_int 0)) |
347 | (match_operand:SI 1 "register_operand" "da,0,da") | |
348 | (match_operand:SI 2 "register_operand" "0,da,da")))] | |
349 | "" | |
350 | "@ | |
351 | if !cc %0 =%1; /* movsicc-1a */ | |
352 | if cc %0 =%2; /* movsicc-1b */ | |
353 | if !cc %0 =%1; if cc %0=%2; /* movsicc-1 */" | |
354 | [(set_attr "length" "2,2,4") | |
96f46444 | 355 | (set_attr "type" "movcc") |
b03149e1 | 356 | (set_attr "seq_insns" "*,*,multi")]) |
0d4a78eb BS |
357 | |
358 | (define_insn "*movsicc_insn2" | |
359 | [(set (match_operand:SI 0 "register_operand" "=da,da,da") | |
360 | (if_then_else:SI | |
4729dc92 | 361 | (ne:BI (match_operand:BI 3 "register_operand" "C,C,C") |
0d4a78eb BS |
362 | (const_int 0)) |
363 | (match_operand:SI 1 "register_operand" "0,da,da") | |
364 | (match_operand:SI 2 "register_operand" "da,0,da")))] | |
365 | "" | |
366 | "@ | |
367 | if !cc %0 =%2; /* movsicc-2b */ | |
368 | if cc %0 =%1; /* movsicc-2a */ | |
369 | if cc %0 =%1; if !cc %0=%2; /* movsicc-1 */" | |
370 | [(set_attr "length" "2,2,4") | |
96f46444 | 371 | (set_attr "type" "movcc") |
b03149e1 | 372 | (set_attr "seq_insns" "*,*,multi")]) |
0d4a78eb BS |
373 | |
374 | ;; Insns to load HIGH and LO_SUM | |
375 | ||
376 | (define_insn "movsi_high" | |
377 | [(set (match_operand:SI 0 "register_operand" "=x") | |
378 | (high:SI (match_operand:SI 1 "immediate_operand" "i")))] | |
379 | "reload_completed" | |
380 | "%d0 = %d1;" | |
381 | [(set_attr "type" "mvi") | |
382 | (set_attr "length" "4")]) | |
383 | ||
384 | (define_insn "movstricthi_high" | |
385 | [(set (match_operand:SI 0 "register_operand" "+x") | |
386 | (ior:SI (and:SI (match_dup 0) (const_int 65535)) | |
387 | (match_operand:SI 1 "immediate_operand" "i")))] | |
388 | "reload_completed" | |
389 | "%d0 = %d1;" | |
390 | [(set_attr "type" "mvi") | |
391 | (set_attr "length" "4")]) | |
392 | ||
393 | (define_insn "movsi_low" | |
394 | [(set (match_operand:SI 0 "register_operand" "=x") | |
395 | (lo_sum:SI (match_operand:SI 1 "register_operand" "0") | |
396 | (match_operand:SI 2 "immediate_operand" "i")))] | |
397 | "reload_completed" | |
398 | "%h0 = %h2;" | |
399 | [(set_attr "type" "mvi") | |
400 | (set_attr "length" "4")]) | |
401 | ||
402 | (define_insn "movsi_high_pic" | |
403 | [(set (match_operand:SI 0 "register_operand" "=x") | |
404 | (high:SI (unspec:SI [(match_operand:SI 1 "" "")] | |
405 | UNSPEC_MOVE_PIC)))] | |
406 | "" | |
407 | "%d0 = %1@GOT_LOW;" | |
408 | [(set_attr "type" "mvi") | |
409 | (set_attr "length" "4")]) | |
410 | ||
411 | (define_insn "movsi_low_pic" | |
412 | [(set (match_operand:SI 0 "register_operand" "=x") | |
413 | (lo_sum:SI (match_operand:SI 1 "register_operand" "0") | |
414 | (unspec:SI [(match_operand:SI 2 "" "")] | |
415 | UNSPEC_MOVE_PIC)))] | |
416 | "" | |
417 | "%h0 = %h2@GOT_HIGH;" | |
418 | [(set_attr "type" "mvi") | |
419 | (set_attr "length" "4")]) | |
420 | ||
421 | ;;; Move instructions | |
422 | ||
423 | (define_insn_and_split "movdi_insn" | |
424 | [(set (match_operand:DI 0 "nonimmediate_operand" "=x,mx,r") | |
425 | (match_operand:DI 1 "general_operand" "iFx,r,mx"))] | |
426 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" | |
427 | "#" | |
428 | "reload_completed" | |
429 | [(set (match_dup 2) (match_dup 3)) | |
430 | (set (match_dup 4) (match_dup 5))] | |
431 | { | |
432 | rtx lo_half[2], hi_half[2]; | |
433 | split_di (operands, 2, lo_half, hi_half); | |
434 | ||
435 | if (reg_overlap_mentioned_p (lo_half[0], hi_half[1])) | |
436 | { | |
437 | operands[2] = hi_half[0]; | |
438 | operands[3] = hi_half[1]; | |
439 | operands[4] = lo_half[0]; | |
440 | operands[5] = lo_half[1]; | |
441 | } | |
442 | else | |
443 | { | |
444 | operands[2] = lo_half[0]; | |
445 | operands[3] = lo_half[1]; | |
446 | operands[4] = hi_half[0]; | |
447 | operands[5] = hi_half[1]; | |
448 | } | |
449 | }) | |
450 | ||
451 | (define_insn "movbi" | |
4729dc92 BS |
452 | [(set (match_operand:BI 0 "nonimmediate_operand" "=x,x,d,md,C,d,C") |
453 | (match_operand:BI 1 "general_operand" "x,xKs3,md,d,d,C,P0"))] | |
0d4a78eb BS |
454 | |
455 | "" | |
456 | "@ | |
457 | %0 = %1; | |
458 | %0 = %1 (X); | |
bbbc206e | 459 | %0 = B %1 (Z)%! |
4729dc92 | 460 | B %0 = %1; |
0d4a78eb | 461 | CC = %1; |
49373252 BS |
462 | %0 = CC; |
463 | R0 = R0 | R0; CC = AC0;" | |
464 | [(set_attr "type" "move,mvi,mcld,mcst,compare,compare,alu0") | |
b03149e1 JZ |
465 | (set_attr "length" "2,2,*,*,2,2,4") |
466 | (set_attr "seq_insns" "*,*,*,*,*,*,multi")]) | |
0d4a78eb BS |
467 | |
468 | (define_insn "movpdi" | |
469 | [(set (match_operand:PDI 0 "nonimmediate_operand" "=e,<,e") | |
470 | (match_operand:PDI 1 "general_operand" " e,e,>"))] | |
471 | "" | |
472 | "@ | |
473 | %0 = %1; | |
474 | %0 = %x1; %0 = %w1; | |
475 | %w0 = %1; %x0 = %1;" | |
b03149e1 JZ |
476 | [(set_attr "type" "move,mcst,mcld") |
477 | (set_attr "seq_insns" "*,multi,multi")]) | |
0d4a78eb | 478 | |
75d8b2d0 BS |
479 | (define_insn "load_accumulator" |
480 | [(set (match_operand:PDI 0 "register_operand" "=e") | |
481 | (sign_extend:PDI (match_operand:SI 1 "register_operand" "d")))] | |
482 | "" | |
483 | "%0 = %1;" | |
484 | [(set_attr "type" "move")]) | |
485 | ||
486 | (define_insn_and_split "load_accumulator_pair" | |
487 | [(set (match_operand:V2PDI 0 "register_operand" "=e") | |
488 | (sign_extend:V2PDI (vec_concat:V2SI | |
489 | (match_operand:SI 1 "register_operand" "d") | |
490 | (match_operand:SI 2 "register_operand" "d"))))] | |
491 | "" | |
492 | "#" | |
493 | "reload_completed" | |
494 | [(set (match_dup 3) (sign_extend:PDI (match_dup 1))) | |
495 | (set (match_dup 4) (sign_extend:PDI (match_dup 2)))] | |
496 | { | |
497 | operands[3] = gen_rtx_REG (PDImode, REGNO (operands[0])); | |
498 | operands[4] = gen_rtx_REG (PDImode, REGNO (operands[0]) + 1); | |
499 | }) | |
500 | ||
0d4a78eb BS |
501 | (define_insn "*pushsi_insn" |
502 | [(set (mem:SI (pre_dec:SI (reg:SI REG_SP))) | |
503 | (match_operand:SI 0 "register_operand" "xy"))] | |
504 | "" | |
505 | "[--SP] = %0;" | |
506 | [(set_attr "type" "mcst") | |
35e3ced9 | 507 | (set_attr "addrtype" "32bit") |
0d4a78eb BS |
508 | (set_attr "length" "2")]) |
509 | ||
510 | (define_insn "*popsi_insn" | |
35e3ced9 | 511 | [(set (match_operand:SI 0 "register_operand" "=d,xy") |
0d4a78eb BS |
512 | (mem:SI (post_inc:SI (reg:SI REG_SP))))] |
513 | "" | |
bbbc206e | 514 | "%0 = [SP++]%!" |
0d4a78eb | 515 | [(set_attr "type" "mcld") |
35e3ced9 | 516 | (set_attr "addrtype" "preg,32bit") |
0d4a78eb BS |
517 | (set_attr "length" "2")]) |
518 | ||
519 | ;; The first alternative is used to make reload choose a limited register | |
520 | ;; class when faced with a movsi_insn that had its input operand replaced | |
521 | ;; with a PLUS. We generally require fewer secondary reloads this way. | |
0d4a78eb | 522 | |
b03149e1 JZ |
523 | (define_insn "*movsi_insn" |
524 | [(set (match_operand:SI 0 "nonimmediate_operand" "=da,x*y,*k,da,da,x,x,x,da,mr") | |
525 | (match_operand:SI 1 "general_operand" "da,x*y,da,*k,xKs7,xKsh,xKuh,ix,mr,da"))] | |
0d4a78eb | 526 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" |
b03149e1 JZ |
527 | "@ |
528 | %0 = %1; | |
529 | %0 = %1; | |
0d4a78eb BS |
530 | %0 = %1; |
531 | %0 = %1; | |
532 | %0 = %1 (X); | |
533 | %0 = %1 (X); | |
534 | %0 = %1 (Z); | |
535 | # | |
bbbc206e BS |
536 | %0 = %1%! |
537 | %0 = %1%!" | |
b03149e1 JZ |
538 | [(set_attr "type" "move,move,move,move,mvi,mvi,mvi,*,mcld,mcst") |
539 | (set_attr "length" "2,2,2,2,2,4,4,*,*,*")]) | |
0d4a78eb | 540 | |
bbbc206e BS |
541 | (define_insn "*movsi_insn32" |
542 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
543 | (unspec:SI [(match_operand:SI 1 "nonmemory_operand" "d,P0")] UNSPEC_32BIT))] | |
544 | "" | |
545 | "@ | |
546 | %0 = ROT %1 BY 0%! | |
547 | %0 = %0 -|- %0%!" | |
548 | [(set_attr "type" "dsp32")]) | |
549 | ||
550 | (define_split | |
551 | [(set (match_operand:SI 0 "d_register_operand" "") | |
552 | (const_int 0))] | |
553 | "splitting_for_sched && !optimize_size" | |
554 | [(set (match_dup 0) (unspec:SI [(const_int 0)] UNSPEC_32BIT))]) | |
555 | ||
556 | (define_split | |
557 | [(set (match_operand:SI 0 "d_register_operand" "") | |
558 | (match_operand:SI 1 "d_register_operand" ""))] | |
559 | "splitting_for_sched && !optimize_size" | |
560 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_32BIT))]) | |
561 | ||
75d8b2d0 BS |
562 | (define_insn_and_split "*movv2hi_insn" |
563 | [(set (match_operand:V2HI 0 "nonimmediate_operand" "=da,da,d,dm") | |
564 | (match_operand:V2HI 1 "general_operand" "i,di,md,d"))] | |
0d4a78eb BS |
565 | |
566 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" | |
75d8b2d0 BS |
567 | "@ |
568 | # | |
569 | %0 = %1; | |
bbbc206e BS |
570 | %0 = %1%! |
571 | %0 = %1%!" | |
75d8b2d0 BS |
572 | "reload_completed && GET_CODE (operands[1]) == CONST_VECTOR" |
573 | [(set (match_dup 0) (high:SI (match_dup 2))) | |
574 | (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 3)))] | |
575 | { | |
576 | HOST_WIDE_INT intval = INTVAL (XVECEXP (operands[1], 0, 1)) << 16; | |
577 | intval |= INTVAL (XVECEXP (operands[1], 0, 0)) & 0xFFFF; | |
554006bd | 578 | |
75d8b2d0 BS |
579 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[0])); |
580 | operands[2] = operands[3] = GEN_INT (trunc_int_for_mode (intval, SImode)); | |
581 | } | |
582 | [(set_attr "type" "move,move,mcld,mcst") | |
583 | (set_attr "length" "2,2,*,*")]) | |
0d4a78eb BS |
584 | |
585 | (define_insn "*movhi_insn" | |
586 | [(set (match_operand:HI 0 "nonimmediate_operand" "=x,da,x,d,mr") | |
587 | (match_operand:HI 1 "general_operand" "x,xKs7,xKsh,mr,d"))] | |
588 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" | |
c4963a0a BS |
589 | { |
590 | static const char *templates[] = { | |
591 | "%0 = %1;", | |
592 | "%0 = %1 (X);", | |
593 | "%0 = %1 (X);", | |
bbbc206e BS |
594 | "%0 = W %1 (X)%!", |
595 | "W %0 = %1%!", | |
596 | "%h0 = W %1%!", | |
597 | "W %0 = %h1%!" | |
c4963a0a BS |
598 | }; |
599 | int alt = which_alternative; | |
600 | rtx mem = (MEM_P (operands[0]) ? operands[0] | |
601 | : MEM_P (operands[1]) ? operands[1] : NULL_RTX); | |
602 | if (mem && bfin_dsp_memref_p (mem)) | |
603 | alt += 2; | |
604 | return templates[alt]; | |
605 | } | |
0d4a78eb BS |
606 | [(set_attr "type" "move,mvi,mvi,mcld,mcst") |
607 | (set_attr "length" "2,2,4,*,*")]) | |
608 | ||
609 | (define_insn "*movqi_insn" | |
610 | [(set (match_operand:QI 0 "nonimmediate_operand" "=x,da,x,d,mr") | |
611 | (match_operand:QI 1 "general_operand" "x,xKs7,xKsh,mr,d"))] | |
612 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" | |
613 | "@ | |
614 | %0 = %1; | |
615 | %0 = %1 (X); | |
616 | %0 = %1 (X); | |
bbbc206e BS |
617 | %0 = B %1 (X)%! |
618 | B %0 = %1%!" | |
0d4a78eb BS |
619 | [(set_attr "type" "move,mvi,mvi,mcld,mcst") |
620 | (set_attr "length" "2,2,4,*,*")]) | |
621 | ||
622 | (define_insn "*movsf_insn" | |
623 | [(set (match_operand:SF 0 "nonimmediate_operand" "=x,x,da,mr") | |
624 | (match_operand:SF 1 "general_operand" "x,Fx,mr,da"))] | |
625 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" | |
626 | "@ | |
627 | %0 = %1; | |
628 | # | |
bbbc206e BS |
629 | %0 = %1%! |
630 | %0 = %1%!" | |
0d4a78eb BS |
631 | [(set_attr "type" "move,*,mcld,mcst")]) |
632 | ||
633 | (define_insn_and_split "movdf_insn" | |
634 | [(set (match_operand:DF 0 "nonimmediate_operand" "=x,mx,r") | |
635 | (match_operand:DF 1 "general_operand" "iFx,r,mx"))] | |
636 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" | |
637 | "#" | |
638 | "reload_completed" | |
639 | [(set (match_dup 2) (match_dup 3)) | |
640 | (set (match_dup 4) (match_dup 5))] | |
641 | { | |
642 | rtx lo_half[2], hi_half[2]; | |
643 | split_di (operands, 2, lo_half, hi_half); | |
644 | ||
645 | if (reg_overlap_mentioned_p (lo_half[0], hi_half[1])) | |
646 | { | |
647 | operands[2] = hi_half[0]; | |
648 | operands[3] = hi_half[1]; | |
649 | operands[4] = lo_half[0]; | |
650 | operands[5] = lo_half[1]; | |
651 | } | |
652 | else | |
653 | { | |
654 | operands[2] = lo_half[0]; | |
655 | operands[3] = lo_half[1]; | |
656 | operands[4] = hi_half[0]; | |
657 | operands[5] = hi_half[1]; | |
658 | } | |
659 | }) | |
660 | ||
75d8b2d0 BS |
661 | ;; Storing halfwords. |
662 | (define_insn "*movsi_insv" | |
663 | [(set (zero_extract:SI (match_operand 0 "register_operand" "+d,x") | |
664 | (const_int 16) | |
665 | (const_int 16)) | |
666 | (match_operand:SI 1 "nonmemory_operand" "d,n"))] | |
667 | "" | |
668 | "@ | |
bbbc206e | 669 | %d0 = %h1 << 0%! |
75d8b2d0 BS |
670 | %d0 = %1;" |
671 | [(set_attr "type" "dsp32,mvi")]) | |
672 | ||
673 | (define_expand "insv" | |
674 | [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "") | |
675 | (match_operand:SI 1 "immediate_operand" "") | |
676 | (match_operand:SI 2 "immediate_operand" "")) | |
677 | (match_operand:SI 3 "nonmemory_operand" ""))] | |
678 | "" | |
679 | { | |
680 | if (INTVAL (operands[1]) != 16 || INTVAL (operands[2]) != 16) | |
681 | FAIL; | |
682 | ||
683 | /* From mips.md: insert_bit_field doesn't verify that our source | |
684 | matches the predicate, so check it again here. */ | |
685 | if (! register_operand (operands[0], VOIDmode)) | |
686 | FAIL; | |
687 | }) | |
688 | ||
0d4a78eb BS |
689 | ;; This is the main "hook" for PIC code. When generating |
690 | ;; PIC, movsi is responsible for determining when the source address | |
691 | ;; needs PIC relocation and appropriately calling legitimize_pic_address | |
692 | ;; to perform the actual relocation. | |
693 | ||
694 | (define_expand "movsi" | |
695 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
696 | (match_operand:SI 1 "general_operand" ""))] | |
697 | "" | |
d6f6753e BS |
698 | { |
699 | if (expand_move (operands, SImode)) | |
700 | DONE; | |
701 | }) | |
0d4a78eb BS |
702 | |
703 | (define_expand "movv2hi" | |
704 | [(set (match_operand:V2HI 0 "nonimmediate_operand" "") | |
705 | (match_operand:V2HI 1 "general_operand" ""))] | |
706 | "" | |
707 | "expand_move (operands, V2HImode);") | |
708 | ||
709 | (define_expand "movdi" | |
710 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
711 | (match_operand:DI 1 "general_operand" ""))] | |
712 | "" | |
713 | "expand_move (operands, DImode);") | |
714 | ||
715 | (define_expand "movsf" | |
716 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
717 | (match_operand:SF 1 "general_operand" ""))] | |
718 | "" | |
719 | "expand_move (operands, SFmode);") | |
720 | ||
721 | (define_expand "movdf" | |
722 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
723 | (match_operand:DF 1 "general_operand" ""))] | |
724 | "" | |
725 | "expand_move (operands, DFmode);") | |
726 | ||
727 | (define_expand "movhi" | |
728 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
729 | (match_operand:HI 1 "general_operand" ""))] | |
730 | "" | |
731 | "expand_move (operands, HImode);") | |
732 | ||
733 | (define_expand "movqi" | |
734 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
735 | (match_operand:QI 1 "general_operand" ""))] | |
736 | "" | |
737 | " expand_move (operands, QImode); ") | |
738 | ||
739 | ;; Some define_splits to break up SI/SFmode loads of immediate constants. | |
740 | ||
741 | (define_split | |
742 | [(set (match_operand:SI 0 "register_operand" "") | |
743 | (match_operand:SI 1 "symbolic_or_const_operand" ""))] | |
744 | "reload_completed | |
745 | /* Always split symbolic operands; split integer constants that are | |
746 | too large for a single instruction. */ | |
747 | && (GET_CODE (operands[1]) != CONST_INT | |
748 | || (INTVAL (operands[1]) < -32768 | |
749 | || INTVAL (operands[1]) >= 65536 | |
750 | || (INTVAL (operands[1]) >= 32768 && PREG_P (operands[0]))))" | |
751 | [(set (match_dup 0) (high:SI (match_dup 1))) | |
752 | (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 1)))] | |
753 | { | |
754 | if (GET_CODE (operands[1]) == CONST_INT | |
755 | && split_load_immediate (operands)) | |
756 | DONE; | |
757 | /* ??? Do something about TARGET_LOW_64K. */ | |
758 | }) | |
759 | ||
760 | (define_split | |
761 | [(set (match_operand:SF 0 "register_operand" "") | |
762 | (match_operand:SF 1 "immediate_operand" ""))] | |
763 | "reload_completed" | |
764 | [(set (match_dup 2) (high:SI (match_dup 3))) | |
765 | (set (match_dup 2) (lo_sum:SI (match_dup 2) (match_dup 3)))] | |
766 | { | |
767 | long values; | |
768 | REAL_VALUE_TYPE value; | |
769 | ||
3b9dd769 | 770 | gcc_assert (GET_CODE (operands[1]) == CONST_DOUBLE); |
0d4a78eb BS |
771 | |
772 | REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]); | |
773 | REAL_VALUE_TO_TARGET_SINGLE (value, values); | |
774 | ||
775 | operands[2] = gen_rtx_REG (SImode, true_regnum (operands[0])); | |
776 | operands[3] = GEN_INT (trunc_int_for_mode (values, SImode)); | |
777 | if (values >= -32768 && values < 65536) | |
778 | { | |
779 | emit_move_insn (operands[2], operands[3]); | |
780 | DONE; | |
781 | } | |
782 | if (split_load_immediate (operands + 2)) | |
783 | DONE; | |
784 | }) | |
785 | ||
786 | ;; Sadly, this can't be a proper named movstrict pattern, since the compiler | |
787 | ;; expects to be able to use registers for operand 1. | |
788 | ;; Note that the asm instruction is defined by the manual to take an unsigned | |
789 | ;; constant, but it doesn't matter to the assembler, and the compiler only | |
790 | ;; deals with sign-extended constants. Hence "Ksh". | |
75d8b2d0 | 791 | (define_insn "movstricthi_1" |
0d4a78eb BS |
792 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+x")) |
793 | (match_operand:HI 1 "immediate_operand" "Ksh"))] | |
794 | "" | |
795 | "%h0 = %1;" | |
796 | [(set_attr "type" "mvi") | |
797 | (set_attr "length" "4")]) | |
798 | ||
799 | ;; Sign and zero extensions | |
800 | ||
c4963a0a | 801 | (define_insn_and_split "extendhisi2" |
0d4a78eb BS |
802 | [(set (match_operand:SI 0 "register_operand" "=d, d") |
803 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))] | |
804 | "" | |
805 | "@ | |
806 | %0 = %h1 (X); | |
bbbc206e | 807 | %0 = W %h1 (X)%!" |
c4963a0a BS |
808 | "reload_completed && bfin_dsp_memref_p (operands[1])" |
809 | [(set (match_dup 2) (match_dup 1)) | |
810 | (set (match_dup 0) (sign_extend:SI (match_dup 2)))] | |
811 | { | |
812 | operands[2] = gen_lowpart (HImode, operands[0]); | |
813 | } | |
0d4a78eb BS |
814 | [(set_attr "type" "alu0,mcld")]) |
815 | ||
c4963a0a | 816 | (define_insn_and_split "zero_extendhisi2" |
0d4a78eb BS |
817 | [(set (match_operand:SI 0 "register_operand" "=d, d") |
818 | (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))] | |
819 | "" | |
820 | "@ | |
821 | %0 = %h1 (Z); | |
bbbc206e | 822 | %0 = W %h1 (Z)%!" |
c4963a0a BS |
823 | "reload_completed && bfin_dsp_memref_p (operands[1])" |
824 | [(set (match_dup 2) (match_dup 1)) | |
825 | (set (match_dup 0) (zero_extend:SI (match_dup 2)))] | |
826 | { | |
827 | operands[2] = gen_lowpart (HImode, operands[0]); | |
828 | } | |
0d4a78eb BS |
829 | [(set_attr "type" "alu0,mcld")]) |
830 | ||
831 | (define_insn "zero_extendbisi2" | |
832 | [(set (match_operand:SI 0 "register_operand" "=d") | |
833 | (zero_extend:SI (match_operand:BI 1 "nonimmediate_operand" "C")))] | |
834 | "" | |
835 | "%0 = %1;" | |
836 | [(set_attr "type" "compare")]) | |
837 | ||
838 | (define_insn "extendqihi2" | |
839 | [(set (match_operand:HI 0 "register_operand" "=d, d") | |
840 | (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] | |
841 | "" | |
842 | "@ | |
bbbc206e | 843 | %0 = B %1 (X)%! |
0d4a78eb BS |
844 | %0 = %T1 (X);" |
845 | [(set_attr "type" "mcld,alu0")]) | |
846 | ||
847 | (define_insn "extendqisi2" | |
848 | [(set (match_operand:SI 0 "register_operand" "=d, d") | |
849 | (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] | |
850 | "" | |
851 | "@ | |
bbbc206e | 852 | %0 = B %1 (X)%! |
0d4a78eb BS |
853 | %0 = %T1 (X);" |
854 | [(set_attr "type" "mcld,alu0")]) | |
855 | ||
856 | ||
857 | (define_insn "zero_extendqihi2" | |
858 | [(set (match_operand:HI 0 "register_operand" "=d, d") | |
859 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] | |
860 | "" | |
861 | "@ | |
bbbc206e | 862 | %0 = B %1 (Z)%! |
0d4a78eb BS |
863 | %0 = %T1 (Z);" |
864 | [(set_attr "type" "mcld,alu0")]) | |
865 | ||
866 | ||
867 | (define_insn "zero_extendqisi2" | |
868 | [(set (match_operand:SI 0 "register_operand" "=d, d") | |
869 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] | |
870 | "" | |
871 | "@ | |
bbbc206e | 872 | %0 = B %1 (Z)%! |
0d4a78eb BS |
873 | %0 = %T1 (Z);" |
874 | [(set_attr "type" "mcld,alu0")]) | |
875 | ||
876 | ;; DImode logical operations | |
877 | ||
878 | (define_code_macro any_logical [and ior xor]) | |
879 | (define_code_attr optab [(and "and") | |
880 | (ior "ior") | |
881 | (xor "xor")]) | |
882 | (define_code_attr op [(and "&") | |
883 | (ior "|") | |
884 | (xor "^")]) | |
885 | (define_code_attr high_result [(and "0") | |
886 | (ior "%H1") | |
887 | (xor "%H1")]) | |
888 | ||
889 | (define_insn "<optab>di3" | |
890 | [(set (match_operand:DI 0 "register_operand" "=d") | |
891 | (any_logical:DI (match_operand:DI 1 "register_operand" "0") | |
892 | (match_operand:DI 2 "register_operand" "d")))] | |
893 | "" | |
894 | "%0 = %1 <op> %2;\\n\\t%H0 = %H1 <op> %H2;" | |
b03149e1 JZ |
895 | [(set_attr "length" "4") |
896 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
897 | |
898 | (define_insn "*<optab>di_zesidi_di" | |
899 | [(set (match_operand:DI 0 "register_operand" "=d") | |
900 | (any_logical:DI (zero_extend:DI | |
901 | (match_operand:SI 2 "register_operand" "d")) | |
902 | (match_operand:DI 1 "register_operand" "d")))] | |
903 | "" | |
904 | "%0 = %1 <op> %2;\\n\\t%H0 = <high_result>;" | |
b03149e1 JZ |
905 | [(set_attr "length" "4") |
906 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
907 | |
908 | (define_insn "*<optab>di_sesdi_di" | |
909 | [(set (match_operand:DI 0 "register_operand" "=d") | |
910 | (any_logical:DI (sign_extend:DI | |
911 | (match_operand:SI 2 "register_operand" "d")) | |
912 | (match_operand:DI 1 "register_operand" "0"))) | |
913 | (clobber (match_scratch:SI 3 "=&d"))] | |
914 | "" | |
915 | "%0 = %1 <op> %2;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %H1 <op> %3;" | |
b03149e1 JZ |
916 | [(set_attr "length" "8") |
917 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
918 | |
919 | (define_insn "negdi2" | |
920 | [(set (match_operand:DI 0 "register_operand" "=d") | |
921 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
922 | (clobber (match_scratch:SI 2 "=&d")) | |
923 | (clobber (reg:CC REG_CC))] | |
924 | "" | |
925 | "%2 = 0; %2 = %2 - %1; cc = ac0; cc = !cc; %2 = cc;\\n\\t%0 = -%1; %H0 = -%H1; %H0 = %H0 - %2;" | |
b03149e1 JZ |
926 | [(set_attr "length" "16") |
927 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
928 | |
929 | (define_insn "one_cmpldi2" | |
930 | [(set (match_operand:DI 0 "register_operand" "=d") | |
931 | (not:DI (match_operand:DI 1 "register_operand" "d")))] | |
932 | "" | |
933 | "%0 = ~%1;\\n\\t%H0 = ~%H1;" | |
b03149e1 JZ |
934 | [(set_attr "length" "4") |
935 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
936 | |
937 | ;; DImode zero and sign extend patterns | |
938 | ||
939 | (define_insn_and_split "zero_extendsidi2" | |
940 | [(set (match_operand:DI 0 "register_operand" "=d") | |
941 | (zero_extend:DI (match_operand:SI 1 "register_operand" "d")))] | |
942 | "" | |
943 | "#" | |
944 | "reload_completed" | |
945 | [(set (match_dup 3) (const_int 0))] | |
946 | { | |
947 | split_di (operands, 1, operands + 2, operands + 3); | |
948 | if (REGNO (operands[0]) != REGNO (operands[1])) | |
949 | emit_move_insn (operands[2], operands[1]); | |
950 | }) | |
951 | ||
952 | (define_insn "zero_extendqidi2" | |
953 | [(set (match_operand:DI 0 "register_operand" "=d") | |
954 | (zero_extend:DI (match_operand:QI 1 "register_operand" "d")))] | |
955 | "" | |
956 | "%0 = %T1 (Z);\\n\\t%H0 = 0;" | |
b03149e1 JZ |
957 | [(set_attr "length" "4") |
958 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
959 | |
960 | (define_insn "zero_extendhidi2" | |
961 | [(set (match_operand:DI 0 "register_operand" "=d") | |
962 | (zero_extend:DI (match_operand:HI 1 "register_operand" "d")))] | |
963 | "" | |
964 | "%0 = %h1 (Z);\\n\\t%H0 = 0;" | |
b03149e1 JZ |
965 | [(set_attr "length" "4") |
966 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
967 | |
968 | (define_insn_and_split "extendsidi2" | |
969 | [(set (match_operand:DI 0 "register_operand" "=d") | |
970 | (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))] | |
971 | "" | |
972 | "#" | |
973 | "reload_completed" | |
974 | [(set (match_dup 3) (match_dup 1)) | |
975 | (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))] | |
976 | { | |
977 | split_di (operands, 1, operands + 2, operands + 3); | |
978 | if (REGNO (operands[0]) != REGNO (operands[1])) | |
979 | emit_move_insn (operands[2], operands[1]); | |
980 | }) | |
981 | ||
982 | (define_insn_and_split "extendqidi2" | |
983 | [(set (match_operand:DI 0 "register_operand" "=d") | |
984 | (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))] | |
985 | "" | |
986 | "#" | |
987 | "reload_completed" | |
988 | [(set (match_dup 2) (sign_extend:SI (match_dup 1))) | |
989 | (set (match_dup 3) (sign_extend:SI (match_dup 1))) | |
990 | (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))] | |
991 | { | |
992 | split_di (operands, 1, operands + 2, operands + 3); | |
993 | }) | |
994 | ||
995 | (define_insn_and_split "extendhidi2" | |
996 | [(set (match_operand:DI 0 "register_operand" "=d") | |
997 | (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))] | |
998 | "" | |
999 | "#" | |
1000 | "reload_completed" | |
1001 | [(set (match_dup 2) (sign_extend:SI (match_dup 1))) | |
1002 | (set (match_dup 3) (sign_extend:SI (match_dup 1))) | |
1003 | (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))] | |
1004 | { | |
1005 | split_di (operands, 1, operands + 2, operands + 3); | |
1006 | }) | |
1007 | ||
1008 | ;; DImode arithmetic operations | |
1009 | ||
2889abed BS |
1010 | (define_insn "add_with_carry" |
1011 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1012 | (plus:SI (match_operand:SI 1 "register_operand" "%0,0") | |
1013 | (match_operand:SI 2 "nonmemory_operand" "Ks7,d"))) | |
1014 | (set (match_operand:SI 3 "register_operand" "=d,d") | |
1015 | (truncate:SI | |
1016 | (lshiftrt:DI (plus:DI (zero_extend:DI (match_dup 1)) | |
1017 | (zero_extend:DI (match_dup 2))) | |
1018 | (const_int 32)))) | |
1019 | (clobber (reg:CC 34))] | |
1020 | "" | |
1021 | "@ | |
1022 | %0 += %2; cc = ac0; %3 = cc; | |
1023 | %0 = %0 + %2; cc = ac0; %3 = cc;" | |
1024 | [(set_attr "type" "alu0") | |
1025 | (set_attr "length" "6") | |
1026 | (set_attr "seq_insns" "multi")]) | |
1027 | ||
0d4a78eb BS |
1028 | (define_insn "adddi3" |
1029 | [(set (match_operand:DI 0 "register_operand" "=&d,&d,&d") | |
1030 | (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0") | |
1031 | (match_operand:DI 2 "nonmemory_operand" "Kn7,Ks7,d"))) | |
1032 | (clobber (match_scratch:SI 3 "=&d,&d,&d")) | |
1033 | (clobber (reg:CC 34))] | |
1034 | "" | |
1035 | "@ | |
1036 | %0 += %2; cc = ac0; %3 = cc; %H0 += -1; %H0 = %H0 + %3; | |
1037 | %0 += %2; cc = ac0; %3 = cc; %H0 = %H0 + %3; | |
1038 | %0 = %0 + %2; cc = ac0; %3 = cc; %H0 = %H0 + %H2; %H0 = %H0 + %3;" | |
1039 | [(set_attr "type" "alu0") | |
b03149e1 JZ |
1040 | (set_attr "length" "10,8,10") |
1041 | (set_attr "seq_insns" "multi,multi,multi")]) | |
0d4a78eb BS |
1042 | |
1043 | (define_insn "subdi3" | |
1044 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
1045 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
1046 | (match_operand:DI 2 "register_operand" "d"))) | |
1047 | (clobber (reg:CC 34))] | |
1048 | "" | |
1049 | "%0 = %1-%2;\\n\\tcc = ac0;\\n\\t%H0 = %H1-%H2;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:" | |
b03149e1 JZ |
1050 | [(set_attr "length" "10") |
1051 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
1052 | |
1053 | (define_insn "*subdi_di_zesidi" | |
1054 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1055 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
1056 | (zero_extend:DI | |
1057 | (match_operand:SI 2 "register_operand" "d")))) | |
1058 | (clobber (match_scratch:SI 3 "=&d")) | |
1059 | (clobber (reg:CC 34))] | |
1060 | "" | |
1061 | "%0 = %1 - %2;\\n\\tcc = ac0;\\n\\tcc = ! cc;\\n\\t%3 = cc;\\n\\t%H0 = %H1 - %3;" | |
b03149e1 JZ |
1062 | [(set_attr "length" "10") |
1063 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
1064 | |
1065 | (define_insn "*subdi_zesidi_di" | |
1066 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1067 | (minus:DI (zero_extend:DI | |
1068 | (match_operand:SI 2 "register_operand" "d")) | |
1069 | (match_operand:DI 1 "register_operand" "0"))) | |
1070 | (clobber (match_scratch:SI 3 "=&d")) | |
1071 | (clobber (reg:CC 34))] | |
1072 | "" | |
1073 | "%0 = %2 - %1;\\n\\tcc = ac0;\\n\\tcc = ! cc;\\n\\t%3 = cc;\\n\\t%3 = -%3;\\n\\t%H0 = %3 - %H1" | |
b03149e1 JZ |
1074 | [(set_attr "length" "12") |
1075 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
1076 | |
1077 | (define_insn "*subdi_di_sesidi" | |
1078 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1079 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
1080 | (sign_extend:DI | |
1081 | (match_operand:SI 2 "register_operand" "d")))) | |
1082 | (clobber (match_scratch:SI 3 "=&d")) | |
1083 | (clobber (reg:CC 34))] | |
1084 | "" | |
1085 | "%0 = %1 - %2;\\n\\tcc = ac0;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %H1 - %3;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:" | |
b03149e1 JZ |
1086 | [(set_attr "length" "14") |
1087 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
1088 | |
1089 | (define_insn "*subdi_sesidi_di" | |
1090 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1091 | (minus:DI (sign_extend:DI | |
1092 | (match_operand:SI 2 "register_operand" "d")) | |
1093 | (match_operand:DI 1 "register_operand" "0"))) | |
1094 | (clobber (match_scratch:SI 3 "=&d")) | |
1095 | (clobber (reg:CC 34))] | |
1096 | "" | |
1097 | "%0 = %2 - %1;\\n\\tcc = ac0;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %3 - %H1;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:" | |
b03149e1 JZ |
1098 | [(set_attr "length" "14") |
1099 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
1100 | |
1101 | ;; Combined shift/add instructions | |
1102 | ||
1103 | (define_insn "" | |
1104 | [(set (match_operand:SI 0 "register_operand" "=a,d") | |
1105 | (ashift:SI (plus:SI (match_operand:SI 1 "register_operand" "%0,0") | |
1106 | (match_operand:SI 2 "register_operand" "a,d")) | |
1107 | (match_operand:SI 3 "pos_scale_operand" "P1P2,P1P2")))] | |
1108 | "" | |
1109 | "%0 = (%0 + %2) << %3;" /* "shadd %0,%2,%3;" */ | |
1110 | [(set_attr "type" "alu0")]) | |
1111 | ||
1112 | (define_insn "" | |
1113 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1114 | (plus:SI (match_operand:SI 1 "register_operand" "a") | |
1115 | (mult:SI (match_operand:SI 2 "register_operand" "a") | |
1116 | (match_operand:SI 3 "scale_by_operand" "i"))))] | |
1117 | "" | |
1118 | "%0 = %1 + (%2 << %X3);" | |
1119 | [(set_attr "type" "alu0")]) | |
1120 | ||
1121 | (define_insn "" | |
1122 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1123 | (plus:SI (match_operand:SI 1 "register_operand" "a") | |
1124 | (ashift:SI (match_operand:SI 2 "register_operand" "a") | |
1125 | (match_operand:SI 3 "pos_scale_operand" "i"))))] | |
1126 | "" | |
1127 | "%0 = %1 + (%2 << %3);" | |
1128 | [(set_attr "type" "alu0")]) | |
1129 | ||
1130 | (define_insn "" | |
1131 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1132 | (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "a") | |
1133 | (match_operand:SI 2 "scale_by_operand" "i")) | |
1134 | (match_operand:SI 3 "register_operand" "a")))] | |
1135 | "" | |
1136 | "%0 = %3 + (%1 << %X2);" | |
1137 | [(set_attr "type" "alu0")]) | |
1138 | ||
1139 | (define_insn "" | |
1140 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1141 | (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "a") | |
1142 | (match_operand:SI 2 "pos_scale_operand" "i")) | |
1143 | (match_operand:SI 3 "register_operand" "a")))] | |
1144 | "" | |
1145 | "%0 = %3 + (%1 << %2);" | |
1146 | [(set_attr "type" "alu0")]) | |
1147 | ||
1148 | (define_insn "mulhisi3" | |
1149 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1150 | (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%d")) | |
1151 | (sign_extend:SI (match_operand:HI 2 "register_operand" "d"))))] | |
1152 | "" | |
bbbc206e | 1153 | "%0 = %h1 * %h2 (IS)%!" |
0d4a78eb BS |
1154 | [(set_attr "type" "dsp32")]) |
1155 | ||
1156 | (define_insn "umulhisi3" | |
1157 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1158 | (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%d")) | |
1159 | (zero_extend:SI (match_operand:HI 2 "register_operand" "d"))))] | |
1160 | "" | |
bbbc206e | 1161 | "%0 = %h1 * %h2 (FU)%!" |
0d4a78eb BS |
1162 | [(set_attr "type" "dsp32")]) |
1163 | ||
8b44057d BS |
1164 | (define_insn "usmulhisi3" |
1165 | [(set (match_operand:SI 0 "register_operand" "=W") | |
1166 | (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "W")) | |
1167 | (sign_extend:SI (match_operand:HI 2 "register_operand" "W"))))] | |
1168 | "" | |
bbbc206e | 1169 | "%0 = %h2 * %h1 (IS,M)%!" |
8b44057d BS |
1170 | [(set_attr "type" "dsp32")]) |
1171 | ||
0d4a78eb BS |
1172 | ;; The processor also supports ireg += mreg or ireg -= mreg, but these |
1173 | ;; are unusable if we don't ensure that the corresponding lreg is zero. | |
1174 | ;; The same applies to the add/subtract constant versions involving | |
1175 | ;; iregs | |
1176 | ||
1177 | (define_insn "addsi3" | |
1178 | [(set (match_operand:SI 0 "register_operand" "=ad,a,d") | |
1179 | (plus:SI (match_operand:SI 1 "register_operand" "%0, a,d") | |
1180 | (match_operand:SI 2 "reg_or_7bit_operand" "Ks7, a,d")))] | |
1181 | "" | |
1182 | "@ | |
1183 | %0 += %2; | |
1184 | %0 = %1 + %2; | |
1185 | %0 = %1 + %2;" | |
1186 | [(set_attr "type" "alu0") | |
1187 | (set_attr "length" "2,2,2")]) | |
1188 | ||
75d8b2d0 BS |
1189 | (define_insn "ssaddsi3" |
1190 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1191 | (ss_plus:SI (match_operand:SI 1 "register_operand" "d") | |
1192 | (match_operand:SI 2 "register_operand" "d")))] | |
1193 | "" | |
bbbc206e | 1194 | "%0 = %1 + %2 (S)%!" |
75d8b2d0 BS |
1195 | [(set_attr "type" "dsp32")]) |
1196 | ||
d4e85050 | 1197 | (define_insn "subsi3" |
0d4a78eb BS |
1198 | [(set (match_operand:SI 0 "register_operand" "=da,d,a") |
1199 | (minus:SI (match_operand:SI 1 "register_operand" "0,d,0") | |
d4e85050 BS |
1200 | (match_operand:SI 2 "reg_or_neg7bit_operand" "KN7,d,a")))] |
1201 | "" | |
0d4a78eb BS |
1202 | { |
1203 | static const char *const strings_subsi3[] = { | |
1204 | "%0 += -%2;", | |
1205 | "%0 = %1 - %2;", | |
1206 | "%0 -= %2;", | |
1207 | }; | |
1208 | ||
1209 | if (CONSTANT_P (operands[2]) && INTVAL (operands[2]) < 0) { | |
1210 | rtx tmp_op = operands[2]; | |
1211 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
1212 | output_asm_insn ("%0 += %2;", operands); | |
1213 | operands[2] = tmp_op; | |
1214 | return ""; | |
1215 | } | |
1216 | ||
1217 | return strings_subsi3[which_alternative]; | |
1218 | } | |
1219 | [(set_attr "type" "alu0")]) | |
1220 | ||
75d8b2d0 BS |
1221 | (define_insn "sssubsi3" |
1222 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1223 | (ss_minus:SI (match_operand:SI 1 "register_operand" "d") | |
1224 | (match_operand:SI 2 "register_operand" "d")))] | |
1225 | "" | |
bbbc206e | 1226 | "%0 = %1 - %2 (S)%!" |
75d8b2d0 BS |
1227 | [(set_attr "type" "dsp32")]) |
1228 | ||
0d4a78eb BS |
1229 | ;; Bit test instructions |
1230 | ||
1231 | (define_insn "*not_bittst" | |
4729dc92 | 1232 | [(set (match_operand:BI 0 "register_operand" "=C") |
0d4a78eb BS |
1233 | (eq:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d") |
1234 | (const_int 1) | |
1235 | (match_operand:SI 2 "immediate_operand" "Ku5")) | |
1236 | (const_int 0)))] | |
1237 | "" | |
1238 | "cc = !BITTST (%1,%2);" | |
1239 | [(set_attr "type" "alu0")]) | |
1240 | ||
1241 | (define_insn "*bittst" | |
4729dc92 | 1242 | [(set (match_operand:BI 0 "register_operand" "=C") |
0d4a78eb BS |
1243 | (ne:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d") |
1244 | (const_int 1) | |
1245 | (match_operand:SI 2 "immediate_operand" "Ku5")) | |
1246 | (const_int 0)))] | |
1247 | "" | |
1248 | "cc = BITTST (%1,%2);" | |
1249 | [(set_attr "type" "alu0")]) | |
1250 | ||
1251 | (define_insn_and_split "*bit_extract" | |
1252 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1253 | (zero_extract:SI (match_operand:SI 1 "register_operand" "d") | |
1254 | (const_int 1) | |
1255 | (match_operand:SI 2 "immediate_operand" "Ku5"))) | |
1256 | (clobber (reg:BI REG_CC))] | |
1257 | "" | |
1258 | "#" | |
1259 | "" | |
1260 | [(set (reg:BI REG_CC) | |
1261 | (ne:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2)) | |
1262 | (const_int 0))) | |
1263 | (set (match_dup 0) | |
1264 | (ne:SI (reg:BI REG_CC) (const_int 0)))]) | |
1265 | ||
1266 | (define_insn_and_split "*not_bit_extract" | |
1267 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1268 | (zero_extract:SI (not:SI (match_operand:SI 1 "register_operand" "d")) | |
1269 | (const_int 1) | |
1270 | (match_operand:SI 2 "immediate_operand" "Ku5"))) | |
1271 | (clobber (reg:BI REG_CC))] | |
1272 | "" | |
1273 | "#" | |
1274 | "" | |
1275 | [(set (reg:BI REG_CC) | |
1276 | (eq:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2)) | |
1277 | (const_int 0))) | |
1278 | (set (match_dup 0) | |
1279 | (ne:SI (reg:BI REG_CC) (const_int 0)))]) | |
1280 | ||
1281 | (define_insn "*andsi_insn" | |
1282 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") | |
1283 | (and:SI (match_operand:SI 1 "register_operand" "%0,d,d,d") | |
1284 | (match_operand:SI 2 "rhs_andsi3_operand" "L,M1,M2,d")))] | |
1285 | "" | |
1286 | "@ | |
1287 | BITCLR (%0,%Y2); | |
1288 | %0 = %T1 (Z); | |
1289 | %0 = %h1 (Z); | |
1290 | %0 = %1 & %2;" | |
1291 | [(set_attr "type" "alu0")]) | |
1292 | ||
1293 | (define_expand "andsi3" | |
1294 | [(set (match_operand:SI 0 "register_operand" "") | |
1295 | (and:SI (match_operand:SI 1 "register_operand" "") | |
1296 | (match_operand:SI 2 "general_operand" "")))] | |
1297 | "" | |
1298 | { | |
1299 | if (highbits_operand (operands[2], SImode)) | |
1300 | { | |
1301 | operands[2] = GEN_INT (exact_log2 (-INTVAL (operands[2]))); | |
1302 | emit_insn (gen_ashrsi3 (operands[0], operands[1], operands[2])); | |
1303 | emit_insn (gen_ashlsi3 (operands[0], operands[0], operands[2])); | |
1304 | DONE; | |
1305 | } | |
1306 | if (! rhs_andsi3_operand (operands[2], SImode)) | |
1307 | operands[2] = force_reg (SImode, operands[2]); | |
1308 | }) | |
1309 | ||
1310 | (define_insn "iorsi3" | |
1311 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1312 | (ior:SI (match_operand:SI 1 "register_operand" "%0,d") | |
1313 | (match_operand:SI 2 "regorlog2_operand" "J,d")))] | |
1314 | "" | |
1315 | "@ | |
1316 | BITSET (%0, %X2); | |
1317 | %0 = %1 | %2;" | |
1318 | [(set_attr "type" "alu0")]) | |
1319 | ||
1320 | (define_insn "xorsi3" | |
1321 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1322 | (xor:SI (match_operand:SI 1 "register_operand" "%0,d") | |
1323 | (match_operand:SI 2 "regorlog2_operand" "J,d")))] | |
1324 | "" | |
1325 | "@ | |
1326 | BITTGL (%0, %X2); | |
1327 | %0 = %1 ^ %2;" | |
1328 | [(set_attr "type" "alu0")]) | |
1329 | ||
1330 | (define_insn "smaxsi3" | |
1331 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1332 | (smax:SI (match_operand:SI 1 "register_operand" "d") | |
1333 | (match_operand:SI 2 "register_operand" "d")))] | |
1334 | "" | |
bbbc206e | 1335 | "%0 = max(%1,%2)%!" |
0d4a78eb BS |
1336 | [(set_attr "type" "dsp32")]) |
1337 | ||
1338 | (define_insn "sminsi3" | |
1339 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1340 | (smin:SI (match_operand:SI 1 "register_operand" "d") | |
1341 | (match_operand:SI 2 "register_operand" "d")))] | |
1342 | "" | |
bbbc206e | 1343 | "%0 = min(%1,%2)%!" |
0d4a78eb BS |
1344 | [(set_attr "type" "dsp32")]) |
1345 | ||
1346 | (define_insn "abssi2" | |
1347 | [(set (match_operand:SI 0 "register_operand" "=d") | |
75d8b2d0 | 1348 | (abs:SI (match_operand:SI 1 "register_operand" "d")))] |
0d4a78eb | 1349 | "" |
bbbc206e | 1350 | "%0 = abs %1%!" |
0d4a78eb BS |
1351 | [(set_attr "type" "dsp32")]) |
1352 | ||
0d4a78eb BS |
1353 | (define_insn "negsi2" |
1354 | [(set (match_operand:SI 0 "register_operand" "=d") | |
75d8b2d0 | 1355 | (neg:SI (match_operand:SI 1 "register_operand" "d")))] |
0d4a78eb | 1356 | "" |
75d8b2d0 | 1357 | "%0 = -%1;" |
0d4a78eb BS |
1358 | [(set_attr "type" "alu0")]) |
1359 | ||
75d8b2d0 BS |
1360 | (define_insn "ssnegsi2" |
1361 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1362 | (ss_neg:SI (match_operand:SI 1 "register_operand" "d")))] | |
1363 | "" | |
bbbc206e | 1364 | "%0 = -%1 (S)%!" |
75d8b2d0 BS |
1365 | [(set_attr "type" "dsp32")]) |
1366 | ||
0d4a78eb BS |
1367 | (define_insn "one_cmplsi2" |
1368 | [(set (match_operand:SI 0 "register_operand" "=d") | |
75d8b2d0 | 1369 | (not:SI (match_operand:SI 1 "register_operand" "d")))] |
0d4a78eb | 1370 | "" |
75d8b2d0 | 1371 | "%0 = ~%1;" |
0d4a78eb BS |
1372 | [(set_attr "type" "alu0")]) |
1373 | ||
75d8b2d0 BS |
1374 | (define_insn "signbitssi2" |
1375 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1376 | (if_then_else:HI | |
1377 | (lt (match_operand:SI 1 "register_operand" "d") (const_int 0)) | |
1378 | (clz:HI (not:SI (match_dup 1))) | |
1379 | (clz:HI (match_dup 1))))] | |
1380 | "" | |
bbbc206e | 1381 | "%h0 = signbits %1%!" |
75d8b2d0 BS |
1382 | [(set_attr "type" "dsp32")]) |
1383 | ||
1384 | (define_insn "smaxhi3" | |
1385 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1386 | (smax:HI (match_operand:HI 1 "register_operand" "d") | |
1387 | (match_operand:HI 2 "register_operand" "d")))] | |
1388 | "" | |
bbbc206e | 1389 | "%0 = max(%1,%2) (V)%!" |
75d8b2d0 BS |
1390 | [(set_attr "type" "dsp32")]) |
1391 | ||
1392 | (define_insn "sminhi3" | |
1393 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1394 | (smin:HI (match_operand:HI 1 "register_operand" "d") | |
1395 | (match_operand:HI 2 "register_operand" "d")))] | |
1396 | "" | |
bbbc206e | 1397 | "%0 = min(%1,%2) (V)%!" |
75d8b2d0 BS |
1398 | [(set_attr "type" "dsp32")]) |
1399 | ||
1400 | (define_insn "abshi2" | |
1401 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1402 | (abs:HI (match_operand:HI 1 "register_operand" "d")))] | |
1403 | "" | |
bbbc206e | 1404 | "%0 = abs %1 (V)%!" |
75d8b2d0 BS |
1405 | [(set_attr "type" "dsp32")]) |
1406 | ||
1407 | (define_insn "neghi2" | |
1408 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1409 | (neg:HI (match_operand:HI 1 "register_operand" "d")))] | |
1410 | "" | |
1411 | "%0 = -%1;" | |
bbbc206e | 1412 | [(set_attr "type" "alu0")]) |
75d8b2d0 BS |
1413 | |
1414 | (define_insn "ssneghi2" | |
1415 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1416 | (ss_neg:HI (match_operand:HI 1 "register_operand" "d")))] | |
1417 | "" | |
bbbc206e | 1418 | "%0 = -%1 (V)%!" |
75d8b2d0 BS |
1419 | [(set_attr "type" "dsp32")]) |
1420 | ||
1421 | (define_insn "signbitshi2" | |
1422 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1423 | (if_then_else:HI | |
1424 | (lt (match_operand:HI 1 "register_operand" "d") (const_int 0)) | |
1425 | (clz:HI (not:HI (match_dup 1))) | |
1426 | (clz:HI (match_dup 1))))] | |
1427 | "" | |
bbbc206e | 1428 | "%h0 = signbits %h1%!" |
75d8b2d0 BS |
1429 | [(set_attr "type" "dsp32")]) |
1430 | ||
0d4a78eb BS |
1431 | (define_insn "mulsi3" |
1432 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1433 | (mult:SI (match_operand:SI 1 "register_operand" "%0") | |
1434 | (match_operand:SI 2 "register_operand" "d")))] | |
1435 | "" | |
75d8b2d0 | 1436 | "%0 *= %2;" |
0d4a78eb BS |
1437 | [(set_attr "type" "mult")]) |
1438 | ||
01e7cd6e BS |
1439 | (define_expand "umulsi3_highpart" |
1440 | [(set (match_operand:SI 0 "register_operand" "") | |
1441 | (truncate:SI | |
1442 | (lshiftrt:DI | |
1443 | (mult:DI (zero_extend:DI | |
1444 | (match_operand:SI 1 "nonimmediate_operand" "")) | |
1445 | (zero_extend:DI | |
1446 | (match_operand:SI 2 "register_operand" ""))) | |
1447 | (const_int 32))))] | |
1448 | "" | |
1449 | { | |
1450 | rtx umulsi3_highpart_libfunc | |
1451 | = init_one_libfunc ("__umulsi3_highpart"); | |
1452 | ||
1453 | emit_library_call_value (umulsi3_highpart_libfunc, | |
1454 | operands[0], LCT_NORMAL, SImode, | |
1455 | 2, operands[1], SImode, operands[2], SImode); | |
1456 | DONE; | |
1457 | }) | |
1458 | ||
1459 | (define_expand "smulsi3_highpart" | |
1460 | [(set (match_operand:SI 0 "register_operand" "") | |
1461 | (truncate:SI | |
1462 | (lshiftrt:DI | |
1463 | (mult:DI (sign_extend:DI | |
1464 | (match_operand:SI 1 "nonimmediate_operand" "")) | |
1465 | (sign_extend:DI | |
1466 | (match_operand:SI 2 "register_operand" ""))) | |
1467 | (const_int 32))))] | |
1468 | "" | |
1469 | { | |
1470 | rtx smulsi3_highpart_libfunc | |
1471 | = init_one_libfunc ("__smulsi3_highpart"); | |
1472 | ||
1473 | emit_library_call_value (smulsi3_highpart_libfunc, | |
1474 | operands[0], LCT_NORMAL, SImode, | |
1475 | 2, operands[1], SImode, operands[2], SImode); | |
1476 | DONE; | |
1477 | }) | |
1478 | ||
0d4a78eb BS |
1479 | (define_expand "ashlsi3" |
1480 | [(set (match_operand:SI 0 "register_operand" "") | |
1481 | (ashift:SI (match_operand:SI 1 "register_operand" "") | |
1482 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
1483 | "" | |
1484 | { | |
1485 | if (GET_CODE (operands[2]) == CONST_INT | |
1486 | && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) | |
1487 | { | |
1488 | emit_insn (gen_movsi (operands[0], const0_rtx)); | |
1489 | DONE; | |
1490 | } | |
1491 | }) | |
1492 | ||
1493 | (define_insn_and_split "*ashlsi3_insn" | |
bbbc206e BS |
1494 | [(set (match_operand:SI 0 "register_operand" "=d,d,a,a,a") |
1495 | (ashift:SI (match_operand:SI 1 "register_operand" "0,d,a,a,a") | |
1496 | (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5,P1,P2,?P3P4")))] | |
0d4a78eb BS |
1497 | "" |
1498 | "@ | |
1499 | %0 <<= %2; | |
bbbc206e | 1500 | %0 = %1 << %2%! |
0d4a78eb BS |
1501 | %0 = %1 + %1; |
1502 | %0 = %1 << %2; | |
1503 | #" | |
1504 | "PREG_P (operands[0]) && INTVAL (operands[2]) > 2" | |
1505 | [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 2))) | |
1506 | (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))] | |
1507 | "operands[3] = GEN_INT (INTVAL (operands[2]) - 2);" | |
bbbc206e | 1508 | [(set_attr "type" "shft,dsp32,shft,shft,*")]) |
0d4a78eb BS |
1509 | |
1510 | (define_insn "ashrsi3" | |
bbbc206e BS |
1511 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
1512 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d") | |
1513 | (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5")))] | |
0d4a78eb | 1514 | "" |
bbbc206e BS |
1515 | "@ |
1516 | %0 >>>= %2; | |
1517 | %0 = %1 >>> %2%!" | |
1518 | [(set_attr "type" "shft,dsp32")]) | |
0d4a78eb | 1519 | |
97130915 BS |
1520 | (define_insn "rotl16" |
1521 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1522 | (rotate:SI (match_operand:SI 1 "register_operand" "d") | |
1523 | (const_int 16)))] | |
1524 | "" | |
1525 | "%0 = PACK (%h1, %d1)%!" | |
1526 | [(set_attr "type" "dsp32")]) | |
1527 | ||
1528 | (define_expand "rotlsi3" | |
1529 | [(set (match_operand:SI 0 "register_operand" "") | |
1530 | (rotate:SI (match_operand:SI 1 "register_operand" "") | |
1531 | (match_operand:SI 2 "immediate_operand" "")))] | |
1532 | "" | |
1533 | { | |
1534 | if (INTVAL (operands[2]) != 16) | |
1535 | FAIL; | |
1536 | }) | |
1537 | ||
1538 | (define_expand "rotrsi3" | |
1539 | [(set (match_operand:SI 0 "register_operand" "") | |
1540 | (rotatert:SI (match_operand:SI 1 "register_operand" "") | |
1541 | (match_operand:SI 2 "immediate_operand" "")))] | |
1542 | "" | |
1543 | { | |
1544 | if (INTVAL (operands[2]) != 16) | |
1545 | FAIL; | |
1546 | emit_insn (gen_rotl16 (operands[0], operands[1])); | |
1547 | DONE; | |
1548 | }) | |
1549 | ||
1550 | ||
49373252 BS |
1551 | (define_insn "ror_one" |
1552 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1553 | (ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") (const_int 1)) | |
1554 | (ashift:SI (zero_extend:SI (reg:BI REG_CC)) (const_int 31)))) | |
1555 | (set (reg:BI REG_CC) | |
1556 | (zero_extract:BI (match_dup 1) (const_int 1) (const_int 0)))] | |
1557 | "" | |
bbbc206e BS |
1558 | "%0 = ROT %1 BY -1%!" |
1559 | [(set_attr "type" "dsp32")]) | |
49373252 BS |
1560 | |
1561 | (define_insn "rol_one" | |
1562 | [(set (match_operand:SI 0 "register_operand" "+d") | |
1563 | (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") (const_int 1)) | |
1564 | (zero_extend:SI (reg:BI REG_CC)))) | |
1565 | (set (reg:BI REG_CC) | |
1566 | (zero_extract:BI (match_dup 1) (const_int 31) (const_int 0)))] | |
1567 | "" | |
bbbc206e BS |
1568 | "%0 = ROT %1 BY 1%!" |
1569 | [(set_attr "type" "dsp32")]) | |
49373252 BS |
1570 | |
1571 | (define_expand "lshrdi3" | |
1572 | [(set (match_operand:DI 0 "register_operand" "") | |
1573 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
1574 | (match_operand:DI 2 "general_operand" "")))] | |
1575 | "" | |
1576 | { | |
1577 | rtx lo_half[2], hi_half[2]; | |
1578 | ||
1579 | if (operands[2] != const1_rtx) | |
1580 | FAIL; | |
1581 | if (! rtx_equal_p (operands[0], operands[1])) | |
1582 | emit_move_insn (operands[0], operands[1]); | |
1583 | ||
1584 | split_di (operands, 2, lo_half, hi_half); | |
1585 | ||
1586 | emit_move_insn (bfin_cc_rtx, const0_rtx); | |
1587 | emit_insn (gen_ror_one (hi_half[0], hi_half[0])); | |
1588 | emit_insn (gen_ror_one (lo_half[0], lo_half[0])); | |
1589 | DONE; | |
1590 | }) | |
1591 | ||
1592 | (define_expand "ashrdi3" | |
1593 | [(set (match_operand:DI 0 "register_operand" "") | |
1594 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
1595 | (match_operand:DI 2 "general_operand" "")))] | |
1596 | "" | |
1597 | { | |
1598 | rtx lo_half[2], hi_half[2]; | |
1599 | ||
1600 | if (operands[2] != const1_rtx) | |
1601 | FAIL; | |
1602 | if (! rtx_equal_p (operands[0], operands[1])) | |
1603 | emit_move_insn (operands[0], operands[1]); | |
1604 | ||
1605 | split_di (operands, 2, lo_half, hi_half); | |
1606 | ||
1607 | emit_insn (gen_compare_lt (gen_rtx_REG (BImode, REG_CC), | |
1608 | hi_half[1], const0_rtx)); | |
1609 | emit_insn (gen_ror_one (hi_half[0], hi_half[0])); | |
1610 | emit_insn (gen_ror_one (lo_half[0], lo_half[0])); | |
1611 | DONE; | |
1612 | }) | |
1613 | ||
1614 | (define_expand "ashldi3" | |
1615 | [(set (match_operand:DI 0 "register_operand" "") | |
1616 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
1617 | (match_operand:DI 2 "general_operand" "")))] | |
1618 | "" | |
1619 | { | |
1620 | rtx lo_half[2], hi_half[2]; | |
1621 | ||
1622 | if (operands[2] != const1_rtx) | |
1623 | FAIL; | |
1624 | if (! rtx_equal_p (operands[0], operands[1])) | |
1625 | emit_move_insn (operands[0], operands[1]); | |
1626 | ||
1627 | split_di (operands, 2, lo_half, hi_half); | |
1628 | ||
1629 | emit_move_insn (bfin_cc_rtx, const0_rtx); | |
1630 | emit_insn (gen_rol_one (lo_half[0], lo_half[0])); | |
1631 | emit_insn (gen_rol_one (hi_half[0], hi_half[0])); | |
1632 | DONE; | |
1633 | }) | |
1634 | ||
0d4a78eb | 1635 | (define_insn "lshrsi3" |
bbbc206e BS |
1636 | [(set (match_operand:SI 0 "register_operand" "=d,d,a") |
1637 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,d,a") | |
1638 | (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5,P1P2")))] | |
0d4a78eb BS |
1639 | "" |
1640 | "@ | |
1641 | %0 >>= %2; | |
bbbc206e | 1642 | %0 = %1 >> %2%! |
0d4a78eb | 1643 | %0 = %1 >> %2;" |
bbbc206e | 1644 | [(set_attr "type" "shft,dsp32,shft")]) |
0d4a78eb BS |
1645 | |
1646 | ;; A pattern to reload the equivalent of | |
1647 | ;; (set (Dreg) (plus (FP) (large_constant))) | |
1648 | ;; or | |
1649 | ;; (set (dagreg) (plus (FP) (arbitrary_constant))) | |
1650 | ;; using a scratch register | |
1651 | (define_expand "reload_insi" | |
1652 | [(parallel [(set (match_operand:SI 0 "register_operand" "=w") | |
1653 | (match_operand:SI 1 "fp_plus_const_operand" "")) | |
1654 | (clobber (match_operand:SI 2 "register_operand" "=&a"))])] | |
1655 | "" | |
1656 | { | |
1657 | rtx fp_op = XEXP (operands[1], 0); | |
1658 | rtx const_op = XEXP (operands[1], 1); | |
1659 | rtx primary = operands[0]; | |
1660 | rtx scratch = operands[2]; | |
1661 | ||
1662 | emit_move_insn (scratch, const_op); | |
1663 | emit_insn (gen_addsi3 (scratch, scratch, fp_op)); | |
1664 | emit_move_insn (primary, scratch); | |
1665 | DONE; | |
1666 | }) | |
1667 | ||
1668 | ;; Jump instructions | |
1669 | ||
1670 | (define_insn "jump" | |
1671 | [(set (pc) | |
1672 | (label_ref (match_operand 0 "" "")))] | |
1673 | "" | |
1674 | { | |
1675 | if (get_attr_length (insn) == 2) | |
1676 | return "jump.s %0;"; | |
1677 | else | |
1678 | return "jump.l %0;"; | |
1679 | } | |
1680 | [(set_attr "type" "br")]) | |
1681 | ||
1682 | (define_insn "indirect_jump" | |
1683 | [(set (pc) | |
1684 | (match_operand:SI 0 "register_operand" "a"))] | |
1685 | "" | |
1686 | "jump (%0);" | |
1687 | [(set_attr "type" "misc")]) | |
1688 | ||
1689 | (define_expand "tablejump" | |
1690 | [(parallel [(set (pc) (match_operand:SI 0 "register_operand" "a")) | |
1691 | (use (label_ref (match_operand 1 "" "")))])] | |
1692 | "" | |
1693 | { | |
1694 | /* In PIC mode, the table entries are stored PC relative. | |
1695 | Convert the relative address to an absolute address. */ | |
1696 | if (flag_pic) | |
1697 | { | |
1698 | rtx op1 = gen_rtx_LABEL_REF (Pmode, operands[1]); | |
1699 | ||
1700 | operands[0] = expand_simple_binop (Pmode, PLUS, operands[0], | |
1701 | op1, NULL_RTX, 0, OPTAB_DIRECT); | |
1702 | } | |
1703 | }) | |
1704 | ||
1705 | (define_insn "*tablejump_internal" | |
1706 | [(set (pc) (match_operand:SI 0 "register_operand" "a")) | |
1707 | (use (label_ref (match_operand 1 "" "")))] | |
1708 | "" | |
1709 | "jump (%0);" | |
1710 | [(set_attr "type" "misc")]) | |
1711 | ||
b03149e1 JZ |
1712 | ;; Hardware loop |
1713 | ||
1714 | ; operand 0 is the loop count pseudo register | |
1715 | ; operand 1 is the number of loop iterations or 0 if it is unknown | |
1716 | ; operand 2 is the maximum number of loop iterations | |
1717 | ; operand 3 is the number of levels of enclosed loops | |
1718 | ; operand 4 is the label to jump to at the top of the loop | |
1719 | (define_expand "doloop_end" | |
1720 | [(parallel [(set (pc) (if_then_else | |
1721 | (ne (match_operand:SI 0 "" "") | |
1722 | (const_int 1)) | |
1723 | (label_ref (match_operand 4 "" "")) | |
1724 | (pc))) | |
1725 | (set (match_dup 0) | |
1726 | (plus:SI (match_dup 0) | |
1727 | (const_int -1))) | |
1728 | (unspec [(const_int 0)] UNSPEC_LSETUP_END) | |
1729 | (clobber (match_scratch:SI 5 ""))])] | |
1730 | "" | |
0a8f8c45 | 1731 | { |
9b02a95e BS |
1732 | /* The loop optimizer doesn't check the predicates... */ |
1733 | if (GET_MODE (operands[0]) != SImode) | |
1734 | FAIL; | |
0a8f8c45 BS |
1735 | /* Due to limitations in the hardware (an initial loop count of 0 |
1736 | does not loop 2^32 times) we must avoid to generate a hardware | |
1737 | loops when we cannot rule out this case. */ | |
0a8f8c45 BS |
1738 | if (!flag_unsafe_loop_optimizations |
1739 | && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 0xFFFFFFFF) | |
1740 | FAIL; | |
1741 | bfin_hardware_loop (); | |
1742 | }) | |
b03149e1 JZ |
1743 | |
1744 | (define_insn "loop_end" | |
1745 | [(set (pc) | |
a9c46998 | 1746 | (if_then_else (ne (match_operand:SI 0 "nonimmediate_operand" "+a*d,*b*v*f,m") |
b03149e1 JZ |
1747 | (const_int 1)) |
1748 | (label_ref (match_operand 1 "" "")) | |
1749 | (pc))) | |
1750 | (set (match_dup 0) | |
1751 | (plus (match_dup 0) | |
1752 | (const_int -1))) | |
1753 | (unspec [(const_int 0)] UNSPEC_LSETUP_END) | |
1754 | (clobber (match_scratch:SI 2 "=X,&r,&r"))] | |
1755 | "" | |
1756 | "@ | |
1757 | /* loop end %0 %l1 */ | |
1758 | # | |
1759 | #" | |
1760 | [(set_attr "length" "6,10,14")]) | |
1761 | ||
1762 | (define_split | |
1763 | [(set (pc) | |
1764 | (if_then_else (ne (match_operand:SI 0 "nondp_reg_or_memory_operand" "") | |
1765 | (const_int 1)) | |
1766 | (label_ref (match_operand 1 "" "")) | |
1767 | (pc))) | |
1768 | (set (match_dup 0) | |
1769 | (plus (match_dup 0) | |
1770 | (const_int -1))) | |
1771 | (unspec [(const_int 0)] UNSPEC_LSETUP_END) | |
1772 | (clobber (match_scratch:SI 2 "=&r"))] | |
1773 | "reload_completed" | |
1774 | [(set (match_dup 2) (match_dup 0)) | |
1775 | (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
1776 | (set (match_dup 0) (match_dup 2)) | |
1777 | (set (reg:BI REG_CC) (eq:BI (match_dup 2) (const_int 0))) | |
1778 | (set (pc) | |
1779 | (if_then_else (eq (reg:BI REG_CC) | |
1780 | (const_int 0)) | |
1781 | (label_ref (match_dup 1)) | |
1782 | (pc)))] | |
1783 | "") | |
1784 | ||
1785 | (define_insn "lsetup_with_autoinit" | |
1786 | [(set (match_operand:SI 0 "lt_register_operand" "=t") | |
1787 | (label_ref (match_operand 1 "" ""))) | |
a9c46998 | 1788 | (set (match_operand:SI 2 "lb_register_operand" "=u") |
b03149e1 JZ |
1789 | (label_ref (match_operand 3 "" ""))) |
1790 | (set (match_operand:SI 4 "lc_register_operand" "=k") | |
1791 | (match_operand:SI 5 "register_operand" "a"))] | |
1792 | "" | |
1793 | "LSETUP (%1, %3) %4 = %5;" | |
1794 | [(set_attr "length" "4")]) | |
1795 | ||
1796 | (define_insn "lsetup_without_autoinit" | |
1797 | [(set (match_operand:SI 0 "lt_register_operand" "=t") | |
1798 | (label_ref (match_operand 1 "" ""))) | |
a9c46998 | 1799 | (set (match_operand:SI 2 "lb_register_operand" "=u") |
b03149e1 JZ |
1800 | (label_ref (match_operand 3 "" ""))) |
1801 | (use (match_operand:SI 4 "lc_register_operand" "k"))] | |
1802 | "" | |
1803 | "LSETUP (%1, %3) %4;" | |
1804 | [(set_attr "length" "4")]) | |
1805 | ||
0d4a78eb BS |
1806 | ;; Call instructions.. |
1807 | ||
6614f9f5 BS |
1808 | ;; The explicit MEM inside the UNSPEC prevents the compiler from moving |
1809 | ;; the load before a branch after a NULL test, or before a store that | |
1810 | ;; initializes a function descriptor. | |
1811 | ||
1812 | (define_insn_and_split "load_funcdescsi" | |
1813 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1814 | (unspec_volatile:SI [(mem:SI (match_operand:SI 1 "address_operand" "p"))] | |
1815 | UNSPEC_VOLATILE_LOAD_FUNCDESC))] | |
1816 | "" | |
1817 | "#" | |
1818 | "reload_completed" | |
1819 | [(set (match_dup 0) (mem:SI (match_dup 1)))]) | |
1820 | ||
0d4a78eb | 1821 | (define_expand "call" |
6d459e2b BS |
1822 | [(parallel [(call (match_operand:SI 0 "" "") |
1823 | (match_operand 1 "" "")) | |
1824 | (use (match_operand 2 "" ""))])] | |
0d4a78eb | 1825 | "" |
6d459e2b BS |
1826 | { |
1827 | bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 0); | |
1828 | DONE; | |
1829 | }) | |
0d4a78eb BS |
1830 | |
1831 | (define_expand "sibcall" | |
1832 | [(parallel [(call (match_operand:SI 0 "" "") | |
1833 | (match_operand 1 "" "")) | |
6d459e2b | 1834 | (use (match_operand 2 "" "")) |
0d4a78eb BS |
1835 | (return)])] |
1836 | "" | |
6d459e2b BS |
1837 | { |
1838 | bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 1); | |
1839 | DONE; | |
1840 | }) | |
0d4a78eb BS |
1841 | |
1842 | (define_expand "call_value" | |
6d459e2b BS |
1843 | [(parallel [(set (match_operand 0 "register_operand" "") |
1844 | (call (match_operand:SI 1 "" "") | |
1845 | (match_operand 2 "" ""))) | |
1846 | (use (match_operand 3 "" ""))])] | |
0d4a78eb | 1847 | "" |
6d459e2b BS |
1848 | { |
1849 | bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 0); | |
1850 | DONE; | |
1851 | }) | |
0d4a78eb BS |
1852 | |
1853 | (define_expand "sibcall_value" | |
1854 | [(parallel [(set (match_operand 0 "register_operand" "") | |
1855 | (call (match_operand:SI 1 "" "") | |
1856 | (match_operand 2 "" ""))) | |
6d459e2b | 1857 | (use (match_operand 3 "" "")) |
0d4a78eb BS |
1858 | (return)])] |
1859 | "" | |
6d459e2b BS |
1860 | { |
1861 | bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 1); | |
1862 | DONE; | |
1863 | }) | |
0d4a78eb | 1864 | |
6614f9f5 BS |
1865 | (define_insn "*call_symbol_fdpic" |
1866 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q")) | |
1867 | (match_operand 1 "general_operand" "g")) | |
1868 | (use (match_operand:SI 2 "register_operand" "Z")) | |
1869 | (use (match_operand 3 "" ""))] | |
1870 | "! SIBLING_CALL_P (insn) | |
1871 | && GET_CODE (operands[0]) == SYMBOL_REF | |
1872 | && !bfin_longcall_p (operands[0], INTVAL (operands[3]))" | |
1873 | "call %0;" | |
1874 | [(set_attr "type" "call") | |
1875 | (set_attr "length" "4")]) | |
1876 | ||
1877 | (define_insn "*sibcall_symbol_fdpic" | |
1878 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q")) | |
1879 | (match_operand 1 "general_operand" "g")) | |
1880 | (use (match_operand:SI 2 "register_operand" "Z")) | |
1881 | (use (match_operand 3 "" "")) | |
1882 | (return)] | |
1883 | "SIBLING_CALL_P (insn) | |
1884 | && GET_CODE (operands[0]) == SYMBOL_REF | |
1885 | && !bfin_longcall_p (operands[0], INTVAL (operands[3]))" | |
1886 | "jump.l %0;" | |
1887 | [(set_attr "type" "br") | |
1888 | (set_attr "length" "4")]) | |
1889 | ||
1890 | (define_insn "*call_value_symbol_fdpic" | |
1891 | [(set (match_operand 0 "register_operand" "=d") | |
1892 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q")) | |
1893 | (match_operand 2 "general_operand" "g"))) | |
1894 | (use (match_operand:SI 3 "register_operand" "Z")) | |
1895 | (use (match_operand 4 "" ""))] | |
1896 | "! SIBLING_CALL_P (insn) | |
1897 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1898 | && !bfin_longcall_p (operands[1], INTVAL (operands[4]))" | |
1899 | "call %1;" | |
1900 | [(set_attr "type" "call") | |
1901 | (set_attr "length" "4")]) | |
1902 | ||
1903 | (define_insn "*sibcall_value_symbol_fdpic" | |
1904 | [(set (match_operand 0 "register_operand" "=d") | |
1905 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q")) | |
1906 | (match_operand 2 "general_operand" "g"))) | |
1907 | (use (match_operand:SI 3 "register_operand" "Z")) | |
1908 | (use (match_operand 4 "" "")) | |
1909 | (return)] | |
1910 | "SIBLING_CALL_P (insn) | |
1911 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1912 | && !bfin_longcall_p (operands[1], INTVAL (operands[4]))" | |
1913 | "jump.l %1;" | |
1914 | [(set_attr "type" "br") | |
1915 | (set_attr "length" "4")]) | |
1916 | ||
1917 | (define_insn "*call_insn_fdpic" | |
1918 | [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y")) | |
1919 | (match_operand 1 "general_operand" "g")) | |
1920 | (use (match_operand:SI 2 "register_operand" "Z")) | |
1921 | (use (match_operand 3 "" ""))] | |
1922 | "! SIBLING_CALL_P (insn)" | |
1923 | "call (%0);" | |
1924 | [(set_attr "type" "call") | |
1925 | (set_attr "length" "2")]) | |
1926 | ||
1927 | (define_insn "*sibcall_insn_fdpic" | |
1928 | [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y")) | |
1929 | (match_operand 1 "general_operand" "g")) | |
1930 | (use (match_operand:SI 2 "register_operand" "Z")) | |
1931 | (use (match_operand 3 "" "")) | |
1932 | (return)] | |
1933 | "SIBLING_CALL_P (insn)" | |
1934 | "jump (%0);" | |
1935 | [(set_attr "type" "br") | |
1936 | (set_attr "length" "2")]) | |
1937 | ||
1938 | (define_insn "*call_value_insn_fdpic" | |
1939 | [(set (match_operand 0 "register_operand" "=d") | |
1940 | (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y")) | |
1941 | (match_operand 2 "general_operand" "g"))) | |
1942 | (use (match_operand:SI 3 "register_operand" "Z")) | |
1943 | (use (match_operand 4 "" ""))] | |
1944 | "! SIBLING_CALL_P (insn)" | |
1945 | "call (%1);" | |
1946 | [(set_attr "type" "call") | |
1947 | (set_attr "length" "2")]) | |
1948 | ||
1949 | (define_insn "*sibcall_value_insn_fdpic" | |
1950 | [(set (match_operand 0 "register_operand" "=d") | |
1951 | (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y")) | |
1952 | (match_operand 2 "general_operand" "g"))) | |
1953 | (use (match_operand:SI 3 "register_operand" "Z")) | |
1954 | (use (match_operand 4 "" "")) | |
1955 | (return)] | |
1956 | "SIBLING_CALL_P (insn)" | |
1957 | "jump (%1);" | |
1958 | [(set_attr "type" "br") | |
1959 | (set_attr "length" "2")]) | |
1960 | ||
6d459e2b BS |
1961 | (define_insn "*call_symbol" |
1962 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q")) | |
1963 | (match_operand 1 "general_operand" "g")) | |
1964 | (use (match_operand 2 "" ""))] | |
0d4a78eb | 1965 | "! SIBLING_CALL_P (insn) |
93147119 | 1966 | && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY) |
6d459e2b BS |
1967 | && GET_CODE (operands[0]) == SYMBOL_REF |
1968 | && !bfin_longcall_p (operands[0], INTVAL (operands[2]))" | |
96c30d2a | 1969 | "call %0;" |
0d4a78eb | 1970 | [(set_attr "type" "call") |
6d459e2b | 1971 | (set_attr "length" "4")]) |
0d4a78eb | 1972 | |
6d459e2b BS |
1973 | (define_insn "*sibcall_symbol" |
1974 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q")) | |
1975 | (match_operand 1 "general_operand" "g")) | |
1976 | (use (match_operand 2 "" "")) | |
0d4a78eb BS |
1977 | (return)] |
1978 | "SIBLING_CALL_P (insn) | |
93147119 | 1979 | && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY) |
6d459e2b BS |
1980 | && GET_CODE (operands[0]) == SYMBOL_REF |
1981 | && !bfin_longcall_p (operands[0], INTVAL (operands[2]))" | |
96c30d2a | 1982 | "jump.l %0;" |
0d4a78eb | 1983 | [(set_attr "type" "br") |
6d459e2b | 1984 | (set_attr "length" "4")]) |
0d4a78eb | 1985 | |
6d459e2b BS |
1986 | (define_insn "*call_value_symbol" |
1987 | [(set (match_operand 0 "register_operand" "=d") | |
1988 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q")) | |
1989 | (match_operand 2 "general_operand" "g"))) | |
1990 | (use (match_operand 3 "" ""))] | |
0d4a78eb | 1991 | "! SIBLING_CALL_P (insn) |
93147119 | 1992 | && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY) |
6d459e2b BS |
1993 | && GET_CODE (operands[1]) == SYMBOL_REF |
1994 | && !bfin_longcall_p (operands[1], INTVAL (operands[3]))" | |
96c30d2a | 1995 | "call %1;" |
0d4a78eb | 1996 | [(set_attr "type" "call") |
6d459e2b | 1997 | (set_attr "length" "4")]) |
0d4a78eb | 1998 | |
6d459e2b BS |
1999 | (define_insn "*sibcall_value_symbol" |
2000 | [(set (match_operand 0 "register_operand" "=d") | |
2001 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q")) | |
2002 | (match_operand 2 "general_operand" "g"))) | |
2003 | (use (match_operand 3 "" "")) | |
0d4a78eb BS |
2004 | (return)] |
2005 | "SIBLING_CALL_P (insn) | |
93147119 | 2006 | && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY) |
6d459e2b BS |
2007 | && GET_CODE (operands[1]) == SYMBOL_REF |
2008 | && !bfin_longcall_p (operands[1], INTVAL (operands[3]))" | |
96c30d2a | 2009 | "jump.l %1;" |
6d459e2b BS |
2010 | [(set_attr "type" "br") |
2011 | (set_attr "length" "4")]) | |
2012 | ||
2013 | (define_insn "*call_insn" | |
2014 | [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "a")) | |
2015 | (match_operand 1 "general_operand" "g")) | |
2016 | (use (match_operand 2 "" ""))] | |
2017 | "! SIBLING_CALL_P (insn)" | |
2018 | "call (%0);" | |
2019 | [(set_attr "type" "call") | |
2020 | (set_attr "length" "2")]) | |
2021 | ||
2022 | (define_insn "*sibcall_insn" | |
2023 | [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "z")) | |
2024 | (match_operand 1 "general_operand" "g")) | |
2025 | (use (match_operand 2 "" "")) | |
2026 | (return)] | |
2027 | "SIBLING_CALL_P (insn)" | |
2028 | "jump (%0);" | |
2029 | [(set_attr "type" "br") | |
2030 | (set_attr "length" "2")]) | |
2031 | ||
2032 | (define_insn "*call_value_insn" | |
2033 | [(set (match_operand 0 "register_operand" "=d") | |
2034 | (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "a")) | |
2035 | (match_operand 2 "general_operand" "g"))) | |
2036 | (use (match_operand 3 "" ""))] | |
2037 | "! SIBLING_CALL_P (insn)" | |
2038 | "call (%1);" | |
2039 | [(set_attr "type" "call") | |
2040 | (set_attr "length" "2")]) | |
2041 | ||
2042 | (define_insn "*sibcall_value_insn" | |
2043 | [(set (match_operand 0 "register_operand" "=d") | |
2044 | (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "z")) | |
2045 | (match_operand 2 "general_operand" "g"))) | |
2046 | (use (match_operand 3 "" "")) | |
2047 | (return)] | |
2048 | "SIBLING_CALL_P (insn)" | |
2049 | "jump (%1);" | |
0d4a78eb | 2050 | [(set_attr "type" "br") |
6d459e2b | 2051 | (set_attr "length" "2")]) |
0d4a78eb BS |
2052 | |
2053 | ;; Block move patterns | |
2054 | ||
2055 | ;; We cheat. This copies one more word than operand 2 indicates. | |
2056 | ||
2057 | (define_insn "rep_movsi" | |
2058 | [(set (match_operand:SI 0 "register_operand" "=&a") | |
2059 | (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0") | |
2060 | (ashift:SI (match_operand:SI 2 "register_operand" "a") | |
2061 | (const_int 2))) | |
2062 | (const_int 4))) | |
2063 | (set (match_operand:SI 1 "register_operand" "=&b") | |
2064 | (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1") | |
2065 | (ashift:SI (match_dup 2) (const_int 2))) | |
2066 | (const_int 4))) | |
2067 | (set (mem:BLK (match_dup 3)) | |
2068 | (mem:BLK (match_dup 4))) | |
2069 | (use (match_dup 2)) | |
b03149e1 JZ |
2070 | (clobber (match_scratch:HI 5 "=&d")) |
2071 | (clobber (reg:SI REG_LT1)) | |
2072 | (clobber (reg:SI REG_LC1)) | |
2073 | (clobber (reg:SI REG_LB1))] | |
0d4a78eb | 2074 | "" |
51a641fd | 2075 | "%5 = [%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || [%3++] = %5 || %5 = [%4++]; [%3++] = %5;" |
0d4a78eb | 2076 | [(set_attr "type" "misc") |
b03149e1 JZ |
2077 | (set_attr "length" "16") |
2078 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb BS |
2079 | |
2080 | (define_insn "rep_movhi" | |
2081 | [(set (match_operand:SI 0 "register_operand" "=&a") | |
2082 | (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0") | |
2083 | (ashift:SI (match_operand:SI 2 "register_operand" "a") | |
2084 | (const_int 1))) | |
2085 | (const_int 2))) | |
2086 | (set (match_operand:SI 1 "register_operand" "=&b") | |
2087 | (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1") | |
2088 | (ashift:SI (match_dup 2) (const_int 1))) | |
2089 | (const_int 2))) | |
2090 | (set (mem:BLK (match_dup 3)) | |
2091 | (mem:BLK (match_dup 4))) | |
2092 | (use (match_dup 2)) | |
b03149e1 JZ |
2093 | (clobber (match_scratch:HI 5 "=&d")) |
2094 | (clobber (reg:SI REG_LT1)) | |
2095 | (clobber (reg:SI REG_LC1)) | |
2096 | (clobber (reg:SI REG_LB1))] | |
0d4a78eb | 2097 | "" |
51a641fd | 2098 | "%h5 = W[%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || W [%3++] = %5 || %h5 = W [%4++]; W [%3++] = %5;" |
0d4a78eb | 2099 | [(set_attr "type" "misc") |
b03149e1 JZ |
2100 | (set_attr "length" "16") |
2101 | (set_attr "seq_insns" "multi")]) | |
0d4a78eb | 2102 | |
144f8315 | 2103 | (define_expand "movmemsi" |
0d4a78eb BS |
2104 | [(match_operand:BLK 0 "general_operand" "") |
2105 | (match_operand:BLK 1 "general_operand" "") | |
2106 | (match_operand:SI 2 "const_int_operand" "") | |
2107 | (match_operand:SI 3 "const_int_operand" "")] | |
2108 | "" | |
2109 | { | |
144f8315 | 2110 | if (bfin_expand_movmem (operands[0], operands[1], operands[2], operands[3])) |
0d4a78eb BS |
2111 | DONE; |
2112 | FAIL; | |
2113 | }) | |
2114 | ||
2115 | ;; Conditional branch patterns | |
2116 | ;; The Blackfin has only few condition codes: eq, lt, lte, ltu, leu | |
2117 | ||
2118 | ;; The only outcome of this pattern is that global variables | |
2119 | ;; bfin_compare_op[01] are set for use in bcond patterns. | |
2120 | ||
2121 | (define_expand "cmpbi" | |
2122 | [(set (cc0) (compare (match_operand:BI 0 "register_operand" "") | |
2123 | (match_operand:BI 1 "immediate_operand" "")))] | |
2124 | "" | |
2125 | { | |
2126 | bfin_compare_op0 = operands[0]; | |
2127 | bfin_compare_op1 = operands[1]; | |
2128 | DONE; | |
2129 | }) | |
2130 | ||
2131 | (define_expand "cmpsi" | |
2132 | [(set (cc0) (compare (match_operand:SI 0 "register_operand" "") | |
7ddcf3d2 | 2133 | (match_operand:SI 1 "reg_or_const_int_operand" "")))] |
0d4a78eb BS |
2134 | "" |
2135 | { | |
2136 | bfin_compare_op0 = operands[0]; | |
2137 | bfin_compare_op1 = operands[1]; | |
2138 | DONE; | |
2139 | }) | |
2140 | ||
49373252 | 2141 | (define_insn "compare_eq" |
4729dc92 | 2142 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2143 | (eq:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2144 | (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] |
0d4a78eb BS |
2145 | "" |
2146 | "cc =%1==%2;" | |
2147 | [(set_attr "type" "compare")]) | |
2148 | ||
49373252 | 2149 | (define_insn "compare_ne" |
4729dc92 | 2150 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2151 | (ne:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2152 | (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] |
0d4a78eb BS |
2153 | "0" |
2154 | "cc =%1!=%2;" | |
2155 | [(set_attr "type" "compare")]) | |
2156 | ||
49373252 | 2157 | (define_insn "compare_lt" |
4729dc92 | 2158 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2159 | (lt:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2160 | (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] |
0d4a78eb BS |
2161 | "" |
2162 | "cc =%1<%2;" | |
2163 | [(set_attr "type" "compare")]) | |
2164 | ||
49373252 | 2165 | (define_insn "compare_le" |
4729dc92 | 2166 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2167 | (le:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2168 | (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] |
0d4a78eb BS |
2169 | "" |
2170 | "cc =%1<=%2;" | |
2171 | [(set_attr "type" "compare")]) | |
2172 | ||
49373252 | 2173 | (define_insn "compare_leu" |
4729dc92 | 2174 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2175 | (leu:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2176 | (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))] |
0d4a78eb BS |
2177 | "" |
2178 | "cc =%1<=%2 (iu);" | |
2179 | [(set_attr "type" "compare")]) | |
2180 | ||
49373252 | 2181 | (define_insn "compare_ltu" |
4729dc92 | 2182 | [(set (match_operand:BI 0 "register_operand" "=C,C") |
0d4a78eb | 2183 | (ltu:BI (match_operand:SI 1 "register_operand" "d,a") |
7ddcf3d2 | 2184 | (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))] |
0d4a78eb BS |
2185 | "" |
2186 | "cc =%1<%2 (iu);" | |
2187 | [(set_attr "type" "compare")]) | |
2188 | ||
2189 | (define_expand "beq" | |
2190 | [(set (match_dup 1) (match_dup 2)) | |
2191 | (set (pc) | |
2192 | (if_then_else (match_dup 3) | |
2193 | (label_ref (match_operand 0 "" "")) | |
2194 | (pc)))] | |
2195 | "" | |
2196 | { | |
2197 | rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1; | |
2198 | operands[1] = bfin_cc_rtx; /* hard register: CC */ | |
2199 | operands[2] = gen_rtx_EQ (BImode, op0, op1); | |
2200 | /* If we have a BImode input, then we already have a compare result, and | |
2201 | do not need to emit another comparison. */ | |
2202 | if (GET_MODE (bfin_compare_op0) == BImode) | |
2203 | { | |
3b9dd769 NS |
2204 | gcc_assert (bfin_compare_op1 == const0_rtx); |
2205 | emit_insn (gen_cbranchbi4 (operands[2], op0, op1, operands[0])); | |
2206 | DONE; | |
0d4a78eb BS |
2207 | } |
2208 | ||
2209 | operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx); | |
2210 | }) | |
2211 | ||
2212 | (define_expand "bne" | |
2213 | [(set (match_dup 1) (match_dup 2)) | |
2214 | (set (pc) | |
2215 | (if_then_else (match_dup 3) | |
2216 | (label_ref (match_operand 0 "" "")) | |
2217 | (pc)))] | |
2218 | "" | |
2219 | { | |
2220 | rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1; | |
2221 | /* If we have a BImode input, then we already have a compare result, and | |
2222 | do not need to emit another comparison. */ | |
2223 | if (GET_MODE (bfin_compare_op0) == BImode) | |
2224 | { | |
3b9dd769 NS |
2225 | rtx cmp = gen_rtx_NE (BImode, op0, op1); |
2226 | ||
2227 | gcc_assert (bfin_compare_op1 == const0_rtx); | |
2228 | emit_insn (gen_cbranchbi4 (cmp, op0, op1, operands[0])); | |
2229 | DONE; | |
0d4a78eb BS |
2230 | } |
2231 | ||
2232 | operands[1] = bfin_cc_rtx; /* hard register: CC */ | |
2233 | operands[2] = gen_rtx_EQ (BImode, op0, op1); | |
2234 | operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx); | |
2235 | }) | |
2236 | ||
2237 | (define_expand "bgt" | |
2238 | [(set (match_dup 1) (match_dup 2)) | |
2239 | (set (pc) | |
2240 | (if_then_else (match_dup 3) | |
2241 | (label_ref (match_operand 0 "" "")) | |
2242 | (pc)))] | |
2243 | "" | |
2244 | { | |
2245 | operands[1] = bfin_cc_rtx; | |
2246 | operands[2] = gen_rtx_LE (BImode, bfin_compare_op0, bfin_compare_op1); | |
2247 | operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx); | |
2248 | }) | |
2249 | ||
2250 | (define_expand "bgtu" | |
2251 | [(set (match_dup 1) (match_dup 2)) | |
2252 | (set (pc) | |
2253 | (if_then_else (match_dup 3) | |
2254 | (label_ref (match_operand 0 "" "")) | |
2255 | (pc)))] | |
2256 | "" | |
2257 | { | |
2258 | operands[1] = bfin_cc_rtx; | |
2259 | operands[2] = gen_rtx_LEU (BImode, bfin_compare_op0, bfin_compare_op1); | |
2260 | operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx); | |
2261 | }) | |
2262 | ||
2263 | (define_expand "blt" | |
2264 | [(set (match_dup 1) (match_dup 2)) | |
2265 | (set (pc) | |
2266 | (if_then_else (match_dup 3) | |
2267 | (label_ref (match_operand 0 "" "")) | |
2268 | (pc)))] | |
2269 | "" | |
2270 | { | |
2271 | operands[1] = bfin_cc_rtx; | |
2272 | operands[2] = gen_rtx_LT (BImode, bfin_compare_op0, bfin_compare_op1); | |
2273 | operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx); | |
2274 | }) | |
2275 | ||
2276 | (define_expand "bltu" | |
2277 | [(set (match_dup 1) (match_dup 2)) | |
2278 | (set (pc) | |
2279 | (if_then_else (match_dup 3) | |
2280 | (label_ref (match_operand 0 "" "")) | |
2281 | (pc)))] | |
2282 | "" | |
2283 | { | |
2284 | operands[1] = bfin_cc_rtx; | |
2285 | operands[2] = gen_rtx_LTU (BImode, bfin_compare_op0, bfin_compare_op1); | |
2286 | operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx); | |
2287 | }) | |
2288 | ||
2289 | ||
2290 | (define_expand "bge" | |
2291 | [(set (match_dup 1) (match_dup 2)) | |
2292 | (set (pc) | |
2293 | (if_then_else (match_dup 3) | |
2294 | (label_ref (match_operand 0 "" "")) | |
2295 | (pc)))] | |
2296 | "" | |
2297 | { | |
2298 | operands[1] = bfin_cc_rtx; | |
2299 | operands[2] = gen_rtx_LT (BImode, bfin_compare_op0, bfin_compare_op1); | |
2300 | operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx); | |
2301 | }) | |
2302 | ||
2303 | (define_expand "bgeu" | |
2304 | [(set (match_dup 1) (match_dup 2)) | |
2305 | (set (pc) | |
2306 | (if_then_else (match_dup 3) | |
2307 | (label_ref (match_operand 0 "" "")) | |
2308 | (pc)))] | |
2309 | "" | |
2310 | { | |
2311 | operands[1] = bfin_cc_rtx; | |
2312 | operands[2] = gen_rtx_LTU (BImode, bfin_compare_op0, bfin_compare_op1); | |
2313 | operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx); | |
2314 | }) | |
2315 | ||
2316 | (define_expand "ble" | |
2317 | [(set (match_dup 1) (match_dup 2)) | |
2318 | (set (pc) | |
2319 | (if_then_else (match_dup 3) | |
2320 | (label_ref (match_operand 0 "" "")) | |
2321 | (pc)))] | |
2322 | "" | |
2323 | { | |
2324 | operands[1] = bfin_cc_rtx; | |
2325 | operands[2] = gen_rtx_LE (BImode, bfin_compare_op0, bfin_compare_op1); | |
2326 | operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx); | |
2327 | }) | |
2328 | ||
2329 | (define_expand "bleu" | |
2330 | [(set (match_dup 1) (match_dup 2)) | |
2331 | (set (pc) | |
2332 | (if_then_else (match_dup 3) | |
2333 | (label_ref (match_operand 0 "" "")) | |
2334 | (pc))) | |
2335 | ] | |
2336 | "" | |
2337 | { | |
2338 | operands[1] = bfin_cc_rtx; | |
2339 | operands[2] = gen_rtx_LEU (BImode, bfin_compare_op0, bfin_compare_op1); | |
2340 | operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx); | |
2341 | }) | |
2342 | ||
2343 | (define_insn "cbranchbi4" | |
2344 | [(set (pc) | |
2345 | (if_then_else | |
2346 | (match_operator 0 "bfin_cbranch_operator" | |
4729dc92 | 2347 | [(match_operand:BI 1 "register_operand" "C") |
0d4a78eb BS |
2348 | (match_operand:BI 2 "immediate_operand" "P0")]) |
2349 | (label_ref (match_operand 3 "" "")) | |
2350 | (pc)))] | |
2351 | "" | |
2352 | { | |
2353 | asm_conditional_branch (insn, operands, 0, 0); | |
2354 | return ""; | |
2355 | } | |
2356 | [(set_attr "type" "brcc")]) | |
2357 | ||
2358 | ;; Special cbranch patterns to deal with the speculative load problem - see | |
2359 | ;; bfin_reorg for details. | |
2360 | ||
2361 | (define_insn "cbranch_predicted_taken" | |
2362 | [(set (pc) | |
2363 | (if_then_else | |
2364 | (match_operator 0 "bfin_cbranch_operator" | |
4729dc92 | 2365 | [(match_operand:BI 1 "register_operand" "C") |
0d4a78eb BS |
2366 | (match_operand:BI 2 "immediate_operand" "P0")]) |
2367 | (label_ref (match_operand 3 "" "")) | |
2368 | (pc))) | |
2369 | (unspec [(const_int 0)] UNSPEC_CBRANCH_TAKEN)] | |
2370 | "" | |
2371 | { | |
2372 | asm_conditional_branch (insn, operands, 0, 1); | |
2373 | return ""; | |
2374 | } | |
2375 | [(set_attr "type" "brcc")]) | |
2376 | ||
2377 | (define_insn "cbranch_with_nops" | |
2378 | [(set (pc) | |
2379 | (if_then_else | |
2380 | (match_operator 0 "bfin_cbranch_operator" | |
4729dc92 | 2381 | [(match_operand:BI 1 "register_operand" "C") |
0d4a78eb BS |
2382 | (match_operand:BI 2 "immediate_operand" "P0")]) |
2383 | (label_ref (match_operand 3 "" "")) | |
2384 | (pc))) | |
2385 | (unspec [(match_operand 4 "immediate_operand" "")] UNSPEC_CBRANCH_NOPS)] | |
2386 | "reload_completed" | |
2387 | { | |
2388 | asm_conditional_branch (insn, operands, INTVAL (operands[4]), 0); | |
2389 | return ""; | |
2390 | } | |
2391 | [(set_attr "type" "brcc") | |
2392 | (set_attr "length" "6")]) | |
2393 | ||
2394 | ;; setcc insns. */ | |
2395 | (define_expand "seq" | |
2396 | [(set (match_dup 1) (eq:BI (match_dup 2) (match_dup 3))) | |
2397 | (set (match_operand:SI 0 "register_operand" "") | |
2398 | (ne:SI (match_dup 1) (const_int 0)))] | |
2399 | "" | |
2400 | { | |
2401 | operands[2] = bfin_compare_op0; | |
2402 | operands[3] = bfin_compare_op1; | |
2403 | operands[1] = bfin_cc_rtx; | |
2404 | }) | |
2405 | ||
2406 | (define_expand "slt" | |
2407 | [(set (match_dup 1) (lt:BI (match_dup 2) (match_dup 3))) | |
2408 | (set (match_operand:SI 0 "register_operand" "") | |
2409 | (ne:SI (match_dup 1) (const_int 0)))] | |
2410 | "" | |
2411 | { | |
2412 | operands[2] = bfin_compare_op0; | |
2413 | operands[3] = bfin_compare_op1; | |
2414 | operands[1] = bfin_cc_rtx; | |
2415 | }) | |
2416 | ||
2417 | (define_expand "sle" | |
2418 | [(set (match_dup 1) (le:BI (match_dup 2) (match_dup 3))) | |
2419 | (set (match_operand:SI 0 "register_operand" "") | |
2420 | (ne:SI (match_dup 1) (const_int 0)))] | |
2421 | "" | |
2422 | { | |
2423 | operands[2] = bfin_compare_op0; | |
2424 | operands[3] = bfin_compare_op1; | |
2425 | operands[1] = bfin_cc_rtx; | |
2426 | }) | |
2427 | ||
2428 | (define_expand "sltu" | |
2429 | [(set (match_dup 1) (ltu:BI (match_dup 2) (match_dup 3))) | |
2430 | (set (match_operand:SI 0 "register_operand" "") | |
2431 | (ne:SI (match_dup 1) (const_int 0)))] | |
2432 | "" | |
2433 | { | |
2434 | operands[2] = bfin_compare_op0; | |
2435 | operands[3] = bfin_compare_op1; | |
2436 | operands[1] = bfin_cc_rtx; | |
2437 | }) | |
2438 | ||
2439 | (define_expand "sleu" | |
2440 | [(set (match_dup 1) (leu:BI (match_dup 2) (match_dup 3))) | |
2441 | (set (match_operand:SI 0 "register_operand" "") | |
2442 | (ne:SI (match_dup 1) (const_int 0)))] | |
2443 | "" | |
2444 | { | |
2445 | operands[2] = bfin_compare_op0; | |
2446 | operands[3] = bfin_compare_op1; | |
2447 | operands[1] = bfin_cc_rtx; | |
2448 | }) | |
2449 | ||
2450 | (define_insn "nop" | |
2451 | [(const_int 0)] | |
2452 | "" | |
2453 | "nop;") | |
2454 | ||
bbbc206e BS |
2455 | (define_insn "mnop" |
2456 | [(unspec [(const_int 0)] UNSPEC_32BIT)] | |
2457 | "" | |
2458 | "mnop%!" | |
2459 | [(set_attr "type" "dsp32")]) | |
2460 | ||
0d4a78eb BS |
2461 | ;;;;;;;;;;;;;;;;;;;; CC2dreg ;;;;;;;;;;;;;;;;;;;;;;;;; |
2462 | (define_insn "movsibi" | |
4729dc92 | 2463 | [(set (match_operand:BI 0 "register_operand" "=C") |
0d4a78eb BS |
2464 | (ne:BI (match_operand:SI 1 "register_operand" "d") |
2465 | (const_int 0)))] | |
2466 | "" | |
2467 | "CC = %1;" | |
2468 | [(set_attr "length" "2")]) | |
2469 | ||
2470 | (define_insn "movbisi" | |
2471 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4729dc92 | 2472 | (ne:SI (match_operand:BI 1 "register_operand" "C") |
0d4a78eb BS |
2473 | (const_int 0)))] |
2474 | "" | |
2475 | "%0 = CC;" | |
2476 | [(set_attr "length" "2")]) | |
2477 | ||
2478 | (define_insn "" | |
4729dc92 BS |
2479 | [(set (match_operand:BI 0 "register_operand" "=C") |
2480 | (eq:BI (match_operand:BI 1 "register_operand" " 0") | |
0d4a78eb BS |
2481 | (const_int 0)))] |
2482 | "" | |
2483 | "%0 = ! %0;" /* NOT CC;" */ | |
2484 | [(set_attr "type" "compare")]) | |
2485 | ||
2486 | ;; Vector and DSP insns | |
2487 | ||
2488 | (define_insn "" | |
2489 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2490 | (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") | |
2491 | (const_int 24)) | |
2492 | (lshiftrt:SI (match_operand:SI 2 "register_operand" "d") | |
2493 | (const_int 8))))] | |
2494 | "" | |
bbbc206e | 2495 | "%0 = ALIGN8(%1, %2)%!" |
0d4a78eb BS |
2496 | [(set_attr "type" "dsp32")]) |
2497 | ||
2498 | (define_insn "" | |
2499 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2500 | (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") | |
2501 | (const_int 16)) | |
2502 | (lshiftrt:SI (match_operand:SI 2 "register_operand" "d") | |
2503 | (const_int 16))))] | |
2504 | "" | |
bbbc206e | 2505 | "%0 = ALIGN16(%1, %2)%!" |
0d4a78eb BS |
2506 | [(set_attr "type" "dsp32")]) |
2507 | ||
2508 | (define_insn "" | |
2509 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2510 | (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") | |
2511 | (const_int 8)) | |
2512 | (lshiftrt:SI (match_operand:SI 2 "register_operand" "d") | |
2513 | (const_int 24))))] | |
2514 | "" | |
bbbc206e | 2515 | "%0 = ALIGN24(%1, %2)%!" |
0d4a78eb BS |
2516 | [(set_attr "type" "dsp32")]) |
2517 | ||
2518 | ;; Prologue and epilogue. | |
2519 | ||
2520 | (define_expand "prologue" | |
2521 | [(const_int 1)] | |
2522 | "" | |
2523 | "bfin_expand_prologue (); DONE;") | |
2524 | ||
2525 | (define_expand "epilogue" | |
2526 | [(const_int 1)] | |
2527 | "" | |
2528 | "bfin_expand_epilogue (1, 0); DONE;") | |
2529 | ||
2530 | (define_expand "sibcall_epilogue" | |
2531 | [(const_int 1)] | |
2532 | "" | |
2533 | "bfin_expand_epilogue (0, 0); DONE;") | |
2534 | ||
2535 | (define_expand "eh_return" | |
2536 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "")] | |
2537 | UNSPEC_VOLATILE_EH_RETURN)] | |
2538 | "" | |
2539 | { | |
2540 | emit_move_insn (EH_RETURN_HANDLER_RTX, operands[0]); | |
1e96b1c3 | 2541 | emit_jump_insn (gen_eh_return_internal ()); |
0d4a78eb | 2542 | emit_barrier (); |
4193ce73 | 2543 | DONE; |
0d4a78eb BS |
2544 | }) |
2545 | ||
2546 | (define_insn_and_split "eh_return_internal" | |
1e96b1c3 JZ |
2547 | [(set (pc) |
2548 | (unspec_volatile [(reg:SI REG_P2)] UNSPEC_VOLATILE_EH_RETURN))] | |
0d4a78eb BS |
2549 | "" |
2550 | "#" | |
2551 | "reload_completed" | |
2552 | [(const_int 1)] | |
2553 | "bfin_expand_epilogue (1, 1); DONE;") | |
2554 | ||
2555 | (define_insn "link" | |
2556 | [(set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -4))) (reg:SI REG_RETS)) | |
2557 | (set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -8))) (reg:SI REG_FP)) | |
2558 | (set (reg:SI REG_FP) | |
2559 | (plus:SI (reg:SI REG_SP) (const_int -8))) | |
2560 | (set (reg:SI REG_SP) | |
2561 | (plus:SI (reg:SI REG_SP) (match_operand:SI 0 "immediate_operand" "i")))] | |
2562 | "" | |
2563 | "LINK %Z0;" | |
2564 | [(set_attr "length" "4")]) | |
2565 | ||
2566 | (define_insn "unlink" | |
2567 | [(set (reg:SI REG_FP) (mem:SI (reg:SI REG_FP))) | |
2568 | (set (reg:SI REG_RETS) (mem:SI (plus:SI (reg:SI REG_FP) (const_int 4)))) | |
2569 | (set (reg:SI REG_SP) (plus:SI (reg:SI REG_FP) (const_int 8)))] | |
2570 | "" | |
2571 | "UNLINK;" | |
2572 | [(set_attr "length" "4")]) | |
2573 | ||
2574 | ;; This pattern is slightly clumsy. The stack adjust must be the final SET in | |
2575 | ;; the pattern, otherwise dwarf2out becomes very confused about which reg goes | |
2576 | ;; where on the stack, since it goes through all elements of the parallel in | |
2577 | ;; sequence. | |
2578 | (define_insn "push_multiple" | |
2579 | [(match_parallel 0 "push_multiple_operation" | |
2580 | [(unspec [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_PUSH_MULTIPLE)])] | |
2581 | "" | |
2582 | { | |
2583 | output_push_multiple (insn, operands); | |
2584 | return ""; | |
2585 | }) | |
2586 | ||
2587 | (define_insn "pop_multiple" | |
2588 | [(match_parallel 0 "pop_multiple_operation" | |
2589 | [(set (reg:SI REG_SP) | |
2590 | (plus:SI (reg:SI REG_SP) (match_operand:SI 1 "immediate_operand" "i")))])] | |
2591 | "" | |
2592 | { | |
2593 | output_pop_multiple (insn, operands); | |
2594 | return ""; | |
2595 | }) | |
2596 | ||
2597 | (define_insn "return_internal" | |
2598 | [(return) | |
2599 | (unspec [(match_operand 0 "immediate_operand" "i")] UNSPEC_RETURN)] | |
2600 | "reload_completed" | |
2601 | { | |
2602 | switch (INTVAL (operands[0])) | |
2603 | { | |
2604 | case EXCPT_HANDLER: | |
2605 | return "rtx;"; | |
2606 | case NMI_HANDLER: | |
2607 | return "rtn;"; | |
2608 | case INTERRUPT_HANDLER: | |
2609 | return "rti;"; | |
2610 | case SUBROUTINE: | |
2611 | return "rts;"; | |
2612 | } | |
2613 | gcc_unreachable (); | |
2614 | }) | |
2615 | ||
5fcead21 BS |
2616 | (define_insn "csync" |
2617 | [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_CSYNC)] | |
2618 | "" | |
2619 | "csync;" | |
3fb192d2 | 2620 | [(set_attr "type" "sync")]) |
5fcead21 BS |
2621 | |
2622 | (define_insn "ssync" | |
2623 | [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_SSYNC)] | |
2624 | "" | |
2625 | "ssync;" | |
3fb192d2 | 2626 | [(set_attr "type" "sync")]) |
5fcead21 | 2627 | |
3d33a056 JZ |
2628 | (define_insn "trap" |
2629 | [(trap_if (const_int 1) (const_int 3))] | |
2630 | "" | |
2631 | "excpt 3;" | |
2632 | [(set_attr "type" "misc") | |
2633 | (set_attr "length" "2")]) | |
2634 | ||
09350e36 BS |
2635 | (define_insn "trapifcc" |
2636 | [(trap_if (reg:BI REG_CC) (const_int 3))] | |
2637 | "" | |
2638 | "if !cc jump 4 (bp); excpt 3;" | |
2639 | [(set_attr "type" "misc") | |
b03149e1 JZ |
2640 | (set_attr "length" "4") |
2641 | (set_attr "seq_insns" "multi")]) | |
09350e36 | 2642 | |
0d4a78eb BS |
2643 | ;;; Vector instructions |
2644 | ||
75d8b2d0 BS |
2645 | ;; First, all sorts of move variants |
2646 | ||
2647 | (define_insn "movhi_low2high" | |
2648 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2649 | (vec_concat:V2HI | |
2650 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
2651 | (parallel [(const_int 0)])) | |
2652 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2653 | (parallel [(const_int 0)]))))] | |
2654 | "" | |
bbbc206e | 2655 | "%d0 = %h2 << 0%!" |
75d8b2d0 BS |
2656 | [(set_attr "type" "dsp32")]) |
2657 | ||
2658 | (define_insn "movhi_high2high" | |
2659 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2660 | (vec_concat:V2HI | |
2661 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
2662 | (parallel [(const_int 0)])) | |
2663 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2664 | (parallel [(const_int 1)]))))] | |
2665 | "" | |
bbbc206e | 2666 | "%d0 = %d2 << 0%!" |
75d8b2d0 BS |
2667 | [(set_attr "type" "dsp32")]) |
2668 | ||
2669 | (define_insn "movhi_low2low" | |
2670 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2671 | (vec_concat:V2HI | |
2672 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2673 | (parallel [(const_int 0)])) | |
2674 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
2675 | (parallel [(const_int 1)]))))] | |
2676 | "" | |
bbbc206e | 2677 | "%h0 = %h2 << 0%!" |
75d8b2d0 BS |
2678 | [(set_attr "type" "dsp32")]) |
2679 | ||
2680 | (define_insn "movhi_high2low" | |
2681 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2682 | (vec_concat:V2HI | |
2683 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2684 | (parallel [(const_int 1)])) | |
2685 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
2686 | (parallel [(const_int 1)]))))] | |
2687 | "" | |
bbbc206e | 2688 | "%h0 = %d2 << 0%!" |
75d8b2d0 BS |
2689 | [(set_attr "type" "dsp32")]) |
2690 | ||
2691 | (define_insn "movhiv2hi_low" | |
2692 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2693 | (vec_concat:V2HI | |
2694 | (match_operand:HI 2 "register_operand" "d") | |
2695 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
2696 | (parallel [(const_int 1)]))))] | |
2697 | "" | |
bbbc206e | 2698 | "%h0 = %h2 << 0%!" |
75d8b2d0 BS |
2699 | [(set_attr "type" "dsp32")]) |
2700 | ||
2701 | (define_insn "movhiv2hi_high" | |
2702 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2703 | (vec_concat:V2HI | |
2704 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") | |
2705 | (parallel [(const_int 0)])) | |
2706 | (match_operand:HI 2 "register_operand" "d")))] | |
2707 | "" | |
bbbc206e | 2708 | "%d0 = %h2 << 0%!" |
75d8b2d0 BS |
2709 | [(set_attr "type" "dsp32")]) |
2710 | ||
2711 | ;; No earlyclobber on alternative two since our sequence ought to be safe. | |
2712 | ;; The order of operands is intentional to match the VDSP builtin (high word | |
2713 | ;; is passed first). | |
2714 | (define_insn_and_split "composev2hi" | |
2715 | [(set (match_operand:V2HI 0 "register_operand" "=d,d") | |
2716 | (vec_concat:V2HI (match_operand:HI 2 "register_operand" "0,d") | |
2717 | (match_operand:HI 1 "register_operand" "d,d")))] | |
2718 | "" | |
2719 | "@ | |
bbbc206e | 2720 | %d0 = %h2 << 0%! |
75d8b2d0 BS |
2721 | #" |
2722 | "reload_completed" | |
2723 | [(set (match_dup 0) | |
2724 | (vec_concat:V2HI | |
2725 | (vec_select:HI (match_dup 0) (parallel [(const_int 0)])) | |
2726 | (match_dup 2))) | |
2727 | (set (match_dup 0) | |
2728 | (vec_concat:V2HI | |
2729 | (match_dup 1) | |
2730 | (vec_select:HI (match_dup 0) (parallel [(const_int 1)]))))] | |
2731 | "" | |
2732 | [(set_attr "type" "dsp32")]) | |
2733 | ||
2734 | ; Like composev2hi, but operating on elements of V2HI vectors. | |
2735 | ; Useful on its own, and as a combiner bridge for the multiply and | |
2736 | ; mac patterns. | |
2737 | (define_insn "packv2hi" | |
2738 | [(set (match_operand:V2HI 0 "register_operand" "=d,d,d,d") | |
2739 | (vec_concat:V2HI (vec_select:HI | |
2740 | (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
2741 | (parallel [(match_operand 3 "const01_operand" "P0,P1,P0,P1")])) | |
2742 | (vec_select:HI | |
2743 | (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
2744 | (parallel [(match_operand 4 "const01_operand" "P0,P0,P1,P1")]))))] | |
2745 | "" | |
2746 | "@ | |
bbbc206e BS |
2747 | %0 = PACK (%h2,%h1)%! |
2748 | %0 = PACK (%h2,%d1)%! | |
2749 | %0 = PACK (%d2,%h1)%! | |
2750 | %0 = PACK (%d2,%d1)%!" | |
75d8b2d0 BS |
2751 | [(set_attr "type" "dsp32")]) |
2752 | ||
2753 | (define_insn "movv2hi_hi" | |
2754 | [(set (match_operand:HI 0 "register_operand" "=d,d,d") | |
2755 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "0,d,d") | |
554006bd | 2756 | (parallel [(match_operand 2 "const01_operand" "P0,P0,P1")])))] |
75d8b2d0 BS |
2757 | "" |
2758 | "@ | |
2759 | /* optimized out */ | |
bbbc206e BS |
2760 | %h0 = %h1 << 0%! |
2761 | %h0 = %d1 << 0%!" | |
75d8b2d0 BS |
2762 | [(set_attr "type" "dsp32")]) |
2763 | ||
2764 | (define_expand "movv2hi_hi_low" | |
2765 | [(set (match_operand:HI 0 "register_operand" "") | |
2766 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "") | |
2767 | (parallel [(const_int 0)])))] | |
2768 | "" | |
2769 | "") | |
2770 | ||
2771 | (define_expand "movv2hi_hi_high" | |
2772 | [(set (match_operand:HI 0 "register_operand" "") | |
2773 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "") | |
2774 | (parallel [(const_int 1)])))] | |
2775 | "" | |
2776 | "") | |
2777 | ||
942fd98f | 2778 | ;; Unusual arithmetic operations on 16-bit registers. |
75d8b2d0 BS |
2779 | |
2780 | (define_insn "ssaddhi3" | |
2781 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2782 | (ss_plus:HI (match_operand:HI 1 "register_operand" "d") | |
2783 | (match_operand:HI 2 "register_operand" "d")))] | |
2784 | "" | |
bbbc206e | 2785 | "%h0 = %h1 + %h2 (S)%!" |
75d8b2d0 BS |
2786 | [(set_attr "type" "dsp32")]) |
2787 | ||
2788 | (define_insn "sssubhi3" | |
2789 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2790 | (ss_minus:HI (match_operand:HI 1 "register_operand" "d") | |
2791 | (match_operand:HI 2 "register_operand" "d")))] | |
2792 | "" | |
bbbc206e | 2793 | "%h0 = %h1 - %h2 (S)%!" |
75d8b2d0 BS |
2794 | [(set_attr "type" "dsp32")]) |
2795 | ||
2796 | ;; V2HI vector insns | |
2797 | ||
c9b3f817 | 2798 | (define_insn "addv2hi3" |
0d4a78eb BS |
2799 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
2800 | (plus:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
2801 | (match_operand:V2HI 2 "register_operand" "d")))] | |
2802 | "" | |
bbbc206e | 2803 | "%0 = %1 +|+ %2%!" |
0d4a78eb BS |
2804 | [(set_attr "type" "dsp32")]) |
2805 | ||
75d8b2d0 BS |
2806 | (define_insn "ssaddv2hi3" |
2807 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2808 | (ss_plus:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
2809 | (match_operand:V2HI 2 "register_operand" "d")))] | |
2810 | "" | |
bbbc206e | 2811 | "%0 = %1 +|+ %2 (S)%!" |
75d8b2d0 BS |
2812 | [(set_attr "type" "dsp32")]) |
2813 | ||
c9b3f817 | 2814 | (define_insn "subv2hi3" |
0d4a78eb BS |
2815 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
2816 | (minus:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
2817 | (match_operand:V2HI 2 "register_operand" "d")))] | |
2818 | "" | |
bbbc206e | 2819 | "%0 = %1 -|- %2%!" |
0d4a78eb BS |
2820 | [(set_attr "type" "dsp32")]) |
2821 | ||
75d8b2d0 BS |
2822 | (define_insn "sssubv2hi3" |
2823 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2824 | (ss_minus:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
2825 | (match_operand:V2HI 2 "register_operand" "d")))] | |
2826 | "" | |
bbbc206e | 2827 | "%0 = %1 -|- %2 (S)%!" |
75d8b2d0 BS |
2828 | [(set_attr "type" "dsp32")]) |
2829 | ||
2830 | (define_insn "addsubv2hi3" | |
2831 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2832 | (vec_concat:V2HI | |
2833 | (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2834 | (parallel [(const_int 0)])) | |
2835 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2836 | (parallel [(const_int 0)]))) | |
2837 | (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])) | |
2838 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
2839 | "" | |
bbbc206e | 2840 | "%0 = %1 +|- %2%!" |
75d8b2d0 BS |
2841 | [(set_attr "type" "dsp32")]) |
2842 | ||
2843 | (define_insn "subaddv2hi3" | |
2844 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2845 | (vec_concat:V2HI | |
2846 | (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2847 | (parallel [(const_int 0)])) | |
2848 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2849 | (parallel [(const_int 0)]))) | |
2850 | (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])) | |
2851 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
2852 | "" | |
bbbc206e | 2853 | "%0 = %1 -|+ %2%!" |
75d8b2d0 BS |
2854 | [(set_attr "type" "dsp32")]) |
2855 | ||
2856 | (define_insn "ssaddsubv2hi3" | |
2857 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2858 | (vec_concat:V2HI | |
2859 | (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2860 | (parallel [(const_int 0)])) | |
2861 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2862 | (parallel [(const_int 0)]))) | |
2863 | (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])) | |
2864 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
2865 | "" | |
bbbc206e | 2866 | "%0 = %1 +|- %2 (S)%!" |
75d8b2d0 BS |
2867 | [(set_attr "type" "dsp32")]) |
2868 | ||
2869 | (define_insn "sssubaddv2hi3" | |
2870 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
2871 | (vec_concat:V2HI | |
2872 | (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2873 | (parallel [(const_int 0)])) | |
2874 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2875 | (parallel [(const_int 0)]))) | |
2876 | (ss_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])) | |
2877 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
2878 | "" | |
bbbc206e | 2879 | "%0 = %1 -|+ %2 (S)%!" |
75d8b2d0 BS |
2880 | [(set_attr "type" "dsp32")]) |
2881 | ||
2882 | (define_insn "sublohiv2hi3" | |
2883 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2884 | (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2885 | (parallel [(const_int 1)])) | |
2886 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2887 | (parallel [(const_int 0)]))))] | |
2888 | "" | |
bbbc206e | 2889 | "%h0 = %d1 - %h2%!" |
75d8b2d0 BS |
2890 | [(set_attr "type" "dsp32")]) |
2891 | ||
2892 | (define_insn "subhilov2hi3" | |
2893 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2894 | (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2895 | (parallel [(const_int 0)])) | |
2896 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2897 | (parallel [(const_int 1)]))))] | |
2898 | "" | |
bbbc206e | 2899 | "%h0 = %h1 - %d2%!" |
75d8b2d0 BS |
2900 | [(set_attr "type" "dsp32")]) |
2901 | ||
2902 | (define_insn "sssublohiv2hi3" | |
2903 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2904 | (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2905 | (parallel [(const_int 1)])) | |
2906 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2907 | (parallel [(const_int 0)]))))] | |
2908 | "" | |
bbbc206e | 2909 | "%h0 = %d1 - %h2 (S)%!" |
75d8b2d0 BS |
2910 | [(set_attr "type" "dsp32")]) |
2911 | ||
2912 | (define_insn "sssubhilov2hi3" | |
2913 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2914 | (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2915 | (parallel [(const_int 0)])) | |
2916 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2917 | (parallel [(const_int 1)]))))] | |
2918 | "" | |
bbbc206e | 2919 | "%h0 = %h1 - %d2 (S)%!" |
75d8b2d0 BS |
2920 | [(set_attr "type" "dsp32")]) |
2921 | ||
2922 | (define_insn "addlohiv2hi3" | |
2923 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2924 | (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2925 | (parallel [(const_int 1)])) | |
2926 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2927 | (parallel [(const_int 0)]))))] | |
2928 | "" | |
bbbc206e | 2929 | "%h0 = %d1 + %h2%!" |
75d8b2d0 BS |
2930 | [(set_attr "type" "dsp32")]) |
2931 | ||
2932 | (define_insn "addhilov2hi3" | |
2933 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2934 | (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2935 | (parallel [(const_int 0)])) | |
2936 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2937 | (parallel [(const_int 1)]))))] | |
2938 | "" | |
bbbc206e | 2939 | "%h0 = %h1 + %d2%!" |
75d8b2d0 BS |
2940 | [(set_attr "type" "dsp32")]) |
2941 | ||
2942 | (define_insn "ssaddlohiv2hi3" | |
2943 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2944 | (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2945 | (parallel [(const_int 1)])) | |
2946 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2947 | (parallel [(const_int 0)]))))] | |
2948 | "" | |
bbbc206e | 2949 | "%h0 = %d1 + %h2 (S)%!" |
75d8b2d0 BS |
2950 | [(set_attr "type" "dsp32")]) |
2951 | ||
2952 | (define_insn "ssaddhilov2hi3" | |
2953 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2954 | (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
2955 | (parallel [(const_int 0)])) | |
2956 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
2957 | (parallel [(const_int 1)]))))] | |
2958 | "" | |
bbbc206e | 2959 | "%h0 = %h1 + %d2 (S)%!" |
75d8b2d0 BS |
2960 | [(set_attr "type" "dsp32")]) |
2961 | ||
c9b3f817 | 2962 | (define_insn "sminv2hi3" |
0d4a78eb BS |
2963 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
2964 | (smin:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
2965 | (match_operand:V2HI 2 "register_operand" "d")))] | |
2966 | "" | |
bbbc206e | 2967 | "%0 = MIN (%1, %2) (V)%!" |
0d4a78eb BS |
2968 | [(set_attr "type" "dsp32")]) |
2969 | ||
c9b3f817 | 2970 | (define_insn "smaxv2hi3" |
0d4a78eb BS |
2971 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
2972 | (smax:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
2973 | (match_operand:V2HI 2 "register_operand" "d")))] | |
2974 | "" | |
bbbc206e | 2975 | "%0 = MAX (%1, %2) (V)%!" |
0d4a78eb BS |
2976 | [(set_attr "type" "dsp32")]) |
2977 | ||
75d8b2d0 BS |
2978 | ;; Multiplications. |
2979 | ||
2980 | ;; The Blackfin allows a lot of different options, and we need many patterns to | |
2981 | ;; cover most of the hardware's abilities. | |
2982 | ;; There are a few simple patterns using MULT rtx codes, but most of them use | |
2983 | ;; an unspec with a const_int operand that determines which flag to use in the | |
2984 | ;; instruction. | |
2985 | ;; There are variants for single and parallel multiplications. | |
942fd98f | 2986 | ;; There are variants which just use 16-bit lowparts as inputs, and variants |
75d8b2d0 BS |
2987 | ;; which allow the user to choose just which halves to use as input values. |
2988 | ;; There are variants which set D registers, variants which set accumulators, | |
2989 | ;; variants which set both, some of them optionally using the accumulators as | |
2990 | ;; inputs for multiply-accumulate operations. | |
2991 | ||
2992 | (define_insn "flag_mulhi" | |
2993 | [(set (match_operand:HI 0 "register_operand" "=d") | |
2994 | (unspec:HI [(match_operand:HI 1 "register_operand" "d") | |
2995 | (match_operand:HI 2 "register_operand" "d") | |
2996 | (match_operand 3 "const_int_operand" "n")] | |
2997 | UNSPEC_MUL_WITH_FLAG))] | |
2998 | "" | |
bbbc206e | 2999 | "%h0 = %h1 * %h2 %M3%!" |
75d8b2d0 BS |
3000 | [(set_attr "type" "dsp32")]) |
3001 | ||
3002 | (define_insn "flag_mulhisi" | |
3003 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3004 | (unspec:SI [(match_operand:HI 1 "register_operand" "d") | |
3005 | (match_operand:HI 2 "register_operand" "d") | |
3006 | (match_operand 3 "const_int_operand" "n")] | |
3007 | UNSPEC_MUL_WITH_FLAG))] | |
3008 | "" | |
bbbc206e | 3009 | "%0 = %h1 * %h2 %M3%!" |
75d8b2d0 BS |
3010 | [(set_attr "type" "dsp32")]) |
3011 | ||
3012 | (define_insn "flag_mulhisi_parts" | |
3013 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3014 | (unspec:SI [(vec_select:HI | |
3015 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3016 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3017 | (vec_select:HI |
3018 | (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3019 | (parallel [(match_operand 4 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3020 | (match_operand 5 "const_int_operand" "n")] |
3021 | UNSPEC_MUL_WITH_FLAG))] | |
3022 | "" | |
3023 | { | |
3024 | const char *templates[] = { | |
bbbc206e BS |
3025 | "%0 = %h1 * %h2 %M5%!", |
3026 | "%0 = %d1 * %h2 %M5%!", | |
3027 | "%0 = %h1 * %d2 %M5%!", | |
3028 | "%0 = %d1 * %d2 %M5%!" }; | |
75d8b2d0 BS |
3029 | int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1); |
3030 | return templates[alt]; | |
3031 | } | |
3032 | [(set_attr "type" "dsp32")]) | |
3033 | ||
3034 | (define_insn "flag_machi" | |
3035 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3036 | (unspec:HI [(match_operand:HI 1 "register_operand" "d") | |
3037 | (match_operand:HI 2 "register_operand" "d") | |
3038 | (match_operand 3 "register_operand" "A") | |
3039 | (match_operand 4 "const01_operand" "P0P1") | |
3040 | (match_operand 5 "const_int_operand" "n")] | |
3041 | UNSPEC_MAC_WITH_FLAG)) | |
3042 | (set (match_operand:PDI 6 "register_operand" "=A") | |
3043 | (unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3) | |
3044 | (match_dup 4) (match_dup 5)] | |
3045 | UNSPEC_MAC_WITH_FLAG))] | |
3046 | "" | |
bbbc206e | 3047 | "%h0 = (A0 %b4 %h1 * %h2) %M6%!" |
75d8b2d0 BS |
3048 | [(set_attr "type" "dsp32")]) |
3049 | ||
3050 | (define_insn "flag_machi_acconly" | |
3051 | [(set (match_operand:PDI 0 "register_operand" "=e") | |
3052 | (unspec:PDI [(match_operand:HI 1 "register_operand" "d") | |
3053 | (match_operand:HI 2 "register_operand" "d") | |
3054 | (match_operand 3 "register_operand" "A") | |
3055 | (match_operand 4 "const01_operand" "P0P1") | |
3056 | (match_operand 5 "const_int_operand" "n")] | |
3057 | UNSPEC_MAC_WITH_FLAG))] | |
3058 | "" | |
bbbc206e | 3059 | "%0 %b4 %h1 * %h2 %M6%!" |
75d8b2d0 BS |
3060 | [(set_attr "type" "dsp32")]) |
3061 | ||
3062 | (define_insn "flag_macinithi" | |
3063 | [(set (match_operand:HI 0 "register_operand" "=d") | |
3064 | (unspec:HI [(match_operand:HI 1 "register_operand" "d") | |
3065 | (match_operand:HI 2 "register_operand" "d") | |
3066 | (match_operand 3 "const_int_operand" "n")] | |
3067 | UNSPEC_MAC_WITH_FLAG)) | |
3068 | (set (match_operand:PDI 4 "register_operand" "=A") | |
3069 | (unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3)] | |
3070 | UNSPEC_MAC_WITH_FLAG))] | |
3071 | "" | |
bbbc206e | 3072 | "%h0 = (A0 = %h1 * %h2) %M3%!" |
75d8b2d0 BS |
3073 | [(set_attr "type" "dsp32")]) |
3074 | ||
3075 | (define_insn "flag_macinit1hi" | |
3076 | [(set (match_operand:PDI 0 "register_operand" "=e") | |
3077 | (unspec:PDI [(match_operand:HI 1 "register_operand" "d") | |
3078 | (match_operand:HI 2 "register_operand" "d") | |
3079 | (match_operand 3 "const_int_operand" "n")] | |
3080 | UNSPEC_MAC_WITH_FLAG))] | |
3081 | "" | |
bbbc206e | 3082 | "%0 = %h1 * %h2 %M3%!" |
75d8b2d0 BS |
3083 | [(set_attr "type" "dsp32")]) |
3084 | ||
c9b3f817 | 3085 | (define_insn "mulv2hi3" |
0d4a78eb BS |
3086 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
3087 | (mult:V2HI (match_operand:V2HI 1 "register_operand" "d") | |
3088 | (match_operand:V2HI 2 "register_operand" "d")))] | |
3089 | "" | |
bbbc206e | 3090 | "%h0 = %h1 * %h2, %d0 = %d1 * %d2 (IS)%!" |
0d4a78eb BS |
3091 | [(set_attr "type" "dsp32")]) |
3092 | ||
75d8b2d0 BS |
3093 | (define_insn "flag_mulv2hi" |
3094 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3095 | (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d") | |
3096 | (match_operand:V2HI 2 "register_operand" "d") | |
3097 | (match_operand 3 "const_int_operand" "n")] | |
3098 | UNSPEC_MUL_WITH_FLAG))] | |
3099 | "" | |
bbbc206e | 3100 | "%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M3%!" |
75d8b2d0 BS |
3101 | [(set_attr "type" "dsp32")]) |
3102 | ||
3103 | (define_insn "flag_mulv2hi_parts" | |
3104 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3105 | (unspec:V2HI [(vec_concat:V2HI | |
3106 | (vec_select:HI | |
3107 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3108 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3109 | (vec_select:HI |
3110 | (match_dup 1) | |
554006bd | 3111 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3112 | (vec_concat:V2HI |
3113 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3114 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3115 | (vec_select:HI (match_dup 2) |
554006bd | 3116 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3117 | (match_operand 7 "const_int_operand" "n")] |
3118 | UNSPEC_MUL_WITH_FLAG))] | |
3119 | "" | |
3120 | { | |
3121 | const char *templates[] = { | |
bbbc206e BS |
3122 | "%h0 = %h1 * %h2, %d0 = %h1 * %h2 %M7%!", |
3123 | "%h0 = %d1 * %h2, %d0 = %h1 * %h2 %M7%!", | |
3124 | "%h0 = %h1 * %h2, %d0 = %d1 * %h2 %M7%!", | |
3125 | "%h0 = %d1 * %h2, %d0 = %d1 * %h2 %M7%!", | |
3126 | "%h0 = %h1 * %d2, %d0 = %h1 * %h2 %M7%!", | |
3127 | "%h0 = %d1 * %d2, %d0 = %h1 * %h2 %M7%!", | |
3128 | "%h0 = %h1 * %d2, %d0 = %d1 * %h2 %M7%!", | |
3129 | "%h0 = %d1 * %d2, %d0 = %d1 * %h2 %M7%!", | |
3130 | "%h0 = %h1 * %h2, %d0 = %h1 * %d2 %M7%!", | |
3131 | "%h0 = %d1 * %h2, %d0 = %h1 * %d2 %M7%!", | |
3132 | "%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M7%!", | |
3133 | "%h0 = %d1 * %h2, %d0 = %d1 * %d2 %M7%!", | |
3134 | "%h0 = %h1 * %d2, %d0 = %h1 * %d2 %M7%!", | |
3135 | "%h0 = %d1 * %d2, %d0 = %h1 * %d2 %M7%!", | |
3136 | "%h0 = %h1 * %d2, %d0 = %d1 * %d2 %M7%!", | |
3137 | "%h0 = %d1 * %d2, %d0 = %d1 * %d2 %M7%!" }; | |
75d8b2d0 BS |
3138 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3139 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3140 | return templates[alt]; | |
3141 | } | |
3142 | [(set_attr "type" "dsp32")]) | |
3143 | ||
3144 | ;; A slightly complicated pattern. | |
3145 | ;; Operand 0 is the halfword output; operand 11 is the accumulator output | |
3146 | ;; Halfword inputs are operands 1 and 2; operands 3, 4, 5 and 6 specify which | |
3147 | ;; parts of these 2x16 bit registers to use. | |
3148 | ;; Operand 7 is the accumulator input. | |
3149 | ;; Operands 8/9 specify whether low/high parts are mac (0) or msu (1) | |
3150 | ;; Operand 10 is the macflag to be used. | |
3151 | (define_insn "flag_macv2hi_parts" | |
3152 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3153 | (unspec:V2HI [(vec_concat:V2HI | |
3154 | (vec_select:HI | |
3155 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3156 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3157 | (vec_select:HI |
3158 | (match_dup 1) | |
554006bd | 3159 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3160 | (vec_concat:V2HI |
3161 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3162 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3163 | (vec_select:HI (match_dup 2) |
554006bd | 3164 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3165 | (match_operand:V2PDI 7 "register_operand" "e") |
3166 | (match_operand 8 "const01_operand" "P0P1") | |
3167 | (match_operand 9 "const01_operand" "P0P1") | |
3168 | (match_operand 10 "const_int_operand" "n")] | |
3169 | UNSPEC_MAC_WITH_FLAG)) | |
3170 | (set (match_operand:V2PDI 11 "register_operand" "=e") | |
3171 | (unspec:V2PDI [(vec_concat:V2HI | |
3172 | (vec_select:HI (match_dup 1) (parallel [(match_dup 3)])) | |
3173 | (vec_select:HI (match_dup 1) (parallel [(match_dup 4)]))) | |
3174 | (vec_concat:V2HI | |
3175 | (vec_select:HI (match_dup 2) (parallel [(match_dup 5)])) | |
3176 | (vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))) | |
3177 | (match_dup 7) (match_dup 8) (match_dup 9) (match_dup 10)] | |
3178 | UNSPEC_MAC_WITH_FLAG))] | |
3179 | "" | |
3180 | { | |
3181 | const char *templates[] = { | |
bbbc206e BS |
3182 | "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10%!", |
3183 | "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10%!", | |
3184 | "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10%!", | |
3185 | "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10%!", | |
3186 | "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10%!", | |
3187 | "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10%!", | |
3188 | "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10%!", | |
3189 | "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10%!", | |
3190 | "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10%!", | |
3191 | "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10%!", | |
3192 | "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10%!", | |
3193 | "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10%!", | |
3194 | "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10%!", | |
3195 | "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10%!", | |
3196 | "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10%!", | |
3197 | "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10%!" }; | |
75d8b2d0 BS |
3198 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3199 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3200 | return templates[alt]; | |
3201 | } | |
3202 | [(set_attr "type" "dsp32")]) | |
3203 | ||
3204 | (define_insn "flag_macv2hi_parts_acconly" | |
3205 | [(set (match_operand:V2PDI 0 "register_operand" "=e") | |
3206 | (unspec:V2PDI [(vec_concat:V2HI | |
3207 | (vec_select:HI | |
3208 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3209 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3210 | (vec_select:HI |
3211 | (match_dup 1) | |
554006bd | 3212 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3213 | (vec_concat:V2HI |
3214 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3215 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3216 | (vec_select:HI (match_dup 2) |
554006bd | 3217 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3218 | (match_operand:V2PDI 7 "register_operand" "e") |
3219 | (match_operand 8 "const01_operand" "P0P1") | |
3220 | (match_operand 9 "const01_operand" "P0P1") | |
3221 | (match_operand 10 "const_int_operand" "n")] | |
3222 | UNSPEC_MAC_WITH_FLAG))] | |
3223 | "" | |
3224 | { | |
3225 | const char *templates[] = { | |
bbbc206e BS |
3226 | "A0 %b8 %h1 * %h2, A1 %b9 %h1 * %h2 %M10%!", |
3227 | "A0 %b8 %d1 * %h2, A1 %b9 %h1 * %h2 %M10%!", | |
3228 | "A0 %b8 %h1 * %h2, A1 %b9 %d1 * %h2 %M10%!", | |
3229 | "A0 %b8 %d1 * %h2, A1 %b9 %d1 * %h2 %M10%!", | |
3230 | "A0 %b8 %h1 * %d2, A1 %b9 %h1 * %h2 %M10%!", | |
3231 | "A0 %b8 %d1 * %d2, A1 %b9 %h1 * %h2 %M10%!", | |
3232 | "A0 %b8 %h1 * %d2, A1 %b9 %d1 * %h2 %M10%!", | |
3233 | "A0 %b8 %d1 * %d2, A1 %b9 %d1 * %h2 %M10%!", | |
3234 | "A0 %b8 %h1 * %h2, A1 %b9 %h1 * %d2 %M10%!", | |
3235 | "A0 %b8 %d1 * %h2, A1 %b9 %h1 * %d2 %M10%!", | |
3236 | "A0 %b8 %h1 * %h2, A1 %b9 %d1 * %d2 %M10%!", | |
3237 | "A0 %b8 %d1 * %h2, A1 %b9 %d1 * %d2 %M10%!", | |
3238 | "A0 %b8 %h1 * %d2, A1 %b9 %h1 * %d2 %M10%!", | |
3239 | "A0 %b8 %d1 * %d2, A1 %b9 %h1 * %d2 %M10%!", | |
3240 | "A0 %b8 %h1 * %d2, A1 %b9 %d1 * %d2 %M10%!", | |
3241 | "A0 %b8 %d1 * %d2, A1 %b9 %d1 * %d2 %M10%!" }; | |
75d8b2d0 BS |
3242 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3243 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3244 | return templates[alt]; | |
3245 | } | |
3246 | [(set_attr "type" "dsp32")]) | |
3247 | ||
3248 | ;; Same as above, but initializing the accumulators and therefore a couple fewer | |
3249 | ;; necessary operands. | |
3250 | (define_insn "flag_macinitv2hi_parts" | |
0d4a78eb | 3251 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
75d8b2d0 BS |
3252 | (unspec:V2HI [(vec_concat:V2HI |
3253 | (vec_select:HI | |
3254 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3255 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3256 | (vec_select:HI |
3257 | (match_dup 1) | |
554006bd | 3258 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3259 | (vec_concat:V2HI |
3260 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3261 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3262 | (vec_select:HI (match_dup 2) |
554006bd | 3263 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3264 | (match_operand 7 "const_int_operand" "n")] |
3265 | UNSPEC_MAC_WITH_FLAG)) | |
3266 | (set (match_operand:V2PDI 8 "register_operand" "=e") | |
3267 | (unspec:V2PDI [(vec_concat:V2HI | |
3268 | (vec_select:HI (match_dup 1) (parallel [(match_dup 3)])) | |
3269 | (vec_select:HI (match_dup 1) (parallel [(match_dup 4)]))) | |
3270 | (vec_concat:V2HI | |
3271 | (vec_select:HI (match_dup 2) (parallel [(match_dup 5)])) | |
3272 | (vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))) | |
3273 | (match_dup 7)] | |
3274 | UNSPEC_MAC_WITH_FLAG))] | |
3275 | "" | |
3276 | { | |
3277 | const char *templates[] = { | |
bbbc206e BS |
3278 | "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %h2) %M7%!", |
3279 | "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %h2) %M7%!", | |
3280 | "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %h2) %M7%!", | |
3281 | "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %h2) %M7%!", | |
3282 | "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %h2) %M7%!", | |
3283 | "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %h2) %M7%!", | |
3284 | "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %h2) %M7%!", | |
3285 | "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %h2) %M7%!", | |
3286 | "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %d2) %M7%!", | |
3287 | "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %d2) %M7%!", | |
3288 | "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %d2) %M7%!", | |
3289 | "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %d2) %M7%!", | |
3290 | "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %d2) %M7%!", | |
3291 | "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %d2) %M7%!", | |
3292 | "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %d2) %M7%!", | |
3293 | "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %d2) %M7%!" }; | |
75d8b2d0 BS |
3294 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3295 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3296 | return templates[alt]; | |
3297 | } | |
3298 | [(set_attr "type" "dsp32")]) | |
3299 | ||
3300 | (define_insn "flag_macinit1v2hi_parts" | |
3301 | [(set (match_operand:V2PDI 0 "register_operand" "=e") | |
3302 | (unspec:V2PDI [(vec_concat:V2HI | |
3303 | (vec_select:HI | |
3304 | (match_operand:V2HI 1 "register_operand" "d") | |
554006bd | 3305 | (parallel [(match_operand 3 "const01_operand" "P0P1")])) |
75d8b2d0 BS |
3306 | (vec_select:HI |
3307 | (match_dup 1) | |
554006bd | 3308 | (parallel [(match_operand 4 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3309 | (vec_concat:V2HI |
3310 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
554006bd | 3311 | (parallel [(match_operand 5 "const01_operand" "P0P1")])) |
75d8b2d0 | 3312 | (vec_select:HI (match_dup 2) |
554006bd | 3313 | (parallel [(match_operand 6 "const01_operand" "P0P1")]))) |
75d8b2d0 BS |
3314 | (match_operand 7 "const_int_operand" "n")] |
3315 | UNSPEC_MAC_WITH_FLAG))] | |
3316 | "" | |
3317 | { | |
3318 | const char *templates[] = { | |
bbbc206e BS |
3319 | "A0 = %h1 * %h2, A1 = %h1 * %h2 %M7%!", |
3320 | "A0 = %d1 * %h2, A1 = %h1 * %h2 %M7%!", | |
3321 | "A0 = %h1 * %h2, A1 = %d1 * %h2 %M7%!", | |
3322 | "A0 = %d1 * %h2, A1 = %d1 * %h2 %M7%!", | |
3323 | "A0 = %h1 * %d2, A1 = %h1 * %h2 %M7%!", | |
3324 | "A0 = %d1 * %d2, A1 = %h1 * %h2 %M7%!", | |
3325 | "A0 = %h1 * %d2, A1 = %d1 * %h2 %M7%!", | |
3326 | "A0 = %d1 * %d2, A1 = %d1 * %h2 %M7%!", | |
3327 | "A0 = %h1 * %h2, A1 = %h1 * %d2 %M7%!", | |
3328 | "A0 = %d1 * %h2, A1 = %h1 * %d2 %M7%!", | |
3329 | "A0 = %h1 * %h2, A1 = %d1 * %d2 %M7%!", | |
3330 | "A0 = %d1 * %h2, A1 = %d1 * %d2 %M7%!", | |
3331 | "A0 = %h1 * %d2, A1 = %h1 * %d2 %M7%!", | |
3332 | "A0 = %d1 * %d2, A1 = %h1 * %d2 %M7%!", | |
3333 | "A0 = %h1 * %d2, A1 = %d1 * %d2 %M7%!", | |
3334 | "A0 = %d1 * %d2, A1 = %d1 * %d2 %M7%!" }; | |
75d8b2d0 BS |
3335 | int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) |
3336 | + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3)); | |
3337 | return templates[alt]; | |
3338 | } | |
3339 | [(set_attr "type" "dsp32")]) | |
3340 | ||
2889abed BS |
3341 | (define_code_macro s_or_u [sign_extend zero_extend]) |
3342 | (define_code_attr su_optab [(sign_extend "mul") | |
3343 | (zero_extend "umul")]) | |
3344 | (define_code_attr su_modifier [(sign_extend "IS") | |
3345 | (zero_extend "FU")]) | |
3346 | ||
3347 | (define_insn "<su_optab>hisi_ll" | |
75d8b2d0 | 3348 | [(set (match_operand:SI 0 "register_operand" "=d") |
2889abed | 3349 | (mult:SI (s_or_u:SI |
75d8b2d0 BS |
3350 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d") |
3351 | (parallel [(const_int 0)]))) | |
2889abed | 3352 | (s_or_u:SI |
75d8b2d0 BS |
3353 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") |
3354 | (parallel [(const_int 0)])))))] | |
3355 | "" | |
2889abed | 3356 | "%0 = %h1 * %h2 (<su_modifier>)%!" |
75d8b2d0 BS |
3357 | [(set_attr "type" "dsp32")]) |
3358 | ||
2889abed | 3359 | (define_insn "<su_optab>hisi_lh" |
75d8b2d0 | 3360 | [(set (match_operand:SI 0 "register_operand" "=d") |
2889abed BS |
3361 | (mult:SI (s_or_u:SI |
3362 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
75d8b2d0 | 3363 | (parallel [(const_int 0)]))) |
2889abed | 3364 | (s_or_u:SI |
75d8b2d0 BS |
3365 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") |
3366 | (parallel [(const_int 1)])))))] | |
3367 | "" | |
2889abed | 3368 | "%0 = %h1 * %d2 (<su_modifier>)%!" |
75d8b2d0 BS |
3369 | [(set_attr "type" "dsp32")]) |
3370 | ||
2889abed | 3371 | (define_insn "<su_optab>hisi_hl" |
75d8b2d0 | 3372 | [(set (match_operand:SI 0 "register_operand" "=d") |
2889abed BS |
3373 | (mult:SI (s_or_u:SI |
3374 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3375 | (parallel [(const_int 1)]))) | |
3376 | (s_or_u:SI | |
3377 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3378 | (parallel [(const_int 0)])))))] | |
3379 | "" | |
3380 | "%0 = %d1 * %h2 (<su_modifier>)%!" | |
3381 | [(set_attr "type" "dsp32")]) | |
3382 | ||
3383 | (define_insn "<su_optab>hisi_hh" | |
3384 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3385 | (mult:SI (s_or_u:SI | |
75d8b2d0 BS |
3386 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d") |
3387 | (parallel [(const_int 1)]))) | |
2889abed BS |
3388 | (s_or_u:SI |
3389 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3390 | (parallel [(const_int 1)])))))] | |
3391 | "" | |
3392 | "%0 = %d1 * %d2 (<su_modifier>)%!" | |
3393 | [(set_attr "type" "dsp32")]) | |
3394 | ||
3395 | ;; Additional variants for signed * unsigned multiply. | |
3396 | ||
3397 | (define_insn "usmulhisi_ull" | |
3398 | [(set (match_operand:SI 0 "register_operand" "=W") | |
3399 | (mult:SI (zero_extend:SI | |
3400 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d") | |
3401 | (parallel [(const_int 0)]))) | |
75d8b2d0 BS |
3402 | (sign_extend:SI |
3403 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3404 | (parallel [(const_int 0)])))))] | |
3405 | "" | |
2889abed | 3406 | "%0 = %h2 * %h1 (IS,M)%!" |
75d8b2d0 BS |
3407 | [(set_attr "type" "dsp32")]) |
3408 | ||
2889abed BS |
3409 | (define_insn "usmulhisi_ulh" |
3410 | [(set (match_operand:SI 0 "register_operand" "=W") | |
3411 | (mult:SI (zero_extend:SI | |
3412 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3413 | (parallel [(const_int 0)]))) | |
3414 | (sign_extend:SI | |
3415 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3416 | (parallel [(const_int 1)])))))] | |
3417 | "" | |
3418 | "%0 = %d2 * %h1 (IS,M)%!" | |
3419 | [(set_attr "type" "dsp32")]) | |
3420 | ||
3421 | (define_insn "usmulhisi_uhl" | |
3422 | [(set (match_operand:SI 0 "register_operand" "=W") | |
3423 | (mult:SI (zero_extend:SI | |
3424 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") | |
3425 | (parallel [(const_int 1)]))) | |
3426 | (sign_extend:SI | |
3427 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3428 | (parallel [(const_int 0)])))))] | |
3429 | "" | |
3430 | "%0 = %h2 * %d1 (IS,M)%!" | |
3431 | [(set_attr "type" "dsp32")]) | |
3432 | ||
3433 | (define_insn "usmulhisi_uhh" | |
3434 | [(set (match_operand:SI 0 "register_operand" "=W") | |
3435 | (mult:SI (zero_extend:SI | |
75d8b2d0 BS |
3436 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d") |
3437 | (parallel [(const_int 1)]))) | |
3438 | (sign_extend:SI | |
3439 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") | |
3440 | (parallel [(const_int 1)])))))] | |
3441 | "" | |
2889abed BS |
3442 | "%0 = %d2 * %d1 (IS,M)%!" |
3443 | [(set_attr "type" "dsp32")]) | |
3444 | ||
3445 | ;; Parallel versions of these operations. First, normal signed or unsigned | |
3446 | ;; multiplies. | |
3447 | ||
3448 | (define_insn "<su_optab>hisi_ll_lh" | |
3449 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3450 | (mult:SI (s_or_u:SI | |
3451 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3452 | (parallel [(const_int 0)]))) | |
3453 | (s_or_u:SI | |
3454 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3455 | (parallel [(const_int 0)]))))) | |
3456 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3457 | (mult:SI (s_or_u:SI | |
3458 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3459 | (s_or_u:SI | |
3460 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3461 | "" | |
3462 | "%0 = %h1 * %h2, %3 = %h1 * %d2 (<su_modifier>)%!" | |
3463 | [(set_attr "type" "dsp32")]) | |
3464 | ||
3465 | (define_insn "<su_optab>hisi_ll_hl" | |
3466 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3467 | (mult:SI (s_or_u:SI | |
3468 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3469 | (parallel [(const_int 0)]))) | |
3470 | (s_or_u:SI | |
3471 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3472 | (parallel [(const_int 0)]))))) | |
3473 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3474 | (mult:SI (s_or_u:SI | |
3475 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3476 | (s_or_u:SI | |
3477 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3478 | "" | |
3479 | "%0 = %h1 * %h2, %3 = %d1 * %h2 (<su_modifier>)%!" | |
3480 | [(set_attr "type" "dsp32")]) | |
3481 | ||
3482 | (define_insn "<su_optab>hisi_ll_hh" | |
3483 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3484 | (mult:SI (s_or_u:SI | |
3485 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3486 | (parallel [(const_int 0)]))) | |
3487 | (s_or_u:SI | |
3488 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3489 | (parallel [(const_int 0)]))))) | |
3490 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3491 | (mult:SI (s_or_u:SI | |
3492 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3493 | (s_or_u:SI | |
3494 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3495 | "" | |
3496 | "%0 = %h1 * %h2, %3 = %d1 * %d2 (<su_modifier>)%!" | |
3497 | [(set_attr "type" "dsp32")]) | |
3498 | ||
3499 | (define_insn "<su_optab>hisi_lh_hl" | |
3500 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3501 | (mult:SI (s_or_u:SI | |
3502 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3503 | (parallel [(const_int 0)]))) | |
3504 | (s_or_u:SI | |
3505 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3506 | (parallel [(const_int 1)]))))) | |
3507 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3508 | (mult:SI (s_or_u:SI | |
3509 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3510 | (s_or_u:SI | |
3511 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3512 | "" | |
3513 | "%0 = %h1 * %d2, %3 = %d1 * %h2 (<su_modifier>)%!" | |
3514 | [(set_attr "type" "dsp32")]) | |
3515 | ||
3516 | (define_insn "<su_optab>hisi_lh_hh" | |
3517 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3518 | (mult:SI (s_or_u:SI | |
3519 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3520 | (parallel [(const_int 0)]))) | |
3521 | (s_or_u:SI | |
3522 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3523 | (parallel [(const_int 1)]))))) | |
3524 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3525 | (mult:SI (s_or_u:SI | |
3526 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3527 | (s_or_u:SI | |
3528 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3529 | "" | |
3530 | "%0 = %h1 * %d2, %3 = %d1 * %d2 (<su_modifier>)%!" | |
3531 | [(set_attr "type" "dsp32")]) | |
3532 | ||
3533 | (define_insn "<su_optab>hisi_hl_hh" | |
3534 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3535 | (mult:SI (s_or_u:SI | |
3536 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3537 | (parallel [(const_int 1)]))) | |
3538 | (s_or_u:SI | |
3539 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3540 | (parallel [(const_int 0)]))))) | |
3541 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3542 | (mult:SI (s_or_u:SI | |
3543 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3544 | (s_or_u:SI | |
3545 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3546 | "" | |
3547 | "%0 = %d1 * %h2, %3 = %d1 * %d2 (<su_modifier>)%!" | |
3548 | [(set_attr "type" "dsp32")]) | |
3549 | ||
3550 | ;; Special signed * unsigned variants. | |
3551 | ||
3552 | (define_insn "usmulhisi_ll_lul" | |
3553 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3554 | (mult:SI (sign_extend:SI | |
3555 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3556 | (parallel [(const_int 0)]))) | |
3557 | (sign_extend:SI | |
3558 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3559 | (parallel [(const_int 0)]))))) | |
3560 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3561 | (mult:SI (sign_extend:SI | |
3562 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3563 | (zero_extend:SI | |
3564 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3565 | "" | |
3566 | "%0 = %h1 * %h2, %3 = %h1 * %h2 (IS,M)%!" | |
3567 | [(set_attr "type" "dsp32")]) | |
3568 | ||
3569 | (define_insn "usmulhisi_ll_luh" | |
3570 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3571 | (mult:SI (sign_extend:SI | |
3572 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3573 | (parallel [(const_int 0)]))) | |
3574 | (sign_extend:SI | |
3575 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3576 | (parallel [(const_int 0)]))))) | |
3577 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3578 | (mult:SI (sign_extend:SI | |
3579 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3580 | (zero_extend:SI | |
3581 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3582 | "" | |
3583 | "%0 = %h1 * %h2, %3 = %h1 * %d2 (IS,M)%!" | |
3584 | [(set_attr "type" "dsp32")]) | |
3585 | ||
3586 | (define_insn "usmulhisi_ll_hul" | |
3587 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3588 | (mult:SI (sign_extend:SI | |
3589 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3590 | (parallel [(const_int 0)]))) | |
3591 | (sign_extend:SI | |
3592 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3593 | (parallel [(const_int 0)]))))) | |
3594 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3595 | (mult:SI (sign_extend:SI | |
3596 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3597 | (zero_extend:SI | |
3598 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3599 | "" | |
3600 | "%0 = %h1 * %h2, %3 = %d1 * %h2 (IS,M)%!" | |
3601 | [(set_attr "type" "dsp32")]) | |
3602 | ||
3603 | (define_insn "usmulhisi_ll_huh" | |
3604 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3605 | (mult:SI (sign_extend:SI | |
3606 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3607 | (parallel [(const_int 0)]))) | |
3608 | (sign_extend:SI | |
3609 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3610 | (parallel [(const_int 0)]))))) | |
3611 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3612 | (mult:SI (sign_extend:SI | |
3613 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3614 | (zero_extend:SI | |
3615 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3616 | "" | |
3617 | "%0 = %h1 * %h2, %3 = %d1 * %d2 (IS,M)%!" | |
3618 | [(set_attr "type" "dsp32")]) | |
3619 | ||
3620 | (define_insn "usmulhisi_lh_lul" | |
3621 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3622 | (mult:SI (sign_extend:SI | |
3623 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3624 | (parallel [(const_int 0)]))) | |
3625 | (sign_extend:SI | |
3626 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3627 | (parallel [(const_int 1)]))))) | |
3628 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3629 | (mult:SI (sign_extend:SI | |
3630 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3631 | (zero_extend:SI | |
3632 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3633 | "" | |
3634 | "%0 = %h1 * %d2, %3 = %h1 * %h2 (IS,M)%!" | |
3635 | [(set_attr "type" "dsp32")]) | |
3636 | ||
3637 | (define_insn "usmulhisi_lh_luh" | |
3638 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3639 | (mult:SI (sign_extend:SI | |
3640 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3641 | (parallel [(const_int 0)]))) | |
3642 | (sign_extend:SI | |
3643 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3644 | (parallel [(const_int 1)]))))) | |
3645 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3646 | (mult:SI (sign_extend:SI | |
3647 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3648 | (zero_extend:SI | |
3649 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3650 | "" | |
3651 | "%0 = %h1 * %d2, %3 = %h1 * %d2 (IS,M)%!" | |
3652 | [(set_attr "type" "dsp32")]) | |
3653 | ||
3654 | (define_insn "usmulhisi_lh_hul" | |
3655 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3656 | (mult:SI (sign_extend:SI | |
3657 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3658 | (parallel [(const_int 0)]))) | |
3659 | (sign_extend:SI | |
3660 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3661 | (parallel [(const_int 1)]))))) | |
3662 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3663 | (mult:SI (sign_extend:SI | |
3664 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3665 | (zero_extend:SI | |
3666 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3667 | "" | |
3668 | "%0 = %h1 * %d2, %3 = %d1 * %h2 (IS,M)%!" | |
3669 | [(set_attr "type" "dsp32")]) | |
3670 | ||
3671 | (define_insn "usmulhisi_lh_huh" | |
3672 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3673 | (mult:SI (sign_extend:SI | |
3674 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3675 | (parallel [(const_int 0)]))) | |
3676 | (sign_extend:SI | |
3677 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3678 | (parallel [(const_int 1)]))))) | |
3679 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3680 | (mult:SI (sign_extend:SI | |
3681 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3682 | (zero_extend:SI | |
3683 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3684 | "" | |
3685 | "%0 = %h1 * %d2, %3 = %d1 * %d2 (IS,M)%!" | |
3686 | [(set_attr "type" "dsp32")]) | |
3687 | ||
3688 | (define_insn "usmulhisi_hl_lul" | |
3689 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3690 | (mult:SI (sign_extend:SI | |
3691 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3692 | (parallel [(const_int 1)]))) | |
3693 | (sign_extend:SI | |
3694 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3695 | (parallel [(const_int 0)]))))) | |
3696 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3697 | (mult:SI (sign_extend:SI | |
3698 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3699 | (zero_extend:SI | |
3700 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3701 | "" | |
3702 | "%0 = %d1 * %h2, %3 = %h1 * %h2 (IS,M)%!" | |
3703 | [(set_attr "type" "dsp32")]) | |
3704 | ||
3705 | (define_insn "usmulhisi_hl_luh" | |
3706 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3707 | (mult:SI (sign_extend:SI | |
3708 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3709 | (parallel [(const_int 1)]))) | |
3710 | (sign_extend:SI | |
3711 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3712 | (parallel [(const_int 0)]))))) | |
3713 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3714 | (mult:SI (sign_extend:SI | |
3715 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3716 | (zero_extend:SI | |
3717 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3718 | "" | |
3719 | "%0 = %d1 * %h2, %3 = %h1 * %d2 (IS,M)%!" | |
3720 | [(set_attr "type" "dsp32")]) | |
3721 | ||
3722 | (define_insn "usmulhisi_hl_hul" | |
3723 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3724 | (mult:SI (sign_extend:SI | |
3725 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3726 | (parallel [(const_int 1)]))) | |
3727 | (sign_extend:SI | |
3728 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3729 | (parallel [(const_int 0)]))))) | |
3730 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3731 | (mult:SI (sign_extend:SI | |
3732 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3733 | (zero_extend:SI | |
3734 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3735 | "" | |
3736 | "%0 = %d1 * %h2, %3 = %d1 * %h2 (IS,M)%!" | |
3737 | [(set_attr "type" "dsp32")]) | |
3738 | ||
3739 | (define_insn "usmulhisi_hl_huh" | |
3740 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3741 | (mult:SI (sign_extend:SI | |
3742 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3743 | (parallel [(const_int 1)]))) | |
3744 | (sign_extend:SI | |
3745 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3746 | (parallel [(const_int 0)]))))) | |
3747 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3748 | (mult:SI (sign_extend:SI | |
3749 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3750 | (zero_extend:SI | |
3751 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3752 | "" | |
3753 | "%0 = %d1 * %h2, %3 = %d1 * %d2 (IS,M)%!" | |
3754 | [(set_attr "type" "dsp32")]) | |
3755 | ||
3756 | (define_insn "usmulhisi_hh_lul" | |
3757 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3758 | (mult:SI (sign_extend:SI | |
3759 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3760 | (parallel [(const_int 1)]))) | |
3761 | (sign_extend:SI | |
3762 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3763 | (parallel [(const_int 1)]))))) | |
3764 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3765 | (mult:SI (sign_extend:SI | |
3766 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3767 | (zero_extend:SI | |
3768 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3769 | "" | |
3770 | "%0 = %d1 * %d2, %3 = %h1 * %h2 (IS,M)%!" | |
75d8b2d0 BS |
3771 | [(set_attr "type" "dsp32")]) |
3772 | ||
2889abed BS |
3773 | (define_insn "usmulhisi_hh_luh" |
3774 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3775 | (mult:SI (sign_extend:SI | |
3776 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3777 | (parallel [(const_int 1)]))) | |
3778 | (sign_extend:SI | |
3779 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3780 | (parallel [(const_int 1)]))))) | |
3781 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3782 | (mult:SI (sign_extend:SI | |
3783 | (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) | |
3784 | (zero_extend:SI | |
3785 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3786 | "" | |
3787 | "%0 = %d1 * %d2, %3 = %h1 * %d2 (IS,M)%!" | |
3788 | [(set_attr "type" "dsp32")]) | |
3789 | ||
3790 | (define_insn "usmulhisi_hh_hul" | |
3791 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3792 | (mult:SI (sign_extend:SI | |
3793 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3794 | (parallel [(const_int 1)]))) | |
3795 | (sign_extend:SI | |
3796 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3797 | (parallel [(const_int 1)]))))) | |
3798 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3799 | (mult:SI (sign_extend:SI | |
3800 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3801 | (zero_extend:SI | |
3802 | (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))] | |
3803 | "" | |
3804 | "%0 = %d1 * %d2, %3 = %d1 * %h2 (IS,M)%!" | |
3805 | [(set_attr "type" "dsp32")]) | |
3806 | ||
3807 | (define_insn "usmulhisi_hh_huh" | |
3808 | [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6") | |
3809 | (mult:SI (sign_extend:SI | |
3810 | (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d") | |
3811 | (parallel [(const_int 1)]))) | |
3812 | (sign_extend:SI | |
3813 | (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d") | |
3814 | (parallel [(const_int 1)]))))) | |
3815 | (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7") | |
3816 | (mult:SI (sign_extend:SI | |
3817 | (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) | |
3818 | (zero_extend:SI | |
3819 | (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] | |
3820 | "" | |
3821 | "%0 = %d1 * %d2, %3 = %d1 * %d2 (IS,M)%!" | |
3822 | [(set_attr "type" "dsp32")]) | |
3823 | ||
3824 | ;; Vector neg/abs. | |
3825 | ||
75d8b2d0 BS |
3826 | (define_insn "ssnegv2hi2" |
3827 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
3828 | (ss_neg:V2HI (match_operand:V2HI 1 "register_operand" "d")))] | |
0d4a78eb | 3829 | "" |
bbbc206e | 3830 | "%0 = - %1 (V)%!" |
0d4a78eb BS |
3831 | [(set_attr "type" "dsp32")]) |
3832 | ||
c9b3f817 | 3833 | (define_insn "absv2hi2" |
0d4a78eb BS |
3834 | [(set (match_operand:V2HI 0 "register_operand" "=d") |
3835 | (abs:V2HI (match_operand:V2HI 1 "register_operand" "d")))] | |
3836 | "" | |
bbbc206e | 3837 | "%0 = ABS %1 (V)%!" |
0d4a78eb BS |
3838 | [(set_attr "type" "dsp32")]) |
3839 | ||
75d8b2d0 BS |
3840 | ;; Shifts. |
3841 | ||
3842 | (define_insn "ssashiftv2hi3" | |
3843 | [(set (match_operand:V2HI 0 "register_operand" "=d,d,d") | |
3844 | (if_then_else:V2HI | |
3845 | (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) | |
3846 | (ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d") | |
3847 | (match_dup 2)) | |
3848 | (ss_ashift:V2HI (match_dup 1) (match_dup 2))))] | |
3849 | "" | |
3850 | "@ | |
329437dd | 3851 | %0 = ASHIFT %1 BY %h2 (V, S)%! |
58f76679 BS |
3852 | %0 = %1 << %2 (V,S)%! |
3853 | %0 = %1 >>> %N2 (V,S)%!" | |
75d8b2d0 BS |
3854 | [(set_attr "type" "dsp32")]) |
3855 | ||
3856 | (define_insn "ssashifthi3" | |
3857 | [(set (match_operand:HI 0 "register_operand" "=d,d,d") | |
3858 | (if_then_else:HI | |
3859 | (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) | |
3860 | (ashiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d") | |
3861 | (match_dup 2)) | |
3862 | (ss_ashift:HI (match_dup 1) (match_dup 2))))] | |
3863 | "" | |
3864 | "@ | |
329437dd | 3865 | %0 = ASHIFT %1 BY %h2 (V, S)%! |
58f76679 BS |
3866 | %0 = %1 << %2 (V,S)%! |
3867 | %0 = %1 >>> %N2 (V,S)%!" | |
75d8b2d0 BS |
3868 | [(set_attr "type" "dsp32")]) |
3869 | ||
3870 | (define_insn "lshiftv2hi3" | |
3871 | [(set (match_operand:V2HI 0 "register_operand" "=d,d,d") | |
3872 | (if_then_else:V2HI | |
3873 | (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) | |
3874 | (lshiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d") | |
3875 | (match_dup 2)) | |
3876 | (ashift:V2HI (match_dup 1) (match_dup 2))))] | |
3877 | "" | |
3878 | "@ | |
329437dd | 3879 | %0 = LSHIFT %1 BY %h2 (V)%! |
58f76679 BS |
3880 | %0 = %1 << %2 (V)%! |
3881 | %0 = %1 >> %N2 (V)%!" | |
75d8b2d0 BS |
3882 | [(set_attr "type" "dsp32")]) |
3883 | ||
3884 | (define_insn "lshifthi3" | |
3885 | [(set (match_operand:HI 0 "register_operand" "=d,d,d") | |
3886 | (if_then_else:HI | |
3887 | (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) | |
3888 | (lshiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d") | |
3889 | (match_dup 2)) | |
3890 | (ashift:HI (match_dup 1) (match_dup 2))))] | |
3891 | "" | |
3892 | "@ | |
329437dd | 3893 | %0 = LSHIFT %1 BY %h2 (V)%! |
58f76679 BS |
3894 | %0 = %1 << %2 (V)%! |
3895 | %0 = %1 >> %N2 (V)%!" | |
75d8b2d0 BS |
3896 | [(set_attr "type" "dsp32")]) |
3897 |