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e03f789f | 1 | /* Definitions for GCC. Part of the machine description for CRIS. |
3aea1f79 | 2 | Copyright (C) 1998-2014 Free Software Foundation, Inc. |
e03f789f | 3 | Contributed by Axis Communications. Written by Hans-Peter Nilsson. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
038d1e19 | 9 | the Free Software Foundation; either version 3, or (at your option) |
e03f789f | 10 | any later version. |
11 | ||
12 | GCC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
038d1e19 | 18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
e03f789f | 20 | |
21 | #include "config.h" | |
22 | #include "system.h" | |
805e22b2 | 23 | #include "coretypes.h" |
24 | #include "tm.h" | |
e03f789f | 25 | #include "rtl.h" |
26 | #include "regs.h" | |
27 | #include "hard-reg-set.h" | |
e03f789f | 28 | #include "insn-config.h" |
29 | #include "conditions.h" | |
e03f789f | 30 | #include "insn-attr.h" |
31 | #include "flags.h" | |
32 | #include "tree.h" | |
9ed99284 | 33 | #include "varasm.h" |
34 | #include "stor-layout.h" | |
35 | #include "calls.h" | |
36 | #include "stmt.h" | |
e03f789f | 37 | #include "expr.h" |
38 | #include "except.h" | |
a3020f2f | 39 | #include "hashtab.h" |
40 | #include "hash-set.h" | |
41 | #include "vec.h" | |
42 | #include "machmode.h" | |
43 | #include "input.h" | |
e03f789f | 44 | #include "function.h" |
0b205f4c | 45 | #include "diagnostic-core.h" |
e03f789f | 46 | #include "recog.h" |
acb2d1bb | 47 | #include "reload.h" |
e03f789f | 48 | #include "tm_p.h" |
49 | #include "debug.h" | |
1c0b423f | 50 | #include "output.h" |
83ba0b6d | 51 | #include "tm-constrs.h" |
e03f789f | 52 | #include "target.h" |
53 | #include "target-def.h" | |
d98f844a | 54 | #include "ggc.h" |
f2f543a3 | 55 | #include "optabs.h" |
94ea8568 | 56 | #include "dominance.h" |
57 | #include "cfg.h" | |
58 | #include "cfgrtl.h" | |
59 | #include "cfganal.h" | |
60 | #include "lcm.h" | |
61 | #include "cfgbuild.h" | |
62 | #include "cfgcleanup.h" | |
63 | #include "predict.h" | |
64 | #include "basic-block.h" | |
a3d70904 | 65 | #include "df.h" |
fba5dd52 | 66 | #include "opts.h" |
1140c305 | 67 | #include "hash-map.h" |
68 | #include "is-a.h" | |
69 | #include "plugin-api.h" | |
70 | #include "ipa-ref.h" | |
97a652ea | 71 | #include "cgraph.h" |
f7715905 | 72 | #include "builtins.h" |
e03f789f | 73 | |
74 | /* Usable when we have an amount to add or subtract, and want the | |
75 | optimal size of the insn. */ | |
76 | #define ADDITIVE_SIZE_MODIFIER(size) \ | |
77 | ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d") | |
78 | ||
a1657b95 | 79 | #define LOSE_AND_RETURN(msgid, x) \ |
7c5e81ea | 80 | do \ |
81 | { \ | |
a1657b95 | 82 | cris_operand_lossage (msgid, x); \ |
7c5e81ea | 83 | return; \ |
84 | } while (0) | |
85 | ||
72db90ce | 86 | enum cris_retinsn_type |
87 | { CRIS_RETINSN_UNKNOWN = 0, CRIS_RETINSN_RET, CRIS_RETINSN_JUMP }; | |
88 | ||
e03f789f | 89 | /* Per-function machine data. */ |
fb1e4f4a | 90 | struct GTY(()) machine_function |
e03f789f | 91 | { |
92 | int needs_return_address_on_stack; | |
dfc30596 | 93 | |
94 | /* This is the number of registers we save in the prologue due to | |
95 | stdarg. */ | |
96 | int stdarg_regs; | |
97 | ||
72db90ce | 98 | enum cris_retinsn_type return_type; |
e03f789f | 99 | }; |
100 | ||
e03f789f | 101 | /* This little fix suppresses the 'u' or 's' when '%e' in assembly |
102 | pattern. */ | |
103 | static char cris_output_insn_is_bound = 0; | |
104 | ||
f382dce0 | 105 | /* In code for output macros, this is how we know whether e.g. constant |
106 | goes in code or in a static initializer. */ | |
107 | static int in_code = 0; | |
108 | ||
7c5e81ea | 109 | /* Fix for reg_overlap_mentioned_p. */ |
21f64ad5 | 110 | static int cris_reg_overlap_mentioned_p (rtx, rtx); |
e03f789f | 111 | |
3754d046 | 112 | static machine_mode cris_promote_function_mode (const_tree, machine_mode, |
3b2411a8 | 113 | int *, const_tree, int); |
114 | ||
3754d046 | 115 | static unsigned int cris_atomic_align_for_mode (machine_mode); |
60dc82ea | 116 | |
21f64ad5 | 117 | static void cris_print_base (rtx, FILE *); |
e03f789f | 118 | |
21f64ad5 | 119 | static void cris_print_index (rtx, FILE *); |
e03f789f | 120 | |
f382dce0 | 121 | static void cris_output_addr_const (FILE *, rtx); |
122 | ||
21f64ad5 | 123 | static struct machine_function * cris_init_machine_status (void); |
e03f789f | 124 | |
9beb7d17 | 125 | static rtx cris_struct_value_rtx (tree, int); |
126 | ||
3754d046 | 127 | static void cris_setup_incoming_varargs (cumulative_args_t, machine_mode, |
05b21e76 | 128 | tree type, int *, int); |
129 | ||
21f64ad5 | 130 | static int cris_initial_frame_pointer_offset (void); |
7c5e81ea | 131 | |
21f64ad5 | 132 | static void cris_operand_lossage (const char *, rtx); |
7c5e81ea | 133 | |
72db90ce | 134 | static int cris_reg_saved_in_regsave_area (unsigned int, bool); |
135 | ||
0c662fd1 | 136 | static void cris_print_operand (FILE *, rtx, int); |
137 | ||
138 | static void cris_print_operand_address (FILE *, rtx); | |
139 | ||
140 | static bool cris_print_operand_punct_valid_p (unsigned char code); | |
141 | ||
13f42429 | 142 | static bool cris_output_addr_const_extra (FILE *, rtx); |
143 | ||
b2d7ede1 | 144 | static void cris_conditional_register_usage (void); |
145 | ||
6988553d | 146 | static void cris_asm_output_mi_thunk |
21f64ad5 | 147 | (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree); |
6988553d | 148 | |
21f64ad5 | 149 | static void cris_file_start (void); |
f2f543a3 | 150 | static void cris_init_libfuncs (void); |
92c473b8 | 151 | |
66e59d7a | 152 | static reg_class_t cris_preferred_reload_class (rtx, reg_class_t); |
153 | ||
3754d046 | 154 | static int cris_register_move_cost (machine_mode, reg_class_t, reg_class_t); |
155 | static int cris_memory_move_cost (machine_mode, reg_class_t, bool); | |
20d892d1 | 156 | static bool cris_rtx_costs (rtx, int, int, int, int *, bool); |
3754d046 | 157 | static int cris_address_cost (rtx, machine_mode, addr_space_t, bool); |
158 | static bool cris_pass_by_reference (cumulative_args_t, machine_mode, | |
fb80456a | 159 | const_tree, bool); |
3754d046 | 160 | static int cris_arg_partial_bytes (cumulative_args_t, machine_mode, |
f054eb3c | 161 | tree, bool); |
3754d046 | 162 | static rtx cris_function_arg (cumulative_args_t, machine_mode, |
0834de52 | 163 | const_tree, bool); |
39cba157 | 164 | static rtx cris_function_incoming_arg (cumulative_args_t, |
3754d046 | 165 | machine_mode, const_tree, bool); |
166 | static void cris_function_arg_advance (cumulative_args_t, machine_mode, | |
0834de52 | 167 | const_tree, bool); |
64d5fb6a | 168 | static tree cris_md_asm_clobbers (tree, tree, tree); |
3754d046 | 169 | static bool cris_cannot_force_const_mem (machine_mode, rtx); |
6988553d | 170 | |
4c834714 | 171 | static void cris_option_override (void); |
c419af1d | 172 | |
5a1c68c3 | 173 | static bool cris_frame_pointer_required (void); |
174 | ||
f6ddc27b | 175 | static void cris_asm_trampoline_template (FILE *); |
176 | static void cris_trampoline_init (rtx, tree, rtx); | |
177 | ||
5e9082a7 | 178 | static rtx cris_function_value(const_tree, const_tree, bool); |
3754d046 | 179 | static rtx cris_libcall_value (machine_mode, const_rtx); |
7a5dfde8 | 180 | static bool cris_function_value_regno_p (const unsigned int); |
5baeff2b | 181 | static void cris_file_end (void); |
5e9082a7 | 182 | |
e03f789f | 183 | /* This is the parsed result of the "-max-stack-stackframe=" option. If |
184 | it (still) is zero, then there was no such option given. */ | |
185 | int cris_max_stackframe = 0; | |
186 | ||
187 | /* This is the parsed result of the "-march=" option, if given. */ | |
188 | int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION; | |
189 | ||
58356836 | 190 | #undef TARGET_ASM_ALIGNED_HI_OP |
191 | #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
192 | #undef TARGET_ASM_ALIGNED_SI_OP | |
193 | #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t" | |
194 | #undef TARGET_ASM_ALIGNED_DI_OP | |
195 | #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" | |
196 | ||
197 | /* We need to define these, since the 2byte, 4byte, 8byte op:s are only | |
198 | available in ELF. These "normal" pseudos do not have any alignment | |
199 | constraints or side-effects. */ | |
200 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
201 | #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP | |
202 | ||
203 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
204 | #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP | |
205 | ||
206 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
207 | #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP | |
208 | ||
0c662fd1 | 209 | #undef TARGET_PRINT_OPERAND |
210 | #define TARGET_PRINT_OPERAND cris_print_operand | |
211 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
212 | #define TARGET_PRINT_OPERAND_ADDRESS cris_print_operand_address | |
213 | #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P | |
214 | #define TARGET_PRINT_OPERAND_PUNCT_VALID_P cris_print_operand_punct_valid_p | |
13f42429 | 215 | #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA |
216 | #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA cris_output_addr_const_extra | |
0c662fd1 | 217 | |
b2d7ede1 | 218 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
219 | #define TARGET_CONDITIONAL_REGISTER_USAGE cris_conditional_register_usage | |
220 | ||
6988553d | 221 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
222 | #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk | |
eb344f43 | 223 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
224 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
6988553d | 225 | |
92c473b8 | 226 | #undef TARGET_ASM_FILE_START |
227 | #define TARGET_ASM_FILE_START cris_file_start | |
5baeff2b | 228 | #undef TARGET_ASM_FILE_END |
229 | #define TARGET_ASM_FILE_END cris_file_end | |
92c473b8 | 230 | |
f2f543a3 | 231 | #undef TARGET_INIT_LIBFUNCS |
232 | #define TARGET_INIT_LIBFUNCS cris_init_libfuncs | |
233 | ||
5b96044e | 234 | #undef TARGET_LEGITIMATE_ADDRESS_P |
235 | #define TARGET_LEGITIMATE_ADDRESS_P cris_legitimate_address_p | |
236 | ||
f69bb65a | 237 | #undef TARGET_LEGITIMATE_CONSTANT_P |
238 | #define TARGET_LEGITIMATE_CONSTANT_P cris_legitimate_constant_p | |
239 | ||
66e59d7a | 240 | #undef TARGET_PREFERRED_RELOAD_CLASS |
241 | #define TARGET_PREFERRED_RELOAD_CLASS cris_preferred_reload_class | |
242 | ||
d0056fa5 | 243 | #undef TARGET_REGISTER_MOVE_COST |
244 | #define TARGET_REGISTER_MOVE_COST cris_register_move_cost | |
245 | #undef TARGET_MEMORY_MOVE_COST | |
246 | #define TARGET_MEMORY_MOVE_COST cris_memory_move_cost | |
9517cd99 | 247 | #undef TARGET_RTX_COSTS |
248 | #define TARGET_RTX_COSTS cris_rtx_costs | |
249 | #undef TARGET_ADDRESS_COST | |
250 | #define TARGET_ADDRESS_COST cris_address_cost | |
251 | ||
3b2411a8 | 252 | #undef TARGET_PROMOTE_FUNCTION_MODE |
253 | #define TARGET_PROMOTE_FUNCTION_MODE cris_promote_function_mode | |
254 | ||
60dc82ea | 255 | #undef TARGET_ATOMIC_ALIGN_FOR_MODE |
256 | #define TARGET_ATOMIC_ALIGN_FOR_MODE cris_atomic_align_for_mode | |
257 | ||
9beb7d17 | 258 | #undef TARGET_STRUCT_VALUE_RTX |
259 | #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx | |
05b21e76 | 260 | #undef TARGET_SETUP_INCOMING_VARARGS |
261 | #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs | |
b981d932 | 262 | #undef TARGET_PASS_BY_REFERENCE |
263 | #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference | |
f054eb3c | 264 | #undef TARGET_ARG_PARTIAL_BYTES |
265 | #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes | |
0834de52 | 266 | #undef TARGET_FUNCTION_ARG |
267 | #define TARGET_FUNCTION_ARG cris_function_arg | |
268 | #undef TARGET_FUNCTION_INCOMING_ARG | |
269 | #define TARGET_FUNCTION_INCOMING_ARG cris_function_incoming_arg | |
270 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
271 | #define TARGET_FUNCTION_ARG_ADVANCE cris_function_arg_advance | |
8a2947fe | 272 | #undef TARGET_MD_ASM_CLOBBERS |
273 | #define TARGET_MD_ASM_CLOBBERS cris_md_asm_clobbers | |
f69bb65a | 274 | |
275 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
276 | #define TARGET_CANNOT_FORCE_CONST_MEM cris_cannot_force_const_mem | |
277 | ||
5a1c68c3 | 278 | #undef TARGET_FRAME_POINTER_REQUIRED |
279 | #define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required | |
05b21e76 | 280 | |
4c834714 | 281 | #undef TARGET_OPTION_OVERRIDE |
282 | #define TARGET_OPTION_OVERRIDE cris_option_override | |
283 | ||
f6ddc27b | 284 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE |
285 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE cris_asm_trampoline_template | |
286 | #undef TARGET_TRAMPOLINE_INIT | |
287 | #define TARGET_TRAMPOLINE_INIT cris_trampoline_init | |
288 | ||
5e9082a7 | 289 | #undef TARGET_FUNCTION_VALUE |
290 | #define TARGET_FUNCTION_VALUE cris_function_value | |
291 | #undef TARGET_LIBCALL_VALUE | |
292 | #define TARGET_LIBCALL_VALUE cris_libcall_value | |
7a5dfde8 | 293 | #undef TARGET_FUNCTION_VALUE_REGNO_P |
294 | #define TARGET_FUNCTION_VALUE_REGNO_P cris_function_value_regno_p | |
5e9082a7 | 295 | |
e03f789f | 296 | struct gcc_target targetm = TARGET_INITIALIZER; |
297 | ||
72db90ce | 298 | /* Helper for cris_load_multiple_op and cris_ret_movem_op. */ |
299 | ||
48be990a | 300 | bool |
72db90ce | 301 | cris_movem_load_rest_p (rtx op, int offs) |
302 | { | |
303 | unsigned int reg_count = XVECLEN (op, 0) - offs; | |
304 | rtx src_addr; | |
305 | int i; | |
306 | rtx elt; | |
307 | int setno; | |
308 | int regno_dir = 1; | |
309 | unsigned int regno = 0; | |
310 | ||
311 | /* Perform a quick check so we don't blow up below. FIXME: Adjust for | |
312 | other than (MEM reg). */ | |
313 | if (reg_count <= 1 | |
314 | || GET_CODE (XVECEXP (op, 0, offs)) != SET | |
683d2985 | 315 | || !REG_P (SET_DEST (XVECEXP (op, 0, offs))) |
316 | || !MEM_P (SET_SRC (XVECEXP (op, 0, offs)))) | |
48be990a | 317 | return false; |
72db90ce | 318 | |
319 | /* Check a possible post-inc indicator. */ | |
320 | if (GET_CODE (SET_SRC (XVECEXP (op, 0, offs + 1))) == PLUS) | |
321 | { | |
322 | rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 0); | |
323 | rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 1); | |
324 | ||
325 | reg_count--; | |
326 | ||
327 | if (reg_count == 1 | |
328 | || !REG_P (reg) | |
329 | || !REG_P (SET_DEST (XVECEXP (op, 0, offs + 1))) | |
330 | || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, offs + 1))) | |
683d2985 | 331 | || !CONST_INT_P (inc) |
72db90ce | 332 | || INTVAL (inc) != (HOST_WIDE_INT) reg_count * 4) |
48be990a | 333 | return false; |
72db90ce | 334 | i = offs + 2; |
335 | } | |
336 | else | |
337 | i = offs + 1; | |
338 | ||
c85bb9fb | 339 | if (!TARGET_V32) |
340 | { | |
341 | regno_dir = -1; | |
342 | regno = reg_count - 1; | |
343 | } | |
72db90ce | 344 | |
345 | elt = XVECEXP (op, 0, offs); | |
346 | src_addr = XEXP (SET_SRC (elt), 0); | |
347 | ||
348 | if (GET_CODE (elt) != SET | |
683d2985 | 349 | || !REG_P (SET_DEST (elt)) |
72db90ce | 350 | || GET_MODE (SET_DEST (elt)) != SImode |
351 | || REGNO (SET_DEST (elt)) != regno | |
683d2985 | 352 | || !MEM_P (SET_SRC (elt)) |
72db90ce | 353 | || GET_MODE (SET_SRC (elt)) != SImode |
354 | || !memory_address_p (SImode, src_addr)) | |
48be990a | 355 | return false; |
72db90ce | 356 | |
357 | for (setno = 1; i < XVECLEN (op, 0); setno++, i++) | |
358 | { | |
359 | rtx elt = XVECEXP (op, 0, i); | |
360 | regno += regno_dir; | |
361 | ||
362 | if (GET_CODE (elt) != SET | |
683d2985 | 363 | || !REG_P (SET_DEST (elt)) |
72db90ce | 364 | || GET_MODE (SET_DEST (elt)) != SImode |
365 | || REGNO (SET_DEST (elt)) != regno | |
683d2985 | 366 | || !MEM_P (SET_SRC (elt)) |
72db90ce | 367 | || GET_MODE (SET_SRC (elt)) != SImode |
368 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
369 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
683d2985 | 370 | || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt), 0), 1)) |
72db90ce | 371 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != setno * 4) |
48be990a | 372 | return false; |
72db90ce | 373 | } |
374 | ||
48be990a | 375 | return true; |
72db90ce | 376 | } |
377 | ||
48be990a | 378 | /* Worker function for predicate for the parallel contents in a movem |
379 | to-memory. */ | |
dfc30596 | 380 | |
48be990a | 381 | bool |
382 | cris_store_multiple_op_p (rtx op) | |
dfc30596 | 383 | { |
384 | int reg_count = XVECLEN (op, 0); | |
385 | rtx dest; | |
386 | rtx dest_addr; | |
387 | rtx dest_base; | |
388 | int i; | |
389 | rtx elt; | |
390 | int setno; | |
391 | int regno_dir = 1; | |
392 | int regno = 0; | |
393 | int offset = 0; | |
394 | ||
395 | /* Perform a quick check so we don't blow up below. FIXME: Adjust for | |
396 | other than (MEM reg) and (MEM (PLUS reg const)). */ | |
397 | if (reg_count <= 1) | |
48be990a | 398 | return false; |
dfc30596 | 399 | |
400 | elt = XVECEXP (op, 0, 0); | |
401 | ||
402 | if (GET_CODE (elt) != SET) | |
48be990a | 403 | return false; |
dfc30596 | 404 | |
405 | dest = SET_DEST (elt); | |
406 | ||
683d2985 | 407 | if (!REG_P (SET_SRC (elt)) || !MEM_P (dest)) |
48be990a | 408 | return false; |
dfc30596 | 409 | |
410 | dest_addr = XEXP (dest, 0); | |
411 | ||
412 | /* Check a possible post-inc indicator. */ | |
413 | if (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS) | |
414 | { | |
415 | rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 0); | |
416 | rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1); | |
417 | ||
418 | reg_count--; | |
419 | ||
420 | if (reg_count == 1 | |
421 | || !REG_P (reg) | |
422 | || !REG_P (SET_DEST (XVECEXP (op, 0, 1))) | |
423 | || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, 1))) | |
683d2985 | 424 | || !CONST_INT_P (inc) |
dfc30596 | 425 | /* Support increment by number of registers, and by the offset |
426 | of the destination, if it has the form (MEM (PLUS reg | |
427 | offset)). */ | |
428 | || !((REG_P (dest_addr) | |
429 | && REGNO (dest_addr) == REGNO (reg) | |
430 | && INTVAL (inc) == (HOST_WIDE_INT) reg_count * 4) | |
431 | || (GET_CODE (dest_addr) == PLUS | |
432 | && REG_P (XEXP (dest_addr, 0)) | |
433 | && REGNO (XEXP (dest_addr, 0)) == REGNO (reg) | |
683d2985 | 434 | && CONST_INT_P (XEXP (dest_addr, 1)) |
dfc30596 | 435 | && INTVAL (XEXP (dest_addr, 1)) == INTVAL (inc)))) |
48be990a | 436 | return false; |
dfc30596 | 437 | |
438 | i = 2; | |
439 | } | |
440 | else | |
441 | i = 1; | |
442 | ||
c85bb9fb | 443 | if (!TARGET_V32) |
444 | { | |
445 | regno_dir = -1; | |
446 | regno = reg_count - 1; | |
447 | } | |
dfc30596 | 448 | |
449 | if (GET_CODE (elt) != SET | |
683d2985 | 450 | || !REG_P (SET_SRC (elt)) |
dfc30596 | 451 | || GET_MODE (SET_SRC (elt)) != SImode |
452 | || REGNO (SET_SRC (elt)) != (unsigned int) regno | |
683d2985 | 453 | || !MEM_P (SET_DEST (elt)) |
dfc30596 | 454 | || GET_MODE (SET_DEST (elt)) != SImode) |
48be990a | 455 | return false; |
dfc30596 | 456 | |
457 | if (REG_P (dest_addr)) | |
458 | { | |
459 | dest_base = dest_addr; | |
460 | offset = 0; | |
461 | } | |
462 | else if (GET_CODE (dest_addr) == PLUS | |
463 | && REG_P (XEXP (dest_addr, 0)) | |
683d2985 | 464 | && CONST_INT_P (XEXP (dest_addr, 1))) |
dfc30596 | 465 | { |
466 | dest_base = XEXP (dest_addr, 0); | |
467 | offset = INTVAL (XEXP (dest_addr, 1)); | |
468 | } | |
469 | else | |
48be990a | 470 | return false; |
dfc30596 | 471 | |
472 | for (setno = 1; i < XVECLEN (op, 0); setno++, i++) | |
473 | { | |
474 | rtx elt = XVECEXP (op, 0, i); | |
475 | regno += regno_dir; | |
476 | ||
477 | if (GET_CODE (elt) != SET | |
683d2985 | 478 | || !REG_P (SET_SRC (elt)) |
dfc30596 | 479 | || GET_MODE (SET_SRC (elt)) != SImode |
480 | || REGNO (SET_SRC (elt)) != (unsigned int) regno | |
683d2985 | 481 | || !MEM_P (SET_DEST (elt)) |
dfc30596 | 482 | || GET_MODE (SET_DEST (elt)) != SImode |
483 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
484 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_base) | |
683d2985 | 485 | || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt), 0), 1)) |
dfc30596 | 486 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != setno * 4 + offset) |
48be990a | 487 | return false; |
dfc30596 | 488 | } |
489 | ||
48be990a | 490 | return true; |
dfc30596 | 491 | } |
492 | ||
b2d7ede1 | 493 | /* The TARGET_CONDITIONAL_REGISTER_USAGE worker. */ |
e03f789f | 494 | |
b2d7ede1 | 495 | static void |
21f64ad5 | 496 | cris_conditional_register_usage (void) |
e03f789f | 497 | { |
498 | /* FIXME: This isn't nice. We should be able to use that register for | |
499 | something else if the PIC table isn't needed. */ | |
500 | if (flag_pic) | |
501 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] | |
502 | = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; | |
8a2947fe | 503 | |
c85bb9fb | 504 | /* Allow use of ACR (PC in pre-V32) and tweak order. */ |
505 | if (TARGET_V32) | |
506 | { | |
507 | static const int reg_alloc_order_v32[] = REG_ALLOC_ORDER_V32; | |
508 | unsigned int i; | |
509 | ||
510 | fixed_regs[CRIS_ACR_REGNUM] = 0; | |
511 | ||
512 | for (i = 0; | |
513 | i < sizeof (reg_alloc_order_v32)/sizeof (reg_alloc_order_v32[0]); | |
514 | i++) | |
515 | reg_alloc_order[i] = reg_alloc_order_v32[i]; | |
516 | } | |
517 | ||
8a2947fe | 518 | if (TARGET_HAS_MUL_INSNS) |
519 | fixed_regs[CRIS_MOF_REGNUM] = 0; | |
2586cf34 | 520 | |
521 | /* On early versions, we must use the 16-bit condition-code register, | |
522 | which has another name. */ | |
523 | if (cris_cpu_version < 8) | |
524 | reg_names[CRIS_CC0_REGNUM] = "ccr"; | |
e03f789f | 525 | } |
526 | ||
18d50ae6 | 527 | /* Return crtl->uses_pic_offset_table. For use in cris.md, |
e03f789f | 528 | since some generated files do not include function.h. */ |
529 | ||
530 | int | |
21f64ad5 | 531 | cris_cfun_uses_pic_table (void) |
e03f789f | 532 | { |
18d50ae6 | 533 | return crtl->uses_pic_offset_table; |
e03f789f | 534 | } |
535 | ||
f69bb65a | 536 | /* Worker function for TARGET_CANNOT_FORCE_CONST_MEM. |
537 | We can't put PIC addresses in the constant pool, not even the ones that | |
538 | can be reached as pc-relative as we can't tell when or how to do that. */ | |
539 | ||
540 | static bool | |
3754d046 | 541 | cris_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) |
f69bb65a | 542 | { |
543 | enum cris_symbol_type t = cris_symbol_type_of (x); | |
544 | ||
545 | return | |
546 | t == cris_unspec | |
547 | || t == cris_got_symbol | |
548 | || t == cris_rel_symbol; | |
549 | } | |
550 | ||
e03f789f | 551 | /* Given an rtx, return the text string corresponding to the CODE of X. |
552 | Intended for use in the assembly language output section of a | |
553 | define_insn. */ | |
554 | ||
555 | const char * | |
21f64ad5 | 556 | cris_op_str (rtx x) |
e03f789f | 557 | { |
558 | cris_output_insn_is_bound = 0; | |
559 | switch (GET_CODE (x)) | |
560 | { | |
561 | case PLUS: | |
562 | return "add"; | |
563 | break; | |
564 | ||
565 | case MINUS: | |
566 | return "sub"; | |
567 | break; | |
568 | ||
569 | case MULT: | |
9ebd0bb2 | 570 | /* This function is for retrieving a part of an instruction name for |
571 | an operator, for immediate output. If that ever happens for | |
572 | MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure | |
573 | we notice. */ | |
c14afa19 | 574 | internal_error ("MULT case in cris_op_str"); |
e03f789f | 575 | break; |
576 | ||
577 | case DIV: | |
578 | return "div"; | |
579 | break; | |
580 | ||
581 | case AND: | |
582 | return "and"; | |
583 | break; | |
584 | ||
585 | case IOR: | |
586 | return "or"; | |
587 | break; | |
588 | ||
589 | case XOR: | |
590 | return "xor"; | |
591 | break; | |
592 | ||
593 | case NOT: | |
594 | return "not"; | |
595 | break; | |
596 | ||
597 | case ASHIFT: | |
598 | return "lsl"; | |
599 | break; | |
600 | ||
601 | case LSHIFTRT: | |
602 | return "lsr"; | |
603 | break; | |
604 | ||
605 | case ASHIFTRT: | |
606 | return "asr"; | |
607 | break; | |
608 | ||
609 | case UMIN: | |
4bbddcaa | 610 | /* Used to control the sign/zero-extend character for the 'E' modifier. |
e03f789f | 611 | BOUND has none. */ |
612 | cris_output_insn_is_bound = 1; | |
613 | return "bound"; | |
614 | break; | |
615 | ||
616 | default: | |
617 | return "Unknown operator"; | |
618 | break; | |
619 | } | |
620 | } | |
621 | ||
7c5e81ea | 622 | /* Emit an error message when we're in an asm, and a fatal error for |
623 | "normal" insns. Formatted output isn't easily implemented, since we | |
624 | use output_operand_lossage to output the actual message and handle the | |
625 | categorization of the error. */ | |
626 | ||
627 | static void | |
21f64ad5 | 628 | cris_operand_lossage (const char *msgid, rtx op) |
7c5e81ea | 629 | { |
630 | debug_rtx (op); | |
a1657b95 | 631 | output_operand_lossage ("%s", msgid); |
7c5e81ea | 632 | } |
633 | ||
e03f789f | 634 | /* Print an index part of an address to file. */ |
635 | ||
636 | static void | |
21f64ad5 | 637 | cris_print_index (rtx index, FILE *file) |
e03f789f | 638 | { |
e03f789f | 639 | /* Make the index "additive" unless we'll output a negative number, in |
640 | which case the sign character is free (as in free beer). */ | |
683d2985 | 641 | if (!CONST_INT_P (index) || INTVAL (index) >= 0) |
e03f789f | 642 | putc ('+', file); |
643 | ||
644 | if (REG_P (index)) | |
645 | fprintf (file, "$%s.b", reg_names[REGNO (index)]); | |
f69bb65a | 646 | else if (CRIS_CONSTANT_P (index)) |
e03f789f | 647 | cris_output_addr_const (file, index); |
648 | else if (GET_CODE (index) == MULT) | |
649 | { | |
650 | fprintf (file, "$%s.", | |
651 | reg_names[REGNO (XEXP (index, 0))]); | |
652 | ||
653 | putc (INTVAL (XEXP (index, 1)) == 2 ? 'w' : 'd', file); | |
654 | } | |
94d1be51 | 655 | else if (GET_CODE (index) == SIGN_EXTEND && MEM_P (XEXP (index, 0))) |
e03f789f | 656 | { |
94d1be51 | 657 | rtx inner = XEXP (index, 0); |
e03f789f | 658 | rtx inner_inner = XEXP (inner, 0); |
659 | ||
660 | if (GET_CODE (inner_inner) == POST_INC) | |
661 | { | |
662 | fprintf (file, "[$%s+].", | |
663 | reg_names[REGNO (XEXP (inner_inner, 0))]); | |
664 | putc (GET_MODE (inner) == HImode ? 'w' : 'b', file); | |
665 | } | |
666 | else | |
667 | { | |
668 | fprintf (file, "[$%s].", reg_names[REGNO (inner_inner)]); | |
669 | ||
670 | putc (GET_MODE (inner) == HImode ? 'w' : 'b', file); | |
671 | } | |
672 | } | |
683d2985 | 673 | else if (MEM_P (index)) |
e03f789f | 674 | { |
94d1be51 | 675 | rtx inner = XEXP (index, 0); |
e03f789f | 676 | if (GET_CODE (inner) == POST_INC) |
677 | fprintf (file, "[$%s+].d", reg_names[REGNO (XEXP (inner, 0))]); | |
678 | else | |
679 | fprintf (file, "[$%s].d", reg_names[REGNO (inner)]); | |
680 | } | |
681 | else | |
7f9cab51 | 682 | cris_operand_lossage ("unexpected index-type in cris_print_index", |
7c5e81ea | 683 | index); |
e03f789f | 684 | } |
685 | ||
686 | /* Print a base rtx of an address to file. */ | |
687 | ||
688 | static void | |
21f64ad5 | 689 | cris_print_base (rtx base, FILE *file) |
e03f789f | 690 | { |
691 | if (REG_P (base)) | |
692 | fprintf (file, "$%s", reg_names[REGNO (base)]); | |
693 | else if (GET_CODE (base) == POST_INC) | |
c85bb9fb | 694 | { |
695 | gcc_assert (REGNO (XEXP (base, 0)) != CRIS_ACR_REGNUM); | |
696 | fprintf (file, "$%s+", reg_names[REGNO (XEXP (base, 0))]); | |
697 | } | |
e03f789f | 698 | else |
7f9cab51 | 699 | cris_operand_lossage ("unexpected base-type in cris_print_base", |
7c5e81ea | 700 | base); |
e03f789f | 701 | } |
702 | ||
703 | /* Usable as a guard in expressions. */ | |
704 | ||
705 | int | |
21f64ad5 | 706 | cris_fatal (char *arg) |
e03f789f | 707 | { |
708 | internal_error (arg); | |
709 | ||
710 | /* We'll never get here; this is just to appease compilers. */ | |
711 | return 0; | |
712 | } | |
713 | ||
72db90ce | 714 | /* Return nonzero if REGNO is an ordinary register that *needs* to be |
715 | saved together with other registers, possibly by a MOVEM instruction, | |
716 | or is saved for target-independent reasons. There may be | |
717 | target-dependent reasons to save the register anyway; this is just a | |
718 | wrapper for a complicated conditional. */ | |
719 | ||
720 | static int | |
721 | cris_reg_saved_in_regsave_area (unsigned int regno, bool got_really_used) | |
722 | { | |
723 | return | |
3072d30e | 724 | (((df_regs_ever_live_p (regno) |
72db90ce | 725 | && !call_used_regs[regno]) |
726 | || (regno == PIC_OFFSET_TABLE_REGNUM | |
727 | && (got_really_used | |
728 | /* It is saved anyway, if there would be a gap. */ | |
729 | || (flag_pic | |
3072d30e | 730 | && df_regs_ever_live_p (regno + 1) |
72db90ce | 731 | && !call_used_regs[regno + 1])))) |
732 | && (regno != FRAME_POINTER_REGNUM || !frame_pointer_needed) | |
733 | && regno != CRIS_SRP_REGNUM) | |
18d50ae6 | 734 | || (crtl->calls_eh_return |
72db90ce | 735 | && (regno == EH_RETURN_DATA_REGNO (0) |
736 | || regno == EH_RETURN_DATA_REGNO (1) | |
737 | || regno == EH_RETURN_DATA_REGNO (2) | |
738 | || regno == EH_RETURN_DATA_REGNO (3))); | |
739 | } | |
740 | ||
e03f789f | 741 | /* The PRINT_OPERAND worker. */ |
742 | ||
0c662fd1 | 743 | static void |
21f64ad5 | 744 | cris_print_operand (FILE *file, rtx x, int code) |
e03f789f | 745 | { |
746 | rtx operand = x; | |
747 | ||
748 | /* Size-strings corresponding to MULT expressions. */ | |
c8834c5f | 749 | static const char *const mults[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" }; |
e03f789f | 750 | |
751 | /* New code entries should just be added to the switch below. If | |
752 | handling is finished, just return. If handling was just a | |
753 | modification of the operand, the modified operand should be put in | |
754 | "operand", and then do a break to let default handling | |
755 | (zero-modifier) output the operand. */ | |
756 | ||
757 | switch (code) | |
758 | { | |
759 | case 'b': | |
58552ed0 | 760 | /* Print the unsigned supplied integer as if it were signed |
e03f789f | 761 | and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */ |
83ba0b6d | 762 | if (!satisfies_constraint_O (x)) |
7c5e81ea | 763 | LOSE_AND_RETURN ("invalid operand for 'b' modifier", x); |
a8de02e7 | 764 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
765 | INTVAL (x)| (INTVAL (x) <= 255 ? ~255 : ~65535)); | |
e03f789f | 766 | return; |
767 | ||
768 | case 'x': | |
769 | /* Print assembler code for operator. */ | |
770 | fprintf (file, "%s", cris_op_str (operand)); | |
771 | return; | |
772 | ||
72db90ce | 773 | case 'o': |
774 | { | |
775 | /* A movem modifier working on a parallel; output the register | |
776 | name. */ | |
777 | int regno; | |
778 | ||
779 | if (GET_CODE (x) != PARALLEL) | |
780 | LOSE_AND_RETURN ("invalid operand for 'o' modifier", x); | |
781 | ||
782 | /* The second item can be (set reg (plus reg const)) to denote a | |
783 | postincrement. */ | |
784 | regno | |
785 | = (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS | |
786 | ? XVECLEN (x, 0) - 2 | |
787 | : XVECLEN (x, 0) - 1); | |
788 | ||
789 | fprintf (file, "$%s", reg_names [regno]); | |
790 | } | |
791 | return; | |
792 | ||
793 | case 'O': | |
794 | { | |
795 | /* A similar movem modifier; output the memory operand. */ | |
796 | rtx addr; | |
797 | ||
798 | if (GET_CODE (x) != PARALLEL) | |
799 | LOSE_AND_RETURN ("invalid operand for 'O' modifier", x); | |
800 | ||
801 | /* The lowest mem operand is in the first item, but perhaps it | |
802 | needs to be output as postincremented. */ | |
683d2985 | 803 | addr = MEM_P (SET_SRC (XVECEXP (x, 0, 0))) |
72db90ce | 804 | ? XEXP (SET_SRC (XVECEXP (x, 0, 0)), 0) |
805 | : XEXP (SET_DEST (XVECEXP (x, 0, 0)), 0); | |
806 | ||
dfc30596 | 807 | /* The second item can be a (set reg (plus reg const)) to denote |
808 | a modification. */ | |
72db90ce | 809 | if (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS) |
dfc30596 | 810 | { |
811 | /* It's a post-increment, if the address is a naked (reg). */ | |
812 | if (REG_P (addr)) | |
813 | addr = gen_rtx_POST_INC (SImode, addr); | |
814 | else | |
815 | { | |
816 | /* Otherwise, it's a side-effect; RN=RN+M. */ | |
817 | fprintf (file, "[$%s=$%s%s%d]", | |
818 | reg_names [REGNO (SET_DEST (XVECEXP (x, 0, 1)))], | |
819 | reg_names [REGNO (XEXP (addr, 0))], | |
820 | INTVAL (XEXP (addr, 1)) < 0 ? "" : "+", | |
821 | (int) INTVAL (XEXP (addr, 1))); | |
822 | return; | |
823 | } | |
824 | } | |
72db90ce | 825 | output_address (addr); |
826 | } | |
827 | return; | |
828 | ||
e03f789f | 829 | case 'p': |
830 | /* Adjust a power of two to its log2. */ | |
683d2985 | 831 | if (!CONST_INT_P (x) || exact_log2 (INTVAL (x)) < 0 ) |
7c5e81ea | 832 | LOSE_AND_RETURN ("invalid operand for 'p' modifier", x); |
e03f789f | 833 | fprintf (file, "%d", exact_log2 (INTVAL (x))); |
834 | return; | |
835 | ||
836 | case 's': | |
837 | /* For an integer, print 'b' or 'w' if <= 255 or <= 65535 | |
838 | respectively. This modifier also terminates the inhibiting | |
839 | effects of the 'x' modifier. */ | |
840 | cris_output_insn_is_bound = 0; | |
683d2985 | 841 | if (GET_MODE (x) == VOIDmode && CONST_INT_P (x)) |
e03f789f | 842 | { |
843 | if (INTVAL (x) >= 0) | |
844 | { | |
845 | if (INTVAL (x) <= 255) | |
846 | putc ('b', file); | |
847 | else if (INTVAL (x) <= 65535) | |
848 | putc ('w', file); | |
849 | else | |
850 | putc ('d', file); | |
851 | } | |
852 | else | |
853 | putc ('d', file); | |
854 | return; | |
855 | } | |
856 | ||
857 | /* For a non-integer, print the size of the operand. */ | |
858 | putc ((GET_MODE (x) == SImode || GET_MODE (x) == SFmode) | |
859 | ? 'd' : GET_MODE (x) == HImode ? 'w' | |
860 | : GET_MODE (x) == QImode ? 'b' | |
861 | /* If none of the above, emit an erroneous size letter. */ | |
862 | : 'X', | |
863 | file); | |
864 | return; | |
865 | ||
866 | case 'z': | |
867 | /* Const_int: print b for -127 <= x <= 255, | |
c14afa19 | 868 | w for -32768 <= x <= 65535, else die. */ |
683d2985 | 869 | if (!CONST_INT_P (x) |
e03f789f | 870 | || INTVAL (x) < -32768 || INTVAL (x) > 65535) |
7c5e81ea | 871 | LOSE_AND_RETURN ("invalid operand for 'z' modifier", x); |
e03f789f | 872 | putc (INTVAL (x) >= -128 && INTVAL (x) <= 255 ? 'b' : 'w', file); |
873 | return; | |
874 | ||
c85bb9fb | 875 | case 'Z': |
876 | /* If this is a GOT-symbol, print the size-letter corresponding to | |
877 | -fpic/-fPIC. For everything else, print "d". */ | |
878 | putc ((flag_pic == 1 | |
879 | && GET_CODE (x) == CONST | |
880 | && GET_CODE (XEXP (x, 0)) == UNSPEC | |
881 | && XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREAD) | |
882 | ? 'w' : 'd', file); | |
883 | return; | |
884 | ||
e03f789f | 885 | case '#': |
886 | /* Output a 'nop' if there's nothing for the delay slot. | |
887 | This method stolen from the sparc files. */ | |
888 | if (dbr_sequence_length () == 0) | |
889 | fputs ("\n\tnop", file); | |
890 | return; | |
891 | ||
9ebd0bb2 | 892 | case '!': |
893 | /* Output directive for alignment padded with "nop" insns. | |
894 | Optimizing for size, it's plain 4-byte alignment, otherwise we | |
895 | align the section to a cache-line (32 bytes) and skip at max 2 | |
896 | bytes, i.e. we skip if it's the last insn on a cache-line. The | |
897 | latter is faster by a small amount (for two test-programs 99.6% | |
898 | and 99.9%) and larger by a small amount (ditto 100.1% and | |
899 | 100.2%). This is supposed to be the simplest yet performance- | |
900 | wise least intrusive way to make sure the immediately following | |
901 | (supposed) muls/mulu insn isn't located at the end of a | |
902 | cache-line. */ | |
903 | if (TARGET_MUL_BUG) | |
904 | fputs (optimize_size | |
905 | ? ".p2alignw 2,0x050f\n\t" | |
906 | : ".p2alignw 5,0x050f,2\n\t", file); | |
907 | return; | |
908 | ||
6a6dcc7c | 909 | case ':': |
910 | /* The PIC register. */ | |
911 | if (! flag_pic) | |
912 | internal_error ("invalid use of ':' modifier"); | |
913 | fprintf (file, "$%s", reg_names [PIC_OFFSET_TABLE_REGNUM]); | |
914 | return; | |
915 | ||
e03f789f | 916 | case 'H': |
917 | /* Print high (most significant) part of something. */ | |
918 | switch (GET_CODE (operand)) | |
919 | { | |
920 | case CONST_INT: | |
bfbfacd5 | 921 | /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode) |
922 | value is kept here, and so may be other than 0 or -1. */ | |
923 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, | |
924 | INTVAL (operand_subword (operand, 1, 0, DImode))); | |
e03f789f | 925 | return; |
926 | ||
927 | case CONST_DOUBLE: | |
928 | /* High part of a long long constant. */ | |
929 | if (GET_MODE (operand) == VOIDmode) | |
930 | { | |
a8de02e7 | 931 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_HIGH (x)); |
e03f789f | 932 | return; |
933 | } | |
934 | else | |
7c5e81ea | 935 | LOSE_AND_RETURN ("invalid operand for 'H' modifier", x); |
e03f789f | 936 | |
937 | case REG: | |
938 | /* Print reg + 1. Check that there's not an attempt to print | |
c85bb9fb | 939 | high-parts of registers like stack-pointer or higher, except |
940 | for SRP (where the "high part" is MOF). */ | |
941 | if (REGNO (operand) > STACK_POINTER_REGNUM - 2 | |
942 | && (REGNO (operand) != CRIS_SRP_REGNUM | |
943 | || CRIS_SRP_REGNUM + 1 != CRIS_MOF_REGNUM | |
944 | || fixed_regs[CRIS_MOF_REGNUM] != 0)) | |
7c5e81ea | 945 | LOSE_AND_RETURN ("bad register", operand); |
e03f789f | 946 | fprintf (file, "$%s", reg_names[REGNO (operand) + 1]); |
947 | return; | |
948 | ||
949 | case MEM: | |
950 | /* Adjust memory address to high part. */ | |
951 | { | |
952 | rtx adj_mem = operand; | |
953 | int size | |
954 | = GET_MODE_BITSIZE (GET_MODE (operand)) / BITS_PER_UNIT; | |
955 | ||
956 | /* Adjust so we can use two SImode in DImode. | |
957 | Calling adj_offsettable_operand will make sure it is an | |
958 | offsettable address. Don't do this for a postincrement | |
959 | though; it should remain as it was. */ | |
960 | if (GET_CODE (XEXP (adj_mem, 0)) != POST_INC) | |
961 | adj_mem | |
962 | = adjust_address (adj_mem, GET_MODE (adj_mem), size / 2); | |
963 | ||
964 | output_address (XEXP (adj_mem, 0)); | |
965 | return; | |
966 | } | |
967 | ||
968 | default: | |
7c5e81ea | 969 | LOSE_AND_RETURN ("invalid operand for 'H' modifier", x); |
e03f789f | 970 | } |
971 | ||
972 | case 'L': | |
973 | /* Strip the MEM expression. */ | |
974 | operand = XEXP (operand, 0); | |
975 | break; | |
976 | ||
977 | case 'e': | |
4bbddcaa | 978 | /* Like 'E', but ignore state set by 'x'. FIXME: Use code |
fd781bb2 | 979 | iterators and attributes in cris.md to avoid the need for %x |
980 | and %E (and %e) and state passed between those modifiers. */ | |
4bbddcaa | 981 | cris_output_insn_is_bound = 0; |
982 | /* FALL THROUGH. */ | |
983 | case 'E': | |
e03f789f | 984 | /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless |
985 | cris_output_insn_is_bound is nonzero. */ | |
986 | if (GET_CODE (operand) != SIGN_EXTEND | |
987 | && GET_CODE (operand) != ZERO_EXTEND | |
683d2985 | 988 | && !CONST_INT_P (operand)) |
7c5e81ea | 989 | LOSE_AND_RETURN ("invalid operand for 'e' modifier", x); |
e03f789f | 990 | |
991 | if (cris_output_insn_is_bound) | |
992 | { | |
993 | cris_output_insn_is_bound = 0; | |
994 | return; | |
995 | } | |
996 | ||
997 | putc (GET_CODE (operand) == SIGN_EXTEND | |
683d2985 | 998 | || (CONST_INT_P (operand) && INTVAL (operand) < 0) |
e03f789f | 999 | ? 's' : 'u', file); |
1000 | return; | |
1001 | ||
1002 | case 'm': | |
1003 | /* Print the size letter of the inner element. We can do it by | |
1004 | calling ourselves with the 's' modifier. */ | |
1005 | if (GET_CODE (operand) != SIGN_EXTEND && GET_CODE (operand) != ZERO_EXTEND) | |
7c5e81ea | 1006 | LOSE_AND_RETURN ("invalid operand for 'm' modifier", x); |
e03f789f | 1007 | cris_print_operand (file, XEXP (operand, 0), 's'); |
1008 | return; | |
1009 | ||
1010 | case 'M': | |
1011 | /* Print the least significant part of operand. */ | |
1012 | if (GET_CODE (operand) == CONST_DOUBLE) | |
1013 | { | |
a8de02e7 | 1014 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_LOW (x)); |
e03f789f | 1015 | return; |
1016 | } | |
683d2985 | 1017 | else if (HOST_BITS_PER_WIDE_INT > 32 && CONST_INT_P (operand)) |
82d8cc5a | 1018 | { |
a8de02e7 | 1019 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
3dfc21d3 | 1020 | INTVAL (x) & ((unsigned int) 0x7fffffff * 2 + 1)); |
82d8cc5a | 1021 | return; |
1022 | } | |
1023 | /* Otherwise the least significant part equals the normal part, | |
1024 | so handle it normally. */ | |
e03f789f | 1025 | break; |
1026 | ||
1027 | case 'A': | |
1028 | /* When emitting an add for the high part of a DImode constant, we | |
1029 | want to use addq for 0 and adds.w for -1. */ | |
683d2985 | 1030 | if (!CONST_INT_P (operand)) |
7c5e81ea | 1031 | LOSE_AND_RETURN ("invalid operand for 'A' modifier", x); |
e03f789f | 1032 | fprintf (file, INTVAL (operand) < 0 ? "adds.w" : "addq"); |
1033 | return; | |
1034 | ||
71b2d56a | 1035 | case 'P': |
1036 | /* For const_int operands, print the additive mnemonic and the | |
1037 | modified operand (byte-sized operands don't save anything): | |
1038 | N=MIN_INT..-65536: add.d N | |
1039 | -65535..-64: subu.w -N | |
1040 | -63..-1: subq -N | |
1041 | 0..63: addq N | |
1042 | 64..65535: addu.w N | |
1043 | 65536..MAX_INT: add.d N. | |
1044 | (Emitted mnemonics are capitalized to simplify testing.) | |
1045 | For anything else (N.B: only register is valid), print "add.d". */ | |
1046 | if (REG_P (operand)) | |
1047 | { | |
1048 | fprintf (file, "Add.d "); | |
1049 | ||
1050 | /* Deal with printing the operand by dropping through to the | |
1051 | normal path. */ | |
1052 | break; | |
1053 | } | |
1054 | else | |
1055 | { | |
1056 | int val; | |
1057 | gcc_assert (CONST_INT_P (operand)); | |
1058 | ||
1059 | val = INTVAL (operand); | |
1060 | if (!IN_RANGE (val, -65535, 65535)) | |
1061 | fprintf (file, "Add.d %d", val); | |
1062 | else if (val <= -64) | |
1063 | fprintf (file, "Subu.w %d", -val); | |
1064 | else if (val <= -1) | |
1065 | fprintf (file, "Subq %d", -val); | |
1066 | else if (val <= 63) | |
1067 | fprintf (file, "Addq %d", val); | |
1068 | else if (val <= 65535) | |
1069 | fprintf (file, "Addu.w %d", val); | |
1070 | return; | |
1071 | } | |
1072 | break; | |
1073 | ||
1074 | case 'q': | |
1075 | /* If the operand is an integer -31..31, print "q" else ".d". */ | |
1076 | if (CONST_INT_P (operand) && IN_RANGE (INTVAL (operand), -31, 31)) | |
1077 | fprintf (file, "q"); | |
1078 | else | |
1079 | fprintf (file, ".d"); | |
1080 | return; | |
1081 | ||
8a2947fe | 1082 | case 'd': |
6a6dcc7c | 1083 | /* If this is a GOT symbol, force it to be emitted as :GOT and |
1084 | :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16). | |
1085 | Avoid making this too much of a special case. */ | |
f69bb65a | 1086 | if (flag_pic == 1 && CRIS_CONSTANT_P (operand)) |
8a2947fe | 1087 | { |
6a6dcc7c | 1088 | int flag_pic_save = flag_pic; |
1089 | ||
1090 | flag_pic = 2; | |
8a2947fe | 1091 | cris_output_addr_const (file, operand); |
6a6dcc7c | 1092 | flag_pic = flag_pic_save; |
8a2947fe | 1093 | return; |
1094 | } | |
1095 | break; | |
1096 | ||
e03f789f | 1097 | case 'D': |
1098 | /* When emitting an sub for the high part of a DImode constant, we | |
1099 | want to use subq for 0 and subs.w for -1. */ | |
683d2985 | 1100 | if (!CONST_INT_P (operand)) |
7c5e81ea | 1101 | LOSE_AND_RETURN ("invalid operand for 'D' modifier", x); |
e03f789f | 1102 | fprintf (file, INTVAL (operand) < 0 ? "subs.w" : "subq"); |
1103 | return; | |
1104 | ||
1105 | case 'S': | |
1106 | /* Print the operand as the index-part of an address. | |
1107 | Easiest way out is to use cris_print_index. */ | |
1108 | cris_print_index (operand, file); | |
1109 | return; | |
1110 | ||
1111 | case 'T': | |
1112 | /* Print the size letter for an operand to a MULT, which must be a | |
1113 | const_int with a suitable value. */ | |
683d2985 | 1114 | if (!CONST_INT_P (operand) || INTVAL (operand) > 4) |
7c5e81ea | 1115 | LOSE_AND_RETURN ("invalid operand for 'T' modifier", x); |
e03f789f | 1116 | fprintf (file, "%s", mults[INTVAL (operand)]); |
1117 | return; | |
1118 | ||
c85bb9fb | 1119 | case 'u': |
1120 | /* Print "u.w" if a GOT symbol and flag_pic == 1, else ".d". */ | |
1121 | if (flag_pic == 1 | |
1122 | && GET_CODE (operand) == CONST | |
1123 | && GET_CODE (XEXP (operand, 0)) == UNSPEC | |
1124 | && XINT (XEXP (operand, 0), 1) == CRIS_UNSPEC_GOTREAD) | |
1125 | fprintf (file, "u.w"); | |
1126 | else | |
1127 | fprintf (file, ".d"); | |
1128 | return; | |
1129 | ||
e03f789f | 1130 | case 0: |
4e69477b | 1131 | /* No code, print as usual. */ |
e03f789f | 1132 | break; |
1133 | ||
1134 | default: | |
7c5e81ea | 1135 | LOSE_AND_RETURN ("invalid operand modifier letter", x); |
e03f789f | 1136 | } |
1137 | ||
4e69477b | 1138 | /* Print an operand as without a modifier letter. */ |
e03f789f | 1139 | switch (GET_CODE (operand)) |
1140 | { | |
1141 | case REG: | |
8a2947fe | 1142 | if (REGNO (operand) > 15 |
1143 | && REGNO (operand) != CRIS_MOF_REGNUM | |
2586cf34 | 1144 | && REGNO (operand) != CRIS_SRP_REGNUM |
1145 | && REGNO (operand) != CRIS_CC0_REGNUM) | |
68435912 | 1146 | internal_error ("internal error: bad register: %d", REGNO (operand)); |
e03f789f | 1147 | fprintf (file, "$%s", reg_names[REGNO (operand)]); |
1148 | return; | |
1149 | ||
1150 | case MEM: | |
1151 | output_address (XEXP (operand, 0)); | |
1152 | return; | |
1153 | ||
1154 | case CONST_DOUBLE: | |
1155 | if (GET_MODE (operand) == VOIDmode) | |
1156 | /* A long long constant. */ | |
1157 | output_addr_const (file, operand); | |
1158 | else | |
1159 | { | |
1160 | /* Only single precision is allowed as plain operands the | |
1161 | moment. FIXME: REAL_VALUE_FROM_CONST_DOUBLE isn't | |
1162 | documented. */ | |
1163 | REAL_VALUE_TYPE r; | |
1164 | long l; | |
1165 | ||
1166 | /* FIXME: Perhaps check overflow of the "single". */ | |
1167 | REAL_VALUE_FROM_CONST_DOUBLE (r, operand); | |
1168 | REAL_VALUE_TO_TARGET_SINGLE (r, l); | |
1169 | ||
1170 | fprintf (file, "0x%lx", l); | |
1171 | } | |
1172 | return; | |
1173 | ||
1174 | case UNSPEC: | |
e03f789f | 1175 | /* Fall through. */ |
e03f789f | 1176 | case CONST: |
1177 | cris_output_addr_const (file, operand); | |
1178 | return; | |
1179 | ||
1180 | case MULT: | |
1181 | case ASHIFT: | |
1182 | { | |
1183 | /* For a (MULT (reg X) const_int) we output "rX.S". */ | |
683d2985 | 1184 | int i = CONST_INT_P (XEXP (operand, 1)) |
e03f789f | 1185 | ? INTVAL (XEXP (operand, 1)) : INTVAL (XEXP (operand, 0)); |
683d2985 | 1186 | rtx reg = CONST_INT_P (XEXP (operand, 1)) |
e03f789f | 1187 | ? XEXP (operand, 0) : XEXP (operand, 1); |
1188 | ||
683d2985 | 1189 | if (!REG_P (reg) |
1190 | || (!CONST_INT_P (XEXP (operand, 0)) | |
1191 | && !CONST_INT_P (XEXP (operand, 1)))) | |
7c5e81ea | 1192 | LOSE_AND_RETURN ("unexpected multiplicative operand", x); |
e03f789f | 1193 | |
1194 | cris_print_base (reg, file); | |
1195 | fprintf (file, ".%c", | |
1196 | i == 0 || (i == 1 && GET_CODE (operand) == MULT) ? 'b' | |
1197 | : i == 4 ? 'd' | |
1198 | : (i == 2 && GET_CODE (operand) == MULT) || i == 1 ? 'w' | |
1199 | : 'd'); | |
1200 | return; | |
1201 | } | |
1202 | ||
1203 | default: | |
1204 | /* No need to handle all strange variants, let output_addr_const | |
1205 | do it for us. */ | |
f69bb65a | 1206 | if (CRIS_CONSTANT_P (operand)) |
e03f789f | 1207 | { |
1208 | cris_output_addr_const (file, operand); | |
1209 | return; | |
1210 | } | |
1211 | ||
7c5e81ea | 1212 | LOSE_AND_RETURN ("unexpected operand", x); |
e03f789f | 1213 | } |
1214 | } | |
1215 | ||
0c662fd1 | 1216 | static bool |
1217 | cris_print_operand_punct_valid_p (unsigned char code) | |
1218 | { | |
1219 | return (code == '#' || code == '!' || code == ':'); | |
1220 | } | |
1221 | ||
e03f789f | 1222 | /* The PRINT_OPERAND_ADDRESS worker. */ |
1223 | ||
0c662fd1 | 1224 | static void |
21f64ad5 | 1225 | cris_print_operand_address (FILE *file, rtx x) |
e03f789f | 1226 | { |
1227 | /* All these were inside MEM:s so output indirection characters. */ | |
1228 | putc ('[', file); | |
1229 | ||
1230 | if (CONSTANT_ADDRESS_P (x)) | |
1231 | cris_output_addr_const (file, x); | |
5b96044e | 1232 | else if (cris_base_or_autoincr_p (x, true)) |
e03f789f | 1233 | cris_print_base (x, file); |
1234 | else if (GET_CODE (x) == PLUS) | |
1235 | { | |
1236 | rtx x1, x2; | |
1237 | ||
1238 | x1 = XEXP (x, 0); | |
1239 | x2 = XEXP (x, 1); | |
5b96044e | 1240 | if (cris_base_p (x1, true)) |
e03f789f | 1241 | { |
1242 | cris_print_base (x1, file); | |
1243 | cris_print_index (x2, file); | |
1244 | } | |
5b96044e | 1245 | else if (cris_base_p (x2, true)) |
e03f789f | 1246 | { |
1247 | cris_print_base (x2, file); | |
1248 | cris_print_index (x1, file); | |
1249 | } | |
1250 | else | |
7c5e81ea | 1251 | LOSE_AND_RETURN ("unrecognized address", x); |
e03f789f | 1252 | } |
683d2985 | 1253 | else if (MEM_P (x)) |
e03f789f | 1254 | { |
1255 | /* A DIP. Output more indirection characters. */ | |
1256 | putc ('[', file); | |
1257 | cris_print_base (XEXP (x, 0), file); | |
1258 | putc (']', file); | |
1259 | } | |
1260 | else | |
7c5e81ea | 1261 | LOSE_AND_RETURN ("unrecognized address", x); |
e03f789f | 1262 | |
1263 | putc (']', file); | |
1264 | } | |
1265 | ||
1266 | /* The RETURN_ADDR_RTX worker. | |
1267 | We mark that the return address is used, either by EH or | |
1268 | __builtin_return_address, for use by the function prologue and | |
1269 | epilogue. FIXME: This isn't optimal; we just use the mark in the | |
1270 | prologue and epilogue to say that the return address is to be stored | |
1271 | in the stack frame. We could return SRP for leaf-functions and use the | |
1272 | initial-value machinery. */ | |
1273 | ||
1274 | rtx | |
21f64ad5 | 1275 | cris_return_addr_rtx (int count, rtx frameaddr ATTRIBUTE_UNUSED) |
e03f789f | 1276 | { |
1277 | cfun->machine->needs_return_address_on_stack = 1; | |
1278 | ||
1279 | /* The return-address is stored just above the saved frame-pointer (if | |
1280 | present). Apparently we can't eliminate from the frame-pointer in | |
1281 | that direction, so use the incoming args (maybe pretended) pointer. */ | |
1282 | return count == 0 | |
29c05e22 | 1283 | ? gen_rtx_MEM (Pmode, plus_constant (Pmode, virtual_incoming_args_rtx, -4)) |
e03f789f | 1284 | : NULL_RTX; |
1285 | } | |
1286 | ||
228e7e10 | 1287 | /* Accessor used in cris.md:return because cfun->machine isn't available |
1288 | there. */ | |
1289 | ||
72db90ce | 1290 | bool |
dfc30596 | 1291 | cris_return_address_on_stack (void) |
228e7e10 | 1292 | { |
3072d30e | 1293 | return df_regs_ever_live_p (CRIS_SRP_REGNUM) |
72db90ce | 1294 | || cfun->machine->needs_return_address_on_stack; |
1295 | } | |
1296 | ||
1297 | /* Accessor used in cris.md:return because cfun->machine isn't available | |
1298 | there. */ | |
1299 | ||
1300 | bool | |
dfc30596 | 1301 | cris_return_address_on_stack_for_return (void) |
72db90ce | 1302 | { |
1303 | return cfun->machine->return_type == CRIS_RETINSN_RET ? false | |
1304 | : cris_return_address_on_stack (); | |
228e7e10 | 1305 | } |
1306 | ||
e03f789f | 1307 | /* This used to be the INITIAL_FRAME_POINTER_OFFSET worker; now only |
1308 | handles FP -> SP elimination offset. */ | |
1309 | ||
1310 | static int | |
21f64ad5 | 1311 | cris_initial_frame_pointer_offset (void) |
e03f789f | 1312 | { |
1313 | int regno; | |
1314 | ||
8ef587dc | 1315 | /* Initial offset is 0 if we don't have a frame pointer. */ |
e03f789f | 1316 | int offs = 0; |
6a6dcc7c | 1317 | bool got_really_used = false; |
1318 | ||
18d50ae6 | 1319 | if (crtl->uses_pic_offset_table) |
6a6dcc7c | 1320 | { |
1321 | push_topmost_sequence (); | |
1322 | got_really_used | |
1323 | = reg_used_between_p (pic_offset_table_rtx, get_insns (), | |
91a55c11 | 1324 | NULL); |
6a6dcc7c | 1325 | pop_topmost_sequence (); |
1326 | } | |
e03f789f | 1327 | |
1328 | /* And 4 for each register pushed. */ | |
1329 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
72db90ce | 1330 | if (cris_reg_saved_in_regsave_area (regno, got_really_used)) |
e03f789f | 1331 | offs += 4; |
1332 | ||
1333 | /* And then, last, we add the locals allocated. */ | |
1334 | offs += get_frame_size (); | |
1335 | ||
1336 | /* And more; the accumulated args size. */ | |
abe32cce | 1337 | offs += crtl->outgoing_args_size; |
e03f789f | 1338 | |
1339 | /* Then round it off, in case we use aligned stack. */ | |
1340 | if (TARGET_STACK_ALIGN) | |
1341 | offs = TARGET_ALIGN_BY_32 ? (offs + 3) & ~3 : (offs + 1) & ~1; | |
1342 | ||
1343 | return offs; | |
1344 | } | |
1345 | ||
1346 | /* The INITIAL_ELIMINATION_OFFSET worker. | |
1347 | Calculate the difference between imaginary registers such as frame | |
1348 | pointer and the stack pointer. Used to eliminate the frame pointer | |
1349 | and imaginary arg pointer. */ | |
1350 | ||
1351 | int | |
21f64ad5 | 1352 | cris_initial_elimination_offset (int fromreg, int toreg) |
e03f789f | 1353 | { |
1354 | int fp_sp_offset | |
1355 | = cris_initial_frame_pointer_offset (); | |
1356 | ||
1357 | /* We should be able to use regs_ever_live and related prologue | |
1358 | information here, or alpha should not as well. */ | |
72db90ce | 1359 | bool return_address_on_stack = cris_return_address_on_stack (); |
e03f789f | 1360 | |
58552ed0 | 1361 | /* Here we act as if the frame-pointer were needed. */ |
e03f789f | 1362 | int ap_fp_offset = 4 + (return_address_on_stack ? 4 : 0); |
1363 | ||
1364 | if (fromreg == ARG_POINTER_REGNUM | |
1365 | && toreg == FRAME_POINTER_REGNUM) | |
1366 | return ap_fp_offset; | |
1367 | ||
1368 | /* Between the frame pointer and the stack are only "normal" stack | |
1369 | variables and saved registers. */ | |
1370 | if (fromreg == FRAME_POINTER_REGNUM | |
1371 | && toreg == STACK_POINTER_REGNUM) | |
1372 | return fp_sp_offset; | |
1373 | ||
4e69477b | 1374 | /* We need to balance out the frame pointer here. */ |
e03f789f | 1375 | if (fromreg == ARG_POINTER_REGNUM |
1376 | && toreg == STACK_POINTER_REGNUM) | |
1377 | return ap_fp_offset + fp_sp_offset - 4; | |
1378 | ||
c14afa19 | 1379 | gcc_unreachable (); |
e03f789f | 1380 | } |
1381 | ||
5b96044e | 1382 | /* Nonzero if X is a hard reg that can be used as an index. */ |
1383 | static inline bool | |
1384 | reg_ok_for_base_p (const_rtx x, bool strict) | |
1385 | { | |
1386 | return ((! strict && ! HARD_REGISTER_P (x)) | |
1387 | || REGNO_OK_FOR_BASE_P (REGNO (x))); | |
1388 | } | |
1389 | ||
1390 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
1391 | static inline bool | |
1392 | reg_ok_for_index_p (const_rtx x, bool strict) | |
1393 | { | |
1394 | return reg_ok_for_base_p (x, strict); | |
1395 | } | |
1396 | ||
1397 | /* No symbol can be used as an index (or more correct, as a base) together | |
1398 | with a register with PIC; the PIC register must be there. */ | |
1399 | ||
1400 | bool | |
1401 | cris_constant_index_p (const_rtx x) | |
1402 | { | |
f69bb65a | 1403 | return (CRIS_CONSTANT_P (x) && (!flag_pic || cris_valid_pic_const (x, true))); |
5b96044e | 1404 | } |
1405 | ||
1406 | /* True if X is a valid base register. */ | |
1407 | ||
1408 | bool | |
1409 | cris_base_p (const_rtx x, bool strict) | |
1410 | { | |
1411 | return (REG_P (x) && reg_ok_for_base_p (x, strict)); | |
1412 | } | |
1413 | ||
1414 | /* True if X is a valid index register. */ | |
1415 | ||
1416 | static inline bool | |
1417 | cris_index_p (const_rtx x, bool strict) | |
1418 | { | |
1419 | return (REG_P (x) && reg_ok_for_index_p (x, strict)); | |
1420 | } | |
1421 | ||
1422 | /* True if X is a valid base register with or without autoincrement. */ | |
1423 | ||
1424 | bool | |
1425 | cris_base_or_autoincr_p (const_rtx x, bool strict) | |
1426 | { | |
1427 | return (cris_base_p (x, strict) | |
1428 | || (GET_CODE (x) == POST_INC | |
1429 | && cris_base_p (XEXP (x, 0), strict) | |
1430 | && REGNO (XEXP (x, 0)) != CRIS_ACR_REGNUM)); | |
1431 | } | |
1432 | ||
1433 | /* True if X is a valid (register) index for BDAP, i.e. [Rs].S or [Rs+].S. */ | |
1434 | ||
1435 | bool | |
1436 | cris_bdap_index_p (const_rtx x, bool strict) | |
1437 | { | |
1438 | return ((MEM_P (x) | |
1439 | && GET_MODE (x) == SImode | |
1440 | && cris_base_or_autoincr_p (XEXP (x, 0), strict)) | |
1441 | || (GET_CODE (x) == SIGN_EXTEND | |
1442 | && MEM_P (XEXP (x, 0)) | |
1443 | && (GET_MODE (XEXP (x, 0)) == HImode | |
1444 | || GET_MODE (XEXP (x, 0)) == QImode) | |
1445 | && cris_base_or_autoincr_p (XEXP (XEXP (x, 0), 0), strict))); | |
1446 | } | |
1447 | ||
1448 | /* True if X is a valid (register) index for BIAP, i.e. Rd.m. */ | |
1449 | ||
1450 | bool | |
1451 | cris_biap_index_p (const_rtx x, bool strict) | |
1452 | { | |
1453 | return (cris_index_p (x, strict) | |
1454 | || (GET_CODE (x) == MULT | |
1455 | && cris_index_p (XEXP (x, 0), strict) | |
1456 | && cris_scale_int_operand (XEXP (x, 1), VOIDmode))); | |
1457 | } | |
1458 | ||
1459 | /* Worker function for TARGET_LEGITIMATE_ADDRESS_P. | |
1460 | ||
1461 | A PIC operand looks like a normal symbol here. At output we dress it | |
1462 | in "[rPIC+symbol:GOT]" (global symbol) or "rPIC+symbol:GOTOFF" (local | |
1463 | symbol) so we exclude all addressing modes where we can't replace a | |
1464 | plain "symbol" with that. A global PIC symbol does not fit anywhere | |
1465 | here (but is thankfully a general_operand in itself). A local PIC | |
1466 | symbol is valid for the plain "symbol + offset" case. */ | |
1467 | ||
d5c0ec8e | 1468 | bool |
3754d046 | 1469 | cris_legitimate_address_p (machine_mode mode, rtx x, bool strict) |
5b96044e | 1470 | { |
1471 | const_rtx x1, x2; | |
1472 | ||
1473 | if (cris_base_or_autoincr_p (x, strict)) | |
1474 | return true; | |
1475 | else if (TARGET_V32) | |
1476 | /* Nothing else is valid then. */ | |
1477 | return false; | |
1478 | else if (cris_constant_index_p (x)) | |
1479 | return true; | |
1480 | /* Indexed? */ | |
1481 | else if (GET_CODE (x) == PLUS) | |
1482 | { | |
1483 | x1 = XEXP (x, 0); | |
1484 | x2 = XEXP (x, 1); | |
1485 | /* BDAP o, Rd. */ | |
1486 | if ((cris_base_p (x1, strict) && cris_constant_index_p (x2)) | |
1487 | || (cris_base_p (x2, strict) && cris_constant_index_p (x1)) | |
1488 | /* BDAP Rs[+], Rd. */ | |
1489 | || (GET_MODE_SIZE (mode) <= UNITS_PER_WORD | |
1490 | && ((cris_base_p (x1, strict) | |
1491 | && cris_bdap_index_p (x2, strict)) | |
1492 | || (cris_base_p (x2, strict) | |
1493 | && cris_bdap_index_p (x1, strict)) | |
1494 | /* BIAP.m Rs, Rd */ | |
1495 | || (cris_base_p (x1, strict) | |
1496 | && cris_biap_index_p (x2, strict)) | |
1497 | || (cris_base_p (x2, strict) | |
1498 | && cris_biap_index_p (x1, strict))))) | |
1499 | return true; | |
1500 | } | |
1501 | else if (MEM_P (x)) | |
1502 | { | |
1503 | /* DIP (Rs). Reject [[reg+]] and [[reg]] for DImode (long long). */ | |
1504 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD | |
1505 | && cris_base_or_autoincr_p (XEXP (x, 0), strict)) | |
1506 | return true; | |
1507 | } | |
1508 | ||
1509 | return false; | |
1510 | } | |
1511 | ||
f69bb65a | 1512 | /* Worker function for TARGET_LEGITIMATE_CONSTANT_P. We have to handle |
1513 | PIC constants that aren't legitimized. FIXME: there used to be a | |
1514 | guarantee that the target LEGITIMATE_CONSTANT_P didn't have to handle | |
1515 | PIC constants, but no more (4.7 era); testcase: glibc init-first.c. | |
1516 | While that may be seen as a bug, that guarantee seems a wart by design, | |
1517 | so don't bother; fix the documentation instead. */ | |
1518 | ||
1519 | bool | |
3754d046 | 1520 | cris_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x) |
f69bb65a | 1521 | { |
1522 | enum cris_symbol_type t; | |
1523 | ||
1524 | if (flag_pic) | |
1525 | return LEGITIMATE_PIC_OPERAND_P (x); | |
1526 | ||
1527 | t = cris_symbol_type_of (x); | |
1528 | ||
1529 | return | |
1530 | t == cris_no_symbol | |
1531 | || t == cris_offsettable_symbol | |
1532 | || t == cris_unspec; | |
1533 | } | |
1534 | ||
acb2d1bb | 1535 | /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */ |
1536 | ||
1537 | bool | |
1538 | cris_reload_address_legitimized (rtx x, | |
3754d046 | 1539 | machine_mode mode ATTRIBUTE_UNUSED, |
acb2d1bb | 1540 | int opnum ATTRIBUTE_UNUSED, |
1541 | int itype, | |
1542 | int ind_levels ATTRIBUTE_UNUSED) | |
1543 | { | |
39e09a0c | 1544 | enum reload_type type = (enum reload_type) itype; |
acb2d1bb | 1545 | rtx op0, op1; |
acb2d1bb | 1546 | rtx *op1p; |
1547 | ||
1548 | if (GET_CODE (x) != PLUS) | |
1549 | return false; | |
1550 | ||
c85bb9fb | 1551 | if (TARGET_V32) |
1552 | return false; | |
1553 | ||
acb2d1bb | 1554 | op0 = XEXP (x, 0); |
acb2d1bb | 1555 | op1 = XEXP (x, 1); |
1556 | op1p = &XEXP (x, 1); | |
1557 | ||
1558 | if (!REG_P (op1)) | |
1559 | return false; | |
1560 | ||
683d2985 | 1561 | if (GET_CODE (op0) == SIGN_EXTEND && MEM_P (XEXP (op0, 0))) |
acb2d1bb | 1562 | { |
1563 | rtx op00 = XEXP (op0, 0); | |
1564 | rtx op000 = XEXP (op00, 0); | |
1565 | rtx *op000p = &XEXP (op00, 0); | |
1566 | ||
1567 | if ((GET_MODE (op00) == HImode || GET_MODE (op00) == QImode) | |
1568 | && (REG_P (op000) | |
1569 | || (GET_CODE (op000) == POST_INC && REG_P (XEXP (op000, 0))))) | |
1570 | { | |
1571 | bool something_reloaded = false; | |
1572 | ||
1573 | if (GET_CODE (op000) == POST_INC | |
1574 | && REG_P (XEXP (op000, 0)) | |
1575 | && REGNO (XEXP (op000, 0)) > CRIS_LAST_GENERAL_REGISTER) | |
1576 | /* No, this gets too complicated and is too rare to care | |
1577 | about trying to improve on the general code Here. | |
1578 | As the return-value is an all-or-nothing indicator, we | |
1579 | punt on the other register too. */ | |
1580 | return false; | |
1581 | ||
1582 | if ((REG_P (op000) | |
1583 | && REGNO (op000) > CRIS_LAST_GENERAL_REGISTER)) | |
1584 | { | |
1585 | /* The address of the inner mem is a pseudo or wrong | |
1586 | reg: reload that. */ | |
1587 | push_reload (op000, NULL_RTX, op000p, NULL, GENERAL_REGS, | |
1588 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); | |
1589 | something_reloaded = true; | |
1590 | } | |
1591 | ||
1592 | if (REGNO (op1) > CRIS_LAST_GENERAL_REGISTER) | |
1593 | { | |
1594 | /* Base register is a pseudo or wrong reg: reload it. */ | |
1595 | push_reload (op1, NULL_RTX, op1p, NULL, GENERAL_REGS, | |
1596 | GET_MODE (x), VOIDmode, 0, 0, | |
1597 | opnum, type); | |
1598 | something_reloaded = true; | |
1599 | } | |
1600 | ||
1601 | gcc_assert (something_reloaded); | |
1602 | ||
1603 | return true; | |
1604 | } | |
1605 | } | |
1606 | ||
1607 | return false; | |
1608 | } | |
1609 | ||
66e59d7a | 1610 | |
1611 | /* Worker function for TARGET_PREFERRED_RELOAD_CLASS. | |
1612 | ||
1613 | It seems like gcc (2.7.2 and 2.9x of 2000-03-22) may send "NO_REGS" as | |
1614 | the class for a constant (testcase: __Mul in arit.c). To avoid forcing | |
1615 | out a constant into the constant pool, we will trap this case and | |
1616 | return something a bit more sane. FIXME: Check if this is a bug. | |
1617 | Beware that we must not "override" classes that can be specified as | |
1618 | constraint letters, or else asm operands using them will fail when | |
1619 | they need to be reloaded. FIXME: Investigate whether that constitutes | |
1620 | a bug. */ | |
1621 | ||
1622 | static reg_class_t | |
1623 | cris_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass) | |
1624 | { | |
1625 | if (rclass != ACR_REGS | |
1626 | && rclass != MOF_REGS | |
bd503556 | 1627 | && rclass != MOF_SRP_REGS |
66e59d7a | 1628 | && rclass != SRP_REGS |
1629 | && rclass != CC0_REGS | |
1630 | && rclass != SPECIAL_REGS) | |
1631 | return GENERAL_REGS; | |
1632 | ||
1633 | return rclass; | |
1634 | } | |
1635 | ||
d0056fa5 | 1636 | /* Worker function for TARGET_REGISTER_MOVE_COST. */ |
e03f789f | 1637 | |
d0056fa5 | 1638 | static int |
3754d046 | 1639 | cris_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, |
d0056fa5 | 1640 | reg_class_t from, reg_class_t to) |
e03f789f | 1641 | { |
c85bb9fb | 1642 | /* Can't move to and from a SPECIAL_REGS register, so we have to say |
1643 | their move cost within that class is higher. How about 7? That's 3 | |
1644 | for a move to a GENERAL_REGS register, 3 for the move from the | |
1645 | GENERAL_REGS register, and 1 for the increased register pressure. | |
34569717 | 1646 | Also, it's higher than the memory move cost, as it should. |
c85bb9fb | 1647 | We also do this for ALL_REGS, since we don't want that class to be |
1648 | preferred (even to memory) at all where GENERAL_REGS doesn't fit. | |
1649 | Whenever it's about to be used, it's for SPECIAL_REGS. If we don't | |
1650 | present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be | |
1651 | used when a GENERAL_REGS should be used, even if there are call-saved | |
1652 | GENERAL_REGS left to allocate. This is because the fall-back when | |
1653 | the most preferred register class isn't available, isn't the next | |
1654 | (or next good) wider register class, but the *most widest* register | |
34569717 | 1655 | class. FIXME: pre-IRA comment, perhaps obsolete now. */ |
c85bb9fb | 1656 | |
1657 | if ((reg_classes_intersect_p (from, SPECIAL_REGS) | |
1658 | && reg_classes_intersect_p (to, SPECIAL_REGS)) | |
1659 | || from == ALL_REGS || to == ALL_REGS) | |
1660 | return 7; | |
1661 | ||
34569717 | 1662 | /* Make moves to/from SPECIAL_REGS slightly more expensive, as we |
1663 | generally prefer GENERAL_REGS. */ | |
c85bb9fb | 1664 | if (reg_classes_intersect_p (from, SPECIAL_REGS) |
1665 | || reg_classes_intersect_p (to, SPECIAL_REGS)) | |
1666 | return 3; | |
1667 | ||
1668 | return 2; | |
1669 | } | |
e03f789f | 1670 | |
d0056fa5 | 1671 | /* Worker function for TARGET_MEMORY_MOVE_COST. |
1672 | ||
1673 | This isn't strictly correct for v0..3 in buswidth-8bit mode, but should | |
1674 | suffice. */ | |
1675 | ||
1676 | static int | |
3754d046 | 1677 | cris_memory_move_cost (machine_mode mode, |
d0056fa5 | 1678 | reg_class_t rclass ATTRIBUTE_UNUSED, |
1679 | bool in ATTRIBUTE_UNUSED) | |
1680 | { | |
1681 | if (mode == QImode | |
1682 | || mode == HImode) | |
1683 | return 4; | |
1684 | else | |
1685 | return 6; | |
1686 | } | |
1687 | ||
c85bb9fb | 1688 | /* Worker for cris_notice_update_cc; handles the "normal" cases. |
1689 | FIXME: this code is historical; its functionality should be | |
1690 | refactored to look at insn attributes and moved to | |
1691 | cris_notice_update_cc. Except, we better lose cc0 entirely. */ | |
e03f789f | 1692 | |
c85bb9fb | 1693 | static void |
1694 | cris_normal_notice_update_cc (rtx exp, rtx insn) | |
1695 | { | |
1696 | /* "Normal" means, for: | |
1697 | (set (cc0) (...)): | |
1698 | CC is (...). | |
e03f789f | 1699 | |
c85bb9fb | 1700 | (set (reg) (...)): |
1701 | CC is (reg) and (...) - unless (...) is 0 or reg is a special | |
1702 | register or (v32 and (...) is -32..-1), then CC does not change. | |
1703 | CC_NO_OVERFLOW unless (...) is reg or mem. | |
e03f789f | 1704 | |
c85bb9fb | 1705 | (set (mem) (...)): |
1706 | CC does not change. | |
e03f789f | 1707 | |
c85bb9fb | 1708 | (set (pc) (...)): |
1709 | CC does not change. | |
e03f789f | 1710 | |
c85bb9fb | 1711 | (parallel |
1712 | (set (reg1) (mem (bdap/biap))) | |
1713 | (set (reg2) (bdap/biap))): | |
1714 | CC is (reg1) and (mem (reg2)) | |
e03f789f | 1715 | |
c85bb9fb | 1716 | (parallel |
1717 | (set (mem (bdap/biap)) (reg1)) [or 0] | |
1718 | (set (reg2) (bdap/biap))): | |
1719 | CC does not change. | |
e03f789f | 1720 | |
c85bb9fb | 1721 | (where reg and mem includes strict_low_parts variants thereof) |
e03f789f | 1722 | |
c85bb9fb | 1723 | For all others, assume CC is clobbered. |
1724 | Note that we do not have to care about setting CC_NO_OVERFLOW, | |
1725 | since the overflow flag is set to 0 (i.e. right) for | |
1726 | instructions where it does not have any sane sense, but where | |
1727 | other flags have meanings. (This includes shifts; the carry is | |
1728 | not set by them). | |
e03f789f | 1729 | |
c85bb9fb | 1730 | Note that there are other parallel constructs we could match, |
1731 | but we don't do that yet. */ | |
e03f789f | 1732 | |
c85bb9fb | 1733 | if (GET_CODE (exp) == SET) |
1734 | { | |
1735 | /* FIXME: Check when this happens. It looks like we should | |
1736 | actually do a CC_STATUS_INIT here to be safe. */ | |
1737 | if (SET_DEST (exp) == pc_rtx) | |
1738 | return; | |
e03f789f | 1739 | |
c85bb9fb | 1740 | /* Record CC0 changes, so we do not have to output multiple |
1741 | test insns. */ | |
1742 | if (SET_DEST (exp) == cc0_rtx) | |
e03f789f | 1743 | { |
c85bb9fb | 1744 | CC_STATUS_INIT; |
e03f789f | 1745 | |
74f4459c | 1746 | if (GET_CODE (SET_SRC (exp)) == COMPARE |
1747 | && XEXP (SET_SRC (exp), 1) == const0_rtx) | |
1748 | cc_status.value1 = XEXP (SET_SRC (exp), 0); | |
1749 | else | |
1750 | cc_status.value1 = SET_SRC (exp); | |
1751 | ||
1752 | /* Handle flags for the special btstq on one bit. */ | |
1753 | if (GET_CODE (cc_status.value1) == ZERO_EXTRACT | |
1754 | && XEXP (cc_status.value1, 1) == const1_rtx) | |
e03f789f | 1755 | { |
74f4459c | 1756 | if (CONST_INT_P (XEXP (cc_status.value1, 0))) |
c85bb9fb | 1757 | /* Using cmpq. */ |
1758 | cc_status.flags = CC_INVERTED; | |
e03f789f | 1759 | else |
c85bb9fb | 1760 | /* A one-bit btstq. */ |
1761 | cc_status.flags = CC_Z_IN_NOT_N; | |
e03f789f | 1762 | } |
e03f789f | 1763 | |
74f4459c | 1764 | else if (GET_CODE (SET_SRC (exp)) == COMPARE) |
c85bb9fb | 1765 | { |
1766 | if (!REG_P (XEXP (SET_SRC (exp), 0)) | |
1767 | && XEXP (SET_SRC (exp), 1) != const0_rtx) | |
1768 | /* For some reason gcc will not canonicalize compare | |
1769 | operations, reversing the sign by itself if | |
1770 | operands are in wrong order. */ | |
1771 | /* (But NOT inverted; eq is still eq.) */ | |
1772 | cc_status.flags = CC_REVERSED; | |
1773 | ||
1774 | /* This seems to be overlooked by gcc. FIXME: Check again. | |
1775 | FIXME: Is it really safe? */ | |
1776 | cc_status.value2 | |
1777 | = gen_rtx_MINUS (GET_MODE (SET_SRC (exp)), | |
1778 | XEXP (SET_SRC (exp), 0), | |
1779 | XEXP (SET_SRC (exp), 1)); | |
1780 | } | |
1781 | return; | |
1782 | } | |
1783 | else if (REG_P (SET_DEST (exp)) | |
1784 | || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART | |
1785 | && REG_P (XEXP (SET_DEST (exp), 0)))) | |
1786 | { | |
1787 | /* A register is set; normally CC is set to show that no | |
1788 | test insn is needed. Catch the exceptions. */ | |
e03f789f | 1789 | |
c85bb9fb | 1790 | /* If not to cc0, then no "set"s in non-natural mode give |
1791 | ok cc0... */ | |
1792 | if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp))) > UNITS_PER_WORD | |
1793 | || GET_MODE_CLASS (GET_MODE (SET_DEST (exp))) == MODE_FLOAT) | |
1794 | { | |
1795 | /* ... except add:s and sub:s in DImode. */ | |
1796 | if (GET_MODE (SET_DEST (exp)) == DImode | |
1797 | && (GET_CODE (SET_SRC (exp)) == PLUS | |
1798 | || GET_CODE (SET_SRC (exp)) == MINUS)) | |
e03f789f | 1799 | { |
c85bb9fb | 1800 | CC_STATUS_INIT; |
e03f789f | 1801 | cc_status.value1 = SET_DEST (exp); |
1802 | cc_status.value2 = SET_SRC (exp); | |
1803 | ||
1804 | if (cris_reg_overlap_mentioned_p (cc_status.value1, | |
1805 | cc_status.value2)) | |
1806 | cc_status.value2 = 0; | |
1807 | ||
c85bb9fb | 1808 | /* Add and sub may set V, which gets us |
e03f789f | 1809 | unoptimizable results in "gt" and "le" condition |
1810 | codes. */ | |
c85bb9fb | 1811 | cc_status.flags |= CC_NO_OVERFLOW; |
e03f789f | 1812 | |
1813 | return; | |
1814 | } | |
1815 | } | |
c85bb9fb | 1816 | else if (SET_SRC (exp) == const0_rtx |
1817 | || (REG_P (SET_SRC (exp)) | |
1818 | && (REGNO (SET_SRC (exp)) | |
1819 | > CRIS_LAST_GENERAL_REGISTER)) | |
1820 | || (TARGET_V32 | |
826e3285 | 1821 | && REG_P (SET_DEST (exp)) |
83ba0b6d | 1822 | && satisfies_constraint_I (SET_SRC (exp)))) |
e03f789f | 1823 | { |
c85bb9fb | 1824 | /* There's no CC0 change for this case. Just check |
1825 | for overlap. */ | |
37ed48c7 | 1826 | if (cc_status.value1 |
1827 | && modified_in_p (cc_status.value1, insn)) | |
e03f789f | 1828 | cc_status.value1 = 0; |
1829 | ||
37ed48c7 | 1830 | if (cc_status.value2 |
1831 | && modified_in_p (cc_status.value2, insn)) | |
e03f789f | 1832 | cc_status.value2 = 0; |
1833 | ||
1834 | return; | |
1835 | } | |
c85bb9fb | 1836 | else |
1837 | { | |
1838 | CC_STATUS_INIT; | |
1839 | cc_status.value1 = SET_DEST (exp); | |
1840 | cc_status.value2 = SET_SRC (exp); | |
1841 | ||
1842 | if (cris_reg_overlap_mentioned_p (cc_status.value1, | |
1843 | cc_status.value2)) | |
1844 | cc_status.value2 = 0; | |
1845 | ||
1846 | /* Some operations may set V, which gets us | |
1847 | unoptimizable results in "gt" and "le" condition | |
1848 | codes. */ | |
1849 | if (GET_CODE (SET_SRC (exp)) == PLUS | |
1850 | || GET_CODE (SET_SRC (exp)) == MINUS | |
1851 | || GET_CODE (SET_SRC (exp)) == NEG) | |
1852 | cc_status.flags |= CC_NO_OVERFLOW; | |
1853 | ||
1854 | /* For V32, nothing with a register destination sets | |
1855 | C and V usefully. */ | |
1856 | if (TARGET_V32) | |
1857 | cc_status.flags |= CC_NO_OVERFLOW; | |
1858 | ||
1859 | return; | |
1860 | } | |
1861 | } | |
1862 | else if (MEM_P (SET_DEST (exp)) | |
1863 | || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART | |
1864 | && MEM_P (XEXP (SET_DEST (exp), 0)))) | |
1865 | { | |
1866 | /* When SET to MEM, then CC is not changed (except for | |
1867 | overlap). */ | |
1868 | if (cc_status.value1 | |
1869 | && modified_in_p (cc_status.value1, insn)) | |
1870 | cc_status.value1 = 0; | |
1871 | ||
1872 | if (cc_status.value2 | |
1873 | && modified_in_p (cc_status.value2, insn)) | |
1874 | cc_status.value2 = 0; | |
1875 | ||
1876 | return; | |
e03f789f | 1877 | } |
c85bb9fb | 1878 | } |
1879 | else if (GET_CODE (exp) == PARALLEL) | |
1880 | { | |
1881 | if (GET_CODE (XVECEXP (exp, 0, 0)) == SET | |
1882 | && GET_CODE (XVECEXP (exp, 0, 1)) == SET | |
1883 | && REG_P (XEXP (XVECEXP (exp, 0, 1), 0))) | |
e03f789f | 1884 | { |
c85bb9fb | 1885 | if (REG_P (XEXP (XVECEXP (exp, 0, 0), 0)) |
1886 | && MEM_P (XEXP (XVECEXP (exp, 0, 0), 1))) | |
e03f789f | 1887 | { |
c85bb9fb | 1888 | CC_STATUS_INIT; |
1889 | ||
1890 | /* For "move.S [rx=ry+o],rz", say CC reflects | |
1891 | value1=rz and value2=[rx] */ | |
1892 | cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0); | |
1893 | cc_status.value2 | |
1894 | = replace_equiv_address (XEXP (XVECEXP (exp, 0, 0), 1), | |
1895 | XEXP (XVECEXP (exp, 0, 1), 0)); | |
1896 | ||
1897 | /* Huh? A side-effect cannot change the destination | |
1898 | register. */ | |
1899 | if (cris_reg_overlap_mentioned_p (cc_status.value1, | |
1900 | cc_status.value2)) | |
1901 | internal_error ("internal error: sideeffect-insn affecting main effect"); | |
1902 | ||
1903 | /* For V32, moves to registers don't set C and V. */ | |
1904 | if (TARGET_V32) | |
1905 | cc_status.flags |= CC_NO_OVERFLOW; | |
1906 | return; | |
1907 | } | |
1908 | else if ((REG_P (XEXP (XVECEXP (exp, 0, 0), 1)) | |
1909 | || XEXP (XVECEXP (exp, 0, 0), 1) == const0_rtx) | |
1910 | && MEM_P (XEXP (XVECEXP (exp, 0, 0), 0))) | |
1911 | { | |
1912 | /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]", | |
1913 | say flags are not changed, except for overlap. */ | |
1914 | if (cc_status.value1 | |
1915 | && modified_in_p (cc_status.value1, insn)) | |
1916 | cc_status.value1 = 0; | |
78e05be1 | 1917 | |
c85bb9fb | 1918 | if (cc_status.value2 |
1919 | && modified_in_p (cc_status.value2, insn)) | |
1920 | cc_status.value2 = 0; | |
1921 | ||
1922 | return; | |
e03f789f | 1923 | } |
1924 | } | |
c85bb9fb | 1925 | } |
1926 | ||
1927 | /* If we got here, the case wasn't covered by the code above. */ | |
1928 | CC_STATUS_INIT; | |
1929 | } | |
1930 | ||
1931 | /* This function looks into the pattern to see how this insn affects | |
1932 | condition codes. | |
1933 | ||
1934 | Used when to eliminate test insns before a condition-code user, | |
1935 | such as a "scc" insn or a conditional branch. This includes | |
1936 | checking if the entities that cc was updated by, are changed by the | |
1937 | operation. | |
1938 | ||
1939 | Currently a jumble of the old peek-inside-the-insn and the newer | |
1940 | check-cc-attribute methods. */ | |
1941 | ||
1942 | void | |
d3ffa7b4 | 1943 | cris_notice_update_cc (rtx exp, rtx_insn *insn) |
c85bb9fb | 1944 | { |
1945 | enum attr_cc attrval = get_attr_cc (insn); | |
1946 | ||
1947 | /* Check if user specified "-mcc-init" as a bug-workaround. Remember | |
1948 | to still set CC_REVERSED as below, since that's required by some | |
1949 | compare insn alternatives. (FIXME: GCC should do this virtual | |
1950 | operand swap by itself.) A test-case that may otherwise fail is | |
1951 | gcc.c-torture/execute/20000217-1.c -O0 and -O1. */ | |
1952 | if (TARGET_CCINIT) | |
1953 | { | |
1954 | CC_STATUS_INIT; | |
1955 | ||
1956 | if (attrval == CC_REV) | |
1957 | cc_status.flags = CC_REVERSED; | |
1958 | return; | |
1959 | } | |
1960 | ||
1961 | /* Slowly, we're converting to using attributes to control the setting | |
1962 | of condition-code status. */ | |
1963 | switch (attrval) | |
1964 | { | |
1965 | case CC_NONE: | |
1966 | /* Even if it is "none", a setting may clobber a previous | |
1967 | cc-value, so check. */ | |
1968 | if (GET_CODE (exp) == SET) | |
1969 | { | |
1970 | if (cc_status.value1 | |
1971 | && modified_in_p (cc_status.value1, insn)) | |
1972 | cc_status.value1 = 0; | |
1973 | ||
1974 | if (cc_status.value2 | |
1975 | && modified_in_p (cc_status.value2, insn)) | |
1976 | cc_status.value2 = 0; | |
1977 | } | |
1978 | return; | |
1979 | ||
1980 | case CC_CLOBBER: | |
1981 | CC_STATUS_INIT; | |
1982 | return; | |
1983 | ||
1984 | case CC_REV: | |
1985 | case CC_NOOV32: | |
1986 | case CC_NORMAL: | |
1987 | cris_normal_notice_update_cc (exp, insn); | |
1988 | ||
1989 | /* The "test" insn doesn't clear (carry and) overflow on V32. We | |
1990 | can change bge => bpl and blt => bmi by passing on to the cc0 | |
1991 | user that V should not be considered; bgt and ble are taken | |
1992 | care of by other methods (see {tst,cmp}{si,hi,qi}). */ | |
1993 | if (attrval == CC_NOOV32 && TARGET_V32) | |
1994 | cc_status.flags |= CC_NO_OVERFLOW; | |
1995 | return; | |
e03f789f | 1996 | |
1997 | default: | |
0a81f5a0 | 1998 | internal_error ("unknown cc_attr value"); |
e03f789f | 1999 | } |
2000 | ||
2001 | CC_STATUS_INIT; | |
2002 | } | |
2003 | ||
2004 | /* Return != 0 if the return sequence for the current function is short, | |
72db90ce | 2005 | like "ret" or "jump [sp+]". Prior to reloading, we can't tell if |
2006 | registers must be saved, so return 0 then. */ | |
e03f789f | 2007 | |
72db90ce | 2008 | bool |
21f64ad5 | 2009 | cris_simple_epilogue (void) |
e03f789f | 2010 | { |
72db90ce | 2011 | unsigned int regno; |
2012 | unsigned int reglimit = STACK_POINTER_REGNUM; | |
6a6dcc7c | 2013 | bool got_really_used = false; |
e03f789f | 2014 | |
2015 | if (! reload_completed | |
2016 | || frame_pointer_needed | |
2017 | || get_frame_size () != 0 | |
abe32cce | 2018 | || crtl->args.pretend_args_size |
2019 | || crtl->args.size | |
2020 | || crtl->outgoing_args_size | |
18d50ae6 | 2021 | || crtl->calls_eh_return |
e03f789f | 2022 | |
2023 | /* If we're not supposed to emit prologue and epilogue, we must | |
2024 | not emit return-type instructions. */ | |
2025 | || !TARGET_PROLOGUE_EPILOGUE) | |
72db90ce | 2026 | return false; |
e03f789f | 2027 | |
c85bb9fb | 2028 | /* Can't return from stacked return address with v32. */ |
2029 | if (TARGET_V32 && cris_return_address_on_stack ()) | |
2030 | return false; | |
2031 | ||
18d50ae6 | 2032 | if (crtl->uses_pic_offset_table) |
6a6dcc7c | 2033 | { |
2034 | push_topmost_sequence (); | |
2035 | got_really_used | |
91a55c11 | 2036 | = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL); |
6a6dcc7c | 2037 | pop_topmost_sequence (); |
2038 | } | |
2039 | ||
72db90ce | 2040 | /* No simple epilogue if there are saved registers. */ |
e03f789f | 2041 | for (regno = 0; regno < reglimit; regno++) |
72db90ce | 2042 | if (cris_reg_saved_in_regsave_area (regno, got_really_used)) |
2043 | return false; | |
e03f789f | 2044 | |
72db90ce | 2045 | return true; |
2046 | } | |
2047 | ||
2ef7687b | 2048 | /* Emit checking that MEM is aligned for an access in MODE, failing |
2049 | that, executing a "break 8" (or call to abort, if "break 8" is | |
2050 | disabled). */ | |
2051 | ||
2052 | void | |
2053 | cris_emit_trap_for_misalignment (rtx mem) | |
2054 | { | |
ee5f6585 | 2055 | rtx addr, reg, ok_label, andop; |
2056 | rtx_insn *jmp; | |
2ef7687b | 2057 | int natural_alignment; |
2058 | gcc_assert (MEM_P (mem)); | |
2059 | ||
2060 | natural_alignment = GET_MODE_SIZE (GET_MODE (mem)); | |
2061 | addr = XEXP (mem, 0); | |
2062 | reg = force_reg (Pmode, addr); | |
2063 | ok_label = gen_label_rtx (); | |
2064 | ||
2065 | /* This will yield a btstq without a separate register used, usually - | |
2066 | with the exception for PRE hoisting the "and" but not the branch | |
d0df4894 | 2067 | around the trap: see testsuite/gcc.target/cris/sync-3s.c. */ |
32354eaf | 2068 | andop = gen_rtx_AND (Pmode, reg, GEN_INT (natural_alignment - 1)); |
2069 | emit_cmp_and_jump_insns (force_reg (SImode, andop), const0_rtx, EQ, | |
2ef7687b | 2070 | NULL_RTX, Pmode, 1, ok_label); |
2071 | jmp = get_last_insn (); | |
2072 | gcc_assert (JUMP_P (jmp)); | |
2073 | ||
d0df4894 | 2074 | predict_insn_def (jmp, PRED_NORETURN, TAKEN); |
2ef7687b | 2075 | expand_builtin_trap (); |
2076 | emit_label (ok_label); | |
2077 | } | |
2078 | ||
72db90ce | 2079 | /* Expand a return insn (just one insn) marked as using SRP or stack |
2080 | slot depending on parameter ON_STACK. */ | |
2081 | ||
2082 | void | |
2083 | cris_expand_return (bool on_stack) | |
2084 | { | |
2085 | /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to | |
2086 | tell "ret" from "jump [sp+]". Some, but not all, other parts of | |
2087 | GCC expect just (return) to do the right thing when optimizing, so | |
2088 | we do that until they're fixed. Currently, all return insns in a | |
2089 | function must be the same (not really a limiting factor) so we need | |
2090 | to check that it doesn't change half-way through. */ | |
1a860023 | 2091 | emit_jump_insn (ret_rtx); |
72db90ce | 2092 | |
c14afa19 | 2093 | CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_RET || !on_stack); |
2094 | CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_JUMP || on_stack); | |
72db90ce | 2095 | |
2096 | cfun->machine->return_type | |
2097 | = on_stack ? CRIS_RETINSN_JUMP : CRIS_RETINSN_RET; | |
e03f789f | 2098 | } |
2099 | ||
fab7adbf | 2100 | /* Compute a (partial) cost for rtx X. Return true if the complete |
2101 | cost has been computed, and false if subexpressions should be | |
2102 | scanned. In either case, *TOTAL contains the cost result. */ | |
2103 | ||
2104 | static bool | |
20d892d1 | 2105 | cris_rtx_costs (rtx x, int code, int outer_code, int opno, int *total, |
f529eb25 | 2106 | bool speed) |
fab7adbf | 2107 | { |
2108 | switch (code) | |
2109 | { | |
2110 | case CONST_INT: | |
2111 | { | |
2112 | HOST_WIDE_INT val = INTVAL (x); | |
2113 | if (val == 0) | |
2114 | *total = 0; | |
2115 | else if (val < 32 && val >= -32) | |
2116 | *total = 1; | |
2117 | /* Eight or 16 bits are a word and cycle more expensive. */ | |
2118 | else if (val <= 32767 && val >= -32768) | |
2119 | *total = 2; | |
5b865faf | 2120 | /* A 32-bit constant (or very seldom, unsigned 16 bits) costs |
fab7adbf | 2121 | another word. FIXME: This isn't linear to 16 bits. */ |
2122 | else | |
2123 | *total = 4; | |
2124 | return true; | |
2125 | } | |
2126 | ||
2127 | case LABEL_REF: | |
2128 | *total = 6; | |
2129 | return true; | |
2130 | ||
2131 | case CONST: | |
2132 | case SYMBOL_REF: | |
6a6dcc7c | 2133 | *total = 6; |
fab7adbf | 2134 | return true; |
2135 | ||
2136 | case CONST_DOUBLE: | |
2137 | if (x != CONST0_RTX (GET_MODE (x) == VOIDmode ? DImode : GET_MODE (x))) | |
2138 | *total = 12; | |
2139 | else | |
2140 | /* Make 0.0 cheap, else test-insns will not be used. */ | |
2141 | *total = 0; | |
2142 | return true; | |
2143 | ||
2144 | case MULT: | |
2082fc3b | 2145 | /* If we have one arm of an ADDI, make sure it gets the cost of |
2146 | one insn, i.e. zero cost for this operand, and just the cost | |
2147 | of the PLUS, as the insn is created by combine from a PLUS | |
2148 | and an ASHIFT, and the MULT cost below would make the | |
2149 | combined value be larger than the separate insns. The insn | |
2150 | validity is checked elsewhere by combine. | |
2151 | ||
2152 | FIXME: this case is a stop-gap for 4.3 and 4.4, this whole | |
2153 | function should be rewritten. */ | |
5b96044e | 2154 | if (outer_code == PLUS && cris_biap_index_p (x, false)) |
2082fc3b | 2155 | { |
2156 | *total = 0; | |
2157 | return true; | |
2158 | } | |
2159 | ||
fab7adbf | 2160 | /* Identify values that are no powers of two. Powers of 2 are |
2161 | taken care of already and those values should not be changed. */ | |
683d2985 | 2162 | if (!CONST_INT_P (XEXP (x, 1)) |
fab7adbf | 2163 | || exact_log2 (INTVAL (XEXP (x, 1)) < 0)) |
2164 | { | |
2165 | /* If we have a multiply insn, then the cost is between | |
2166 | 1 and 2 "fast" instructions. */ | |
2167 | if (TARGET_HAS_MUL_INSNS) | |
2168 | { | |
2169 | *total = COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2; | |
2170 | return true; | |
2171 | } | |
2172 | ||
2173 | /* Estimate as 4 + 4 * #ofbits. */ | |
2174 | *total = COSTS_N_INSNS (132); | |
2175 | return true; | |
2176 | } | |
2177 | return false; | |
2178 | ||
2179 | case UDIV: | |
2180 | case MOD: | |
2181 | case UMOD: | |
2182 | case DIV: | |
683d2985 | 2183 | if (!CONST_INT_P (XEXP (x, 1)) |
9d6707d3 | 2184 | || exact_log2 (INTVAL (XEXP (x, 1)) < 0)) |
fab7adbf | 2185 | { |
2186 | /* Estimate this as 4 + 8 * #of bits. */ | |
2187 | *total = COSTS_N_INSNS (260); | |
2188 | return true; | |
2189 | } | |
2190 | return false; | |
2191 | ||
2192 | case AND: | |
683d2985 | 2193 | if (CONST_INT_P (XEXP (x, 1)) |
fab7adbf | 2194 | /* Two constants may actually happen before optimization. */ |
683d2985 | 2195 | && !CONST_INT_P (XEXP (x, 0)) |
83ba0b6d | 2196 | && !satisfies_constraint_I (XEXP (x, 1))) |
fab7adbf | 2197 | { |
39e09a0c | 2198 | *total |
20d892d1 | 2199 | = (rtx_cost (XEXP (x, 0), (enum rtx_code) outer_code, |
2200 | opno, speed) + 2 | |
39e09a0c | 2201 | + 2 * GET_MODE_NUNITS (GET_MODE (XEXP (x, 0)))); |
fab7adbf | 2202 | return true; |
2203 | } | |
2204 | return false; | |
2205 | ||
74f4459c | 2206 | case ZERO_EXTRACT: |
2207 | if (outer_code != COMPARE) | |
2208 | return false; | |
2209 | /* fall through */ | |
2210 | ||
fab7adbf | 2211 | case ZERO_EXTEND: case SIGN_EXTEND: |
20d892d1 | 2212 | *total = rtx_cost (XEXP (x, 0), (enum rtx_code) outer_code, opno, speed); |
fab7adbf | 2213 | return true; |
2214 | ||
2215 | default: | |
2216 | return false; | |
2217 | } | |
2218 | } | |
2219 | ||
e03f789f | 2220 | /* The ADDRESS_COST worker. */ |
2221 | ||
9517cd99 | 2222 | static int |
3754d046 | 2223 | cris_address_cost (rtx x, machine_mode mode ATTRIBUTE_UNUSED, |
d9c5e5f4 | 2224 | addr_space_t as ATTRIBUTE_UNUSED, |
2225 | bool speed ATTRIBUTE_UNUSED) | |
e03f789f | 2226 | { |
2227 | /* The metric to use for the cost-macros is unclear. | |
2228 | The metric used here is (the number of cycles needed) / 2, | |
2229 | where we consider equal a cycle for a word of code and a cycle to | |
a3d70904 | 2230 | read memory. FIXME: Adding "+ 1" to all values would avoid |
2231 | returning 0, as tree-ssa-loop-ivopts.c as of r128272 "normalizes" | |
2232 | 0 to 1, thereby giving equal costs to [rN + rM] and [rN]. | |
2233 | Unfortunately(?) such a hack would expose other pessimizations, | |
2234 | at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the | |
2235 | loop there, without apparent reason. */ | |
e03f789f | 2236 | |
2237 | /* The cheapest addressing modes get 0, since nothing extra is needed. */ | |
5b96044e | 2238 | if (cris_base_or_autoincr_p (x, false)) |
e03f789f | 2239 | return 0; |
2240 | ||
2241 | /* An indirect mem must be a DIP. This means two bytes extra for code, | |
2242 | and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */ | |
683d2985 | 2243 | if (MEM_P (x)) |
e03f789f | 2244 | return (2 + 4) / 2; |
2245 | ||
2246 | /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs | |
6a6dcc7c | 2247 | an extra DIP prefix and 4 bytes of constant in most cases. */ |
e03f789f | 2248 | if (CONSTANT_P (x)) |
6a6dcc7c | 2249 | return (2 + 4) / 2; |
e03f789f | 2250 | |
2251 | /* Handle BIAP and BDAP prefixes. */ | |
2252 | if (GET_CODE (x) == PLUS) | |
2253 | { | |
2254 | rtx tem1 = XEXP (x, 0); | |
2255 | rtx tem2 = XEXP (x, 1); | |
2256 | ||
fbedf334 | 2257 | /* Local extended canonicalization rule: the first operand must |
2258 | be REG, unless it's an operation (MULT). */ | |
2259 | if (!REG_P (tem1) && GET_CODE (tem1) != MULT) | |
2260 | tem1 = tem2, tem2 = XEXP (x, 0); | |
2261 | ||
2262 | /* We'll "assume" we have canonical RTX now. */ | |
a3d70904 | 2263 | gcc_assert (REG_P (tem1) || GET_CODE (tem1) == MULT); |
e03f789f | 2264 | |
a3d70904 | 2265 | /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We |
2266 | recognize the typical MULT which is always in tem1 because of | |
2267 | insn canonicalization. */ | |
5b96044e | 2268 | if ((GET_CODE (tem1) == MULT && cris_biap_index_p (tem1, false)) |
a3d70904 | 2269 | || REG_P (tem2)) |
2270 | return 2 / 2; | |
2271 | ||
2272 | /* A BDAP (quick) is 2 extra bytes. Any constant operand to the | |
2273 | PLUS is always found in tem2. */ | |
2274 | if (CONST_INT_P (tem2) && INTVAL (tem2) < 128 && INTVAL (tem2) >= -128) | |
2275 | return 2 / 2; | |
2276 | ||
2277 | /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra | |
2278 | bytes. */ | |
83ba0b6d | 2279 | if (satisfies_constraint_L (tem2)) |
a3d70904 | 2280 | return (2 + 2) / 2; |
2281 | ||
2282 | /* A BDAP with some other constant is 2 bytes extra. */ | |
f69bb65a | 2283 | if (CRIS_CONSTANT_P (tem2)) |
a3d70904 | 2284 | return (2 + 2 + 2) / 2; |
2285 | ||
2286 | /* BDAP with something indirect should have a higher cost than | |
2287 | BIAP with register. FIXME: Should it cost like a MEM or more? */ | |
2288 | return (2 + 2 + 2) / 2; | |
2289 | } | |
e03f789f | 2290 | |
2291 | /* What else? Return a high cost. It matters only for valid | |
2292 | addressing modes. */ | |
2293 | return 10; | |
2294 | } | |
2295 | ||
2296 | /* Check various objections to the side-effect. Used in the test-part | |
2297 | of an anonymous insn describing an insn with a possible side-effect. | |
2298 | Returns nonzero if the implied side-effect is ok. | |
2299 | ||
2300 | code : PLUS or MULT | |
2301 | ops : An array of rtx:es. lreg, rreg, rval, | |
2302 | The variables multop and other_op are indexes into this, | |
2303 | or -1 if they are not applicable. | |
2304 | lreg : The register that gets assigned in the side-effect. | |
2305 | rreg : One register in the side-effect expression | |
2306 | rval : The other register, or an int. | |
2307 | multop : An integer to multiply rval with. | |
2308 | other_op : One of the entities of the main effect, | |
2309 | whose mode we must consider. */ | |
2310 | ||
2311 | int | |
21f64ad5 | 2312 | cris_side_effect_mode_ok (enum rtx_code code, rtx *ops, |
2313 | int lreg, int rreg, int rval, | |
2314 | int multop, int other_op) | |
e03f789f | 2315 | { |
2316 | /* Find what value to multiply with, for rx =ry + rz * n. */ | |
2317 | int mult = multop < 0 ? 1 : INTVAL (ops[multop]); | |
2318 | ||
2319 | rtx reg_rtx = ops[rreg]; | |
2320 | rtx val_rtx = ops[rval]; | |
2321 | ||
2322 | /* The operands may be swapped. Canonicalize them in reg_rtx and | |
2323 | val_rtx, where reg_rtx always is a reg (for this constraint to | |
2324 | match). */ | |
5b96044e | 2325 | if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed)) |
e03f789f | 2326 | reg_rtx = val_rtx, val_rtx = ops[rreg]; |
2327 | ||
2328 | /* Don't forget to check that reg_rtx really is a reg. If it isn't, | |
2329 | we have no business. */ | |
5b96044e | 2330 | if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed)) |
e03f789f | 2331 | return 0; |
2332 | ||
2333 | /* Don't do this when -mno-split. */ | |
2334 | if (!TARGET_SIDE_EFFECT_PREFIXES) | |
2335 | return 0; | |
2336 | ||
2337 | /* The mult expression may be hidden in lreg. FIXME: Add more | |
2338 | commentary about that. */ | |
2339 | if (GET_CODE (val_rtx) == MULT) | |
2340 | { | |
2341 | mult = INTVAL (XEXP (val_rtx, 1)); | |
2342 | val_rtx = XEXP (val_rtx, 0); | |
2343 | code = MULT; | |
2344 | } | |
2345 | ||
2346 | /* First check the "other operand". */ | |
2347 | if (other_op >= 0) | |
2348 | { | |
2349 | if (GET_MODE_SIZE (GET_MODE (ops[other_op])) > UNITS_PER_WORD) | |
2350 | return 0; | |
2351 | ||
2352 | /* Check if the lvalue register is the same as the "other | |
2353 | operand". If so, the result is undefined and we shouldn't do | |
2354 | this. FIXME: Check again. */ | |
5b96044e | 2355 | if ((cris_base_p (ops[lreg], reload_in_progress || reload_completed) |
2356 | && cris_base_p (ops[other_op], | |
2357 | reload_in_progress || reload_completed) | |
e03f789f | 2358 | && REGNO (ops[lreg]) == REGNO (ops[other_op])) |
2359 | || rtx_equal_p (ops[other_op], ops[lreg])) | |
2360 | return 0; | |
2361 | } | |
2362 | ||
2363 | /* Do not accept frame_pointer_rtx as any operand. */ | |
2364 | if (ops[lreg] == frame_pointer_rtx || ops[rreg] == frame_pointer_rtx | |
2365 | || ops[rval] == frame_pointer_rtx | |
2366 | || (other_op >= 0 && ops[other_op] == frame_pointer_rtx)) | |
2367 | return 0; | |
2368 | ||
2369 | if (code == PLUS | |
5b96044e | 2370 | && ! cris_base_p (val_rtx, reload_in_progress || reload_completed)) |
e03f789f | 2371 | { |
2372 | ||
2373 | /* Do not allow rx = rx + n if a normal add or sub with same size | |
2374 | would do. */ | |
2375 | if (rtx_equal_p (ops[lreg], reg_rtx) | |
683d2985 | 2376 | && CONST_INT_P (val_rtx) |
e03f789f | 2377 | && (INTVAL (val_rtx) <= 63 && INTVAL (val_rtx) >= -63)) |
2378 | return 0; | |
2379 | ||
6a6dcc7c | 2380 | /* Check allowed cases, like [r(+)?].[bwd] and const. */ |
f69bb65a | 2381 | if (CRIS_CONSTANT_P (val_rtx)) |
6a6dcc7c | 2382 | return 1; |
e03f789f | 2383 | |
5b96044e | 2384 | if (MEM_P (val_rtx) |
2385 | && cris_base_or_autoincr_p (XEXP (val_rtx, 0), | |
2386 | reload_in_progress || reload_completed)) | |
e03f789f | 2387 | return 1; |
2388 | ||
2389 | if (GET_CODE (val_rtx) == SIGN_EXTEND | |
683d2985 | 2390 | && MEM_P (XEXP (val_rtx, 0)) |
5b96044e | 2391 | && cris_base_or_autoincr_p (XEXP (XEXP (val_rtx, 0), 0), |
2392 | reload_in_progress || reload_completed)) | |
e03f789f | 2393 | return 1; |
2394 | ||
2395 | /* If we got here, it's not a valid addressing mode. */ | |
2396 | return 0; | |
2397 | } | |
2398 | else if (code == MULT | |
5b96044e | 2399 | || (code == PLUS |
2400 | && cris_base_p (val_rtx, | |
2401 | reload_in_progress || reload_completed))) | |
e03f789f | 2402 | { |
2403 | /* Do not allow rx = rx + ry.S, since it doesn't give better code. */ | |
2404 | if (rtx_equal_p (ops[lreg], reg_rtx) | |
2405 | || (mult == 1 && rtx_equal_p (ops[lreg], val_rtx))) | |
2406 | return 0; | |
2407 | ||
2408 | /* Do not allow bad multiply-values. */ | |
2409 | if (mult != 1 && mult != 2 && mult != 4) | |
2410 | return 0; | |
2411 | ||
2412 | /* Only allow r + ... */ | |
5b96044e | 2413 | if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed)) |
e03f789f | 2414 | return 0; |
2415 | ||
2416 | /* If we got here, all seems ok. | |
2417 | (All checks need to be done above). */ | |
2418 | return 1; | |
2419 | } | |
2420 | ||
2421 | /* If we get here, the caller got its initial tests wrong. */ | |
68435912 | 2422 | internal_error ("internal error: cris_side_effect_mode_ok with bad operands"); |
e03f789f | 2423 | } |
2424 | ||
c85bb9fb | 2425 | /* Whether next_cc0_user of insn is LE or GT or requires a real compare |
2426 | insn for other reasons. */ | |
2427 | ||
2428 | bool | |
2429 | cris_cc0_user_requires_cmp (rtx insn) | |
2430 | { | |
50fc2d35 | 2431 | rtx_insn *cc0_user = NULL; |
c85bb9fb | 2432 | rtx body; |
2433 | rtx set; | |
2434 | ||
2435 | gcc_assert (insn != NULL); | |
2436 | ||
2437 | if (!TARGET_V32) | |
2438 | return false; | |
2439 | ||
2440 | cc0_user = next_cc0_user (insn); | |
2441 | if (cc0_user == NULL) | |
2442 | return false; | |
2443 | ||
2444 | body = PATTERN (cc0_user); | |
2445 | set = single_set (cc0_user); | |
2446 | ||
2447 | /* Users can be sCC and bCC. */ | |
2448 | if (JUMP_P (cc0_user) | |
2449 | && GET_CODE (body) == SET | |
2450 | && SET_DEST (body) == pc_rtx | |
2451 | && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE | |
2452 | && XEXP (XEXP (SET_SRC (body), 0), 0) == cc0_rtx) | |
2453 | { | |
2454 | return | |
2455 | GET_CODE (XEXP (SET_SRC (body), 0)) == GT | |
2456 | || GET_CODE (XEXP (SET_SRC (body), 0)) == LE; | |
2457 | } | |
2458 | else if (set) | |
2459 | { | |
2460 | return | |
2461 | GET_CODE (SET_SRC (body)) == GT | |
2462 | || GET_CODE (SET_SRC (body)) == LE; | |
2463 | } | |
2464 | ||
2465 | gcc_unreachable (); | |
2466 | } | |
2467 | ||
e03f789f | 2468 | /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16) |
2469 | does not handle the case where the IN operand is strict_low_part; it | |
2470 | does handle it for X. Test-case in Axis-20010516. This function takes | |
2471 | care of that for THIS port. FIXME: strict_low_part is going away | |
2472 | anyway. */ | |
2473 | ||
2474 | static int | |
21f64ad5 | 2475 | cris_reg_overlap_mentioned_p (rtx x, rtx in) |
e03f789f | 2476 | { |
2477 | /* The function reg_overlap_mentioned now handles when X is | |
2478 | strict_low_part, but not when IN is a STRICT_LOW_PART. */ | |
2479 | if (GET_CODE (in) == STRICT_LOW_PART) | |
2480 | in = XEXP (in, 0); | |
2481 | ||
2482 | return reg_overlap_mentioned_p (x, in); | |
2483 | } | |
2484 | ||
c85bb9fb | 2485 | /* Return TRUE iff X is a CONST valid for e.g. indexing. |
2486 | ANY_OPERAND is 0 if X is in a CALL_P insn or movsi, 1 | |
2487 | elsewhere. */ | |
e03f789f | 2488 | |
6a6dcc7c | 2489 | bool |
5b96044e | 2490 | cris_valid_pic_const (const_rtx x, bool any_operand) |
e03f789f | 2491 | { |
6a6dcc7c | 2492 | gcc_assert (flag_pic); |
e03f789f | 2493 | |
e03f789f | 2494 | switch (GET_CODE (x)) |
2495 | { | |
e03f789f | 2496 | case CONST_INT: |
2497 | case CONST_DOUBLE: | |
6a6dcc7c | 2498 | return true; |
e03f789f | 2499 | default: |
6a6dcc7c | 2500 | ; |
e03f789f | 2501 | } |
2502 | ||
6a6dcc7c | 2503 | if (GET_CODE (x) != CONST) |
2504 | return false; | |
2505 | ||
2506 | x = XEXP (x, 0); | |
2507 | ||
2508 | /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */ | |
2509 | if (GET_CODE (x) == PLUS | |
2510 | && GET_CODE (XEXP (x, 0)) == UNSPEC | |
c85bb9fb | 2511 | && (XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREL |
2512 | || XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_PCREL) | |
683d2985 | 2513 | && CONST_INT_P (XEXP (x, 1))) |
6a6dcc7c | 2514 | x = XEXP (x, 0); |
2515 | ||
2516 | if (GET_CODE (x) == UNSPEC) | |
2517 | switch (XINT (x, 1)) | |
2518 | { | |
c85bb9fb | 2519 | /* A PCREL operand is only valid for call and movsi. */ |
2520 | case CRIS_UNSPEC_PLT_PCREL: | |
2521 | case CRIS_UNSPEC_PCREL: | |
2522 | return !any_operand; | |
2523 | ||
2524 | case CRIS_UNSPEC_PLT_GOTREL: | |
6a6dcc7c | 2525 | case CRIS_UNSPEC_PLTGOTREAD: |
2526 | case CRIS_UNSPEC_GOTREAD: | |
2527 | case CRIS_UNSPEC_GOTREL: | |
2528 | return true; | |
2529 | default: | |
2530 | gcc_unreachable (); | |
2531 | } | |
2532 | ||
f69bb65a | 2533 | return cris_symbol_type_of (x) == cris_no_symbol; |
e03f789f | 2534 | } |
2535 | ||
f69bb65a | 2536 | /* Helper function to find the right symbol-type to generate, |
6a6dcc7c | 2537 | given the original (non-PIC) representation. */ |
e03f789f | 2538 | |
f69bb65a | 2539 | enum cris_symbol_type |
2540 | cris_symbol_type_of (const_rtx x) | |
e03f789f | 2541 | { |
2542 | switch (GET_CODE (x)) | |
2543 | { | |
e03f789f | 2544 | case SYMBOL_REF: |
f69bb65a | 2545 | return flag_pic |
2546 | ? (SYMBOL_REF_LOCAL_P (x) | |
2547 | ? cris_rel_symbol : cris_got_symbol) | |
2548 | : cris_offsettable_symbol; | |
e03f789f | 2549 | |
2550 | case LABEL_REF: | |
f69bb65a | 2551 | return flag_pic ? cris_rel_symbol : cris_offsettable_symbol; |
e03f789f | 2552 | |
2553 | case CONST: | |
f69bb65a | 2554 | return cris_symbol_type_of (XEXP (x, 0)); |
e03f789f | 2555 | |
2556 | case PLUS: | |
2557 | case MINUS: | |
2558 | { | |
f69bb65a | 2559 | enum cris_symbol_type t1 = cris_symbol_type_of (XEXP (x, 0)); |
2560 | enum cris_symbol_type t2 = cris_symbol_type_of (XEXP (x, 1)); | |
6a6dcc7c | 2561 | |
2562 | gcc_assert (t1 == cris_no_symbol || t2 == cris_no_symbol); | |
2563 | ||
e4442746 | 2564 | if (t1 == cris_got_symbol || t2 == cris_got_symbol) |
6a6dcc7c | 2565 | return cris_got_symbol_needing_fixup; |
2566 | ||
2567 | return t1 != cris_no_symbol ? t1 : t2; | |
e03f789f | 2568 | } |
2569 | ||
2570 | case CONST_INT: | |
2571 | case CONST_DOUBLE: | |
6a6dcc7c | 2572 | return cris_no_symbol; |
2573 | ||
2574 | case UNSPEC: | |
f69bb65a | 2575 | return cris_unspec; |
e03f789f | 2576 | |
2577 | default: | |
68435912 | 2578 | fatal_insn ("unrecognized supposed constant", x); |
e03f789f | 2579 | } |
2580 | ||
6a6dcc7c | 2581 | gcc_unreachable (); |
e03f789f | 2582 | } |
2583 | ||
6a6dcc7c | 2584 | /* The LEGITIMATE_PIC_OPERAND_P worker. */ |
e03f789f | 2585 | |
2586 | int | |
6a6dcc7c | 2587 | cris_legitimate_pic_operand (rtx x) |
e03f789f | 2588 | { |
6a6dcc7c | 2589 | /* Symbols are not valid PIC operands as-is; just constants. */ |
c85bb9fb | 2590 | return cris_valid_pic_const (x, true); |
2591 | } | |
2592 | ||
367b1459 | 2593 | /* Queue an .ident string in the queue of top-level asm statements. |
2594 | If the front-end is done, we must be being called from toplev.c. | |
2595 | In that case, do nothing. */ | |
2596 | void | |
2597 | cris_asm_output_ident (const char *string) | |
2598 | { | |
35ee1c66 | 2599 | if (symtab->state != PARSING) |
367b1459 | 2600 | return; |
2601 | ||
2602 | default_asm_output_ident_directive (string); | |
2603 | } | |
2604 | ||
c85bb9fb | 2605 | /* The ASM_OUTPUT_CASE_END worker. */ |
2606 | ||
2607 | void | |
2608 | cris_asm_output_case_end (FILE *stream, int num, rtx table) | |
2609 | { | |
18425913 | 2610 | /* Step back, over the label for the table, to the actual casejump and |
2611 | assert that we find only what's expected. */ | |
2612 | rtx whole_jump_insn = prev_nonnote_nondebug_insn (table); | |
2613 | gcc_assert (whole_jump_insn != NULL_RTX && LABEL_P (whole_jump_insn)); | |
2614 | whole_jump_insn = prev_nonnote_nondebug_insn (whole_jump_insn); | |
2615 | gcc_assert (whole_jump_insn != NULL_RTX | |
2616 | && (JUMP_P (whole_jump_insn) | |
2617 | || (TARGET_V32 && INSN_P (whole_jump_insn) | |
2618 | && GET_CODE (PATTERN (whole_jump_insn)) == SEQUENCE))); | |
2619 | /* Get the pattern of the casejump, so we can extract the default label. */ | |
2620 | whole_jump_insn = PATTERN (whole_jump_insn); | |
2621 | ||
c85bb9fb | 2622 | if (TARGET_V32) |
2623 | { | |
c85bb9fb | 2624 | /* This can be a SEQUENCE, meaning the delay-slot of the jump is |
18425913 | 2625 | filled. We also output the offset word a little differently. */ |
c85bb9fb | 2626 | rtx parallel_jump |
2627 | = (GET_CODE (whole_jump_insn) == SEQUENCE | |
2628 | ? PATTERN (XVECEXP (whole_jump_insn, 0, 0)) : whole_jump_insn); | |
2629 | ||
2630 | asm_fprintf (stream, | |
2631 | "\t.word %LL%d-.%s\n", | |
2632 | CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (XVECEXP | |
2633 | (parallel_jump, 0, 0), | |
2634 | 1), 2), 0)), | |
2635 | (TARGET_PDEBUG ? "; default" : "")); | |
2636 | return; | |
2637 | } | |
2638 | ||
2639 | asm_fprintf (stream, | |
2640 | "\t.word %LL%d-%LL%d%s\n", | |
2641 | CODE_LABEL_NUMBER (XEXP | |
2642 | (XEXP | |
18425913 | 2643 | (XEXP (XVECEXP (whole_jump_insn, 0, 0), 1), |
c85bb9fb | 2644 | 2), 0)), |
2645 | num, | |
2646 | (TARGET_PDEBUG ? "; default" : "")); | |
e03f789f | 2647 | } |
2648 | ||
4c834714 | 2649 | /* The TARGET_OPTION_OVERRIDE worker. |
e03f789f | 2650 | As is the norm, this also parses -mfoo=bar type parameters. */ |
2651 | ||
4c834714 | 2652 | static void |
2653 | cris_option_override (void) | |
e03f789f | 2654 | { |
2655 | if (cris_max_stackframe_str) | |
2656 | { | |
2657 | cris_max_stackframe = atoi (cris_max_stackframe_str); | |
2658 | ||
2659 | /* Do some sanity checking. */ | |
2660 | if (cris_max_stackframe < 0 || cris_max_stackframe > 0x20000000) | |
2661 | internal_error ("-max-stackframe=%d is not usable, not between 0 and %d", | |
2662 | cris_max_stackframe, 0x20000000); | |
2663 | } | |
2664 | ||
2665 | /* Let "-metrax4" and "-metrax100" change the cpu version. */ | |
2666 | if (TARGET_SVINTO && cris_cpu_version < CRIS_CPU_SVINTO) | |
2667 | cris_cpu_version = CRIS_CPU_SVINTO; | |
2668 | else if (TARGET_ETRAX4_ADD && cris_cpu_version < CRIS_CPU_ETRAX4) | |
2669 | cris_cpu_version = CRIS_CPU_ETRAX4; | |
2670 | ||
2671 | /* Parse -march=... and its synonym, the deprecated -mcpu=... */ | |
2672 | if (cris_cpu_str) | |
2673 | { | |
2674 | cris_cpu_version | |
2675 | = (*cris_cpu_str == 'v' ? atoi (cris_cpu_str + 1) : -1); | |
2676 | ||
2677 | if (strcmp ("etrax4", cris_cpu_str) == 0) | |
2678 | cris_cpu_version = 3; | |
2679 | ||
2680 | if (strcmp ("svinto", cris_cpu_str) == 0 | |
2681 | || strcmp ("etrax100", cris_cpu_str) == 0) | |
2682 | cris_cpu_version = 8; | |
2683 | ||
2684 | if (strcmp ("ng", cris_cpu_str) == 0 | |
2685 | || strcmp ("etrax100lx", cris_cpu_str) == 0) | |
2686 | cris_cpu_version = 10; | |
2687 | ||
c85bb9fb | 2688 | if (cris_cpu_version < 0 || cris_cpu_version > 32) |
68435912 | 2689 | error ("unknown CRIS version specification in -march= or -mcpu= : %s", |
e03f789f | 2690 | cris_cpu_str); |
2691 | ||
2692 | /* Set the target flags. */ | |
2693 | if (cris_cpu_version >= CRIS_CPU_ETRAX4) | |
c419af1d | 2694 | target_flags |= MASK_ETRAX4_ADD; |
e03f789f | 2695 | |
2696 | /* If this is Svinto or higher, align for 32 bit accesses. */ | |
2697 | if (cris_cpu_version >= CRIS_CPU_SVINTO) | |
2698 | target_flags | |
c419af1d | 2699 | |= (MASK_SVINTO | MASK_ALIGN_BY_32 |
2700 | | MASK_STACK_ALIGN | MASK_CONST_ALIGN | |
2701 | | MASK_DATA_ALIGN); | |
e03f789f | 2702 | |
2703 | /* Note that we do not add new flags when it can be completely | |
2704 | described with a macro that uses -mcpu=X. So | |
2705 | TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */ | |
2706 | } | |
2707 | ||
2708 | if (cris_tune_str) | |
2709 | { | |
2710 | int cris_tune | |
2711 | = (*cris_tune_str == 'v' ? atoi (cris_tune_str + 1) : -1); | |
2712 | ||
2713 | if (strcmp ("etrax4", cris_tune_str) == 0) | |
2714 | cris_tune = 3; | |
2715 | ||
2716 | if (strcmp ("svinto", cris_tune_str) == 0 | |
2717 | || strcmp ("etrax100", cris_tune_str) == 0) | |
2718 | cris_tune = 8; | |
2719 | ||
2720 | if (strcmp ("ng", cris_tune_str) == 0 | |
2721 | || strcmp ("etrax100lx", cris_tune_str) == 0) | |
2722 | cris_tune = 10; | |
2723 | ||
c85bb9fb | 2724 | if (cris_tune < 0 || cris_tune > 32) |
68435912 | 2725 | error ("unknown CRIS cpu version specification in -mtune= : %s", |
e03f789f | 2726 | cris_tune_str); |
2727 | ||
2728 | if (cris_tune >= CRIS_CPU_SVINTO) | |
2729 | /* We have currently nothing more to tune than alignment for | |
2730 | memory accesses. */ | |
2731 | target_flags | |
c419af1d | 2732 | |= (MASK_STACK_ALIGN | MASK_CONST_ALIGN |
2733 | | MASK_DATA_ALIGN | MASK_ALIGN_BY_32); | |
e03f789f | 2734 | } |
2735 | ||
c85bb9fb | 2736 | if (cris_cpu_version >= CRIS_CPU_V32) |
2737 | target_flags &= ~(MASK_SIDE_EFFECT_PREFIXES|MASK_MUL_BUG); | |
2738 | ||
e03f789f | 2739 | if (flag_pic) |
2740 | { | |
2741 | /* Use error rather than warning, so invalid use is easily | |
2742 | detectable. Still change to the values we expect, to avoid | |
2743 | further errors. */ | |
2744 | if (! TARGET_LINUX) | |
2745 | { | |
0fb176ea | 2746 | error ("-fPIC and -fpic are not supported in this configuration"); |
e03f789f | 2747 | flag_pic = 0; |
2748 | } | |
2749 | ||
2750 | /* Turn off function CSE. We need to have the addresses reach the | |
2751 | call expanders to get PLT-marked, as they could otherwise be | |
2752 | compared against zero directly or indirectly. After visiting the | |
2753 | call expanders they will then be cse:ed, as the call expanders | |
2754 | force_reg the addresses, effectively forcing flag_no_function_cse | |
2755 | to 0. */ | |
2756 | flag_no_function_cse = 1; | |
2757 | } | |
2758 | ||
e03f789f | 2759 | /* Set the per-function-data initializer. */ |
2760 | init_machine_status = cris_init_machine_status; | |
2761 | } | |
2762 | ||
e7f5e241 | 2763 | /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */ |
e03f789f | 2764 | |
6988553d | 2765 | static void |
21f64ad5 | 2766 | cris_asm_output_mi_thunk (FILE *stream, |
2767 | tree thunkdecl ATTRIBUTE_UNUSED, | |
2768 | HOST_WIDE_INT delta, | |
2769 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
2770 | tree funcdecl) | |
e03f789f | 2771 | { |
1675d36d | 2772 | /* Make sure unwind info is emitted for the thunk if needed. */ |
2773 | final_start_function (emit_barrier (), stream, 1); | |
2774 | ||
e03f789f | 2775 | if (delta > 0) |
4840a03a | 2776 | fprintf (stream, "\tadd%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n", |
2777 | ADDITIVE_SIZE_MODIFIER (delta), delta, | |
2778 | reg_names[CRIS_FIRST_ARG_REG]); | |
e03f789f | 2779 | else if (delta < 0) |
4840a03a | 2780 | fprintf (stream, "\tsub%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n", |
2781 | ADDITIVE_SIZE_MODIFIER (-delta), -delta, | |
2782 | reg_names[CRIS_FIRST_ARG_REG]); | |
e03f789f | 2783 | |
2784 | if (flag_pic) | |
2785 | { | |
2786 | const char *name = XSTR (XEXP (DECL_RTL (funcdecl), 0), 0); | |
2787 | ||
7b4a38a6 | 2788 | name = (* targetm.strip_name_encoding) (name); |
c85bb9fb | 2789 | |
2790 | if (TARGET_V32) | |
2791 | { | |
2792 | fprintf (stream, "\tba "); | |
2793 | assemble_name (stream, name); | |
2794 | fprintf (stream, "%s\n", CRIS_PLT_PCOFFSET_SUFFIX); | |
2795 | } | |
2796 | else | |
2797 | { | |
2798 | fprintf (stream, "add.d "); | |
2799 | assemble_name (stream, name); | |
2800 | fprintf (stream, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX); | |
2801 | } | |
e03f789f | 2802 | } |
2803 | else | |
2804 | { | |
2805 | fprintf (stream, "jump "); | |
2806 | assemble_name (stream, XSTR (XEXP (DECL_RTL (funcdecl), 0), 0)); | |
2807 | fprintf (stream, "\n"); | |
c85bb9fb | 2808 | |
2809 | if (TARGET_V32) | |
2810 | fprintf (stream, "\tnop\n"); | |
e03f789f | 2811 | } |
1675d36d | 2812 | |
2813 | final_end_function (); | |
e03f789f | 2814 | } |
2815 | ||
acb2d1bb | 2816 | /* Boilerplate emitted at start of file. |
92c473b8 | 2817 | |
2818 | NO_APP *only at file start* means faster assembly. It also means | |
2819 | comments are not allowed. In some cases comments will be output | |
6df83406 | 2820 | for debugging purposes. Make sure they are allowed then. */ |
92c473b8 | 2821 | static void |
21f64ad5 | 2822 | cris_file_start (void) |
92c473b8 | 2823 | { |
2824 | /* These expressions can vary at run time, so we cannot put | |
2825 | them into TARGET_INITIALIZER. */ | |
202d6e5f | 2826 | targetm.asm_file_start_app_off = !(TARGET_PDEBUG || flag_print_asm_name); |
92c473b8 | 2827 | |
2828 | default_file_start (); | |
2829 | } | |
2830 | ||
5baeff2b | 2831 | /* Output that goes at the end of the file, similarly. */ |
2832 | ||
2833 | static void | |
2834 | cris_file_end (void) | |
2835 | { | |
2836 | /* For CRIS, the default is to assume *no* executable stack, so output | |
2837 | an executable-stack-note only when needed. */ | |
2838 | if (TARGET_LINUX && trampolines_created) | |
2839 | file_end_indicate_exec_stack (); | |
2840 | } | |
2841 | ||
f2f543a3 | 2842 | /* Rename the function calls for integer multiply and divide. */ |
2843 | static void | |
a141da51 | 2844 | cris_init_libfuncs (void) |
f2f543a3 | 2845 | { |
2846 | set_optab_libfunc (smul_optab, SImode, "__Mul"); | |
2847 | set_optab_libfunc (sdiv_optab, SImode, "__Div"); | |
2848 | set_optab_libfunc (udiv_optab, SImode, "__Udiv"); | |
2849 | set_optab_libfunc (smod_optab, SImode, "__Mod"); | |
2850 | set_optab_libfunc (umod_optab, SImode, "__Umod"); | |
102c21ad | 2851 | |
2852 | /* Atomic data being unaligned is unfortunately a reality. | |
2853 | Deal with it. */ | |
2854 | if (TARGET_ATOMICS_MAY_CALL_LIBFUNCS) | |
2855 | { | |
2856 | set_optab_libfunc (sync_compare_and_swap_optab, SImode, | |
2857 | "__cris_atcmpxchgr32"); | |
2858 | set_optab_libfunc (sync_compare_and_swap_optab, HImode, | |
2859 | "__cris_atcmpxchgr16"); | |
2860 | } | |
f2f543a3 | 2861 | } |
2862 | ||
e03f789f | 2863 | /* The INIT_EXPANDERS worker sets the per-function-data initializer and |
2864 | mark functions. */ | |
2865 | ||
2866 | void | |
21f64ad5 | 2867 | cris_init_expanders (void) |
e03f789f | 2868 | { |
2869 | /* Nothing here at the moment. */ | |
2870 | } | |
2871 | ||
2872 | /* Zero initialization is OK for all current fields. */ | |
2873 | ||
1f3233d1 | 2874 | static struct machine_function * |
21f64ad5 | 2875 | cris_init_machine_status (void) |
e03f789f | 2876 | { |
25a27413 | 2877 | return ggc_cleared_alloc<machine_function> (); |
e03f789f | 2878 | } |
2879 | ||
2880 | /* Split a 2 word move (DI or presumably DF) into component parts. | |
2881 | Originally a copy of gen_split_move_double in m32r.c. */ | |
2882 | ||
2883 | rtx | |
21f64ad5 | 2884 | cris_split_movdx (rtx *operands) |
e03f789f | 2885 | { |
3754d046 | 2886 | machine_mode mode = GET_MODE (operands[0]); |
e03f789f | 2887 | rtx dest = operands[0]; |
2888 | rtx src = operands[1]; | |
2889 | rtx val; | |
2890 | ||
7c5e81ea | 2891 | /* We used to have to handle (SUBREG (MEM)) here, but that should no |
2892 | longer happen; after reload there are no SUBREGs any more, and we're | |
2893 | only called after reload. */ | |
c14afa19 | 2894 | CRIS_ASSERT (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG); |
e03f789f | 2895 | |
2896 | start_sequence (); | |
683d2985 | 2897 | if (REG_P (dest)) |
e03f789f | 2898 | { |
2899 | int dregno = REGNO (dest); | |
2900 | ||
2901 | /* Reg-to-reg copy. */ | |
683d2985 | 2902 | if (REG_P (src)) |
e03f789f | 2903 | { |
2904 | int sregno = REGNO (src); | |
2905 | ||
2906 | int reverse = (dregno == sregno + 1); | |
2907 | ||
2908 | /* We normally copy the low-numbered register first. However, if | |
2909 | the first register operand 0 is the same as the second register of | |
2910 | operand 1, we must copy in the opposite order. */ | |
2911 | emit_insn (gen_rtx_SET (VOIDmode, | |
2912 | operand_subword (dest, reverse, TRUE, mode), | |
2913 | operand_subword (src, reverse, TRUE, mode))); | |
2914 | ||
2915 | emit_insn (gen_rtx_SET (VOIDmode, | |
2916 | operand_subword (dest, !reverse, TRUE, mode), | |
2917 | operand_subword (src, !reverse, TRUE, mode))); | |
2918 | } | |
2919 | /* Constant-to-reg copy. */ | |
683d2985 | 2920 | else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE) |
e03f789f | 2921 | { |
2922 | rtx words[2]; | |
2923 | split_double (src, &words[0], &words[1]); | |
2924 | emit_insn (gen_rtx_SET (VOIDmode, | |
2925 | operand_subword (dest, 0, TRUE, mode), | |
2926 | words[0])); | |
2927 | ||
2928 | emit_insn (gen_rtx_SET (VOIDmode, | |
2929 | operand_subword (dest, 1, TRUE, mode), | |
2930 | words[1])); | |
2931 | } | |
2932 | /* Mem-to-reg copy. */ | |
683d2985 | 2933 | else if (MEM_P (src)) |
e03f789f | 2934 | { |
2935 | /* If the high-address word is used in the address, we must load it | |
2936 | last. Otherwise, load it first. */ | |
2937 | rtx addr = XEXP (src, 0); | |
2938 | int reverse | |
2939 | = (refers_to_regno_p (dregno, dregno + 1, addr, NULL) != 0); | |
2940 | ||
7bd28bba | 2941 | /* The original code implies that we can't do |
e03f789f | 2942 | move.x [rN+],rM move.x [rN],rM+1 |
2943 | when rN is dead, because of REG_NOTES damage. That is | |
2944 | consistent with what I've seen, so don't try it. | |
2945 | ||
2946 | We have two different cases here; if the addr is POST_INC, | |
2947 | just pass it through, otherwise add constants. */ | |
2948 | ||
2949 | if (GET_CODE (addr) == POST_INC) | |
2950 | { | |
32c277e4 | 2951 | rtx mem; |
2952 | rtx insn; | |
2953 | ||
2954 | /* Whenever we emit insns with post-incremented | |
2955 | addresses ourselves, we must add a post-inc note | |
2956 | manually. */ | |
2957 | mem = change_address (src, SImode, addr); | |
2958 | insn | |
2959 | = gen_rtx_SET (VOIDmode, | |
2960 | operand_subword (dest, 0, TRUE, mode), mem); | |
2961 | insn = emit_insn (insn); | |
2962 | if (GET_CODE (XEXP (mem, 0)) == POST_INC) | |
2963 | REG_NOTES (insn) | |
2964 | = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), | |
2965 | REG_NOTES (insn)); | |
2966 | ||
c85bb9fb | 2967 | mem = copy_rtx (mem); |
32c277e4 | 2968 | insn |
2969 | = gen_rtx_SET (VOIDmode, | |
2970 | operand_subword (dest, 1, TRUE, mode), mem); | |
2971 | insn = emit_insn (insn); | |
2972 | if (GET_CODE (XEXP (mem, 0)) == POST_INC) | |
2973 | REG_NOTES (insn) | |
2974 | = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), | |
2975 | REG_NOTES (insn)); | |
e03f789f | 2976 | } |
2977 | else | |
2978 | { | |
2979 | /* Make sure we don't get any other addresses with | |
2980 | embedded postincrements. They should be stopped in | |
2981 | GO_IF_LEGITIMATE_ADDRESS, but we're here for your | |
2982 | safety. */ | |
2983 | if (side_effects_p (addr)) | |
68435912 | 2984 | fatal_insn ("unexpected side-effects in address", addr); |
e03f789f | 2985 | |
2986 | emit_insn (gen_rtx_SET | |
2987 | (VOIDmode, | |
2988 | operand_subword (dest, reverse, TRUE, mode), | |
2989 | change_address | |
2990 | (src, SImode, | |
29c05e22 | 2991 | plus_constant (Pmode, addr, |
e03f789f | 2992 | reverse * UNITS_PER_WORD)))); |
2993 | emit_insn (gen_rtx_SET | |
2994 | (VOIDmode, | |
2995 | operand_subword (dest, ! reverse, TRUE, mode), | |
2996 | change_address | |
2997 | (src, SImode, | |
29c05e22 | 2998 | plus_constant (Pmode, addr, |
e03f789f | 2999 | (! reverse) * |
3000 | UNITS_PER_WORD)))); | |
3001 | } | |
3002 | } | |
3003 | else | |
bf776685 | 3004 | internal_error ("unknown src"); |
e03f789f | 3005 | } |
3006 | /* Reg-to-mem copy or clear mem. */ | |
683d2985 | 3007 | else if (MEM_P (dest) |
3008 | && (REG_P (src) | |
e03f789f | 3009 | || src == const0_rtx |
3010 | || src == CONST0_RTX (DFmode))) | |
3011 | { | |
3012 | rtx addr = XEXP (dest, 0); | |
3013 | ||
3014 | if (GET_CODE (addr) == POST_INC) | |
3015 | { | |
32c277e4 | 3016 | rtx mem; |
3017 | rtx insn; | |
683d2985 | 3018 | |
32c277e4 | 3019 | /* Whenever we emit insns with post-incremented addresses |
3020 | ourselves, we must add a post-inc note manually. */ | |
3021 | mem = change_address (dest, SImode, addr); | |
3022 | insn | |
3023 | = gen_rtx_SET (VOIDmode, | |
3024 | mem, operand_subword (src, 0, TRUE, mode)); | |
3025 | insn = emit_insn (insn); | |
3026 | if (GET_CODE (XEXP (mem, 0)) == POST_INC) | |
3027 | REG_NOTES (insn) | |
3028 | = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), | |
3029 | REG_NOTES (insn)); | |
3030 | ||
c85bb9fb | 3031 | mem = copy_rtx (mem); |
32c277e4 | 3032 | insn |
3033 | = gen_rtx_SET (VOIDmode, | |
3034 | mem, | |
3035 | operand_subword (src, 1, TRUE, mode)); | |
3036 | insn = emit_insn (insn); | |
3037 | if (GET_CODE (XEXP (mem, 0)) == POST_INC) | |
3038 | REG_NOTES (insn) | |
3039 | = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), | |
3040 | REG_NOTES (insn)); | |
e03f789f | 3041 | } |
3042 | else | |
3043 | { | |
3044 | /* Make sure we don't get any other addresses with embedded | |
3045 | postincrements. They should be stopped in | |
3046 | GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */ | |
3047 | if (side_effects_p (addr)) | |
68435912 | 3048 | fatal_insn ("unexpected side-effects in address", addr); |
e03f789f | 3049 | |
3050 | emit_insn (gen_rtx_SET | |
3051 | (VOIDmode, | |
3052 | change_address (dest, SImode, addr), | |
3053 | operand_subword (src, 0, TRUE, mode))); | |
3054 | ||
3055 | emit_insn (gen_rtx_SET | |
3056 | (VOIDmode, | |
3057 | change_address (dest, SImode, | |
29c05e22 | 3058 | plus_constant (Pmode, addr, |
e03f789f | 3059 | UNITS_PER_WORD)), |
3060 | operand_subword (src, 1, TRUE, mode))); | |
3061 | } | |
3062 | } | |
3063 | ||
3064 | else | |
bf776685 | 3065 | internal_error ("unknown dest"); |
e03f789f | 3066 | |
31d3e01c | 3067 | val = get_insns (); |
e03f789f | 3068 | end_sequence (); |
3069 | return val; | |
3070 | } | |
3071 | ||
dfc30596 | 3072 | /* The expander for the prologue pattern name. */ |
3073 | ||
3074 | void | |
3075 | cris_expand_prologue (void) | |
3076 | { | |
3077 | int regno; | |
3078 | int size = get_frame_size (); | |
3079 | /* Shorten the used name for readability. */ | |
abe32cce | 3080 | int cfoa_size = crtl->outgoing_args_size; |
dfc30596 | 3081 | int last_movem_reg = -1; |
3082 | int framesize = 0; | |
3083 | rtx mem, insn; | |
3084 | int return_address_on_stack = cris_return_address_on_stack (); | |
6a6dcc7c | 3085 | int got_really_used = false; |
dfc30596 | 3086 | int n_movem_regs = 0; |
abe32cce | 3087 | int pretend = crtl->args.pretend_args_size; |
dfc30596 | 3088 | |
3089 | /* Don't do anything if no prologues or epilogues are wanted. */ | |
3090 | if (!TARGET_PROLOGUE_EPILOGUE) | |
3091 | return; | |
3092 | ||
c14afa19 | 3093 | CRIS_ASSERT (size >= 0); |
dfc30596 | 3094 | |
18d50ae6 | 3095 | if (crtl->uses_pic_offset_table) |
6a6dcc7c | 3096 | { |
3097 | /* A reference may have been optimized out (like the abort () in | |
3098 | fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that | |
3099 | it's still used. */ | |
3100 | push_topmost_sequence (); | |
3101 | got_really_used | |
91a55c11 | 3102 | = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL); |
6a6dcc7c | 3103 | pop_topmost_sequence (); |
3104 | } | |
3105 | ||
dfc30596 | 3106 | /* Align the size to what's best for the CPU model. */ |
3107 | if (TARGET_STACK_ALIGN) | |
3108 | size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1; | |
3109 | ||
3110 | if (pretend) | |
3111 | { | |
3112 | /* See also cris_setup_incoming_varargs where | |
3113 | cfun->machine->stdarg_regs is set. There are other setters of | |
abe32cce | 3114 | crtl->args.pretend_args_size than stdarg handling, like |
dfc30596 | 3115 | for an argument passed with parts in R13 and stack. We must |
3116 | not store R13 into the pretend-area for that case, as GCC does | |
3117 | that itself. "Our" store would be marked as redundant and GCC | |
3118 | will attempt to remove it, which will then be flagged as an | |
3119 | internal error; trying to remove a frame-related insn. */ | |
3120 | int stdarg_regs = cfun->machine->stdarg_regs; | |
3121 | ||
3122 | framesize += pretend; | |
3123 | ||
3124 | for (regno = CRIS_FIRST_ARG_REG + CRIS_MAX_ARGS_IN_REGS - 1; | |
3125 | stdarg_regs > 0; | |
3126 | regno--, pretend -= 4, stdarg_regs--) | |
3127 | { | |
3128 | insn = emit_insn (gen_rtx_SET (VOIDmode, | |
3129 | stack_pointer_rtx, | |
29c05e22 | 3130 | plus_constant (Pmode, |
3131 | stack_pointer_rtx, | |
dfc30596 | 3132 | -4))); |
3133 | /* FIXME: When dwarf2 frame output and unless asynchronous | |
3134 | exceptions, make dwarf2 bundle together all stack | |
3135 | adjustments like it does for registers between stack | |
3136 | adjustments. */ | |
3137 | RTX_FRAME_RELATED_P (insn) = 1; | |
3138 | ||
3139 | mem = gen_rtx_MEM (SImode, stack_pointer_rtx); | |
3140 | set_mem_alias_set (mem, get_varargs_alias_set ()); | |
3141 | insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, regno)); | |
3142 | ||
3143 | /* Note the absence of RTX_FRAME_RELATED_P on the above insn: | |
3144 | the value isn't restored, so we don't want to tell dwarf2 | |
3145 | that it's been stored to stack, else EH handling info would | |
3146 | get confused. */ | |
3147 | } | |
3148 | ||
abe32cce | 3149 | /* For other setters of crtl->args.pretend_args_size, we |
dfc30596 | 3150 | just adjust the stack by leaving the remaining size in |
3151 | "pretend", handled below. */ | |
3152 | } | |
3153 | ||
3154 | /* Save SRP if not a leaf function. */ | |
3155 | if (return_address_on_stack) | |
3156 | { | |
3157 | insn = emit_insn (gen_rtx_SET (VOIDmode, | |
3158 | stack_pointer_rtx, | |
29c05e22 | 3159 | plus_constant (Pmode, stack_pointer_rtx, |
dfc30596 | 3160 | -4 - pretend))); |
3161 | pretend = 0; | |
3162 | RTX_FRAME_RELATED_P (insn) = 1; | |
3163 | ||
3164 | mem = gen_rtx_MEM (SImode, stack_pointer_rtx); | |
3165 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
3166 | insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM)); | |
3167 | RTX_FRAME_RELATED_P (insn) = 1; | |
3168 | framesize += 4; | |
3169 | } | |
3170 | ||
3171 | /* Set up the frame pointer, if needed. */ | |
3172 | if (frame_pointer_needed) | |
3173 | { | |
3174 | insn = emit_insn (gen_rtx_SET (VOIDmode, | |
3175 | stack_pointer_rtx, | |
29c05e22 | 3176 | plus_constant (Pmode, stack_pointer_rtx, |
dfc30596 | 3177 | -4 - pretend))); |
3178 | pretend = 0; | |
3179 | RTX_FRAME_RELATED_P (insn) = 1; | |
3180 | ||
3181 | mem = gen_rtx_MEM (SImode, stack_pointer_rtx); | |
3182 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
3183 | insn = emit_move_insn (mem, frame_pointer_rtx); | |
3184 | RTX_FRAME_RELATED_P (insn) = 1; | |
3185 | ||
3186 | insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); | |
3187 | RTX_FRAME_RELATED_P (insn) = 1; | |
3188 | ||
3189 | framesize += 4; | |
3190 | } | |
3191 | ||
3192 | /* Between frame-pointer and saved registers lie the area for local | |
3193 | variables. If we get here with "pretended" size remaining, count | |
3194 | it into the general stack size. */ | |
3195 | size += pretend; | |
3196 | ||
3197 | /* Get a contiguous sequence of registers, starting with R0, that need | |
3198 | to be saved. */ | |
3199 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
3200 | { | |
3201 | if (cris_reg_saved_in_regsave_area (regno, got_really_used)) | |
3202 | { | |
3203 | n_movem_regs++; | |
3204 | ||
3205 | /* Check if movem may be used for registers so far. */ | |
3206 | if (regno == last_movem_reg + 1) | |
3207 | /* Yes, update next expected register. */ | |
3208 | last_movem_reg = regno; | |
3209 | else | |
3210 | { | |
3211 | /* We cannot use movem for all registers. We have to flush | |
3212 | any movem:ed registers we got so far. */ | |
3213 | if (last_movem_reg != -1) | |
3214 | { | |
3215 | int n_saved | |
3216 | = (n_movem_regs == 1) ? 1 : last_movem_reg + 1; | |
3217 | ||
3218 | /* It is a win to use a side-effect assignment for | |
3219 | 64 <= size <= 128. But side-effect on movem was | |
3220 | not usable for CRIS v0..3. Also only do it if | |
3221 | side-effects insns are allowed. */ | |
3222 | if ((last_movem_reg + 1) * 4 + size >= 64 | |
3223 | && (last_movem_reg + 1) * 4 + size <= 128 | |
3224 | && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1) | |
3225 | && TARGET_SIDE_EFFECT_PREFIXES) | |
3226 | { | |
3227 | mem | |
3228 | = gen_rtx_MEM (SImode, | |
29c05e22 | 3229 | plus_constant (Pmode, stack_pointer_rtx, |
dfc30596 | 3230 | -(n_saved * 4 + size))); |
3231 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
3232 | insn | |
3233 | = cris_emit_movem_store (mem, GEN_INT (n_saved), | |
3234 | -(n_saved * 4 + size), | |
3235 | true); | |
3236 | } | |
3237 | else | |
3238 | { | |
3239 | insn | |
3240 | = gen_rtx_SET (VOIDmode, | |
3241 | stack_pointer_rtx, | |
29c05e22 | 3242 | plus_constant (Pmode, stack_pointer_rtx, |
dfc30596 | 3243 | -(n_saved * 4 + size))); |
3244 | insn = emit_insn (insn); | |
3245 | RTX_FRAME_RELATED_P (insn) = 1; | |
3246 | ||
3247 | mem = gen_rtx_MEM (SImode, stack_pointer_rtx); | |
3248 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
3249 | insn = cris_emit_movem_store (mem, GEN_INT (n_saved), | |
3250 | 0, true); | |
3251 | } | |
3252 | ||
3253 | framesize += n_saved * 4 + size; | |
3254 | last_movem_reg = -1; | |
3255 | size = 0; | |
3256 | } | |
3257 | ||
3258 | insn = emit_insn (gen_rtx_SET (VOIDmode, | |
3259 | stack_pointer_rtx, | |
29c05e22 | 3260 | plus_constant (Pmode, |
3261 | stack_pointer_rtx, | |
dfc30596 | 3262 | -4 - size))); |
3263 | RTX_FRAME_RELATED_P (insn) = 1; | |
3264 | ||
3265 | mem = gen_rtx_MEM (SImode, stack_pointer_rtx); | |
3266 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
3267 | insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, regno)); | |
3268 | RTX_FRAME_RELATED_P (insn) = 1; | |
3269 | ||
3270 | framesize += 4 + size; | |
3271 | size = 0; | |
3272 | } | |
3273 | } | |
3274 | } | |
3275 | ||
3276 | /* Check after, if we could movem all registers. This is the normal case. */ | |
3277 | if (last_movem_reg != -1) | |
3278 | { | |
3279 | int n_saved | |
3280 | = (n_movem_regs == 1) ? 1 : last_movem_reg + 1; | |
3281 | ||
3282 | /* Side-effect on movem was not usable for CRIS v0..3. Also only | |
3283 | do it if side-effects insns are allowed. */ | |
3284 | if ((last_movem_reg + 1) * 4 + size >= 64 | |
3285 | && (last_movem_reg + 1) * 4 + size <= 128 | |
3286 | && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1) | |
3287 | && TARGET_SIDE_EFFECT_PREFIXES) | |
3288 | { | |
3289 | mem | |
3290 | = gen_rtx_MEM (SImode, | |
29c05e22 | 3291 | plus_constant (Pmode, stack_pointer_rtx, |
dfc30596 | 3292 | -(n_saved * 4 + size))); |
3293 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
3294 | insn = cris_emit_movem_store (mem, GEN_INT (n_saved), | |
3295 | -(n_saved * 4 + size), true); | |
3296 | } | |
3297 | else | |
3298 | { | |
3299 | insn | |
3300 | = gen_rtx_SET (VOIDmode, | |
3301 | stack_pointer_rtx, | |
29c05e22 | 3302 | plus_constant (Pmode, stack_pointer_rtx, |
dfc30596 | 3303 | -(n_saved * 4 + size))); |
3304 | insn = emit_insn (insn); | |
3305 | RTX_FRAME_RELATED_P (insn) = 1; | |
3306 | ||
3307 | mem = gen_rtx_MEM (SImode, stack_pointer_rtx); | |
3308 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
3309 | insn = cris_emit_movem_store (mem, GEN_INT (n_saved), 0, true); | |
3310 | } | |
3311 | ||
3312 | framesize += n_saved * 4 + size; | |
3313 | /* We have to put outgoing argument space after regs. */ | |
3314 | if (cfoa_size) | |
3315 | { | |
3316 | insn = emit_insn (gen_rtx_SET (VOIDmode, | |
3317 | stack_pointer_rtx, | |
29c05e22 | 3318 | plus_constant (Pmode, |
3319 | stack_pointer_rtx, | |
dfc30596 | 3320 | -cfoa_size))); |
3321 | RTX_FRAME_RELATED_P (insn) = 1; | |
3322 | framesize += cfoa_size; | |
3323 | } | |
3324 | } | |
3325 | else if ((size + cfoa_size) > 0) | |
3326 | { | |
3327 | insn = emit_insn (gen_rtx_SET (VOIDmode, | |
3328 | stack_pointer_rtx, | |
29c05e22 | 3329 | plus_constant (Pmode, |
3330 | stack_pointer_rtx, | |
dfc30596 | 3331 | -(cfoa_size + size)))); |
3332 | RTX_FRAME_RELATED_P (insn) = 1; | |
3333 | framesize += size + cfoa_size; | |
3334 | } | |
3335 | ||
3336 | /* Set up the PIC register, if it is used. */ | |
3337 | if (got_really_used) | |
3338 | { | |
3339 | rtx got | |
3340 | = gen_rtx_UNSPEC (SImode, gen_rtvec (1, const0_rtx), CRIS_UNSPEC_GOT); | |
3341 | emit_move_insn (pic_offset_table_rtx, got); | |
3342 | ||
3343 | /* FIXME: This is a cover-up for flow2 messing up; it doesn't | |
3344 | follow exceptional paths and tries to delete the GOT load as | |
3345 | unused, if it isn't used on the non-exceptional paths. Other | |
3346 | ports have similar or other cover-ups, or plain bugs marking | |
3347 | the GOT register load as maybe-dead. To see this, remove the | |
3348 | line below and try libsupc++/vec.cc or a trivial | |
3349 | "static void y (); void x () {try {y ();} catch (...) {}}". */ | |
18b42941 | 3350 | emit_use (pic_offset_table_rtx); |
dfc30596 | 3351 | } |
3352 | ||
3353 | if (cris_max_stackframe && framesize > cris_max_stackframe) | |
c3ceba8e | 3354 | warning (0, "stackframe too big: %d bytes", framesize); |
dfc30596 | 3355 | } |
3356 | ||
72db90ce | 3357 | /* The expander for the epilogue pattern. */ |
3358 | ||
3359 | void | |
3360 | cris_expand_epilogue (void) | |
3361 | { | |
3362 | int regno; | |
3363 | int size = get_frame_size (); | |
3364 | int last_movem_reg = -1; | |
abe32cce | 3365 | int argspace_offset = crtl->outgoing_args_size; |
3366 | int pretend = crtl->args.pretend_args_size; | |
72db90ce | 3367 | rtx mem; |
3368 | bool return_address_on_stack = cris_return_address_on_stack (); | |
3369 | /* A reference may have been optimized out | |
3370 | (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1) | |
3371 | so check that it's still used. */ | |
6a6dcc7c | 3372 | int got_really_used = false; |
72db90ce | 3373 | int n_movem_regs = 0; |
3374 | ||
3375 | if (!TARGET_PROLOGUE_EPILOGUE) | |
3376 | return; | |
3377 | ||
18d50ae6 | 3378 | if (crtl->uses_pic_offset_table) |
6a6dcc7c | 3379 | { |
3380 | /* A reference may have been optimized out (like the abort () in | |
3381 | fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that | |
3382 | it's still used. */ | |
3383 | push_topmost_sequence (); | |
3384 | got_really_used | |
91a55c11 | 3385 | = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL); |
6a6dcc7c | 3386 | pop_topmost_sequence (); |
3387 | } | |
3388 | ||
72db90ce | 3389 | /* Align byte count of stack frame. */ |
3390 | if (TARGET_STACK_ALIGN) | |
3391 | size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1; | |
3392 | ||
3393 | /* Check how many saved regs we can movem. They start at r0 and must | |
3394 | be contiguous. */ | |
3395 | for (regno = 0; | |
3396 | regno < FIRST_PSEUDO_REGISTER; | |
3397 | regno++) | |
3398 | if (cris_reg_saved_in_regsave_area (regno, got_really_used)) | |
3399 | { | |
3400 | n_movem_regs++; | |
3401 | ||
3402 | if (regno == last_movem_reg + 1) | |
3403 | last_movem_reg = regno; | |
3404 | else | |
3405 | break; | |
3406 | } | |
3407 | ||
3408 | /* If there was only one register that really needed to be saved | |
3409 | through movem, don't use movem. */ | |
3410 | if (n_movem_regs == 1) | |
3411 | last_movem_reg = -1; | |
3412 | ||
3413 | /* Now emit "normal" move insns for all regs higher than the movem | |
3414 | regs. */ | |
3415 | for (regno = FIRST_PSEUDO_REGISTER - 1; | |
3416 | regno > last_movem_reg; | |
3417 | regno--) | |
3418 | if (cris_reg_saved_in_regsave_area (regno, got_really_used)) | |
3419 | { | |
32c277e4 | 3420 | rtx insn; |
3421 | ||
72db90ce | 3422 | if (argspace_offset) |
3423 | { | |
3424 | /* There is an area for outgoing parameters located before | |
3425 | the saved registers. We have to adjust for that. */ | |
3426 | emit_insn (gen_rtx_SET (VOIDmode, | |
3427 | stack_pointer_rtx, | |
29c05e22 | 3428 | plus_constant (Pmode, stack_pointer_rtx, |
72db90ce | 3429 | argspace_offset))); |
3430 | /* Make sure we only do this once. */ | |
3431 | argspace_offset = 0; | |
3432 | } | |
3433 | ||
3434 | mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode, | |
3435 | stack_pointer_rtx)); | |
3436 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
32c277e4 | 3437 | insn = emit_move_insn (gen_rtx_raw_REG (SImode, regno), mem); |
3438 | ||
3439 | /* Whenever we emit insns with post-incremented addresses | |
3440 | ourselves, we must add a post-inc note manually. */ | |
3441 | REG_NOTES (insn) | |
3442 | = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); | |
72db90ce | 3443 | } |
3444 | ||
3445 | /* If we have any movem-restore, do it now. */ | |
3446 | if (last_movem_reg != -1) | |
3447 | { | |
32c277e4 | 3448 | rtx insn; |
3449 | ||
72db90ce | 3450 | if (argspace_offset) |
3451 | { | |
3452 | emit_insn (gen_rtx_SET (VOIDmode, | |
3453 | stack_pointer_rtx, | |
29c05e22 | 3454 | plus_constant (Pmode, stack_pointer_rtx, |
72db90ce | 3455 | argspace_offset))); |
3456 | argspace_offset = 0; | |
3457 | } | |
3458 | ||
3459 | mem = gen_rtx_MEM (SImode, | |
3460 | gen_rtx_POST_INC (SImode, stack_pointer_rtx)); | |
3461 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
32c277e4 | 3462 | insn |
3463 | = emit_insn (cris_gen_movem_load (mem, | |
3464 | GEN_INT (last_movem_reg + 1), 0)); | |
3465 | /* Whenever we emit insns with post-incremented addresses | |
3466 | ourselves, we must add a post-inc note manually. */ | |
3467 | if (side_effects_p (PATTERN (insn))) | |
3468 | REG_NOTES (insn) | |
3469 | = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); | |
72db90ce | 3470 | } |
3471 | ||
3472 | /* If we don't clobber all of the allocated stack area (we've already | |
3473 | deallocated saved registers), GCC might want to schedule loads from | |
3474 | the stack to *after* the stack-pointer restore, which introduces an | |
3475 | interrupt race condition. This happened for the initial-value | |
3476 | SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of | |
3477 | other failure for that test). It also happened for the stack slot | |
3478 | for the return value in (one version of) | |
3479 | linux/fs/dcache.c:__d_lookup, at least with "-O2 | |
3480 | -fno-omit-frame-pointer". */ | |
3481 | ||
3482 | /* Restore frame pointer if necessary. */ | |
3483 | if (frame_pointer_needed) | |
3484 | { | |
32c277e4 | 3485 | rtx insn; |
3486 | ||
72db90ce | 3487 | emit_insn (gen_cris_frame_deallocated_barrier ()); |
3488 | ||
3489 | emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); | |
3490 | mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode, | |
3491 | stack_pointer_rtx)); | |
3492 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
32c277e4 | 3493 | insn = emit_move_insn (frame_pointer_rtx, mem); |
3494 | ||
3495 | /* Whenever we emit insns with post-incremented addresses | |
3496 | ourselves, we must add a post-inc note manually. */ | |
3497 | REG_NOTES (insn) | |
3498 | = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); | |
72db90ce | 3499 | } |
3500 | else if ((size + argspace_offset) != 0) | |
3501 | { | |
3502 | emit_insn (gen_cris_frame_deallocated_barrier ()); | |
3503 | ||
3504 | /* If there was no frame-pointer to restore sp from, we must | |
3505 | explicitly deallocate local variables. */ | |
3506 | ||
3507 | /* Handle space for outgoing parameters that hasn't been handled | |
3508 | yet. */ | |
3509 | size += argspace_offset; | |
3510 | ||
3511 | emit_insn (gen_rtx_SET (VOIDmode, | |
3512 | stack_pointer_rtx, | |
29c05e22 | 3513 | plus_constant (Pmode, stack_pointer_rtx, size))); |
72db90ce | 3514 | } |
3515 | ||
3516 | /* If this function has no pushed register parameters | |
3517 | (stdargs/varargs), and if it is not a leaf function, then we have | |
3518 | the return address on the stack. */ | |
3519 | if (return_address_on_stack && pretend == 0) | |
3520 | { | |
18d50ae6 | 3521 | if (TARGET_V32 || crtl->calls_eh_return) |
72db90ce | 3522 | { |
3523 | rtx mem; | |
32c277e4 | 3524 | rtx insn; |
72db90ce | 3525 | rtx srpreg = gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM); |
3526 | mem = gen_rtx_MEM (SImode, | |
3527 | gen_rtx_POST_INC (SImode, | |
3528 | stack_pointer_rtx)); | |
3529 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
32c277e4 | 3530 | insn = emit_move_insn (srpreg, mem); |
3531 | ||
3532 | /* Whenever we emit insns with post-incremented addresses | |
3533 | ourselves, we must add a post-inc note manually. */ | |
3534 | REG_NOTES (insn) | |
3535 | = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); | |
72db90ce | 3536 | |
18d50ae6 | 3537 | if (crtl->calls_eh_return) |
c85bb9fb | 3538 | emit_insn (gen_addsi3 (stack_pointer_rtx, |
3539 | stack_pointer_rtx, | |
3540 | gen_rtx_raw_REG (SImode, | |
3541 | CRIS_STACKADJ_REG))); | |
72db90ce | 3542 | cris_expand_return (false); |
3543 | } | |
3544 | else | |
3545 | cris_expand_return (true); | |
3546 | ||
3547 | return; | |
3548 | } | |
3549 | ||
3550 | /* If we pushed some register parameters, then adjust the stack for | |
3551 | them. */ | |
3552 | if (pretend != 0) | |
3553 | { | |
3554 | /* If SRP is stored on the way, we need to restore it first. */ | |
3555 | if (return_address_on_stack) | |
3556 | { | |
3557 | rtx mem; | |
3558 | rtx srpreg = gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM); | |
32c277e4 | 3559 | rtx insn; |
3560 | ||
72db90ce | 3561 | mem = gen_rtx_MEM (SImode, |
3562 | gen_rtx_POST_INC (SImode, | |
3563 | stack_pointer_rtx)); | |
3564 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
32c277e4 | 3565 | insn = emit_move_insn (srpreg, mem); |
3566 | ||
3567 | /* Whenever we emit insns with post-incremented addresses | |
3568 | ourselves, we must add a post-inc note manually. */ | |
3569 | REG_NOTES (insn) | |
3570 | = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); | |
72db90ce | 3571 | } |
3572 | ||
3573 | emit_insn (gen_rtx_SET (VOIDmode, | |
3574 | stack_pointer_rtx, | |
29c05e22 | 3575 | plus_constant (Pmode, stack_pointer_rtx, |
3576 | pretend))); | |
72db90ce | 3577 | } |
3578 | ||
3579 | /* Perform the "physical" unwinding that the EH machinery calculated. */ | |
18d50ae6 | 3580 | if (crtl->calls_eh_return) |
72db90ce | 3581 | emit_insn (gen_addsi3 (stack_pointer_rtx, |
3582 | stack_pointer_rtx, | |
3583 | gen_rtx_raw_REG (SImode, | |
3584 | CRIS_STACKADJ_REG))); | |
3585 | cris_expand_return (false); | |
3586 | } | |
3587 | ||
3588 | /* Worker function for generating movem from mem for load_multiple. */ | |
3589 | ||
3590 | rtx | |
dfc30596 | 3591 | cris_gen_movem_load (rtx src, rtx nregs_rtx, int nprefix) |
72db90ce | 3592 | { |
3593 | int nregs = INTVAL (nregs_rtx); | |
3594 | rtvec vec; | |
3595 | int eltno = 1; | |
3596 | int i; | |
dfc30596 | 3597 | rtx srcreg = XEXP (src, 0); |
72db90ce | 3598 | unsigned int regno = nregs - 1; |
3599 | int regno_inc = -1; | |
3600 | ||
c85bb9fb | 3601 | if (TARGET_V32) |
3602 | { | |
3603 | regno = 0; | |
3604 | regno_inc = 1; | |
3605 | } | |
3606 | ||
72db90ce | 3607 | if (GET_CODE (srcreg) == POST_INC) |
3608 | srcreg = XEXP (srcreg, 0); | |
3609 | ||
c14afa19 | 3610 | CRIS_ASSERT (REG_P (srcreg)); |
72db90ce | 3611 | |
3612 | /* Don't use movem for just one insn. The insns are equivalent except | |
dfc30596 | 3613 | for the pipeline hazard (on v32); movem does not forward the loaded |
3614 | registers so there's a three cycles penalty for their use. */ | |
72db90ce | 3615 | if (nregs == 1) |
dfc30596 | 3616 | return gen_movsi (gen_rtx_REG (SImode, 0), src); |
72db90ce | 3617 | |
3618 | vec = rtvec_alloc (nprefix + nregs | |
dfc30596 | 3619 | + (GET_CODE (XEXP (src, 0)) == POST_INC)); |
72db90ce | 3620 | |
dfc30596 | 3621 | if (GET_CODE (XEXP (src, 0)) == POST_INC) |
72db90ce | 3622 | { |
3623 | RTVEC_ELT (vec, nprefix + 1) | |
29c05e22 | 3624 | = gen_rtx_SET (VOIDmode, srcreg, |
3625 | plus_constant (Pmode, srcreg, nregs * 4)); | |
72db90ce | 3626 | eltno++; |
3627 | } | |
3628 | ||
dfc30596 | 3629 | src = replace_equiv_address (src, srcreg); |
3630 | RTVEC_ELT (vec, nprefix) | |
3631 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno), src); | |
3632 | regno += regno_inc; | |
3633 | ||
72db90ce | 3634 | for (i = 1; i < nregs; i++, eltno++) |
3635 | { | |
3636 | RTVEC_ELT (vec, nprefix + eltno) | |
3637 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno), | |
3638 | adjust_address_nv (src, SImode, i * 4)); | |
3639 | regno += regno_inc; | |
3640 | } | |
3641 | ||
3642 | return gen_rtx_PARALLEL (VOIDmode, vec); | |
3643 | } | |
3644 | ||
dfc30596 | 3645 | /* Worker function for generating movem to mem. If FRAME_RELATED, notes |
3646 | are added that the dwarf2 machinery understands. */ | |
3647 | ||
3648 | rtx | |
3649 | cris_emit_movem_store (rtx dest, rtx nregs_rtx, int increment, | |
3650 | bool frame_related) | |
3651 | { | |
3652 | int nregs = INTVAL (nregs_rtx); | |
3653 | rtvec vec; | |
3654 | int eltno = 1; | |
3655 | int i; | |
3656 | rtx insn; | |
3657 | rtx destreg = XEXP (dest, 0); | |
3658 | unsigned int regno = nregs - 1; | |
3659 | int regno_inc = -1; | |
3660 | ||
c85bb9fb | 3661 | if (TARGET_V32) |
3662 | { | |
3663 | regno = 0; | |
3664 | regno_inc = 1; | |
3665 | } | |
3666 | ||
dfc30596 | 3667 | if (GET_CODE (destreg) == POST_INC) |
3668 | increment += nregs * 4; | |
3669 | ||
3670 | if (GET_CODE (destreg) == POST_INC || GET_CODE (destreg) == PLUS) | |
3671 | destreg = XEXP (destreg, 0); | |
3672 | ||
c14afa19 | 3673 | CRIS_ASSERT (REG_P (destreg)); |
dfc30596 | 3674 | |
3675 | /* Don't use movem for just one insn. The insns are equivalent except | |
3676 | for the pipeline hazard (on v32); movem does not forward the loaded | |
3677 | registers so there's a three cycles penalty for use. */ | |
3678 | if (nregs == 1) | |
3679 | { | |
3680 | rtx mov = gen_rtx_SET (VOIDmode, dest, gen_rtx_REG (SImode, 0)); | |
3681 | ||
3682 | if (increment == 0) | |
3683 | { | |
3684 | insn = emit_insn (mov); | |
3685 | if (frame_related) | |
3686 | RTX_FRAME_RELATED_P (insn) = 1; | |
3687 | return insn; | |
3688 | } | |
3689 | ||
3690 | /* If there was a request for a side-effect, create the ordinary | |
3691 | parallel. */ | |
3692 | vec = rtvec_alloc (2); | |
3693 | ||
3694 | RTVEC_ELT (vec, 0) = mov; | |
3695 | RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, destreg, | |
29c05e22 | 3696 | plus_constant (Pmode, destreg, |
3697 | increment)); | |
dfc30596 | 3698 | if (frame_related) |
3699 | { | |
3700 | RTX_FRAME_RELATED_P (mov) = 1; | |
3701 | RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1; | |
3702 | } | |
3703 | } | |
3704 | else | |
3705 | { | |
3706 | vec = rtvec_alloc (nregs + (increment != 0 ? 1 : 0)); | |
3707 | RTVEC_ELT (vec, 0) | |
3708 | = gen_rtx_SET (VOIDmode, | |
3709 | replace_equiv_address (dest, | |
29c05e22 | 3710 | plus_constant (Pmode, destreg, |
dfc30596 | 3711 | increment)), |
3712 | gen_rtx_REG (SImode, regno)); | |
3713 | regno += regno_inc; | |
3714 | ||
3715 | /* The dwarf2 info wants this mark on each component in a parallel | |
3716 | that's part of the prologue (though it's optional on the first | |
3717 | component). */ | |
3718 | if (frame_related) | |
3719 | RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 0)) = 1; | |
3720 | ||
3721 | if (increment != 0) | |
3722 | { | |
3723 | RTVEC_ELT (vec, 1) | |
3724 | = gen_rtx_SET (VOIDmode, destreg, | |
29c05e22 | 3725 | plus_constant (Pmode, destreg, |
dfc30596 | 3726 | increment != 0 |
3727 | ? increment : nregs * 4)); | |
3728 | eltno++; | |
3729 | ||
3730 | if (frame_related) | |
3731 | RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1; | |
3732 | ||
3733 | /* Don't call adjust_address_nv on a post-incremented address if | |
3734 | we can help it. */ | |
3735 | if (GET_CODE (XEXP (dest, 0)) == POST_INC) | |
3736 | dest = replace_equiv_address (dest, destreg); | |
3737 | } | |
3738 | ||
3739 | for (i = 1; i < nregs; i++, eltno++) | |
3740 | { | |
3741 | RTVEC_ELT (vec, eltno) | |
3742 | = gen_rtx_SET (VOIDmode, adjust_address_nv (dest, SImode, i * 4), | |
3743 | gen_rtx_REG (SImode, regno)); | |
3744 | if (frame_related) | |
3745 | RTX_FRAME_RELATED_P (RTVEC_ELT (vec, eltno)) = 1; | |
3746 | regno += regno_inc; | |
3747 | } | |
3748 | } | |
3749 | ||
3750 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, vec)); | |
3751 | ||
3752 | /* Because dwarf2out.c handles the insns in a parallel as a sequence, | |
3753 | we need to keep the stack adjustment separate, after the | |
3754 | MEM-setters. Else the stack-adjustment in the second component of | |
3755 | the parallel would be mishandled; the offsets for the SETs that | |
3756 | follow it would be wrong. We prepare for this by adding a | |
3757 | REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE | |
3758 | followed by the increment. Note that we have FRAME_RELATED_P on | |
3759 | all the SETs, including the original stack adjustment SET in the | |
3760 | parallel. */ | |
3761 | if (frame_related) | |
3762 | { | |
3763 | if (increment != 0) | |
3764 | { | |
3765 | rtx seq = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (nregs + 1)); | |
5ea3a301 | 3766 | XVECEXP (seq, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn), 0, 0)); |
dfc30596 | 3767 | for (i = 1; i < nregs; i++) |
5ea3a301 | 3768 | XVECEXP (seq, 0, i) |
3769 | = copy_rtx (XVECEXP (PATTERN (insn), 0, i + 1)); | |
3770 | XVECEXP (seq, 0, nregs) = copy_rtx (XVECEXP (PATTERN (insn), 0, 1)); | |
39e09a0c | 3771 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, seq); |
dfc30596 | 3772 | } |
3773 | ||
3774 | RTX_FRAME_RELATED_P (insn) = 1; | |
3775 | } | |
3776 | ||
3777 | return insn; | |
3778 | } | |
3779 | ||
6a6dcc7c | 3780 | /* Worker function for expanding the address for PIC function calls. */ |
3781 | ||
3782 | void | |
f69bb65a | 3783 | cris_expand_pic_call_address (rtx *opp, rtx *markerp) |
6a6dcc7c | 3784 | { |
3785 | rtx op = *opp; | |
3786 | ||
f69bb65a | 3787 | gcc_assert (flag_pic && MEM_P (op)); |
6a6dcc7c | 3788 | op = XEXP (op, 0); |
3789 | ||
3790 | /* It might be that code can be generated that jumps to 0 (or to a | |
3791 | specific address). Don't die on that. (There is a | |
3792 | testcase.) */ | |
f69bb65a | 3793 | if (CONSTANT_P (op) && !CONST_INT_P (op)) |
6a6dcc7c | 3794 | { |
f69bb65a | 3795 | enum cris_symbol_type t = cris_symbol_type_of (op); |
6a6dcc7c | 3796 | |
e1ba4a27 | 3797 | CRIS_ASSERT (can_create_pseudo_p ()); |
6a6dcc7c | 3798 | |
3799 | /* For local symbols (non-PLT), just get the plain symbol | |
3800 | reference into a register. For symbols that can be PLT, make | |
3801 | them PLT. */ | |
c85bb9fb | 3802 | if (t == cris_rel_symbol) |
3803 | { | |
3804 | /* For v32, we're fine as-is; just PICify the symbol. Forcing | |
3805 | into a register caused performance regression for 3.2.1, | |
3806 | observable in __floatdidf and elsewhere in libgcc. */ | |
3807 | if (TARGET_V32) | |
3808 | { | |
3809 | rtx sym = GET_CODE (op) != CONST ? op : get_related_value (op); | |
3810 | HOST_WIDE_INT offs = get_integer_term (op); | |
3811 | ||
3812 | /* We can't get calls to sym+N, N integer, can we? */ | |
3813 | gcc_assert (offs == 0); | |
3814 | ||
3815 | op = gen_rtx_CONST (Pmode, | |
3816 | gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), | |
3817 | CRIS_UNSPEC_PCREL)); | |
3818 | } | |
3819 | else | |
3820 | op = force_reg (Pmode, op); | |
f69bb65a | 3821 | |
3822 | /* A local call. */ | |
3823 | *markerp = const0_rtx; | |
c85bb9fb | 3824 | } |
6a6dcc7c | 3825 | else if (t == cris_got_symbol) |
3826 | { | |
3827 | if (TARGET_AVOID_GOTPLT) | |
3828 | { | |
3829 | /* Change a "jsr sym" into (allocate register rM, rO) | |
f69bb65a | 3830 | "move.d (const (unspec [sym] CRIS_UNSPEC_PLT_GOTREL)),rM" |
c85bb9fb | 3831 | "add.d rPIC,rM,rO", "jsr rO" for pre-v32 and |
f69bb65a | 3832 | "jsr (const (unspec [sym] CRIS_UNSPEC_PLT_PCREL))" |
c85bb9fb | 3833 | for v32. */ |
6a6dcc7c | 3834 | rtx tem, rm, ro; |
f69bb65a | 3835 | |
18d50ae6 | 3836 | crtl->uses_pic_offset_table = 1; |
c85bb9fb | 3837 | tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op), |
3838 | TARGET_V32 | |
3839 | ? CRIS_UNSPEC_PLT_PCREL | |
3840 | : CRIS_UNSPEC_PLT_GOTREL); | |
3841 | tem = gen_rtx_CONST (Pmode, tem); | |
3842 | if (TARGET_V32) | |
3843 | op = tem; | |
3844 | else | |
3845 | { | |
3846 | rm = gen_reg_rtx (Pmode); | |
3847 | emit_move_insn (rm, tem); | |
3848 | ro = gen_reg_rtx (Pmode); | |
3849 | if (expand_binop (Pmode, add_optab, rm, | |
3850 | pic_offset_table_rtx, | |
3851 | ro, 0, OPTAB_LIB_WIDEN) != ro) | |
3852 | internal_error ("expand_binop failed in movsi got"); | |
3853 | op = ro; | |
3854 | } | |
6a6dcc7c | 3855 | } |
3856 | else | |
3857 | { | |
3858 | /* Change a "jsr sym" into (allocate register rM, rO) | |
c85bb9fb | 3859 | "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOTREAD)),rM" |
6a6dcc7c | 3860 | "add.d rPIC,rM,rO" "jsr [rO]" with the memory access |
3861 | marked as not trapping and not aliasing. No "move.d | |
3862 | [rO],rP" as that would invite to re-use of a value | |
3863 | that should not be reused. FIXME: Need a peephole2 | |
3864 | for cases when this is cse:d from the call, to change | |
3865 | back to just get the PLT entry address, so we don't | |
3866 | resolve the same symbol over and over (the memory | |
3867 | access of the PLTGOT isn't constant). */ | |
3868 | rtx tem, mem, rm, ro; | |
3869 | ||
e1ba4a27 | 3870 | gcc_assert (can_create_pseudo_p ()); |
18d50ae6 | 3871 | crtl->uses_pic_offset_table = 1; |
6a6dcc7c | 3872 | tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op), |
3873 | CRIS_UNSPEC_PLTGOTREAD); | |
3874 | rm = gen_reg_rtx (Pmode); | |
3875 | emit_move_insn (rm, gen_rtx_CONST (Pmode, tem)); | |
3876 | ro = gen_reg_rtx (Pmode); | |
3877 | if (expand_binop (Pmode, add_optab, rm, | |
3878 | pic_offset_table_rtx, | |
3879 | ro, 0, OPTAB_LIB_WIDEN) != ro) | |
3880 | internal_error ("expand_binop failed in movsi got"); | |
3881 | mem = gen_rtx_MEM (Pmode, ro); | |
3882 | ||
3883 | /* This MEM doesn't alias anything. Whether it aliases | |
3884 | other same symbols is unimportant. */ | |
3885 | set_mem_alias_set (mem, new_alias_set ()); | |
3886 | MEM_NOTRAP_P (mem) = 1; | |
3887 | op = mem; | |
3888 | } | |
f69bb65a | 3889 | |
3890 | /* We need to prepare this call to go through the PLT; we | |
3891 | need to make GOT available. */ | |
3892 | *markerp = pic_offset_table_rtx; | |
6a6dcc7c | 3893 | } |
3894 | else | |
f69bb65a | 3895 | /* Can't possibly get anything else for a function-call, right? */ |
bf776685 | 3896 | fatal_insn ("unidentifiable call op", op); |
6a6dcc7c | 3897 | |
f69bb65a | 3898 | /* If the validizing variant is called, it will try to validize |
3899 | the address as a valid any-operand constant, but as it's only | |
3900 | valid for calls and moves, it will fail and always be forced | |
3901 | into a register. */ | |
3902 | *opp = replace_equiv_address_nv (*opp, op); | |
6a6dcc7c | 3903 | } |
f69bb65a | 3904 | else |
3905 | /* Can't tell what locality a call to a non-constant address has; | |
3906 | better make the GOT register alive at it. | |
3907 | FIXME: Can we see whether the register has known constant | |
3908 | contents? */ | |
3909 | *markerp = pic_offset_table_rtx; | |
6a6dcc7c | 3910 | } |
3911 | ||
af9c3aeb | 3912 | /* Make sure operands are in the right order for an addsi3 insn as |
41ef479c | 3913 | generated by a define_split. Nothing but REG_P as the first |
3914 | operand is recognized by addsi3 after reload. OPERANDS contains | |
3915 | the operands, with the first at OPERANDS[N] and the second at | |
3916 | OPERANDS[N+1]. */ | |
af9c3aeb | 3917 | |
3918 | void | |
3919 | cris_order_for_addsi3 (rtx *operands, int n) | |
3920 | { | |
41ef479c | 3921 | if (!REG_P (operands[n])) |
af9c3aeb | 3922 | { |
3923 | rtx tem = operands[n]; | |
3924 | operands[n] = operands[n + 1]; | |
3925 | operands[n + 1] = tem; | |
3926 | } | |
3927 | } | |
3928 | ||
f382dce0 | 3929 | /* Use from within code, from e.g. PRINT_OPERAND and |
3930 | PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit | |
3931 | different things depending on whether code operand or constant is | |
3932 | emitted. */ | |
e03f789f | 3933 | |
f382dce0 | 3934 | static void |
21f64ad5 | 3935 | cris_output_addr_const (FILE *file, rtx x) |
e03f789f | 3936 | { |
f382dce0 | 3937 | in_code++; |
3938 | output_addr_const (file, x); | |
3939 | in_code--; | |
3940 | } | |
e03f789f | 3941 | |
f382dce0 | 3942 | /* Worker function for ASM_OUTPUT_SYMBOL_REF. */ |
e03f789f | 3943 | |
f382dce0 | 3944 | void |
3945 | cris_asm_output_symbol_ref (FILE *file, rtx x) | |
3946 | { | |
6a6dcc7c | 3947 | gcc_assert (GET_CODE (x) == SYMBOL_REF); |
3948 | ||
f382dce0 | 3949 | if (flag_pic && in_code > 0) |
3950 | { | |
6a6dcc7c | 3951 | const char *origstr = XSTR (x, 0); |
3952 | const char *str; | |
3953 | str = (* targetm.strip_name_encoding) (origstr); | |
3954 | assemble_name (file, str); | |
3955 | ||
3956 | /* Sanity check. */ | |
18d50ae6 | 3957 | if (!TARGET_V32 && !crtl->uses_pic_offset_table) |
6a6dcc7c | 3958 | output_operand_lossage ("PIC register isn't set up"); |
f382dce0 | 3959 | } |
3960 | else | |
3961 | assemble_name (file, XSTR (x, 0)); | |
3962 | } | |
e03f789f | 3963 | |
f382dce0 | 3964 | /* Worker function for ASM_OUTPUT_LABEL_REF. */ |
e03f789f | 3965 | |
f382dce0 | 3966 | void |
3967 | cris_asm_output_label_ref (FILE *file, char *buf) | |
3968 | { | |
3969 | if (flag_pic && in_code > 0) | |
3970 | { | |
f382dce0 | 3971 | assemble_name (file, buf); |
e03f789f | 3972 | |
f382dce0 | 3973 | /* Sanity check. */ |
18d50ae6 | 3974 | if (!TARGET_V32 && !crtl->uses_pic_offset_table) |
bf776685 | 3975 | internal_error ("emitting PIC operand, but PIC register " |
3976 | "isn%'t set up"); | |
f382dce0 | 3977 | } |
3978 | else | |
3979 | assemble_name (file, buf); | |
3980 | } | |
e03f789f | 3981 | |
13f42429 | 3982 | /* Worker function for TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */ |
e03f789f | 3983 | |
13f42429 | 3984 | static bool |
6a6dcc7c | 3985 | cris_output_addr_const_extra (FILE *file, rtx xconst) |
f382dce0 | 3986 | { |
6a6dcc7c | 3987 | switch (GET_CODE (xconst)) |
f382dce0 | 3988 | { |
6a6dcc7c | 3989 | rtx x; |
e03f789f | 3990 | |
f382dce0 | 3991 | case UNSPEC: |
6a6dcc7c | 3992 | x = XVECEXP (xconst, 0, 0); |
3993 | CRIS_ASSERT (GET_CODE (x) == SYMBOL_REF | |
3994 | || GET_CODE (x) == LABEL_REF | |
3995 | || GET_CODE (x) == CONST); | |
3996 | output_addr_const (file, x); | |
3997 | switch (XINT (xconst, 1)) | |
e03f789f | 3998 | { |
c85bb9fb | 3999 | case CRIS_UNSPEC_PCREL: |
4000 | /* We only get this with -fpic/PIC to tell it apart from an | |
4001 | invalid symbol. We can't tell here, but it should only | |
4002 | be the operand of a call or movsi. */ | |
4003 | gcc_assert (TARGET_V32 && flag_pic); | |
4004 | break; | |
4005 | ||
4006 | case CRIS_UNSPEC_PLT_PCREL: | |
4007 | gcc_assert (TARGET_V32); | |
4008 | fprintf (file, ":PLT"); | |
4009 | break; | |
4010 | ||
4011 | case CRIS_UNSPEC_PLT_GOTREL: | |
4012 | gcc_assert (!TARGET_V32); | |
f382dce0 | 4013 | fprintf (file, ":PLTG"); |
6a6dcc7c | 4014 | break; |
e03f789f | 4015 | |
6a6dcc7c | 4016 | case CRIS_UNSPEC_GOTREL: |
c85bb9fb | 4017 | gcc_assert (!TARGET_V32); |
6a6dcc7c | 4018 | fprintf (file, ":GOTOFF"); |
4019 | break; | |
f382dce0 | 4020 | |
6a6dcc7c | 4021 | case CRIS_UNSPEC_GOTREAD: |
f382dce0 | 4022 | if (flag_pic == 1) |
6a6dcc7c | 4023 | fprintf (file, ":GOT16"); |
f382dce0 | 4024 | else |
6a6dcc7c | 4025 | fprintf (file, ":GOT"); |
4026 | break; | |
4027 | ||
4028 | case CRIS_UNSPEC_PLTGOTREAD: | |
4029 | if (flag_pic == 1) | |
4030 | fprintf (file, CRIS_GOTPLT_SUFFIX "16"); | |
4031 | else | |
4032 | fprintf (file, CRIS_GOTPLT_SUFFIX); | |
4033 | break; | |
4034 | ||
4035 | default: | |
4036 | gcc_unreachable (); | |
e03f789f | 4037 | } |
f382dce0 | 4038 | return true; |
e03f789f | 4039 | |
4040 | default: | |
f382dce0 | 4041 | return false; |
e03f789f | 4042 | } |
4043 | } | |
4044 | ||
9beb7d17 | 4045 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ |
4046 | ||
4047 | static rtx | |
4048 | cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
4049 | int incoming ATTRIBUTE_UNUSED) | |
4050 | { | |
4051 | return gen_rtx_REG (Pmode, CRIS_STRUCT_VALUE_REGNUM); | |
4052 | } | |
4053 | ||
05b21e76 | 4054 | /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */ |
4055 | ||
4056 | static void | |
39cba157 | 4057 | cris_setup_incoming_varargs (cumulative_args_t ca_v, |
3754d046 | 4058 | machine_mode mode ATTRIBUTE_UNUSED, |
05b21e76 | 4059 | tree type ATTRIBUTE_UNUSED, |
4060 | int *pretend_arg_size, | |
4061 | int second_time) | |
4062 | { | |
39cba157 | 4063 | CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); |
4064 | ||
05b21e76 | 4065 | if (ca->regs < CRIS_MAX_ARGS_IN_REGS) |
05b21e76 | 4066 | { |
dfc30596 | 4067 | int stdarg_regs = CRIS_MAX_ARGS_IN_REGS - ca->regs; |
4068 | cfun->machine->stdarg_regs = stdarg_regs; | |
4069 | *pretend_arg_size = stdarg_regs * 4; | |
05b21e76 | 4070 | } |
dfc30596 | 4071 | |
4072 | if (TARGET_PDEBUG) | |
4073 | fprintf (asm_out_file, | |
4074 | "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n", | |
4075 | ca->regs, *pretend_arg_size, second_time); | |
05b21e76 | 4076 | } |
4077 | ||
b981d932 | 4078 | /* Return true if TYPE must be passed by invisible reference. |
4079 | For cris, we pass <= 8 bytes by value, others by reference. */ | |
4080 | ||
4081 | static bool | |
39cba157 | 4082 | cris_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED, |
3754d046 | 4083 | machine_mode mode, const_tree type, |
b981d932 | 4084 | bool named ATTRIBUTE_UNUSED) |
4085 | { | |
4086 | return (targetm.calls.must_pass_in_stack (mode, type) | |
4087 | || CRIS_FUNCTION_ARG_SIZE (mode, type) > 8); | |
4088 | } | |
4089 | ||
3b2411a8 | 4090 | /* A combination of defining TARGET_PROMOTE_FUNCTION_MODE, promoting arguments |
4091 | and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the | |
4092 | best code size and speed for gcc, ipps and products in gcc-2.7.2. */ | |
4093 | ||
3754d046 | 4094 | machine_mode |
3b2411a8 | 4095 | cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED, |
3754d046 | 4096 | machine_mode mode, |
3b2411a8 | 4097 | int *punsignedp ATTRIBUTE_UNUSED, |
4098 | const_tree fntype ATTRIBUTE_UNUSED, | |
4099 | int for_return) | |
4100 | { | |
4101 | /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even | |
5e9082a7 | 4102 | when modifying TARGET_FUNCTION_VALUE to return the promoted mode). |
4103 | Maybe pointless as of now, but let's keep the old behavior. */ | |
c879dbcf | 4104 | if (for_return == 1) |
3b2411a8 | 4105 | return mode; |
4106 | return CRIS_PROMOTED_MODE (mode, *punsignedp, type); | |
4107 | } | |
4108 | ||
60dc82ea | 4109 | /* Atomic types require alignment to be at least their "natural" size. */ |
4110 | ||
4111 | static unsigned int | |
3754d046 | 4112 | cris_atomic_align_for_mode (machine_mode mode) |
60dc82ea | 4113 | { |
4114 | return GET_MODE_BITSIZE (mode); | |
4115 | } | |
4116 | ||
5e9082a7 | 4117 | /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the |
4118 | time being. */ | |
4119 | ||
4120 | static rtx | |
4121 | cris_function_value(const_tree type, | |
4122 | const_tree func ATTRIBUTE_UNUSED, | |
4123 | bool outgoing ATTRIBUTE_UNUSED) | |
4124 | { | |
4125 | return gen_rtx_REG (TYPE_MODE (type), CRIS_FIRST_ARG_REG); | |
4126 | } | |
4127 | ||
4128 | /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the | |
4129 | time being. */ | |
4130 | ||
4131 | static rtx | |
3754d046 | 4132 | cris_libcall_value (machine_mode mode, |
5e9082a7 | 4133 | const_rtx fun ATTRIBUTE_UNUSED) |
4134 | { | |
4135 | return gen_rtx_REG (mode, CRIS_FIRST_ARG_REG); | |
4136 | } | |
4137 | ||
4138 | /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the | |
4139 | time being. */ | |
4140 | ||
7a5dfde8 | 4141 | static bool |
5e9082a7 | 4142 | cris_function_value_regno_p (const unsigned int regno) |
4143 | { | |
4144 | return (regno == CRIS_FIRST_ARG_REG); | |
4145 | } | |
b981d932 | 4146 | |
f054eb3c | 4147 | static int |
3754d046 | 4148 | cris_arg_partial_bytes (cumulative_args_t ca, machine_mode mode, |
f054eb3c | 4149 | tree type, bool named ATTRIBUTE_UNUSED) |
4150 | { | |
39cba157 | 4151 | if (get_cumulative_args (ca)->regs == CRIS_MAX_ARGS_IN_REGS - 1 |
f054eb3c | 4152 | && !targetm.calls.must_pass_in_stack (mode, type) |
4153 | && CRIS_FUNCTION_ARG_SIZE (mode, type) > 4 | |
4154 | && CRIS_FUNCTION_ARG_SIZE (mode, type) <= 8) | |
4155 | return UNITS_PER_WORD; | |
4156 | else | |
4157 | return 0; | |
4158 | } | |
4159 | ||
0834de52 | 4160 | static rtx |
39cba157 | 4161 | cris_function_arg_1 (cumulative_args_t ca_v, |
3754d046 | 4162 | machine_mode mode ATTRIBUTE_UNUSED, |
0834de52 | 4163 | const_tree type ATTRIBUTE_UNUSED, |
4164 | bool named, bool incoming) | |
4165 | { | |
39cba157 | 4166 | const CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); |
4167 | ||
0834de52 | 4168 | if ((!incoming || named) && ca->regs < CRIS_MAX_ARGS_IN_REGS) |
4169 | return gen_rtx_REG (mode, CRIS_FIRST_ARG_REG + ca->regs); | |
4170 | else | |
4171 | return NULL_RTX; | |
4172 | } | |
4173 | ||
4174 | /* Worker function for TARGET_FUNCTION_ARG. | |
4175 | The void_type_node is sent as a "closing" call. */ | |
4176 | ||
4177 | static rtx | |
3754d046 | 4178 | cris_function_arg (cumulative_args_t ca, machine_mode mode, |
0834de52 | 4179 | const_tree type, bool named) |
4180 | { | |
4181 | return cris_function_arg_1 (ca, mode, type, named, false); | |
4182 | } | |
4183 | ||
4184 | /* Worker function for TARGET_FUNCTION_INCOMING_ARG. | |
4185 | ||
4186 | The differences between this and the previous, is that this one checks | |
4187 | that an argument is named, since incoming stdarg/varargs arguments are | |
4188 | pushed onto the stack, and we don't have to check against the "closing" | |
4189 | void_type_node TYPE parameter. */ | |
4190 | ||
4191 | static rtx | |
3754d046 | 4192 | cris_function_incoming_arg (cumulative_args_t ca, machine_mode mode, |
0834de52 | 4193 | const_tree type, bool named) |
4194 | { | |
4195 | return cris_function_arg_1 (ca, mode, type, named, true); | |
4196 | } | |
4197 | ||
4198 | /* Worker function for TARGET_FUNCTION_ARG_ADVANCE. */ | |
4199 | ||
4200 | static void | |
3754d046 | 4201 | cris_function_arg_advance (cumulative_args_t ca_v, machine_mode mode, |
0834de52 | 4202 | const_tree type, bool named ATTRIBUTE_UNUSED) |
4203 | { | |
39cba157 | 4204 | CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); |
4205 | ||
0834de52 | 4206 | ca->regs += (3 + CRIS_FUNCTION_ARG_SIZE (mode, type)) / 4; |
4207 | } | |
4208 | ||
8a2947fe | 4209 | /* Worker function for TARGET_MD_ASM_CLOBBERS. */ |
4210 | ||
4211 | static tree | |
2586cf34 | 4212 | cris_md_asm_clobbers (tree outputs, tree inputs, tree in_clobbers) |
8a2947fe | 4213 | { |
64d5fb6a | 4214 | HARD_REG_SET mof_set; |
2586cf34 | 4215 | tree clobbers; |
64d5fb6a | 4216 | tree t; |
4217 | ||
4218 | CLEAR_HARD_REG_SET (mof_set); | |
4219 | SET_HARD_REG_BIT (mof_set, CRIS_MOF_REGNUM); | |
4220 | ||
2586cf34 | 4221 | /* For the time being, all asms clobber condition codes. Revisit when |
4222 | there's a reasonable use for inputs/outputs that mention condition | |
4223 | codes. */ | |
4224 | clobbers | |
4225 | = tree_cons (NULL_TREE, | |
4226 | build_string (strlen (reg_names[CRIS_CC0_REGNUM]), | |
4227 | reg_names[CRIS_CC0_REGNUM]), | |
4228 | in_clobbers); | |
4229 | ||
64d5fb6a | 4230 | for (t = outputs; t != NULL; t = TREE_CHAIN (t)) |
4231 | { | |
4232 | tree val = TREE_VALUE (t); | |
4233 | ||
4234 | /* The constraint letter for the singleton register class of MOF | |
4235 | is 'h'. If it's mentioned in the constraints, the asm is | |
4236 | MOF-aware and adding it to the clobbers would cause it to have | |
4237 | impossible constraints. */ | |
4238 | if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t))), | |
4239 | 'h') != NULL | |
2389b26b | 4240 | || tree_overlaps_hard_reg_set (val, &mof_set) != NULL_TREE) |
64d5fb6a | 4241 | return clobbers; |
4242 | } | |
4243 | ||
4244 | for (t = inputs; t != NULL; t = TREE_CHAIN (t)) | |
4245 | { | |
4246 | tree val = TREE_VALUE (t); | |
4247 | ||
4248 | if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t))), | |
4249 | 'h') != NULL | |
2389b26b | 4250 | || tree_overlaps_hard_reg_set (val, &mof_set) != NULL_TREE) |
64d5fb6a | 4251 | return clobbers; |
4252 | } | |
4253 | ||
8a2947fe | 4254 | return tree_cons (NULL_TREE, |
4255 | build_string (strlen (reg_names[CRIS_MOF_REGNUM]), | |
4256 | reg_names[CRIS_MOF_REGNUM]), | |
4257 | clobbers); | |
4258 | } | |
f054eb3c | 4259 | |
5a1c68c3 | 4260 | /* Implement TARGET_FRAME_POINTER_REQUIRED. |
4261 | ||
4262 | Really only needed if the stack frame has variable length (alloca | |
4263 | or variable sized local arguments (GNU C extension). See PR39499 and | |
4264 | PR38609 for the reason this isn't just 0. */ | |
4265 | ||
4266 | bool | |
4267 | cris_frame_pointer_required (void) | |
4268 | { | |
d5bf7b64 | 4269 | return !crtl->sp_is_unchanging; |
5a1c68c3 | 4270 | } |
4271 | ||
f6ddc27b | 4272 | /* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE. |
4273 | ||
4274 | This looks too complicated, and it is. I assigned r7 to be the | |
4275 | static chain register, but it is call-saved, so we have to save it, | |
4276 | and come back to restore it after the call, so we have to save srp... | |
4277 | Anyway, trampolines are rare enough that we can cope with this | |
4278 | somewhat lack of elegance. | |
4279 | (Do not be tempted to "straighten up" whitespace in the asms; the | |
4280 | assembler #NO_APP state mandates strict spacing). */ | |
4281 | /* ??? See the i386 regparm=3 implementation that pushes the static | |
4282 | chain value to the stack in the trampoline, and uses a call-saved | |
4283 | register when called directly. */ | |
4284 | ||
4285 | static void | |
4286 | cris_asm_trampoline_template (FILE *f) | |
4287 | { | |
4288 | if (TARGET_V32) | |
4289 | { | |
4290 | /* This normally-unused nop insn acts as an instruction to | |
4291 | the simulator to flush its instruction cache. None of | |
4292 | the other instructions in the trampoline template suits | |
4293 | as a trigger for V32. The pc-relative addressing mode | |
4294 | works nicely as a trigger for V10. | |
4295 | FIXME: Have specific V32 template (possibly avoiding the | |
4296 | use of a special instruction). */ | |
4297 | fprintf (f, "\tclearf x\n"); | |
4298 | /* We have to use a register as an intermediate, choosing | |
4299 | semi-randomly R1 (which has to not be the STATIC_CHAIN_REGNUM), | |
4300 | so we can use it for address indirection and jsr target. */ | |
4301 | fprintf (f, "\tmove $r1,$mof\n"); | |
4302 | /* +4 */ | |
4303 | fprintf (f, "\tmove.d 0,$r1\n"); | |
4304 | fprintf (f, "\tmove.d $%s,[$r1]\n", reg_names[STATIC_CHAIN_REGNUM]); | |
4305 | fprintf (f, "\taddq 6,$r1\n"); | |
4306 | fprintf (f, "\tmove $mof,[$r1]\n"); | |
4307 | fprintf (f, "\taddq 6,$r1\n"); | |
4308 | fprintf (f, "\tmove $srp,[$r1]\n"); | |
4309 | /* +20 */ | |
4310 | fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); | |
4311 | /* +26 */ | |
4312 | fprintf (f, "\tmove.d 0,$r1\n"); | |
4313 | fprintf (f, "\tjsr $r1\n"); | |
4314 | fprintf (f, "\tsetf\n"); | |
4315 | /* +36 */ | |
4316 | fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); | |
4317 | /* +42 */ | |
4318 | fprintf (f, "\tmove.d 0,$r1\n"); | |
4319 | /* +48 */ | |
4320 | fprintf (f, "\tmove.d 0,$r9\n"); | |
4321 | fprintf (f, "\tjump $r9\n"); | |
4322 | fprintf (f, "\tsetf\n"); | |
4323 | } | |
4324 | else | |
4325 | { | |
4326 | fprintf (f, "\tmove.d $%s,[$pc+20]\n", reg_names[STATIC_CHAIN_REGNUM]); | |
4327 | fprintf (f, "\tmove $srp,[$pc+22]\n"); | |
4328 | fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); | |
4329 | fprintf (f, "\tjsr 0\n"); | |
4330 | fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); | |
4331 | fprintf (f, "\tjump 0\n"); | |
4332 | } | |
4333 | } | |
4334 | ||
4335 | /* Implement TARGET_TRAMPOLINE_INIT. */ | |
4336 | ||
4337 | static void | |
4338 | cris_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
4339 | { | |
4340 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
4341 | rtx tramp = XEXP (m_tramp, 0); | |
4342 | rtx mem; | |
4343 | ||
4344 | emit_block_move (m_tramp, assemble_trampoline_template (), | |
4345 | GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); | |
4346 | ||
4347 | if (TARGET_V32) | |
4348 | { | |
4349 | mem = adjust_address (m_tramp, SImode, 6); | |
29c05e22 | 4350 | emit_move_insn (mem, plus_constant (Pmode, tramp, 38)); |
f6ddc27b | 4351 | mem = adjust_address (m_tramp, SImode, 22); |
4352 | emit_move_insn (mem, chain_value); | |
4353 | mem = adjust_address (m_tramp, SImode, 28); | |
4354 | emit_move_insn (mem, fnaddr); | |
4355 | } | |
4356 | else | |
4357 | { | |
4358 | mem = adjust_address (m_tramp, SImode, 10); | |
4359 | emit_move_insn (mem, chain_value); | |
4360 | mem = adjust_address (m_tramp, SImode, 16); | |
4361 | emit_move_insn (mem, fnaddr); | |
4362 | } | |
4363 | ||
4364 | /* Note that there is no need to do anything with the cache for | |
4365 | sake of a trampoline. */ | |
4366 | } | |
4367 | ||
4368 | ||
e03f789f | 4369 | #if 0 |
4370 | /* Various small functions to replace macros. Only called from a | |
4371 | debugger. They might collide with gcc functions or system functions, | |
4372 | so only emit them when '#if 1' above. */ | |
4373 | ||
21f64ad5 | 4374 | enum rtx_code Get_code (rtx); |
e03f789f | 4375 | |
4376 | enum rtx_code | |
21f64ad5 | 4377 | Get_code (rtx x) |
e03f789f | 4378 | { |
4379 | return GET_CODE (x); | |
4380 | } | |
4381 | ||
21f64ad5 | 4382 | const char *Get_mode (rtx); |
e03f789f | 4383 | |
4384 | const char * | |
21f64ad5 | 4385 | Get_mode (rtx x) |
e03f789f | 4386 | { |
4387 | return GET_MODE_NAME (GET_MODE (x)); | |
4388 | } | |
4389 | ||
21f64ad5 | 4390 | rtx Xexp (rtx, int); |
e03f789f | 4391 | |
4392 | rtx | |
21f64ad5 | 4393 | Xexp (rtx x, int n) |
e03f789f | 4394 | { |
4395 | return XEXP (x, n); | |
4396 | } | |
4397 | ||
21f64ad5 | 4398 | rtx Xvecexp (rtx, int, int); |
e03f789f | 4399 | |
4400 | rtx | |
21f64ad5 | 4401 | Xvecexp (rtx x, int n, int m) |
7f9cab51 | 4402 | { |
e03f789f | 4403 | return XVECEXP (x, n, m); |
4404 | } | |
4405 | ||
21f64ad5 | 4406 | int Get_rtx_len (rtx); |
e03f789f | 4407 | |
4408 | int | |
21f64ad5 | 4409 | Get_rtx_len (rtx x) |
e03f789f | 4410 | { |
4411 | return GET_RTX_LENGTH (GET_CODE (x)); | |
4412 | } | |
4413 | ||
4414 | /* Use upper-case to distinguish from local variables that are sometimes | |
4415 | called next_insn and prev_insn. */ | |
4416 | ||
21f64ad5 | 4417 | rtx Next_insn (rtx); |
e03f789f | 4418 | |
4419 | rtx | |
21f64ad5 | 4420 | Next_insn (rtx insn) |
e03f789f | 4421 | { |
4422 | return NEXT_INSN (insn); | |
4423 | } | |
4424 | ||
21f64ad5 | 4425 | rtx Prev_insn (rtx); |
e03f789f | 4426 | |
4427 | rtx | |
21f64ad5 | 4428 | Prev_insn (rtx insn) |
e03f789f | 4429 | { |
4430 | return PREV_INSN (insn); | |
4431 | } | |
4432 | #endif | |
4433 | ||
1f3233d1 | 4434 | #include "gt-cris.h" |
4435 | ||
e03f789f | 4436 | /* |
4437 | * Local variables: | |
4438 | * eval: (c-set-style "gnu") | |
4439 | * indent-tabs-mode: t | |
4440 | * End: | |
4441 | */ |