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0b85d816 | 1 | /* Definitions for GCC. Part of the machine description for CRIS. |
23a5b65a | 2 | Copyright (C) 1998-2014 Free Software Foundation, Inc. |
0b85d816 HPN |
3 | Contributed by Axis Communications. Written by Hans-Peter Nilsson. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
2f83c7d6 | 9 | the Free Software Foundation; either version 3, or (at your option) |
0b85d816 HPN |
10 | any later version. |
11 | ||
12 | GCC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
0b85d816 HPN |
20 | |
21 | #include "config.h" | |
22 | #include "system.h" | |
4977bab6 ZW |
23 | #include "coretypes.h" |
24 | #include "tm.h" | |
0b85d816 HPN |
25 | #include "rtl.h" |
26 | #include "regs.h" | |
27 | #include "hard-reg-set.h" | |
0b85d816 HPN |
28 | #include "insn-config.h" |
29 | #include "conditions.h" | |
0b85d816 HPN |
30 | #include "insn-attr.h" |
31 | #include "flags.h" | |
32 | #include "tree.h" | |
d8a2d370 DN |
33 | #include "varasm.h" |
34 | #include "stor-layout.h" | |
35 | #include "calls.h" | |
36 | #include "stmt.h" | |
0b85d816 HPN |
37 | #include "expr.h" |
38 | #include "except.h" | |
39 | #include "function.h" | |
718f9c0f | 40 | #include "diagnostic-core.h" |
0b85d816 | 41 | #include "recog.h" |
15883505 | 42 | #include "reload.h" |
0b85d816 HPN |
43 | #include "tm_p.h" |
44 | #include "debug.h" | |
78b14aa6 | 45 | #include "output.h" |
06cadf63 | 46 | #include "tm-constrs.h" |
0b85d816 HPN |
47 | #include "target.h" |
48 | #include "target-def.h" | |
ae9dbf1f | 49 | #include "ggc.h" |
c15c90bb | 50 | #include "optabs.h" |
a3ef2349 | 51 | #include "df.h" |
96e45421 | 52 | #include "opts.h" |
3e71d953 | 53 | #include "cgraph.h" |
0b85d816 HPN |
54 | |
55 | /* Usable when we have an amount to add or subtract, and want the | |
56 | optimal size of the insn. */ | |
57 | #define ADDITIVE_SIZE_MODIFIER(size) \ | |
58 | ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d") | |
59 | ||
a52453cc | 60 | #define LOSE_AND_RETURN(msgid, x) \ |
3d556836 HPN |
61 | do \ |
62 | { \ | |
a52453cc | 63 | cris_operand_lossage (msgid, x); \ |
3d556836 HPN |
64 | return; \ |
65 | } while (0) | |
66 | ||
04539954 HPN |
67 | enum cris_retinsn_type |
68 | { CRIS_RETINSN_UNKNOWN = 0, CRIS_RETINSN_RET, CRIS_RETINSN_JUMP }; | |
69 | ||
0b85d816 | 70 | /* Per-function machine data. */ |
d1b38208 | 71 | struct GTY(()) machine_function |
0b85d816 HPN |
72 | { |
73 | int needs_return_address_on_stack; | |
d29b4b1b HPN |
74 | |
75 | /* This is the number of registers we save in the prologue due to | |
76 | stdarg. */ | |
77 | int stdarg_regs; | |
78 | ||
04539954 | 79 | enum cris_retinsn_type return_type; |
0b85d816 HPN |
80 | }; |
81 | ||
0b85d816 HPN |
82 | /* This little fix suppresses the 'u' or 's' when '%e' in assembly |
83 | pattern. */ | |
84 | static char cris_output_insn_is_bound = 0; | |
85 | ||
453bd0f5 HPN |
86 | /* In code for output macros, this is how we know whether e.g. constant |
87 | goes in code or in a static initializer. */ | |
88 | static int in_code = 0; | |
89 | ||
3d556836 | 90 | /* Fix for reg_overlap_mentioned_p. */ |
6640377c | 91 | static int cris_reg_overlap_mentioned_p (rtx, rtx); |
0b85d816 | 92 | |
cde0f3fd PB |
93 | static enum machine_mode cris_promote_function_mode (const_tree, enum machine_mode, |
94 | int *, const_tree, int); | |
95 | ||
faee0106 HPN |
96 | static unsigned int cris_atomic_align_for_mode (enum machine_mode); |
97 | ||
6640377c | 98 | static void cris_print_base (rtx, FILE *); |
0b85d816 | 99 | |
6640377c | 100 | static void cris_print_index (rtx, FILE *); |
0b85d816 | 101 | |
453bd0f5 HPN |
102 | static void cris_output_addr_const (FILE *, rtx); |
103 | ||
6640377c | 104 | static struct machine_function * cris_init_machine_status (void); |
0b85d816 | 105 | |
a2fef3a4 KH |
106 | static rtx cris_struct_value_rtx (tree, int); |
107 | ||
d5cc9181 | 108 | static void cris_setup_incoming_varargs (cumulative_args_t, enum machine_mode, |
558d352a KH |
109 | tree type, int *, int); |
110 | ||
6640377c | 111 | static int cris_initial_frame_pointer_offset (void); |
3d556836 | 112 | |
6640377c | 113 | static void cris_operand_lossage (const char *, rtx); |
3d556836 | 114 | |
04539954 HPN |
115 | static int cris_reg_saved_in_regsave_area (unsigned int, bool); |
116 | ||
ed5c4a10 NF |
117 | static void cris_print_operand (FILE *, rtx, int); |
118 | ||
119 | static void cris_print_operand_address (FILE *, rtx); | |
120 | ||
121 | static bool cris_print_operand_punct_valid_p (unsigned char code); | |
122 | ||
586747fc AS |
123 | static bool cris_output_addr_const_extra (FILE *, rtx); |
124 | ||
5efd84c5 NF |
125 | static void cris_conditional_register_usage (void); |
126 | ||
c590b625 | 127 | static void cris_asm_output_mi_thunk |
6640377c | 128 | (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree); |
c590b625 | 129 | |
6640377c | 130 | static void cris_file_start (void); |
c15c90bb | 131 | static void cris_init_libfuncs (void); |
1bc7c5b6 | 132 | |
45dbdfd4 AS |
133 | static reg_class_t cris_preferred_reload_class (rtx, reg_class_t); |
134 | ||
b95491a0 AS |
135 | static int cris_register_move_cost (enum machine_mode, reg_class_t, reg_class_t); |
136 | static int cris_memory_move_cost (enum machine_mode, reg_class_t, bool); | |
68f932c4 | 137 | static bool cris_rtx_costs (rtx, int, int, int, int *, bool); |
b413068c | 138 | static int cris_address_cost (rtx, enum machine_mode, addr_space_t, bool); |
d5cc9181 | 139 | static bool cris_pass_by_reference (cumulative_args_t, enum machine_mode, |
586de218 | 140 | const_tree, bool); |
d5cc9181 | 141 | static int cris_arg_partial_bytes (cumulative_args_t, enum machine_mode, |
78a52f11 | 142 | tree, bool); |
d5cc9181 | 143 | static rtx cris_function_arg (cumulative_args_t, enum machine_mode, |
73f3f841 | 144 | const_tree, bool); |
d5cc9181 | 145 | static rtx cris_function_incoming_arg (cumulative_args_t, |
73f3f841 | 146 | enum machine_mode, const_tree, bool); |
d5cc9181 | 147 | static void cris_function_arg_advance (cumulative_args_t, enum machine_mode, |
73f3f841 | 148 | const_tree, bool); |
61158923 | 149 | static tree cris_md_asm_clobbers (tree, tree, tree); |
c590b625 | 150 | |
c5387660 | 151 | static void cris_option_override (void); |
2a186d97 | 152 | |
b52b1749 AS |
153 | static bool cris_frame_pointer_required (void); |
154 | ||
3e322b77 RH |
155 | static void cris_asm_trampoline_template (FILE *); |
156 | static void cris_trampoline_init (rtx, tree, rtx); | |
157 | ||
4d696ad0 AS |
158 | static rtx cris_function_value(const_tree, const_tree, bool); |
159 | static rtx cris_libcall_value (enum machine_mode, const_rtx); | |
2283c416 | 160 | static bool cris_function_value_regno_p (const unsigned int); |
922a784c | 161 | static void cris_file_end (void); |
4d696ad0 | 162 | |
0b85d816 HPN |
163 | /* This is the parsed result of the "-max-stack-stackframe=" option. If |
164 | it (still) is zero, then there was no such option given. */ | |
165 | int cris_max_stackframe = 0; | |
166 | ||
167 | /* This is the parsed result of the "-march=" option, if given. */ | |
168 | int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION; | |
169 | ||
301d03af RS |
170 | #undef TARGET_ASM_ALIGNED_HI_OP |
171 | #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
172 | #undef TARGET_ASM_ALIGNED_SI_OP | |
173 | #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t" | |
174 | #undef TARGET_ASM_ALIGNED_DI_OP | |
175 | #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" | |
176 | ||
177 | /* We need to define these, since the 2byte, 4byte, 8byte op:s are only | |
178 | available in ELF. These "normal" pseudos do not have any alignment | |
179 | constraints or side-effects. */ | |
180 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
181 | #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP | |
182 | ||
183 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
184 | #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP | |
185 | ||
186 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
187 | #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP | |
188 | ||
ed5c4a10 NF |
189 | #undef TARGET_PRINT_OPERAND |
190 | #define TARGET_PRINT_OPERAND cris_print_operand | |
191 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
192 | #define TARGET_PRINT_OPERAND_ADDRESS cris_print_operand_address | |
193 | #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P | |
194 | #define TARGET_PRINT_OPERAND_PUNCT_VALID_P cris_print_operand_punct_valid_p | |
586747fc AS |
195 | #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA |
196 | #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA cris_output_addr_const_extra | |
ed5c4a10 | 197 | |
5efd84c5 NF |
198 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
199 | #define TARGET_CONDITIONAL_REGISTER_USAGE cris_conditional_register_usage | |
200 | ||
c590b625 RH |
201 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
202 | #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk | |
3961e8fe RH |
203 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
204 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
c590b625 | 205 | |
1bc7c5b6 ZW |
206 | #undef TARGET_ASM_FILE_START |
207 | #define TARGET_ASM_FILE_START cris_file_start | |
922a784c HPN |
208 | #undef TARGET_ASM_FILE_END |
209 | #define TARGET_ASM_FILE_END cris_file_end | |
1bc7c5b6 | 210 | |
c15c90bb ZW |
211 | #undef TARGET_INIT_LIBFUNCS |
212 | #define TARGET_INIT_LIBFUNCS cris_init_libfuncs | |
213 | ||
a08160c3 AS |
214 | #undef TARGET_LEGITIMATE_ADDRESS_P |
215 | #define TARGET_LEGITIMATE_ADDRESS_P cris_legitimate_address_p | |
216 | ||
45dbdfd4 AS |
217 | #undef TARGET_PREFERRED_RELOAD_CLASS |
218 | #define TARGET_PREFERRED_RELOAD_CLASS cris_preferred_reload_class | |
219 | ||
b95491a0 AS |
220 | #undef TARGET_REGISTER_MOVE_COST |
221 | #define TARGET_REGISTER_MOVE_COST cris_register_move_cost | |
222 | #undef TARGET_MEMORY_MOVE_COST | |
223 | #define TARGET_MEMORY_MOVE_COST cris_memory_move_cost | |
75642f32 RH |
224 | #undef TARGET_RTX_COSTS |
225 | #define TARGET_RTX_COSTS cris_rtx_costs | |
226 | #undef TARGET_ADDRESS_COST | |
227 | #define TARGET_ADDRESS_COST cris_address_cost | |
228 | ||
cde0f3fd PB |
229 | #undef TARGET_PROMOTE_FUNCTION_MODE |
230 | #define TARGET_PROMOTE_FUNCTION_MODE cris_promote_function_mode | |
231 | ||
faee0106 HPN |
232 | #undef TARGET_ATOMIC_ALIGN_FOR_MODE |
233 | #define TARGET_ATOMIC_ALIGN_FOR_MODE cris_atomic_align_for_mode | |
234 | ||
a2fef3a4 KH |
235 | #undef TARGET_STRUCT_VALUE_RTX |
236 | #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx | |
558d352a KH |
237 | #undef TARGET_SETUP_INCOMING_VARARGS |
238 | #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs | |
8cd5a4e0 RH |
239 | #undef TARGET_PASS_BY_REFERENCE |
240 | #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference | |
78a52f11 RH |
241 | #undef TARGET_ARG_PARTIAL_BYTES |
242 | #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes | |
73f3f841 NF |
243 | #undef TARGET_FUNCTION_ARG |
244 | #define TARGET_FUNCTION_ARG cris_function_arg | |
245 | #undef TARGET_FUNCTION_INCOMING_ARG | |
246 | #define TARGET_FUNCTION_INCOMING_ARG cris_function_incoming_arg | |
247 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
248 | #define TARGET_FUNCTION_ARG_ADVANCE cris_function_arg_advance | |
f60c7155 HPN |
249 | #undef TARGET_MD_ASM_CLOBBERS |
250 | #define TARGET_MD_ASM_CLOBBERS cris_md_asm_clobbers | |
b52b1749 AS |
251 | #undef TARGET_FRAME_POINTER_REQUIRED |
252 | #define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required | |
558d352a | 253 | |
c5387660 JM |
254 | #undef TARGET_OPTION_OVERRIDE |
255 | #define TARGET_OPTION_OVERRIDE cris_option_override | |
256 | ||
3e322b77 RH |
257 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE |
258 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE cris_asm_trampoline_template | |
259 | #undef TARGET_TRAMPOLINE_INIT | |
260 | #define TARGET_TRAMPOLINE_INIT cris_trampoline_init | |
261 | ||
4d696ad0 AS |
262 | #undef TARGET_FUNCTION_VALUE |
263 | #define TARGET_FUNCTION_VALUE cris_function_value | |
264 | #undef TARGET_LIBCALL_VALUE | |
265 | #define TARGET_LIBCALL_VALUE cris_libcall_value | |
2283c416 AS |
266 | #undef TARGET_FUNCTION_VALUE_REGNO_P |
267 | #define TARGET_FUNCTION_VALUE_REGNO_P cris_function_value_regno_p | |
4d696ad0 | 268 | |
0b85d816 HPN |
269 | struct gcc_target targetm = TARGET_INITIALIZER; |
270 | ||
04539954 HPN |
271 | /* Helper for cris_load_multiple_op and cris_ret_movem_op. */ |
272 | ||
68a81332 | 273 | bool |
04539954 HPN |
274 | cris_movem_load_rest_p (rtx op, int offs) |
275 | { | |
276 | unsigned int reg_count = XVECLEN (op, 0) - offs; | |
277 | rtx src_addr; | |
278 | int i; | |
279 | rtx elt; | |
280 | int setno; | |
281 | int regno_dir = 1; | |
282 | unsigned int regno = 0; | |
283 | ||
284 | /* Perform a quick check so we don't blow up below. FIXME: Adjust for | |
285 | other than (MEM reg). */ | |
286 | if (reg_count <= 1 | |
287 | || GET_CODE (XVECEXP (op, 0, offs)) != SET | |
991c42ac JBG |
288 | || !REG_P (SET_DEST (XVECEXP (op, 0, offs))) |
289 | || !MEM_P (SET_SRC (XVECEXP (op, 0, offs)))) | |
68a81332 | 290 | return false; |
04539954 HPN |
291 | |
292 | /* Check a possible post-inc indicator. */ | |
293 | if (GET_CODE (SET_SRC (XVECEXP (op, 0, offs + 1))) == PLUS) | |
294 | { | |
295 | rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 0); | |
296 | rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 1); | |
297 | ||
298 | reg_count--; | |
299 | ||
300 | if (reg_count == 1 | |
301 | || !REG_P (reg) | |
302 | || !REG_P (SET_DEST (XVECEXP (op, 0, offs + 1))) | |
303 | || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, offs + 1))) | |
991c42ac | 304 | || !CONST_INT_P (inc) |
04539954 | 305 | || INTVAL (inc) != (HOST_WIDE_INT) reg_count * 4) |
68a81332 | 306 | return false; |
04539954 HPN |
307 | i = offs + 2; |
308 | } | |
309 | else | |
310 | i = offs + 1; | |
311 | ||
c31500c2 HPN |
312 | if (!TARGET_V32) |
313 | { | |
314 | regno_dir = -1; | |
315 | regno = reg_count - 1; | |
316 | } | |
04539954 HPN |
317 | |
318 | elt = XVECEXP (op, 0, offs); | |
319 | src_addr = XEXP (SET_SRC (elt), 0); | |
320 | ||
321 | if (GET_CODE (elt) != SET | |
991c42ac | 322 | || !REG_P (SET_DEST (elt)) |
04539954 HPN |
323 | || GET_MODE (SET_DEST (elt)) != SImode |
324 | || REGNO (SET_DEST (elt)) != regno | |
991c42ac | 325 | || !MEM_P (SET_SRC (elt)) |
04539954 HPN |
326 | || GET_MODE (SET_SRC (elt)) != SImode |
327 | || !memory_address_p (SImode, src_addr)) | |
68a81332 | 328 | return false; |
04539954 HPN |
329 | |
330 | for (setno = 1; i < XVECLEN (op, 0); setno++, i++) | |
331 | { | |
332 | rtx elt = XVECEXP (op, 0, i); | |
333 | regno += regno_dir; | |
334 | ||
335 | if (GET_CODE (elt) != SET | |
991c42ac | 336 | || !REG_P (SET_DEST (elt)) |
04539954 HPN |
337 | || GET_MODE (SET_DEST (elt)) != SImode |
338 | || REGNO (SET_DEST (elt)) != regno | |
991c42ac | 339 | || !MEM_P (SET_SRC (elt)) |
04539954 HPN |
340 | || GET_MODE (SET_SRC (elt)) != SImode |
341 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
342 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
991c42ac | 343 | || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt), 0), 1)) |
04539954 | 344 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != setno * 4) |
68a81332 | 345 | return false; |
04539954 HPN |
346 | } |
347 | ||
68a81332 | 348 | return true; |
04539954 HPN |
349 | } |
350 | ||
68a81332 HPN |
351 | /* Worker function for predicate for the parallel contents in a movem |
352 | to-memory. */ | |
d29b4b1b | 353 | |
68a81332 HPN |
354 | bool |
355 | cris_store_multiple_op_p (rtx op) | |
d29b4b1b HPN |
356 | { |
357 | int reg_count = XVECLEN (op, 0); | |
358 | rtx dest; | |
359 | rtx dest_addr; | |
360 | rtx dest_base; | |
361 | int i; | |
362 | rtx elt; | |
363 | int setno; | |
364 | int regno_dir = 1; | |
365 | int regno = 0; | |
366 | int offset = 0; | |
367 | ||
368 | /* Perform a quick check so we don't blow up below. FIXME: Adjust for | |
369 | other than (MEM reg) and (MEM (PLUS reg const)). */ | |
370 | if (reg_count <= 1) | |
68a81332 | 371 | return false; |
d29b4b1b HPN |
372 | |
373 | elt = XVECEXP (op, 0, 0); | |
374 | ||
375 | if (GET_CODE (elt) != SET) | |
68a81332 | 376 | return false; |
d29b4b1b HPN |
377 | |
378 | dest = SET_DEST (elt); | |
379 | ||
991c42ac | 380 | if (!REG_P (SET_SRC (elt)) || !MEM_P (dest)) |
68a81332 | 381 | return false; |
d29b4b1b HPN |
382 | |
383 | dest_addr = XEXP (dest, 0); | |
384 | ||
385 | /* Check a possible post-inc indicator. */ | |
386 | if (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS) | |
387 | { | |
388 | rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 0); | |
389 | rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1); | |
390 | ||
391 | reg_count--; | |
392 | ||
393 | if (reg_count == 1 | |
394 | || !REG_P (reg) | |
395 | || !REG_P (SET_DEST (XVECEXP (op, 0, 1))) | |
396 | || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, 1))) | |
991c42ac | 397 | || !CONST_INT_P (inc) |
d29b4b1b HPN |
398 | /* Support increment by number of registers, and by the offset |
399 | of the destination, if it has the form (MEM (PLUS reg | |
400 | offset)). */ | |
401 | || !((REG_P (dest_addr) | |
402 | && REGNO (dest_addr) == REGNO (reg) | |
403 | && INTVAL (inc) == (HOST_WIDE_INT) reg_count * 4) | |
404 | || (GET_CODE (dest_addr) == PLUS | |
405 | && REG_P (XEXP (dest_addr, 0)) | |
406 | && REGNO (XEXP (dest_addr, 0)) == REGNO (reg) | |
991c42ac | 407 | && CONST_INT_P (XEXP (dest_addr, 1)) |
d29b4b1b | 408 | && INTVAL (XEXP (dest_addr, 1)) == INTVAL (inc)))) |
68a81332 | 409 | return false; |
d29b4b1b HPN |
410 | |
411 | i = 2; | |
412 | } | |
413 | else | |
414 | i = 1; | |
415 | ||
c31500c2 HPN |
416 | if (!TARGET_V32) |
417 | { | |
418 | regno_dir = -1; | |
419 | regno = reg_count - 1; | |
420 | } | |
d29b4b1b HPN |
421 | |
422 | if (GET_CODE (elt) != SET | |
991c42ac | 423 | || !REG_P (SET_SRC (elt)) |
d29b4b1b HPN |
424 | || GET_MODE (SET_SRC (elt)) != SImode |
425 | || REGNO (SET_SRC (elt)) != (unsigned int) regno | |
991c42ac | 426 | || !MEM_P (SET_DEST (elt)) |
d29b4b1b | 427 | || GET_MODE (SET_DEST (elt)) != SImode) |
68a81332 | 428 | return false; |
d29b4b1b HPN |
429 | |
430 | if (REG_P (dest_addr)) | |
431 | { | |
432 | dest_base = dest_addr; | |
433 | offset = 0; | |
434 | } | |
435 | else if (GET_CODE (dest_addr) == PLUS | |
436 | && REG_P (XEXP (dest_addr, 0)) | |
991c42ac | 437 | && CONST_INT_P (XEXP (dest_addr, 1))) |
d29b4b1b HPN |
438 | { |
439 | dest_base = XEXP (dest_addr, 0); | |
440 | offset = INTVAL (XEXP (dest_addr, 1)); | |
441 | } | |
442 | else | |
68a81332 | 443 | return false; |
d29b4b1b HPN |
444 | |
445 | for (setno = 1; i < XVECLEN (op, 0); setno++, i++) | |
446 | { | |
447 | rtx elt = XVECEXP (op, 0, i); | |
448 | regno += regno_dir; | |
449 | ||
450 | if (GET_CODE (elt) != SET | |
991c42ac | 451 | || !REG_P (SET_SRC (elt)) |
d29b4b1b HPN |
452 | || GET_MODE (SET_SRC (elt)) != SImode |
453 | || REGNO (SET_SRC (elt)) != (unsigned int) regno | |
991c42ac | 454 | || !MEM_P (SET_DEST (elt)) |
d29b4b1b HPN |
455 | || GET_MODE (SET_DEST (elt)) != SImode |
456 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
457 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_base) | |
991c42ac | 458 | || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt), 0), 1)) |
d29b4b1b | 459 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != setno * 4 + offset) |
68a81332 | 460 | return false; |
d29b4b1b HPN |
461 | } |
462 | ||
68a81332 | 463 | return true; |
d29b4b1b HPN |
464 | } |
465 | ||
5efd84c5 | 466 | /* The TARGET_CONDITIONAL_REGISTER_USAGE worker. */ |
0b85d816 | 467 | |
5efd84c5 | 468 | static void |
6640377c | 469 | cris_conditional_register_usage (void) |
0b85d816 HPN |
470 | { |
471 | /* FIXME: This isn't nice. We should be able to use that register for | |
472 | something else if the PIC table isn't needed. */ | |
473 | if (flag_pic) | |
474 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] | |
475 | = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; | |
f60c7155 | 476 | |
c31500c2 HPN |
477 | /* Allow use of ACR (PC in pre-V32) and tweak order. */ |
478 | if (TARGET_V32) | |
479 | { | |
480 | static const int reg_alloc_order_v32[] = REG_ALLOC_ORDER_V32; | |
481 | unsigned int i; | |
482 | ||
483 | fixed_regs[CRIS_ACR_REGNUM] = 0; | |
484 | ||
485 | for (i = 0; | |
486 | i < sizeof (reg_alloc_order_v32)/sizeof (reg_alloc_order_v32[0]); | |
487 | i++) | |
488 | reg_alloc_order[i] = reg_alloc_order_v32[i]; | |
489 | } | |
490 | ||
f60c7155 HPN |
491 | if (TARGET_HAS_MUL_INSNS) |
492 | fixed_regs[CRIS_MOF_REGNUM] = 0; | |
f9968e3e HPN |
493 | |
494 | /* On early versions, we must use the 16-bit condition-code register, | |
495 | which has another name. */ | |
496 | if (cris_cpu_version < 8) | |
497 | reg_names[CRIS_CC0_REGNUM] = "ccr"; | |
0b85d816 HPN |
498 | } |
499 | ||
e3b5732b | 500 | /* Return crtl->uses_pic_offset_table. For use in cris.md, |
0b85d816 HPN |
501 | since some generated files do not include function.h. */ |
502 | ||
503 | int | |
6640377c | 504 | cris_cfun_uses_pic_table (void) |
0b85d816 | 505 | { |
e3b5732b | 506 | return crtl->uses_pic_offset_table; |
0b85d816 HPN |
507 | } |
508 | ||
509 | /* Given an rtx, return the text string corresponding to the CODE of X. | |
510 | Intended for use in the assembly language output section of a | |
511 | define_insn. */ | |
512 | ||
513 | const char * | |
6640377c | 514 | cris_op_str (rtx x) |
0b85d816 HPN |
515 | { |
516 | cris_output_insn_is_bound = 0; | |
517 | switch (GET_CODE (x)) | |
518 | { | |
519 | case PLUS: | |
520 | return "add"; | |
521 | break; | |
522 | ||
523 | case MINUS: | |
524 | return "sub"; | |
525 | break; | |
526 | ||
527 | case MULT: | |
86da66b5 HPN |
528 | /* This function is for retrieving a part of an instruction name for |
529 | an operator, for immediate output. If that ever happens for | |
530 | MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure | |
531 | we notice. */ | |
b6c34129 | 532 | internal_error ("MULT case in cris_op_str"); |
0b85d816 HPN |
533 | break; |
534 | ||
535 | case DIV: | |
536 | return "div"; | |
537 | break; | |
538 | ||
539 | case AND: | |
540 | return "and"; | |
541 | break; | |
542 | ||
543 | case IOR: | |
544 | return "or"; | |
545 | break; | |
546 | ||
547 | case XOR: | |
548 | return "xor"; | |
549 | break; | |
550 | ||
551 | case NOT: | |
552 | return "not"; | |
553 | break; | |
554 | ||
555 | case ASHIFT: | |
556 | return "lsl"; | |
557 | break; | |
558 | ||
559 | case LSHIFTRT: | |
560 | return "lsr"; | |
561 | break; | |
562 | ||
563 | case ASHIFTRT: | |
564 | return "asr"; | |
565 | break; | |
566 | ||
567 | case UMIN: | |
9c514326 | 568 | /* Used to control the sign/zero-extend character for the 'E' modifier. |
0b85d816 HPN |
569 | BOUND has none. */ |
570 | cris_output_insn_is_bound = 1; | |
571 | return "bound"; | |
572 | break; | |
573 | ||
574 | default: | |
575 | return "Unknown operator"; | |
576 | break; | |
577 | } | |
578 | } | |
579 | ||
3d556836 HPN |
580 | /* Emit an error message when we're in an asm, and a fatal error for |
581 | "normal" insns. Formatted output isn't easily implemented, since we | |
582 | use output_operand_lossage to output the actual message and handle the | |
583 | categorization of the error. */ | |
584 | ||
585 | static void | |
6640377c | 586 | cris_operand_lossage (const char *msgid, rtx op) |
3d556836 HPN |
587 | { |
588 | debug_rtx (op); | |
a52453cc | 589 | output_operand_lossage ("%s", msgid); |
3d556836 HPN |
590 | } |
591 | ||
0b85d816 HPN |
592 | /* Print an index part of an address to file. */ |
593 | ||
594 | static void | |
6640377c | 595 | cris_print_index (rtx index, FILE *file) |
0b85d816 | 596 | { |
0b85d816 HPN |
597 | /* Make the index "additive" unless we'll output a negative number, in |
598 | which case the sign character is free (as in free beer). */ | |
991c42ac | 599 | if (!CONST_INT_P (index) || INTVAL (index) >= 0) |
0b85d816 HPN |
600 | putc ('+', file); |
601 | ||
602 | if (REG_P (index)) | |
603 | fprintf (file, "$%s.b", reg_names[REGNO (index)]); | |
604 | else if (CONSTANT_P (index)) | |
605 | cris_output_addr_const (file, index); | |
606 | else if (GET_CODE (index) == MULT) | |
607 | { | |
608 | fprintf (file, "$%s.", | |
609 | reg_names[REGNO (XEXP (index, 0))]); | |
610 | ||
611 | putc (INTVAL (XEXP (index, 1)) == 2 ? 'w' : 'd', file); | |
612 | } | |
9e19a50c | 613 | else if (GET_CODE (index) == SIGN_EXTEND && MEM_P (XEXP (index, 0))) |
0b85d816 | 614 | { |
9e19a50c | 615 | rtx inner = XEXP (index, 0); |
0b85d816 HPN |
616 | rtx inner_inner = XEXP (inner, 0); |
617 | ||
618 | if (GET_CODE (inner_inner) == POST_INC) | |
619 | { | |
620 | fprintf (file, "[$%s+].", | |
621 | reg_names[REGNO (XEXP (inner_inner, 0))]); | |
622 | putc (GET_MODE (inner) == HImode ? 'w' : 'b', file); | |
623 | } | |
624 | else | |
625 | { | |
626 | fprintf (file, "[$%s].", reg_names[REGNO (inner_inner)]); | |
627 | ||
628 | putc (GET_MODE (inner) == HImode ? 'w' : 'b', file); | |
629 | } | |
630 | } | |
991c42ac | 631 | else if (MEM_P (index)) |
0b85d816 | 632 | { |
9e19a50c | 633 | rtx inner = XEXP (index, 0); |
0b85d816 HPN |
634 | if (GET_CODE (inner) == POST_INC) |
635 | fprintf (file, "[$%s+].d", reg_names[REGNO (XEXP (inner, 0))]); | |
636 | else | |
637 | fprintf (file, "[$%s].d", reg_names[REGNO (inner)]); | |
638 | } | |
639 | else | |
117b0c0a | 640 | cris_operand_lossage ("unexpected index-type in cris_print_index", |
3d556836 | 641 | index); |
0b85d816 HPN |
642 | } |
643 | ||
644 | /* Print a base rtx of an address to file. */ | |
645 | ||
646 | static void | |
6640377c | 647 | cris_print_base (rtx base, FILE *file) |
0b85d816 HPN |
648 | { |
649 | if (REG_P (base)) | |
650 | fprintf (file, "$%s", reg_names[REGNO (base)]); | |
651 | else if (GET_CODE (base) == POST_INC) | |
c31500c2 HPN |
652 | { |
653 | gcc_assert (REGNO (XEXP (base, 0)) != CRIS_ACR_REGNUM); | |
654 | fprintf (file, "$%s+", reg_names[REGNO (XEXP (base, 0))]); | |
655 | } | |
0b85d816 | 656 | else |
117b0c0a | 657 | cris_operand_lossage ("unexpected base-type in cris_print_base", |
3d556836 | 658 | base); |
0b85d816 HPN |
659 | } |
660 | ||
661 | /* Usable as a guard in expressions. */ | |
662 | ||
663 | int | |
6640377c | 664 | cris_fatal (char *arg) |
0b85d816 HPN |
665 | { |
666 | internal_error (arg); | |
667 | ||
668 | /* We'll never get here; this is just to appease compilers. */ | |
669 | return 0; | |
670 | } | |
671 | ||
04539954 HPN |
672 | /* Return nonzero if REGNO is an ordinary register that *needs* to be |
673 | saved together with other registers, possibly by a MOVEM instruction, | |
674 | or is saved for target-independent reasons. There may be | |
675 | target-dependent reasons to save the register anyway; this is just a | |
676 | wrapper for a complicated conditional. */ | |
677 | ||
678 | static int | |
679 | cris_reg_saved_in_regsave_area (unsigned int regno, bool got_really_used) | |
680 | { | |
681 | return | |
6fb5fa3c | 682 | (((df_regs_ever_live_p (regno) |
04539954 HPN |
683 | && !call_used_regs[regno]) |
684 | || (regno == PIC_OFFSET_TABLE_REGNUM | |
685 | && (got_really_used | |
686 | /* It is saved anyway, if there would be a gap. */ | |
687 | || (flag_pic | |
6fb5fa3c | 688 | && df_regs_ever_live_p (regno + 1) |
04539954 HPN |
689 | && !call_used_regs[regno + 1])))) |
690 | && (regno != FRAME_POINTER_REGNUM || !frame_pointer_needed) | |
691 | && regno != CRIS_SRP_REGNUM) | |
e3b5732b | 692 | || (crtl->calls_eh_return |
04539954 HPN |
693 | && (regno == EH_RETURN_DATA_REGNO (0) |
694 | || regno == EH_RETURN_DATA_REGNO (1) | |
695 | || regno == EH_RETURN_DATA_REGNO (2) | |
696 | || regno == EH_RETURN_DATA_REGNO (3))); | |
697 | } | |
698 | ||
0b85d816 HPN |
699 | /* The PRINT_OPERAND worker. */ |
700 | ||
ed5c4a10 | 701 | static void |
6640377c | 702 | cris_print_operand (FILE *file, rtx x, int code) |
0b85d816 HPN |
703 | { |
704 | rtx operand = x; | |
705 | ||
706 | /* Size-strings corresponding to MULT expressions. */ | |
0139adca | 707 | static const char *const mults[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" }; |
0b85d816 HPN |
708 | |
709 | /* New code entries should just be added to the switch below. If | |
710 | handling is finished, just return. If handling was just a | |
711 | modification of the operand, the modified operand should be put in | |
712 | "operand", and then do a break to let default handling | |
713 | (zero-modifier) output the operand. */ | |
714 | ||
715 | switch (code) | |
716 | { | |
717 | case 'b': | |
59b9a953 | 718 | /* Print the unsigned supplied integer as if it were signed |
0b85d816 | 719 | and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */ |
06cadf63 | 720 | if (!satisfies_constraint_O (x)) |
3d556836 | 721 | LOSE_AND_RETURN ("invalid operand for 'b' modifier", x); |
69487202 KG |
722 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
723 | INTVAL (x)| (INTVAL (x) <= 255 ? ~255 : ~65535)); | |
0b85d816 HPN |
724 | return; |
725 | ||
726 | case 'x': | |
727 | /* Print assembler code for operator. */ | |
728 | fprintf (file, "%s", cris_op_str (operand)); | |
729 | return; | |
730 | ||
04539954 HPN |
731 | case 'o': |
732 | { | |
733 | /* A movem modifier working on a parallel; output the register | |
734 | name. */ | |
735 | int regno; | |
736 | ||
737 | if (GET_CODE (x) != PARALLEL) | |
738 | LOSE_AND_RETURN ("invalid operand for 'o' modifier", x); | |
739 | ||
740 | /* The second item can be (set reg (plus reg const)) to denote a | |
741 | postincrement. */ | |
742 | regno | |
743 | = (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS | |
744 | ? XVECLEN (x, 0) - 2 | |
745 | : XVECLEN (x, 0) - 1); | |
746 | ||
747 | fprintf (file, "$%s", reg_names [regno]); | |
748 | } | |
749 | return; | |
750 | ||
751 | case 'O': | |
752 | { | |
753 | /* A similar movem modifier; output the memory operand. */ | |
754 | rtx addr; | |
755 | ||
756 | if (GET_CODE (x) != PARALLEL) | |
757 | LOSE_AND_RETURN ("invalid operand for 'O' modifier", x); | |
758 | ||
759 | /* The lowest mem operand is in the first item, but perhaps it | |
760 | needs to be output as postincremented. */ | |
991c42ac | 761 | addr = MEM_P (SET_SRC (XVECEXP (x, 0, 0))) |
04539954 HPN |
762 | ? XEXP (SET_SRC (XVECEXP (x, 0, 0)), 0) |
763 | : XEXP (SET_DEST (XVECEXP (x, 0, 0)), 0); | |
764 | ||
d29b4b1b HPN |
765 | /* The second item can be a (set reg (plus reg const)) to denote |
766 | a modification. */ | |
04539954 | 767 | if (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS) |
d29b4b1b HPN |
768 | { |
769 | /* It's a post-increment, if the address is a naked (reg). */ | |
770 | if (REG_P (addr)) | |
771 | addr = gen_rtx_POST_INC (SImode, addr); | |
772 | else | |
773 | { | |
774 | /* Otherwise, it's a side-effect; RN=RN+M. */ | |
775 | fprintf (file, "[$%s=$%s%s%d]", | |
776 | reg_names [REGNO (SET_DEST (XVECEXP (x, 0, 1)))], | |
777 | reg_names [REGNO (XEXP (addr, 0))], | |
778 | INTVAL (XEXP (addr, 1)) < 0 ? "" : "+", | |
779 | (int) INTVAL (XEXP (addr, 1))); | |
780 | return; | |
781 | } | |
782 | } | |
04539954 HPN |
783 | output_address (addr); |
784 | } | |
785 | return; | |
786 | ||
0b85d816 HPN |
787 | case 'p': |
788 | /* Adjust a power of two to its log2. */ | |
991c42ac | 789 | if (!CONST_INT_P (x) || exact_log2 (INTVAL (x)) < 0 ) |
3d556836 | 790 | LOSE_AND_RETURN ("invalid operand for 'p' modifier", x); |
0b85d816 HPN |
791 | fprintf (file, "%d", exact_log2 (INTVAL (x))); |
792 | return; | |
793 | ||
794 | case 's': | |
795 | /* For an integer, print 'b' or 'w' if <= 255 or <= 65535 | |
796 | respectively. This modifier also terminates the inhibiting | |
797 | effects of the 'x' modifier. */ | |
798 | cris_output_insn_is_bound = 0; | |
991c42ac | 799 | if (GET_MODE (x) == VOIDmode && CONST_INT_P (x)) |
0b85d816 HPN |
800 | { |
801 | if (INTVAL (x) >= 0) | |
802 | { | |
803 | if (INTVAL (x) <= 255) | |
804 | putc ('b', file); | |
805 | else if (INTVAL (x) <= 65535) | |
806 | putc ('w', file); | |
807 | else | |
808 | putc ('d', file); | |
809 | } | |
810 | else | |
811 | putc ('d', file); | |
812 | return; | |
813 | } | |
814 | ||
815 | /* For a non-integer, print the size of the operand. */ | |
816 | putc ((GET_MODE (x) == SImode || GET_MODE (x) == SFmode) | |
817 | ? 'd' : GET_MODE (x) == HImode ? 'w' | |
818 | : GET_MODE (x) == QImode ? 'b' | |
819 | /* If none of the above, emit an erroneous size letter. */ | |
820 | : 'X', | |
821 | file); | |
822 | return; | |
823 | ||
824 | case 'z': | |
825 | /* Const_int: print b for -127 <= x <= 255, | |
b6c34129 | 826 | w for -32768 <= x <= 65535, else die. */ |
991c42ac | 827 | if (!CONST_INT_P (x) |
0b85d816 | 828 | || INTVAL (x) < -32768 || INTVAL (x) > 65535) |
3d556836 | 829 | LOSE_AND_RETURN ("invalid operand for 'z' modifier", x); |
0b85d816 HPN |
830 | putc (INTVAL (x) >= -128 && INTVAL (x) <= 255 ? 'b' : 'w', file); |
831 | return; | |
832 | ||
c31500c2 HPN |
833 | case 'Z': |
834 | /* If this is a GOT-symbol, print the size-letter corresponding to | |
835 | -fpic/-fPIC. For everything else, print "d". */ | |
836 | putc ((flag_pic == 1 | |
837 | && GET_CODE (x) == CONST | |
838 | && GET_CODE (XEXP (x, 0)) == UNSPEC | |
839 | && XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREAD) | |
840 | ? 'w' : 'd', file); | |
841 | return; | |
842 | ||
0b85d816 HPN |
843 | case '#': |
844 | /* Output a 'nop' if there's nothing for the delay slot. | |
845 | This method stolen from the sparc files. */ | |
846 | if (dbr_sequence_length () == 0) | |
847 | fputs ("\n\tnop", file); | |
848 | return; | |
849 | ||
86da66b5 HPN |
850 | case '!': |
851 | /* Output directive for alignment padded with "nop" insns. | |
852 | Optimizing for size, it's plain 4-byte alignment, otherwise we | |
853 | align the section to a cache-line (32 bytes) and skip at max 2 | |
854 | bytes, i.e. we skip if it's the last insn on a cache-line. The | |
855 | latter is faster by a small amount (for two test-programs 99.6% | |
856 | and 99.9%) and larger by a small amount (ditto 100.1% and | |
857 | 100.2%). This is supposed to be the simplest yet performance- | |
858 | wise least intrusive way to make sure the immediately following | |
859 | (supposed) muls/mulu insn isn't located at the end of a | |
860 | cache-line. */ | |
861 | if (TARGET_MUL_BUG) | |
862 | fputs (optimize_size | |
863 | ? ".p2alignw 2,0x050f\n\t" | |
864 | : ".p2alignw 5,0x050f,2\n\t", file); | |
865 | return; | |
866 | ||
c00fc5cf HPN |
867 | case ':': |
868 | /* The PIC register. */ | |
869 | if (! flag_pic) | |
870 | internal_error ("invalid use of ':' modifier"); | |
871 | fprintf (file, "$%s", reg_names [PIC_OFFSET_TABLE_REGNUM]); | |
872 | return; | |
873 | ||
0b85d816 HPN |
874 | case 'H': |
875 | /* Print high (most significant) part of something. */ | |
876 | switch (GET_CODE (operand)) | |
877 | { | |
878 | case CONST_INT: | |
2239ced8 HPN |
879 | /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode) |
880 | value is kept here, and so may be other than 0 or -1. */ | |
881 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, | |
882 | INTVAL (operand_subword (operand, 1, 0, DImode))); | |
0b85d816 HPN |
883 | return; |
884 | ||
885 | case CONST_DOUBLE: | |
886 | /* High part of a long long constant. */ | |
887 | if (GET_MODE (operand) == VOIDmode) | |
888 | { | |
69487202 | 889 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_HIGH (x)); |
0b85d816 HPN |
890 | return; |
891 | } | |
892 | else | |
3d556836 | 893 | LOSE_AND_RETURN ("invalid operand for 'H' modifier", x); |
0b85d816 HPN |
894 | |
895 | case REG: | |
896 | /* Print reg + 1. Check that there's not an attempt to print | |
c31500c2 HPN |
897 | high-parts of registers like stack-pointer or higher, except |
898 | for SRP (where the "high part" is MOF). */ | |
899 | if (REGNO (operand) > STACK_POINTER_REGNUM - 2 | |
900 | && (REGNO (operand) != CRIS_SRP_REGNUM | |
901 | || CRIS_SRP_REGNUM + 1 != CRIS_MOF_REGNUM | |
902 | || fixed_regs[CRIS_MOF_REGNUM] != 0)) | |
3d556836 | 903 | LOSE_AND_RETURN ("bad register", operand); |
0b85d816 HPN |
904 | fprintf (file, "$%s", reg_names[REGNO (operand) + 1]); |
905 | return; | |
906 | ||
907 | case MEM: | |
908 | /* Adjust memory address to high part. */ | |
909 | { | |
910 | rtx adj_mem = operand; | |
911 | int size | |
912 | = GET_MODE_BITSIZE (GET_MODE (operand)) / BITS_PER_UNIT; | |
913 | ||
914 | /* Adjust so we can use two SImode in DImode. | |
915 | Calling adj_offsettable_operand will make sure it is an | |
916 | offsettable address. Don't do this for a postincrement | |
917 | though; it should remain as it was. */ | |
918 | if (GET_CODE (XEXP (adj_mem, 0)) != POST_INC) | |
919 | adj_mem | |
920 | = adjust_address (adj_mem, GET_MODE (adj_mem), size / 2); | |
921 | ||
922 | output_address (XEXP (adj_mem, 0)); | |
923 | return; | |
924 | } | |
925 | ||
926 | default: | |
3d556836 | 927 | LOSE_AND_RETURN ("invalid operand for 'H' modifier", x); |
0b85d816 HPN |
928 | } |
929 | ||
930 | case 'L': | |
931 | /* Strip the MEM expression. */ | |
932 | operand = XEXP (operand, 0); | |
933 | break; | |
934 | ||
935 | case 'e': | |
9c514326 | 936 | /* Like 'E', but ignore state set by 'x'. FIXME: Use code |
3abcb3a7 HPN |
937 | iterators and attributes in cris.md to avoid the need for %x |
938 | and %E (and %e) and state passed between those modifiers. */ | |
9c514326 HPN |
939 | cris_output_insn_is_bound = 0; |
940 | /* FALL THROUGH. */ | |
941 | case 'E': | |
0b85d816 HPN |
942 | /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless |
943 | cris_output_insn_is_bound is nonzero. */ | |
944 | if (GET_CODE (operand) != SIGN_EXTEND | |
945 | && GET_CODE (operand) != ZERO_EXTEND | |
991c42ac | 946 | && !CONST_INT_P (operand)) |
3d556836 | 947 | LOSE_AND_RETURN ("invalid operand for 'e' modifier", x); |
0b85d816 HPN |
948 | |
949 | if (cris_output_insn_is_bound) | |
950 | { | |
951 | cris_output_insn_is_bound = 0; | |
952 | return; | |
953 | } | |
954 | ||
955 | putc (GET_CODE (operand) == SIGN_EXTEND | |
991c42ac | 956 | || (CONST_INT_P (operand) && INTVAL (operand) < 0) |
0b85d816 HPN |
957 | ? 's' : 'u', file); |
958 | return; | |
959 | ||
960 | case 'm': | |
961 | /* Print the size letter of the inner element. We can do it by | |
962 | calling ourselves with the 's' modifier. */ | |
963 | if (GET_CODE (operand) != SIGN_EXTEND && GET_CODE (operand) != ZERO_EXTEND) | |
3d556836 | 964 | LOSE_AND_RETURN ("invalid operand for 'm' modifier", x); |
0b85d816 HPN |
965 | cris_print_operand (file, XEXP (operand, 0), 's'); |
966 | return; | |
967 | ||
968 | case 'M': | |
969 | /* Print the least significant part of operand. */ | |
970 | if (GET_CODE (operand) == CONST_DOUBLE) | |
971 | { | |
69487202 | 972 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_LOW (x)); |
0b85d816 HPN |
973 | return; |
974 | } | |
991c42ac | 975 | else if (HOST_BITS_PER_WIDE_INT > 32 && CONST_INT_P (operand)) |
60ffa0e5 | 976 | { |
69487202 | 977 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
4a085d2e | 978 | INTVAL (x) & ((unsigned int) 0x7fffffff * 2 + 1)); |
60ffa0e5 RH |
979 | return; |
980 | } | |
981 | /* Otherwise the least significant part equals the normal part, | |
982 | so handle it normally. */ | |
0b85d816 HPN |
983 | break; |
984 | ||
985 | case 'A': | |
986 | /* When emitting an add for the high part of a DImode constant, we | |
987 | want to use addq for 0 and adds.w for -1. */ | |
991c42ac | 988 | if (!CONST_INT_P (operand)) |
3d556836 | 989 | LOSE_AND_RETURN ("invalid operand for 'A' modifier", x); |
0b85d816 HPN |
990 | fprintf (file, INTVAL (operand) < 0 ? "adds.w" : "addq"); |
991 | return; | |
992 | ||
24ddb79c HPN |
993 | case 'P': |
994 | /* For const_int operands, print the additive mnemonic and the | |
995 | modified operand (byte-sized operands don't save anything): | |
996 | N=MIN_INT..-65536: add.d N | |
997 | -65535..-64: subu.w -N | |
998 | -63..-1: subq -N | |
999 | 0..63: addq N | |
1000 | 64..65535: addu.w N | |
1001 | 65536..MAX_INT: add.d N. | |
1002 | (Emitted mnemonics are capitalized to simplify testing.) | |
1003 | For anything else (N.B: only register is valid), print "add.d". */ | |
1004 | if (REG_P (operand)) | |
1005 | { | |
1006 | fprintf (file, "Add.d "); | |
1007 | ||
1008 | /* Deal with printing the operand by dropping through to the | |
1009 | normal path. */ | |
1010 | break; | |
1011 | } | |
1012 | else | |
1013 | { | |
1014 | int val; | |
1015 | gcc_assert (CONST_INT_P (operand)); | |
1016 | ||
1017 | val = INTVAL (operand); | |
1018 | if (!IN_RANGE (val, -65535, 65535)) | |
1019 | fprintf (file, "Add.d %d", val); | |
1020 | else if (val <= -64) | |
1021 | fprintf (file, "Subu.w %d", -val); | |
1022 | else if (val <= -1) | |
1023 | fprintf (file, "Subq %d", -val); | |
1024 | else if (val <= 63) | |
1025 | fprintf (file, "Addq %d", val); | |
1026 | else if (val <= 65535) | |
1027 | fprintf (file, "Addu.w %d", val); | |
1028 | return; | |
1029 | } | |
1030 | break; | |
1031 | ||
1032 | case 'q': | |
1033 | /* If the operand is an integer -31..31, print "q" else ".d". */ | |
1034 | if (CONST_INT_P (operand) && IN_RANGE (INTVAL (operand), -31, 31)) | |
1035 | fprintf (file, "q"); | |
1036 | else | |
1037 | fprintf (file, ".d"); | |
1038 | return; | |
1039 | ||
f60c7155 | 1040 | case 'd': |
c00fc5cf HPN |
1041 | /* If this is a GOT symbol, force it to be emitted as :GOT and |
1042 | :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16). | |
1043 | Avoid making this too much of a special case. */ | |
1044 | if (flag_pic == 1 && CONSTANT_P (operand)) | |
f60c7155 | 1045 | { |
c00fc5cf HPN |
1046 | int flag_pic_save = flag_pic; |
1047 | ||
1048 | flag_pic = 2; | |
f60c7155 | 1049 | cris_output_addr_const (file, operand); |
c00fc5cf | 1050 | flag_pic = flag_pic_save; |
f60c7155 HPN |
1051 | return; |
1052 | } | |
1053 | break; | |
1054 | ||
0b85d816 HPN |
1055 | case 'D': |
1056 | /* When emitting an sub for the high part of a DImode constant, we | |
1057 | want to use subq for 0 and subs.w for -1. */ | |
991c42ac | 1058 | if (!CONST_INT_P (operand)) |
3d556836 | 1059 | LOSE_AND_RETURN ("invalid operand for 'D' modifier", x); |
0b85d816 HPN |
1060 | fprintf (file, INTVAL (operand) < 0 ? "subs.w" : "subq"); |
1061 | return; | |
1062 | ||
1063 | case 'S': | |
1064 | /* Print the operand as the index-part of an address. | |
1065 | Easiest way out is to use cris_print_index. */ | |
1066 | cris_print_index (operand, file); | |
1067 | return; | |
1068 | ||
1069 | case 'T': | |
1070 | /* Print the size letter for an operand to a MULT, which must be a | |
1071 | const_int with a suitable value. */ | |
991c42ac | 1072 | if (!CONST_INT_P (operand) || INTVAL (operand) > 4) |
3d556836 | 1073 | LOSE_AND_RETURN ("invalid operand for 'T' modifier", x); |
0b85d816 HPN |
1074 | fprintf (file, "%s", mults[INTVAL (operand)]); |
1075 | return; | |
1076 | ||
c31500c2 HPN |
1077 | case 'u': |
1078 | /* Print "u.w" if a GOT symbol and flag_pic == 1, else ".d". */ | |
1079 | if (flag_pic == 1 | |
1080 | && GET_CODE (operand) == CONST | |
1081 | && GET_CODE (XEXP (operand, 0)) == UNSPEC | |
1082 | && XINT (XEXP (operand, 0), 1) == CRIS_UNSPEC_GOTREAD) | |
1083 | fprintf (file, "u.w"); | |
1084 | else | |
1085 | fprintf (file, ".d"); | |
1086 | return; | |
1087 | ||
0b85d816 | 1088 | case 0: |
e5837c07 | 1089 | /* No code, print as usual. */ |
0b85d816 HPN |
1090 | break; |
1091 | ||
1092 | default: | |
3d556836 | 1093 | LOSE_AND_RETURN ("invalid operand modifier letter", x); |
0b85d816 HPN |
1094 | } |
1095 | ||
e5837c07 | 1096 | /* Print an operand as without a modifier letter. */ |
0b85d816 HPN |
1097 | switch (GET_CODE (operand)) |
1098 | { | |
1099 | case REG: | |
f60c7155 HPN |
1100 | if (REGNO (operand) > 15 |
1101 | && REGNO (operand) != CRIS_MOF_REGNUM | |
f9968e3e HPN |
1102 | && REGNO (operand) != CRIS_SRP_REGNUM |
1103 | && REGNO (operand) != CRIS_CC0_REGNUM) | |
c725bd79 | 1104 | internal_error ("internal error: bad register: %d", REGNO (operand)); |
0b85d816 HPN |
1105 | fprintf (file, "$%s", reg_names[REGNO (operand)]); |
1106 | return; | |
1107 | ||
1108 | case MEM: | |
1109 | output_address (XEXP (operand, 0)); | |
1110 | return; | |
1111 | ||
1112 | case CONST_DOUBLE: | |
1113 | if (GET_MODE (operand) == VOIDmode) | |
1114 | /* A long long constant. */ | |
1115 | output_addr_const (file, operand); | |
1116 | else | |
1117 | { | |
1118 | /* Only single precision is allowed as plain operands the | |
1119 | moment. FIXME: REAL_VALUE_FROM_CONST_DOUBLE isn't | |
1120 | documented. */ | |
1121 | REAL_VALUE_TYPE r; | |
1122 | long l; | |
1123 | ||
1124 | /* FIXME: Perhaps check overflow of the "single". */ | |
1125 | REAL_VALUE_FROM_CONST_DOUBLE (r, operand); | |
1126 | REAL_VALUE_TO_TARGET_SINGLE (r, l); | |
1127 | ||
1128 | fprintf (file, "0x%lx", l); | |
1129 | } | |
1130 | return; | |
1131 | ||
1132 | case UNSPEC: | |
0b85d816 | 1133 | /* Fall through. */ |
0b85d816 HPN |
1134 | case CONST: |
1135 | cris_output_addr_const (file, operand); | |
1136 | return; | |
1137 | ||
1138 | case MULT: | |
1139 | case ASHIFT: | |
1140 | { | |
1141 | /* For a (MULT (reg X) const_int) we output "rX.S". */ | |
991c42ac | 1142 | int i = CONST_INT_P (XEXP (operand, 1)) |
0b85d816 | 1143 | ? INTVAL (XEXP (operand, 1)) : INTVAL (XEXP (operand, 0)); |
991c42ac | 1144 | rtx reg = CONST_INT_P (XEXP (operand, 1)) |
0b85d816 HPN |
1145 | ? XEXP (operand, 0) : XEXP (operand, 1); |
1146 | ||
991c42ac JBG |
1147 | if (!REG_P (reg) |
1148 | || (!CONST_INT_P (XEXP (operand, 0)) | |
1149 | && !CONST_INT_P (XEXP (operand, 1)))) | |
3d556836 | 1150 | LOSE_AND_RETURN ("unexpected multiplicative operand", x); |
0b85d816 HPN |
1151 | |
1152 | cris_print_base (reg, file); | |
1153 | fprintf (file, ".%c", | |
1154 | i == 0 || (i == 1 && GET_CODE (operand) == MULT) ? 'b' | |
1155 | : i == 4 ? 'd' | |
1156 | : (i == 2 && GET_CODE (operand) == MULT) || i == 1 ? 'w' | |
1157 | : 'd'); | |
1158 | return; | |
1159 | } | |
1160 | ||
1161 | default: | |
1162 | /* No need to handle all strange variants, let output_addr_const | |
1163 | do it for us. */ | |
1164 | if (CONSTANT_P (operand)) | |
1165 | { | |
1166 | cris_output_addr_const (file, operand); | |
1167 | return; | |
1168 | } | |
1169 | ||
3d556836 | 1170 | LOSE_AND_RETURN ("unexpected operand", x); |
0b85d816 HPN |
1171 | } |
1172 | } | |
1173 | ||
ed5c4a10 NF |
1174 | static bool |
1175 | cris_print_operand_punct_valid_p (unsigned char code) | |
1176 | { | |
1177 | return (code == '#' || code == '!' || code == ':'); | |
1178 | } | |
1179 | ||
0b85d816 HPN |
1180 | /* The PRINT_OPERAND_ADDRESS worker. */ |
1181 | ||
ed5c4a10 | 1182 | static void |
6640377c | 1183 | cris_print_operand_address (FILE *file, rtx x) |
0b85d816 HPN |
1184 | { |
1185 | /* All these were inside MEM:s so output indirection characters. */ | |
1186 | putc ('[', file); | |
1187 | ||
1188 | if (CONSTANT_ADDRESS_P (x)) | |
1189 | cris_output_addr_const (file, x); | |
a08160c3 | 1190 | else if (cris_base_or_autoincr_p (x, true)) |
0b85d816 HPN |
1191 | cris_print_base (x, file); |
1192 | else if (GET_CODE (x) == PLUS) | |
1193 | { | |
1194 | rtx x1, x2; | |
1195 | ||
1196 | x1 = XEXP (x, 0); | |
1197 | x2 = XEXP (x, 1); | |
a08160c3 | 1198 | if (cris_base_p (x1, true)) |
0b85d816 HPN |
1199 | { |
1200 | cris_print_base (x1, file); | |
1201 | cris_print_index (x2, file); | |
1202 | } | |
a08160c3 | 1203 | else if (cris_base_p (x2, true)) |
0b85d816 HPN |
1204 | { |
1205 | cris_print_base (x2, file); | |
1206 | cris_print_index (x1, file); | |
1207 | } | |
1208 | else | |
3d556836 | 1209 | LOSE_AND_RETURN ("unrecognized address", x); |
0b85d816 | 1210 | } |
991c42ac | 1211 | else if (MEM_P (x)) |
0b85d816 HPN |
1212 | { |
1213 | /* A DIP. Output more indirection characters. */ | |
1214 | putc ('[', file); | |
1215 | cris_print_base (XEXP (x, 0), file); | |
1216 | putc (']', file); | |
1217 | } | |
1218 | else | |
3d556836 | 1219 | LOSE_AND_RETURN ("unrecognized address", x); |
0b85d816 HPN |
1220 | |
1221 | putc (']', file); | |
1222 | } | |
1223 | ||
1224 | /* The RETURN_ADDR_RTX worker. | |
1225 | We mark that the return address is used, either by EH or | |
1226 | __builtin_return_address, for use by the function prologue and | |
1227 | epilogue. FIXME: This isn't optimal; we just use the mark in the | |
1228 | prologue and epilogue to say that the return address is to be stored | |
1229 | in the stack frame. We could return SRP for leaf-functions and use the | |
1230 | initial-value machinery. */ | |
1231 | ||
1232 | rtx | |
6640377c | 1233 | cris_return_addr_rtx (int count, rtx frameaddr ATTRIBUTE_UNUSED) |
0b85d816 HPN |
1234 | { |
1235 | cfun->machine->needs_return_address_on_stack = 1; | |
1236 | ||
1237 | /* The return-address is stored just above the saved frame-pointer (if | |
1238 | present). Apparently we can't eliminate from the frame-pointer in | |
1239 | that direction, so use the incoming args (maybe pretended) pointer. */ | |
1240 | return count == 0 | |
0a81f074 | 1241 | ? gen_rtx_MEM (Pmode, plus_constant (Pmode, virtual_incoming_args_rtx, -4)) |
0b85d816 HPN |
1242 | : NULL_RTX; |
1243 | } | |
1244 | ||
b2416742 HPN |
1245 | /* Accessor used in cris.md:return because cfun->machine isn't available |
1246 | there. */ | |
1247 | ||
04539954 | 1248 | bool |
d29b4b1b | 1249 | cris_return_address_on_stack (void) |
b2416742 | 1250 | { |
6fb5fa3c | 1251 | return df_regs_ever_live_p (CRIS_SRP_REGNUM) |
04539954 HPN |
1252 | || cfun->machine->needs_return_address_on_stack; |
1253 | } | |
1254 | ||
1255 | /* Accessor used in cris.md:return because cfun->machine isn't available | |
1256 | there. */ | |
1257 | ||
1258 | bool | |
d29b4b1b | 1259 | cris_return_address_on_stack_for_return (void) |
04539954 HPN |
1260 | { |
1261 | return cfun->machine->return_type == CRIS_RETINSN_RET ? false | |
1262 | : cris_return_address_on_stack (); | |
b2416742 HPN |
1263 | } |
1264 | ||
0b85d816 HPN |
1265 | /* This used to be the INITIAL_FRAME_POINTER_OFFSET worker; now only |
1266 | handles FP -> SP elimination offset. */ | |
1267 | ||
1268 | static int | |
6640377c | 1269 | cris_initial_frame_pointer_offset (void) |
0b85d816 HPN |
1270 | { |
1271 | int regno; | |
1272 | ||
f710504c | 1273 | /* Initial offset is 0 if we don't have a frame pointer. */ |
0b85d816 | 1274 | int offs = 0; |
c00fc5cf HPN |
1275 | bool got_really_used = false; |
1276 | ||
e3b5732b | 1277 | if (crtl->uses_pic_offset_table) |
c00fc5cf HPN |
1278 | { |
1279 | push_topmost_sequence (); | |
1280 | got_really_used | |
1281 | = reg_used_between_p (pic_offset_table_rtx, get_insns (), | |
1282 | NULL_RTX); | |
1283 | pop_topmost_sequence (); | |
1284 | } | |
0b85d816 HPN |
1285 | |
1286 | /* And 4 for each register pushed. */ | |
1287 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
04539954 | 1288 | if (cris_reg_saved_in_regsave_area (regno, got_really_used)) |
0b85d816 HPN |
1289 | offs += 4; |
1290 | ||
1291 | /* And then, last, we add the locals allocated. */ | |
1292 | offs += get_frame_size (); | |
1293 | ||
1294 | /* And more; the accumulated args size. */ | |
38173d38 | 1295 | offs += crtl->outgoing_args_size; |
0b85d816 HPN |
1296 | |
1297 | /* Then round it off, in case we use aligned stack. */ | |
1298 | if (TARGET_STACK_ALIGN) | |
1299 | offs = TARGET_ALIGN_BY_32 ? (offs + 3) & ~3 : (offs + 1) & ~1; | |
1300 | ||
1301 | return offs; | |
1302 | } | |
1303 | ||
1304 | /* The INITIAL_ELIMINATION_OFFSET worker. | |
1305 | Calculate the difference between imaginary registers such as frame | |
1306 | pointer and the stack pointer. Used to eliminate the frame pointer | |
1307 | and imaginary arg pointer. */ | |
1308 | ||
1309 | int | |
6640377c | 1310 | cris_initial_elimination_offset (int fromreg, int toreg) |
0b85d816 HPN |
1311 | { |
1312 | int fp_sp_offset | |
1313 | = cris_initial_frame_pointer_offset (); | |
1314 | ||
1315 | /* We should be able to use regs_ever_live and related prologue | |
1316 | information here, or alpha should not as well. */ | |
04539954 | 1317 | bool return_address_on_stack = cris_return_address_on_stack (); |
0b85d816 | 1318 | |
59b9a953 | 1319 | /* Here we act as if the frame-pointer were needed. */ |
0b85d816 HPN |
1320 | int ap_fp_offset = 4 + (return_address_on_stack ? 4 : 0); |
1321 | ||
1322 | if (fromreg == ARG_POINTER_REGNUM | |
1323 | && toreg == FRAME_POINTER_REGNUM) | |
1324 | return ap_fp_offset; | |
1325 | ||
1326 | /* Between the frame pointer and the stack are only "normal" stack | |
1327 | variables and saved registers. */ | |
1328 | if (fromreg == FRAME_POINTER_REGNUM | |
1329 | && toreg == STACK_POINTER_REGNUM) | |
1330 | return fp_sp_offset; | |
1331 | ||
e5837c07 | 1332 | /* We need to balance out the frame pointer here. */ |
0b85d816 HPN |
1333 | if (fromreg == ARG_POINTER_REGNUM |
1334 | && toreg == STACK_POINTER_REGNUM) | |
1335 | return ap_fp_offset + fp_sp_offset - 4; | |
1336 | ||
b6c34129 | 1337 | gcc_unreachable (); |
0b85d816 HPN |
1338 | } |
1339 | ||
a08160c3 AS |
1340 | /* Nonzero if X is a hard reg that can be used as an index. */ |
1341 | static inline bool | |
1342 | reg_ok_for_base_p (const_rtx x, bool strict) | |
1343 | { | |
1344 | return ((! strict && ! HARD_REGISTER_P (x)) | |
1345 | || REGNO_OK_FOR_BASE_P (REGNO (x))); | |
1346 | } | |
1347 | ||
1348 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
1349 | static inline bool | |
1350 | reg_ok_for_index_p (const_rtx x, bool strict) | |
1351 | { | |
1352 | return reg_ok_for_base_p (x, strict); | |
1353 | } | |
1354 | ||
1355 | /* No symbol can be used as an index (or more correct, as a base) together | |
1356 | with a register with PIC; the PIC register must be there. */ | |
1357 | ||
1358 | bool | |
1359 | cris_constant_index_p (const_rtx x) | |
1360 | { | |
1361 | return (CONSTANT_P (x) && (!flag_pic || cris_valid_pic_const (x, true))); | |
1362 | } | |
1363 | ||
1364 | /* True if X is a valid base register. */ | |
1365 | ||
1366 | bool | |
1367 | cris_base_p (const_rtx x, bool strict) | |
1368 | { | |
1369 | return (REG_P (x) && reg_ok_for_base_p (x, strict)); | |
1370 | } | |
1371 | ||
1372 | /* True if X is a valid index register. */ | |
1373 | ||
1374 | static inline bool | |
1375 | cris_index_p (const_rtx x, bool strict) | |
1376 | { | |
1377 | return (REG_P (x) && reg_ok_for_index_p (x, strict)); | |
1378 | } | |
1379 | ||
1380 | /* True if X is a valid base register with or without autoincrement. */ | |
1381 | ||
1382 | bool | |
1383 | cris_base_or_autoincr_p (const_rtx x, bool strict) | |
1384 | { | |
1385 | return (cris_base_p (x, strict) | |
1386 | || (GET_CODE (x) == POST_INC | |
1387 | && cris_base_p (XEXP (x, 0), strict) | |
1388 | && REGNO (XEXP (x, 0)) != CRIS_ACR_REGNUM)); | |
1389 | } | |
1390 | ||
1391 | /* True if X is a valid (register) index for BDAP, i.e. [Rs].S or [Rs+].S. */ | |
1392 | ||
1393 | bool | |
1394 | cris_bdap_index_p (const_rtx x, bool strict) | |
1395 | { | |
1396 | return ((MEM_P (x) | |
1397 | && GET_MODE (x) == SImode | |
1398 | && cris_base_or_autoincr_p (XEXP (x, 0), strict)) | |
1399 | || (GET_CODE (x) == SIGN_EXTEND | |
1400 | && MEM_P (XEXP (x, 0)) | |
1401 | && (GET_MODE (XEXP (x, 0)) == HImode | |
1402 | || GET_MODE (XEXP (x, 0)) == QImode) | |
1403 | && cris_base_or_autoincr_p (XEXP (XEXP (x, 0), 0), strict))); | |
1404 | } | |
1405 | ||
1406 | /* True if X is a valid (register) index for BIAP, i.e. Rd.m. */ | |
1407 | ||
1408 | bool | |
1409 | cris_biap_index_p (const_rtx x, bool strict) | |
1410 | { | |
1411 | return (cris_index_p (x, strict) | |
1412 | || (GET_CODE (x) == MULT | |
1413 | && cris_index_p (XEXP (x, 0), strict) | |
1414 | && cris_scale_int_operand (XEXP (x, 1), VOIDmode))); | |
1415 | } | |
1416 | ||
1417 | /* Worker function for TARGET_LEGITIMATE_ADDRESS_P. | |
1418 | ||
1419 | A PIC operand looks like a normal symbol here. At output we dress it | |
1420 | in "[rPIC+symbol:GOT]" (global symbol) or "rPIC+symbol:GOTOFF" (local | |
1421 | symbol) so we exclude all addressing modes where we can't replace a | |
1422 | plain "symbol" with that. A global PIC symbol does not fit anywhere | |
1423 | here (but is thankfully a general_operand in itself). A local PIC | |
1424 | symbol is valid for the plain "symbol + offset" case. */ | |
1425 | ||
a502bdb6 | 1426 | bool |
a08160c3 AS |
1427 | cris_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) |
1428 | { | |
1429 | const_rtx x1, x2; | |
1430 | ||
1431 | if (cris_base_or_autoincr_p (x, strict)) | |
1432 | return true; | |
1433 | else if (TARGET_V32) | |
1434 | /* Nothing else is valid then. */ | |
1435 | return false; | |
1436 | else if (cris_constant_index_p (x)) | |
1437 | return true; | |
1438 | /* Indexed? */ | |
1439 | else if (GET_CODE (x) == PLUS) | |
1440 | { | |
1441 | x1 = XEXP (x, 0); | |
1442 | x2 = XEXP (x, 1); | |
1443 | /* BDAP o, Rd. */ | |
1444 | if ((cris_base_p (x1, strict) && cris_constant_index_p (x2)) | |
1445 | || (cris_base_p (x2, strict) && cris_constant_index_p (x1)) | |
1446 | /* BDAP Rs[+], Rd. */ | |
1447 | || (GET_MODE_SIZE (mode) <= UNITS_PER_WORD | |
1448 | && ((cris_base_p (x1, strict) | |
1449 | && cris_bdap_index_p (x2, strict)) | |
1450 | || (cris_base_p (x2, strict) | |
1451 | && cris_bdap_index_p (x1, strict)) | |
1452 | /* BIAP.m Rs, Rd */ | |
1453 | || (cris_base_p (x1, strict) | |
1454 | && cris_biap_index_p (x2, strict)) | |
1455 | || (cris_base_p (x2, strict) | |
1456 | && cris_biap_index_p (x1, strict))))) | |
1457 | return true; | |
1458 | } | |
1459 | else if (MEM_P (x)) | |
1460 | { | |
1461 | /* DIP (Rs). Reject [[reg+]] and [[reg]] for DImode (long long). */ | |
1462 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD | |
1463 | && cris_base_or_autoincr_p (XEXP (x, 0), strict)) | |
1464 | return true; | |
1465 | } | |
1466 | ||
1467 | return false; | |
1468 | } | |
1469 | ||
15883505 HPN |
1470 | /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */ |
1471 | ||
1472 | bool | |
1473 | cris_reload_address_legitimized (rtx x, | |
1474 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
1475 | int opnum ATTRIBUTE_UNUSED, | |
1476 | int itype, | |
1477 | int ind_levels ATTRIBUTE_UNUSED) | |
1478 | { | |
973c3795 | 1479 | enum reload_type type = (enum reload_type) itype; |
15883505 | 1480 | rtx op0, op1; |
15883505 HPN |
1481 | rtx *op1p; |
1482 | ||
1483 | if (GET_CODE (x) != PLUS) | |
1484 | return false; | |
1485 | ||
c31500c2 HPN |
1486 | if (TARGET_V32) |
1487 | return false; | |
1488 | ||
15883505 | 1489 | op0 = XEXP (x, 0); |
15883505 HPN |
1490 | op1 = XEXP (x, 1); |
1491 | op1p = &XEXP (x, 1); | |
1492 | ||
1493 | if (!REG_P (op1)) | |
1494 | return false; | |
1495 | ||
991c42ac | 1496 | if (GET_CODE (op0) == SIGN_EXTEND && MEM_P (XEXP (op0, 0))) |
15883505 HPN |
1497 | { |
1498 | rtx op00 = XEXP (op0, 0); | |
1499 | rtx op000 = XEXP (op00, 0); | |
1500 | rtx *op000p = &XEXP (op00, 0); | |
1501 | ||
1502 | if ((GET_MODE (op00) == HImode || GET_MODE (op00) == QImode) | |
1503 | && (REG_P (op000) | |
1504 | || (GET_CODE (op000) == POST_INC && REG_P (XEXP (op000, 0))))) | |
1505 | { | |
1506 | bool something_reloaded = false; | |
1507 | ||
1508 | if (GET_CODE (op000) == POST_INC | |
1509 | && REG_P (XEXP (op000, 0)) | |
1510 | && REGNO (XEXP (op000, 0)) > CRIS_LAST_GENERAL_REGISTER) | |
1511 | /* No, this gets too complicated and is too rare to care | |
1512 | about trying to improve on the general code Here. | |
1513 | As the return-value is an all-or-nothing indicator, we | |
1514 | punt on the other register too. */ | |
1515 | return false; | |
1516 | ||
1517 | if ((REG_P (op000) | |
1518 | && REGNO (op000) > CRIS_LAST_GENERAL_REGISTER)) | |
1519 | { | |
1520 | /* The address of the inner mem is a pseudo or wrong | |
1521 | reg: reload that. */ | |
1522 | push_reload (op000, NULL_RTX, op000p, NULL, GENERAL_REGS, | |
1523 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); | |
1524 | something_reloaded = true; | |
1525 | } | |
1526 | ||
1527 | if (REGNO (op1) > CRIS_LAST_GENERAL_REGISTER) | |
1528 | { | |
1529 | /* Base register is a pseudo or wrong reg: reload it. */ | |
1530 | push_reload (op1, NULL_RTX, op1p, NULL, GENERAL_REGS, | |
1531 | GET_MODE (x), VOIDmode, 0, 0, | |
1532 | opnum, type); | |
1533 | something_reloaded = true; | |
1534 | } | |
1535 | ||
1536 | gcc_assert (something_reloaded); | |
1537 | ||
1538 | return true; | |
1539 | } | |
1540 | } | |
1541 | ||
1542 | return false; | |
1543 | } | |
1544 | ||
45dbdfd4 AS |
1545 | |
1546 | /* Worker function for TARGET_PREFERRED_RELOAD_CLASS. | |
1547 | ||
1548 | It seems like gcc (2.7.2 and 2.9x of 2000-03-22) may send "NO_REGS" as | |
1549 | the class for a constant (testcase: __Mul in arit.c). To avoid forcing | |
1550 | out a constant into the constant pool, we will trap this case and | |
1551 | return something a bit more sane. FIXME: Check if this is a bug. | |
1552 | Beware that we must not "override" classes that can be specified as | |
1553 | constraint letters, or else asm operands using them will fail when | |
1554 | they need to be reloaded. FIXME: Investigate whether that constitutes | |
1555 | a bug. */ | |
1556 | ||
1557 | static reg_class_t | |
1558 | cris_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass) | |
1559 | { | |
1560 | if (rclass != ACR_REGS | |
1561 | && rclass != MOF_REGS | |
ff57d866 | 1562 | && rclass != MOF_SRP_REGS |
45dbdfd4 AS |
1563 | && rclass != SRP_REGS |
1564 | && rclass != CC0_REGS | |
1565 | && rclass != SPECIAL_REGS) | |
1566 | return GENERAL_REGS; | |
1567 | ||
1568 | return rclass; | |
1569 | } | |
1570 | ||
b95491a0 | 1571 | /* Worker function for TARGET_REGISTER_MOVE_COST. */ |
0b85d816 | 1572 | |
b95491a0 | 1573 | static int |
c31500c2 | 1574 | cris_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, |
b95491a0 | 1575 | reg_class_t from, reg_class_t to) |
0b85d816 | 1576 | { |
c31500c2 HPN |
1577 | /* Can't move to and from a SPECIAL_REGS register, so we have to say |
1578 | their move cost within that class is higher. How about 7? That's 3 | |
1579 | for a move to a GENERAL_REGS register, 3 for the move from the | |
1580 | GENERAL_REGS register, and 1 for the increased register pressure. | |
2ea91d6b | 1581 | Also, it's higher than the memory move cost, as it should. |
c31500c2 HPN |
1582 | We also do this for ALL_REGS, since we don't want that class to be |
1583 | preferred (even to memory) at all where GENERAL_REGS doesn't fit. | |
1584 | Whenever it's about to be used, it's for SPECIAL_REGS. If we don't | |
1585 | present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be | |
1586 | used when a GENERAL_REGS should be used, even if there are call-saved | |
1587 | GENERAL_REGS left to allocate. This is because the fall-back when | |
1588 | the most preferred register class isn't available, isn't the next | |
1589 | (or next good) wider register class, but the *most widest* register | |
2ea91d6b | 1590 | class. FIXME: pre-IRA comment, perhaps obsolete now. */ |
c31500c2 HPN |
1591 | |
1592 | if ((reg_classes_intersect_p (from, SPECIAL_REGS) | |
1593 | && reg_classes_intersect_p (to, SPECIAL_REGS)) | |
1594 | || from == ALL_REGS || to == ALL_REGS) | |
1595 | return 7; | |
1596 | ||
2ea91d6b HPN |
1597 | /* Make moves to/from SPECIAL_REGS slightly more expensive, as we |
1598 | generally prefer GENERAL_REGS. */ | |
c31500c2 HPN |
1599 | if (reg_classes_intersect_p (from, SPECIAL_REGS) |
1600 | || reg_classes_intersect_p (to, SPECIAL_REGS)) | |
1601 | return 3; | |
1602 | ||
1603 | return 2; | |
1604 | } | |
0b85d816 | 1605 | |
b95491a0 AS |
1606 | /* Worker function for TARGET_MEMORY_MOVE_COST. |
1607 | ||
1608 | This isn't strictly correct for v0..3 in buswidth-8bit mode, but should | |
1609 | suffice. */ | |
1610 | ||
1611 | static int | |
1612 | cris_memory_move_cost (enum machine_mode mode, | |
1613 | reg_class_t rclass ATTRIBUTE_UNUSED, | |
1614 | bool in ATTRIBUTE_UNUSED) | |
1615 | { | |
1616 | if (mode == QImode | |
1617 | || mode == HImode) | |
1618 | return 4; | |
1619 | else | |
1620 | return 6; | |
1621 | } | |
1622 | ||
c31500c2 HPN |
1623 | /* Worker for cris_notice_update_cc; handles the "normal" cases. |
1624 | FIXME: this code is historical; its functionality should be | |
1625 | refactored to look at insn attributes and moved to | |
1626 | cris_notice_update_cc. Except, we better lose cc0 entirely. */ | |
0b85d816 | 1627 | |
c31500c2 HPN |
1628 | static void |
1629 | cris_normal_notice_update_cc (rtx exp, rtx insn) | |
1630 | { | |
1631 | /* "Normal" means, for: | |
1632 | (set (cc0) (...)): | |
1633 | CC is (...). | |
0b85d816 | 1634 | |
c31500c2 HPN |
1635 | (set (reg) (...)): |
1636 | CC is (reg) and (...) - unless (...) is 0 or reg is a special | |
1637 | register or (v32 and (...) is -32..-1), then CC does not change. | |
1638 | CC_NO_OVERFLOW unless (...) is reg or mem. | |
0b85d816 | 1639 | |
c31500c2 HPN |
1640 | (set (mem) (...)): |
1641 | CC does not change. | |
0b85d816 | 1642 | |
c31500c2 HPN |
1643 | (set (pc) (...)): |
1644 | CC does not change. | |
0b85d816 | 1645 | |
c31500c2 HPN |
1646 | (parallel |
1647 | (set (reg1) (mem (bdap/biap))) | |
1648 | (set (reg2) (bdap/biap))): | |
1649 | CC is (reg1) and (mem (reg2)) | |
0b85d816 | 1650 | |
c31500c2 HPN |
1651 | (parallel |
1652 | (set (mem (bdap/biap)) (reg1)) [or 0] | |
1653 | (set (reg2) (bdap/biap))): | |
1654 | CC does not change. | |
0b85d816 | 1655 | |
c31500c2 | 1656 | (where reg and mem includes strict_low_parts variants thereof) |
0b85d816 | 1657 | |
c31500c2 HPN |
1658 | For all others, assume CC is clobbered. |
1659 | Note that we do not have to care about setting CC_NO_OVERFLOW, | |
1660 | since the overflow flag is set to 0 (i.e. right) for | |
1661 | instructions where it does not have any sane sense, but where | |
1662 | other flags have meanings. (This includes shifts; the carry is | |
1663 | not set by them). | |
0b85d816 | 1664 | |
c31500c2 HPN |
1665 | Note that there are other parallel constructs we could match, |
1666 | but we don't do that yet. */ | |
0b85d816 | 1667 | |
c31500c2 HPN |
1668 | if (GET_CODE (exp) == SET) |
1669 | { | |
1670 | /* FIXME: Check when this happens. It looks like we should | |
1671 | actually do a CC_STATUS_INIT here to be safe. */ | |
1672 | if (SET_DEST (exp) == pc_rtx) | |
1673 | return; | |
0b85d816 | 1674 | |
c31500c2 HPN |
1675 | /* Record CC0 changes, so we do not have to output multiple |
1676 | test insns. */ | |
1677 | if (SET_DEST (exp) == cc0_rtx) | |
0b85d816 | 1678 | { |
c31500c2 | 1679 | CC_STATUS_INIT; |
0b85d816 | 1680 | |
f90b7a5a PB |
1681 | if (GET_CODE (SET_SRC (exp)) == COMPARE |
1682 | && XEXP (SET_SRC (exp), 1) == const0_rtx) | |
1683 | cc_status.value1 = XEXP (SET_SRC (exp), 0); | |
1684 | else | |
1685 | cc_status.value1 = SET_SRC (exp); | |
1686 | ||
1687 | /* Handle flags for the special btstq on one bit. */ | |
1688 | if (GET_CODE (cc_status.value1) == ZERO_EXTRACT | |
1689 | && XEXP (cc_status.value1, 1) == const1_rtx) | |
0b85d816 | 1690 | { |
f90b7a5a | 1691 | if (CONST_INT_P (XEXP (cc_status.value1, 0))) |
c31500c2 HPN |
1692 | /* Using cmpq. */ |
1693 | cc_status.flags = CC_INVERTED; | |
0b85d816 | 1694 | else |
c31500c2 HPN |
1695 | /* A one-bit btstq. */ |
1696 | cc_status.flags = CC_Z_IN_NOT_N; | |
0b85d816 | 1697 | } |
0b85d816 | 1698 | |
f90b7a5a | 1699 | else if (GET_CODE (SET_SRC (exp)) == COMPARE) |
c31500c2 HPN |
1700 | { |
1701 | if (!REG_P (XEXP (SET_SRC (exp), 0)) | |
1702 | && XEXP (SET_SRC (exp), 1) != const0_rtx) | |
1703 | /* For some reason gcc will not canonicalize compare | |
1704 | operations, reversing the sign by itself if | |
1705 | operands are in wrong order. */ | |
1706 | /* (But NOT inverted; eq is still eq.) */ | |
1707 | cc_status.flags = CC_REVERSED; | |
1708 | ||
1709 | /* This seems to be overlooked by gcc. FIXME: Check again. | |
1710 | FIXME: Is it really safe? */ | |
1711 | cc_status.value2 | |
1712 | = gen_rtx_MINUS (GET_MODE (SET_SRC (exp)), | |
1713 | XEXP (SET_SRC (exp), 0), | |
1714 | XEXP (SET_SRC (exp), 1)); | |
1715 | } | |
1716 | return; | |
1717 | } | |
1718 | else if (REG_P (SET_DEST (exp)) | |
1719 | || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART | |
1720 | && REG_P (XEXP (SET_DEST (exp), 0)))) | |
1721 | { | |
1722 | /* A register is set; normally CC is set to show that no | |
1723 | test insn is needed. Catch the exceptions. */ | |
0b85d816 | 1724 | |
c31500c2 HPN |
1725 | /* If not to cc0, then no "set"s in non-natural mode give |
1726 | ok cc0... */ | |
1727 | if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp))) > UNITS_PER_WORD | |
1728 | || GET_MODE_CLASS (GET_MODE (SET_DEST (exp))) == MODE_FLOAT) | |
1729 | { | |
1730 | /* ... except add:s and sub:s in DImode. */ | |
1731 | if (GET_MODE (SET_DEST (exp)) == DImode | |
1732 | && (GET_CODE (SET_SRC (exp)) == PLUS | |
1733 | || GET_CODE (SET_SRC (exp)) == MINUS)) | |
0b85d816 | 1734 | { |
c31500c2 | 1735 | CC_STATUS_INIT; |
0b85d816 HPN |
1736 | cc_status.value1 = SET_DEST (exp); |
1737 | cc_status.value2 = SET_SRC (exp); | |
1738 | ||
1739 | if (cris_reg_overlap_mentioned_p (cc_status.value1, | |
1740 | cc_status.value2)) | |
1741 | cc_status.value2 = 0; | |
1742 | ||
c31500c2 | 1743 | /* Add and sub may set V, which gets us |
0b85d816 HPN |
1744 | unoptimizable results in "gt" and "le" condition |
1745 | codes. */ | |
c31500c2 | 1746 | cc_status.flags |= CC_NO_OVERFLOW; |
0b85d816 HPN |
1747 | |
1748 | return; | |
1749 | } | |
1750 | } | |
c31500c2 HPN |
1751 | else if (SET_SRC (exp) == const0_rtx |
1752 | || (REG_P (SET_SRC (exp)) | |
1753 | && (REGNO (SET_SRC (exp)) | |
1754 | > CRIS_LAST_GENERAL_REGISTER)) | |
1755 | || (TARGET_V32 | |
b3374f14 | 1756 | && REG_P (SET_DEST (exp)) |
06cadf63 | 1757 | && satisfies_constraint_I (SET_SRC (exp)))) |
0b85d816 | 1758 | { |
c31500c2 HPN |
1759 | /* There's no CC0 change for this case. Just check |
1760 | for overlap. */ | |
f4ddaddd HPN |
1761 | if (cc_status.value1 |
1762 | && modified_in_p (cc_status.value1, insn)) | |
0b85d816 HPN |
1763 | cc_status.value1 = 0; |
1764 | ||
f4ddaddd HPN |
1765 | if (cc_status.value2 |
1766 | && modified_in_p (cc_status.value2, insn)) | |
0b85d816 HPN |
1767 | cc_status.value2 = 0; |
1768 | ||
1769 | return; | |
1770 | } | |
c31500c2 HPN |
1771 | else |
1772 | { | |
1773 | CC_STATUS_INIT; | |
1774 | cc_status.value1 = SET_DEST (exp); | |
1775 | cc_status.value2 = SET_SRC (exp); | |
1776 | ||
1777 | if (cris_reg_overlap_mentioned_p (cc_status.value1, | |
1778 | cc_status.value2)) | |
1779 | cc_status.value2 = 0; | |
1780 | ||
1781 | /* Some operations may set V, which gets us | |
1782 | unoptimizable results in "gt" and "le" condition | |
1783 | codes. */ | |
1784 | if (GET_CODE (SET_SRC (exp)) == PLUS | |
1785 | || GET_CODE (SET_SRC (exp)) == MINUS | |
1786 | || GET_CODE (SET_SRC (exp)) == NEG) | |
1787 | cc_status.flags |= CC_NO_OVERFLOW; | |
1788 | ||
1789 | /* For V32, nothing with a register destination sets | |
1790 | C and V usefully. */ | |
1791 | if (TARGET_V32) | |
1792 | cc_status.flags |= CC_NO_OVERFLOW; | |
1793 | ||
1794 | return; | |
1795 | } | |
1796 | } | |
1797 | else if (MEM_P (SET_DEST (exp)) | |
1798 | || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART | |
1799 | && MEM_P (XEXP (SET_DEST (exp), 0)))) | |
1800 | { | |
1801 | /* When SET to MEM, then CC is not changed (except for | |
1802 | overlap). */ | |
1803 | if (cc_status.value1 | |
1804 | && modified_in_p (cc_status.value1, insn)) | |
1805 | cc_status.value1 = 0; | |
1806 | ||
1807 | if (cc_status.value2 | |
1808 | && modified_in_p (cc_status.value2, insn)) | |
1809 | cc_status.value2 = 0; | |
1810 | ||
1811 | return; | |
0b85d816 | 1812 | } |
c31500c2 HPN |
1813 | } |
1814 | else if (GET_CODE (exp) == PARALLEL) | |
1815 | { | |
1816 | if (GET_CODE (XVECEXP (exp, 0, 0)) == SET | |
1817 | && GET_CODE (XVECEXP (exp, 0, 1)) == SET | |
1818 | && REG_P (XEXP (XVECEXP (exp, 0, 1), 0))) | |
0b85d816 | 1819 | { |
c31500c2 HPN |
1820 | if (REG_P (XEXP (XVECEXP (exp, 0, 0), 0)) |
1821 | && MEM_P (XEXP (XVECEXP (exp, 0, 0), 1))) | |
0b85d816 | 1822 | { |
c31500c2 HPN |
1823 | CC_STATUS_INIT; |
1824 | ||
1825 | /* For "move.S [rx=ry+o],rz", say CC reflects | |
1826 | value1=rz and value2=[rx] */ | |
1827 | cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0); | |
1828 | cc_status.value2 | |
1829 | = replace_equiv_address (XEXP (XVECEXP (exp, 0, 0), 1), | |
1830 | XEXP (XVECEXP (exp, 0, 1), 0)); | |
1831 | ||
1832 | /* Huh? A side-effect cannot change the destination | |
1833 | register. */ | |
1834 | if (cris_reg_overlap_mentioned_p (cc_status.value1, | |
1835 | cc_status.value2)) | |
1836 | internal_error ("internal error: sideeffect-insn affecting main effect"); | |
1837 | ||
1838 | /* For V32, moves to registers don't set C and V. */ | |
1839 | if (TARGET_V32) | |
1840 | cc_status.flags |= CC_NO_OVERFLOW; | |
1841 | return; | |
1842 | } | |
1843 | else if ((REG_P (XEXP (XVECEXP (exp, 0, 0), 1)) | |
1844 | || XEXP (XVECEXP (exp, 0, 0), 1) == const0_rtx) | |
1845 | && MEM_P (XEXP (XVECEXP (exp, 0, 0), 0))) | |
1846 | { | |
1847 | /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]", | |
1848 | say flags are not changed, except for overlap. */ | |
1849 | if (cc_status.value1 | |
1850 | && modified_in_p (cc_status.value1, insn)) | |
1851 | cc_status.value1 = 0; | |
d3295e25 | 1852 | |
c31500c2 HPN |
1853 | if (cc_status.value2 |
1854 | && modified_in_p (cc_status.value2, insn)) | |
1855 | cc_status.value2 = 0; | |
1856 | ||
1857 | return; | |
0b85d816 HPN |
1858 | } |
1859 | } | |
c31500c2 HPN |
1860 | } |
1861 | ||
1862 | /* If we got here, the case wasn't covered by the code above. */ | |
1863 | CC_STATUS_INIT; | |
1864 | } | |
1865 | ||
1866 | /* This function looks into the pattern to see how this insn affects | |
1867 | condition codes. | |
1868 | ||
1869 | Used when to eliminate test insns before a condition-code user, | |
1870 | such as a "scc" insn or a conditional branch. This includes | |
1871 | checking if the entities that cc was updated by, are changed by the | |
1872 | operation. | |
1873 | ||
1874 | Currently a jumble of the old peek-inside-the-insn and the newer | |
1875 | check-cc-attribute methods. */ | |
1876 | ||
1877 | void | |
1878 | cris_notice_update_cc (rtx exp, rtx insn) | |
1879 | { | |
1880 | enum attr_cc attrval = get_attr_cc (insn); | |
1881 | ||
1882 | /* Check if user specified "-mcc-init" as a bug-workaround. Remember | |
1883 | to still set CC_REVERSED as below, since that's required by some | |
1884 | compare insn alternatives. (FIXME: GCC should do this virtual | |
1885 | operand swap by itself.) A test-case that may otherwise fail is | |
1886 | gcc.c-torture/execute/20000217-1.c -O0 and -O1. */ | |
1887 | if (TARGET_CCINIT) | |
1888 | { | |
1889 | CC_STATUS_INIT; | |
1890 | ||
1891 | if (attrval == CC_REV) | |
1892 | cc_status.flags = CC_REVERSED; | |
1893 | return; | |
1894 | } | |
1895 | ||
1896 | /* Slowly, we're converting to using attributes to control the setting | |
1897 | of condition-code status. */ | |
1898 | switch (attrval) | |
1899 | { | |
1900 | case CC_NONE: | |
1901 | /* Even if it is "none", a setting may clobber a previous | |
1902 | cc-value, so check. */ | |
1903 | if (GET_CODE (exp) == SET) | |
1904 | { | |
1905 | if (cc_status.value1 | |
1906 | && modified_in_p (cc_status.value1, insn)) | |
1907 | cc_status.value1 = 0; | |
1908 | ||
1909 | if (cc_status.value2 | |
1910 | && modified_in_p (cc_status.value2, insn)) | |
1911 | cc_status.value2 = 0; | |
1912 | } | |
1913 | return; | |
1914 | ||
1915 | case CC_CLOBBER: | |
1916 | CC_STATUS_INIT; | |
1917 | return; | |
1918 | ||
1919 | case CC_REV: | |
1920 | case CC_NOOV32: | |
1921 | case CC_NORMAL: | |
1922 | cris_normal_notice_update_cc (exp, insn); | |
1923 | ||
1924 | /* The "test" insn doesn't clear (carry and) overflow on V32. We | |
1925 | can change bge => bpl and blt => bmi by passing on to the cc0 | |
1926 | user that V should not be considered; bgt and ble are taken | |
1927 | care of by other methods (see {tst,cmp}{si,hi,qi}). */ | |
1928 | if (attrval == CC_NOOV32 && TARGET_V32) | |
1929 | cc_status.flags |= CC_NO_OVERFLOW; | |
1930 | return; | |
0b85d816 HPN |
1931 | |
1932 | default: | |
ab532386 | 1933 | internal_error ("unknown cc_attr value"); |
0b85d816 HPN |
1934 | } |
1935 | ||
1936 | CC_STATUS_INIT; | |
1937 | } | |
1938 | ||
1939 | /* Return != 0 if the return sequence for the current function is short, | |
04539954 HPN |
1940 | like "ret" or "jump [sp+]". Prior to reloading, we can't tell if |
1941 | registers must be saved, so return 0 then. */ | |
0b85d816 | 1942 | |
04539954 | 1943 | bool |
6640377c | 1944 | cris_simple_epilogue (void) |
0b85d816 | 1945 | { |
04539954 HPN |
1946 | unsigned int regno; |
1947 | unsigned int reglimit = STACK_POINTER_REGNUM; | |
c00fc5cf | 1948 | bool got_really_used = false; |
0b85d816 HPN |
1949 | |
1950 | if (! reload_completed | |
1951 | || frame_pointer_needed | |
1952 | || get_frame_size () != 0 | |
38173d38 JH |
1953 | || crtl->args.pretend_args_size |
1954 | || crtl->args.size | |
1955 | || crtl->outgoing_args_size | |
e3b5732b | 1956 | || crtl->calls_eh_return |
0b85d816 HPN |
1957 | |
1958 | /* If we're not supposed to emit prologue and epilogue, we must | |
1959 | not emit return-type instructions. */ | |
1960 | || !TARGET_PROLOGUE_EPILOGUE) | |
04539954 | 1961 | return false; |
0b85d816 | 1962 | |
c31500c2 HPN |
1963 | /* Can't return from stacked return address with v32. */ |
1964 | if (TARGET_V32 && cris_return_address_on_stack ()) | |
1965 | return false; | |
1966 | ||
e3b5732b | 1967 | if (crtl->uses_pic_offset_table) |
c00fc5cf HPN |
1968 | { |
1969 | push_topmost_sequence (); | |
1970 | got_really_used | |
1971 | = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX); | |
1972 | pop_topmost_sequence (); | |
1973 | } | |
1974 | ||
04539954 | 1975 | /* No simple epilogue if there are saved registers. */ |
0b85d816 | 1976 | for (regno = 0; regno < reglimit; regno++) |
04539954 HPN |
1977 | if (cris_reg_saved_in_regsave_area (regno, got_really_used)) |
1978 | return false; | |
0b85d816 | 1979 | |
04539954 HPN |
1980 | return true; |
1981 | } | |
1982 | ||
21ed4444 HPN |
1983 | /* Emit checking that MEM is aligned for an access in MODE, failing |
1984 | that, executing a "break 8" (or call to abort, if "break 8" is | |
1985 | disabled). */ | |
1986 | ||
1987 | void | |
1988 | cris_emit_trap_for_misalignment (rtx mem) | |
1989 | { | |
2f352e3d | 1990 | rtx addr, reg, ok_label, andop, jmp; |
21ed4444 HPN |
1991 | int natural_alignment; |
1992 | gcc_assert (MEM_P (mem)); | |
1993 | ||
1994 | natural_alignment = GET_MODE_SIZE (GET_MODE (mem)); | |
1995 | addr = XEXP (mem, 0); | |
1996 | reg = force_reg (Pmode, addr); | |
1997 | ok_label = gen_label_rtx (); | |
1998 | ||
1999 | /* This will yield a btstq without a separate register used, usually - | |
2000 | with the exception for PRE hoisting the "and" but not the branch | |
f02827cd | 2001 | around the trap: see testsuite/gcc.target/cris/sync-3s.c. */ |
2f352e3d HPN |
2002 | andop = gen_rtx_AND (Pmode, reg, GEN_INT (natural_alignment - 1)); |
2003 | emit_cmp_and_jump_insns (force_reg (SImode, andop), const0_rtx, EQ, | |
21ed4444 HPN |
2004 | NULL_RTX, Pmode, 1, ok_label); |
2005 | jmp = get_last_insn (); | |
2006 | gcc_assert (JUMP_P (jmp)); | |
2007 | ||
f02827cd | 2008 | predict_insn_def (jmp, PRED_NORETURN, TAKEN); |
21ed4444 HPN |
2009 | expand_builtin_trap (); |
2010 | emit_label (ok_label); | |
2011 | } | |
2012 | ||
04539954 HPN |
2013 | /* Expand a return insn (just one insn) marked as using SRP or stack |
2014 | slot depending on parameter ON_STACK. */ | |
2015 | ||
2016 | void | |
2017 | cris_expand_return (bool on_stack) | |
2018 | { | |
2019 | /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to | |
2020 | tell "ret" from "jump [sp+]". Some, but not all, other parts of | |
2021 | GCC expect just (return) to do the right thing when optimizing, so | |
2022 | we do that until they're fixed. Currently, all return insns in a | |
2023 | function must be the same (not really a limiting factor) so we need | |
2024 | to check that it doesn't change half-way through. */ | |
3810076b | 2025 | emit_jump_insn (ret_rtx); |
04539954 | 2026 | |
b6c34129 HPN |
2027 | CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_RET || !on_stack); |
2028 | CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_JUMP || on_stack); | |
04539954 HPN |
2029 | |
2030 | cfun->machine->return_type | |
2031 | = on_stack ? CRIS_RETINSN_JUMP : CRIS_RETINSN_RET; | |
0b85d816 HPN |
2032 | } |
2033 | ||
3c50106f RH |
2034 | /* Compute a (partial) cost for rtx X. Return true if the complete |
2035 | cost has been computed, and false if subexpressions should be | |
2036 | scanned. In either case, *TOTAL contains the cost result. */ | |
2037 | ||
2038 | static bool | |
68f932c4 | 2039 | cris_rtx_costs (rtx x, int code, int outer_code, int opno, int *total, |
f40751dd | 2040 | bool speed) |
3c50106f RH |
2041 | { |
2042 | switch (code) | |
2043 | { | |
2044 | case CONST_INT: | |
2045 | { | |
2046 | HOST_WIDE_INT val = INTVAL (x); | |
2047 | if (val == 0) | |
2048 | *total = 0; | |
2049 | else if (val < 32 && val >= -32) | |
2050 | *total = 1; | |
2051 | /* Eight or 16 bits are a word and cycle more expensive. */ | |
2052 | else if (val <= 32767 && val >= -32768) | |
2053 | *total = 2; | |
a7b376ee | 2054 | /* A 32-bit constant (or very seldom, unsigned 16 bits) costs |
3c50106f RH |
2055 | another word. FIXME: This isn't linear to 16 bits. */ |
2056 | else | |
2057 | *total = 4; | |
2058 | return true; | |
2059 | } | |
2060 | ||
2061 | case LABEL_REF: | |
2062 | *total = 6; | |
2063 | return true; | |
2064 | ||
2065 | case CONST: | |
2066 | case SYMBOL_REF: | |
c00fc5cf | 2067 | *total = 6; |
3c50106f RH |
2068 | return true; |
2069 | ||
2070 | case CONST_DOUBLE: | |
2071 | if (x != CONST0_RTX (GET_MODE (x) == VOIDmode ? DImode : GET_MODE (x))) | |
2072 | *total = 12; | |
2073 | else | |
2074 | /* Make 0.0 cheap, else test-insns will not be used. */ | |
2075 | *total = 0; | |
2076 | return true; | |
2077 | ||
2078 | case MULT: | |
aa05ad86 HPN |
2079 | /* If we have one arm of an ADDI, make sure it gets the cost of |
2080 | one insn, i.e. zero cost for this operand, and just the cost | |
2081 | of the PLUS, as the insn is created by combine from a PLUS | |
2082 | and an ASHIFT, and the MULT cost below would make the | |
2083 | combined value be larger than the separate insns. The insn | |
2084 | validity is checked elsewhere by combine. | |
2085 | ||
2086 | FIXME: this case is a stop-gap for 4.3 and 4.4, this whole | |
2087 | function should be rewritten. */ | |
a08160c3 | 2088 | if (outer_code == PLUS && cris_biap_index_p (x, false)) |
aa05ad86 HPN |
2089 | { |
2090 | *total = 0; | |
2091 | return true; | |
2092 | } | |
2093 | ||
3c50106f RH |
2094 | /* Identify values that are no powers of two. Powers of 2 are |
2095 | taken care of already and those values should not be changed. */ | |
991c42ac | 2096 | if (!CONST_INT_P (XEXP (x, 1)) |
3c50106f RH |
2097 | || exact_log2 (INTVAL (XEXP (x, 1)) < 0)) |
2098 | { | |
2099 | /* If we have a multiply insn, then the cost is between | |
2100 | 1 and 2 "fast" instructions. */ | |
2101 | if (TARGET_HAS_MUL_INSNS) | |
2102 | { | |
2103 | *total = COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2; | |
2104 | return true; | |
2105 | } | |
2106 | ||
2107 | /* Estimate as 4 + 4 * #ofbits. */ | |
2108 | *total = COSTS_N_INSNS (132); | |
2109 | return true; | |
2110 | } | |
2111 | return false; | |
2112 | ||
2113 | case UDIV: | |
2114 | case MOD: | |
2115 | case UMOD: | |
2116 | case DIV: | |
991c42ac | 2117 | if (!CONST_INT_P (XEXP (x, 1)) |
5b296d93 | 2118 | || exact_log2 (INTVAL (XEXP (x, 1)) < 0)) |
3c50106f RH |
2119 | { |
2120 | /* Estimate this as 4 + 8 * #of bits. */ | |
2121 | *total = COSTS_N_INSNS (260); | |
2122 | return true; | |
2123 | } | |
2124 | return false; | |
2125 | ||
2126 | case AND: | |
991c42ac | 2127 | if (CONST_INT_P (XEXP (x, 1)) |
3c50106f | 2128 | /* Two constants may actually happen before optimization. */ |
991c42ac | 2129 | && !CONST_INT_P (XEXP (x, 0)) |
06cadf63 | 2130 | && !satisfies_constraint_I (XEXP (x, 1))) |
3c50106f | 2131 | { |
973c3795 | 2132 | *total |
68f932c4 RS |
2133 | = (rtx_cost (XEXP (x, 0), (enum rtx_code) outer_code, |
2134 | opno, speed) + 2 | |
973c3795 | 2135 | + 2 * GET_MODE_NUNITS (GET_MODE (XEXP (x, 0)))); |
3c50106f RH |
2136 | return true; |
2137 | } | |
2138 | return false; | |
2139 | ||
f90b7a5a PB |
2140 | case ZERO_EXTRACT: |
2141 | if (outer_code != COMPARE) | |
2142 | return false; | |
2143 | /* fall through */ | |
2144 | ||
3c50106f | 2145 | case ZERO_EXTEND: case SIGN_EXTEND: |
68f932c4 | 2146 | *total = rtx_cost (XEXP (x, 0), (enum rtx_code) outer_code, opno, speed); |
3c50106f RH |
2147 | return true; |
2148 | ||
2149 | default: | |
2150 | return false; | |
2151 | } | |
2152 | } | |
2153 | ||
0b85d816 HPN |
2154 | /* The ADDRESS_COST worker. */ |
2155 | ||
75642f32 | 2156 | static int |
b413068c OE |
2157 | cris_address_cost (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED, |
2158 | addr_space_t as ATTRIBUTE_UNUSED, | |
2159 | bool speed ATTRIBUTE_UNUSED) | |
0b85d816 HPN |
2160 | { |
2161 | /* The metric to use for the cost-macros is unclear. | |
2162 | The metric used here is (the number of cycles needed) / 2, | |
2163 | where we consider equal a cycle for a word of code and a cycle to | |
a3ef2349 HPN |
2164 | read memory. FIXME: Adding "+ 1" to all values would avoid |
2165 | returning 0, as tree-ssa-loop-ivopts.c as of r128272 "normalizes" | |
2166 | 0 to 1, thereby giving equal costs to [rN + rM] and [rN]. | |
2167 | Unfortunately(?) such a hack would expose other pessimizations, | |
2168 | at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the | |
2169 | loop there, without apparent reason. */ | |
0b85d816 HPN |
2170 | |
2171 | /* The cheapest addressing modes get 0, since nothing extra is needed. */ | |
a08160c3 | 2172 | if (cris_base_or_autoincr_p (x, false)) |
0b85d816 HPN |
2173 | return 0; |
2174 | ||
2175 | /* An indirect mem must be a DIP. This means two bytes extra for code, | |
2176 | and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */ | |
991c42ac | 2177 | if (MEM_P (x)) |
0b85d816 HPN |
2178 | return (2 + 4) / 2; |
2179 | ||
2180 | /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs | |
c00fc5cf | 2181 | an extra DIP prefix and 4 bytes of constant in most cases. */ |
0b85d816 | 2182 | if (CONSTANT_P (x)) |
c00fc5cf | 2183 | return (2 + 4) / 2; |
0b85d816 HPN |
2184 | |
2185 | /* Handle BIAP and BDAP prefixes. */ | |
2186 | if (GET_CODE (x) == PLUS) | |
2187 | { | |
2188 | rtx tem1 = XEXP (x, 0); | |
2189 | rtx tem2 = XEXP (x, 1); | |
2190 | ||
582be0a1 HPN |
2191 | /* Local extended canonicalization rule: the first operand must |
2192 | be REG, unless it's an operation (MULT). */ | |
2193 | if (!REG_P (tem1) && GET_CODE (tem1) != MULT) | |
2194 | tem1 = tem2, tem2 = XEXP (x, 0); | |
2195 | ||
2196 | /* We'll "assume" we have canonical RTX now. */ | |
a3ef2349 | 2197 | gcc_assert (REG_P (tem1) || GET_CODE (tem1) == MULT); |
0b85d816 | 2198 | |
a3ef2349 HPN |
2199 | /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We |
2200 | recognize the typical MULT which is always in tem1 because of | |
2201 | insn canonicalization. */ | |
a08160c3 | 2202 | if ((GET_CODE (tem1) == MULT && cris_biap_index_p (tem1, false)) |
a3ef2349 HPN |
2203 | || REG_P (tem2)) |
2204 | return 2 / 2; | |
2205 | ||
2206 | /* A BDAP (quick) is 2 extra bytes. Any constant operand to the | |
2207 | PLUS is always found in tem2. */ | |
2208 | if (CONST_INT_P (tem2) && INTVAL (tem2) < 128 && INTVAL (tem2) >= -128) | |
2209 | return 2 / 2; | |
2210 | ||
2211 | /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra | |
2212 | bytes. */ | |
06cadf63 | 2213 | if (satisfies_constraint_L (tem2)) |
a3ef2349 HPN |
2214 | return (2 + 2) / 2; |
2215 | ||
2216 | /* A BDAP with some other constant is 2 bytes extra. */ | |
2217 | if (CONSTANT_P (tem2)) | |
2218 | return (2 + 2 + 2) / 2; | |
2219 | ||
2220 | /* BDAP with something indirect should have a higher cost than | |
2221 | BIAP with register. FIXME: Should it cost like a MEM or more? */ | |
2222 | return (2 + 2 + 2) / 2; | |
2223 | } | |
0b85d816 HPN |
2224 | |
2225 | /* What else? Return a high cost. It matters only for valid | |
2226 | addressing modes. */ | |
2227 | return 10; | |
2228 | } | |
2229 | ||
2230 | /* Check various objections to the side-effect. Used in the test-part | |
2231 | of an anonymous insn describing an insn with a possible side-effect. | |
2232 | Returns nonzero if the implied side-effect is ok. | |
2233 | ||
2234 | code : PLUS or MULT | |
2235 | ops : An array of rtx:es. lreg, rreg, rval, | |
2236 | The variables multop and other_op are indexes into this, | |
2237 | or -1 if they are not applicable. | |
2238 | lreg : The register that gets assigned in the side-effect. | |
2239 | rreg : One register in the side-effect expression | |
2240 | rval : The other register, or an int. | |
2241 | multop : An integer to multiply rval with. | |
2242 | other_op : One of the entities of the main effect, | |
2243 | whose mode we must consider. */ | |
2244 | ||
2245 | int | |
6640377c SB |
2246 | cris_side_effect_mode_ok (enum rtx_code code, rtx *ops, |
2247 | int lreg, int rreg, int rval, | |
2248 | int multop, int other_op) | |
0b85d816 HPN |
2249 | { |
2250 | /* Find what value to multiply with, for rx =ry + rz * n. */ | |
2251 | int mult = multop < 0 ? 1 : INTVAL (ops[multop]); | |
2252 | ||
2253 | rtx reg_rtx = ops[rreg]; | |
2254 | rtx val_rtx = ops[rval]; | |
2255 | ||
2256 | /* The operands may be swapped. Canonicalize them in reg_rtx and | |
2257 | val_rtx, where reg_rtx always is a reg (for this constraint to | |
2258 | match). */ | |
a08160c3 | 2259 | if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed)) |
0b85d816 HPN |
2260 | reg_rtx = val_rtx, val_rtx = ops[rreg]; |
2261 | ||
2262 | /* Don't forget to check that reg_rtx really is a reg. If it isn't, | |
2263 | we have no business. */ | |
a08160c3 | 2264 | if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed)) |
0b85d816 HPN |
2265 | return 0; |
2266 | ||
2267 | /* Don't do this when -mno-split. */ | |
2268 | if (!TARGET_SIDE_EFFECT_PREFIXES) | |
2269 | return 0; | |
2270 | ||
2271 | /* The mult expression may be hidden in lreg. FIXME: Add more | |
2272 | commentary about that. */ | |
2273 | if (GET_CODE (val_rtx) == MULT) | |
2274 | { | |
2275 | mult = INTVAL (XEXP (val_rtx, 1)); | |
2276 | val_rtx = XEXP (val_rtx, 0); | |
2277 | code = MULT; | |
2278 | } | |
2279 | ||
2280 | /* First check the "other operand". */ | |
2281 | if (other_op >= 0) | |
2282 | { | |
2283 | if (GET_MODE_SIZE (GET_MODE (ops[other_op])) > UNITS_PER_WORD) | |
2284 | return 0; | |
2285 | ||
2286 | /* Check if the lvalue register is the same as the "other | |
2287 | operand". If so, the result is undefined and we shouldn't do | |
2288 | this. FIXME: Check again. */ | |
a08160c3 AS |
2289 | if ((cris_base_p (ops[lreg], reload_in_progress || reload_completed) |
2290 | && cris_base_p (ops[other_op], | |
2291 | reload_in_progress || reload_completed) | |
0b85d816 HPN |
2292 | && REGNO (ops[lreg]) == REGNO (ops[other_op])) |
2293 | || rtx_equal_p (ops[other_op], ops[lreg])) | |
2294 | return 0; | |
2295 | } | |
2296 | ||
2297 | /* Do not accept frame_pointer_rtx as any operand. */ | |
2298 | if (ops[lreg] == frame_pointer_rtx || ops[rreg] == frame_pointer_rtx | |
2299 | || ops[rval] == frame_pointer_rtx | |
2300 | || (other_op >= 0 && ops[other_op] == frame_pointer_rtx)) | |
2301 | return 0; | |
2302 | ||
2303 | if (code == PLUS | |
a08160c3 | 2304 | && ! cris_base_p (val_rtx, reload_in_progress || reload_completed)) |
0b85d816 HPN |
2305 | { |
2306 | ||
2307 | /* Do not allow rx = rx + n if a normal add or sub with same size | |
2308 | would do. */ | |
2309 | if (rtx_equal_p (ops[lreg], reg_rtx) | |
991c42ac | 2310 | && CONST_INT_P (val_rtx) |
0b85d816 HPN |
2311 | && (INTVAL (val_rtx) <= 63 && INTVAL (val_rtx) >= -63)) |
2312 | return 0; | |
2313 | ||
c00fc5cf | 2314 | /* Check allowed cases, like [r(+)?].[bwd] and const. */ |
0b85d816 | 2315 | if (CONSTANT_P (val_rtx)) |
c00fc5cf | 2316 | return 1; |
0b85d816 | 2317 | |
a08160c3 AS |
2318 | if (MEM_P (val_rtx) |
2319 | && cris_base_or_autoincr_p (XEXP (val_rtx, 0), | |
2320 | reload_in_progress || reload_completed)) | |
0b85d816 HPN |
2321 | return 1; |
2322 | ||
2323 | if (GET_CODE (val_rtx) == SIGN_EXTEND | |
991c42ac | 2324 | && MEM_P (XEXP (val_rtx, 0)) |
a08160c3 AS |
2325 | && cris_base_or_autoincr_p (XEXP (XEXP (val_rtx, 0), 0), |
2326 | reload_in_progress || reload_completed)) | |
0b85d816 HPN |
2327 | return 1; |
2328 | ||
2329 | /* If we got here, it's not a valid addressing mode. */ | |
2330 | return 0; | |
2331 | } | |
2332 | else if (code == MULT | |
a08160c3 AS |
2333 | || (code == PLUS |
2334 | && cris_base_p (val_rtx, | |
2335 | reload_in_progress || reload_completed))) | |
0b85d816 HPN |
2336 | { |
2337 | /* Do not allow rx = rx + ry.S, since it doesn't give better code. */ | |
2338 | if (rtx_equal_p (ops[lreg], reg_rtx) | |
2339 | || (mult == 1 && rtx_equal_p (ops[lreg], val_rtx))) | |
2340 | return 0; | |
2341 | ||
2342 | /* Do not allow bad multiply-values. */ | |
2343 | if (mult != 1 && mult != 2 && mult != 4) | |
2344 | return 0; | |
2345 | ||
2346 | /* Only allow r + ... */ | |
a08160c3 | 2347 | if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed)) |
0b85d816 HPN |
2348 | return 0; |
2349 | ||
2350 | /* If we got here, all seems ok. | |
2351 | (All checks need to be done above). */ | |
2352 | return 1; | |
2353 | } | |
2354 | ||
2355 | /* If we get here, the caller got its initial tests wrong. */ | |
c725bd79 | 2356 | internal_error ("internal error: cris_side_effect_mode_ok with bad operands"); |
0b85d816 HPN |
2357 | } |
2358 | ||
c31500c2 HPN |
2359 | /* Whether next_cc0_user of insn is LE or GT or requires a real compare |
2360 | insn for other reasons. */ | |
2361 | ||
2362 | bool | |
2363 | cris_cc0_user_requires_cmp (rtx insn) | |
2364 | { | |
2365 | rtx cc0_user = NULL; | |
2366 | rtx body; | |
2367 | rtx set; | |
2368 | ||
2369 | gcc_assert (insn != NULL); | |
2370 | ||
2371 | if (!TARGET_V32) | |
2372 | return false; | |
2373 | ||
2374 | cc0_user = next_cc0_user (insn); | |
2375 | if (cc0_user == NULL) | |
2376 | return false; | |
2377 | ||
2378 | body = PATTERN (cc0_user); | |
2379 | set = single_set (cc0_user); | |
2380 | ||
2381 | /* Users can be sCC and bCC. */ | |
2382 | if (JUMP_P (cc0_user) | |
2383 | && GET_CODE (body) == SET | |
2384 | && SET_DEST (body) == pc_rtx | |
2385 | && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE | |
2386 | && XEXP (XEXP (SET_SRC (body), 0), 0) == cc0_rtx) | |
2387 | { | |
2388 | return | |
2389 | GET_CODE (XEXP (SET_SRC (body), 0)) == GT | |
2390 | || GET_CODE (XEXP (SET_SRC (body), 0)) == LE; | |
2391 | } | |
2392 | else if (set) | |
2393 | { | |
2394 | return | |
2395 | GET_CODE (SET_SRC (body)) == GT | |
2396 | || GET_CODE (SET_SRC (body)) == LE; | |
2397 | } | |
2398 | ||
2399 | gcc_unreachable (); | |
2400 | } | |
2401 | ||
0b85d816 HPN |
2402 | /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16) |
2403 | does not handle the case where the IN operand is strict_low_part; it | |
2404 | does handle it for X. Test-case in Axis-20010516. This function takes | |
2405 | care of that for THIS port. FIXME: strict_low_part is going away | |
2406 | anyway. */ | |
2407 | ||
2408 | static int | |
6640377c | 2409 | cris_reg_overlap_mentioned_p (rtx x, rtx in) |
0b85d816 HPN |
2410 | { |
2411 | /* The function reg_overlap_mentioned now handles when X is | |
2412 | strict_low_part, but not when IN is a STRICT_LOW_PART. */ | |
2413 | if (GET_CODE (in) == STRICT_LOW_PART) | |
2414 | in = XEXP (in, 0); | |
2415 | ||
2416 | return reg_overlap_mentioned_p (x, in); | |
2417 | } | |
2418 | ||
c31500c2 HPN |
2419 | /* Return TRUE iff X is a CONST valid for e.g. indexing. |
2420 | ANY_OPERAND is 0 if X is in a CALL_P insn or movsi, 1 | |
2421 | elsewhere. */ | |
0b85d816 | 2422 | |
c00fc5cf | 2423 | bool |
a08160c3 | 2424 | cris_valid_pic_const (const_rtx x, bool any_operand) |
0b85d816 | 2425 | { |
c00fc5cf | 2426 | gcc_assert (flag_pic); |
0b85d816 | 2427 | |
0b85d816 HPN |
2428 | switch (GET_CODE (x)) |
2429 | { | |
0b85d816 HPN |
2430 | case CONST_INT: |
2431 | case CONST_DOUBLE: | |
c00fc5cf | 2432 | return true; |
0b85d816 | 2433 | default: |
c00fc5cf | 2434 | ; |
0b85d816 HPN |
2435 | } |
2436 | ||
c00fc5cf HPN |
2437 | if (GET_CODE (x) != CONST) |
2438 | return false; | |
2439 | ||
2440 | x = XEXP (x, 0); | |
2441 | ||
2442 | /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */ | |
2443 | if (GET_CODE (x) == PLUS | |
2444 | && GET_CODE (XEXP (x, 0)) == UNSPEC | |
c31500c2 HPN |
2445 | && (XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREL |
2446 | || XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_PCREL) | |
991c42ac | 2447 | && CONST_INT_P (XEXP (x, 1))) |
c00fc5cf HPN |
2448 | x = XEXP (x, 0); |
2449 | ||
2450 | if (GET_CODE (x) == UNSPEC) | |
2451 | switch (XINT (x, 1)) | |
2452 | { | |
c31500c2 HPN |
2453 | /* A PCREL operand is only valid for call and movsi. */ |
2454 | case CRIS_UNSPEC_PLT_PCREL: | |
2455 | case CRIS_UNSPEC_PCREL: | |
2456 | return !any_operand; | |
2457 | ||
2458 | case CRIS_UNSPEC_PLT_GOTREL: | |
c00fc5cf HPN |
2459 | case CRIS_UNSPEC_PLTGOTREAD: |
2460 | case CRIS_UNSPEC_GOTREAD: | |
2461 | case CRIS_UNSPEC_GOTREL: | |
2462 | return true; | |
2463 | default: | |
2464 | gcc_unreachable (); | |
2465 | } | |
2466 | ||
2467 | return cris_pic_symbol_type_of (x) == cris_no_symbol; | |
0b85d816 HPN |
2468 | } |
2469 | ||
c00fc5cf HPN |
2470 | /* Helper function to find the right PIC-type symbol to generate, |
2471 | given the original (non-PIC) representation. */ | |
0b85d816 | 2472 | |
c00fc5cf | 2473 | enum cris_pic_symbol_type |
a08160c3 | 2474 | cris_pic_symbol_type_of (const_rtx x) |
0b85d816 HPN |
2475 | { |
2476 | switch (GET_CODE (x)) | |
2477 | { | |
0b85d816 | 2478 | case SYMBOL_REF: |
c00fc5cf | 2479 | return SYMBOL_REF_LOCAL_P (x) |
c31500c2 | 2480 | ? cris_rel_symbol : cris_got_symbol; |
0b85d816 HPN |
2481 | |
2482 | case LABEL_REF: | |
c31500c2 | 2483 | return cris_rel_symbol; |
0b85d816 HPN |
2484 | |
2485 | case CONST: | |
c00fc5cf | 2486 | return cris_pic_symbol_type_of (XEXP (x, 0)); |
0b85d816 HPN |
2487 | |
2488 | case PLUS: | |
2489 | case MINUS: | |
2490 | { | |
c00fc5cf HPN |
2491 | enum cris_pic_symbol_type t1 = cris_pic_symbol_type_of (XEXP (x, 0)); |
2492 | enum cris_pic_symbol_type t2 = cris_pic_symbol_type_of (XEXP (x, 1)); | |
2493 | ||
2494 | gcc_assert (t1 == cris_no_symbol || t2 == cris_no_symbol); | |
2495 | ||
c09c8f70 | 2496 | if (t1 == cris_got_symbol || t2 == cris_got_symbol) |
c00fc5cf HPN |
2497 | return cris_got_symbol_needing_fixup; |
2498 | ||
2499 | return t1 != cris_no_symbol ? t1 : t2; | |
0b85d816 HPN |
2500 | } |
2501 | ||
2502 | case CONST_INT: | |
2503 | case CONST_DOUBLE: | |
c00fc5cf HPN |
2504 | return cris_no_symbol; |
2505 | ||
2506 | case UNSPEC: | |
2507 | /* Likely an offsettability-test attempting to add a constant to | |
2508 | a GOTREAD symbol, which can't be handled. */ | |
2509 | return cris_invalid_pic_symbol; | |
0b85d816 HPN |
2510 | |
2511 | default: | |
c725bd79 | 2512 | fatal_insn ("unrecognized supposed constant", x); |
0b85d816 HPN |
2513 | } |
2514 | ||
c00fc5cf | 2515 | gcc_unreachable (); |
0b85d816 HPN |
2516 | } |
2517 | ||
c00fc5cf | 2518 | /* The LEGITIMATE_PIC_OPERAND_P worker. */ |
0b85d816 HPN |
2519 | |
2520 | int | |
c00fc5cf | 2521 | cris_legitimate_pic_operand (rtx x) |
0b85d816 | 2522 | { |
c00fc5cf | 2523 | /* Symbols are not valid PIC operands as-is; just constants. */ |
c31500c2 HPN |
2524 | return cris_valid_pic_const (x, true); |
2525 | } | |
2526 | ||
a8781821 SB |
2527 | /* Queue an .ident string in the queue of top-level asm statements. |
2528 | If the front-end is done, we must be being called from toplev.c. | |
2529 | In that case, do nothing. */ | |
2530 | void | |
2531 | cris_asm_output_ident (const char *string) | |
2532 | { | |
a8781821 SB |
2533 | if (cgraph_state != CGRAPH_STATE_PARSING) |
2534 | return; | |
2535 | ||
2536 | default_asm_output_ident_directive (string); | |
2537 | } | |
2538 | ||
c31500c2 HPN |
2539 | /* The ASM_OUTPUT_CASE_END worker. */ |
2540 | ||
2541 | void | |
2542 | cris_asm_output_case_end (FILE *stream, int num, rtx table) | |
2543 | { | |
a50023f9 HPN |
2544 | /* Step back, over the label for the table, to the actual casejump and |
2545 | assert that we find only what's expected. */ | |
2546 | rtx whole_jump_insn = prev_nonnote_nondebug_insn (table); | |
2547 | gcc_assert (whole_jump_insn != NULL_RTX && LABEL_P (whole_jump_insn)); | |
2548 | whole_jump_insn = prev_nonnote_nondebug_insn (whole_jump_insn); | |
2549 | gcc_assert (whole_jump_insn != NULL_RTX | |
2550 | && (JUMP_P (whole_jump_insn) | |
2551 | || (TARGET_V32 && INSN_P (whole_jump_insn) | |
2552 | && GET_CODE (PATTERN (whole_jump_insn)) == SEQUENCE))); | |
2553 | /* Get the pattern of the casejump, so we can extract the default label. */ | |
2554 | whole_jump_insn = PATTERN (whole_jump_insn); | |
2555 | ||
c31500c2 HPN |
2556 | if (TARGET_V32) |
2557 | { | |
c31500c2 | 2558 | /* This can be a SEQUENCE, meaning the delay-slot of the jump is |
a50023f9 | 2559 | filled. We also output the offset word a little differently. */ |
c31500c2 HPN |
2560 | rtx parallel_jump |
2561 | = (GET_CODE (whole_jump_insn) == SEQUENCE | |
2562 | ? PATTERN (XVECEXP (whole_jump_insn, 0, 0)) : whole_jump_insn); | |
2563 | ||
2564 | asm_fprintf (stream, | |
2565 | "\t.word %LL%d-.%s\n", | |
2566 | CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (XVECEXP | |
2567 | (parallel_jump, 0, 0), | |
2568 | 1), 2), 0)), | |
2569 | (TARGET_PDEBUG ? "; default" : "")); | |
2570 | return; | |
2571 | } | |
2572 | ||
2573 | asm_fprintf (stream, | |
2574 | "\t.word %LL%d-%LL%d%s\n", | |
2575 | CODE_LABEL_NUMBER (XEXP | |
2576 | (XEXP | |
a50023f9 | 2577 | (XEXP (XVECEXP (whole_jump_insn, 0, 0), 1), |
c31500c2 HPN |
2578 | 2), 0)), |
2579 | num, | |
2580 | (TARGET_PDEBUG ? "; default" : "")); | |
0b85d816 HPN |
2581 | } |
2582 | ||
c5387660 | 2583 | /* The TARGET_OPTION_OVERRIDE worker. |
0b85d816 HPN |
2584 | As is the norm, this also parses -mfoo=bar type parameters. */ |
2585 | ||
c5387660 JM |
2586 | static void |
2587 | cris_option_override (void) | |
0b85d816 HPN |
2588 | { |
2589 | if (cris_max_stackframe_str) | |
2590 | { | |
2591 | cris_max_stackframe = atoi (cris_max_stackframe_str); | |
2592 | ||
2593 | /* Do some sanity checking. */ | |
2594 | if (cris_max_stackframe < 0 || cris_max_stackframe > 0x20000000) | |
2595 | internal_error ("-max-stackframe=%d is not usable, not between 0 and %d", | |
2596 | cris_max_stackframe, 0x20000000); | |
2597 | } | |
2598 | ||
2599 | /* Let "-metrax4" and "-metrax100" change the cpu version. */ | |
2600 | if (TARGET_SVINTO && cris_cpu_version < CRIS_CPU_SVINTO) | |
2601 | cris_cpu_version = CRIS_CPU_SVINTO; | |
2602 | else if (TARGET_ETRAX4_ADD && cris_cpu_version < CRIS_CPU_ETRAX4) | |
2603 | cris_cpu_version = CRIS_CPU_ETRAX4; | |
2604 | ||
2605 | /* Parse -march=... and its synonym, the deprecated -mcpu=... */ | |
2606 | if (cris_cpu_str) | |
2607 | { | |
2608 | cris_cpu_version | |
2609 | = (*cris_cpu_str == 'v' ? atoi (cris_cpu_str + 1) : -1); | |
2610 | ||
2611 | if (strcmp ("etrax4", cris_cpu_str) == 0) | |
2612 | cris_cpu_version = 3; | |
2613 | ||
2614 | if (strcmp ("svinto", cris_cpu_str) == 0 | |
2615 | || strcmp ("etrax100", cris_cpu_str) == 0) | |
2616 | cris_cpu_version = 8; | |
2617 | ||
2618 | if (strcmp ("ng", cris_cpu_str) == 0 | |
2619 | || strcmp ("etrax100lx", cris_cpu_str) == 0) | |
2620 | cris_cpu_version = 10; | |
2621 | ||
c31500c2 | 2622 | if (cris_cpu_version < 0 || cris_cpu_version > 32) |
c725bd79 | 2623 | error ("unknown CRIS version specification in -march= or -mcpu= : %s", |
0b85d816 HPN |
2624 | cris_cpu_str); |
2625 | ||
2626 | /* Set the target flags. */ | |
2627 | if (cris_cpu_version >= CRIS_CPU_ETRAX4) | |
2a186d97 | 2628 | target_flags |= MASK_ETRAX4_ADD; |
0b85d816 HPN |
2629 | |
2630 | /* If this is Svinto or higher, align for 32 bit accesses. */ | |
2631 | if (cris_cpu_version >= CRIS_CPU_SVINTO) | |
2632 | target_flags | |
2a186d97 HPN |
2633 | |= (MASK_SVINTO | MASK_ALIGN_BY_32 |
2634 | | MASK_STACK_ALIGN | MASK_CONST_ALIGN | |
2635 | | MASK_DATA_ALIGN); | |
0b85d816 HPN |
2636 | |
2637 | /* Note that we do not add new flags when it can be completely | |
2638 | described with a macro that uses -mcpu=X. So | |
2639 | TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */ | |
2640 | } | |
2641 | ||
2642 | if (cris_tune_str) | |
2643 | { | |
2644 | int cris_tune | |
2645 | = (*cris_tune_str == 'v' ? atoi (cris_tune_str + 1) : -1); | |
2646 | ||
2647 | if (strcmp ("etrax4", cris_tune_str) == 0) | |
2648 | cris_tune = 3; | |
2649 | ||
2650 | if (strcmp ("svinto", cris_tune_str) == 0 | |
2651 | || strcmp ("etrax100", cris_tune_str) == 0) | |
2652 | cris_tune = 8; | |
2653 | ||
2654 | if (strcmp ("ng", cris_tune_str) == 0 | |
2655 | || strcmp ("etrax100lx", cris_tune_str) == 0) | |
2656 | cris_tune = 10; | |
2657 | ||
c31500c2 | 2658 | if (cris_tune < 0 || cris_tune > 32) |
c725bd79 | 2659 | error ("unknown CRIS cpu version specification in -mtune= : %s", |
0b85d816 HPN |
2660 | cris_tune_str); |
2661 | ||
2662 | if (cris_tune >= CRIS_CPU_SVINTO) | |
2663 | /* We have currently nothing more to tune than alignment for | |
2664 | memory accesses. */ | |
2665 | target_flags | |
2a186d97 HPN |
2666 | |= (MASK_STACK_ALIGN | MASK_CONST_ALIGN |
2667 | | MASK_DATA_ALIGN | MASK_ALIGN_BY_32); | |
0b85d816 HPN |
2668 | } |
2669 | ||
c31500c2 HPN |
2670 | if (cris_cpu_version >= CRIS_CPU_V32) |
2671 | target_flags &= ~(MASK_SIDE_EFFECT_PREFIXES|MASK_MUL_BUG); | |
2672 | ||
0b85d816 HPN |
2673 | if (flag_pic) |
2674 | { | |
2675 | /* Use error rather than warning, so invalid use is easily | |
2676 | detectable. Still change to the values we expect, to avoid | |
2677 | further errors. */ | |
2678 | if (! TARGET_LINUX) | |
2679 | { | |
1a05e874 | 2680 | error ("-fPIC and -fpic are not supported in this configuration"); |
0b85d816 HPN |
2681 | flag_pic = 0; |
2682 | } | |
2683 | ||
2684 | /* Turn off function CSE. We need to have the addresses reach the | |
2685 | call expanders to get PLT-marked, as they could otherwise be | |
2686 | compared against zero directly or indirectly. After visiting the | |
2687 | call expanders they will then be cse:ed, as the call expanders | |
2688 | force_reg the addresses, effectively forcing flag_no_function_cse | |
2689 | to 0. */ | |
2690 | flag_no_function_cse = 1; | |
2691 | } | |
2692 | ||
0b85d816 HPN |
2693 | /* Set the per-function-data initializer. */ |
2694 | init_machine_status = cris_init_machine_status; | |
2695 | } | |
2696 | ||
eb0424da | 2697 | /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */ |
0b85d816 | 2698 | |
c590b625 | 2699 | static void |
6640377c SB |
2700 | cris_asm_output_mi_thunk (FILE *stream, |
2701 | tree thunkdecl ATTRIBUTE_UNUSED, | |
2702 | HOST_WIDE_INT delta, | |
2703 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
2704 | tree funcdecl) | |
0b85d816 | 2705 | { |
097f98d4 HPN |
2706 | /* Make sure unwind info is emitted for the thunk if needed. */ |
2707 | final_start_function (emit_barrier (), stream, 1); | |
2708 | ||
0b85d816 | 2709 | if (delta > 0) |
4a0a75dd KG |
2710 | fprintf (stream, "\tadd%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n", |
2711 | ADDITIVE_SIZE_MODIFIER (delta), delta, | |
2712 | reg_names[CRIS_FIRST_ARG_REG]); | |
0b85d816 | 2713 | else if (delta < 0) |
4a0a75dd KG |
2714 | fprintf (stream, "\tsub%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n", |
2715 | ADDITIVE_SIZE_MODIFIER (-delta), -delta, | |
2716 | reg_names[CRIS_FIRST_ARG_REG]); | |
0b85d816 HPN |
2717 | |
2718 | if (flag_pic) | |
2719 | { | |
2720 | const char *name = XSTR (XEXP (DECL_RTL (funcdecl), 0), 0); | |
2721 | ||
772c5265 | 2722 | name = (* targetm.strip_name_encoding) (name); |
c31500c2 HPN |
2723 | |
2724 | if (TARGET_V32) | |
2725 | { | |
2726 | fprintf (stream, "\tba "); | |
2727 | assemble_name (stream, name); | |
2728 | fprintf (stream, "%s\n", CRIS_PLT_PCOFFSET_SUFFIX); | |
2729 | } | |
2730 | else | |
2731 | { | |
2732 | fprintf (stream, "add.d "); | |
2733 | assemble_name (stream, name); | |
2734 | fprintf (stream, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX); | |
2735 | } | |
0b85d816 HPN |
2736 | } |
2737 | else | |
2738 | { | |
2739 | fprintf (stream, "jump "); | |
2740 | assemble_name (stream, XSTR (XEXP (DECL_RTL (funcdecl), 0), 0)); | |
2741 | fprintf (stream, "\n"); | |
c31500c2 HPN |
2742 | |
2743 | if (TARGET_V32) | |
2744 | fprintf (stream, "\tnop\n"); | |
0b85d816 | 2745 | } |
097f98d4 HPN |
2746 | |
2747 | final_end_function (); | |
0b85d816 HPN |
2748 | } |
2749 | ||
15883505 | 2750 | /* Boilerplate emitted at start of file. |
1bc7c5b6 ZW |
2751 | |
2752 | NO_APP *only at file start* means faster assembly. It also means | |
2753 | comments are not allowed. In some cases comments will be output | |
0df965d7 | 2754 | for debugging purposes. Make sure they are allowed then. */ |
1bc7c5b6 | 2755 | static void |
6640377c | 2756 | cris_file_start (void) |
1bc7c5b6 ZW |
2757 | { |
2758 | /* These expressions can vary at run time, so we cannot put | |
2759 | them into TARGET_INITIALIZER. */ | |
38f8b050 | 2760 | targetm.asm_file_start_app_off = !(TARGET_PDEBUG || flag_print_asm_name); |
1bc7c5b6 ZW |
2761 | |
2762 | default_file_start (); | |
2763 | } | |
2764 | ||
922a784c HPN |
2765 | /* Output that goes at the end of the file, similarly. */ |
2766 | ||
2767 | static void | |
2768 | cris_file_end (void) | |
2769 | { | |
2770 | /* For CRIS, the default is to assume *no* executable stack, so output | |
2771 | an executable-stack-note only when needed. */ | |
2772 | if (TARGET_LINUX && trampolines_created) | |
2773 | file_end_indicate_exec_stack (); | |
2774 | } | |
2775 | ||
c15c90bb ZW |
2776 | /* Rename the function calls for integer multiply and divide. */ |
2777 | static void | |
30ee56e1 | 2778 | cris_init_libfuncs (void) |
c15c90bb ZW |
2779 | { |
2780 | set_optab_libfunc (smul_optab, SImode, "__Mul"); | |
2781 | set_optab_libfunc (sdiv_optab, SImode, "__Div"); | |
2782 | set_optab_libfunc (udiv_optab, SImode, "__Udiv"); | |
2783 | set_optab_libfunc (smod_optab, SImode, "__Mod"); | |
2784 | set_optab_libfunc (umod_optab, SImode, "__Umod"); | |
dec4306f HPN |
2785 | |
2786 | /* Atomic data being unaligned is unfortunately a reality. | |
2787 | Deal with it. */ | |
2788 | if (TARGET_ATOMICS_MAY_CALL_LIBFUNCS) | |
2789 | { | |
2790 | set_optab_libfunc (sync_compare_and_swap_optab, SImode, | |
2791 | "__cris_atcmpxchgr32"); | |
2792 | set_optab_libfunc (sync_compare_and_swap_optab, HImode, | |
2793 | "__cris_atcmpxchgr16"); | |
2794 | } | |
c15c90bb ZW |
2795 | } |
2796 | ||
0b85d816 HPN |
2797 | /* The INIT_EXPANDERS worker sets the per-function-data initializer and |
2798 | mark functions. */ | |
2799 | ||
2800 | void | |
6640377c | 2801 | cris_init_expanders (void) |
0b85d816 HPN |
2802 | { |
2803 | /* Nothing here at the moment. */ | |
2804 | } | |
2805 | ||
2806 | /* Zero initialization is OK for all current fields. */ | |
2807 | ||
e2500fed | 2808 | static struct machine_function * |
6640377c | 2809 | cris_init_machine_status (void) |
0b85d816 | 2810 | { |
766090c2 | 2811 | return ggc_cleared_alloc<machine_function> (); |
0b85d816 HPN |
2812 | } |
2813 | ||
2814 | /* Split a 2 word move (DI or presumably DF) into component parts. | |
2815 | Originally a copy of gen_split_move_double in m32r.c. */ | |
2816 | ||
2817 | rtx | |
6640377c | 2818 | cris_split_movdx (rtx *operands) |
0b85d816 HPN |
2819 | { |
2820 | enum machine_mode mode = GET_MODE (operands[0]); | |
2821 | rtx dest = operands[0]; | |
2822 | rtx src = operands[1]; | |
2823 | rtx val; | |
2824 | ||
3d556836 HPN |
2825 | /* We used to have to handle (SUBREG (MEM)) here, but that should no |
2826 | longer happen; after reload there are no SUBREGs any more, and we're | |
2827 | only called after reload. */ | |
b6c34129 | 2828 | CRIS_ASSERT (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG); |
0b85d816 HPN |
2829 | |
2830 | start_sequence (); | |
991c42ac | 2831 | if (REG_P (dest)) |
0b85d816 HPN |
2832 | { |
2833 | int dregno = REGNO (dest); | |
2834 | ||
2835 | /* Reg-to-reg copy. */ | |
991c42ac | 2836 | if (REG_P (src)) |
0b85d816 HPN |
2837 | { |
2838 | int sregno = REGNO (src); | |
2839 | ||
2840 | int reverse = (dregno == sregno + 1); | |
2841 | ||
2842 | /* We normally copy the low-numbered register first. However, if | |
2843 | the first register operand 0 is the same as the second register of | |
2844 | operand 1, we must copy in the opposite order. */ | |
2845 | emit_insn (gen_rtx_SET (VOIDmode, | |
2846 | operand_subword (dest, reverse, TRUE, mode), | |
2847 | operand_subword (src, reverse, TRUE, mode))); | |
2848 | ||
2849 | emit_insn (gen_rtx_SET (VOIDmode, | |
2850 | operand_subword (dest, !reverse, TRUE, mode), | |
2851 | operand_subword (src, !reverse, TRUE, mode))); | |
2852 | } | |
2853 | /* Constant-to-reg copy. */ | |
991c42ac | 2854 | else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE) |
0b85d816 HPN |
2855 | { |
2856 | rtx words[2]; | |
2857 | split_double (src, &words[0], &words[1]); | |
2858 | emit_insn (gen_rtx_SET (VOIDmode, | |
2859 | operand_subword (dest, 0, TRUE, mode), | |
2860 | words[0])); | |
2861 | ||
2862 | emit_insn (gen_rtx_SET (VOIDmode, | |
2863 | operand_subword (dest, 1, TRUE, mode), | |
2864 | words[1])); | |
2865 | } | |
2866 | /* Mem-to-reg copy. */ | |
991c42ac | 2867 | else if (MEM_P (src)) |
0b85d816 HPN |
2868 | { |
2869 | /* If the high-address word is used in the address, we must load it | |
2870 | last. Otherwise, load it first. */ | |
2871 | rtx addr = XEXP (src, 0); | |
2872 | int reverse | |
2873 | = (refers_to_regno_p (dregno, dregno + 1, addr, NULL) != 0); | |
2874 | ||
1ae58c30 | 2875 | /* The original code implies that we can't do |
0b85d816 HPN |
2876 | move.x [rN+],rM move.x [rN],rM+1 |
2877 | when rN is dead, because of REG_NOTES damage. That is | |
2878 | consistent with what I've seen, so don't try it. | |
2879 | ||
2880 | We have two different cases here; if the addr is POST_INC, | |
2881 | just pass it through, otherwise add constants. */ | |
2882 | ||
2883 | if (GET_CODE (addr) == POST_INC) | |
2884 | { | |
752b602f HPN |
2885 | rtx mem; |
2886 | rtx insn; | |
2887 | ||
2888 | /* Whenever we emit insns with post-incremented | |
2889 | addresses ourselves, we must add a post-inc note | |
2890 | manually. */ | |
2891 | mem = change_address (src, SImode, addr); | |
2892 | insn | |
2893 | = gen_rtx_SET (VOIDmode, | |
2894 | operand_subword (dest, 0, TRUE, mode), mem); | |
2895 | insn = emit_insn (insn); | |
2896 | if (GET_CODE (XEXP (mem, 0)) == POST_INC) | |
2897 | REG_NOTES (insn) | |
2898 | = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), | |
2899 | REG_NOTES (insn)); | |
2900 | ||
c31500c2 | 2901 | mem = copy_rtx (mem); |
752b602f HPN |
2902 | insn |
2903 | = gen_rtx_SET (VOIDmode, | |
2904 | operand_subword (dest, 1, TRUE, mode), mem); | |
2905 | insn = emit_insn (insn); | |
2906 | if (GET_CODE (XEXP (mem, 0)) == POST_INC) | |
2907 | REG_NOTES (insn) | |
2908 | = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), | |
2909 | REG_NOTES (insn)); | |
0b85d816 HPN |
2910 | } |
2911 | else | |
2912 | { | |
2913 | /* Make sure we don't get any other addresses with | |
2914 | embedded postincrements. They should be stopped in | |
2915 | GO_IF_LEGITIMATE_ADDRESS, but we're here for your | |
2916 | safety. */ | |
2917 | if (side_effects_p (addr)) | |
c725bd79 | 2918 | fatal_insn ("unexpected side-effects in address", addr); |
0b85d816 HPN |
2919 | |
2920 | emit_insn (gen_rtx_SET | |
2921 | (VOIDmode, | |
2922 | operand_subword (dest, reverse, TRUE, mode), | |
2923 | change_address | |
2924 | (src, SImode, | |
0a81f074 | 2925 | plus_constant (Pmode, addr, |
0b85d816 HPN |
2926 | reverse * UNITS_PER_WORD)))); |
2927 | emit_insn (gen_rtx_SET | |
2928 | (VOIDmode, | |
2929 | operand_subword (dest, ! reverse, TRUE, mode), | |
2930 | change_address | |
2931 | (src, SImode, | |
0a81f074 | 2932 | plus_constant (Pmode, addr, |
0b85d816 HPN |
2933 | (! reverse) * |
2934 | UNITS_PER_WORD)))); | |
2935 | } | |
2936 | } | |
2937 | else | |
d8a07487 | 2938 | internal_error ("unknown src"); |
0b85d816 HPN |
2939 | } |
2940 | /* Reg-to-mem copy or clear mem. */ | |
991c42ac JBG |
2941 | else if (MEM_P (dest) |
2942 | && (REG_P (src) | |
0b85d816 HPN |
2943 | || src == const0_rtx |
2944 | || src == CONST0_RTX (DFmode))) | |
2945 | { | |
2946 | rtx addr = XEXP (dest, 0); | |
2947 | ||
2948 | if (GET_CODE (addr) == POST_INC) | |
2949 | { | |
752b602f HPN |
2950 | rtx mem; |
2951 | rtx insn; | |
991c42ac | 2952 | |
752b602f HPN |
2953 | /* Whenever we emit insns with post-incremented addresses |
2954 | ourselves, we must add a post-inc note manually. */ | |
2955 | mem = change_address (dest, SImode, addr); | |
2956 | insn | |
2957 | = gen_rtx_SET (VOIDmode, | |
2958 | mem, operand_subword (src, 0, TRUE, mode)); | |
2959 | insn = emit_insn (insn); | |
2960 | if (GET_CODE (XEXP (mem, 0)) == POST_INC) | |
2961 | REG_NOTES (insn) | |
2962 | = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), | |
2963 | REG_NOTES (insn)); | |
2964 | ||
c31500c2 | 2965 | mem = copy_rtx (mem); |
752b602f HPN |
2966 | insn |
2967 | = gen_rtx_SET (VOIDmode, | |
2968 | mem, | |
2969 | operand_subword (src, 1, TRUE, mode)); | |
2970 | insn = emit_insn (insn); | |
2971 | if (GET_CODE (XEXP (mem, 0)) == POST_INC) | |
2972 | REG_NOTES (insn) | |
2973 | = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), | |
2974 | REG_NOTES (insn)); | |
0b85d816 HPN |
2975 | } |
2976 | else | |
2977 | { | |
2978 | /* Make sure we don't get any other addresses with embedded | |
2979 | postincrements. They should be stopped in | |
2980 | GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */ | |
2981 | if (side_effects_p (addr)) | |
c725bd79 | 2982 | fatal_insn ("unexpected side-effects in address", addr); |
0b85d816 HPN |
2983 | |
2984 | emit_insn (gen_rtx_SET | |
2985 | (VOIDmode, | |
2986 | change_address (dest, SImode, addr), | |
2987 | operand_subword (src, 0, TRUE, mode))); | |
2988 | ||
2989 | emit_insn (gen_rtx_SET | |
2990 | (VOIDmode, | |
2991 | change_address (dest, SImode, | |
0a81f074 | 2992 | plus_constant (Pmode, addr, |
0b85d816 HPN |
2993 | UNITS_PER_WORD)), |
2994 | operand_subword (src, 1, TRUE, mode))); | |
2995 | } | |
2996 | } | |
2997 | ||
2998 | else | |
d8a07487 | 2999 | internal_error ("unknown dest"); |
0b85d816 | 3000 | |
2f937369 | 3001 | val = get_insns (); |
0b85d816 HPN |
3002 | end_sequence (); |
3003 | return val; | |
3004 | } | |
3005 | ||
d29b4b1b HPN |
3006 | /* The expander for the prologue pattern name. */ |
3007 | ||
3008 | void | |
3009 | cris_expand_prologue (void) | |
3010 | { | |
3011 | int regno; | |
3012 | int size = get_frame_size (); | |
3013 | /* Shorten the used name for readability. */ | |
38173d38 | 3014 | int cfoa_size = crtl->outgoing_args_size; |
d29b4b1b HPN |
3015 | int last_movem_reg = -1; |
3016 | int framesize = 0; | |
3017 | rtx mem, insn; | |
3018 | int return_address_on_stack = cris_return_address_on_stack (); | |
c00fc5cf | 3019 | int got_really_used = false; |
d29b4b1b | 3020 | int n_movem_regs = 0; |
38173d38 | 3021 | int pretend = crtl->args.pretend_args_size; |
d29b4b1b HPN |
3022 | |
3023 | /* Don't do anything if no prologues or epilogues are wanted. */ | |
3024 | if (!TARGET_PROLOGUE_EPILOGUE) | |
3025 | return; | |
3026 | ||
b6c34129 | 3027 | CRIS_ASSERT (size >= 0); |
d29b4b1b | 3028 | |
e3b5732b | 3029 | if (crtl->uses_pic_offset_table) |
c00fc5cf HPN |
3030 | { |
3031 | /* A reference may have been optimized out (like the abort () in | |
3032 | fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that | |
3033 | it's still used. */ | |
3034 | push_topmost_sequence (); | |
3035 | got_really_used | |
3036 | = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX); | |
3037 | pop_topmost_sequence (); | |
3038 | } | |
3039 | ||
d29b4b1b HPN |
3040 | /* Align the size to what's best for the CPU model. */ |
3041 | if (TARGET_STACK_ALIGN) | |
3042 | size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1; | |
3043 | ||
3044 | if (pretend) | |
3045 | { | |
3046 | /* See also cris_setup_incoming_varargs where | |
3047 | cfun->machine->stdarg_regs is set. There are other setters of | |
38173d38 | 3048 | crtl->args.pretend_args_size than stdarg handling, like |
d29b4b1b HPN |
3049 | for an argument passed with parts in R13 and stack. We must |
3050 | not store R13 into the pretend-area for that case, as GCC does | |
3051 | that itself. "Our" store would be marked as redundant and GCC | |
3052 | will attempt to remove it, which will then be flagged as an | |
3053 | internal error; trying to remove a frame-related insn. */ | |
3054 | int stdarg_regs = cfun->machine->stdarg_regs; | |
3055 | ||
3056 | framesize += pretend; | |
3057 | ||
3058 | for (regno = CRIS_FIRST_ARG_REG + CRIS_MAX_ARGS_IN_REGS - 1; | |
3059 | stdarg_regs > 0; | |
3060 | regno--, pretend -= 4, stdarg_regs--) | |
3061 | { | |
3062 | insn = emit_insn (gen_rtx_SET (VOIDmode, | |
3063 | stack_pointer_rtx, | |
0a81f074 RS |
3064 | plus_constant (Pmode, |
3065 | stack_pointer_rtx, | |
d29b4b1b HPN |
3066 | -4))); |
3067 | /* FIXME: When dwarf2 frame output and unless asynchronous | |
3068 | exceptions, make dwarf2 bundle together all stack | |
3069 | adjustments like it does for registers between stack | |
3070 | adjustments. */ | |
3071 | RTX_FRAME_RELATED_P (insn) = 1; | |
3072 | ||
3073 | mem = gen_rtx_MEM (SImode, stack_pointer_rtx); | |
3074 | set_mem_alias_set (mem, get_varargs_alias_set ()); | |
3075 | insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, regno)); | |
3076 | ||
3077 | /* Note the absence of RTX_FRAME_RELATED_P on the above insn: | |
3078 | the value isn't restored, so we don't want to tell dwarf2 | |
3079 | that it's been stored to stack, else EH handling info would | |
3080 | get confused. */ | |
3081 | } | |
3082 | ||
38173d38 | 3083 | /* For other setters of crtl->args.pretend_args_size, we |
d29b4b1b HPN |
3084 | just adjust the stack by leaving the remaining size in |
3085 | "pretend", handled below. */ | |
3086 | } | |
3087 | ||
3088 | /* Save SRP if not a leaf function. */ | |
3089 | if (return_address_on_stack) | |
3090 | { | |
3091 | insn = emit_insn (gen_rtx_SET (VOIDmode, | |
3092 | stack_pointer_rtx, | |
0a81f074 | 3093 | plus_constant (Pmode, stack_pointer_rtx, |
d29b4b1b HPN |
3094 | -4 - pretend))); |
3095 | pretend = 0; | |
3096 | RTX_FRAME_RELATED_P (insn) = 1; | |
3097 | ||
3098 | mem = gen_rtx_MEM (SImode, stack_pointer_rtx); | |
3099 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
3100 | insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM)); | |
3101 | RTX_FRAME_RELATED_P (insn) = 1; | |
3102 | framesize += 4; | |
3103 | } | |
3104 | ||
3105 | /* Set up the frame pointer, if needed. */ | |
3106 | if (frame_pointer_needed) | |
3107 | { | |
3108 | insn = emit_insn (gen_rtx_SET (VOIDmode, | |
3109 | stack_pointer_rtx, | |
0a81f074 | 3110 | plus_constant (Pmode, stack_pointer_rtx, |
d29b4b1b HPN |
3111 | -4 - pretend))); |
3112 | pretend = 0; | |
3113 | RTX_FRAME_RELATED_P (insn) = 1; | |
3114 | ||
3115 | mem = gen_rtx_MEM (SImode, stack_pointer_rtx); | |
3116 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
3117 | insn = emit_move_insn (mem, frame_pointer_rtx); | |
3118 | RTX_FRAME_RELATED_P (insn) = 1; | |
3119 | ||
3120 | insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); | |
3121 | RTX_FRAME_RELATED_P (insn) = 1; | |
3122 | ||
3123 | framesize += 4; | |
3124 | } | |
3125 | ||
3126 | /* Between frame-pointer and saved registers lie the area for local | |
3127 | variables. If we get here with "pretended" size remaining, count | |
3128 | it into the general stack size. */ | |
3129 | size += pretend; | |
3130 | ||
3131 | /* Get a contiguous sequence of registers, starting with R0, that need | |
3132 | to be saved. */ | |
3133 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
3134 | { | |
3135 | if (cris_reg_saved_in_regsave_area (regno, got_really_used)) | |
3136 | { | |
3137 | n_movem_regs++; | |
3138 | ||
3139 | /* Check if movem may be used for registers so far. */ | |
3140 | if (regno == last_movem_reg + 1) | |
3141 | /* Yes, update next expected register. */ | |
3142 | last_movem_reg = regno; | |
3143 | else | |
3144 | { | |
3145 | /* We cannot use movem for all registers. We have to flush | |
3146 | any movem:ed registers we got so far. */ | |
3147 | if (last_movem_reg != -1) | |
3148 | { | |
3149 | int n_saved | |
3150 | = (n_movem_regs == 1) ? 1 : last_movem_reg + 1; | |
3151 | ||
3152 | /* It is a win to use a side-effect assignment for | |
3153 | 64 <= size <= 128. But side-effect on movem was | |
3154 | not usable for CRIS v0..3. Also only do it if | |
3155 | side-effects insns are allowed. */ | |
3156 | if ((last_movem_reg + 1) * 4 + size >= 64 | |
3157 | && (last_movem_reg + 1) * 4 + size <= 128 | |
3158 | && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1) | |
3159 | && TARGET_SIDE_EFFECT_PREFIXES) | |
3160 | { | |
3161 | mem | |
3162 | = gen_rtx_MEM (SImode, | |
0a81f074 | 3163 | plus_constant (Pmode, stack_pointer_rtx, |
d29b4b1b HPN |
3164 | -(n_saved * 4 + size))); |
3165 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
3166 | insn | |
3167 | = cris_emit_movem_store (mem, GEN_INT (n_saved), | |
3168 | -(n_saved * 4 + size), | |
3169 | true); | |
3170 | } | |
3171 | else | |
3172 | { | |
3173 | insn | |
3174 | = gen_rtx_SET (VOIDmode, | |
3175 | stack_pointer_rtx, | |
0a81f074 | 3176 | plus_constant (Pmode, stack_pointer_rtx, |
d29b4b1b HPN |
3177 | -(n_saved * 4 + size))); |
3178 | insn = emit_insn (insn); | |
3179 | RTX_FRAME_RELATED_P (insn) = 1; | |
3180 | ||
3181 | mem = gen_rtx_MEM (SImode, stack_pointer_rtx); | |
3182 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
3183 | insn = cris_emit_movem_store (mem, GEN_INT (n_saved), | |
3184 | 0, true); | |
3185 | } | |
3186 | ||
3187 | framesize += n_saved * 4 + size; | |
3188 | last_movem_reg = -1; | |
3189 | size = 0; | |
3190 | } | |
3191 | ||
3192 | insn = emit_insn (gen_rtx_SET (VOIDmode, | |
3193 | stack_pointer_rtx, | |
0a81f074 RS |
3194 | plus_constant (Pmode, |
3195 | stack_pointer_rtx, | |
d29b4b1b HPN |
3196 | -4 - size))); |
3197 | RTX_FRAME_RELATED_P (insn) = 1; | |
3198 | ||
3199 | mem = gen_rtx_MEM (SImode, stack_pointer_rtx); | |
3200 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
3201 | insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, regno)); | |
3202 | RTX_FRAME_RELATED_P (insn) = 1; | |
3203 | ||
3204 | framesize += 4 + size; | |
3205 | size = 0; | |
3206 | } | |
3207 | } | |
3208 | } | |
3209 | ||
3210 | /* Check after, if we could movem all registers. This is the normal case. */ | |
3211 | if (last_movem_reg != -1) | |
3212 | { | |
3213 | int n_saved | |
3214 | = (n_movem_regs == 1) ? 1 : last_movem_reg + 1; | |
3215 | ||
3216 | /* Side-effect on movem was not usable for CRIS v0..3. Also only | |
3217 | do it if side-effects insns are allowed. */ | |
3218 | if ((last_movem_reg + 1) * 4 + size >= 64 | |
3219 | && (last_movem_reg + 1) * 4 + size <= 128 | |
3220 | && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1) | |
3221 | && TARGET_SIDE_EFFECT_PREFIXES) | |
3222 | { | |
3223 | mem | |
3224 | = gen_rtx_MEM (SImode, | |
0a81f074 | 3225 | plus_constant (Pmode, stack_pointer_rtx, |
d29b4b1b HPN |
3226 | -(n_saved * 4 + size))); |
3227 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
3228 | insn = cris_emit_movem_store (mem, GEN_INT (n_saved), | |
3229 | -(n_saved * 4 + size), true); | |
3230 | } | |
3231 | else | |
3232 | { | |
3233 | insn | |
3234 | = gen_rtx_SET (VOIDmode, | |
3235 | stack_pointer_rtx, | |
0a81f074 | 3236 | plus_constant (Pmode, stack_pointer_rtx, |
d29b4b1b HPN |
3237 | -(n_saved * 4 + size))); |
3238 | insn = emit_insn (insn); | |
3239 | RTX_FRAME_RELATED_P (insn) = 1; | |
3240 | ||
3241 | mem = gen_rtx_MEM (SImode, stack_pointer_rtx); | |
3242 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
3243 | insn = cris_emit_movem_store (mem, GEN_INT (n_saved), 0, true); | |
3244 | } | |
3245 | ||
3246 | framesize += n_saved * 4 + size; | |
3247 | /* We have to put outgoing argument space after regs. */ | |
3248 | if (cfoa_size) | |
3249 | { | |
3250 | insn = emit_insn (gen_rtx_SET (VOIDmode, | |
3251 | stack_pointer_rtx, | |
0a81f074 RS |
3252 | plus_constant (Pmode, |
3253 | stack_pointer_rtx, | |
d29b4b1b HPN |
3254 | -cfoa_size))); |
3255 | RTX_FRAME_RELATED_P (insn) = 1; | |
3256 | framesize += cfoa_size; | |
3257 | } | |
3258 | } | |
3259 | else if ((size + cfoa_size) > 0) | |
3260 | { | |
3261 | insn = emit_insn (gen_rtx_SET (VOIDmode, | |
3262 | stack_pointer_rtx, | |
0a81f074 RS |
3263 | plus_constant (Pmode, |
3264 | stack_pointer_rtx, | |
d29b4b1b HPN |
3265 | -(cfoa_size + size)))); |
3266 | RTX_FRAME_RELATED_P (insn) = 1; | |
3267 | framesize += size + cfoa_size; | |
3268 | } | |
3269 | ||
3270 | /* Set up the PIC register, if it is used. */ | |
3271 | if (got_really_used) | |
3272 | { | |
3273 | rtx got | |
3274 | = gen_rtx_UNSPEC (SImode, gen_rtvec (1, const0_rtx), CRIS_UNSPEC_GOT); | |
3275 | emit_move_insn (pic_offset_table_rtx, got); | |
3276 | ||
3277 | /* FIXME: This is a cover-up for flow2 messing up; it doesn't | |
3278 | follow exceptional paths and tries to delete the GOT load as | |
3279 | unused, if it isn't used on the non-exceptional paths. Other | |
3280 | ports have similar or other cover-ups, or plain bugs marking | |
3281 | the GOT register load as maybe-dead. To see this, remove the | |
3282 | line below and try libsupc++/vec.cc or a trivial | |
3283 | "static void y (); void x () {try {y ();} catch (...) {}}". */ | |
c41c1387 | 3284 | emit_use (pic_offset_table_rtx); |
d29b4b1b HPN |
3285 | } |
3286 | ||
3287 | if (cris_max_stackframe && framesize > cris_max_stackframe) | |
d4ee4d25 | 3288 | warning (0, "stackframe too big: %d bytes", framesize); |
d29b4b1b HPN |
3289 | } |
3290 | ||
04539954 HPN |
3291 | /* The expander for the epilogue pattern. */ |
3292 | ||
3293 | void | |
3294 | cris_expand_epilogue (void) | |
3295 | { | |
3296 | int regno; | |
3297 | int size = get_frame_size (); | |
3298 | int last_movem_reg = -1; | |
38173d38 JH |
3299 | int argspace_offset = crtl->outgoing_args_size; |
3300 | int pretend = crtl->args.pretend_args_size; | |
04539954 HPN |
3301 | rtx mem; |
3302 | bool return_address_on_stack = cris_return_address_on_stack (); | |
3303 | /* A reference may have been optimized out | |
3304 | (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1) | |
3305 | so check that it's still used. */ | |
c00fc5cf | 3306 | int got_really_used = false; |
04539954 HPN |
3307 | int n_movem_regs = 0; |
3308 | ||
3309 | if (!TARGET_PROLOGUE_EPILOGUE) | |
3310 | return; | |
3311 | ||
e3b5732b | 3312 | if (crtl->uses_pic_offset_table) |
c00fc5cf HPN |
3313 | { |
3314 | /* A reference may have been optimized out (like the abort () in | |
3315 | fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that | |
3316 | it's still used. */ | |
3317 | push_topmost_sequence (); | |
3318 | got_really_used | |
3319 | = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX); | |
3320 | pop_topmost_sequence (); | |
3321 | } | |
3322 | ||
04539954 HPN |
3323 | /* Align byte count of stack frame. */ |
3324 | if (TARGET_STACK_ALIGN) | |
3325 | size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1; | |
3326 | ||
3327 | /* Check how many saved regs we can movem. They start at r0 and must | |
3328 | be contiguous. */ | |
3329 | for (regno = 0; | |
3330 | regno < FIRST_PSEUDO_REGISTER; | |
3331 | regno++) | |
3332 | if (cris_reg_saved_in_regsave_area (regno, got_really_used)) | |
3333 | { | |
3334 | n_movem_regs++; | |
3335 | ||
3336 | if (regno == last_movem_reg + 1) | |
3337 | last_movem_reg = regno; | |
3338 | else | |
3339 | break; | |
3340 | } | |
3341 | ||
3342 | /* If there was only one register that really needed to be saved | |
3343 | through movem, don't use movem. */ | |
3344 | if (n_movem_regs == 1) | |
3345 | last_movem_reg = -1; | |
3346 | ||
3347 | /* Now emit "normal" move insns for all regs higher than the movem | |
3348 | regs. */ | |
3349 | for (regno = FIRST_PSEUDO_REGISTER - 1; | |
3350 | regno > last_movem_reg; | |
3351 | regno--) | |
3352 | if (cris_reg_saved_in_regsave_area (regno, got_really_used)) | |
3353 | { | |
752b602f HPN |
3354 | rtx insn; |
3355 | ||
04539954 HPN |
3356 | if (argspace_offset) |
3357 | { | |
3358 | /* There is an area for outgoing parameters located before | |
3359 | the saved registers. We have to adjust for that. */ | |
3360 | emit_insn (gen_rtx_SET (VOIDmode, | |
3361 | stack_pointer_rtx, | |
0a81f074 | 3362 | plus_constant (Pmode, stack_pointer_rtx, |
04539954 HPN |
3363 | argspace_offset))); |
3364 | /* Make sure we only do this once. */ | |
3365 | argspace_offset = 0; | |
3366 | } | |
3367 | ||
3368 | mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode, | |
3369 | stack_pointer_rtx)); | |
3370 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
752b602f HPN |
3371 | insn = emit_move_insn (gen_rtx_raw_REG (SImode, regno), mem); |
3372 | ||
3373 | /* Whenever we emit insns with post-incremented addresses | |
3374 | ourselves, we must add a post-inc note manually. */ | |
3375 | REG_NOTES (insn) | |
3376 | = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); | |
04539954 HPN |
3377 | } |
3378 | ||
3379 | /* If we have any movem-restore, do it now. */ | |
3380 | if (last_movem_reg != -1) | |
3381 | { | |
752b602f HPN |
3382 | rtx insn; |
3383 | ||
04539954 HPN |
3384 | if (argspace_offset) |
3385 | { | |
3386 | emit_insn (gen_rtx_SET (VOIDmode, | |
3387 | stack_pointer_rtx, | |
0a81f074 | 3388 | plus_constant (Pmode, stack_pointer_rtx, |
04539954 HPN |
3389 | argspace_offset))); |
3390 | argspace_offset = 0; | |
3391 | } | |
3392 | ||
3393 | mem = gen_rtx_MEM (SImode, | |
3394 | gen_rtx_POST_INC (SImode, stack_pointer_rtx)); | |
3395 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
752b602f HPN |
3396 | insn |
3397 | = emit_insn (cris_gen_movem_load (mem, | |
3398 | GEN_INT (last_movem_reg + 1), 0)); | |
3399 | /* Whenever we emit insns with post-incremented addresses | |
3400 | ourselves, we must add a post-inc note manually. */ | |
3401 | if (side_effects_p (PATTERN (insn))) | |
3402 | REG_NOTES (insn) | |
3403 | = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); | |
04539954 HPN |
3404 | } |
3405 | ||
3406 | /* If we don't clobber all of the allocated stack area (we've already | |
3407 | deallocated saved registers), GCC might want to schedule loads from | |
3408 | the stack to *after* the stack-pointer restore, which introduces an | |
3409 | interrupt race condition. This happened for the initial-value | |
3410 | SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of | |
3411 | other failure for that test). It also happened for the stack slot | |
3412 | for the return value in (one version of) | |
3413 | linux/fs/dcache.c:__d_lookup, at least with "-O2 | |
3414 | -fno-omit-frame-pointer". */ | |
3415 | ||
3416 | /* Restore frame pointer if necessary. */ | |
3417 | if (frame_pointer_needed) | |
3418 | { | |
752b602f HPN |
3419 | rtx insn; |
3420 | ||
04539954 HPN |
3421 | emit_insn (gen_cris_frame_deallocated_barrier ()); |
3422 | ||
3423 | emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); | |
3424 | mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode, | |
3425 | stack_pointer_rtx)); | |
3426 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
752b602f HPN |
3427 | insn = emit_move_insn (frame_pointer_rtx, mem); |
3428 | ||
3429 | /* Whenever we emit insns with post-incremented addresses | |
3430 | ourselves, we must add a post-inc note manually. */ | |
3431 | REG_NOTES (insn) | |
3432 | = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); | |
04539954 HPN |
3433 | } |
3434 | else if ((size + argspace_offset) != 0) | |
3435 | { | |
3436 | emit_insn (gen_cris_frame_deallocated_barrier ()); | |
3437 | ||
3438 | /* If there was no frame-pointer to restore sp from, we must | |
3439 | explicitly deallocate local variables. */ | |
3440 | ||
3441 | /* Handle space for outgoing parameters that hasn't been handled | |
3442 | yet. */ | |
3443 | size += argspace_offset; | |
3444 | ||
3445 | emit_insn (gen_rtx_SET (VOIDmode, | |
3446 | stack_pointer_rtx, | |
0a81f074 | 3447 | plus_constant (Pmode, stack_pointer_rtx, size))); |
04539954 HPN |
3448 | } |
3449 | ||
3450 | /* If this function has no pushed register parameters | |
3451 | (stdargs/varargs), and if it is not a leaf function, then we have | |
3452 | the return address on the stack. */ | |
3453 | if (return_address_on_stack && pretend == 0) | |
3454 | { | |
e3b5732b | 3455 | if (TARGET_V32 || crtl->calls_eh_return) |
04539954 HPN |
3456 | { |
3457 | rtx mem; | |
752b602f | 3458 | rtx insn; |
04539954 HPN |
3459 | rtx srpreg = gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM); |
3460 | mem = gen_rtx_MEM (SImode, | |
3461 | gen_rtx_POST_INC (SImode, | |
3462 | stack_pointer_rtx)); | |
3463 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
752b602f HPN |
3464 | insn = emit_move_insn (srpreg, mem); |
3465 | ||
3466 | /* Whenever we emit insns with post-incremented addresses | |
3467 | ourselves, we must add a post-inc note manually. */ | |
3468 | REG_NOTES (insn) | |
3469 | = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); | |
04539954 | 3470 | |
e3b5732b | 3471 | if (crtl->calls_eh_return) |
c31500c2 HPN |
3472 | emit_insn (gen_addsi3 (stack_pointer_rtx, |
3473 | stack_pointer_rtx, | |
3474 | gen_rtx_raw_REG (SImode, | |
3475 | CRIS_STACKADJ_REG))); | |
04539954 HPN |
3476 | cris_expand_return (false); |
3477 | } | |
3478 | else | |
3479 | cris_expand_return (true); | |
3480 | ||
3481 | return; | |
3482 | } | |
3483 | ||
3484 | /* If we pushed some register parameters, then adjust the stack for | |
3485 | them. */ | |
3486 | if (pretend != 0) | |
3487 | { | |
3488 | /* If SRP is stored on the way, we need to restore it first. */ | |
3489 | if (return_address_on_stack) | |
3490 | { | |
3491 | rtx mem; | |
3492 | rtx srpreg = gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM); | |
752b602f HPN |
3493 | rtx insn; |
3494 | ||
04539954 HPN |
3495 | mem = gen_rtx_MEM (SImode, |
3496 | gen_rtx_POST_INC (SImode, | |
3497 | stack_pointer_rtx)); | |
3498 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
752b602f HPN |
3499 | insn = emit_move_insn (srpreg, mem); |
3500 | ||
3501 | /* Whenever we emit insns with post-incremented addresses | |
3502 | ourselves, we must add a post-inc note manually. */ | |
3503 | REG_NOTES (insn) | |
3504 | = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); | |
04539954 HPN |
3505 | } |
3506 | ||
3507 | emit_insn (gen_rtx_SET (VOIDmode, | |
3508 | stack_pointer_rtx, | |
0a81f074 RS |
3509 | plus_constant (Pmode, stack_pointer_rtx, |
3510 | pretend))); | |
04539954 HPN |
3511 | } |
3512 | ||
3513 | /* Perform the "physical" unwinding that the EH machinery calculated. */ | |
e3b5732b | 3514 | if (crtl->calls_eh_return) |
04539954 HPN |
3515 | emit_insn (gen_addsi3 (stack_pointer_rtx, |
3516 | stack_pointer_rtx, | |
3517 | gen_rtx_raw_REG (SImode, | |
3518 | CRIS_STACKADJ_REG))); | |
3519 | cris_expand_return (false); | |
3520 | } | |
3521 | ||
3522 | /* Worker function for generating movem from mem for load_multiple. */ | |
3523 | ||
3524 | rtx | |
d29b4b1b | 3525 | cris_gen_movem_load (rtx src, rtx nregs_rtx, int nprefix) |
04539954 HPN |
3526 | { |
3527 | int nregs = INTVAL (nregs_rtx); | |
3528 | rtvec vec; | |
3529 | int eltno = 1; | |
3530 | int i; | |
d29b4b1b | 3531 | rtx srcreg = XEXP (src, 0); |
04539954 HPN |
3532 | unsigned int regno = nregs - 1; |
3533 | int regno_inc = -1; | |
3534 | ||
c31500c2 HPN |
3535 | if (TARGET_V32) |
3536 | { | |
3537 | regno = 0; | |
3538 | regno_inc = 1; | |
3539 | } | |
3540 | ||
04539954 HPN |
3541 | if (GET_CODE (srcreg) == POST_INC) |
3542 | srcreg = XEXP (srcreg, 0); | |
3543 | ||
b6c34129 | 3544 | CRIS_ASSERT (REG_P (srcreg)); |
04539954 HPN |
3545 | |
3546 | /* Don't use movem for just one insn. The insns are equivalent except | |
d29b4b1b HPN |
3547 | for the pipeline hazard (on v32); movem does not forward the loaded |
3548 | registers so there's a three cycles penalty for their use. */ | |
04539954 | 3549 | if (nregs == 1) |
d29b4b1b | 3550 | return gen_movsi (gen_rtx_REG (SImode, 0), src); |
04539954 HPN |
3551 | |
3552 | vec = rtvec_alloc (nprefix + nregs | |
d29b4b1b | 3553 | + (GET_CODE (XEXP (src, 0)) == POST_INC)); |
04539954 | 3554 | |
d29b4b1b | 3555 | if (GET_CODE (XEXP (src, 0)) == POST_INC) |
04539954 HPN |
3556 | { |
3557 | RTVEC_ELT (vec, nprefix + 1) | |
0a81f074 RS |
3558 | = gen_rtx_SET (VOIDmode, srcreg, |
3559 | plus_constant (Pmode, srcreg, nregs * 4)); | |
04539954 HPN |
3560 | eltno++; |
3561 | } | |
3562 | ||
d29b4b1b HPN |
3563 | src = replace_equiv_address (src, srcreg); |
3564 | RTVEC_ELT (vec, nprefix) | |
3565 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno), src); | |
3566 | regno += regno_inc; | |
3567 | ||
04539954 HPN |
3568 | for (i = 1; i < nregs; i++, eltno++) |
3569 | { | |
3570 | RTVEC_ELT (vec, nprefix + eltno) | |
3571 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno), | |
3572 | adjust_address_nv (src, SImode, i * 4)); | |
3573 | regno += regno_inc; | |
3574 | } | |
3575 | ||
3576 | return gen_rtx_PARALLEL (VOIDmode, vec); | |
3577 | } | |
3578 | ||
d29b4b1b HPN |
3579 | /* Worker function for generating movem to mem. If FRAME_RELATED, notes |
3580 | are added that the dwarf2 machinery understands. */ | |
3581 | ||
3582 | rtx | |
3583 | cris_emit_movem_store (rtx dest, rtx nregs_rtx, int increment, | |
3584 | bool frame_related) | |
3585 | { | |
3586 | int nregs = INTVAL (nregs_rtx); | |
3587 | rtvec vec; | |
3588 | int eltno = 1; | |
3589 | int i; | |
3590 | rtx insn; | |
3591 | rtx destreg = XEXP (dest, 0); | |
3592 | unsigned int regno = nregs - 1; | |
3593 | int regno_inc = -1; | |
3594 | ||
c31500c2 HPN |
3595 | if (TARGET_V32) |
3596 | { | |
3597 | regno = 0; | |
3598 | regno_inc = 1; | |
3599 | } | |
3600 | ||
d29b4b1b HPN |
3601 | if (GET_CODE (destreg) == POST_INC) |
3602 | increment += nregs * 4; | |
3603 | ||
3604 | if (GET_CODE (destreg) == POST_INC || GET_CODE (destreg) == PLUS) | |
3605 | destreg = XEXP (destreg, 0); | |
3606 | ||
b6c34129 | 3607 | CRIS_ASSERT (REG_P (destreg)); |
d29b4b1b HPN |
3608 | |
3609 | /* Don't use movem for just one insn. The insns are equivalent except | |
3610 | for the pipeline hazard (on v32); movem does not forward the loaded | |
3611 | registers so there's a three cycles penalty for use. */ | |
3612 | if (nregs == 1) | |
3613 | { | |
3614 | rtx mov = gen_rtx_SET (VOIDmode, dest, gen_rtx_REG (SImode, 0)); | |
3615 | ||
3616 | if (increment == 0) | |
3617 | { | |
3618 | insn = emit_insn (mov); | |
3619 | if (frame_related) | |
3620 | RTX_FRAME_RELATED_P (insn) = 1; | |
3621 | return insn; | |
3622 | } | |
3623 | ||
3624 | /* If there was a request for a side-effect, create the ordinary | |
3625 | parallel. */ | |
3626 | vec = rtvec_alloc (2); | |
3627 | ||
3628 | RTVEC_ELT (vec, 0) = mov; | |
3629 | RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, destreg, | |
0a81f074 RS |
3630 | plus_constant (Pmode, destreg, |
3631 | increment)); | |
d29b4b1b HPN |
3632 | if (frame_related) |
3633 | { | |
3634 | RTX_FRAME_RELATED_P (mov) = 1; | |
3635 | RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1; | |
3636 | } | |
3637 | } | |
3638 | else | |
3639 | { | |
3640 | vec = rtvec_alloc (nregs + (increment != 0 ? 1 : 0)); | |
3641 | RTVEC_ELT (vec, 0) | |
3642 | = gen_rtx_SET (VOIDmode, | |
3643 | replace_equiv_address (dest, | |
0a81f074 | 3644 | plus_constant (Pmode, destreg, |
d29b4b1b HPN |
3645 | increment)), |
3646 | gen_rtx_REG (SImode, regno)); | |
3647 | regno += regno_inc; | |
3648 | ||
3649 | /* The dwarf2 info wants this mark on each component in a parallel | |
3650 | that's part of the prologue (though it's optional on the first | |
3651 | component). */ | |
3652 | if (frame_related) | |
3653 | RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 0)) = 1; | |
3654 | ||
3655 | if (increment != 0) | |
3656 | { | |
3657 | RTVEC_ELT (vec, 1) | |
3658 | = gen_rtx_SET (VOIDmode, destreg, | |
0a81f074 | 3659 | plus_constant (Pmode, destreg, |
d29b4b1b HPN |
3660 | increment != 0 |
3661 | ? increment : nregs * 4)); | |
3662 | eltno++; | |
3663 | ||
3664 | if (frame_related) | |
3665 | RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1; | |
3666 | ||
3667 | /* Don't call adjust_address_nv on a post-incremented address if | |
3668 | we can help it. */ | |
3669 | if (GET_CODE (XEXP (dest, 0)) == POST_INC) | |
3670 | dest = replace_equiv_address (dest, destreg); | |
3671 | } | |
3672 | ||
3673 | for (i = 1; i < nregs; i++, eltno++) | |
3674 | { | |
3675 | RTVEC_ELT (vec, eltno) | |
3676 | = gen_rtx_SET (VOIDmode, adjust_address_nv (dest, SImode, i * 4), | |
3677 | gen_rtx_REG (SImode, regno)); | |
3678 | if (frame_related) | |
3679 | RTX_FRAME_RELATED_P (RTVEC_ELT (vec, eltno)) = 1; | |
3680 | regno += regno_inc; | |
3681 | } | |
3682 | } | |
3683 | ||
3684 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, vec)); | |
3685 | ||
3686 | /* Because dwarf2out.c handles the insns in a parallel as a sequence, | |
3687 | we need to keep the stack adjustment separate, after the | |
3688 | MEM-setters. Else the stack-adjustment in the second component of | |
3689 | the parallel would be mishandled; the offsets for the SETs that | |
3690 | follow it would be wrong. We prepare for this by adding a | |
3691 | REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE | |
3692 | followed by the increment. Note that we have FRAME_RELATED_P on | |
3693 | all the SETs, including the original stack adjustment SET in the | |
3694 | parallel. */ | |
3695 | if (frame_related) | |
3696 | { | |
3697 | if (increment != 0) | |
3698 | { | |
3699 | rtx seq = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (nregs + 1)); | |
dfc0fb23 | 3700 | XVECEXP (seq, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn), 0, 0)); |
d29b4b1b | 3701 | for (i = 1; i < nregs; i++) |
dfc0fb23 HPN |
3702 | XVECEXP (seq, 0, i) |
3703 | = copy_rtx (XVECEXP (PATTERN (insn), 0, i + 1)); | |
3704 | XVECEXP (seq, 0, nregs) = copy_rtx (XVECEXP (PATTERN (insn), 0, 1)); | |
973c3795 | 3705 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, seq); |
d29b4b1b HPN |
3706 | } |
3707 | ||
3708 | RTX_FRAME_RELATED_P (insn) = 1; | |
3709 | } | |
3710 | ||
3711 | return insn; | |
3712 | } | |
3713 | ||
c00fc5cf HPN |
3714 | /* Worker function for expanding the address for PIC function calls. */ |
3715 | ||
3716 | void | |
3717 | cris_expand_pic_call_address (rtx *opp) | |
3718 | { | |
3719 | rtx op = *opp; | |
3720 | ||
3721 | gcc_assert (MEM_P (op)); | |
3722 | op = XEXP (op, 0); | |
3723 | ||
3724 | /* It might be that code can be generated that jumps to 0 (or to a | |
3725 | specific address). Don't die on that. (There is a | |
3726 | testcase.) */ | |
31af2dca | 3727 | if (CONSTANT_ADDRESS_P (op) && !CONST_INT_P (op)) |
c00fc5cf HPN |
3728 | { |
3729 | enum cris_pic_symbol_type t = cris_pic_symbol_type_of (op); | |
3730 | ||
b3a13419 | 3731 | CRIS_ASSERT (can_create_pseudo_p ()); |
c00fc5cf HPN |
3732 | |
3733 | /* For local symbols (non-PLT), just get the plain symbol | |
3734 | reference into a register. For symbols that can be PLT, make | |
3735 | them PLT. */ | |
c31500c2 HPN |
3736 | if (t == cris_rel_symbol) |
3737 | { | |
3738 | /* For v32, we're fine as-is; just PICify the symbol. Forcing | |
3739 | into a register caused performance regression for 3.2.1, | |
3740 | observable in __floatdidf and elsewhere in libgcc. */ | |
3741 | if (TARGET_V32) | |
3742 | { | |
3743 | rtx sym = GET_CODE (op) != CONST ? op : get_related_value (op); | |
3744 | HOST_WIDE_INT offs = get_integer_term (op); | |
3745 | ||
3746 | /* We can't get calls to sym+N, N integer, can we? */ | |
3747 | gcc_assert (offs == 0); | |
3748 | ||
3749 | op = gen_rtx_CONST (Pmode, | |
3750 | gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), | |
3751 | CRIS_UNSPEC_PCREL)); | |
3752 | } | |
3753 | else | |
3754 | op = force_reg (Pmode, op); | |
3755 | } | |
c00fc5cf HPN |
3756 | else if (t == cris_got_symbol) |
3757 | { | |
3758 | if (TARGET_AVOID_GOTPLT) | |
3759 | { | |
3760 | /* Change a "jsr sym" into (allocate register rM, rO) | |
c31500c2 HPN |
3761 | "move.d (const (unspec [sym rPIC] CRIS_UNSPEC_PLT_GOTREL)),rM" |
3762 | "add.d rPIC,rM,rO", "jsr rO" for pre-v32 and | |
3763 | "jsr (const (unspec [sym rPIC] CRIS_UNSPEC_PLT_PCREL))" | |
3764 | for v32. */ | |
c00fc5cf | 3765 | rtx tem, rm, ro; |
b3a13419 | 3766 | gcc_assert (can_create_pseudo_p ()); |
e3b5732b | 3767 | crtl->uses_pic_offset_table = 1; |
c31500c2 HPN |
3768 | tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op), |
3769 | TARGET_V32 | |
3770 | ? CRIS_UNSPEC_PLT_PCREL | |
3771 | : CRIS_UNSPEC_PLT_GOTREL); | |
3772 | tem = gen_rtx_CONST (Pmode, tem); | |
3773 | if (TARGET_V32) | |
3774 | op = tem; | |
3775 | else | |
3776 | { | |
3777 | rm = gen_reg_rtx (Pmode); | |
3778 | emit_move_insn (rm, tem); | |
3779 | ro = gen_reg_rtx (Pmode); | |
3780 | if (expand_binop (Pmode, add_optab, rm, | |
3781 | pic_offset_table_rtx, | |
3782 | ro, 0, OPTAB_LIB_WIDEN) != ro) | |
3783 | internal_error ("expand_binop failed in movsi got"); | |
3784 | op = ro; | |
3785 | } | |
c00fc5cf HPN |
3786 | } |
3787 | else | |
3788 | { | |
3789 | /* Change a "jsr sym" into (allocate register rM, rO) | |
c31500c2 | 3790 | "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOTREAD)),rM" |
c00fc5cf HPN |
3791 | "add.d rPIC,rM,rO" "jsr [rO]" with the memory access |
3792 | marked as not trapping and not aliasing. No "move.d | |
3793 | [rO],rP" as that would invite to re-use of a value | |
3794 | that should not be reused. FIXME: Need a peephole2 | |
3795 | for cases when this is cse:d from the call, to change | |
3796 | back to just get the PLT entry address, so we don't | |
3797 | resolve the same symbol over and over (the memory | |
3798 | access of the PLTGOT isn't constant). */ | |
3799 | rtx tem, mem, rm, ro; | |
3800 | ||
b3a13419 | 3801 | gcc_assert (can_create_pseudo_p ()); |
e3b5732b | 3802 | crtl->uses_pic_offset_table = 1; |
c00fc5cf HPN |
3803 | tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op), |
3804 | CRIS_UNSPEC_PLTGOTREAD); | |
3805 | rm = gen_reg_rtx (Pmode); | |
3806 | emit_move_insn (rm, gen_rtx_CONST (Pmode, tem)); | |
3807 | ro = gen_reg_rtx (Pmode); | |
3808 | if (expand_binop (Pmode, add_optab, rm, | |
3809 | pic_offset_table_rtx, | |
3810 | ro, 0, OPTAB_LIB_WIDEN) != ro) | |
3811 | internal_error ("expand_binop failed in movsi got"); | |
3812 | mem = gen_rtx_MEM (Pmode, ro); | |
3813 | ||
3814 | /* This MEM doesn't alias anything. Whether it aliases | |
3815 | other same symbols is unimportant. */ | |
3816 | set_mem_alias_set (mem, new_alias_set ()); | |
3817 | MEM_NOTRAP_P (mem) = 1; | |
3818 | op = mem; | |
3819 | } | |
3820 | } | |
3821 | else | |
3822 | /* Can't possibly get a GOT-needing-fixup for a function-call, | |
3823 | right? */ | |
d8a07487 | 3824 | fatal_insn ("unidentifiable call op", op); |
c00fc5cf HPN |
3825 | |
3826 | *opp = replace_equiv_address (*opp, op); | |
3827 | } | |
3828 | } | |
3829 | ||
7faa3eb8 | 3830 | /* Make sure operands are in the right order for an addsi3 insn as |
5e41dd6f HPN |
3831 | generated by a define_split. Nothing but REG_P as the first |
3832 | operand is recognized by addsi3 after reload. OPERANDS contains | |
3833 | the operands, with the first at OPERANDS[N] and the second at | |
3834 | OPERANDS[N+1]. */ | |
7faa3eb8 HPN |
3835 | |
3836 | void | |
3837 | cris_order_for_addsi3 (rtx *operands, int n) | |
3838 | { | |
5e41dd6f | 3839 | if (!REG_P (operands[n])) |
7faa3eb8 HPN |
3840 | { |
3841 | rtx tem = operands[n]; | |
3842 | operands[n] = operands[n + 1]; | |
3843 | operands[n + 1] = tem; | |
3844 | } | |
3845 | } | |
3846 | ||
453bd0f5 HPN |
3847 | /* Use from within code, from e.g. PRINT_OPERAND and |
3848 | PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit | |
3849 | different things depending on whether code operand or constant is | |
3850 | emitted. */ | |
0b85d816 | 3851 | |
453bd0f5 | 3852 | static void |
6640377c | 3853 | cris_output_addr_const (FILE *file, rtx x) |
0b85d816 | 3854 | { |
453bd0f5 HPN |
3855 | in_code++; |
3856 | output_addr_const (file, x); | |
3857 | in_code--; | |
3858 | } | |
0b85d816 | 3859 | |
453bd0f5 | 3860 | /* Worker function for ASM_OUTPUT_SYMBOL_REF. */ |
0b85d816 | 3861 | |
453bd0f5 HPN |
3862 | void |
3863 | cris_asm_output_symbol_ref (FILE *file, rtx x) | |
3864 | { | |
c00fc5cf HPN |
3865 | gcc_assert (GET_CODE (x) == SYMBOL_REF); |
3866 | ||
453bd0f5 HPN |
3867 | if (flag_pic && in_code > 0) |
3868 | { | |
c00fc5cf HPN |
3869 | const char *origstr = XSTR (x, 0); |
3870 | const char *str; | |
3871 | str = (* targetm.strip_name_encoding) (origstr); | |
3872 | assemble_name (file, str); | |
3873 | ||
3874 | /* Sanity check. */ | |
e3b5732b | 3875 | if (!TARGET_V32 && !crtl->uses_pic_offset_table) |
c00fc5cf | 3876 | output_operand_lossage ("PIC register isn't set up"); |
453bd0f5 HPN |
3877 | } |
3878 | else | |
3879 | assemble_name (file, XSTR (x, 0)); | |
3880 | } | |
0b85d816 | 3881 | |
453bd0f5 | 3882 | /* Worker function for ASM_OUTPUT_LABEL_REF. */ |
0b85d816 | 3883 | |
453bd0f5 HPN |
3884 | void |
3885 | cris_asm_output_label_ref (FILE *file, char *buf) | |
3886 | { | |
3887 | if (flag_pic && in_code > 0) | |
3888 | { | |
453bd0f5 | 3889 | assemble_name (file, buf); |
0b85d816 | 3890 | |
453bd0f5 | 3891 | /* Sanity check. */ |
e3b5732b | 3892 | if (!TARGET_V32 && !crtl->uses_pic_offset_table) |
d8a07487 JM |
3893 | internal_error ("emitting PIC operand, but PIC register " |
3894 | "isn%'t set up"); | |
453bd0f5 HPN |
3895 | } |
3896 | else | |
3897 | assemble_name (file, buf); | |
3898 | } | |
0b85d816 | 3899 | |
586747fc | 3900 | /* Worker function for TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */ |
0b85d816 | 3901 | |
586747fc | 3902 | static bool |
c00fc5cf | 3903 | cris_output_addr_const_extra (FILE *file, rtx xconst) |
453bd0f5 | 3904 | { |
c00fc5cf | 3905 | switch (GET_CODE (xconst)) |
453bd0f5 | 3906 | { |
c00fc5cf | 3907 | rtx x; |
0b85d816 | 3908 | |
453bd0f5 | 3909 | case UNSPEC: |
c00fc5cf HPN |
3910 | x = XVECEXP (xconst, 0, 0); |
3911 | CRIS_ASSERT (GET_CODE (x) == SYMBOL_REF | |
3912 | || GET_CODE (x) == LABEL_REF | |
3913 | || GET_CODE (x) == CONST); | |
3914 | output_addr_const (file, x); | |
3915 | switch (XINT (xconst, 1)) | |
0b85d816 | 3916 | { |
c31500c2 HPN |
3917 | case CRIS_UNSPEC_PCREL: |
3918 | /* We only get this with -fpic/PIC to tell it apart from an | |
3919 | invalid symbol. We can't tell here, but it should only | |
3920 | be the operand of a call or movsi. */ | |
3921 | gcc_assert (TARGET_V32 && flag_pic); | |
3922 | break; | |
3923 | ||
3924 | case CRIS_UNSPEC_PLT_PCREL: | |
3925 | gcc_assert (TARGET_V32); | |
3926 | fprintf (file, ":PLT"); | |
3927 | break; | |
3928 | ||
3929 | case CRIS_UNSPEC_PLT_GOTREL: | |
3930 | gcc_assert (!TARGET_V32); | |
453bd0f5 | 3931 | fprintf (file, ":PLTG"); |
c00fc5cf | 3932 | break; |
0b85d816 | 3933 | |
c00fc5cf | 3934 | case CRIS_UNSPEC_GOTREL: |
c31500c2 | 3935 | gcc_assert (!TARGET_V32); |
c00fc5cf HPN |
3936 | fprintf (file, ":GOTOFF"); |
3937 | break; | |
453bd0f5 | 3938 | |
c00fc5cf | 3939 | case CRIS_UNSPEC_GOTREAD: |
453bd0f5 | 3940 | if (flag_pic == 1) |
c00fc5cf | 3941 | fprintf (file, ":GOT16"); |
453bd0f5 | 3942 | else |
c00fc5cf HPN |
3943 | fprintf (file, ":GOT"); |
3944 | break; | |
3945 | ||
3946 | case CRIS_UNSPEC_PLTGOTREAD: | |
3947 | if (flag_pic == 1) | |
3948 | fprintf (file, CRIS_GOTPLT_SUFFIX "16"); | |
3949 | else | |
3950 | fprintf (file, CRIS_GOTPLT_SUFFIX); | |
3951 | break; | |
3952 | ||
3953 | default: | |
3954 | gcc_unreachable (); | |
0b85d816 | 3955 | } |
453bd0f5 | 3956 | return true; |
0b85d816 HPN |
3957 | |
3958 | default: | |
453bd0f5 | 3959 | return false; |
0b85d816 HPN |
3960 | } |
3961 | } | |
3962 | ||
a2fef3a4 KH |
3963 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ |
3964 | ||
3965 | static rtx | |
3966 | cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
3967 | int incoming ATTRIBUTE_UNUSED) | |
3968 | { | |
3969 | return gen_rtx_REG (Pmode, CRIS_STRUCT_VALUE_REGNUM); | |
3970 | } | |
3971 | ||
558d352a KH |
3972 | /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */ |
3973 | ||
3974 | static void | |
d5cc9181 | 3975 | cris_setup_incoming_varargs (cumulative_args_t ca_v, |
558d352a KH |
3976 | enum machine_mode mode ATTRIBUTE_UNUSED, |
3977 | tree type ATTRIBUTE_UNUSED, | |
3978 | int *pretend_arg_size, | |
3979 | int second_time) | |
3980 | { | |
d5cc9181 JR |
3981 | CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); |
3982 | ||
558d352a | 3983 | if (ca->regs < CRIS_MAX_ARGS_IN_REGS) |
558d352a | 3984 | { |
d29b4b1b HPN |
3985 | int stdarg_regs = CRIS_MAX_ARGS_IN_REGS - ca->regs; |
3986 | cfun->machine->stdarg_regs = stdarg_regs; | |
3987 | *pretend_arg_size = stdarg_regs * 4; | |
558d352a | 3988 | } |
d29b4b1b HPN |
3989 | |
3990 | if (TARGET_PDEBUG) | |
3991 | fprintf (asm_out_file, | |
3992 | "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n", | |
3993 | ca->regs, *pretend_arg_size, second_time); | |
558d352a KH |
3994 | } |
3995 | ||
8cd5a4e0 RH |
3996 | /* Return true if TYPE must be passed by invisible reference. |
3997 | For cris, we pass <= 8 bytes by value, others by reference. */ | |
3998 | ||
3999 | static bool | |
d5cc9181 | 4000 | cris_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED, |
586de218 | 4001 | enum machine_mode mode, const_tree type, |
8cd5a4e0 RH |
4002 | bool named ATTRIBUTE_UNUSED) |
4003 | { | |
4004 | return (targetm.calls.must_pass_in_stack (mode, type) | |
4005 | || CRIS_FUNCTION_ARG_SIZE (mode, type) > 8); | |
4006 | } | |
4007 | ||
cde0f3fd PB |
4008 | /* A combination of defining TARGET_PROMOTE_FUNCTION_MODE, promoting arguments |
4009 | and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the | |
4010 | best code size and speed for gcc, ipps and products in gcc-2.7.2. */ | |
4011 | ||
4012 | enum machine_mode | |
4013 | cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED, | |
4014 | enum machine_mode mode, | |
4015 | int *punsignedp ATTRIBUTE_UNUSED, | |
4016 | const_tree fntype ATTRIBUTE_UNUSED, | |
4017 | int for_return) | |
4018 | { | |
4019 | /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even | |
4d696ad0 AS |
4020 | when modifying TARGET_FUNCTION_VALUE to return the promoted mode). |
4021 | Maybe pointless as of now, but let's keep the old behavior. */ | |
666e3ceb | 4022 | if (for_return == 1) |
cde0f3fd PB |
4023 | return mode; |
4024 | return CRIS_PROMOTED_MODE (mode, *punsignedp, type); | |
4025 | } | |
4026 | ||
faee0106 HPN |
4027 | /* Atomic types require alignment to be at least their "natural" size. */ |
4028 | ||
4029 | static unsigned int | |
4030 | cris_atomic_align_for_mode (enum machine_mode mode) | |
4031 | { | |
4032 | return GET_MODE_BITSIZE (mode); | |
4033 | } | |
4034 | ||
4d696ad0 AS |
4035 | /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the |
4036 | time being. */ | |
4037 | ||
4038 | static rtx | |
4039 | cris_function_value(const_tree type, | |
4040 | const_tree func ATTRIBUTE_UNUSED, | |
4041 | bool outgoing ATTRIBUTE_UNUSED) | |
4042 | { | |
4043 | return gen_rtx_REG (TYPE_MODE (type), CRIS_FIRST_ARG_REG); | |
4044 | } | |
4045 | ||
4046 | /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the | |
4047 | time being. */ | |
4048 | ||
4049 | static rtx | |
4050 | cris_libcall_value (enum machine_mode mode, | |
4051 | const_rtx fun ATTRIBUTE_UNUSED) | |
4052 | { | |
4053 | return gen_rtx_REG (mode, CRIS_FIRST_ARG_REG); | |
4054 | } | |
4055 | ||
4056 | /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the | |
4057 | time being. */ | |
4058 | ||
2283c416 | 4059 | static bool |
4d696ad0 AS |
4060 | cris_function_value_regno_p (const unsigned int regno) |
4061 | { | |
4062 | return (regno == CRIS_FIRST_ARG_REG); | |
4063 | } | |
8cd5a4e0 | 4064 | |
78a52f11 | 4065 | static int |
d5cc9181 | 4066 | cris_arg_partial_bytes (cumulative_args_t ca, enum machine_mode mode, |
78a52f11 RH |
4067 | tree type, bool named ATTRIBUTE_UNUSED) |
4068 | { | |
d5cc9181 | 4069 | if (get_cumulative_args (ca)->regs == CRIS_MAX_ARGS_IN_REGS - 1 |
78a52f11 RH |
4070 | && !targetm.calls.must_pass_in_stack (mode, type) |
4071 | && CRIS_FUNCTION_ARG_SIZE (mode, type) > 4 | |
4072 | && CRIS_FUNCTION_ARG_SIZE (mode, type) <= 8) | |
4073 | return UNITS_PER_WORD; | |
4074 | else | |
4075 | return 0; | |
4076 | } | |
4077 | ||
73f3f841 | 4078 | static rtx |
d5cc9181 | 4079 | cris_function_arg_1 (cumulative_args_t ca_v, |
73f3f841 NF |
4080 | enum machine_mode mode ATTRIBUTE_UNUSED, |
4081 | const_tree type ATTRIBUTE_UNUSED, | |
4082 | bool named, bool incoming) | |
4083 | { | |
d5cc9181 JR |
4084 | const CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); |
4085 | ||
73f3f841 NF |
4086 | if ((!incoming || named) && ca->regs < CRIS_MAX_ARGS_IN_REGS) |
4087 | return gen_rtx_REG (mode, CRIS_FIRST_ARG_REG + ca->regs); | |
4088 | else | |
4089 | return NULL_RTX; | |
4090 | } | |
4091 | ||
4092 | /* Worker function for TARGET_FUNCTION_ARG. | |
4093 | The void_type_node is sent as a "closing" call. */ | |
4094 | ||
4095 | static rtx | |
d5cc9181 | 4096 | cris_function_arg (cumulative_args_t ca, enum machine_mode mode, |
73f3f841 NF |
4097 | const_tree type, bool named) |
4098 | { | |
4099 | return cris_function_arg_1 (ca, mode, type, named, false); | |
4100 | } | |
4101 | ||
4102 | /* Worker function for TARGET_FUNCTION_INCOMING_ARG. | |
4103 | ||
4104 | The differences between this and the previous, is that this one checks | |
4105 | that an argument is named, since incoming stdarg/varargs arguments are | |
4106 | pushed onto the stack, and we don't have to check against the "closing" | |
4107 | void_type_node TYPE parameter. */ | |
4108 | ||
4109 | static rtx | |
d5cc9181 | 4110 | cris_function_incoming_arg (cumulative_args_t ca, enum machine_mode mode, |
73f3f841 NF |
4111 | const_tree type, bool named) |
4112 | { | |
4113 | return cris_function_arg_1 (ca, mode, type, named, true); | |
4114 | } | |
4115 | ||
4116 | /* Worker function for TARGET_FUNCTION_ARG_ADVANCE. */ | |
4117 | ||
4118 | static void | |
d5cc9181 | 4119 | cris_function_arg_advance (cumulative_args_t ca_v, enum machine_mode mode, |
73f3f841 NF |
4120 | const_tree type, bool named ATTRIBUTE_UNUSED) |
4121 | { | |
d5cc9181 JR |
4122 | CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); |
4123 | ||
73f3f841 NF |
4124 | ca->regs += (3 + CRIS_FUNCTION_ARG_SIZE (mode, type)) / 4; |
4125 | } | |
4126 | ||
f60c7155 HPN |
4127 | /* Worker function for TARGET_MD_ASM_CLOBBERS. */ |
4128 | ||
4129 | static tree | |
f9968e3e | 4130 | cris_md_asm_clobbers (tree outputs, tree inputs, tree in_clobbers) |
f60c7155 | 4131 | { |
61158923 | 4132 | HARD_REG_SET mof_set; |
f9968e3e | 4133 | tree clobbers; |
61158923 HPN |
4134 | tree t; |
4135 | ||
4136 | CLEAR_HARD_REG_SET (mof_set); | |
4137 | SET_HARD_REG_BIT (mof_set, CRIS_MOF_REGNUM); | |
4138 | ||
f9968e3e HPN |
4139 | /* For the time being, all asms clobber condition codes. Revisit when |
4140 | there's a reasonable use for inputs/outputs that mention condition | |
4141 | codes. */ | |
4142 | clobbers | |
4143 | = tree_cons (NULL_TREE, | |
4144 | build_string (strlen (reg_names[CRIS_CC0_REGNUM]), | |
4145 | reg_names[CRIS_CC0_REGNUM]), | |
4146 | in_clobbers); | |
4147 | ||
61158923 HPN |
4148 | for (t = outputs; t != NULL; t = TREE_CHAIN (t)) |
4149 | { | |
4150 | tree val = TREE_VALUE (t); | |
4151 | ||
4152 | /* The constraint letter for the singleton register class of MOF | |
4153 | is 'h'. If it's mentioned in the constraints, the asm is | |
4154 | MOF-aware and adding it to the clobbers would cause it to have | |
4155 | impossible constraints. */ | |
4156 | if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t))), | |
4157 | 'h') != NULL | |
91b4415a | 4158 | || tree_overlaps_hard_reg_set (val, &mof_set) != NULL_TREE) |
61158923 HPN |
4159 | return clobbers; |
4160 | } | |
4161 | ||
4162 | for (t = inputs; t != NULL; t = TREE_CHAIN (t)) | |
4163 | { | |
4164 | tree val = TREE_VALUE (t); | |
4165 | ||
4166 | if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t))), | |
4167 | 'h') != NULL | |
91b4415a | 4168 | || tree_overlaps_hard_reg_set (val, &mof_set) != NULL_TREE) |
61158923 HPN |
4169 | return clobbers; |
4170 | } | |
4171 | ||
f60c7155 HPN |
4172 | return tree_cons (NULL_TREE, |
4173 | build_string (strlen (reg_names[CRIS_MOF_REGNUM]), | |
4174 | reg_names[CRIS_MOF_REGNUM]), | |
4175 | clobbers); | |
4176 | } | |
78a52f11 | 4177 | |
b52b1749 AS |
4178 | /* Implement TARGET_FRAME_POINTER_REQUIRED. |
4179 | ||
4180 | Really only needed if the stack frame has variable length (alloca | |
4181 | or variable sized local arguments (GNU C extension). See PR39499 and | |
4182 | PR38609 for the reason this isn't just 0. */ | |
4183 | ||
4184 | bool | |
4185 | cris_frame_pointer_required (void) | |
4186 | { | |
416ff32e | 4187 | return !crtl->sp_is_unchanging; |
b52b1749 AS |
4188 | } |
4189 | ||
3e322b77 RH |
4190 | /* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE. |
4191 | ||
4192 | This looks too complicated, and it is. I assigned r7 to be the | |
4193 | static chain register, but it is call-saved, so we have to save it, | |
4194 | and come back to restore it after the call, so we have to save srp... | |
4195 | Anyway, trampolines are rare enough that we can cope with this | |
4196 | somewhat lack of elegance. | |
4197 | (Do not be tempted to "straighten up" whitespace in the asms; the | |
4198 | assembler #NO_APP state mandates strict spacing). */ | |
4199 | /* ??? See the i386 regparm=3 implementation that pushes the static | |
4200 | chain value to the stack in the trampoline, and uses a call-saved | |
4201 | register when called directly. */ | |
4202 | ||
4203 | static void | |
4204 | cris_asm_trampoline_template (FILE *f) | |
4205 | { | |
4206 | if (TARGET_V32) | |
4207 | { | |
4208 | /* This normally-unused nop insn acts as an instruction to | |
4209 | the simulator to flush its instruction cache. None of | |
4210 | the other instructions in the trampoline template suits | |
4211 | as a trigger for V32. The pc-relative addressing mode | |
4212 | works nicely as a trigger for V10. | |
4213 | FIXME: Have specific V32 template (possibly avoiding the | |
4214 | use of a special instruction). */ | |
4215 | fprintf (f, "\tclearf x\n"); | |
4216 | /* We have to use a register as an intermediate, choosing | |
4217 | semi-randomly R1 (which has to not be the STATIC_CHAIN_REGNUM), | |
4218 | so we can use it for address indirection and jsr target. */ | |
4219 | fprintf (f, "\tmove $r1,$mof\n"); | |
4220 | /* +4 */ | |
4221 | fprintf (f, "\tmove.d 0,$r1\n"); | |
4222 | fprintf (f, "\tmove.d $%s,[$r1]\n", reg_names[STATIC_CHAIN_REGNUM]); | |
4223 | fprintf (f, "\taddq 6,$r1\n"); | |
4224 | fprintf (f, "\tmove $mof,[$r1]\n"); | |
4225 | fprintf (f, "\taddq 6,$r1\n"); | |
4226 | fprintf (f, "\tmove $srp,[$r1]\n"); | |
4227 | /* +20 */ | |
4228 | fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); | |
4229 | /* +26 */ | |
4230 | fprintf (f, "\tmove.d 0,$r1\n"); | |
4231 | fprintf (f, "\tjsr $r1\n"); | |
4232 | fprintf (f, "\tsetf\n"); | |
4233 | /* +36 */ | |
4234 | fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); | |
4235 | /* +42 */ | |
4236 | fprintf (f, "\tmove.d 0,$r1\n"); | |
4237 | /* +48 */ | |
4238 | fprintf (f, "\tmove.d 0,$r9\n"); | |
4239 | fprintf (f, "\tjump $r9\n"); | |
4240 | fprintf (f, "\tsetf\n"); | |
4241 | } | |
4242 | else | |
4243 | { | |
4244 | fprintf (f, "\tmove.d $%s,[$pc+20]\n", reg_names[STATIC_CHAIN_REGNUM]); | |
4245 | fprintf (f, "\tmove $srp,[$pc+22]\n"); | |
4246 | fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); | |
4247 | fprintf (f, "\tjsr 0\n"); | |
4248 | fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); | |
4249 | fprintf (f, "\tjump 0\n"); | |
4250 | } | |
4251 | } | |
4252 | ||
4253 | /* Implement TARGET_TRAMPOLINE_INIT. */ | |
4254 | ||
4255 | static void | |
4256 | cris_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
4257 | { | |
4258 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
4259 | rtx tramp = XEXP (m_tramp, 0); | |
4260 | rtx mem; | |
4261 | ||
4262 | emit_block_move (m_tramp, assemble_trampoline_template (), | |
4263 | GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); | |
4264 | ||
4265 | if (TARGET_V32) | |
4266 | { | |
4267 | mem = adjust_address (m_tramp, SImode, 6); | |
0a81f074 | 4268 | emit_move_insn (mem, plus_constant (Pmode, tramp, 38)); |
3e322b77 RH |
4269 | mem = adjust_address (m_tramp, SImode, 22); |
4270 | emit_move_insn (mem, chain_value); | |
4271 | mem = adjust_address (m_tramp, SImode, 28); | |
4272 | emit_move_insn (mem, fnaddr); | |
4273 | } | |
4274 | else | |
4275 | { | |
4276 | mem = adjust_address (m_tramp, SImode, 10); | |
4277 | emit_move_insn (mem, chain_value); | |
4278 | mem = adjust_address (m_tramp, SImode, 16); | |
4279 | emit_move_insn (mem, fnaddr); | |
4280 | } | |
4281 | ||
4282 | /* Note that there is no need to do anything with the cache for | |
4283 | sake of a trampoline. */ | |
4284 | } | |
4285 | ||
4286 | ||
0b85d816 HPN |
4287 | #if 0 |
4288 | /* Various small functions to replace macros. Only called from a | |
4289 | debugger. They might collide with gcc functions or system functions, | |
4290 | so only emit them when '#if 1' above. */ | |
4291 | ||
6640377c | 4292 | enum rtx_code Get_code (rtx); |
0b85d816 HPN |
4293 | |
4294 | enum rtx_code | |
6640377c | 4295 | Get_code (rtx x) |
0b85d816 HPN |
4296 | { |
4297 | return GET_CODE (x); | |
4298 | } | |
4299 | ||
6640377c | 4300 | const char *Get_mode (rtx); |
0b85d816 HPN |
4301 | |
4302 | const char * | |
6640377c | 4303 | Get_mode (rtx x) |
0b85d816 HPN |
4304 | { |
4305 | return GET_MODE_NAME (GET_MODE (x)); | |
4306 | } | |
4307 | ||
6640377c | 4308 | rtx Xexp (rtx, int); |
0b85d816 HPN |
4309 | |
4310 | rtx | |
6640377c | 4311 | Xexp (rtx x, int n) |
0b85d816 HPN |
4312 | { |
4313 | return XEXP (x, n); | |
4314 | } | |
4315 | ||
6640377c | 4316 | rtx Xvecexp (rtx, int, int); |
0b85d816 HPN |
4317 | |
4318 | rtx | |
6640377c | 4319 | Xvecexp (rtx x, int n, int m) |
117b0c0a | 4320 | { |
0b85d816 HPN |
4321 | return XVECEXP (x, n, m); |
4322 | } | |
4323 | ||
6640377c | 4324 | int Get_rtx_len (rtx); |
0b85d816 HPN |
4325 | |
4326 | int | |
6640377c | 4327 | Get_rtx_len (rtx x) |
0b85d816 HPN |
4328 | { |
4329 | return GET_RTX_LENGTH (GET_CODE (x)); | |
4330 | } | |
4331 | ||
4332 | /* Use upper-case to distinguish from local variables that are sometimes | |
4333 | called next_insn and prev_insn. */ | |
4334 | ||
6640377c | 4335 | rtx Next_insn (rtx); |
0b85d816 HPN |
4336 | |
4337 | rtx | |
6640377c | 4338 | Next_insn (rtx insn) |
0b85d816 HPN |
4339 | { |
4340 | return NEXT_INSN (insn); | |
4341 | } | |
4342 | ||
6640377c | 4343 | rtx Prev_insn (rtx); |
0b85d816 HPN |
4344 | |
4345 | rtx | |
6640377c | 4346 | Prev_insn (rtx insn) |
0b85d816 HPN |
4347 | { |
4348 | return PREV_INSN (insn); | |
4349 | } | |
4350 | #endif | |
4351 | ||
e2500fed GK |
4352 | #include "gt-cris.h" |
4353 | ||
0b85d816 HPN |
4354 | /* |
4355 | * Local variables: | |
4356 | * eval: (c-set-style "gnu") | |
4357 | * indent-tabs-mode: t | |
4358 | * End: | |
4359 | */ |