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Commit | Line | Data |
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0b85d816 | 1 | /* Definitions for GCC. Part of the machine description for CRIS. |
6fb5fa3c | 2 | Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
5cfc5f84 | 3 | Free Software Foundation, Inc. |
0b85d816 HPN |
4 | Contributed by Axis Communications. Written by Hans-Peter Nilsson. |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
2f83c7d6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
0b85d816 HPN |
11 | any later version. |
12 | ||
13 | GCC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
0b85d816 HPN |
21 | |
22 | #include "config.h" | |
23 | #include "system.h" | |
4977bab6 ZW |
24 | #include "coretypes.h" |
25 | #include "tm.h" | |
0b85d816 HPN |
26 | #include "rtl.h" |
27 | #include "regs.h" | |
28 | #include "hard-reg-set.h" | |
29 | #include "real.h" | |
30 | #include "insn-config.h" | |
31 | #include "conditions.h" | |
0b85d816 HPN |
32 | #include "insn-attr.h" |
33 | #include "flags.h" | |
34 | #include "tree.h" | |
35 | #include "expr.h" | |
36 | #include "except.h" | |
37 | #include "function.h" | |
38 | #include "toplev.h" | |
39 | #include "recog.h" | |
15883505 | 40 | #include "reload.h" |
0b85d816 HPN |
41 | #include "tm_p.h" |
42 | #include "debug.h" | |
78b14aa6 | 43 | #include "output.h" |
0b85d816 HPN |
44 | #include "target.h" |
45 | #include "target-def.h" | |
ae9dbf1f | 46 | #include "ggc.h" |
c15c90bb | 47 | #include "optabs.h" |
a3ef2349 | 48 | #include "df.h" |
0b85d816 HPN |
49 | |
50 | /* Usable when we have an amount to add or subtract, and want the | |
51 | optimal size of the insn. */ | |
52 | #define ADDITIVE_SIZE_MODIFIER(size) \ | |
53 | ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d") | |
54 | ||
a52453cc | 55 | #define LOSE_AND_RETURN(msgid, x) \ |
3d556836 HPN |
56 | do \ |
57 | { \ | |
a52453cc | 58 | cris_operand_lossage (msgid, x); \ |
3d556836 HPN |
59 | return; \ |
60 | } while (0) | |
61 | ||
04539954 HPN |
62 | enum cris_retinsn_type |
63 | { CRIS_RETINSN_UNKNOWN = 0, CRIS_RETINSN_RET, CRIS_RETINSN_JUMP }; | |
64 | ||
0b85d816 | 65 | /* Per-function machine data. */ |
e2500fed | 66 | struct machine_function GTY(()) |
0b85d816 HPN |
67 | { |
68 | int needs_return_address_on_stack; | |
d29b4b1b HPN |
69 | |
70 | /* This is the number of registers we save in the prologue due to | |
71 | stdarg. */ | |
72 | int stdarg_regs; | |
73 | ||
04539954 | 74 | enum cris_retinsn_type return_type; |
0b85d816 HPN |
75 | }; |
76 | ||
0b85d816 HPN |
77 | /* This little fix suppresses the 'u' or 's' when '%e' in assembly |
78 | pattern. */ | |
79 | static char cris_output_insn_is_bound = 0; | |
80 | ||
453bd0f5 HPN |
81 | /* In code for output macros, this is how we know whether e.g. constant |
82 | goes in code or in a static initializer. */ | |
83 | static int in_code = 0; | |
84 | ||
3d556836 | 85 | /* Fix for reg_overlap_mentioned_p. */ |
6640377c | 86 | static int cris_reg_overlap_mentioned_p (rtx, rtx); |
0b85d816 | 87 | |
6640377c | 88 | static void cris_print_base (rtx, FILE *); |
0b85d816 | 89 | |
6640377c | 90 | static void cris_print_index (rtx, FILE *); |
0b85d816 | 91 | |
453bd0f5 HPN |
92 | static void cris_output_addr_const (FILE *, rtx); |
93 | ||
6640377c | 94 | static struct machine_function * cris_init_machine_status (void); |
0b85d816 | 95 | |
a2fef3a4 KH |
96 | static rtx cris_struct_value_rtx (tree, int); |
97 | ||
558d352a KH |
98 | static void cris_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, |
99 | tree type, int *, int); | |
100 | ||
6640377c | 101 | static int cris_initial_frame_pointer_offset (void); |
3d556836 | 102 | |
6640377c | 103 | static int saved_regs_mentioned (rtx); |
0b85d816 | 104 | |
6640377c | 105 | static void cris_operand_lossage (const char *, rtx); |
3d556836 | 106 | |
04539954 HPN |
107 | static int cris_reg_saved_in_regsave_area (unsigned int, bool); |
108 | ||
c590b625 | 109 | static void cris_asm_output_mi_thunk |
6640377c | 110 | (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree); |
c590b625 | 111 | |
6640377c | 112 | static void cris_file_start (void); |
c15c90bb | 113 | static void cris_init_libfuncs (void); |
1bc7c5b6 | 114 | |
6640377c SB |
115 | static bool cris_rtx_costs (rtx, int, int, int *); |
116 | static int cris_address_cost (rtx); | |
8cd5a4e0 | 117 | static bool cris_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, |
586de218 | 118 | const_tree, bool); |
78a52f11 RH |
119 | static int cris_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
120 | tree, bool); | |
61158923 | 121 | static tree cris_md_asm_clobbers (tree, tree, tree); |
c590b625 | 122 | |
2a186d97 HPN |
123 | static bool cris_handle_option (size_t, const char *, int); |
124 | ||
0b85d816 HPN |
125 | /* This is the parsed result of the "-max-stack-stackframe=" option. If |
126 | it (still) is zero, then there was no such option given. */ | |
127 | int cris_max_stackframe = 0; | |
128 | ||
129 | /* This is the parsed result of the "-march=" option, if given. */ | |
130 | int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION; | |
131 | ||
301d03af RS |
132 | #undef TARGET_ASM_ALIGNED_HI_OP |
133 | #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
134 | #undef TARGET_ASM_ALIGNED_SI_OP | |
135 | #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t" | |
136 | #undef TARGET_ASM_ALIGNED_DI_OP | |
137 | #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" | |
138 | ||
139 | /* We need to define these, since the 2byte, 4byte, 8byte op:s are only | |
140 | available in ELF. These "normal" pseudos do not have any alignment | |
141 | constraints or side-effects. */ | |
142 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
143 | #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP | |
144 | ||
145 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
146 | #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP | |
147 | ||
148 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
149 | #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP | |
150 | ||
c590b625 RH |
151 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
152 | #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk | |
3961e8fe RH |
153 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
154 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
c590b625 | 155 | |
1bc7c5b6 ZW |
156 | #undef TARGET_ASM_FILE_START |
157 | #define TARGET_ASM_FILE_START cris_file_start | |
158 | ||
c15c90bb ZW |
159 | #undef TARGET_INIT_LIBFUNCS |
160 | #define TARGET_INIT_LIBFUNCS cris_init_libfuncs | |
161 | ||
75642f32 RH |
162 | #undef TARGET_RTX_COSTS |
163 | #define TARGET_RTX_COSTS cris_rtx_costs | |
164 | #undef TARGET_ADDRESS_COST | |
165 | #define TARGET_ADDRESS_COST cris_address_cost | |
166 | ||
a2fef3a4 | 167 | #undef TARGET_PROMOTE_FUNCTION_ARGS |
586de218 | 168 | #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true |
a2fef3a4 KH |
169 | #undef TARGET_STRUCT_VALUE_RTX |
170 | #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx | |
558d352a KH |
171 | #undef TARGET_SETUP_INCOMING_VARARGS |
172 | #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs | |
8cd5a4e0 RH |
173 | #undef TARGET_PASS_BY_REFERENCE |
174 | #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference | |
78a52f11 RH |
175 | #undef TARGET_ARG_PARTIAL_BYTES |
176 | #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes | |
f60c7155 HPN |
177 | #undef TARGET_MD_ASM_CLOBBERS |
178 | #define TARGET_MD_ASM_CLOBBERS cris_md_asm_clobbers | |
2a186d97 HPN |
179 | #undef TARGET_DEFAULT_TARGET_FLAGS |
180 | #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | CRIS_SUBTARGET_DEFAULT) | |
181 | #undef TARGET_HANDLE_OPTION | |
182 | #define TARGET_HANDLE_OPTION cris_handle_option | |
558d352a | 183 | |
0b85d816 HPN |
184 | struct gcc_target targetm = TARGET_INITIALIZER; |
185 | ||
04539954 HPN |
186 | /* Helper for cris_load_multiple_op and cris_ret_movem_op. */ |
187 | ||
68a81332 | 188 | bool |
04539954 HPN |
189 | cris_movem_load_rest_p (rtx op, int offs) |
190 | { | |
191 | unsigned int reg_count = XVECLEN (op, 0) - offs; | |
192 | rtx src_addr; | |
193 | int i; | |
194 | rtx elt; | |
195 | int setno; | |
196 | int regno_dir = 1; | |
197 | unsigned int regno = 0; | |
198 | ||
199 | /* Perform a quick check so we don't blow up below. FIXME: Adjust for | |
200 | other than (MEM reg). */ | |
201 | if (reg_count <= 1 | |
202 | || GET_CODE (XVECEXP (op, 0, offs)) != SET | |
991c42ac JBG |
203 | || !REG_P (SET_DEST (XVECEXP (op, 0, offs))) |
204 | || !MEM_P (SET_SRC (XVECEXP (op, 0, offs)))) | |
68a81332 | 205 | return false; |
04539954 HPN |
206 | |
207 | /* Check a possible post-inc indicator. */ | |
208 | if (GET_CODE (SET_SRC (XVECEXP (op, 0, offs + 1))) == PLUS) | |
209 | { | |
210 | rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 0); | |
211 | rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 1); | |
212 | ||
213 | reg_count--; | |
214 | ||
215 | if (reg_count == 1 | |
216 | || !REG_P (reg) | |
217 | || !REG_P (SET_DEST (XVECEXP (op, 0, offs + 1))) | |
218 | || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, offs + 1))) | |
991c42ac | 219 | || !CONST_INT_P (inc) |
04539954 | 220 | || INTVAL (inc) != (HOST_WIDE_INT) reg_count * 4) |
68a81332 | 221 | return false; |
04539954 HPN |
222 | i = offs + 2; |
223 | } | |
224 | else | |
225 | i = offs + 1; | |
226 | ||
c31500c2 HPN |
227 | if (!TARGET_V32) |
228 | { | |
229 | regno_dir = -1; | |
230 | regno = reg_count - 1; | |
231 | } | |
04539954 HPN |
232 | |
233 | elt = XVECEXP (op, 0, offs); | |
234 | src_addr = XEXP (SET_SRC (elt), 0); | |
235 | ||
236 | if (GET_CODE (elt) != SET | |
991c42ac | 237 | || !REG_P (SET_DEST (elt)) |
04539954 HPN |
238 | || GET_MODE (SET_DEST (elt)) != SImode |
239 | || REGNO (SET_DEST (elt)) != regno | |
991c42ac | 240 | || !MEM_P (SET_SRC (elt)) |
04539954 HPN |
241 | || GET_MODE (SET_SRC (elt)) != SImode |
242 | || !memory_address_p (SImode, src_addr)) | |
68a81332 | 243 | return false; |
04539954 HPN |
244 | |
245 | for (setno = 1; i < XVECLEN (op, 0); setno++, i++) | |
246 | { | |
247 | rtx elt = XVECEXP (op, 0, i); | |
248 | regno += regno_dir; | |
249 | ||
250 | if (GET_CODE (elt) != SET | |
991c42ac | 251 | || !REG_P (SET_DEST (elt)) |
04539954 HPN |
252 | || GET_MODE (SET_DEST (elt)) != SImode |
253 | || REGNO (SET_DEST (elt)) != regno | |
991c42ac | 254 | || !MEM_P (SET_SRC (elt)) |
04539954 HPN |
255 | || GET_MODE (SET_SRC (elt)) != SImode |
256 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
257 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
991c42ac | 258 | || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt), 0), 1)) |
04539954 | 259 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != setno * 4) |
68a81332 | 260 | return false; |
04539954 HPN |
261 | } |
262 | ||
68a81332 | 263 | return true; |
04539954 HPN |
264 | } |
265 | ||
68a81332 HPN |
266 | /* Worker function for predicate for the parallel contents in a movem |
267 | to-memory. */ | |
d29b4b1b | 268 | |
68a81332 HPN |
269 | bool |
270 | cris_store_multiple_op_p (rtx op) | |
d29b4b1b HPN |
271 | { |
272 | int reg_count = XVECLEN (op, 0); | |
273 | rtx dest; | |
274 | rtx dest_addr; | |
275 | rtx dest_base; | |
276 | int i; | |
277 | rtx elt; | |
278 | int setno; | |
279 | int regno_dir = 1; | |
280 | int regno = 0; | |
281 | int offset = 0; | |
282 | ||
283 | /* Perform a quick check so we don't blow up below. FIXME: Adjust for | |
284 | other than (MEM reg) and (MEM (PLUS reg const)). */ | |
285 | if (reg_count <= 1) | |
68a81332 | 286 | return false; |
d29b4b1b HPN |
287 | |
288 | elt = XVECEXP (op, 0, 0); | |
289 | ||
290 | if (GET_CODE (elt) != SET) | |
68a81332 | 291 | return false; |
d29b4b1b HPN |
292 | |
293 | dest = SET_DEST (elt); | |
294 | ||
991c42ac | 295 | if (!REG_P (SET_SRC (elt)) || !MEM_P (dest)) |
68a81332 | 296 | return false; |
d29b4b1b HPN |
297 | |
298 | dest_addr = XEXP (dest, 0); | |
299 | ||
300 | /* Check a possible post-inc indicator. */ | |
301 | if (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS) | |
302 | { | |
303 | rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 0); | |
304 | rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1); | |
305 | ||
306 | reg_count--; | |
307 | ||
308 | if (reg_count == 1 | |
309 | || !REG_P (reg) | |
310 | || !REG_P (SET_DEST (XVECEXP (op, 0, 1))) | |
311 | || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, 1))) | |
991c42ac | 312 | || !CONST_INT_P (inc) |
d29b4b1b HPN |
313 | /* Support increment by number of registers, and by the offset |
314 | of the destination, if it has the form (MEM (PLUS reg | |
315 | offset)). */ | |
316 | || !((REG_P (dest_addr) | |
317 | && REGNO (dest_addr) == REGNO (reg) | |
318 | && INTVAL (inc) == (HOST_WIDE_INT) reg_count * 4) | |
319 | || (GET_CODE (dest_addr) == PLUS | |
320 | && REG_P (XEXP (dest_addr, 0)) | |
321 | && REGNO (XEXP (dest_addr, 0)) == REGNO (reg) | |
991c42ac | 322 | && CONST_INT_P (XEXP (dest_addr, 1)) |
d29b4b1b | 323 | && INTVAL (XEXP (dest_addr, 1)) == INTVAL (inc)))) |
68a81332 | 324 | return false; |
d29b4b1b HPN |
325 | |
326 | i = 2; | |
327 | } | |
328 | else | |
329 | i = 1; | |
330 | ||
c31500c2 HPN |
331 | if (!TARGET_V32) |
332 | { | |
333 | regno_dir = -1; | |
334 | regno = reg_count - 1; | |
335 | } | |
d29b4b1b HPN |
336 | |
337 | if (GET_CODE (elt) != SET | |
991c42ac | 338 | || !REG_P (SET_SRC (elt)) |
d29b4b1b HPN |
339 | || GET_MODE (SET_SRC (elt)) != SImode |
340 | || REGNO (SET_SRC (elt)) != (unsigned int) regno | |
991c42ac | 341 | || !MEM_P (SET_DEST (elt)) |
d29b4b1b | 342 | || GET_MODE (SET_DEST (elt)) != SImode) |
68a81332 | 343 | return false; |
d29b4b1b HPN |
344 | |
345 | if (REG_P (dest_addr)) | |
346 | { | |
347 | dest_base = dest_addr; | |
348 | offset = 0; | |
349 | } | |
350 | else if (GET_CODE (dest_addr) == PLUS | |
351 | && REG_P (XEXP (dest_addr, 0)) | |
991c42ac | 352 | && CONST_INT_P (XEXP (dest_addr, 1))) |
d29b4b1b HPN |
353 | { |
354 | dest_base = XEXP (dest_addr, 0); | |
355 | offset = INTVAL (XEXP (dest_addr, 1)); | |
356 | } | |
357 | else | |
68a81332 | 358 | return false; |
d29b4b1b HPN |
359 | |
360 | for (setno = 1; i < XVECLEN (op, 0); setno++, i++) | |
361 | { | |
362 | rtx elt = XVECEXP (op, 0, i); | |
363 | regno += regno_dir; | |
364 | ||
365 | if (GET_CODE (elt) != SET | |
991c42ac | 366 | || !REG_P (SET_SRC (elt)) |
d29b4b1b HPN |
367 | || GET_MODE (SET_SRC (elt)) != SImode |
368 | || REGNO (SET_SRC (elt)) != (unsigned int) regno | |
991c42ac | 369 | || !MEM_P (SET_DEST (elt)) |
d29b4b1b HPN |
370 | || GET_MODE (SET_DEST (elt)) != SImode |
371 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
372 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_base) | |
991c42ac | 373 | || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt), 0), 1)) |
d29b4b1b | 374 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != setno * 4 + offset) |
68a81332 | 375 | return false; |
d29b4b1b HPN |
376 | } |
377 | ||
68a81332 | 378 | return true; |
d29b4b1b HPN |
379 | } |
380 | ||
71cc389b | 381 | /* The CONDITIONAL_REGISTER_USAGE worker. */ |
0b85d816 HPN |
382 | |
383 | void | |
6640377c | 384 | cris_conditional_register_usage (void) |
0b85d816 HPN |
385 | { |
386 | /* FIXME: This isn't nice. We should be able to use that register for | |
387 | something else if the PIC table isn't needed. */ | |
388 | if (flag_pic) | |
389 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] | |
390 | = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; | |
f60c7155 | 391 | |
c31500c2 HPN |
392 | /* Allow use of ACR (PC in pre-V32) and tweak order. */ |
393 | if (TARGET_V32) | |
394 | { | |
395 | static const int reg_alloc_order_v32[] = REG_ALLOC_ORDER_V32; | |
396 | unsigned int i; | |
397 | ||
398 | fixed_regs[CRIS_ACR_REGNUM] = 0; | |
399 | ||
400 | for (i = 0; | |
401 | i < sizeof (reg_alloc_order_v32)/sizeof (reg_alloc_order_v32[0]); | |
402 | i++) | |
403 | reg_alloc_order[i] = reg_alloc_order_v32[i]; | |
404 | } | |
405 | ||
f60c7155 HPN |
406 | if (TARGET_HAS_MUL_INSNS) |
407 | fixed_regs[CRIS_MOF_REGNUM] = 0; | |
f9968e3e HPN |
408 | |
409 | /* On early versions, we must use the 16-bit condition-code register, | |
410 | which has another name. */ | |
411 | if (cris_cpu_version < 8) | |
412 | reg_names[CRIS_CC0_REGNUM] = "ccr"; | |
0b85d816 HPN |
413 | } |
414 | ||
e3b5732b | 415 | /* Return crtl->uses_pic_offset_table. For use in cris.md, |
0b85d816 HPN |
416 | since some generated files do not include function.h. */ |
417 | ||
418 | int | |
6640377c | 419 | cris_cfun_uses_pic_table (void) |
0b85d816 | 420 | { |
e3b5732b | 421 | return crtl->uses_pic_offset_table; |
0b85d816 HPN |
422 | } |
423 | ||
424 | /* Given an rtx, return the text string corresponding to the CODE of X. | |
425 | Intended for use in the assembly language output section of a | |
426 | define_insn. */ | |
427 | ||
428 | const char * | |
6640377c | 429 | cris_op_str (rtx x) |
0b85d816 HPN |
430 | { |
431 | cris_output_insn_is_bound = 0; | |
432 | switch (GET_CODE (x)) | |
433 | { | |
434 | case PLUS: | |
435 | return "add"; | |
436 | break; | |
437 | ||
438 | case MINUS: | |
439 | return "sub"; | |
440 | break; | |
441 | ||
442 | case MULT: | |
86da66b5 HPN |
443 | /* This function is for retrieving a part of an instruction name for |
444 | an operator, for immediate output. If that ever happens for | |
445 | MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure | |
446 | we notice. */ | |
b6c34129 | 447 | internal_error ("MULT case in cris_op_str"); |
0b85d816 HPN |
448 | break; |
449 | ||
450 | case DIV: | |
451 | return "div"; | |
452 | break; | |
453 | ||
454 | case AND: | |
455 | return "and"; | |
456 | break; | |
457 | ||
458 | case IOR: | |
459 | return "or"; | |
460 | break; | |
461 | ||
462 | case XOR: | |
463 | return "xor"; | |
464 | break; | |
465 | ||
466 | case NOT: | |
467 | return "not"; | |
468 | break; | |
469 | ||
470 | case ASHIFT: | |
471 | return "lsl"; | |
472 | break; | |
473 | ||
474 | case LSHIFTRT: | |
475 | return "lsr"; | |
476 | break; | |
477 | ||
478 | case ASHIFTRT: | |
479 | return "asr"; | |
480 | break; | |
481 | ||
482 | case UMIN: | |
9c514326 | 483 | /* Used to control the sign/zero-extend character for the 'E' modifier. |
0b85d816 HPN |
484 | BOUND has none. */ |
485 | cris_output_insn_is_bound = 1; | |
486 | return "bound"; | |
487 | break; | |
488 | ||
489 | default: | |
490 | return "Unknown operator"; | |
491 | break; | |
492 | } | |
493 | } | |
494 | ||
3d556836 HPN |
495 | /* Emit an error message when we're in an asm, and a fatal error for |
496 | "normal" insns. Formatted output isn't easily implemented, since we | |
497 | use output_operand_lossage to output the actual message and handle the | |
498 | categorization of the error. */ | |
499 | ||
500 | static void | |
6640377c | 501 | cris_operand_lossage (const char *msgid, rtx op) |
3d556836 HPN |
502 | { |
503 | debug_rtx (op); | |
a52453cc | 504 | output_operand_lossage ("%s", msgid); |
3d556836 HPN |
505 | } |
506 | ||
0b85d816 HPN |
507 | /* Print an index part of an address to file. */ |
508 | ||
509 | static void | |
6640377c | 510 | cris_print_index (rtx index, FILE *file) |
0b85d816 | 511 | { |
0b85d816 HPN |
512 | /* Make the index "additive" unless we'll output a negative number, in |
513 | which case the sign character is free (as in free beer). */ | |
991c42ac | 514 | if (!CONST_INT_P (index) || INTVAL (index) >= 0) |
0b85d816 HPN |
515 | putc ('+', file); |
516 | ||
517 | if (REG_P (index)) | |
518 | fprintf (file, "$%s.b", reg_names[REGNO (index)]); | |
519 | else if (CONSTANT_P (index)) | |
520 | cris_output_addr_const (file, index); | |
521 | else if (GET_CODE (index) == MULT) | |
522 | { | |
523 | fprintf (file, "$%s.", | |
524 | reg_names[REGNO (XEXP (index, 0))]); | |
525 | ||
526 | putc (INTVAL (XEXP (index, 1)) == 2 ? 'w' : 'd', file); | |
527 | } | |
9e19a50c | 528 | else if (GET_CODE (index) == SIGN_EXTEND && MEM_P (XEXP (index, 0))) |
0b85d816 | 529 | { |
9e19a50c | 530 | rtx inner = XEXP (index, 0); |
0b85d816 HPN |
531 | rtx inner_inner = XEXP (inner, 0); |
532 | ||
533 | if (GET_CODE (inner_inner) == POST_INC) | |
534 | { | |
535 | fprintf (file, "[$%s+].", | |
536 | reg_names[REGNO (XEXP (inner_inner, 0))]); | |
537 | putc (GET_MODE (inner) == HImode ? 'w' : 'b', file); | |
538 | } | |
539 | else | |
540 | { | |
541 | fprintf (file, "[$%s].", reg_names[REGNO (inner_inner)]); | |
542 | ||
543 | putc (GET_MODE (inner) == HImode ? 'w' : 'b', file); | |
544 | } | |
545 | } | |
991c42ac | 546 | else if (MEM_P (index)) |
0b85d816 | 547 | { |
9e19a50c | 548 | rtx inner = XEXP (index, 0); |
0b85d816 HPN |
549 | if (GET_CODE (inner) == POST_INC) |
550 | fprintf (file, "[$%s+].d", reg_names[REGNO (XEXP (inner, 0))]); | |
551 | else | |
552 | fprintf (file, "[$%s].d", reg_names[REGNO (inner)]); | |
553 | } | |
554 | else | |
117b0c0a | 555 | cris_operand_lossage ("unexpected index-type in cris_print_index", |
3d556836 | 556 | index); |
0b85d816 HPN |
557 | } |
558 | ||
559 | /* Print a base rtx of an address to file. */ | |
560 | ||
561 | static void | |
6640377c | 562 | cris_print_base (rtx base, FILE *file) |
0b85d816 HPN |
563 | { |
564 | if (REG_P (base)) | |
565 | fprintf (file, "$%s", reg_names[REGNO (base)]); | |
566 | else if (GET_CODE (base) == POST_INC) | |
c31500c2 HPN |
567 | { |
568 | gcc_assert (REGNO (XEXP (base, 0)) != CRIS_ACR_REGNUM); | |
569 | fprintf (file, "$%s+", reg_names[REGNO (XEXP (base, 0))]); | |
570 | } | |
0b85d816 | 571 | else |
117b0c0a | 572 | cris_operand_lossage ("unexpected base-type in cris_print_base", |
3d556836 | 573 | base); |
0b85d816 HPN |
574 | } |
575 | ||
576 | /* Usable as a guard in expressions. */ | |
577 | ||
578 | int | |
6640377c | 579 | cris_fatal (char *arg) |
0b85d816 HPN |
580 | { |
581 | internal_error (arg); | |
582 | ||
583 | /* We'll never get here; this is just to appease compilers. */ | |
584 | return 0; | |
585 | } | |
586 | ||
04539954 HPN |
587 | /* Return nonzero if REGNO is an ordinary register that *needs* to be |
588 | saved together with other registers, possibly by a MOVEM instruction, | |
589 | or is saved for target-independent reasons. There may be | |
590 | target-dependent reasons to save the register anyway; this is just a | |
591 | wrapper for a complicated conditional. */ | |
592 | ||
593 | static int | |
594 | cris_reg_saved_in_regsave_area (unsigned int regno, bool got_really_used) | |
595 | { | |
596 | return | |
6fb5fa3c | 597 | (((df_regs_ever_live_p (regno) |
04539954 HPN |
598 | && !call_used_regs[regno]) |
599 | || (regno == PIC_OFFSET_TABLE_REGNUM | |
600 | && (got_really_used | |
601 | /* It is saved anyway, if there would be a gap. */ | |
602 | || (flag_pic | |
6fb5fa3c | 603 | && df_regs_ever_live_p (regno + 1) |
04539954 HPN |
604 | && !call_used_regs[regno + 1])))) |
605 | && (regno != FRAME_POINTER_REGNUM || !frame_pointer_needed) | |
606 | && regno != CRIS_SRP_REGNUM) | |
e3b5732b | 607 | || (crtl->calls_eh_return |
04539954 HPN |
608 | && (regno == EH_RETURN_DATA_REGNO (0) |
609 | || regno == EH_RETURN_DATA_REGNO (1) | |
610 | || regno == EH_RETURN_DATA_REGNO (2) | |
611 | || regno == EH_RETURN_DATA_REGNO (3))); | |
612 | } | |
613 | ||
0b85d816 HPN |
614 | /* Return nonzero if there are regs mentioned in the insn that are not all |
615 | in the call_used regs. This is part of the decision whether an insn | |
616 | can be put in the epilogue. */ | |
617 | ||
618 | static int | |
6640377c | 619 | saved_regs_mentioned (rtx x) |
0b85d816 HPN |
620 | { |
621 | int i; | |
622 | const char *fmt; | |
623 | RTX_CODE code; | |
624 | ||
e5837c07 | 625 | /* Mainly stolen from refers_to_regno_p in rtlanal.c. */ |
0b85d816 HPN |
626 | |
627 | code = GET_CODE (x); | |
628 | ||
629 | switch (code) | |
630 | { | |
631 | case REG: | |
632 | i = REGNO (x); | |
633 | return !call_used_regs[i]; | |
634 | ||
635 | case SUBREG: | |
636 | /* If this is a SUBREG of a hard reg, we can see exactly which | |
637 | registers are being modified. Otherwise, handle normally. */ | |
638 | i = REGNO (SUBREG_REG (x)); | |
639 | return !call_used_regs[i]; | |
640 | ||
641 | default: | |
642 | ; | |
643 | } | |
644 | ||
645 | fmt = GET_RTX_FORMAT (code); | |
646 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
647 | { | |
648 | if (fmt[i] == 'e') | |
649 | { | |
650 | if (saved_regs_mentioned (XEXP (x, i))) | |
651 | return 1; | |
652 | } | |
653 | else if (fmt[i] == 'E') | |
654 | { | |
655 | int j; | |
656 | for (j = XVECLEN (x, i) - 1; j >=0; j--) | |
657 | if (saved_regs_mentioned (XEXP (x, i))) | |
658 | return 1; | |
659 | } | |
660 | } | |
661 | ||
662 | return 0; | |
663 | } | |
664 | ||
0b85d816 HPN |
665 | /* The PRINT_OPERAND worker. */ |
666 | ||
667 | void | |
6640377c | 668 | cris_print_operand (FILE *file, rtx x, int code) |
0b85d816 HPN |
669 | { |
670 | rtx operand = x; | |
671 | ||
672 | /* Size-strings corresponding to MULT expressions. */ | |
0139adca | 673 | static const char *const mults[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" }; |
0b85d816 HPN |
674 | |
675 | /* New code entries should just be added to the switch below. If | |
676 | handling is finished, just return. If handling was just a | |
677 | modification of the operand, the modified operand should be put in | |
678 | "operand", and then do a break to let default handling | |
679 | (zero-modifier) output the operand. */ | |
680 | ||
681 | switch (code) | |
682 | { | |
683 | case 'b': | |
59b9a953 | 684 | /* Print the unsigned supplied integer as if it were signed |
0b85d816 | 685 | and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */ |
991c42ac | 686 | if (!CONST_INT_P (x) |
0b85d816 | 687 | || ! CONST_OK_FOR_LETTER_P (INTVAL (x), 'O')) |
3d556836 | 688 | LOSE_AND_RETURN ("invalid operand for 'b' modifier", x); |
69487202 KG |
689 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
690 | INTVAL (x)| (INTVAL (x) <= 255 ? ~255 : ~65535)); | |
0b85d816 HPN |
691 | return; |
692 | ||
693 | case 'x': | |
694 | /* Print assembler code for operator. */ | |
695 | fprintf (file, "%s", cris_op_str (operand)); | |
696 | return; | |
697 | ||
04539954 HPN |
698 | case 'o': |
699 | { | |
700 | /* A movem modifier working on a parallel; output the register | |
701 | name. */ | |
702 | int regno; | |
703 | ||
704 | if (GET_CODE (x) != PARALLEL) | |
705 | LOSE_AND_RETURN ("invalid operand for 'o' modifier", x); | |
706 | ||
707 | /* The second item can be (set reg (plus reg const)) to denote a | |
708 | postincrement. */ | |
709 | regno | |
710 | = (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS | |
711 | ? XVECLEN (x, 0) - 2 | |
712 | : XVECLEN (x, 0) - 1); | |
713 | ||
714 | fprintf (file, "$%s", reg_names [regno]); | |
715 | } | |
716 | return; | |
717 | ||
718 | case 'O': | |
719 | { | |
720 | /* A similar movem modifier; output the memory operand. */ | |
721 | rtx addr; | |
722 | ||
723 | if (GET_CODE (x) != PARALLEL) | |
724 | LOSE_AND_RETURN ("invalid operand for 'O' modifier", x); | |
725 | ||
726 | /* The lowest mem operand is in the first item, but perhaps it | |
727 | needs to be output as postincremented. */ | |
991c42ac | 728 | addr = MEM_P (SET_SRC (XVECEXP (x, 0, 0))) |
04539954 HPN |
729 | ? XEXP (SET_SRC (XVECEXP (x, 0, 0)), 0) |
730 | : XEXP (SET_DEST (XVECEXP (x, 0, 0)), 0); | |
731 | ||
d29b4b1b HPN |
732 | /* The second item can be a (set reg (plus reg const)) to denote |
733 | a modification. */ | |
04539954 | 734 | if (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS) |
d29b4b1b HPN |
735 | { |
736 | /* It's a post-increment, if the address is a naked (reg). */ | |
737 | if (REG_P (addr)) | |
738 | addr = gen_rtx_POST_INC (SImode, addr); | |
739 | else | |
740 | { | |
741 | /* Otherwise, it's a side-effect; RN=RN+M. */ | |
742 | fprintf (file, "[$%s=$%s%s%d]", | |
743 | reg_names [REGNO (SET_DEST (XVECEXP (x, 0, 1)))], | |
744 | reg_names [REGNO (XEXP (addr, 0))], | |
745 | INTVAL (XEXP (addr, 1)) < 0 ? "" : "+", | |
746 | (int) INTVAL (XEXP (addr, 1))); | |
747 | return; | |
748 | } | |
749 | } | |
04539954 HPN |
750 | output_address (addr); |
751 | } | |
752 | return; | |
753 | ||
0b85d816 HPN |
754 | case 'p': |
755 | /* Adjust a power of two to its log2. */ | |
991c42ac | 756 | if (!CONST_INT_P (x) || exact_log2 (INTVAL (x)) < 0 ) |
3d556836 | 757 | LOSE_AND_RETURN ("invalid operand for 'p' modifier", x); |
0b85d816 HPN |
758 | fprintf (file, "%d", exact_log2 (INTVAL (x))); |
759 | return; | |
760 | ||
761 | case 's': | |
762 | /* For an integer, print 'b' or 'w' if <= 255 or <= 65535 | |
763 | respectively. This modifier also terminates the inhibiting | |
764 | effects of the 'x' modifier. */ | |
765 | cris_output_insn_is_bound = 0; | |
991c42ac | 766 | if (GET_MODE (x) == VOIDmode && CONST_INT_P (x)) |
0b85d816 HPN |
767 | { |
768 | if (INTVAL (x) >= 0) | |
769 | { | |
770 | if (INTVAL (x) <= 255) | |
771 | putc ('b', file); | |
772 | else if (INTVAL (x) <= 65535) | |
773 | putc ('w', file); | |
774 | else | |
775 | putc ('d', file); | |
776 | } | |
777 | else | |
778 | putc ('d', file); | |
779 | return; | |
780 | } | |
781 | ||
782 | /* For a non-integer, print the size of the operand. */ | |
783 | putc ((GET_MODE (x) == SImode || GET_MODE (x) == SFmode) | |
784 | ? 'd' : GET_MODE (x) == HImode ? 'w' | |
785 | : GET_MODE (x) == QImode ? 'b' | |
786 | /* If none of the above, emit an erroneous size letter. */ | |
787 | : 'X', | |
788 | file); | |
789 | return; | |
790 | ||
791 | case 'z': | |
792 | /* Const_int: print b for -127 <= x <= 255, | |
b6c34129 | 793 | w for -32768 <= x <= 65535, else die. */ |
991c42ac | 794 | if (!CONST_INT_P (x) |
0b85d816 | 795 | || INTVAL (x) < -32768 || INTVAL (x) > 65535) |
3d556836 | 796 | LOSE_AND_RETURN ("invalid operand for 'z' modifier", x); |
0b85d816 HPN |
797 | putc (INTVAL (x) >= -128 && INTVAL (x) <= 255 ? 'b' : 'w', file); |
798 | return; | |
799 | ||
c31500c2 HPN |
800 | case 'Z': |
801 | /* If this is a GOT-symbol, print the size-letter corresponding to | |
802 | -fpic/-fPIC. For everything else, print "d". */ | |
803 | putc ((flag_pic == 1 | |
804 | && GET_CODE (x) == CONST | |
805 | && GET_CODE (XEXP (x, 0)) == UNSPEC | |
806 | && XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREAD) | |
807 | ? 'w' : 'd', file); | |
808 | return; | |
809 | ||
0b85d816 HPN |
810 | case '#': |
811 | /* Output a 'nop' if there's nothing for the delay slot. | |
812 | This method stolen from the sparc files. */ | |
813 | if (dbr_sequence_length () == 0) | |
814 | fputs ("\n\tnop", file); | |
815 | return; | |
816 | ||
86da66b5 HPN |
817 | case '!': |
818 | /* Output directive for alignment padded with "nop" insns. | |
819 | Optimizing for size, it's plain 4-byte alignment, otherwise we | |
820 | align the section to a cache-line (32 bytes) and skip at max 2 | |
821 | bytes, i.e. we skip if it's the last insn on a cache-line. The | |
822 | latter is faster by a small amount (for two test-programs 99.6% | |
823 | and 99.9%) and larger by a small amount (ditto 100.1% and | |
824 | 100.2%). This is supposed to be the simplest yet performance- | |
825 | wise least intrusive way to make sure the immediately following | |
826 | (supposed) muls/mulu insn isn't located at the end of a | |
827 | cache-line. */ | |
828 | if (TARGET_MUL_BUG) | |
829 | fputs (optimize_size | |
830 | ? ".p2alignw 2,0x050f\n\t" | |
831 | : ".p2alignw 5,0x050f,2\n\t", file); | |
832 | return; | |
833 | ||
c00fc5cf HPN |
834 | case ':': |
835 | /* The PIC register. */ | |
836 | if (! flag_pic) | |
837 | internal_error ("invalid use of ':' modifier"); | |
838 | fprintf (file, "$%s", reg_names [PIC_OFFSET_TABLE_REGNUM]); | |
839 | return; | |
840 | ||
0b85d816 HPN |
841 | case 'H': |
842 | /* Print high (most significant) part of something. */ | |
843 | switch (GET_CODE (operand)) | |
844 | { | |
845 | case CONST_INT: | |
2239ced8 HPN |
846 | /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode) |
847 | value is kept here, and so may be other than 0 or -1. */ | |
848 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, | |
849 | INTVAL (operand_subword (operand, 1, 0, DImode))); | |
0b85d816 HPN |
850 | return; |
851 | ||
852 | case CONST_DOUBLE: | |
853 | /* High part of a long long constant. */ | |
854 | if (GET_MODE (operand) == VOIDmode) | |
855 | { | |
69487202 | 856 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_HIGH (x)); |
0b85d816 HPN |
857 | return; |
858 | } | |
859 | else | |
3d556836 | 860 | LOSE_AND_RETURN ("invalid operand for 'H' modifier", x); |
0b85d816 HPN |
861 | |
862 | case REG: | |
863 | /* Print reg + 1. Check that there's not an attempt to print | |
c31500c2 HPN |
864 | high-parts of registers like stack-pointer or higher, except |
865 | for SRP (where the "high part" is MOF). */ | |
866 | if (REGNO (operand) > STACK_POINTER_REGNUM - 2 | |
867 | && (REGNO (operand) != CRIS_SRP_REGNUM | |
868 | || CRIS_SRP_REGNUM + 1 != CRIS_MOF_REGNUM | |
869 | || fixed_regs[CRIS_MOF_REGNUM] != 0)) | |
3d556836 | 870 | LOSE_AND_RETURN ("bad register", operand); |
0b85d816 HPN |
871 | fprintf (file, "$%s", reg_names[REGNO (operand) + 1]); |
872 | return; | |
873 | ||
874 | case MEM: | |
875 | /* Adjust memory address to high part. */ | |
876 | { | |
877 | rtx adj_mem = operand; | |
878 | int size | |
879 | = GET_MODE_BITSIZE (GET_MODE (operand)) / BITS_PER_UNIT; | |
880 | ||
881 | /* Adjust so we can use two SImode in DImode. | |
882 | Calling adj_offsettable_operand will make sure it is an | |
883 | offsettable address. Don't do this for a postincrement | |
884 | though; it should remain as it was. */ | |
885 | if (GET_CODE (XEXP (adj_mem, 0)) != POST_INC) | |
886 | adj_mem | |
887 | = adjust_address (adj_mem, GET_MODE (adj_mem), size / 2); | |
888 | ||
889 | output_address (XEXP (adj_mem, 0)); | |
890 | return; | |
891 | } | |
892 | ||
893 | default: | |
3d556836 | 894 | LOSE_AND_RETURN ("invalid operand for 'H' modifier", x); |
0b85d816 HPN |
895 | } |
896 | ||
897 | case 'L': | |
898 | /* Strip the MEM expression. */ | |
899 | operand = XEXP (operand, 0); | |
900 | break; | |
901 | ||
902 | case 'e': | |
9c514326 | 903 | /* Like 'E', but ignore state set by 'x'. FIXME: Use code |
3abcb3a7 HPN |
904 | iterators and attributes in cris.md to avoid the need for %x |
905 | and %E (and %e) and state passed between those modifiers. */ | |
9c514326 HPN |
906 | cris_output_insn_is_bound = 0; |
907 | /* FALL THROUGH. */ | |
908 | case 'E': | |
0b85d816 HPN |
909 | /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless |
910 | cris_output_insn_is_bound is nonzero. */ | |
911 | if (GET_CODE (operand) != SIGN_EXTEND | |
912 | && GET_CODE (operand) != ZERO_EXTEND | |
991c42ac | 913 | && !CONST_INT_P (operand)) |
3d556836 | 914 | LOSE_AND_RETURN ("invalid operand for 'e' modifier", x); |
0b85d816 HPN |
915 | |
916 | if (cris_output_insn_is_bound) | |
917 | { | |
918 | cris_output_insn_is_bound = 0; | |
919 | return; | |
920 | } | |
921 | ||
922 | putc (GET_CODE (operand) == SIGN_EXTEND | |
991c42ac | 923 | || (CONST_INT_P (operand) && INTVAL (operand) < 0) |
0b85d816 HPN |
924 | ? 's' : 'u', file); |
925 | return; | |
926 | ||
927 | case 'm': | |
928 | /* Print the size letter of the inner element. We can do it by | |
929 | calling ourselves with the 's' modifier. */ | |
930 | if (GET_CODE (operand) != SIGN_EXTEND && GET_CODE (operand) != ZERO_EXTEND) | |
3d556836 | 931 | LOSE_AND_RETURN ("invalid operand for 'm' modifier", x); |
0b85d816 HPN |
932 | cris_print_operand (file, XEXP (operand, 0), 's'); |
933 | return; | |
934 | ||
935 | case 'M': | |
936 | /* Print the least significant part of operand. */ | |
937 | if (GET_CODE (operand) == CONST_DOUBLE) | |
938 | { | |
69487202 | 939 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_LOW (x)); |
0b85d816 HPN |
940 | return; |
941 | } | |
991c42ac | 942 | else if (HOST_BITS_PER_WIDE_INT > 32 && CONST_INT_P (operand)) |
60ffa0e5 | 943 | { |
69487202 | 944 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
4a085d2e | 945 | INTVAL (x) & ((unsigned int) 0x7fffffff * 2 + 1)); |
60ffa0e5 RH |
946 | return; |
947 | } | |
948 | /* Otherwise the least significant part equals the normal part, | |
949 | so handle it normally. */ | |
0b85d816 HPN |
950 | break; |
951 | ||
952 | case 'A': | |
953 | /* When emitting an add for the high part of a DImode constant, we | |
954 | want to use addq for 0 and adds.w for -1. */ | |
991c42ac | 955 | if (!CONST_INT_P (operand)) |
3d556836 | 956 | LOSE_AND_RETURN ("invalid operand for 'A' modifier", x); |
0b85d816 HPN |
957 | fprintf (file, INTVAL (operand) < 0 ? "adds.w" : "addq"); |
958 | return; | |
959 | ||
f60c7155 | 960 | case 'd': |
c00fc5cf HPN |
961 | /* If this is a GOT symbol, force it to be emitted as :GOT and |
962 | :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16). | |
963 | Avoid making this too much of a special case. */ | |
964 | if (flag_pic == 1 && CONSTANT_P (operand)) | |
f60c7155 | 965 | { |
c00fc5cf HPN |
966 | int flag_pic_save = flag_pic; |
967 | ||
968 | flag_pic = 2; | |
f60c7155 | 969 | cris_output_addr_const (file, operand); |
c00fc5cf | 970 | flag_pic = flag_pic_save; |
f60c7155 HPN |
971 | return; |
972 | } | |
973 | break; | |
974 | ||
0b85d816 HPN |
975 | case 'D': |
976 | /* When emitting an sub for the high part of a DImode constant, we | |
977 | want to use subq for 0 and subs.w for -1. */ | |
991c42ac | 978 | if (!CONST_INT_P (operand)) |
3d556836 | 979 | LOSE_AND_RETURN ("invalid operand for 'D' modifier", x); |
0b85d816 HPN |
980 | fprintf (file, INTVAL (operand) < 0 ? "subs.w" : "subq"); |
981 | return; | |
982 | ||
983 | case 'S': | |
984 | /* Print the operand as the index-part of an address. | |
985 | Easiest way out is to use cris_print_index. */ | |
986 | cris_print_index (operand, file); | |
987 | return; | |
988 | ||
989 | case 'T': | |
990 | /* Print the size letter for an operand to a MULT, which must be a | |
991 | const_int with a suitable value. */ | |
991c42ac | 992 | if (!CONST_INT_P (operand) || INTVAL (operand) > 4) |
3d556836 | 993 | LOSE_AND_RETURN ("invalid operand for 'T' modifier", x); |
0b85d816 HPN |
994 | fprintf (file, "%s", mults[INTVAL (operand)]); |
995 | return; | |
996 | ||
c31500c2 HPN |
997 | case 'u': |
998 | /* Print "u.w" if a GOT symbol and flag_pic == 1, else ".d". */ | |
999 | if (flag_pic == 1 | |
1000 | && GET_CODE (operand) == CONST | |
1001 | && GET_CODE (XEXP (operand, 0)) == UNSPEC | |
1002 | && XINT (XEXP (operand, 0), 1) == CRIS_UNSPEC_GOTREAD) | |
1003 | fprintf (file, "u.w"); | |
1004 | else | |
1005 | fprintf (file, ".d"); | |
1006 | return; | |
1007 | ||
0b85d816 | 1008 | case 0: |
e5837c07 | 1009 | /* No code, print as usual. */ |
0b85d816 HPN |
1010 | break; |
1011 | ||
1012 | default: | |
3d556836 | 1013 | LOSE_AND_RETURN ("invalid operand modifier letter", x); |
0b85d816 HPN |
1014 | } |
1015 | ||
e5837c07 | 1016 | /* Print an operand as without a modifier letter. */ |
0b85d816 HPN |
1017 | switch (GET_CODE (operand)) |
1018 | { | |
1019 | case REG: | |
f60c7155 HPN |
1020 | if (REGNO (operand) > 15 |
1021 | && REGNO (operand) != CRIS_MOF_REGNUM | |
f9968e3e HPN |
1022 | && REGNO (operand) != CRIS_SRP_REGNUM |
1023 | && REGNO (operand) != CRIS_CC0_REGNUM) | |
c725bd79 | 1024 | internal_error ("internal error: bad register: %d", REGNO (operand)); |
0b85d816 HPN |
1025 | fprintf (file, "$%s", reg_names[REGNO (operand)]); |
1026 | return; | |
1027 | ||
1028 | case MEM: | |
1029 | output_address (XEXP (operand, 0)); | |
1030 | return; | |
1031 | ||
1032 | case CONST_DOUBLE: | |
1033 | if (GET_MODE (operand) == VOIDmode) | |
1034 | /* A long long constant. */ | |
1035 | output_addr_const (file, operand); | |
1036 | else | |
1037 | { | |
1038 | /* Only single precision is allowed as plain operands the | |
1039 | moment. FIXME: REAL_VALUE_FROM_CONST_DOUBLE isn't | |
1040 | documented. */ | |
1041 | REAL_VALUE_TYPE r; | |
1042 | long l; | |
1043 | ||
1044 | /* FIXME: Perhaps check overflow of the "single". */ | |
1045 | REAL_VALUE_FROM_CONST_DOUBLE (r, operand); | |
1046 | REAL_VALUE_TO_TARGET_SINGLE (r, l); | |
1047 | ||
1048 | fprintf (file, "0x%lx", l); | |
1049 | } | |
1050 | return; | |
1051 | ||
1052 | case UNSPEC: | |
0b85d816 | 1053 | /* Fall through. */ |
0b85d816 HPN |
1054 | case CONST: |
1055 | cris_output_addr_const (file, operand); | |
1056 | return; | |
1057 | ||
1058 | case MULT: | |
1059 | case ASHIFT: | |
1060 | { | |
1061 | /* For a (MULT (reg X) const_int) we output "rX.S". */ | |
991c42ac | 1062 | int i = CONST_INT_P (XEXP (operand, 1)) |
0b85d816 | 1063 | ? INTVAL (XEXP (operand, 1)) : INTVAL (XEXP (operand, 0)); |
991c42ac | 1064 | rtx reg = CONST_INT_P (XEXP (operand, 1)) |
0b85d816 HPN |
1065 | ? XEXP (operand, 0) : XEXP (operand, 1); |
1066 | ||
991c42ac JBG |
1067 | if (!REG_P (reg) |
1068 | || (!CONST_INT_P (XEXP (operand, 0)) | |
1069 | && !CONST_INT_P (XEXP (operand, 1)))) | |
3d556836 | 1070 | LOSE_AND_RETURN ("unexpected multiplicative operand", x); |
0b85d816 HPN |
1071 | |
1072 | cris_print_base (reg, file); | |
1073 | fprintf (file, ".%c", | |
1074 | i == 0 || (i == 1 && GET_CODE (operand) == MULT) ? 'b' | |
1075 | : i == 4 ? 'd' | |
1076 | : (i == 2 && GET_CODE (operand) == MULT) || i == 1 ? 'w' | |
1077 | : 'd'); | |
1078 | return; | |
1079 | } | |
1080 | ||
1081 | default: | |
1082 | /* No need to handle all strange variants, let output_addr_const | |
1083 | do it for us. */ | |
1084 | if (CONSTANT_P (operand)) | |
1085 | { | |
1086 | cris_output_addr_const (file, operand); | |
1087 | return; | |
1088 | } | |
1089 | ||
3d556836 | 1090 | LOSE_AND_RETURN ("unexpected operand", x); |
0b85d816 HPN |
1091 | } |
1092 | } | |
1093 | ||
1094 | /* The PRINT_OPERAND_ADDRESS worker. */ | |
1095 | ||
1096 | void | |
6640377c | 1097 | cris_print_operand_address (FILE *file, rtx x) |
0b85d816 HPN |
1098 | { |
1099 | /* All these were inside MEM:s so output indirection characters. */ | |
1100 | putc ('[', file); | |
1101 | ||
1102 | if (CONSTANT_ADDRESS_P (x)) | |
1103 | cris_output_addr_const (file, x); | |
1104 | else if (BASE_OR_AUTOINCR_P (x)) | |
1105 | cris_print_base (x, file); | |
1106 | else if (GET_CODE (x) == PLUS) | |
1107 | { | |
1108 | rtx x1, x2; | |
1109 | ||
1110 | x1 = XEXP (x, 0); | |
1111 | x2 = XEXP (x, 1); | |
1112 | if (BASE_P (x1)) | |
1113 | { | |
1114 | cris_print_base (x1, file); | |
1115 | cris_print_index (x2, file); | |
1116 | } | |
1117 | else if (BASE_P (x2)) | |
1118 | { | |
1119 | cris_print_base (x2, file); | |
1120 | cris_print_index (x1, file); | |
1121 | } | |
1122 | else | |
3d556836 | 1123 | LOSE_AND_RETURN ("unrecognized address", x); |
0b85d816 | 1124 | } |
991c42ac | 1125 | else if (MEM_P (x)) |
0b85d816 HPN |
1126 | { |
1127 | /* A DIP. Output more indirection characters. */ | |
1128 | putc ('[', file); | |
1129 | cris_print_base (XEXP (x, 0), file); | |
1130 | putc (']', file); | |
1131 | } | |
1132 | else | |
3d556836 | 1133 | LOSE_AND_RETURN ("unrecognized address", x); |
0b85d816 HPN |
1134 | |
1135 | putc (']', file); | |
1136 | } | |
1137 | ||
1138 | /* The RETURN_ADDR_RTX worker. | |
1139 | We mark that the return address is used, either by EH or | |
1140 | __builtin_return_address, for use by the function prologue and | |
1141 | epilogue. FIXME: This isn't optimal; we just use the mark in the | |
1142 | prologue and epilogue to say that the return address is to be stored | |
1143 | in the stack frame. We could return SRP for leaf-functions and use the | |
1144 | initial-value machinery. */ | |
1145 | ||
1146 | rtx | |
6640377c | 1147 | cris_return_addr_rtx (int count, rtx frameaddr ATTRIBUTE_UNUSED) |
0b85d816 HPN |
1148 | { |
1149 | cfun->machine->needs_return_address_on_stack = 1; | |
1150 | ||
1151 | /* The return-address is stored just above the saved frame-pointer (if | |
1152 | present). Apparently we can't eliminate from the frame-pointer in | |
1153 | that direction, so use the incoming args (maybe pretended) pointer. */ | |
1154 | return count == 0 | |
1155 | ? gen_rtx_MEM (Pmode, plus_constant (virtual_incoming_args_rtx, -4)) | |
1156 | : NULL_RTX; | |
1157 | } | |
1158 | ||
b2416742 HPN |
1159 | /* Accessor used in cris.md:return because cfun->machine isn't available |
1160 | there. */ | |
1161 | ||
04539954 | 1162 | bool |
d29b4b1b | 1163 | cris_return_address_on_stack (void) |
b2416742 | 1164 | { |
6fb5fa3c | 1165 | return df_regs_ever_live_p (CRIS_SRP_REGNUM) |
04539954 HPN |
1166 | || cfun->machine->needs_return_address_on_stack; |
1167 | } | |
1168 | ||
1169 | /* Accessor used in cris.md:return because cfun->machine isn't available | |
1170 | there. */ | |
1171 | ||
1172 | bool | |
d29b4b1b | 1173 | cris_return_address_on_stack_for_return (void) |
04539954 HPN |
1174 | { |
1175 | return cfun->machine->return_type == CRIS_RETINSN_RET ? false | |
1176 | : cris_return_address_on_stack (); | |
b2416742 HPN |
1177 | } |
1178 | ||
0b85d816 HPN |
1179 | /* This used to be the INITIAL_FRAME_POINTER_OFFSET worker; now only |
1180 | handles FP -> SP elimination offset. */ | |
1181 | ||
1182 | static int | |
6640377c | 1183 | cris_initial_frame_pointer_offset (void) |
0b85d816 HPN |
1184 | { |
1185 | int regno; | |
1186 | ||
f710504c | 1187 | /* Initial offset is 0 if we don't have a frame pointer. */ |
0b85d816 | 1188 | int offs = 0; |
c00fc5cf HPN |
1189 | bool got_really_used = false; |
1190 | ||
e3b5732b | 1191 | if (crtl->uses_pic_offset_table) |
c00fc5cf HPN |
1192 | { |
1193 | push_topmost_sequence (); | |
1194 | got_really_used | |
1195 | = reg_used_between_p (pic_offset_table_rtx, get_insns (), | |
1196 | NULL_RTX); | |
1197 | pop_topmost_sequence (); | |
1198 | } | |
0b85d816 HPN |
1199 | |
1200 | /* And 4 for each register pushed. */ | |
1201 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
04539954 | 1202 | if (cris_reg_saved_in_regsave_area (regno, got_really_used)) |
0b85d816 HPN |
1203 | offs += 4; |
1204 | ||
1205 | /* And then, last, we add the locals allocated. */ | |
1206 | offs += get_frame_size (); | |
1207 | ||
1208 | /* And more; the accumulated args size. */ | |
38173d38 | 1209 | offs += crtl->outgoing_args_size; |
0b85d816 HPN |
1210 | |
1211 | /* Then round it off, in case we use aligned stack. */ | |
1212 | if (TARGET_STACK_ALIGN) | |
1213 | offs = TARGET_ALIGN_BY_32 ? (offs + 3) & ~3 : (offs + 1) & ~1; | |
1214 | ||
1215 | return offs; | |
1216 | } | |
1217 | ||
1218 | /* The INITIAL_ELIMINATION_OFFSET worker. | |
1219 | Calculate the difference between imaginary registers such as frame | |
1220 | pointer and the stack pointer. Used to eliminate the frame pointer | |
1221 | and imaginary arg pointer. */ | |
1222 | ||
1223 | int | |
6640377c | 1224 | cris_initial_elimination_offset (int fromreg, int toreg) |
0b85d816 HPN |
1225 | { |
1226 | int fp_sp_offset | |
1227 | = cris_initial_frame_pointer_offset (); | |
1228 | ||
1229 | /* We should be able to use regs_ever_live and related prologue | |
1230 | information here, or alpha should not as well. */ | |
04539954 | 1231 | bool return_address_on_stack = cris_return_address_on_stack (); |
0b85d816 | 1232 | |
59b9a953 | 1233 | /* Here we act as if the frame-pointer were needed. */ |
0b85d816 HPN |
1234 | int ap_fp_offset = 4 + (return_address_on_stack ? 4 : 0); |
1235 | ||
1236 | if (fromreg == ARG_POINTER_REGNUM | |
1237 | && toreg == FRAME_POINTER_REGNUM) | |
1238 | return ap_fp_offset; | |
1239 | ||
1240 | /* Between the frame pointer and the stack are only "normal" stack | |
1241 | variables and saved registers. */ | |
1242 | if (fromreg == FRAME_POINTER_REGNUM | |
1243 | && toreg == STACK_POINTER_REGNUM) | |
1244 | return fp_sp_offset; | |
1245 | ||
e5837c07 | 1246 | /* We need to balance out the frame pointer here. */ |
0b85d816 HPN |
1247 | if (fromreg == ARG_POINTER_REGNUM |
1248 | && toreg == STACK_POINTER_REGNUM) | |
1249 | return ap_fp_offset + fp_sp_offset - 4; | |
1250 | ||
b6c34129 | 1251 | gcc_unreachable (); |
0b85d816 HPN |
1252 | } |
1253 | ||
15883505 HPN |
1254 | /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */ |
1255 | ||
1256 | bool | |
1257 | cris_reload_address_legitimized (rtx x, | |
1258 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
1259 | int opnum ATTRIBUTE_UNUSED, | |
1260 | int itype, | |
1261 | int ind_levels ATTRIBUTE_UNUSED) | |
1262 | { | |
1263 | enum reload_type type = itype; | |
1264 | rtx op0, op1; | |
1265 | rtx *op0p; | |
1266 | rtx *op1p; | |
1267 | ||
1268 | if (GET_CODE (x) != PLUS) | |
1269 | return false; | |
1270 | ||
c31500c2 HPN |
1271 | if (TARGET_V32) |
1272 | return false; | |
1273 | ||
15883505 HPN |
1274 | op0 = XEXP (x, 0); |
1275 | op0p = &XEXP (x, 0); | |
1276 | op1 = XEXP (x, 1); | |
1277 | op1p = &XEXP (x, 1); | |
1278 | ||
1279 | if (!REG_P (op1)) | |
1280 | return false; | |
1281 | ||
991c42ac | 1282 | if (GET_CODE (op0) == SIGN_EXTEND && MEM_P (XEXP (op0, 0))) |
15883505 HPN |
1283 | { |
1284 | rtx op00 = XEXP (op0, 0); | |
1285 | rtx op000 = XEXP (op00, 0); | |
1286 | rtx *op000p = &XEXP (op00, 0); | |
1287 | ||
1288 | if ((GET_MODE (op00) == HImode || GET_MODE (op00) == QImode) | |
1289 | && (REG_P (op000) | |
1290 | || (GET_CODE (op000) == POST_INC && REG_P (XEXP (op000, 0))))) | |
1291 | { | |
1292 | bool something_reloaded = false; | |
1293 | ||
1294 | if (GET_CODE (op000) == POST_INC | |
1295 | && REG_P (XEXP (op000, 0)) | |
1296 | && REGNO (XEXP (op000, 0)) > CRIS_LAST_GENERAL_REGISTER) | |
1297 | /* No, this gets too complicated and is too rare to care | |
1298 | about trying to improve on the general code Here. | |
1299 | As the return-value is an all-or-nothing indicator, we | |
1300 | punt on the other register too. */ | |
1301 | return false; | |
1302 | ||
1303 | if ((REG_P (op000) | |
1304 | && REGNO (op000) > CRIS_LAST_GENERAL_REGISTER)) | |
1305 | { | |
1306 | /* The address of the inner mem is a pseudo or wrong | |
1307 | reg: reload that. */ | |
1308 | push_reload (op000, NULL_RTX, op000p, NULL, GENERAL_REGS, | |
1309 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); | |
1310 | something_reloaded = true; | |
1311 | } | |
1312 | ||
1313 | if (REGNO (op1) > CRIS_LAST_GENERAL_REGISTER) | |
1314 | { | |
1315 | /* Base register is a pseudo or wrong reg: reload it. */ | |
1316 | push_reload (op1, NULL_RTX, op1p, NULL, GENERAL_REGS, | |
1317 | GET_MODE (x), VOIDmode, 0, 0, | |
1318 | opnum, type); | |
1319 | something_reloaded = true; | |
1320 | } | |
1321 | ||
1322 | gcc_assert (something_reloaded); | |
1323 | ||
1324 | return true; | |
1325 | } | |
1326 | } | |
1327 | ||
1328 | return false; | |
1329 | } | |
1330 | ||
c31500c2 | 1331 | /* Worker function for REGISTER_MOVE_COST. */ |
0b85d816 | 1332 | |
c31500c2 HPN |
1333 | int |
1334 | cris_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, | |
1335 | enum reg_class from, enum reg_class to) | |
0b85d816 | 1336 | { |
c31500c2 | 1337 | if (!TARGET_V32) |
0b85d816 | 1338 | { |
c31500c2 HPN |
1339 | /* Pretend that classes that we don't support are ALL_REGS, so |
1340 | we give them the highest cost. */ | |
1341 | if (from != SPECIAL_REGS && from != MOF_REGS | |
1342 | && from != GENERAL_REGS && from != GENNONACR_REGS) | |
1343 | from = ALL_REGS; | |
1344 | ||
1345 | if (to != SPECIAL_REGS && to != MOF_REGS | |
1346 | && to != GENERAL_REGS && to != GENNONACR_REGS) | |
1347 | to = ALL_REGS; | |
0b85d816 HPN |
1348 | } |
1349 | ||
c31500c2 HPN |
1350 | /* Can't move to and from a SPECIAL_REGS register, so we have to say |
1351 | their move cost within that class is higher. How about 7? That's 3 | |
1352 | for a move to a GENERAL_REGS register, 3 for the move from the | |
1353 | GENERAL_REGS register, and 1 for the increased register pressure. | |
1354 | Also, it's higher than the memory move cost, which is in order. | |
1355 | We also do this for ALL_REGS, since we don't want that class to be | |
1356 | preferred (even to memory) at all where GENERAL_REGS doesn't fit. | |
1357 | Whenever it's about to be used, it's for SPECIAL_REGS. If we don't | |
1358 | present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be | |
1359 | used when a GENERAL_REGS should be used, even if there are call-saved | |
1360 | GENERAL_REGS left to allocate. This is because the fall-back when | |
1361 | the most preferred register class isn't available, isn't the next | |
1362 | (or next good) wider register class, but the *most widest* register | |
1363 | class. */ | |
1364 | ||
1365 | if ((reg_classes_intersect_p (from, SPECIAL_REGS) | |
1366 | && reg_classes_intersect_p (to, SPECIAL_REGS)) | |
1367 | || from == ALL_REGS || to == ALL_REGS) | |
1368 | return 7; | |
1369 | ||
1370 | if (reg_classes_intersect_p (from, SPECIAL_REGS) | |
1371 | || reg_classes_intersect_p (to, SPECIAL_REGS)) | |
1372 | return 3; | |
1373 | ||
1374 | return 2; | |
1375 | } | |
0b85d816 | 1376 | |
c31500c2 HPN |
1377 | /* Worker for cris_notice_update_cc; handles the "normal" cases. |
1378 | FIXME: this code is historical; its functionality should be | |
1379 | refactored to look at insn attributes and moved to | |
1380 | cris_notice_update_cc. Except, we better lose cc0 entirely. */ | |
0b85d816 | 1381 | |
c31500c2 HPN |
1382 | static void |
1383 | cris_normal_notice_update_cc (rtx exp, rtx insn) | |
1384 | { | |
1385 | /* "Normal" means, for: | |
1386 | (set (cc0) (...)): | |
1387 | CC is (...). | |
0b85d816 | 1388 | |
c31500c2 HPN |
1389 | (set (reg) (...)): |
1390 | CC is (reg) and (...) - unless (...) is 0 or reg is a special | |
1391 | register or (v32 and (...) is -32..-1), then CC does not change. | |
1392 | CC_NO_OVERFLOW unless (...) is reg or mem. | |
0b85d816 | 1393 | |
c31500c2 HPN |
1394 | (set (mem) (...)): |
1395 | CC does not change. | |
0b85d816 | 1396 | |
c31500c2 HPN |
1397 | (set (pc) (...)): |
1398 | CC does not change. | |
0b85d816 | 1399 | |
c31500c2 HPN |
1400 | (parallel |
1401 | (set (reg1) (mem (bdap/biap))) | |
1402 | (set (reg2) (bdap/biap))): | |
1403 | CC is (reg1) and (mem (reg2)) | |
0b85d816 | 1404 | |
c31500c2 HPN |
1405 | (parallel |
1406 | (set (mem (bdap/biap)) (reg1)) [or 0] | |
1407 | (set (reg2) (bdap/biap))): | |
1408 | CC does not change. | |
0b85d816 | 1409 | |
c31500c2 | 1410 | (where reg and mem includes strict_low_parts variants thereof) |
0b85d816 | 1411 | |
c31500c2 HPN |
1412 | For all others, assume CC is clobbered. |
1413 | Note that we do not have to care about setting CC_NO_OVERFLOW, | |
1414 | since the overflow flag is set to 0 (i.e. right) for | |
1415 | instructions where it does not have any sane sense, but where | |
1416 | other flags have meanings. (This includes shifts; the carry is | |
1417 | not set by them). | |
0b85d816 | 1418 | |
c31500c2 HPN |
1419 | Note that there are other parallel constructs we could match, |
1420 | but we don't do that yet. */ | |
0b85d816 | 1421 | |
c31500c2 HPN |
1422 | if (GET_CODE (exp) == SET) |
1423 | { | |
1424 | /* FIXME: Check when this happens. It looks like we should | |
1425 | actually do a CC_STATUS_INIT here to be safe. */ | |
1426 | if (SET_DEST (exp) == pc_rtx) | |
1427 | return; | |
0b85d816 | 1428 | |
c31500c2 HPN |
1429 | /* Record CC0 changes, so we do not have to output multiple |
1430 | test insns. */ | |
1431 | if (SET_DEST (exp) == cc0_rtx) | |
0b85d816 | 1432 | { |
c31500c2 HPN |
1433 | CC_STATUS_INIT; |
1434 | cc_status.value1 = SET_SRC (exp); | |
0b85d816 | 1435 | |
c31500c2 HPN |
1436 | /* Handle flags for the special btstq on one bit. */ |
1437 | if (GET_CODE (SET_SRC (exp)) == ZERO_EXTRACT | |
1438 | && XEXP (SET_SRC (exp), 1) == const1_rtx) | |
0b85d816 | 1439 | { |
c31500c2 HPN |
1440 | if (CONST_INT_P (XEXP (SET_SRC (exp), 0))) |
1441 | /* Using cmpq. */ | |
1442 | cc_status.flags = CC_INVERTED; | |
0b85d816 | 1443 | else |
c31500c2 HPN |
1444 | /* A one-bit btstq. */ |
1445 | cc_status.flags = CC_Z_IN_NOT_N; | |
0b85d816 | 1446 | } |
0b85d816 | 1447 | |
c31500c2 HPN |
1448 | if (GET_CODE (SET_SRC (exp)) == COMPARE) |
1449 | { | |
1450 | if (!REG_P (XEXP (SET_SRC (exp), 0)) | |
1451 | && XEXP (SET_SRC (exp), 1) != const0_rtx) | |
1452 | /* For some reason gcc will not canonicalize compare | |
1453 | operations, reversing the sign by itself if | |
1454 | operands are in wrong order. */ | |
1455 | /* (But NOT inverted; eq is still eq.) */ | |
1456 | cc_status.flags = CC_REVERSED; | |
1457 | ||
1458 | /* This seems to be overlooked by gcc. FIXME: Check again. | |
1459 | FIXME: Is it really safe? */ | |
1460 | cc_status.value2 | |
1461 | = gen_rtx_MINUS (GET_MODE (SET_SRC (exp)), | |
1462 | XEXP (SET_SRC (exp), 0), | |
1463 | XEXP (SET_SRC (exp), 1)); | |
1464 | } | |
1465 | return; | |
1466 | } | |
1467 | else if (REG_P (SET_DEST (exp)) | |
1468 | || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART | |
1469 | && REG_P (XEXP (SET_DEST (exp), 0)))) | |
1470 | { | |
1471 | /* A register is set; normally CC is set to show that no | |
1472 | test insn is needed. Catch the exceptions. */ | |
0b85d816 | 1473 | |
c31500c2 HPN |
1474 | /* If not to cc0, then no "set"s in non-natural mode give |
1475 | ok cc0... */ | |
1476 | if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp))) > UNITS_PER_WORD | |
1477 | || GET_MODE_CLASS (GET_MODE (SET_DEST (exp))) == MODE_FLOAT) | |
1478 | { | |
1479 | /* ... except add:s and sub:s in DImode. */ | |
1480 | if (GET_MODE (SET_DEST (exp)) == DImode | |
1481 | && (GET_CODE (SET_SRC (exp)) == PLUS | |
1482 | || GET_CODE (SET_SRC (exp)) == MINUS)) | |
0b85d816 | 1483 | { |
c31500c2 | 1484 | CC_STATUS_INIT; |
0b85d816 HPN |
1485 | cc_status.value1 = SET_DEST (exp); |
1486 | cc_status.value2 = SET_SRC (exp); | |
1487 | ||
1488 | if (cris_reg_overlap_mentioned_p (cc_status.value1, | |
1489 | cc_status.value2)) | |
1490 | cc_status.value2 = 0; | |
1491 | ||
c31500c2 | 1492 | /* Add and sub may set V, which gets us |
0b85d816 HPN |
1493 | unoptimizable results in "gt" and "le" condition |
1494 | codes. */ | |
c31500c2 | 1495 | cc_status.flags |= CC_NO_OVERFLOW; |
0b85d816 HPN |
1496 | |
1497 | return; | |
1498 | } | |
1499 | } | |
c31500c2 HPN |
1500 | else if (SET_SRC (exp) == const0_rtx |
1501 | || (REG_P (SET_SRC (exp)) | |
1502 | && (REGNO (SET_SRC (exp)) | |
1503 | > CRIS_LAST_GENERAL_REGISTER)) | |
1504 | || (TARGET_V32 | |
1505 | && GET_CODE (SET_SRC (exp)) == CONST_INT | |
1506 | && CONST_OK_FOR_LETTER_P (INTVAL (SET_SRC (exp)), | |
1507 | 'I'))) | |
0b85d816 | 1508 | { |
c31500c2 HPN |
1509 | /* There's no CC0 change for this case. Just check |
1510 | for overlap. */ | |
f4ddaddd HPN |
1511 | if (cc_status.value1 |
1512 | && modified_in_p (cc_status.value1, insn)) | |
0b85d816 HPN |
1513 | cc_status.value1 = 0; |
1514 | ||
f4ddaddd HPN |
1515 | if (cc_status.value2 |
1516 | && modified_in_p (cc_status.value2, insn)) | |
0b85d816 HPN |
1517 | cc_status.value2 = 0; |
1518 | ||
1519 | return; | |
1520 | } | |
c31500c2 HPN |
1521 | else |
1522 | { | |
1523 | CC_STATUS_INIT; | |
1524 | cc_status.value1 = SET_DEST (exp); | |
1525 | cc_status.value2 = SET_SRC (exp); | |
1526 | ||
1527 | if (cris_reg_overlap_mentioned_p (cc_status.value1, | |
1528 | cc_status.value2)) | |
1529 | cc_status.value2 = 0; | |
1530 | ||
1531 | /* Some operations may set V, which gets us | |
1532 | unoptimizable results in "gt" and "le" condition | |
1533 | codes. */ | |
1534 | if (GET_CODE (SET_SRC (exp)) == PLUS | |
1535 | || GET_CODE (SET_SRC (exp)) == MINUS | |
1536 | || GET_CODE (SET_SRC (exp)) == NEG) | |
1537 | cc_status.flags |= CC_NO_OVERFLOW; | |
1538 | ||
1539 | /* For V32, nothing with a register destination sets | |
1540 | C and V usefully. */ | |
1541 | if (TARGET_V32) | |
1542 | cc_status.flags |= CC_NO_OVERFLOW; | |
1543 | ||
1544 | return; | |
1545 | } | |
1546 | } | |
1547 | else if (MEM_P (SET_DEST (exp)) | |
1548 | || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART | |
1549 | && MEM_P (XEXP (SET_DEST (exp), 0)))) | |
1550 | { | |
1551 | /* When SET to MEM, then CC is not changed (except for | |
1552 | overlap). */ | |
1553 | if (cc_status.value1 | |
1554 | && modified_in_p (cc_status.value1, insn)) | |
1555 | cc_status.value1 = 0; | |
1556 | ||
1557 | if (cc_status.value2 | |
1558 | && modified_in_p (cc_status.value2, insn)) | |
1559 | cc_status.value2 = 0; | |
1560 | ||
1561 | return; | |
0b85d816 | 1562 | } |
c31500c2 HPN |
1563 | } |
1564 | else if (GET_CODE (exp) == PARALLEL) | |
1565 | { | |
1566 | if (GET_CODE (XVECEXP (exp, 0, 0)) == SET | |
1567 | && GET_CODE (XVECEXP (exp, 0, 1)) == SET | |
1568 | && REG_P (XEXP (XVECEXP (exp, 0, 1), 0))) | |
0b85d816 | 1569 | { |
c31500c2 HPN |
1570 | if (REG_P (XEXP (XVECEXP (exp, 0, 0), 0)) |
1571 | && MEM_P (XEXP (XVECEXP (exp, 0, 0), 1))) | |
0b85d816 | 1572 | { |
c31500c2 HPN |
1573 | CC_STATUS_INIT; |
1574 | ||
1575 | /* For "move.S [rx=ry+o],rz", say CC reflects | |
1576 | value1=rz and value2=[rx] */ | |
1577 | cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0); | |
1578 | cc_status.value2 | |
1579 | = replace_equiv_address (XEXP (XVECEXP (exp, 0, 0), 1), | |
1580 | XEXP (XVECEXP (exp, 0, 1), 0)); | |
1581 | ||
1582 | /* Huh? A side-effect cannot change the destination | |
1583 | register. */ | |
1584 | if (cris_reg_overlap_mentioned_p (cc_status.value1, | |
1585 | cc_status.value2)) | |
1586 | internal_error ("internal error: sideeffect-insn affecting main effect"); | |
1587 | ||
1588 | /* For V32, moves to registers don't set C and V. */ | |
1589 | if (TARGET_V32) | |
1590 | cc_status.flags |= CC_NO_OVERFLOW; | |
1591 | return; | |
1592 | } | |
1593 | else if ((REG_P (XEXP (XVECEXP (exp, 0, 0), 1)) | |
1594 | || XEXP (XVECEXP (exp, 0, 0), 1) == const0_rtx) | |
1595 | && MEM_P (XEXP (XVECEXP (exp, 0, 0), 0))) | |
1596 | { | |
1597 | /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]", | |
1598 | say flags are not changed, except for overlap. */ | |
1599 | if (cc_status.value1 | |
1600 | && modified_in_p (cc_status.value1, insn)) | |
1601 | cc_status.value1 = 0; | |
d3295e25 | 1602 | |
c31500c2 HPN |
1603 | if (cc_status.value2 |
1604 | && modified_in_p (cc_status.value2, insn)) | |
1605 | cc_status.value2 = 0; | |
1606 | ||
1607 | return; | |
0b85d816 HPN |
1608 | } |
1609 | } | |
c31500c2 HPN |
1610 | } |
1611 | ||
1612 | /* If we got here, the case wasn't covered by the code above. */ | |
1613 | CC_STATUS_INIT; | |
1614 | } | |
1615 | ||
1616 | /* This function looks into the pattern to see how this insn affects | |
1617 | condition codes. | |
1618 | ||
1619 | Used when to eliminate test insns before a condition-code user, | |
1620 | such as a "scc" insn or a conditional branch. This includes | |
1621 | checking if the entities that cc was updated by, are changed by the | |
1622 | operation. | |
1623 | ||
1624 | Currently a jumble of the old peek-inside-the-insn and the newer | |
1625 | check-cc-attribute methods. */ | |
1626 | ||
1627 | void | |
1628 | cris_notice_update_cc (rtx exp, rtx insn) | |
1629 | { | |
1630 | enum attr_cc attrval = get_attr_cc (insn); | |
1631 | ||
1632 | /* Check if user specified "-mcc-init" as a bug-workaround. Remember | |
1633 | to still set CC_REVERSED as below, since that's required by some | |
1634 | compare insn alternatives. (FIXME: GCC should do this virtual | |
1635 | operand swap by itself.) A test-case that may otherwise fail is | |
1636 | gcc.c-torture/execute/20000217-1.c -O0 and -O1. */ | |
1637 | if (TARGET_CCINIT) | |
1638 | { | |
1639 | CC_STATUS_INIT; | |
1640 | ||
1641 | if (attrval == CC_REV) | |
1642 | cc_status.flags = CC_REVERSED; | |
1643 | return; | |
1644 | } | |
1645 | ||
1646 | /* Slowly, we're converting to using attributes to control the setting | |
1647 | of condition-code status. */ | |
1648 | switch (attrval) | |
1649 | { | |
1650 | case CC_NONE: | |
1651 | /* Even if it is "none", a setting may clobber a previous | |
1652 | cc-value, so check. */ | |
1653 | if (GET_CODE (exp) == SET) | |
1654 | { | |
1655 | if (cc_status.value1 | |
1656 | && modified_in_p (cc_status.value1, insn)) | |
1657 | cc_status.value1 = 0; | |
1658 | ||
1659 | if (cc_status.value2 | |
1660 | && modified_in_p (cc_status.value2, insn)) | |
1661 | cc_status.value2 = 0; | |
1662 | } | |
1663 | return; | |
1664 | ||
1665 | case CC_CLOBBER: | |
1666 | CC_STATUS_INIT; | |
1667 | return; | |
1668 | ||
1669 | case CC_REV: | |
1670 | case CC_NOOV32: | |
1671 | case CC_NORMAL: | |
1672 | cris_normal_notice_update_cc (exp, insn); | |
1673 | ||
1674 | /* The "test" insn doesn't clear (carry and) overflow on V32. We | |
1675 | can change bge => bpl and blt => bmi by passing on to the cc0 | |
1676 | user that V should not be considered; bgt and ble are taken | |
1677 | care of by other methods (see {tst,cmp}{si,hi,qi}). */ | |
1678 | if (attrval == CC_NOOV32 && TARGET_V32) | |
1679 | cc_status.flags |= CC_NO_OVERFLOW; | |
1680 | return; | |
0b85d816 HPN |
1681 | |
1682 | default: | |
ab532386 | 1683 | internal_error ("unknown cc_attr value"); |
0b85d816 HPN |
1684 | } |
1685 | ||
1686 | CC_STATUS_INIT; | |
1687 | } | |
1688 | ||
1689 | /* Return != 0 if the return sequence for the current function is short, | |
04539954 HPN |
1690 | like "ret" or "jump [sp+]". Prior to reloading, we can't tell if |
1691 | registers must be saved, so return 0 then. */ | |
0b85d816 | 1692 | |
04539954 | 1693 | bool |
6640377c | 1694 | cris_simple_epilogue (void) |
0b85d816 | 1695 | { |
04539954 HPN |
1696 | unsigned int regno; |
1697 | unsigned int reglimit = STACK_POINTER_REGNUM; | |
c00fc5cf | 1698 | bool got_really_used = false; |
0b85d816 HPN |
1699 | |
1700 | if (! reload_completed | |
1701 | || frame_pointer_needed | |
1702 | || get_frame_size () != 0 | |
38173d38 JH |
1703 | || crtl->args.pretend_args_size |
1704 | || crtl->args.size | |
1705 | || crtl->outgoing_args_size | |
e3b5732b | 1706 | || crtl->calls_eh_return |
0b85d816 HPN |
1707 | |
1708 | /* If we're not supposed to emit prologue and epilogue, we must | |
1709 | not emit return-type instructions. */ | |
1710 | || !TARGET_PROLOGUE_EPILOGUE) | |
04539954 | 1711 | return false; |
0b85d816 | 1712 | |
c31500c2 HPN |
1713 | /* Can't return from stacked return address with v32. */ |
1714 | if (TARGET_V32 && cris_return_address_on_stack ()) | |
1715 | return false; | |
1716 | ||
e3b5732b | 1717 | if (crtl->uses_pic_offset_table) |
c00fc5cf HPN |
1718 | { |
1719 | push_topmost_sequence (); | |
1720 | got_really_used | |
1721 | = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX); | |
1722 | pop_topmost_sequence (); | |
1723 | } | |
1724 | ||
04539954 | 1725 | /* No simple epilogue if there are saved registers. */ |
0b85d816 | 1726 | for (regno = 0; regno < reglimit; regno++) |
04539954 HPN |
1727 | if (cris_reg_saved_in_regsave_area (regno, got_really_used)) |
1728 | return false; | |
0b85d816 | 1729 | |
04539954 HPN |
1730 | return true; |
1731 | } | |
1732 | ||
1733 | /* Expand a return insn (just one insn) marked as using SRP or stack | |
1734 | slot depending on parameter ON_STACK. */ | |
1735 | ||
1736 | void | |
1737 | cris_expand_return (bool on_stack) | |
1738 | { | |
1739 | /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to | |
1740 | tell "ret" from "jump [sp+]". Some, but not all, other parts of | |
1741 | GCC expect just (return) to do the right thing when optimizing, so | |
1742 | we do that until they're fixed. Currently, all return insns in a | |
1743 | function must be the same (not really a limiting factor) so we need | |
1744 | to check that it doesn't change half-way through. */ | |
1745 | emit_jump_insn (gen_rtx_RETURN (VOIDmode)); | |
1746 | ||
b6c34129 HPN |
1747 | CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_RET || !on_stack); |
1748 | CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_JUMP || on_stack); | |
04539954 HPN |
1749 | |
1750 | cfun->machine->return_type | |
1751 | = on_stack ? CRIS_RETINSN_JUMP : CRIS_RETINSN_RET; | |
0b85d816 HPN |
1752 | } |
1753 | ||
3c50106f RH |
1754 | /* Compute a (partial) cost for rtx X. Return true if the complete |
1755 | cost has been computed, and false if subexpressions should be | |
1756 | scanned. In either case, *TOTAL contains the cost result. */ | |
1757 | ||
1758 | static bool | |
6640377c | 1759 | cris_rtx_costs (rtx x, int code, int outer_code, int *total) |
3c50106f RH |
1760 | { |
1761 | switch (code) | |
1762 | { | |
1763 | case CONST_INT: | |
1764 | { | |
1765 | HOST_WIDE_INT val = INTVAL (x); | |
1766 | if (val == 0) | |
1767 | *total = 0; | |
1768 | else if (val < 32 && val >= -32) | |
1769 | *total = 1; | |
1770 | /* Eight or 16 bits are a word and cycle more expensive. */ | |
1771 | else if (val <= 32767 && val >= -32768) | |
1772 | *total = 2; | |
a7b376ee | 1773 | /* A 32-bit constant (or very seldom, unsigned 16 bits) costs |
3c50106f RH |
1774 | another word. FIXME: This isn't linear to 16 bits. */ |
1775 | else | |
1776 | *total = 4; | |
1777 | return true; | |
1778 | } | |
1779 | ||
1780 | case LABEL_REF: | |
1781 | *total = 6; | |
1782 | return true; | |
1783 | ||
1784 | case CONST: | |
1785 | case SYMBOL_REF: | |
c00fc5cf | 1786 | *total = 6; |
3c50106f RH |
1787 | return true; |
1788 | ||
1789 | case CONST_DOUBLE: | |
1790 | if (x != CONST0_RTX (GET_MODE (x) == VOIDmode ? DImode : GET_MODE (x))) | |
1791 | *total = 12; | |
1792 | else | |
1793 | /* Make 0.0 cheap, else test-insns will not be used. */ | |
1794 | *total = 0; | |
1795 | return true; | |
1796 | ||
1797 | case MULT: | |
1798 | /* Identify values that are no powers of two. Powers of 2 are | |
1799 | taken care of already and those values should not be changed. */ | |
991c42ac | 1800 | if (!CONST_INT_P (XEXP (x, 1)) |
3c50106f RH |
1801 | || exact_log2 (INTVAL (XEXP (x, 1)) < 0)) |
1802 | { | |
1803 | /* If we have a multiply insn, then the cost is between | |
1804 | 1 and 2 "fast" instructions. */ | |
1805 | if (TARGET_HAS_MUL_INSNS) | |
1806 | { | |
1807 | *total = COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2; | |
1808 | return true; | |
1809 | } | |
1810 | ||
1811 | /* Estimate as 4 + 4 * #ofbits. */ | |
1812 | *total = COSTS_N_INSNS (132); | |
1813 | return true; | |
1814 | } | |
1815 | return false; | |
1816 | ||
1817 | case UDIV: | |
1818 | case MOD: | |
1819 | case UMOD: | |
1820 | case DIV: | |
991c42ac | 1821 | if (!CONST_INT_P (XEXP (x, 1)) |
5b296d93 | 1822 | || exact_log2 (INTVAL (XEXP (x, 1)) < 0)) |
3c50106f RH |
1823 | { |
1824 | /* Estimate this as 4 + 8 * #of bits. */ | |
1825 | *total = COSTS_N_INSNS (260); | |
1826 | return true; | |
1827 | } | |
1828 | return false; | |
1829 | ||
1830 | case AND: | |
991c42ac | 1831 | if (CONST_INT_P (XEXP (x, 1)) |
3c50106f | 1832 | /* Two constants may actually happen before optimization. */ |
991c42ac | 1833 | && !CONST_INT_P (XEXP (x, 0)) |
3c50106f RH |
1834 | && !CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I')) |
1835 | { | |
1836 | *total = (rtx_cost (XEXP (x, 0), outer_code) + 2 | |
1837 | + 2 * GET_MODE_NUNITS (GET_MODE (XEXP (x, 0)))); | |
1838 | return true; | |
1839 | } | |
1840 | return false; | |
1841 | ||
1842 | case ZERO_EXTEND: case SIGN_EXTEND: | |
1843 | *total = rtx_cost (XEXP (x, 0), outer_code); | |
1844 | return true; | |
1845 | ||
1846 | default: | |
1847 | return false; | |
1848 | } | |
1849 | } | |
1850 | ||
0b85d816 HPN |
1851 | /* The ADDRESS_COST worker. */ |
1852 | ||
75642f32 | 1853 | static int |
6640377c | 1854 | cris_address_cost (rtx x) |
0b85d816 HPN |
1855 | { |
1856 | /* The metric to use for the cost-macros is unclear. | |
1857 | The metric used here is (the number of cycles needed) / 2, | |
1858 | where we consider equal a cycle for a word of code and a cycle to | |
a3ef2349 HPN |
1859 | read memory. FIXME: Adding "+ 1" to all values would avoid |
1860 | returning 0, as tree-ssa-loop-ivopts.c as of r128272 "normalizes" | |
1861 | 0 to 1, thereby giving equal costs to [rN + rM] and [rN]. | |
1862 | Unfortunately(?) such a hack would expose other pessimizations, | |
1863 | at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the | |
1864 | loop there, without apparent reason. */ | |
0b85d816 HPN |
1865 | |
1866 | /* The cheapest addressing modes get 0, since nothing extra is needed. */ | |
1867 | if (BASE_OR_AUTOINCR_P (x)) | |
1868 | return 0; | |
1869 | ||
1870 | /* An indirect mem must be a DIP. This means two bytes extra for code, | |
1871 | and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */ | |
991c42ac | 1872 | if (MEM_P (x)) |
0b85d816 HPN |
1873 | return (2 + 4) / 2; |
1874 | ||
1875 | /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs | |
c00fc5cf | 1876 | an extra DIP prefix and 4 bytes of constant in most cases. */ |
0b85d816 | 1877 | if (CONSTANT_P (x)) |
c00fc5cf | 1878 | return (2 + 4) / 2; |
0b85d816 HPN |
1879 | |
1880 | /* Handle BIAP and BDAP prefixes. */ | |
1881 | if (GET_CODE (x) == PLUS) | |
1882 | { | |
1883 | rtx tem1 = XEXP (x, 0); | |
1884 | rtx tem2 = XEXP (x, 1); | |
1885 | ||
582be0a1 HPN |
1886 | /* Local extended canonicalization rule: the first operand must |
1887 | be REG, unless it's an operation (MULT). */ | |
1888 | if (!REG_P (tem1) && GET_CODE (tem1) != MULT) | |
1889 | tem1 = tem2, tem2 = XEXP (x, 0); | |
1890 | ||
1891 | /* We'll "assume" we have canonical RTX now. */ | |
a3ef2349 | 1892 | gcc_assert (REG_P (tem1) || GET_CODE (tem1) == MULT); |
0b85d816 | 1893 | |
a3ef2349 HPN |
1894 | /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We |
1895 | recognize the typical MULT which is always in tem1 because of | |
1896 | insn canonicalization. */ | |
1897 | if ((GET_CODE (tem1) == MULT && BIAP_INDEX_P (tem1)) | |
1898 | || REG_P (tem2)) | |
1899 | return 2 / 2; | |
1900 | ||
1901 | /* A BDAP (quick) is 2 extra bytes. Any constant operand to the | |
1902 | PLUS is always found in tem2. */ | |
1903 | if (CONST_INT_P (tem2) && INTVAL (tem2) < 128 && INTVAL (tem2) >= -128) | |
1904 | return 2 / 2; | |
1905 | ||
1906 | /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra | |
1907 | bytes. */ | |
1908 | if (CONST_INT_P (tem2) && CONST_OK_FOR_LETTER_P (INTVAL (tem2), 'L')) | |
1909 | return (2 + 2) / 2; | |
1910 | ||
1911 | /* A BDAP with some other constant is 2 bytes extra. */ | |
1912 | if (CONSTANT_P (tem2)) | |
1913 | return (2 + 2 + 2) / 2; | |
1914 | ||
1915 | /* BDAP with something indirect should have a higher cost than | |
1916 | BIAP with register. FIXME: Should it cost like a MEM or more? */ | |
1917 | return (2 + 2 + 2) / 2; | |
1918 | } | |
0b85d816 HPN |
1919 | |
1920 | /* What else? Return a high cost. It matters only for valid | |
1921 | addressing modes. */ | |
1922 | return 10; | |
1923 | } | |
1924 | ||
1925 | /* Check various objections to the side-effect. Used in the test-part | |
1926 | of an anonymous insn describing an insn with a possible side-effect. | |
1927 | Returns nonzero if the implied side-effect is ok. | |
1928 | ||
1929 | code : PLUS or MULT | |
1930 | ops : An array of rtx:es. lreg, rreg, rval, | |
1931 | The variables multop and other_op are indexes into this, | |
1932 | or -1 if they are not applicable. | |
1933 | lreg : The register that gets assigned in the side-effect. | |
1934 | rreg : One register in the side-effect expression | |
1935 | rval : The other register, or an int. | |
1936 | multop : An integer to multiply rval with. | |
1937 | other_op : One of the entities of the main effect, | |
1938 | whose mode we must consider. */ | |
1939 | ||
1940 | int | |
6640377c SB |
1941 | cris_side_effect_mode_ok (enum rtx_code code, rtx *ops, |
1942 | int lreg, int rreg, int rval, | |
1943 | int multop, int other_op) | |
0b85d816 HPN |
1944 | { |
1945 | /* Find what value to multiply with, for rx =ry + rz * n. */ | |
1946 | int mult = multop < 0 ? 1 : INTVAL (ops[multop]); | |
1947 | ||
1948 | rtx reg_rtx = ops[rreg]; | |
1949 | rtx val_rtx = ops[rval]; | |
1950 | ||
1951 | /* The operands may be swapped. Canonicalize them in reg_rtx and | |
1952 | val_rtx, where reg_rtx always is a reg (for this constraint to | |
1953 | match). */ | |
1954 | if (! BASE_P (reg_rtx)) | |
1955 | reg_rtx = val_rtx, val_rtx = ops[rreg]; | |
1956 | ||
1957 | /* Don't forget to check that reg_rtx really is a reg. If it isn't, | |
1958 | we have no business. */ | |
1959 | if (! BASE_P (reg_rtx)) | |
1960 | return 0; | |
1961 | ||
1962 | /* Don't do this when -mno-split. */ | |
1963 | if (!TARGET_SIDE_EFFECT_PREFIXES) | |
1964 | return 0; | |
1965 | ||
1966 | /* The mult expression may be hidden in lreg. FIXME: Add more | |
1967 | commentary about that. */ | |
1968 | if (GET_CODE (val_rtx) == MULT) | |
1969 | { | |
1970 | mult = INTVAL (XEXP (val_rtx, 1)); | |
1971 | val_rtx = XEXP (val_rtx, 0); | |
1972 | code = MULT; | |
1973 | } | |
1974 | ||
1975 | /* First check the "other operand". */ | |
1976 | if (other_op >= 0) | |
1977 | { | |
1978 | if (GET_MODE_SIZE (GET_MODE (ops[other_op])) > UNITS_PER_WORD) | |
1979 | return 0; | |
1980 | ||
1981 | /* Check if the lvalue register is the same as the "other | |
1982 | operand". If so, the result is undefined and we shouldn't do | |
1983 | this. FIXME: Check again. */ | |
1984 | if ((BASE_P (ops[lreg]) | |
1985 | && BASE_P (ops[other_op]) | |
1986 | && REGNO (ops[lreg]) == REGNO (ops[other_op])) | |
1987 | || rtx_equal_p (ops[other_op], ops[lreg])) | |
1988 | return 0; | |
1989 | } | |
1990 | ||
1991 | /* Do not accept frame_pointer_rtx as any operand. */ | |
1992 | if (ops[lreg] == frame_pointer_rtx || ops[rreg] == frame_pointer_rtx | |
1993 | || ops[rval] == frame_pointer_rtx | |
1994 | || (other_op >= 0 && ops[other_op] == frame_pointer_rtx)) | |
1995 | return 0; | |
1996 | ||
1997 | if (code == PLUS | |
1998 | && ! BASE_P (val_rtx)) | |
1999 | { | |
2000 | ||
2001 | /* Do not allow rx = rx + n if a normal add or sub with same size | |
2002 | would do. */ | |
2003 | if (rtx_equal_p (ops[lreg], reg_rtx) | |
991c42ac | 2004 | && CONST_INT_P (val_rtx) |
0b85d816 HPN |
2005 | && (INTVAL (val_rtx) <= 63 && INTVAL (val_rtx) >= -63)) |
2006 | return 0; | |
2007 | ||
c00fc5cf | 2008 | /* Check allowed cases, like [r(+)?].[bwd] and const. */ |
0b85d816 | 2009 | if (CONSTANT_P (val_rtx)) |
c00fc5cf | 2010 | return 1; |
0b85d816 | 2011 | |
991c42ac | 2012 | if (MEM_P (val_rtx) && BASE_OR_AUTOINCR_P (XEXP (val_rtx, 0))) |
0b85d816 HPN |
2013 | return 1; |
2014 | ||
2015 | if (GET_CODE (val_rtx) == SIGN_EXTEND | |
991c42ac | 2016 | && MEM_P (XEXP (val_rtx, 0)) |
0b85d816 HPN |
2017 | && BASE_OR_AUTOINCR_P (XEXP (XEXP (val_rtx, 0), 0))) |
2018 | return 1; | |
2019 | ||
2020 | /* If we got here, it's not a valid addressing mode. */ | |
2021 | return 0; | |
2022 | } | |
2023 | else if (code == MULT | |
2024 | || (code == PLUS && BASE_P (val_rtx))) | |
2025 | { | |
2026 | /* Do not allow rx = rx + ry.S, since it doesn't give better code. */ | |
2027 | if (rtx_equal_p (ops[lreg], reg_rtx) | |
2028 | || (mult == 1 && rtx_equal_p (ops[lreg], val_rtx))) | |
2029 | return 0; | |
2030 | ||
2031 | /* Do not allow bad multiply-values. */ | |
2032 | if (mult != 1 && mult != 2 && mult != 4) | |
2033 | return 0; | |
2034 | ||
2035 | /* Only allow r + ... */ | |
2036 | if (! BASE_P (reg_rtx)) | |
2037 | return 0; | |
2038 | ||
2039 | /* If we got here, all seems ok. | |
2040 | (All checks need to be done above). */ | |
2041 | return 1; | |
2042 | } | |
2043 | ||
2044 | /* If we get here, the caller got its initial tests wrong. */ | |
c725bd79 | 2045 | internal_error ("internal error: cris_side_effect_mode_ok with bad operands"); |
0b85d816 HPN |
2046 | } |
2047 | ||
c31500c2 HPN |
2048 | /* Whether next_cc0_user of insn is LE or GT or requires a real compare |
2049 | insn for other reasons. */ | |
2050 | ||
2051 | bool | |
2052 | cris_cc0_user_requires_cmp (rtx insn) | |
2053 | { | |
2054 | rtx cc0_user = NULL; | |
2055 | rtx body; | |
2056 | rtx set; | |
2057 | ||
2058 | gcc_assert (insn != NULL); | |
2059 | ||
2060 | if (!TARGET_V32) | |
2061 | return false; | |
2062 | ||
2063 | cc0_user = next_cc0_user (insn); | |
2064 | if (cc0_user == NULL) | |
2065 | return false; | |
2066 | ||
2067 | body = PATTERN (cc0_user); | |
2068 | set = single_set (cc0_user); | |
2069 | ||
2070 | /* Users can be sCC and bCC. */ | |
2071 | if (JUMP_P (cc0_user) | |
2072 | && GET_CODE (body) == SET | |
2073 | && SET_DEST (body) == pc_rtx | |
2074 | && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE | |
2075 | && XEXP (XEXP (SET_SRC (body), 0), 0) == cc0_rtx) | |
2076 | { | |
2077 | return | |
2078 | GET_CODE (XEXP (SET_SRC (body), 0)) == GT | |
2079 | || GET_CODE (XEXP (SET_SRC (body), 0)) == LE; | |
2080 | } | |
2081 | else if (set) | |
2082 | { | |
2083 | return | |
2084 | GET_CODE (SET_SRC (body)) == GT | |
2085 | || GET_CODE (SET_SRC (body)) == LE; | |
2086 | } | |
2087 | ||
2088 | gcc_unreachable (); | |
2089 | } | |
2090 | ||
0b85d816 HPN |
2091 | /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16) |
2092 | does not handle the case where the IN operand is strict_low_part; it | |
2093 | does handle it for X. Test-case in Axis-20010516. This function takes | |
2094 | care of that for THIS port. FIXME: strict_low_part is going away | |
2095 | anyway. */ | |
2096 | ||
2097 | static int | |
6640377c | 2098 | cris_reg_overlap_mentioned_p (rtx x, rtx in) |
0b85d816 HPN |
2099 | { |
2100 | /* The function reg_overlap_mentioned now handles when X is | |
2101 | strict_low_part, but not when IN is a STRICT_LOW_PART. */ | |
2102 | if (GET_CODE (in) == STRICT_LOW_PART) | |
2103 | in = XEXP (in, 0); | |
2104 | ||
2105 | return reg_overlap_mentioned_p (x, in); | |
2106 | } | |
2107 | ||
2108 | /* The TARGET_ASM_NAMED_SECTION worker. | |
2109 | We just dispatch to the functions for ELF and a.out. */ | |
2110 | ||
2111 | void | |
c18a5b6c MM |
2112 | cris_target_asm_named_section (const char *name, unsigned int flags, |
2113 | tree decl) | |
0b85d816 HPN |
2114 | { |
2115 | if (! TARGET_ELF) | |
c18a5b6c | 2116 | default_no_named_section (name, flags, decl); |
0b85d816 | 2117 | else |
c18a5b6c | 2118 | default_elf_asm_named_section (name, flags, decl); |
0b85d816 HPN |
2119 | } |
2120 | ||
c31500c2 HPN |
2121 | /* Return TRUE iff X is a CONST valid for e.g. indexing. |
2122 | ANY_OPERAND is 0 if X is in a CALL_P insn or movsi, 1 | |
2123 | elsewhere. */ | |
0b85d816 | 2124 | |
c00fc5cf | 2125 | bool |
c31500c2 | 2126 | cris_valid_pic_const (rtx x, bool any_operand) |
0b85d816 | 2127 | { |
c00fc5cf | 2128 | gcc_assert (flag_pic); |
0b85d816 | 2129 | |
0b85d816 HPN |
2130 | switch (GET_CODE (x)) |
2131 | { | |
0b85d816 HPN |
2132 | case CONST_INT: |
2133 | case CONST_DOUBLE: | |
c00fc5cf | 2134 | return true; |
0b85d816 | 2135 | default: |
c00fc5cf | 2136 | ; |
0b85d816 HPN |
2137 | } |
2138 | ||
c00fc5cf HPN |
2139 | if (GET_CODE (x) != CONST) |
2140 | return false; | |
2141 | ||
2142 | x = XEXP (x, 0); | |
2143 | ||
2144 | /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */ | |
2145 | if (GET_CODE (x) == PLUS | |
2146 | && GET_CODE (XEXP (x, 0)) == UNSPEC | |
c31500c2 HPN |
2147 | && (XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREL |
2148 | || XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_PCREL) | |
991c42ac | 2149 | && CONST_INT_P (XEXP (x, 1))) |
c00fc5cf HPN |
2150 | x = XEXP (x, 0); |
2151 | ||
2152 | if (GET_CODE (x) == UNSPEC) | |
2153 | switch (XINT (x, 1)) | |
2154 | { | |
c31500c2 HPN |
2155 | /* A PCREL operand is only valid for call and movsi. */ |
2156 | case CRIS_UNSPEC_PLT_PCREL: | |
2157 | case CRIS_UNSPEC_PCREL: | |
2158 | return !any_operand; | |
2159 | ||
2160 | case CRIS_UNSPEC_PLT_GOTREL: | |
c00fc5cf HPN |
2161 | case CRIS_UNSPEC_PLTGOTREAD: |
2162 | case CRIS_UNSPEC_GOTREAD: | |
2163 | case CRIS_UNSPEC_GOTREL: | |
2164 | return true; | |
2165 | default: | |
2166 | gcc_unreachable (); | |
2167 | } | |
2168 | ||
2169 | return cris_pic_symbol_type_of (x) == cris_no_symbol; | |
0b85d816 HPN |
2170 | } |
2171 | ||
c00fc5cf HPN |
2172 | /* Helper function to find the right PIC-type symbol to generate, |
2173 | given the original (non-PIC) representation. */ | |
0b85d816 | 2174 | |
c00fc5cf HPN |
2175 | enum cris_pic_symbol_type |
2176 | cris_pic_symbol_type_of (rtx x) | |
0b85d816 HPN |
2177 | { |
2178 | switch (GET_CODE (x)) | |
2179 | { | |
0b85d816 | 2180 | case SYMBOL_REF: |
c00fc5cf | 2181 | return SYMBOL_REF_LOCAL_P (x) |
c31500c2 | 2182 | ? cris_rel_symbol : cris_got_symbol; |
0b85d816 HPN |
2183 | |
2184 | case LABEL_REF: | |
c31500c2 | 2185 | return cris_rel_symbol; |
0b85d816 HPN |
2186 | |
2187 | case CONST: | |
c00fc5cf | 2188 | return cris_pic_symbol_type_of (XEXP (x, 0)); |
0b85d816 HPN |
2189 | |
2190 | case PLUS: | |
2191 | case MINUS: | |
2192 | { | |
c00fc5cf HPN |
2193 | enum cris_pic_symbol_type t1 = cris_pic_symbol_type_of (XEXP (x, 0)); |
2194 | enum cris_pic_symbol_type t2 = cris_pic_symbol_type_of (XEXP (x, 1)); | |
2195 | ||
2196 | gcc_assert (t1 == cris_no_symbol || t2 == cris_no_symbol); | |
2197 | ||
2198 | if (t1 == cris_got_symbol || t1 == cris_got_symbol) | |
2199 | return cris_got_symbol_needing_fixup; | |
2200 | ||
2201 | return t1 != cris_no_symbol ? t1 : t2; | |
0b85d816 HPN |
2202 | } |
2203 | ||
2204 | case CONST_INT: | |
2205 | case CONST_DOUBLE: | |
c00fc5cf HPN |
2206 | return cris_no_symbol; |
2207 | ||
2208 | case UNSPEC: | |
2209 | /* Likely an offsettability-test attempting to add a constant to | |
2210 | a GOTREAD symbol, which can't be handled. */ | |
2211 | return cris_invalid_pic_symbol; | |
0b85d816 HPN |
2212 | |
2213 | default: | |
c725bd79 | 2214 | fatal_insn ("unrecognized supposed constant", x); |
0b85d816 HPN |
2215 | } |
2216 | ||
c00fc5cf | 2217 | gcc_unreachable (); |
0b85d816 HPN |
2218 | } |
2219 | ||
c00fc5cf | 2220 | /* The LEGITIMATE_PIC_OPERAND_P worker. */ |
0b85d816 HPN |
2221 | |
2222 | int | |
c00fc5cf | 2223 | cris_legitimate_pic_operand (rtx x) |
0b85d816 | 2224 | { |
c00fc5cf | 2225 | /* Symbols are not valid PIC operands as-is; just constants. */ |
c31500c2 HPN |
2226 | return cris_valid_pic_const (x, true); |
2227 | } | |
2228 | ||
2229 | /* The ASM_OUTPUT_CASE_END worker. */ | |
2230 | ||
2231 | void | |
2232 | cris_asm_output_case_end (FILE *stream, int num, rtx table) | |
2233 | { | |
2234 | if (TARGET_V32) | |
2235 | { | |
2236 | rtx whole_jump_insn = PATTERN (PREV_INSN (PREV_INSN (table))); | |
2237 | ||
2238 | /* This can be a SEQUENCE, meaning the delay-slot of the jump is | |
2239 | filled. */ | |
2240 | rtx parallel_jump | |
2241 | = (GET_CODE (whole_jump_insn) == SEQUENCE | |
2242 | ? PATTERN (XVECEXP (whole_jump_insn, 0, 0)) : whole_jump_insn); | |
2243 | ||
2244 | asm_fprintf (stream, | |
2245 | "\t.word %LL%d-.%s\n", | |
2246 | CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (XVECEXP | |
2247 | (parallel_jump, 0, 0), | |
2248 | 1), 2), 0)), | |
2249 | (TARGET_PDEBUG ? "; default" : "")); | |
2250 | return; | |
2251 | } | |
2252 | ||
2253 | asm_fprintf (stream, | |
2254 | "\t.word %LL%d-%LL%d%s\n", | |
2255 | CODE_LABEL_NUMBER (XEXP | |
2256 | (XEXP | |
2257 | (XEXP | |
2258 | (XVECEXP | |
2259 | (PATTERN | |
2260 | (PREV_INSN | |
2261 | (PREV_INSN (table))), 0, 0), 1), | |
2262 | 2), 0)), | |
2263 | num, | |
2264 | (TARGET_PDEBUG ? "; default" : "")); | |
0b85d816 HPN |
2265 | } |
2266 | ||
2a186d97 HPN |
2267 | /* TARGET_HANDLE_OPTION worker. We just store the values into local |
2268 | variables here. Checks for correct semantics are in | |
2269 | cris_override_options. */ | |
2270 | ||
2271 | static bool | |
c00fc5cf HPN |
2272 | cris_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, |
2273 | int value ATTRIBUTE_UNUSED) | |
2a186d97 HPN |
2274 | { |
2275 | switch (code) | |
2276 | { | |
2277 | case OPT_metrax100: | |
2278 | target_flags | |
2279 | |= (MASK_SVINTO | |
2280 | + MASK_ETRAX4_ADD | |
2281 | + MASK_ALIGN_BY_32); | |
2282 | break; | |
2283 | ||
2284 | case OPT_mno_etrax100: | |
2285 | target_flags | |
2286 | &= ~(MASK_SVINTO | |
2287 | + MASK_ETRAX4_ADD | |
2288 | + MASK_ALIGN_BY_32); | |
2289 | break; | |
2290 | ||
2291 | case OPT_m32_bit: | |
2292 | case OPT_m32bit: | |
2293 | target_flags | |
2294 | |= (MASK_STACK_ALIGN | |
2295 | + MASK_CONST_ALIGN | |
2296 | + MASK_DATA_ALIGN | |
2297 | + MASK_ALIGN_BY_32); | |
2298 | break; | |
2299 | ||
2300 | case OPT_m16_bit: | |
2301 | case OPT_m16bit: | |
2302 | target_flags | |
2303 | |= (MASK_STACK_ALIGN | |
2304 | + MASK_CONST_ALIGN | |
2305 | + MASK_DATA_ALIGN); | |
2306 | break; | |
2307 | ||
2308 | case OPT_m8_bit: | |
2309 | case OPT_m8bit: | |
2310 | target_flags | |
2311 | &= ~(MASK_STACK_ALIGN | |
2312 | + MASK_CONST_ALIGN | |
2313 | + MASK_DATA_ALIGN); | |
2314 | break; | |
2315 | ||
2a186d97 HPN |
2316 | default: |
2317 | break; | |
2318 | } | |
2319 | ||
2320 | CRIS_SUBTARGET_HANDLE_OPTION(code, arg, value); | |
2321 | ||
2322 | return true; | |
2323 | } | |
2324 | ||
0b85d816 HPN |
2325 | /* The OVERRIDE_OPTIONS worker. |
2326 | As is the norm, this also parses -mfoo=bar type parameters. */ | |
2327 | ||
2328 | void | |
6640377c | 2329 | cris_override_options (void) |
0b85d816 HPN |
2330 | { |
2331 | if (cris_max_stackframe_str) | |
2332 | { | |
2333 | cris_max_stackframe = atoi (cris_max_stackframe_str); | |
2334 | ||
2335 | /* Do some sanity checking. */ | |
2336 | if (cris_max_stackframe < 0 || cris_max_stackframe > 0x20000000) | |
2337 | internal_error ("-max-stackframe=%d is not usable, not between 0 and %d", | |
2338 | cris_max_stackframe, 0x20000000); | |
2339 | } | |
2340 | ||
2341 | /* Let "-metrax4" and "-metrax100" change the cpu version. */ | |
2342 | if (TARGET_SVINTO && cris_cpu_version < CRIS_CPU_SVINTO) | |
2343 | cris_cpu_version = CRIS_CPU_SVINTO; | |
2344 | else if (TARGET_ETRAX4_ADD && cris_cpu_version < CRIS_CPU_ETRAX4) | |
2345 | cris_cpu_version = CRIS_CPU_ETRAX4; | |
2346 | ||
2347 | /* Parse -march=... and its synonym, the deprecated -mcpu=... */ | |
2348 | if (cris_cpu_str) | |
2349 | { | |
2350 | cris_cpu_version | |
2351 | = (*cris_cpu_str == 'v' ? atoi (cris_cpu_str + 1) : -1); | |
2352 | ||
2353 | if (strcmp ("etrax4", cris_cpu_str) == 0) | |
2354 | cris_cpu_version = 3; | |
2355 | ||
2356 | if (strcmp ("svinto", cris_cpu_str) == 0 | |
2357 | || strcmp ("etrax100", cris_cpu_str) == 0) | |
2358 | cris_cpu_version = 8; | |
2359 | ||
2360 | if (strcmp ("ng", cris_cpu_str) == 0 | |
2361 | || strcmp ("etrax100lx", cris_cpu_str) == 0) | |
2362 | cris_cpu_version = 10; | |
2363 | ||
c31500c2 | 2364 | if (cris_cpu_version < 0 || cris_cpu_version > 32) |
c725bd79 | 2365 | error ("unknown CRIS version specification in -march= or -mcpu= : %s", |
0b85d816 HPN |
2366 | cris_cpu_str); |
2367 | ||
2368 | /* Set the target flags. */ | |
2369 | if (cris_cpu_version >= CRIS_CPU_ETRAX4) | |
2a186d97 | 2370 | target_flags |= MASK_ETRAX4_ADD; |
0b85d816 HPN |
2371 | |
2372 | /* If this is Svinto or higher, align for 32 bit accesses. */ | |
2373 | if (cris_cpu_version >= CRIS_CPU_SVINTO) | |
2374 | target_flags | |
2a186d97 HPN |
2375 | |= (MASK_SVINTO | MASK_ALIGN_BY_32 |
2376 | | MASK_STACK_ALIGN | MASK_CONST_ALIGN | |
2377 | | MASK_DATA_ALIGN); | |
0b85d816 HPN |
2378 | |
2379 | /* Note that we do not add new flags when it can be completely | |
2380 | described with a macro that uses -mcpu=X. So | |
2381 | TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */ | |
2382 | } | |
2383 | ||
2384 | if (cris_tune_str) | |
2385 | { | |
2386 | int cris_tune | |
2387 | = (*cris_tune_str == 'v' ? atoi (cris_tune_str + 1) : -1); | |
2388 | ||
2389 | if (strcmp ("etrax4", cris_tune_str) == 0) | |
2390 | cris_tune = 3; | |
2391 | ||
2392 | if (strcmp ("svinto", cris_tune_str) == 0 | |
2393 | || strcmp ("etrax100", cris_tune_str) == 0) | |
2394 | cris_tune = 8; | |
2395 | ||
2396 | if (strcmp ("ng", cris_tune_str) == 0 | |
2397 | || strcmp ("etrax100lx", cris_tune_str) == 0) | |
2398 | cris_tune = 10; | |
2399 | ||
c31500c2 | 2400 | if (cris_tune < 0 || cris_tune > 32) |
c725bd79 | 2401 | error ("unknown CRIS cpu version specification in -mtune= : %s", |
0b85d816 HPN |
2402 | cris_tune_str); |
2403 | ||
2404 | if (cris_tune >= CRIS_CPU_SVINTO) | |
2405 | /* We have currently nothing more to tune than alignment for | |
2406 | memory accesses. */ | |
2407 | target_flags | |
2a186d97 HPN |
2408 | |= (MASK_STACK_ALIGN | MASK_CONST_ALIGN |
2409 | | MASK_DATA_ALIGN | MASK_ALIGN_BY_32); | |
0b85d816 HPN |
2410 | } |
2411 | ||
c31500c2 HPN |
2412 | if (cris_cpu_version >= CRIS_CPU_V32) |
2413 | target_flags &= ~(MASK_SIDE_EFFECT_PREFIXES|MASK_MUL_BUG); | |
2414 | ||
0b85d816 HPN |
2415 | if (flag_pic) |
2416 | { | |
2417 | /* Use error rather than warning, so invalid use is easily | |
2418 | detectable. Still change to the values we expect, to avoid | |
2419 | further errors. */ | |
2420 | if (! TARGET_LINUX) | |
2421 | { | |
1a05e874 | 2422 | error ("-fPIC and -fpic are not supported in this configuration"); |
0b85d816 HPN |
2423 | flag_pic = 0; |
2424 | } | |
2425 | ||
2426 | /* Turn off function CSE. We need to have the addresses reach the | |
2427 | call expanders to get PLT-marked, as they could otherwise be | |
2428 | compared against zero directly or indirectly. After visiting the | |
2429 | call expanders they will then be cse:ed, as the call expanders | |
2430 | force_reg the addresses, effectively forcing flag_no_function_cse | |
2431 | to 0. */ | |
2432 | flag_no_function_cse = 1; | |
2433 | } | |
2434 | ||
f8ca7e49 | 2435 | if (write_symbols == DWARF2_DEBUG && ! TARGET_ELF) |
0b85d816 | 2436 | { |
d4ee4d25 | 2437 | warning (0, "that particular -g option is invalid with -maout and -melinux"); |
0b85d816 HPN |
2438 | write_symbols = DBX_DEBUG; |
2439 | } | |
2440 | ||
2441 | /* Set the per-function-data initializer. */ | |
2442 | init_machine_status = cris_init_machine_status; | |
2443 | } | |
2444 | ||
eb0424da | 2445 | /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */ |
0b85d816 | 2446 | |
c590b625 | 2447 | static void |
6640377c SB |
2448 | cris_asm_output_mi_thunk (FILE *stream, |
2449 | tree thunkdecl ATTRIBUTE_UNUSED, | |
2450 | HOST_WIDE_INT delta, | |
2451 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
2452 | tree funcdecl) | |
0b85d816 HPN |
2453 | { |
2454 | if (delta > 0) | |
4a0a75dd KG |
2455 | fprintf (stream, "\tadd%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n", |
2456 | ADDITIVE_SIZE_MODIFIER (delta), delta, | |
2457 | reg_names[CRIS_FIRST_ARG_REG]); | |
0b85d816 | 2458 | else if (delta < 0) |
4a0a75dd KG |
2459 | fprintf (stream, "\tsub%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n", |
2460 | ADDITIVE_SIZE_MODIFIER (-delta), -delta, | |
2461 | reg_names[CRIS_FIRST_ARG_REG]); | |
0b85d816 HPN |
2462 | |
2463 | if (flag_pic) | |
2464 | { | |
2465 | const char *name = XSTR (XEXP (DECL_RTL (funcdecl), 0), 0); | |
2466 | ||
772c5265 | 2467 | name = (* targetm.strip_name_encoding) (name); |
c31500c2 HPN |
2468 | |
2469 | if (TARGET_V32) | |
2470 | { | |
2471 | fprintf (stream, "\tba "); | |
2472 | assemble_name (stream, name); | |
2473 | fprintf (stream, "%s\n", CRIS_PLT_PCOFFSET_SUFFIX); | |
2474 | } | |
2475 | else | |
2476 | { | |
2477 | fprintf (stream, "add.d "); | |
2478 | assemble_name (stream, name); | |
2479 | fprintf (stream, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX); | |
2480 | } | |
0b85d816 HPN |
2481 | } |
2482 | else | |
2483 | { | |
2484 | fprintf (stream, "jump "); | |
2485 | assemble_name (stream, XSTR (XEXP (DECL_RTL (funcdecl), 0), 0)); | |
2486 | fprintf (stream, "\n"); | |
c31500c2 HPN |
2487 | |
2488 | if (TARGET_V32) | |
2489 | fprintf (stream, "\tnop\n"); | |
0b85d816 HPN |
2490 | } |
2491 | } | |
2492 | ||
15883505 | 2493 | /* Boilerplate emitted at start of file. |
1bc7c5b6 ZW |
2494 | |
2495 | NO_APP *only at file start* means faster assembly. It also means | |
2496 | comments are not allowed. In some cases comments will be output | |
2497 | for debugging purposes. Make sure they are allowed then. | |
2498 | ||
2499 | We want a .file directive only if TARGET_ELF. */ | |
2500 | static void | |
6640377c | 2501 | cris_file_start (void) |
1bc7c5b6 ZW |
2502 | { |
2503 | /* These expressions can vary at run time, so we cannot put | |
2504 | them into TARGET_INITIALIZER. */ | |
2505 | targetm.file_start_app_off = !(TARGET_PDEBUG || flag_print_asm_name); | |
2506 | targetm.file_start_file_directive = TARGET_ELF; | |
2507 | ||
2508 | default_file_start (); | |
2509 | } | |
2510 | ||
c15c90bb ZW |
2511 | /* Rename the function calls for integer multiply and divide. */ |
2512 | static void | |
30ee56e1 | 2513 | cris_init_libfuncs (void) |
c15c90bb ZW |
2514 | { |
2515 | set_optab_libfunc (smul_optab, SImode, "__Mul"); | |
2516 | set_optab_libfunc (sdiv_optab, SImode, "__Div"); | |
2517 | set_optab_libfunc (udiv_optab, SImode, "__Udiv"); | |
2518 | set_optab_libfunc (smod_optab, SImode, "__Mod"); | |
2519 | set_optab_libfunc (umod_optab, SImode, "__Umod"); | |
2520 | } | |
2521 | ||
0b85d816 HPN |
2522 | /* The INIT_EXPANDERS worker sets the per-function-data initializer and |
2523 | mark functions. */ | |
2524 | ||
2525 | void | |
6640377c | 2526 | cris_init_expanders (void) |
0b85d816 HPN |
2527 | { |
2528 | /* Nothing here at the moment. */ | |
2529 | } | |
2530 | ||
2531 | /* Zero initialization is OK for all current fields. */ | |
2532 | ||
e2500fed | 2533 | static struct machine_function * |
6640377c | 2534 | cris_init_machine_status (void) |
0b85d816 | 2535 | { |
e2500fed | 2536 | return ggc_alloc_cleared (sizeof (struct machine_function)); |
0b85d816 HPN |
2537 | } |
2538 | ||
2539 | /* Split a 2 word move (DI or presumably DF) into component parts. | |
2540 | Originally a copy of gen_split_move_double in m32r.c. */ | |
2541 | ||
2542 | rtx | |
6640377c | 2543 | cris_split_movdx (rtx *operands) |
0b85d816 HPN |
2544 | { |
2545 | enum machine_mode mode = GET_MODE (operands[0]); | |
2546 | rtx dest = operands[0]; | |
2547 | rtx src = operands[1]; | |
2548 | rtx val; | |
2549 | ||
3d556836 HPN |
2550 | /* We used to have to handle (SUBREG (MEM)) here, but that should no |
2551 | longer happen; after reload there are no SUBREGs any more, and we're | |
2552 | only called after reload. */ | |
b6c34129 | 2553 | CRIS_ASSERT (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG); |
0b85d816 HPN |
2554 | |
2555 | start_sequence (); | |
991c42ac | 2556 | if (REG_P (dest)) |
0b85d816 HPN |
2557 | { |
2558 | int dregno = REGNO (dest); | |
2559 | ||
2560 | /* Reg-to-reg copy. */ | |
991c42ac | 2561 | if (REG_P (src)) |
0b85d816 HPN |
2562 | { |
2563 | int sregno = REGNO (src); | |
2564 | ||
2565 | int reverse = (dregno == sregno + 1); | |
2566 | ||
2567 | /* We normally copy the low-numbered register first. However, if | |
2568 | the first register operand 0 is the same as the second register of | |
2569 | operand 1, we must copy in the opposite order. */ | |
2570 | emit_insn (gen_rtx_SET (VOIDmode, | |
2571 | operand_subword (dest, reverse, TRUE, mode), | |
2572 | operand_subword (src, reverse, TRUE, mode))); | |
2573 | ||
2574 | emit_insn (gen_rtx_SET (VOIDmode, | |
2575 | operand_subword (dest, !reverse, TRUE, mode), | |
2576 | operand_subword (src, !reverse, TRUE, mode))); | |
2577 | } | |
2578 | /* Constant-to-reg copy. */ | |
991c42ac | 2579 | else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE) |
0b85d816 HPN |
2580 | { |
2581 | rtx words[2]; | |
2582 | split_double (src, &words[0], &words[1]); | |
2583 | emit_insn (gen_rtx_SET (VOIDmode, | |
2584 | operand_subword (dest, 0, TRUE, mode), | |
2585 | words[0])); | |
2586 | ||
2587 | emit_insn (gen_rtx_SET (VOIDmode, | |
2588 | operand_subword (dest, 1, TRUE, mode), | |
2589 | words[1])); | |
2590 | } | |
2591 | /* Mem-to-reg copy. */ | |
991c42ac | 2592 | else if (MEM_P (src)) |
0b85d816 HPN |
2593 | { |
2594 | /* If the high-address word is used in the address, we must load it | |
2595 | last. Otherwise, load it first. */ | |
2596 | rtx addr = XEXP (src, 0); | |
2597 | int reverse | |
2598 | = (refers_to_regno_p (dregno, dregno + 1, addr, NULL) != 0); | |
2599 | ||
1ae58c30 | 2600 | /* The original code implies that we can't do |
0b85d816 HPN |
2601 | move.x [rN+],rM move.x [rN],rM+1 |
2602 | when rN is dead, because of REG_NOTES damage. That is | |
2603 | consistent with what I've seen, so don't try it. | |
2604 | ||
2605 | We have two different cases here; if the addr is POST_INC, | |
2606 | just pass it through, otherwise add constants. */ | |
2607 | ||
2608 | if (GET_CODE (addr) == POST_INC) | |
2609 | { | |
752b602f HPN |
2610 | rtx mem; |
2611 | rtx insn; | |
2612 | ||
2613 | /* Whenever we emit insns with post-incremented | |
2614 | addresses ourselves, we must add a post-inc note | |
2615 | manually. */ | |
2616 | mem = change_address (src, SImode, addr); | |
2617 | insn | |
2618 | = gen_rtx_SET (VOIDmode, | |
2619 | operand_subword (dest, 0, TRUE, mode), mem); | |
2620 | insn = emit_insn (insn); | |
2621 | if (GET_CODE (XEXP (mem, 0)) == POST_INC) | |
2622 | REG_NOTES (insn) | |
2623 | = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), | |
2624 | REG_NOTES (insn)); | |
2625 | ||
c31500c2 | 2626 | mem = copy_rtx (mem); |
752b602f HPN |
2627 | insn |
2628 | = gen_rtx_SET (VOIDmode, | |
2629 | operand_subword (dest, 1, TRUE, mode), mem); | |
2630 | insn = emit_insn (insn); | |
2631 | if (GET_CODE (XEXP (mem, 0)) == POST_INC) | |
2632 | REG_NOTES (insn) | |
2633 | = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), | |
2634 | REG_NOTES (insn)); | |
0b85d816 HPN |
2635 | } |
2636 | else | |
2637 | { | |
2638 | /* Make sure we don't get any other addresses with | |
2639 | embedded postincrements. They should be stopped in | |
2640 | GO_IF_LEGITIMATE_ADDRESS, but we're here for your | |
2641 | safety. */ | |
2642 | if (side_effects_p (addr)) | |
c725bd79 | 2643 | fatal_insn ("unexpected side-effects in address", addr); |
0b85d816 HPN |
2644 | |
2645 | emit_insn (gen_rtx_SET | |
2646 | (VOIDmode, | |
2647 | operand_subword (dest, reverse, TRUE, mode), | |
2648 | change_address | |
2649 | (src, SImode, | |
2650 | plus_constant (addr, | |
2651 | reverse * UNITS_PER_WORD)))); | |
2652 | emit_insn (gen_rtx_SET | |
2653 | (VOIDmode, | |
2654 | operand_subword (dest, ! reverse, TRUE, mode), | |
2655 | change_address | |
2656 | (src, SImode, | |
2657 | plus_constant (addr, | |
2658 | (! reverse) * | |
2659 | UNITS_PER_WORD)))); | |
2660 | } | |
2661 | } | |
2662 | else | |
b6c34129 | 2663 | internal_error ("Unknown src"); |
0b85d816 HPN |
2664 | } |
2665 | /* Reg-to-mem copy or clear mem. */ | |
991c42ac JBG |
2666 | else if (MEM_P (dest) |
2667 | && (REG_P (src) | |
0b85d816 HPN |
2668 | || src == const0_rtx |
2669 | || src == CONST0_RTX (DFmode))) | |
2670 | { | |
2671 | rtx addr = XEXP (dest, 0); | |
2672 | ||
2673 | if (GET_CODE (addr) == POST_INC) | |
2674 | { | |
752b602f HPN |
2675 | rtx mem; |
2676 | rtx insn; | |
991c42ac | 2677 | |
752b602f HPN |
2678 | /* Whenever we emit insns with post-incremented addresses |
2679 | ourselves, we must add a post-inc note manually. */ | |
2680 | mem = change_address (dest, SImode, addr); | |
2681 | insn | |
2682 | = gen_rtx_SET (VOIDmode, | |
2683 | mem, operand_subword (src, 0, TRUE, mode)); | |
2684 | insn = emit_insn (insn); | |
2685 | if (GET_CODE (XEXP (mem, 0)) == POST_INC) | |
2686 | REG_NOTES (insn) | |
2687 | = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), | |
2688 | REG_NOTES (insn)); | |
2689 | ||
c31500c2 | 2690 | mem = copy_rtx (mem); |
752b602f HPN |
2691 | insn |
2692 | = gen_rtx_SET (VOIDmode, | |
2693 | mem, | |
2694 | operand_subword (src, 1, TRUE, mode)); | |
2695 | insn = emit_insn (insn); | |
2696 | if (GET_CODE (XEXP (mem, 0)) == POST_INC) | |
2697 | REG_NOTES (insn) | |
2698 | = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), | |
2699 | REG_NOTES (insn)); | |
0b85d816 HPN |
2700 | } |
2701 | else | |
2702 | { | |
2703 | /* Make sure we don't get any other addresses with embedded | |
2704 | postincrements. They should be stopped in | |
2705 | GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */ | |
2706 | if (side_effects_p (addr)) | |
c725bd79 | 2707 | fatal_insn ("unexpected side-effects in address", addr); |
0b85d816 HPN |
2708 | |
2709 | emit_insn (gen_rtx_SET | |
2710 | (VOIDmode, | |
2711 | change_address (dest, SImode, addr), | |
2712 | operand_subword (src, 0, TRUE, mode))); | |
2713 | ||
2714 | emit_insn (gen_rtx_SET | |
2715 | (VOIDmode, | |
2716 | change_address (dest, SImode, | |
2717 | plus_constant (addr, | |
2718 | UNITS_PER_WORD)), | |
2719 | operand_subword (src, 1, TRUE, mode))); | |
2720 | } | |
2721 | } | |
2722 | ||
2723 | else | |
b6c34129 | 2724 | internal_error ("Unknown dest"); |
0b85d816 | 2725 | |
2f937369 | 2726 | val = get_insns (); |
0b85d816 HPN |
2727 | end_sequence (); |
2728 | return val; | |
2729 | } | |
2730 | ||
d29b4b1b HPN |
2731 | /* The expander for the prologue pattern name. */ |
2732 | ||
2733 | void | |
2734 | cris_expand_prologue (void) | |
2735 | { | |
2736 | int regno; | |
2737 | int size = get_frame_size (); | |
2738 | /* Shorten the used name for readability. */ | |
38173d38 | 2739 | int cfoa_size = crtl->outgoing_args_size; |
d29b4b1b HPN |
2740 | int last_movem_reg = -1; |
2741 | int framesize = 0; | |
2742 | rtx mem, insn; | |
2743 | int return_address_on_stack = cris_return_address_on_stack (); | |
c00fc5cf | 2744 | int got_really_used = false; |
d29b4b1b | 2745 | int n_movem_regs = 0; |
38173d38 | 2746 | int pretend = crtl->args.pretend_args_size; |
d29b4b1b HPN |
2747 | |
2748 | /* Don't do anything if no prologues or epilogues are wanted. */ | |
2749 | if (!TARGET_PROLOGUE_EPILOGUE) | |
2750 | return; | |
2751 | ||
b6c34129 | 2752 | CRIS_ASSERT (size >= 0); |
d29b4b1b | 2753 | |
e3b5732b | 2754 | if (crtl->uses_pic_offset_table) |
c00fc5cf HPN |
2755 | { |
2756 | /* A reference may have been optimized out (like the abort () in | |
2757 | fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that | |
2758 | it's still used. */ | |
2759 | push_topmost_sequence (); | |
2760 | got_really_used | |
2761 | = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX); | |
2762 | pop_topmost_sequence (); | |
2763 | } | |
2764 | ||
d29b4b1b HPN |
2765 | /* Align the size to what's best for the CPU model. */ |
2766 | if (TARGET_STACK_ALIGN) | |
2767 | size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1; | |
2768 | ||
2769 | if (pretend) | |
2770 | { | |
2771 | /* See also cris_setup_incoming_varargs where | |
2772 | cfun->machine->stdarg_regs is set. There are other setters of | |
38173d38 | 2773 | crtl->args.pretend_args_size than stdarg handling, like |
d29b4b1b HPN |
2774 | for an argument passed with parts in R13 and stack. We must |
2775 | not store R13 into the pretend-area for that case, as GCC does | |
2776 | that itself. "Our" store would be marked as redundant and GCC | |
2777 | will attempt to remove it, which will then be flagged as an | |
2778 | internal error; trying to remove a frame-related insn. */ | |
2779 | int stdarg_regs = cfun->machine->stdarg_regs; | |
2780 | ||
2781 | framesize += pretend; | |
2782 | ||
2783 | for (regno = CRIS_FIRST_ARG_REG + CRIS_MAX_ARGS_IN_REGS - 1; | |
2784 | stdarg_regs > 0; | |
2785 | regno--, pretend -= 4, stdarg_regs--) | |
2786 | { | |
2787 | insn = emit_insn (gen_rtx_SET (VOIDmode, | |
2788 | stack_pointer_rtx, | |
2789 | plus_constant (stack_pointer_rtx, | |
2790 | -4))); | |
2791 | /* FIXME: When dwarf2 frame output and unless asynchronous | |
2792 | exceptions, make dwarf2 bundle together all stack | |
2793 | adjustments like it does for registers between stack | |
2794 | adjustments. */ | |
2795 | RTX_FRAME_RELATED_P (insn) = 1; | |
2796 | ||
2797 | mem = gen_rtx_MEM (SImode, stack_pointer_rtx); | |
2798 | set_mem_alias_set (mem, get_varargs_alias_set ()); | |
2799 | insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, regno)); | |
2800 | ||
2801 | /* Note the absence of RTX_FRAME_RELATED_P on the above insn: | |
2802 | the value isn't restored, so we don't want to tell dwarf2 | |
2803 | that it's been stored to stack, else EH handling info would | |
2804 | get confused. */ | |
2805 | } | |
2806 | ||
38173d38 | 2807 | /* For other setters of crtl->args.pretend_args_size, we |
d29b4b1b HPN |
2808 | just adjust the stack by leaving the remaining size in |
2809 | "pretend", handled below. */ | |
2810 | } | |
2811 | ||
2812 | /* Save SRP if not a leaf function. */ | |
2813 | if (return_address_on_stack) | |
2814 | { | |
2815 | insn = emit_insn (gen_rtx_SET (VOIDmode, | |
2816 | stack_pointer_rtx, | |
2817 | plus_constant (stack_pointer_rtx, | |
2818 | -4 - pretend))); | |
2819 | pretend = 0; | |
2820 | RTX_FRAME_RELATED_P (insn) = 1; | |
2821 | ||
2822 | mem = gen_rtx_MEM (SImode, stack_pointer_rtx); | |
2823 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
2824 | insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM)); | |
2825 | RTX_FRAME_RELATED_P (insn) = 1; | |
2826 | framesize += 4; | |
2827 | } | |
2828 | ||
2829 | /* Set up the frame pointer, if needed. */ | |
2830 | if (frame_pointer_needed) | |
2831 | { | |
2832 | insn = emit_insn (gen_rtx_SET (VOIDmode, | |
2833 | stack_pointer_rtx, | |
2834 | plus_constant (stack_pointer_rtx, | |
2835 | -4 - pretend))); | |
2836 | pretend = 0; | |
2837 | RTX_FRAME_RELATED_P (insn) = 1; | |
2838 | ||
2839 | mem = gen_rtx_MEM (SImode, stack_pointer_rtx); | |
2840 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
2841 | insn = emit_move_insn (mem, frame_pointer_rtx); | |
2842 | RTX_FRAME_RELATED_P (insn) = 1; | |
2843 | ||
2844 | insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); | |
2845 | RTX_FRAME_RELATED_P (insn) = 1; | |
2846 | ||
2847 | framesize += 4; | |
2848 | } | |
2849 | ||
2850 | /* Between frame-pointer and saved registers lie the area for local | |
2851 | variables. If we get here with "pretended" size remaining, count | |
2852 | it into the general stack size. */ | |
2853 | size += pretend; | |
2854 | ||
2855 | /* Get a contiguous sequence of registers, starting with R0, that need | |
2856 | to be saved. */ | |
2857 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
2858 | { | |
2859 | if (cris_reg_saved_in_regsave_area (regno, got_really_used)) | |
2860 | { | |
2861 | n_movem_regs++; | |
2862 | ||
2863 | /* Check if movem may be used for registers so far. */ | |
2864 | if (regno == last_movem_reg + 1) | |
2865 | /* Yes, update next expected register. */ | |
2866 | last_movem_reg = regno; | |
2867 | else | |
2868 | { | |
2869 | /* We cannot use movem for all registers. We have to flush | |
2870 | any movem:ed registers we got so far. */ | |
2871 | if (last_movem_reg != -1) | |
2872 | { | |
2873 | int n_saved | |
2874 | = (n_movem_regs == 1) ? 1 : last_movem_reg + 1; | |
2875 | ||
2876 | /* It is a win to use a side-effect assignment for | |
2877 | 64 <= size <= 128. But side-effect on movem was | |
2878 | not usable for CRIS v0..3. Also only do it if | |
2879 | side-effects insns are allowed. */ | |
2880 | if ((last_movem_reg + 1) * 4 + size >= 64 | |
2881 | && (last_movem_reg + 1) * 4 + size <= 128 | |
2882 | && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1) | |
2883 | && TARGET_SIDE_EFFECT_PREFIXES) | |
2884 | { | |
2885 | mem | |
2886 | = gen_rtx_MEM (SImode, | |
2887 | plus_constant (stack_pointer_rtx, | |
2888 | -(n_saved * 4 + size))); | |
2889 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
2890 | insn | |
2891 | = cris_emit_movem_store (mem, GEN_INT (n_saved), | |
2892 | -(n_saved * 4 + size), | |
2893 | true); | |
2894 | } | |
2895 | else | |
2896 | { | |
2897 | insn | |
2898 | = gen_rtx_SET (VOIDmode, | |
2899 | stack_pointer_rtx, | |
2900 | plus_constant (stack_pointer_rtx, | |
2901 | -(n_saved * 4 + size))); | |
2902 | insn = emit_insn (insn); | |
2903 | RTX_FRAME_RELATED_P (insn) = 1; | |
2904 | ||
2905 | mem = gen_rtx_MEM (SImode, stack_pointer_rtx); | |
2906 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
2907 | insn = cris_emit_movem_store (mem, GEN_INT (n_saved), | |
2908 | 0, true); | |
2909 | } | |
2910 | ||
2911 | framesize += n_saved * 4 + size; | |
2912 | last_movem_reg = -1; | |
2913 | size = 0; | |
2914 | } | |
2915 | ||
2916 | insn = emit_insn (gen_rtx_SET (VOIDmode, | |
2917 | stack_pointer_rtx, | |
2918 | plus_constant (stack_pointer_rtx, | |
2919 | -4 - size))); | |
2920 | RTX_FRAME_RELATED_P (insn) = 1; | |
2921 | ||
2922 | mem = gen_rtx_MEM (SImode, stack_pointer_rtx); | |
2923 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
2924 | insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, regno)); | |
2925 | RTX_FRAME_RELATED_P (insn) = 1; | |
2926 | ||
2927 | framesize += 4 + size; | |
2928 | size = 0; | |
2929 | } | |
2930 | } | |
2931 | } | |
2932 | ||
2933 | /* Check after, if we could movem all registers. This is the normal case. */ | |
2934 | if (last_movem_reg != -1) | |
2935 | { | |
2936 | int n_saved | |
2937 | = (n_movem_regs == 1) ? 1 : last_movem_reg + 1; | |
2938 | ||
2939 | /* Side-effect on movem was not usable for CRIS v0..3. Also only | |
2940 | do it if side-effects insns are allowed. */ | |
2941 | if ((last_movem_reg + 1) * 4 + size >= 64 | |
2942 | && (last_movem_reg + 1) * 4 + size <= 128 | |
2943 | && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1) | |
2944 | && TARGET_SIDE_EFFECT_PREFIXES) | |
2945 | { | |
2946 | mem | |
2947 | = gen_rtx_MEM (SImode, | |
2948 | plus_constant (stack_pointer_rtx, | |
2949 | -(n_saved * 4 + size))); | |
2950 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
2951 | insn = cris_emit_movem_store (mem, GEN_INT (n_saved), | |
2952 | -(n_saved * 4 + size), true); | |
2953 | } | |
2954 | else | |
2955 | { | |
2956 | insn | |
2957 | = gen_rtx_SET (VOIDmode, | |
2958 | stack_pointer_rtx, | |
2959 | plus_constant (stack_pointer_rtx, | |
2960 | -(n_saved * 4 + size))); | |
2961 | insn = emit_insn (insn); | |
2962 | RTX_FRAME_RELATED_P (insn) = 1; | |
2963 | ||
2964 | mem = gen_rtx_MEM (SImode, stack_pointer_rtx); | |
2965 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
2966 | insn = cris_emit_movem_store (mem, GEN_INT (n_saved), 0, true); | |
2967 | } | |
2968 | ||
2969 | framesize += n_saved * 4 + size; | |
2970 | /* We have to put outgoing argument space after regs. */ | |
2971 | if (cfoa_size) | |
2972 | { | |
2973 | insn = emit_insn (gen_rtx_SET (VOIDmode, | |
2974 | stack_pointer_rtx, | |
2975 | plus_constant (stack_pointer_rtx, | |
2976 | -cfoa_size))); | |
2977 | RTX_FRAME_RELATED_P (insn) = 1; | |
2978 | framesize += cfoa_size; | |
2979 | } | |
2980 | } | |
2981 | else if ((size + cfoa_size) > 0) | |
2982 | { | |
2983 | insn = emit_insn (gen_rtx_SET (VOIDmode, | |
2984 | stack_pointer_rtx, | |
2985 | plus_constant (stack_pointer_rtx, | |
2986 | -(cfoa_size + size)))); | |
2987 | RTX_FRAME_RELATED_P (insn) = 1; | |
2988 | framesize += size + cfoa_size; | |
2989 | } | |
2990 | ||
2991 | /* Set up the PIC register, if it is used. */ | |
2992 | if (got_really_used) | |
2993 | { | |
2994 | rtx got | |
2995 | = gen_rtx_UNSPEC (SImode, gen_rtvec (1, const0_rtx), CRIS_UNSPEC_GOT); | |
2996 | emit_move_insn (pic_offset_table_rtx, got); | |
2997 | ||
2998 | /* FIXME: This is a cover-up for flow2 messing up; it doesn't | |
2999 | follow exceptional paths and tries to delete the GOT load as | |
3000 | unused, if it isn't used on the non-exceptional paths. Other | |
3001 | ports have similar or other cover-ups, or plain bugs marking | |
3002 | the GOT register load as maybe-dead. To see this, remove the | |
3003 | line below and try libsupc++/vec.cc or a trivial | |
3004 | "static void y (); void x () {try {y ();} catch (...) {}}". */ | |
c41c1387 | 3005 | emit_use (pic_offset_table_rtx); |
d29b4b1b HPN |
3006 | } |
3007 | ||
3008 | if (cris_max_stackframe && framesize > cris_max_stackframe) | |
d4ee4d25 | 3009 | warning (0, "stackframe too big: %d bytes", framesize); |
d29b4b1b HPN |
3010 | } |
3011 | ||
04539954 HPN |
3012 | /* The expander for the epilogue pattern. */ |
3013 | ||
3014 | void | |
3015 | cris_expand_epilogue (void) | |
3016 | { | |
3017 | int regno; | |
3018 | int size = get_frame_size (); | |
3019 | int last_movem_reg = -1; | |
38173d38 JH |
3020 | int argspace_offset = crtl->outgoing_args_size; |
3021 | int pretend = crtl->args.pretend_args_size; | |
04539954 HPN |
3022 | rtx mem; |
3023 | bool return_address_on_stack = cris_return_address_on_stack (); | |
3024 | /* A reference may have been optimized out | |
3025 | (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1) | |
3026 | so check that it's still used. */ | |
c00fc5cf | 3027 | int got_really_used = false; |
04539954 HPN |
3028 | int n_movem_regs = 0; |
3029 | ||
3030 | if (!TARGET_PROLOGUE_EPILOGUE) | |
3031 | return; | |
3032 | ||
e3b5732b | 3033 | if (crtl->uses_pic_offset_table) |
c00fc5cf HPN |
3034 | { |
3035 | /* A reference may have been optimized out (like the abort () in | |
3036 | fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that | |
3037 | it's still used. */ | |
3038 | push_topmost_sequence (); | |
3039 | got_really_used | |
3040 | = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX); | |
3041 | pop_topmost_sequence (); | |
3042 | } | |
3043 | ||
04539954 HPN |
3044 | /* Align byte count of stack frame. */ |
3045 | if (TARGET_STACK_ALIGN) | |
3046 | size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1; | |
3047 | ||
3048 | /* Check how many saved regs we can movem. They start at r0 and must | |
3049 | be contiguous. */ | |
3050 | for (regno = 0; | |
3051 | regno < FIRST_PSEUDO_REGISTER; | |
3052 | regno++) | |
3053 | if (cris_reg_saved_in_regsave_area (regno, got_really_used)) | |
3054 | { | |
3055 | n_movem_regs++; | |
3056 | ||
3057 | if (regno == last_movem_reg + 1) | |
3058 | last_movem_reg = regno; | |
3059 | else | |
3060 | break; | |
3061 | } | |
3062 | ||
3063 | /* If there was only one register that really needed to be saved | |
3064 | through movem, don't use movem. */ | |
3065 | if (n_movem_regs == 1) | |
3066 | last_movem_reg = -1; | |
3067 | ||
3068 | /* Now emit "normal" move insns for all regs higher than the movem | |
3069 | regs. */ | |
3070 | for (regno = FIRST_PSEUDO_REGISTER - 1; | |
3071 | regno > last_movem_reg; | |
3072 | regno--) | |
3073 | if (cris_reg_saved_in_regsave_area (regno, got_really_used)) | |
3074 | { | |
752b602f HPN |
3075 | rtx insn; |
3076 | ||
04539954 HPN |
3077 | if (argspace_offset) |
3078 | { | |
3079 | /* There is an area for outgoing parameters located before | |
3080 | the saved registers. We have to adjust for that. */ | |
3081 | emit_insn (gen_rtx_SET (VOIDmode, | |
3082 | stack_pointer_rtx, | |
3083 | plus_constant (stack_pointer_rtx, | |
3084 | argspace_offset))); | |
3085 | /* Make sure we only do this once. */ | |
3086 | argspace_offset = 0; | |
3087 | } | |
3088 | ||
3089 | mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode, | |
3090 | stack_pointer_rtx)); | |
3091 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
752b602f HPN |
3092 | insn = emit_move_insn (gen_rtx_raw_REG (SImode, regno), mem); |
3093 | ||
3094 | /* Whenever we emit insns with post-incremented addresses | |
3095 | ourselves, we must add a post-inc note manually. */ | |
3096 | REG_NOTES (insn) | |
3097 | = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); | |
04539954 HPN |
3098 | } |
3099 | ||
3100 | /* If we have any movem-restore, do it now. */ | |
3101 | if (last_movem_reg != -1) | |
3102 | { | |
752b602f HPN |
3103 | rtx insn; |
3104 | ||
04539954 HPN |
3105 | if (argspace_offset) |
3106 | { | |
3107 | emit_insn (gen_rtx_SET (VOIDmode, | |
3108 | stack_pointer_rtx, | |
3109 | plus_constant (stack_pointer_rtx, | |
3110 | argspace_offset))); | |
3111 | argspace_offset = 0; | |
3112 | } | |
3113 | ||
3114 | mem = gen_rtx_MEM (SImode, | |
3115 | gen_rtx_POST_INC (SImode, stack_pointer_rtx)); | |
3116 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
752b602f HPN |
3117 | insn |
3118 | = emit_insn (cris_gen_movem_load (mem, | |
3119 | GEN_INT (last_movem_reg + 1), 0)); | |
3120 | /* Whenever we emit insns with post-incremented addresses | |
3121 | ourselves, we must add a post-inc note manually. */ | |
3122 | if (side_effects_p (PATTERN (insn))) | |
3123 | REG_NOTES (insn) | |
3124 | = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); | |
04539954 HPN |
3125 | } |
3126 | ||
3127 | /* If we don't clobber all of the allocated stack area (we've already | |
3128 | deallocated saved registers), GCC might want to schedule loads from | |
3129 | the stack to *after* the stack-pointer restore, which introduces an | |
3130 | interrupt race condition. This happened for the initial-value | |
3131 | SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of | |
3132 | other failure for that test). It also happened for the stack slot | |
3133 | for the return value in (one version of) | |
3134 | linux/fs/dcache.c:__d_lookup, at least with "-O2 | |
3135 | -fno-omit-frame-pointer". */ | |
3136 | ||
3137 | /* Restore frame pointer if necessary. */ | |
3138 | if (frame_pointer_needed) | |
3139 | { | |
752b602f HPN |
3140 | rtx insn; |
3141 | ||
04539954 HPN |
3142 | emit_insn (gen_cris_frame_deallocated_barrier ()); |
3143 | ||
3144 | emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); | |
3145 | mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode, | |
3146 | stack_pointer_rtx)); | |
3147 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
752b602f HPN |
3148 | insn = emit_move_insn (frame_pointer_rtx, mem); |
3149 | ||
3150 | /* Whenever we emit insns with post-incremented addresses | |
3151 | ourselves, we must add a post-inc note manually. */ | |
3152 | REG_NOTES (insn) | |
3153 | = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); | |
04539954 HPN |
3154 | } |
3155 | else if ((size + argspace_offset) != 0) | |
3156 | { | |
3157 | emit_insn (gen_cris_frame_deallocated_barrier ()); | |
3158 | ||
3159 | /* If there was no frame-pointer to restore sp from, we must | |
3160 | explicitly deallocate local variables. */ | |
3161 | ||
3162 | /* Handle space for outgoing parameters that hasn't been handled | |
3163 | yet. */ | |
3164 | size += argspace_offset; | |
3165 | ||
3166 | emit_insn (gen_rtx_SET (VOIDmode, | |
3167 | stack_pointer_rtx, | |
3168 | plus_constant (stack_pointer_rtx, size))); | |
3169 | } | |
3170 | ||
3171 | /* If this function has no pushed register parameters | |
3172 | (stdargs/varargs), and if it is not a leaf function, then we have | |
3173 | the return address on the stack. */ | |
3174 | if (return_address_on_stack && pretend == 0) | |
3175 | { | |
e3b5732b | 3176 | if (TARGET_V32 || crtl->calls_eh_return) |
04539954 HPN |
3177 | { |
3178 | rtx mem; | |
752b602f | 3179 | rtx insn; |
04539954 HPN |
3180 | rtx srpreg = gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM); |
3181 | mem = gen_rtx_MEM (SImode, | |
3182 | gen_rtx_POST_INC (SImode, | |
3183 | stack_pointer_rtx)); | |
3184 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
752b602f HPN |
3185 | insn = emit_move_insn (srpreg, mem); |
3186 | ||
3187 | /* Whenever we emit insns with post-incremented addresses | |
3188 | ourselves, we must add a post-inc note manually. */ | |
3189 | REG_NOTES (insn) | |
3190 | = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); | |
04539954 | 3191 | |
e3b5732b | 3192 | if (crtl->calls_eh_return) |
c31500c2 HPN |
3193 | emit_insn (gen_addsi3 (stack_pointer_rtx, |
3194 | stack_pointer_rtx, | |
3195 | gen_rtx_raw_REG (SImode, | |
3196 | CRIS_STACKADJ_REG))); | |
04539954 HPN |
3197 | cris_expand_return (false); |
3198 | } | |
3199 | else | |
3200 | cris_expand_return (true); | |
3201 | ||
3202 | return; | |
3203 | } | |
3204 | ||
3205 | /* If we pushed some register parameters, then adjust the stack for | |
3206 | them. */ | |
3207 | if (pretend != 0) | |
3208 | { | |
3209 | /* If SRP is stored on the way, we need to restore it first. */ | |
3210 | if (return_address_on_stack) | |
3211 | { | |
3212 | rtx mem; | |
3213 | rtx srpreg = gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM); | |
752b602f HPN |
3214 | rtx insn; |
3215 | ||
04539954 HPN |
3216 | mem = gen_rtx_MEM (SImode, |
3217 | gen_rtx_POST_INC (SImode, | |
3218 | stack_pointer_rtx)); | |
3219 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
752b602f HPN |
3220 | insn = emit_move_insn (srpreg, mem); |
3221 | ||
3222 | /* Whenever we emit insns with post-incremented addresses | |
3223 | ourselves, we must add a post-inc note manually. */ | |
3224 | REG_NOTES (insn) | |
3225 | = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); | |
04539954 HPN |
3226 | } |
3227 | ||
3228 | emit_insn (gen_rtx_SET (VOIDmode, | |
3229 | stack_pointer_rtx, | |
3230 | plus_constant (stack_pointer_rtx, pretend))); | |
3231 | } | |
3232 | ||
3233 | /* Perform the "physical" unwinding that the EH machinery calculated. */ | |
e3b5732b | 3234 | if (crtl->calls_eh_return) |
04539954 HPN |
3235 | emit_insn (gen_addsi3 (stack_pointer_rtx, |
3236 | stack_pointer_rtx, | |
3237 | gen_rtx_raw_REG (SImode, | |
3238 | CRIS_STACKADJ_REG))); | |
3239 | cris_expand_return (false); | |
3240 | } | |
3241 | ||
3242 | /* Worker function for generating movem from mem for load_multiple. */ | |
3243 | ||
3244 | rtx | |
d29b4b1b | 3245 | cris_gen_movem_load (rtx src, rtx nregs_rtx, int nprefix) |
04539954 HPN |
3246 | { |
3247 | int nregs = INTVAL (nregs_rtx); | |
3248 | rtvec vec; | |
3249 | int eltno = 1; | |
3250 | int i; | |
d29b4b1b | 3251 | rtx srcreg = XEXP (src, 0); |
04539954 HPN |
3252 | unsigned int regno = nregs - 1; |
3253 | int regno_inc = -1; | |
3254 | ||
c31500c2 HPN |
3255 | if (TARGET_V32) |
3256 | { | |
3257 | regno = 0; | |
3258 | regno_inc = 1; | |
3259 | } | |
3260 | ||
04539954 HPN |
3261 | if (GET_CODE (srcreg) == POST_INC) |
3262 | srcreg = XEXP (srcreg, 0); | |
3263 | ||
b6c34129 | 3264 | CRIS_ASSERT (REG_P (srcreg)); |
04539954 HPN |
3265 | |
3266 | /* Don't use movem for just one insn. The insns are equivalent except | |
d29b4b1b HPN |
3267 | for the pipeline hazard (on v32); movem does not forward the loaded |
3268 | registers so there's a three cycles penalty for their use. */ | |
04539954 | 3269 | if (nregs == 1) |
d29b4b1b | 3270 | return gen_movsi (gen_rtx_REG (SImode, 0), src); |
04539954 HPN |
3271 | |
3272 | vec = rtvec_alloc (nprefix + nregs | |
d29b4b1b | 3273 | + (GET_CODE (XEXP (src, 0)) == POST_INC)); |
04539954 | 3274 | |
d29b4b1b | 3275 | if (GET_CODE (XEXP (src, 0)) == POST_INC) |
04539954 HPN |
3276 | { |
3277 | RTVEC_ELT (vec, nprefix + 1) | |
3278 | = gen_rtx_SET (VOIDmode, srcreg, plus_constant (srcreg, nregs * 4)); | |
3279 | eltno++; | |
3280 | } | |
3281 | ||
d29b4b1b HPN |
3282 | src = replace_equiv_address (src, srcreg); |
3283 | RTVEC_ELT (vec, nprefix) | |
3284 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno), src); | |
3285 | regno += regno_inc; | |
3286 | ||
04539954 HPN |
3287 | for (i = 1; i < nregs; i++, eltno++) |
3288 | { | |
3289 | RTVEC_ELT (vec, nprefix + eltno) | |
3290 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno), | |
3291 | adjust_address_nv (src, SImode, i * 4)); | |
3292 | regno += regno_inc; | |
3293 | } | |
3294 | ||
3295 | return gen_rtx_PARALLEL (VOIDmode, vec); | |
3296 | } | |
3297 | ||
d29b4b1b HPN |
3298 | /* Worker function for generating movem to mem. If FRAME_RELATED, notes |
3299 | are added that the dwarf2 machinery understands. */ | |
3300 | ||
3301 | rtx | |
3302 | cris_emit_movem_store (rtx dest, rtx nregs_rtx, int increment, | |
3303 | bool frame_related) | |
3304 | { | |
3305 | int nregs = INTVAL (nregs_rtx); | |
3306 | rtvec vec; | |
3307 | int eltno = 1; | |
3308 | int i; | |
3309 | rtx insn; | |
3310 | rtx destreg = XEXP (dest, 0); | |
3311 | unsigned int regno = nregs - 1; | |
3312 | int regno_inc = -1; | |
3313 | ||
c31500c2 HPN |
3314 | if (TARGET_V32) |
3315 | { | |
3316 | regno = 0; | |
3317 | regno_inc = 1; | |
3318 | } | |
3319 | ||
d29b4b1b HPN |
3320 | if (GET_CODE (destreg) == POST_INC) |
3321 | increment += nregs * 4; | |
3322 | ||
3323 | if (GET_CODE (destreg) == POST_INC || GET_CODE (destreg) == PLUS) | |
3324 | destreg = XEXP (destreg, 0); | |
3325 | ||
b6c34129 | 3326 | CRIS_ASSERT (REG_P (destreg)); |
d29b4b1b HPN |
3327 | |
3328 | /* Don't use movem for just one insn. The insns are equivalent except | |
3329 | for the pipeline hazard (on v32); movem does not forward the loaded | |
3330 | registers so there's a three cycles penalty for use. */ | |
3331 | if (nregs == 1) | |
3332 | { | |
3333 | rtx mov = gen_rtx_SET (VOIDmode, dest, gen_rtx_REG (SImode, 0)); | |
3334 | ||
3335 | if (increment == 0) | |
3336 | { | |
3337 | insn = emit_insn (mov); | |
3338 | if (frame_related) | |
3339 | RTX_FRAME_RELATED_P (insn) = 1; | |
3340 | return insn; | |
3341 | } | |
3342 | ||
3343 | /* If there was a request for a side-effect, create the ordinary | |
3344 | parallel. */ | |
3345 | vec = rtvec_alloc (2); | |
3346 | ||
3347 | RTVEC_ELT (vec, 0) = mov; | |
3348 | RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, destreg, | |
3349 | plus_constant (destreg, increment)); | |
3350 | if (frame_related) | |
3351 | { | |
3352 | RTX_FRAME_RELATED_P (mov) = 1; | |
3353 | RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1; | |
3354 | } | |
3355 | } | |
3356 | else | |
3357 | { | |
3358 | vec = rtvec_alloc (nregs + (increment != 0 ? 1 : 0)); | |
3359 | RTVEC_ELT (vec, 0) | |
3360 | = gen_rtx_SET (VOIDmode, | |
3361 | replace_equiv_address (dest, | |
3362 | plus_constant (destreg, | |
3363 | increment)), | |
3364 | gen_rtx_REG (SImode, regno)); | |
3365 | regno += regno_inc; | |
3366 | ||
3367 | /* The dwarf2 info wants this mark on each component in a parallel | |
3368 | that's part of the prologue (though it's optional on the first | |
3369 | component). */ | |
3370 | if (frame_related) | |
3371 | RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 0)) = 1; | |
3372 | ||
3373 | if (increment != 0) | |
3374 | { | |
3375 | RTVEC_ELT (vec, 1) | |
3376 | = gen_rtx_SET (VOIDmode, destreg, | |
3377 | plus_constant (destreg, | |
3378 | increment != 0 | |
3379 | ? increment : nregs * 4)); | |
3380 | eltno++; | |
3381 | ||
3382 | if (frame_related) | |
3383 | RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1; | |
3384 | ||
3385 | /* Don't call adjust_address_nv on a post-incremented address if | |
3386 | we can help it. */ | |
3387 | if (GET_CODE (XEXP (dest, 0)) == POST_INC) | |
3388 | dest = replace_equiv_address (dest, destreg); | |
3389 | } | |
3390 | ||
3391 | for (i = 1; i < nregs; i++, eltno++) | |
3392 | { | |
3393 | RTVEC_ELT (vec, eltno) | |
3394 | = gen_rtx_SET (VOIDmode, adjust_address_nv (dest, SImode, i * 4), | |
3395 | gen_rtx_REG (SImode, regno)); | |
3396 | if (frame_related) | |
3397 | RTX_FRAME_RELATED_P (RTVEC_ELT (vec, eltno)) = 1; | |
3398 | regno += regno_inc; | |
3399 | } | |
3400 | } | |
3401 | ||
3402 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, vec)); | |
3403 | ||
3404 | /* Because dwarf2out.c handles the insns in a parallel as a sequence, | |
3405 | we need to keep the stack adjustment separate, after the | |
3406 | MEM-setters. Else the stack-adjustment in the second component of | |
3407 | the parallel would be mishandled; the offsets for the SETs that | |
3408 | follow it would be wrong. We prepare for this by adding a | |
3409 | REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE | |
3410 | followed by the increment. Note that we have FRAME_RELATED_P on | |
3411 | all the SETs, including the original stack adjustment SET in the | |
3412 | parallel. */ | |
3413 | if (frame_related) | |
3414 | { | |
3415 | if (increment != 0) | |
3416 | { | |
3417 | rtx seq = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (nregs + 1)); | |
dfc0fb23 | 3418 | XVECEXP (seq, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn), 0, 0)); |
d29b4b1b | 3419 | for (i = 1; i < nregs; i++) |
dfc0fb23 HPN |
3420 | XVECEXP (seq, 0, i) |
3421 | = copy_rtx (XVECEXP (PATTERN (insn), 0, i + 1)); | |
3422 | XVECEXP (seq, 0, nregs) = copy_rtx (XVECEXP (PATTERN (insn), 0, 1)); | |
d29b4b1b HPN |
3423 | REG_NOTES (insn) |
3424 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, seq, | |
3425 | REG_NOTES (insn)); | |
3426 | } | |
3427 | ||
3428 | RTX_FRAME_RELATED_P (insn) = 1; | |
3429 | } | |
3430 | ||
3431 | return insn; | |
3432 | } | |
3433 | ||
c00fc5cf HPN |
3434 | /* Worker function for expanding the address for PIC function calls. */ |
3435 | ||
3436 | void | |
3437 | cris_expand_pic_call_address (rtx *opp) | |
3438 | { | |
3439 | rtx op = *opp; | |
3440 | ||
3441 | gcc_assert (MEM_P (op)); | |
3442 | op = XEXP (op, 0); | |
3443 | ||
3444 | /* It might be that code can be generated that jumps to 0 (or to a | |
3445 | specific address). Don't die on that. (There is a | |
3446 | testcase.) */ | |
31af2dca | 3447 | if (CONSTANT_ADDRESS_P (op) && !CONST_INT_P (op)) |
c00fc5cf HPN |
3448 | { |
3449 | enum cris_pic_symbol_type t = cris_pic_symbol_type_of (op); | |
3450 | ||
b3a13419 | 3451 | CRIS_ASSERT (can_create_pseudo_p ()); |
c00fc5cf HPN |
3452 | |
3453 | /* For local symbols (non-PLT), just get the plain symbol | |
3454 | reference into a register. For symbols that can be PLT, make | |
3455 | them PLT. */ | |
c31500c2 HPN |
3456 | if (t == cris_rel_symbol) |
3457 | { | |
3458 | /* For v32, we're fine as-is; just PICify the symbol. Forcing | |
3459 | into a register caused performance regression for 3.2.1, | |
3460 | observable in __floatdidf and elsewhere in libgcc. */ | |
3461 | if (TARGET_V32) | |
3462 | { | |
3463 | rtx sym = GET_CODE (op) != CONST ? op : get_related_value (op); | |
3464 | HOST_WIDE_INT offs = get_integer_term (op); | |
3465 | ||
3466 | /* We can't get calls to sym+N, N integer, can we? */ | |
3467 | gcc_assert (offs == 0); | |
3468 | ||
3469 | op = gen_rtx_CONST (Pmode, | |
3470 | gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), | |
3471 | CRIS_UNSPEC_PCREL)); | |
3472 | } | |
3473 | else | |
3474 | op = force_reg (Pmode, op); | |
3475 | } | |
c00fc5cf HPN |
3476 | else if (t == cris_got_symbol) |
3477 | { | |
3478 | if (TARGET_AVOID_GOTPLT) | |
3479 | { | |
3480 | /* Change a "jsr sym" into (allocate register rM, rO) | |
c31500c2 HPN |
3481 | "move.d (const (unspec [sym rPIC] CRIS_UNSPEC_PLT_GOTREL)),rM" |
3482 | "add.d rPIC,rM,rO", "jsr rO" for pre-v32 and | |
3483 | "jsr (const (unspec [sym rPIC] CRIS_UNSPEC_PLT_PCREL))" | |
3484 | for v32. */ | |
c00fc5cf | 3485 | rtx tem, rm, ro; |
b3a13419 | 3486 | gcc_assert (can_create_pseudo_p ()); |
e3b5732b | 3487 | crtl->uses_pic_offset_table = 1; |
c31500c2 HPN |
3488 | tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op), |
3489 | TARGET_V32 | |
3490 | ? CRIS_UNSPEC_PLT_PCREL | |
3491 | : CRIS_UNSPEC_PLT_GOTREL); | |
3492 | tem = gen_rtx_CONST (Pmode, tem); | |
3493 | if (TARGET_V32) | |
3494 | op = tem; | |
3495 | else | |
3496 | { | |
3497 | rm = gen_reg_rtx (Pmode); | |
3498 | emit_move_insn (rm, tem); | |
3499 | ro = gen_reg_rtx (Pmode); | |
3500 | if (expand_binop (Pmode, add_optab, rm, | |
3501 | pic_offset_table_rtx, | |
3502 | ro, 0, OPTAB_LIB_WIDEN) != ro) | |
3503 | internal_error ("expand_binop failed in movsi got"); | |
3504 | op = ro; | |
3505 | } | |
c00fc5cf HPN |
3506 | } |
3507 | else | |
3508 | { | |
3509 | /* Change a "jsr sym" into (allocate register rM, rO) | |
c31500c2 | 3510 | "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOTREAD)),rM" |
c00fc5cf HPN |
3511 | "add.d rPIC,rM,rO" "jsr [rO]" with the memory access |
3512 | marked as not trapping and not aliasing. No "move.d | |
3513 | [rO],rP" as that would invite to re-use of a value | |
3514 | that should not be reused. FIXME: Need a peephole2 | |
3515 | for cases when this is cse:d from the call, to change | |
3516 | back to just get the PLT entry address, so we don't | |
3517 | resolve the same symbol over and over (the memory | |
3518 | access of the PLTGOT isn't constant). */ | |
3519 | rtx tem, mem, rm, ro; | |
3520 | ||
b3a13419 | 3521 | gcc_assert (can_create_pseudo_p ()); |
e3b5732b | 3522 | crtl->uses_pic_offset_table = 1; |
c00fc5cf HPN |
3523 | tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op), |
3524 | CRIS_UNSPEC_PLTGOTREAD); | |
3525 | rm = gen_reg_rtx (Pmode); | |
3526 | emit_move_insn (rm, gen_rtx_CONST (Pmode, tem)); | |
3527 | ro = gen_reg_rtx (Pmode); | |
3528 | if (expand_binop (Pmode, add_optab, rm, | |
3529 | pic_offset_table_rtx, | |
3530 | ro, 0, OPTAB_LIB_WIDEN) != ro) | |
3531 | internal_error ("expand_binop failed in movsi got"); | |
3532 | mem = gen_rtx_MEM (Pmode, ro); | |
3533 | ||
3534 | /* This MEM doesn't alias anything. Whether it aliases | |
3535 | other same symbols is unimportant. */ | |
3536 | set_mem_alias_set (mem, new_alias_set ()); | |
3537 | MEM_NOTRAP_P (mem) = 1; | |
3538 | op = mem; | |
3539 | } | |
3540 | } | |
3541 | else | |
3542 | /* Can't possibly get a GOT-needing-fixup for a function-call, | |
3543 | right? */ | |
3544 | fatal_insn ("Unidentifiable call op", op); | |
3545 | ||
3546 | *opp = replace_equiv_address (*opp, op); | |
3547 | } | |
3548 | } | |
3549 | ||
7faa3eb8 HPN |
3550 | /* Make sure operands are in the right order for an addsi3 insn as |
3551 | generated by a define_split. A MEM as the first operand isn't | |
3552 | recognized by addsi3 after reload. OPERANDS contains the operands, | |
3553 | with the first at OPERANDS[N] and the second at OPERANDS[N+1]. */ | |
3554 | ||
3555 | void | |
3556 | cris_order_for_addsi3 (rtx *operands, int n) | |
3557 | { | |
3558 | if (MEM_P (operands[n])) | |
3559 | { | |
3560 | rtx tem = operands[n]; | |
3561 | operands[n] = operands[n + 1]; | |
3562 | operands[n + 1] = tem; | |
3563 | } | |
3564 | } | |
3565 | ||
453bd0f5 HPN |
3566 | /* Use from within code, from e.g. PRINT_OPERAND and |
3567 | PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit | |
3568 | different things depending on whether code operand or constant is | |
3569 | emitted. */ | |
0b85d816 | 3570 | |
453bd0f5 | 3571 | static void |
6640377c | 3572 | cris_output_addr_const (FILE *file, rtx x) |
0b85d816 | 3573 | { |
453bd0f5 HPN |
3574 | in_code++; |
3575 | output_addr_const (file, x); | |
3576 | in_code--; | |
3577 | } | |
0b85d816 | 3578 | |
453bd0f5 | 3579 | /* Worker function for ASM_OUTPUT_SYMBOL_REF. */ |
0b85d816 | 3580 | |
453bd0f5 HPN |
3581 | void |
3582 | cris_asm_output_symbol_ref (FILE *file, rtx x) | |
3583 | { | |
c00fc5cf HPN |
3584 | gcc_assert (GET_CODE (x) == SYMBOL_REF); |
3585 | ||
453bd0f5 HPN |
3586 | if (flag_pic && in_code > 0) |
3587 | { | |
c00fc5cf HPN |
3588 | const char *origstr = XSTR (x, 0); |
3589 | const char *str; | |
3590 | str = (* targetm.strip_name_encoding) (origstr); | |
3591 | assemble_name (file, str); | |
3592 | ||
3593 | /* Sanity check. */ | |
e3b5732b | 3594 | if (!TARGET_V32 && !crtl->uses_pic_offset_table) |
c00fc5cf | 3595 | output_operand_lossage ("PIC register isn't set up"); |
453bd0f5 HPN |
3596 | } |
3597 | else | |
3598 | assemble_name (file, XSTR (x, 0)); | |
3599 | } | |
0b85d816 | 3600 | |
453bd0f5 | 3601 | /* Worker function for ASM_OUTPUT_LABEL_REF. */ |
0b85d816 | 3602 | |
453bd0f5 HPN |
3603 | void |
3604 | cris_asm_output_label_ref (FILE *file, char *buf) | |
3605 | { | |
3606 | if (flag_pic && in_code > 0) | |
3607 | { | |
453bd0f5 | 3608 | assemble_name (file, buf); |
0b85d816 | 3609 | |
453bd0f5 | 3610 | /* Sanity check. */ |
e3b5732b | 3611 | if (!TARGET_V32 && !crtl->uses_pic_offset_table) |
453bd0f5 HPN |
3612 | internal_error ("emitting PIC operand, but PIC register isn't set up"); |
3613 | } | |
3614 | else | |
3615 | assemble_name (file, buf); | |
3616 | } | |
0b85d816 | 3617 | |
453bd0f5 | 3618 | /* Worker function for OUTPUT_ADDR_CONST_EXTRA. */ |
0b85d816 | 3619 | |
453bd0f5 | 3620 | bool |
c00fc5cf | 3621 | cris_output_addr_const_extra (FILE *file, rtx xconst) |
453bd0f5 | 3622 | { |
c00fc5cf | 3623 | switch (GET_CODE (xconst)) |
453bd0f5 | 3624 | { |
c00fc5cf | 3625 | rtx x; |
0b85d816 | 3626 | |
453bd0f5 | 3627 | case UNSPEC: |
c00fc5cf HPN |
3628 | x = XVECEXP (xconst, 0, 0); |
3629 | CRIS_ASSERT (GET_CODE (x) == SYMBOL_REF | |
3630 | || GET_CODE (x) == LABEL_REF | |
3631 | || GET_CODE (x) == CONST); | |
3632 | output_addr_const (file, x); | |
3633 | switch (XINT (xconst, 1)) | |
0b85d816 | 3634 | { |
c31500c2 HPN |
3635 | case CRIS_UNSPEC_PCREL: |
3636 | /* We only get this with -fpic/PIC to tell it apart from an | |
3637 | invalid symbol. We can't tell here, but it should only | |
3638 | be the operand of a call or movsi. */ | |
3639 | gcc_assert (TARGET_V32 && flag_pic); | |
3640 | break; | |
3641 | ||
3642 | case CRIS_UNSPEC_PLT_PCREL: | |
3643 | gcc_assert (TARGET_V32); | |
3644 | fprintf (file, ":PLT"); | |
3645 | break; | |
3646 | ||
3647 | case CRIS_UNSPEC_PLT_GOTREL: | |
3648 | gcc_assert (!TARGET_V32); | |
453bd0f5 | 3649 | fprintf (file, ":PLTG"); |
c00fc5cf | 3650 | break; |
0b85d816 | 3651 | |
c00fc5cf | 3652 | case CRIS_UNSPEC_GOTREL: |
c31500c2 | 3653 | gcc_assert (!TARGET_V32); |
c00fc5cf HPN |
3654 | fprintf (file, ":GOTOFF"); |
3655 | break; | |
453bd0f5 | 3656 | |
c00fc5cf | 3657 | case CRIS_UNSPEC_GOTREAD: |
453bd0f5 | 3658 | if (flag_pic == 1) |
c00fc5cf | 3659 | fprintf (file, ":GOT16"); |
453bd0f5 | 3660 | else |
c00fc5cf HPN |
3661 | fprintf (file, ":GOT"); |
3662 | break; | |
3663 | ||
3664 | case CRIS_UNSPEC_PLTGOTREAD: | |
3665 | if (flag_pic == 1) | |
3666 | fprintf (file, CRIS_GOTPLT_SUFFIX "16"); | |
3667 | else | |
3668 | fprintf (file, CRIS_GOTPLT_SUFFIX); | |
3669 | break; | |
3670 | ||
3671 | default: | |
3672 | gcc_unreachable (); | |
0b85d816 | 3673 | } |
453bd0f5 | 3674 | return true; |
0b85d816 HPN |
3675 | |
3676 | default: | |
453bd0f5 | 3677 | return false; |
0b85d816 HPN |
3678 | } |
3679 | } | |
3680 | ||
a2fef3a4 KH |
3681 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ |
3682 | ||
3683 | static rtx | |
3684 | cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
3685 | int incoming ATTRIBUTE_UNUSED) | |
3686 | { | |
3687 | return gen_rtx_REG (Pmode, CRIS_STRUCT_VALUE_REGNUM); | |
3688 | } | |
3689 | ||
558d352a KH |
3690 | /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */ |
3691 | ||
3692 | static void | |
3693 | cris_setup_incoming_varargs (CUMULATIVE_ARGS *ca, | |
3694 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
3695 | tree type ATTRIBUTE_UNUSED, | |
3696 | int *pretend_arg_size, | |
3697 | int second_time) | |
3698 | { | |
3699 | if (ca->regs < CRIS_MAX_ARGS_IN_REGS) | |
558d352a | 3700 | { |
d29b4b1b HPN |
3701 | int stdarg_regs = CRIS_MAX_ARGS_IN_REGS - ca->regs; |
3702 | cfun->machine->stdarg_regs = stdarg_regs; | |
3703 | *pretend_arg_size = stdarg_regs * 4; | |
558d352a | 3704 | } |
d29b4b1b HPN |
3705 | |
3706 | if (TARGET_PDEBUG) | |
3707 | fprintf (asm_out_file, | |
3708 | "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n", | |
3709 | ca->regs, *pretend_arg_size, second_time); | |
558d352a KH |
3710 | } |
3711 | ||
8cd5a4e0 RH |
3712 | /* Return true if TYPE must be passed by invisible reference. |
3713 | For cris, we pass <= 8 bytes by value, others by reference. */ | |
3714 | ||
3715 | static bool | |
3716 | cris_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, | |
586de218 | 3717 | enum machine_mode mode, const_tree type, |
8cd5a4e0 RH |
3718 | bool named ATTRIBUTE_UNUSED) |
3719 | { | |
3720 | return (targetm.calls.must_pass_in_stack (mode, type) | |
3721 | || CRIS_FUNCTION_ARG_SIZE (mode, type) > 8); | |
3722 | } | |
3723 | ||
3724 | ||
78a52f11 RH |
3725 | static int |
3726 | cris_arg_partial_bytes (CUMULATIVE_ARGS *ca, enum machine_mode mode, | |
3727 | tree type, bool named ATTRIBUTE_UNUSED) | |
3728 | { | |
3729 | if (ca->regs == CRIS_MAX_ARGS_IN_REGS - 1 | |
3730 | && !targetm.calls.must_pass_in_stack (mode, type) | |
3731 | && CRIS_FUNCTION_ARG_SIZE (mode, type) > 4 | |
3732 | && CRIS_FUNCTION_ARG_SIZE (mode, type) <= 8) | |
3733 | return UNITS_PER_WORD; | |
3734 | else | |
3735 | return 0; | |
3736 | } | |
3737 | ||
f60c7155 HPN |
3738 | /* Worker function for TARGET_MD_ASM_CLOBBERS. */ |
3739 | ||
3740 | static tree | |
f9968e3e | 3741 | cris_md_asm_clobbers (tree outputs, tree inputs, tree in_clobbers) |
f60c7155 | 3742 | { |
61158923 | 3743 | HARD_REG_SET mof_set; |
f9968e3e | 3744 | tree clobbers; |
61158923 HPN |
3745 | tree t; |
3746 | ||
3747 | CLEAR_HARD_REG_SET (mof_set); | |
3748 | SET_HARD_REG_BIT (mof_set, CRIS_MOF_REGNUM); | |
3749 | ||
f9968e3e HPN |
3750 | /* For the time being, all asms clobber condition codes. Revisit when |
3751 | there's a reasonable use for inputs/outputs that mention condition | |
3752 | codes. */ | |
3753 | clobbers | |
3754 | = tree_cons (NULL_TREE, | |
3755 | build_string (strlen (reg_names[CRIS_CC0_REGNUM]), | |
3756 | reg_names[CRIS_CC0_REGNUM]), | |
3757 | in_clobbers); | |
3758 | ||
61158923 HPN |
3759 | for (t = outputs; t != NULL; t = TREE_CHAIN (t)) |
3760 | { | |
3761 | tree val = TREE_VALUE (t); | |
3762 | ||
3763 | /* The constraint letter for the singleton register class of MOF | |
3764 | is 'h'. If it's mentioned in the constraints, the asm is | |
3765 | MOF-aware and adding it to the clobbers would cause it to have | |
3766 | impossible constraints. */ | |
3767 | if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t))), | |
3768 | 'h') != NULL | |
91b4415a | 3769 | || tree_overlaps_hard_reg_set (val, &mof_set) != NULL_TREE) |
61158923 HPN |
3770 | return clobbers; |
3771 | } | |
3772 | ||
3773 | for (t = inputs; t != NULL; t = TREE_CHAIN (t)) | |
3774 | { | |
3775 | tree val = TREE_VALUE (t); | |
3776 | ||
3777 | if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t))), | |
3778 | 'h') != NULL | |
91b4415a | 3779 | || tree_overlaps_hard_reg_set (val, &mof_set) != NULL_TREE) |
61158923 HPN |
3780 | return clobbers; |
3781 | } | |
3782 | ||
f60c7155 HPN |
3783 | return tree_cons (NULL_TREE, |
3784 | build_string (strlen (reg_names[CRIS_MOF_REGNUM]), | |
3785 | reg_names[CRIS_MOF_REGNUM]), | |
3786 | clobbers); | |
3787 | } | |
78a52f11 | 3788 | |
0b85d816 HPN |
3789 | #if 0 |
3790 | /* Various small functions to replace macros. Only called from a | |
3791 | debugger. They might collide with gcc functions or system functions, | |
3792 | so only emit them when '#if 1' above. */ | |
3793 | ||
6640377c | 3794 | enum rtx_code Get_code (rtx); |
0b85d816 HPN |
3795 | |
3796 | enum rtx_code | |
6640377c | 3797 | Get_code (rtx x) |
0b85d816 HPN |
3798 | { |
3799 | return GET_CODE (x); | |
3800 | } | |
3801 | ||
6640377c | 3802 | const char *Get_mode (rtx); |
0b85d816 HPN |
3803 | |
3804 | const char * | |
6640377c | 3805 | Get_mode (rtx x) |
0b85d816 HPN |
3806 | { |
3807 | return GET_MODE_NAME (GET_MODE (x)); | |
3808 | } | |
3809 | ||
6640377c | 3810 | rtx Xexp (rtx, int); |
0b85d816 HPN |
3811 | |
3812 | rtx | |
6640377c | 3813 | Xexp (rtx x, int n) |
0b85d816 HPN |
3814 | { |
3815 | return XEXP (x, n); | |
3816 | } | |
3817 | ||
6640377c | 3818 | rtx Xvecexp (rtx, int, int); |
0b85d816 HPN |
3819 | |
3820 | rtx | |
6640377c | 3821 | Xvecexp (rtx x, int n, int m) |
117b0c0a | 3822 | { |
0b85d816 HPN |
3823 | return XVECEXP (x, n, m); |
3824 | } | |
3825 | ||
6640377c | 3826 | int Get_rtx_len (rtx); |
0b85d816 HPN |
3827 | |
3828 | int | |
6640377c | 3829 | Get_rtx_len (rtx x) |
0b85d816 HPN |
3830 | { |
3831 | return GET_RTX_LENGTH (GET_CODE (x)); | |
3832 | } | |
3833 | ||
3834 | /* Use upper-case to distinguish from local variables that are sometimes | |
3835 | called next_insn and prev_insn. */ | |
3836 | ||
6640377c | 3837 | rtx Next_insn (rtx); |
0b85d816 HPN |
3838 | |
3839 | rtx | |
6640377c | 3840 | Next_insn (rtx insn) |
0b85d816 HPN |
3841 | { |
3842 | return NEXT_INSN (insn); | |
3843 | } | |
3844 | ||
6640377c | 3845 | rtx Prev_insn (rtx); |
0b85d816 HPN |
3846 | |
3847 | rtx | |
6640377c | 3848 | Prev_insn (rtx insn) |
0b85d816 HPN |
3849 | { |
3850 | return PREV_INSN (insn); | |
3851 | } | |
3852 | #endif | |
3853 | ||
e2500fed GK |
3854 | #include "gt-cris.h" |
3855 | ||
0b85d816 HPN |
3856 | /* |
3857 | * Local variables: | |
3858 | * eval: (c-set-style "gnu") | |
3859 | * indent-tabs-mode: t | |
3860 | * End: | |
3861 | */ |