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0b85d816 | 1 | ;; GCC machine description for CRIS cpu cores. |
1c563bed KH |
2 | ;; Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004 |
3 | ;; Free Software Foundation, Inc. | |
0b85d816 HPN |
4 | ;; Contributed by Axis Communications. |
5 | ||
6 | ;; This file is part of GCC. | |
7 | ;; | |
8 | ;; GCC is free software; you can redistribute it and/or modify | |
9 | ;; it under the terms of the GNU General Public License as published by | |
10 | ;; the Free Software Foundation; either version 2, or (at your option) | |
11 | ;; any later version. | |
12 | ;; | |
13 | ;; GCC is distributed in the hope that it will be useful, | |
14 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ;; GNU General Public License for more details. | |
17 | ;; | |
18 | ;; You should have received a copy of the GNU General Public License | |
19 | ;; along with GCC; see the file COPYING. If not, write to | |
20 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, | |
21 | ;; Boston, MA 02111-1307, USA. | |
22 | ||
23 | ;; The original PO technology requires these to be ordered by speed, | |
24 | ;; so that assigner will pick the fastest. | |
25 | ||
26 | ;; See files "md.texi" and "rtl.def" for documentation on define_insn, | |
27 | ;; match_*, et. al. | |
28 | ;; | |
29 | ;; The function cris_notice_update_cc in cris.c handles condition code | |
30 | ;; updates for most instructions, helped by the "cc" attribute. | |
31 | ||
32 | ;; There are several instructions that are orthogonal in size, and seems | |
33 | ;; they could be matched by a single pattern without a specified size | |
34 | ;; for the operand that is orthogonal. However, this did not work on | |
839a4992 | 35 | ;; gcc-2.7.2 (and probably not on gcc-2.8.1), relating to that when a |
0b85d816 HPN |
36 | ;; constant is substituted into an operand, the actual mode must be |
37 | ;; deduced from the pattern. There is reasonable hope that that has been | |
d2f55c5c | 38 | ;; fixed, so FIXME: try again. |
0b85d816 HPN |
39 | |
40 | ;; You will notice that three-operand alternatives ("=r", "r", "!To") | |
41 | ;; are marked with a "!" constraint modifier to avoid being reloaded | |
42 | ;; into. This is because gcc would otherwise prefer to use the constant | |
43 | ;; pool and its offsettable address instead of reloading to an | |
44 | ;; ("=r", "0", "i") alternative. Also, the constant-pool support was not | |
45 | ;; only suboptimal but also buggy in 2.7.2, ??? maybe only in 2.6.3. | |
46 | ||
47 | ;; All insns that look like (set (...) (plus (...) (reg:SI 8))) | |
48 | ;; get problems when reloading r8 (frame pointer) to r14 + offs (stack | |
49 | ;; pointer). Thus the instructions that get into trouble have specific | |
50 | ;; checks against matching frame_pointer_rtx. | |
51 | ;; ??? But it should be re-checked for gcc > 2.7.2 | |
52 | ;; FIXME: This changed some time ago (from 2000-03-16) for gcc-2.9x. | |
53 | ||
54 | ;; FIXME: When PIC, all [rX=rY+S] could be enabled to match | |
55 | ;; [rX=gotless_symbol]. | |
56 | ;; The movsi for a gotless symbol could be split (post reload). | |
57 | \f | |
58 | ;; UNSPEC Usage: | |
59 | ;; 0 PLT reference from call expansion: operand 0 is the address, | |
60 | ;; the mode is VOIDmode. Always wrapped in CONST. | |
61 | ||
62 | ;; We need an attribute to define whether an instruction can be put in | |
63 | ;; a branch-delay slot or not, and whether it has a delay slot. | |
64 | ;; | |
65 | ;; Branches and return instructions have a delay slot, and cannot | |
66 | ;; themselves be put in a delay slot. This has changed *for short | |
67 | ;; branches only* between architecture variants, but the possible win | |
68 | ;; is presumed negligible compared to the added complexity of the machine | |
69 | ;; description: one would have to add always-correct infrastructure to | |
70 | ;; distinguish short branches. | |
71 | ;; | |
72 | ;; Whether an instruction can be put in a delay slot depends on the | |
73 | ;; instruction (all short instructions except jumps and branches) | |
74 | ;; and the addressing mode (must not be prefixed or referring to pc). | |
75 | ;; In short, any "slottable" instruction must be 16 bit and not refer | |
76 | ;; to pc, or alter it. | |
77 | ;; | |
78 | ;; The possible values are "yes", "no" and "has_slot". Yes/no means if | |
79 | ;; the insn is slottable or not. Has_slot means that the insn is a | |
80 | ;; return insn or branch insn (which are not considered slottable since | |
839a4992 | 81 | ;; that is generally true). Having the seemingly illogical value |
0b85d816 HPN |
82 | ;; "has_slot" means we do not have to add another attribute just to say |
83 | ;; that an insn has a delay-slot, since it also infers that it is not | |
84 | ;; slottable. Better names for the attribute were found to be longer and | |
85 | ;; not add readability to the machine description. | |
86 | ;; | |
87 | ;; The default that is defined here for this attribute is "no", not | |
88 | ;; slottable, not having a delay-slot, so there's no need to worry about | |
89 | ;; it being wrong for non-branch and return instructions. | |
90 | ;; The default could depend on the kind of insn and the addressing | |
91 | ;; mode, but that would need more attributes and hairier, more error | |
92 | ;; prone code. | |
93 | ;; | |
94 | ;; There is an extra constraint, 'Q', which recognizes indirect reg, | |
95 | ;; except when the reg is pc. The constraints 'Q' and '>' together match | |
96 | ;; all possible memory operands that are slottable. | |
97 | ;; For other operands, you need to check if it has a valid "slottable" | |
98 | ;; quick-immediate operand, where the particular signedness-variation | |
99 | ;; may match the constraints 'I' or 'J'.), and include it in the | |
100 | ;; constraint pattern for the slottable pattern. An alternative using | |
101 | ;; only "r" constraints is most often slottable. | |
102 | ||
103 | (define_attr "slottable" "no,yes,has_slot" (const_string "no")) | |
104 | ||
105 | ;; We also need attributes to sanely determine the condition code | |
106 | ;; state. See cris_notice_update_cc for how this is used. | |
107 | ||
108 | (define_attr "cc" "none,clobber,normal" (const_string "normal")) | |
109 | ||
110 | ;; A branch or return has one delay-slot. The instruction in the | |
111 | ;; delay-slot is always executed, independent of whether the branch is | |
112 | ;; taken or not. Note that besides setting "slottable" to "has_slot", | |
113 | ;; there also has to be a "%#" at the end of a "delayed" instruction | |
114 | ;; output pattern (for "jump" this means "ba %l0%#"), so print_operand can | |
115 | ;; catch it and print a "nop" if necessary. This method was stolen from | |
116 | ;; sparc.md. | |
117 | ||
118 | (define_delay (eq_attr "slottable" "has_slot") | |
119 | [(eq_attr "slottable" "yes") (nil) (nil)]) | |
120 | \f | |
121 | ;; Test insns. | |
122 | ||
123 | ;; DImode | |
124 | ;; | |
125 | ;; Allow register and offsettable mem operands only; post-increment is | |
126 | ;; not worth the trouble. | |
127 | ||
128 | (define_insn "tstdi" | |
129 | [(set (cc0) | |
130 | (match_operand:DI 0 "nonimmediate_operand" "r,o"))] | |
131 | "" | |
132 | "test.d %M0\;ax\;test.d %H0") | |
133 | ||
134 | ;; No test insns with side-effect on the mem addressing. | |
135 | ;; | |
136 | ;; See note on cmp-insns with side-effects (or lack of them) | |
137 | ||
138 | ;; Normal named test patterns from SI on. | |
139 | ;; FIXME: Seems they should change to be in order smallest..largest. | |
140 | ||
141 | (define_insn "tstsi" | |
142 | [(set (cc0) | |
143 | (match_operand:SI 0 "nonimmediate_operand" "r,Q>,m"))] | |
144 | "" | |
145 | "test.d %0" | |
146 | [(set_attr "slottable" "yes,yes,no")]) | |
147 | ||
148 | (define_insn "tsthi" | |
149 | [(set (cc0) | |
150 | (match_operand:HI 0 "nonimmediate_operand" "r,Q>,m"))] | |
151 | "" | |
152 | "test.w %0" | |
153 | [(set_attr "slottable" "yes,yes,no")]) | |
154 | ||
155 | (define_insn "tstqi" | |
156 | [(set (cc0) | |
157 | (match_operand:QI 0 "nonimmediate_operand" "r,Q>,m"))] | |
158 | "" | |
159 | "test.b %0" | |
160 | [(set_attr "slottable" "yes,yes,no")]) | |
161 | ||
162 | ;; It seems that the position of the sign-bit and the fact that 0.0 is | |
163 | ;; all 0-bits would make "tstsf" a straight-forward implementation; | |
164 | ;; either "test.d" it for positive/negative or "btstq 30,r" it for | |
165 | ;; zeroness. | |
166 | ;; | |
167 | ;; FIXME: Do that some time; check next_cc0_user to determine if | |
168 | ;; zero or negative is tested for. | |
169 | \f | |
170 | ;; Compare insns. | |
171 | ||
172 | ;; We could optimize the sizes of the immediate operands for various | |
173 | ;; cases, but that is not worth it because of the very little usage of | |
174 | ;; DImode for anything else but a structure/block-mode. Just do the | |
175 | ;; obvious stuff for the straight-forward constraint letters. | |
176 | ||
177 | (define_insn "cmpdi" | |
178 | [(set (cc0) | |
179 | (compare (match_operand:DI 0 "nonimmediate_operand" "r,r,r,r,r,r,o") | |
180 | (match_operand:DI 1 "general_operand" "K,I,P,n,r,o,r")))] | |
181 | "" | |
182 | "@ | |
183 | cmpq %1,%M0\;ax\;cmpq 0,%H0 | |
184 | cmpq %1,%M0\;ax\;cmpq -1,%H0 | |
185 | cmp%e1.%z1 %1,%M0\;ax\;cmpq %H1,%H0 | |
186 | cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0 | |
187 | cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0 | |
188 | cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0 | |
189 | cmp.d %M0,%M1\;ax\;cmp.d %H0,%H1") | |
190 | ||
191 | ;; Note that compare insns with side effect addressing mode (e.g.): | |
192 | ;; | |
193 | ;; cmp.S [rx=ry+i],rz; | |
194 | ;; cmp.S [%3=%1+%2],%0 | |
195 | ;; | |
196 | ;; are *not* usable for gcc since the reloader *does not accept* | |
197 | ;; cc0-changing insns with side-effects other than setting the condition | |
198 | ;; codes. The reason is that the reload stage *may* cause another insn to | |
199 | ;; be output after the main instruction, in turn invalidating cc0 for the | |
200 | ;; insn using the test. (This does not apply to the CRIS case, since a | |
201 | ;; reload for output -- move to memory -- does not change the condition | |
202 | ;; code. Unfortunately we have no way to describe that at the moment. I | |
203 | ;; think code would improve being in the order of one percent faster. | |
204 | \f | |
205 | ;; We have cmps and cmpu (compare reg w. sign/zero extended mem). | |
206 | ;; These are mostly useful for compares in SImode, using 8 or 16-bit | |
207 | ;; constants, but sometimes gcc will find its way to use it for other | |
208 | ;; (memory) operands. Avoid side-effect patterns, though (see above). | |
209 | ;; | |
210 | ;; FIXME: These could have an anonymous mode for operand 1. | |
211 | ||
212 | ;; QImode | |
213 | ||
214 | (define_insn "*cmp_extsi" | |
215 | [(set (cc0) | |
216 | (compare | |
217 | (match_operand:SI 0 "register_operand" "r,r") | |
218 | (match_operator:SI 2 "cris_extend_operator" | |
219 | [(match_operand:QI 1 "memory_operand" "Q>,m")])))] | |
220 | "" | |
221 | "cmp%e2.%s1 %1,%0" | |
222 | [(set_attr "slottable" "yes,no")]) | |
223 | ||
224 | ;; HImode | |
225 | (define_insn "*cmp_exthi" | |
226 | [(set (cc0) | |
227 | (compare | |
228 | (match_operand:SI 0 "register_operand" "r,r") | |
229 | (match_operator:SI 2 "cris_extend_operator" | |
230 | [(match_operand:HI 1 "memory_operand" "Q>,m")])))] | |
231 | "" | |
232 | "cmp%e2.%s1 %1,%0" | |
233 | [(set_attr "slottable" "yes,no")]) | |
234 | ||
235 | ;; Swap operands; it seems the canonical look (if any) is not enforced. | |
236 | ;; | |
237 | ;; FIXME: Investigate that. | |
238 | ;; FIXME: These could have an anonymous mode for operand 1. | |
239 | ||
240 | ;; QImode | |
241 | ||
242 | (define_insn "*cmp_swapextqi" | |
243 | [(set (cc0) | |
244 | (compare | |
245 | (match_operator:SI 2 "cris_extend_operator" | |
246 | [(match_operand:QI 0 "memory_operand" "Q>,m")]) | |
247 | (match_operand:SI 1 "register_operand" "r,r")))] | |
248 | "" | |
249 | "cmp%e2.%s0 %0,%1" ; The function cris_notice_update_cc knows about | |
250 | ; swapped operands to compares. | |
251 | [(set_attr "slottable" "yes,no")]) | |
252 | ||
253 | ;; HImode | |
254 | ||
255 | (define_insn "*cmp_swapexthi" | |
256 | [(set (cc0) | |
257 | (compare | |
258 | (match_operator:SI 2 "cris_extend_operator" | |
259 | [(match_operand:HI 0 "memory_operand" "Q>,m")]) | |
260 | (match_operand:SI 1 "register_operand" "r,r")))] | |
261 | "" | |
262 | "cmp%e2.%s0 %0,%1" ; The function cris_notice_update_cc knows about | |
263 | ; swapped operands to compares. | |
264 | [(set_attr "slottable" "yes,no")]) | |
265 | \f | |
266 | ;; The "normal" compare patterns, from SI on. | |
267 | ||
268 | (define_insn "cmpsi" | |
269 | [(set (cc0) | |
270 | (compare | |
271 | (match_operand:SI 0 "nonimmediate_operand" "r,r,r,r,Q>,Q>,r,r,m,m") | |
272 | (match_operand:SI 1 "general_operand" "I,r,Q>,M,M,r,P,g,M,r")))] | |
273 | "" | |
274 | "@ | |
275 | cmpq %1,%0 | |
276 | cmp.d %1,%0 | |
277 | cmp.d %1,%0 | |
278 | test.d %0 | |
279 | test.d %0 | |
280 | cmp.d %0,%1 | |
281 | cmp%e1.%z1 %1,%0 | |
282 | cmp.d %1,%0 | |
283 | test.d %0 | |
284 | cmp.d %0,%1" | |
285 | [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no")]) | |
286 | ||
287 | (define_insn "cmphi" | |
288 | [(set (cc0) | |
289 | (compare (match_operand:HI 0 "nonimmediate_operand" "r,r,Q>,Q>,r,m,m") | |
290 | (match_operand:HI 1 "general_operand" "r,Q>,M,r,g,M,r")))] | |
291 | "" | |
292 | "@ | |
293 | cmp.w %1,%0 | |
294 | cmp.w %1,%0 | |
295 | test.w %0 | |
296 | cmp.w %0,%1 | |
297 | cmp.w %1,%0 | |
298 | test.w %0 | |
299 | cmp.w %0,%1" | |
300 | [(set_attr "slottable" "yes,yes,yes,yes,no,no,no")]) | |
301 | ||
302 | (define_insn "cmpqi" | |
303 | [(set (cc0) | |
304 | (compare | |
305 | (match_operand:QI 0 "nonimmediate_operand" "r,r,r,Q>,Q>,r,m,m") | |
306 | (match_operand:QI 1 "general_operand" "r,Q>,M,M,r,g,M,r")))] | |
307 | "" | |
308 | "@ | |
309 | cmp.b %1,%0 | |
310 | cmp.b %1,%0 | |
311 | test.b %0 | |
312 | test.b %0 | |
313 | cmp.b %0,%1 | |
314 | cmp.b %1,%0 | |
315 | test.b %0 | |
316 | cmp.b %0,%1" | |
317 | [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")]) | |
318 | \f | |
319 | ;; Pattern matching the BTST insn. | |
320 | ;; It is useful for "if (i & val)" constructs, where val is an exact | |
321 | ;; power of 2, or if val + 1 is a power of two, where we check for a bunch | |
322 | ;; of zeros starting at bit 0). | |
323 | ||
324 | ;; SImode. This mode is the only one needed, since gcc automatically | |
109b748d | 325 | ;; extends subregs for lower-size modes. FIXME: Add testcase. |
0b85d816 HPN |
326 | (define_insn "*btst" |
327 | [(set (cc0) | |
328 | (zero_extract | |
329 | (match_operand:SI 0 "nonmemory_operand" "r,r,r,r,r,r,n") | |
330 | (match_operand:SI 1 "const_int_operand" "K,n,K,n,K,n,n") | |
331 | (match_operand:SI 2 "nonmemory_operand" "M,M,K,n,r,r,r")))] | |
332 | ;; Either it is a single bit, or consecutive ones starting at 0. | |
333 | "GET_CODE (operands[1]) == CONST_INT | |
334 | && (operands[1] == const1_rtx || operands[2] == const0_rtx) | |
335 | && (REG_S_P (operands[0]) | |
336 | || (operands[1] == const1_rtx | |
337 | && REG_S_P (operands[2]) | |
338 | && GET_CODE (operands[0]) == CONST_INT | |
339 | && exact_log2 (INTVAL (operands[0])) >= 0))" | |
340 | ||
341 | ;; The last "&&" condition above should be caught by some kind of | |
342 | ;; canonicalization in gcc, but we can easily help with it here. | |
343 | ;; It results from expressions of the type | |
344 | ;; "power_of_2_value & (1 << y)". | |
345 | ;; | |
346 | ;; Since there may be codes with tests in on bits (in constant position) | |
347 | ;; beyond the size of a word, handle that by assuming those bits are 0. | |
348 | ;; GCC should handle that, but it's a matter of easily-added belts while | |
349 | ;; having suspenders. | |
350 | ||
351 | "@ | |
352 | btstq (%1-1),%0 | |
353 | test.d %0 | |
354 | btstq %2,%0 | |
355 | clearf nz | |
356 | btst %2,%0 | |
357 | clearf nz | |
358 | cmpq %p0,%2" | |
359 | [(set_attr "slottable" "yes")]) | |
360 | \f | |
361 | ;; Move insns. | |
362 | ||
363 | ;; The whole mandatory movdi family is here; expander, "anonymous" | |
364 | ;; recognizer and splitter. We're forced to have a movdi pattern, | |
365 | ;; although GCC should be able to split it up itself. Normally it can, | |
366 | ;; but if other insns have DI operands (as is the case here), reload | |
367 | ;; must be able to generate or match a movdi. many testcases fail at | |
368 | ;; -O3 or -fssa if we don't have this. FIXME: Fix GCC... See | |
369 | ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00104.html>. | |
370 | ;; However, a patch from Richard Kenner (similar to the cause of | |
371 | ;; discussion at the URL above), indicates otherwise. See | |
372 | ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00554.html>. | |
373 | ;; The truth has IMO is not been decided yet, so check from time to | |
374 | ;; time by disabling the movdi patterns. | |
375 | ||
376 | (define_expand "movdi" | |
377 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
378 | (match_operand:DI 1 "general_operand" ""))] | |
379 | "" | |
380 | " | |
381 | { | |
382 | if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx) | |
383 | operands[1] = copy_to_mode_reg (DImode, operands[1]); | |
384 | ||
385 | /* Some other ports (as of 2001-09-10 for example mcore and romp) also | |
386 | prefer to split up constants early, like this. The testcase in | |
387 | gcc.c-torture/execute/961213-1.c shows that CSE2 gets confused by the | |
388 | resulting subreg sets when using the construct from mcore (as of FSF | |
049746c2 | 389 | CVS, version -r 1.5), and it believes that the high part (the last one |
0b85d816 HPN |
390 | emitted) is the final value. This construct from romp seems more |
391 | robust, especially considering the head comments from | |
392 | emit_no_conflict_block. */ | |
393 | if ((GET_CODE (operands[1]) == CONST_INT | |
394 | || GET_CODE (operands[1]) == CONST_DOUBLE) | |
395 | && ! reload_completed | |
396 | && ! reload_in_progress) | |
397 | { | |
398 | rtx insns; | |
399 | rtx op0 = operands[0]; | |
400 | rtx op1 = operands[1]; | |
401 | ||
402 | start_sequence (); | |
403 | emit_move_insn (operand_subword (op0, 0, 1, DImode), | |
404 | operand_subword (op1, 0, 1, DImode)); | |
405 | emit_move_insn (operand_subword (op0, 1, 1, DImode), | |
406 | operand_subword (op1, 1, 1, DImode)); | |
407 | insns = get_insns (); | |
408 | end_sequence (); | |
409 | ||
410 | emit_no_conflict_block (insns, op0, op1, 0, op1); | |
411 | DONE; | |
412 | } | |
413 | }") | |
414 | ||
415 | (define_insn "*movdi_insn" | |
416 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m") | |
417 | (match_operand:DI 1 "general_operand" "r,g,rM"))] | |
418 | "register_operand (operands[0], DImode) | |
419 | || register_operand (operands[1], DImode) | |
420 | || operands[1] == const0_rtx" | |
421 | "#") | |
422 | ||
423 | (define_split | |
424 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
425 | (match_operand:DI 1 "general_operand" ""))] | |
426 | "reload_completed" | |
427 | [(match_dup 2)] | |
428 | "operands[2] = cris_split_movdx (operands);") | |
429 | \f | |
430 | ;; Side-effect patterns for move.S1 [rx=ry+rx.S2],rw | |
431 | ;; and move.S1 [rx=ry+i],rz | |
432 | ;; Then movs.S1 and movu.S1 for both modes. | |
433 | ;; | |
434 | ;; move.S1 [rx=ry+rz.S],rw avoiding when rx is ry, or rw is rx | |
435 | ;; FIXME: These could have anonymous mode for operand 0. | |
436 | ||
437 | ;; QImode | |
438 | ||
439 | (define_insn "*mov_sideqi_biap" | |
440 | [(set (match_operand:QI 0 "register_operand" "=r,r") | |
441 | (mem:QI (plus:SI | |
442 | (mult:SI (match_operand:SI 1 "register_operand" "r,r") | |
443 | (match_operand:SI 2 "const_int_operand" "n,n")) | |
444 | (match_operand:SI 3 "register_operand" "r,r")))) | |
445 | (set (match_operand:SI 4 "register_operand" "=*3,r") | |
446 | (plus:SI (mult:SI (match_dup 1) | |
447 | (match_dup 2)) | |
448 | (match_dup 3)))] | |
449 | "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)" | |
450 | "@ | |
451 | # | |
452 | move.%s0 [%4=%3+%1%T2],%0") | |
453 | ||
454 | ;; HImode | |
455 | ||
456 | (define_insn "*mov_sidehi_biap" | |
457 | [(set (match_operand:HI 0 "register_operand" "=r,r") | |
458 | (mem:HI (plus:SI | |
459 | (mult:SI (match_operand:SI 1 "register_operand" "r,r") | |
460 | (match_operand:SI 2 "const_int_operand" "n,n")) | |
461 | (match_operand:SI 3 "register_operand" "r,r")))) | |
462 | (set (match_operand:SI 4 "register_operand" "=*3,r") | |
463 | (plus:SI (mult:SI (match_dup 1) | |
464 | (match_dup 2)) | |
465 | (match_dup 3)))] | |
466 | "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)" | |
467 | "@ | |
468 | # | |
469 | move.%s0 [%4=%3+%1%T2],%0") | |
470 | ||
471 | ;; SImode | |
472 | ||
473 | (define_insn "*mov_sidesi_biap" | |
474 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
475 | (mem:SI (plus:SI | |
476 | (mult:SI (match_operand:SI 1 "register_operand" "r,r") | |
477 | (match_operand:SI 2 "const_int_operand" "n,n")) | |
478 | (match_operand:SI 3 "register_operand" "r,r")))) | |
479 | (set (match_operand:SI 4 "register_operand" "=*3,r") | |
480 | (plus:SI (mult:SI (match_dup 1) | |
481 | (match_dup 2)) | |
482 | (match_dup 3)))] | |
483 | "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)" | |
484 | "@ | |
485 | # | |
486 | move.%s0 [%4=%3+%1%T2],%0") | |
487 | \f | |
488 | ;; move.S1 [rx=ry+i],rz | |
489 | ;; avoiding move.S1 [ry=ry+i],rz | |
490 | ;; and move.S1 [rz=ry+i],rz | |
491 | ;; Note that "i" is allowed to be a register. | |
492 | ;; FIXME: These could have anonymous mode for operand 0. | |
493 | ||
494 | ;; QImode | |
495 | ||
496 | (define_insn "*mov_sideqi" | |
497 | [(set (match_operand:QI 0 "register_operand" "=r,r,r") | |
498 | (mem:QI | |
499 | (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r") | |
747a0d9d | 500 | (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn")))) |
0b85d816 HPN |
501 | (set (match_operand:SI 3 "register_operand" "=*1,r,r") |
502 | (plus:SI (match_dup 1) | |
503 | (match_dup 2)))] | |
504 | "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)" | |
505 | "* | |
506 | { | |
507 | if (which_alternative == 0 | |
508 | && (GET_CODE (operands[2]) != CONST_INT | |
509 | || INTVAL (operands[2]) > 127 | |
510 | || INTVAL (operands[2]) < -128 | |
511 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N') | |
512 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))) | |
513 | return \"#\"; | |
514 | return \"move.%s0 [%3=%1%S2],%0\"; | |
515 | }") | |
516 | ||
517 | ;; HImode | |
518 | ||
519 | (define_insn "*mov_sidehi" | |
520 | [(set (match_operand:HI 0 "register_operand" "=r,r,r") | |
521 | (mem:HI | |
522 | (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r") | |
747a0d9d | 523 | (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn")))) |
0b85d816 HPN |
524 | (set (match_operand:SI 3 "register_operand" "=*1,r,r") |
525 | (plus:SI (match_dup 1) | |
526 | (match_dup 2)))] | |
527 | "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)" | |
528 | "* | |
529 | { | |
530 | if (which_alternative == 0 | |
531 | && (GET_CODE (operands[2]) != CONST_INT | |
532 | || INTVAL (operands[2]) > 127 | |
533 | || INTVAL (operands[2]) < -128 | |
534 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N') | |
535 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))) | |
536 | return \"#\"; | |
537 | return \"move.%s0 [%3=%1%S2],%0\"; | |
538 | }") | |
539 | ||
540 | ;; SImode | |
541 | ||
542 | (define_insn "*mov_sidesi" | |
543 | [(set (match_operand:SI 0 "register_operand" "=r,r,r") | |
544 | (mem:SI | |
545 | (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r") | |
747a0d9d | 546 | (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn")))) |
0b85d816 HPN |
547 | (set (match_operand:SI 3 "register_operand" "=*1,r,r") |
548 | (plus:SI (match_dup 1) | |
549 | (match_dup 2)))] | |
550 | "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)" | |
551 | "* | |
552 | { | |
553 | if (which_alternative == 0 | |
554 | && (GET_CODE (operands[2]) != CONST_INT | |
555 | || INTVAL (operands[2]) > 127 | |
556 | || INTVAL (operands[2]) < -128 | |
557 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N') | |
558 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))) | |
559 | return \"#\"; | |
560 | return \"move.%s0 [%3=%1%S2],%0\"; | |
561 | }") | |
562 | \f | |
563 | ;; Other way around; move to memory. | |
564 | ||
049746c2 HPN |
565 | ;; Note that the condition (which for side-effect patterns is usually a |
566 | ;; call to cris_side_effect_mode_ok), isn't consulted for register | |
567 | ;; allocation preferences -- constraints is the method for that. The | |
568 | ;; drawback is that we can't exclude register allocation to cause | |
569 | ;; "move.s rw,[rx=ry+rz.S]" when rw==rx without also excluding rx==ry or | |
570 | ;; rx==rz if we use an earlyclobber modifier for the constraint for rx. | |
571 | ;; Instead of that, we recognize and split the cases where dangerous | |
572 | ;; register combinations are spotted: where a register is set in the | |
573 | ;; side-effect, and used in the main insn. We don't handle the case where | |
574 | ;; the set in the main insn overlaps the set in the side-effect; that case | |
575 | ;; must be handled in gcc. We handle just the case where the set in the | |
576 | ;; side-effect overlaps the input operand of the main insn (i.e. just | |
577 | ;; moves to memory). | |
0b85d816 HPN |
578 | |
579 | ;; | |
049746c2 | 580 | ;; move.s rz,[ry=rx+rw.S] |
0b85d816 HPN |
581 | ;; FIXME: These could have anonymous mode for operand 3. |
582 | ||
583 | ;; QImode | |
584 | ||
585 | (define_insn "*mov_sideqi_biap_mem" | |
586 | [(set (mem:QI (plus:SI | |
587 | (mult:SI (match_operand:SI 0 "register_operand" "r,r,r") | |
588 | (match_operand:SI 1 "const_int_operand" "n,n,n")) | |
589 | (match_operand:SI 2 "register_operand" "r,r,r"))) | |
590 | (match_operand:QI 3 "register_operand" "r,r,r")) | |
049746c2 | 591 | (set (match_operand:SI 4 "register_operand" "=*2,!3,r") |
0b85d816 HPN |
592 | (plus:SI (mult:SI (match_dup 0) |
593 | (match_dup 1)) | |
594 | (match_dup 2)))] | |
595 | "cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)" | |
596 | "@ | |
597 | # | |
598 | # | |
599 | move.%s3 %3,[%4=%2+%0%T1]") | |
600 | ||
601 | ;; HImode | |
602 | ||
603 | (define_insn "*mov_sidehi_biap_mem" | |
604 | [(set (mem:HI (plus:SI | |
605 | (mult:SI (match_operand:SI 0 "register_operand" "r,r,r") | |
606 | (match_operand:SI 1 "const_int_operand" "n,n,n")) | |
607 | (match_operand:SI 2 "register_operand" "r,r,r"))) | |
608 | (match_operand:HI 3 "register_operand" "r,r,r")) | |
049746c2 | 609 | (set (match_operand:SI 4 "register_operand" "=*2,!3,r") |
0b85d816 HPN |
610 | (plus:SI (mult:SI (match_dup 0) |
611 | (match_dup 1)) | |
612 | (match_dup 2)))] | |
613 | "cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)" | |
614 | "@ | |
615 | # | |
616 | # | |
617 | move.%s3 %3,[%4=%2+%0%T1]") | |
618 | ||
619 | ;; SImode | |
620 | ||
621 | (define_insn "*mov_sidesi_biap_mem" | |
622 | [(set (mem:SI (plus:SI | |
623 | (mult:SI (match_operand:SI 0 "register_operand" "r,r,r") | |
624 | (match_operand:SI 1 "const_int_operand" "n,n,n")) | |
625 | (match_operand:SI 2 "register_operand" "r,r,r"))) | |
626 | (match_operand:SI 3 "register_operand" "r,r,r")) | |
049746c2 | 627 | (set (match_operand:SI 4 "register_operand" "=*2,!3,r") |
0b85d816 HPN |
628 | (plus:SI (mult:SI (match_dup 0) |
629 | (match_dup 1)) | |
630 | (match_dup 2)))] | |
631 | "cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)" | |
632 | "@ | |
633 | # | |
634 | # | |
635 | move.%s3 %3,[%4=%2+%0%T1]") | |
636 | ||
049746c2 HPN |
637 | ;; Split for the case above where we're out of luck with register |
638 | ;; allocation (again, the condition isn't checked for that), and we end up | |
639 | ;; with the set in the side-effect getting the same register as the input | |
640 | ;; register. | |
0b85d816 HPN |
641 | |
642 | (define_split | |
643 | [(parallel | |
dbb138ce HPN |
644 | [(set (match_operator |
645 | 6 "cris_mem_op" | |
646 | [(plus:SI | |
647 | (mult:SI (match_operand:SI 0 "register_operand" "") | |
648 | (match_operand:SI 1 "const_int_operand" "")) | |
649 | (match_operand:SI 2 "register_operand" ""))]) | |
0b85d816 HPN |
650 | (match_operand 3 "register_operand" "")) |
651 | (set (match_operand:SI 4 "register_operand" "") | |
652 | (plus:SI (mult:SI (match_dup 0) | |
653 | (match_dup 1)) | |
654 | (match_dup 2)))])] | |
655 | "reload_completed && reg_overlap_mentioned_p (operands[4], operands[3])" | |
656 | [(set (match_dup 5) (match_dup 3)) | |
657 | (set (match_dup 4) (match_dup 2)) | |
658 | (set (match_dup 4) | |
659 | (plus:SI (mult:SI (match_dup 0) | |
660 | (match_dup 1)) | |
661 | (match_dup 4)))] | |
662 | "operands[5] | |
dbb138ce HPN |
663 | = replace_equiv_address (operands[6], |
664 | gen_rtx_PLUS (SImode, | |
665 | gen_rtx_MULT (SImode, | |
666 | operands[0], | |
667 | operands[1]), | |
668 | operands[2]));") | |
0b85d816 HPN |
669 | \f |
670 | ;; move.s rx,[ry=rz+i] | |
671 | ;; FIXME: These could have anonymous mode for operand 2. | |
672 | ||
673 | ;; QImode | |
674 | ||
675 | (define_insn "*mov_sideqi_mem" | |
676 | [(set (mem:QI | |
677 | (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r") | |
747a0d9d | 678 | (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn"))) |
0b85d816 | 679 | (match_operand:QI 2 "register_operand" "r,r,r,r")) |
049746c2 | 680 | (set (match_operand:SI 3 "register_operand" "=*0,!2,r,r") |
0b85d816 HPN |
681 | (plus:SI (match_dup 0) |
682 | (match_dup 1)))] | |
683 | "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)" | |
684 | "* | |
685 | { | |
686 | if (which_alternative == 0 | |
687 | && (GET_CODE (operands[1]) != CONST_INT | |
688 | || INTVAL (operands[1]) > 127 | |
689 | || INTVAL (operands[1]) < -128 | |
690 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N') | |
691 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J'))) | |
692 | return \"#\"; | |
693 | if (which_alternative == 1) | |
694 | return \"#\"; | |
695 | return \"move.%s2 %2,[%3=%0%S1]\"; | |
696 | }") | |
697 | ||
698 | ;; HImode | |
699 | ||
700 | (define_insn "*mov_sidehi_mem" | |
701 | [(set (mem:HI | |
702 | (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r") | |
747a0d9d | 703 | (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn"))) |
0b85d816 | 704 | (match_operand:HI 2 "register_operand" "r,r,r,r")) |
049746c2 | 705 | (set (match_operand:SI 3 "register_operand" "=*0,!2,r,r") |
0b85d816 HPN |
706 | (plus:SI (match_dup 0) |
707 | (match_dup 1)))] | |
708 | "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)" | |
709 | "* | |
710 | { | |
711 | if (which_alternative == 0 | |
712 | && (GET_CODE (operands[1]) != CONST_INT | |
713 | || INTVAL (operands[1]) > 127 | |
714 | || INTVAL (operands[1]) < -128 | |
715 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N') | |
716 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J'))) | |
717 | return \"#\"; | |
718 | if (which_alternative == 1) | |
719 | return \"#\"; | |
720 | return \"move.%s2 %2,[%3=%0%S1]\"; | |
721 | }") | |
722 | ||
723 | ;; SImode | |
724 | ||
725 | (define_insn "*mov_sidesi_mem" | |
726 | [(set (mem:SI | |
727 | (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r") | |
747a0d9d | 728 | (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn"))) |
0b85d816 | 729 | (match_operand:SI 2 "register_operand" "r,r,r,r")) |
049746c2 | 730 | (set (match_operand:SI 3 "register_operand" "=*0,!2,r,r") |
0b85d816 HPN |
731 | (plus:SI (match_dup 0) |
732 | (match_dup 1)))] | |
733 | "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)" | |
734 | "* | |
735 | { | |
736 | if (which_alternative == 0 | |
737 | && (GET_CODE (operands[1]) != CONST_INT | |
738 | || INTVAL (operands[1]) > 127 | |
739 | || INTVAL (operands[1]) < -128 | |
740 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N') | |
741 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J'))) | |
742 | return \"#\"; | |
743 | if (which_alternative == 1) | |
744 | return \"#\"; | |
745 | return \"move.%s2 %2,[%3=%0%S1]\"; | |
746 | }") | |
747 | ||
748 | ;; Like the biap case, a split where the set in the side-effect gets the | |
049746c2 HPN |
749 | ;; same register as the input register to the main insn, since the |
750 | ;; condition isn't checked at register allocation. | |
0b85d816 HPN |
751 | |
752 | (define_split | |
753 | [(parallel | |
dbb138ce HPN |
754 | [(set (match_operator |
755 | 4 "cris_mem_op" | |
756 | [(plus:SI | |
757 | (match_operand:SI 0 "cris_bdap_operand" "") | |
758 | (match_operand:SI 1 "cris_bdap_operand" ""))]) | |
049746c2 | 759 | (match_operand 2 "register_operand" "")) |
0b85d816 HPN |
760 | (set (match_operand:SI 3 "register_operand" "") |
761 | (plus:SI (match_dup 0) (match_dup 1)))])] | |
762 | "reload_completed && reg_overlap_mentioned_p (operands[3], operands[2])" | |
763 | [(set (match_dup 4) (match_dup 2)) | |
764 | (set (match_dup 3) (match_dup 0)) | |
765 | (set (match_dup 3) (plus:SI (match_dup 3) (match_dup 1)))] | |
dbb138ce | 766 | "") |
0b85d816 HPN |
767 | \f |
768 | ;; Clear memory side-effect patterns. It is hard to get to the mode if | |
769 | ;; the MEM was anonymous, so there will be one for each mode. | |
770 | ||
771 | ;; clear.d [ry=rx+rw.s2] | |
772 | ||
773 | (define_insn "*clear_sidesi_biap" | |
774 | [(set (mem:SI (plus:SI | |
775 | (mult:SI (match_operand:SI 0 "register_operand" "r,r") | |
776 | (match_operand:SI 1 "const_int_operand" "n,n")) | |
777 | (match_operand:SI 2 "register_operand" "r,r"))) | |
778 | (const_int 0)) | |
779 | (set (match_operand:SI 3 "register_operand" "=*2,r") | |
780 | (plus:SI (mult:SI (match_dup 0) | |
781 | (match_dup 1)) | |
782 | (match_dup 2)))] | |
783 | "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)" | |
784 | "@ | |
785 | # | |
786 | clear.d [%3=%2+%0%T1]") | |
787 | ||
788 | ;; clear.d [ry=rz+i] | |
789 | ||
790 | (define_insn "*clear_sidesi" | |
791 | [(set (mem:SI | |
792 | (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r") | |
747a0d9d | 793 | (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn"))) |
0b85d816 HPN |
794 | (const_int 0)) |
795 | (set (match_operand:SI 2 "register_operand" "=*0,r,r") | |
796 | (plus:SI (match_dup 0) | |
797 | (match_dup 1)))] | |
798 | "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)" | |
799 | "* | |
800 | { | |
801 | if (which_alternative == 0 | |
802 | && (GET_CODE (operands[1]) != CONST_INT | |
803 | || INTVAL (operands[1]) > 127 | |
804 | || INTVAL (operands[1]) < -128 | |
805 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N') | |
806 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J'))) | |
807 | return \"#\"; | |
808 | return \"clear.d [%2=%0%S1]\"; | |
809 | }") | |
810 | ||
811 | ;; clear.w [ry=rx+rw.s2] | |
812 | ||
813 | (define_insn "*clear_sidehi_biap" | |
814 | [(set (mem:HI (plus:SI | |
815 | (mult:SI (match_operand:SI 0 "register_operand" "r,r") | |
816 | (match_operand:SI 1 "const_int_operand" "n,n")) | |
817 | (match_operand:SI 2 "register_operand" "r,r"))) | |
818 | (const_int 0)) | |
819 | (set (match_operand:SI 3 "register_operand" "=*2,r") | |
820 | (plus:SI (mult:SI (match_dup 0) | |
821 | (match_dup 1)) | |
822 | (match_dup 2)))] | |
823 | "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)" | |
824 | "@ | |
825 | # | |
826 | clear.w [%3=%2+%0%T1]") | |
827 | ||
828 | ;; clear.w [ry=rz+i] | |
829 | ||
830 | (define_insn "*clear_sidehi" | |
831 | [(set (mem:HI | |
832 | (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r") | |
747a0d9d | 833 | (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn"))) |
0b85d816 HPN |
834 | (const_int 0)) |
835 | (set (match_operand:SI 2 "register_operand" "=*0,r,r") | |
836 | (plus:SI (match_dup 0) | |
837 | (match_dup 1)))] | |
838 | "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)" | |
839 | "* | |
840 | { | |
841 | if (which_alternative == 0 | |
842 | && (GET_CODE (operands[1]) != CONST_INT | |
843 | || INTVAL (operands[1]) > 127 | |
844 | || INTVAL (operands[1]) < -128 | |
845 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N') | |
846 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J'))) | |
847 | return \"#\"; | |
848 | return \"clear.w [%2=%0%S1]\"; | |
849 | }") | |
850 | ||
851 | ;; clear.b [ry=rx+rw.s2] | |
852 | ||
853 | (define_insn "*clear_sideqi_biap" | |
854 | [(set (mem:QI (plus:SI | |
855 | (mult:SI (match_operand:SI 0 "register_operand" "r,r") | |
856 | (match_operand:SI 1 "const_int_operand" "n,n")) | |
857 | (match_operand:SI 2 "register_operand" "r,r"))) | |
858 | (const_int 0)) | |
859 | (set (match_operand:SI 3 "register_operand" "=*2,r") | |
860 | (plus:SI (mult:SI (match_dup 0) | |
861 | (match_dup 1)) | |
862 | (match_dup 2)))] | |
863 | "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)" | |
864 | "@ | |
865 | # | |
866 | clear.b [%3=%2+%0%T1]") | |
867 | ||
868 | ;; clear.b [ry=rz+i] | |
869 | ||
870 | (define_insn "*clear_sideqi" | |
871 | [(set (mem:QI | |
872 | (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r") | |
747a0d9d | 873 | (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn"))) |
0b85d816 HPN |
874 | (const_int 0)) |
875 | (set (match_operand:SI 2 "register_operand" "=*0,r,r") | |
876 | (plus:SI (match_dup 0) | |
877 | (match_dup 1)))] | |
878 | "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)" | |
879 | "* | |
880 | { | |
881 | if (which_alternative == 0 | |
882 | && (GET_CODE (operands[1]) != CONST_INT | |
883 | || INTVAL (operands[1]) > 127 | |
884 | || INTVAL (operands[1]) < -128 | |
885 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N') | |
886 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J'))) | |
887 | return \"#\"; | |
888 | return \"clear.b [%2=%0%S1]\"; | |
889 | }") | |
890 | \f | |
109b748d | 891 | ;; To appease testcase gcc.c-torture/execute/920501-2.c (and others) at |
0b85d816 HPN |
892 | ;; -O0, we need a movdi as a temporary measure. Here's how things fail: |
893 | ;; A cmpdi RTX needs reloading (global): | |
894 | ;; (insn 185 326 186 (set (cc0) | |
895 | ;; (compare (mem/f:DI (reg/v:SI 22) 0) | |
896 | ;; (const_int 1 [0x1]))) 4 {cmpdi} (nil) | |
897 | ;; (nil)) | |
898 | ;; Now, reg 22 is reloaded for input address, and the mem is also moved | |
899 | ;; out of the instruction (into a register), since one of the operands | |
900 | ;; must be a register. Reg 22 is reloaded (into reg 10), and the mem is | |
901 | ;; moved out and synthesized in SImode parts (reg 9, reg 10 - should be ok | |
902 | ;; wrt. overlap). The bad things happen with the synthesis in | |
903 | ;; emit_move_insn_1; the location where to substitute reg 10 is lost into | |
904 | ;; two new RTX:es, both still having reg 22. Later on, the left-over reg | |
905 | ;; 22 is recognized to have an equivalent in memory which is substituted | |
906 | ;; straight in, and we end up with an unrecognizable insn: | |
907 | ;; (insn 325 324 326 (set (reg:SI 9 r9) | |
908 | ;; (mem/f:SI (mem:SI (plus:SI (reg:SI 8 r8) | |
909 | ;; (const_int -84 [0xffffffac])) 0) 0)) -1 (nil) | |
910 | ;; (nil)) | |
911 | ;; which is the first part of the reloaded synthesized "movdi". | |
912 | ;; The right thing would be to add equivalent replacement locations for | |
913 | ;; insn with pseudos that need more reloading. The question is where. | |
914 | ||
915 | ;; Normal move patterns from SI on. | |
916 | ||
917 | (define_expand "movsi" | |
918 | [(set | |
919 | (match_operand:SI 0 "nonimmediate_operand" "") | |
920 | (match_operand:SI 1 "cris_general_operand_or_symbol" ""))] | |
921 | "" | |
922 | " | |
923 | { | |
924 | /* If the output goes to a MEM, make sure we have zero or a register as | |
925 | input. */ | |
926 | if (GET_CODE (operands[0]) == MEM | |
927 | && ! REG_S_P (operands[1]) | |
928 | && operands[1] != const0_rtx | |
929 | && ! no_new_pseudos) | |
930 | operands[1] = force_reg (SImode, operands[1]); | |
931 | ||
932 | /* If we're generating PIC and have an incoming symbol, validize it to a | |
933 | general operand or something that will match a special pattern. | |
934 | ||
935 | FIXME: Do we *have* to recognize anything that would normally be a | |
936 | valid symbol? Can we exclude global PIC addresses with an added | |
937 | offset? */ | |
938 | if (flag_pic | |
939 | && CONSTANT_ADDRESS_P (operands[1]) | |
940 | && cris_symbol (operands[1])) | |
941 | { | |
942 | /* We must have a register as destination for what we're about to | |
943 | do, and for the patterns we generate. */ | |
944 | if (! REG_S_P (operands[0])) | |
945 | { | |
946 | if (no_new_pseudos) | |
947 | abort (); | |
948 | operands[1] = force_reg (SImode, operands[1]); | |
949 | } | |
950 | else | |
951 | { | |
952 | /* Mark a needed PIC setup for a LABEL_REF:s coming in here: | |
953 | they are so rare not-being-branch-targets that we don't mark | |
954 | a function as needing PIC setup just because we have | |
955 | inspected LABEL_REF:s as operands. It is only in | |
956 | __builtin_setjmp and such that we can get a LABEL_REF | |
957 | assigned to a register. */ | |
958 | if (GET_CODE (operands[1]) == LABEL_REF) | |
959 | current_function_uses_pic_offset_table = 1; | |
960 | ||
961 | /* We don't have to do anything for global PIC operands; they | |
962 | look just like ``[rPIC+sym]''. */ | |
963 | if (! cris_got_symbol (operands[1]) | |
964 | /* We don't do anything for local PIC operands; we match | |
965 | that with a special alternative. */ | |
966 | && ! cris_gotless_symbol (operands[1])) | |
967 | { | |
968 | /* We get here when we have to change something that would | |
969 | be recognizable if it wasn't PIC. A ``sym'' is ok for | |
970 | PIC symbols both with and without a GOT entry. And ``sym | |
971 | + offset'' is ok for local symbols, so the only thing it | |
972 | could be, is a global symbol with an offset. Check and | |
973 | abort if not. */ | |
974 | rtx sym = get_related_value (operands[1]); | |
975 | HOST_WIDE_INT offs = get_integer_term (operands[1]); | |
976 | ||
977 | if (sym == NULL_RTX || offs == 0) | |
978 | abort (); | |
979 | emit_move_insn (operands[0], sym); | |
980 | if (expand_binop (SImode, add_optab, operands[0], | |
981 | GEN_INT (offs), operands[0], 0, | |
982 | OPTAB_LIB_WIDEN) != operands[0]) | |
983 | abort (); | |
984 | DONE; | |
985 | } | |
986 | } | |
987 | } | |
988 | }") | |
989 | ||
990 | (define_insn "*movsi_internal" | |
991 | [(set | |
992 | (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,Q>,r,Q>,g,r,r,r,g") | |
993 | (match_operand:SI 1 | |
994 | ;; FIXME: We want to put S last, but apparently g matches S. | |
995 | ;; It's a bug: an S is not a general_operand and shouldn't match g. | |
996 | "cris_general_operand_or_gotless_symbol" "r,Q>,M,M,I,r,M,n,!S,g,r"))] | |
997 | "" | |
998 | "* | |
999 | { | |
1000 | /* Better to have c-switch here; it is worth it to optimize the size of | |
1001 | move insns. The alternative would be to try to find more constraint | |
1002 | letters. FIXME: Check again. It seems this could shrink a bit. */ | |
1003 | switch (which_alternative) | |
1004 | { | |
1005 | case 0: | |
1006 | case 1: | |
1007 | case 5: | |
1008 | case 9: | |
1009 | case 10: | |
1010 | return \"move.d %1,%0\"; | |
1011 | ||
1012 | case 2: | |
1013 | case 3: | |
1014 | case 6: | |
1015 | return \"clear.d %0\"; | |
1016 | ||
1017 | /* Constants -32..31 except 0. */ | |
1018 | case 4: | |
1019 | return \"moveq %1,%0\"; | |
1020 | ||
1021 | /* We can win a little on constants -32768..-33, 32..65535. */ | |
1022 | case 7: | |
1023 | if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) < 65536) | |
1024 | { | |
1025 | if (INTVAL (operands[1]) < 256) | |
1026 | return \"movu.b %1,%0\"; | |
1027 | return \"movu.w %1,%0\"; | |
1028 | } | |
1029 | else if (INTVAL (operands[1]) >= -32768 && INTVAL (operands[1]) < 32768) | |
1030 | { | |
1031 | if (INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) < 128) | |
1032 | return \"movs.b %1,%0\"; | |
1033 | return \"movs.w %1,%0\"; | |
1034 | } | |
1035 | return \"move.d %1,%0\"; | |
1036 | ||
1037 | case 8: | |
1038 | /* FIXME: Try and split this into pieces GCC makes better code of, | |
1039 | than this multi-insn pattern. Synopsis: wrap the GOT-relative | |
1040 | symbol into an unspec, and when PIC, recognize the unspec | |
1041 | everywhere a symbol is normally recognized. (The PIC register | |
1042 | should be recognized by GCC as pic_offset_table_rtx when needed | |
1043 | and similar for PC.) Each component can then be optimized with | |
1044 | the rest of the code; it should be possible to have a constant | |
1045 | term added on an unspec. Don't forget to add a REG_EQUAL (or | |
1046 | is it REG_EQUIV) note to the destination. It might not be | |
1047 | worth it. Measure. | |
1048 | ||
1049 | Note that the 'v' modifier makes PLT references be output as | |
1050 | sym:PLT rather than [rPIC+sym:GOTPLT]. */ | |
1051 | return \"move.d %v1,%0\;add.d %P1,%0\"; | |
1052 | ||
1053 | default: | |
1054 | return \"BOGUS: %1 to %0\"; | |
1055 | } | |
1056 | }" | |
1057 | [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no,no")]) | |
1058 | \f | |
1059 | ;; Extend operations with side-effect from mem to register, using | |
1060 | ;; MOVS/MOVU. These are from mem to register only. | |
1061 | ;; | |
1062 | ;; [rx=ry+rz.S] | |
1063 | ;; | |
1064 | ;; QImode to HImode | |
1065 | ;; | |
1066 | ;; FIXME: Can we omit extend to HImode, since GCC should truncate for | |
1067 | ;; HImode by itself? Perhaps use only anonymous modes? | |
1068 | ||
1069 | (define_insn "*ext_sideqihi_biap" | |
1070 | [(set (match_operand:HI 0 "register_operand" "=r,r") | |
1071 | (match_operator:HI | |
1072 | 5 "cris_extend_operator" | |
1073 | [(mem:QI (plus:SI | |
1074 | (mult:SI (match_operand:SI 1 "register_operand" "r,r") | |
1075 | (match_operand:SI 2 "const_int_operand" "n,n")) | |
1076 | (match_operand:SI 3 "register_operand" "r,r")))])) | |
1077 | (set (match_operand:SI 4 "register_operand" "=*3,r") | |
1078 | (plus:SI (mult:SI (match_dup 1) | |
1079 | (match_dup 2)) | |
1080 | (match_dup 3)))] | |
1081 | "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)" | |
1082 | "@ | |
1083 | # | |
1084 | mov%e5.%m5 [%4=%3+%1%T2],%0") | |
1085 | ||
1086 | ;; QImode to SImode | |
1087 | ||
1088 | (define_insn "*ext_sideqisi_biap" | |
1089 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
1090 | (match_operator:SI | |
1091 | 5 "cris_extend_operator" | |
1092 | [(mem:QI (plus:SI | |
1093 | (mult:SI (match_operand:SI 1 "register_operand" "r,r") | |
1094 | (match_operand:SI 2 "const_int_operand" "n,n")) | |
1095 | (match_operand:SI 3 "register_operand" "r,r")))])) | |
1096 | (set (match_operand:SI 4 "register_operand" "=*3,r") | |
1097 | (plus:SI (mult:SI (match_dup 1) | |
1098 | (match_dup 2)) | |
1099 | (match_dup 3)))] | |
1100 | "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)" | |
1101 | "@ | |
1102 | # | |
1103 | mov%e5.%m5 [%4=%3+%1%T2],%0") | |
1104 | ||
1105 | ;; HImode to SImode | |
1106 | ||
1107 | (define_insn "*ext_sidehisi_biap" | |
1108 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
1109 | (match_operator:SI | |
1110 | 5 "cris_extend_operator" | |
1111 | [(mem:HI (plus:SI | |
1112 | (mult:SI (match_operand:SI 1 "register_operand" "r,r") | |
1113 | (match_operand:SI 2 "const_int_operand" "n,n")) | |
1114 | (match_operand:SI 3 "register_operand" "r,r")))])) | |
1115 | (set (match_operand:SI 4 "register_operand" "=*3,r") | |
1116 | (plus:SI (mult:SI (match_dup 1) | |
1117 | (match_dup 2)) | |
1118 | (match_dup 3)))] | |
1119 | "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)" | |
1120 | "@ | |
1121 | # | |
1122 | mov%e5.%m5 [%4=%3+%1%T2],%0") | |
1123 | \f | |
1124 | ;; Same but [rx=ry+i] | |
1125 | ||
1126 | ;; QImode to HImode | |
1127 | ||
1128 | (define_insn "*ext_sideqihi" | |
1129 | [(set (match_operand:HI 0 "register_operand" "=r,r,r") | |
1130 | (match_operator:HI | |
1131 | 4 "cris_extend_operator" | |
1132 | [(mem:QI (plus:SI | |
1133 | (match_operand:SI 1 "cris_bdap_operand" "%r,r,r") | |
747a0d9d | 1134 | (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn")))])) |
0b85d816 HPN |
1135 | (set (match_operand:SI 3 "register_operand" "=*1,r,r") |
1136 | (plus:SI (match_dup 1) | |
1137 | (match_dup 2)))] | |
1138 | "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)" | |
1139 | "* | |
1140 | { | |
1141 | if (which_alternative == 0 | |
1142 | && (GET_CODE (operands[2]) != CONST_INT | |
1143 | || INTVAL (operands[2]) > 127 | |
1144 | || INTVAL (operands[2]) < -128 | |
1145 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N') | |
1146 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))) | |
1147 | return \"#\"; | |
1148 | return \"mov%e4.%m4 [%3=%1%S2],%0\"; | |
1149 | }") | |
1150 | ||
1151 | ;; QImode to SImode | |
1152 | ||
1153 | (define_insn "*ext_sideqisi" | |
1154 | [(set (match_operand:SI 0 "register_operand" "=r,r,r") | |
1155 | (match_operator:SI | |
1156 | 4 "cris_extend_operator" | |
1157 | [(mem:QI (plus:SI | |
1158 | (match_operand:SI 1 "cris_bdap_operand" "%r,r,r") | |
747a0d9d | 1159 | (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn")))])) |
0b85d816 HPN |
1160 | (set (match_operand:SI 3 "register_operand" "=*1,r,r") |
1161 | (plus:SI (match_dup 1) | |
1162 | (match_dup 2)))] | |
1163 | "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)" | |
1164 | "* | |
1165 | { | |
1166 | if (which_alternative == 0 | |
1167 | && (GET_CODE (operands[2]) != CONST_INT | |
1168 | || INTVAL (operands[2]) > 127 | |
1169 | || INTVAL (operands[2]) < -128 | |
1170 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N') | |
1171 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))) | |
1172 | return \"#\"; | |
1173 | return \"mov%e4.%m4 [%3=%1%S2],%0\"; | |
1174 | }") | |
1175 | ||
1176 | ;; HImode to SImode | |
1177 | ||
1178 | (define_insn "*ext_sidehisi" | |
1179 | [(set (match_operand:SI 0 "register_operand" "=r,r,r") | |
1180 | (match_operator:SI | |
1181 | 4 "cris_extend_operator" | |
1182 | [(mem:HI (plus:SI | |
1183 | (match_operand:SI 1 "cris_bdap_operand" "%r,r,r") | |
747a0d9d | 1184 | (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn")))])) |
0b85d816 HPN |
1185 | (set (match_operand:SI 3 "register_operand" "=*1,r,r") |
1186 | (plus:SI (match_dup 1) | |
1187 | (match_dup 2)))] | |
1188 | "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)" | |
1189 | "* | |
1190 | { | |
1191 | if (which_alternative == 0 | |
1192 | && (GET_CODE (operands[2]) != CONST_INT | |
1193 | || INTVAL (operands[2]) > 127 | |
1194 | || INTVAL (operands[2]) < -128 | |
1195 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N') | |
1196 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))) | |
1197 | return \"#\"; | |
1198 | return \"mov%e4.%m4 [%3=%1%S2],%0\"; | |
1199 | }") | |
1200 | \f | |
1201 | ;; FIXME: See movsi. | |
1202 | ||
1203 | (define_insn "movhi" | |
1204 | [(set | |
1205 | (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,Q>,r,Q>,r,r,r,g,g,r") | |
1206 | (match_operand:HI 1 "general_operand" "r,Q>,M,M,I,r,L,O,n,M,r,g"))] | |
1207 | "" | |
1208 | "* | |
1209 | { | |
1210 | switch (which_alternative) | |
1211 | { | |
1212 | case 0: | |
1213 | case 1: | |
1214 | case 5: | |
1215 | case 10: | |
1216 | case 11: | |
1217 | return \"move.w %1,%0\"; | |
1218 | case 2: | |
1219 | case 3: | |
1220 | case 9: | |
1221 | return \"clear.w %0\"; | |
1222 | case 4: | |
1223 | return \"moveq %1,%0\"; | |
1224 | case 6: | |
1225 | case 8: | |
1226 | if (INTVAL (operands[1]) < 256 && INTVAL (operands[1]) >= -128) | |
1227 | { | |
1228 | if (INTVAL (operands[1]) > 0) | |
1229 | return \"movu.b %1,%0\"; | |
1230 | return \"movs.b %1,%0\"; | |
1231 | } | |
1232 | return \"move.w %1,%0\"; | |
1233 | case 7: | |
1234 | return \"movEq %b1,%0\"; | |
1235 | default: | |
1236 | return \"BOGUS: %1 to %0\"; | |
1237 | } | |
1238 | }" | |
1239 | [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,yes,no,no,no,no") | |
1240 | (set (attr "cc") | |
1241 | (if_then_else (eq_attr "alternative" "7") | |
1242 | (const_string "clobber") | |
1243 | (const_string "normal")))]) | |
1244 | ||
1245 | (define_insn "movstricthi" | |
1246 | [(set | |
1247 | (strict_low_part | |
1248 | (match_operand:HI 0 "nonimmediate_operand" "+r,r,r,Q>,Q>,g,r,g")) | |
1249 | (match_operand:HI 1 "general_operand" "r,Q>,M,M,r,M,g,r"))] | |
1250 | "" | |
1251 | "@ | |
1252 | move.w %1,%0 | |
1253 | move.w %1,%0 | |
1254 | clear.w %0 | |
1255 | clear.w %0 | |
1256 | move.w %1,%0 | |
1257 | clear.w %0 | |
1258 | move.w %1,%0 | |
1259 | move.w %1,%0" | |
1260 | [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")]) | |
1261 | \f | |
1262 | (define_insn "movqi" | |
1263 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,Q>,r,r,Q>,r,g,g,r,r") | |
1264 | (match_operand:QI 1 "general_operand" "r,r,Q>,M,M,I,M,r,O,g"))] | |
1265 | "" | |
1266 | "@ | |
1267 | move.b %1,%0 | |
1268 | move.b %1,%0 | |
1269 | move.b %1,%0 | |
1270 | clear.b %0 | |
1271 | clear.b %0 | |
1272 | moveq %1,%0 | |
1273 | clear.b %0 | |
1274 | move.b %1,%0 | |
1275 | moveq %b1,%0 | |
1276 | move.b %1,%0" | |
1277 | [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,yes,no") | |
1278 | (set (attr "cc") | |
1279 | (if_then_else (eq_attr "alternative" "8") | |
1280 | (const_string "clobber") | |
1281 | (const_string "normal")))]) | |
1282 | ||
1283 | (define_insn "movstrictqi" | |
1284 | [(set (strict_low_part | |
1285 | (match_operand:QI 0 "nonimmediate_operand" "+r,Q>,r,r,Q>,g,g,r")) | |
1286 | (match_operand:QI 1 "general_operand" "r,r,Q>,M,M,M,r,g"))] | |
1287 | "" | |
1288 | "@ | |
1289 | move.b %1,%0 | |
1290 | move.b %1,%0 | |
1291 | move.b %1,%0 | |
1292 | clear.b %0 | |
1293 | clear.b %0 | |
1294 | clear.b %0 | |
1295 | move.b %1,%0 | |
1296 | move.b %1,%0" | |
1297 | [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")]) | |
1298 | ||
1299 | ;; The valid "quick" bit-patterns are, except for 0.0, denormalized | |
1300 | ;; values REALLY close to 0, and some NaN:s (I think; their exponent is | |
1301 | ;; all ones); the worthwhile one is "0.0". | |
1302 | ;; It will use clear, so we know ALL types of immediate 0 never change cc. | |
1303 | ||
1304 | (define_insn "movsf" | |
1305 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,Q>,r,r,Q>,g,g,r") | |
1306 | (match_operand:SF 1 "general_operand" "r,r,Q>,G,G,G,r,g"))] | |
1307 | "" | |
1308 | "@ | |
1309 | move.d %1,%0 | |
1310 | move.d %1,%0 | |
1311 | move.d %1,%0 | |
1312 | clear.d %0 | |
1313 | clear.d %0 | |
1314 | clear.d %0 | |
1315 | move.d %1,%0 | |
1316 | move.d %1,%0" | |
1317 | [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")]) | |
1318 | \f | |
1319 | ||
1320 | ;; Sign- and zero-extend insns with standard names. | |
1321 | ;; Those for integer source operand are ordered with the widest source | |
1322 | ;; type first. | |
1323 | ||
1324 | ;; Sign-extend. | |
1325 | ||
1326 | (define_insn "extendsidi2" | |
1327 | [(set (match_operand:DI 0 "register_operand" "=r") | |
1328 | (sign_extend:DI (match_operand:SI 1 "general_operand" "g")))] | |
1329 | "" | |
1330 | "move.d %1,%M0\;smi %H0\;neg.d %H0,%H0") | |
1331 | ||
1332 | (define_insn "extendhidi2" | |
1333 | [(set (match_operand:DI 0 "register_operand" "=r") | |
1334 | (sign_extend:DI (match_operand:HI 1 "general_operand" "g")))] | |
1335 | "" | |
1336 | "movs.w %1,%M0\;smi %H0\;neg.d %H0,%H0") | |
1337 | ||
1338 | (define_insn "extendhisi2" | |
1339 | [(set (match_operand:SI 0 "register_operand" "=r,r,r") | |
1340 | (sign_extend:SI (match_operand:HI 1 "general_operand" "r,Q>,g")))] | |
1341 | "" | |
1342 | "movs.w %1,%0" | |
1343 | [(set_attr "slottable" "yes,yes,no")]) | |
1344 | ||
1345 | (define_insn "extendqidi2" | |
1346 | [(set (match_operand:DI 0 "register_operand" "=r") | |
1347 | (sign_extend:DI (match_operand:QI 1 "general_operand" "g")))] | |
1348 | "" | |
1349 | "movs.b %1,%M0\;smi %H0\;neg.d %H0,%H0") | |
1350 | ||
1351 | (define_insn "extendqisi2" | |
1352 | [(set (match_operand:SI 0 "register_operand" "=r,r,r") | |
1353 | (sign_extend:SI (match_operand:QI 1 "general_operand" "r,Q>,g")))] | |
1354 | "" | |
1355 | "movs.b %1,%0" | |
1356 | [(set_attr "slottable" "yes,yes,no")]) | |
1357 | ||
839a4992 | 1358 | ;; To do a byte->word extension, extend to dword, exept that the top half |
0b85d816 HPN |
1359 | ;; of the register will be clobbered. FIXME: Perhaps this is not needed. |
1360 | ||
1361 | (define_insn "extendqihi2" | |
1362 | [(set (match_operand:HI 0 "register_operand" "=r,r,r") | |
1363 | (sign_extend:HI (match_operand:QI 1 "general_operand" "r,Q>,g")))] | |
1364 | "" | |
1365 | "movs.b %1,%0" | |
1366 | [(set_attr "slottable" "yes,yes,no")]) | |
1367 | \f | |
1368 | ||
1369 | ;; Zero-extend. The DImode ones are synthesized by gcc, so we don't | |
1370 | ;; specify them here. | |
1371 | ||
1372 | (define_insn "zero_extendhisi2" | |
1373 | [(set (match_operand:SI 0 "register_operand" "=r,r,r") | |
1374 | (zero_extend:SI | |
1375 | (match_operand:HI 1 "nonimmediate_operand" "r,Q>,m")))] | |
1376 | "" | |
1377 | "movu.w %1,%0" | |
1378 | [(set_attr "slottable" "yes,yes,no")]) | |
1379 | ||
1380 | (define_insn "zero_extendqisi2" | |
1381 | [(set (match_operand:SI 0 "register_operand" "=r,r,r") | |
1382 | (zero_extend:SI | |
1383 | (match_operand:QI 1 "nonimmediate_operand" "r,Q>,m")))] | |
1384 | "" | |
1385 | "movu.b %1,%0" | |
1386 | [(set_attr "slottable" "yes,yes,no")]) | |
1387 | ||
1388 | ;; Same comment as sign-extend QImode to HImode above applies. | |
1389 | ||
1390 | (define_insn "zero_extendqihi2" | |
1391 | [(set (match_operand:HI 0 "register_operand" "=r,r,r") | |
1392 | (zero_extend:HI | |
1393 | (match_operand:QI 1 "nonimmediate_operand" "r,Q>,m")))] | |
1394 | "" | |
1395 | "movu.b %1,%0" | |
1396 | [(set_attr "slottable" "yes,yes,no")]) | |
1397 | \f | |
1398 | ;; All kinds of arithmetic and logical instructions. | |
1399 | ;; | |
1400 | ;; First, anonymous patterns to match addressing modes with | |
1401 | ;; side-effects. | |
1402 | ;; | |
1403 | ;; op.S [rx=ry+I],rz; (add, sub, or, and, bound). | |
1404 | ;; | |
1405 | ;; [rx=ry+rz.S] | |
1406 | ;; FIXME: These could have anonymous mode for operand 0. | |
1407 | ||
1408 | ;; QImode | |
1409 | ||
1410 | (define_insn "*op_sideqi_biap" | |
1411 | [(set (match_operand:QI 0 "register_operand" "=r,r") | |
1412 | (match_operator:QI | |
1413 | 6 "cris_orthogonal_operator" | |
1414 | [(match_operand:QI 1 "register_operand" "0,0") | |
1415 | (mem:QI (plus:SI | |
1416 | (mult:SI (match_operand:SI 2 "register_operand" "r,r") | |
1417 | (match_operand:SI 3 "const_int_operand" "n,n")) | |
1418 | (match_operand:SI 4 "register_operand" "r,r")))])) | |
1419 | (set (match_operand:SI 5 "register_operand" "=*4,r") | |
1420 | (plus:SI (mult:SI (match_dup 2) | |
1421 | (match_dup 3)) | |
1422 | (match_dup 4)))] | |
1423 | "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" | |
1424 | "@ | |
1425 | # | |
1426 | %x6.%s0 [%5=%4+%2%T3],%0") | |
1427 | ||
1428 | ;; HImode | |
1429 | ||
1430 | (define_insn "*op_sidehi_biap" | |
1431 | [(set (match_operand:HI 0 "register_operand" "=r,r") | |
1432 | (match_operator:HI | |
1433 | 6 "cris_orthogonal_operator" | |
1434 | [(match_operand:HI 1 "register_operand" "0,0") | |
1435 | (mem:HI (plus:SI | |
1436 | (mult:SI (match_operand:SI 2 "register_operand" "r,r") | |
1437 | (match_operand:SI 3 "const_int_operand" "n,n")) | |
1438 | (match_operand:SI 4 "register_operand" "r,r")))])) | |
1439 | (set (match_operand:SI 5 "register_operand" "=*4,r") | |
1440 | (plus:SI (mult:SI (match_dup 2) | |
1441 | (match_dup 3)) | |
1442 | (match_dup 4)))] | |
1443 | "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" | |
1444 | "@ | |
1445 | # | |
1446 | %x6.%s0 [%5=%4+%2%T3],%0") | |
1447 | ||
1448 | ;; SImode | |
1449 | ||
1450 | (define_insn "*op_sidesi_biap" | |
1451 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
1452 | (match_operator:SI | |
1453 | 6 "cris_orthogonal_operator" | |
1454 | [(match_operand:SI 1 "register_operand" "0,0") | |
1455 | (mem:SI (plus:SI | |
1456 | (mult:SI (match_operand:SI 2 "register_operand" "r,r") | |
1457 | (match_operand:SI 3 "const_int_operand" "n,n")) | |
1458 | (match_operand:SI 4 "register_operand" "r,r")))])) | |
1459 | (set (match_operand:SI 5 "register_operand" "=*4,r") | |
1460 | (plus:SI (mult:SI (match_dup 2) | |
1461 | (match_dup 3)) | |
1462 | (match_dup 4)))] | |
1463 | "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" | |
1464 | "@ | |
1465 | # | |
1466 | %x6.%s0 [%5=%4+%2%T3],%0") | |
1467 | \f | |
1468 | ;; [rx=ry+i] ([%4=%2+%3]) | |
1469 | ;; FIXME: These could have anonymous mode for operand 0. | |
1470 | ||
1471 | ;; QImode | |
1472 | ||
1473 | (define_insn "*op_sideqi" | |
1474 | [(set (match_operand:QI 0 "register_operand" "=r,r,r") | |
1475 | (match_operator:QI | |
1476 | 5 "cris_orthogonal_operator" | |
1477 | [(match_operand:QI 1 "register_operand" "0,0,0") | |
1478 | (mem:QI (plus:SI | |
1479 | (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") | |
747a0d9d | 1480 | (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))])) |
0b85d816 HPN |
1481 | (set (match_operand:SI 4 "register_operand" "=*2,r,r") |
1482 | (plus:SI (match_dup 2) | |
1483 | (match_dup 3)))] | |
1484 | "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" | |
1485 | "* | |
1486 | { | |
1487 | if (which_alternative == 0 | |
1488 | && (GET_CODE (operands[3]) != CONST_INT | |
1489 | || INTVAL (operands[3]) > 127 | |
1490 | || INTVAL (operands[3]) < -128 | |
1491 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') | |
1492 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) | |
1493 | return \"#\"; | |
1494 | return \"%x5.%s0 [%4=%2%S3],%0\"; | |
1495 | }") | |
1496 | ||
1497 | ;; HImode | |
1498 | ||
1499 | (define_insn "*op_sidehi" | |
1500 | [(set (match_operand:HI 0 "register_operand" "=r,r,r") | |
1501 | (match_operator:HI | |
1502 | 5 "cris_orthogonal_operator" | |
1503 | [(match_operand:HI 1 "register_operand" "0,0,0") | |
1504 | (mem:HI (plus:SI | |
1505 | (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") | |
747a0d9d | 1506 | (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))])) |
0b85d816 HPN |
1507 | (set (match_operand:SI 4 "register_operand" "=*2,r,r") |
1508 | (plus:SI (match_dup 2) | |
1509 | (match_dup 3)))] | |
1510 | "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" | |
1511 | "* | |
1512 | { | |
1513 | if (which_alternative == 0 | |
1514 | && (GET_CODE (operands[3]) != CONST_INT | |
1515 | || INTVAL (operands[3]) > 127 | |
1516 | || INTVAL (operands[3]) < -128 | |
1517 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') | |
1518 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) | |
1519 | return \"#\"; | |
1520 | return \"%x5.%s0 [%4=%2%S3],%0\"; | |
1521 | }") | |
1522 | ||
1523 | ;; SImode | |
1524 | ||
1525 | (define_insn "*op_sidesi" | |
1526 | [(set (match_operand:SI 0 "register_operand" "=r,r,r") | |
1527 | (match_operator:SI | |
1528 | 5 "cris_orthogonal_operator" | |
1529 | [(match_operand:SI 1 "register_operand" "0,0,0") | |
1530 | (mem:SI (plus:SI | |
1531 | (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") | |
747a0d9d | 1532 | (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))])) |
0b85d816 HPN |
1533 | (set (match_operand:SI 4 "register_operand" "=*2,r,r") |
1534 | (plus:SI (match_dup 2) | |
1535 | (match_dup 3)))] | |
1536 | "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" | |
1537 | "* | |
1538 | { | |
1539 | if (which_alternative == 0 | |
1540 | && (GET_CODE (operands[3]) != CONST_INT | |
1541 | || INTVAL (operands[3]) > 127 | |
1542 | || INTVAL (operands[3]) < -128 | |
1543 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') | |
1544 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) | |
1545 | return \"#\"; | |
1546 | return \"%x5.%s0 [%4=%2%S3],%0\"; | |
1547 | }") | |
1548 | \f | |
1549 | ;; To match all cases for commutative operations we may have to have the | |
1550 | ;; following pattern for add, or & and. I do not know really, but it does | |
1551 | ;; not break anything. | |
1552 | ;; | |
1553 | ;; FIXME: This really ought to be checked. | |
1554 | ;; | |
1555 | ;; op.S [rx=ry+I],rz; | |
1556 | ;; | |
1557 | ;; [rx=ry+rz.S] | |
1558 | ;; FIXME: These could have anonymous mode for operand 0. | |
1559 | ||
1560 | ;; QImode | |
1561 | ||
1562 | (define_insn "*op_swap_sideqi_biap" | |
1563 | [(set (match_operand:QI 0 "register_operand" "=r,r") | |
1564 | (match_operator:QI | |
1565 | 6 "cris_commutative_orth_op" | |
1566 | [(mem:QI (plus:SI | |
1567 | (mult:SI (match_operand:SI 2 "register_operand" "r,r") | |
1568 | (match_operand:SI 3 "const_int_operand" "n,n")) | |
1569 | (match_operand:SI 4 "register_operand" "r,r"))) | |
1570 | (match_operand:QI 1 "register_operand" "0,0")])) | |
1571 | (set (match_operand:SI 5 "register_operand" "=*4,r") | |
1572 | (plus:SI (mult:SI (match_dup 2) | |
1573 | (match_dup 3)) | |
1574 | (match_dup 4)))] | |
1575 | "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" | |
1576 | "@ | |
1577 | # | |
1578 | %x6.%s0 [%5=%4+%2%T3],%0") | |
1579 | ||
1580 | ;; HImode | |
1581 | ||
1582 | (define_insn "*op_swap_sidehi_biap" | |
1583 | [(set (match_operand:HI 0 "register_operand" "=r,r") | |
1584 | (match_operator:HI | |
1585 | 6 "cris_commutative_orth_op" | |
1586 | [(mem:HI (plus:SI | |
1587 | (mult:SI (match_operand:SI 2 "register_operand" "r,r") | |
1588 | (match_operand:SI 3 "const_int_operand" "n,n")) | |
1589 | (match_operand:SI 4 "register_operand" "r,r"))) | |
1590 | (match_operand:HI 1 "register_operand" "0,0")])) | |
1591 | (set (match_operand:SI 5 "register_operand" "=*4,r") | |
1592 | (plus:SI (mult:SI (match_dup 2) | |
1593 | (match_dup 3)) | |
1594 | (match_dup 4)))] | |
1595 | "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" | |
1596 | "@ | |
1597 | # | |
1598 | %x6.%s0 [%5=%4+%2%T3],%0") | |
1599 | ||
1600 | ;; SImode | |
1601 | ||
1602 | (define_insn "*op_swap_sidesi_biap" | |
1603 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
1604 | (match_operator:SI | |
1605 | 6 "cris_commutative_orth_op" | |
1606 | [(mem:SI (plus:SI | |
1607 | (mult:SI (match_operand:SI 2 "register_operand" "r,r") | |
1608 | (match_operand:SI 3 "const_int_operand" "n,n")) | |
1609 | (match_operand:SI 4 "register_operand" "r,r"))) | |
1610 | (match_operand:SI 1 "register_operand" "0,0")])) | |
1611 | (set (match_operand:SI 5 "register_operand" "=*4,r") | |
1612 | (plus:SI (mult:SI (match_dup 2) | |
1613 | (match_dup 3)) | |
1614 | (match_dup 4)))] | |
1615 | "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" | |
1616 | "@ | |
1617 | # | |
1618 | %x6.%s0 [%5=%4+%2%T3],%0") | |
1619 | \f | |
1620 | ;; [rx=ry+i] ([%4=%2+%3]) | |
1621 | ;; FIXME: These could have anonymous mode for operand 0. | |
1622 | ||
1623 | ;; QImode | |
1624 | ||
1625 | (define_insn "*op_swap_sideqi" | |
1626 | [(set (match_operand:QI 0 "register_operand" "=r,r,r") | |
1627 | (match_operator:QI | |
1628 | 5 "cris_commutative_orth_op" | |
1629 | [(mem:QI | |
1630 | (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") | |
747a0d9d | 1631 | (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn"))) |
0b85d816 HPN |
1632 | (match_operand:QI 1 "register_operand" "0,0,0")])) |
1633 | (set (match_operand:SI 4 "register_operand" "=*2,r,r") | |
1634 | (plus:SI (match_dup 2) | |
1635 | (match_dup 3)))] | |
1636 | "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" | |
1637 | "* | |
1638 | { | |
1639 | if (which_alternative == 0 | |
1640 | && (GET_CODE (operands[3]) != CONST_INT | |
1641 | || INTVAL (operands[3]) > 127 | |
1642 | || INTVAL (operands[3]) < -128 | |
1643 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') | |
1644 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) | |
1645 | return \"#\"; | |
1646 | return \"%x5.%s0 [%4=%2%S3],%0\"; | |
1647 | }") | |
1648 | ||
1649 | ;; HImode | |
1650 | ||
1651 | (define_insn "*op_swap_sidehi" | |
1652 | [(set (match_operand:HI 0 "register_operand" "=r,r,r") | |
1653 | (match_operator:HI | |
1654 | 5 "cris_commutative_orth_op" | |
1655 | [(mem:HI | |
1656 | (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") | |
747a0d9d | 1657 | (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn"))) |
0b85d816 HPN |
1658 | (match_operand:HI 1 "register_operand" "0,0,0")])) |
1659 | (set (match_operand:SI 4 "register_operand" "=*2,r,r") | |
1660 | (plus:SI (match_dup 2) | |
1661 | (match_dup 3)))] | |
1662 | "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" | |
1663 | "* | |
1664 | { | |
1665 | if (which_alternative == 0 | |
1666 | && (GET_CODE (operands[3]) != CONST_INT | |
1667 | || INTVAL (operands[3]) > 127 | |
1668 | || INTVAL (operands[3]) < -128 | |
1669 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') | |
1670 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) | |
1671 | return \"#\"; | |
1672 | return \"%x5.%s0 [%4=%2%S3],%0\"; | |
1673 | }") | |
1674 | ||
1675 | ;; SImode | |
1676 | ||
1677 | (define_insn "*op_swap_sidesi" | |
1678 | [(set (match_operand:SI 0 "register_operand" "=r,r,r") | |
1679 | (match_operator:SI | |
1680 | 5 "cris_commutative_orth_op" | |
1681 | [(mem:SI | |
1682 | (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") | |
747a0d9d | 1683 | (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn"))) |
0b85d816 HPN |
1684 | (match_operand:SI 1 "register_operand" "0,0,0")])) |
1685 | (set (match_operand:SI 4 "register_operand" "=*2,r,r") | |
1686 | (plus:SI (match_dup 2) | |
1687 | (match_dup 3)))] | |
1688 | "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" | |
1689 | "* | |
1690 | { | |
1691 | if (which_alternative == 0 | |
1692 | && (GET_CODE (operands[3]) != CONST_INT | |
1693 | || INTVAL (operands[3]) > 127 | |
1694 | || INTVAL (operands[3]) < -128 | |
1695 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') | |
1696 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) | |
1697 | return \"#\"; | |
1698 | return \"%x5.%s0 [%4=%2%S3],%0\"; | |
1699 | }") | |
1700 | \f | |
1701 | ;; Add operations, standard names. | |
1702 | ||
1703 | ;; Note that for the 'P' constraint, the high part can be -1 or 0. We | |
1704 | ;; output the insn through the 'A' output modifier as "adds.w" and "addq", | |
1705 | ;; respectively. | |
1706 | (define_insn "adddi3" | |
1707 | [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r") | |
1708 | (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,r") | |
1709 | (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))] | |
1710 | "" | |
1711 | "@ | |
1712 | addq %2,%M0\;ax\;addq 0,%H0 | |
1713 | subq %n2,%M0\;ax\;subq 0,%H0 | |
1714 | add%e2.%z2 %2,%M0\;ax\;%A2 %H2,%H0 | |
1715 | add.d %M2,%M0\;ax\;add.d %H2,%H0 | |
1716 | add.d %M2,%M1,%M0\;ax\;add.d %H2,%H1,%H0") | |
1717 | ||
1718 | (define_insn "addsi3" | |
1719 | [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r") | |
1720 | (plus:SI | |
1721 | (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r") | |
1722 | (match_operand:SI 2 "general_operand" "r,Q>,J,N,n,g,!To,0")))] | |
1723 | ||
1724 | ;; The last constraint is due to that after reload, the '%' is not | |
1725 | ;; honored, and canonicalization doesn't care about keeping the same | |
1726 | ;; register as in destination. This will happen after insn splitting. | |
1727 | ;; gcc <= 2.7.2. FIXME: Check for gcc-2.9x | |
1728 | ||
1729 | "" | |
1730 | "* | |
1731 | { | |
1732 | switch (which_alternative) | |
1733 | { | |
1734 | case 0: | |
1735 | case 1: | |
1736 | return \"add.d %2,%0\"; | |
1737 | case 2: | |
1738 | return \"addq %2,%0\"; | |
1739 | case 3: | |
1740 | return \"subq %n2,%0\"; | |
1741 | case 4: | |
1742 | /* 'Known value', but not in -63..63. | |
1743 | Check if addu/subu may be used. */ | |
1744 | if (INTVAL (operands[2]) > 0) | |
1745 | { | |
1746 | if (INTVAL (operands[2]) < 256) | |
1747 | return \"addu.b %2,%0\"; | |
1748 | if (INTVAL (operands[2]) < 65536) | |
1749 | return \"addu.w %2,%0\"; | |
1750 | } | |
1751 | else | |
1752 | { | |
1753 | if (INTVAL (operands[2]) >= -255) | |
1754 | return \"subu.b %n2,%0\"; | |
1755 | if (INTVAL (operands[2]) >= -65535) | |
1756 | return \"subu.w %n2,%0\"; | |
1757 | } | |
1758 | return \"add.d %2,%0\"; | |
1759 | case 6: | |
1760 | return \"add.d %2,%1,%0\"; | |
1761 | case 5: | |
1762 | return \"add.d %2,%0\"; | |
1763 | case 7: | |
1764 | return \"add.d %1,%0\"; | |
1765 | default: | |
1766 | return \"BOGUS addsi %2+%1 to %0\"; | |
1767 | } | |
1768 | }" | |
1769 | [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,yes")]) | |
1770 | \f | |
1771 | (define_insn "addhi3" | |
1772 | [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r") | |
1773 | (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,r") | |
1774 | (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))] | |
1775 | "" | |
1776 | "@ | |
1777 | add.w %2,%0 | |
1778 | add.w %2,%0 | |
1779 | addq %2,%0 | |
1780 | subq %n2,%0 | |
1781 | add.w %2,%0 | |
1782 | add.w %2,%1,%0" | |
1783 | [(set_attr "slottable" "yes,yes,yes,yes,no,no") | |
1784 | (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")]) | |
1785 | ||
1786 | (define_insn "addqi3" | |
1787 | [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r,r") | |
1788 | (plus:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0,r") | |
1789 | (match_operand:QI 2 "general_operand" "r,Q>,J,N,O,g,!To")))] | |
1790 | "" | |
1791 | "@ | |
1792 | add.b %2,%0 | |
1793 | add.b %2,%0 | |
1794 | addq %2,%0 | |
1795 | subq %n2,%0 | |
1796 | subQ -%b2,%0 | |
1797 | add.b %2,%0 | |
1798 | add.b %2,%1,%0" | |
1799 | [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no") | |
1800 | (set_attr "cc" "normal,normal,clobber,clobber,clobber,normal,normal")]) | |
1801 | \f | |
1802 | ;; Subtract. | |
1803 | ;; | |
1804 | ;; Note that because of insn canonicalization these will *seldom* but | |
1805 | ;; rarely be used with a known constant as an operand. | |
1806 | ||
1807 | ;; Note that for the 'P' constraint, the high part can be -1 or 0. We | |
1808 | ;; output the insn through the 'D' output modifier as "subs.w" and "subq", | |
1809 | ;; respectively. | |
1810 | (define_insn "subdi3" | |
1811 | [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r") | |
1812 | (minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0,r") | |
1813 | (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))] | |
1814 | "" | |
1815 | "@ | |
1816 | subq %2,%M0\;ax\;subq 0,%H0 | |
1817 | addq %n2,%M0\;ax\;addq 0,%H0 | |
1818 | sub%e2.%z2 %2,%M0\;ax\;%D2 %H2,%H0 | |
1819 | sub.d %M2,%M0\;ax\;sub.d %H2,%H0 | |
1820 | sub.d %M2,%M1,%M0\;ax\;sub.d %H2,%H1,%H0") | |
1821 | ||
1822 | (define_insn "subsi3" | |
1823 | [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r") | |
1824 | (minus:SI | |
1825 | (match_operand:SI 1 "register_operand" "0,0,0,0,0,0,0,r") | |
1826 | (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g,!To")))] | |
1827 | "" | |
1828 | ||
1829 | ;; This does not do the optimal: "addu.w 65535,r0" when %2 is negative. | |
1830 | ;; But then again, %2 should not be negative. | |
1831 | ||
1832 | "@ | |
1833 | sub.d %2,%0 | |
1834 | sub.d %2,%0 | |
1835 | subq %2,%0 | |
1836 | addq %n2,%0 | |
1837 | sub%e2.%z2 %2,%0 | |
1838 | sub.d %2,%0 | |
1839 | sub.d %2,%0 | |
1840 | sub.d %2,%1,%0" | |
1841 | [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no")]) | |
1842 | \f | |
1843 | (define_insn "subhi3" | |
1844 | [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r") | |
1845 | (minus:HI (match_operand:HI 1 "register_operand" "0,0,0,0,0,r") | |
1846 | (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))] | |
1847 | "" | |
1848 | "@ | |
1849 | sub.w %2,%0 | |
1850 | sub.w %2,%0 | |
1851 | subq %2,%0 | |
1852 | addq %n2,%0 | |
1853 | sub.w %2,%0 | |
1854 | sub.w %2,%1,%0" | |
1855 | [(set_attr "slottable" "yes,yes,yes,yes,no,no") | |
1856 | (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")]) | |
1857 | ||
1858 | (define_insn "subqi3" | |
1859 | [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r") | |
1860 | (minus:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,r") | |
1861 | (match_operand:QI 2 "general_operand" "r,Q>,J,N,g,!To")))] | |
1862 | "" | |
1863 | "@ | |
1864 | sub.b %2,%0 | |
1865 | sub.b %2,%0 | |
1866 | subq %2,%0 | |
1867 | addq %2,%0 | |
1868 | sub.b %2,%0 | |
1869 | sub.b %2,%1,%0" | |
1870 | [(set_attr "slottable" "yes,yes,yes,yes,no,no") | |
1871 | (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")]) | |
1872 | \f | |
1873 | ;; CRIS has some add/sub-with-sign/zero-extend instructions. | |
1874 | ;; Although these perform sign/zero-extension to SImode, they are | |
1875 | ;; equally applicable for the HImode case. | |
1876 | ;; FIXME: Check; GCC should handle the widening. | |
1877 | ;; Note that these must be located after the normal add/sub patterns, | |
1878 | ;; so not to get constants into any less specific operands. | |
1879 | ;; | |
1880 | ;; Extend with add/sub and side-effect. | |
1881 | ;; | |
1882 | ;; ADDS/SUBS/ADDU/SUBU and BOUND, which needs a check for zero_extend | |
1883 | ;; | |
1884 | ;; adds/subs/addu/subu bound [rx=ry+rz.S] | |
1885 | ;; FIXME: These could have anonymous mode for operand 0. | |
1886 | ||
1887 | ;; QImode to HImode | |
1888 | ;; FIXME: GCC should widen. | |
1889 | ||
1890 | (define_insn "*extopqihi_side_biap" | |
1891 | [(set (match_operand:HI 0 "register_operand" "=r,r") | |
1892 | (match_operator:HI | |
d2f55c5c | 1893 | 6 "cris_additive_operand_extend_operator" |
0b85d816 HPN |
1894 | [(match_operand:HI 1 "register_operand" "0,0") |
1895 | (match_operator:HI | |
1896 | 7 "cris_extend_operator" | |
1897 | [(mem:QI (plus:SI | |
1898 | (mult:SI (match_operand:SI 2 "register_operand" "r,r") | |
1899 | (match_operand:SI 3 "const_int_operand" "n,n")) | |
1900 | (match_operand:SI 4 "register_operand" "r,r")))])])) | |
1901 | (set (match_operand:SI 5 "register_operand" "=*4,r") | |
1902 | (plus:SI (mult:SI (match_dup 2) | |
1903 | (match_dup 3)) | |
1904 | (match_dup 4)))] | |
d2f55c5c | 1905 | "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" |
0b85d816 HPN |
1906 | "@ |
1907 | # | |
1908 | %x6%e7.%m7 [%5=%4+%2%T3],%0") | |
1909 | ||
1910 | ;; QImode to SImode | |
1911 | ||
1912 | (define_insn "*extopqisi_side_biap" | |
1913 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
1914 | (match_operator:SI | |
1915 | 6 "cris_operand_extend_operator" | |
1916 | [(match_operand:SI 1 "register_operand" "0,0") | |
1917 | (match_operator:SI | |
1918 | 7 "cris_extend_operator" | |
1919 | [(mem:QI (plus:SI | |
1920 | (mult:SI (match_operand:SI 2 "register_operand" "r,r") | |
1921 | (match_operand:SI 3 "const_int_operand" "n,n")) | |
1922 | (match_operand:SI 4 "register_operand" "r,r")))])])) | |
1923 | (set (match_operand:SI 5 "register_operand" "=*4,r") | |
1924 | (plus:SI (mult:SI (match_dup 2) | |
1925 | (match_dup 3)) | |
1926 | (match_dup 4)))] | |
d2f55c5c | 1927 | "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[7]) == ZERO_EXTEND) |
0b85d816 HPN |
1928 | && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" |
1929 | "@ | |
1930 | # | |
1931 | %x6%e7.%m7 [%5=%4+%2%T3],%0") | |
1932 | ||
1933 | ;; HImode to SImode | |
1934 | ||
1935 | (define_insn "*extophisi_side_biap" | |
1936 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
1937 | (match_operator:SI | |
1938 | 6 "cris_operand_extend_operator" | |
1939 | [(match_operand:SI 1 "register_operand" "0,0") | |
1940 | (match_operator:SI | |
1941 | 7 "cris_extend_operator" | |
1942 | [(mem:HI (plus:SI | |
1943 | (mult:SI (match_operand:SI 2 "register_operand" "r,r") | |
1944 | (match_operand:SI 3 "const_int_operand" "n,n")) | |
1945 | (match_operand:SI 4 "register_operand" "r,r")))])])) | |
1946 | (set (match_operand:SI 5 "register_operand" "=*4,r") | |
1947 | (plus:SI (mult:SI (match_dup 2) | |
1948 | (match_dup 3)) | |
1949 | (match_dup 4)))] | |
d2f55c5c | 1950 | "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[7]) == ZERO_EXTEND) |
0b85d816 HPN |
1951 | && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" |
1952 | "@ | |
1953 | # | |
1954 | %x6%e7.%m7 [%5=%4+%2%T3],%0") | |
1955 | \f | |
1956 | ||
1957 | ;; [rx=ry+i] | |
1958 | ;; FIXME: These could have anonymous mode for operand 0. | |
1959 | ||
1960 | ;; QImode to HImode | |
1961 | ||
1962 | (define_insn "*extopqihi_side" | |
1963 | [(set (match_operand:HI 0 "register_operand" "=r,r,r") | |
1964 | (match_operator:HI | |
d2f55c5c | 1965 | 5 "cris_additive_operand_extend_operator" |
0b85d816 HPN |
1966 | [(match_operand:HI 1 "register_operand" "0,0,0") |
1967 | (match_operator:HI | |
1968 | 6 "cris_extend_operator" | |
1969 | [(mem:QI | |
1970 | (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") | |
747a0d9d | 1971 | (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn") |
0b85d816 HPN |
1972 | ))])])) |
1973 | (set (match_operand:SI 4 "register_operand" "=*2,r,r") | |
1974 | (plus:SI (match_dup 2) | |
1975 | (match_dup 3)))] | |
d2f55c5c | 1976 | "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" |
0b85d816 HPN |
1977 | "* |
1978 | { | |
1979 | if (which_alternative == 0 | |
1980 | && (GET_CODE (operands[3]) != CONST_INT | |
1981 | || INTVAL (operands[3]) > 127 | |
1982 | || INTVAL (operands[3]) < -128 | |
1983 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') | |
1984 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) | |
1985 | return \"#\"; | |
1986 | return \"%x5%e6.%m6 [%4=%2%S3],%0\"; | |
1987 | }") | |
1988 | ||
1989 | ;; QImode to SImode | |
1990 | ||
1991 | (define_insn "*extopqisi_side" | |
1992 | [(set (match_operand:SI 0 "register_operand" "=r,r,r") | |
1993 | (match_operator:SI | |
1994 | 5 "cris_operand_extend_operator" | |
1995 | [(match_operand:SI 1 "register_operand" "0,0,0") | |
1996 | (match_operator:SI | |
1997 | 6 "cris_extend_operator" | |
1998 | [(mem:QI | |
1999 | (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") | |
747a0d9d | 2000 | (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn") |
0b85d816 HPN |
2001 | ))])])) |
2002 | (set (match_operand:SI 4 "register_operand" "=*2,r,r") | |
2003 | (plus:SI (match_dup 2) | |
2004 | (match_dup 3)))] | |
2005 | ||
2006 | "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND) | |
2007 | && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" | |
2008 | "* | |
2009 | { | |
2010 | if (which_alternative == 0 | |
2011 | && (GET_CODE (operands[3]) != CONST_INT | |
2012 | || INTVAL (operands[3]) > 127 | |
2013 | || INTVAL (operands[3]) < -128 | |
2014 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') | |
2015 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) | |
2016 | return \"#\"; | |
2017 | return \"%x5%e6.%m6 [%4=%2%S3],%0\"; | |
2018 | }") | |
2019 | ||
2020 | ;; HImode to SImode | |
2021 | ||
2022 | (define_insn "*extophisi_side" | |
2023 | [(set (match_operand:SI 0 "register_operand" "=r,r,r") | |
2024 | (match_operator:SI | |
2025 | 5 "cris_operand_extend_operator" | |
2026 | [(match_operand:SI 1 "register_operand" "0,0,0") | |
2027 | (match_operator:SI | |
2028 | 6 "cris_extend_operator" | |
2029 | [(mem:HI | |
2030 | (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") | |
747a0d9d | 2031 | (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn") |
0b85d816 HPN |
2032 | ))])])) |
2033 | (set (match_operand:SI 4 "register_operand" "=*2,r,r") | |
2034 | (plus:SI (match_dup 2) | |
2035 | (match_dup 3)))] | |
2036 | "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND) | |
2037 | && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" | |
2038 | "* | |
2039 | { | |
2040 | if (which_alternative == 0 | |
2041 | && (GET_CODE (operands[3]) != CONST_INT | |
2042 | || INTVAL (operands[3]) > 127 | |
2043 | || INTVAL (operands[3]) < -128 | |
2044 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') | |
2045 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) | |
2046 | return \"#\"; | |
2047 | return \"%x5%e6.%m6 [%4=%2%S3],%0\"; | |
2048 | }") | |
2049 | \f | |
2050 | ||
2051 | ;; As with op.S we may have to add special pattern to match commuted | |
2052 | ;; operands to adds/addu and bound | |
2053 | ;; | |
2054 | ;; adds/addu/bound [rx=ry+rz.S] | |
2055 | ||
2056 | ;; QImode to HImode | |
2057 | ;; FIXME: GCC should widen. | |
0b85d816 HPN |
2058 | |
2059 | (define_insn "*extopqihi_swap_side_biap" | |
2060 | [(set (match_operand:HI 0 "register_operand" "=r,r") | |
d2f55c5c HPN |
2061 | (plus:HI |
2062 | (match_operator:HI | |
2063 | 6 "cris_extend_operator" | |
2064 | [(mem:QI (plus:SI | |
2065 | (mult:SI (match_operand:SI 2 "register_operand" "r,r") | |
2066 | (match_operand:SI 3 "const_int_operand" "n,n")) | |
2067 | (match_operand:SI 4 "register_operand" "r,r")))]) | |
2068 | (match_operand:HI 1 "register_operand" "0,0"))) | |
0b85d816 HPN |
2069 | (set (match_operand:SI 5 "register_operand" "=*4,r") |
2070 | (plus:SI (mult:SI (match_dup 2) | |
2071 | (match_dup 3)) | |
2072 | (match_dup 4)))] | |
d2f55c5c | 2073 | "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" |
0b85d816 HPN |
2074 | "@ |
2075 | # | |
d2f55c5c | 2076 | add%e6.b [%5=%4+%2%T3],%0") |
0b85d816 HPN |
2077 | |
2078 | ;; QImode to SImode | |
2079 | ||
2080 | (define_insn "*extopqisi_swap_side_biap" | |
2081 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
2082 | (match_operator:SI | |
2083 | 7 "cris_plus_or_bound_operator" | |
2084 | [(match_operator:SI | |
2085 | 6 "cris_extend_operator" | |
2086 | [(mem:QI (plus:SI | |
2087 | (mult:SI (match_operand:SI 2 "register_operand" "r,r") | |
2088 | (match_operand:SI 3 "const_int_operand" "n,n")) | |
2089 | (match_operand:SI 4 "register_operand" "r,r")))]) | |
2090 | (match_operand:SI 1 "register_operand" "0,0")])) | |
2091 | (set (match_operand:SI 5 "register_operand" "=*4,r") | |
2092 | (plus:SI (mult:SI (match_dup 2) | |
2093 | (match_dup 3)) | |
2094 | (match_dup 4)))] | |
d2f55c5c | 2095 | "(GET_CODE (operands[7]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND) |
0b85d816 HPN |
2096 | && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" |
2097 | "@ | |
2098 | # | |
2099 | %x7%e6.%m6 [%5=%4+%2%T3],%0") | |
2100 | ||
2101 | ;; HImode to SImode | |
2102 | (define_insn "*extophisi_swap_side_biap" | |
2103 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
2104 | (match_operator:SI | |
2105 | 7 "cris_plus_or_bound_operator" | |
2106 | [(match_operator:SI | |
2107 | 6 "cris_extend_operator" | |
2108 | [(mem:HI (plus:SI | |
2109 | (mult:SI (match_operand:SI 2 "register_operand" "r,r") | |
2110 | (match_operand:SI 3 "const_int_operand" "n,n")) | |
2111 | (match_operand:SI 4 "register_operand" "r,r")))]) | |
2112 | (match_operand:SI 1 "register_operand" "0,0")])) | |
2113 | (set (match_operand:SI 5 "register_operand" "=*4,r") | |
2114 | (plus:SI (mult:SI (match_dup 2) | |
2115 | (match_dup 3)) | |
2116 | (match_dup 4)))] | |
d2f55c5c | 2117 | "(GET_CODE (operands[7]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND) |
0b85d816 HPN |
2118 | && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" |
2119 | "@ | |
2120 | # | |
2121 | %x7%e6.%m6 [%5=%4+%2%T3],%0") | |
2122 | \f | |
2123 | ;; [rx=ry+i] | |
2124 | ;; FIXME: These could have anonymous mode for operand 0. | |
2125 | ;; FIXME: GCC should widen. | |
2126 | ||
2127 | ;; QImode to HImode | |
2128 | ||
2129 | (define_insn "*extopqihi_swap_side" | |
2130 | [(set (match_operand:HI 0 "register_operand" "=r,r,r") | |
d2f55c5c HPN |
2131 | (plus:HI |
2132 | (match_operator:HI | |
2133 | 5 "cris_extend_operator" | |
2134 | [(mem:QI (plus:SI | |
2135 | (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") | |
747a0d9d | 2136 | (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))]) |
d2f55c5c | 2137 | (match_operand:HI 1 "register_operand" "0,0,0"))) |
0b85d816 HPN |
2138 | (set (match_operand:SI 4 "register_operand" "=*2,r,r") |
2139 | (plus:SI (match_dup 2) | |
2140 | (match_dup 3)))] | |
d2f55c5c | 2141 | "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" |
0b85d816 HPN |
2142 | "* |
2143 | { | |
2144 | if (which_alternative == 0 | |
2145 | && (GET_CODE (operands[3]) != CONST_INT | |
2146 | || INTVAL (operands[3]) > 127 | |
2147 | || INTVAL (operands[3]) < -128 | |
2148 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') | |
2149 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) | |
2150 | return \"#\"; | |
d2f55c5c | 2151 | return \"add%e5.b [%4=%2%S3],%0\"; |
0b85d816 HPN |
2152 | }") |
2153 | ||
2154 | ;; QImode to SImode | |
2155 | ||
2156 | (define_insn "*extopqisi_swap_side" | |
2157 | [(set (match_operand:SI 0 "register_operand" "=r,r,r") | |
2158 | (match_operator:SI | |
2159 | 6 "cris_plus_or_bound_operator" | |
2160 | [(match_operator:SI | |
2161 | 5 "cris_extend_operator" | |
2162 | [(mem:QI (plus:SI | |
2163 | (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") | |
747a0d9d | 2164 | (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))]) |
0b85d816 HPN |
2165 | (match_operand:SI 1 "register_operand" "0,0,0")])) |
2166 | (set (match_operand:SI 4 "register_operand" "=*2,r,r") | |
2167 | (plus:SI (match_dup 2) | |
2168 | (match_dup 3)))] | |
2169 | "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[5]) == ZERO_EXTEND) | |
2170 | && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" | |
2171 | "* | |
2172 | { | |
2173 | if (which_alternative == 0 | |
2174 | && (GET_CODE (operands[3]) != CONST_INT | |
2175 | || INTVAL (operands[3]) > 127 | |
2176 | || INTVAL (operands[3]) < -128 | |
2177 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') | |
2178 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) | |
2179 | return \"#\"; | |
2180 | return \"%x6%e5.%m5 [%4=%2%S3],%0\"; | |
2181 | }") | |
2182 | ||
2183 | ;; HImode to SImode | |
2184 | ||
2185 | (define_insn "*extophisi_swap_side" | |
2186 | [(set (match_operand:SI 0 "register_operand" "=r,r,r") | |
2187 | (match_operator:SI | |
2188 | 6 "cris_plus_or_bound_operator" | |
2189 | [(match_operator:SI | |
2190 | 5 "cris_extend_operator" | |
2191 | [(mem:HI (plus:SI | |
2192 | (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") | |
747a0d9d | 2193 | (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))]) |
0b85d816 HPN |
2194 | (match_operand:SI 1 "register_operand" "0,0,0")])) |
2195 | (set (match_operand:SI 4 "register_operand" "=*2,r,r") | |
2196 | (plus:SI (match_dup 2) | |
2197 | (match_dup 3)))] | |
2198 | "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[5]) == ZERO_EXTEND) | |
2199 | && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" | |
2200 | "* | |
2201 | { | |
2202 | if (which_alternative == 0 | |
2203 | && (GET_CODE (operands[3]) != CONST_INT | |
2204 | || INTVAL (operands[3]) > 127 | |
2205 | || INTVAL (operands[3]) < -128 | |
2206 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') | |
2207 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) | |
2208 | return \"#\"; | |
2209 | return \"%x6%e5.%m5 [%4=%2%S3],%0\"; | |
2210 | }") | |
2211 | \f | |
2212 | ;; Extend versions (zero/sign) of normal add/sub (no side-effects). | |
2213 | ;; FIXME: These could have anonymous mode for operand 0. | |
2214 | ||
2215 | ;; QImode to HImode | |
2216 | ;; FIXME: GCC should widen. | |
2217 | ||
2218 | (define_insn "*extopqihi" | |
2219 | [(set (match_operand:HI 0 "register_operand" "=r,r,r,r") | |
2220 | (match_operator:HI | |
d2f55c5c | 2221 | 3 "cris_additive_operand_extend_operator" |
0b85d816 HPN |
2222 | [(match_operand:HI 1 "register_operand" "0,0,0,r") |
2223 | (match_operator:HI | |
2224 | 4 "cris_extend_operator" | |
2225 | [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))] | |
d2f55c5c | 2226 | "GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD |
0b85d816 HPN |
2227 | && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)" |
2228 | "@ | |
2229 | %x3%e4.%m4 %2,%0 | |
2230 | %x3%e4.%m4 %2,%0 | |
2231 | %x3%e4.%m4 %2,%0 | |
2232 | %x3%e4.%m4 %2,%1,%0" | |
2233 | [(set_attr "slottable" "yes,yes,no,no") | |
2234 | (set_attr "cc" "clobber")]) | |
2235 | ||
2236 | ;; QImode to SImode | |
2237 | ||
2238 | (define_insn "*extopqisi" | |
2239 | [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") | |
2240 | (match_operator:SI | |
2241 | 3 "cris_operand_extend_operator" | |
2242 | [(match_operand:SI 1 "register_operand" "0,0,0,r") | |
2243 | (match_operator:SI | |
2244 | 4 "cris_extend_operator" | |
2245 | [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))] | |
2246 | "(GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND) | |
2247 | && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD | |
2248 | && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)" | |
2249 | "@ | |
2250 | %x3%e4.%m4 %2,%0 | |
2251 | %x3%e4.%m4 %2,%0 | |
2252 | %x3%e4.%m4 %2,%0 | |
2253 | %x3%e4.%m4 %2,%1,%0" | |
2254 | [(set_attr "slottable" "yes,yes,no,no")]) | |
2255 | ||
2256 | ;; HImode to SImode | |
2257 | ||
2258 | (define_insn "*extophisi" | |
2259 | [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") | |
2260 | (match_operator:SI | |
2261 | 3 "cris_operand_extend_operator" | |
2262 | [(match_operand:SI 1 "register_operand" "0,0,0,r") | |
2263 | (match_operator:SI | |
2264 | 4 "cris_extend_operator" | |
2265 | [(match_operand:HI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))] | |
2266 | "(GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND) | |
2267 | && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD | |
2268 | && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)" | |
2269 | "@ | |
2270 | %x3%e4.%m4 %2,%0 | |
2271 | %x3%e4.%m4 %2,%0 | |
2272 | %x3%e4.%m4 %2,%0 | |
2273 | %x3%e4.%m4 %2,%1,%0" | |
2274 | [(set_attr "slottable" "yes,yes,no,no")]) | |
2275 | \f | |
2276 | ||
2277 | ;; As with the side-effect patterns, may have to have swapped operands for add. | |
2278 | ;; FIXME: *should* be redundant to gcc. | |
2279 | ||
2280 | ;; QImode to HImode | |
2281 | ||
2282 | (define_insn "*extopqihi_swap" | |
2283 | [(set (match_operand:HI 0 "register_operand" "=r,r,r,r") | |
d2f55c5c HPN |
2284 | (plus:HI |
2285 | (match_operator:HI | |
2286 | 3 "cris_extend_operator" | |
2287 | [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")]) | |
2288 | (match_operand:HI 1 "register_operand" "0,0,0,r")))] | |
2289 | "operands[1] != frame_pointer_rtx" | |
0b85d816 | 2290 | "@ |
d2f55c5c HPN |
2291 | add%e3.b %2,%0 |
2292 | add%e3.b %2,%0 | |
2293 | add%e3.b %2,%0 | |
2294 | add%e3.b %2,%1,%0" | |
0b85d816 HPN |
2295 | [(set_attr "slottable" "yes,yes,no,no") |
2296 | (set_attr "cc" "clobber")]) | |
2297 | ||
2298 | ;; QImode to SImode | |
2299 | ||
2300 | (define_insn "*extopqisi_swap" | |
2301 | [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") | |
2302 | (match_operator:SI | |
2303 | 4 "cris_plus_or_bound_operator" | |
2304 | [(match_operator:SI | |
2305 | 3 "cris_extend_operator" | |
2306 | [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")]) | |
2307 | (match_operand:SI 1 "register_operand" "0,0,0,r")]))] | |
d2f55c5c | 2308 | "(GET_CODE (operands[4]) != UMIN || GET_CODE (operands[3]) == ZERO_EXTEND) |
0b85d816 HPN |
2309 | && operands[1] != frame_pointer_rtx" |
2310 | "@ | |
2311 | %x4%e3.%m3 %2,%0 | |
2312 | %x4%e3.%m3 %2,%0 | |
2313 | %x4%e3.%m3 %2,%0 | |
2314 | %x4%e3.%m3 %2,%1,%0" | |
2315 | [(set_attr "slottable" "yes,yes,no,no")]) | |
2316 | ||
2317 | ;; HImode to SImode | |
2318 | ||
2319 | (define_insn "*extophisi_swap" | |
2320 | [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") | |
2321 | (match_operator:SI | |
2322 | 4 "cris_plus_or_bound_operator" | |
2323 | [(match_operator:SI | |
2324 | 3 "cris_extend_operator" | |
2325 | [(match_operand:HI 2 "nonimmediate_operand" "r,Q>,m,!To")]) | |
2326 | (match_operand:SI 1 "register_operand" "0,0,0,r")]))] | |
d2f55c5c | 2327 | "(GET_CODE (operands[4]) != UMIN || GET_CODE (operands[3]) == ZERO_EXTEND) |
0b85d816 HPN |
2328 | && operands[1] != frame_pointer_rtx" |
2329 | "@ | |
2330 | %x4%e3.%m3 %2,%0 | |
2331 | %x4%e3.%m3 %2,%0 | |
2332 | %x4%e3.%m3 %2,%0 | |
2333 | %x4%e3.%m3 %2,%1,%0" | |
2334 | [(set_attr "slottable" "yes,yes,no,no")]) | |
2335 | \f | |
2336 | ;; This is the special case when we use what corresponds to the | |
2337 | ;; instruction above in "casesi". Do *not* change it to use the generic | |
2338 | ;; pattern and "REG 15" as pc; I did that and it led to madness and | |
2339 | ;; maintenance problems: Instead of (as imagined) recognizing and removing | |
2340 | ;; or replacing this pattern with something simpler, other variant | |
2341 | ;; patterns were recognized or combined, including some prefix variants | |
2342 | ;; where the value in pc is not that of the next instruction (which means | |
2343 | ;; this instruction actually *is* special and *should* be marked as such). | |
2344 | ;; When switching from the "generic pattern match" approach to this simpler | |
2345 | ;; approach, there were insignificant differences in gcc, ipps and | |
2346 | ;; product code, somehow due to scratching reload behind the ear or | |
2347 | ;; something. Testcase "gcc" looked .01% slower and 4 bytes bigger; | |
2348 | ;; product code became .001% smaller but "looked better". The testcase | |
2349 | ;; "ipps" was just different at register allocation). | |
2350 | ;; | |
2351 | ;; Assumptions in the jump optimizer forces us to use IF_THEN_ELSE in this | |
2352 | ;; pattern with the default-label as the else, with the "if" being | |
2353 | ;; index-is-less-than the max number of cases plus one. The default-label | |
2354 | ;; is attached to the end of the case-table at time of output. | |
2355 | ||
2356 | (define_insn "*casesi_adds_w" | |
2357 | [(set (pc) | |
2358 | (if_then_else | |
2359 | (ltu (match_operand:SI 0 "register_operand" "r") | |
2360 | (match_operand:SI 1 "const_int_operand" "n")) | |
2361 | (plus:SI (sign_extend:SI | |
2362 | (mem:HI | |
2363 | (plus:SI (mult:SI (match_dup 0) (const_int 2)) | |
2364 | (pc)))) | |
2365 | (pc)) | |
2366 | (label_ref (match_operand 2 "" "")))) | |
2367 | (use (label_ref (match_operand 3 "" "")))] | |
2368 | ||
2369 | "operands[0] != frame_pointer_rtx" | |
2370 | ||
2371 | "adds.w [$pc+%0.w],$pc" | |
2372 | [(set_attr "cc" "clobber")]) | |
2373 | \f | |
2374 | ;; Multiply instructions. | |
2375 | ||
2376 | ;; Sometimes powers of 2 (which are normally canonicalized to a | |
2377 | ;; left-shift) appear here, as a result of address reloading. | |
2378 | ;; As a special, for values 3 and 5, we can match with an addi, so add those. | |
2379 | ;; | |
2380 | ;; FIXME: This may be unnecessary now. | |
2381 | ;; Explicitly named for convenience of having a gen_... function. | |
2382 | ||
2383 | (define_insn "addi_mul" | |
2384 | [(set (match_operand:SI 0 "register_operand" "=r") | |
2385 | (mult:SI | |
2386 | (match_operand:SI 1 "register_operand" "%0") | |
2387 | (match_operand:SI 2 "const_int_operand" "n")))] | |
2388 | "operands[0] != frame_pointer_rtx | |
2389 | && operands[1] != frame_pointer_rtx | |
2390 | && GET_CODE (operands[2]) == CONST_INT | |
2391 | && (INTVAL (operands[2]) == 2 | |
2392 | || INTVAL (operands[2]) == 4 || INTVAL (operands[2]) == 3 | |
2393 | || INTVAL (operands[2]) == 5)" | |
2394 | "* | |
2395 | { | |
2396 | if (INTVAL (operands[2]) == 2) | |
2397 | return \"lslq 1,%0\"; | |
2398 | else if (INTVAL (operands[2]) == 4) | |
2399 | return \"lslq 2,%0\"; | |
2400 | else if (INTVAL (operands[2]) == 3) | |
2401 | return \"addi %0.w,%0\"; | |
2402 | else if (INTVAL (operands[2]) == 5) | |
2403 | return \"addi %0.d,%0\"; | |
2404 | return \"BAD: adr_mulsi: %0=%1*%2\"; | |
2405 | }" | |
2406 | [(set_attr "slottable" "yes") | |
2407 | ;; No flags are changed if this insn is "addi", but it does not seem | |
2408 | ;; worth the trouble to distinguish that to the lslq cases. | |
2409 | (set_attr "cc" "clobber")]) | |
2410 | ||
2411 | ;; The addi insn as it is normally used. | |
2412 | ||
2413 | (define_insn "*addi" | |
2414 | [(set (match_operand:SI 0 "register_operand" "=r") | |
2415 | (plus:SI | |
2416 | (mult:SI (match_operand:SI 2 "register_operand" "r") | |
2417 | (match_operand:SI 3 "const_int_operand" "n")) | |
2418 | (match_operand:SI 1 "register_operand" "0")))] | |
2419 | "operands[0] != frame_pointer_rtx | |
2420 | && operands[1] != frame_pointer_rtx | |
2421 | && GET_CODE (operands[3]) == CONST_INT | |
2422 | && (INTVAL (operands[3]) == 1 | |
2423 | || INTVAL (operands[3]) == 2 || INTVAL (operands[3]) == 4)" | |
2424 | "addi %2%T3,%0" | |
2425 | [(set_attr "slottable" "yes") | |
2426 | (set_attr "cc" "none")]) | |
2427 | ||
2428 | ;; The mstep instruction. Probably not useful by itself; it's to | |
2429 | ;; non-linear wrt. the other insns. We used to expand to it, so at least | |
2430 | ;; it's correct. | |
2431 | ||
2432 | (define_insn "mstep_shift" | |
2433 | [(set (match_operand:SI 0 "register_operand" "=r") | |
2434 | (if_then_else:SI | |
2435 | (lt:SI (cc0) (const_int 0)) | |
2436 | (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "0") | |
2437 | (const_int 1)) | |
2438 | (match_operand:SI 2 "register_operand" "r")) | |
2439 | (ashift:SI (match_operand:SI 3 "register_operand" "0") | |
2440 | (const_int 1))))] | |
2441 | "" | |
2442 | "mstep %2,%0" | |
2443 | [(set_attr "slottable" "yes")]) | |
2444 | ||
2445 | ;; When illegitimate addresses are legitimized, sometimes gcc forgets | |
2446 | ;; to canonicalize the multiplications. | |
2447 | ;; | |
2448 | ;; FIXME: Check gcc > 2.7.2, remove and possibly fix in gcc. | |
2449 | ||
2450 | (define_insn "mstep_mul" | |
2451 | [(set (match_operand:SI 0 "register_operand" "=r") | |
2452 | (if_then_else:SI | |
2453 | (lt:SI (cc0) (const_int 0)) | |
2454 | (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0") | |
2455 | (const_int 2)) | |
2456 | (match_operand:SI 2 "register_operand" "r")) | |
2457 | (mult:SI (match_operand:SI 3 "register_operand" "0") | |
2458 | (const_int 2))))] | |
2459 | "operands[0] != frame_pointer_rtx | |
2460 | && operands[1] != frame_pointer_rtx | |
2461 | && operands[2] != frame_pointer_rtx | |
2462 | && operands[3] != frame_pointer_rtx" | |
2463 | "mstep %2,%0" | |
2464 | [(set_attr "slottable" "yes")]) | |
2465 | ||
2466 | (define_insn "umulhisi3" | |
2467 | [(set (match_operand:SI 0 "register_operand" "=r") | |
2468 | (mult:SI | |
2469 | (zero_extend:SI (match_operand:HI 1 "register_operand" "0")) | |
2470 | (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))] | |
2471 | "TARGET_HAS_MUL_INSNS" | |
2472 | "mulu.w %2,%0" | |
2473 | [(set_attr "slottable" "yes") | |
2474 | ;; Just N unusable here, but let's be safe. | |
2475 | (set_attr "cc" "clobber")]) | |
2476 | ||
2477 | (define_insn "umulqihi3" | |
2478 | [(set (match_operand:HI 0 "register_operand" "=r") | |
2479 | (mult:HI | |
2480 | (zero_extend:HI (match_operand:QI 1 "register_operand" "0")) | |
2481 | (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))] | |
2482 | "TARGET_HAS_MUL_INSNS" | |
2483 | "mulu.b %2,%0" | |
2484 | [(set_attr "slottable" "yes") | |
2485 | ;; Not exactly sure, but let's be safe. | |
2486 | (set_attr "cc" "clobber")]) | |
2487 | ||
2488 | ;; Note that gcc does not make use of such a thing as umulqisi3. It gets | |
2489 | ;; confused and will erroneously use it instead of umulhisi3, failing (at | |
2490 | ;; least) gcc.c-torture/execute/arith-rand.c at all optimization levels. | |
2491 | ;; Inspection of optab code shows that there must be only one widening | |
2492 | ;; multiplication per mode widened to. | |
2493 | ||
2494 | (define_insn "mulsi3" | |
2495 | [(set (match_operand:SI 0 "register_operand" "=r") | |
2496 | (mult:SI (match_operand:SI 1 "register_operand" "0") | |
2497 | (match_operand:SI 2 "register_operand" "r")))] | |
2498 | "TARGET_HAS_MUL_INSNS" | |
2499 | "muls.d %2,%0" | |
2500 | [(set_attr "slottable" "yes") | |
2501 | ;; Just N unusable here, but let's be safe. | |
2502 | (set_attr "cc" "clobber")]) | |
2503 | \f | |
2504 | ;; A few multiply variations. | |
2505 | ||
2506 | ;; This really extends to SImode, so cc should be considered clobbered. | |
2507 | ||
2508 | (define_insn "mulqihi3" | |
2509 | [(set (match_operand:HI 0 "register_operand" "=r") | |
2510 | (mult:HI | |
2511 | (sign_extend:HI (match_operand:QI 1 "register_operand" "0")) | |
2512 | (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))] | |
2513 | "TARGET_HAS_MUL_INSNS" | |
2514 | "muls.b %2,%0" | |
2515 | [(set_attr "slottable" "yes") | |
2516 | (set_attr "cc" "clobber")]) | |
2517 | ||
2518 | (define_insn "mulhisi3" | |
2519 | [(set (match_operand:SI 0 "register_operand" "=r") | |
2520 | (mult:SI | |
2521 | (sign_extend:SI (match_operand:HI 1 "register_operand" "0")) | |
2522 | (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))] | |
2523 | "TARGET_HAS_MUL_INSNS" | |
2524 | "muls.w %2,%0" | |
2525 | [(set_attr "slottable" "yes") | |
2526 | ;; Just N unusable here, but let's be safe. | |
2527 | (set_attr "cc" "clobber")]) | |
2528 | ||
2529 | ;; When needed, we can get the high 32 bits from the overflow | |
2530 | ;; register. We don't care to split and optimize these. | |
2531 | ;; | |
2532 | ;; Note that cc0 is still valid after the move-from-overflow-register | |
2533 | ;; insn; no special precaution need to be taken in cris_notice_update_cc. | |
2534 | ||
2535 | (define_insn "mulsidi3" | |
2536 | [(set (match_operand:DI 0 "register_operand" "=r") | |
2537 | (mult:DI | |
2538 | (sign_extend:DI (match_operand:SI 1 "register_operand" "0")) | |
2539 | (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))] | |
2540 | "TARGET_HAS_MUL_INSNS" | |
2541 | "muls.d %2,%M0\;move $mof,%H0") | |
2542 | ||
2543 | (define_insn "umulsidi3" | |
2544 | [(set (match_operand:DI 0 "register_operand" "=r") | |
2545 | (mult:DI | |
2546 | (zero_extend:DI (match_operand:SI 1 "register_operand" "0")) | |
2547 | (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))] | |
2548 | "TARGET_HAS_MUL_INSNS" | |
2549 | "mulu.d %2,%M0\;move $mof,%H0") | |
2550 | ||
2551 | ;; This pattern would probably not be needed if we add "mof" in its own | |
2552 | ;; register class (and open a can of worms about /not/ pairing it with a | |
2553 | ;; "normal" register). Having multiple register classes here, and | |
2554 | ;; applicable to the v10 variant only, seems worse than having these two | |
2555 | ;; patterns with multi-insn contents for now (may change; having a free | |
2556 | ;; call-clobbered register is worth some trouble). | |
2557 | ||
2558 | (define_insn "smulsi3_highpart" | |
2559 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m") | |
2560 | (truncate:SI | |
2561 | (lshiftrt:DI | |
2562 | (mult:DI | |
2563 | (sign_extend:DI (match_operand:SI 1 "register_operand" "%0,r,r")) | |
2564 | (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r,r"))) | |
2565 | (const_int 32)))) | |
2566 | (clobber (match_scratch:SI 3 "=X,1,1"))] | |
2567 | "TARGET_HAS_MUL_INSNS" | |
2568 | "muls.d %2,%1\;move $mof,%0" | |
2569 | [(set_attr "cc" "clobber")]) | |
2570 | ||
2571 | (define_insn "umulsi3_highpart" | |
2572 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m") | |
2573 | (truncate:SI | |
2574 | (lshiftrt:DI | |
2575 | (mult:DI | |
2576 | (zero_extend:DI (match_operand:SI 1 "register_operand" "%0,r,r")) | |
2577 | (zero_extend:DI (match_operand:SI 2 "register_operand" "r,r,r"))) | |
2578 | (const_int 32)))) | |
2579 | (clobber (match_scratch:SI 3 "=X,1,1"))] | |
2580 | "TARGET_HAS_MUL_INSNS" | |
2581 | "mulu.d %2,%1\;move $mof,%0" | |
2582 | [(set_attr "cc" "clobber")]) | |
2583 | \f | |
2584 | ;; Divide and modulus instructions. CRIS only has a step instruction. | |
2585 | ||
2586 | (define_insn "dstep_shift" | |
2587 | [(set (match_operand:SI 0 "register_operand" "=r") | |
2588 | (if_then_else:SI | |
2589 | (geu:SI (ashift:SI (match_operand:SI 1 "register_operand" "0") | |
2590 | (const_int 1)) | |
2591 | (match_operand:SI 2 "register_operand" "r")) | |
2592 | (minus:SI (ashift:SI (match_operand:SI 3 "register_operand" "0") | |
2593 | (const_int 1)) | |
2594 | (match_operand:SI 4 "register_operand" "2")) | |
2595 | (ashift:SI (match_operand:SI 5 "register_operand" "0") | |
2596 | (const_int 1))))] | |
2597 | "" | |
2598 | "dstep %2,%0" | |
2599 | [(set_attr "slottable" "yes")]) | |
2600 | ||
2601 | ;; Here's a variant with mult instead of ashift. | |
2602 | ;; | |
2603 | ;; FIXME: This should be investigated. Which one matches through combination? | |
2604 | ||
2605 | (define_insn "dstep_mul" | |
2606 | [(set (match_operand:SI 0 "register_operand" "=r") | |
2607 | (if_then_else:SI | |
2608 | (geu:SI (mult:SI (match_operand:SI 1 "register_operand" "0") | |
2609 | (const_int 2)) | |
2610 | (match_operand:SI 2 "register_operand" "r")) | |
2611 | (minus:SI (mult:SI (match_operand:SI 3 "register_operand" "0") | |
2612 | (const_int 2)) | |
2613 | (match_operand:SI 4 "register_operand" "2")) | |
2614 | (mult:SI (match_operand:SI 5 "register_operand" "0") | |
2615 | (const_int 2))))] | |
2616 | "operands[0] != frame_pointer_rtx | |
2617 | && operands[1] != frame_pointer_rtx | |
2618 | && operands[2] != frame_pointer_rtx | |
2619 | && operands[3] != frame_pointer_rtx" | |
2620 | "dstep %2,%0" | |
2621 | [(set_attr "slottable" "yes")]) | |
2622 | \f | |
2623 | ;; Logical operators. | |
2624 | ||
2625 | ;; Bitwise "and". | |
2626 | ||
2627 | ;; There is no use in defining "anddi3", because gcc can expand this by | |
2628 | ;; itself, and make reasonable code without interference. | |
2629 | ||
2630 | ;; If the first operand is memory or a register and is the same as the | |
2631 | ;; second operand, and the third operand is -256 or -65536, we can use | |
2632 | ;; CLEAR instead. Or, if the first operand is a register, and the third | |
2633 | ;; operand is 255 or 65535, we can zero_extend. | |
f5143c46 | 2634 | ;; GCC isn't smart enough to recognize these cases (yet), and they seem |
0b85d816 HPN |
2635 | ;; to be common enough to be worthwhile. |
2636 | ;; FIXME: This should be made obsolete. | |
2637 | ||
2638 | (define_expand "andsi3" | |
2639 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
2640 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
2641 | (match_operand:SI 2 "general_operand" "")))] | |
2642 | "" | |
2643 | " | |
2644 | { | |
2645 | if (! (GET_CODE (operands[2]) == CONST_INT | |
2646 | && (((INTVAL (operands[2]) == -256 | |
2647 | || INTVAL (operands[2]) == -65536) | |
2648 | && rtx_equal_p (operands[1], operands[0])) | |
2649 | || ((INTVAL (operands[2]) == 255 | |
2650 | || INTVAL (operands[2]) == 65535) | |
2651 | && REG_P (operands[0]))))) | |
2652 | { | |
2653 | /* Make intermediate steps if operand0 is not a register or | |
2654 | operand1 is not a register, and hope that the reload pass will | |
2655 | make something useful out of it. Note that the operands are | |
2656 | *not* canonicalized. For the moment, I chicken out on this, | |
2657 | because all or most ports do not describe 'and' with | |
2658 | canonicalized operands, and I seem to remember magic in reload, | |
2659 | checking that operand1 has constraint '%0', in which case | |
2660 | operand0 and operand1 must have similar predicates. | |
2661 | FIXME: Investigate. */ | |
2662 | rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode); | |
2663 | rtx reg1 = operands[1]; | |
2664 | ||
2665 | if (! REG_P (reg1)) | |
2666 | { | |
2667 | emit_move_insn (reg0, reg1); | |
2668 | reg1 = reg0; | |
2669 | } | |
2670 | ||
2671 | emit_insn (gen_rtx_SET (SImode, reg0, | |
2672 | gen_rtx_AND (SImode, reg1, operands[2]))); | |
2673 | ||
2674 | /* Make sure we get the right *final* destination. */ | |
2675 | if (! REG_P (operands[0])) | |
2676 | emit_move_insn (operands[0], reg0); | |
2677 | ||
2678 | DONE; | |
2679 | } | |
2680 | }") | |
2681 | ||
2682 | ;; Some special cases of andsi3. | |
2683 | ||
2684 | (define_insn "*andsi_movu" | |
2685 | [(set (match_operand:SI 0 "register_operand" "=r,r,r") | |
2686 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%r,Q>,m") | |
2687 | (match_operand:SI 2 "const_int_operand" "n,n,n")))] | |
2688 | "INTVAL (operands[2]) == 255 || INTVAL (operands[2]) == 65535" | |
2689 | "movu.%z2 %1,%0" | |
2690 | [(set_attr "slottable" "yes,yes,no")]) | |
2691 | ||
2692 | (define_insn "*andsi_clear" | |
2693 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,Q>,Q>,m,m") | |
2694 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0") | |
2695 | (match_operand:SI 2 "const_int_operand" "P,n,P,n,P,n")))] | |
2696 | "INTVAL (operands[2]) == -65536 || INTVAL (operands[2]) == -256" | |
2697 | "@ | |
2698 | cLear.b %0 | |
2699 | cLear.w %0 | |
2700 | cLear.b %0 | |
2701 | cLear.w %0 | |
2702 | cLear.b %0 | |
2703 | cLear.w %0" | |
2704 | [(set_attr "slottable" "yes,yes,yes,yes,no,no") | |
2705 | (set_attr "cc" "none")]) | |
2706 | ||
2707 | ;; This is a catch-all pattern, taking care of everything that was not | |
2708 | ;; matched in the insns above. | |
2709 | ;; | |
2710 | ;; Sidenote: the tightening from "nonimmediate_operand" to | |
2711 | ;; "register_operand" for operand 1 actually increased the register | |
2712 | ;; pressure (worse code). That will hopefully change with an | |
2713 | ;; improved reload pass. | |
2714 | ||
2715 | (define_insn "*expanded_andsi" | |
2716 | [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") | |
2717 | (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,r") | |
2718 | (match_operand:SI 2 "general_operand" "I,r,Q>,g,!To")))] | |
2719 | "" | |
2720 | "@ | |
2721 | andq %2,%0 | |
2722 | and.d %2,%0 | |
2723 | and.d %2,%0 | |
2724 | and.d %2,%0 | |
2725 | and.d %2,%1,%0" | |
2726 | [(set_attr "slottable" "yes,yes,yes,no,no")]) | |
2727 | \f | |
2728 | ;; For both QI and HI we may use the quick patterns. This results in | |
2729 | ;; useless condition codes, but that is used rarely enough for it to | |
2730 | ;; normally be a win (could check ahead for use of cc0, but seems to be | |
2731 | ;; more pain than win). | |
2732 | ||
2733 | ;; FIXME: See note for andsi3 | |
2734 | ||
2735 | (define_expand "andhi3" | |
2736 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
2737 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
2738 | (match_operand:HI 2 "general_operand" "")))] | |
2739 | "" | |
2740 | " | |
2741 | { | |
2742 | if (! (GET_CODE (operands[2]) == CONST_INT | |
2743 | && (((INTVAL (operands[2]) == -256 | |
2744 | || INTVAL (operands[2]) == 65280) | |
2745 | && rtx_equal_p (operands[1], operands[0])) | |
2746 | || (INTVAL (operands[2]) == 255 | |
2747 | && REG_P (operands[0]))))) | |
2748 | { | |
2749 | /* See comment for andsi3. */ | |
2750 | rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (HImode); | |
2751 | rtx reg1 = operands[1]; | |
2752 | ||
2753 | if (! REG_P (reg1)) | |
2754 | { | |
2755 | emit_move_insn (reg0, reg1); | |
2756 | reg1 = reg0; | |
2757 | } | |
2758 | ||
2759 | emit_insn (gen_rtx_SET (HImode, reg0, | |
2760 | gen_rtx_AND (HImode, reg1, operands[2]))); | |
2761 | ||
2762 | /* Make sure we get the right destination. */ | |
2763 | if (! REG_P (operands[0])) | |
2764 | emit_move_insn (operands[0], reg0); | |
2765 | ||
2766 | DONE; | |
2767 | } | |
2768 | }") | |
2769 | ||
2770 | ;; Some fast andhi3 special cases. | |
2771 | ||
2772 | (define_insn "*andhi_movu" | |
2773 | [(set (match_operand:HI 0 "register_operand" "=r,r,r") | |
2774 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "r,Q>,m") | |
2775 | (const_int 255)))] | |
2776 | "" | |
2777 | "mOvu.b %1,%0" | |
2778 | [(set_attr "slottable" "yes,yes,no")]) | |
2779 | ||
2780 | (define_insn "*andhi_clear_signed" | |
2781 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,Q>,m") | |
2782 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "0,0,0") | |
2783 | (const_int -256)))] | |
2784 | "" | |
2785 | "cLear.b %0" | |
2786 | [(set_attr "slottable" "yes,yes,no") | |
2787 | (set_attr "cc" "none")]) | |
2788 | ||
2789 | ;; FIXME: Either this or the pattern above should be redundant. | |
2790 | (define_insn "*andhi_clear_unsigned" | |
2791 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,Q>,m") | |
2792 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "0,0,0") | |
2793 | (const_int 65280)))] | |
2794 | "" | |
2795 | "cLear.b %0" | |
2796 | [(set_attr "slottable" "yes,yes,no") | |
2797 | (set_attr "cc" "none")]) | |
2798 | ||
2799 | ;; Catch-all andhi3 pattern. | |
2800 | ||
2801 | (define_insn "*expanded_andhi" | |
2802 | [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r") | |
2803 | (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0,r") | |
2804 | (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))] | |
2805 | ||
2806 | ;; Sidenote: the tightening from "general_operand" to | |
2807 | ;; "register_operand" for operand 1 actually increased the register | |
2808 | ;; pressure (worse code). That will hopefully change with an | |
2809 | ;; improved reload pass. | |
2810 | ||
2811 | "" | |
2812 | "@ | |
2813 | andq %2,%0 | |
2814 | and.w %2,%0 | |
2815 | and.w %2,%0 | |
2816 | and.w %2,%0 | |
2817 | anDq %b2,%0 | |
2818 | and.w %2,%0 | |
2819 | and.w %2,%1,%0" | |
2820 | [(set_attr "slottable" "yes,yes,yes,no,yes,no,no") | |
2821 | (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")]) | |
2822 | ||
2823 | ;; A strict_low_part pattern. | |
2824 | ||
2825 | (define_insn "*andhi_lowpart" | |
2826 | [(set (strict_low_part | |
2827 | (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")) | |
2828 | (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,r") | |
2829 | (match_operand:HI 2 "general_operand" "r,Q>,L,O,g,!To")))] | |
2830 | "" | |
2831 | "@ | |
2832 | and.w %2,%0 | |
2833 | and.w %2,%0 | |
2834 | and.w %2,%0 | |
2835 | anDq %b2,%0 | |
2836 | and.w %2,%0 | |
2837 | and.w %2,%1,%0" | |
2838 | [(set_attr "slottable" "yes,yes,no,yes,no,no") | |
2839 | (set_attr "cc" "normal,normal,normal,clobber,normal,normal")]) | |
2840 | \f | |
2841 | (define_insn "andqi3" | |
2842 | [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r") | |
2843 | (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,r") | |
2844 | (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))] | |
2845 | "" | |
2846 | "@ | |
2847 | andq %2,%0 | |
2848 | and.b %2,%0 | |
2849 | and.b %2,%0 | |
2850 | andQ %b2,%0 | |
2851 | and.b %2,%0 | |
2852 | and.b %2,%1,%0" | |
2853 | [(set_attr "slottable" "yes,yes,yes,yes,no,no") | |
2854 | (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")]) | |
2855 | ||
2856 | (define_insn "*andqi_lowpart" | |
2857 | [(set (strict_low_part | |
2858 | (match_operand:QI 0 "register_operand" "=r,r,r,r,r")) | |
2859 | (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,r") | |
2860 | (match_operand:QI 2 "general_operand" "r,Q>,O,g,!To")))] | |
2861 | "" | |
2862 | "@ | |
2863 | and.b %2,%0 | |
2864 | and.b %2,%0 | |
2865 | andQ %b2,%0 | |
2866 | and.b %2,%0 | |
2867 | and.b %2,%1,%0" | |
2868 | [(set_attr "slottable" "yes,yes,yes,no,no") | |
2869 | (set_attr "cc" "normal,normal,clobber,normal,normal")]) | |
2870 | \f | |
2871 | ;; Bitwise or. | |
2872 | ||
2873 | ;; Same comment as anddi3 applies here - no need for such a pattern. | |
2874 | ||
2875 | ;; It seems there's no need to jump through hoops to get good code such as | |
2876 | ;; with andsi3. | |
2877 | ||
2878 | (define_insn "iorsi3" | |
2879 | [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r") | |
2880 | (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,r") | |
2881 | (match_operand:SI 2 "general_operand" "I,r,Q>,n,g,!To")))] | |
2882 | "" | |
2883 | "@ | |
2884 | orq %2,%0 | |
2885 | or.d %2,%0 | |
2886 | or.d %2,%0 | |
2887 | oR.%s2 %2,%0 | |
2888 | or.d %2,%0 | |
2889 | or.d %2,%1,%0" | |
2890 | [(set_attr "slottable" "yes,yes,yes,no,no,no") | |
2891 | (set_attr "cc" "normal,normal,normal,clobber,normal,normal")]) | |
2892 | ||
2893 | (define_insn "iorhi3" | |
2894 | [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r") | |
2895 | (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0,r") | |
2896 | (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))] | |
2897 | "" | |
2898 | "@ | |
2899 | orq %2,%0 | |
2900 | or.w %2,%0 | |
2901 | or.w %2,%0 | |
2902 | or.w %2,%0 | |
2903 | oRq %b2,%0 | |
2904 | or.w %2,%0 | |
2905 | or.w %2,%1,%0" | |
2906 | [(set_attr "slottable" "yes,yes,yes,no,yes,no,no") | |
2907 | (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")]) | |
2908 | ||
2909 | (define_insn "iorqi3" | |
2910 | [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r") | |
2911 | (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,r") | |
2912 | (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))] | |
2913 | "" | |
2914 | "@ | |
2915 | orq %2,%0 | |
2916 | or.b %2,%0 | |
2917 | or.b %2,%0 | |
2918 | orQ %b2,%0 | |
2919 | or.b %2,%0 | |
2920 | or.b %2,%1,%0" | |
2921 | [(set_attr "slottable" "yes,yes,yes,yes,no,no") | |
2922 | (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")]) | |
2923 | \f | |
2924 | ;; Exclusive-or | |
2925 | ||
2926 | ;; See comment about "anddi3" for xordi3 - no need for such a pattern. | |
2927 | ||
2928 | (define_insn "xorsi3" | |
2929 | [(set (match_operand:SI 0 "register_operand" "=r") | |
2930 | (xor:SI (match_operand:SI 1 "register_operand" "%0") | |
2931 | (match_operand:SI 2 "register_operand" "r")))] | |
2932 | "" | |
2933 | "xor %2,%0" | |
2934 | [(set_attr "slottable" "yes")]) | |
2935 | ||
2936 | (define_insn "xorhi3" | |
2937 | [(set (match_operand:HI 0 "register_operand" "=r") | |
2938 | (xor:HI (match_operand:HI 1 "register_operand" "%0") | |
2939 | (match_operand:HI 2 "register_operand" "r")))] | |
2940 | "" | |
2941 | "xor %2,%0" | |
2942 | [(set_attr "slottable" "yes") | |
2943 | (set_attr "cc" "clobber")]) | |
2944 | ||
2945 | (define_insn "xorqi3" | |
2946 | [(set (match_operand:QI 0 "register_operand" "=r") | |
2947 | (xor:QI (match_operand:QI 1 "register_operand" "%0") | |
2948 | (match_operand:QI 2 "register_operand" "r")))] | |
2949 | "" | |
2950 | "xor %2,%0" | |
2951 | [(set_attr "slottable" "yes") | |
2952 | (set_attr "cc" "clobber")]) | |
2953 | \f | |
2954 | ;; Negation insns. | |
2955 | ||
2956 | ;; Questionable use, here mostly as a (slightly usable) define_expand | |
2957 | ;; example. | |
2958 | ||
2959 | (define_expand "negsf2" | |
2960 | [(set (match_dup 2) | |
2961 | (match_dup 3)) | |
2962 | (parallel [(set (match_operand:SF 0 "register_operand" "=r") | |
2963 | (neg:SF (match_operand:SF 1 | |
2964 | "register_operand" "0"))) | |
2965 | (use (match_dup 2))])] | |
2966 | "" | |
2967 | " | |
2968 | { | |
2969 | operands[2] = gen_reg_rtx (SImode); | |
2970 | operands[3] = GEN_INT (1 << 31); | |
2971 | }") | |
2972 | ||
2973 | (define_insn "*expanded_negsf2" | |
2974 | [(set (match_operand:SF 0 "register_operand" "=r") | |
2975 | (neg:SF (match_operand:SF 1 "register_operand" "0"))) | |
2976 | (use (match_operand:SI 2 "register_operand" "r"))] | |
2977 | "" | |
2978 | "xor %2,%0" | |
2979 | [(set_attr "slottable" "yes")]) | |
2980 | ||
2981 | ;; No "negdi2" although we could make one up that may be faster than | |
2982 | ;; the one in libgcc. | |
2983 | ||
2984 | (define_insn "negsi2" | |
2985 | [(set (match_operand:SI 0 "register_operand" "=r") | |
2986 | (neg:SI (match_operand:SI 1 "register_operand" "r")))] | |
2987 | "" | |
2988 | "neg.d %1,%0" | |
2989 | [(set_attr "slottable" "yes")]) | |
2990 | ||
2991 | (define_insn "neghi2" | |
2992 | [(set (match_operand:HI 0 "register_operand" "=r") | |
2993 | (neg:HI (match_operand:HI 1 "register_operand" "r")))] | |
2994 | "" | |
2995 | "neg.w %1,%0" | |
2996 | [(set_attr "slottable" "yes")]) | |
2997 | ||
2998 | (define_insn "negqi2" | |
2999 | [(set (match_operand:QI 0 "register_operand" "=r") | |
3000 | (neg:QI (match_operand:QI 1 "register_operand" "r")))] | |
3001 | "" | |
3002 | "neg.b %1,%0" | |
3003 | [(set_attr "slottable" "yes")]) | |
3004 | \f | |
3005 | ;; One-complements. | |
3006 | ||
3007 | ;; See comment on anddi3 - no need for a DImode pattern. | |
3008 | ||
3009 | (define_insn "one_cmplsi2" | |
3010 | [(set (match_operand:SI 0 "register_operand" "=r") | |
3011 | (not:SI (match_operand:SI 1 "register_operand" "0")))] | |
3012 | "" | |
3013 | "not %0" | |
3014 | [(set_attr "slottable" "yes")]) | |
3015 | ||
3016 | (define_insn "one_cmplhi2" | |
3017 | [(set (match_operand:HI 0 "register_operand" "=r") | |
3018 | (not:HI (match_operand:HI 1 "register_operand" "0")))] | |
3019 | "" | |
3020 | "not %0" | |
3021 | [(set_attr "slottable" "yes") | |
3022 | (set_attr "cc" "clobber")]) | |
3023 | ||
3024 | (define_insn "one_cmplqi2" | |
3025 | [(set (match_operand:QI 0 "register_operand" "=r") | |
3026 | (not:QI (match_operand:QI 1 "register_operand" "0")))] | |
3027 | "" | |
3028 | "not %0" | |
3029 | [(set_attr "slottable" "yes") | |
3030 | (set_attr "cc" "clobber")]) | |
3031 | \f | |
3032 | ;; Arithmetic shift right. | |
3033 | ||
3034 | (define_insn "ashrsi3" | |
3035 | [(set (match_operand:SI 0 "register_operand" "=r") | |
3036 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
3037 | (match_operand:SI 2 "nonmemory_operand" "Kr")))] | |
3038 | "" | |
3039 | "* | |
3040 | { | |
3041 | if (REG_S_P (operands[2])) | |
3042 | return \"asr.d %2,%0\"; | |
3043 | ||
3044 | return \"asrq %2,%0\"; | |
3045 | }" | |
3046 | [(set_attr "slottable" "yes")]) | |
3047 | ||
3048 | ;; Since gcc gets lost, and forgets to zero-extend the source (or mask | |
3049 | ;; the destination) when it changes shifts of lower modes into SImode, | |
3050 | ;; it is better to make these expands an anonymous patterns instead of | |
3051 | ;; the more correct define_insns. This occurs when gcc thinks that is | |
3052 | ;; is better to widen to SImode and use immediate shift count. | |
3053 | ||
3054 | ;; FIXME: Is this legacy or still true for gcc >= 2.7.2? | |
3055 | ||
3056 | (define_expand "ashrhi3" | |
3057 | [(set (match_dup 3) | |
3058 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm"))) | |
3059 | (set (match_dup 4) | |
3060 | (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rm"))) | |
3061 | (set (match_dup 5) (ashiftrt:SI (match_dup 3) (match_dup 4))) | |
3062 | (set (match_operand:HI 0 "general_operand" "=g") | |
3063 | (subreg:HI (match_dup 5) 0))] | |
3064 | "" | |
3065 | " | |
3066 | { | |
3067 | int i; | |
3068 | ||
3069 | for (i = 3; i < 6; i++) | |
3070 | operands[i] = gen_reg_rtx (SImode); | |
3071 | }") | |
3072 | ||
3073 | (define_insn "*expanded_ashrhi" | |
3074 | [(set (match_operand:HI 0 "register_operand" "=r") | |
3075 | (ashiftrt:HI (match_operand:HI 1 "register_operand" "0") | |
3076 | (match_operand:HI 2 "register_operand" "r")))] | |
3077 | "" | |
3078 | "asr.w %2,%0" | |
3079 | [(set_attr "slottable" "yes")]) | |
3080 | ||
3081 | (define_insn "*ashrhi_lowpart" | |
3082 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r")) | |
3083 | (ashiftrt:HI (match_dup 0) | |
3084 | (match_operand:HI 1 "register_operand" "r")))] | |
3085 | "" | |
3086 | "asr.w %1,%0" | |
3087 | [(set_attr "slottable" "yes")]) | |
3088 | ||
3089 | ;; Same comment goes as for "ashrhi3". | |
3090 | ||
3091 | (define_expand "ashrqi3" | |
3092 | [(set (match_dup 3) | |
3093 | (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g"))) | |
3094 | (set (match_dup 4) | |
3095 | (zero_extend:SI (match_operand:QI 2 "nonimmediate_operand" "g"))) | |
3096 | (set (match_dup 5) (ashiftrt:SI (match_dup 3) (match_dup 4))) | |
3097 | (set (match_operand:QI 0 "general_operand" "=g") | |
3098 | (subreg:QI (match_dup 5) 0))] | |
3099 | "" | |
3100 | " | |
3101 | { | |
3102 | int i; | |
3103 | ||
3104 | for (i = 3; i < 6; i++) | |
3105 | operands[i] = gen_reg_rtx (SImode); | |
3106 | }") | |
3107 | ||
3108 | (define_insn "*expanded_ashrqi" | |
3109 | [(set (match_operand:QI 0 "register_operand" "=r") | |
3110 | (ashiftrt:QI (match_operand:QI 1 "register_operand" "0") | |
3111 | (match_operand:QI 2 "register_operand" "r")))] | |
3112 | "" | |
3113 | "asr.b %2,%0" | |
3114 | [(set_attr "slottable" "yes")]) | |
3115 | ||
3116 | ;; A strict_low_part matcher. | |
3117 | ||
3118 | (define_insn "*ashrqi_lowpart" | |
3119 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r")) | |
3120 | (ashiftrt:QI (match_dup 0) | |
3121 | (match_operand:QI 1 "register_operand" "r")))] | |
3122 | "" | |
3123 | "asr.b %1,%0" | |
3124 | [(set_attr "slottable" "yes")]) | |
3125 | \f | |
3126 | ;; Logical shift right. | |
3127 | ||
3128 | (define_insn "lshrsi3" | |
3129 | [(set (match_operand:SI 0 "register_operand" "=r") | |
3130 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
3131 | (match_operand:SI 2 "nonmemory_operand" "Kr")))] | |
3132 | "" | |
3133 | "* | |
3134 | { | |
3135 | if (REG_S_P (operands[2])) | |
3136 | return \"lsr.d %2,%0\"; | |
3137 | ||
3138 | return \"lsrq %2,%0\"; | |
3139 | }" | |
3140 | [(set_attr "slottable" "yes")]) | |
3141 | ||
3142 | ;; Same comments as for ashrhi3. | |
3143 | ||
3144 | (define_expand "lshrhi3" | |
3145 | [(set (match_dup 3) | |
3146 | (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g"))) | |
3147 | (set (match_dup 4) | |
3148 | (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "g"))) | |
3149 | (set (match_dup 5) (lshiftrt:SI (match_dup 3) (match_dup 4))) | |
3150 | (set (match_operand:HI 0 "general_operand" "=g") | |
3151 | (subreg:HI (match_dup 5) 0))] | |
3152 | "" | |
3153 | " | |
3154 | { | |
3155 | int i; | |
3156 | ||
3157 | for (i = 3; i < 6; i++) | |
3158 | operands[i] = gen_reg_rtx (SImode); | |
3159 | }") | |
3160 | ||
3161 | (define_insn "*expanded_lshrhi" | |
3162 | [(set (match_operand:HI 0 "register_operand" "=r") | |
3163 | (lshiftrt:HI (match_operand:HI 1 "register_operand" "0") | |
3164 | (match_operand:HI 2 "register_operand" "r")))] | |
3165 | "" | |
3166 | "lsr.w %2,%0" | |
3167 | [(set_attr "slottable" "yes")]) | |
3168 | ||
3169 | ;; A strict_low_part matcher. | |
3170 | ||
3171 | (define_insn "*lshrhi_lowpart" | |
3172 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r")) | |
3173 | (lshiftrt:HI (match_dup 0) | |
3174 | (match_operand:HI 1 "register_operand" "r")))] | |
3175 | "" | |
3176 | "lsr.w %1,%0" | |
3177 | [(set_attr "slottable" "yes")]) | |
3178 | ||
3179 | ;; Same comments as for ashrhi3. | |
3180 | ||
3181 | (define_expand "lshrqi3" | |
3182 | [(set (match_dup 3) | |
3183 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g"))) | |
3184 | (set (match_dup 4) | |
3185 | (zero_extend:SI (match_operand:QI 2 "nonimmediate_operand" "g"))) | |
3186 | (set (match_dup 5) (lshiftrt:SI (match_dup 3) (match_dup 4))) | |
3187 | (set (match_operand:QI 0 "general_operand" "=g") | |
3188 | (subreg:QI (match_dup 5) 0))] | |
3189 | "" | |
3190 | " | |
3191 | { | |
3192 | int i; | |
3193 | ||
3194 | for (i = 3; i < 6; i++) | |
3195 | operands[i] = gen_reg_rtx (SImode); | |
3196 | }") | |
3197 | ||
3198 | (define_insn "*expanded_lshrqi" | |
3199 | [(set (match_operand:QI 0 "register_operand" "=r") | |
3200 | (lshiftrt:QI (match_operand:QI 1 "register_operand" "0") | |
3201 | (match_operand:QI 2 "register_operand" "r")))] | |
3202 | "" | |
3203 | "lsr.b %2,%0" | |
3204 | [(set_attr "slottable" "yes")]) | |
3205 | ||
3206 | ;; A strict_low_part matcher. | |
3207 | ||
3208 | (define_insn "*lshrqi_lowpart" | |
3209 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r")) | |
3210 | (lshiftrt:QI (match_dup 0) | |
3211 | (match_operand:QI 1 "register_operand" "r")))] | |
3212 | "" | |
3213 | "lsr.b %1,%0" | |
3214 | [(set_attr "slottable" "yes")]) | |
3215 | \f | |
3216 | ;; Arithmetic/logical shift left. | |
3217 | ||
3218 | (define_insn "ashlsi3" | |
3219 | [(set (match_operand:SI 0 "register_operand" "=r") | |
3220 | (ashift:SI (match_operand:SI 1 "register_operand" "0") | |
3221 | (match_operand:SI 2 "nonmemory_operand" "Kr")))] | |
3222 | "" | |
3223 | "* | |
3224 | { | |
3225 | if (REG_S_P (operands[2])) | |
3226 | return \"lsl.d %2,%0\"; | |
3227 | ||
3228 | return \"lslq %2,%0\"; | |
3229 | }" | |
3230 | [(set_attr "slottable" "yes")]) | |
3231 | ||
3232 | ;; For narrower modes than SI, we can use lslq although it makes cc | |
3233 | ;; unusable. The win is that we do not have to reload the shift-count | |
3234 | ;; into a register. | |
3235 | ||
3236 | (define_insn "ashlhi3" | |
3237 | [(set (match_operand:HI 0 "register_operand" "=r,r") | |
3238 | (ashift:HI (match_operand:HI 1 "register_operand" "0,0") | |
3239 | (match_operand:HI 2 "nonmemory_operand" "r,K")))] | |
3240 | "" | |
3241 | "* | |
3242 | { | |
3243 | return | |
3244 | (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 15) | |
3245 | ? \"moveq 0,%0\" | |
3246 | : (CONSTANT_P (operands[2]) | |
3247 | ? \"lslq %2,%0\" : \"lsl.w %2,%0\"); | |
3248 | }" | |
3249 | [(set_attr "slottable" "yes") | |
3250 | (set_attr "cc" "normal,clobber")]) | |
3251 | ||
3252 | ;; A strict_low_part matcher. | |
3253 | ||
3254 | (define_insn "*ashlhi_lowpart" | |
3255 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r")) | |
3256 | (ashift:HI (match_dup 0) | |
3257 | (match_operand:HI 1 "register_operand" "r")))] | |
3258 | "" | |
3259 | "lsl.w %1,%0" | |
3260 | [(set_attr "slottable" "yes")]) | |
3261 | ||
3262 | (define_insn "ashlqi3" | |
3263 | [(set (match_operand:QI 0 "register_operand" "=r,r") | |
3264 | (ashift:QI (match_operand:QI 1 "register_operand" "0,0") | |
3265 | (match_operand:QI 2 "nonmemory_operand" "r,K")))] | |
3266 | "" | |
3267 | "* | |
3268 | { | |
3269 | return | |
3270 | (GET_CODE (operands[2]) == CONST_INT | |
3271 | && INTVAL (operands[2]) > 7) | |
3272 | ? \"moveq 0,%0\" | |
3273 | : (CONSTANT_P (operands[2]) | |
3274 | ? \"lslq %2,%0\" : \"lsl.b %2,%0\"); | |
3275 | }" | |
3276 | [(set_attr "slottable" "yes") | |
3277 | (set_attr "cc" "normal,clobber")]) | |
3278 | ||
3279 | ;; A strict_low_part matcher. | |
3280 | ||
3281 | (define_insn "*ashlqi_lowpart" | |
3282 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r")) | |
3283 | (ashift:QI (match_dup 0) | |
3284 | (match_operand:QI 1 "register_operand" "r")))] | |
3285 | "" | |
3286 | "lsl.b %1,%0" | |
3287 | [(set_attr "slottable" "yes")]) | |
3288 | \f | |
3289 | ;; Various strange insns that gcc likes. | |
3290 | ||
3291 | ;; Fortunately, it is simple to construct an abssf (although it may not | |
3292 | ;; be very much used in practice). | |
3293 | ||
3294 | (define_insn "abssf2" | |
3295 | [(set (match_operand:SF 0 "register_operand" "=r") | |
3296 | (abs:SF (match_operand:SF 1 "register_operand" "0")))] | |
3297 | "" | |
3298 | "lslq 1,%0\;lsrq 1,%0") | |
3299 | ||
3300 | (define_insn "abssi2" | |
3301 | [(set (match_operand:SI 0 "register_operand" "=r") | |
3302 | (abs:SI (match_operand:SI 1 "register_operand" "r")))] | |
3303 | "" | |
3304 | "abs %1,%0" | |
3305 | [(set_attr "slottable" "yes")]) | |
3306 | ||
3307 | ;; FIXME: GCC should be able to do these expansions itself. | |
3308 | ||
3309 | (define_expand "abshi2" | |
3310 | [(set (match_dup 2) | |
3311 | (sign_extend:SI (match_operand:HI 1 "general_operand" "g"))) | |
3312 | (set (match_dup 3) (abs:SI (match_dup 2))) | |
3313 | (set (match_operand:HI 0 "register_operand" "=r") | |
3314 | (subreg:HI (match_dup 3) 0))] | |
3315 | "" | |
3316 | "operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);") | |
3317 | ||
3318 | (define_expand "absqi2" | |
3319 | [(set (match_dup 2) | |
3320 | (sign_extend:SI (match_operand:QI 1 "general_operand" "g"))) | |
3321 | (set (match_dup 3) (abs:SI (match_dup 2))) | |
3322 | (set (match_operand:QI 0 "register_operand" "=r") | |
3323 | (subreg:QI (match_dup 3) 0))] | |
3324 | "" | |
3325 | "operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);") | |
3326 | \f | |
3327 | ;; Bound-insn. Defined to be the same as an unsigned minimum, which is an | |
3328 | ;; operation supported by gcc. Used in casesi, but used now and then in | |
3329 | ;; normal code too. | |
3330 | ||
3331 | (define_insn "uminsi3" | |
3332 | [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") | |
3333 | (umin:SI (match_operand:SI 1 "register_operand" "%0,0,0,r") | |
3334 | (match_operand:SI 2 "general_operand" "r,Q>,g,!STo")))] | |
3335 | "" | |
3336 | "* | |
3337 | { | |
3338 | if (GET_CODE (operands[2]) == CONST_INT) | |
3339 | { | |
3340 | if (INTVAL (operands[2]) < 256) | |
3341 | return \"bound.b %2,%0\"; | |
3342 | ||
3343 | if (INTVAL (operands[2]) < 65536) | |
3344 | return \"bound.w %2,%0\"; | |
3345 | } | |
3346 | else if (which_alternative == 3) | |
3347 | return \"bound.d %2,%1,%0\"; | |
3348 | ||
3349 | return \"bound.d %2,%0\"; | |
3350 | }" | |
3351 | [(set_attr "slottable" "yes,yes,no,no")]) | |
3352 | \f | |
3353 | ;; Jump and branch insns. | |
3354 | ||
3355 | (define_insn "jump" | |
3356 | [(set (pc) | |
3357 | (label_ref (match_operand 0 "" "")))] | |
3358 | "" | |
3359 | "ba %l0%#" | |
3360 | [(set_attr "slottable" "has_slot")]) | |
3361 | ||
3362 | ;; Testcase gcc.c-torture/compile/991213-3.c fails if we allow a constant | |
3363 | ;; here, since the insn is not recognized as an indirect jump by | |
3364 | ;; jmp_uses_reg_or_mem used by computed_jump_p. Perhaps it is a kludge to | |
3365 | ;; change from general_operand to nonimmediate_operand (at least the docs | |
3366 | ;; should be changed), but then again the pattern is called indirect_jump. | |
3367 | (define_insn "indirect_jump" | |
3368 | [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))] | |
3369 | "" | |
3370 | "jump %0") | |
3371 | ||
3372 | ;; Return insn. Used whenever the epilogue is very simple; if it is only | |
3373 | ;; a single ret or jump [sp+] or a contiguous sequence of movem:able saved | |
3374 | ;; registers. No allocated stack space is allowed. | |
3375 | ;; Note that for this pattern, although named, it is ok to check the | |
3376 | ;; context of the insn in the test, not only compiler switches. | |
3377 | ||
3378 | (define_insn "return" | |
3379 | [(return)] | |
3380 | "cris_simple_epilogue ()" | |
3381 | "* | |
3382 | { | |
3383 | int i; | |
3384 | ||
3385 | /* Just needs to hold a 'movem [sp+],rN'. */ | |
3386 | char rd[sizeof (\"movem [$sp+],$r99\")]; | |
3387 | ||
c134da6b HPN |
3388 | /* Try to avoid reorg.c surprises; avoid emitting invalid code, prefer |
3389 | crashing. This test would have avoided invalid code for target/7042. */ | |
3390 | if (current_function_epilogue_delay_list != NULL) | |
3391 | abort (); | |
3392 | ||
0b85d816 HPN |
3393 | *rd = 0; |
3394 | ||
3395 | /* Start from the last call-saved register. We know that we have a | |
3396 | simple epilogue, so we just have to find the last register in the | |
3397 | movem sequence. */ | |
3398 | for (i = 8; i >= 0; i--) | |
3399 | if (regs_ever_live[i] | |
3400 | || (i == PIC_OFFSET_TABLE_REGNUM | |
3401 | && current_function_uses_pic_offset_table)) | |
3402 | break; | |
3403 | ||
3404 | if (i >= 0) | |
3405 | sprintf (rd, \"movem [$sp+],$%s\", reg_names [i]); | |
3406 | ||
3407 | if (regs_ever_live[CRIS_SRP_REGNUM]) | |
3408 | { | |
3409 | if (*rd) | |
3410 | output_asm_insn (rd, operands); | |
3411 | return \"jump [$sp+]\"; | |
3412 | } | |
3413 | ||
3414 | if (*rd) | |
3415 | { | |
3416 | output_asm_insn (\"reT\", operands); | |
3417 | output_asm_insn (rd, operands); | |
3418 | return \"\"; | |
3419 | } | |
3420 | ||
3421 | return \"ret%#\"; | |
3422 | }" | |
3423 | [(set (attr "slottable") | |
3424 | (if_then_else | |
3425 | (ne (symbol_ref "regs_ever_live[CRIS_SRP_REGNUM]") (const_int 0)) | |
3426 | (const_string "no") ; If jump then not slottable. | |
3427 | (if_then_else | |
3428 | (ne (symbol_ref | |
3429 | "(regs_ever_live[0] | |
3430 | || (flag_pic != 0 && regs_ever_live[1]) | |
3431 | || (PIC_OFFSET_TABLE_REGNUM == 0 | |
3432 | && cris_cfun_uses_pic_table ()))") | |
3433 | (const_int 0)) | |
3434 | (const_string "no") ; ret+movem [sp+],rx: slot already filled. | |
3435 | (const_string "has_slot")))) ; If ret then need to fill a slot. | |
3436 | (set_attr "cc" "none")]) | |
3437 | \f | |
3438 | ;; Conditional branches. | |
3439 | ||
3440 | ;; We suffer from the same overflow-bit-gets-in-the-way problem as | |
3441 | ;; e.g. m68k, so we have to check if overflow bit is set on all "signed" | |
3442 | ;; conditions. | |
3443 | ||
3444 | (define_insn "beq" | |
3445 | [(set (pc) | |
3446 | (if_then_else (eq (cc0) | |
3447 | (const_int 0)) | |
3448 | (label_ref (match_operand 0 "" "")) | |
3449 | (pc)))] | |
3450 | "" | |
3451 | "beq %l0%#" | |
3452 | [(set_attr "slottable" "has_slot")]) | |
3453 | ||
3454 | (define_insn "bne" | |
3455 | [(set (pc) | |
3456 | (if_then_else (ne (cc0) | |
3457 | (const_int 0)) | |
3458 | (label_ref (match_operand 0 "" "")) | |
3459 | (pc)))] | |
3460 | "" | |
3461 | "bne %l0%#" | |
3462 | [(set_attr "slottable" "has_slot")]) | |
3463 | ||
3464 | (define_insn "bgt" | |
3465 | [(set (pc) | |
3466 | (if_then_else (gt (cc0) | |
3467 | (const_int 0)) | |
3468 | (label_ref (match_operand 0 "" "")) | |
3469 | (pc)))] | |
3470 | "" | |
3471 | "* | |
3472 | { | |
3473 | return | |
3474 | (cc_prev_status.flags & CC_NO_OVERFLOW) | |
3475 | ? 0 : \"bgt %l0%#\"; | |
3476 | }" | |
3477 | [(set_attr "slottable" "has_slot")]) | |
3478 | ||
3479 | (define_insn "bgtu" | |
3480 | [(set (pc) | |
3481 | (if_then_else (gtu (cc0) | |
3482 | (const_int 0)) | |
3483 | (label_ref (match_operand 0 "" "")) | |
3484 | (pc)))] | |
3485 | "" | |
3486 | "bhi %l0%#" | |
3487 | [(set_attr "slottable" "has_slot")]) | |
3488 | ||
3489 | (define_insn "blt" | |
3490 | [(set (pc) | |
3491 | (if_then_else (lt (cc0) | |
3492 | (const_int 0)) | |
3493 | (label_ref (match_operand 0 "" "")) | |
3494 | (pc)))] | |
3495 | "" | |
3496 | "* | |
3497 | { | |
3498 | return | |
3499 | (cc_prev_status.flags & CC_NO_OVERFLOW) | |
3500 | ? \"bmi %l0%#\" : \"blt %l0%#\"; | |
3501 | }" | |
3502 | [(set_attr "slottable" "has_slot")]) | |
3503 | ||
3504 | (define_insn "bltu" | |
3505 | [(set (pc) | |
3506 | (if_then_else (ltu (cc0) | |
3507 | (const_int 0)) | |
3508 | (label_ref (match_operand 0 "" "")) | |
3509 | (pc)))] | |
3510 | "" | |
3511 | "blo %l0%#" | |
3512 | [(set_attr "slottable" "has_slot")]) | |
3513 | ||
3514 | (define_insn "bge" | |
3515 | [(set (pc) | |
3516 | (if_then_else (ge (cc0) | |
3517 | (const_int 0)) | |
3518 | (label_ref (match_operand 0 "" "")) | |
3519 | (pc)))] | |
3520 | "" | |
3521 | "* | |
3522 | { | |
3523 | return | |
3524 | (cc_prev_status.flags & CC_NO_OVERFLOW) | |
3525 | ? \"bpl %l0%#\" : \"bge %l0%#\"; | |
3526 | }" | |
3527 | [(set_attr "slottable" "has_slot")]) | |
3528 | ||
3529 | (define_insn "bgeu" | |
3530 | [(set (pc) | |
3531 | (if_then_else (geu (cc0) | |
3532 | (const_int 0)) | |
3533 | (label_ref (match_operand 0 "" "")) | |
3534 | (pc)))] | |
3535 | "" | |
3536 | "bhs %l0%#" | |
3537 | [(set_attr "slottable" "has_slot")]) | |
3538 | ||
3539 | (define_insn "ble" | |
3540 | [(set (pc) | |
3541 | (if_then_else (le (cc0) | |
3542 | (const_int 0)) | |
3543 | (label_ref (match_operand 0 "" "")) | |
3544 | (pc)))] | |
3545 | "" | |
3546 | "* | |
3547 | { | |
3548 | return | |
3549 | (cc_prev_status.flags & CC_NO_OVERFLOW) | |
3550 | ? 0 : \"ble %l0%#\"; | |
3551 | }" | |
3552 | [(set_attr "slottable" "has_slot")]) | |
3553 | ||
3554 | (define_insn "bleu" | |
3555 | [(set (pc) | |
3556 | (if_then_else (leu (cc0) | |
3557 | (const_int 0)) | |
3558 | (label_ref (match_operand 0 "" "")) | |
3559 | (pc)))] | |
3560 | "" | |
3561 | "bls %l0%#" | |
3562 | [(set_attr "slottable" "has_slot")]) | |
3563 | \f | |
3564 | ;; Reversed anonymous patterns to the ones above, as mandated. | |
3565 | ||
3566 | (define_insn "*beq_reversed" | |
3567 | [(set (pc) | |
3568 | (if_then_else (eq (cc0) | |
3569 | (const_int 0)) | |
3570 | (pc) | |
3571 | (label_ref (match_operand 0 "" ""))))] | |
3572 | "" | |
3573 | "bne %l0%#" | |
3574 | [(set_attr "slottable" "has_slot")]) | |
3575 | ||
3576 | (define_insn "*bne_reversed" | |
3577 | [(set (pc) | |
3578 | (if_then_else (ne (cc0) | |
3579 | (const_int 0)) | |
3580 | (pc) | |
3581 | (label_ref (match_operand 0 "" ""))))] | |
3582 | "" | |
3583 | "beq %l0%#" | |
3584 | [(set_attr "slottable" "has_slot")]) | |
3585 | ||
3586 | (define_insn "*bgt_reversed" | |
3587 | [(set (pc) | |
3588 | (if_then_else (gt (cc0) | |
3589 | (const_int 0)) | |
3590 | (pc) | |
3591 | (label_ref (match_operand 0 "" ""))))] | |
3592 | "" | |
3593 | "* | |
3594 | { | |
3595 | return | |
3596 | (cc_prev_status.flags & CC_NO_OVERFLOW) | |
3597 | ? 0 : \"ble %l0%#\"; | |
3598 | }" | |
3599 | [(set_attr "slottable" "has_slot")]) | |
3600 | ||
3601 | (define_insn "*bgtu_reversed" | |
3602 | [(set (pc) | |
3603 | (if_then_else (gtu (cc0) | |
3604 | (const_int 0)) | |
3605 | (pc) | |
3606 | (label_ref (match_operand 0 "" ""))))] | |
3607 | "" | |
3608 | "bls %l0%#" | |
3609 | [(set_attr "slottable" "has_slot")]) | |
3610 | ||
3611 | (define_insn "*blt_reversed" | |
3612 | [(set (pc) | |
3613 | (if_then_else (lt (cc0) | |
3614 | (const_int 0)) | |
3615 | (pc) | |
3616 | (label_ref (match_operand 0 "" ""))))] | |
3617 | "" | |
3618 | "* | |
3619 | { | |
3620 | return | |
3621 | (cc_prev_status.flags & CC_NO_OVERFLOW) | |
3622 | ? \"bpl %l0%#\" : \"bge %l0%#\"; | |
3623 | }" | |
3624 | [(set_attr "slottable" "has_slot")]) | |
3625 | ||
3626 | (define_insn "*bltu_reversed" | |
3627 | [(set (pc) | |
3628 | (if_then_else (ltu (cc0) | |
3629 | (const_int 0)) | |
3630 | (pc) | |
3631 | (label_ref (match_operand 0 "" ""))))] | |
3632 | "" | |
3633 | "bhs %l0%#" | |
3634 | [(set_attr "slottable" "has_slot")]) | |
3635 | ||
3636 | (define_insn "*bge_reversed" | |
3637 | [(set (pc) | |
3638 | (if_then_else (ge (cc0) | |
3639 | (const_int 0)) | |
3640 | (pc) | |
3641 | (label_ref (match_operand 0 "" ""))))] | |
3642 | "" | |
3643 | "* | |
3644 | { | |
3645 | return | |
3646 | (cc_prev_status.flags & CC_NO_OVERFLOW) | |
3647 | ? \"bmi %l0%#\" : \"blt %l0%#\"; | |
3648 | }" | |
3649 | [(set_attr "slottable" "has_slot")]) | |
3650 | ||
3651 | (define_insn "*bgeu_reversed" | |
3652 | [(set (pc) | |
3653 | (if_then_else (geu (cc0) | |
3654 | (const_int 0)) | |
3655 | (pc) | |
3656 | (label_ref (match_operand 0 "" ""))))] | |
3657 | "" | |
3658 | "blo %l0%#" | |
3659 | [(set_attr "slottable" "has_slot")]) | |
3660 | ||
3661 | (define_insn "*ble_reversed" | |
3662 | [(set (pc) | |
3663 | (if_then_else (le (cc0) | |
3664 | (const_int 0)) | |
3665 | (pc) | |
3666 | (label_ref (match_operand 0 "" ""))))] | |
3667 | "" | |
3668 | "* | |
3669 | { | |
3670 | return | |
3671 | (cc_prev_status.flags & CC_NO_OVERFLOW) | |
3672 | ? 0 : \"bgt %l0%#\"; | |
3673 | }" | |
3674 | [(set_attr "slottable" "has_slot")]) | |
3675 | ||
3676 | (define_insn "*bleu_reversed" | |
3677 | [(set (pc) | |
3678 | (if_then_else (leu (cc0) | |
3679 | (const_int 0)) | |
3680 | (pc) | |
3681 | (label_ref (match_operand 0 "" ""))))] | |
3682 | "" | |
3683 | "bhi %l0%#" | |
3684 | [(set_attr "slottable" "has_slot")]) | |
3685 | \f | |
3686 | ;; Set on condition: sCC. | |
3687 | ||
3688 | ;; Like bCC, we have to check the overflow bit for | |
3689 | ;; signed conditions. | |
3690 | ||
3691 | (define_insn "sgeu" | |
3692 | [(set (match_operand:SI 0 "register_operand" "=r") | |
3693 | (geu:SI (cc0) (const_int 0)))] | |
3694 | "" | |
3695 | "shs %0" | |
3696 | [(set_attr "slottable" "yes") | |
3697 | (set_attr "cc" "none")]) | |
3698 | ||
3699 | (define_insn "sltu" | |
3700 | [(set (match_operand:SI 0 "register_operand" "=r") | |
3701 | (ltu:SI (cc0) (const_int 0)))] | |
3702 | "" | |
3703 | "slo %0" | |
3704 | [(set_attr "slottable" "yes") | |
3705 | (set_attr "cc" "none")]) | |
3706 | ||
3707 | (define_insn "seq" | |
3708 | [(set (match_operand:SI 0 "register_operand" "=r") | |
3709 | (eq:SI (cc0) (const_int 0)))] | |
3710 | "" | |
3711 | "seq %0" | |
3712 | [(set_attr "slottable" "yes") | |
3713 | (set_attr "cc" "none")]) | |
3714 | ||
3715 | (define_insn "sge" | |
3716 | [(set (match_operand:SI 0 "register_operand" "=r") | |
3717 | (ge:SI (cc0) (const_int 0)))] | |
3718 | "" | |
3719 | "* | |
3720 | { | |
3721 | return | |
3722 | (cc_prev_status.flags & CC_NO_OVERFLOW) | |
3723 | ? \"spl %0\" : \"sge %0\"; | |
3724 | }" | |
3725 | [(set_attr "slottable" "yes") | |
3726 | (set_attr "cc" "none")]) | |
3727 | ||
3728 | (define_insn "sgt" | |
3729 | [(set (match_operand:SI 0 "register_operand" "=r") | |
3730 | (gt:SI (cc0) (const_int 0)))] | |
3731 | "" | |
3732 | "* | |
3733 | { | |
3734 | return | |
3735 | (cc_prev_status.flags & CC_NO_OVERFLOW) | |
3736 | ? 0 : \"sgt %0\"; | |
3737 | }" | |
3738 | [(set_attr "slottable" "yes") | |
3739 | (set_attr "cc" "none")]) | |
3740 | ||
3741 | (define_insn "sgtu" | |
3742 | [(set (match_operand:SI 0 "register_operand" "=r") | |
3743 | (gtu:SI (cc0) (const_int 0)))] | |
3744 | "" | |
3745 | "shi %0" | |
3746 | [(set_attr "slottable" "yes") | |
3747 | (set_attr "cc" "none")]) | |
3748 | ||
3749 | (define_insn "sle" | |
3750 | [(set (match_operand:SI 0 "register_operand" "=r") | |
3751 | (le:SI (cc0) (const_int 0)))] | |
3752 | "" | |
3753 | "* | |
3754 | { | |
3755 | return | |
3756 | (cc_prev_status.flags & CC_NO_OVERFLOW) | |
3757 | ? 0 : \"sle %0\"; | |
3758 | }" | |
3759 | [(set_attr "slottable" "yes") | |
3760 | (set_attr "cc" "none")]) | |
3761 | ||
3762 | (define_insn "sleu" | |
3763 | [(set (match_operand:SI 0 "register_operand" "=r") | |
3764 | (leu:SI (cc0) (const_int 0)))] | |
3765 | "" | |
3766 | "sls %0" | |
0cec6af1 HPN |
3767 | [(set_attr "slottable" "yes") |
3768 | (set_attr "cc" "none")]) | |
0b85d816 HPN |
3769 | |
3770 | (define_insn "slt" | |
3771 | [(set (match_operand:SI 0 "register_operand" "=r") | |
3772 | (lt:SI (cc0) (const_int 0)))] | |
3773 | "" | |
3774 | "* | |
3775 | { | |
3776 | return | |
3777 | (cc_prev_status.flags & CC_NO_OVERFLOW) | |
3778 | ? \"smi %0\" : \"slt %0\"; | |
3779 | }" | |
3780 | [(set_attr "slottable" "yes") | |
3781 | (set_attr "cc" "none")]) | |
3782 | ||
3783 | (define_insn "sne" | |
3784 | [(set (match_operand:SI 0 "register_operand" "=r") | |
3785 | (ne:SI (cc0) (const_int 0)))] | |
3786 | "" | |
3787 | "sne %0" | |
3788 | [(set_attr "slottable" "yes") | |
3789 | (set_attr "cc" "none")]) | |
3790 | \f | |
3791 | ;; Call insns. | |
3792 | ||
3793 | ;; We need to make these patterns "expand", since the real operand is | |
3794 | ;; hidden in a (mem:QI ) inside operand[0] (call_value: operand[1]), | |
3795 | ;; and cannot be checked if it were a "normal" pattern. | |
3796 | ;; Note that "call" and "call_value" are *always* called with a | |
3797 | ;; mem-operand for operand 0 and 1 respective. What happens for combined | |
3798 | ;; instructions is a different issue. | |
3799 | ||
3800 | (define_expand "call" | |
3801 | [(parallel [(call (match_operand:QI 0 "cris_mem_call_operand" "") | |
3802 | (match_operand 1 "general_operand" "")) | |
3803 | ;; 16 is the srp (can't use the symbolic name here) | |
3804 | (clobber (reg:SI 16))])] | |
3805 | "" | |
3806 | " | |
3807 | { | |
3808 | rtx op0; | |
3809 | ||
3810 | if (GET_CODE (operands[0]) != MEM) | |
3811 | abort (); | |
3812 | ||
3813 | if (flag_pic) | |
3814 | { | |
3815 | op0 = XEXP (operands[0], 0); | |
3816 | ||
3817 | /* It might be that code can be generated that jumps to 0 (or to a | |
3818 | specific address). Don't abort on that. At least there's a | |
109b748d | 3819 | testcase. */ |
0b85d816 HPN |
3820 | if (CONSTANT_ADDRESS_P (op0) && GET_CODE (op0) != CONST_INT) |
3821 | { | |
3822 | if (no_new_pseudos) | |
3823 | abort (); | |
3824 | ||
3825 | /* For local symbols (non-PLT), get the plain symbol reference | |
3826 | into a register. For symbols that can be PLT, make them PLT. */ | |
3827 | if (cris_gotless_symbol (op0) || GET_CODE (op0) != SYMBOL_REF) | |
3828 | op0 = force_reg (Pmode, op0); | |
3829 | else if (cris_symbol (op0)) | |
3830 | /* FIXME: Would hanging a REG_EQUIV/EQUAL on that register | |
3831 | for the symbol cause bad recombinatorial effects? */ | |
3832 | op0 = force_reg (Pmode, | |
3833 | gen_rtx_CONST | |
3834 | (VOIDmode, | |
3835 | gen_rtx_UNSPEC (VOIDmode, | |
3836 | gen_rtvec (1, op0), 0))); | |
3837 | else | |
3838 | abort (); | |
3839 | ||
dbb138ce | 3840 | operands[0] = replace_equiv_address (operands[0], op0); |
0b85d816 HPN |
3841 | } |
3842 | } | |
3843 | }") | |
3844 | ||
3845 | ;; Accept *anything* as operand 1. Accept operands for operand 0 in | |
3846 | ;; order of preference (Q includes r, but r is shorter, faster) | |
3847 | ||
3848 | (define_insn "*expanded_call" | |
3849 | [(call (mem:QI (match_operand:SI | |
3850 | 0 "cris_general_operand_or_plt_symbol" "r,Q>,g,S")) | |
3851 | (match_operand 1 "" "")) | |
3852 | (clobber (reg:SI 16))] ;; 16 is the srp (can't use symbolic name) | |
3853 | "! TARGET_AVOID_GOTPLT" | |
3854 | "jsr %0") | |
3855 | ||
3856 | ;; Same as above, since can't afford wasting a constraint letter to mean | |
3857 | ;; "S unless TARGET_AVOID_GOTPLT". | |
3858 | (define_insn "*expanded_call_no_gotplt" | |
3859 | [(call (mem:QI (match_operand:SI | |
3860 | 0 "cris_general_operand_or_plt_symbol" "r,Q>,g")) | |
3861 | (match_operand 1 "" "")) | |
3862 | (clobber (reg:SI 16))] ;; 16 is the srp (can't use symbolic name) | |
3863 | "TARGET_AVOID_GOTPLT" | |
3864 | "jsr %0") | |
3865 | ||
3866 | (define_expand "call_value" | |
3867 | [(parallel [(set (match_operand 0 "" "") | |
3868 | (call (match_operand:QI 1 "cris_mem_call_operand" "") | |
3869 | (match_operand 2 "" ""))) | |
3870 | ;; 16 is the srp (can't use symbolic name) | |
3871 | (clobber (reg:SI 16))])] | |
3872 | "" | |
3873 | " | |
3874 | { | |
3875 | rtx op1; | |
3876 | ||
3877 | if (GET_CODE (operands[1]) != MEM) | |
3878 | abort (); | |
3879 | ||
3880 | if (flag_pic) | |
3881 | { | |
3882 | op1 = XEXP (operands[1], 0); | |
3883 | ||
3884 | /* It might be that code can be generated that jumps to 0 (or to a | |
3885 | specific address). Don't abort on that. At least there's a | |
109b748d | 3886 | testcase. */ |
0b85d816 HPN |
3887 | if (CONSTANT_ADDRESS_P (op1) && GET_CODE (op1) != CONST_INT) |
3888 | { | |
3889 | if (no_new_pseudos) | |
3890 | abort (); | |
3891 | ||
3892 | if (cris_gotless_symbol (op1)) | |
3893 | op1 = force_reg (Pmode, op1); | |
3894 | else if (cris_symbol (op1)) | |
3895 | /* FIXME: Would hanging a REG_EQUIV/EQUAL on that register | |
3896 | for the symbol cause bad recombinatorial effects? */ | |
3897 | op1 = force_reg (Pmode, | |
3898 | gen_rtx_CONST | |
3899 | (VOIDmode, | |
3900 | gen_rtx_UNSPEC (VOIDmode, | |
3901 | gen_rtvec (1, op1), 0))); | |
3902 | else | |
3903 | abort (); | |
3904 | ||
dbb138ce | 3905 | operands[1] = replace_equiv_address (operands[1], op1); |
0b85d816 HPN |
3906 | } |
3907 | } | |
3908 | }") | |
3909 | ||
3910 | ;; Accept *anything* as operand 2. The validity other than "general" of | |
3911 | ;; operand 0 will be checked elsewhere. Accept operands for operand 1 in | |
3912 | ;; order of preference (Q includes r, but r is shorter, faster). | |
3913 | ;; We also accept a PLT symbol. We output it as [rPIC+sym:GOTPLT] rather | |
3914 | ;; than requiring getting rPIC + sym:PLT into a register. | |
3915 | ||
3916 | (define_insn "*expanded_call_value" | |
3917 | [(set (match_operand 0 "nonimmediate_operand" "=g,g,g,g") | |
3918 | (call (mem:QI (match_operand:SI | |
3919 | 1 "cris_general_operand_or_plt_symbol" "r,Q>,g,S")) | |
3920 | (match_operand 2 "" ""))) | |
3921 | (clobber (reg:SI 16))] | |
3922 | "! TARGET_AVOID_GOTPLT" | |
3923 | "Jsr %1" | |
3924 | [(set_attr "cc" "clobber")]) | |
3925 | ||
3926 | ;; Same as above, since can't afford wasting a constraint letter to mean | |
3927 | ;; "S unless TARGET_AVOID_GOTPLT". | |
3928 | (define_insn "*expanded_call_value_no_gotplt" | |
3929 | [(set (match_operand 0 "nonimmediate_operand" "=g,g,g") | |
3930 | (call (mem:QI (match_operand:SI | |
3931 | 1 "cris_general_operand_or_plt_symbol" "r,Q>,g")) | |
3932 | (match_operand 2 "" ""))) | |
3933 | (clobber (reg:SI 16))] | |
3934 | "TARGET_AVOID_GOTPLT" | |
3935 | "Jsr %1" | |
3936 | [(set_attr "cc" "clobber")]) | |
3937 | ||
3938 | ;; Used in debugging. No use for the direct pattern; unfilled | |
3939 | ;; delayed-branches are taken care of by other means. | |
3940 | ||
3941 | (define_insn "nop" | |
3942 | [(const_int 0)] | |
3943 | "" | |
3944 | "nop" | |
3945 | [(set_attr "cc" "none")]) | |
3946 | \f | |
3947 | ;; We expand on casesi so we can use "bound" and "add offset fetched from | |
3948 | ;; a table to pc" (adds.w [pc+%0.w],pc). | |
3949 | ||
3950 | ;; Note: if you change the "parallel" (or add anything after it) in | |
3951 | ;; this expansion, you must change the macro ASM_OUTPUT_CASE_END | |
3952 | ;; accordingly, to add the default case at the end of the jump-table. | |
3953 | ||
3954 | (define_expand "casesi" | |
3955 | [(set (match_dup 5) (match_operand:SI 0 "general_operand" "")) | |
3956 | (set (match_dup 6) | |
3957 | (minus:SI (match_dup 5) | |
3958 | (match_operand:SI 1 "const_int_operand" "n"))) | |
3959 | (set (match_dup 7) | |
3960 | (umin:SI (match_dup 6) | |
3961 | (match_operand:SI 2 "const_int_operand" "n"))) | |
3962 | (parallel | |
3963 | [(set (pc) | |
3964 | (if_then_else | |
3965 | (ltu (match_dup 7) (match_dup 2)) | |
3966 | (plus:SI (sign_extend:SI | |
3967 | (mem:HI | |
3968 | (plus:SI (mult:SI (match_dup 7) (const_int 2)) | |
3969 | (pc)))) | |
3970 | (pc)) | |
3971 | (label_ref (match_operand 4 "" "")))) | |
3972 | (use (label_ref (match_operand 3 "" "")))])] | |
3973 | "" | |
3974 | " | |
3975 | { | |
3976 | operands[2] = plus_constant (operands[2], 1); | |
3977 | operands[5] = gen_reg_rtx (SImode); | |
3978 | operands[6] = gen_reg_rtx (SImode); | |
3979 | operands[7] = gen_reg_rtx (SImode); | |
3980 | }") | |
3981 | \f | |
3982 | ;; Split-patterns. Some of them have modes unspecified. This | |
3983 | ;; should always be ok; if for no other reason sparc.md has it as | |
3984 | ;; well. | |
3985 | ;; | |
3986 | ;; When register_operand is specified for an operand, we can get a | |
3987 | ;; subreg as well (Axis-990331), so don't just assume that REG_P is true | |
3988 | ;; for a register_operand and that REGNO can be used as is. It is best to | |
3989 | ;; guard with REG_P, unless it is worth it to adjust for the subreg case. | |
3990 | ||
3991 | ;; op [rx + 0],ry,rz | |
3992 | ;; The index to rx is optimized into zero, and gone. | |
3993 | ||
3994 | ;; First, recognize bound [rx],ry,rz; where [rx] is zero-extended, | |
3995 | ;; and add/sub [rx],ry,rz, with zero or sign-extend on [rx]. | |
3996 | ;; Split this into: | |
3997 | ;; move ry,rz | |
3998 | ;; op [rx],rz | |
3999 | ;; Lose if rz=ry or rx=rz. | |
4000 | ;; Call this op-extend-split | |
4001 | ||
4002 | (define_split | |
4003 | [(set (match_operand 0 "register_operand" "") | |
4004 | (match_operator | |
4005 | 4 "cris_operand_extend_operator" | |
4006 | [(match_operand 1 "register_operand" "") | |
4007 | (match_operator | |
4008 | 3 "cris_extend_operator" | |
4009 | [(match_operand 2 "memory_operand" "")])]))] | |
4010 | "REG_P (operands[0]) | |
4011 | && REG_P (operands[1]) | |
4012 | && REGNO (operands[1]) != REGNO (operands[0]) | |
4013 | && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD | |
4014 | && REG_P (XEXP (operands[2], 0)) | |
4015 | && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])" | |
4016 | [(set (match_dup 0) | |
4017 | (match_dup 1)) | |
4018 | (set (match_dup 0) | |
4019 | (match_op_dup | |
4020 | 4 [(match_dup 0) | |
4021 | (match_op_dup 3 [(match_dup 2)])]))] | |
4022 | "") | |
4023 | ||
4024 | ;; As op-extend-split, but recognize and split op [rz],ry,rz into | |
4025 | ;; ext [rz],rz | |
4026 | ;; op ry,rz | |
4027 | ;; Do this for plus or bound only, being commutative operations, since we | |
4028 | ;; have swapped the operands. | |
4029 | ;; Call this op-extend-split-rx=rz | |
4030 | ||
4031 | (define_split | |
4032 | [(set (match_operand 0 "register_operand" "") | |
4033 | (match_operator | |
4034 | 4 "cris_plus_or_bound_operator" | |
4035 | [(match_operand 1 "register_operand" "") | |
4036 | (match_operator | |
4037 | 3 "cris_extend_operator" | |
4038 | [(match_operand 2 "memory_operand" "")])]))] | |
4039 | "REG_P (operands[0]) | |
4040 | && REG_P (operands[1]) | |
4041 | && REGNO (operands[1]) != REGNO (operands[0]) | |
4042 | && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD | |
4043 | && REG_P (XEXP (operands[2], 0)) | |
4044 | && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])" | |
4045 | [(set (match_dup 0) | |
4046 | (match_op_dup 3 [(match_dup 2)])) | |
4047 | (set (match_dup 0) | |
4048 | (match_op_dup | |
4049 | 4 [(match_dup 0) | |
4050 | (match_dup 1)]))] | |
4051 | "") | |
4052 | ||
4053 | ;; As the op-extend-split, but swapped operands, and only for | |
4054 | ;; plus or bound, being the commutative extend-operators. FIXME: Why is | |
4055 | ;; this needed? Is it? | |
4056 | ;; Call this op-extend-split-swapped | |
4057 | ||
4058 | (define_split | |
4059 | [(set (match_operand 0 "register_operand" "") | |
4060 | (match_operator | |
4061 | 4 "cris_plus_or_bound_operator" | |
4062 | [(match_operator | |
4063 | 3 "cris_extend_operator" | |
4064 | [(match_operand 2 "memory_operand" "")]) | |
4065 | (match_operand 1 "register_operand" "")]))] | |
4066 | "REG_P (operands[0]) | |
4067 | && REG_P (operands[1]) | |
4068 | && REGNO (operands[1]) != REGNO (operands[0]) | |
4069 | && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD | |
4070 | && REG_P (XEXP (operands[2], 0)) | |
4071 | && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])" | |
4072 | [(set (match_dup 0) | |
4073 | (match_dup 1)) | |
4074 | (set (match_dup 0) | |
4075 | (match_op_dup | |
4076 | 4 [(match_dup 0) | |
4077 | (match_op_dup 3 [(match_dup 2)])]))] | |
4078 | "") | |
4079 | ||
4080 | ;; As op-extend-split-rx=rz, but swapped operands, only for plus or | |
4081 | ;; bound. Call this op-extend-split-swapped-rx=rz. | |
4082 | ||
4083 | (define_split | |
4084 | [(set (match_operand 0 "register_operand" "") | |
4085 | (match_operator | |
4086 | 4 "cris_plus_or_bound_operator" | |
4087 | [(match_operator | |
4088 | 3 "cris_extend_operator" | |
4089 | [(match_operand 2 "memory_operand" "")]) | |
4090 | (match_operand 1 "register_operand" "")]))] | |
4091 | "REG_P (operands[0]) | |
4092 | && REG_P (operands[1]) | |
4093 | && REGNO (operands[1]) != REGNO (operands[0]) | |
4094 | && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD | |
4095 | && REG_P (XEXP (operands[2], 0)) | |
4096 | && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])" | |
4097 | [(set (match_dup 0) | |
4098 | (match_op_dup 3 [(match_dup 2)])) | |
4099 | (set (match_dup 0) | |
4100 | (match_op_dup | |
4101 | 4 [(match_dup 0) | |
4102 | (match_dup 1)]))] | |
4103 | "") | |
4104 | ||
4105 | ;; As op-extend-split, but the mem operand is not extended. | |
4106 | ;; | |
4107 | ;; op [rx],ry,rz changed into | |
4108 | ;; move ry,rz | |
4109 | ;; op [rx],rz | |
4110 | ;; lose if ry=rz or rx=rz | |
4111 | ;; Call this op-extend. | |
4112 | ||
4113 | (define_split | |
4114 | [(set (match_operand 0 "register_operand" "") | |
4115 | (match_operator | |
4116 | 3 "cris_orthogonal_operator" | |
4117 | [(match_operand 1 "register_operand" "") | |
4118 | (match_operand 2 "memory_operand" "")]))] | |
4119 | "REG_P (operands[0]) | |
4120 | && REG_P (operands[1]) | |
4121 | && REGNO (operands[1]) != REGNO (operands[0]) | |
4122 | && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD | |
4123 | && REG_P (XEXP (operands[2], 0)) | |
4124 | && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])" | |
4125 | [(set (match_dup 0) | |
4126 | (match_dup 1)) | |
4127 | (set (match_dup 0) | |
4128 | (match_op_dup | |
4129 | 3 [(match_dup 0) | |
4130 | (match_dup 2)]))] | |
4131 | "") | |
4132 | ||
4133 | ;; As op-extend-split-rx=rz, non-extended. | |
4134 | ;; Call this op-split-rx=rz | |
4135 | ||
4136 | (define_split | |
4137 | [(set (match_operand 0 "register_operand" "") | |
4138 | (match_operator | |
4139 | 3 "cris_commutative_orth_op" | |
4140 | [(match_operand 2 "memory_operand" "") | |
4141 | (match_operand 1 "register_operand" "")]))] | |
4142 | "REG_P (operands[0]) | |
4143 | && REG_P (operands[1]) | |
4144 | && REGNO (operands[1]) != REGNO (operands[0]) | |
4145 | && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD | |
4146 | && REG_P (XEXP (operands[2], 0)) | |
4147 | && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])" | |
4148 | [(set (match_dup 0) | |
4149 | (match_dup 1)) | |
4150 | (set (match_dup 0) | |
4151 | (match_op_dup | |
4152 | 3 [(match_dup 0) | |
4153 | (match_dup 2)]))] | |
4154 | "") | |
4155 | ||
4156 | ;; As op-extend-split-swapped, nonextended. | |
4157 | ;; Call this op-split-swapped. | |
4158 | ||
4159 | (define_split | |
4160 | [(set (match_operand 0 "register_operand" "") | |
4161 | (match_operator | |
4162 | 3 "cris_commutative_orth_op" | |
4163 | [(match_operand 1 "register_operand" "") | |
4164 | (match_operand 2 "memory_operand" "")]))] | |
4165 | "REG_P (operands[0]) && REG_P (operands[1]) | |
4166 | && REGNO (operands[1]) != REGNO (operands[0]) | |
4167 | && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD | |
4168 | && REG_P (XEXP (operands[2], 0)) | |
4169 | && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])" | |
4170 | [(set (match_dup 0) | |
4171 | (match_dup 2)) | |
4172 | (set (match_dup 0) | |
4173 | (match_op_dup | |
4174 | 3 [(match_dup 0) | |
4175 | (match_dup 1)]))] | |
4176 | "") | |
4177 | ||
4178 | ;; As op-extend-split-swapped-rx=rz, non-extended. | |
4179 | ;; Call this op-split-swapped-rx=rz. | |
4180 | ||
4181 | (define_split | |
4182 | [(set (match_operand 0 "register_operand" "") | |
4183 | (match_operator | |
4184 | 3 "cris_orthogonal_operator" | |
4185 | [(match_operand 2 "memory_operand" "") | |
4186 | (match_operand 1 "register_operand" "")]))] | |
4187 | "REG_P (operands[0]) && REG_P (operands[1]) | |
4188 | && REGNO (operands[1]) != REGNO (operands[0]) | |
4189 | && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD | |
4190 | && REG_P (XEXP (operands[2], 0)) | |
4191 | && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])" | |
4192 | [(set (match_dup 0) | |
4193 | (match_dup 2)) | |
4194 | (set (match_dup 0) | |
4195 | (match_op_dup | |
4196 | 3 [(match_dup 0) | |
4197 | (match_dup 1)]))] | |
4198 | "") | |
4199 | \f | |
4200 | ;; Splits for all cases in side-effect insns where (possibly after reload | |
4201 | ;; and register allocation) rx and ry in [rx=ry+i] are equal. | |
4202 | ||
4203 | ;; move.S1 [rx=rx+rz.S2],ry | |
4204 | ||
4205 | (define_split | |
4206 | [(parallel | |
4207 | [(set (match_operand 0 "register_operand" "") | |
dbb138ce HPN |
4208 | (match_operator |
4209 | 6 "cris_mem_op" | |
4210 | [(plus:SI | |
4211 | (mult:SI (match_operand:SI 1 "register_operand" "") | |
4212 | (match_operand:SI 2 "const_int_operand" "")) | |
4213 | (match_operand:SI 3 "register_operand" ""))])) | |
0b85d816 HPN |
4214 | (set (match_operand:SI 4 "register_operand" "") |
4215 | (plus:SI (mult:SI (match_dup 1) | |
4216 | (match_dup 2)) | |
4217 | (match_dup 3)))])] | |
4218 | "REG_P (operands[3]) && REG_P (operands[4]) | |
4219 | && REGNO (operands[3]) == REGNO (operands[4])" | |
4220 | [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2)) | |
4221 | (match_dup 3))) | |
4222 | (set (match_dup 0) (match_dup 5))] | |
dbb138ce | 4223 | "operands[5] = replace_equiv_address (operands[6], operands[3]);") |
0b85d816 HPN |
4224 | |
4225 | ;; move.S1 [rx=rx+i],ry | |
4226 | ||
4227 | (define_split | |
4228 | [(parallel | |
4229 | [(set (match_operand 0 "register_operand" "") | |
dbb138ce HPN |
4230 | (match_operator |
4231 | 5 "cris_mem_op" | |
4232 | [(plus:SI (match_operand:SI 1 "cris_bdap_operand" "") | |
4233 | (match_operand:SI 2 "cris_bdap_operand" ""))])) | |
0b85d816 HPN |
4234 | (set (match_operand:SI 3 "register_operand" "") |
4235 | (plus:SI (match_dup 1) | |
4236 | (match_dup 2)))])] | |
4237 | "(rtx_equal_p (operands[3], operands[1]) | |
4238 | || rtx_equal_p (operands[3], operands[2]))" | |
4239 | [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2))) | |
4240 | (set (match_dup 0) (match_dup 4))] | |
dbb138ce | 4241 | "operands[4] = replace_equiv_address (operands[5], operands[3]);") |
0b85d816 HPN |
4242 | |
4243 | ;; move.S1 ry,[rx=rx+rz.S2] | |
4244 | ||
4245 | (define_split | |
4246 | [(parallel | |
dbb138ce HPN |
4247 | [(set (match_operator |
4248 | 6 "cris_mem_op" | |
4249 | [(plus:SI | |
4250 | (mult:SI (match_operand:SI 0 "register_operand" "") | |
4251 | (match_operand:SI 1 "const_int_operand" "")) | |
4252 | (match_operand:SI 2 "register_operand" ""))]) | |
4253 | (match_operand 3 "register_operand" "")) | |
0b85d816 HPN |
4254 | (set (match_operand:SI 4 "register_operand" "") |
4255 | (plus:SI (mult:SI (match_dup 0) | |
4256 | (match_dup 1)) | |
4257 | (match_dup 2)))])] | |
4258 | "REG_P (operands[2]) && REG_P (operands[4]) | |
4259 | && REGNO (operands[4]) == REGNO (operands[2])" | |
4260 | [(set (match_dup 4) (plus:SI (mult:SI (match_dup 0) (match_dup 1)) | |
4261 | (match_dup 2))) | |
4262 | (set (match_dup 5) (match_dup 3))] | |
dbb138ce | 4263 | "operands[5] = replace_equiv_address (operands[6], operands[4]);") |
0b85d816 HPN |
4264 | |
4265 | ;; move.S1 ry,[rx=rx+i] | |
4266 | ||
4267 | (define_split | |
4268 | [(parallel | |
dbb138ce HPN |
4269 | [(set (match_operator |
4270 | 6 "cris_mem_op" | |
4271 | [(plus:SI (match_operand:SI 0 "cris_bdap_operand" "") | |
4272 | (match_operand:SI 1 "cris_bdap_operand" ""))]) | |
4273 | (match_operand 2 "register_operand" "")) | |
0b85d816 HPN |
4274 | (set (match_operand:SI 3 "register_operand" "") |
4275 | (plus:SI (match_dup 0) | |
4276 | (match_dup 1)))])] | |
4277 | "(rtx_equal_p (operands[3], operands[0]) | |
4278 | || rtx_equal_p (operands[3], operands[1]))" | |
4279 | [(set (match_dup 3) (plus:SI (match_dup 0) (match_dup 1))) | |
4280 | (set (match_dup 5) (match_dup 2))] | |
dbb138ce | 4281 | "operands[5] = replace_equiv_address (operands[6], operands[3]);") |
0b85d816 | 4282 | |
049746c2 | 4283 | ;; clear.d [rx=rx+rz.S2] |
0b85d816 HPN |
4284 | |
4285 | (define_split | |
4286 | [(parallel | |
4287 | [(set (mem:SI (plus:SI | |
4288 | (mult:SI (match_operand:SI 0 "register_operand" "") | |
4289 | (match_operand:SI 1 "const_int_operand" "")) | |
4290 | (match_operand:SI 2 "register_operand" ""))) | |
4291 | (const_int 0)) | |
4292 | (set (match_operand:SI 3 "register_operand" "") | |
4293 | (plus:SI (mult:SI (match_dup 0) | |
4294 | (match_dup 1)) | |
4295 | (match_dup 2)))])] | |
4296 | "REG_P (operands[2]) && REG_P (operands[3]) | |
4297 | && REGNO (operands[3]) == REGNO (operands[2])" | |
4298 | [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1)) | |
4299 | (match_dup 2))) | |
4300 | (set (mem:SI (match_dup 3)) (const_int 0))] | |
4301 | "") | |
4302 | ||
049746c2 | 4303 | ;; clear.w [rx=rx+rz.S2] |
0b85d816 HPN |
4304 | |
4305 | (define_split | |
4306 | [(parallel | |
4307 | [(set (mem:HI (plus:SI | |
4308 | (mult:SI (match_operand:SI 0 "register_operand" "") | |
4309 | (match_operand:SI 1 "const_int_operand" "")) | |
4310 | (match_operand:SI 2 "register_operand" ""))) | |
4311 | (const_int 0)) | |
4312 | (set (match_operand:SI 3 "register_operand" "") | |
4313 | (plus:SI (mult:SI (match_dup 0) | |
4314 | (match_dup 1)) | |
4315 | (match_dup 2)))])] | |
4316 | "REG_P (operands[2]) && REG_P (operands[3]) | |
4317 | && REGNO (operands[3]) == REGNO (operands[2])" | |
4318 | [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1)) | |
4319 | (match_dup 2))) | |
4320 | (set (mem:HI (match_dup 3)) (const_int 0))] | |
4321 | "") | |
4322 | ||
049746c2 | 4323 | ;; clear.b [rx=rx+rz.S2] |
0b85d816 HPN |
4324 | |
4325 | (define_split | |
4326 | [(parallel | |
4327 | [(set (mem:QI (plus:SI | |
4328 | (mult:SI (match_operand:SI 0 "register_operand" "") | |
4329 | (match_operand:SI 1 "const_int_operand" "")) | |
4330 | (match_operand:SI 2 "register_operand" ""))) | |
4331 | (const_int 0)) | |
4332 | (set (match_operand:SI 3 "register_operand" "") | |
4333 | (plus:SI (mult:SI (match_dup 0) | |
4334 | (match_dup 1)) | |
4335 | (match_dup 2)))])] | |
4336 | "REG_P (operands[2]) && REG_P (operands[3]) | |
4337 | && REGNO (operands[3]) == REGNO (operands[2])" | |
4338 | [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1)) | |
4339 | (match_dup 2))) | |
4340 | (set (mem:QI (match_dup 3)) (const_int 0))] | |
4341 | "") | |
4342 | ||
049746c2 | 4343 | ;; clear.d [rx=rx+i] |
0b85d816 HPN |
4344 | |
4345 | (define_split | |
4346 | [(parallel | |
4347 | [(set (mem:SI | |
4348 | (plus:SI (match_operand:SI 0 "cris_bdap_operand" "") | |
4349 | (match_operand:SI 1 "cris_bdap_operand" ""))) | |
4350 | (const_int 0)) | |
4351 | (set (match_operand:SI 2 "register_operand" "") | |
4352 | (plus:SI (match_dup 0) | |
4353 | (match_dup 1)))])] | |
4354 | "(rtx_equal_p (operands[0], operands[2]) | |
4355 | || rtx_equal_p (operands[2], operands[1]))" | |
4356 | [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1))) | |
4357 | (set (mem:SI (match_dup 2)) (const_int 0))] | |
4358 | "") | |
4359 | ||
049746c2 | 4360 | ;; clear.w [rx=rx+i] |
0b85d816 HPN |
4361 | |
4362 | (define_split | |
4363 | [(parallel | |
4364 | [(set (mem:HI | |
4365 | (plus:SI (match_operand:SI 0 "cris_bdap_operand" "") | |
4366 | (match_operand:SI 1 "cris_bdap_operand" ""))) | |
4367 | (const_int 0)) | |
4368 | (set (match_operand:SI 2 "register_operand" "") | |
4369 | (plus:SI (match_dup 0) | |
4370 | (match_dup 1)))])] | |
4371 | "(rtx_equal_p (operands[0], operands[2]) | |
4372 | || rtx_equal_p (operands[2], operands[1]))" | |
4373 | [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1))) | |
4374 | (set (mem:HI (match_dup 2)) (const_int 0))] | |
4375 | "") | |
4376 | ||
049746c2 | 4377 | ;; clear.b [rx=rx+i] |
0b85d816 HPN |
4378 | |
4379 | (define_split | |
4380 | [(parallel | |
4381 | [(set (mem:QI | |
4382 | (plus:SI (match_operand:SI 0 "cris_bdap_operand" "") | |
4383 | (match_operand:SI 1 "cris_bdap_operand" ""))) | |
4384 | (const_int 0)) | |
4385 | (set (match_operand:SI 2 "register_operand" "") | |
4386 | (plus:SI (match_dup 0) | |
4387 | (match_dup 1)))])] | |
4388 | "(rtx_equal_p (operands[0], operands[2]) | |
4389 | || rtx_equal_p (operands[2], operands[1]))" | |
4390 | [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1))) | |
4391 | (set (mem:QI (match_dup 2)) (const_int 0))] | |
4392 | "") | |
4393 | ||
4394 | ;; mov(s|u).S1 [rx=rx+rz.S2],ry | |
4395 | ||
4396 | (define_split | |
4397 | [(parallel | |
4398 | [(set (match_operand 0 "register_operand" "") | |
4399 | (match_operator | |
4400 | 5 "cris_extend_operator" | |
4401 | [(mem (plus:SI | |
4402 | (mult:SI (match_operand:SI 1 "register_operand" "") | |
4403 | (match_operand:SI 2 "const_int_operand" "")) | |
4404 | (match_operand:SI 3 "register_operand" "")))])) | |
4405 | (set (match_operand:SI 4 "register_operand" "") | |
4406 | (plus:SI (mult:SI (match_dup 1) | |
4407 | (match_dup 2)) | |
4408 | (match_dup 3)))])] | |
4409 | "REG_P (operands[3]) | |
4410 | && REG_P (operands[4]) | |
4411 | && REGNO (operands[3]) == REGNO (operands[4])" | |
4412 | [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2)) | |
4413 | (match_dup 3))) | |
4414 | (set (match_dup 0) (match_op_dup 5 [(match_dup 6)]))] | |
dbb138ce | 4415 | "operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);") |
0b85d816 HPN |
4416 | |
4417 | ;; mov(s|u).S1 [rx=rx+i],ry | |
4418 | ||
4419 | (define_split | |
4420 | [(parallel | |
4421 | [(set (match_operand 0 "register_operand" "") | |
4422 | (match_operator | |
4423 | 4 "cris_extend_operator" | |
4424 | [(mem (plus:SI | |
4425 | (match_operand:SI 1 "cris_bdap_operand" "") | |
4426 | (match_operand:SI 2 "cris_bdap_operand" "")))])) | |
4427 | (set (match_operand:SI 3 "register_operand" "") | |
4428 | (plus:SI (match_dup 1) | |
4429 | (match_dup 2)))])] | |
4430 | "(rtx_equal_p (operands[1], operands[3]) | |
4431 | || rtx_equal_p (operands[2], operands[3]))" | |
4432 | [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2))) | |
4433 | (set (match_dup 0) (match_op_dup 4 [(match_dup 5)]))] | |
dbb138ce | 4434 | "operands[5] = replace_equiv_address (XEXP (operands[4], 0), operands[3]);") |
0b85d816 HPN |
4435 | |
4436 | ;; op.S1 [rx=rx+i],ry | |
4437 | ||
4438 | (define_split | |
4439 | [(parallel | |
4440 | [(set (match_operand 0 "register_operand" "") | |
4441 | (match_operator | |
4442 | 5 "cris_orthogonal_operator" | |
4443 | [(match_operand 1 "register_operand" "") | |
4444 | (mem (plus:SI | |
4445 | (match_operand:SI 2 "cris_bdap_operand" "") | |
4446 | (match_operand:SI 3 "cris_bdap_operand" "")))])) | |
4447 | (set (match_operand:SI 4 "register_operand" "") | |
4448 | (plus:SI (match_dup 2) | |
4449 | (match_dup 3)))])] | |
4450 | "(rtx_equal_p (operands[4], operands[2]) | |
4451 | || rtx_equal_p (operands[4], operands[3]))" | |
4452 | [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3))) | |
4453 | (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 6)]))] | |
dbb138ce | 4454 | "operands[6] = replace_equiv_address (XEXP (operands[5], 1), operands[4]);") |
0b85d816 HPN |
4455 | |
4456 | ;; op.S1 [rx=rx+rz.S2],ry | |
4457 | ||
4458 | (define_split | |
4459 | [(parallel | |
4460 | [(set (match_operand 0 "register_operand" "") | |
4461 | (match_operator | |
4462 | 6 "cris_orthogonal_operator" | |
4463 | [(match_operand 1 "register_operand" "") | |
4464 | (mem (plus:SI | |
4465 | (mult:SI (match_operand:SI 2 "register_operand" "") | |
4466 | (match_operand:SI 3 "const_int_operand" "")) | |
4467 | (match_operand:SI 4 "register_operand" "")))])) | |
4468 | (set (match_operand:SI 5 "register_operand" "") | |
4469 | (plus:SI (mult:SI (match_dup 2) | |
4470 | (match_dup 3)) | |
4471 | (match_dup 4)))])] | |
4472 | "REG_P (operands[4]) | |
4473 | && REG_P (operands[5]) | |
4474 | && REGNO (operands[5]) == REGNO (operands[4])" | |
4475 | [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3)) | |
4476 | (match_dup 4))) | |
4477 | (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 7)]))] | |
dbb138ce | 4478 | "operands[7] = replace_equiv_address (XEXP (operands[6], 1), operands[5]);") |
0b85d816 HPN |
4479 | |
4480 | ;; op.S1 [rx=rx+rz.S2],ry (swapped) | |
4481 | ||
4482 | (define_split | |
4483 | [(parallel | |
4484 | [(set (match_operand 0 "register_operand" "") | |
4485 | (match_operator | |
4486 | 6 "cris_commutative_orth_op" | |
4487 | [(mem (plus:SI | |
4488 | (mult:SI (match_operand:SI 2 "register_operand" "") | |
4489 | (match_operand:SI 3 "const_int_operand" "")) | |
4490 | (match_operand:SI 4 "register_operand" ""))) | |
4491 | (match_operand 1 "register_operand" "")])) | |
4492 | (set (match_operand:SI 5 "register_operand" "") | |
4493 | (plus:SI (mult:SI (match_dup 2) | |
4494 | (match_dup 3)) | |
4495 | (match_dup 4)))])] | |
4496 | "REG_P (operands[4]) | |
4497 | && REG_P (operands[5]) | |
4498 | && REGNO (operands[5]) == REGNO (operands[4])" | |
4499 | [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3)) | |
4500 | (match_dup 4))) | |
4501 | (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))] | |
dbb138ce | 4502 | "operands[7] = replace_equiv_address (XEXP (operands[6], 0), operands[5]);") |
0b85d816 HPN |
4503 | |
4504 | ;; op.S1 [rx=rx+i],ry (swapped) | |
4505 | ||
4506 | (define_split | |
4507 | [(parallel | |
4508 | [(set (match_operand 0 "register_operand" "") | |
4509 | (match_operator | |
4510 | 5 "cris_commutative_orth_op" | |
4511 | [(mem | |
4512 | (plus:SI (match_operand:SI 2 "cris_bdap_operand" "") | |
4513 | (match_operand:SI 3 "cris_bdap_operand" ""))) | |
4514 | (match_operand 1 "register_operand" "")])) | |
4515 | (set (match_operand:SI 4 "register_operand" "") | |
4516 | (plus:SI (match_dup 2) | |
4517 | (match_dup 3)))])] | |
4518 | "(rtx_equal_p (operands[4], operands[2]) | |
4519 | || rtx_equal_p (operands[4], operands[3]))" | |
4520 | [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3))) | |
4521 | (set (match_dup 0) (match_op_dup 5 [(match_dup 6) (match_dup 1)]))] | |
dbb138ce | 4522 | "operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);") |
0b85d816 HPN |
4523 | |
4524 | ;; op(s|u).S1 [rx=rx+rz.S2],ry | |
4525 | ||
4526 | (define_split | |
4527 | [(parallel | |
4528 | [(set (match_operand 0 "register_operand" "") | |
4529 | (match_operator | |
4530 | 6 "cris_operand_extend_operator" | |
4531 | [(match_operand 1 "register_operand" "") | |
4532 | (match_operator | |
4533 | 7 "cris_extend_operator" | |
4534 | [(mem (plus:SI | |
4535 | (mult:SI (match_operand:SI 2 "register_operand" "") | |
4536 | (match_operand:SI 3 "const_int_operand" "")) | |
4537 | (match_operand:SI 4 "register_operand" "")))])])) | |
4538 | (set (match_operand:SI 5 "register_operand" "") | |
4539 | (plus:SI (mult:SI (match_dup 2) | |
4540 | (match_dup 3)) | |
4541 | (match_dup 4)))])] | |
4542 | "REG_P (operands[4]) | |
4543 | && REG_P (operands[5]) | |
4544 | && REGNO (operands[5]) == REGNO (operands[4])" | |
4545 | [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3)) | |
4546 | (match_dup 4))) | |
4547 | (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 8)]))] | |
1c563bed | 4548 | "operands[8] = gen_rtx_fmt_e (GET_CODE (operands[7]), GET_MODE (operands[7]), |
dbb138ce HPN |
4549 | replace_equiv_address (XEXP (operands[7], 0), |
4550 | operands[5]));") | |
0b85d816 HPN |
4551 | |
4552 | ;; op(s|u).S1 [rx=rx+i],ry | |
4553 | ||
4554 | (define_split | |
4555 | [(parallel | |
4556 | [(set (match_operand 0 "register_operand" "") | |
4557 | (match_operator | |
4558 | 5 "cris_operand_extend_operator" | |
4559 | [(match_operand 1 "register_operand" "") | |
4560 | (match_operator | |
4561 | 6 "cris_extend_operator" | |
4562 | [(mem | |
4563 | (plus:SI (match_operand:SI 2 "cris_bdap_operand" "") | |
4564 | (match_operand:SI 3 "cris_bdap_operand" "") | |
4565 | ))])])) | |
4566 | (set (match_operand:SI 4 "register_operand" "") | |
4567 | (plus:SI (match_dup 2) | |
4568 | (match_dup 3)))])] | |
4569 | "(rtx_equal_p (operands[4], operands[2]) | |
4570 | || rtx_equal_p (operands[4], operands[3]))" | |
4571 | [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3))) | |
4572 | (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 7)]))] | |
1c563bed | 4573 | "operands[7] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]), |
dbb138ce HPN |
4574 | replace_equiv_address (XEXP (operands[6], 0), |
4575 | operands[4]));") | |
0b85d816 HPN |
4576 | |
4577 | ;; op(s|u).S1 [rx=rx+rz.S2],ry (swapped, plus or bound) | |
4578 | ||
4579 | (define_split | |
4580 | [(parallel | |
4581 | [(set (match_operand 0 "register_operand" "") | |
4582 | (match_operator | |
4583 | 7 "cris_plus_or_bound_operator" | |
4584 | [(match_operator | |
4585 | 6 "cris_extend_operator" | |
4586 | [(mem (plus:SI | |
4587 | (mult:SI (match_operand:SI 2 "register_operand" "") | |
4588 | (match_operand:SI 3 "const_int_operand" "")) | |
4589 | (match_operand:SI 4 "register_operand" "")))]) | |
4590 | (match_operand 1 "register_operand" "")])) | |
4591 | (set (match_operand:SI 5 "register_operand" "") | |
4592 | (plus:SI (mult:SI (match_dup 2) | |
4593 | (match_dup 3)) | |
4594 | (match_dup 4)))])] | |
4595 | "REG_P (operands[4]) && REG_P (operands[5]) | |
4596 | && REGNO (operands[5]) == REGNO (operands[4])" | |
4597 | [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3)) | |
4598 | (match_dup 4))) | |
4599 | (set (match_dup 0) (match_op_dup 6 [(match_dup 8) (match_dup 1)]))] | |
1c563bed | 4600 | "operands[8] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]), |
dbb138ce HPN |
4601 | replace_equiv_address (XEXP (operands[6], 0), |
4602 | operands[5]));") | |
0b85d816 HPN |
4603 | |
4604 | ;; op(s|u).S1 [rx=rx+i],ry (swapped, plus or bound) | |
4605 | ||
4606 | (define_split | |
4607 | [(parallel | |
4608 | [(set (match_operand 0 "register_operand" "") | |
4609 | (match_operator | |
4610 | 6 "cris_plus_or_bound_operator" | |
4611 | [(match_operator | |
4612 | 5 "cris_extend_operator" | |
4613 | [(mem (plus:SI | |
4614 | (match_operand:SI 2 "cris_bdap_operand" "") | |
4615 | (match_operand:SI 3 "cris_bdap_operand" "")))]) | |
4616 | (match_operand 1 "register_operand" "")])) | |
4617 | (set (match_operand:SI 4 "register_operand" "") | |
4618 | (plus:SI (match_dup 2) | |
4619 | (match_dup 3)))])] | |
4620 | "(rtx_equal_p (operands[4], operands[2]) | |
4621 | || rtx_equal_p (operands[4], operands[3]))" | |
4622 | [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3))) | |
4623 | (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))] | |
1c563bed | 4624 | "operands[7] = gen_rtx_fmt_e (GET_CODE (operands[5]), GET_MODE (operands[5]), |
dbb138ce HPN |
4625 | replace_equiv_address (XEXP (operands[5], 0), |
4626 | operands[4]));") | |
0b85d816 HPN |
4627 | \f |
4628 | ;; Splits for addressing prefixes that have no side-effects, so we can | |
4629 | ;; fill a delay slot. Never split if we lose something, though. | |
4630 | ||
4631 | ;; If we have a | |
4632 | ;; move [indirect_ref],rx | |
4633 | ;; where indirect ref = {const, [r+], [r]}, it costs as much as | |
4634 | ;; move indirect_ref,rx | |
4635 | ;; move [rx],rx | |
4636 | ;; Take care not to allow indirect_ref = register. | |
4637 | ||
4638 | ;; We're not allowed to generate copies of registers with different mode | |
4639 | ;; until after reload; copying pseudos upsets reload. CVS as of | |
4640 | ;; 2001-08-24, unwind-dw2-fde.c, _Unwind_Find_FDE ICE in | |
4641 | ;; cselib_invalidate_regno. | |
4642 | ||
4643 | (define_split | |
4644 | [(set (match_operand 0 "register_operand" "") | |
4645 | (match_operand 1 "indirect_operand" ""))] | |
4646 | "reload_completed | |
4647 | && REG_P (operands[0]) | |
4648 | && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD | |
4649 | && (GET_CODE (XEXP (operands[1], 0)) == MEM | |
4650 | || CONSTANT_P (XEXP (operands[1], 0)))" | |
4651 | [(set (match_dup 2) (match_dup 4)) | |
4652 | (set (match_dup 0) (match_dup 3))] | |
4653 | "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0])); | |
dbb138ce | 4654 | operands[3] = replace_equiv_address (operands[1], operands[2]); |
0b85d816 HPN |
4655 | operands[4] = XEXP (operands[1], 0);") |
4656 | ||
4657 | ;; As the above, but MOVS and MOVU. | |
4658 | ||
4659 | (define_split | |
4660 | [(set (match_operand 0 "register_operand" "") | |
4661 | (match_operator | |
4662 | 4 "cris_extend_operator" | |
4663 | [(match_operand 1 "indirect_operand" "")]))] | |
4664 | "reload_completed | |
4665 | && REG_P (operands[0]) | |
4666 | && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD | |
4667 | && (GET_CODE (XEXP (operands[1], 0)) == MEM | |
4668 | || CONSTANT_P (XEXP (operands[1], 0)))" | |
4669 | [(set (match_dup 2) (match_dup 5)) | |
4670 | (set (match_dup 0) (match_op_dup 4 [(match_dup 3)]))] | |
4671 | "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0])); | |
dbb138ce | 4672 | operands[3] = replace_equiv_address (XEXP (operands[4], 0), operands[2]); |
0b85d816 HPN |
4673 | operands[5] = XEXP (operands[1], 0);") |
4674 | \f | |
4675 | ;; Various peephole optimizations. | |
4676 | ;; | |
4677 | ;; Watch out: when you exchange one set of instructions for another, the | |
4678 | ;; condition codes setting must be the same, or you have to CC_INIT or | |
4679 | ;; whatever is appropriate, in the pattern before you emit the | |
4680 | ;; assembly text. This is best done here, not in cris_notice_update_cc, | |
4681 | ;; to keep changes local to their cause. | |
4682 | ;; | |
4683 | ;; Do not add patterns that you do not know will be matched. | |
109b748d | 4684 | ;; Please also add a self-contained testcase. |
0b85d816 HPN |
4685 | |
4686 | ;; We have trouble with and:s and shifts. Maybe something is broken in | |
43a88a8c | 4687 | ;; gcc? Or it could just be that bit-field insn expansion is a bit |
0b85d816 HPN |
4688 | ;; suboptimal when not having extzv insns. |
4689 | ||
4690 | (define_peephole | |
4691 | [(set (match_operand 0 "register_operand" "=r") | |
4692 | (ashiftrt:SI (match_dup 0) | |
4693 | (match_operand:SI 1 "const_int_operand" "n"))) | |
4694 | (set (match_dup 0) | |
4695 | (and:SI (match_dup 0) | |
4696 | (match_operand 2 "const_int_operand" "n")))] | |
4697 | "INTVAL (operands[2]) > 31 | |
4698 | && INTVAL (operands[2]) < 255 | |
4699 | && INTVAL (operands[1]) > 23" | |
4700 | ||
4701 | ;; The m flag should be ignored, because this will be a *byte* "and" | |
4702 | ;; operation. | |
4703 | ||
4704 | "* | |
4705 | { | |
4706 | cc_status.flags |= CC_NOT_NEGATIVE; | |
4707 | ||
4708 | return \"lsrq %1,%0\;and.b %2,%0\"; | |
4709 | }") | |
4710 | ||
4711 | (define_peephole | |
4712 | [(set (match_operand 0 "register_operand" "=r") | |
4713 | (ashiftrt:SI (match_dup 0) | |
4714 | (match_operand:SI 1 "const_int_operand" "n"))) | |
4715 | (set (match_dup 0) | |
4716 | (and:SI (match_dup 0) | |
4717 | (match_operand 2 "const_int_operand" "n")))] | |
4718 | "INTVAL (operands[2]) > 31 | |
4719 | && INTVAL (operands[2]) < 65535 | |
4720 | && INTVAL (operands[2]) != 255 | |
4721 | && INTVAL (operands[1]) > 15" | |
4722 | ||
4723 | ;; The m flag should be ignored, because this will be a *word* "and" | |
4724 | ;; operation. | |
4725 | ||
4726 | "* | |
4727 | { | |
4728 | cc_status.flags |= CC_NOT_NEGATIVE; | |
4729 | ||
4730 | return \"lsrq %1,%0\;and.w %2,%0\"; | |
4731 | }") | |
4732 | ||
4733 | (define_peephole | |
4734 | [(set (match_operand 0 "register_operand" "=r") | |
4735 | (lshiftrt:SI (match_dup 0) | |
4736 | (match_operand:SI 1 "const_int_operand" "n"))) | |
4737 | (set (match_dup 0) | |
4738 | (and:SI (match_dup 0) | |
4739 | (match_operand 2 "const_int_operand" "n")))] | |
4740 | "INTVAL (operands[2]) > 31 | |
4741 | && INTVAL (operands[2]) < 255 | |
4742 | && INTVAL (operands[1]) > 23" | |
4743 | ||
4744 | ;; The m flag should be ignored, because this will be a *byte* "and" | |
4745 | ;; operation. | |
4746 | ||
4747 | "* | |
4748 | { | |
4749 | cc_status.flags |= CC_NOT_NEGATIVE; | |
4750 | ||
4751 | return \"lsrq %1,%0\;and.b %2,%0\"; | |
4752 | }") | |
4753 | ||
4754 | (define_peephole | |
4755 | [(set (match_operand 0 "register_operand" "=r") | |
4756 | (lshiftrt:SI (match_dup 0) | |
4757 | (match_operand:SI 1 "const_int_operand" "n"))) | |
4758 | (set (match_dup 0) | |
4759 | (and:SI (match_dup 0) | |
4760 | (match_operand 2 "const_int_operand" "n")))] | |
4761 | "INTVAL (operands[2]) > 31 && INTVAL (operands[2]) < 65535 | |
4762 | && INTVAL (operands[2]) != 255 | |
4763 | && INTVAL (operands[1]) > 15" | |
4764 | ||
4765 | ;; The m flag should be ignored, because this will be a *word* "and" | |
4766 | ;; operation. | |
4767 | ||
4768 | "* | |
4769 | { | |
4770 | cc_status.flags |= CC_NOT_NEGATIVE; | |
4771 | ||
4772 | return \"lsrq %1,%0\;and.w %2,%0\"; | |
4773 | }") | |
4774 | \f | |
4775 | ||
4776 | ;; Change | |
4777 | ;; add.d n,rx | |
4778 | ;; move [rx],ry | |
4779 | ;; into | |
4780 | ;; move [rx=rx+n],ry | |
4781 | ;; when -128 <= n <= 127. | |
4782 | ;; This will reduce the size of the assembler code for n = [-128..127], | |
4783 | ;; and speed up accordingly. | |
4784 | ||
4785 | (define_peephole | |
4786 | [(set (match_operand:SI 0 "register_operand" "=r") | |
4787 | (plus:SI (match_operand:SI 1 "register_operand" "0") | |
4788 | (match_operand:SI 2 "const_int_operand" "n"))) | |
4789 | (set (match_operand 3 "register_operand" "=r") | |
4790 | (mem (match_dup 0)))] | |
4791 | "GET_MODE (operands[3]) != DImode | |
4792 | && REGNO (operands[3]) != REGNO (operands[0]) | |
4793 | && (BASE_P (operands[1]) || BASE_P (operands[2])) | |
4794 | && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J') | |
4795 | && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N') | |
4796 | && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128)" | |
4797 | "move.%s3 [%0=%1%S2],%3") | |
4798 | ||
4799 | ;; Vice versa: move ry,[rx=rx+n] | |
4800 | ||
4801 | (define_peephole | |
4802 | [(set (match_operand:SI 0 "register_operand" "=r") | |
4803 | (plus:SI (match_operand:SI 1 "register_operand" "0") | |
4804 | (match_operand:SI 2 "const_int_operand" "n"))) | |
4805 | (set (mem (match_dup 0)) | |
4806 | (match_operand 3 "register_operand" "=r"))] | |
4807 | "GET_MODE (operands[3]) != DImode | |
4808 | && REGNO (operands[3]) != REGNO (operands[0]) | |
4809 | && (BASE_P (operands[1]) || BASE_P (operands[2])) | |
4810 | && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J') | |
4811 | && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N') | |
4812 | && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128)" | |
4813 | "move.%s3 %3,[%0=%1%S2]" | |
4814 | [(set_attr "cc" "none")]) | |
4815 | \f | |
4816 | ;; As above, change: | |
4817 | ;; add.d n,rx | |
4818 | ;; op.d [rx],ry | |
4819 | ;; into: | |
4820 | ;; op.d [rx=rx+n],ry | |
4821 | ;; Saves when n = [-128..127]. | |
4822 | ;; | |
4823 | ;; Splitting and joining combinations for side-effect modes are slightly | |
4824 | ;; out of hand. They probably will not save the time they take typing in, | |
4825 | ;; not to mention the bugs that creep in. FIXME: Get rid of as many of | |
4826 | ;; the splits and peepholes as possible. | |
4827 | ||
4828 | (define_peephole | |
4829 | [(set (match_operand:SI 0 "register_operand" "=r") | |
4830 | (plus:SI (match_operand:SI 1 "register_operand" "0") | |
4831 | (match_operand:SI 2 "const_int_operand" "n"))) | |
4832 | (set (match_operand 3 "register_operand" "=r") | |
4833 | (match_operator 4 "cris_orthogonal_operator" | |
4834 | [(match_dup 3) | |
4835 | (mem (match_dup 0))]))] | |
4836 | "GET_MODE (operands[3]) != DImode | |
4837 | && REGNO (operands[0]) != REGNO (operands[3]) | |
4838 | && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J') | |
4839 | && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N') | |
4840 | && INTVAL (operands[2]) >= -128 | |
4841 | && INTVAL (operands[2]) <= 127" | |
4842 | "%x4.%s3 [%0=%1%S2],%3") | |
4843 | ||
4844 | ;; Sometimes, for some reason the pattern | |
4845 | ;; move x,rx | |
4846 | ;; add y,rx | |
4847 | ;; move [rx],rz | |
4848 | ;; will occur. Solve this, and likewise for to-memory. | |
4849 | ||
4850 | (define_peephole | |
4851 | [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") | |
747a0d9d | 4852 | (match_operand:SI 1 "cris_bdap_biap_operand" "r,>Rn,r,>Rn")) |
0b85d816 | 4853 | (set (match_dup 0) |
747a0d9d HPN |
4854 | (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "0,0,r>Rn,r") |
4855 | (match_operand:SI 3 "cris_bdap_biap_operand" "r>Rn,r,0,0"))) | |
0b85d816 HPN |
4856 | (set (match_operand 4 "register_operand" "=r,r,r,r") |
4857 | (mem (match_dup 0)))] | |
4858 | "(rtx_equal_p (operands[2], operands[0]) | |
4859 | || rtx_equal_p (operands[3], operands[0])) | |
4860 | && cris_side_effect_mode_ok (PLUS, operands, 0, | |
4861 | (REG_S_P (operands[1]) | |
4862 | ? 1 | |
4863 | : (rtx_equal_p (operands[2], operands[0]) | |
4864 | ? 3 : 2)), | |
4865 | (! REG_S_P (operands[1]) | |
4866 | ? 1 | |
4867 | : (rtx_equal_p (operands[2], operands[0]) | |
4868 | ? 3 : 2)), | |
4869 | -1, 4)" | |
4870 | "@ | |
4871 | move.%s4 [%0=%1%S3],%4 | |
4872 | move.%s4 [%0=%3%S1],%4 | |
4873 | move.%s4 [%0=%1%S2],%4 | |
4874 | move.%s4 [%0=%2%S1],%4") | |
4875 | ||
4876 | ;; As above but to memory. | |
4877 | ||
4878 | (define_peephole | |
4879 | [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") | |
747a0d9d | 4880 | (match_operand:SI 1 "cris_bdap_biap_operand" "r,>Rn,r,>Rn")) |
0b85d816 | 4881 | (set (match_dup 0) |
747a0d9d HPN |
4882 | (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "0,0,r>Rn,r") |
4883 | (match_operand:SI 3 "cris_bdap_biap_operand" "r>Rn,r,0,0"))) | |
0b85d816 HPN |
4884 | (set (mem (match_dup 0)) |
4885 | (match_operand 4 "register_operand" "=r,r,r,r"))] | |
4886 | "(rtx_equal_p (operands[2], operands[0]) | |
4887 | || rtx_equal_p (operands[3], operands[0])) | |
4888 | && cris_side_effect_mode_ok (PLUS, operands, 0, | |
4889 | (REG_S_P (operands[1]) | |
4890 | ? 1 | |
4891 | : (rtx_equal_p (operands[2], operands[0]) | |
4892 | ? 3 : 2)), | |
4893 | (! REG_S_P (operands[1]) | |
4894 | ? 1 | |
4895 | : (rtx_equal_p (operands[2], operands[0]) | |
4896 | ? 3 : 2)), | |
4897 | -1, 4)" | |
4898 | "@ | |
4899 | move.%s4 %4,[%0=%1%S3] | |
4900 | move.%s4 %4,[%0=%3%S1] | |
4901 | move.%s4 %4,[%0=%1%S2] | |
4902 | move.%s4 %4,[%0=%2%S1]" | |
4903 | [(set_attr "cc" "none")]) | |
4904 | ||
4905 | ||
4906 | ;; As the move from-memory above, but with an operation. | |
4907 | ||
4908 | (define_peephole | |
4909 | [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") | |
747a0d9d | 4910 | (match_operand:SI 1 "cris_bdap_biap_operand" "r,>Rn,r,>Rn")) |
0b85d816 | 4911 | (set (match_dup 0) |
747a0d9d HPN |
4912 | (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "0,0,r>Rn,r") |
4913 | (match_operand:SI 3 "cris_bdap_biap_operand" "r>Rn,r,0,0"))) | |
0b85d816 HPN |
4914 | (set (match_operand 4 "register_operand" "=r,r,r,r") |
4915 | (match_operator 5 "cris_orthogonal_operator" | |
4916 | [(match_dup 3) | |
4917 | (mem (match_dup 0))]))] | |
4918 | "(rtx_equal_p (operands[2], operands[0]) | |
4919 | || rtx_equal_p (operands[3], operands[0])) | |
4920 | && cris_side_effect_mode_ok (PLUS, operands, 0, | |
4921 | (REG_S_P (operands[1]) | |
4922 | ? 1 | |
4923 | : (rtx_equal_p (operands[2], operands[0]) | |
4924 | ? 3 : 2)), | |
4925 | (! REG_S_P (operands[1]) | |
4926 | ? 1 | |
4927 | : (rtx_equal_p (operands[2], operands[0]) | |
4928 | ? 3 : 2)), | |
4929 | -1, 4)" | |
4930 | "@ | |
4931 | %x5.%s4 [%0=%1%S3],%4 | |
4932 | %x5.%s4 [%0=%3%S1],%4 | |
4933 | %x5.%s4 [%0=%1%S2],%4 | |
4934 | %x5.%s4 [%0=%2%S1],%4") | |
4935 | ||
4936 | ;; Same, but with swapped operands (and commutative operation). | |
4937 | ||
4938 | (define_peephole | |
4939 | [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") | |
747a0d9d | 4940 | (match_operand:SI 1 "cris_bdap_biap_operand" "r,>Rn,r,>Rn")) |
0b85d816 | 4941 | (set (match_dup 0) |
747a0d9d HPN |
4942 | (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "0,0,r>Rn,r") |
4943 | (match_operand:SI 3 "cris_bdap_biap_operand" "r>Rn,r,0,0"))) | |
0b85d816 HPN |
4944 | (set (match_operand 4 "register_operand" "=r,r,r,r") |
4945 | (match_operator 5 "cris_commutative_orth_op" | |
4946 | [(mem (match_dup 0)) | |
4947 | (match_dup 3)]))] | |
4948 | "(rtx_equal_p (operands[2], operands[0]) | |
4949 | || rtx_equal_p (operands[3], operands[0])) | |
4950 | && cris_side_effect_mode_ok (PLUS, operands, 0, | |
4951 | (REG_S_P (operands[1]) | |
4952 | ? 1 | |
4953 | : (rtx_equal_p (operands[2], operands[0]) | |
4954 | ? 3 : 2)), | |
4955 | (! REG_S_P (operands[1]) | |
4956 | ? 1 | |
4957 | : (rtx_equal_p (operands[2], operands[0]) | |
4958 | ? 3 : 2)), | |
4959 | -1, 4)" | |
4960 | "@ | |
4961 | %x5.%s4 [%0=%1%S3],%4 | |
4962 | %x5.%s4 [%0=%3%S1],%4 | |
4963 | %x5.%s4 [%0=%1%S2],%4 | |
4964 | %x5.%s4 [%0=%2%S1],%4") | |
4965 | ||
4966 | ;; Another spotted bad code: | |
4967 | ;; move rx,ry | |
4968 | ;; move [ry],ry | |
4969 | ||
4970 | (define_peephole | |
4971 | [(set (match_operand:SI 0 "register_operand" "=r") | |
4972 | (match_operand:SI 1 "register_operand" "r")) | |
4973 | (set (match_operand 2 "register_operand" "=r") | |
4974 | (mem (match_dup 0)))] | |
4975 | "REGNO (operands[0]) == REGNO (operands[2]) | |
4976 | && GET_MODE_SIZE (GET_MODE (operands[2])) <= UNITS_PER_WORD" | |
4977 | "move.%s2 [%1],%0" | |
4978 | [(set_attr "slottable" "yes")]) | |
4979 | ||
4980 | ;; And a simple variant with extended operand. | |
4981 | ||
4982 | (define_peephole | |
4983 | [(set (match_operand:SI 0 "register_operand" "=r") | |
4984 | (match_operand:SI 1 "register_operand" "r")) | |
4985 | (set (match_operand 2 "register_operand" "=r") | |
4986 | (match_operator 3 "cris_extend_operator" [(mem (match_dup 0))]))] | |
4987 | "REGNO (operands[0]) == REGNO (operands[2]) | |
4988 | && GET_MODE_SIZE (GET_MODE (operands[2])) <= UNITS_PER_WORD" | |
4989 | "mov%e3.%m3 [%1],%0" | |
4990 | [(set_attr "slottable" "yes")]) | |
4991 | \f | |
4992 | ;; Here are all peepholes that have a saved testcase. | |
4993 | ;; Do not add new peepholes without testcases. | |
4994 | ||
4995 | ;; peep-1: | |
4996 | ;; move.d [r10+16],r9 | |
4997 | ;; and.d r12,r9 | |
4998 | ;; change to | |
4999 | ;; and.d [r10+16],r12,r9 | |
5000 | ;; With generalization of the operation, the size and the addressing mode. | |
5001 | ;; This seems to be the result of a quirk in register allocation | |
5002 | ;; missing the three-operand cases when having different predicates. | |
5003 | ;; Maybe that it matters that it is a commutative operation. | |
5004 | ;; This pattern helps that situation, but there's still the increased | |
5005 | ;; register pressure. | |
5006 | ;; Note that adding the noncommutative variant did not show any matches | |
5007 | ;; in ipps and cc1, so it's not here. | |
5008 | ||
5009 | (define_peephole | |
5010 | [(set (match_operand 0 "register_operand" "=r,r,r,r") | |
5011 | (mem (plus:SI | |
747a0d9d HPN |
5012 | (match_operand:SI 1 "cris_bdap_biap_operand" "r,r>Rn,r,r>Rn") |
5013 | (match_operand:SI 2 "cris_bdap_biap_operand" "r>Rn,r,r>Rn,r")))) | |
0b85d816 HPN |
5014 | (set (match_dup 0) |
5015 | (match_operator 5 "cris_commutative_orth_op" | |
5016 | [(match_operand 3 "register_operand" "0,0,r,r") | |
5017 | (match_operand 4 "register_operand" "r,r,0,0")]))] | |
5018 | "(rtx_equal_p (operands[3], operands[0]) | |
5019 | || rtx_equal_p (operands[4], operands[0])) | |
5020 | && ! rtx_equal_p (operands[3], operands[4]) | |
5021 | && (REG_S_P (operands[1]) || REG_S_P (operands[2])) | |
5022 | && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD" | |
5023 | "@ | |
5024 | %x5.%s0 [%1%S2],%4,%0 | |
5025 | %x5.%s0 [%2%S1],%4,%0 | |
5026 | %x5.%s0 [%1%S2],%3,%0 | |
5027 | %x5.%s0 [%2%S1],%3,%0") | |
5028 | ||
5029 | ;; peep-2: | |
5030 | ;; I cannot tell GCC (2.1, 2.7.2) how to correctly reload an instruction | |
5031 | ;; that looks like | |
5032 | ;; and.b some_byte,const,reg_32 | |
5033 | ;; where reg_32 is the destination of the "three-address" code optimally. | |
5034 | ;; It should be: | |
5035 | ;; movu.b some_byte,reg_32 | |
5036 | ;; and.b const,reg_32 | |
5037 | ;; but is turns into: | |
5038 | ;; move.b some_byte,reg_32 | |
5039 | ;; and.d const,reg_32 | |
5040 | ;; Fix it here. | |
5041 | ||
5042 | (define_peephole | |
5043 | [(set (match_operand:SI 0 "register_operand" "=r") | |
5044 | (match_operand:SI 1 "nonimmediate_operand" "rm")) | |
5045 | (set (match_operand:SI 2 "register_operand" "=0") | |
5046 | (and:SI (match_dup 0) | |
5047 | (match_operand:SI 3 "const_int_operand" "n")))] | |
5048 | ||
5049 | ;; Since the size of the memory access could be made different here, | |
5050 | ;; don't do this for a mem-volatile access. | |
5051 | ||
5052 | "REGNO (operands[2]) == REGNO (operands[0]) | |
5053 | && INTVAL (operands[3]) <= 65535 && INTVAL (operands[3]) >= 0 | |
5054 | && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'I') | |
5055 | && (GET_CODE (operands[1]) != MEM || ! MEM_VOLATILE_P (operands[1]))" | |
5056 | "* | |
5057 | { | |
5058 | if (CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'O')) | |
5059 | return \"movu.%z3 %1,%0\;andq %b3,%0\"; | |
5060 | ||
5061 | cc_status.flags |= CC_NOT_NEGATIVE; | |
5062 | ||
5063 | return \"movu.%z3 %1,%0\;and.%z3 %3,%0\"; | |
5064 | }") | |
5065 | ||
5066 | ;; peep-3 | |
5067 | ||
5068 | (define_peephole | |
5069 | [(set (match_operand 0 "register_operand" "=r") | |
5070 | (match_operand 1 "nonimmediate_operand" "rm")) | |
5071 | (set (match_operand:SI 2 "register_operand" "=r") | |
5072 | (and:SI (subreg:SI (match_dup 0) 0) | |
5073 | (match_operand 3 "const_int_operand" "n")))] | |
5074 | ||
5075 | ;; Since the size of the memory access could be made different here, | |
5076 | ;; don't do this for a mem-volatile access. | |
5077 | ||
5078 | "REGNO (operands[0]) == REGNO (operands[2]) | |
5079 | && INTVAL (operands[3]) > 0 | |
5080 | && INTVAL (operands[3]) <= 65535 | |
5081 | && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'I') | |
5082 | && (GET_CODE (operands[1]) != MEM || ! MEM_VOLATILE_P (operands[1]))" | |
5083 | "* | |
5084 | { | |
5085 | if (CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'O')) | |
5086 | return \"movu.%z3 %1,%0\;andq %b3,%0\"; | |
5087 | ||
5088 | cc_status.flags |= CC_NOT_NEGATIVE; | |
5089 | ||
5090 | return \"movu.%z3 %1,%0\;and.%z3 %3,%0\"; | |
5091 | }") | |
5092 | \f | |
5093 | ;; Local variables: | |
5094 | ;; mode:emacs-lisp | |
5095 | ;; comment-start: ";; " | |
5096 | ;; eval: (set-syntax-table (copy-sequence (syntax-table))) | |
5097 | ;; eval: (modify-syntax-entry ?[ "(]") | |
5098 | ;; eval: (modify-syntax-entry ?] ")[") | |
5099 | ;; eval: (modify-syntax-entry ?{ "(}") | |
5100 | ;; eval: (modify-syntax-entry ?} "){") | |
5101 | ;; eval: (setq indent-tabs-mode t) | |
5102 | ;; End: |