[thirdparty/gcc.git] / gcc / config / crx / crx.h

/* Definitions of target machine for GNU compiler, for CRX.
   Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
   2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
   Free Software Foundation, Inc.

   This file is part of GCC.

   GCC is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published
   by the Free Software Foundation; either version 3, or (at your
   option) any later version.

   GCC is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with GCC; see the file COPYING3.  If not see
   <http://www.gnu.org/licenses/>.  */

#ifndef GCC_CRX_H
#define GCC_CRX_H

/*****************************************************************************/
/* CONTROLLING THE DRIVER						     */
/*****************************************************************************/

#define CC1PLUS_SPEC "%{!frtti:-fno-rtti} \
    %{!fenforce-eh-specs:-fno-enforce-eh-specs} \
    %{!fexceptions:-fno-exceptions} \
    %{!fthreadsafe-statics:-fno-threadsafe-statics}"

#undef  STARTFILE_SPEC
#define STARTFILE_SPEC "crti.o%s crtbegin.o%s"

#undef  ENDFILE_SPEC
#define ENDFILE_SPEC "crtend.o%s crtn.o%s"

#undef MATH_LIBRARY
#define MATH_LIBRARY ""

/*****************************************************************************/
/* RUN-TIME TARGET SPECIFICATION					     */
/*****************************************************************************/

#ifndef TARGET_CPU_CPP_BUILTINS
#define TARGET_CPU_CPP_BUILTINS()				\
do {								\
     builtin_define("__CRX__");					\
     builtin_define("__CR__");		  			\
} while (0)
#endif

#define TARGET_VERSION fputs (" (CRX/ELF)", stderr);

/*****************************************************************************/
/* STORAGE LAYOUT							     */
/*****************************************************************************/

#define BITS_BIG_ENDIAN  0

#define BYTES_BIG_ENDIAN 0

#define WORDS_BIG_ENDIAN 0

#define UNITS_PER_WORD 4

#define POINTER_SIZE 32

#define PARM_BOUNDARY 32

#define STACK_BOUNDARY 32

#define FUNCTION_BOUNDARY 32

#define STRUCTURE_SIZE_BOUNDARY 32

#define BIGGEST_ALIGNMENT 32

/* In CRX arrays of chars are word-aligned, so strcpy() will be faster.  */
#define DATA_ALIGNMENT(TYPE, ALIGN) \
  (TREE_CODE (TYPE) == ARRAY_TYPE && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
   && (ALIGN) < BITS_PER_WORD \
   ? (BITS_PER_WORD) : (ALIGN))

/* In CRX strings are word-aligned so strcpy from constants will be faster. */
#define CONSTANT_ALIGNMENT(CONSTANT, ALIGN) \
  (TREE_CODE (CONSTANT) == STRING_CST && (ALIGN) < BITS_PER_WORD \
   ? (BITS_PER_WORD) : (ALIGN))

#define STRICT_ALIGNMENT 0

#define PCC_BITFIELD_TYPE_MATTERS 1

/*****************************************************************************/
/* LAYOUT OF SOURCE LANGUAGE DATA TYPES					     */
/*****************************************************************************/

#define INT_TYPE_SIZE		32

#define SHORT_TYPE_SIZE		16

#define LONG_TYPE_SIZE		32

#define LONG_LONG_TYPE_SIZE	64

#define FLOAT_TYPE_SIZE 	32

#define DOUBLE_TYPE_SIZE 	64

#define LONG_DOUBLE_TYPE_SIZE   64

#define DEFAULT_SIGNED_CHAR	1

#define SIZE_TYPE		"unsigned int"

#define PTRDIFF_TYPE		"int"

/*****************************************************************************/
/* REGISTER USAGE.							     */
/*****************************************************************************/

#define FIRST_PSEUDO_REGISTER	19

/* On the CRX, only the stack pointer (r15) is such. */
#define FIXED_REGISTERS \
  { \
 /* r0  r1  r2  r3  r4  r5  r6  r7  r8  r9  r10 */  \
    0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,	    \
 /* r11 r12 r13 ra  sp  r16 r17 cc */		    \
    0,  0,  0,  0,  1,  0,  0,  1		    \
  }

/* On the CRX, calls clobbers r0-r6 (scratch registers), ra (the return address)
 * and sp - (the stack pointer which is fixed). */
#define CALL_USED_REGISTERS \
  { \
 /* r0  r1  r2  r3  r4  r5  r6  r7  r8  r9  r10 */  \
    1,  1,  1,  1,  1,  1,  1,  0,  0,  0,  0,	    \
 /* r11 r12 r13 ra  sp  r16 r17 cc */		    \
    0,  0,  0,  1,  1,  1,  1,  1		    \
  }

#define HARD_REGNO_NREGS(REGNO, MODE) \
    ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)

/* On the CRX architecture, HILO regs can only hold SI mode. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) crx_hard_regno_mode_ok(REGNO, MODE)

/* So far no patterns for moving CCMODE data are available */
#define AVOID_CCMODE_COPIES

/* Interrupt functions can only use registers that have already been saved by
 * the prologue, even if they would normally be call-clobbered. */
#define HARD_REGNO_RENAME_OK(SRC, DEST)	\
  (!crx_interrupt_function_p () || df_regs_ever_live_p (DEST))

#define MODES_TIEABLE_P(MODE1, MODE2)  1

enum reg_class
{
  NO_REGS,
  LO_REGS,
  HI_REGS,
  HILO_REGS,
  NOSP_REGS,
  GENERAL_REGS,
  ALL_REGS,
  LIM_REG_CLASSES
};

#define N_REG_CLASSES (int) LIM_REG_CLASSES

/* The following macro defines cover classes for Integrated Register
   Allocator.  Cover classes is a set of non-intersected register
   classes covering all hard registers used for register allocation
   purpose.  Any move between two registers of a cover class should be
   cheaper than load or store of the registers.  The macro value is
   array of register classes with LIM_REG_CLASSES used as the end
   marker.  */

#define IRA_COVER_CLASSES         \
{                                 \
   GENERAL_REGS, LIM_REG_CLASSES  \
} 

#define REG_CLASS_NAMES \
  {			\
    "NO_REGS",		\
    "LO_REGS",		\
    "HI_REGS",		\
    "HILO_REGS",	\
    "NOSP_REGS",	\
    "GENERAL_REGS",	\
    "ALL_REGS"		\
  }

#define REG_CLASS_CONTENTS				\
  {							\
    {0x00000000}, /* NO_REGS			*/	\
    {0x00010000}, /* LO_REGS :		16 	*/	\
    {0x00020000}, /* HI_REGS :		17	*/	\
    {0x00030000}, /* HILO_REGS :	16, 17	*/	\
    {0x00007fff}, /* NOSP_REGS : 	0 - 14	*/	\
    {0x0000ffff}, /* GENERAL_REGS : 	0 - 15	*/	\
    {0x0007ffff}  /* ALL_REGS : 	0 - 18	*/	\
  }

#define REGNO_REG_CLASS(REGNO)  crx_regno_reg_class(REGNO)

#define BASE_REG_CLASS		GENERAL_REGS

#define INDEX_REG_CLASS		GENERAL_REGS

#define REG_CLASS_FROM_LETTER(C)	\
  ((C) == 'b' ? NOSP_REGS :		\
   (C) == 'l' ? LO_REGS : 		\
   (C) == 'h' ? HI_REGS :		\
   (C) == 'k' ? HILO_REGS :		\
  NO_REGS)

#define REGNO_OK_FOR_BASE_P(REGNO) \
  ((REGNO) < 16 \
   || (reg_renumber && (unsigned)reg_renumber[REGNO] < 16))

#define REGNO_OK_FOR_INDEX_P(REGNO)	   REGNO_OK_FOR_BASE_P(REGNO)

#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
  crx_secondary_reload_class (CLASS, MODE, X)

#define CLASS_MAX_NREGS(CLASS, MODE) \
    (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD

#define SIGNED_INT_FITS_N_BITS(imm, N) \
  ((((imm) < ((long long)1<<((N)-1))) && ((imm) >= -((long long)1<<((N)-1)))) ? 1 : 0)

#define UNSIGNED_INT_FITS_N_BITS(imm, N) \
  (((imm) < ((long long)1<<(N)) && (imm) >= (long long)0) ? 1 : 0)

#define HILO_REGNO_P(regno) \
  (reg_classes_intersect_p(REGNO_REG_CLASS(regno), HILO_REGS))

#define INT_CST4(VALUE) \
  (((VALUE) >= -1 && (VALUE) <= 4) || (VALUE) == -4 \
  || (VALUE) == 7 || (VALUE) == 8 || (VALUE) == 16 || (VALUE) == 32 \
  || (VALUE) == 20 || (VALUE) == 12 || (VALUE) == 48)

#define CONST_OK_FOR_LETTER_P(VALUE, C)				\
  /* Legal const for store immediate instructions */		\
  ((C) == 'I' ? UNSIGNED_INT_FITS_N_BITS(VALUE, 3) :		\
   (C) == 'J' ? UNSIGNED_INT_FITS_N_BITS(VALUE, 4) :		\
   (C) == 'K' ? UNSIGNED_INT_FITS_N_BITS(VALUE, 5) :		\
   (C) == 'L' ? INT_CST4(VALUE) :				\
  0)

#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)	\
  ((C) == 'G' ? crx_const_double_ok (VALUE) :	\
  0)

/*****************************************************************************/
/* STACK LAYOUT AND CALLING CONVENTIONS.				     */
/*****************************************************************************/

#define STACK_GROWS_DOWNWARD

#define STARTING_FRAME_OFFSET  0

#define	STACK_POINTER_REGNUM	15

#define	FRAME_POINTER_REGNUM	13

#define	ARG_POINTER_REGNUM	12

#define STATIC_CHAIN_REGNUM	1

#define	RETURN_ADDRESS_REGNUM	14

#define FIRST_PARM_OFFSET(FNDECL)  0

#define ELIMINABLE_REGS \
  { \
    { ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM}, \
    { ARG_POINTER_REGNUM,   FRAME_POINTER_REGNUM}, \
    { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}  \
  }

#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)			\
  do {									\
    (OFFSET) = crx_initial_elimination_offset ((FROM), (TO));		\
  } while (0)

/*****************************************************************************/
/* PASSING FUNCTION ARGUMENTS						     */
/*****************************************************************************/

#define ACCUMULATE_OUTGOING_ARGS (TARGET_NO_PUSH_ARGS)

#define PUSH_ARGS (!TARGET_NO_PUSH_ARGS)

#define PUSH_ROUNDING(BYTES) (((BYTES) + 3) & ~3)

#ifndef CUMULATIVE_ARGS
struct cumulative_args
{
  int ints;
};

#define CUMULATIVE_ARGS struct cumulative_args
#endif

/* On the CRX architecture, Varargs routines should receive their parameters on
 * the stack.  */

#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
  crx_init_cumulative_args(&(CUM), (FNTYPE), (LIBNAME))

#define FUNCTION_ARG_REGNO_P(REGNO)  crx_function_arg_regno_p(REGNO)

/*****************************************************************************/
/* RETURNING FUNCTION VALUE						     */
/*****************************************************************************/

/* On the CRX, the return value is in R0 */

#define FUNCTION_VALUE(VALTYPE, FUNC) \
	gen_rtx_REG(TYPE_MODE (VALTYPE), 0)

#define LIBCALL_VALUE(MODE)	gen_rtx_REG (MODE, 0)

#define FUNCTION_VALUE_REGNO_P(N)	((N) == 0)

#define CRX_STRUCT_VALUE_REGNUM  0

/*****************************************************************************/
/* GENERATING CODE FOR PROFILING - NOT IMPLEMENTED			     */
/*****************************************************************************/

#undef  FUNCTION_PROFILER
#define FUNCTION_PROFILER(STREAM, LABELNO)	\
{						\
    sorry ("profiler support for CRX");		\
}
	
/*****************************************************************************/
/* TRAMPOLINES FOR NESTED FUNCTIONS - NOT SUPPORTED      		     */
/*****************************************************************************/

#define TRAMPOLINE_SIZE	32

/*****************************************************************************/
/* ADDRESSING MODES							     */
/*****************************************************************************/

#define CONSTANT_ADDRESS_P(X)						\
  (GET_CODE (X) == LABEL_REF						\
   || GET_CODE (X) == SYMBOL_REF					\
   || GET_CODE (X) == CONST						\
   || GET_CODE (X) == CONST_INT)

#define MAX_REGS_PER_ADDRESS 2

#define HAVE_POST_INCREMENT  1
#define HAVE_POST_DECREMENT  1
#define HAVE_POST_MODIFY_DISP 1
#define HAVE_POST_MODIFY_REG 0

#ifdef REG_OK_STRICT
#define REG_OK_FOR_BASE_P(X)	REGNO_OK_FOR_BASE_P (REGNO (X))
#define REG_OK_FOR_INDEX_P(X)	REGNO_OK_FOR_INDEX_P (REGNO (X))
#else
#define REG_OK_FOR_BASE_P(X)	1
#define REG_OK_FOR_INDEX_P(X)	1
#endif /* REG_OK_STRICT */

#define LEGITIMATE_CONSTANT_P(X)  1

/*****************************************************************************/
/* CONDITION CODE STATUS						     */
/*****************************************************************************/

/*****************************************************************************/
/* RELATIVE COSTS OF OPERATIONS						     */
/*****************************************************************************/

#define MEMORY_MOVE_COST(MODE, CLASS, IN) crx_memory_move_cost(MODE, CLASS, IN)
/* Moving to processor register flushes pipeline - thus asymmetric */
#define REGISTER_MOVE_COST(MODE, FROM, TO) ((TO != GENERAL_REGS) ? 8 : 2)
/* Assume best case (branch predicted) */
#define BRANCH_COST(speed_p, predictable_p) 2

#define SLOW_BYTE_ACCESS  1

/*****************************************************************************/
/* DIVIDING THE OUTPUT INTO SECTIONS					     */
/*****************************************************************************/

#define TEXT_SECTION_ASM_OP	"\t.section\t.text"

#define DATA_SECTION_ASM_OP	"\t.section\t.data"

#define BSS_SECTION_ASM_OP	"\t.section\t.bss"

/*****************************************************************************/
/* POSITION INDEPENDENT CODE						     */
/*****************************************************************************/

#define PIC_OFFSET_TABLE_REGNUM  12

#define LEGITIMATE_PIC_OPERAND_P(X)  1

/*****************************************************************************/
/* ASSEMBLER FORMAT							     */
/*****************************************************************************/

#define GLOBAL_ASM_OP "\t.globl\t"

#undef	USER_LABEL_PREFIX
#define	USER_LABEL_PREFIX "_"

#undef	ASM_OUTPUT_LABELREF
#define ASM_OUTPUT_LABELREF(STREAM, NAME) \
  asm_fprintf (STREAM, "%U%s", (*targetm.strip_name_encoding) (NAME));

#undef	ASM_APP_ON
#define ASM_APP_ON   "#APP\n"

#undef	ASM_APP_OFF
#define ASM_APP_OFF  "#NO_APP\n"

/*****************************************************************************/
/* INSTRUCTION OUTPUT							     */
/*****************************************************************************/

#define REGISTER_NAMES \
  { \
    "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7", \
    "r8",  "r9",  "r10", "r11", "r12", "r13", "ra",  "sp", \
    "lo",  "hi",  "cc" \
  }

#define PRINT_OPERAND(STREAM, X, CODE) \
  crx_print_operand(STREAM, X, CODE)

#define PRINT_OPERAND_ADDRESS(STREAM, ADDR) \
  crx_print_operand_address(STREAM, ADDR)

/*****************************************************************************/
/* OUTPUT OF DISPATCH TABLES						     */
/*****************************************************************************/

#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
  asm_fprintf ((STREAM), "\t.long\t.L%d\n", (VALUE))

/*****************************************************************************/
/* ALIGNMENT IN ASSEMBLER FILE						     */
/*****************************************************************************/

#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
  asm_fprintf ((STREAM), "\t.align\t%d\n", 1 << (POWER))

/*****************************************************************************/
/* MISCELLANEOUS PARAMETERS						     */
/*****************************************************************************/

#define CASE_VECTOR_MODE  Pmode

#define MOVE_MAX 4

#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC)  1

#define STORE_FLAG_VALUE  1

#define Pmode		SImode

#define FUNCTION_MODE	QImode

#endif /* ! GCC_CRX_H */
Commit	Line	Data
db869733 PW	1	/* Definitions of target machine for GNU compiler, for CRX.
db869733 PW	2	Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
fac0f722	3	2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
66647d44	4	Free Software Foundation, Inc.
db869733 PW	5
	6	This file is part of GCC.
	7
	8	GCC is free software; you can redistribute it and/or modify it
	9	under the terms of the GNU General Public License as published
2f83c7d6	10	by the Free Software Foundation; either version 3, or (at your
db869733 PW	11	option) any later version.
	12
	13	GCC is distributed in the hope that it will be useful, but WITHOUT
	14	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	15	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	16	License for more details.
	17
	18	You should have received a copy of the GNU General Public License
2f83c7d6 NC	19	along with GCC; see the file COPYING3. If not see
2f83c7d6 NC	20	<http://www.gnu.org/licenses/>. */
db869733 PW	21
	22	#ifndef GCC_CRX_H
	23	#define GCC_CRX_H
	24
	25	/*****************************************************************************/
	26	/* CONTROLLING THE DRIVER */
	27	/*****************************************************************************/
	28
	29	#define CC1PLUS_SPEC "%{!frtti:-fno-rtti} \
	30	%{!fenforce-eh-specs:-fno-enforce-eh-specs} \
	31	%{!fexceptions:-fno-exceptions} \
	32	%{!fthreadsafe-statics:-fno-threadsafe-statics}"
	33
	34	#undef STARTFILE_SPEC
	35	#define STARTFILE_SPEC "crti.o%s crtbegin.o%s"
	36
	37	#undef ENDFILE_SPEC
	38	#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
	39
d3f663ff PW	40	#undef MATH_LIBRARY
	41	#define MATH_LIBRARY ""
	42
db869733 PW	43	/*****************************************************************************/
	44	/* RUN-TIME TARGET SPECIFICATION */
	45	/*****************************************************************************/
	46
	47	#ifndef TARGET_CPU_CPP_BUILTINS
	48	#define TARGET_CPU_CPP_BUILTINS() \
	49	do { \
	50	builtin_define("__CRX__"); \
	51	builtin_define("__CR__"); \
	52	} while (0)
	53	#endif
	54
	55	#define TARGET_VERSION fputs (" (CRX/ELF)", stderr);
	56
db869733 PW	57	/*****************************************************************************/
	58	/* STORAGE LAYOUT */
	59	/*****************************************************************************/
	60
	61	#define BITS_BIG_ENDIAN 0
	62
	63	#define BYTES_BIG_ENDIAN 0
	64
	65	#define WORDS_BIG_ENDIAN 0
	66
	67	#define UNITS_PER_WORD 4
	68
	69	#define POINTER_SIZE 32
	70
	71	#define PARM_BOUNDARY 32
	72
	73	#define STACK_BOUNDARY 32
	74
	75	#define FUNCTION_BOUNDARY 32
	76
	77	#define STRUCTURE_SIZE_BOUNDARY 32
	78
	79	#define BIGGEST_ALIGNMENT 32
	80
	81	/* In CRX arrays of chars are word-aligned, so strcpy() will be faster. */
	82	#define DATA_ALIGNMENT(TYPE, ALIGN) \
	83	(TREE_CODE (TYPE) == ARRAY_TYPE && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
	84	&& (ALIGN) < BITS_PER_WORD \
	85	? (BITS_PER_WORD) : (ALIGN))
	86
	87	/* In CRX strings are word-aligned so strcpy from constants will be faster. */
	88	#define CONSTANT_ALIGNMENT(CONSTANT, ALIGN) \
	89	(TREE_CODE (CONSTANT) == STRING_CST && (ALIGN) < BITS_PER_WORD \
	90	? (BITS_PER_WORD) : (ALIGN))
	91
	92	#define STRICT_ALIGNMENT 0
	93
	94	#define PCC_BITFIELD_TYPE_MATTERS 1
	95
	96	/*****************************************************************************/
	97	/* LAYOUT OF SOURCE LANGUAGE DATA TYPES */
	98	/*****************************************************************************/
	99
	100	#define INT_TYPE_SIZE 32
	101
	102	#define SHORT_TYPE_SIZE 16
	103
	104	#define LONG_TYPE_SIZE 32
	105
	106	#define LONG_LONG_TYPE_SIZE 64
	107
	108	#define FLOAT_TYPE_SIZE 32
	109
	110	#define DOUBLE_TYPE_SIZE 64
	111
	112	#define LONG_DOUBLE_TYPE_SIZE 64
	113
	114	#define DEFAULT_SIGNED_CHAR 1
	115
	116	#define SIZE_TYPE "unsigned int"
	117
	118	#define PTRDIFF_TYPE "int"
	119
	120	/*****************************************************************************/
121	/* REGISTER USAGE. */
122	/*****************************************************************************/
123
124	#define FIRST_PSEUDO_REGISTER 19
125
126	/* On the CRX, only the stack pointer (r15) is such. */
127	#define FIXED_REGISTERS \
128	{ \
129	/* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 */ \
130	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
131	/* r11 r12 r13 ra sp r16 r17 cc */ \
132	0, 0, 0, 0, 1, 0, 0, 1 \
133	}
134
135	/* On the CRX, calls clobbers r0-r6 (scratch registers), ra (the return address)
136	* and sp - (the stack pointer which is fixed). */
137	#define CALL_USED_REGISTERS \
138	{ \
139	/* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 */ \
140	1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
141	/* r11 r12 r13 ra sp r16 r17 cc */ \
142	0, 0, 0, 1, 1, 1, 1, 1 \
143	}
144
145	#define HARD_REGNO_NREGS(REGNO, MODE) \
146	((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
147
148	/* On the CRX architecture, HILO regs can only hold SI mode. */
149	#define HARD_REGNO_MODE_OK(REGNO, MODE) crx_hard_regno_mode_ok(REGNO, MODE)
150
151	/* So far no patterns for moving CCMODE data are available */
152	#define AVOID_CCMODE_COPIES
153
154	/* Interrupt functions can only use registers that have already been saved by
155	* the prologue, even if they would normally be call-clobbered. */
156	#define HARD_REGNO_RENAME_OK(SRC, DEST) \
6fb5fa3c	157	(!crx_interrupt_function_p () \|\| df_regs_ever_live_p (DEST))
db869733 PW	158
	159	#define MODES_TIEABLE_P(MODE1, MODE2) 1
	160
	161	enum reg_class
	162	{
	163	NO_REGS,
	164	LO_REGS,
	165	HI_REGS,
	166	HILO_REGS,
	167	NOSP_REGS,
	168	GENERAL_REGS,
	169	ALL_REGS,
	170	LIM_REG_CLASSES
	171	};
	172
	173	#define N_REG_CLASSES (int) LIM_REG_CLASSES
	174
37022b7c SR	175	/* The following macro defines cover classes for Integrated Register
	176	Allocator. Cover classes is a set of non-intersected register
	177	classes covering all hard registers used for register allocation
	178	purpose. Any move between two registers of a cover class should be
	179	cheaper than load or store of the registers. The macro value is
	180	array of register classes with LIM_REG_CLASSES used as the end
	181	marker. */
	182
	183	#define IRA_COVER_CLASSES \
	184	{ \
	185	GENERAL_REGS, LIM_REG_CLASSES \
	186	}
	187
db869733 PW	188	#define REG_CLASS_NAMES \
	189	{ \
	190	"NO_REGS", \
	191	"LO_REGS", \
	192	"HI_REGS", \
	193	"HILO_REGS", \
	194	"NOSP_REGS", \
	195	"GENERAL_REGS", \
	196	"ALL_REGS" \
	197	}
	198
	199	#define REG_CLASS_CONTENTS \
	200	{ \
	201	{0x00000000}, /* NO_REGS */ \
	202	{0x00010000}, /* LO_REGS : 16 */ \
	203	{0x00020000}, /* HI_REGS : 17 */ \
	204	{0x00030000}, /* HILO_REGS : 16, 17 */ \
	205	{0x00007fff}, /* NOSP_REGS : 0 - 14 */ \
	206	{0x0000ffff}, /* GENERAL_REGS : 0 - 15 */ \
	207	{0x0007ffff} /* ALL_REGS : 0 - 18 */ \
	208	}
	209
	210	#define REGNO_REG_CLASS(REGNO) crx_regno_reg_class(REGNO)
	211
	212	#define BASE_REG_CLASS GENERAL_REGS
	213
	214	#define INDEX_REG_CLASS GENERAL_REGS
	215
	216	#define REG_CLASS_FROM_LETTER(C) \
	217	((C) == 'b' ? NOSP_REGS : \
	218	(C) == 'l' ? LO_REGS : \
	219	(C) == 'h' ? HI_REGS : \
	220	(C) == 'k' ? HILO_REGS : \
	221	NO_REGS)
	222
	223	#define REGNO_OK_FOR_BASE_P(REGNO) \
	224	((REGNO) < 16 \
	225	\|\| (reg_renumber && (unsigned)reg_renumber[REGNO] < 16))
	226
	227	#define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
db869733	228
db869733 PW	229	#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
	230	crx_secondary_reload_class (CLASS, MODE, X)
	231
	232	#define CLASS_MAX_NREGS(CLASS, MODE) \
	233	(GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD
	234
	235	#define SIGNED_INT_FITS_N_BITS(imm, N) \
	236	((((imm) < ((long long)1<<((N)-1))) && ((imm) >= -((long long)1<<((N)-1)))) ? 1 : 0)
	237
	238	#define UNSIGNED_INT_FITS_N_BITS(imm, N) \
	239	(((imm) < ((long long)1<<(N)) && (imm) >= (long long)0) ? 1 : 0)
	240
	241	#define HILO_REGNO_P(regno) \
	242	(reg_classes_intersect_p(REGNO_REG_CLASS(regno), HILO_REGS))
	243
	244	#define INT_CST4(VALUE) \
	245	(((VALUE) >= -1 && (VALUE) <= 4) \|\| (VALUE) == -4 \
	246	\|\| (VALUE) == 7 \|\| (VALUE) == 8 \|\| (VALUE) == 16 \|\| (VALUE) == 32 \
	247	\|\| (VALUE) == 20 \|\| (VALUE) == 12 \|\| (VALUE) == 48)
	248
	249	#define CONST_OK_FOR_LETTER_P(VALUE, C) \
	250	/* Legal const for store immediate instructions */ \
	251	((C) == 'I' ? UNSIGNED_INT_FITS_N_BITS(VALUE, 3) : \
	252	(C) == 'J' ? UNSIGNED_INT_FITS_N_BITS(VALUE, 4) : \
	253	(C) == 'K' ? UNSIGNED_INT_FITS_N_BITS(VALUE, 5) : \
	254	(C) == 'L' ? INT_CST4(VALUE) : \
	255	0)
	256
	257	#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
	258	((C) == 'G' ? crx_const_double_ok (VALUE) : \
	259	0)
	260
	261	/*****************************************************************************/
	262	/* STACK LAYOUT AND CALLING CONVENTIONS. */
	263	/*****************************************************************************/
	264
	265	#define STACK_GROWS_DOWNWARD
	266
	267	#define STARTING_FRAME_OFFSET 0
	268
	269	#define STACK_POINTER_REGNUM 15
	270
	271	#define FRAME_POINTER_REGNUM 13
	272
	273	#define ARG_POINTER_REGNUM 12
	274
	275	#define STATIC_CHAIN_REGNUM 1
	276
	277	#define RETURN_ADDRESS_REGNUM 14
	278
	279	#define FIRST_PARM_OFFSET(FNDECL) 0
	280
db869733 PW	281	#define ELIMINABLE_REGS \
	282	{ \
	283	{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
	284	{ ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
	285	{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \
	286	}
	287
db869733 PW	288	#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
	289	do { \
	290	(OFFSET) = crx_initial_elimination_offset ((FROM), (TO)); \
	291	} while (0)
	292
	293	/*****************************************************************************/
	294	/* PASSING FUNCTION ARGUMENTS */
	295	/*****************************************************************************/
	296
	297	#define ACCUMULATE_OUTGOING_ARGS (TARGET_NO_PUSH_ARGS)
	298
	299	#define PUSH_ARGS (!TARGET_NO_PUSH_ARGS)
	300
	301	#define PUSH_ROUNDING(BYTES) (((BYTES) + 3) & ~3)
	302
db869733 PW	303	#ifndef CUMULATIVE_ARGS
	304	struct cumulative_args
	305	{
	306	int ints;
	307	};
	308
	309	#define CUMULATIVE_ARGS struct cumulative_args
	310	#endif
	311
	312	/* On the CRX architecture, Varargs routines should receive their parameters on
	313	* the stack. */
	314
	315	#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
	316	crx_init_cumulative_args(&(CUM), (FNTYPE), (LIBNAME))
	317
e95cfa3b	318	#define FUNCTION_ARG_REGNO_P(REGNO) crx_function_arg_regno_p(REGNO)
db869733 PW	319
	320	/*****************************************************************************/
	321	/* RETURNING FUNCTION VALUE */
	322	/*****************************************************************************/
	323
	324	/* On the CRX, the return value is in R0 */
	325
	326	#define FUNCTION_VALUE(VALTYPE, FUNC) \
	327	gen_rtx_REG(TYPE_MODE (VALTYPE), 0)
	328
	329	#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
	330
	331	#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
	332
	333	#define CRX_STRUCT_VALUE_REGNUM 0
	334
	335	/*****************************************************************************/
	336	/* GENERATING CODE FOR PROFILING - NOT IMPLEMENTED */
	337	/*****************************************************************************/
	338
	339	#undef FUNCTION_PROFILER
	340	#define FUNCTION_PROFILER(STREAM, LABELNO) \
	341	{ \
d8a07487	342	sorry ("profiler support for CRX"); \
db869733 PW	343	}
	344
	345	/*****************************************************************************/
	346	/* TRAMPOLINES FOR NESTED FUNCTIONS - NOT SUPPORTED */
	347	/*****************************************************************************/
	348
	349	#define TRAMPOLINE_SIZE 32
	350
db869733 PW	351	/*****************************************************************************/
	352	/* ADDRESSING MODES */
	353	/*****************************************************************************/
	354
	355	#define CONSTANT_ADDRESS_P(X) \
	356	(GET_CODE (X) == LABEL_REF \
	357	\|\| GET_CODE (X) == SYMBOL_REF \
	358	\|\| GET_CODE (X) == CONST \
	359	\|\| GET_CODE (X) == CONST_INT)
	360
	361	#define MAX_REGS_PER_ADDRESS 2
	362
	363	#define HAVE_POST_INCREMENT 1
	364	#define HAVE_POST_DECREMENT 1
	365	#define HAVE_POST_MODIFY_DISP 1
	366	#define HAVE_POST_MODIFY_REG 0
	367
db869733	368	#ifdef REG_OK_STRICT
e95cfa3b PW	369	#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
e95cfa3b PW	370	#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
db869733	371	#else
e95cfa3b PW	372	#define REG_OK_FOR_BASE_P(X) 1
e95cfa3b PW	373	#define REG_OK_FOR_INDEX_P(X) 1
db869733 PW	374	#endif /* REG_OK_STRICT */
db869733 PW	375
db869733 PW	376	#define LEGITIMATE_CONSTANT_P(X) 1
	377
	378	/*****************************************************************************/
	379	/* CONDITION CODE STATUS */
	380	/*****************************************************************************/
	381
	382	/*****************************************************************************/
	383	/* RELATIVE COSTS OF OPERATIONS */
	384	/*****************************************************************************/
	385
	386	#define MEMORY_MOVE_COST(MODE, CLASS, IN) crx_memory_move_cost(MODE, CLASS, IN)
	387	/* Moving to processor register flushes pipeline - thus asymmetric */
	388	#define REGISTER_MOVE_COST(MODE, FROM, TO) ((TO != GENERAL_REGS) ? 8 : 2)
	389	/* Assume best case (branch predicted) */
3a4fd356	390	#define BRANCH_COST(speed_p, predictable_p) 2
db869733 PW	391
	392	#define SLOW_BYTE_ACCESS 1
	393
	394	/*****************************************************************************/
	395	/* DIVIDING THE OUTPUT INTO SECTIONS */
	396	/*****************************************************************************/
	397
	398	#define TEXT_SECTION_ASM_OP "\t.section\t.text"
	399
	400	#define DATA_SECTION_ASM_OP "\t.section\t.data"
	401
	402	#define BSS_SECTION_ASM_OP "\t.section\t.bss"
	403
	404	/*****************************************************************************/
	405	/* POSITION INDEPENDENT CODE */
	406	/*****************************************************************************/
	407
	408	#define PIC_OFFSET_TABLE_REGNUM 12
	409
	410	#define LEGITIMATE_PIC_OPERAND_P(X) 1
	411
	412	/*****************************************************************************/
	413	/* ASSEMBLER FORMAT */
	414	/*****************************************************************************/
	415
	416	#define GLOBAL_ASM_OP "\t.globl\t"
	417
	418	#undef USER_LABEL_PREFIX
	419	#define USER_LABEL_PREFIX "_"
	420
	421	#undef ASM_OUTPUT_LABELREF
	422	#define ASM_OUTPUT_LABELREF(STREAM, NAME) \
	423	asm_fprintf (STREAM, "%U%s", (*targetm.strip_name_encoding) (NAME));
	424
	425	#undef ASM_APP_ON
	426	#define ASM_APP_ON "#APP\n"
	427
	428	#undef ASM_APP_OFF
	429	#define ASM_APP_OFF "#NO_APP\n"
	430
	431	/*****************************************************************************/
	432	/* INSTRUCTION OUTPUT */
	433	/*****************************************************************************/
	434
	435	#define REGISTER_NAMES \
	436	{ \
	437	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
	438	"r8", "r9", "r10", "r11", "r12", "r13", "ra", "sp", \
	439	"lo", "hi", "cc" \
	440	}
	441
	442	#define PRINT_OPERAND(STREAM, X, CODE) \
	443	crx_print_operand(STREAM, X, CODE)
	444
	445	#define PRINT_OPERAND_ADDRESS(STREAM, ADDR) \
	446	crx_print_operand_address(STREAM, ADDR)
	447
	448	/*****************************************************************************/
	449	/* OUTPUT OF DISPATCH TABLES */
	450	/*****************************************************************************/
	451
	452	#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
	453	asm_fprintf ((STREAM), "\t.long\t.L%d\n", (VALUE))
	454
455	/*****************************************************************************/
456	/* ALIGNMENT IN ASSEMBLER FILE */
457	/*****************************************************************************/
458
459	#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
460	asm_fprintf ((STREAM), "\t.align\t%d\n", 1 << (POWER))
461
462	/*****************************************************************************/
463	/* MISCELLANEOUS PARAMETERS */
464	/*****************************************************************************/
465
466	#define CASE_VECTOR_MODE Pmode
467
468	#define MOVE_MAX 4
469
470	#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
471
472	#define STORE_FLAG_VALUE 1
473
474	#define Pmode SImode
475
476	#define FUNCTION_MODE QImode
477
db869733	478	#endif /* ! GCC_CRX_H */