]>
Commit | Line | Data |
---|---|---|
a5c874cb | 1 | /* Definitions of target machine for Mitsubishi D30V. |
a06ef755 | 2 | Copyright (C) 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. |
a5c874cb RH |
3 | Contributed by Cygnus Solutions. |
4 | ||
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #include "config.h" | |
23 | #include "system.h" | |
4977bab6 ZW |
24 | #include "coretypes.h" |
25 | #include "tm.h" | |
a5c874cb RH |
26 | #include "rtl.h" |
27 | #include "tree.h" | |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
a5c874cb RH |
33 | #include "output.h" |
34 | #include "insn-attr.h" | |
35 | #include "flags.h" | |
36 | #include "recog.h" | |
37 | #include "expr.h" | |
38 | #include "obstack.h" | |
39 | #include "tm_p.h" | |
40 | #include "except.h" | |
41 | #include "function.h" | |
42 | #include "toplev.h" | |
1943c2c1 | 43 | #include "integrate.h" |
a5c874cb | 44 | #include "ggc.h" |
672a6f42 NB |
45 | #include "target.h" |
46 | #include "target-def.h" | |
f1e639b1 | 47 | #include "langhooks.h" |
a5c874cb RH |
48 | |
49 | static void d30v_print_operand_memory_reference PARAMS ((FILE *, rtx)); | |
50 | static void d30v_build_long_insn PARAMS ((HOST_WIDE_INT, HOST_WIDE_INT, | |
51 | rtx, rtx)); | |
e2500fed | 52 | static struct machine_function * d30v_init_machine_status PARAMS ((void)); |
08c148a8 NB |
53 | static void d30v_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); |
54 | static void d30v_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); | |
c237e94a ZW |
55 | static int d30v_adjust_cost PARAMS ((rtx, rtx, rtx, int)); |
56 | static int d30v_issue_rate PARAMS ((void)); | |
a5c874cb RH |
57 | |
58 | /* Define the information needed to generate branch and scc insns. This is | |
59 | stored from the compare operation. */ | |
60 | ||
61 | struct rtx_def *d30v_compare_op0; | |
62 | struct rtx_def *d30v_compare_op1; | |
63 | ||
a5c874cb RH |
64 | /* Cached value of d30v_stack_info */ |
65 | static d30v_stack_t *d30v_stack_cache = (d30v_stack_t *)0; | |
66 | ||
a5c874cb RH |
67 | /* Values of the -mbranch-cost=n string. */ |
68 | int d30v_branch_cost = D30V_DEFAULT_BRANCH_COST; | |
69 | const char *d30v_branch_cost_string = (const char *)0; | |
70 | ||
71 | /* Values of the -mcond-exec=n string. */ | |
72 | int d30v_cond_exec = D30V_DEFAULT_MAX_CONDITIONAL_EXECUTE; | |
73 | const char *d30v_cond_exec_string = (const char *)0; | |
74 | ||
75 | /* Whether or not a hard register can accept a register */ | |
76 | unsigned char hard_regno_mode_ok[ (int)MAX_MACHINE_MODE ][FIRST_PSEUDO_REGISTER]; | |
77 | ||
78 | /* Whether to try and avoid moves between two different modes */ | |
79 | unsigned char modes_tieable_p[ (NUM_MACHINE_MODES) * (NUM_MACHINE_MODES) ]; | |
80 | ||
81 | /* Map register number to smallest register class. */ | |
82 | enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; | |
83 | ||
84 | /* Map class letter into register class */ | |
85 | enum reg_class reg_class_from_letter[256]; | |
672a6f42 NB |
86 | \f |
87 | /* Initialize the GCC target structure. */ | |
301d03af RS |
88 | #undef TARGET_ASM_ALIGNED_HI_OP |
89 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" | |
90 | #undef TARGET_ASM_ALIGNED_SI_OP | |
91 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
92 | ||
08c148a8 NB |
93 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
94 | #define TARGET_ASM_FUNCTION_PROLOGUE d30v_output_function_prologue | |
95 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
96 | #define TARGET_ASM_FUNCTION_EPILOGUE d30v_output_function_epilogue | |
c237e94a ZW |
97 | #undef TARGET_SCHED_ADJUST_COST |
98 | #define TARGET_SCHED_ADJUST_COST d30v_adjust_cost | |
99 | #undef TARGET_SCHED_ISSUE_RATE | |
100 | #define TARGET_SCHED_ISSUE_RATE d30v_issue_rate | |
a5c874cb | 101 | |
f6897b10 | 102 | struct gcc_target targetm = TARGET_INITIALIZER; |
a5c874cb RH |
103 | \f |
104 | /* Sometimes certain combinations of command options do not make | |
105 | sense on a particular target machine. You can define a macro | |
106 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
107 | defined, is executed once just after all the command options have | |
108 | been parsed. | |
109 | ||
110 | Don't use this macro to turn on various extra optimizations for | |
111 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
112 | ||
113 | void | |
114 | override_options () | |
115 | { | |
116 | int regno, i, ok_p; | |
117 | enum machine_mode mode1, mode2; | |
118 | ||
119 | /* Set up the branch cost information */ | |
120 | if (d30v_branch_cost_string) | |
121 | d30v_branch_cost = atoi (d30v_branch_cost_string); | |
122 | ||
123 | /* Set up max # instructions to use with conditional execution */ | |
124 | if (d30v_cond_exec_string) | |
125 | d30v_cond_exec = atoi (d30v_cond_exec_string); | |
126 | ||
127 | /* Setup hard_regno_mode_ok/modes_tieable_p */ | |
128 | for (mode1 = VOIDmode; | |
129 | (int)mode1 < NUM_MACHINE_MODES; | |
130 | mode1 = (enum machine_mode)((int)mode1 + 1)) | |
131 | { | |
132 | int size = GET_MODE_SIZE (mode1); | |
133 | int large_p = size > UNITS_PER_WORD; | |
134 | int int_p = GET_MODE_CLASS (mode1) == MODE_INT; | |
135 | ||
136 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
137 | { | |
138 | if (mode1 == VOIDmode) | |
139 | ok_p = FALSE; | |
140 | ||
141 | else if (GPR_P (regno)) | |
142 | { | |
143 | if (!large_p) | |
144 | ok_p = TRUE; | |
145 | else | |
146 | ok_p = (((regno - GPR_FIRST) & 1) == 0); | |
147 | } | |
148 | ||
149 | else if (FLAG_P (regno)) | |
150 | ok_p = (mode1 == CCmode); | |
151 | ||
152 | else if (CR_P (regno)) | |
153 | ok_p = int_p && !large_p; | |
154 | ||
155 | else if (ACCUM_P (regno)) | |
156 | ok_p = (mode1 == DImode); | |
157 | ||
158 | else if (SPECIAL_REG_P (regno)) | |
159 | ok_p = (mode1 == SImode); | |
160 | ||
161 | else | |
162 | ok_p = FALSE; | |
163 | ||
164 | hard_regno_mode_ok[ (int)mode1 ][ regno ] = ok_p; | |
165 | } | |
166 | ||
167 | /* A C expression that is nonzero if it is desirable to choose | |
168 | register allocation so as to avoid move instructions between a | |
169 | value of mode MODE1 and a value of mode MODE2. | |
170 | ||
171 | If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, | |
172 | MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1, | |
173 | MODE2)' must be zero. */ | |
174 | for (mode2 = VOIDmode; | |
175 | (int)mode2 <= NUM_MACHINE_MODES; | |
176 | mode2 = (enum machine_mode)((int)mode2 + 1)) | |
177 | { | |
178 | if (mode1 == mode2) | |
179 | ok_p = TRUE; | |
180 | ||
181 | #if 0 | |
182 | else if (GET_MODE_CLASS (mode1) == MODE_INT | |
183 | && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD | |
184 | && GET_MODE_CLASS (mode2) == MODE_INT | |
185 | && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD) | |
186 | ok_p = TRUE; | |
187 | #endif | |
188 | ||
189 | else | |
190 | ok_p = FALSE; | |
191 | ||
192 | modes_tieable_p[ ((int)mode1 * (NUM_MACHINE_MODES)) + (int)mode2 ] = ok_p; | |
193 | } | |
194 | } | |
195 | ||
196 | #if 0 | |
197 | for (mode1 = VOIDmode; | |
198 | (int)mode1 < NUM_MACHINE_MODES; | |
199 | mode1 = (enum machine_mode)((int)mode1 + 1)) | |
200 | { | |
201 | for (mode2 = VOIDmode; | |
202 | (int)mode2 <= NUM_MACHINE_MODES; | |
203 | mode2 = (enum machine_mode)((int)mode2 + 1)) | |
204 | { | |
205 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
206 | if (ok_p | |
207 | && (hard_regno_mode_ok[(int)mode1][regno] | |
208 | != hard_regno_mode_ok[(int)mode2][regno])) | |
c725bd79 | 209 | error ("bad modes_tieable_p for register %s, mode1 %s, mode2 %s", |
a5c874cb RH |
210 | reg_names[regno], GET_MODE_NAME (mode1), |
211 | GET_MODE_NAME (mode2)); | |
212 | } | |
213 | } | |
214 | #endif | |
215 | ||
216 | /* A C expression whose value is a register class containing hard | |
217 | register REGNO. In general there is more than one such class; | |
218 | choose a class which is "minimal", meaning that no smaller class | |
219 | also contains the register. */ | |
220 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
221 | { | |
222 | enum reg_class class; | |
223 | ||
224 | if (GPR_P (regno)) | |
225 | class = (IN_RANGE_P (regno, GPR_FIRST+2, GPR_FIRST+62) | |
226 | && ((regno - GPR_FIRST) & 1) == 0) ? EVEN_REGS : GPR_REGS; | |
227 | ||
228 | else if (regno == FLAG_F0) | |
229 | class = F0_REGS; | |
230 | ||
231 | else if (regno == FLAG_F1) | |
232 | class = F1_REGS; | |
233 | ||
234 | else if (FLAG_P (regno)) | |
235 | class = OTHER_FLAG_REGS; | |
236 | ||
237 | else if (ACCUM_P (regno)) | |
238 | class = ACCUM_REGS; | |
239 | ||
240 | else if (regno == CR_RPT_C) | |
241 | class = REPEAT_REGS; | |
242 | ||
243 | else if (CR_P (regno)) | |
244 | class = CR_REGS; | |
245 | ||
246 | else if (SPECIAL_REG_P (regno)) | |
247 | class = GPR_REGS; | |
248 | ||
249 | else | |
250 | class = NO_REGS; | |
251 | ||
252 | regno_reg_class[regno] = class; | |
253 | ||
254 | #if 0 | |
255 | { | |
8b60264b | 256 | static const char *const names[] = REG_CLASS_NAMES; |
a5c874cb RH |
257 | fprintf (stderr, "Register %s class is %s, can hold modes", reg_names[regno], names[class]); |
258 | for (mode1 = VOIDmode; | |
259 | (int)mode1 < NUM_MACHINE_MODES; | |
260 | mode1 = (enum machine_mode)((int)mode1 + 1)) | |
261 | { | |
262 | if (hard_regno_mode_ok[ (int)mode1 ][ regno ]) | |
263 | fprintf (stderr, " %s", GET_MODE_NAME (mode1)); | |
264 | } | |
265 | fprintf (stderr, "\n"); | |
266 | } | |
267 | #endif | |
268 | } | |
269 | ||
270 | /* A C expression which defines the machine-dependent operand | |
271 | constraint letters for register classes. If CHAR is such a | |
272 | letter, the value should be the register class corresponding to | |
273 | it. Otherwise, the value should be `NO_REGS'. The register | |
274 | letter `r', corresponding to class `GENERAL_REGS', will not be | |
275 | passed to this macro; you do not need to handle it. | |
276 | ||
277 | The following letters are unavailable, due to being used as | |
278 | constraints: | |
279 | '0'..'9' | |
280 | '<', '>' | |
281 | 'E', 'F', 'G', 'H' | |
282 | 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P' | |
283 | 'Q', 'R', 'S', 'T', 'U' | |
284 | 'V', 'X' | |
285 | 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */ | |
286 | ||
287 | for (i = 0; i < 256; i++) | |
288 | reg_class_from_letter[i] = NO_REGS; | |
289 | ||
290 | reg_class_from_letter['a'] = ACCUM_REGS; | |
291 | reg_class_from_letter['b'] = BR_FLAG_REGS; | |
292 | reg_class_from_letter['c'] = CR_REGS; | |
293 | reg_class_from_letter['d'] = GPR_REGS; | |
294 | reg_class_from_letter['e'] = EVEN_REGS; | |
295 | reg_class_from_letter['f'] = FLAG_REGS; | |
296 | reg_class_from_letter['l'] = REPEAT_REGS; | |
297 | reg_class_from_letter['x'] = F0_REGS; | |
298 | reg_class_from_letter['y'] = F1_REGS; | |
299 | reg_class_from_letter['z'] = OTHER_FLAG_REGS; | |
a5c874cb RH |
300 | } |
301 | ||
302 | \f | |
303 | /* Return true if a memory operand is a short memory operand. */ | |
304 | ||
305 | int | |
306 | short_memory_operand (op, mode) | |
307 | register rtx op; | |
308 | enum machine_mode mode; | |
309 | { | |
310 | if (GET_CODE (op) != MEM) | |
311 | return FALSE; | |
312 | ||
313 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
314 | return FALSE; | |
315 | ||
316 | return (d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed) | |
317 | == 1); | |
318 | } | |
319 | ||
320 | /* Return true if a memory operand is a long operand. */ | |
321 | ||
322 | int | |
323 | long_memory_operand (op, mode) | |
324 | rtx op; | |
325 | enum machine_mode mode; | |
326 | { | |
327 | if (GET_CODE (op) != MEM) | |
328 | return FALSE; | |
329 | ||
330 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
331 | return FALSE; | |
332 | ||
333 | return (d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed) | |
334 | == 2); | |
335 | } | |
336 | ||
337 | /* Return true if a memory operand is valid for the D30V. */ | |
338 | ||
339 | int | |
340 | d30v_memory_operand (op, mode) | |
341 | rtx op; | |
342 | enum machine_mode mode; | |
343 | { | |
344 | if (GET_CODE (op) != MEM) | |
345 | return FALSE; | |
346 | ||
347 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
348 | return FALSE; | |
349 | ||
350 | return (d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed) | |
351 | != 0); | |
352 | } | |
353 | ||
354 | /* Return true if a memory operand uses a single register for the | |
355 | address. */ | |
356 | ||
357 | int | |
358 | single_reg_memory_operand (op, mode) | |
359 | rtx op; | |
360 | enum machine_mode mode; | |
361 | { | |
362 | rtx addr; | |
363 | ||
364 | if (GET_CODE (op) != MEM) | |
365 | return FALSE; | |
366 | ||
367 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
368 | return FALSE; | |
369 | ||
370 | addr = XEXP (op, 0); | |
371 | if (! d30v_legitimate_address_p (mode, addr, reload_completed)) | |
372 | return FALSE; | |
373 | ||
374 | if (GET_CODE (addr) == SUBREG) | |
375 | addr = SUBREG_REG (addr); | |
376 | ||
377 | return (GET_CODE (addr) == REG); | |
378 | } | |
379 | ||
380 | /* Return true if a memory operand uses a constant address. */ | |
381 | ||
382 | int | |
383 | const_addr_memory_operand (op, mode) | |
384 | rtx op; | |
385 | enum machine_mode mode; | |
386 | { | |
387 | if (GET_CODE (op) != MEM) | |
388 | return FALSE; | |
389 | ||
390 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
391 | return FALSE; | |
392 | ||
393 | if (! d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed)) | |
394 | return FALSE; | |
395 | ||
396 | switch (GET_CODE (XEXP (op, 0))) | |
397 | { | |
398 | default: | |
399 | break; | |
400 | ||
401 | case SYMBOL_REF: | |
402 | case LABEL_REF: | |
403 | case CONST_INT: | |
404 | case CONST: | |
405 | return TRUE; | |
406 | } | |
407 | ||
408 | return FALSE; | |
409 | } | |
410 | ||
411 | /* Return true if operand is a memory reference suitable for a call. */ | |
412 | ||
413 | int | |
414 | call_operand (op, mode) | |
415 | rtx op; | |
416 | enum machine_mode mode; | |
417 | { | |
418 | if (GET_CODE (op) != MEM) | |
419 | return FALSE; | |
420 | ||
421 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
422 | return FALSE; | |
423 | ||
424 | if (! d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed)) | |
425 | return FALSE; | |
426 | ||
427 | switch (GET_CODE (XEXP (op, 0))) | |
428 | { | |
429 | default: | |
430 | break; | |
431 | ||
432 | case SUBREG: | |
433 | op = SUBREG_REG (op); | |
434 | if (GET_CODE (op) != REG) | |
435 | return FALSE; | |
436 | ||
437 | /* fall through */ | |
438 | ||
439 | case REG: | |
440 | return (GPR_OR_PSEUDO_P (REGNO (XEXP (op, 0)))); | |
441 | ||
442 | case SYMBOL_REF: | |
443 | case LABEL_REF: | |
444 | case CONST_INT: | |
445 | case CONST: | |
446 | return TRUE; | |
447 | } | |
448 | ||
449 | return FALSE; | |
450 | } | |
451 | ||
452 | /* Return true if operand is a GPR register. */ | |
453 | ||
454 | int | |
455 | gpr_operand (op, mode) | |
456 | rtx op; | |
457 | enum machine_mode mode; | |
458 | { | |
459 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
460 | return FALSE; | |
461 | ||
462 | if (GET_CODE (op) == SUBREG) | |
463 | { | |
464 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
465 | return register_operand (op, mode); | |
466 | ||
467 | op = SUBREG_REG (op); | |
468 | } | |
469 | ||
470 | if (GET_CODE (op) != REG) | |
471 | return FALSE; | |
472 | ||
473 | return GPR_OR_PSEUDO_P (REGNO (op)); | |
474 | } | |
475 | ||
476 | /* Return true if operand is an accumulator register. */ | |
477 | ||
478 | int | |
479 | accum_operand (op, mode) | |
480 | rtx op; | |
481 | enum machine_mode mode; | |
482 | { | |
483 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
484 | return FALSE; | |
485 | ||
486 | if (GET_CODE (op) == SUBREG) | |
487 | { | |
488 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
489 | return register_operand (op, mode); | |
490 | ||
491 | op = SUBREG_REG (op); | |
492 | } | |
493 | ||
494 | if (GET_CODE (op) != REG) | |
495 | return FALSE; | |
496 | ||
497 | return ACCUM_OR_PSEUDO_P (REGNO (op)); | |
498 | } | |
499 | ||
500 | /* Return true if operand is a GPR or an accumulator register. */ | |
501 | ||
502 | int | |
503 | gpr_or_accum_operand (op, mode) | |
504 | rtx op; | |
505 | enum machine_mode mode; | |
506 | { | |
507 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
508 | return FALSE; | |
509 | ||
510 | if (GET_CODE (op) == SUBREG) | |
511 | { | |
512 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
513 | return register_operand (op, mode); | |
514 | ||
515 | op = SUBREG_REG (op); | |
516 | } | |
517 | ||
518 | if (GET_CODE (op) != REG) | |
519 | return FALSE; | |
520 | ||
521 | if (ACCUM_P (REGNO (op))) | |
522 | return TRUE; | |
523 | ||
524 | return GPR_OR_PSEUDO_P (REGNO (op)); | |
525 | } | |
526 | ||
527 | /* Return true if operand is a CR register. */ | |
528 | ||
529 | int | |
530 | cr_operand (op, mode) | |
531 | rtx op; | |
532 | enum machine_mode mode; | |
533 | { | |
534 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
535 | return FALSE; | |
536 | ||
537 | if (GET_CODE (op) == SUBREG) | |
538 | { | |
539 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
540 | return register_operand (op, mode); | |
541 | ||
542 | op = SUBREG_REG (op); | |
543 | } | |
544 | ||
545 | if (GET_CODE (op) != REG) | |
546 | return FALSE; | |
547 | ||
548 | return CR_OR_PSEUDO_P (REGNO (op)); | |
549 | } | |
550 | ||
551 | /* Return true if operand is the repeat count register. */ | |
552 | ||
553 | int | |
554 | repeat_operand (op, mode) | |
555 | rtx op; | |
556 | enum machine_mode mode; | |
557 | { | |
558 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
559 | return FALSE; | |
560 | ||
561 | if (GET_CODE (op) == SUBREG) | |
562 | { | |
563 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
564 | return register_operand (op, mode); | |
565 | ||
566 | op = SUBREG_REG (op); | |
567 | } | |
568 | ||
569 | if (GET_CODE (op) != REG) | |
570 | return FALSE; | |
571 | ||
572 | return (REGNO (op) == CR_RPT_C || REGNO (op) >= FIRST_PSEUDO_REGISTER); | |
573 | } | |
574 | ||
575 | /* Return true if operand is a FLAG register. */ | |
576 | ||
577 | int | |
578 | flag_operand (op, mode) | |
579 | rtx op; | |
580 | enum machine_mode mode; | |
581 | { | |
582 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
583 | return FALSE; | |
584 | ||
585 | if (GET_CODE (op) == SUBREG) | |
586 | { | |
587 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
588 | return register_operand (op, mode); | |
589 | ||
590 | op = SUBREG_REG (op); | |
591 | } | |
592 | ||
593 | if (GET_CODE (op) != REG) | |
594 | return FALSE; | |
595 | ||
596 | return FLAG_OR_PSEUDO_P (REGNO (op)); | |
597 | } | |
598 | ||
599 | /* Return true if operand is either F0 or F1. */ | |
600 | ||
601 | int | |
602 | br_flag_operand (op, mode) | |
603 | rtx op; | |
604 | enum machine_mode mode; | |
605 | { | |
606 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
607 | return FALSE; | |
608 | ||
609 | if (GET_CODE (op) == SUBREG) | |
610 | { | |
611 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
612 | return register_operand (op, mode); | |
613 | ||
614 | op = SUBREG_REG (op); | |
615 | } | |
616 | ||
617 | if (GET_CODE (op) != REG) | |
618 | return FALSE; | |
619 | ||
620 | return BR_FLAG_OR_PSEUDO_P (REGNO (op)); | |
621 | } | |
622 | ||
623 | /* Return true if operand is either F0/F1 or the constants 0/1. */ | |
624 | ||
625 | int | |
626 | br_flag_or_constant_operand (op, mode) | |
627 | rtx op; | |
628 | enum machine_mode mode; | |
629 | { | |
630 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
631 | return FALSE; | |
632 | ||
633 | if (GET_CODE (op) == SUBREG) | |
634 | { | |
635 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
636 | return register_operand (op, mode); | |
637 | ||
638 | op = SUBREG_REG (op); | |
639 | } | |
640 | ||
641 | if (GET_CODE (op) == CONST_INT) | |
642 | return (INTVAL (op) == 0 || INTVAL (op) == 1); | |
643 | ||
644 | if (GET_CODE (op) != REG) | |
645 | return FALSE; | |
646 | ||
647 | return BR_FLAG_OR_PSEUDO_P (REGNO (op)); | |
648 | } | |
649 | ||
650 | /* Return true if operand is either F0 or F1, or a GPR register. */ | |
651 | ||
652 | int | |
653 | gpr_or_br_flag_operand (op, mode) | |
654 | rtx op; | |
655 | enum machine_mode mode; | |
656 | { | |
657 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
658 | return FALSE; | |
659 | ||
660 | if (GET_CODE (op) == SUBREG) | |
661 | { | |
662 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
663 | return register_operand (op, mode); | |
664 | ||
665 | op = SUBREG_REG (op); | |
666 | } | |
667 | ||
668 | if (GET_CODE (op) != REG) | |
669 | return FALSE; | |
670 | ||
671 | return GPR_OR_PSEUDO_P (REGNO (op)) || BR_FLAG_P (REGNO (op)); | |
672 | } | |
673 | ||
674 | /* Return true if operand is the F0 register. */ | |
675 | ||
676 | int | |
677 | f0_operand (op, mode) | |
678 | rtx op; | |
679 | enum machine_mode mode; | |
680 | { | |
681 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
682 | return FALSE; | |
683 | ||
684 | if (GET_CODE (op) == SUBREG) | |
685 | { | |
686 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
687 | return register_operand (op, mode); | |
688 | ||
689 | op = SUBREG_REG (op); | |
690 | } | |
691 | ||
692 | if (GET_CODE (op) != REG) | |
693 | return FALSE; | |
694 | ||
695 | return (REGNO (op) == FLAG_F0 || REGNO (op) >= FIRST_PSEUDO_REGISTER); | |
696 | } | |
697 | ||
698 | /* Return true if operand is the F1 register. */ | |
699 | ||
700 | int | |
701 | f1_operand (op, mode) | |
702 | rtx op; | |
703 | enum machine_mode mode; | |
704 | { | |
705 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
706 | return FALSE; | |
707 | ||
708 | if (GET_CODE (op) == SUBREG) | |
709 | { | |
710 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
711 | return register_operand (op, mode); | |
712 | ||
713 | op = SUBREG_REG (op); | |
714 | } | |
715 | ||
716 | if (GET_CODE (op) != REG) | |
717 | return FALSE; | |
718 | ||
719 | return (REGNO (op) == FLAG_F1 || REGNO (op) >= FIRST_PSEUDO_REGISTER); | |
720 | } | |
721 | ||
722 | /* Return true if operand is the F1 register. */ | |
723 | ||
724 | int | |
725 | carry_operand (op, mode) | |
726 | rtx op; | |
727 | enum machine_mode mode; | |
728 | { | |
729 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
730 | return FALSE; | |
731 | ||
732 | if (GET_CODE (op) == SUBREG) | |
733 | { | |
734 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
735 | return register_operand (op, mode); | |
736 | ||
737 | op = SUBREG_REG (op); | |
738 | } | |
739 | ||
740 | if (GET_CODE (op) != REG) | |
741 | return FALSE; | |
742 | ||
743 | return (REGNO (op) == FLAG_CARRY || REGNO (op) >= FIRST_PSEUDO_REGISTER); | |
744 | } | |
745 | ||
746 | /* Return true if operand is a register of any flavor or a 0 of the | |
747 | appropriate type. */ | |
748 | ||
749 | int | |
750 | reg_or_0_operand (op, mode) | |
751 | rtx op; | |
752 | enum machine_mode mode; | |
753 | { | |
754 | switch (GET_CODE (op)) | |
755 | { | |
756 | default: | |
757 | break; | |
758 | ||
759 | case REG: | |
760 | case SUBREG: | |
761 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
762 | return FALSE; | |
763 | ||
764 | return register_operand (op, mode); | |
765 | ||
766 | case CONST_INT: | |
767 | return INTVAL (op) == 0; | |
768 | ||
769 | case CONST_DOUBLE: | |
770 | return CONST_DOUBLE_HIGH (op) == 0 && CONST_DOUBLE_LOW (op) == 0; | |
771 | } | |
772 | ||
773 | return FALSE; | |
774 | } | |
775 | ||
776 | /* Return true if operand is a GPR register or a signed 6 bit immediate. */ | |
777 | ||
778 | int | |
779 | gpr_or_signed6_operand (op, mode) | |
780 | rtx op; | |
781 | enum machine_mode mode; | |
782 | { | |
783 | if (GET_CODE (op) == SUBREG) | |
784 | { | |
785 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
786 | return register_operand (op, mode); | |
787 | ||
788 | op = SUBREG_REG (op); | |
789 | } | |
790 | ||
791 | if (GET_CODE (op) == CONST_INT) | |
792 | return IN_RANGE_P (INTVAL (op), -32, 31); | |
793 | ||
794 | if (GET_CODE (op) != REG) | |
795 | return FALSE; | |
796 | ||
797 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
798 | return FALSE; | |
799 | ||
800 | return GPR_OR_PSEUDO_P (REGNO (op)); | |
801 | } | |
802 | ||
803 | /* Return true if operand is a GPR register or an unsigned 5 bit immediate. */ | |
804 | ||
805 | int | |
806 | gpr_or_unsigned5_operand (op, mode) | |
807 | rtx op; | |
808 | enum machine_mode mode; | |
809 | { | |
810 | if (GET_CODE (op) == SUBREG) | |
811 | { | |
812 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
813 | return register_operand (op, mode); | |
814 | ||
815 | op = SUBREG_REG (op); | |
816 | } | |
817 | ||
818 | if (GET_CODE (op) == CONST_INT) | |
819 | return IN_RANGE_P (INTVAL (op), 0, 31); | |
820 | ||
821 | if (GET_CODE (op) != REG) | |
822 | return FALSE; | |
823 | ||
824 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
825 | return FALSE; | |
826 | ||
827 | return GPR_OR_PSEUDO_P (REGNO (op)); | |
828 | } | |
829 | ||
830 | /* Return true if operand is a GPR register or an unsigned 6 bit immediate. */ | |
831 | ||
832 | int | |
833 | gpr_or_unsigned6_operand (op, mode) | |
834 | rtx op; | |
835 | enum machine_mode mode; | |
836 | { | |
837 | if (GET_CODE (op) == SUBREG) | |
838 | { | |
839 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
840 | return register_operand (op, mode); | |
841 | ||
842 | op = SUBREG_REG (op); | |
843 | } | |
844 | ||
845 | if (GET_CODE (op) == CONST_INT) | |
846 | return IN_RANGE_P (INTVAL (op), 0, 63); | |
847 | ||
848 | if (GET_CODE (op) != REG) | |
849 | return FALSE; | |
850 | ||
851 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
852 | return FALSE; | |
853 | ||
854 | return GPR_OR_PSEUDO_P (REGNO (op)); | |
855 | } | |
856 | ||
857 | /* Return true if operand is a GPR register or a constant of some form. */ | |
858 | ||
859 | int | |
860 | gpr_or_constant_operand (op, mode) | |
861 | rtx op; | |
862 | enum machine_mode mode; | |
863 | { | |
864 | switch (GET_CODE (op)) | |
865 | { | |
866 | default: | |
867 | break; | |
868 | ||
869 | case CONST_INT: | |
870 | case SYMBOL_REF: | |
871 | case LABEL_REF: | |
872 | case CONST: | |
873 | return TRUE; | |
874 | ||
875 | case SUBREG: | |
876 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
877 | return register_operand (op, mode); | |
878 | ||
879 | op = SUBREG_REG (op); | |
880 | /* fall through */ | |
881 | ||
882 | case REG: | |
883 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
884 | return FALSE; | |
885 | ||
886 | return GPR_OR_PSEUDO_P (REGNO (op)); | |
887 | } | |
888 | ||
889 | return FALSE; | |
890 | } | |
891 | ||
892 | /* Return true if operand is a GPR register or a constant of some form, | |
893 | including a CONST_DOUBLE, which gpr_or_constant_operand doesn't recognize. */ | |
894 | ||
895 | int | |
896 | gpr_or_dbl_const_operand (op, mode) | |
897 | rtx op; | |
898 | enum machine_mode mode; | |
899 | { | |
900 | switch (GET_CODE (op)) | |
901 | { | |
902 | default: | |
903 | break; | |
904 | ||
905 | case CONST_INT: | |
906 | case CONST_DOUBLE: | |
907 | case SYMBOL_REF: | |
908 | case LABEL_REF: | |
909 | case CONST: | |
910 | return TRUE; | |
911 | ||
912 | case SUBREG: | |
913 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
914 | return register_operand (op, mode); | |
915 | ||
916 | op = SUBREG_REG (op); | |
917 | /* fall through */ | |
918 | ||
919 | case REG: | |
920 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
921 | return FALSE; | |
922 | ||
923 | return GPR_OR_PSEUDO_P (REGNO (op)); | |
924 | } | |
925 | ||
926 | return FALSE; | |
927 | } | |
928 | ||
929 | /* Return true if operand is a gpr register or a valid memory operation. */ | |
930 | ||
931 | int | |
932 | gpr_or_memory_operand (op, mode) | |
933 | rtx op; | |
934 | enum machine_mode mode; | |
935 | { | |
936 | switch (GET_CODE (op)) | |
937 | { | |
938 | default: | |
939 | break; | |
940 | ||
941 | case SUBREG: | |
942 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
943 | return register_operand (op, mode); | |
944 | ||
945 | op = SUBREG_REG (op); | |
946 | /* fall through */ | |
947 | ||
948 | case REG: | |
949 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
950 | return FALSE; | |
951 | ||
952 | return GPR_OR_PSEUDO_P (REGNO (op)); | |
953 | ||
954 | case MEM: | |
955 | return d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed); | |
956 | } | |
957 | ||
958 | return FALSE; | |
959 | } | |
960 | ||
961 | /* Return true if operand is something that can be an input for a move | |
962 | operation. */ | |
963 | ||
964 | int | |
965 | move_input_operand (op, mode) | |
966 | rtx op; | |
967 | enum machine_mode mode; | |
968 | { | |
969 | rtx subreg; | |
970 | enum rtx_code code; | |
971 | ||
972 | switch (GET_CODE (op)) | |
973 | { | |
974 | default: | |
975 | break; | |
976 | ||
977 | case CONST_INT: | |
978 | case CONST_DOUBLE: | |
979 | case SYMBOL_REF: | |
980 | case LABEL_REF: | |
981 | case CONST: | |
982 | return TRUE; | |
983 | ||
984 | case SUBREG: | |
985 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
986 | return FALSE; | |
987 | ||
988 | subreg = SUBREG_REG (op); | |
989 | code = GET_CODE (subreg); | |
990 | if (code == MEM) | |
991 | return d30v_legitimate_address_p ((int)mode, XEXP (subreg, 0), | |
992 | reload_completed); | |
993 | ||
994 | return (code == REG); | |
995 | ||
996 | case REG: | |
997 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
998 | return FALSE; | |
999 | ||
1000 | return TRUE; | |
1001 | ||
1002 | case MEM: | |
1003 | if (GET_CODE (XEXP (op, 0)) == ADDRESSOF) | |
1004 | return TRUE; | |
1005 | return d30v_legitimate_address_p (mode, XEXP (op, 0), | |
1006 | reload_completed); | |
1007 | } | |
1008 | ||
1009 | return FALSE; | |
1010 | } | |
1011 | ||
1012 | /* Return true if operand is something that can be an output for a move | |
1013 | operation. */ | |
1014 | ||
1015 | int | |
1016 | move_output_operand (op, mode) | |
1017 | rtx op; | |
1018 | enum machine_mode mode; | |
1019 | { | |
1020 | rtx subreg; | |
1021 | enum rtx_code code; | |
1022 | ||
1023 | switch (GET_CODE (op)) | |
1024 | { | |
1025 | default: | |
1026 | break; | |
1027 | ||
1028 | case SUBREG: | |
1029 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
1030 | return FALSE; | |
1031 | ||
1032 | subreg = SUBREG_REG (op); | |
1033 | code = GET_CODE (subreg); | |
1034 | if (code == MEM) | |
1035 | return d30v_legitimate_address_p ((int)mode, XEXP (subreg, 0), | |
1036 | reload_completed); | |
1037 | ||
1038 | return (code == REG); | |
1039 | ||
1040 | case REG: | |
1041 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
1042 | return FALSE; | |
1043 | ||
1044 | return TRUE; | |
1045 | ||
1046 | case MEM: | |
1047 | if (GET_CODE (XEXP (op, 0)) == ADDRESSOF) | |
1048 | return TRUE; | |
1049 | return d30v_legitimate_address_p (mode, XEXP (op, 0), | |
1050 | reload_completed); | |
1051 | } | |
1052 | ||
1053 | return FALSE; | |
1054 | } | |
1055 | ||
1056 | /* Return true if operand is a signed 6 bit immediate. */ | |
1057 | ||
1058 | int | |
1059 | signed6_operand (op, mode) | |
1060 | rtx op; | |
1061 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1062 | { | |
1063 | if (GET_CODE (op) == CONST_INT) | |
1064 | return IN_RANGE_P (INTVAL (op), -32, 31); | |
1065 | ||
1066 | return FALSE; | |
1067 | } | |
1068 | ||
1069 | /* Return true if operand is an unsigned 5 bit immediate. */ | |
1070 | ||
1071 | int | |
1072 | unsigned5_operand (op, mode) | |
1073 | rtx op; | |
1074 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1075 | { | |
1076 | if (GET_CODE (op) == CONST_INT) | |
1077 | return IN_RANGE_P (INTVAL (op), 0, 31); | |
1078 | ||
1079 | return FALSE; | |
1080 | } | |
1081 | ||
1082 | /* Return true if operand is an unsigned 6 bit immediate. */ | |
1083 | ||
1084 | int | |
1085 | unsigned6_operand (op, mode) | |
1086 | rtx op; | |
1087 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1088 | { | |
1089 | if (GET_CODE (op) == CONST_INT) | |
1090 | return IN_RANGE_P (INTVAL (op), 0, 63); | |
1091 | ||
1092 | return FALSE; | |
1093 | } | |
1094 | ||
1095 | /* Return true if operand is a constant with a single bit set. */ | |
1096 | ||
1097 | int | |
1098 | bitset_operand (op, mode) | |
1099 | rtx op; | |
1100 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1101 | { | |
1102 | if (GET_CODE (op) == CONST_INT) | |
1103 | return IN_RANGE_P (exact_log2 (INTVAL (op)), 0, 31); | |
1104 | ||
1105 | return FALSE; | |
1106 | } | |
1107 | ||
1108 | /* Return true if the operator is a ==/!= test against f0 or f1 that can be | |
1109 | used in conditional execution. */ | |
1110 | ||
1111 | int | |
1112 | condexec_test_operator (op, mode) | |
1113 | rtx op; | |
1114 | enum machine_mode mode; | |
1115 | { | |
1116 | rtx x0, x1; | |
1117 | ||
1118 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
1119 | return FALSE; | |
1120 | ||
1121 | if (GET_CODE (op) != EQ && GET_CODE (op) != NE) | |
1122 | return FALSE; | |
1123 | ||
1124 | x0 = XEXP (op, 0); | |
1125 | if (GET_CODE (x0) != REG || !BR_FLAG_OR_PSEUDO_P (REGNO (x0))) | |
1126 | return FALSE; | |
1127 | ||
1128 | x1 = XEXP (op, 1); | |
1129 | if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0) | |
1130 | return FALSE; | |
1131 | ||
1132 | return TRUE; | |
1133 | } | |
1134 | ||
1135 | /* Return true if the operator is a ==/!= test against f0, f1, or a general | |
1136 | register that can be used in a branch instruction. */ | |
1137 | ||
1138 | int | |
1139 | condexec_branch_operator (op, mode) | |
1140 | rtx op; | |
1141 | enum machine_mode mode; | |
1142 | { | |
1143 | rtx x0, x1; | |
1144 | ||
1145 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
1146 | return FALSE; | |
1147 | ||
1148 | if (GET_CODE (op) != EQ && GET_CODE (op) != NE) | |
1149 | return FALSE; | |
1150 | ||
1151 | x0 = XEXP (op, 0); | |
1152 | if (GET_CODE (x0) == REG) | |
1153 | { | |
1154 | int regno = REGNO (x0); | |
1155 | if (!GPR_OR_PSEUDO_P (regno) && !BR_FLAG_P (regno)) | |
1156 | return FALSE; | |
1157 | } | |
1158 | /* Allow the optimizer to generate things like: | |
1159 | (if_then_else (ne (const_int 1) (const_int 0))) */ | |
1160 | else if (GET_CODE (x0) != CONST_INT) | |
1161 | return FALSE; | |
1162 | ||
1163 | x1 = XEXP (op, 1); | |
1164 | if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0) | |
1165 | return FALSE; | |
1166 | ||
1167 | return TRUE; | |
1168 | } | |
1169 | ||
1170 | /* Return true if the unary operator can be executed with conditional | |
1171 | execution. */ | |
1172 | ||
1173 | int | |
1174 | condexec_unary_operator (op, mode) | |
1175 | rtx op; | |
1176 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1177 | { | |
1178 | rtx op0; | |
1179 | ||
1180 | /* Only do this after register allocation, so that we can look at the register # */ | |
1181 | if (!reload_completed) | |
1182 | return FALSE; | |
1183 | ||
1184 | if (GET_RTX_CLASS (GET_CODE (op)) != '1') | |
1185 | return FALSE; | |
1186 | ||
1187 | op0 = XEXP (op, 0); | |
1188 | if (GET_CODE (op0) == SUBREG) | |
1189 | op0 = SUBREG_REG (op0); | |
1190 | ||
1191 | switch (GET_CODE (op)) | |
1192 | { | |
1193 | default: | |
1194 | break; | |
1195 | ||
1196 | case ABS: | |
1197 | case NOT: | |
1198 | if (GET_MODE (op) == SImode && GET_CODE (op0) == REG && GPR_P (REGNO (op0))) | |
1199 | return TRUE; | |
1200 | ||
1201 | break; | |
1202 | } | |
1203 | ||
1204 | return FALSE; | |
1205 | } | |
1206 | ||
1207 | /* Return true if the add or subtraction can be executed with conditional | |
1208 | execution. */ | |
1209 | ||
1210 | int | |
1211 | condexec_addsub_operator (op, mode) | |
1212 | rtx op; | |
1213 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1214 | { | |
1215 | rtx op0, op1; | |
1216 | ||
1217 | /* Only do this after register allocation, so that we can look at the register # */ | |
1218 | if (!reload_completed) | |
1219 | return FALSE; | |
1220 | ||
1221 | if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c') | |
1222 | return FALSE; | |
1223 | ||
1224 | op0 = XEXP (op, 0); | |
1225 | op1 = XEXP (op, 1); | |
1226 | ||
1227 | if (GET_CODE (op0) == SUBREG) | |
1228 | op0 = SUBREG_REG (op0); | |
1229 | ||
1230 | if (GET_CODE (op1) == SUBREG) | |
1231 | op1 = SUBREG_REG (op1); | |
1232 | ||
1233 | if (GET_CODE (op0) != REG) | |
1234 | return FALSE; | |
1235 | ||
1236 | switch (GET_CODE (op)) | |
1237 | { | |
1238 | default: | |
1239 | break; | |
1240 | ||
1241 | case PLUS: | |
1242 | case MINUS: | |
1243 | return (GET_MODE (op) == SImode && GPR_P (REGNO (op0)) | |
1244 | && gpr_or_constant_operand (op1, SImode)); | |
1245 | } | |
1246 | ||
1247 | return FALSE; | |
1248 | } | |
1249 | ||
1250 | /* Return true if the binary operator can be executed with conditional | |
1251 | execution. We don't include add/sub here, since they have extra | |
1252 | clobbers for the flags registers. */ | |
1253 | ||
1254 | int | |
1255 | condexec_binary_operator (op, mode) | |
1256 | rtx op; | |
1257 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1258 | { | |
1259 | rtx op0, op1; | |
1260 | ||
1261 | /* Only do this after register allocation, so that we can look at the register # */ | |
1262 | if (!reload_completed) | |
1263 | return FALSE; | |
1264 | ||
1265 | if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c') | |
1266 | return FALSE; | |
1267 | ||
1268 | op0 = XEXP (op, 0); | |
1269 | op1 = XEXP (op, 1); | |
1270 | ||
1271 | if (GET_CODE (op0) == SUBREG) | |
1272 | op0 = SUBREG_REG (op0); | |
1273 | ||
1274 | if (GET_CODE (op1) == SUBREG) | |
1275 | op1 = SUBREG_REG (op1); | |
1276 | ||
1277 | if (GET_CODE (op0) != REG) | |
1278 | return FALSE; | |
1279 | ||
1280 | /* MULT is not included here, because it is an IU only instruction. */ | |
1281 | switch (GET_CODE (op)) | |
1282 | { | |
1283 | default: | |
1284 | break; | |
1285 | ||
1286 | case AND: | |
1287 | case IOR: | |
1288 | case XOR: | |
1289 | case ASHIFTRT: | |
1290 | case LSHIFTRT: | |
1291 | case ROTATERT: | |
1292 | return (GET_MODE (op) == SImode && GPR_P (REGNO (op0)) | |
1293 | && gpr_or_constant_operand (op1, SImode)); | |
1294 | ||
1295 | case ASHIFT: | |
1296 | case ROTATE: | |
1297 | return (GET_MODE (op) == SImode && GPR_P (REGNO (op0)) | |
1298 | && GET_CODE (op1) == CONST_INT); | |
1299 | } | |
1300 | ||
1301 | return FALSE; | |
1302 | } | |
1303 | ||
1304 | /* Return true if the shift/rotate left operator can be executed with | |
1305 | conditional execution. */ | |
1306 | ||
1307 | int | |
1308 | condexec_shiftl_operator (op, mode) | |
1309 | rtx op; | |
1310 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1311 | { | |
1312 | rtx op0, op1; | |
1313 | ||
1314 | /* Only do this after register allocation, so that we can look at the register # */ | |
1315 | if (!reload_completed) | |
1316 | return FALSE; | |
1317 | ||
1318 | if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c') | |
1319 | return FALSE; | |
1320 | ||
1321 | op0 = XEXP (op, 0); | |
1322 | op1 = XEXP (op, 1); | |
1323 | ||
1324 | if (GET_CODE (op0) == SUBREG) | |
1325 | op0 = SUBREG_REG (op0); | |
1326 | ||
1327 | if (GET_CODE (op1) == SUBREG) | |
1328 | op1 = SUBREG_REG (op1); | |
1329 | ||
1330 | if (GET_CODE (op0) != REG) | |
1331 | return FALSE; | |
1332 | ||
1333 | switch (GET_CODE (op)) | |
1334 | { | |
1335 | default: | |
1336 | break; | |
1337 | ||
1338 | case ASHIFT: | |
1339 | case ROTATE: | |
1340 | return (GET_MODE (op) == SImode && GPR_P (REGNO (op0)) | |
1341 | && GET_CODE (op1) == NEG | |
1342 | && GET_CODE (XEXP (op1, 0)) == REG | |
1343 | && GPR_P (REGNO (XEXP (op1, 0)))); | |
1344 | } | |
1345 | ||
1346 | return FALSE; | |
1347 | } | |
1348 | ||
1349 | /* Return true if the {sign,zero} extend operator from memory can be | |
1350 | conditionally executed. */ | |
1351 | ||
1352 | int | |
1353 | condexec_extend_operator (op, mode) | |
1354 | rtx op; | |
1355 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1356 | { | |
1357 | /* Only do this after register allocation, so that we can look at the register # */ | |
1358 | if (!reload_completed) | |
1359 | return FALSE; | |
1360 | ||
1361 | if (GET_RTX_CLASS (GET_CODE (op)) != '1') | |
1362 | return FALSE; | |
1363 | ||
1364 | switch (GET_CODE (op)) | |
1365 | { | |
1366 | default: | |
1367 | break; | |
1368 | ||
1369 | case SIGN_EXTEND: | |
1370 | case ZERO_EXTEND: | |
1371 | if ((GET_MODE (op) == SImode && GET_MODE (XEXP (op, 0)) == QImode) | |
1372 | || (GET_MODE (op) == SImode && GET_MODE (XEXP (op, 0)) == HImode) | |
1373 | || (GET_MODE (op) == HImode && GET_MODE (XEXP (op, 0)) == QImode)) | |
1374 | return TRUE; | |
1375 | ||
1376 | break; | |
1377 | } | |
1378 | ||
1379 | return FALSE; | |
1380 | } | |
1381 | ||
1382 | /* Return true for comparisons against 0 that can be turned into a | |
1383 | bratnz/bratzr instruction. */ | |
1384 | ||
1385 | int | |
1386 | branch_zero_operator (op, mode) | |
1387 | rtx op; | |
1388 | enum machine_mode mode; | |
1389 | { | |
1390 | rtx x0, x1; | |
1391 | ||
1392 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
1393 | return FALSE; | |
1394 | ||
1395 | if (GET_CODE (op) != EQ && GET_CODE (op) != NE) | |
1396 | return FALSE; | |
1397 | ||
1398 | x0 = XEXP (op, 0); | |
1399 | if (GET_CODE (x0) != REG || !GPR_OR_PSEUDO_P (REGNO (x0))) | |
1400 | return FALSE; | |
1401 | ||
1402 | x1 = XEXP (op, 1); | |
1403 | if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0) | |
1404 | return FALSE; | |
1405 | ||
1406 | return TRUE; | |
1407 | } | |
1408 | ||
1409 | /* Return true if an operand is simple, suitable for use as the destination of | |
1410 | a conditional move */ | |
1411 | ||
1412 | int | |
1413 | cond_move_dest_operand (op, mode) | |
1414 | register rtx op; | |
1415 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1416 | { | |
1417 | rtx addr; | |
1418 | ||
1419 | if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode) | |
1420 | return FALSE; | |
1421 | ||
1422 | switch (GET_CODE (op)) | |
1423 | { | |
1424 | default: | |
1425 | break; | |
1426 | ||
1427 | case REG: | |
1428 | case SUBREG: | |
1429 | return gpr_operand (op, mode); | |
1430 | ||
1431 | /* Don't allow post dec/inc, since we might not get the side effects correct. */ | |
1432 | case MEM: | |
1433 | addr = XEXP (op, 0); | |
1434 | return (GET_CODE (addr) != POST_DEC | |
1435 | && GET_CODE (addr) != POST_INC | |
1436 | && d30v_legitimate_address_p (mode, addr, reload_completed)); | |
1437 | } | |
1438 | ||
1439 | return FALSE; | |
1440 | } | |
1441 | ||
1442 | /* Return true if an operand is simple, suitable for use in a conditional move */ | |
1443 | ||
1444 | int | |
1445 | cond_move_operand (op, mode) | |
1446 | register rtx op; | |
1447 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1448 | { | |
1449 | rtx addr; | |
1450 | ||
1451 | if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode) | |
1452 | return FALSE; | |
1453 | ||
1454 | switch (GET_CODE (op)) | |
1455 | { | |
1456 | default: | |
1457 | break; | |
1458 | ||
1459 | case REG: | |
1460 | case SUBREG: | |
1461 | return gpr_operand (op, mode); | |
1462 | ||
1463 | case CONST_DOUBLE: | |
1464 | return GET_MODE (op) == SFmode; | |
1465 | ||
1466 | case CONST_INT: | |
1467 | case SYMBOL_REF: | |
1468 | case LABEL_REF: | |
1469 | case CONST: | |
1470 | return TRUE; | |
1471 | ||
1472 | /* Don't allow post dec/inc, since we might not get the side effects correct. */ | |
1473 | case MEM: | |
1474 | addr = XEXP (op, 0); | |
1475 | return (GET_CODE (addr) != POST_DEC | |
1476 | && GET_CODE (addr) != POST_INC | |
1477 | && d30v_legitimate_address_p (mode, addr, reload_completed)); | |
1478 | } | |
1479 | ||
1480 | return FALSE; | |
1481 | } | |
1482 | ||
1483 | /* Return true if an operand is simple, suitable for use in conditional execution. | |
1484 | Unlike cond_move, we can allow auto inc/dec. */ | |
1485 | ||
1486 | int | |
1487 | cond_exec_operand (op, mode) | |
1488 | register rtx op; | |
1489 | enum machine_mode mode; | |
1490 | { | |
1491 | if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode) | |
1492 | return FALSE; | |
1493 | ||
1494 | switch (GET_CODE (op)) | |
1495 | { | |
1496 | default: | |
1497 | break; | |
1498 | ||
1499 | case REG: | |
1500 | case SUBREG: | |
1501 | return gpr_operand (op, mode); | |
1502 | ||
1503 | case CONST_DOUBLE: | |
1504 | return GET_MODE (op) == SFmode; | |
1505 | ||
1506 | case CONST_INT: | |
1507 | case SYMBOL_REF: | |
1508 | case LABEL_REF: | |
1509 | case CONST: | |
1510 | return TRUE; | |
1511 | ||
1512 | case MEM: | |
1513 | return memory_operand (op, mode); | |
1514 | } | |
1515 | ||
1516 | return FALSE; | |
1517 | } | |
1518 | ||
1519 | /* Return true if operand is a SI mode signed relational test. */ | |
1520 | ||
1521 | int | |
1522 | srelational_si_operator (op, mode) | |
1523 | register rtx op; | |
1524 | enum machine_mode mode; | |
1525 | { | |
1526 | rtx x0, x1; | |
1527 | ||
1528 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
1529 | return FALSE; | |
1530 | ||
1531 | switch (GET_CODE (op)) | |
1532 | { | |
1533 | default: | |
1534 | return FALSE; | |
1535 | ||
1536 | case EQ: | |
1537 | case NE: | |
1538 | case LT: | |
1539 | case LE: | |
1540 | case GT: | |
1541 | case GE: | |
1542 | break; | |
1543 | } | |
1544 | ||
1545 | x0 = XEXP (op, 0); | |
1546 | if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG) | |
1547 | return FALSE; | |
1548 | ||
1549 | if (GET_MODE (x0) != SImode) | |
1550 | return FALSE; | |
1551 | ||
1552 | x1 = XEXP (op, 1); | |
1553 | switch (GET_CODE (x1)) | |
1554 | { | |
1555 | default: | |
1556 | return FALSE; | |
1557 | ||
1558 | case REG: | |
1559 | case SUBREG: | |
1560 | case CONST_INT: | |
1561 | case LABEL_REF: | |
1562 | case SYMBOL_REF: | |
1563 | case CONST: | |
1564 | break; | |
1565 | } | |
1566 | ||
1567 | return TRUE; | |
1568 | } | |
1569 | ||
1570 | /* Return true if operand is a SI mode unsigned relational test. */ | |
1571 | ||
1572 | int | |
1573 | urelational_si_operator (op, mode) | |
1574 | register rtx op; | |
1575 | enum machine_mode mode; | |
1576 | { | |
1577 | rtx x0, x1; | |
1578 | ||
1579 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
1580 | return FALSE; | |
1581 | ||
1582 | switch (GET_CODE (op)) | |
1583 | { | |
1584 | default: | |
1585 | return FALSE; | |
1586 | ||
1587 | case LTU: | |
1588 | case LEU: | |
1589 | case GTU: | |
1590 | case GEU: | |
1591 | break; | |
1592 | } | |
1593 | ||
1594 | x0 = XEXP (op, 0); | |
1595 | if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG) | |
1596 | return FALSE; | |
1597 | ||
1598 | if (GET_MODE (x0) != SImode) | |
1599 | return FALSE; | |
1600 | ||
1601 | x1 = XEXP (op, 1); | |
1602 | switch (GET_CODE (x1)) | |
1603 | { | |
1604 | default: | |
1605 | return FALSE; | |
1606 | ||
1607 | case REG: | |
1608 | case SUBREG: | |
1609 | case CONST_INT: | |
1610 | case LABEL_REF: | |
1611 | case SYMBOL_REF: | |
1612 | case CONST: | |
1613 | break; | |
1614 | } | |
1615 | ||
1616 | return TRUE; | |
1617 | } | |
1618 | ||
1619 | /* Return true if operand is a DI mode relational test. */ | |
1620 | ||
1621 | int | |
1622 | relational_di_operator (op, mode) | |
1623 | register rtx op; | |
1624 | enum machine_mode mode; | |
1625 | { | |
1626 | rtx x0, x1; | |
1627 | ||
1628 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
1629 | return FALSE; | |
1630 | ||
1631 | if (GET_RTX_CLASS (GET_CODE (op)) != '<') | |
1632 | return FALSE; | |
1633 | ||
1634 | x0 = XEXP (op, 0); | |
1635 | if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG) | |
1636 | return FALSE; | |
1637 | ||
1638 | if (GET_MODE (x0) != DImode) | |
1639 | return FALSE; | |
1640 | ||
1641 | x1 = XEXP (op, 1); | |
1642 | if (GET_CODE (x1) != REG && GET_CODE (x1) != SUBREG | |
1643 | && GET_CODE (x1) != CONST_INT && GET_CODE (x1) != CONST_DOUBLE) | |
1644 | return FALSE; | |
1645 | ||
1646 | return TRUE; | |
1647 | } | |
1648 | ||
1649 | \f | |
1650 | /* Calculate the stack information for the current function. | |
1651 | ||
1652 | D30V stack frames look like: | |
1653 | ||
1654 | high | .... | | |
1655 | +-------------------------------+ | |
1656 | | Argument word #19 | | |
1657 | +-------------------------------+ | |
1658 | | Argument word #18 | | |
1659 | +-------------------------------+ | |
1660 | | Argument word #17 | | |
1661 | +-------------------------------+ | |
1662 | | Argument word #16 | | |
1663 | Prev sp +-------------------------------+ | |
1664 | | | | |
1665 | | Save for arguments 1..16 if | | |
1666 | | the func. uses stdarg/varargs | | |
1667 | | | | |
1668 | +-------------------------------+ | |
1669 | | | | |
1670 | | Save area for GPR registers | | |
1671 | | | | |
1672 | +-------------------------------+ | |
1673 | | | | |
1674 | | Save area for accumulators | | |
1675 | | | | |
1676 | +-------------------------------+ | |
1677 | | | | |
1678 | | Local variables | | |
1679 | | | | |
1680 | +-------------------------------+ | |
1681 | | | | |
1682 | | alloca space if used | | |
1683 | | | | |
1684 | +-------------------------------+ | |
1685 | | | | |
1686 | | Space for outgoing arguments | | |
1687 | | | | |
1688 | low SP----> +-------------------------------+ | |
1689 | */ | |
1690 | ||
1691 | d30v_stack_t * | |
1692 | d30v_stack_info () | |
1693 | { | |
1694 | static d30v_stack_t info, zero_info; | |
1695 | d30v_stack_t *info_ptr = &info; | |
1696 | tree fndecl = current_function_decl; | |
1697 | tree fntype = TREE_TYPE (fndecl); | |
1698 | int varargs_p = 0; | |
1699 | tree cur_arg; | |
1700 | tree next_arg; | |
1701 | int saved_gprs; | |
1702 | int saved_accs; | |
1703 | int memrefs_2words; | |
1704 | int memrefs_1word; | |
1705 | unsigned char save_gpr_p[GPR_LAST]; | |
1706 | int i; | |
1707 | ||
1708 | /* If we've already calculated the values and reload is complete, just return now */ | |
1709 | if (d30v_stack_cache) | |
1710 | return d30v_stack_cache; | |
1711 | ||
1712 | /* Zero all fields */ | |
1713 | info = zero_info; | |
1714 | ||
70f4f91c | 1715 | if (current_function_profile) |
a5c874cb RH |
1716 | regs_ever_live[GPR_LINK] = 1; |
1717 | ||
1718 | /* Determine if this is a stdarg function */ | |
1719 | if (TYPE_ARG_TYPES (fntype) != 0 | |
1720 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) != void_type_node)) | |
1721 | varargs_p = 1; | |
1722 | else | |
1723 | { | |
1724 | /* Find the last argument, and see if it is __builtin_va_alist. */ | |
1725 | for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg) | |
1726 | { | |
1727 | next_arg = TREE_CHAIN (cur_arg); | |
1728 | if (next_arg == (tree)0) | |
1729 | { | |
1730 | if (DECL_NAME (cur_arg) | |
1731 | && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist")) | |
1732 | varargs_p = 1; | |
1733 | ||
1734 | break; | |
1735 | } | |
1736 | } | |
1737 | } | |
1738 | ||
1739 | /* Calculate which registers need to be saved & save area size */ | |
1740 | saved_accs = 0; | |
1741 | memrefs_2words = 0; | |
1742 | memrefs_1word = 0; | |
1743 | for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++) | |
1744 | { | |
1745 | if (regs_ever_live[i] && !call_used_regs[i]) | |
1746 | { | |
1747 | info_ptr->save_p[i] = 2; | |
1748 | saved_accs++; | |
1749 | memrefs_2words++; | |
1750 | } | |
1751 | } | |
1752 | ||
1753 | saved_gprs = 0; | |
1754 | for (i = GPR_FIRST; i <= GPR_LAST; i++) | |
1755 | { | |
1756 | if (regs_ever_live[i] && (!call_used_regs[i] || i == GPR_LINK)) | |
1757 | { | |
1758 | save_gpr_p[i] = 1; | |
1759 | saved_gprs++; | |
1760 | } | |
1761 | else | |
1762 | save_gpr_p[i] = 0; | |
1763 | } | |
1764 | ||
1765 | /* Determine which register pairs can be saved together with ld2w/st2w */ | |
1766 | for (i = GPR_FIRST; i <= GPR_LAST; i++) | |
1767 | { | |
1768 | if (((i - GPR_FIRST) & 1) == 0 && save_gpr_p[i] && save_gpr_p[i+1]) | |
1769 | { | |
1770 | memrefs_2words++; | |
1771 | info_ptr->save_p[i++] = 2; | |
1772 | } | |
1773 | else if (save_gpr_p[i]) | |
1774 | { | |
1775 | memrefs_1word++; | |
1776 | info_ptr->save_p[i] = 1; | |
1777 | } | |
1778 | } | |
1779 | ||
1780 | /* Determine various sizes */ | |
1781 | info_ptr->varargs_p = varargs_p; | |
1782 | info_ptr->varargs_size = ((varargs_p) | |
1783 | ? (GPR_ARG_LAST + 1 - GPR_ARG_FIRST) * UNITS_PER_WORD | |
1784 | : 0); | |
1785 | ||
1786 | info_ptr->accum_size = 2 * UNITS_PER_WORD * saved_accs; | |
1787 | info_ptr->gpr_size = D30V_ALIGN (UNITS_PER_WORD * saved_gprs, | |
1788 | 2 * UNITS_PER_WORD); | |
1789 | info_ptr->vars_size = D30V_ALIGN (get_frame_size (), 2 * UNITS_PER_WORD); | |
1790 | info_ptr->parm_size = D30V_ALIGN (current_function_outgoing_args_size, | |
1791 | 2 * UNITS_PER_WORD); | |
1792 | ||
1793 | info_ptr->total_size = D30V_ALIGN ((info_ptr->gpr_size | |
1794 | + info_ptr->accum_size | |
1795 | + info_ptr->vars_size | |
1796 | + info_ptr->parm_size | |
1797 | + info_ptr->varargs_size | |
1798 | + current_function_pretend_args_size), | |
1799 | (STACK_BOUNDARY / BITS_PER_UNIT)); | |
1800 | ||
1801 | info_ptr->save_offset = (info_ptr->total_size | |
1802 | - (current_function_pretend_args_size | |
1803 | + info_ptr->varargs_size | |
1804 | + info_ptr->gpr_size | |
1805 | + info_ptr->accum_size)); | |
1806 | ||
1807 | /* The link register is the last GPR saved, but there might be some padding | |
1808 | bytes after it, so account for that. */ | |
1809 | info_ptr->link_offset = (info_ptr->total_size | |
1810 | - (current_function_pretend_args_size | |
1811 | + info_ptr->varargs_size | |
1812 | + (info_ptr->gpr_size | |
1813 | - UNITS_PER_WORD * saved_gprs) | |
1814 | + UNITS_PER_WORD)); | |
1815 | ||
1816 | info_ptr->memrefs_varargs = info_ptr->varargs_size / (2 * UNITS_PER_WORD); | |
1817 | info_ptr->memrefs_2words = memrefs_2words; | |
1818 | info_ptr->memrefs_1word = memrefs_1word; | |
1819 | ||
1820 | if (reload_completed) | |
1821 | d30v_stack_cache = info_ptr; | |
1822 | ||
1823 | return info_ptr; | |
1824 | } | |
1825 | ||
1826 | \f | |
1827 | /* Internal function to print all of the information about the stack */ | |
1828 | ||
1829 | void | |
1830 | debug_stack_info (info) | |
1831 | d30v_stack_t *info; | |
1832 | { | |
1833 | int i; | |
1834 | ||
1835 | if (!info) | |
1836 | info = d30v_stack_info (); | |
1837 | ||
1838 | fprintf (stderr, "\nStack information for function %s:\n", | |
1839 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
1840 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
1841 | : "<unknown>")); | |
1842 | ||
1843 | fprintf (stderr, "\tsave_offset = %d\n", info->save_offset); | |
1844 | fprintf (stderr, "\tmemrefs_varargs = %d\n", info->memrefs_varargs); | |
1845 | fprintf (stderr, "\tmemrefs_2words = %d\n", info->memrefs_2words); | |
1846 | fprintf (stderr, "\tmemrefs_1word = %d\n", info->memrefs_1word); | |
1847 | fprintf (stderr, "\tvarargs_p = %d\n", info->varargs_p); | |
1848 | fprintf (stderr, "\tvarargs_size = %d\n", info->varargs_size); | |
1849 | fprintf (stderr, "\tvars_size = %d\n", info->vars_size); | |
1850 | fprintf (stderr, "\tparm_size = %d\n", info->parm_size); | |
1851 | fprintf (stderr, "\tgpr_size = %d\n", info->gpr_size); | |
1852 | fprintf (stderr, "\taccum_size = %d\n", info->accum_size); | |
1853 | fprintf (stderr, "\ttotal_size = %d\n", info->total_size); | |
1854 | fprintf (stderr, "\tsaved registers ="); | |
1855 | ||
1856 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1857 | { | |
1858 | if (info->save_p[i] == 2) | |
1859 | { | |
1860 | fprintf (stderr, " %s-%s", reg_names[i], reg_names[i+1]); | |
1861 | i++; | |
1862 | } | |
1863 | else if (info->save_p[i]) | |
1864 | fprintf (stderr, " %s", reg_names[i]); | |
1865 | } | |
1866 | ||
1867 | putc ('\n', stderr); | |
1868 | fflush (stderr); | |
1869 | } | |
1870 | ||
1871 | \f | |
9cd10576 | 1872 | /* Return nonzero if this function is known to have a null or 1 instruction epilogue. */ |
a5c874cb RH |
1873 | |
1874 | int | |
1875 | direct_return () | |
1876 | { | |
1877 | if (reload_completed) | |
1878 | { | |
1879 | d30v_stack_t *info = d30v_stack_info (); | |
1880 | ||
1881 | /* If no epilogue code is needed, can use just a simple jump */ | |
1882 | if (info->total_size == 0) | |
1883 | return 1; | |
1884 | ||
1885 | #if 0 | |
1886 | /* If just a small amount of local stack was allocated and no registers | |
1887 | saved, skip forward branch */ | |
1888 | if (info->total_size == info->vars_size | |
1889 | && IN_RANGE_P (info->total_size, 1, 31)) | |
1890 | return 1; | |
1891 | #endif | |
1892 | } | |
1893 | ||
1894 | return 0; | |
1895 | } | |
1896 | ||
1897 | \f | |
1898 | /* A C statement (sans semicolon) for initializing the variable CUM for the | |
1899 | state at the beginning of the argument list. The variable has type | |
1900 | `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type | |
1901 | of the function which will receive the args, or 0 if the args are to a | |
1902 | compiler support library function. The value of INDIRECT is nonzero when | |
1903 | processing an indirect call, for example a call through a function pointer. | |
1904 | The value of INDIRECT is zero for a call to an explicitly named function, a | |
1905 | library function call, or when `INIT_CUMULATIVE_ARGS' is used to find | |
1906 | arguments for the function being compiled. | |
1907 | ||
1908 | When processing a call to a compiler support library function, LIBNAME | |
1909 | identifies which one. It is a `symbol_ref' rtx which contains the name of | |
1910 | the function, as a string. LIBNAME is 0 when an ordinary C function call is | |
1911 | being processed. Thus, each time this macro is called, either LIBNAME or | |
1912 | FNTYPE is nonzero, but never both of them at once. */ | |
1913 | ||
1914 | void | |
1915 | d30v_init_cumulative_args (cum, fntype, libname, indirect, incoming) | |
1916 | CUMULATIVE_ARGS *cum; | |
1917 | tree fntype; | |
1918 | rtx libname; | |
1919 | int indirect; | |
1920 | int incoming; | |
1921 | { | |
1922 | *cum = GPR_ARG_FIRST; | |
1923 | ||
1924 | if (TARGET_DEBUG_ARG) | |
1925 | { | |
1926 | fprintf (stderr, "\ninit_cumulative_args:"); | |
1927 | if (indirect) | |
1928 | fputs (" indirect", stderr); | |
1929 | ||
1930 | if (incoming) | |
1931 | fputs (" incoming", stderr); | |
1932 | ||
1933 | if (fntype) | |
1934 | { | |
1935 | tree ret_type = TREE_TYPE (fntype); | |
1936 | fprintf (stderr, " return=%s,", | |
1937 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
1938 | } | |
1939 | ||
1940 | if (libname && GET_CODE (libname) == SYMBOL_REF) | |
1941 | fprintf (stderr, " libname=%s", XSTR (libname, 0)); | |
1942 | ||
1943 | putc ('\n', stderr); | |
1944 | } | |
1945 | } | |
1946 | ||
1947 | \f | |
1948 | /* If defined, a C expression that gives the alignment boundary, in bits, of an | |
1949 | argument with the specified mode and type. If it is not defined, | |
1950 | `PARM_BOUNDARY' is used for all arguments. */ | |
1951 | ||
1952 | int | |
1953 | d30v_function_arg_boundary (mode, type) | |
1954 | enum machine_mode mode; | |
1955 | tree type; | |
1956 | { | |
1957 | int size = ((mode == BLKmode && type) | |
1958 | ? int_size_in_bytes (type) | |
1943c2c1 | 1959 | : (int) GET_MODE_SIZE (mode)); |
a5c874cb RH |
1960 | |
1961 | return (size > UNITS_PER_WORD) ? 2*UNITS_PER_WORD : UNITS_PER_WORD; | |
1962 | } | |
1963 | ||
1964 | \f | |
1965 | /* A C expression that controls whether a function argument is passed in a | |
1966 | register, and which register. | |
1967 | ||
1968 | The arguments are CUM, which summarizes all the previous arguments; MODE, | |
1969 | the machine mode of the argument; TYPE, the data type of the argument as a | |
1970 | tree node or 0 if that is not known (which happens for C support library | |
1971 | functions); and NAMED, which is 1 for an ordinary argument and 0 for | |
1972 | nameless arguments that correspond to `...' in the called function's | |
1973 | prototype. | |
1974 | ||
1975 | The value of the expression should either be a `reg' RTX for the hard | |
1976 | register in which to pass the argument, or zero to pass the argument on the | |
1977 | stack. | |
1978 | ||
8aeea6e6 | 1979 | For machines like the VAX and 68000, where normally all arguments are |
a5c874cb RH |
1980 | pushed, zero suffices as a definition. |
1981 | ||
1982 | The usual way to make the ANSI library `stdarg.h' work on a machine where | |
1983 | some arguments are usually passed in registers, is to cause nameless | |
1984 | arguments to be passed on the stack instead. This is done by making | |
1985 | `FUNCTION_ARG' return 0 whenever NAMED is 0. | |
1986 | ||
1987 | You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of | |
1988 | this macro to determine if this argument is of a type that must be passed in | |
1989 | the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG' | |
9cd10576 | 1990 | returns nonzero for such an argument, the compiler will abort. If |
a5c874cb RH |
1991 | `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the |
1992 | stack and then loaded into a register. */ | |
1993 | ||
1994 | rtx | |
1995 | d30v_function_arg (cum, mode, type, named, incoming) | |
1996 | CUMULATIVE_ARGS *cum; | |
1997 | enum machine_mode mode; | |
1998 | tree type; | |
1999 | int named; | |
2000 | int incoming ATTRIBUTE_UNUSED; | |
2001 | { | |
2002 | int size = ((mode == BLKmode && type) | |
2003 | ? int_size_in_bytes (type) | |
1943c2c1 | 2004 | : (int) GET_MODE_SIZE (mode)); |
a5c874cb RH |
2005 | int adjust = (size > UNITS_PER_WORD && (*cum & 1) != 0); |
2006 | rtx ret; | |
2007 | ||
2008 | /* Return a marker for use in the call instruction. */ | |
2009 | if (mode == VOIDmode) | |
2010 | ret = const0_rtx; | |
2011 | ||
2012 | else if (*cum + adjust <= GPR_ARG_LAST) | |
2013 | ret = gen_rtx (REG, mode, *cum + adjust); | |
2014 | ||
2015 | else | |
2016 | ret = NULL_RTX; | |
2017 | ||
2018 | if (TARGET_DEBUG_ARG) | |
2019 | fprintf (stderr, | |
2020 | "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, adjust = %1d, arg = %s\n", | |
2021 | *cum, GET_MODE_NAME (mode), named, size, adjust, | |
2022 | (ret) ? ((ret == const0_rtx) ? "<0>" : reg_names[ REGNO (ret) ]) : "memory"); | |
2023 | ||
2024 | return ret; | |
2025 | } | |
2026 | ||
2027 | \f | |
2028 | /* A C expression for the number of words, at the beginning of an argument, | |
2029 | must be put in registers. The value must be zero for arguments that are | |
2030 | passed entirely in registers or that are entirely pushed on the stack. | |
2031 | ||
2032 | On some machines, certain arguments must be passed partially in registers | |
2033 | and partially in memory. On these machines, typically the first N words of | |
2034 | arguments are passed in registers, and the rest on the stack. If a | |
2035 | multi-word argument (a `double' or a structure) crosses that boundary, its | |
2036 | first few words must be passed in registers and the rest must be pushed. | |
2037 | This macro tells the compiler when this occurs, and how many of the words | |
2038 | should go in registers. | |
2039 | ||
2040 | `FUNCTION_ARG' for these arguments should return the first register to be | |
2041 | used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for | |
2042 | the called function. */ | |
2043 | ||
2044 | int | |
2045 | d30v_function_arg_partial_nregs (cum, mode, type, named) | |
2046 | CUMULATIVE_ARGS *cum; | |
2047 | enum machine_mode mode; | |
2048 | tree type; | |
2049 | int named ATTRIBUTE_UNUSED; | |
2050 | { | |
2051 | int bytes = ((mode == BLKmode) | |
2052 | ? int_size_in_bytes (type) | |
1943c2c1 | 2053 | : (int) GET_MODE_SIZE (mode)); |
a5c874cb RH |
2054 | int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; |
2055 | int adjust = (bytes > UNITS_PER_WORD && (*cum & 1) != 0); | |
2056 | int arg_num = *cum + adjust; | |
2057 | int ret; | |
2058 | ||
2059 | ret = ((arg_num <= GPR_ARG_LAST && arg_num + words > GPR_ARG_LAST+1) | |
2060 | ? GPR_ARG_LAST - arg_num + 1 | |
2061 | : 0); | |
2062 | ||
2063 | if (TARGET_DEBUG_ARG && ret) | |
2064 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
2065 | ||
2066 | return ret; | |
2067 | } | |
2068 | ||
2069 | \f | |
2070 | /* A C expression that indicates when an argument must be passed by reference. | |
2071 | If nonzero for an argument, a copy of that argument is made in memory and a | |
2072 | pointer to the argument is passed instead of the argument itself. The | |
2073 | pointer is passed in whatever way is appropriate for passing a pointer to | |
2074 | that type. | |
2075 | ||
2076 | On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable | |
2077 | definition of this macro might be | |
2078 | #define FUNCTION_ARG_PASS_BY_REFERENCE\ | |
2079 | (CUM, MODE, TYPE, NAMED) \ | |
2080 | MUST_PASS_IN_STACK (MODE, TYPE) */ | |
2081 | ||
2082 | int | |
2083 | d30v_function_arg_pass_by_reference (cum, mode, type, named) | |
2084 | CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; | |
2085 | enum machine_mode mode; | |
2086 | tree type; | |
2087 | int named ATTRIBUTE_UNUSED; | |
2088 | { | |
2089 | int ret = MUST_PASS_IN_STACK (mode, type); | |
2090 | ||
2091 | if (TARGET_DEBUG_ARG && ret) | |
2092 | fprintf (stderr, "function_arg_pass_by_reference: %d\n", ret); | |
2093 | ||
2094 | return ret; | |
2095 | } | |
2096 | ||
2097 | \f | |
2098 | /* A C statement (sans semicolon) to update the summarizer variable CUM to | |
2099 | advance past an argument in the argument list. The values MODE, TYPE and | |
2100 | NAMED describe that argument. Once this is done, the variable CUM is | |
2101 | suitable for analyzing the *following* argument with `FUNCTION_ARG', etc. | |
2102 | ||
2103 | This macro need not do anything if the argument in question was passed on | |
2104 | the stack. The compiler knows how to track the amount of stack space used | |
2105 | for arguments without any special help. */ | |
2106 | ||
2107 | void | |
2108 | d30v_function_arg_advance (cum, mode, type, named) | |
2109 | CUMULATIVE_ARGS *cum; | |
2110 | enum machine_mode mode; | |
2111 | tree type; | |
2112 | int named; | |
2113 | { | |
2114 | int bytes = ((mode == BLKmode) | |
2115 | ? int_size_in_bytes (type) | |
1943c2c1 | 2116 | : (int) GET_MODE_SIZE (mode)); |
a5c874cb RH |
2117 | int words = D30V_ALIGN (bytes, UNITS_PER_WORD) / UNITS_PER_WORD; |
2118 | int adjust = (bytes > UNITS_PER_WORD && (*cum & 1) != 0); | |
2119 | ||
2120 | *cum += words + adjust; | |
2121 | ||
2122 | if (TARGET_DEBUG_ARG) | |
2123 | fprintf (stderr, | |
2124 | "function_adv: words = %2d, mode = %4s, named = %d, size = %3d, adjust = %1d\n", | |
2125 | *cum, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD, adjust); | |
2126 | } | |
2127 | ||
2128 | \f | |
2129 | /* If defined, is a C expression that produces the machine-specific code for a | |
2130 | call to `__builtin_saveregs'. This code will be moved to the very beginning | |
2131 | of the function, before any parameter access are made. The return value of | |
2132 | this function should be an RTX that contains the value to use as the return | |
2133 | of `__builtin_saveregs'. | |
2134 | ||
2135 | If this macro is not defined, the compiler will output an ordinary call to | |
2136 | the library function `__builtin_saveregs'. */ | |
2137 | ||
2138 | rtx | |
2139 | d30v_expand_builtin_saveregs () | |
2140 | { | |
2141 | int offset = UNITS_PER_WORD * (GPR_ARG_LAST + 1 - GPR_ARG_FIRST); | |
2142 | ||
2143 | if (TARGET_DEBUG_ARG) | |
2144 | fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n", | |
2145 | offset); | |
2146 | ||
2147 | return gen_rtx (PLUS, Pmode, virtual_incoming_args_rtx, GEN_INT (- offset)); | |
2148 | } | |
2149 | ||
2150 | \f | |
2151 | /* This macro offers an alternative to using `__builtin_saveregs' and defining | |
2152 | the macro `EXPAND_BUILTIN_SAVEREGS'. Use it to store the anonymous register | |
2153 | arguments into the stack so that all the arguments appear to have been | |
2154 | passed consecutively on the stack. Once this is done, you can use the | |
2155 | standard implementation of varargs that works for machines that pass all | |
2156 | their arguments on the stack. | |
2157 | ||
2158 | The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure, containing | |
2159 | the values that obtain after processing of the named arguments. The | |
2160 | arguments MODE and TYPE describe the last named argument--its machine mode | |
2161 | and its data type as a tree node. | |
2162 | ||
2163 | The macro implementation should do two things: first, push onto the stack | |
2164 | all the argument registers *not* used for the named arguments, and second, | |
2165 | store the size of the data thus pushed into the `int'-valued variable whose | |
2166 | name is supplied as the argument PRETEND_ARGS_SIZE. The value that you | |
2167 | store here will serve as additional offset for setting up the stack frame. | |
2168 | ||
2169 | Because you must generate code to push the anonymous arguments at compile | |
2170 | time without knowing their data types, `SETUP_INCOMING_VARARGS' is only | |
2171 | useful on machines that have just a single category of argument register and | |
2172 | use it uniformly for all data types. | |
2173 | ||
2174 | If the argument SECOND_TIME is nonzero, it means that the arguments of the | |
2175 | function are being analyzed for the second time. This happens for an inline | |
2176 | function, which is not actually compiled until the end of the source file. | |
2177 | The macro `SETUP_INCOMING_VARARGS' should not generate any instructions in | |
2178 | this case. */ | |
2179 | ||
2180 | void | |
2181 | d30v_setup_incoming_varargs (cum, mode, type, pretend_size, second_time) | |
2182 | CUMULATIVE_ARGS *cum; | |
2183 | enum machine_mode mode; | |
2184 | tree type ATTRIBUTE_UNUSED; | |
2185 | int *pretend_size ATTRIBUTE_UNUSED; | |
2186 | int second_time; | |
2187 | { | |
2188 | if (TARGET_DEBUG_ARG) | |
2189 | fprintf (stderr, | |
2190 | "setup_vararg: words = %2d, mode = %4s, second_time = %d\n", | |
2191 | *cum, GET_MODE_NAME (mode), second_time); | |
2192 | } | |
2193 | ||
2194 | \f | |
2195 | /* Create the va_list data type. */ | |
2196 | ||
2197 | tree | |
2198 | d30v_build_va_list () | |
2199 | { | |
2200 | tree f_arg_ptr, f_arg_num, record, type_decl; | |
2201 | tree int_type_node; | |
2202 | ||
f1e639b1 | 2203 | record = (*lang_hooks.types.make_type) (RECORD_TYPE); |
a5c874cb RH |
2204 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
2205 | int_type_node = make_signed_type (INT_TYPE_SIZE); | |
2206 | ||
2207 | f_arg_ptr = build_decl (FIELD_DECL, get_identifier ("__va_arg_ptr"), | |
2208 | ptr_type_node); | |
2209 | f_arg_num = build_decl (FIELD_DECL, get_identifier ("__va_arg_num"), | |
2210 | int_type_node); | |
2211 | ||
2212 | DECL_FIELD_CONTEXT (f_arg_ptr) = record; | |
2213 | DECL_FIELD_CONTEXT (f_arg_num) = record; | |
2214 | ||
2215 | TREE_CHAIN (record) = type_decl; | |
2216 | TYPE_NAME (record) = type_decl; | |
2217 | TYPE_FIELDS (record) = f_arg_ptr; | |
2218 | TREE_CHAIN (f_arg_ptr) = f_arg_num; | |
2219 | ||
2220 | layout_type (record); | |
2221 | ||
2222 | /* The correct type is an array type of one element. */ | |
2223 | return build_array_type (record, build_index_type (size_zero_node)); | |
2224 | } | |
2225 | ||
2226 | \f | |
2227 | /* Expand __builtin_va_start to do the va_start macro. */ | |
2228 | ||
2229 | void | |
e5faf155 | 2230 | d30v_expand_builtin_va_start (valist, nextarg) |
a5c874cb RH |
2231 | tree valist; |
2232 | rtx nextarg ATTRIBUTE_UNUSED; | |
2233 | { | |
2234 | HOST_WIDE_INT words; | |
2235 | tree f_arg_ptr, f_arg_num; | |
2236 | tree arg_ptr, arg_num, saveregs, t; | |
2237 | ||
2238 | f_arg_ptr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); | |
2239 | f_arg_num = TREE_CHAIN (f_arg_ptr); | |
2240 | ||
2241 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); | |
2242 | arg_ptr = build (COMPONENT_REF, TREE_TYPE (f_arg_ptr), valist, f_arg_ptr); | |
2243 | arg_num = build (COMPONENT_REF, TREE_TYPE (f_arg_num), valist, f_arg_num); | |
2244 | ||
2245 | words = current_function_args_info; /* __builtin_args_info (0) */ | |
2246 | ||
2247 | /* (AP)->__va_arg_ptr = (int *) __builtin_saveregs (); */ | |
2248 | saveregs = make_tree (TREE_TYPE (arg_ptr), d30v_expand_builtin_saveregs ()); | |
2249 | t = build (MODIFY_EXPR, TREE_TYPE (arg_ptr), arg_ptr, saveregs); | |
2250 | TREE_SIDE_EFFECTS (t) = 1; | |
2251 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2252 | ||
2253 | /* (AP)->__va_arg_num = __builtin_args_info (0) - 2; */ | |
2254 | t = build (PLUS_EXPR, TREE_TYPE (arg_num), build_int_2 (words, 0), | |
2255 | build_int_2 (-GPR_ARG_FIRST, 0)); | |
2256 | t = build (MODIFY_EXPR, TREE_TYPE (arg_num), arg_num, t); | |
2257 | TREE_SIDE_EFFECTS (t) = 1; | |
2258 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2259 | } | |
2260 | ||
2261 | \f | |
2262 | /* Expand __builtin_va_arg to do the va_arg macro. */ | |
2263 | ||
2264 | rtx | |
2265 | d30v_expand_builtin_va_arg(valist, type) | |
2266 | tree valist; | |
2267 | tree type; | |
2268 | { | |
2269 | tree f_arg_ptr, f_arg_num; | |
2270 | tree arg_ptr, arg_num, t, ptr; | |
2271 | int num, size; | |
2272 | rtx lab_false, ptr_rtx, r; | |
2273 | ||
2274 | f_arg_ptr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); | |
2275 | f_arg_num = TREE_CHAIN (f_arg_ptr); | |
2276 | ||
2277 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); | |
2278 | arg_ptr = build (COMPONENT_REF, TREE_TYPE (f_arg_ptr), valist, f_arg_ptr); | |
2279 | arg_num = build (COMPONENT_REF, TREE_TYPE (f_arg_num), valist, f_arg_num); | |
2280 | ||
2281 | size = int_size_in_bytes (type); | |
2282 | ||
2283 | lab_false = gen_label_rtx (); | |
2284 | ptr_rtx = gen_reg_rtx (Pmode); | |
2285 | ||
2286 | /* if (sizeof (TYPE) > 4 && ((AP)->__va_arg_num & 1) != 0) | |
2287 | (AP)->__va_arg_num++; */ | |
2288 | ||
2289 | if (size > UNITS_PER_WORD) | |
2290 | { | |
2291 | t = build (BIT_AND_EXPR, TREE_TYPE (arg_num), arg_num, | |
2292 | build_int_2 (1, 0)); | |
2293 | ||
2294 | emit_cmp_and_jump_insns (expand_expr (t, NULL_RTX, QImode, EXPAND_NORMAL), | |
a06ef755 | 2295 | GEN_INT (0), EQ, const1_rtx, QImode, 1, |
a5c874cb RH |
2296 | lab_false); |
2297 | ||
2298 | t = build (POSTINCREMENT_EXPR, TREE_TYPE (arg_num), arg_num, | |
2299 | build_int_2 (1, 0)); | |
2300 | TREE_SIDE_EFFECTS (t) = 1; | |
2301 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2302 | ||
2303 | emit_label (lab_false); | |
2304 | } | |
2305 | ||
2306 | ||
2307 | /* __ptr = (TYPE *)(((char *)(void *)((AP)->__va_arg_ptr | |
2308 | + (AP)->__va_arg_num))); */ | |
2309 | ||
2310 | t = build (MULT_EXPR, TREE_TYPE (arg_num), arg_num, build_int_2 (4, 0)); | |
2311 | t = build (PLUS_EXPR, ptr_type_node, arg_ptr, t); | |
2312 | ||
2313 | /* if (sizeof (TYPE) < 4) | |
2314 | __ptr = (void *)__ptr + 4 - sizeof (TYPE); */ | |
2315 | ||
2316 | if (size < UNITS_PER_WORD) | |
2317 | t = build (PLUS_EXPR, ptr_type_node, t, | |
2318 | build_int_2 (UNITS_PER_WORD - size, 0)); | |
2319 | ||
2320 | TREE_SIDE_EFFECTS (t) = 1; | |
2321 | ||
2322 | ptr = build1 (NOP_EXPR, build_pointer_type (type), t); | |
2323 | t = build (MODIFY_EXPR, type, ptr, t); | |
2324 | ||
2325 | r = expand_expr (t, ptr_rtx, Pmode, EXPAND_NORMAL); | |
2326 | if (r != ptr_rtx) | |
2327 | emit_move_insn (ptr_rtx, r); | |
2328 | ||
2329 | ||
2330 | /* (AP)->__va_arg_num += (sizeof (TYPE) + 3) / 4; */ | |
2331 | num = (size + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD; | |
2332 | t = build (POSTINCREMENT_EXPR, TREE_TYPE (arg_num), arg_num, | |
2333 | build_int_2 (num, 0)); | |
2334 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2335 | ||
2336 | return ptr_rtx; | |
2337 | } | |
2338 | \f | |
08c148a8 NB |
2339 | /* Generate the assembly code for function entry. FILE is a stdio |
2340 | stream to output the code to. SIZE is an int: how many units of | |
2341 | temporary storage to allocate. | |
a5c874cb | 2342 | |
08c148a8 NB |
2343 | Refer to the array `regs_ever_live' to determine which registers to |
2344 | save; `regs_ever_live[I]' is nonzero if register number I is ever | |
2345 | used in the function. This function is responsible for knowing | |
2346 | which registers should not be saved even if used. */ | |
2347 | ||
2348 | static void | |
2349 | d30v_output_function_prologue (stream, size) | |
a5c874cb | 2350 | FILE *stream ATTRIBUTE_UNUSED; |
08c148a8 | 2351 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
a5c874cb | 2352 | { |
08c148a8 NB |
2353 | /* For the d30v, move all of the prologue processing into separate |
2354 | insns. */ | |
a5c874cb RH |
2355 | } |
2356 | ||
2357 | \f | |
08c148a8 NB |
2358 | /* Called after register allocation to add any instructions needed for |
2359 | the prologue. Using a prologue insn is favored compared to putting | |
2360 | all of the instructions in output_function_prologue (), since it | |
2361 | allows the scheduler to intermix instructions with the saves of the | |
2362 | caller saved registers. In some cases, it might be necessary to | |
2363 | emit a barrier instruction as the last insn to prevent such | |
2364 | scheduling. */ | |
a5c874cb RH |
2365 | |
2366 | void | |
2367 | d30v_expand_prologue () | |
2368 | { | |
2369 | rtx sp = stack_pointer_rtx; | |
2370 | d30v_stack_t *info = d30v_stack_info (); | |
2371 | int i; | |
2372 | rtx mem_di = NULL_RTX; | |
2373 | rtx mem_si = NULL_RTX; | |
2374 | int num_memrefs = (info->memrefs_2words | |
2375 | + info->memrefs_1word | |
2376 | + info->memrefs_varargs); | |
2377 | ||
2378 | if (TARGET_DEBUG_STACK) | |
2379 | debug_stack_info (info); | |
2380 | ||
2381 | /* Grow the stack. */ | |
2382 | if (info->total_size) | |
2383 | emit_insn (gen_addsi3 (sp, sp, GEN_INT (- info->total_size))); | |
2384 | ||
2385 | /* If there is more than one save, use post-increment addressing which will | |
2386 | result in smaller code, than would the normal references. If there is | |
2387 | only one save, just do the store as normal. */ | |
2388 | ||
2389 | if (num_memrefs > 1) | |
2390 | { | |
2391 | rtx save_tmp = gen_rtx (REG, Pmode, GPR_STACK_TMP); | |
2392 | rtx post_inc = gen_rtx (POST_INC, Pmode, save_tmp); | |
2393 | mem_di = gen_rtx (MEM, DImode, post_inc); | |
2394 | mem_si = gen_rtx (MEM, SImode, post_inc); | |
2395 | emit_insn (gen_addsi3 (save_tmp, sp, GEN_INT (info->save_offset))); | |
2396 | } | |
2397 | else if (num_memrefs == 1) | |
2398 | { | |
2399 | rtx addr = plus_constant (sp, info->save_offset); | |
2400 | mem_di = gen_rtx (MEM, DImode, addr); | |
2401 | mem_si = gen_rtx (MEM, SImode, addr); | |
2402 | } | |
2403 | ||
2404 | /* Save the accumulators. */ | |
2405 | for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++) | |
2406 | if (info->save_p[i]) | |
2407 | { | |
2408 | rtx acc_tmp = gen_rtx (REG, DImode, GPR_ATMP_FIRST); | |
2409 | emit_insn (gen_movdi (acc_tmp, gen_rtx (REG, DImode, i))); | |
2410 | emit_insn (gen_movdi (mem_di, acc_tmp)); | |
2411 | } | |
2412 | ||
2413 | /* Save the GPR registers that are adjacent to each other with st2w. */ | |
2414 | for (i = GPR_FIRST; i <= GPR_LAST; i += 2) | |
2415 | if (info->save_p[i] == 2) | |
2416 | emit_insn (gen_movdi (mem_di, gen_rtx (REG, DImode, i))); | |
2417 | ||
2418 | /* Save the GPR registers that need to be saved with a single word store. */ | |
2419 | for (i = GPR_FIRST; i <= GPR_LAST; i++) | |
2420 | if (info->save_p[i] == 1) | |
2421 | emit_insn (gen_movsi (mem_si, gen_rtx (REG, SImode, i))); | |
2422 | ||
2423 | /* Save the argument registers if this function accepts variable args. */ | |
2424 | if (info->varargs_p) | |
2425 | { | |
2426 | /* Realign r22 if an odd # of GPRs were saved. */ | |
2427 | if ((info->memrefs_1word & 1) != 0) | |
2428 | { | |
2429 | rtx save_tmp = XEXP (XEXP (mem_si, 0), 0); | |
2430 | emit_insn (gen_addsi3 (save_tmp, save_tmp, GEN_INT (UNITS_PER_WORD))); | |
2431 | } | |
2432 | ||
2433 | for (i = GPR_ARG_FIRST; i <= GPR_ARG_LAST; i += 2) | |
2434 | emit_insn (gen_movdi (mem_di, gen_rtx (REG, DImode, i))); | |
2435 | } | |
2436 | ||
2437 | /* Update the frame pointer. */ | |
2438 | if (frame_pointer_needed) | |
2439 | emit_move_insn (frame_pointer_rtx, sp); | |
2440 | ||
2441 | /* Hack for now, to prevent scheduler from being too cleaver */ | |
2442 | emit_insn (gen_blockage ()); | |
2443 | } | |
2444 | ||
2445 | \f | |
08c148a8 NB |
2446 | /* This function generates the assembly code for function exit. |
2447 | Args are as for output_function_prologue (). | |
2448 | ||
2449 | The function epilogue should not depend on the current stack | |
2450 | pointer! It should use the frame pointer only. This is mandatory | |
2451 | because of alloca; we also take advantage of it to omit stack | |
2452 | adjustments before returning. */ | |
2453 | ||
2454 | static void | |
2455 | d30v_output_function_epilogue (stream, size) | |
a5c874cb | 2456 | FILE *stream ATTRIBUTE_UNUSED; |
08c148a8 | 2457 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
a5c874cb | 2458 | { |
08c148a8 NB |
2459 | /* For the d30v, move all processing to be as insns, but do any |
2460 | cleanup here, since it is done after handling all of the insns. */ | |
a5c874cb RH |
2461 | d30v_stack_cache = (d30v_stack_t *)0; /* reset stack cache */ |
2462 | } | |
2463 | ||
2464 | \f | |
2465 | ||
08c148a8 | 2466 | /* Called after register allocation to add any instructions needed for |
5519a4f9 | 2467 | the epilogue. Using an epilogue insn is favored compared to putting |
08c148a8 NB |
2468 | all of the instructions in output_function_prologue(), since it |
2469 | allows the scheduler to intermix instructions with the saves of the | |
2470 | caller saved registers. In some cases, it might be necessary to | |
2471 | emit a barrier instruction as the last insn to prevent such | |
2472 | scheduling. */ | |
a5c874cb RH |
2473 | |
2474 | void | |
2475 | d30v_expand_epilogue () | |
2476 | { | |
2477 | rtx sp = stack_pointer_rtx; | |
2478 | d30v_stack_t *info = d30v_stack_info (); | |
2479 | int i; | |
2480 | rtx mem_di = NULL_RTX; | |
2481 | rtx mem_si = NULL_RTX; | |
2482 | rtx post_inc; | |
2483 | int extra_stack; | |
2484 | ||
2485 | /* Hack for now, to prevent scheduler from being too cleaver */ | |
2486 | emit_insn (gen_blockage ()); | |
2487 | ||
2488 | /* Restore sp from fp. */ | |
2489 | if (frame_pointer_needed) | |
2490 | emit_move_insn (sp, frame_pointer_rtx); | |
2491 | ||
2492 | /* For the epilogue, use post-increment addressing all of the time. First | |
2493 | adjust the sp, to eliminate all of the stack, except for the save area. */ | |
2494 | ||
2495 | if (info->save_offset) | |
2496 | emit_insn (gen_addsi3 (sp, sp, GEN_INT (info->save_offset))); | |
2497 | ||
2498 | post_inc = gen_rtx (POST_INC, Pmode, sp); | |
2499 | mem_di = gen_rtx (MEM, DImode, post_inc); | |
2500 | mem_si = gen_rtx (MEM, SImode, post_inc); | |
2501 | ||
2502 | /* Restore the accumulators. */ | |
2503 | for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++) | |
2504 | if (info->save_p[i]) | |
2505 | { | |
2506 | rtx acc_tmp = gen_rtx (REG, DImode, GPR_ATMP_FIRST); | |
2507 | emit_insn (gen_movdi (acc_tmp, mem_di)); | |
2508 | emit_insn (gen_movdi (gen_rtx (REG, DImode, i), acc_tmp)); | |
2509 | } | |
2510 | ||
2511 | /* Restore the GPR registers that are adjacent to each other with ld2w. */ | |
2512 | for (i = GPR_FIRST; i <= GPR_LAST; i += 2) | |
2513 | if (info->save_p[i] == 2) | |
2514 | emit_insn (gen_movdi (gen_rtx (REG, DImode, i), mem_di)); | |
2515 | ||
2516 | /* Save the GPR registers that need to be saved with a single word store. */ | |
2517 | extra_stack = 0; | |
2518 | for (i = GPR_FIRST; i <= GPR_LAST; i++) | |
2519 | if (info->save_p[i] == 1) | |
2520 | { | |
a2e11fd9 | 2521 | if (cfun->machine->eh_epilogue_sp_ofs && i == GPR_LINK) |
a5c874cb RH |
2522 | extra_stack = 4; |
2523 | else | |
2524 | { | |
2525 | if (extra_stack) | |
2526 | { | |
2527 | emit_insn (gen_addsi3 (sp, sp, GEN_INT (extra_stack))); | |
2528 | extra_stack = 0; | |
2529 | } | |
2530 | emit_insn (gen_movsi (gen_rtx (REG, SImode, i), mem_si)); | |
2531 | } | |
2532 | } | |
2533 | ||
2534 | /* Release any remaining stack that was allocated for saving the | |
2535 | varargs registers or because an odd # of registers were stored. */ | |
2536 | if ((info->memrefs_1word & 1) != 0) | |
2537 | extra_stack += UNITS_PER_WORD; | |
2538 | extra_stack += current_function_pretend_args_size + info->varargs_size; | |
2539 | ||
2540 | if (extra_stack) | |
2541 | { | |
a2e11fd9 NC |
2542 | if (cfun->machine->eh_epilogue_sp_ofs) |
2543 | emit_insn (gen_addsi3 (cfun->machine->eh_epilogue_sp_ofs, | |
2544 | cfun->machine->eh_epilogue_sp_ofs, | |
a5c874cb RH |
2545 | GEN_INT (extra_stack))); |
2546 | else | |
2547 | emit_insn (gen_addsi3 (sp, sp, GEN_INT (extra_stack))); | |
2548 | } | |
a2e11fd9 NC |
2549 | if (cfun->machine->eh_epilogue_sp_ofs) |
2550 | emit_insn (gen_addsi3 (sp, sp, cfun->machine->eh_epilogue_sp_ofs)); | |
a5c874cb RH |
2551 | |
2552 | /* Now emit the return instruction. */ | |
2553 | emit_jump_insn (gen_rtx_RETURN (VOIDmode)); | |
2554 | } | |
2555 | ||
2556 | \f | |
2557 | /* A C statement or compound statement to output to FILE some assembler code to | |
2558 | call the profiling subroutine `mcount'. Before calling, the assembler code | |
2559 | must load the address of a counter variable into a register where `mcount' | |
2560 | expects to find the address. The name of this variable is `LP' followed by | |
2561 | the number LABELNO, so you would generate the name using `LP%d' in a | |
2562 | `fprintf'. | |
2563 | ||
2564 | The details of how the address should be passed to `mcount' are determined | |
2565 | by your operating system environment, not by GNU CC. To figure them out, | |
2566 | compile a small program for profiling using the system's installed C | |
2567 | compiler and look at the assembler code that results. */ | |
2568 | ||
2569 | void | |
2570 | d30v_function_profiler (stream, labelno) | |
2571 | FILE *stream; | |
2572 | int labelno ATTRIBUTE_UNUSED; | |
2573 | { | |
2574 | fprintf (stream, "# profile\n"); | |
2575 | } | |
2576 | ||
2577 | \f | |
2578 | /* Split a 64 bit item into an upper and a lower part. We specifically do not | |
2579 | want to call gen_highpart/gen_lowpart on CONST_DOUBLEs since it will give us | |
2580 | the wrong part for floating point in cross compilers, and split_double does | |
2581 | not handle registers. Also abort if the register is not a general purpose | |
2582 | register. */ | |
2583 | ||
2584 | void | |
2585 | d30v_split_double (value, p_high, p_low) | |
2586 | rtx value; | |
2587 | rtx *p_high; | |
2588 | rtx *p_low; | |
2589 | { | |
2590 | int offset = 0; | |
2591 | int regno; | |
2592 | ||
2593 | if (!reload_completed) | |
2594 | abort (); | |
2595 | ||
2596 | switch (GET_CODE (value)) | |
2597 | { | |
2598 | case SUBREG: | |
ddef6bc7 | 2599 | if (GET_CODE (SUBREG_REG (value)) != REG) |
a5c874cb | 2600 | abort (); |
ddef6bc7 JJ |
2601 | offset = subreg_regno_offset (REGNO (SUBREG_REG (value)), |
2602 | GET_MODE (SUBREG_REG (value)), | |
2603 | SUBREG_BYTE (value), | |
2604 | GET_MODE (value)); | |
2605 | value = SUBREG_REG (value); | |
a5c874cb RH |
2606 | |
2607 | /* fall through */ | |
2608 | ||
2609 | case REG: | |
2610 | regno = REGNO (value) + offset; | |
2611 | if (!GPR_P (regno)) | |
2612 | abort (); | |
2613 | ||
2614 | *p_high = gen_rtx (REG, SImode, regno); | |
2615 | *p_low = gen_rtx (REG, SImode, regno+1); | |
2616 | break; | |
2617 | ||
2618 | case CONST_INT: | |
2619 | case CONST_DOUBLE: | |
2620 | split_double (value, p_high, p_low); | |
2621 | break; | |
2622 | ||
2623 | default: | |
2624 | abort (); | |
2625 | } | |
2626 | } | |
2627 | ||
2628 | \f | |
2629 | /* A C compound statement to output to stdio stream STREAM the assembler syntax | |
2630 | for an instruction operand that is a memory reference whose address is X. X | |
fb49053f | 2631 | is an RTL expression. */ |
a5c874cb RH |
2632 | |
2633 | void | |
2634 | d30v_print_operand_address (stream, x) | |
2635 | FILE *stream; | |
2636 | rtx x; | |
2637 | { | |
2638 | if (GET_CODE (x) == MEM) | |
2639 | x = XEXP (x, 0); | |
2640 | ||
2641 | switch (GET_CODE (x)) | |
2642 | { | |
2643 | default: | |
2644 | break; | |
2645 | ||
2646 | case REG: | |
2647 | fputs (reg_names[ REGNO (x) ], stream); | |
2648 | return; | |
2649 | ||
2650 | case CONST_INT: | |
2651 | fprintf (stream, "%ld", (long) INTVAL (x)); | |
2652 | return; | |
2653 | ||
2654 | /* We wrap simple symbol refs inside a parenthesis, so that a name | |
2655 | like `r2' is not taken for a register name. */ | |
2656 | case SYMBOL_REF: | |
2657 | fputs ("(", stream); | |
2658 | assemble_name (stream, XSTR (x, 0)); | |
2659 | fputs (")", stream); | |
2660 | return; | |
2661 | ||
2662 | case LABEL_REF: | |
2663 | case CONST: | |
2664 | output_addr_const (stream, x); | |
2665 | return; | |
2666 | } | |
2667 | ||
c725bd79 | 2668 | fatal_insn ("bad insn to d30v_print_operand_address:", x); |
a5c874cb RH |
2669 | } |
2670 | ||
2671 | \f | |
2672 | /* Print a memory reference suitable for the ld/st instructions. */ | |
2673 | ||
2674 | static void | |
2675 | d30v_print_operand_memory_reference (stream, x) | |
2676 | FILE *stream; | |
2677 | rtx x; | |
2678 | { | |
2679 | rtx x0 = NULL_RTX; | |
2680 | rtx x1 = NULL_RTX; | |
2681 | ||
2682 | switch (GET_CODE (x)) | |
2683 | { | |
2684 | default: | |
c725bd79 | 2685 | fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x); |
a5c874cb RH |
2686 | break; |
2687 | ||
2688 | case SUBREG: | |
2689 | case REG: | |
2690 | case POST_DEC: | |
2691 | case POST_INC: | |
2692 | x0 = x; | |
2693 | break; | |
2694 | ||
2695 | case CONST_INT: | |
2696 | case SYMBOL_REF: | |
2697 | case LABEL_REF: | |
2698 | case CONST: | |
2699 | x1 = x; | |
2700 | break; | |
2701 | ||
2702 | case PLUS: | |
2703 | x0 = XEXP (x, 0); | |
2704 | x1 = XEXP (x, 1); | |
2705 | if (GET_CODE (x0) == CONST_INT || GET_CODE (x0) == SYMBOL_REF | |
2706 | || GET_CODE (x0) == CONST || GET_CODE (x0) == LABEL_REF) | |
2707 | { | |
2708 | x0 = XEXP (x, 1); | |
2709 | x1 = XEXP (x, 0); | |
2710 | } | |
2711 | break; | |
2712 | } | |
2713 | ||
2714 | fputs ("@(", stream); | |
2715 | if (!x0) | |
2716 | fputs (reg_names[GPR_R0], stream); | |
2717 | ||
2718 | else | |
2719 | { | |
1943c2c1 | 2720 | const char *suffix = ""; |
a5c874cb RH |
2721 | int offset0 = 0; |
2722 | ||
2723 | if (GET_CODE (x0) == SUBREG) | |
2724 | { | |
ddef6bc7 JJ |
2725 | offset0 = subreg_regno_offset (REGNO (SUBREG_REG (x0)), |
2726 | GET_MODE (SUBREG_REG (x0)), | |
2727 | SUBREG_BYTE (x0), | |
2728 | GET_MODE (x0)); | |
a5c874cb RH |
2729 | x0 = SUBREG_REG (x0); |
2730 | } | |
2731 | ||
2732 | if (GET_CODE (x0) == POST_INC) | |
2733 | { | |
2734 | x0 = XEXP (x0, 0); | |
2735 | suffix = "+"; | |
2736 | } | |
2737 | else if (GET_CODE (x0) == POST_DEC) | |
2738 | { | |
2739 | x0 = XEXP (x0, 0); | |
2740 | suffix = "-"; | |
2741 | } | |
2742 | ||
2743 | if (GET_CODE (x0) == REG && GPR_P (REGNO (x0))) | |
2744 | fprintf (stream, "%s%s", reg_names[REGNO (x0) + offset0], suffix); | |
2745 | else | |
c725bd79 | 2746 | fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x); |
a5c874cb RH |
2747 | } |
2748 | ||
2749 | fputs (",", stream); | |
2750 | ||
2751 | if (!x1) | |
2752 | fputs (reg_names[GPR_R0], stream); | |
2753 | ||
2754 | else | |
2755 | { | |
2756 | int offset1 = 0; | |
2757 | ||
2758 | switch (GET_CODE (x1)) | |
2759 | { | |
2760 | case SUBREG: | |
ddef6bc7 JJ |
2761 | offset1 = subreg_regno_offset (REGNO (SUBREG_REG (x1)), |
2762 | GET_MODE (SUBREG_REG (x1)), | |
2763 | SUBREG_BYTE (x1), | |
2764 | GET_MODE (x1)); | |
a5c874cb RH |
2765 | x1 = SUBREG_REG (x1); |
2766 | if (GET_CODE (x1) != REG) | |
c725bd79 | 2767 | fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x); |
a5c874cb RH |
2768 | |
2769 | /* fall through */ | |
2770 | case REG: | |
2771 | fputs (reg_names[REGNO (x1) + offset1], stream); | |
2772 | break; | |
2773 | ||
2774 | case CONST_INT: | |
2775 | fprintf (stream, "%ld", (long) INTVAL (x1)); | |
2776 | break; | |
2777 | ||
2778 | case SYMBOL_REF: | |
2779 | case LABEL_REF: | |
2780 | case CONST: | |
2781 | d30v_print_operand_address (stream, x1); | |
2782 | break; | |
2783 | ||
2784 | default: | |
c725bd79 | 2785 | fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x); |
a5c874cb RH |
2786 | } |
2787 | } | |
2788 | ||
2789 | fputs (")", stream); | |
2790 | } | |
2791 | ||
2792 | \f | |
2793 | /* A C compound statement to output to stdio stream STREAM the assembler syntax | |
2794 | for an instruction operand X. X is an RTL expression. | |
2795 | ||
2796 | LETTER is a value that can be used to specify one of several ways of | |
2797 | printing the operand. It is used when identical operands must be printed | |
2798 | differently depending on the context. LETTER comes from the `%' | |
2799 | specification that was used to request printing of the operand. If the | |
2800 | specification was just `%DIGIT' then LETTER is 0; if the specification was | |
2801 | `%LTR DIGIT' then LETTER is the ASCII code for LTR. | |
2802 | ||
2803 | If X is a register, this macro should print the register's name. The names | |
2804 | can be found in an array `reg_names' whose type is `char *[]'. `reg_names' | |
2805 | is initialized from `REGISTER_NAMES'. | |
2806 | ||
2807 | When the machine description has a specification `%PUNCT' (a `%' followed by | |
2808 | a punctuation character), this macro is called with a null pointer for X and | |
2809 | the punctuation character for LETTER. | |
2810 | ||
2811 | Standard operand flags that are handled elsewhere: | |
2812 | `=' Output a number unique to each instruction in the compilation. | |
2813 | `a' Substitute an operand as if it were a memory reference. | |
2814 | `c' Omit the syntax that indicates an immediate operand. | |
2815 | `l' Substitute a LABEL_REF into a jump instruction. | |
2816 | `n' Like %cDIGIT, except negate the value before printing. | |
2817 | ||
2818 | The d30v specific operand flags are: | |
2819 | `.' Print r0. | |
2820 | `f' Print a SF constant as an int. | |
2821 | `s' Subtract 32 and negate. | |
2822 | `A' Print accumulator number without an `a' in front of it. | |
2823 | `B' Print bit offset for BSET, etc. instructions. | |
2824 | `E' Print u if this is zero extend, nothing if this is sign extend. | |
2825 | `F' Emit /{f,t,x}{f,t,x} for executing a false condition. | |
2826 | `L' Print the lower half of a 64 bit item. | |
2827 | `M' Print a memory reference for ld/st instructions. | |
2828 | `R' Return appropriate cmp instruction for relational test. | |
2829 | `S' Subtract 32. | |
2830 | `T' Emit /{f,t,x}{f,t,x} for executing a true condition. | |
2831 | `U' Print the upper half of a 64 bit item. */ | |
2832 | ||
2833 | void | |
2834 | d30v_print_operand (stream, x, letter) | |
2835 | FILE *stream; | |
2836 | rtx x; | |
2837 | int letter; | |
2838 | { | |
2839 | enum rtx_code code = (x) ? GET_CODE (x) : NIL; | |
2840 | rtx split_values[2]; | |
2841 | REAL_VALUE_TYPE rv; | |
2842 | long num; | |
2843 | int log; | |
2844 | ||
2845 | switch (letter) | |
2846 | { | |
2847 | case '.': /* Output r0 */ | |
2848 | fputs (reg_names[GPR_R0], stream); | |
2849 | break; | |
2850 | ||
2851 | case 'f': /* Print a SF floating constant as an int */ | |
2852 | if (GET_CODE (x) != CONST_DOUBLE) | |
c725bd79 | 2853 | fatal_insn ("bad insn to d30v_print_operand, 'f' modifier:", x); |
a5c874cb RH |
2854 | |
2855 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
2856 | REAL_VALUE_TO_TARGET_SINGLE (rv, num); | |
2857 | fprintf (stream, "%ld", num); | |
2858 | break; | |
2859 | ||
2860 | case 'A': /* Print accumulator number without an `a' in front of it. */ | |
2861 | if (GET_CODE (x) != REG || !ACCUM_P (REGNO (x))) | |
c725bd79 | 2862 | fatal_insn ("bad insn to d30v_print_operand, 'A' modifier:", x); |
a5c874cb RH |
2863 | |
2864 | putc ('0' + REGNO (x) - ACCUM_FIRST, stream); | |
2865 | break; | |
2866 | ||
2867 | case 'M': /* Print a memory reference for ld/st */ | |
2868 | if (GET_CODE (x) != MEM) | |
c725bd79 | 2869 | fatal_insn ("bad insn to d30v_print_operand, 'M' modifier:", x); |
a5c874cb RH |
2870 | |
2871 | d30v_print_operand_memory_reference (stream, XEXP (x, 0)); | |
2872 | break; | |
2873 | ||
2874 | case 'L': /* print lower part of 64 bit item. */ | |
2875 | case 'U': /* print upper part of 64 bit item. */ | |
2876 | d30v_split_double (x, &split_values[0], &split_values[1]); | |
2877 | d30v_print_operand (stream, split_values[ letter == 'L' ], '\0'); | |
2878 | break; | |
2879 | ||
5401747e RH |
2880 | case ':': /* Output the condition for the current insn. */ |
2881 | x = current_insn_predicate; | |
2882 | if (x == NULL_RTX) | |
2883 | break; | |
2884 | letter = 'T'; | |
2885 | /* FALLTHRU */ | |
2886 | ||
a5c874cb RH |
2887 | case 'F': /* Print an appropriate suffix for a false comparision. */ |
2888 | case 'T': /* Print an appropriate suffix for a true comparision. */ | |
2889 | /* Note that the sense of appropriate suffix is for conditional execution | |
2890 | and opposite of what branches want. Branches just use the inverse | |
2891 | operation. */ | |
2892 | if ((GET_CODE (x) == NE || GET_CODE (x) == EQ) | |
2893 | && GET_MODE (x) == CCmode | |
2894 | && GET_CODE (XEXP (x, 0)) == REG | |
2895 | && (GPR_P (REGNO (XEXP (x, 0))) || BR_FLAG_P (REGNO (XEXP (x, 0)))) | |
2896 | && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0) | |
2897 | { | |
2898 | int true_false = (letter == 'T'); | |
2899 | ||
2900 | if (GET_CODE (x) == EQ) | |
2901 | true_false = !true_false; | |
2902 | ||
2903 | if (REGNO (XEXP (x, 0)) == FLAG_F0) | |
2904 | fprintf (stream, "/%cx", (true_false) ? 'f' : 't'); | |
2905 | ||
2906 | else if (REGNO (XEXP (x, 0)) == FLAG_F1) | |
2907 | fprintf (stream, "/x%c", (true_false) ? 'f' : 't'); | |
2908 | ||
2909 | else | |
2910 | fputs ((true_false) ? "tnz" : "tzr", stream); | |
2911 | } | |
2912 | ||
2913 | else if (GET_CODE (x) == REG && REGNO (x) == FLAG_F0) | |
2914 | fprintf (stream, "/%cx", (letter == 'T') ? 't' : 'f'); | |
2915 | ||
2916 | else if (GET_CODE (x) == REG && REGNO (x) == FLAG_F1) | |
2917 | fprintf (stream, "/x%c", (letter == 'T') ? 't' : 'f'); | |
2918 | ||
2919 | else if (GET_CODE (x) == REG && GPR_P (REGNO (x))) | |
2920 | fputs ((letter == 'T') ? "tnz" : "tzr", stream); | |
2921 | ||
2922 | else | |
c725bd79 | 2923 | fatal_insn ("bad insn to print_operand, 'F' or 'T' modifier:", x); |
a5c874cb RH |
2924 | break; |
2925 | ||
2926 | case 'B': /* emit offset single bit to change */ | |
2927 | if (GET_CODE (x) == CONST_INT && (log = exact_log2 (INTVAL (x))) >= 0) | |
2928 | fprintf (stream, "%d", 31 - log); | |
2929 | ||
2930 | else if (GET_CODE (x) == CONST_INT && (log = exact_log2 (~ INTVAL (x))) >= 0) | |
2931 | fprintf (stream, "%d", 31 - log); | |
2932 | ||
2933 | else | |
c725bd79 | 2934 | fatal_insn ("bad insn to print_operand, 'B' modifier:", x); |
a5c874cb RH |
2935 | break; |
2936 | ||
2937 | case 'E': /* Print u if this is zero extend, nothing if sign extend. */ | |
2938 | if (GET_CODE (x) == ZERO_EXTEND) | |
2939 | putc ('u', stream); | |
2940 | else if (GET_CODE (x) != SIGN_EXTEND) | |
c725bd79 | 2941 | fatal_insn ("bad insn to print_operand, 'E' modifier:", x); |
a5c874cb RH |
2942 | break; |
2943 | ||
2944 | case 'R': /* Return appropriate cmp instruction for relational test. */ | |
2945 | switch (GET_CODE (x)) | |
2946 | { | |
2947 | case EQ: fputs ("cmpeq", stream); break; | |
2948 | case NE: fputs ("cmpne", stream); break; | |
2949 | case LT: fputs ("cmplt", stream); break; | |
2950 | case LE: fputs ("cmple", stream); break; | |
2951 | case GT: fputs ("cmpgt", stream); break; | |
2952 | case GE: fputs ("cmpge", stream); break; | |
2953 | case LTU: fputs ("cmpult", stream); break; | |
2954 | case LEU: fputs ("cmpule", stream); break; | |
2955 | case GTU: fputs ("cmpugt", stream); break; | |
2956 | case GEU: fputs ("cmpuge", stream); break; | |
2957 | ||
2958 | default: | |
c725bd79 | 2959 | fatal_insn ("bad insn to print_operand, 'R' modifier:", x); |
a5c874cb RH |
2960 | } |
2961 | break; | |
2962 | ||
2963 | case 's': /* Subtract 32 and negate (for 64 bit shifts). */ | |
2964 | if (GET_CODE (x) == CONST_INT) | |
2965 | fprintf (stream, "%d", (int) (32 - INTVAL (x))); | |
2966 | ||
2967 | else | |
c725bd79 | 2968 | fatal_insn ("bad insn to print_operand, 's' modifier:", x); |
a5c874cb RH |
2969 | break; |
2970 | ||
2971 | case 'S': /* Subtract 32. */ | |
2972 | if (GET_CODE (x) == CONST_INT) | |
2973 | fprintf (stream, "%d", (int)(INTVAL (x) - 32)); | |
2974 | ||
2975 | else | |
c725bd79 | 2976 | fatal_insn ("bad insn to print_operand, 's' modifier:", x); |
a5c874cb RH |
2977 | break; |
2978 | ||
2979 | ||
2980 | case 'z': /* If arg is 0 or 0.0, print r0, otherwise print as normal */ | |
2981 | if ((GET_CODE (x) == CONST_INT && INTVAL (x) == 0) | |
2982 | || (GET_CODE (x) == CONST_DOUBLE && CONST_DOUBLE_LOW (x) == 0 | |
2983 | && CONST_DOUBLE_HIGH (x) == 0)) | |
2984 | { | |
2985 | fputs (reg_names[GPR_FIRST], stream); | |
2986 | return; | |
2987 | } | |
2988 | ||
2989 | /* fall through */ | |
2990 | ||
2991 | case '\0': | |
2992 | if (code == REG) | |
2993 | fputs (reg_names[ REGNO (x) ], stream); | |
2994 | ||
2995 | else if (code == CONST_INT) | |
2996 | fprintf (stream, "%d", (int)INTVAL (x)); | |
2997 | ||
2998 | else if (code == MEM) | |
2999 | d30v_print_operand_address (stream, XEXP (x, 0)); | |
3000 | ||
3001 | else if (CONSTANT_ADDRESS_P (x)) | |
3002 | d30v_print_operand_address (stream, x); | |
3003 | ||
3004 | else | |
c725bd79 | 3005 | fatal_insn ("bad insn in d30v_print_operand, 0 case", x); |
a5c874cb RH |
3006 | |
3007 | return; | |
3008 | ||
3009 | default: | |
3010 | { | |
3011 | char buf[80]; | |
3012 | ||
c725bd79 | 3013 | sprintf (buf, "invalid asm template character '%%%c'", letter); |
a5c874cb RH |
3014 | fatal_insn (buf, x); |
3015 | } | |
3016 | } | |
3017 | } | |
3018 | ||
3019 | \f | |
3020 | /* A C expression for the size in bytes of the trampoline, as an integer. */ | |
3021 | ||
3022 | int | |
3023 | d30v_trampoline_size () | |
3024 | { | |
3025 | return 16; | |
3026 | } | |
3027 | ||
3028 | \f | |
3029 | /* Create a long instruction for building up a trampoline. */ | |
3030 | ||
3031 | static void | |
3032 | d30v_build_long_insn (high_bits, low_bits, imm, mem) | |
3033 | HOST_WIDE_INT high_bits; | |
3034 | HOST_WIDE_INT low_bits; | |
3035 | rtx imm; | |
3036 | rtx mem; | |
3037 | { | |
3038 | rtx reg = gen_reg_rtx (DImode); | |
3039 | rtx high_word = gen_highpart (SImode, reg); | |
3040 | rtx low_word = gen_lowpart (SImode, reg); | |
3041 | rtx tmp1 = gen_reg_rtx (SImode); | |
3042 | rtx tmp2 = gen_reg_rtx (SImode); | |
3043 | rtx tmp3 = gen_reg_rtx (SImode); | |
3044 | rtx tmp4 = gen_reg_rtx (SImode); | |
3045 | rtx tmp5 = gen_reg_rtx (SImode); | |
3046 | rtx tmp6 = gen_reg_rtx (SImode); | |
3047 | ||
3048 | imm = force_reg (SImode, imm); | |
3049 | ||
3050 | /* Stuff top 6 bits of immediate value into high word */ | |
3051 | emit_insn (gen_lshrsi3 (tmp1, imm, GEN_INT (26))); | |
3052 | emit_insn (gen_andsi3 (tmp2, tmp1, GEN_INT (0x3F))); | |
3053 | emit_insn (gen_iorsi3 (high_word, tmp2, GEN_INT (high_bits))); | |
3054 | ||
3055 | /* Now get the next 8 bits for building the low word */ | |
3056 | emit_insn (gen_andsi3 (tmp3, imm, GEN_INT (0x03FC0000))); | |
3057 | emit_insn (gen_ashlsi3 (tmp4, tmp3, GEN_INT (2))); | |
3058 | ||
3059 | /* And the bottom 18 bits */ | |
3060 | emit_insn (gen_andsi3 (tmp5, imm, GEN_INT (0x0003FFFF))); | |
3061 | emit_insn (gen_iorsi3 (tmp6, tmp4, tmp5)); | |
3062 | emit_insn (gen_iorsi3 (low_word, tmp6, GEN_INT (low_bits))); | |
3063 | ||
3064 | /* Store the instruction */ | |
3065 | emit_insn (gen_movdi (mem, reg)); | |
3066 | } | |
3067 | ||
3068 | \f | |
3069 | /* A C statement to initialize the variable parts of a trampoline. ADDR is an | |
3070 | RTX for the address of the trampoline; FNADDR is an RTX for the address of | |
3071 | the nested function; STATIC_CHAIN is an RTX for the static chain value that | |
3072 | should be passed to the function when it is called. */ | |
3073 | ||
3074 | void | |
3075 | d30v_initialize_trampoline (addr, fnaddr, static_chain) | |
3076 | rtx addr; | |
3077 | rtx fnaddr; | |
3078 | rtx static_chain; | |
3079 | { | |
3080 | /* The instruction space can only be accessed by ld2w/st2w. | |
3081 | Generate on the fly: | |
3082 | or r18,r0,<static-chain> | |
3083 | jmp <fnaddr> */ | |
3084 | d30v_build_long_insn (0x83A80000 | ((STATIC_CHAIN_REGNUM - GPR_FIRST) << 12), | |
3085 | 0x80000000, static_chain, | |
3086 | gen_rtx (MEM, DImode, addr)); | |
3087 | ||
3088 | d30v_build_long_insn (0x80180000, 0x80000000, fnaddr, | |
3089 | gen_rtx (MEM, DImode, plus_constant (addr, 8))); | |
3090 | } | |
3091 | ||
3092 | \f | |
3093 | /* A C compound statement with a conditional `goto LABEL;' executed if X (an | |
3094 | RTX) is a legitimate memory address on the target machine for a memory | |
fb49053f | 3095 | operand of mode MODE. */ |
a5c874cb RH |
3096 | |
3097 | #define XREGNO_OK_FOR_BASE_P(REGNO, STRICT_P) \ | |
3098 | ((STRICT_P) \ | |
3099 | ? REGNO_OK_FOR_BASE_P (REGNO) \ | |
3100 | : GPR_OR_PSEUDO_P (REGNO)) | |
3101 | ||
3102 | int | |
3103 | d30v_legitimate_address_p (mode, x, strict_p) | |
3104 | enum machine_mode mode; | |
3105 | rtx x; | |
3106 | int strict_p; | |
3107 | { | |
3108 | rtx x0, x1; | |
3109 | int ret = 0; | |
3110 | ||
3111 | switch (GET_CODE (x)) | |
3112 | { | |
3113 | default: | |
3114 | break; | |
3115 | ||
3116 | case SUBREG: | |
3117 | x = SUBREG_REG (x); | |
3118 | if (GET_CODE (x) != REG) | |
3119 | break; | |
3120 | ||
3121 | /* fall through */ | |
3122 | ||
3123 | case REG: | |
3124 | ret = XREGNO_OK_FOR_BASE_P (REGNO (x), strict_p); | |
3125 | break; | |
3126 | ||
3127 | case PLUS: | |
3128 | x0 = XEXP (x, 0); | |
3129 | x1 = XEXP (x, 1); | |
3130 | ||
3131 | if (GET_CODE (x0) == SUBREG) | |
3132 | x0 = SUBREG_REG (x0); | |
3133 | ||
3134 | if (GET_CODE (x0) == POST_INC || GET_CODE (x0) == POST_DEC) | |
3135 | x0 = XEXP (x0, 0); | |
3136 | ||
3137 | if (GET_CODE (x0) != REG || !XREGNO_OK_FOR_BASE_P (REGNO (x0), strict_p)) | |
3138 | break; | |
3139 | ||
3140 | switch (GET_CODE (x1)) | |
3141 | { | |
3142 | default: | |
3143 | break; | |
3144 | ||
3145 | case SUBREG: | |
3146 | x1 = SUBREG_REG (x1); | |
3147 | if (GET_CODE (x1) != REG) | |
3148 | break; | |
3149 | ||
3150 | /* fall through */ | |
3151 | ||
3152 | case REG: | |
3153 | ret = XREGNO_OK_FOR_BASE_P (REGNO (x1), strict_p); | |
3154 | break; | |
3155 | ||
3156 | case CONST_INT: | |
3157 | ret = (IN_RANGE_P (INTVAL (x1), -32, 31)) ? 1 : 2; | |
3158 | break; | |
3159 | ||
3160 | case SYMBOL_REF: | |
3161 | case LABEL_REF: | |
3162 | case CONST: | |
3163 | ret = 2; | |
3164 | break; | |
3165 | } | |
3166 | break; | |
3167 | ||
3168 | case CONST_INT: | |
3169 | ret = (IN_RANGE_P (INTVAL (x), -32, 31)) ? 1 : 2; | |
3170 | break; | |
3171 | ||
3172 | case SYMBOL_REF: | |
3173 | case LABEL_REF: | |
3174 | case CONST: | |
3175 | ret = 2; | |
3176 | break; | |
3177 | ||
3178 | case POST_INC: | |
3179 | case POST_DEC: | |
3180 | x0 = XEXP (x, 0); | |
3181 | if (GET_CODE (x0) == REG && XREGNO_OK_FOR_BASE_P (REGNO (x0), strict_p)) | |
3182 | ret = 1; | |
3183 | break; | |
3184 | } | |
3185 | ||
3186 | if (TARGET_DEBUG_ADDR) | |
3187 | { | |
3188 | fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict\n", | |
3189 | GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not "); | |
3190 | debug_rtx (x); | |
3191 | } | |
3192 | ||
3193 | return ret; | |
3194 | } | |
3195 | ||
3196 | \f | |
3197 | /* A C compound statement that attempts to replace X with a valid memory | |
3198 | address for an operand of mode MODE. WIN will be a C statement label | |
3199 | elsewhere in the code; the macro definition may use | |
3200 | ||
3201 | GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); | |
3202 | ||
3203 | to avoid further processing if the address has become legitimate. | |
3204 | ||
3205 | X will always be the result of a call to `break_out_memory_refs', and OLDX | |
3206 | will be the operand that was given to that function to produce X. | |
3207 | ||
3208 | The code generated by this macro should not alter the substructure of X. If | |
3209 | it transforms X into a more legitimate form, it should assign X (which will | |
3210 | always be a C variable) a new value. | |
3211 | ||
3212 | It is not necessary for this macro to come up with a legitimate address. | |
3213 | The compiler has standard ways of doing so in all cases. In fact, it is | |
3214 | safe for this macro to do nothing. But often a machine-dependent strategy | |
3215 | can generate better code. */ | |
3216 | ||
3217 | rtx | |
3218 | d30v_legitimize_address (x, oldx, mode, strict_p) | |
3219 | rtx x; | |
3220 | rtx oldx ATTRIBUTE_UNUSED; | |
3221 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3222 | int strict_p ATTRIBUTE_UNUSED; | |
3223 | { | |
3224 | rtx ret = NULL_RTX; | |
3225 | ||
3226 | if (TARGET_DEBUG_ADDR) | |
3227 | { | |
3228 | if (ret) | |
3229 | { | |
3230 | fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, transformed:\n"); | |
3231 | debug_rtx (x); | |
3232 | fprintf (stderr, "\ninto:\n"); | |
3233 | debug_rtx (ret); | |
3234 | } | |
3235 | else | |
3236 | { | |
3237 | fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, did nothing with:\n"); | |
3238 | debug_rtx (x); | |
3239 | } | |
3240 | } | |
3241 | ||
3242 | return ret; | |
3243 | } | |
3244 | ||
3245 | \f | |
3246 | /* A C statement or compound statement with a conditional `goto LABEL;' | |
3247 | executed if memory address X (an RTX) can have different meanings depending | |
3248 | on the machine mode of the memory reference it is used for or if the address | |
3249 | is valid for some modes but not others. | |
3250 | ||
3251 | Autoincrement and autodecrement addresses typically have mode-dependent | |
3252 | effects because the amount of the increment or decrement is the size of the | |
3253 | operand being addressed. Some machines have other mode-dependent addresses. | |
3254 | Many RISC machines have no mode-dependent addresses. | |
3255 | ||
3256 | You may assume that ADDR is a valid address for the machine. */ | |
3257 | ||
3258 | int | |
3259 | d30v_mode_dependent_address_p (addr) | |
3260 | rtx addr; | |
3261 | { | |
3262 | switch (GET_CODE (addr)) | |
3263 | { | |
3264 | default: | |
3265 | break; | |
3266 | ||
3267 | case POST_INC: | |
3268 | case POST_DEC: | |
3269 | return TRUE; | |
3270 | } | |
3271 | ||
3272 | return FALSE; | |
3273 | } | |
3274 | ||
3275 | \f | |
3276 | /* Generate the appropriate comparison code for a test. */ | |
3277 | ||
3278 | rtx | |
3279 | d30v_emit_comparison (test_int, result, arg1, arg2) | |
3280 | int test_int; | |
3281 | rtx result; | |
3282 | rtx arg1; | |
3283 | rtx arg2; | |
3284 | { | |
3285 | enum rtx_code test = (enum rtx_code) test_int; | |
3286 | enum machine_mode mode = GET_MODE (arg1); | |
3287 | rtx rtx_test = gen_rtx (SET, VOIDmode, result, gen_rtx (test, CCmode, arg1, arg2)); | |
3288 | ||
3289 | if (mode == SImode | |
3290 | || (mode == DImode && (test == EQ || test == NE)) | |
3291 | || (mode == DImode && (test == LT || test == GE) | |
3292 | && GET_CODE (arg2) == CONST_INT && INTVAL (arg2) == 0)) | |
3293 | return rtx_test; | |
3294 | ||
3295 | else if (mode == DImode) | |
3296 | return gen_rtx (PARALLEL, VOIDmode, | |
3297 | gen_rtvec (2, | |
3298 | rtx_test, | |
3299 | gen_rtx (CLOBBER, VOIDmode, | |
3300 | gen_reg_rtx (CCmode)))); | |
3301 | ||
3302 | else | |
3303 | fatal_insn ("d30v_emit_comparison", rtx_test); | |
3304 | } | |
3305 | ||
3306 | \f | |
3307 | /* Return appropriate code to move 2 words. Since DImode registers must start | |
3308 | on even register numbers, there is no possibility of overlap. */ | |
3309 | ||
1943c2c1 | 3310 | const char * |
a5c874cb RH |
3311 | d30v_move_2words (operands, insn) |
3312 | rtx operands[]; | |
3313 | rtx insn; | |
3314 | { | |
3315 | if (GET_CODE (operands[0]) == REG && GPR_P (REGNO (operands[0]))) | |
3316 | { | |
3317 | if (GET_CODE (operands[1]) == REG && GPR_P (REGNO (operands[1]))) | |
3318 | return "or %U0,%.,%U1\n\tor %L0,%.,%L1"; | |
3319 | ||
3320 | else if (GET_CODE (operands[1]) == REG && ACCUM_P (REGNO (operands[1]))) | |
3321 | return "mvfacc %L0,%1,%.\n\tmvfacc %U0,%1,32"; | |
3322 | ||
3323 | else if (GET_CODE (operands[1]) == MEM) | |
3324 | return "ld2w %0,%M1"; | |
3325 | ||
3326 | else if (GET_CODE (operands[1]) == CONST_INT | |
3327 | || GET_CODE (operands[1]) == CONST_DOUBLE) | |
3328 | return "or %U0,%.,%U1\n\tor %L0,%.,%L1"; | |
3329 | } | |
3330 | ||
3331 | else if (GET_CODE (operands[0]) == REG && ACCUM_P (REGNO (operands[0]))) | |
3332 | { | |
3333 | if (GET_CODE (operands[1]) == REG | |
3334 | && GPR_P (REGNO (operands[1]))) | |
3335 | return "mvtacc %0,%U1,%L1"; | |
3336 | ||
3337 | if (GET_CODE (operands[1]) == CONST_INT | |
3338 | && INTVAL (operands[1]) == 0) | |
3339 | return "mvtacc %0,%.,%."; | |
3340 | } | |
3341 | ||
3342 | else if (GET_CODE (operands[0]) == MEM | |
3343 | && GET_CODE (operands[1]) == REG | |
3344 | && GPR_P (REGNO (operands[1]))) | |
3345 | return "st2w %1,%M0"; | |
3346 | ||
c725bd79 | 3347 | fatal_insn ("bad call to d30v_move_2words", insn); |
a5c874cb RH |
3348 | } |
3349 | ||
3350 | \f | |
3351 | /* Emit the code to do a conditional move instruction. Return FALSE | |
3352 | if the conditional move could not be executed. */ | |
3353 | ||
3354 | int | |
3355 | d30v_emit_cond_move (dest, test, true_value, false_value) | |
3356 | rtx dest; | |
3357 | rtx test; | |
3358 | rtx true_value; | |
3359 | rtx false_value; | |
3360 | { | |
3361 | rtx br_reg; | |
3362 | enum machine_mode mode = GET_MODE (dest); | |
3363 | int two_mem_moves_p = FALSE; | |
3364 | ||
3365 | if (GET_CODE (dest) == MEM) | |
3366 | { | |
3367 | if (!reg_or_0_operand (true_value, mode)) | |
3368 | return FALSE; | |
3369 | ||
3370 | if (rtx_equal_p (dest, false_value)) | |
3371 | two_mem_moves_p = TRUE; | |
3372 | ||
3373 | else if (!reg_or_0_operand (false_value, mode)) | |
3374 | return FALSE; | |
3375 | } | |
3376 | ||
3377 | /* We used to try to optimize setting 0/1 by using mvfsys, but that turns out | |
3378 | to be slower than just doing the conditional execution. */ | |
3379 | ||
3380 | br_reg = gen_reg_rtx (CCmode); | |
3381 | emit_insn (d30v_emit_comparison (GET_CODE (test), br_reg, | |
3382 | d30v_compare_op0, d30v_compare_op1)); | |
3383 | ||
3384 | if (!two_mem_moves_p) | |
3385 | emit_insn (gen_rtx_SET (VOIDmode, | |
3386 | dest, | |
3387 | gen_rtx_IF_THEN_ELSE (mode, | |
3388 | gen_rtx_NE (CCmode, br_reg, | |
3389 | const0_rtx), | |
3390 | true_value, | |
3391 | false_value))); | |
3392 | else | |
3393 | { | |
3394 | /* Emit conditional stores as two separate stores. This avoids a problem | |
3395 | where you have a conditional store, and one of the arms of the | |
3396 | conditional store is spilled to memory. */ | |
3397 | emit_insn (gen_rtx_SET (VOIDmode, | |
3398 | dest, | |
3399 | gen_rtx_IF_THEN_ELSE (mode, | |
3400 | gen_rtx_NE (CCmode, br_reg, | |
3401 | const0_rtx), | |
3402 | true_value, | |
3403 | dest))); | |
3404 | ||
3405 | emit_insn (gen_rtx_SET (VOIDmode, | |
3406 | dest, | |
3407 | gen_rtx_IF_THEN_ELSE (mode, | |
3408 | gen_rtx_EQ (CCmode, br_reg, | |
3409 | const0_rtx), | |
3410 | false_value, | |
3411 | dest))); | |
3412 | ||
3413 | } | |
3414 | ||
3415 | return TRUE; | |
3416 | } | |
3417 | ||
3418 | \f | |
3419 | /* In rare cases, correct code generation requires extra machine dependent | |
3420 | processing between the second jump optimization pass and delayed branch | |
3421 | scheduling. On those machines, define this macro as a C statement to act on | |
3422 | the code starting at INSN. */ | |
3423 | ||
3424 | void | |
3425 | d30v_machine_dependent_reorg (insn) | |
3426 | rtx insn ATTRIBUTE_UNUSED; | |
3427 | { | |
3428 | } | |
3429 | ||
3430 | \f | |
3431 | /* A C statement (sans semicolon) to update the integer variable COST based on | |
3432 | the relationship between INSN that is dependent on DEP_INSN through the | |
3433 | dependence LINK. The default is to make no adjustment to COST. This can be | |
3434 | used for example to specify to the scheduler that an output- or | |
3435 | anti-dependence does not incur the same cost as a data-dependence. */ | |
3436 | ||
3437 | /* For the d30v, try to insure that the source operands for a load/store are | |
3438 | set 2 cycles before the memory reference. */ | |
3439 | ||
c237e94a | 3440 | static int |
a5c874cb RH |
3441 | d30v_adjust_cost (insn, link, dep_insn, cost) |
3442 | rtx insn; | |
3443 | rtx link ATTRIBUTE_UNUSED; | |
3444 | rtx dep_insn; | |
3445 | int cost; | |
3446 | { | |
3447 | rtx set_dep = single_set (dep_insn); | |
3448 | rtx set_insn = single_set (insn); | |
3449 | ||
3450 | if (set_dep != NULL_RTX && set_insn != NULL_RTX | |
3451 | && GET_CODE (SET_DEST (set_dep)) == REG) | |
3452 | { | |
3453 | rtx reg = SET_DEST (set_dep); | |
3454 | rtx mem; | |
3455 | ||
3456 | if ((GET_CODE (mem = SET_SRC (set_insn)) == MEM | |
3457 | && reg_mentioned_p (reg, XEXP (mem, 0))) | |
3458 | || (GET_CODE (mem = SET_DEST (set_insn)) == MEM | |
3459 | && reg_mentioned_p (reg, XEXP (mem, 0)))) | |
3460 | { | |
c237e94a | 3461 | return cost + 2; |
a5c874cb RH |
3462 | } |
3463 | } | |
3464 | ||
3465 | return cost; | |
3466 | } | |
3467 | ||
c237e94a ZW |
3468 | /* Function which returns the number of insns that can be |
3469 | scheduled in the same machine cycle. This must be constant | |
3470 | over an entire compilation. The default is 1. */ | |
3471 | static int | |
3472 | d30v_issue_rate () | |
3473 | { | |
3474 | return 2; | |
3475 | } | |
3476 | ||
a5c874cb | 3477 | \f |
a2e11fd9 NC |
3478 | /* Routine to allocate, mark and free a per-function, |
3479 | machine specific structure. */ | |
a5c874cb | 3480 | |
e2500fed GK |
3481 | static struct machine_function * |
3482 | d30v_init_machine_status () | |
a5c874cb | 3483 | { |
e2500fed | 3484 | return ggc_alloc_cleared (sizeof (machine_function)); |
a5c874cb RH |
3485 | } |
3486 | ||
3487 | /* Do anything needed before RTL is emitted for each function. */ | |
3488 | ||
3489 | void | |
3490 | d30v_init_expanders () | |
3491 | { | |
a5c874cb | 3492 | /* Arrange to save and restore machine status around nested functions. */ |
a2e11fd9 | 3493 | init_machine_status = d30v_init_machine_status; |
a5c874cb RH |
3494 | } |
3495 | ||
3496 | /* Find the current function's return address. | |
3497 | ||
3498 | ??? It would be better to arrange things such that if we would ordinarily | |
3499 | have been a leaf function and we didn't spill the hard reg that we | |
3500 | wouldn't have to save the register in the prolog. But it's not clear | |
3501 | how to get the right information at the right time. */ | |
3502 | ||
3503 | rtx | |
3504 | d30v_return_addr () | |
3505 | { | |
9e2f7ec7 | 3506 | return get_hard_reg_initial_val (Pmode, GPR_LINK); |
a5c874cb | 3507 | } |