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49ac143d | 1 | ;; Constraint definitions for FRV. |
a5544970 | 2 | ;; Copyright (C) 2001-2019 Free Software Foundation, Inc. |
49ac143d NF |
3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
8 | ;; the Free Software Foundation; either version 3, or (at your option) | |
9 | ;; any later version. | |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
17 | ;; along with GCC; see the file COPYING3. If not see | |
18 | ;; <http://www.gnu.org/licenses/>. | |
19 | ||
20 | ;; Register constraints. | |
21 | (define_register_constraint "a" "ACC_REGS" | |
22 | "@internal") | |
23 | ||
24 | (define_register_constraint "b" "EVEN_ACC_REGS" | |
25 | "@internal") | |
26 | ||
27 | (define_register_constraint "c" "CC_REGS" | |
28 | "@internal") | |
29 | ||
30 | (define_register_constraint "d" "GPR_REGS" | |
31 | "@internal") | |
32 | ||
33 | (define_register_constraint "e" "EVEN_REGS" | |
34 | "@internal") | |
35 | ||
36 | (define_register_constraint "f" "FPR_REGS" | |
37 | "@internal") | |
38 | ||
39 | (define_register_constraint "h" "FEVEN_REGS" | |
40 | "@internal") | |
41 | ||
42 | (define_register_constraint "l" "LR_REG" | |
43 | "@internal") | |
44 | ||
45 | (define_register_constraint "q" "QUAD_REGS" | |
46 | "@internal") | |
47 | ||
48 | (define_register_constraint "t" "ICC_REGS" | |
49 | "@internal") | |
50 | ||
51 | (define_register_constraint "u" "FCC_REGS" | |
52 | "@internal") | |
53 | ||
54 | (define_register_constraint "v" "ICR_REGS" | |
55 | "@internal") | |
56 | ||
57 | (define_register_constraint "w" "FCR_REGS" | |
58 | "@internal") | |
59 | ||
60 | (define_register_constraint "x" "QUAD_FPR_REGS" | |
61 | "@internal") | |
62 | ||
63 | (define_register_constraint "y" "LCR_REG" | |
64 | "@internal") | |
65 | ||
66 | (define_register_constraint "z" "SPR_REGS" | |
67 | "@internal") | |
68 | ||
69 | (define_register_constraint "A" "QUAD_ACC_REGS" | |
70 | "@internal") | |
71 | ||
72 | (define_register_constraint "B" "ACCG_REGS" | |
73 | "@internal") | |
74 | ||
75 | (define_register_constraint "C" "CR_REGS" | |
76 | "@internal") | |
77 | ||
78 | (define_register_constraint "D89" "GR89_REGS" | |
79 | "@internal") | |
80 | ||
81 | (define_register_constraint "D09" "GR9_REGS" | |
82 | "@internal") | |
83 | ||
84 | (define_register_constraint "D08" "GR8_REGS" | |
85 | "@internal") | |
86 | ||
87 | (define_register_constraint "D14" "FDPIC_FPTR_REGS" | |
88 | "@internal") | |
89 | ||
90 | (define_register_constraint "D15" "FDPIC_REGS" | |
91 | "@internal") | |
92 | ||
93 | (define_register_constraint "W" "FDPIC_CALL_REGS" | |
94 | "@internal") | |
95 | ||
96 | (define_register_constraint "Z" "FDPIC_REGS" | |
97 | "@internal") | |
98 | ||
99 | ;; Integer constraints. | |
100 | (define_constraint "I" | |
101 | "A signed 6-bit immediate." | |
102 | (and (match_code "const_int") | |
103 | (match_test "IN_RANGE (ival, -32, 31)"))) | |
104 | ||
105 | (define_constraint "J" | |
106 | "A signed 10-bit immediate." | |
107 | (and (match_code "const_int") | |
108 | (match_test "IN_RANGE (ival, -512, 511)"))) | |
109 | ||
110 | (define_constraint "K" | |
111 | "@internal" | |
112 | ;; Unused. | |
113 | (and (match_code "const_int") | |
114 | (match_test "0"))) | |
115 | ||
116 | (define_constraint "L" | |
117 | "A signed 16-bit immediate." | |
118 | (and (match_code "const_int") | |
119 | (match_test "IN_RANGE (ival, -32768, 32767)"))) | |
120 | ||
121 | (define_constraint "M" | |
122 | "An unsigned 16-bit immediate." | |
123 | (and (match_code "const_int") | |
124 | (match_test "IN_RANGE (ival, 0, 65535)"))) | |
125 | ||
126 | (define_constraint "N" | |
127 | "A signed 12-bit immediate that is negative." | |
128 | (and (match_code "const_int") | |
129 | (match_test "IN_RANGE (ival, -2048, -1)"))) | |
130 | ||
131 | (define_constraint "O" | |
132 | "Zero." | |
133 | (and (match_code "const_int") | |
134 | (match_test "ival == 0"))) | |
135 | ||
136 | (define_constraint "P" | |
137 | "A signed 12-bit immediate that is positive." | |
138 | (and (match_code "const_int") | |
139 | (match_test "IN_RANGE (ival, 1, 2047)"))) | |
140 | ||
141 | ;; Floating-point constraints. | |
142 | (define_constraint "G" | |
143 | "Floating-point zero." | |
144 | (and (match_code "const_double") | |
145 | (ior (and (match_test "mode == VOIDmode") | |
146 | (match_test "hval == 0 && lval == 0")) | |
147 | (and (match_test "mode == SFmode || mode == DFmode") | |
148 | (match_test "op == CONST0_RTX (mode)"))))) | |
149 | ||
150 | (define_constraint "H" | |
151 | "@internal" | |
152 | ;; Unused. | |
153 | (and (match_code "const_double") | |
154 | (match_test "0"))) | |
155 | ||
156 | (define_constraint "Q" | |
157 | "12-bit relocations." | |
158 | (match_test "got12_operand (op, mode)")) | |
159 | ||
160 | (define_memory_constraint "R" | |
161 | "Double word memory ops that take one instruction." | |
162 | (match_test "dbl_memory_one_insn_operand (op, mode)")) | |
163 | ||
164 | (define_constraint "S" | |
165 | "SYMBOL_REF." | |
166 | (match_test "CONSTANT_P (op) && call_operand (op, VOIDmode)")) | |
167 | ||
168 | (define_memory_constraint "T" | |
169 | "Double word memory ops that take two instructions." | |
170 | (match_test "dbl_memory_two_insn_operand (op, mode)")) | |
171 | ||
172 | (define_memory_constraint "U" | |
173 | "Memory operand for conditional execution." | |
174 | (match_test "condexec_memory_operand (op, mode)")) |