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34208acf | 1 | /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004 |
8ac411c7 | 2 | Free Software Foundation, Inc. |
36a05131 BS |
3 | Contributed by Red Hat, Inc. |
4 | ||
7ec022b2 | 5 | This file is part of GCC. |
36a05131 | 6 | |
7ec022b2 | 7 | GCC is free software; you can redistribute it and/or modify |
36a05131 BS |
8 | it under the terms of the GNU General Public License as published by |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
7ec022b2 | 12 | GCC is distributed in the hope that it will be useful, |
36a05131 BS |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
7ec022b2 | 18 | along with GCC; see the file COPYING. If not, write to |
36a05131 BS |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #include "config.h" | |
23 | #include "system.h" | |
4977bab6 ZW |
24 | #include "coretypes.h" |
25 | #include "tm.h" | |
36a05131 BS |
26 | #include "rtl.h" |
27 | #include "tree.h" | |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
33 | #include "insn-flags.h" | |
34 | #include "output.h" | |
35 | #include "insn-attr.h" | |
36 | #include "flags.h" | |
37 | #include "recog.h" | |
38 | #include "reload.h" | |
39 | #include "expr.h" | |
40 | #include "obstack.h" | |
41 | #include "except.h" | |
42 | #include "function.h" | |
43 | #include "optabs.h" | |
44 | #include "toplev.h" | |
45 | #include "basic-block.h" | |
46 | #include "tm_p.h" | |
47 | #include "ggc.h" | |
48 | #include <ctype.h> | |
49 | #include "target.h" | |
50 | #include "target-def.h" | |
34208acf | 51 | #include "integrate.h" |
36a05131 BS |
52 | |
53 | #ifndef FRV_INLINE | |
54 | #define FRV_INLINE inline | |
55 | #endif | |
56 | ||
34208acf AO |
57 | /* Information about a relocation unspec. SYMBOL is the relocation symbol |
58 | (a SYMBOL_REF or LABEL_REF), RELOC is the type of relocation and OFFSET | |
59 | is the constant addend. */ | |
60 | struct frv_unspec { | |
61 | rtx symbol; | |
62 | int reloc; | |
63 | HOST_WIDE_INT offset; | |
64 | }; | |
65 | ||
36a05131 BS |
66 | /* Temporary register allocation support structure. */ |
67 | typedef struct frv_tmp_reg_struct | |
68 | { | |
69 | HARD_REG_SET regs; /* possible registers to allocate */ | |
70 | int next_reg[N_REG_CLASSES]; /* next register to allocate per class */ | |
71 | } | |
72 | frv_tmp_reg_t; | |
73 | ||
74 | /* Register state information for VLIW re-packing phase. These values must fit | |
75 | within an unsigned char. */ | |
76 | #define REGSTATE_DEAD 0x00 /* register is currently dead */ | |
77 | #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */ | |
78 | #define REGSTATE_LIVE 0x08 /* register is live */ | |
79 | #define REGSTATE_MODIFIED 0x10 /* reg modified in current VLIW insn */ | |
80 | #define REGSTATE_IF_TRUE 0x20 /* reg modified in cond exec true */ | |
81 | #define REGSTATE_IF_FALSE 0x40 /* reg modified in cond exec false */ | |
82 | #define REGSTATE_UNUSED 0x80 /* bit for hire */ | |
83 | #define REGSTATE_MASK 0xff /* mask for the bits to set */ | |
84 | ||
85 | /* conditional expression used */ | |
86 | #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE) | |
87 | ||
87b483a1 | 88 | /* The following is not sure in the reg_state bytes, so can have a larger value |
36a05131 BS |
89 | than 0xff. */ |
90 | #define REGSTATE_CONDJUMP 0x100 /* conditional jump done in VLIW insn */ | |
91 | ||
92 | /* Used in frv_frame_accessor_t to indicate the direction of a register-to- | |
93 | memory move. */ | |
94 | enum frv_stack_op | |
95 | { | |
96 | FRV_LOAD, | |
97 | FRV_STORE | |
98 | }; | |
99 | ||
100 | /* Information required by frv_frame_access. */ | |
101 | typedef struct | |
102 | { | |
103 | /* This field is FRV_LOAD if registers are to be loaded from the stack and | |
104 | FRV_STORE if they should be stored onto the stack. FRV_STORE implies | |
105 | the move is being done by the prologue code while FRV_LOAD implies it | |
106 | is being done by the epilogue. */ | |
107 | enum frv_stack_op op; | |
108 | ||
109 | /* The base register to use when accessing the stack. This may be the | |
110 | frame pointer, stack pointer, or a temporary. The choice of register | |
111 | depends on which part of the frame is being accessed and how big the | |
112 | frame is. */ | |
113 | rtx base; | |
114 | ||
115 | /* The offset of BASE from the bottom of the current frame, in bytes. */ | |
116 | int base_offset; | |
117 | } frv_frame_accessor_t; | |
118 | ||
119 | /* Define the information needed to generate branch and scc insns. This is | |
120 | stored from the compare operation. */ | |
121 | rtx frv_compare_op0; | |
122 | rtx frv_compare_op1; | |
123 | ||
87b483a1 | 124 | /* Conditional execution support gathered together in one structure. */ |
36a05131 BS |
125 | typedef struct |
126 | { | |
127 | /* Linked list of insns to add if the conditional execution conversion was | |
128 | successful. Each link points to an EXPR_LIST which points to the pattern | |
129 | of the insn to add, and the insn to be inserted before. */ | |
130 | rtx added_insns_list; | |
131 | ||
132 | /* Identify which registers are safe to allocate for if conversions to | |
133 | conditional execution. We keep the last allocated register in the | |
134 | register classes between COND_EXEC statements. This will mean we allocate | |
135 | different registers for each different COND_EXEC group if we can. This | |
136 | might allow the scheduler to intermix two different COND_EXEC sections. */ | |
137 | frv_tmp_reg_t tmp_reg; | |
138 | ||
139 | /* For nested IFs, identify which CC registers are used outside of setting | |
140 | via a compare isnsn, and using via a check insn. This will allow us to | |
141 | know if we can rewrite the register to use a different register that will | |
142 | be paired with the CR register controlling the nested IF-THEN blocks. */ | |
143 | HARD_REG_SET nested_cc_ok_rewrite; | |
144 | ||
145 | /* Temporary registers allocated to hold constants during conditional | |
146 | execution. */ | |
147 | rtx scratch_regs[FIRST_PSEUDO_REGISTER]; | |
148 | ||
149 | /* Current number of temp registers available. */ | |
150 | int cur_scratch_regs; | |
151 | ||
87b483a1 | 152 | /* Number of nested conditional execution blocks. */ |
36a05131 BS |
153 | int num_nested_cond_exec; |
154 | ||
155 | /* Map of insns that set up constants in scratch registers. */ | |
156 | bitmap scratch_insns_bitmap; | |
157 | ||
87b483a1 | 158 | /* Conditional execution test register (CC0..CC7). */ |
36a05131 BS |
159 | rtx cr_reg; |
160 | ||
161 | /* Conditional execution compare register that is paired with cr_reg, so that | |
162 | nested compares can be done. The csubcc and caddcc instructions don't | |
163 | have enough bits to specify both a CC register to be set and a CR register | |
164 | to do the test on, so the same bit number is used for both. Needless to | |
839a4992 | 165 | say, this is rather inconvenient for GCC. */ |
36a05131 BS |
166 | rtx nested_cc_reg; |
167 | ||
168 | /* Extra CR registers used for &&, ||. */ | |
169 | rtx extra_int_cr; | |
170 | rtx extra_fp_cr; | |
171 | ||
172 | /* Previous CR used in nested if, to make sure we are dealing with the same | |
87b483a1 | 173 | nested if as the previous statement. */ |
36a05131 BS |
174 | rtx last_nested_if_cr; |
175 | } | |
176 | frv_ifcvt_t; | |
177 | ||
178 | static /* GTY(()) */ frv_ifcvt_t frv_ifcvt; | |
179 | ||
180 | /* Map register number to smallest register class. */ | |
181 | enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; | |
182 | ||
87b483a1 | 183 | /* Map class letter into register class. */ |
36a05131 BS |
184 | enum reg_class reg_class_from_letter[256]; |
185 | ||
87b483a1 | 186 | /* Cached value of frv_stack_info. */ |
36a05131 BS |
187 | static frv_stack_t *frv_stack_cache = (frv_stack_t *)0; |
188 | ||
189 | /* -mbranch-cost= support */ | |
190 | const char *frv_branch_cost_string; | |
191 | int frv_branch_cost_int = DEFAULT_BRANCH_COST; | |
192 | ||
193 | /* -mcpu= support */ | |
194 | const char *frv_cpu_string; /* -mcpu= option */ | |
195 | frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */ | |
196 | ||
197 | /* -mcond-exec-insns= support */ | |
198 | const char *frv_condexec_insns_str; /* -mcond-exec-insns= option */ | |
199 | int frv_condexec_insns = DEFAULT_CONDEXEC_INSNS; /* value of -mcond-exec-insns*/ | |
200 | ||
201 | /* -mcond-exec-temps= support */ | |
202 | const char *frv_condexec_temps_str; /* -mcond-exec-temps= option */ | |
203 | int frv_condexec_temps = DEFAULT_CONDEXEC_TEMPS; /* value of -mcond-exec-temps*/ | |
204 | ||
205 | /* -msched-lookahead=n */ | |
206 | const char *frv_sched_lookahead_str; /* -msched-lookahead=n */ | |
207 | int frv_sched_lookahead = 4; /* -msched-lookahead=n */ | |
208 | ||
209 | /* Forward references */ | |
f2206911 KC |
210 | static int frv_default_flags_for_cpu (void); |
211 | static int frv_string_begins_with (tree, const char *); | |
34208acf AO |
212 | static FRV_INLINE bool frv_small_data_reloc_p (rtx, int); |
213 | static FRV_INLINE bool frv_const_unspec_p (rtx, struct frv_unspec *); | |
36a05131 | 214 | static void frv_print_operand_memory_reference_reg |
f2206911 KC |
215 | (FILE *, rtx); |
216 | static void frv_print_operand_memory_reference (FILE *, rtx, int); | |
217 | static int frv_print_operand_jump_hint (rtx); | |
218 | static FRV_INLINE int frv_regno_ok_for_base_p (int, int); | |
219 | static rtx single_set_pattern (rtx); | |
220 | static int frv_function_contains_far_jump (void); | |
221 | static rtx frv_alloc_temp_reg (frv_tmp_reg_t *, | |
222 | enum reg_class, | |
223 | enum machine_mode, | |
224 | int, int); | |
225 | static rtx frv_frame_offset_rtx (int); | |
226 | static rtx frv_frame_mem (enum machine_mode, rtx, int); | |
227 | static rtx frv_dwarf_store (rtx, int); | |
228 | static void frv_frame_insn (rtx, rtx); | |
229 | static void frv_frame_access (frv_frame_accessor_t*, | |
230 | rtx, int); | |
231 | static void frv_frame_access_multi (frv_frame_accessor_t*, | |
232 | frv_stack_t *, int); | |
233 | static void frv_frame_access_standard_regs (enum frv_stack_op, | |
234 | frv_stack_t *); | |
235 | static struct machine_function *frv_init_machine_status (void); | |
236 | static int frv_legitimate_memory_operand (rtx, enum machine_mode, int); | |
237 | static rtx frv_int_to_acc (enum insn_code, int, rtx); | |
238 | static enum machine_mode frv_matching_accg_mode (enum machine_mode); | |
239 | static rtx frv_read_argument (tree *); | |
240 | static int frv_check_constant_argument (enum insn_code, int, rtx); | |
241 | static rtx frv_legitimize_target (enum insn_code, rtx); | |
242 | static rtx frv_legitimize_argument (enum insn_code, int, rtx); | |
243 | static rtx frv_expand_set_builtin (enum insn_code, tree, rtx); | |
244 | static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx); | |
245 | static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx); | |
246 | static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx); | |
247 | static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx); | |
248 | static rtx frv_expand_voidbinop_builtin (enum insn_code, tree); | |
249 | static rtx frv_expand_voidtriop_builtin (enum insn_code, tree); | |
250 | static rtx frv_expand_voidaccop_builtin (enum insn_code, tree); | |
251 | static rtx frv_expand_mclracc_builtin (tree); | |
252 | static rtx frv_expand_mrdacc_builtin (enum insn_code, tree); | |
253 | static rtx frv_expand_mwtacc_builtin (enum insn_code, tree); | |
254 | static rtx frv_expand_noargs_builtin (enum insn_code); | |
255 | static rtx frv_emit_comparison (enum rtx_code, rtx, rtx); | |
256 | static int frv_clear_registers_used (rtx *, void *); | |
257 | static void frv_ifcvt_add_insn (rtx, rtx, int); | |
258 | static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx); | |
259 | static rtx frv_ifcvt_load_value (rtx, rtx); | |
260 | static void frv_registers_update (rtx, unsigned char [], | |
261 | int [], int *, int); | |
262 | static int frv_registers_used_p (rtx, unsigned char [], int); | |
263 | static int frv_registers_set_p (rtx, unsigned char [], int); | |
264 | static int frv_issue_rate (void); | |
f2206911 KC |
265 | static void frv_pack_insns (void); |
266 | static void frv_function_prologue (FILE *, HOST_WIDE_INT); | |
267 | static void frv_function_epilogue (FILE *, HOST_WIDE_INT); | |
268 | static bool frv_assemble_integer (rtx, unsigned, int); | |
269 | static void frv_init_builtins (void); | |
270 | static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
271 | static void frv_init_libfuncs (void); | |
272 | static bool frv_in_small_data_p (tree); | |
3961e8fe | 273 | static void frv_asm_output_mi_thunk |
f2206911 | 274 | (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree); |
d8c2bed3 KH |
275 | static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *, |
276 | enum machine_mode, | |
277 | tree, int *, int); | |
8ac411c7 | 278 | static rtx frv_expand_builtin_saveregs (void); |
f2206911 KC |
279 | static bool frv_rtx_costs (rtx, int, int, int*); |
280 | static void frv_asm_out_constructor (rtx, int); | |
281 | static void frv_asm_out_destructor (rtx, int); | |
34208acf AO |
282 | static bool frv_function_symbol_referenced_p (rtx); |
283 | static bool frv_cannot_force_const_mem (rtx); | |
284 | static const char *unspec_got_name (int); | |
285 | static void frv_output_const_unspec (FILE *, | |
286 | const struct frv_unspec *); | |
764678d1 | 287 | static bool frv_function_ok_for_sibcall (tree, tree); |
8ac411c7 | 288 | static rtx frv_struct_value_rtx (tree, int); |
fe984136 | 289 | static bool frv_must_pass_in_stack (enum machine_mode mode, tree type); |
36a05131 BS |
290 | \f |
291 | /* Initialize the GCC target structure. */ | |
292 | #undef TARGET_ASM_FUNCTION_PROLOGUE | |
293 | #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue | |
294 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
295 | #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue | |
296 | #undef TARGET_ASM_INTEGER | |
297 | #define TARGET_ASM_INTEGER frv_assemble_integer | |
14966b94 KG |
298 | #undef TARGET_INIT_BUILTINS |
299 | #define TARGET_INIT_BUILTINS frv_init_builtins | |
300 | #undef TARGET_EXPAND_BUILTIN | |
301 | #define TARGET_EXPAND_BUILTIN frv_expand_builtin | |
c15c90bb ZW |
302 | #undef TARGET_INIT_LIBFUNCS |
303 | #define TARGET_INIT_LIBFUNCS frv_init_libfuncs | |
b3fbfc07 KG |
304 | #undef TARGET_IN_SMALL_DATA_P |
305 | #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p | |
3c50106f RH |
306 | #undef TARGET_RTX_COSTS |
307 | #define TARGET_RTX_COSTS frv_rtx_costs | |
90a63880 RH |
308 | #undef TARGET_ASM_CONSTRUCTOR |
309 | #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor | |
310 | #undef TARGET_ASM_DESTRUCTOR | |
311 | #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor | |
36a05131 | 312 | |
c590b625 RH |
313 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
314 | #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk | |
3961e8fe RH |
315 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
316 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
c590b625 | 317 | |
28a60850 RS |
318 | #undef TARGET_SCHED_ISSUE_RATE |
319 | #define TARGET_SCHED_ISSUE_RATE frv_issue_rate | |
ffb344c1 | 320 | #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE |
ca4f3d13 | 321 | #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1 |
ffb344c1 | 322 | |
764678d1 AO |
323 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
324 | #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall | |
34208acf AO |
325 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
326 | #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem | |
327 | ||
8ac411c7 KH |
328 | #undef TARGET_STRUCT_VALUE_RTX |
329 | #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx | |
fe984136 RH |
330 | #undef TARGET_MUST_PASS_IN_STACK |
331 | #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack | |
8ac411c7 KH |
332 | |
333 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
334 | #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs | |
d8c2bed3 KH |
335 | #undef TARGET_SETUP_INCOMING_VARARGS |
336 | #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs | |
8ac411c7 | 337 | |
36a05131 BS |
338 | struct gcc_target targetm = TARGET_INITIALIZER; |
339 | \f | |
764678d1 AO |
340 | /* Any function call that satisfies the machine-independent |
341 | requirements is eligible on FR-V. */ | |
342 | ||
343 | static bool | |
344 | frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED, | |
345 | tree exp ATTRIBUTE_UNUSED) | |
346 | { | |
347 | return true; | |
348 | } | |
349 | ||
34208acf AO |
350 | /* Return true if SYMBOL is a small data symbol and relocation RELOC |
351 | can be used to access it directly in a load or store. */ | |
36a05131 | 352 | |
34208acf AO |
353 | static FRV_INLINE bool |
354 | frv_small_data_reloc_p (rtx symbol, int reloc) | |
36a05131 | 355 | { |
34208acf AO |
356 | return (GET_CODE (symbol) == SYMBOL_REF |
357 | && SYMBOL_REF_SMALL_P (symbol) | |
358 | && (!TARGET_FDPIC || flag_pic == 1) | |
359 | && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12)); | |
360 | } | |
36a05131 | 361 | |
34208acf AO |
362 | /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC |
363 | appropriately. */ | |
36a05131 | 364 | |
34208acf AO |
365 | static FRV_INLINE bool |
366 | frv_const_unspec_p (rtx x, struct frv_unspec *unspec) | |
367 | { | |
368 | if (GET_CODE (x) == CONST) | |
369 | { | |
370 | unspec->offset = 0; | |
371 | x = XEXP (x, 0); | |
372 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
373 | { | |
374 | unspec->offset += INTVAL (XEXP (x, 1)); | |
375 | x = XEXP (x, 0); | |
376 | } | |
377 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT) | |
378 | { | |
379 | unspec->symbol = XVECEXP (x, 0, 0); | |
380 | unspec->reloc = INTVAL (XVECEXP (x, 0, 1)); | |
36a05131 | 381 | |
34208acf AO |
382 | if (unspec->offset == 0) |
383 | return true; | |
36a05131 | 384 | |
34208acf AO |
385 | if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc) |
386 | && unspec->offset > 0 | |
387 | && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value) | |
388 | return true; | |
389 | } | |
390 | } | |
391 | return false; | |
36a05131 BS |
392 | } |
393 | ||
34208acf AO |
394 | /* Decide whether we can force certain constants to memory. If we |
395 | decide we can't, the caller should be able to cope with it in | |
396 | another way. | |
36a05131 | 397 | |
34208acf AO |
398 | We never allow constants to be forced into memory for TARGET_FDPIC. |
399 | This is necessary for several reasons: | |
36a05131 | 400 | |
34208acf AO |
401 | 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the |
402 | target-independent code will try to force them into the constant | |
403 | pool, thus leading to infinite recursion. | |
36a05131 | 404 | |
34208acf AO |
405 | 2. We can never introduce new constant pool references during reload. |
406 | Any such reference would require use of the pseudo FDPIC register. | |
36a05131 | 407 | |
34208acf AO |
408 | 3. We can't represent a constant added to a function pointer (which is |
409 | not the same as a pointer to a function+constant). | |
410 | ||
411 | 4. In many cases, it's more efficient to calculate the constant in-line. */ | |
412 | ||
413 | static bool | |
414 | frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED) | |
415 | { | |
416 | return TARGET_FDPIC; | |
417 | } | |
36a05131 BS |
418 | \f |
419 | static int | |
f2206911 | 420 | frv_default_flags_for_cpu (void) |
36a05131 BS |
421 | { |
422 | switch (frv_cpu_type) | |
423 | { | |
424 | case FRV_CPU_GENERIC: | |
425 | return MASK_DEFAULT_FRV; | |
426 | ||
427 | case FRV_CPU_FR500: | |
428 | case FRV_CPU_TOMCAT: | |
429 | return MASK_DEFAULT_FR500; | |
430 | ||
431 | case FRV_CPU_FR400: | |
432 | return MASK_DEFAULT_FR400; | |
433 | ||
434 | case FRV_CPU_FR300: | |
435 | case FRV_CPU_SIMPLE: | |
436 | return MASK_DEFAULT_SIMPLE; | |
437 | } | |
438 | abort (); | |
439 | } | |
440 | ||
441 | /* Sometimes certain combinations of command options do not make | |
442 | sense on a particular target machine. You can define a macro | |
443 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
444 | defined, is executed once just after all the command options have | |
445 | been parsed. | |
446 | ||
447 | Don't use this macro to turn on various extra optimizations for | |
448 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
449 | ||
450 | void | |
f2206911 | 451 | frv_override_options (void) |
36a05131 BS |
452 | { |
453 | int regno, i; | |
454 | ||
87b483a1 | 455 | /* Set the cpu type. */ |
36a05131 BS |
456 | if (frv_cpu_string) |
457 | { | |
458 | if (strcmp (frv_cpu_string, "simple") == 0) | |
459 | frv_cpu_type = FRV_CPU_SIMPLE; | |
460 | ||
461 | else if (strcmp (frv_cpu_string, "tomcat") == 0) | |
462 | frv_cpu_type = FRV_CPU_TOMCAT; | |
463 | ||
464 | else if (strncmp (frv_cpu_string, "fr", sizeof ("fr")-1) != 0) | |
465 | error ("Unknown cpu: -mcpu=%s", frv_cpu_string); | |
466 | ||
467 | else | |
468 | { | |
469 | const char *p = frv_cpu_string + sizeof ("fr") - 1; | |
470 | if (strcmp (p, "500") == 0) | |
471 | frv_cpu_type = FRV_CPU_FR500; | |
472 | ||
473 | else if (strcmp (p, "400") == 0) | |
474 | frv_cpu_type = FRV_CPU_FR400; | |
475 | ||
476 | else if (strcmp (p, "300") == 0) | |
477 | frv_cpu_type = FRV_CPU_FR300; | |
478 | ||
479 | else if (strcmp (p, "v") == 0) | |
480 | frv_cpu_type = FRV_CPU_GENERIC; | |
481 | ||
482 | else | |
483 | error ("Unknown cpu: -mcpu=%s", frv_cpu_string); | |
484 | } | |
485 | } | |
486 | ||
487 | target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit); | |
488 | ||
489 | /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the | |
490 | linker about linking pic and non-pic code. */ | |
491 | if (TARGET_LIBPIC) | |
492 | { | |
493 | if (!flag_pic) /* -fPIC */ | |
494 | flag_pic = 2; | |
495 | ||
496 | if (! g_switch_set) /* -G0 */ | |
497 | { | |
498 | g_switch_set = 1; | |
499 | g_switch_value = 0; | |
500 | } | |
501 | } | |
502 | ||
503 | /* Both -fpic and -gdwarf want to use .previous and the assembler only keeps | |
504 | one level. */ | |
505 | if (write_symbols == DWARF_DEBUG && flag_pic) | |
506 | error ("-fpic and -gdwarf are incompatible (-fpic and -g/-gdwarf-2 are fine)"); | |
507 | ||
87b483a1 | 508 | /* Change the branch cost value. */ |
36a05131 BS |
509 | if (frv_branch_cost_string) |
510 | frv_branch_cost_int = atoi (frv_branch_cost_string); | |
511 | ||
87b483a1 | 512 | /* Change the # of insns to be converted to conditional execution. */ |
36a05131 BS |
513 | if (frv_condexec_insns_str) |
514 | frv_condexec_insns = atoi (frv_condexec_insns_str); | |
515 | ||
87b483a1 | 516 | /* Change # of temporary registers used to hold integer constants. */ |
36a05131 BS |
517 | if (frv_condexec_temps_str) |
518 | frv_condexec_temps = atoi (frv_condexec_temps_str); | |
519 | ||
87b483a1 | 520 | /* Change scheduling look ahead. */ |
36a05131 BS |
521 | if (frv_sched_lookahead_str) |
522 | frv_sched_lookahead = atoi (frv_sched_lookahead_str); | |
523 | ||
524 | /* A C expression whose value is a register class containing hard | |
525 | register REGNO. In general there is more than one such class; | |
526 | choose a class which is "minimal", meaning that no smaller class | |
87b483a1 | 527 | also contains the register. */ |
36a05131 BS |
528 | |
529 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
530 | { | |
531 | enum reg_class class; | |
532 | ||
533 | if (GPR_P (regno)) | |
534 | { | |
535 | int gpr_reg = regno - GPR_FIRST; | |
536 | if ((gpr_reg & 3) == 0) | |
537 | class = QUAD_REGS; | |
538 | ||
539 | else if ((gpr_reg & 1) == 0) | |
540 | class = EVEN_REGS; | |
541 | ||
542 | else | |
543 | class = GPR_REGS; | |
544 | } | |
545 | ||
546 | else if (FPR_P (regno)) | |
547 | { | |
548 | int fpr_reg = regno - GPR_FIRST; | |
549 | if ((fpr_reg & 3) == 0) | |
550 | class = QUAD_FPR_REGS; | |
551 | ||
552 | else if ((fpr_reg & 1) == 0) | |
553 | class = FEVEN_REGS; | |
554 | ||
555 | else | |
556 | class = FPR_REGS; | |
557 | } | |
558 | ||
559 | else if (regno == LR_REGNO) | |
560 | class = LR_REG; | |
561 | ||
562 | else if (regno == LCR_REGNO) | |
563 | class = LCR_REG; | |
564 | ||
565 | else if (ICC_P (regno)) | |
566 | class = ICC_REGS; | |
567 | ||
568 | else if (FCC_P (regno)) | |
569 | class = FCC_REGS; | |
570 | ||
571 | else if (ICR_P (regno)) | |
572 | class = ICR_REGS; | |
573 | ||
574 | else if (FCR_P (regno)) | |
575 | class = FCR_REGS; | |
576 | ||
577 | else if (ACC_P (regno)) | |
578 | { | |
579 | int r = regno - ACC_FIRST; | |
580 | if ((r & 3) == 0) | |
581 | class = QUAD_ACC_REGS; | |
582 | else if ((r & 1) == 0) | |
583 | class = EVEN_ACC_REGS; | |
584 | else | |
585 | class = ACC_REGS; | |
586 | } | |
587 | ||
588 | else if (ACCG_P (regno)) | |
589 | class = ACCG_REGS; | |
590 | ||
591 | else | |
592 | class = NO_REGS; | |
593 | ||
594 | regno_reg_class[regno] = class; | |
595 | } | |
596 | ||
597 | /* Check for small data option */ | |
598 | if (!g_switch_set) | |
599 | g_switch_value = SDATA_DEFAULT_SIZE; | |
600 | ||
601 | /* A C expression which defines the machine-dependent operand | |
602 | constraint letters for register classes. If CHAR is such a | |
603 | letter, the value should be the register class corresponding to | |
604 | it. Otherwise, the value should be `NO_REGS'. The register | |
605 | letter `r', corresponding to class `GENERAL_REGS', will not be | |
606 | passed to this macro; you do not need to handle it. | |
607 | ||
608 | The following letters are unavailable, due to being used as | |
609 | constraints: | |
610 | '0'..'9' | |
611 | '<', '>' | |
612 | 'E', 'F', 'G', 'H' | |
613 | 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P' | |
614 | 'Q', 'R', 'S', 'T', 'U' | |
615 | 'V', 'X' | |
616 | 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */ | |
617 | ||
618 | for (i = 0; i < 256; i++) | |
619 | reg_class_from_letter[i] = NO_REGS; | |
620 | ||
621 | reg_class_from_letter['a'] = ACC_REGS; | |
622 | reg_class_from_letter['b'] = EVEN_ACC_REGS; | |
623 | reg_class_from_letter['c'] = CC_REGS; | |
624 | reg_class_from_letter['d'] = GPR_REGS; | |
625 | reg_class_from_letter['e'] = EVEN_REGS; | |
626 | reg_class_from_letter['f'] = FPR_REGS; | |
627 | reg_class_from_letter['h'] = FEVEN_REGS; | |
628 | reg_class_from_letter['l'] = LR_REG; | |
629 | reg_class_from_letter['q'] = QUAD_REGS; | |
630 | reg_class_from_letter['t'] = ICC_REGS; | |
631 | reg_class_from_letter['u'] = FCC_REGS; | |
632 | reg_class_from_letter['v'] = ICR_REGS; | |
633 | reg_class_from_letter['w'] = FCR_REGS; | |
634 | reg_class_from_letter['x'] = QUAD_FPR_REGS; | |
635 | reg_class_from_letter['y'] = LCR_REG; | |
636 | reg_class_from_letter['z'] = SPR_REGS; | |
637 | reg_class_from_letter['A'] = QUAD_ACC_REGS; | |
638 | reg_class_from_letter['B'] = ACCG_REGS; | |
639 | reg_class_from_letter['C'] = CR_REGS; | |
34208acf AO |
640 | reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */ |
641 | reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */ | |
36a05131 BS |
642 | |
643 | /* There is no single unaligned SI op for PIC code. Sometimes we | |
644 | need to use ".4byte" and sometimes we need to use ".picptr". | |
645 | See frv_assemble_integer for details. */ | |
34208acf | 646 | if (flag_pic || TARGET_FDPIC) |
36a05131 BS |
647 | targetm.asm_out.unaligned_op.si = 0; |
648 | ||
34208acf AO |
649 | if ((target_flags_explicit & MASK_LINKED_FP) == 0) |
650 | target_flags |= MASK_LINKED_FP; | |
651 | ||
36a05131 BS |
652 | init_machine_status = frv_init_machine_status; |
653 | } | |
654 | ||
655 | \f | |
656 | /* Some machines may desire to change what optimizations are performed for | |
657 | various optimization levels. This macro, if defined, is executed once just | |
658 | after the optimization level is determined and before the remainder of the | |
659 | command options have been parsed. Values set in this macro are used as the | |
660 | default values for the other command line options. | |
661 | ||
662 | LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if | |
663 | `-O' is specified, and 0 if neither is specified. | |
664 | ||
9cd10576 | 665 | SIZE is nonzero if `-Os' is specified, 0 otherwise. |
36a05131 BS |
666 | |
667 | You should not use this macro to change options that are not | |
668 | machine-specific. These should uniformly selected by the same optimization | |
669 | level on all supported machines. Use this macro to enable machbine-specific | |
670 | optimizations. | |
671 | ||
672 | *Do not examine `write_symbols' in this macro!* The debugging options are | |
673 | *not supposed to alter the generated code. */ | |
674 | ||
675 | /* On the FRV, possibly disable VLIW packing which is done by the 2nd | |
676 | scheduling pass at the current time. */ | |
677 | void | |
f2206911 | 678 | frv_optimization_options (int level, int size ATTRIBUTE_UNUSED) |
36a05131 BS |
679 | { |
680 | if (level >= 2) | |
681 | { | |
682 | #ifdef DISABLE_SCHED2 | |
683 | flag_schedule_insns_after_reload = 0; | |
684 | #endif | |
685 | #ifdef ENABLE_RCSP | |
686 | flag_rcsp = 1; | |
687 | #endif | |
688 | } | |
689 | } | |
690 | ||
36a05131 BS |
691 | \f |
692 | /* Return true if NAME (a STRING_CST node) begins with PREFIX. */ | |
693 | ||
694 | static int | |
f2206911 | 695 | frv_string_begins_with (tree name, const char *prefix) |
36a05131 BS |
696 | { |
697 | int prefix_len = strlen (prefix); | |
698 | ||
699 | /* Remember: NAME's length includes the null terminator. */ | |
700 | return (TREE_STRING_LENGTH (name) > prefix_len | |
701 | && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0); | |
702 | } | |
36a05131 BS |
703 | \f |
704 | /* Zero or more C statements that may conditionally modify two variables | |
705 | `fixed_regs' and `call_used_regs' (both of type `char []') after they have | |
706 | been initialized from the two preceding macros. | |
707 | ||
708 | This is necessary in case the fixed or call-clobbered registers depend on | |
709 | target flags. | |
710 | ||
711 | You need not define this macro if it has no work to do. | |
712 | ||
713 | If the usage of an entire class of registers depends on the target flags, | |
714 | you may indicate this to GCC by using this macro to modify `fixed_regs' and | |
715 | `call_used_regs' to 1 for each of the registers in the classes which should | |
716 | not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return | |
717 | `NO_REGS' if it is called with a letter for a class that shouldn't be used. | |
718 | ||
719 | (However, if this class is not included in `GENERAL_REGS' and all of the | |
720 | insn patterns whose constraints permit this class are controlled by target | |
721 | switches, then GCC will automatically avoid using these registers when the | |
722 | target switches are opposed to them.) */ | |
723 | ||
724 | void | |
f2206911 | 725 | frv_conditional_register_usage (void) |
36a05131 BS |
726 | { |
727 | int i; | |
728 | ||
729 | for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++) | |
730 | fixed_regs[i] = call_used_regs[i] = 1; | |
731 | ||
732 | for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++) | |
733 | fixed_regs[i] = call_used_regs[i] = 1; | |
734 | ||
735 | for (i = ACC_FIRST + NUM_ACCS; i <= ACC_LAST; i++) | |
736 | fixed_regs[i] = call_used_regs[i] = 1; | |
737 | ||
738 | for (i = ACCG_FIRST + NUM_ACCS; i <= ACCG_LAST; i++) | |
739 | fixed_regs[i] = call_used_regs[i] = 1; | |
740 | ||
741 | /* Reserve the registers used for conditional execution. At present, we need | |
742 | 1 ICC and 1 ICR register. */ | |
743 | fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1; | |
744 | fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1; | |
745 | ||
746 | if (TARGET_FIXED_CC) | |
747 | { | |
748 | fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1; | |
749 | fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1; | |
750 | fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1; | |
751 | fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1; | |
752 | } | |
753 | ||
34208acf AO |
754 | if (TARGET_FDPIC) |
755 | fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] = | |
756 | call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0; | |
757 | ||
36a05131 BS |
758 | #if 0 |
759 | /* If -fpic, SDA_BASE_REG is the PIC register. */ | |
760 | if (g_switch_value == 0 && !flag_pic) | |
761 | fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0; | |
762 | ||
763 | if (!flag_pic) | |
764 | fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0; | |
765 | #endif | |
766 | } | |
767 | ||
768 | \f | |
769 | /* | |
770 | * Compute the stack frame layout | |
771 | * | |
772 | * Register setup: | |
773 | * +---------------+-----------------------+-----------------------+ | |
774 | * |Register |type |caller-save/callee-save| | |
775 | * +---------------+-----------------------+-----------------------+ | |
776 | * |GR0 |Zero register | - | | |
777 | * |GR1 |Stack pointer(SP) | - | | |
778 | * |GR2 |Frame pointer(FP) | - | | |
779 | * |GR3 |Hidden parameter | caller save | | |
780 | * |GR4-GR7 | - | caller save | | |
781 | * |GR8-GR13 |Argument register | caller save | | |
782 | * |GR14-GR15 | - | caller save | | |
783 | * |GR16-GR31 | - | callee save | | |
784 | * |GR32-GR47 | - | caller save | | |
785 | * |GR48-GR63 | - | callee save | | |
786 | * |FR0-FR15 | - | caller save | | |
787 | * |FR16-FR31 | - | callee save | | |
788 | * |FR32-FR47 | - | caller save | | |
789 | * |FR48-FR63 | - | callee save | | |
790 | * +---------------+-----------------------+-----------------------+ | |
791 | * | |
792 | * Stack frame setup: | |
793 | * Low | |
794 | * SP-> |-----------------------------------| | |
795 | * | Argument area | | |
796 | * |-----------------------------------| | |
797 | * | Register save area | | |
798 | * |-----------------------------------| | |
799 | * | Local variable save area | | |
800 | * FP-> |-----------------------------------| | |
801 | * | Old FP | | |
802 | * |-----------------------------------| | |
803 | * | Hidden parameter save area | | |
804 | * |-----------------------------------| | |
805 | * | Return address(LR) storage area | | |
806 | * |-----------------------------------| | |
807 | * | Padding for alignment | | |
808 | * |-----------------------------------| | |
809 | * | Register argument area | | |
810 | * OLD SP-> |-----------------------------------| | |
811 | * | Parameter area | | |
812 | * |-----------------------------------| | |
813 | * High | |
814 | * | |
815 | * Argument area/Parameter area: | |
816 | * | |
817 | * When a function is called, this area is used for argument transfer. When | |
818 | * the argument is set up by the caller function, this area is referred to as | |
819 | * the argument area. When the argument is referenced by the callee function, | |
820 | * this area is referred to as the parameter area. The area is allocated when | |
821 | * all arguments cannot be placed on the argument register at the time of | |
822 | * argument transfer. | |
823 | * | |
824 | * Register save area: | |
825 | * | |
826 | * This is a register save area that must be guaranteed for the caller | |
827 | * function. This area is not secured when the register save operation is not | |
828 | * needed. | |
829 | * | |
830 | * Local variable save area: | |
831 | * | |
832 | * This is the area for local variables and temporary variables. | |
833 | * | |
834 | * Old FP: | |
835 | * | |
836 | * This area stores the FP value of the caller function. | |
837 | * | |
838 | * Hidden parameter save area: | |
839 | * | |
840 | * This area stores the start address of the return value storage | |
841 | * area for a struct/union return function. | |
842 | * When a struct/union is used as the return value, the caller | |
843 | * function stores the return value storage area start address in | |
844 | * register GR3 and passes it to the caller function. | |
845 | * The callee function interprets the address stored in the GR3 | |
846 | * as the return value storage area start address. | |
847 | * When register GR3 needs to be saved into memory, the callee | |
848 | * function saves it in the hidden parameter save area. This | |
849 | * area is not secured when the save operation is not needed. | |
850 | * | |
851 | * Return address(LR) storage area: | |
852 | * | |
853 | * This area saves the LR. The LR stores the address of a return to the caller | |
854 | * function for the purpose of function calling. | |
855 | * | |
856 | * Argument register area: | |
857 | * | |
858 | * This area saves the argument register. This area is not secured when the | |
859 | * save operation is not needed. | |
860 | * | |
861 | * Argument: | |
862 | * | |
863 | * Arguments, the count of which equals the count of argument registers (6 | |
864 | * words), are positioned in registers GR8 to GR13 and delivered to the callee | |
865 | * function. When a struct/union return function is called, the return value | |
866 | * area address is stored in register GR3. Arguments not placed in the | |
867 | * argument registers will be stored in the stack argument area for transfer | |
868 | * purposes. When an 8-byte type argument is to be delivered using registers, | |
869 | * it is divided into two and placed in two registers for transfer. When | |
870 | * argument registers must be saved to memory, the callee function secures an | |
871 | * argument register save area in the stack. In this case, a continuous | |
872 | * argument register save area must be established in the parameter area. The | |
873 | * argument register save area must be allocated as needed to cover the size of | |
874 | * the argument register to be saved. If the function has a variable count of | |
875 | * arguments, it saves all argument registers in the argument register save | |
876 | * area. | |
877 | * | |
878 | * Argument Extension Format: | |
879 | * | |
880 | * When an argument is to be stored in the stack, its type is converted to an | |
881 | * extended type in accordance with the individual argument type. The argument | |
882 | * is freed by the caller function after the return from the callee function is | |
883 | * made. | |
884 | * | |
885 | * +-----------------------+---------------+------------------------+ | |
886 | * | Argument Type |Extended Type |Stack Storage Size(byte)| | |
887 | * +-----------------------+---------------+------------------------+ | |
888 | * |char |int | 4 | | |
889 | * |signed char |int | 4 | | |
890 | * |unsigned char |int | 4 | | |
891 | * |[signed] short int |int | 4 | | |
892 | * |unsigned short int |int | 4 | | |
893 | * |[signed] int |No extension | 4 | | |
894 | * |unsigned int |No extension | 4 | | |
895 | * |[signed] long int |No extension | 4 | | |
896 | * |unsigned long int |No extension | 4 | | |
897 | * |[signed] long long int |No extension | 8 | | |
898 | * |unsigned long long int |No extension | 8 | | |
899 | * |float |double | 8 | | |
900 | * |double |No extension | 8 | | |
901 | * |long double |No extension | 8 | | |
902 | * |pointer |No extension | 4 | | |
903 | * |struct/union |- | 4 (*1) | | |
904 | * +-----------------------+---------------+------------------------+ | |
905 | * | |
906 | * When a struct/union is to be delivered as an argument, the caller copies it | |
907 | * to the local variable area and delivers the address of that area. | |
908 | * | |
909 | * Return Value: | |
910 | * | |
911 | * +-------------------------------+----------------------+ | |
912 | * |Return Value Type |Return Value Interface| | |
913 | * +-------------------------------+----------------------+ | |
914 | * |void |None | | |
915 | * |[signed|unsigned] char |GR8 | | |
916 | * |[signed|unsigned] short int |GR8 | | |
917 | * |[signed|unsigned] int |GR8 | | |
918 | * |[signed|unsigned] long int |GR8 | | |
919 | * |pointer |GR8 | | |
920 | * |[signed|unsigned] long long int|GR8 & GR9 | | |
921 | * |float |GR8 | | |
922 | * |double |GR8 & GR9 | | |
923 | * |long double |GR8 & GR9 | | |
924 | * |struct/union |(*1) | | |
925 | * +-------------------------------+----------------------+ | |
926 | * | |
927 | * When a struct/union is used as the return value, the caller function stores | |
928 | * the start address of the return value storage area into GR3 and then passes | |
929 | * it to the callee function. The callee function interprets GR3 as the start | |
930 | * address of the return value storage area. When this address needs to be | |
931 | * saved in memory, the callee function secures the hidden parameter save area | |
932 | * and saves the address in that area. | |
933 | */ | |
934 | ||
935 | frv_stack_t * | |
f2206911 | 936 | frv_stack_info (void) |
36a05131 BS |
937 | { |
938 | static frv_stack_t info, zero_info; | |
939 | frv_stack_t *info_ptr = &info; | |
940 | tree fndecl = current_function_decl; | |
941 | int varargs_p = 0; | |
942 | tree cur_arg; | |
943 | tree next_arg; | |
944 | int range; | |
945 | int alignment; | |
946 | int offset; | |
947 | ||
87b483a1 KH |
948 | /* If we've already calculated the values and reload is complete, |
949 | just return now. */ | |
36a05131 BS |
950 | if (frv_stack_cache) |
951 | return frv_stack_cache; | |
952 | ||
87b483a1 | 953 | /* Zero all fields. */ |
36a05131 BS |
954 | info = zero_info; |
955 | ||
87b483a1 | 956 | /* Set up the register range information. */ |
36a05131 BS |
957 | info_ptr->regs[STACK_REGS_GPR].name = "gpr"; |
958 | info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1; | |
959 | info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST; | |
960 | info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE; | |
961 | ||
962 | info_ptr->regs[STACK_REGS_FPR].name = "fpr"; | |
963 | info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST; | |
964 | info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST; | |
965 | info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE; | |
966 | ||
967 | info_ptr->regs[STACK_REGS_LR].name = "lr"; | |
968 | info_ptr->regs[STACK_REGS_LR].first = LR_REGNO; | |
969 | info_ptr->regs[STACK_REGS_LR].last = LR_REGNO; | |
970 | info_ptr->regs[STACK_REGS_LR].special_p = 1; | |
971 | ||
972 | info_ptr->regs[STACK_REGS_CC].name = "cc"; | |
973 | info_ptr->regs[STACK_REGS_CC].first = CC_FIRST; | |
974 | info_ptr->regs[STACK_REGS_CC].last = CC_LAST; | |
975 | info_ptr->regs[STACK_REGS_CC].field_p = TRUE; | |
976 | ||
977 | info_ptr->regs[STACK_REGS_LCR].name = "lcr"; | |
978 | info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO; | |
979 | info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO; | |
980 | ||
981 | info_ptr->regs[STACK_REGS_STDARG].name = "stdarg"; | |
982 | info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM; | |
983 | info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM; | |
984 | info_ptr->regs[STACK_REGS_STDARG].dword_p = 1; | |
985 | info_ptr->regs[STACK_REGS_STDARG].special_p = 1; | |
986 | ||
987 | info_ptr->regs[STACK_REGS_STRUCT].name = "struct"; | |
8ac411c7 KH |
988 | info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM; |
989 | info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM; | |
36a05131 BS |
990 | info_ptr->regs[STACK_REGS_STRUCT].special_p = 1; |
991 | ||
992 | info_ptr->regs[STACK_REGS_FP].name = "fp"; | |
993 | info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM; | |
994 | info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM; | |
995 | info_ptr->regs[STACK_REGS_FP].special_p = 1; | |
996 | ||
997 | /* Determine if this is a stdarg function. If so, allocate space to store | |
998 | the 6 arguments. */ | |
999 | if (cfun->stdarg) | |
1000 | varargs_p = 1; | |
1001 | ||
1002 | else | |
1003 | { | |
1004 | /* Find the last argument, and see if it is __builtin_va_alist. */ | |
1005 | for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg) | |
1006 | { | |
1007 | next_arg = TREE_CHAIN (cur_arg); | |
1008 | if (next_arg == (tree)0) | |
1009 | { | |
1010 | if (DECL_NAME (cur_arg) | |
1011 | && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist")) | |
1012 | varargs_p = 1; | |
1013 | ||
1014 | break; | |
1015 | } | |
1016 | } | |
1017 | } | |
1018 | ||
87b483a1 | 1019 | /* Iterate over all of the register ranges. */ |
36a05131 BS |
1020 | for (range = 0; range < STACK_REGS_MAX; range++) |
1021 | { | |
1022 | frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); | |
1023 | int first = reg_ptr->first; | |
1024 | int last = reg_ptr->last; | |
1025 | int size_1word = 0; | |
1026 | int size_2words = 0; | |
1027 | int regno; | |
1028 | ||
87b483a1 | 1029 | /* Calculate which registers need to be saved & save area size. */ |
36a05131 BS |
1030 | switch (range) |
1031 | { | |
1032 | default: | |
1033 | for (regno = first; regno <= last; regno++) | |
1034 | { | |
1035 | if ((regs_ever_live[regno] && !call_used_regs[regno]) | |
1036 | || (current_function_calls_eh_return | |
1037 | && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM)) | |
34208acf AO |
1038 | || (!TARGET_FDPIC && flag_pic |
1039 | && cfun->uses_pic_offset_table && regno == PIC_REGNO)) | |
36a05131 BS |
1040 | { |
1041 | info_ptr->save_p[regno] = REG_SAVE_1WORD; | |
1042 | size_1word += UNITS_PER_WORD; | |
1043 | } | |
1044 | } | |
1045 | break; | |
1046 | ||
1047 | /* Calculate whether we need to create a frame after everything else | |
1048 | has been processed. */ | |
1049 | case STACK_REGS_FP: | |
1050 | break; | |
1051 | ||
1052 | case STACK_REGS_LR: | |
1053 | if (regs_ever_live[LR_REGNO] | |
1054 | || profile_flag | |
34208acf AO |
1055 | /* This is set for __builtin_return_address, etc. */ |
1056 | || cfun->machine->frame_needed | |
1057 | || (TARGET_LINKED_FP && frame_pointer_needed) | |
1058 | || (!TARGET_FDPIC && flag_pic | |
1059 | && cfun->uses_pic_offset_table)) | |
36a05131 BS |
1060 | { |
1061 | info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD; | |
1062 | size_1word += UNITS_PER_WORD; | |
1063 | } | |
1064 | break; | |
1065 | ||
1066 | case STACK_REGS_STDARG: | |
1067 | if (varargs_p) | |
1068 | { | |
87b483a1 KH |
1069 | /* If this is a stdarg function with a non varardic |
1070 | argument split between registers and the stack, | |
1071 | adjust the saved registers downward. */ | |
36a05131 BS |
1072 | last -= (ADDR_ALIGN (cfun->pretend_args_size, UNITS_PER_WORD) |
1073 | / UNITS_PER_WORD); | |
1074 | ||
1075 | for (regno = first; regno <= last; regno++) | |
1076 | { | |
1077 | info_ptr->save_p[regno] = REG_SAVE_1WORD; | |
1078 | size_1word += UNITS_PER_WORD; | |
1079 | } | |
1080 | ||
1081 | info_ptr->stdarg_size = size_1word; | |
1082 | } | |
1083 | break; | |
1084 | ||
1085 | case STACK_REGS_STRUCT: | |
1086 | if (cfun->returns_struct) | |
1087 | { | |
8ac411c7 | 1088 | info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD; |
36a05131 BS |
1089 | size_1word += UNITS_PER_WORD; |
1090 | } | |
1091 | break; | |
1092 | } | |
1093 | ||
1094 | ||
1095 | if (size_1word) | |
1096 | { | |
87b483a1 | 1097 | /* If this is a field, it only takes one word. */ |
36a05131 BS |
1098 | if (reg_ptr->field_p) |
1099 | size_1word = UNITS_PER_WORD; | |
1100 | ||
87b483a1 | 1101 | /* Determine which register pairs can be saved together. */ |
36a05131 BS |
1102 | else if (reg_ptr->dword_p && TARGET_DWORD) |
1103 | { | |
1104 | for (regno = first; regno < last; regno += 2) | |
1105 | { | |
1106 | if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1]) | |
1107 | { | |
1108 | size_2words += 2 * UNITS_PER_WORD; | |
1109 | size_1word -= 2 * UNITS_PER_WORD; | |
1110 | info_ptr->save_p[regno] = REG_SAVE_2WORDS; | |
1111 | info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE; | |
1112 | } | |
1113 | } | |
1114 | } | |
1115 | ||
1116 | reg_ptr->size_1word = size_1word; | |
1117 | reg_ptr->size_2words = size_2words; | |
1118 | ||
1119 | if (! reg_ptr->special_p) | |
1120 | { | |
1121 | info_ptr->regs_size_1word += size_1word; | |
1122 | info_ptr->regs_size_2words += size_2words; | |
1123 | } | |
1124 | } | |
1125 | } | |
1126 | ||
1127 | /* Set up the sizes of each each field in the frame body, making the sizes | |
1128 | of each be divisible by the size of a dword if dword operations might | |
1129 | be used, or the size of a word otherwise. */ | |
1130 | alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD); | |
1131 | ||
1132 | info_ptr->parameter_size = ADDR_ALIGN (cfun->outgoing_args_size, alignment); | |
1133 | info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words | |
1134 | + info_ptr->regs_size_1word, | |
1135 | alignment); | |
1136 | info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment); | |
1137 | ||
1138 | info_ptr->pretend_size = cfun->pretend_args_size; | |
1139 | ||
1140 | /* Work out the size of the frame, excluding the header. Both the frame | |
1141 | body and register parameter area will be dword-aligned. */ | |
1142 | info_ptr->total_size | |
1143 | = (ADDR_ALIGN (info_ptr->parameter_size | |
1144 | + info_ptr->regs_size | |
1145 | + info_ptr->vars_size, | |
1146 | 2 * UNITS_PER_WORD) | |
1147 | + ADDR_ALIGN (info_ptr->pretend_size | |
1148 | + info_ptr->stdarg_size, | |
1149 | 2 * UNITS_PER_WORD)); | |
1150 | ||
1151 | /* See if we need to create a frame at all, if so add header area. */ | |
1152 | if (info_ptr->total_size > 0 | |
34208acf | 1153 | || frame_pointer_needed |
36a05131 BS |
1154 | || info_ptr->regs[STACK_REGS_LR].size_1word > 0 |
1155 | || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0) | |
1156 | { | |
1157 | offset = info_ptr->parameter_size; | |
1158 | info_ptr->header_size = 4 * UNITS_PER_WORD; | |
1159 | info_ptr->total_size += 4 * UNITS_PER_WORD; | |
1160 | ||
87b483a1 | 1161 | /* Calculate the offsets to save normal register pairs. */ |
36a05131 BS |
1162 | for (range = 0; range < STACK_REGS_MAX; range++) |
1163 | { | |
1164 | frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); | |
1165 | if (! reg_ptr->special_p) | |
1166 | { | |
1167 | int first = reg_ptr->first; | |
1168 | int last = reg_ptr->last; | |
1169 | int regno; | |
1170 | ||
1171 | for (regno = first; regno <= last; regno++) | |
1172 | if (info_ptr->save_p[regno] == REG_SAVE_2WORDS | |
1173 | && regno != FRAME_POINTER_REGNUM | |
1174 | && (regno < FIRST_ARG_REGNUM | |
1175 | || regno > LAST_ARG_REGNUM)) | |
1176 | { | |
1177 | info_ptr->reg_offset[regno] = offset; | |
1178 | offset += 2 * UNITS_PER_WORD; | |
1179 | } | |
1180 | } | |
1181 | } | |
1182 | ||
87b483a1 | 1183 | /* Calculate the offsets to save normal single registers. */ |
36a05131 BS |
1184 | for (range = 0; range < STACK_REGS_MAX; range++) |
1185 | { | |
1186 | frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); | |
1187 | if (! reg_ptr->special_p) | |
1188 | { | |
1189 | int first = reg_ptr->first; | |
1190 | int last = reg_ptr->last; | |
1191 | int regno; | |
1192 | ||
1193 | for (regno = first; regno <= last; regno++) | |
1194 | if (info_ptr->save_p[regno] == REG_SAVE_1WORD | |
1195 | && regno != FRAME_POINTER_REGNUM | |
1196 | && (regno < FIRST_ARG_REGNUM | |
1197 | || regno > LAST_ARG_REGNUM)) | |
1198 | { | |
1199 | info_ptr->reg_offset[regno] = offset; | |
1200 | offset += UNITS_PER_WORD; | |
1201 | } | |
1202 | } | |
1203 | } | |
1204 | ||
1205 | /* Calculate the offset to save the local variables at. */ | |
1206 | offset = ADDR_ALIGN (offset, alignment); | |
1207 | if (info_ptr->vars_size) | |
1208 | { | |
1209 | info_ptr->vars_offset = offset; | |
1210 | offset += info_ptr->vars_size; | |
1211 | } | |
1212 | ||
1213 | /* Align header to a dword-boundary. */ | |
1214 | offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD); | |
1215 | ||
1216 | /* Calculate the offsets in the fixed frame. */ | |
1217 | info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD; | |
1218 | info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset; | |
1219 | info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD; | |
1220 | ||
1221 | info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD; | |
1222 | info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD; | |
1223 | info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD; | |
1224 | ||
1225 | if (cfun->returns_struct) | |
1226 | { | |
8ac411c7 KH |
1227 | info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD; |
1228 | info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD; | |
36a05131 BS |
1229 | info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD; |
1230 | } | |
1231 | ||
1232 | /* Calculate the offsets to store the arguments passed in registers | |
1233 | for stdarg functions. The register pairs are first and the single | |
1234 | register if any is last. The register save area starts on a | |
1235 | dword-boundary. */ | |
1236 | if (info_ptr->stdarg_size) | |
1237 | { | |
1238 | int first = info_ptr->regs[STACK_REGS_STDARG].first; | |
1239 | int last = info_ptr->regs[STACK_REGS_STDARG].last; | |
1240 | int regno; | |
1241 | ||
1242 | /* Skip the header. */ | |
1243 | offset += 4 * UNITS_PER_WORD; | |
1244 | for (regno = first; regno <= last; regno++) | |
1245 | { | |
1246 | if (info_ptr->save_p[regno] == REG_SAVE_2WORDS) | |
1247 | { | |
1248 | info_ptr->reg_offset[regno] = offset; | |
1249 | offset += 2 * UNITS_PER_WORD; | |
1250 | } | |
1251 | else if (info_ptr->save_p[regno] == REG_SAVE_1WORD) | |
1252 | { | |
1253 | info_ptr->reg_offset[regno] = offset; | |
1254 | offset += UNITS_PER_WORD; | |
1255 | } | |
1256 | } | |
1257 | } | |
1258 | } | |
1259 | ||
1260 | if (reload_completed) | |
1261 | frv_stack_cache = info_ptr; | |
1262 | ||
1263 | return info_ptr; | |
1264 | } | |
1265 | ||
1266 | \f | |
87b483a1 | 1267 | /* Print the information about the frv stack offsets, etc. when debugging. */ |
36a05131 BS |
1268 | |
1269 | void | |
f2206911 | 1270 | frv_debug_stack (frv_stack_t *info) |
36a05131 BS |
1271 | { |
1272 | int range; | |
1273 | ||
1274 | if (!info) | |
1275 | info = frv_stack_info (); | |
1276 | ||
1277 | fprintf (stderr, "\nStack information for function %s:\n", | |
1278 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
1279 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
1280 | : "<unknown>")); | |
1281 | ||
1282 | fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size); | |
1283 | fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size); | |
1284 | fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size); | |
1285 | fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n", | |
1286 | info->regs_size, info->regs_size_1word, info->regs_size_2words); | |
1287 | ||
1288 | fprintf (stderr, "\theader_size\t= %6d\n", info->header_size); | |
1289 | fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size); | |
1290 | fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset); | |
1291 | fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset); | |
1292 | ||
1293 | for (range = 0; range < STACK_REGS_MAX; range++) | |
1294 | { | |
1295 | frv_stack_regs_t *regs = &(info->regs[range]); | |
1296 | if ((regs->size_1word + regs->size_2words) > 0) | |
1297 | { | |
1298 | int first = regs->first; | |
1299 | int last = regs->last; | |
1300 | int regno; | |
1301 | ||
1302 | fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =", | |
1303 | regs->name, regs->size_1word + regs->size_2words, | |
1304 | regs->size_1word, regs->size_2words); | |
1305 | ||
1306 | for (regno = first; regno <= last; regno++) | |
1307 | { | |
1308 | if (info->save_p[regno] == REG_SAVE_1WORD) | |
1309 | fprintf (stderr, " %s (%d)", reg_names[regno], | |
1310 | info->reg_offset[regno]); | |
1311 | ||
1312 | else if (info->save_p[regno] == REG_SAVE_2WORDS) | |
1313 | fprintf (stderr, " %s-%s (%d)", reg_names[regno], | |
1314 | reg_names[regno+1], info->reg_offset[regno]); | |
1315 | } | |
1316 | ||
1317 | fputc ('\n', stderr); | |
1318 | } | |
1319 | } | |
1320 | ||
1321 | fflush (stderr); | |
1322 | } | |
1323 | ||
1324 | ||
1325 | \f | |
1326 | ||
1327 | /* The following variable value is TRUE if the next output insn should | |
1328 | finish cpu cycle. In order words the insn will have packing bit | |
87b483a1 | 1329 | (which means absence of asm code suffix `.p' on assembler. */ |
36a05131 BS |
1330 | |
1331 | static int frv_insn_packing_flag; | |
1332 | ||
1333 | /* True if the current function contains a far jump. */ | |
1334 | ||
1335 | static int | |
f2206911 | 1336 | frv_function_contains_far_jump (void) |
36a05131 BS |
1337 | { |
1338 | rtx insn = get_insns (); | |
1339 | while (insn != NULL | |
1340 | && !(GET_CODE (insn) == JUMP_INSN | |
1341 | /* Ignore tablejump patterns. */ | |
1342 | && GET_CODE (PATTERN (insn)) != ADDR_VEC | |
1343 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC | |
1344 | && get_attr_far_jump (insn) == FAR_JUMP_YES)) | |
1345 | insn = NEXT_INSN (insn); | |
1346 | return (insn != NULL); | |
1347 | } | |
1348 | ||
1349 | /* For the FRV, this function makes sure that a function with far jumps | |
1350 | will return correctly. It also does the VLIW packing. */ | |
1351 | ||
1352 | static void | |
f2206911 | 1353 | frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
36a05131 BS |
1354 | { |
1355 | /* If no frame was created, check whether the function uses a call | |
1356 | instruction to implement a far jump. If so, save the link in gr3 and | |
1357 | replace all returns to LR with returns to GR3. GR3 is used because it | |
1358 | is call-clobbered, because is not available to the register allocator, | |
1359 | and because all functions that take a hidden argument pointer will have | |
1360 | a stack frame. */ | |
1361 | if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ()) | |
1362 | { | |
1363 | rtx insn; | |
1364 | ||
1365 | /* Just to check that the above comment is true. */ | |
1366 | if (regs_ever_live[GPR_FIRST + 3]) | |
1367 | abort (); | |
1368 | ||
1369 | /* Generate the instruction that saves the link register. */ | |
1370 | fprintf (file, "\tmovsg lr,gr3\n"); | |
1371 | ||
1372 | /* Replace the LR with GR3 in *return_internal patterns. The insn | |
1373 | will now return using jmpl @(gr3,0) rather than bralr. We cannot | |
1374 | simply emit a different assembly directive because bralr and jmpl | |
1375 | execute in different units. */ | |
1376 | for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn)) | |
1377 | if (GET_CODE (insn) == JUMP_INSN) | |
1378 | { | |
1379 | rtx pattern = PATTERN (insn); | |
1380 | if (GET_CODE (pattern) == PARALLEL | |
1381 | && XVECLEN (pattern, 0) >= 2 | |
1382 | && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN | |
1383 | && GET_CODE (XVECEXP (pattern, 0, 1)) == USE) | |
1384 | { | |
1385 | rtx address = XEXP (XVECEXP (pattern, 0, 1), 0); | |
1386 | if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO) | |
1387 | REGNO (address) = GPR_FIRST + 3; | |
1388 | } | |
1389 | } | |
1390 | } | |
1391 | ||
1392 | frv_pack_insns (); | |
1393 | frv_insn_packing_flag = TRUE; | |
1394 | } | |
1395 | ||
1396 | \f | |
1397 | /* Return the next available temporary register in a given class. */ | |
1398 | ||
1399 | static rtx | |
f2206911 KC |
1400 | frv_alloc_temp_reg ( |
1401 | frv_tmp_reg_t *info, /* which registers are available */ | |
1402 | enum reg_class class, /* register class desired */ | |
1403 | enum machine_mode mode, /* mode to allocate register with */ | |
1404 | int mark_as_used, /* register not available after allocation */ | |
1405 | int no_abort) /* return NULL instead of aborting */ | |
36a05131 BS |
1406 | { |
1407 | int regno = info->next_reg[ (int)class ]; | |
1408 | int orig_regno = regno; | |
1409 | HARD_REG_SET *reg_in_class = ®_class_contents[ (int)class ]; | |
1410 | int i, nr; | |
1411 | ||
1412 | for (;;) | |
1413 | { | |
1414 | if (TEST_HARD_REG_BIT (*reg_in_class, regno) | |
1415 | && TEST_HARD_REG_BIT (info->regs, regno)) | |
1416 | break; | |
1417 | ||
1418 | if (++regno >= FIRST_PSEUDO_REGISTER) | |
1419 | regno = 0; | |
1420 | if (regno == orig_regno) | |
1421 | { | |
1422 | if (no_abort) | |
1423 | return NULL_RTX; | |
1424 | else | |
1425 | abort (); | |
1426 | } | |
1427 | } | |
1428 | ||
1429 | nr = HARD_REGNO_NREGS (regno, mode); | |
1430 | info->next_reg[ (int)class ] = regno + nr; | |
1431 | ||
1432 | if (mark_as_used) | |
1433 | for (i = 0; i < nr; i++) | |
1434 | CLEAR_HARD_REG_BIT (info->regs, regno+i); | |
1435 | ||
1436 | return gen_rtx_REG (mode, regno); | |
1437 | } | |
1438 | ||
1439 | \f | |
1440 | /* Return an rtx with the value OFFSET, which will either be a register or a | |
1441 | signed 12-bit integer. It can be used as the second operand in an "add" | |
1442 | instruction, or as the index in a load or store. | |
1443 | ||
1444 | The function returns a constant rtx if OFFSET is small enough, otherwise | |
1445 | it loads the constant into register OFFSET_REGNO and returns that. */ | |
1446 | static rtx | |
f2206911 | 1447 | frv_frame_offset_rtx (int offset) |
36a05131 BS |
1448 | { |
1449 | rtx offset_rtx = GEN_INT (offset); | |
1450 | if (IN_RANGE_P (offset, -2048, 2047)) | |
1451 | return offset_rtx; | |
1452 | else | |
1453 | { | |
1454 | rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO); | |
1455 | if (IN_RANGE_P (offset, -32768, 32767)) | |
1456 | emit_insn (gen_movsi (reg_rtx, offset_rtx)); | |
1457 | else | |
1458 | { | |
1459 | emit_insn (gen_movsi_high (reg_rtx, offset_rtx)); | |
1460 | emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx)); | |
1461 | } | |
1462 | return reg_rtx; | |
1463 | } | |
1464 | } | |
1465 | ||
1466 | /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The | |
1467 | prologue and epilogue uses such expressions to access the stack. */ | |
1468 | static rtx | |
f2206911 | 1469 | frv_frame_mem (enum machine_mode mode, rtx base, int offset) |
36a05131 BS |
1470 | { |
1471 | return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, | |
1472 | base, | |
1473 | frv_frame_offset_rtx (offset))); | |
1474 | } | |
1475 | ||
1476 | /* Generate a frame-related expression: | |
1477 | ||
1478 | (set REG (mem (plus (sp) (const_int OFFSET)))). | |
1479 | ||
1480 | Such expressions are used in FRAME_RELATED_EXPR notes for more complex | |
1481 | instructions. Marking the expressions as frame-related is superfluous if | |
1482 | the note contains just a single set. But if the note contains a PARALLEL | |
1483 | or SEQUENCE that has several sets, each set must be individually marked | |
1484 | as frame-related. */ | |
1485 | static rtx | |
f2206911 | 1486 | frv_dwarf_store (rtx reg, int offset) |
36a05131 BS |
1487 | { |
1488 | rtx set = gen_rtx_SET (VOIDmode, | |
1489 | gen_rtx_MEM (GET_MODE (reg), | |
1490 | plus_constant (stack_pointer_rtx, | |
1491 | offset)), | |
1492 | reg); | |
1493 | RTX_FRAME_RELATED_P (set) = 1; | |
1494 | return set; | |
1495 | } | |
1496 | ||
1497 | /* Emit a frame-related instruction whose pattern is PATTERN. The | |
1498 | instruction is the last in a sequence that cumulatively performs the | |
1499 | operation described by DWARF_PATTERN. The instruction is marked as | |
1500 | frame-related and has a REG_FRAME_RELATED_EXPR note containing | |
1501 | DWARF_PATTERN. */ | |
1502 | static void | |
f2206911 | 1503 | frv_frame_insn (rtx pattern, rtx dwarf_pattern) |
36a05131 BS |
1504 | { |
1505 | rtx insn = emit_insn (pattern); | |
1506 | RTX_FRAME_RELATED_P (insn) = 1; | |
1507 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
1508 | dwarf_pattern, | |
1509 | REG_NOTES (insn)); | |
1510 | } | |
1511 | ||
1512 | /* Emit instructions that transfer REG to or from the memory location (sp + | |
1513 | STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is | |
1514 | FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this | |
1515 | function to store registers and only the epilogue uses it to load them. | |
1516 | ||
1517 | The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET). | |
1518 | The generated instruction will use BASE as its base register. BASE may | |
1519 | simply be the stack pointer, but if several accesses are being made to a | |
1520 | region far away from the stack pointer, it may be more efficient to set | |
1521 | up a temporary instead. | |
b16c1435 | 1522 | |
36a05131 BS |
1523 | Store instructions will be frame-related and will be annotated with the |
1524 | overall effect of the store. Load instructions will be followed by a | |
1525 | (use) to prevent later optimizations from zapping them. | |
1526 | ||
1527 | The function takes care of the moves to and from SPRs, using TEMP_REGNO | |
1528 | as a temporary in such cases. */ | |
1529 | static void | |
f2206911 | 1530 | frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset) |
36a05131 BS |
1531 | { |
1532 | enum machine_mode mode = GET_MODE (reg); | |
1533 | rtx mem = frv_frame_mem (mode, | |
1534 | accessor->base, | |
1535 | stack_offset - accessor->base_offset); | |
1536 | ||
1537 | if (accessor->op == FRV_LOAD) | |
1538 | { | |
1539 | if (SPR_P (REGNO (reg))) | |
1540 | { | |
1541 | rtx temp = gen_rtx_REG (mode, TEMP_REGNO); | |
1542 | emit_insn (gen_rtx_SET (VOIDmode, temp, mem)); | |
1543 | emit_insn (gen_rtx_SET (VOIDmode, reg, temp)); | |
1544 | } | |
1545 | else | |
1546 | emit_insn (gen_rtx_SET (VOIDmode, reg, mem)); | |
1547 | emit_insn (gen_rtx_USE (VOIDmode, reg)); | |
1548 | } | |
1549 | else | |
1550 | { | |
1551 | if (SPR_P (REGNO (reg))) | |
1552 | { | |
1553 | rtx temp = gen_rtx_REG (mode, TEMP_REGNO); | |
1554 | emit_insn (gen_rtx_SET (VOIDmode, temp, reg)); | |
1555 | frv_frame_insn (gen_rtx_SET (Pmode, mem, temp), | |
1556 | frv_dwarf_store (reg, stack_offset)); | |
1557 | } | |
1558 | else if (GET_MODE (reg) == DImode) | |
1559 | { | |
1560 | /* For DImode saves, the dwarf2 version needs to be a SEQUENCE | |
1561 | with a separate save for each register. */ | |
1562 | rtx reg1 = gen_rtx_REG (SImode, REGNO (reg)); | |
1563 | rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1); | |
1564 | rtx set1 = frv_dwarf_store (reg1, stack_offset); | |
1565 | rtx set2 = frv_dwarf_store (reg2, stack_offset + 4); | |
1566 | frv_frame_insn (gen_rtx_SET (Pmode, mem, reg), | |
1567 | gen_rtx_PARALLEL (VOIDmode, | |
1568 | gen_rtvec (2, set1, set2))); | |
1569 | } | |
1570 | else | |
1571 | frv_frame_insn (gen_rtx_SET (Pmode, mem, reg), | |
1572 | frv_dwarf_store (reg, stack_offset)); | |
1573 | } | |
1574 | } | |
1575 | ||
1576 | /* A function that uses frv_frame_access to transfer a group of registers to | |
1577 | or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO | |
1578 | is the stack information generated by frv_stack_info, and REG_SET is the | |
1579 | number of the register set to transfer. */ | |
1580 | static void | |
f2206911 KC |
1581 | frv_frame_access_multi (frv_frame_accessor_t *accessor, |
1582 | frv_stack_t *info, | |
1583 | int reg_set) | |
36a05131 BS |
1584 | { |
1585 | frv_stack_regs_t *regs_info; | |
1586 | int regno; | |
1587 | ||
1588 | regs_info = &info->regs[reg_set]; | |
1589 | for (regno = regs_info->first; regno <= regs_info->last; regno++) | |
1590 | if (info->save_p[regno]) | |
1591 | frv_frame_access (accessor, | |
1592 | info->save_p[regno] == REG_SAVE_2WORDS | |
1593 | ? gen_rtx_REG (DImode, regno) | |
1594 | : gen_rtx_REG (SImode, regno), | |
1595 | info->reg_offset[regno]); | |
1596 | } | |
1597 | ||
1598 | /* Save or restore callee-saved registers that are kept outside the frame | |
1599 | header. The function saves the registers if OP is FRV_STORE and restores | |
1600 | them if OP is FRV_LOAD. INFO is the stack information generated by | |
1601 | frv_stack_info. */ | |
1602 | static void | |
f2206911 | 1603 | frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info) |
36a05131 BS |
1604 | { |
1605 | frv_frame_accessor_t accessor; | |
1606 | ||
1607 | accessor.op = op; | |
1608 | accessor.base = stack_pointer_rtx; | |
1609 | accessor.base_offset = 0; | |
1610 | frv_frame_access_multi (&accessor, info, STACK_REGS_GPR); | |
1611 | frv_frame_access_multi (&accessor, info, STACK_REGS_FPR); | |
1612 | frv_frame_access_multi (&accessor, info, STACK_REGS_LCR); | |
b16c1435 | 1613 | } |
36a05131 BS |
1614 | |
1615 | ||
1616 | /* Called after register allocation to add any instructions needed for the | |
1617 | prologue. Using a prologue insn is favored compared to putting all of the | |
b88cf82e KH |
1618 | instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since |
1619 | it allows the scheduler to intermix instructions with the saves of | |
1620 | the caller saved registers. In some cases, it might be necessary | |
1621 | to emit a barrier instruction as the last insn to prevent such | |
1622 | scheduling. | |
36a05131 BS |
1623 | |
1624 | Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1 | |
1625 | so that the debug info generation code can handle them properly. */ | |
1626 | void | |
f2206911 | 1627 | frv_expand_prologue (void) |
36a05131 BS |
1628 | { |
1629 | frv_stack_t *info = frv_stack_info (); | |
1630 | rtx sp = stack_pointer_rtx; | |
1631 | rtx fp = frame_pointer_rtx; | |
1632 | frv_frame_accessor_t accessor; | |
1633 | ||
1634 | if (TARGET_DEBUG_STACK) | |
1635 | frv_debug_stack (info); | |
1636 | ||
1637 | if (info->total_size == 0) | |
1638 | return; | |
1639 | ||
1640 | /* We're interested in three areas of the frame here: | |
1641 | ||
1642 | A: the register save area | |
1643 | B: the old FP | |
1644 | C: the header after B | |
1645 | ||
1646 | If the frame pointer isn't used, we'll have to set up A, B and C | |
1647 | using the stack pointer. If the frame pointer is used, we'll access | |
1648 | them as follows: | |
1649 | ||
1650 | A: set up using sp | |
1651 | B: set up using sp or a temporary (see below) | |
1652 | C: set up using fp | |
1653 | ||
1654 | We set up B using the stack pointer if the frame is small enough. | |
1655 | Otherwise, it's more efficient to copy the old stack pointer into a | |
1656 | temporary and use that. | |
1657 | ||
1658 | Note that it's important to make sure the prologue and epilogue use the | |
1659 | same registers to access A and C, since doing otherwise will confuse | |
1660 | the aliasing code. */ | |
1661 | ||
1662 | /* Set up ACCESSOR for accessing region B above. If the frame pointer | |
1663 | isn't used, the same method will serve for C. */ | |
1664 | accessor.op = FRV_STORE; | |
1665 | if (frame_pointer_needed && info->total_size > 2048) | |
1666 | { | |
1667 | rtx insn; | |
1668 | ||
1669 | accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO); | |
1670 | accessor.base_offset = info->total_size; | |
1671 | insn = emit_insn (gen_movsi (accessor.base, sp)); | |
1672 | } | |
1673 | else | |
1674 | { | |
1675 | accessor.base = stack_pointer_rtx; | |
1676 | accessor.base_offset = 0; | |
1677 | } | |
1678 | ||
1679 | /* Allocate the stack space. */ | |
1680 | { | |
1681 | rtx asm_offset = frv_frame_offset_rtx (-info->total_size); | |
1682 | rtx dwarf_offset = GEN_INT (-info->total_size); | |
1683 | ||
1684 | frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset), | |
1685 | gen_rtx_SET (Pmode, | |
1686 | sp, | |
1687 | gen_rtx_PLUS (Pmode, sp, dwarf_offset))); | |
1688 | } | |
1689 | ||
1690 | /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET) | |
1691 | and point the new one to that location. */ | |
1692 | if (frame_pointer_needed) | |
1693 | { | |
1694 | int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM]; | |
1695 | ||
1696 | /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is | |
1697 | based on ACCESSOR.BASE but DWARF_SRC is always based on the stack | |
1698 | pointer. */ | |
1699 | rtx asm_src = plus_constant (accessor.base, | |
1700 | fp_offset - accessor.base_offset); | |
1701 | rtx dwarf_src = plus_constant (sp, fp_offset); | |
1702 | ||
1703 | /* Store the old frame pointer at (sp + FP_OFFSET). */ | |
1704 | frv_frame_access (&accessor, fp, fp_offset); | |
1705 | ||
1706 | /* Set up the new frame pointer. */ | |
1707 | frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src), | |
1708 | gen_rtx_SET (VOIDmode, fp, dwarf_src)); | |
1709 | ||
1710 | /* Access region C from the frame pointer. */ | |
1711 | accessor.base = fp; | |
1712 | accessor.base_offset = fp_offset; | |
1713 | } | |
1714 | ||
1715 | /* Set up region C. */ | |
1716 | frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT); | |
1717 | frv_frame_access_multi (&accessor, info, STACK_REGS_LR); | |
1718 | frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG); | |
1719 | ||
1720 | /* Set up region A. */ | |
1721 | frv_frame_access_standard_regs (FRV_STORE, info); | |
1722 | ||
1723 | /* If this is a varargs/stdarg function, issue a blockage to prevent the | |
1724 | scheduler from moving loads before the stores saving the registers. */ | |
1725 | if (info->stdarg_size > 0) | |
1726 | emit_insn (gen_blockage ()); | |
1727 | ||
87b483a1 | 1728 | /* Set up pic register/small data register for this function. */ |
34208acf | 1729 | if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table) |
36a05131 BS |
1730 | emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO), |
1731 | gen_rtx_REG (Pmode, LR_REGNO), | |
1732 | gen_rtx_REG (SImode, OFFSET_REGNO))); | |
1733 | } | |
1734 | ||
1735 | \f | |
1736 | /* Under frv, all of the work is done via frv_expand_epilogue, but | |
839a4992 | 1737 | this function provides a convenient place to do cleanup. */ |
36a05131 BS |
1738 | |
1739 | static void | |
f2206911 KC |
1740 | frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED, |
1741 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
36a05131 BS |
1742 | { |
1743 | frv_stack_cache = (frv_stack_t *)0; | |
1744 | ||
87b483a1 | 1745 | /* Zap last used registers for conditional execution. */ |
fad205ff | 1746 | memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg)); |
36a05131 | 1747 | |
87b483a1 | 1748 | /* Release the bitmap of created insns. */ |
36a05131 BS |
1749 | BITMAP_XFREE (frv_ifcvt.scratch_insns_bitmap); |
1750 | } | |
1751 | ||
1752 | \f | |
1753 | /* Called after register allocation to add any instructions needed for the | |
43aa4e05 | 1754 | epilogue. Using an epilogue insn is favored compared to putting all of the |
b88cf82e KH |
1755 | instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since |
1756 | it allows the scheduler to intermix instructions with the saves of | |
1757 | the caller saved registers. In some cases, it might be necessary | |
1758 | to emit a barrier instruction as the last insn to prevent such | |
1759 | scheduling. | |
36a05131 BS |
1760 | |
1761 | If SIBCALL_P is true, the final branch back to the calling function is | |
1762 | omitted, and is used for sibling call (aka tail call) sites. For sibcalls, | |
1763 | we must not clobber any arguments used for parameter passing or any stack | |
1764 | slots for arguments passed to the current function. */ | |
1765 | ||
1766 | void | |
764678d1 | 1767 | frv_expand_epilogue (bool emit_return) |
36a05131 BS |
1768 | { |
1769 | frv_stack_t *info = frv_stack_info (); | |
1770 | rtx fp = frame_pointer_rtx; | |
1771 | rtx sp = stack_pointer_rtx; | |
1772 | rtx return_addr; | |
1773 | int fp_offset; | |
1774 | ||
1775 | fp_offset = info->reg_offset[FRAME_POINTER_REGNUM]; | |
1776 | ||
1777 | /* Restore the stack pointer to its original value if alloca or the like | |
1778 | is used. */ | |
1779 | if (! current_function_sp_is_unchanging) | |
1780 | emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset))); | |
1781 | ||
1782 | /* Restore the callee-saved registers that were used in this function. */ | |
1783 | frv_frame_access_standard_regs (FRV_LOAD, info); | |
1784 | ||
1785 | /* Set RETURN_ADDR to the address we should return to. Set it to NULL if | |
1786 | no return instruction should be emitted. */ | |
764678d1 | 1787 | if (info->save_p[LR_REGNO]) |
36a05131 BS |
1788 | { |
1789 | int lr_offset; | |
1790 | rtx mem; | |
1791 | ||
1792 | /* Use the same method to access the link register's slot as we did in | |
1793 | the prologue. In other words, use the frame pointer if available, | |
1794 | otherwise use the stack pointer. | |
1795 | ||
1796 | LR_OFFSET is the offset of the link register's slot from the start | |
1797 | of the frame and MEM is a memory rtx for it. */ | |
1798 | lr_offset = info->reg_offset[LR_REGNO]; | |
1799 | if (frame_pointer_needed) | |
1800 | mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset); | |
1801 | else | |
1802 | mem = frv_frame_mem (Pmode, sp, lr_offset); | |
1803 | ||
1804 | /* Load the old link register into a GPR. */ | |
1805 | return_addr = gen_rtx_REG (Pmode, TEMP_REGNO); | |
1806 | emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem)); | |
1807 | } | |
1808 | else | |
1809 | return_addr = gen_rtx_REG (Pmode, LR_REGNO); | |
1810 | ||
1811 | /* Restore the old frame pointer. Emit a USE afterwards to make sure | |
1812 | the load is preserved. */ | |
1813 | if (frame_pointer_needed) | |
1814 | { | |
1815 | emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp))); | |
1816 | emit_insn (gen_rtx_USE (VOIDmode, fp)); | |
1817 | } | |
1818 | ||
1819 | /* Deallocate the stack frame. */ | |
1820 | if (info->total_size != 0) | |
1821 | { | |
1822 | rtx offset = frv_frame_offset_rtx (info->total_size); | |
1823 | emit_insn (gen_stack_adjust (sp, sp, offset)); | |
1824 | } | |
1825 | ||
1826 | /* If this function uses eh_return, add the final stack adjustment now. */ | |
1827 | if (current_function_calls_eh_return) | |
1828 | emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX)); | |
1829 | ||
764678d1 | 1830 | if (emit_return) |
36a05131 | 1831 | emit_jump_insn (gen_epilogue_return (return_addr)); |
764678d1 AO |
1832 | else |
1833 | { | |
1834 | rtx lr = return_addr; | |
1835 | ||
1836 | if (REGNO (return_addr) != LR_REGNO) | |
1837 | { | |
1838 | lr = gen_rtx_REG (Pmode, LR_REGNO); | |
1839 | emit_move_insn (lr, return_addr); | |
1840 | } | |
1841 | ||
1842 | emit_insn (gen_rtx_USE (VOIDmode, lr)); | |
1843 | } | |
36a05131 BS |
1844 | } |
1845 | ||
1846 | \f | |
b88cf82e | 1847 | /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */ |
36a05131 | 1848 | |
c590b625 | 1849 | static void |
f2206911 KC |
1850 | frv_asm_output_mi_thunk (FILE *file, |
1851 | tree thunk_fndecl ATTRIBUTE_UNUSED, | |
1852 | HOST_WIDE_INT delta, | |
1853 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
1854 | tree function) | |
36a05131 BS |
1855 | { |
1856 | const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0); | |
1857 | const char *name_arg0 = reg_names[FIRST_ARG_REGNUM]; | |
1858 | const char *name_jmp = reg_names[JUMP_REGNO]; | |
1859 | const char *parallel = ((PACKING_FLAG_USED_P ()) ? ".p" : ""); | |
1860 | ||
87b483a1 | 1861 | /* Do the add using an addi if possible. */ |
36a05131 | 1862 | if (IN_RANGE_P (delta, -2048, 2047)) |
eb0424da | 1863 | fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0); |
36a05131 BS |
1864 | else |
1865 | { | |
4a0a75dd KG |
1866 | const char *const name_add = reg_names[TEMP_REGNO]; |
1867 | fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n", | |
1868 | parallel, delta, name_add); | |
1869 | fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n", | |
1870 | delta, name_add); | |
36a05131 BS |
1871 | fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0); |
1872 | } | |
1873 | ||
34208acf AO |
1874 | if (TARGET_FDPIC) |
1875 | { | |
1876 | const char *name_pic = reg_names[FDPIC_REGNO]; | |
1877 | name_jmp = reg_names[FDPIC_FPTR_REGNO]; | |
1878 | ||
1879 | if (flag_pic != 1) | |
1880 | { | |
1881 | fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel); | |
1882 | assemble_name (file, name_func); | |
1883 | fprintf (file, "),%s\n", name_jmp); | |
1884 | ||
1885 | fprintf (file, "\tsetlo #gotofffuncdesclo("); | |
1886 | assemble_name (file, name_func); | |
1887 | fprintf (file, "),%s\n", name_jmp); | |
1888 | ||
1889 | fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp); | |
1890 | } | |
1891 | else | |
1892 | { | |
1893 | fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic); | |
1894 | assemble_name (file, name_func); | |
1895 | fprintf (file, "\t)), %s\n", name_jmp); | |
1896 | } | |
1897 | } | |
1898 | else if (!flag_pic) | |
36a05131 BS |
1899 | { |
1900 | fprintf (file, "\tsethi%s #hi(", parallel); | |
1901 | assemble_name (file, name_func); | |
1902 | fprintf (file, "),%s\n", name_jmp); | |
1903 | ||
1904 | fprintf (file, "\tsetlo #lo("); | |
1905 | assemble_name (file, name_func); | |
1906 | fprintf (file, "),%s\n", name_jmp); | |
1907 | } | |
1908 | else | |
1909 | { | |
1910 | /* Use JUMP_REGNO as a temporary PIC register. */ | |
1911 | const char *name_lr = reg_names[LR_REGNO]; | |
1912 | const char *name_gppic = name_jmp; | |
1913 | const char *name_tmp = reg_names[TEMP_REGNO]; | |
1914 | ||
1915 | fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp); | |
1916 | fprintf (file, "\tcall 1f\n"); | |
1917 | fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic); | |
1918 | fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr); | |
1919 | fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp); | |
1920 | fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp); | |
1921 | fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic); | |
1922 | ||
1923 | fprintf (file, "\tsethi%s #gprelhi(", parallel); | |
1924 | assemble_name (file, name_func); | |
1925 | fprintf (file, "),%s\n", name_tmp); | |
1926 | ||
1927 | fprintf (file, "\tsetlo #gprello("); | |
1928 | assemble_name (file, name_func); | |
1929 | fprintf (file, "),%s\n", name_tmp); | |
1930 | ||
1931 | fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp); | |
1932 | } | |
1933 | ||
87b483a1 | 1934 | /* Jump to the function address. */ |
36a05131 BS |
1935 | fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]); |
1936 | } | |
1937 | ||
1938 | \f | |
1939 | /* A C expression which is nonzero if a function must have and use a frame | |
1940 | pointer. This expression is evaluated in the reload pass. If its value is | |
1941 | nonzero the function will have a frame pointer. | |
1942 | ||
1943 | The expression can in principle examine the current function and decide | |
1944 | according to the facts, but on most machines the constant 0 or the constant | |
1945 | 1 suffices. Use 0 when the machine allows code to be generated with no | |
1946 | frame pointer, and doing so saves some time or space. Use 1 when there is | |
1947 | no possible advantage to avoiding a frame pointer. | |
1948 | ||
1949 | In certain cases, the compiler does not know how to produce valid code | |
1950 | without a frame pointer. The compiler recognizes those cases and | |
1951 | automatically gives the function a frame pointer regardless of what | |
1952 | `FRAME_POINTER_REQUIRED' says. You don't need to worry about them. | |
1953 | ||
1954 | In a function that does not require a frame pointer, the frame pointer | |
1955 | register can be allocated for ordinary usage, unless you mark it as a fixed | |
1956 | register. See `FIXED_REGISTERS' for more information. */ | |
1957 | ||
87b483a1 | 1958 | /* On frv, create a frame whenever we need to create stack. */ |
36a05131 BS |
1959 | |
1960 | int | |
f2206911 | 1961 | frv_frame_pointer_required (void) |
36a05131 | 1962 | { |
34208acf AO |
1963 | /* If we forgoing the usual linkage requirements, we only need |
1964 | a frame pointer if the stack pointer might change. */ | |
1965 | if (!TARGET_LINKED_FP) | |
1966 | return !current_function_sp_is_unchanging; | |
1967 | ||
36a05131 BS |
1968 | if (! current_function_is_leaf) |
1969 | return TRUE; | |
1970 | ||
1971 | if (get_frame_size () != 0) | |
1972 | return TRUE; | |
1973 | ||
1974 | if (cfun->stdarg) | |
1975 | return TRUE; | |
1976 | ||
1977 | if (!current_function_sp_is_unchanging) | |
1978 | return TRUE; | |
1979 | ||
34208acf | 1980 | if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table) |
36a05131 BS |
1981 | return TRUE; |
1982 | ||
1983 | if (profile_flag) | |
1984 | return TRUE; | |
1985 | ||
1986 | if (cfun->machine->frame_needed) | |
1987 | return TRUE; | |
1988 | ||
1989 | return FALSE; | |
1990 | } | |
1991 | ||
1992 | \f | |
1993 | /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the | |
1994 | initial difference between the specified pair of registers. This macro must | |
1995 | be defined if `ELIMINABLE_REGS' is defined. */ | |
1996 | ||
1997 | /* See frv_stack_info for more details on the frv stack frame. */ | |
1998 | ||
1999 | int | |
f2206911 | 2000 | frv_initial_elimination_offset (int from, int to) |
36a05131 BS |
2001 | { |
2002 | frv_stack_t *info = frv_stack_info (); | |
2003 | int ret = 0; | |
2004 | ||
2005 | if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM) | |
2006 | ret = info->total_size - info->pretend_size; | |
2007 | ||
2008 | else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM) | |
88d6a75f | 2009 | ret = info->reg_offset[FRAME_POINTER_REGNUM]; |
36a05131 BS |
2010 | |
2011 | else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM) | |
2012 | ret = (info->total_size | |
2013 | - info->reg_offset[FRAME_POINTER_REGNUM] | |
2014 | - info->pretend_size); | |
2015 | ||
2016 | else | |
2017 | abort (); | |
2018 | ||
2019 | if (TARGET_DEBUG_STACK) | |
2020 | fprintf (stderr, "Eliminate %s to %s by adding %d\n", | |
2021 | reg_names [from], reg_names[to], ret); | |
2022 | ||
2023 | return ret; | |
2024 | } | |
2025 | ||
2026 | \f | |
d8c2bed3 | 2027 | /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */ |
36a05131 | 2028 | |
d8c2bed3 | 2029 | static void |
f2206911 KC |
2030 | frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum, |
2031 | enum machine_mode mode, | |
2032 | tree type ATTRIBUTE_UNUSED, | |
2033 | int *pretend_size, | |
2034 | int second_time) | |
36a05131 BS |
2035 | { |
2036 | if (TARGET_DEBUG_ARG) | |
2037 | fprintf (stderr, | |
2038 | "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n", | |
2039 | *cum, GET_MODE_NAME (mode), *pretend_size, second_time); | |
2040 | } | |
2041 | ||
2042 | \f | |
b88cf82e | 2043 | /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */ |
36a05131 | 2044 | |
8ac411c7 | 2045 | static rtx |
f2206911 | 2046 | frv_expand_builtin_saveregs (void) |
36a05131 BS |
2047 | { |
2048 | int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS; | |
2049 | ||
2050 | if (TARGET_DEBUG_ARG) | |
2051 | fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n", | |
2052 | offset); | |
2053 | ||
f1c25d3b | 2054 | return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset)); |
36a05131 BS |
2055 | } |
2056 | ||
2057 | \f | |
2058 | /* Expand __builtin_va_start to do the va_start macro. */ | |
2059 | ||
2060 | void | |
f2206911 | 2061 | frv_expand_builtin_va_start (tree valist, rtx nextarg) |
36a05131 BS |
2062 | { |
2063 | tree t; | |
2064 | int num = cfun->args_info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS; | |
2065 | ||
2066 | nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, | |
2067 | GEN_INT (UNITS_PER_WORD * num)); | |
2068 | ||
2069 | if (TARGET_DEBUG_ARG) | |
2070 | { | |
2071 | fprintf (stderr, "va_start: args_info = %d, num = %d\n", | |
2072 | cfun->args_info, num); | |
2073 | ||
2074 | debug_rtx (nextarg); | |
2075 | } | |
2076 | ||
2077 | t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, | |
2078 | make_tree (ptr_type_node, nextarg)); | |
2079 | TREE_SIDE_EFFECTS (t) = 1; | |
2080 | ||
2081 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2082 | } | |
2083 | ||
36a05131 BS |
2084 | \f |
2085 | /* Expand a block move operation, and return 1 if successful. Return 0 | |
2086 | if we should let the compiler generate normal code. | |
2087 | ||
2088 | operands[0] is the destination | |
2089 | operands[1] is the source | |
2090 | operands[2] is the length | |
2091 | operands[3] is the alignment */ | |
2092 | ||
2093 | /* Maximum number of loads to do before doing the stores */ | |
2094 | #ifndef MAX_MOVE_REG | |
2095 | #define MAX_MOVE_REG 4 | |
2096 | #endif | |
2097 | ||
2098 | /* Maximum number of total loads to do. */ | |
2099 | #ifndef TOTAL_MOVE_REG | |
2100 | #define TOTAL_MOVE_REG 8 | |
2101 | #endif | |
2102 | ||
2103 | int | |
f2206911 | 2104 | frv_expand_block_move (rtx operands[]) |
36a05131 BS |
2105 | { |
2106 | rtx orig_dest = operands[0]; | |
2107 | rtx orig_src = operands[1]; | |
2108 | rtx bytes_rtx = operands[2]; | |
2109 | rtx align_rtx = operands[3]; | |
2110 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); | |
2111 | int align; | |
2112 | int bytes; | |
2113 | int offset; | |
2114 | int num_reg; | |
2115 | int i; | |
2116 | rtx src_reg; | |
2117 | rtx dest_reg; | |
2118 | rtx src_addr; | |
2119 | rtx dest_addr; | |
2120 | rtx src_mem; | |
2121 | rtx dest_mem; | |
2122 | rtx tmp_reg; | |
2123 | rtx stores[MAX_MOVE_REG]; | |
2124 | int move_bytes; | |
2125 | enum machine_mode mode; | |
2126 | ||
87b483a1 | 2127 | /* If this is not a fixed size move, just call memcpy. */ |
36a05131 BS |
2128 | if (! constp) |
2129 | return FALSE; | |
2130 | ||
87b483a1 | 2131 | /* If this is not a fixed size alignment, abort. */ |
36a05131 BS |
2132 | if (GET_CODE (align_rtx) != CONST_INT) |
2133 | abort (); | |
2134 | ||
2135 | align = INTVAL (align_rtx); | |
2136 | ||
2137 | /* Anything to move? */ | |
2138 | bytes = INTVAL (bytes_rtx); | |
2139 | if (bytes <= 0) | |
2140 | return TRUE; | |
2141 | ||
2142 | /* Don't support real large moves. */ | |
2143 | if (bytes > TOTAL_MOVE_REG*align) | |
2144 | return FALSE; | |
2145 | ||
2146 | /* Move the address into scratch registers. */ | |
2147 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); | |
2148 | src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); | |
2149 | ||
2150 | num_reg = offset = 0; | |
2151 | for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) | |
2152 | { | |
87b483a1 | 2153 | /* Calculate the correct offset for src/dest. */ |
36a05131 BS |
2154 | if (offset == 0) |
2155 | { | |
2156 | src_addr = src_reg; | |
2157 | dest_addr = dest_reg; | |
2158 | } | |
2159 | else | |
2160 | { | |
2161 | src_addr = plus_constant (src_reg, offset); | |
2162 | dest_addr = plus_constant (dest_reg, offset); | |
2163 | } | |
2164 | ||
2165 | /* Generate the appropriate load and store, saving the stores | |
2166 | for later. */ | |
2167 | if (bytes >= 4 && align >= 4) | |
2168 | mode = SImode; | |
2169 | else if (bytes >= 2 && align >= 2) | |
2170 | mode = HImode; | |
2171 | else | |
2172 | mode = QImode; | |
2173 | ||
2174 | move_bytes = GET_MODE_SIZE (mode); | |
2175 | tmp_reg = gen_reg_rtx (mode); | |
2176 | src_mem = change_address (orig_src, mode, src_addr); | |
2177 | dest_mem = change_address (orig_dest, mode, dest_addr); | |
2178 | emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem)); | |
2179 | stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg); | |
2180 | ||
2181 | if (num_reg >= MAX_MOVE_REG) | |
2182 | { | |
2183 | for (i = 0; i < num_reg; i++) | |
2184 | emit_insn (stores[i]); | |
2185 | num_reg = 0; | |
2186 | } | |
2187 | } | |
2188 | ||
2189 | for (i = 0; i < num_reg; i++) | |
2190 | emit_insn (stores[i]); | |
2191 | ||
2192 | return TRUE; | |
2193 | } | |
2194 | ||
2195 | \f | |
2196 | /* Expand a block clear operation, and return 1 if successful. Return 0 | |
2197 | if we should let the compiler generate normal code. | |
2198 | ||
2199 | operands[0] is the destination | |
2200 | operands[1] is the length | |
2201 | operands[2] is the alignment */ | |
2202 | ||
2203 | int | |
f2206911 | 2204 | frv_expand_block_clear (rtx operands[]) |
36a05131 BS |
2205 | { |
2206 | rtx orig_dest = operands[0]; | |
2207 | rtx bytes_rtx = operands[1]; | |
2208 | rtx align_rtx = operands[2]; | |
2209 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); | |
2210 | int align; | |
2211 | int bytes; | |
2212 | int offset; | |
2213 | int num_reg; | |
2214 | rtx dest_reg; | |
2215 | rtx dest_addr; | |
2216 | rtx dest_mem; | |
2217 | int clear_bytes; | |
2218 | enum machine_mode mode; | |
2219 | ||
87b483a1 | 2220 | /* If this is not a fixed size move, just call memcpy. */ |
36a05131 BS |
2221 | if (! constp) |
2222 | return FALSE; | |
2223 | ||
87b483a1 | 2224 | /* If this is not a fixed size alignment, abort. */ |
36a05131 BS |
2225 | if (GET_CODE (align_rtx) != CONST_INT) |
2226 | abort (); | |
2227 | ||
2228 | align = INTVAL (align_rtx); | |
2229 | ||
2230 | /* Anything to move? */ | |
2231 | bytes = INTVAL (bytes_rtx); | |
2232 | if (bytes <= 0) | |
2233 | return TRUE; | |
2234 | ||
2235 | /* Don't support real large clears. */ | |
2236 | if (bytes > TOTAL_MOVE_REG*align) | |
2237 | return FALSE; | |
2238 | ||
2239 | /* Move the address into a scratch register. */ | |
2240 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); | |
2241 | ||
2242 | num_reg = offset = 0; | |
2243 | for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes)) | |
2244 | { | |
87b483a1 | 2245 | /* Calculate the correct offset for src/dest. */ |
36a05131 BS |
2246 | dest_addr = ((offset == 0) |
2247 | ? dest_reg | |
2248 | : plus_constant (dest_reg, offset)); | |
2249 | ||
87b483a1 | 2250 | /* Generate the appropriate store of gr0. */ |
36a05131 BS |
2251 | if (bytes >= 4 && align >= 4) |
2252 | mode = SImode; | |
2253 | else if (bytes >= 2 && align >= 2) | |
2254 | mode = HImode; | |
2255 | else | |
2256 | mode = QImode; | |
2257 | ||
2258 | clear_bytes = GET_MODE_SIZE (mode); | |
2259 | dest_mem = change_address (orig_dest, mode, dest_addr); | |
2260 | emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx)); | |
2261 | } | |
2262 | ||
2263 | return TRUE; | |
2264 | } | |
2265 | ||
2266 | \f | |
2267 | /* The following variable is used to output modifiers of assembler | |
87b483a1 | 2268 | code of the current output insn. */ |
36a05131 BS |
2269 | |
2270 | static rtx *frv_insn_operands; | |
2271 | ||
2272 | /* The following function is used to add assembler insn code suffix .p | |
87b483a1 | 2273 | if it is necessary. */ |
36a05131 BS |
2274 | |
2275 | const char * | |
f2206911 | 2276 | frv_asm_output_opcode (FILE *f, const char *ptr) |
36a05131 BS |
2277 | { |
2278 | int c; | |
2279 | ||
2280 | if (! PACKING_FLAG_USED_P()) | |
2281 | return ptr; | |
2282 | ||
2283 | for (; *ptr && *ptr != ' ' && *ptr != '\t';) | |
2284 | { | |
2285 | c = *ptr++; | |
2286 | if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z') | |
2287 | || (*ptr >= 'A' && *ptr <= 'Z'))) | |
2288 | { | |
2289 | int letter = *ptr++; | |
2290 | ||
2291 | c = atoi (ptr); | |
2292 | frv_print_operand (f, frv_insn_operands [c], letter); | |
2293 | while ((c = *ptr) >= '0' && c <= '9') | |
2294 | ptr++; | |
2295 | } | |
2296 | else | |
2297 | fputc (c, f); | |
2298 | } | |
2299 | ||
2300 | if (!frv_insn_packing_flag) | |
2301 | fprintf (f, ".p"); | |
2302 | ||
2303 | return ptr; | |
2304 | } | |
2305 | ||
2306 | /* The following function sets up the packing bit for the current | |
2307 | output insn. Remember that the function is not called for asm | |
87b483a1 | 2308 | insns. */ |
36a05131 BS |
2309 | |
2310 | void | |
f2206911 | 2311 | frv_final_prescan_insn (rtx insn, rtx *opvec, int noperands ATTRIBUTE_UNUSED) |
36a05131 BS |
2312 | { |
2313 | if (! PACKING_FLAG_USED_P()) | |
2314 | return; | |
2315 | ||
735e8085 | 2316 | if (!INSN_P (insn)) |
36a05131 BS |
2317 | return; |
2318 | ||
2319 | frv_insn_operands = opvec; | |
2320 | ||
2321 | /* Look for the next printable instruction. frv_pack_insns () has set | |
2322 | things up so that any printable instruction will have TImode if it | |
2323 | starts a new packet and VOIDmode if it should be packed with the | |
2324 | previous instruction. | |
2325 | ||
2326 | Printable instructions will be asm_operands or match one of the .md | |
2327 | patterns. Since asm instructions cannot be packed -- and will | |
0b4be7de KH |
2328 | therefore have TImode -- this loop terminates on any recognizable |
2329 | instruction, and on any unrecognizable instruction with TImode. */ | |
36a05131 BS |
2330 | for (insn = NEXT_INSN (insn); insn; insn = NEXT_INSN (insn)) |
2331 | { | |
2332 | if (NOTE_P (insn)) | |
2333 | continue; | |
2334 | else if (!INSN_P (insn)) | |
2335 | break; | |
2336 | else if (GET_MODE (insn) == TImode || INSN_CODE (insn) != -1) | |
2337 | break; | |
2338 | } | |
2339 | ||
2340 | /* Set frv_insn_packing_flag to FALSE if the next instruction should | |
2341 | be packed with this one. Set it to TRUE otherwise. If the next | |
839a4992 | 2342 | instruction is an asm instruction, this statement will set the |
36a05131 BS |
2343 | flag to TRUE, and that value will still hold when the asm operands |
2344 | themselves are printed. */ | |
2345 | frv_insn_packing_flag = ! (insn && INSN_P (insn) | |
2346 | && GET_MODE (insn) != TImode); | |
2347 | } | |
2348 | ||
2349 | ||
2350 | \f | |
2351 | /* A C expression whose value is RTL representing the address in a stack frame | |
2352 | where the pointer to the caller's frame is stored. Assume that FRAMEADDR is | |
2353 | an RTL expression for the address of the stack frame itself. | |
2354 | ||
2355 | If you don't define this macro, the default is to return the value of | |
2356 | FRAMEADDR--that is, the stack frame address is also the address of the stack | |
2357 | word that points to the previous frame. */ | |
2358 | ||
2359 | /* The default is correct, but we need to make sure the frame gets created. */ | |
2360 | rtx | |
f2206911 | 2361 | frv_dynamic_chain_address (rtx frame) |
36a05131 BS |
2362 | { |
2363 | cfun->machine->frame_needed = 1; | |
2364 | return frame; | |
2365 | } | |
2366 | ||
2367 | ||
2368 | /* A C expression whose value is RTL representing the value of the return | |
2369 | address for the frame COUNT steps up from the current frame, after the | |
2370 | prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame | |
2371 | pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is | |
2372 | defined. | |
2373 | ||
2374 | The value of the expression must always be the correct address when COUNT is | |
2375 | zero, but may be `NULL_RTX' if there is not way to determine the return | |
2376 | address of other frames. */ | |
2377 | ||
2378 | rtx | |
34208acf | 2379 | frv_return_addr_rtx (int count, rtx frame) |
36a05131 | 2380 | { |
34208acf AO |
2381 | if (count != 0) |
2382 | return const0_rtx; | |
36a05131 BS |
2383 | cfun->machine->frame_needed = 1; |
2384 | return gen_rtx_MEM (Pmode, plus_constant (frame, 8)); | |
2385 | } | |
2386 | ||
2387 | /* Given a memory reference MEMREF, interpret the referenced memory as | |
2388 | an array of MODE values, and return a reference to the element | |
2389 | specified by INDEX. Assume that any pre-modification implicit in | |
2390 | MEMREF has already happened. | |
2391 | ||
2392 | MEMREF must be a legitimate operand for modes larger than SImode. | |
2393 | GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which | |
2394 | this function cannot handle. */ | |
2395 | rtx | |
f2206911 | 2396 | frv_index_memory (rtx memref, enum machine_mode mode, int index) |
36a05131 BS |
2397 | { |
2398 | rtx base = XEXP (memref, 0); | |
2399 | if (GET_CODE (base) == PRE_MODIFY) | |
2400 | base = XEXP (base, 0); | |
2401 | return change_address (memref, mode, | |
2402 | plus_constant (base, index * GET_MODE_SIZE (mode))); | |
2403 | } | |
2404 | ||
2405 | \f | |
2406 | /* Print a memory address as an operand to reference that memory location. */ | |
2407 | void | |
f2206911 | 2408 | frv_print_operand_address (FILE * stream, rtx x) |
36a05131 BS |
2409 | { |
2410 | if (GET_CODE (x) == MEM) | |
2411 | x = XEXP (x, 0); | |
2412 | ||
2413 | switch (GET_CODE (x)) | |
2414 | { | |
2415 | case REG: | |
2416 | fputs (reg_names [ REGNO (x)], stream); | |
2417 | return; | |
2418 | ||
2419 | case CONST_INT: | |
2420 | fprintf (stream, "%ld", (long) INTVAL (x)); | |
2421 | return; | |
2422 | ||
2423 | case SYMBOL_REF: | |
2424 | assemble_name (stream, XSTR (x, 0)); | |
2425 | return; | |
2426 | ||
2427 | case LABEL_REF: | |
2428 | case CONST: | |
2429 | output_addr_const (stream, x); | |
2430 | return; | |
2431 | ||
2432 | default: | |
2433 | break; | |
2434 | } | |
2435 | ||
2436 | fatal_insn ("Bad insn to frv_print_operand_address:", x); | |
2437 | } | |
2438 | ||
2439 | \f | |
2440 | static void | |
f2206911 | 2441 | frv_print_operand_memory_reference_reg (FILE * stream, rtx x) |
36a05131 BS |
2442 | { |
2443 | int regno = true_regnum (x); | |
2444 | if (GPR_P (regno)) | |
2445 | fputs (reg_names[regno], stream); | |
2446 | else | |
2447 | fatal_insn ("Bad register to frv_print_operand_memory_reference_reg:", x); | |
2448 | } | |
2449 | ||
2450 | /* Print a memory reference suitable for the ld/st instructions. */ | |
2451 | ||
2452 | static void | |
f2206911 | 2453 | frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset) |
36a05131 | 2454 | { |
34208acf | 2455 | struct frv_unspec unspec; |
36a05131 BS |
2456 | rtx x0 = NULL_RTX; |
2457 | rtx x1 = NULL_RTX; | |
2458 | ||
2459 | switch (GET_CODE (x)) | |
2460 | { | |
2461 | case SUBREG: | |
2462 | case REG: | |
2463 | x0 = x; | |
2464 | break; | |
2465 | ||
2466 | case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */ | |
2467 | x0 = XEXP (x, 0); | |
2468 | x1 = XEXP (XEXP (x, 1), 1); | |
2469 | break; | |
2470 | ||
2471 | case CONST_INT: | |
2472 | x1 = x; | |
2473 | break; | |
2474 | ||
2475 | case PLUS: | |
2476 | x0 = XEXP (x, 0); | |
2477 | x1 = XEXP (x, 1); | |
2478 | if (GET_CODE (x0) == CONST_INT) | |
2479 | { | |
2480 | x0 = XEXP (x, 1); | |
2481 | x1 = XEXP (x, 0); | |
2482 | } | |
2483 | break; | |
2484 | ||
2485 | default: | |
2486 | fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x); | |
2487 | break; | |
2488 | ||
2489 | } | |
2490 | ||
2491 | if (addr_offset) | |
2492 | { | |
2493 | if (!x1) | |
2494 | x1 = const0_rtx; | |
2495 | else if (GET_CODE (x1) != CONST_INT) | |
2496 | fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x); | |
2497 | } | |
2498 | ||
2499 | fputs ("@(", stream); | |
2500 | if (!x0) | |
2501 | fputs (reg_names[GPR_R0], stream); | |
2502 | else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG) | |
2503 | frv_print_operand_memory_reference_reg (stream, x0); | |
2504 | else | |
2505 | fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x); | |
2506 | ||
2507 | fputs (",", stream); | |
2508 | if (!x1) | |
2509 | fputs (reg_names [GPR_R0], stream); | |
2510 | ||
2511 | else | |
2512 | { | |
2513 | switch (GET_CODE (x1)) | |
2514 | { | |
2515 | case SUBREG: | |
2516 | case REG: | |
2517 | frv_print_operand_memory_reference_reg (stream, x1); | |
2518 | break; | |
2519 | ||
2520 | case CONST_INT: | |
2521 | fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset)); | |
2522 | break; | |
2523 | ||
36a05131 | 2524 | case CONST: |
34208acf AO |
2525 | if (!frv_const_unspec_p (x1, &unspec)) |
2526 | fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x1); | |
2527 | frv_output_const_unspec (stream, &unspec); | |
36a05131 BS |
2528 | break; |
2529 | ||
2530 | default: | |
2531 | fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x); | |
2532 | } | |
2533 | } | |
2534 | ||
2535 | fputs (")", stream); | |
2536 | } | |
2537 | ||
2538 | \f | |
2539 | /* Return 2 for likely branches and 0 for non-likely branches */ | |
2540 | ||
2541 | #define FRV_JUMP_LIKELY 2 | |
2542 | #define FRV_JUMP_NOT_LIKELY 0 | |
2543 | ||
2544 | static int | |
f2206911 | 2545 | frv_print_operand_jump_hint (rtx insn) |
36a05131 BS |
2546 | { |
2547 | rtx note; | |
2548 | rtx labelref; | |
2549 | int ret; | |
2550 | HOST_WIDE_INT prob = -1; | |
2551 | enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN; | |
2552 | ||
2553 | if (GET_CODE (insn) != JUMP_INSN) | |
2554 | abort (); | |
2555 | ||
2556 | /* Assume any non-conditional jump is likely. */ | |
2557 | if (! any_condjump_p (insn)) | |
2558 | ret = FRV_JUMP_LIKELY; | |
2559 | ||
2560 | else | |
2561 | { | |
2562 | labelref = condjump_label (insn); | |
2563 | if (labelref) | |
2564 | { | |
2565 | rtx label = XEXP (labelref, 0); | |
2566 | jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label)) | |
2567 | ? BACKWARD | |
2568 | : FORWARD); | |
2569 | } | |
2570 | ||
2571 | note = find_reg_note (insn, REG_BR_PROB, 0); | |
2572 | if (!note) | |
2573 | ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY); | |
2574 | ||
2575 | else | |
2576 | { | |
2577 | prob = INTVAL (XEXP (note, 0)); | |
2578 | ret = ((prob >= (REG_BR_PROB_BASE / 2)) | |
2579 | ? FRV_JUMP_LIKELY | |
2580 | : FRV_JUMP_NOT_LIKELY); | |
2581 | } | |
2582 | } | |
2583 | ||
2584 | #if 0 | |
2585 | if (TARGET_DEBUG) | |
2586 | { | |
2587 | char *direction; | |
2588 | ||
2589 | switch (jump_type) | |
2590 | { | |
2591 | default: | |
2592 | case UNKNOWN: direction = "unknown jump direction"; break; | |
2593 | case BACKWARD: direction = "jump backward"; break; | |
2594 | case FORWARD: direction = "jump forward"; break; | |
2595 | } | |
2596 | ||
2597 | fprintf (stderr, | |
2598 | "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n", | |
2599 | IDENTIFIER_POINTER (DECL_NAME (current_function_decl)), | |
2600 | (long)INSN_UID (insn), direction, (long)prob, | |
2601 | (long)REG_BR_PROB_BASE, ret); | |
2602 | } | |
2603 | #endif | |
2604 | ||
2605 | return ret; | |
2606 | } | |
2607 | ||
2608 | \f | |
43aa4e05 | 2609 | /* Print an operand to an assembler instruction. |
36a05131 BS |
2610 | |
2611 | `%' followed by a letter and a digit says to output an operand in an | |
2612 | alternate fashion. Four letters have standard, built-in meanings described | |
2613 | below. The machine description macro `PRINT_OPERAND' can define additional | |
2614 | letters with nonstandard meanings. | |
2615 | ||
2616 | `%cDIGIT' can be used to substitute an operand that is a constant value | |
2617 | without the syntax that normally indicates an immediate operand. | |
2618 | ||
2619 | `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated | |
2620 | before printing. | |
2621 | ||
2622 | `%aDIGIT' can be used to substitute an operand as if it were a memory | |
2623 | reference, with the actual operand treated as the address. This may be | |
2624 | useful when outputting a "load address" instruction, because often the | |
2625 | assembler syntax for such an instruction requires you to write the operand | |
2626 | as if it were a memory reference. | |
2627 | ||
2628 | `%lDIGIT' is used to substitute a `label_ref' into a jump instruction. | |
2629 | ||
2630 | `%=' outputs a number which is unique to each instruction in the entire | |
2631 | compilation. This is useful for making local labels to be referred to more | |
2632 | than once in a single template that generates multiple assembler | |
2633 | instructions. | |
2634 | ||
2635 | `%' followed by a punctuation character specifies a substitution that does | |
2636 | not use an operand. Only one case is standard: `%%' outputs a `%' into the | |
2637 | assembler code. Other nonstandard cases can be defined in the | |
2638 | `PRINT_OPERAND' macro. You must also define which punctuation characters | |
2639 | are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */ | |
2640 | ||
2641 | void | |
f2206911 | 2642 | frv_print_operand (FILE * file, rtx x, int code) |
36a05131 | 2643 | { |
34208acf | 2644 | struct frv_unspec unspec; |
36a05131 BS |
2645 | HOST_WIDE_INT value; |
2646 | int offset; | |
2647 | ||
2648 | if (code != 0 && !isalpha (code)) | |
2649 | value = 0; | |
2650 | ||
2651 | else if (GET_CODE (x) == CONST_INT) | |
2652 | value = INTVAL (x); | |
2653 | ||
2654 | else if (GET_CODE (x) == CONST_DOUBLE) | |
2655 | { | |
2656 | if (GET_MODE (x) == SFmode) | |
2657 | { | |
2658 | REAL_VALUE_TYPE rv; | |
2659 | long l; | |
2660 | ||
2661 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
2662 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
2663 | value = l; | |
2664 | } | |
2665 | ||
2666 | else if (GET_MODE (x) == VOIDmode) | |
2667 | value = CONST_DOUBLE_LOW (x); | |
2668 | ||
2669 | else | |
2670 | fatal_insn ("Bad insn in frv_print_operand, bad const_double", x); | |
2671 | } | |
2672 | ||
2673 | else | |
2674 | value = 0; | |
2675 | ||
2676 | switch (code) | |
2677 | { | |
2678 | ||
2679 | case '.': | |
87b483a1 | 2680 | /* Output r0. */ |
36a05131 BS |
2681 | fputs (reg_names[GPR_R0], file); |
2682 | break; | |
2683 | ||
2684 | case '#': | |
2685 | fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn)); | |
2686 | break; | |
2687 | ||
0f6e5d45 | 2688 | case '@': |
87b483a1 | 2689 | /* Output small data area base register (gr16). */ |
36a05131 BS |
2690 | fputs (reg_names[SDA_BASE_REG], file); |
2691 | break; | |
2692 | ||
2693 | case '~': | |
87b483a1 | 2694 | /* Output pic register (gr17). */ |
36a05131 BS |
2695 | fputs (reg_names[PIC_REGNO], file); |
2696 | break; | |
2697 | ||
2698 | case '*': | |
87b483a1 | 2699 | /* Output the temporary integer CCR register. */ |
36a05131 BS |
2700 | fputs (reg_names[ICR_TEMP], file); |
2701 | break; | |
2702 | ||
2703 | case '&': | |
87b483a1 | 2704 | /* Output the temporary integer CC register. */ |
36a05131 BS |
2705 | fputs (reg_names[ICC_TEMP], file); |
2706 | break; | |
2707 | ||
87b483a1 | 2708 | /* case 'a': print an address. */ |
36a05131 BS |
2709 | |
2710 | case 'C': | |
87b483a1 | 2711 | /* Print appropriate test for integer branch false operation. */ |
36a05131 BS |
2712 | switch (GET_CODE (x)) |
2713 | { | |
2714 | default: | |
2715 | fatal_insn ("Bad insn to frv_print_operand, 'C' modifier:", x); | |
2716 | ||
2717 | case EQ: fputs ("ne", file); break; | |
2718 | case NE: fputs ("eq", file); break; | |
2719 | case LT: fputs ("ge", file); break; | |
2720 | case LE: fputs ("gt", file); break; | |
2721 | case GT: fputs ("le", file); break; | |
2722 | case GE: fputs ("lt", file); break; | |
2723 | case LTU: fputs ("nc", file); break; | |
2724 | case LEU: fputs ("hi", file); break; | |
2725 | case GTU: fputs ("ls", file); break; | |
2726 | case GEU: fputs ("c", file); break; | |
2727 | } | |
2728 | break; | |
2729 | ||
2730 | /* case 'c': print a constant without the constant prefix. If | |
2731 | CONSTANT_ADDRESS_P(x) is not true, PRINT_OPERAND is called. */ | |
2732 | ||
2733 | case 'c': | |
87b483a1 | 2734 | /* Print appropriate test for integer branch true operation. */ |
36a05131 BS |
2735 | switch (GET_CODE (x)) |
2736 | { | |
2737 | default: | |
2738 | fatal_insn ("Bad insn to frv_print_operand, 'c' modifier:", x); | |
2739 | ||
2740 | case EQ: fputs ("eq", file); break; | |
2741 | case NE: fputs ("ne", file); break; | |
2742 | case LT: fputs ("lt", file); break; | |
2743 | case LE: fputs ("le", file); break; | |
2744 | case GT: fputs ("gt", file); break; | |
2745 | case GE: fputs ("ge", file); break; | |
2746 | case LTU: fputs ("c", file); break; | |
2747 | case LEU: fputs ("ls", file); break; | |
2748 | case GTU: fputs ("hi", file); break; | |
2749 | case GEU: fputs ("nc", file); break; | |
2750 | } | |
2751 | break; | |
2752 | ||
2753 | case 'e': | |
2754 | /* Print 1 for a NE and 0 for an EQ to give the final argument | |
2755 | for a conditional instruction. */ | |
2756 | if (GET_CODE (x) == NE) | |
2757 | fputs ("1", file); | |
2758 | ||
2759 | else if (GET_CODE (x) == EQ) | |
2760 | fputs ("0", file); | |
2761 | ||
2762 | else | |
2763 | fatal_insn ("Bad insn to frv_print_operand, 'e' modifier:", x); | |
2764 | break; | |
2765 | ||
2766 | case 'F': | |
87b483a1 | 2767 | /* Print appropriate test for floating point branch false operation. */ |
36a05131 BS |
2768 | switch (GET_CODE (x)) |
2769 | { | |
2770 | default: | |
2771 | fatal_insn ("Bad insn to frv_print_operand, 'F' modifier:", x); | |
2772 | ||
2773 | case EQ: fputs ("ne", file); break; | |
2774 | case NE: fputs ("eq", file); break; | |
2775 | case LT: fputs ("uge", file); break; | |
2776 | case LE: fputs ("ug", file); break; | |
2777 | case GT: fputs ("ule", file); break; | |
2778 | case GE: fputs ("ul", file); break; | |
2779 | } | |
2780 | break; | |
2781 | ||
2782 | case 'f': | |
87b483a1 | 2783 | /* Print appropriate test for floating point branch true operation. */ |
36a05131 BS |
2784 | switch (GET_CODE (x)) |
2785 | { | |
2786 | default: | |
2787 | fatal_insn ("Bad insn to frv_print_operand, 'f' modifier:", x); | |
2788 | ||
2789 | case EQ: fputs ("eq", file); break; | |
2790 | case NE: fputs ("ne", file); break; | |
2791 | case LT: fputs ("lt", file); break; | |
2792 | case LE: fputs ("le", file); break; | |
2793 | case GT: fputs ("gt", file); break; | |
2794 | case GE: fputs ("ge", file); break; | |
2795 | } | |
2796 | break; | |
2797 | ||
34208acf AO |
2798 | case 'g': |
2799 | /* Print appropriate GOT function. */ | |
2800 | if (GET_CODE (x) != CONST_INT) | |
2801 | fatal_insn ("Bad insn to frv_print_operand, 'g' modifier:", x); | |
2802 | fputs (unspec_got_name (INTVAL (x)), file); | |
2803 | break; | |
2804 | ||
36a05131 BS |
2805 | case 'I': |
2806 | /* Print 'i' if the operand is a constant, or is a memory reference that | |
87b483a1 | 2807 | adds a constant. */ |
36a05131 BS |
2808 | if (GET_CODE (x) == MEM) |
2809 | x = ((GET_CODE (XEXP (x, 0)) == PLUS) | |
2810 | ? XEXP (XEXP (x, 0), 1) | |
2811 | : XEXP (x, 0)); | |
34208acf AO |
2812 | else if (GET_CODE (x) == PLUS) |
2813 | x = XEXP (x, 1); | |
36a05131 BS |
2814 | |
2815 | switch (GET_CODE (x)) | |
2816 | { | |
2817 | default: | |
2818 | break; | |
2819 | ||
2820 | case CONST_INT: | |
2821 | case SYMBOL_REF: | |
2822 | case CONST: | |
2823 | fputs ("i", file); | |
2824 | break; | |
2825 | } | |
2826 | break; | |
2827 | ||
2828 | case 'i': | |
2829 | /* For jump instructions, print 'i' if the operand is a constant or | |
87b483a1 | 2830 | is an expression that adds a constant. */ |
36a05131 BS |
2831 | if (GET_CODE (x) == CONST_INT) |
2832 | fputs ("i", file); | |
2833 | ||
2834 | else | |
2835 | { | |
2836 | if (GET_CODE (x) == CONST_INT | |
2837 | || (GET_CODE (x) == PLUS | |
2838 | && (GET_CODE (XEXP (x, 1)) == CONST_INT | |
2839 | || GET_CODE (XEXP (x, 0)) == CONST_INT))) | |
2840 | fputs ("i", file); | |
2841 | } | |
2842 | break; | |
2843 | ||
2844 | case 'L': | |
2845 | /* Print the lower register of a double word register pair */ | |
2846 | if (GET_CODE (x) == REG) | |
2847 | fputs (reg_names[ REGNO (x)+1 ], file); | |
2848 | else | |
2849 | fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x); | |
2850 | break; | |
2851 | ||
87b483a1 | 2852 | /* case 'l': print a LABEL_REF. */ |
36a05131 BS |
2853 | |
2854 | case 'M': | |
2855 | case 'N': | |
2856 | /* Print a memory reference for ld/st/jmp, %N prints a memory reference | |
2857 | for the second word of double memory operations. */ | |
2858 | offset = (code == 'M') ? 0 : UNITS_PER_WORD; | |
2859 | switch (GET_CODE (x)) | |
2860 | { | |
2861 | default: | |
2862 | fatal_insn ("Bad insn to frv_print_operand, 'M/N' modifier:", x); | |
2863 | ||
2864 | case MEM: | |
2865 | frv_print_operand_memory_reference (file, XEXP (x, 0), offset); | |
2866 | break; | |
2867 | ||
2868 | case REG: | |
2869 | case SUBREG: | |
2870 | case CONST_INT: | |
2871 | case PLUS: | |
2872 | case SYMBOL_REF: | |
2873 | frv_print_operand_memory_reference (file, x, offset); | |
2874 | break; | |
2875 | } | |
2876 | break; | |
2877 | ||
2878 | case 'O': | |
2879 | /* Print the opcode of a command. */ | |
2880 | switch (GET_CODE (x)) | |
2881 | { | |
2882 | default: | |
2883 | fatal_insn ("Bad insn to frv_print_operand, 'O' modifier:", x); | |
2884 | ||
2885 | case PLUS: fputs ("add", file); break; | |
2886 | case MINUS: fputs ("sub", file); break; | |
2887 | case AND: fputs ("and", file); break; | |
2888 | case IOR: fputs ("or", file); break; | |
2889 | case XOR: fputs ("xor", file); break; | |
2890 | case ASHIFT: fputs ("sll", file); break; | |
2891 | case ASHIFTRT: fputs ("sra", file); break; | |
2892 | case LSHIFTRT: fputs ("srl", file); break; | |
2893 | } | |
2894 | break; | |
2895 | ||
87b483a1 | 2896 | /* case 'n': negate and print a constant int. */ |
36a05131 BS |
2897 | |
2898 | case 'P': | |
2899 | /* Print PIC label using operand as the number. */ | |
2900 | if (GET_CODE (x) != CONST_INT) | |
2901 | fatal_insn ("Bad insn to frv_print_operand, P modifier:", x); | |
2902 | ||
2903 | fprintf (file, ".LCF%ld", (long)INTVAL (x)); | |
2904 | break; | |
2905 | ||
2906 | case 'U': | |
87b483a1 | 2907 | /* Print 'u' if the operand is a update load/store. */ |
36a05131 BS |
2908 | if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY) |
2909 | fputs ("u", file); | |
2910 | break; | |
2911 | ||
2912 | case 'z': | |
87b483a1 | 2913 | /* If value is 0, print gr0, otherwise it must be a register. */ |
36a05131 BS |
2914 | if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0) |
2915 | fputs (reg_names[GPR_R0], file); | |
2916 | ||
2917 | else if (GET_CODE (x) == REG) | |
2918 | fputs (reg_names [REGNO (x)], file); | |
2919 | ||
2920 | else | |
2921 | fatal_insn ("Bad insn in frv_print_operand, z case", x); | |
2922 | break; | |
2923 | ||
2924 | case 'x': | |
87b483a1 | 2925 | /* Print constant in hex. */ |
36a05131 BS |
2926 | if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) |
2927 | { | |
2928 | fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value); | |
2929 | break; | |
2930 | } | |
2931 | ||
87b483a1 | 2932 | /* Fall through. */ |
36a05131 BS |
2933 | |
2934 | case '\0': | |
2935 | if (GET_CODE (x) == REG) | |
2936 | fputs (reg_names [REGNO (x)], file); | |
2937 | ||
2938 | else if (GET_CODE (x) == CONST_INT | |
2939 | || GET_CODE (x) == CONST_DOUBLE) | |
2940 | fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value); | |
2941 | ||
34208acf AO |
2942 | else if (frv_const_unspec_p (x, &unspec)) |
2943 | frv_output_const_unspec (file, &unspec); | |
2944 | ||
36a05131 BS |
2945 | else if (GET_CODE (x) == MEM) |
2946 | frv_print_operand_address (file, XEXP (x, 0)); | |
2947 | ||
2948 | else if (CONSTANT_ADDRESS_P (x)) | |
2949 | frv_print_operand_address (file, x); | |
2950 | ||
2951 | else | |
2952 | fatal_insn ("Bad insn in frv_print_operand, 0 case", x); | |
2953 | ||
2954 | break; | |
2955 | ||
2956 | default: | |
2957 | fatal_insn ("frv_print_operand: unknown code", x); | |
2958 | break; | |
2959 | } | |
2960 | ||
2961 | return; | |
2962 | } | |
2963 | ||
2964 | \f | |
2965 | /* A C statement (sans semicolon) for initializing the variable CUM for the | |
2966 | state at the beginning of the argument list. The variable has type | |
2967 | `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type | |
2968 | of the function which will receive the args, or 0 if the args are to a | |
2969 | compiler support library function. The value of INDIRECT is nonzero when | |
2970 | processing an indirect call, for example a call through a function pointer. | |
2971 | The value of INDIRECT is zero for a call to an explicitly named function, a | |
2972 | library function call, or when `INIT_CUMULATIVE_ARGS' is used to find | |
2973 | arguments for the function being compiled. | |
2974 | ||
2975 | When processing a call to a compiler support library function, LIBNAME | |
2976 | identifies which one. It is a `symbol_ref' rtx which contains the name of | |
2977 | the function, as a string. LIBNAME is 0 when an ordinary C function call is | |
2978 | being processed. Thus, each time this macro is called, either LIBNAME or | |
2979 | FNTYPE is nonzero, but never both of them at once. */ | |
2980 | ||
2981 | void | |
f2206911 KC |
2982 | frv_init_cumulative_args (CUMULATIVE_ARGS *cum, |
2983 | tree fntype, | |
2984 | rtx libname, | |
2985 | tree fndecl, | |
2986 | int incoming) | |
36a05131 BS |
2987 | { |
2988 | *cum = FIRST_ARG_REGNUM; | |
2989 | ||
2990 | if (TARGET_DEBUG_ARG) | |
2991 | { | |
2992 | fprintf (stderr, "\ninit_cumulative_args:"); | |
563a317a | 2993 | if (!fndecl && fntype) |
36a05131 BS |
2994 | fputs (" indirect", stderr); |
2995 | ||
2996 | if (incoming) | |
2997 | fputs (" incoming", stderr); | |
2998 | ||
2999 | if (fntype) | |
3000 | { | |
3001 | tree ret_type = TREE_TYPE (fntype); | |
3002 | fprintf (stderr, " return=%s,", | |
3003 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
3004 | } | |
3005 | ||
3006 | if (libname && GET_CODE (libname) == SYMBOL_REF) | |
3007 | fprintf (stderr, " libname=%s", XSTR (libname, 0)); | |
3008 | ||
3009 | if (cfun->returns_struct) | |
3010 | fprintf (stderr, " return-struct"); | |
3011 | ||
3012 | putc ('\n', stderr); | |
3013 | } | |
3014 | } | |
3015 | ||
3016 | \f | |
fe984136 RH |
3017 | /* Return true if we should pass an argument on the stack rather than |
3018 | in registers. */ | |
3019 | ||
3020 | static bool | |
3021 | frv_must_pass_in_stack (enum machine_mode mode, tree type) | |
3022 | { | |
3023 | if (mode == BLKmode) | |
3024 | return true; | |
3025 | if (type == NULL) | |
3026 | return false; | |
3027 | return AGGREGATE_TYPE_P (type); | |
3028 | } | |
3029 | ||
36a05131 BS |
3030 | /* If defined, a C expression that gives the alignment boundary, in bits, of an |
3031 | argument with the specified mode and type. If it is not defined, | |
3032 | `PARM_BOUNDARY' is used for all arguments. */ | |
3033 | ||
3034 | int | |
f2206911 KC |
3035 | frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED, |
3036 | tree type ATTRIBUTE_UNUSED) | |
36a05131 BS |
3037 | { |
3038 | return BITS_PER_WORD; | |
3039 | } | |
3040 | ||
36a05131 | 3041 | rtx |
f2206911 KC |
3042 | frv_function_arg (CUMULATIVE_ARGS *cum, |
3043 | enum machine_mode mode, | |
3044 | tree type ATTRIBUTE_UNUSED, | |
3045 | int named, | |
3046 | int incoming ATTRIBUTE_UNUSED) | |
36a05131 BS |
3047 | { |
3048 | enum machine_mode xmode = (mode == BLKmode) ? SImode : mode; | |
3049 | int arg_num = *cum; | |
3050 | rtx ret; | |
3051 | const char *debstr; | |
3052 | ||
3053 | /* Return a marker for use in the call instruction. */ | |
3054 | if (xmode == VOIDmode) | |
3055 | { | |
3056 | ret = const0_rtx; | |
3057 | debstr = "<0>"; | |
3058 | } | |
3059 | ||
3060 | else if (arg_num <= LAST_ARG_REGNUM) | |
3061 | { | |
f1c25d3b | 3062 | ret = gen_rtx_REG (xmode, arg_num); |
36a05131 BS |
3063 | debstr = reg_names[arg_num]; |
3064 | } | |
3065 | ||
3066 | else | |
3067 | { | |
3068 | ret = NULL_RTX; | |
3069 | debstr = "memory"; | |
3070 | } | |
3071 | ||
3072 | if (TARGET_DEBUG_ARG) | |
3073 | fprintf (stderr, | |
3074 | "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n", | |
3075 | arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr); | |
3076 | ||
3077 | return ret; | |
3078 | } | |
3079 | ||
3080 | \f | |
3081 | /* A C statement (sans semicolon) to update the summarizer variable CUM to | |
3082 | advance past an argument in the argument list. The values MODE, TYPE and | |
3083 | NAMED describe that argument. Once this is done, the variable CUM is | |
3084 | suitable for analyzing the *following* argument with `FUNCTION_ARG', etc. | |
3085 | ||
3086 | This macro need not do anything if the argument in question was passed on | |
3087 | the stack. The compiler knows how to track the amount of stack space used | |
3088 | for arguments without any special help. */ | |
3089 | ||
3090 | void | |
f2206911 KC |
3091 | frv_function_arg_advance (CUMULATIVE_ARGS *cum, |
3092 | enum machine_mode mode, | |
3093 | tree type ATTRIBUTE_UNUSED, | |
3094 | int named) | |
36a05131 BS |
3095 | { |
3096 | enum machine_mode xmode = (mode == BLKmode) ? SImode : mode; | |
3097 | int bytes = GET_MODE_SIZE (xmode); | |
3098 | int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
3099 | int arg_num = *cum; | |
3100 | ||
3101 | *cum = arg_num + words; | |
3102 | ||
3103 | if (TARGET_DEBUG_ARG) | |
3104 | fprintf (stderr, | |
3105 | "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n", | |
3106 | arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD); | |
3107 | } | |
3108 | ||
3109 | \f | |
3110 | /* A C expression for the number of words, at the beginning of an argument, | |
3111 | must be put in registers. The value must be zero for arguments that are | |
3112 | passed entirely in registers or that are entirely pushed on the stack. | |
3113 | ||
3114 | On some machines, certain arguments must be passed partially in registers | |
3115 | and partially in memory. On these machines, typically the first N words of | |
3116 | arguments are passed in registers, and the rest on the stack. If a | |
3117 | multi-word argument (a `double' or a structure) crosses that boundary, its | |
3118 | first few words must be passed in registers and the rest must be pushed. | |
3119 | This macro tells the compiler when this occurs, and how many of the words | |
3120 | should go in registers. | |
3121 | ||
3122 | `FUNCTION_ARG' for these arguments should return the first register to be | |
3123 | used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for | |
3124 | the called function. */ | |
3125 | ||
3126 | int | |
f2206911 KC |
3127 | frv_function_arg_partial_nregs (CUMULATIVE_ARGS *cum, |
3128 | enum machine_mode mode, | |
3129 | tree type ATTRIBUTE_UNUSED, | |
3130 | int named ATTRIBUTE_UNUSED) | |
36a05131 BS |
3131 | { |
3132 | enum machine_mode xmode = (mode == BLKmode) ? SImode : mode; | |
3133 | int bytes = GET_MODE_SIZE (xmode); | |
3134 | int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
3135 | int arg_num = *cum; | |
3136 | int ret; | |
3137 | ||
3138 | ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1) | |
3139 | ? LAST_ARG_REGNUM - arg_num + 1 | |
3140 | : 0); | |
3141 | ||
3142 | if (TARGET_DEBUG_ARG && ret) | |
3143 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
3144 | ||
3145 | return ret; | |
3146 | ||
3147 | } | |
3148 | ||
3149 | \f | |
36a05131 | 3150 | int |
f2206911 KC |
3151 | frv_function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, |
3152 | enum machine_mode mode, | |
3153 | tree type, | |
3154 | int named ATTRIBUTE_UNUSED) | |
36a05131 | 3155 | { |
fe984136 | 3156 | return targetm.calls.must_pass_in_stack (mode, type); |
36a05131 BS |
3157 | } |
3158 | ||
3159 | /* If defined, a C expression that indicates when it is the called function's | |
3160 | responsibility to make a copy of arguments passed by invisible reference. | |
3161 | Normally, the caller makes a copy and passes the address of the copy to the | |
3162 | routine being called. When FUNCTION_ARG_CALLEE_COPIES is defined and is | |
3163 | nonzero, the caller does not make a copy. Instead, it passes a pointer to | |
3164 | the "live" value. The called function must not modify this value. If it | |
3165 | can be determined that the value won't be modified, it need not make a copy; | |
3166 | otherwise a copy must be made. */ | |
3167 | ||
3168 | int | |
f2206911 KC |
3169 | frv_function_arg_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, |
3170 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
3171 | tree type ATTRIBUTE_UNUSED, | |
3172 | int named ATTRIBUTE_UNUSED) | |
36a05131 BS |
3173 | { |
3174 | return 0; | |
3175 | } | |
3176 | ||
3177 | \f | |
3178 | /* Return true if a register is ok to use as a base or index register. */ | |
3179 | ||
3180 | static FRV_INLINE int | |
f2206911 | 3181 | frv_regno_ok_for_base_p (int regno, int strict_p) |
36a05131 BS |
3182 | { |
3183 | if (GPR_P (regno)) | |
3184 | return TRUE; | |
3185 | ||
3186 | if (strict_p) | |
3187 | return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno])); | |
3188 | ||
3189 | if (regno == ARG_POINTER_REGNUM) | |
3190 | return TRUE; | |
3191 | ||
3192 | return (regno >= FIRST_PSEUDO_REGISTER); | |
3193 | } | |
3194 | ||
3195 | \f | |
3196 | /* A C compound statement with a conditional `goto LABEL;' executed if X (an | |
3197 | RTX) is a legitimate memory address on the target machine for a memory | |
3198 | operand of mode MODE. | |
3199 | ||
3200 | It usually pays to define several simpler macros to serve as subroutines for | |
3201 | this one. Otherwise it may be too complicated to understand. | |
3202 | ||
3203 | This macro must exist in two variants: a strict variant and a non-strict | |
3204 | one. The strict variant is used in the reload pass. It must be defined so | |
3205 | that any pseudo-register that has not been allocated a hard register is | |
3206 | considered a memory reference. In contexts where some kind of register is | |
3207 | required, a pseudo-register with no hard register must be rejected. | |
3208 | ||
3209 | The non-strict variant is used in other passes. It must be defined to | |
3210 | accept all pseudo-registers in every context where some kind of register is | |
3211 | required. | |
3212 | ||
3213 | Compiler source files that want to use the strict variant of this macro | |
3214 | define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT' | |
3215 | conditional to define the strict variant in that case and the non-strict | |
3216 | variant otherwise. | |
3217 | ||
3218 | Subroutines to check for acceptable registers for various purposes (one for | |
3219 | base registers, one for index registers, and so on) are typically among the | |
3220 | subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these | |
3221 | subroutine macros need have two variants; the higher levels of macros may be | |
3222 | the same whether strict or not. | |
3223 | ||
3224 | Normally, constant addresses which are the sum of a `symbol_ref' and an | |
3225 | integer are stored inside a `const' RTX to mark them as constant. | |
3226 | Therefore, there is no need to recognize such sums specifically as | |
3227 | legitimate addresses. Normally you would simply recognize any `const' as | |
3228 | legitimate. | |
3229 | ||
3230 | Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that | |
3231 | are not marked with `const'. It assumes that a naked `plus' indicates | |
3232 | indexing. If so, then you *must* reject such naked constant sums as | |
3233 | illegitimate addresses, so that none of them will be given to | |
3234 | `PRINT_OPERAND_ADDRESS'. | |
3235 | ||
3236 | On some machines, whether a symbolic address is legitimate depends on the | |
3237 | section that the address refers to. On these machines, define the macro | |
3238 | `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and | |
3239 | then check for it here. When you see a `const', you will have to look | |
3240 | inside it to find the `symbol_ref' in order to determine the section. | |
3241 | ||
3242 | The best way to modify the name string is by adding text to the beginning, | |
3243 | with suitable punctuation to prevent any ambiguity. Allocate the new name | |
3244 | in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to | |
3245 | remove and decode the added text and output the name accordingly, and define | |
14966b94 | 3246 | `(* targetm.strip_name_encoding)' to access the original name string. |
36a05131 BS |
3247 | |
3248 | You can check the information stored here into the `symbol_ref' in the | |
3249 | definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and | |
3250 | `PRINT_OPERAND_ADDRESS'. */ | |
3251 | ||
3252 | int | |
f2206911 KC |
3253 | frv_legitimate_address_p (enum machine_mode mode, |
3254 | rtx x, | |
3255 | int strict_p, | |
34208acf AO |
3256 | int condexec_p, |
3257 | int allow_double_reg_p) | |
36a05131 BS |
3258 | { |
3259 | rtx x0, x1; | |
3260 | int ret = 0; | |
3261 | HOST_WIDE_INT value; | |
3262 | unsigned regno0; | |
3263 | ||
3264 | switch (GET_CODE (x)) | |
3265 | { | |
3266 | default: | |
3267 | break; | |
3268 | ||
3269 | case SUBREG: | |
3270 | x = SUBREG_REG (x); | |
3271 | if (GET_CODE (x) != REG) | |
3272 | break; | |
3273 | ||
87b483a1 | 3274 | /* Fall through. */ |
36a05131 BS |
3275 | |
3276 | case REG: | |
3277 | ret = frv_regno_ok_for_base_p (REGNO (x), strict_p); | |
3278 | break; | |
3279 | ||
3280 | case PRE_MODIFY: | |
3281 | x0 = XEXP (x, 0); | |
3282 | x1 = XEXP (x, 1); | |
3283 | if (GET_CODE (x0) != REG | |
3284 | || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p) | |
3285 | || GET_CODE (x1) != PLUS | |
3286 | || ! rtx_equal_p (x0, XEXP (x1, 0)) | |
3287 | || GET_CODE (XEXP (x1, 1)) != REG | |
3288 | || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p)) | |
3289 | break; | |
3290 | ||
3291 | ret = 1; | |
3292 | break; | |
3293 | ||
3294 | case CONST_INT: | |
3295 | /* 12 bit immediate */ | |
3296 | if (condexec_p) | |
3297 | ret = FALSE; | |
3298 | else | |
3299 | { | |
3300 | ret = IN_RANGE_P (INTVAL (x), -2048, 2047); | |
3301 | ||
3302 | /* If we can't use load/store double operations, make sure we can | |
3303 | address the second word. */ | |
3304 | if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
3305 | ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1, | |
3306 | -2048, 2047); | |
3307 | } | |
3308 | break; | |
3309 | ||
3310 | case PLUS: | |
3311 | x0 = XEXP (x, 0); | |
3312 | x1 = XEXP (x, 1); | |
3313 | ||
3314 | if (GET_CODE (x0) == SUBREG) | |
3315 | x0 = SUBREG_REG (x0); | |
3316 | ||
3317 | if (GET_CODE (x0) != REG) | |
3318 | break; | |
3319 | ||
3320 | regno0 = REGNO (x0); | |
3321 | if (!frv_regno_ok_for_base_p (regno0, strict_p)) | |
3322 | break; | |
3323 | ||
3324 | switch (GET_CODE (x1)) | |
3325 | { | |
3326 | default: | |
3327 | break; | |
3328 | ||
3329 | case SUBREG: | |
3330 | x1 = SUBREG_REG (x1); | |
3331 | if (GET_CODE (x1) != REG) | |
3332 | break; | |
3333 | ||
87b483a1 | 3334 | /* Fall through. */ |
36a05131 BS |
3335 | |
3336 | case REG: | |
87b483a1 KH |
3337 | /* Do not allow reg+reg addressing for modes > 1 word if we |
3338 | can't depend on having move double instructions. */ | |
34208acf | 3339 | if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD) |
36a05131 BS |
3340 | ret = FALSE; |
3341 | else | |
3342 | ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p); | |
3343 | break; | |
3344 | ||
3345 | case CONST_INT: | |
3346 | /* 12 bit immediate */ | |
3347 | if (condexec_p) | |
3348 | ret = FALSE; | |
3349 | else | |
3350 | { | |
3351 | value = INTVAL (x1); | |
3352 | ret = IN_RANGE_P (value, -2048, 2047); | |
3353 | ||
3354 | /* If we can't use load/store double operations, make sure we can | |
3355 | address the second word. */ | |
3356 | if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
3357 | ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047); | |
3358 | } | |
3359 | break; | |
3360 | ||
36a05131 | 3361 | case CONST: |
34208acf | 3362 | if (!condexec_p && got12_operand (x1, VOIDmode)) |
36a05131 BS |
3363 | ret = TRUE; |
3364 | break; | |
3365 | ||
3366 | } | |
3367 | break; | |
3368 | } | |
3369 | ||
3370 | if (TARGET_DEBUG_ADDR) | |
3371 | { | |
3372 | fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n", | |
3373 | GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ", | |
3374 | (condexec_p) ? ", inside conditional code" : ""); | |
3375 | debug_rtx (x); | |
3376 | } | |
3377 | ||
3378 | return ret; | |
3379 | } | |
3380 | ||
3381 | \f | |
34208acf AO |
3382 | /* Test whether a local function descriptor is canonical, i.e., |
3383 | whether we can use FUNCDESC_GOTOFF to compute the address of the | |
3384 | function. */ | |
3385 | ||
3386 | static bool | |
3387 | frv_local_funcdesc_p (rtx fnx) | |
3388 | { | |
3389 | tree fn; | |
3390 | enum symbol_visibility vis; | |
3391 | bool ret; | |
36a05131 | 3392 | |
34208acf AO |
3393 | if (! SYMBOL_REF_LOCAL_P (fnx)) |
3394 | return FALSE; | |
3395 | ||
3396 | fn = SYMBOL_REF_DECL (fnx); | |
3397 | ||
3398 | if (! fn) | |
3399 | return FALSE; | |
36a05131 | 3400 | |
34208acf | 3401 | vis = DECL_VISIBILITY (fn); |
36a05131 | 3402 | |
34208acf AO |
3403 | if (vis == VISIBILITY_PROTECTED) |
3404 | /* Private function descriptors for protected functions are not | |
3405 | canonical. Temporarily change the visibility to global. */ | |
3406 | vis = VISIBILITY_DEFAULT; | |
3407 | else if (flag_shlib) | |
3408 | /* If we're already compiling for a shared library (that, unlike | |
3409 | executables, can't assume that the existence of a definition | |
3410 | implies local binding), we can skip the re-testing. */ | |
3411 | return TRUE; | |
36a05131 | 3412 | |
34208acf | 3413 | ret = default_binds_local_p_1 (fn, flag_pic); |
36a05131 | 3414 | |
34208acf AO |
3415 | DECL_VISIBILITY (fn) = vis; |
3416 | ||
3417 | return ret; | |
3418 | } | |
3419 | ||
3420 | /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC | |
3421 | register. */ | |
36a05131 BS |
3422 | |
3423 | rtx | |
34208acf AO |
3424 | frv_gen_GPsym2reg (rtx dest, rtx src) |
3425 | { | |
3426 | tree gp = get_identifier ("_gp"); | |
3427 | rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp)); | |
36a05131 | 3428 | |
34208acf AO |
3429 | return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12)); |
3430 | } | |
3431 | ||
3432 | static const char * | |
3433 | unspec_got_name (int i) | |
3434 | { | |
3435 | switch (i) | |
36a05131 | 3436 | { |
34208acf AO |
3437 | case R_FRV_GOT12: return "got12"; |
3438 | case R_FRV_GOTHI: return "gothi"; | |
3439 | case R_FRV_GOTLO: return "gotlo"; | |
3440 | case R_FRV_FUNCDESC: return "funcdesc"; | |
3441 | case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12"; | |
3442 | case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi"; | |
3443 | case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo"; | |
3444 | case R_FRV_FUNCDESC_VALUE: return "funcdescvalue"; | |
3445 | case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12"; | |
3446 | case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi"; | |
3447 | case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo"; | |
3448 | case R_FRV_GOTOFF12: return "gotoff12"; | |
3449 | case R_FRV_GOTOFFHI: return "gotoffhi"; | |
3450 | case R_FRV_GOTOFFLO: return "gotofflo"; | |
3451 | case R_FRV_GPREL12: return "gprel12"; | |
3452 | case R_FRV_GPRELHI: return "gprelhi"; | |
3453 | case R_FRV_GPRELLO: return "gprello"; | |
3454 | default: abort (); | |
36a05131 | 3455 | } |
34208acf | 3456 | } |
36a05131 | 3457 | |
34208acf AO |
3458 | /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset |
3459 | is added inside the relocation operator. */ | |
3460 | ||
3461 | static void | |
3462 | frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec) | |
3463 | { | |
3464 | fprintf (stream, "#%s(", unspec_got_name (unspec->reloc)); | |
3465 | output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset)); | |
3466 | fputs (")", stream); | |
3467 | } | |
3468 | ||
3469 | /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo) | |
3470 | or #gotoff12(foo) for some small data symbol foo. If so, return foo, | |
3471 | otherwise return ORIG_X. */ | |
3472 | ||
3473 | rtx | |
3474 | frv_find_base_term (rtx x) | |
3475 | { | |
3476 | struct frv_unspec unspec; | |
3477 | ||
3478 | if (frv_const_unspec_p (x, &unspec) | |
3479 | && frv_small_data_reloc_p (unspec.symbol, unspec.reloc)) | |
3480 | return plus_constant (unspec.symbol, unspec.offset); | |
3481 | ||
3482 | return x; | |
36a05131 BS |
3483 | } |
3484 | ||
3485 | /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if | |
3486 | the operand is used by a predicated instruction. */ | |
3487 | ||
3488 | static int | |
f2206911 | 3489 | frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p) |
36a05131 BS |
3490 | { |
3491 | return ((GET_MODE (op) == mode || mode == VOIDmode) | |
3492 | && GET_CODE (op) == MEM | |
3493 | && frv_legitimate_address_p (mode, XEXP (op, 0), | |
34208acf AO |
3494 | reload_completed, condexec_p, FALSE)); |
3495 | } | |
3496 | ||
3497 | void | |
764678d1 | 3498 | frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall) |
34208acf AO |
3499 | { |
3500 | rtx lr = gen_rtx_REG (Pmode, LR_REGNO); | |
3501 | rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG); | |
3502 | rtx c, rvrtx=0; | |
3503 | rtx addr; | |
3504 | ||
3505 | if (ret_value) | |
3506 | { | |
3507 | rvrtx = operands[0]; | |
3508 | operands ++; | |
3509 | } | |
3510 | ||
3511 | addr = XEXP (operands[0], 0); | |
3512 | ||
3513 | /* Inline PLTs if we're optimizing for speed. We'd like to inline | |
3514 | any calls that would involve a PLT, but can't tell, since we | |
3515 | don't know whether an extern function is going to be provided by | |
3516 | a separate translation unit or imported from a separate module. | |
3517 | When compiling for shared libraries, if the function has default | |
3518 | visibility, we assume it's overridable, so we inline the PLT, but | |
3519 | for executables, we don't really have a way to make a good | |
3520 | decision: a function is as likely to be imported from a shared | |
3521 | library as it is to be defined in the executable itself. We | |
3522 | assume executables will get global functions defined locally, | |
3523 | whereas shared libraries will have them potentially overridden, | |
3524 | so we only inline PLTs when compiling for shared libraries. | |
3525 | ||
3526 | In order to mark a function as local to a shared library, any | |
3527 | non-default visibility attribute suffices. Unfortunately, | |
3528 | there's no simple way to tag a function declaration as ``in a | |
3529 | different module'', which we could then use to trigger PLT | |
3530 | inlining on executables. There's -minline-plt, but it affects | |
3531 | all external functions, so one would have to also mark function | |
3532 | declarations available in the same module with non-default | |
3533 | visibility, which is advantageous in itself. */ | |
764678d1 AO |
3534 | if (GET_CODE (addr) == SYMBOL_REF |
3535 | && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT) | |
3536 | || sibcall)) | |
34208acf AO |
3537 | { |
3538 | rtx x, dest; | |
3539 | dest = gen_reg_rtx (SImode); | |
3540 | if (flag_pic != 1) | |
3541 | x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG, | |
3542 | GEN_INT (R_FRV_FUNCDESC_GOTOFF12)); | |
3543 | else | |
3544 | x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG, | |
3545 | GEN_INT (R_FRV_FUNCDESC_GOTOFF12)); | |
3546 | emit_insn (x); | |
3547 | cfun->uses_pic_offset_table = TRUE; | |
3548 | addr = dest; | |
3549 | } | |
3550 | else if (GET_CODE (addr) == SYMBOL_REF) | |
3551 | { | |
3552 | /* These are always either local, or handled through a local | |
3553 | PLT. */ | |
3554 | if (ret_value) | |
3555 | c = gen_call_value_fdpicsi (rvrtx, addr, operands[1], | |
3556 | operands[2], picreg, lr); | |
3557 | else | |
3558 | c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr); | |
3559 | emit_call_insn (c); | |
3560 | return; | |
3561 | } | |
3562 | else if (! ldd_address_operand (addr, Pmode)) | |
3563 | addr = force_reg (Pmode, addr); | |
3564 | ||
3565 | picreg = gen_reg_rtx (DImode); | |
3566 | emit_insn (gen_movdi_ldd (picreg, addr)); | |
3567 | ||
764678d1 AO |
3568 | if (sibcall && ret_value) |
3569 | c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx); | |
3570 | else if (sibcall) | |
3571 | c = gen_sibcall_fdpicdi (picreg, const0_rtx); | |
3572 | else if (ret_value) | |
34208acf AO |
3573 | c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr); |
3574 | else | |
3575 | c = gen_call_fdpicdi (picreg, const0_rtx, lr); | |
3576 | emit_call_insn (c); | |
36a05131 BS |
3577 | } |
3578 | ||
34208acf AO |
3579 | /* An address operand that may use a pair of registers, an addressing |
3580 | mode that we reject in general. */ | |
3581 | ||
3582 | int | |
3583 | ldd_address_operand (rtx x, enum machine_mode mode) | |
3584 | { | |
3585 | if (GET_MODE (x) != mode && GET_MODE (x) != VOIDmode) | |
3586 | return FALSE; | |
3587 | ||
3588 | return frv_legitimate_address_p (DImode, x, reload_completed, FALSE, TRUE); | |
3589 | } | |
3590 | ||
3591 | int | |
3592 | fdpic_fptr_operand (rtx op, enum machine_mode mode) | |
3593 | { | |
3594 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3595 | return FALSE; | |
3596 | if (GET_CODE (op) != REG) | |
3597 | return FALSE; | |
3598 | if (REGNO (op) != FDPIC_FPTR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER) | |
3599 | return FALSE; | |
3600 | return TRUE; | |
3601 | } | |
36a05131 BS |
3602 | \f |
3603 | /* Return 1 is OP is a memory operand, or will be turned into one by | |
3604 | reload. */ | |
3605 | ||
f2206911 KC |
3606 | int |
3607 | frv_load_operand (rtx op, enum machine_mode mode) | |
36a05131 BS |
3608 | { |
3609 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3610 | return FALSE; | |
3611 | ||
3612 | if (reload_in_progress) | |
3613 | { | |
3614 | rtx tmp = op; | |
3615 | if (GET_CODE (tmp) == SUBREG) | |
3616 | tmp = SUBREG_REG (tmp); | |
3617 | if (GET_CODE (tmp) == REG | |
3618 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER) | |
3619 | op = reg_equiv_memory_loc[REGNO (tmp)]; | |
3620 | } | |
3621 | ||
3622 | return op && memory_operand (op, mode); | |
3623 | } | |
3624 | ||
3625 | ||
3626 | /* Return 1 if operand is a GPR register or a FPR register. */ | |
3627 | ||
f2206911 KC |
3628 | int |
3629 | gpr_or_fpr_operand (rtx op, enum machine_mode mode) | |
36a05131 BS |
3630 | { |
3631 | int regno; | |
3632 | ||
3633 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3634 | return FALSE; | |
3635 | ||
3636 | if (GET_CODE (op) == SUBREG) | |
3637 | { | |
3638 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
3639 | return register_operand (op, mode); | |
3640 | ||
3641 | op = SUBREG_REG (op); | |
3642 | } | |
3643 | ||
3644 | if (GET_CODE (op) != REG) | |
3645 | return FALSE; | |
3646 | ||
3647 | regno = REGNO (op); | |
3648 | if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER) | |
3649 | return TRUE; | |
3650 | ||
3651 | return FALSE; | |
3652 | } | |
3653 | ||
3654 | /* Return 1 if operand is a GPR register or 12 bit signed immediate. */ | |
3655 | ||
f2206911 KC |
3656 | int |
3657 | gpr_or_int12_operand (rtx op, enum machine_mode mode) | |
36a05131 BS |
3658 | { |
3659 | if (GET_CODE (op) == CONST_INT) | |
3660 | return IN_RANGE_P (INTVAL (op), -2048, 2047); | |
3661 | ||
34208acf AO |
3662 | if (got12_operand (op, mode)) |
3663 | return true; | |
3664 | ||
36a05131 BS |
3665 | if (GET_MODE (op) != mode && mode != VOIDmode) |
3666 | return FALSE; | |
3667 | ||
3668 | if (GET_CODE (op) == SUBREG) | |
3669 | { | |
3670 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
3671 | return register_operand (op, mode); | |
3672 | ||
3673 | op = SUBREG_REG (op); | |
3674 | } | |
3675 | ||
3676 | if (GET_CODE (op) != REG) | |
3677 | return FALSE; | |
3678 | ||
3679 | return GPR_OR_PSEUDO_P (REGNO (op)); | |
3680 | } | |
3681 | ||
3682 | /* Return 1 if operand is a GPR register, or a FPR register, or a 12 bit | |
3683 | signed immediate. */ | |
3684 | ||
f2206911 KC |
3685 | int |
3686 | gpr_fpr_or_int12_operand (rtx op, enum machine_mode mode) | |
36a05131 BS |
3687 | { |
3688 | int regno; | |
3689 | ||
3690 | if (GET_CODE (op) == CONST_INT) | |
3691 | return IN_RANGE_P (INTVAL (op), -2048, 2047); | |
3692 | ||
3693 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3694 | return FALSE; | |
3695 | ||
3696 | if (GET_CODE (op) == SUBREG) | |
3697 | { | |
3698 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
3699 | return register_operand (op, mode); | |
3700 | ||
3701 | op = SUBREG_REG (op); | |
3702 | } | |
3703 | ||
3704 | if (GET_CODE (op) != REG) | |
3705 | return FALSE; | |
3706 | ||
3707 | regno = REGNO (op); | |
3708 | if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER) | |
3709 | return TRUE; | |
3710 | ||
3711 | return FALSE; | |
3712 | } | |
3713 | ||
3714 | /* Return 1 if operand is a register or 6 bit signed immediate. */ | |
3715 | ||
f2206911 KC |
3716 | int |
3717 | fpr_or_int6_operand (rtx op, enum machine_mode mode) | |
36a05131 BS |
3718 | { |
3719 | if (GET_CODE (op) == CONST_INT) | |
3720 | return IN_RANGE_P (INTVAL (op), -32, 31); | |
3721 | ||
3722 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3723 | return FALSE; | |
3724 | ||
3725 | if (GET_CODE (op) == SUBREG) | |
3726 | { | |
3727 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
3728 | return register_operand (op, mode); | |
3729 | ||
3730 | op = SUBREG_REG (op); | |
3731 | } | |
3732 | ||
3733 | if (GET_CODE (op) != REG) | |
3734 | return FALSE; | |
3735 | ||
3736 | return FPR_OR_PSEUDO_P (REGNO (op)); | |
3737 | } | |
3738 | ||
3739 | /* Return 1 if operand is a register or 10 bit signed immediate. */ | |
3740 | ||
f2206911 KC |
3741 | int |
3742 | gpr_or_int10_operand (rtx op, enum machine_mode mode) | |
36a05131 BS |
3743 | { |
3744 | if (GET_CODE (op) == CONST_INT) | |
3745 | return IN_RANGE_P (INTVAL (op), -512, 511); | |
3746 | ||
3747 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3748 | return FALSE; | |
3749 | ||
3750 | if (GET_CODE (op) == SUBREG) | |
3751 | { | |
3752 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
3753 | return register_operand (op, mode); | |
3754 | ||
3755 | op = SUBREG_REG (op); | |
3756 | } | |
3757 | ||
3758 | if (GET_CODE (op) != REG) | |
3759 | return FALSE; | |
3760 | ||
3761 | return GPR_OR_PSEUDO_P (REGNO (op)); | |
3762 | } | |
3763 | ||
3764 | /* Return 1 if operand is a register or an integer immediate. */ | |
3765 | ||
f2206911 KC |
3766 | int |
3767 | gpr_or_int_operand (rtx op, enum machine_mode mode) | |
36a05131 BS |
3768 | { |
3769 | if (GET_CODE (op) == CONST_INT) | |
3770 | return TRUE; | |
3771 | ||
3772 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3773 | return FALSE; | |
3774 | ||
3775 | if (GET_CODE (op) == SUBREG) | |
3776 | { | |
3777 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
3778 | return register_operand (op, mode); | |
3779 | ||
3780 | op = SUBREG_REG (op); | |
3781 | } | |
3782 | ||
3783 | if (GET_CODE (op) != REG) | |
3784 | return FALSE; | |
3785 | ||
3786 | return GPR_OR_PSEUDO_P (REGNO (op)); | |
3787 | } | |
3788 | ||
3789 | /* Return 1 if operand is a 12 bit signed immediate. */ | |
3790 | ||
f2206911 KC |
3791 | int |
3792 | int12_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
36a05131 BS |
3793 | { |
3794 | if (GET_CODE (op) != CONST_INT) | |
3795 | return FALSE; | |
3796 | ||
3797 | return IN_RANGE_P (INTVAL (op), -2048, 2047); | |
3798 | } | |
3799 | ||
3800 | /* Return 1 if operand is a 6 bit signed immediate. */ | |
3801 | ||
f2206911 KC |
3802 | int |
3803 | int6_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
36a05131 BS |
3804 | { |
3805 | if (GET_CODE (op) != CONST_INT) | |
3806 | return FALSE; | |
3807 | ||
3808 | return IN_RANGE_P (INTVAL (op), -32, 31); | |
3809 | } | |
3810 | ||
3811 | /* Return 1 if operand is a 5 bit signed immediate. */ | |
3812 | ||
f2206911 KC |
3813 | int |
3814 | int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
36a05131 BS |
3815 | { |
3816 | return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), -16, 15); | |
3817 | } | |
3818 | ||
3819 | /* Return 1 if operand is a 5 bit unsigned immediate. */ | |
3820 | ||
f2206911 KC |
3821 | int |
3822 | uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
36a05131 BS |
3823 | { |
3824 | return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 31); | |
3825 | } | |
3826 | ||
3827 | /* Return 1 if operand is a 4 bit unsigned immediate. */ | |
3828 | ||
f2206911 KC |
3829 | int |
3830 | uint4_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
36a05131 BS |
3831 | { |
3832 | return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 15); | |
3833 | } | |
3834 | ||
3835 | /* Return 1 if operand is a 1 bit unsigned immediate (0 or 1). */ | |
3836 | ||
f2206911 KC |
3837 | int |
3838 | uint1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
36a05131 BS |
3839 | { |
3840 | return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 1); | |
3841 | } | |
3842 | ||
3843 | /* Return 1 if operand is an integer constant that takes 2 instructions | |
3844 | to load up and can be split into sethi/setlo instructions.. */ | |
3845 | ||
f2206911 | 3846 | int |
34208acf | 3847 | int_2word_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
36a05131 BS |
3848 | { |
3849 | HOST_WIDE_INT value; | |
3850 | REAL_VALUE_TYPE rv; | |
3851 | long l; | |
3852 | ||
3853 | switch (GET_CODE (op)) | |
3854 | { | |
3855 | default: | |
3856 | break; | |
3857 | ||
3858 | case LABEL_REF: | |
34208acf AO |
3859 | if (TARGET_FDPIC) |
3860 | return FALSE; | |
3861 | ||
36a05131 BS |
3862 | return (flag_pic == 0); |
3863 | ||
3864 | case CONST: | |
34208acf AO |
3865 | if (flag_pic || TARGET_FDPIC) |
3866 | return FALSE; | |
3867 | ||
3868 | op = XEXP (op, 0); | |
3869 | if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT) | |
3870 | op = XEXP (op, 0); | |
3871 | return GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF; | |
36a05131 BS |
3872 | |
3873 | case SYMBOL_REF: | |
34208acf AO |
3874 | if (TARGET_FDPIC) |
3875 | return FALSE; | |
3876 | ||
36a05131 | 3877 | /* small data references are already 1 word */ |
0f6e5d45 | 3878 | return (flag_pic == 0) && (! SYMBOL_REF_SMALL_P (op)); |
36a05131 BS |
3879 | |
3880 | case CONST_INT: | |
3881 | return ! IN_RANGE_P (INTVAL (op), -32768, 32767); | |
3882 | ||
3883 | case CONST_DOUBLE: | |
3884 | if (GET_MODE (op) == SFmode) | |
3885 | { | |
3886 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
3887 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
3888 | value = l; | |
3889 | return ! IN_RANGE_P (value, -32768, 32767); | |
3890 | } | |
3891 | else if (GET_MODE (op) == VOIDmode) | |
3892 | { | |
3893 | value = CONST_DOUBLE_LOW (op); | |
3894 | return ! IN_RANGE_P (value, -32768, 32767); | |
3895 | } | |
3896 | break; | |
3897 | } | |
3898 | ||
3899 | return FALSE; | |
3900 | } | |
3901 | ||
87b483a1 | 3902 | /* Return 1 if operand is a 16 bit unsigned immediate. */ |
36a05131 | 3903 | |
f2206911 KC |
3904 | int |
3905 | uint16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
36a05131 BS |
3906 | { |
3907 | if (GET_CODE (op) != CONST_INT) | |
3908 | return FALSE; | |
3909 | ||
3910 | return IN_RANGE_P (INTVAL (op), 0, 0xffff); | |
3911 | } | |
3912 | ||
87b483a1 KH |
3913 | /* Return 1 if operand is an integer constant with the bottom 16 bits |
3914 | clear. */ | |
36a05131 | 3915 | |
f2206911 KC |
3916 | int |
3917 | upper_int16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
36a05131 BS |
3918 | { |
3919 | if (GET_CODE (op) != CONST_INT) | |
3920 | return FALSE; | |
3921 | ||
3922 | return ((INTVAL (op) & 0xffff) == 0); | |
3923 | } | |
3924 | ||
87b483a1 | 3925 | /* Return true if operand is a GPR register. */ |
36a05131 BS |
3926 | |
3927 | int | |
f2206911 | 3928 | integer_register_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
3929 | { |
3930 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3931 | return FALSE; | |
3932 | ||
3933 | if (GET_CODE (op) == SUBREG) | |
3934 | { | |
3935 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
3936 | return register_operand (op, mode); | |
3937 | ||
3938 | op = SUBREG_REG (op); | |
3939 | } | |
3940 | ||
3941 | if (GET_CODE (op) != REG) | |
3942 | return FALSE; | |
3943 | ||
3944 | return GPR_OR_PSEUDO_P (REGNO (op)); | |
3945 | } | |
3946 | ||
3947 | /* Return true if operand is a GPR register. Do not allow SUBREG's | |
3948 | here, in order to prevent a combine bug. */ | |
3949 | ||
3950 | int | |
f2206911 | 3951 | gpr_no_subreg_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
3952 | { |
3953 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3954 | return FALSE; | |
3955 | ||
3956 | if (GET_CODE (op) != REG) | |
3957 | return FALSE; | |
3958 | ||
3959 | return GPR_OR_PSEUDO_P (REGNO (op)); | |
3960 | } | |
3961 | ||
87b483a1 | 3962 | /* Return true if operand is a FPR register. */ |
36a05131 BS |
3963 | |
3964 | int | |
f2206911 | 3965 | fpr_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
3966 | { |
3967 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3968 | return FALSE; | |
3969 | ||
3970 | if (GET_CODE (op) == SUBREG) | |
3971 | { | |
3972 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
3973 | return register_operand (op, mode); | |
3974 | ||
3975 | op = SUBREG_REG (op); | |
3976 | } | |
3977 | ||
3978 | if (GET_CODE (op) != REG) | |
3979 | return FALSE; | |
3980 | ||
3981 | return FPR_OR_PSEUDO_P (REGNO (op)); | |
3982 | } | |
3983 | ||
87b483a1 | 3984 | /* Return true if operand is an even GPR or FPR register. */ |
36a05131 BS |
3985 | |
3986 | int | |
f2206911 | 3987 | even_reg_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
3988 | { |
3989 | int regno; | |
3990 | ||
3991 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3992 | return FALSE; | |
3993 | ||
3994 | if (GET_CODE (op) == SUBREG) | |
3995 | { | |
3996 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
3997 | return register_operand (op, mode); | |
3998 | ||
3999 | op = SUBREG_REG (op); | |
4000 | } | |
4001 | ||
4002 | if (GET_CODE (op) != REG) | |
4003 | return FALSE; | |
4004 | ||
4005 | regno = REGNO (op); | |
4006 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4007 | return TRUE; | |
4008 | ||
4009 | if (GPR_P (regno)) | |
4010 | return (((regno - GPR_FIRST) & 1) == 0); | |
4011 | ||
4012 | if (FPR_P (regno)) | |
4013 | return (((regno - FPR_FIRST) & 1) == 0); | |
4014 | ||
4015 | return FALSE; | |
4016 | } | |
4017 | ||
87b483a1 | 4018 | /* Return true if operand is an odd GPR register. */ |
36a05131 BS |
4019 | |
4020 | int | |
f2206911 | 4021 | odd_reg_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4022 | { |
4023 | int regno; | |
4024 | ||
4025 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4026 | return FALSE; | |
4027 | ||
4028 | if (GET_CODE (op) == SUBREG) | |
4029 | { | |
4030 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
4031 | return register_operand (op, mode); | |
4032 | ||
4033 | op = SUBREG_REG (op); | |
4034 | } | |
4035 | ||
4036 | if (GET_CODE (op) != REG) | |
4037 | return FALSE; | |
4038 | ||
4039 | regno = REGNO (op); | |
87b483a1 | 4040 | /* Assume that reload will give us an even register. */ |
36a05131 BS |
4041 | if (regno >= FIRST_PSEUDO_REGISTER) |
4042 | return FALSE; | |
4043 | ||
4044 | if (GPR_P (regno)) | |
4045 | return (((regno - GPR_FIRST) & 1) != 0); | |
4046 | ||
4047 | if (FPR_P (regno)) | |
4048 | return (((regno - FPR_FIRST) & 1) != 0); | |
4049 | ||
4050 | return FALSE; | |
4051 | } | |
4052 | ||
87b483a1 | 4053 | /* Return true if operand is an even GPR register. */ |
36a05131 BS |
4054 | |
4055 | int | |
f2206911 | 4056 | even_gpr_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4057 | { |
4058 | int regno; | |
4059 | ||
4060 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4061 | return FALSE; | |
4062 | ||
4063 | if (GET_CODE (op) == SUBREG) | |
4064 | { | |
4065 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
4066 | return register_operand (op, mode); | |
4067 | ||
4068 | op = SUBREG_REG (op); | |
4069 | } | |
4070 | ||
4071 | if (GET_CODE (op) != REG) | |
4072 | return FALSE; | |
4073 | ||
4074 | regno = REGNO (op); | |
4075 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4076 | return TRUE; | |
4077 | ||
4078 | if (! GPR_P (regno)) | |
4079 | return FALSE; | |
4080 | ||
4081 | return (((regno - GPR_FIRST) & 1) == 0); | |
4082 | } | |
4083 | ||
87b483a1 | 4084 | /* Return true if operand is an odd GPR register. */ |
36a05131 BS |
4085 | |
4086 | int | |
f2206911 | 4087 | odd_gpr_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4088 | { |
4089 | int regno; | |
4090 | ||
4091 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4092 | return FALSE; | |
4093 | ||
4094 | if (GET_CODE (op) == SUBREG) | |
4095 | { | |
4096 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
4097 | return register_operand (op, mode); | |
4098 | ||
4099 | op = SUBREG_REG (op); | |
4100 | } | |
4101 | ||
4102 | if (GET_CODE (op) != REG) | |
4103 | return FALSE; | |
4104 | ||
4105 | regno = REGNO (op); | |
87b483a1 | 4106 | /* Assume that reload will give us an even register. */ |
36a05131 BS |
4107 | if (regno >= FIRST_PSEUDO_REGISTER) |
4108 | return FALSE; | |
4109 | ||
4110 | if (! GPR_P (regno)) | |
4111 | return FALSE; | |
4112 | ||
4113 | return (((regno - GPR_FIRST) & 1) != 0); | |
4114 | } | |
4115 | ||
87b483a1 | 4116 | /* Return true if operand is a quad aligned FPR register. */ |
36a05131 BS |
4117 | |
4118 | int | |
f2206911 | 4119 | quad_fpr_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4120 | { |
4121 | int regno; | |
4122 | ||
4123 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4124 | return FALSE; | |
4125 | ||
4126 | if (GET_CODE (op) == SUBREG) | |
4127 | { | |
4128 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
4129 | return register_operand (op, mode); | |
4130 | ||
4131 | op = SUBREG_REG (op); | |
4132 | } | |
4133 | ||
4134 | if (GET_CODE (op) != REG) | |
4135 | return FALSE; | |
4136 | ||
4137 | regno = REGNO (op); | |
4138 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4139 | return TRUE; | |
4140 | ||
4141 | if (! FPR_P (regno)) | |
4142 | return FALSE; | |
4143 | ||
4144 | return (((regno - FPR_FIRST) & 3) == 0); | |
4145 | } | |
4146 | ||
87b483a1 | 4147 | /* Return true if operand is an even FPR register. */ |
36a05131 BS |
4148 | |
4149 | int | |
f2206911 | 4150 | even_fpr_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4151 | { |
4152 | int regno; | |
4153 | ||
4154 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4155 | return FALSE; | |
4156 | ||
4157 | if (GET_CODE (op) == SUBREG) | |
4158 | { | |
4159 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
4160 | return register_operand (op, mode); | |
4161 | ||
4162 | op = SUBREG_REG (op); | |
4163 | } | |
4164 | ||
4165 | if (GET_CODE (op) != REG) | |
4166 | return FALSE; | |
4167 | ||
4168 | regno = REGNO (op); | |
4169 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4170 | return TRUE; | |
4171 | ||
4172 | if (! FPR_P (regno)) | |
4173 | return FALSE; | |
4174 | ||
4175 | return (((regno - FPR_FIRST) & 1) == 0); | |
4176 | } | |
4177 | ||
87b483a1 | 4178 | /* Return true if operand is an odd FPR register. */ |
36a05131 BS |
4179 | |
4180 | int | |
f2206911 | 4181 | odd_fpr_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4182 | { |
4183 | int regno; | |
4184 | ||
4185 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4186 | return FALSE; | |
4187 | ||
4188 | if (GET_CODE (op) == SUBREG) | |
4189 | { | |
4190 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
4191 | return register_operand (op, mode); | |
4192 | ||
4193 | op = SUBREG_REG (op); | |
4194 | } | |
4195 | ||
4196 | if (GET_CODE (op) != REG) | |
4197 | return FALSE; | |
4198 | ||
4199 | regno = REGNO (op); | |
87b483a1 | 4200 | /* Assume that reload will give us an even register. */ |
36a05131 BS |
4201 | if (regno >= FIRST_PSEUDO_REGISTER) |
4202 | return FALSE; | |
4203 | ||
4204 | if (! FPR_P (regno)) | |
4205 | return FALSE; | |
4206 | ||
4207 | return (((regno - FPR_FIRST) & 1) != 0); | |
4208 | } | |
4209 | ||
4210 | /* Return true if operand is a 2 word memory address that can be loaded in one | |
4211 | instruction to load or store. We assume the stack and frame pointers are | |
4212 | suitably aligned, and variables in the small data area. FIXME -- at some we | |
4213 | should recognize other globals and statics. We can't assume that any old | |
4214 | pointer is aligned, given that arguments could be passed on an odd word on | |
4215 | the stack and the address taken and passed through to another function. */ | |
4216 | ||
4217 | int | |
f2206911 | 4218 | dbl_memory_one_insn_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4219 | { |
4220 | rtx addr; | |
4221 | rtx addr_reg; | |
4222 | ||
4223 | if (! TARGET_DWORD) | |
4224 | return FALSE; | |
4225 | ||
4226 | if (GET_CODE (op) != MEM) | |
4227 | return FALSE; | |
4228 | ||
4229 | if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD) | |
4230 | return FALSE; | |
4231 | ||
4232 | addr = XEXP (op, 0); | |
4233 | if (GET_CODE (addr) == REG) | |
4234 | addr_reg = addr; | |
4235 | ||
4236 | else if (GET_CODE (addr) == PLUS) | |
4237 | { | |
4238 | rtx addr0 = XEXP (addr, 0); | |
4239 | rtx addr1 = XEXP (addr, 1); | |
4240 | ||
4241 | if (GET_CODE (addr0) != REG) | |
4242 | return FALSE; | |
4243 | ||
34208acf | 4244 | if (got12_operand (addr1, VOIDmode)) |
36a05131 BS |
4245 | return TRUE; |
4246 | ||
4247 | if (GET_CODE (addr1) != CONST_INT) | |
4248 | return FALSE; | |
4249 | ||
4250 | if ((INTVAL (addr1) & 7) != 0) | |
4251 | return FALSE; | |
4252 | ||
4253 | addr_reg = addr0; | |
4254 | } | |
4255 | ||
4256 | else | |
4257 | return FALSE; | |
4258 | ||
4259 | if (addr_reg == frame_pointer_rtx || addr_reg == stack_pointer_rtx) | |
4260 | return TRUE; | |
4261 | ||
4262 | return FALSE; | |
4263 | } | |
4264 | ||
4265 | /* Return true if operand is a 2 word memory address that needs to | |
4266 | use two instructions to load or store. */ | |
4267 | ||
4268 | int | |
f2206911 | 4269 | dbl_memory_two_insn_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4270 | { |
4271 | if (GET_CODE (op) != MEM) | |
4272 | return FALSE; | |
4273 | ||
4274 | if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD) | |
4275 | return FALSE; | |
4276 | ||
4277 | if (! TARGET_DWORD) | |
4278 | return TRUE; | |
4279 | ||
4280 | return ! dbl_memory_one_insn_operand (op, mode); | |
4281 | } | |
4282 | ||
4283 | /* Return true if operand is something that can be an output for a move | |
4284 | operation. */ | |
4285 | ||
4286 | int | |
f2206911 | 4287 | move_destination_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4288 | { |
4289 | rtx subreg; | |
4290 | enum rtx_code code; | |
4291 | ||
4292 | switch (GET_CODE (op)) | |
4293 | { | |
4294 | default: | |
4295 | break; | |
4296 | ||
4297 | case SUBREG: | |
4298 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4299 | return FALSE; | |
4300 | ||
4301 | subreg = SUBREG_REG (op); | |
4302 | code = GET_CODE (subreg); | |
4303 | if (code == MEM) | |
4304 | return frv_legitimate_address_p (mode, XEXP (subreg, 0), | |
34208acf | 4305 | reload_completed, FALSE, FALSE); |
36a05131 BS |
4306 | |
4307 | return (code == REG); | |
4308 | ||
4309 | case REG: | |
4310 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4311 | return FALSE; | |
4312 | ||
4313 | return TRUE; | |
4314 | ||
4315 | case MEM: | |
36a05131 BS |
4316 | return frv_legitimate_memory_operand (op, mode, FALSE); |
4317 | } | |
4318 | ||
4319 | return FALSE; | |
4320 | } | |
4321 | ||
34208acf AO |
4322 | /* Look for a SYMBOL_REF of a function in an rtx. We always want to |
4323 | process these separately from any offsets, such that we add any | |
4324 | offsets to the function descriptor (the actual pointer), not to the | |
4325 | function address. */ | |
4326 | ||
4327 | static bool | |
4328 | frv_function_symbol_referenced_p (rtx x) | |
4329 | { | |
4330 | const char *format; | |
4331 | int length; | |
4332 | int j; | |
4333 | ||
4334 | if (GET_CODE (x) == SYMBOL_REF) | |
4335 | return SYMBOL_REF_FUNCTION_P (x); | |
4336 | ||
4337 | length = GET_RTX_LENGTH (GET_CODE (x)); | |
4338 | format = GET_RTX_FORMAT (GET_CODE (x)); | |
4339 | ||
4340 | for (j = 0; j < length; ++j) | |
4341 | { | |
4342 | switch (format[j]) | |
4343 | { | |
4344 | case 'e': | |
4345 | if (frv_function_symbol_referenced_p (XEXP (x, j))) | |
4346 | return TRUE; | |
4347 | break; | |
4348 | ||
4349 | case 'V': | |
4350 | case 'E': | |
4351 | if (XVEC (x, j) != 0) | |
4352 | { | |
4353 | int k; | |
4354 | for (k = 0; k < XVECLEN (x, j); ++k) | |
4355 | if (frv_function_symbol_referenced_p (XVECEXP (x, j, k))) | |
4356 | return TRUE; | |
4357 | } | |
4358 | break; | |
4359 | ||
4360 | default: | |
4361 | /* Nothing to do. */ | |
4362 | break; | |
4363 | } | |
4364 | } | |
4365 | ||
4366 | return FALSE; | |
4367 | } | |
4368 | ||
36a05131 BS |
4369 | /* Return true if operand is something that can be an input for a move |
4370 | operation. */ | |
4371 | ||
4372 | int | |
f2206911 | 4373 | move_source_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4374 | { |
4375 | rtx subreg; | |
4376 | enum rtx_code code; | |
4377 | ||
4378 | switch (GET_CODE (op)) | |
4379 | { | |
4380 | default: | |
4381 | break; | |
4382 | ||
4383 | case CONST_INT: | |
4384 | case CONST_DOUBLE: | |
36a05131 BS |
4385 | return immediate_operand (op, mode); |
4386 | ||
4387 | case SUBREG: | |
4388 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4389 | return FALSE; | |
4390 | ||
4391 | subreg = SUBREG_REG (op); | |
4392 | code = GET_CODE (subreg); | |
4393 | if (code == MEM) | |
4394 | return frv_legitimate_address_p (mode, XEXP (subreg, 0), | |
34208acf | 4395 | reload_completed, FALSE, FALSE); |
36a05131 BS |
4396 | |
4397 | return (code == REG); | |
4398 | ||
4399 | case REG: | |
4400 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4401 | return FALSE; | |
4402 | ||
4403 | return TRUE; | |
4404 | ||
4405 | case MEM: | |
36a05131 BS |
4406 | return frv_legitimate_memory_operand (op, mode, FALSE); |
4407 | } | |
4408 | ||
4409 | return FALSE; | |
4410 | } | |
4411 | ||
4412 | /* Return true if operand is something that can be an output for a conditional | |
4413 | move operation. */ | |
4414 | ||
4415 | int | |
f2206911 | 4416 | condexec_dest_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4417 | { |
4418 | rtx subreg; | |
4419 | enum rtx_code code; | |
4420 | ||
4421 | switch (GET_CODE (op)) | |
4422 | { | |
4423 | default: | |
4424 | break; | |
4425 | ||
4426 | case SUBREG: | |
4427 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4428 | return FALSE; | |
4429 | ||
4430 | subreg = SUBREG_REG (op); | |
4431 | code = GET_CODE (subreg); | |
4432 | if (code == MEM) | |
4433 | return frv_legitimate_address_p (mode, XEXP (subreg, 0), | |
34208acf | 4434 | reload_completed, TRUE, FALSE); |
36a05131 BS |
4435 | |
4436 | return (code == REG); | |
4437 | ||
4438 | case REG: | |
4439 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4440 | return FALSE; | |
4441 | ||
4442 | return TRUE; | |
4443 | ||
4444 | case MEM: | |
36a05131 BS |
4445 | return frv_legitimate_memory_operand (op, mode, TRUE); |
4446 | } | |
4447 | ||
4448 | return FALSE; | |
4449 | } | |
4450 | ||
4451 | /* Return true if operand is something that can be an input for a conditional | |
4452 | move operation. */ | |
4453 | ||
4454 | int | |
f2206911 | 4455 | condexec_source_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4456 | { |
4457 | rtx subreg; | |
4458 | enum rtx_code code; | |
4459 | ||
4460 | switch (GET_CODE (op)) | |
4461 | { | |
4462 | default: | |
4463 | break; | |
4464 | ||
4465 | case CONST_INT: | |
4466 | case CONST_DOUBLE: | |
4467 | return ZERO_P (op); | |
4468 | ||
4469 | case SUBREG: | |
4470 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4471 | return FALSE; | |
4472 | ||
4473 | subreg = SUBREG_REG (op); | |
4474 | code = GET_CODE (subreg); | |
4475 | if (code == MEM) | |
4476 | return frv_legitimate_address_p (mode, XEXP (subreg, 0), | |
34208acf | 4477 | reload_completed, TRUE, FALSE); |
36a05131 BS |
4478 | |
4479 | return (code == REG); | |
4480 | ||
4481 | case REG: | |
4482 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4483 | return FALSE; | |
4484 | ||
4485 | return TRUE; | |
4486 | ||
4487 | case MEM: | |
36a05131 BS |
4488 | return frv_legitimate_memory_operand (op, mode, TRUE); |
4489 | } | |
4490 | ||
4491 | return FALSE; | |
4492 | } | |
4493 | ||
4494 | /* Return true if operand is a register of any flavor or a 0 of the | |
4495 | appropriate type. */ | |
4496 | ||
4497 | int | |
f2206911 | 4498 | reg_or_0_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4499 | { |
4500 | switch (GET_CODE (op)) | |
4501 | { | |
4502 | default: | |
4503 | break; | |
4504 | ||
4505 | case REG: | |
4506 | case SUBREG: | |
4507 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4508 | return FALSE; | |
4509 | ||
4510 | return register_operand (op, mode); | |
4511 | ||
4512 | case CONST_INT: | |
4513 | case CONST_DOUBLE: | |
4514 | return ZERO_P (op); | |
4515 | } | |
4516 | ||
4517 | return FALSE; | |
4518 | } | |
4519 | ||
87b483a1 | 4520 | /* Return true if operand is the link register. */ |
36a05131 BS |
4521 | |
4522 | int | |
f2206911 | 4523 | lr_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4524 | { |
4525 | if (GET_CODE (op) != REG) | |
4526 | return FALSE; | |
4527 | ||
4528 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4529 | return FALSE; | |
4530 | ||
4531 | if (REGNO (op) != LR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER) | |
4532 | return FALSE; | |
4533 | ||
4534 | return TRUE; | |
4535 | } | |
4536 | ||
34208acf AO |
4537 | /* Return true if operand is the uClinux PIC register. */ |
4538 | ||
4539 | int | |
4540 | fdpic_operand (rtx op, enum machine_mode mode) | |
4541 | { | |
4542 | if (!TARGET_FDPIC) | |
4543 | return FALSE; | |
4544 | ||
4545 | if (GET_CODE (op) != REG) | |
4546 | return FALSE; | |
4547 | ||
4548 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4549 | return FALSE; | |
4550 | ||
4551 | if (REGNO (op) != FDPIC_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER) | |
4552 | return FALSE; | |
4553 | ||
4554 | return TRUE; | |
4555 | } | |
4556 | ||
4557 | int | |
4558 | got12_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
4559 | { | |
4560 | struct frv_unspec unspec; | |
4561 | ||
4562 | if (frv_const_unspec_p (op, &unspec)) | |
4563 | switch (unspec.reloc) | |
4564 | { | |
4565 | case R_FRV_GOT12: | |
4566 | case R_FRV_GOTOFF12: | |
4567 | case R_FRV_FUNCDESC_GOT12: | |
4568 | case R_FRV_FUNCDESC_GOTOFF12: | |
4569 | case R_FRV_GPREL12: | |
4570 | return true; | |
4571 | } | |
4572 | return false; | |
4573 | } | |
4574 | ||
4575 | /* Return true if OP is a valid const-unspec expression. */ | |
4576 | ||
4577 | int | |
4578 | const_unspec_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
4579 | { | |
4580 | struct frv_unspec unspec; | |
4581 | ||
4582 | return frv_const_unspec_p (op, &unspec); | |
4583 | } | |
36a05131 BS |
4584 | /* Return true if operand is a gpr register or a valid memory operation. */ |
4585 | ||
4586 | int | |
f2206911 | 4587 | gpr_or_memory_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4588 | { |
4589 | return (integer_register_operand (op, mode) | |
4590 | || frv_legitimate_memory_operand (op, mode, FALSE)); | |
4591 | } | |
4592 | ||
4593 | /* Return true if operand is a fpr register or a valid memory operation. */ | |
4594 | ||
4595 | int | |
f2206911 | 4596 | fpr_or_memory_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4597 | { |
4598 | return (fpr_operand (op, mode) | |
4599 | || frv_legitimate_memory_operand (op, mode, FALSE)); | |
4600 | } | |
4601 | ||
87b483a1 | 4602 | /* Return true if operand is an icc register. */ |
36a05131 BS |
4603 | |
4604 | int | |
f2206911 | 4605 | icc_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4606 | { |
4607 | int regno; | |
4608 | ||
4609 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4610 | return FALSE; | |
4611 | ||
4612 | if (GET_CODE (op) != REG) | |
4613 | return FALSE; | |
4614 | ||
4615 | regno = REGNO (op); | |
4616 | return ICC_OR_PSEUDO_P (regno); | |
4617 | } | |
4618 | ||
87b483a1 | 4619 | /* Return true if operand is an fcc register. */ |
36a05131 BS |
4620 | |
4621 | int | |
f2206911 | 4622 | fcc_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4623 | { |
4624 | int regno; | |
4625 | ||
4626 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4627 | return FALSE; | |
4628 | ||
4629 | if (GET_CODE (op) != REG) | |
4630 | return FALSE; | |
4631 | ||
4632 | regno = REGNO (op); | |
4633 | return FCC_OR_PSEUDO_P (regno); | |
4634 | } | |
4635 | ||
87b483a1 | 4636 | /* Return true if operand is either an fcc or icc register. */ |
36a05131 BS |
4637 | |
4638 | int | |
f2206911 | 4639 | cc_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4640 | { |
4641 | int regno; | |
4642 | ||
4643 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4644 | return FALSE; | |
4645 | ||
4646 | if (GET_CODE (op) != REG) | |
4647 | return FALSE; | |
4648 | ||
4649 | regno = REGNO (op); | |
4650 | if (CC_OR_PSEUDO_P (regno)) | |
4651 | return TRUE; | |
4652 | ||
4653 | return FALSE; | |
4654 | } | |
4655 | ||
87b483a1 | 4656 | /* Return true if operand is an integer CCR register. */ |
36a05131 BS |
4657 | |
4658 | int | |
f2206911 | 4659 | icr_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4660 | { |
4661 | int regno; | |
4662 | ||
4663 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4664 | return FALSE; | |
4665 | ||
4666 | if (GET_CODE (op) != REG) | |
4667 | return FALSE; | |
4668 | ||
4669 | regno = REGNO (op); | |
4670 | return ICR_OR_PSEUDO_P (regno); | |
4671 | } | |
4672 | ||
87b483a1 | 4673 | /* Return true if operand is an fcc register. */ |
36a05131 BS |
4674 | |
4675 | int | |
f2206911 | 4676 | fcr_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4677 | { |
4678 | int regno; | |
4679 | ||
4680 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4681 | return FALSE; | |
4682 | ||
4683 | if (GET_CODE (op) != REG) | |
4684 | return FALSE; | |
4685 | ||
4686 | regno = REGNO (op); | |
4687 | return FCR_OR_PSEUDO_P (regno); | |
4688 | } | |
4689 | ||
87b483a1 | 4690 | /* Return true if operand is either an fcc or icc register. */ |
36a05131 BS |
4691 | |
4692 | int | |
f2206911 | 4693 | cr_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4694 | { |
4695 | int regno; | |
4696 | ||
4697 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4698 | return FALSE; | |
4699 | ||
4700 | if (GET_CODE (op) != REG) | |
4701 | return FALSE; | |
4702 | ||
4703 | regno = REGNO (op); | |
4704 | if (CR_OR_PSEUDO_P (regno)) | |
4705 | return TRUE; | |
4706 | ||
4707 | return FALSE; | |
4708 | } | |
4709 | ||
4710 | /* Return true if operand is a memory reference suitable for a call. */ | |
4711 | ||
4712 | int | |
f2206911 | 4713 | call_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4714 | { |
4715 | if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT) | |
4716 | return FALSE; | |
4717 | ||
4718 | if (GET_CODE (op) == SYMBOL_REF) | |
4719 | return TRUE; | |
4720 | ||
4721 | /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should | |
4722 | never occur anyway), but prevents reload from not handling the case | |
4723 | properly of a call through a pointer on a function that calls | |
4724 | vfork/setjmp, etc. due to the need to flush all of the registers to stack. */ | |
4725 | return gpr_or_int12_operand (op, mode); | |
4726 | } | |
4727 | ||
764678d1 AO |
4728 | /* Return true if operand is a memory reference suitable for a sibcall. */ |
4729 | ||
4730 | int | |
4731 | sibcall_operand (rtx op, enum machine_mode mode) | |
4732 | { | |
4733 | if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT) | |
4734 | return FALSE; | |
4735 | ||
4736 | /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should | |
4737 | never occur anyway), but prevents reload from not handling the case | |
4738 | properly of a call through a pointer on a function that calls | |
4739 | vfork/setjmp, etc. due to the need to flush all of the registers to stack. */ | |
4740 | return gpr_or_int12_operand (op, mode); | |
4741 | } | |
4742 | ||
5bdc5878 | 4743 | /* Return true if operator is a kind of relational operator. */ |
36a05131 BS |
4744 | |
4745 | int | |
f2206911 | 4746 | relational_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
4747 | { |
4748 | rtx op0; | |
4749 | rtx op1; | |
4750 | int regno; | |
4751 | ||
4752 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
4753 | return FALSE; | |
4754 | ||
4755 | switch (GET_CODE (op)) | |
4756 | { | |
4757 | default: | |
4758 | return FALSE; | |
4759 | ||
4760 | case EQ: | |
4761 | case NE: | |
4762 | case LE: | |
4763 | case LT: | |
4764 | case GE: | |
4765 | case GT: | |
4766 | case LEU: | |
4767 | case LTU: | |
4768 | case GEU: | |
4769 | case GTU: | |
4770 | break; | |
4771 | } | |
4772 | ||
4773 | op1 = XEXP (op, 1); | |
4774 | if (op1 != const0_rtx) | |
4775 | return FALSE; | |
4776 | ||
4777 | op0 = XEXP (op, 0); | |
4778 | if (GET_CODE (op0) != REG) | |
4779 | return FALSE; | |
4780 | ||
4781 | regno = REGNO (op0); | |
4782 | switch (GET_MODE (op0)) | |
4783 | { | |
4784 | default: | |
4785 | break; | |
4786 | ||
4787 | case CCmode: | |
4788 | case CC_UNSmode: | |
4789 | return ICC_OR_PSEUDO_P (regno); | |
4790 | ||
4791 | case CC_FPmode: | |
4792 | return FCC_OR_PSEUDO_P (regno); | |
4793 | ||
4794 | case CC_CCRmode: | |
4795 | return CR_OR_PSEUDO_P (regno); | |
4796 | } | |
4797 | ||
4798 | return FALSE; | |
4799 | } | |
4800 | ||
87b483a1 | 4801 | /* Return true if operator is a signed integer relational operator. */ |
36a05131 BS |
4802 | |
4803 | int | |
f2206911 | 4804 | signed_relational_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
4805 | { |
4806 | rtx op0; | |
4807 | rtx op1; | |
4808 | int regno; | |
4809 | ||
4810 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
4811 | return FALSE; | |
4812 | ||
4813 | switch (GET_CODE (op)) | |
4814 | { | |
4815 | default: | |
4816 | return FALSE; | |
4817 | ||
4818 | case EQ: | |
4819 | case NE: | |
4820 | case LE: | |
4821 | case LT: | |
4822 | case GE: | |
4823 | case GT: | |
4824 | break; | |
4825 | } | |
4826 | ||
4827 | op1 = XEXP (op, 1); | |
4828 | if (op1 != const0_rtx) | |
4829 | return FALSE; | |
4830 | ||
4831 | op0 = XEXP (op, 0); | |
4832 | if (GET_CODE (op0) != REG) | |
4833 | return FALSE; | |
4834 | ||
4835 | regno = REGNO (op0); | |
4836 | if (GET_MODE (op0) == CCmode && ICC_OR_PSEUDO_P (regno)) | |
4837 | return TRUE; | |
4838 | ||
4839 | if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno)) | |
4840 | return TRUE; | |
4841 | ||
4842 | return FALSE; | |
4843 | } | |
4844 | ||
87b483a1 | 4845 | /* Return true if operator is a signed integer relational operator. */ |
36a05131 BS |
4846 | |
4847 | int | |
f2206911 | 4848 | unsigned_relational_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
4849 | { |
4850 | rtx op0; | |
4851 | rtx op1; | |
4852 | int regno; | |
4853 | ||
4854 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
4855 | return FALSE; | |
4856 | ||
4857 | switch (GET_CODE (op)) | |
4858 | { | |
4859 | default: | |
4860 | return FALSE; | |
4861 | ||
4862 | case LEU: | |
4863 | case LTU: | |
4864 | case GEU: | |
4865 | case GTU: | |
4866 | break; | |
4867 | } | |
4868 | ||
4869 | op1 = XEXP (op, 1); | |
4870 | if (op1 != const0_rtx) | |
4871 | return FALSE; | |
4872 | ||
4873 | op0 = XEXP (op, 0); | |
4874 | if (GET_CODE (op0) != REG) | |
4875 | return FALSE; | |
4876 | ||
4877 | regno = REGNO (op0); | |
4878 | if (GET_MODE (op0) == CC_UNSmode && ICC_OR_PSEUDO_P (regno)) | |
4879 | return TRUE; | |
4880 | ||
4881 | if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno)) | |
4882 | return TRUE; | |
4883 | ||
4884 | return FALSE; | |
4885 | } | |
4886 | ||
87b483a1 | 4887 | /* Return true if operator is a floating point relational operator. */ |
36a05131 BS |
4888 | |
4889 | int | |
f2206911 | 4890 | float_relational_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
4891 | { |
4892 | rtx op0; | |
4893 | rtx op1; | |
4894 | int regno; | |
4895 | ||
4896 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
4897 | return FALSE; | |
4898 | ||
4899 | switch (GET_CODE (op)) | |
4900 | { | |
4901 | default: | |
4902 | return FALSE; | |
4903 | ||
4904 | case EQ: case NE: | |
4905 | case LE: case LT: | |
4906 | case GE: case GT: | |
4907 | #if 0 | |
4908 | case UEQ: case UNE: | |
4909 | case ULE: case ULT: | |
4910 | case UGE: case UGT: | |
4911 | case ORDERED: | |
4912 | case UNORDERED: | |
4913 | #endif | |
4914 | break; | |
4915 | } | |
4916 | ||
4917 | op1 = XEXP (op, 1); | |
4918 | if (op1 != const0_rtx) | |
4919 | return FALSE; | |
4920 | ||
4921 | op0 = XEXP (op, 0); | |
4922 | if (GET_CODE (op0) != REG) | |
4923 | return FALSE; | |
4924 | ||
4925 | regno = REGNO (op0); | |
4926 | if (GET_MODE (op0) == CC_FPmode && FCC_OR_PSEUDO_P (regno)) | |
4927 | return TRUE; | |
4928 | ||
4929 | if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno)) | |
4930 | return TRUE; | |
4931 | ||
4932 | return FALSE; | |
4933 | } | |
4934 | ||
4935 | /* Return true if operator is EQ/NE of a conditional execution register. */ | |
4936 | ||
4937 | int | |
f2206911 | 4938 | ccr_eqne_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
4939 | { |
4940 | enum machine_mode op_mode = GET_MODE (op); | |
4941 | rtx op0; | |
4942 | rtx op1; | |
4943 | int regno; | |
4944 | ||
4945 | if (mode != VOIDmode && op_mode != mode) | |
4946 | return FALSE; | |
4947 | ||
4948 | switch (GET_CODE (op)) | |
4949 | { | |
4950 | default: | |
4951 | return FALSE; | |
4952 | ||
4953 | case EQ: | |
4954 | case NE: | |
4955 | break; | |
4956 | } | |
4957 | ||
4958 | op1 = XEXP (op, 1); | |
4959 | if (op1 != const0_rtx) | |
4960 | return FALSE; | |
4961 | ||
4962 | op0 = XEXP (op, 0); | |
4963 | if (GET_CODE (op0) != REG) | |
4964 | return FALSE; | |
4965 | ||
4966 | regno = REGNO (op0); | |
4967 | if (op_mode == CC_CCRmode && CR_OR_PSEUDO_P (regno)) | |
4968 | return TRUE; | |
4969 | ||
4970 | return FALSE; | |
4971 | } | |
4972 | ||
4973 | /* Return true if operator is a minimum or maximum operator (both signed and | |
4974 | unsigned). */ | |
4975 | ||
4976 | int | |
f2206911 | 4977 | minmax_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
4978 | { |
4979 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
4980 | return FALSE; | |
4981 | ||
4982 | switch (GET_CODE (op)) | |
4983 | { | |
4984 | default: | |
4985 | return FALSE; | |
4986 | ||
4987 | case SMIN: | |
4988 | case SMAX: | |
4989 | case UMIN: | |
4990 | case UMAX: | |
4991 | break; | |
4992 | } | |
4993 | ||
4994 | if (! integer_register_operand (XEXP (op, 0), mode)) | |
4995 | return FALSE; | |
4996 | ||
4997 | if (! gpr_or_int10_operand (XEXP (op, 1), mode)) | |
4998 | return FALSE; | |
4999 | ||
5000 | return TRUE; | |
5001 | } | |
5002 | ||
5003 | /* Return true if operator is an integer binary operator that can executed | |
5004 | conditionally and takes 1 cycle. */ | |
5005 | ||
5006 | int | |
f2206911 | 5007 | condexec_si_binary_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
5008 | { |
5009 | enum machine_mode op_mode = GET_MODE (op); | |
5010 | ||
5011 | if (mode != VOIDmode && op_mode != mode) | |
5012 | return FALSE; | |
5013 | ||
5014 | switch (GET_CODE (op)) | |
5015 | { | |
5016 | default: | |
5017 | return FALSE; | |
5018 | ||
5019 | case PLUS: | |
5020 | case MINUS: | |
5021 | case AND: | |
5022 | case IOR: | |
5023 | case XOR: | |
5024 | case ASHIFT: | |
5025 | case ASHIFTRT: | |
5026 | case LSHIFTRT: | |
5027 | return TRUE; | |
5028 | } | |
5029 | } | |
5030 | ||
5031 | /* Return true if operator is an integer binary operator that can be | |
5032 | executed conditionally by a media instruction. */ | |
5033 | ||
5034 | int | |
f2206911 | 5035 | condexec_si_media_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
5036 | { |
5037 | enum machine_mode op_mode = GET_MODE (op); | |
5038 | ||
5039 | if (mode != VOIDmode && op_mode != mode) | |
5040 | return FALSE; | |
5041 | ||
5042 | switch (GET_CODE (op)) | |
5043 | { | |
5044 | default: | |
5045 | return FALSE; | |
5046 | ||
5047 | case AND: | |
5048 | case IOR: | |
5049 | case XOR: | |
5050 | return TRUE; | |
5051 | } | |
5052 | } | |
5053 | ||
5054 | /* Return true if operator is an integer division operator that can executed | |
5055 | conditionally. */ | |
5056 | ||
5057 | int | |
f2206911 | 5058 | condexec_si_divide_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
5059 | { |
5060 | enum machine_mode op_mode = GET_MODE (op); | |
5061 | ||
5062 | if (mode != VOIDmode && op_mode != mode) | |
5063 | return FALSE; | |
5064 | ||
5065 | switch (GET_CODE (op)) | |
5066 | { | |
5067 | default: | |
5068 | return FALSE; | |
5069 | ||
5070 | case DIV: | |
5071 | case UDIV: | |
5072 | return TRUE; | |
5073 | } | |
5074 | } | |
5075 | ||
5076 | /* Return true if operator is an integer unary operator that can executed | |
5077 | conditionally. */ | |
5078 | ||
5079 | int | |
f2206911 | 5080 | condexec_si_unary_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
5081 | { |
5082 | enum machine_mode op_mode = GET_MODE (op); | |
5083 | ||
5084 | if (mode != VOIDmode && op_mode != mode) | |
5085 | return FALSE; | |
5086 | ||
5087 | switch (GET_CODE (op)) | |
5088 | { | |
5089 | default: | |
5090 | return FALSE; | |
5091 | ||
5092 | case NEG: | |
5093 | case NOT: | |
5094 | return TRUE; | |
5095 | } | |
5096 | } | |
5097 | ||
5098 | /* Return true if operator is a conversion-type expression that can be | |
5099 | evaluated conditionally by floating-point instructions. */ | |
5100 | ||
5101 | int | |
f2206911 | 5102 | condexec_sf_conv_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
5103 | { |
5104 | enum machine_mode op_mode = GET_MODE (op); | |
5105 | ||
5106 | if (mode != VOIDmode && op_mode != mode) | |
5107 | return FALSE; | |
5108 | ||
5109 | switch (GET_CODE (op)) | |
5110 | { | |
5111 | default: | |
5112 | return FALSE; | |
5113 | ||
5114 | case NEG: | |
5115 | case ABS: | |
5116 | return TRUE; | |
5117 | } | |
5118 | } | |
5119 | ||
5120 | /* Return true if operator is an addition or subtraction expression. | |
5121 | Such expressions can be evaluated conditionally by floating-point | |
5122 | instructions. */ | |
5123 | ||
5124 | int | |
f2206911 | 5125 | condexec_sf_add_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
5126 | { |
5127 | enum machine_mode op_mode = GET_MODE (op); | |
5128 | ||
5129 | if (mode != VOIDmode && op_mode != mode) | |
5130 | return FALSE; | |
5131 | ||
5132 | switch (GET_CODE (op)) | |
5133 | { | |
5134 | default: | |
5135 | return FALSE; | |
5136 | ||
5137 | case PLUS: | |
5138 | case MINUS: | |
5139 | return TRUE; | |
5140 | } | |
5141 | } | |
5142 | ||
5143 | /* Return true if the memory operand is one that can be conditionally | |
5144 | executed. */ | |
5145 | ||
5146 | int | |
f2206911 | 5147 | condexec_memory_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
5148 | { |
5149 | enum machine_mode op_mode = GET_MODE (op); | |
5150 | rtx addr; | |
5151 | ||
5152 | if (mode != VOIDmode && op_mode != mode) | |
5153 | return FALSE; | |
5154 | ||
5155 | switch (op_mode) | |
5156 | { | |
5157 | default: | |
5158 | return FALSE; | |
5159 | ||
5160 | case QImode: | |
5161 | case HImode: | |
5162 | case SImode: | |
5163 | case SFmode: | |
5164 | break; | |
5165 | } | |
5166 | ||
5167 | if (GET_CODE (op) != MEM) | |
5168 | return FALSE; | |
5169 | ||
5170 | addr = XEXP (op, 0); | |
34208acf | 5171 | return frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE); |
36a05131 BS |
5172 | } |
5173 | ||
5174 | /* Return true if operator is an integer binary operator that can be combined | |
5175 | with a setcc operation. Do not allow the arithmetic operations that could | |
5176 | potentially overflow since the FR-V sets the condition code based on the | |
5177 | "true" value of the result, not the result after truncating to a 32-bit | |
5178 | register. */ | |
5179 | ||
5180 | int | |
f2206911 | 5181 | intop_compare_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
5182 | { |
5183 | enum machine_mode op_mode = GET_MODE (op); | |
5184 | ||
5185 | if (mode != VOIDmode && op_mode != mode) | |
5186 | return FALSE; | |
5187 | ||
5188 | switch (GET_CODE (op)) | |
5189 | { | |
5190 | default: | |
5191 | return FALSE; | |
5192 | ||
5193 | case AND: | |
5194 | case IOR: | |
5195 | case XOR: | |
5196 | case ASHIFTRT: | |
5197 | case LSHIFTRT: | |
5198 | break; | |
5199 | } | |
5200 | ||
5201 | if (! integer_register_operand (XEXP (op, 0), SImode)) | |
5202 | return FALSE; | |
5203 | ||
5204 | if (! gpr_or_int10_operand (XEXP (op, 1), SImode)) | |
5205 | return FALSE; | |
5206 | ||
5207 | return TRUE; | |
5208 | } | |
5209 | ||
5210 | /* Return true if operator is an integer binary operator that can be combined | |
5211 | with a setcc operation inside of a conditional execution. */ | |
5212 | ||
5213 | int | |
f2206911 | 5214 | condexec_intop_cmp_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
5215 | { |
5216 | enum machine_mode op_mode = GET_MODE (op); | |
5217 | ||
5218 | if (mode != VOIDmode && op_mode != mode) | |
5219 | return FALSE; | |
5220 | ||
5221 | switch (GET_CODE (op)) | |
5222 | { | |
5223 | default: | |
5224 | return FALSE; | |
5225 | ||
5226 | case AND: | |
5227 | case IOR: | |
5228 | case XOR: | |
5229 | case ASHIFTRT: | |
5230 | case LSHIFTRT: | |
5231 | break; | |
5232 | } | |
5233 | ||
5234 | if (! integer_register_operand (XEXP (op, 0), SImode)) | |
5235 | return FALSE; | |
5236 | ||
5237 | if (! integer_register_operand (XEXP (op, 1), SImode)) | |
5238 | return FALSE; | |
5239 | ||
5240 | return TRUE; | |
5241 | } | |
5242 | ||
87b483a1 | 5243 | /* Return 1 if operand is a valid ACC register number. */ |
36a05131 BS |
5244 | |
5245 | int | |
f2206911 | 5246 | acc_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
5247 | { |
5248 | int regno; | |
5249 | ||
5250 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
5251 | return FALSE; | |
5252 | ||
5253 | if (GET_CODE (op) == SUBREG) | |
5254 | { | |
5255 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
5256 | return register_operand (op, mode); | |
5257 | ||
5258 | op = SUBREG_REG (op); | |
5259 | } | |
5260 | ||
5261 | if (GET_CODE (op) != REG) | |
5262 | return FALSE; | |
5263 | ||
5264 | regno = REGNO (op); | |
5265 | return ACC_OR_PSEUDO_P (regno); | |
5266 | } | |
5267 | ||
87b483a1 | 5268 | /* Return 1 if operand is a valid even ACC register number. */ |
36a05131 BS |
5269 | |
5270 | int | |
f2206911 | 5271 | even_acc_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
5272 | { |
5273 | int regno; | |
5274 | ||
5275 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
5276 | return FALSE; | |
5277 | ||
5278 | if (GET_CODE (op) == SUBREG) | |
5279 | { | |
5280 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
5281 | return register_operand (op, mode); | |
5282 | ||
5283 | op = SUBREG_REG (op); | |
5284 | } | |
5285 | ||
5286 | if (GET_CODE (op) != REG) | |
5287 | return FALSE; | |
5288 | ||
5289 | regno = REGNO (op); | |
5290 | return (ACC_OR_PSEUDO_P (regno) && ((regno - ACC_FIRST) & 1) == 0); | |
5291 | } | |
5292 | ||
87b483a1 | 5293 | /* Return 1 if operand is zero or four. */ |
36a05131 BS |
5294 | |
5295 | int | |
f2206911 | 5296 | quad_acc_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
5297 | { |
5298 | int regno; | |
5299 | ||
5300 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
5301 | return FALSE; | |
5302 | ||
5303 | if (GET_CODE (op) == SUBREG) | |
5304 | { | |
5305 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
5306 | return register_operand (op, mode); | |
5307 | ||
5308 | op = SUBREG_REG (op); | |
5309 | } | |
5310 | ||
5311 | if (GET_CODE (op) != REG) | |
5312 | return FALSE; | |
5313 | ||
5314 | regno = REGNO (op); | |
5315 | return (ACC_OR_PSEUDO_P (regno) && ((regno - ACC_FIRST) & 3) == 0); | |
5316 | } | |
5317 | ||
87b483a1 | 5318 | /* Return 1 if operand is a valid ACCG register number. */ |
36a05131 BS |
5319 | |
5320 | int | |
f2206911 | 5321 | accg_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
5322 | { |
5323 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
5324 | return FALSE; | |
5325 | ||
5326 | if (GET_CODE (op) == SUBREG) | |
5327 | { | |
5328 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
5329 | return register_operand (op, mode); | |
5330 | ||
5331 | op = SUBREG_REG (op); | |
5332 | } | |
5333 | ||
5334 | if (GET_CODE (op) != REG) | |
5335 | return FALSE; | |
5336 | ||
5337 | return ACCG_OR_PSEUDO_P (REGNO (op)); | |
5338 | } | |
5339 | ||
5340 | \f | |
5341 | /* Return true if the bare return instruction can be used outside of the | |
5342 | epilog code. For frv, we only do it if there was no stack allocation. */ | |
5343 | ||
5344 | int | |
f2206911 | 5345 | direct_return_p (void) |
36a05131 BS |
5346 | { |
5347 | frv_stack_t *info; | |
5348 | ||
5349 | if (!reload_completed) | |
5350 | return FALSE; | |
5351 | ||
5352 | info = frv_stack_info (); | |
5353 | return (info->total_size == 0); | |
5354 | } | |
5355 | ||
5356 | \f | |
5357 | /* Emit code to handle a MOVSI, adding in the small data register or pic | |
5358 | register if needed to load up addresses. Return TRUE if the appropriate | |
5359 | instructions are emitted. */ | |
5360 | ||
5361 | int | |
f2206911 | 5362 | frv_emit_movsi (rtx dest, rtx src) |
36a05131 BS |
5363 | { |
5364 | int base_regno = -1; | |
34208acf AO |
5365 | int unspec = 0; |
5366 | rtx sym = src; | |
5367 | struct frv_unspec old_unspec; | |
36a05131 BS |
5368 | |
5369 | if (!reload_in_progress | |
5370 | && !reload_completed | |
5371 | && !register_operand (dest, SImode) | |
5372 | && (!reg_or_0_operand (src, SImode) | |
5373 | /* Virtual registers will almost always be replaced by an | |
5374 | add instruction, so expose this to CSE by copying to | |
87b483a1 | 5375 | an intermediate register. */ |
36a05131 BS |
5376 | || (GET_CODE (src) == REG |
5377 | && IN_RANGE_P (REGNO (src), | |
5378 | FIRST_VIRTUAL_REGISTER, | |
5379 | LAST_VIRTUAL_REGISTER)))) | |
5380 | { | |
5381 | emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src))); | |
5382 | return TRUE; | |
5383 | } | |
5384 | ||
5385 | /* Explicitly add in the PIC or small data register if needed. */ | |
5386 | switch (GET_CODE (src)) | |
5387 | { | |
5388 | default: | |
5389 | break; | |
5390 | ||
5391 | case LABEL_REF: | |
34208acf AO |
5392 | handle_label: |
5393 | if (TARGET_FDPIC) | |
5394 | { | |
5395 | /* Using GPREL12, we use a single GOT entry for all symbols | |
5396 | in read-only sections, but trade sequences such as: | |
5397 | ||
5398 | sethi #gothi(label), gr# | |
5399 | setlo #gotlo(label), gr# | |
5400 | ld @(gr15,gr#), gr# | |
5401 | ||
5402 | for | |
5403 | ||
5404 | ld @(gr15,#got12(_gp)), gr# | |
5405 | sethi #gprelhi(label), gr## | |
5406 | setlo #gprello(label), gr## | |
5407 | add gr#, gr##, gr## | |
5408 | ||
5409 | We may often be able to share gr# for multiple | |
5410 | computations of GPREL addresses, and we may often fold | |
5411 | the final add into the pair of registers of a load or | |
5412 | store instruction, so it's often profitable. Even when | |
5413 | optimizing for size, we're trading a GOT entry for an | |
5414 | additional instruction, which trades GOT space | |
5415 | (read-write) for code size (read-only, shareable), as | |
5416 | long as the symbol is not used in more than two different | |
5417 | locations. | |
5418 | ||
5419 | With -fpie/-fpic, we'd be trading a single load for a | |
5420 | sequence of 4 instructions, because the offset of the | |
4ee31f1e | 5421 | label can't be assumed to be addressable with 12 bits, so |
34208acf AO |
5422 | we don't do this. */ |
5423 | if (TARGET_GPREL_RO) | |
5424 | unspec = R_FRV_GPREL12; | |
5425 | else | |
5426 | unspec = R_FRV_GOT12; | |
5427 | } | |
5428 | else if (flag_pic) | |
36a05131 BS |
5429 | base_regno = PIC_REGNO; |
5430 | ||
5431 | break; | |
5432 | ||
5433 | case CONST: | |
34208acf AO |
5434 | if (frv_const_unspec_p (src, &old_unspec)) |
5435 | break; | |
36a05131 | 5436 | |
34208acf AO |
5437 | if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0))) |
5438 | { | |
5439 | handle_whatever: | |
5440 | src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0)); | |
5441 | emit_move_insn (dest, src); | |
5442 | return TRUE; | |
5443 | } | |
5444 | else | |
5445 | { | |
5446 | sym = XEXP (sym, 0); | |
5447 | if (GET_CODE (sym) == PLUS | |
5448 | && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF | |
5449 | && GET_CODE (XEXP (sym, 1)) == CONST_INT) | |
5450 | sym = XEXP (sym, 0); | |
5451 | if (GET_CODE (sym) == SYMBOL_REF) | |
5452 | goto handle_sym; | |
5453 | else if (GET_CODE (sym) == LABEL_REF) | |
5454 | goto handle_label; | |
5455 | else | |
5456 | goto handle_whatever; | |
5457 | } | |
36a05131 BS |
5458 | break; |
5459 | ||
5460 | case SYMBOL_REF: | |
34208acf AO |
5461 | handle_sym: |
5462 | if (TARGET_FDPIC) | |
5463 | { | |
5464 | if (SYMBOL_REF_FUNCTION_P (sym)) | |
5465 | { | |
5466 | if (frv_local_funcdesc_p (sym)) | |
5467 | unspec = R_FRV_FUNCDESC_GOTOFF12; | |
5468 | else | |
5469 | unspec = R_FRV_FUNCDESC_GOT12; | |
5470 | } | |
5471 | else | |
5472 | { | |
5473 | if (CONSTANT_POOL_ADDRESS_P (sym)) | |
5474 | switch (GET_CODE (get_pool_constant (sym))) | |
5475 | { | |
5476 | case CONST: | |
5477 | case SYMBOL_REF: | |
5478 | case LABEL_REF: | |
5479 | if (flag_pic) | |
5480 | { | |
5481 | unspec = R_FRV_GOTOFF12; | |
5482 | break; | |
5483 | } | |
5484 | /* Fall through. */ | |
5485 | default: | |
5486 | if (TARGET_GPREL_RO) | |
5487 | unspec = R_FRV_GPREL12; | |
5488 | else | |
5489 | unspec = R_FRV_GOT12; | |
5490 | break; | |
5491 | } | |
5492 | else if (SYMBOL_REF_LOCAL_P (sym) | |
5493 | && !SYMBOL_REF_EXTERNAL_P (sym) | |
5494 | && SYMBOL_REF_DECL (sym) | |
5495 | && (!DECL_P (SYMBOL_REF_DECL (sym)) | |
5496 | || !DECL_COMMON (SYMBOL_REF_DECL (sym)))) | |
5497 | { | |
5498 | tree decl = SYMBOL_REF_DECL (sym); | |
5499 | tree init = TREE_CODE (decl) == VAR_DECL | |
5500 | ? DECL_INITIAL (decl) | |
5501 | : TREE_CODE (decl) == CONSTRUCTOR | |
5502 | ? decl : 0; | |
5503 | int reloc = 0; | |
5504 | bool named_section, readonly; | |
5505 | ||
5506 | if (init && init != error_mark_node) | |
5507 | reloc = compute_reloc_for_constant (init); | |
5508 | ||
5509 | named_section = TREE_CODE (decl) == VAR_DECL | |
5510 | && lookup_attribute ("section", DECL_ATTRIBUTES (decl)); | |
5511 | readonly = decl_readonly_section (decl, reloc); | |
5512 | ||
5513 | if (named_section) | |
5514 | unspec = R_FRV_GOT12; | |
5515 | else if (!readonly) | |
5516 | unspec = R_FRV_GOTOFF12; | |
5517 | else if (readonly && TARGET_GPREL_RO) | |
5518 | unspec = R_FRV_GPREL12; | |
5519 | else | |
5520 | unspec = R_FRV_GOT12; | |
5521 | } | |
5522 | else | |
5523 | unspec = R_FRV_GOT12; | |
5524 | } | |
5525 | } | |
5526 | ||
5527 | else if (SYMBOL_REF_SMALL_P (sym)) | |
36a05131 BS |
5528 | base_regno = SDA_BASE_REG; |
5529 | ||
5530 | else if (flag_pic) | |
5531 | base_regno = PIC_REGNO; | |
5532 | ||
5533 | break; | |
5534 | } | |
5535 | ||
5536 | if (base_regno >= 0) | |
5537 | { | |
34208acf AO |
5538 | if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym)) |
5539 | emit_insn (gen_symGOTOFF2reg (dest, src, | |
5540 | gen_rtx_REG (Pmode, base_regno), | |
5541 | GEN_INT (R_FRV_GPREL12))); | |
5542 | else | |
5543 | emit_insn (gen_symGOTOFF2reg_hilo (dest, src, | |
5544 | gen_rtx_REG (Pmode, base_regno), | |
5545 | GEN_INT (R_FRV_GPREL12))); | |
36a05131 BS |
5546 | if (base_regno == PIC_REGNO) |
5547 | cfun->uses_pic_offset_table = TRUE; | |
34208acf AO |
5548 | return TRUE; |
5549 | } | |
36a05131 | 5550 | |
34208acf AO |
5551 | if (unspec) |
5552 | { | |
5553 | rtx x; | |
5554 | ||
5555 | /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce | |
5556 | new uses of it once reload has begun. */ | |
5557 | if (reload_in_progress || reload_completed) | |
5558 | abort (); | |
5559 | ||
5560 | switch (unspec) | |
5561 | { | |
5562 | case R_FRV_GOTOFF12: | |
5563 | if (!frv_small_data_reloc_p (sym, unspec)) | |
5564 | x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG, | |
5565 | GEN_INT (unspec)); | |
5566 | else | |
5567 | x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); | |
5568 | break; | |
5569 | case R_FRV_GPREL12: | |
5570 | if (!frv_small_data_reloc_p (sym, unspec)) | |
5571 | x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG, | |
5572 | GEN_INT (unspec)); | |
5573 | else | |
5574 | x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); | |
5575 | break; | |
5576 | case R_FRV_FUNCDESC_GOTOFF12: | |
5577 | if (flag_pic != 1) | |
5578 | x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG, | |
5579 | GEN_INT (unspec)); | |
5580 | else | |
5581 | x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); | |
5582 | break; | |
5583 | default: | |
5584 | if (flag_pic != 1) | |
5585 | x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG, | |
5586 | GEN_INT (unspec)); | |
5587 | else | |
5588 | x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); | |
5589 | break; | |
5590 | } | |
5591 | emit_insn (x); | |
5592 | cfun->uses_pic_offset_table = TRUE; | |
36a05131 BS |
5593 | return TRUE; |
5594 | } | |
5595 | ||
34208acf | 5596 | |
36a05131 BS |
5597 | return FALSE; |
5598 | } | |
5599 | ||
5600 | \f | |
5601 | /* Return a string to output a single word move. */ | |
5602 | ||
5603 | const char * | |
f2206911 | 5604 | output_move_single (rtx operands[], rtx insn) |
36a05131 BS |
5605 | { |
5606 | rtx dest = operands[0]; | |
5607 | rtx src = operands[1]; | |
5608 | ||
5609 | if (GET_CODE (dest) == REG) | |
5610 | { | |
5611 | int dest_regno = REGNO (dest); | |
5612 | enum machine_mode mode = GET_MODE (dest); | |
5613 | ||
5614 | if (GPR_P (dest_regno)) | |
5615 | { | |
5616 | if (GET_CODE (src) == REG) | |
5617 | { | |
5618 | /* gpr <- some sort of register */ | |
5619 | int src_regno = REGNO (src); | |
5620 | ||
5621 | if (GPR_P (src_regno)) | |
5622 | return "mov %1, %0"; | |
5623 | ||
5624 | else if (FPR_P (src_regno)) | |
5625 | return "movfg %1, %0"; | |
5626 | ||
5627 | else if (SPR_P (src_regno)) | |
5628 | return "movsg %1, %0"; | |
5629 | } | |
5630 | ||
5631 | else if (GET_CODE (src) == MEM) | |
5632 | { | |
5633 | /* gpr <- memory */ | |
5634 | switch (mode) | |
5635 | { | |
5636 | default: | |
5637 | break; | |
5638 | ||
5639 | case QImode: | |
5640 | return "ldsb%I1%U1 %M1,%0"; | |
5641 | ||
5642 | case HImode: | |
5643 | return "ldsh%I1%U1 %M1,%0"; | |
5644 | ||
5645 | case SImode: | |
5646 | case SFmode: | |
5647 | return "ld%I1%U1 %M1, %0"; | |
5648 | } | |
5649 | } | |
5650 | ||
5651 | else if (GET_CODE (src) == CONST_INT | |
5652 | || GET_CODE (src) == CONST_DOUBLE) | |
5653 | { | |
5654 | /* gpr <- integer/floating constant */ | |
5655 | HOST_WIDE_INT value; | |
5656 | ||
5657 | if (GET_CODE (src) == CONST_INT) | |
5658 | value = INTVAL (src); | |
5659 | ||
5660 | else if (mode == SFmode) | |
5661 | { | |
5662 | REAL_VALUE_TYPE rv; | |
5663 | long l; | |
5664 | ||
5665 | REAL_VALUE_FROM_CONST_DOUBLE (rv, src); | |
5666 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
5667 | value = l; | |
5668 | } | |
5669 | ||
5670 | else | |
5671 | value = CONST_DOUBLE_LOW (src); | |
5672 | ||
5673 | if (IN_RANGE_P (value, -32768, 32767)) | |
5674 | return "setlos %1, %0"; | |
5675 | ||
5676 | return "#"; | |
5677 | } | |
5678 | ||
5679 | else if (GET_CODE (src) == SYMBOL_REF | |
5680 | || GET_CODE (src) == LABEL_REF | |
5681 | || GET_CODE (src) == CONST) | |
5682 | { | |
36a05131 BS |
5683 | return "#"; |
5684 | } | |
5685 | } | |
5686 | ||
5687 | else if (FPR_P (dest_regno)) | |
5688 | { | |
5689 | if (GET_CODE (src) == REG) | |
5690 | { | |
5691 | /* fpr <- some sort of register */ | |
5692 | int src_regno = REGNO (src); | |
5693 | ||
5694 | if (GPR_P (src_regno)) | |
5695 | return "movgf %1, %0"; | |
5696 | ||
5697 | else if (FPR_P (src_regno)) | |
5698 | { | |
5699 | if (TARGET_HARD_FLOAT) | |
5700 | return "fmovs %1, %0"; | |
5701 | else | |
5702 | return "mor %1, %1, %0"; | |
5703 | } | |
5704 | } | |
5705 | ||
5706 | else if (GET_CODE (src) == MEM) | |
5707 | { | |
5708 | /* fpr <- memory */ | |
5709 | switch (mode) | |
5710 | { | |
5711 | default: | |
5712 | break; | |
5713 | ||
5714 | case QImode: | |
5715 | return "ldbf%I1%U1 %M1,%0"; | |
5716 | ||
5717 | case HImode: | |
5718 | return "ldhf%I1%U1 %M1,%0"; | |
5719 | ||
5720 | case SImode: | |
5721 | case SFmode: | |
5722 | return "ldf%I1%U1 %M1, %0"; | |
5723 | } | |
5724 | } | |
5725 | ||
5726 | else if (ZERO_P (src)) | |
5727 | return "movgf %., %0"; | |
5728 | } | |
5729 | ||
5730 | else if (SPR_P (dest_regno)) | |
5731 | { | |
5732 | if (GET_CODE (src) == REG) | |
5733 | { | |
5734 | /* spr <- some sort of register */ | |
5735 | int src_regno = REGNO (src); | |
5736 | ||
5737 | if (GPR_P (src_regno)) | |
5738 | return "movgs %1, %0"; | |
5739 | } | |
5740 | } | |
5741 | } | |
5742 | ||
5743 | else if (GET_CODE (dest) == MEM) | |
5744 | { | |
5745 | if (GET_CODE (src) == REG) | |
5746 | { | |
5747 | int src_regno = REGNO (src); | |
5748 | enum machine_mode mode = GET_MODE (dest); | |
5749 | ||
5750 | if (GPR_P (src_regno)) | |
5751 | { | |
5752 | switch (mode) | |
5753 | { | |
5754 | default: | |
5755 | break; | |
5756 | ||
5757 | case QImode: | |
5758 | return "stb%I0%U0 %1, %M0"; | |
5759 | ||
5760 | case HImode: | |
5761 | return "sth%I0%U0 %1, %M0"; | |
5762 | ||
5763 | case SImode: | |
5764 | case SFmode: | |
5765 | return "st%I0%U0 %1, %M0"; | |
5766 | } | |
5767 | } | |
5768 | ||
5769 | else if (FPR_P (src_regno)) | |
5770 | { | |
5771 | switch (mode) | |
5772 | { | |
5773 | default: | |
5774 | break; | |
5775 | ||
5776 | case QImode: | |
5777 | return "stbf%I0%U0 %1, %M0"; | |
5778 | ||
5779 | case HImode: | |
5780 | return "sthf%I0%U0 %1, %M0"; | |
5781 | ||
5782 | case SImode: | |
5783 | case SFmode: | |
5784 | return "stf%I0%U0 %1, %M0"; | |
5785 | } | |
5786 | } | |
5787 | } | |
5788 | ||
5789 | else if (ZERO_P (src)) | |
5790 | { | |
5791 | switch (GET_MODE (dest)) | |
5792 | { | |
5793 | default: | |
5794 | break; | |
5795 | ||
5796 | case QImode: | |
5797 | return "stb%I0%U0 %., %M0"; | |
5798 | ||
5799 | case HImode: | |
5800 | return "sth%I0%U0 %., %M0"; | |
5801 | ||
5802 | case SImode: | |
5803 | case SFmode: | |
5804 | return "st%I0%U0 %., %M0"; | |
5805 | } | |
5806 | } | |
5807 | } | |
5808 | ||
5809 | fatal_insn ("Bad output_move_single operand", insn); | |
5810 | return ""; | |
5811 | } | |
5812 | ||
5813 | \f | |
5814 | /* Return a string to output a double word move. */ | |
5815 | ||
5816 | const char * | |
f2206911 | 5817 | output_move_double (rtx operands[], rtx insn) |
36a05131 BS |
5818 | { |
5819 | rtx dest = operands[0]; | |
5820 | rtx src = operands[1]; | |
5821 | enum machine_mode mode = GET_MODE (dest); | |
5822 | ||
5823 | if (GET_CODE (dest) == REG) | |
5824 | { | |
5825 | int dest_regno = REGNO (dest); | |
5826 | ||
5827 | if (GPR_P (dest_regno)) | |
5828 | { | |
5829 | if (GET_CODE (src) == REG) | |
5830 | { | |
5831 | /* gpr <- some sort of register */ | |
5832 | int src_regno = REGNO (src); | |
5833 | ||
5834 | if (GPR_P (src_regno)) | |
5835 | return "#"; | |
5836 | ||
5837 | else if (FPR_P (src_regno)) | |
5838 | { | |
5839 | if (((dest_regno - GPR_FIRST) & 1) == 0 | |
5840 | && ((src_regno - FPR_FIRST) & 1) == 0) | |
5841 | return "movfgd %1, %0"; | |
5842 | ||
5843 | return "#"; | |
5844 | } | |
5845 | } | |
5846 | ||
5847 | else if (GET_CODE (src) == MEM) | |
5848 | { | |
5849 | /* gpr <- memory */ | |
5850 | if (dbl_memory_one_insn_operand (src, mode)) | |
5851 | return "ldd%I1%U1 %M1, %0"; | |
5852 | ||
5853 | return "#"; | |
5854 | } | |
5855 | ||
5856 | else if (GET_CODE (src) == CONST_INT | |
5857 | || GET_CODE (src) == CONST_DOUBLE) | |
5858 | return "#"; | |
5859 | } | |
5860 | ||
5861 | else if (FPR_P (dest_regno)) | |
5862 | { | |
5863 | if (GET_CODE (src) == REG) | |
5864 | { | |
5865 | /* fpr <- some sort of register */ | |
5866 | int src_regno = REGNO (src); | |
5867 | ||
5868 | if (GPR_P (src_regno)) | |
5869 | { | |
5870 | if (((dest_regno - FPR_FIRST) & 1) == 0 | |
5871 | && ((src_regno - GPR_FIRST) & 1) == 0) | |
5872 | return "movgfd %1, %0"; | |
5873 | ||
5874 | return "#"; | |
5875 | } | |
5876 | ||
5877 | else if (FPR_P (src_regno)) | |
5878 | { | |
5879 | if (TARGET_DOUBLE | |
5880 | && ((dest_regno - FPR_FIRST) & 1) == 0 | |
5881 | && ((src_regno - FPR_FIRST) & 1) == 0) | |
5882 | return "fmovd %1, %0"; | |
5883 | ||
5884 | return "#"; | |
5885 | } | |
5886 | } | |
5887 | ||
5888 | else if (GET_CODE (src) == MEM) | |
5889 | { | |
5890 | /* fpr <- memory */ | |
5891 | if (dbl_memory_one_insn_operand (src, mode)) | |
5892 | return "lddf%I1%U1 %M1, %0"; | |
5893 | ||
5894 | return "#"; | |
5895 | } | |
5896 | ||
5897 | else if (ZERO_P (src)) | |
5898 | return "#"; | |
5899 | } | |
5900 | } | |
5901 | ||
5902 | else if (GET_CODE (dest) == MEM) | |
5903 | { | |
5904 | if (GET_CODE (src) == REG) | |
5905 | { | |
5906 | int src_regno = REGNO (src); | |
5907 | ||
5908 | if (GPR_P (src_regno)) | |
5909 | { | |
5910 | if (((src_regno - GPR_FIRST) & 1) == 0 | |
5911 | && dbl_memory_one_insn_operand (dest, mode)) | |
5912 | return "std%I0%U0 %1, %M0"; | |
5913 | ||
5914 | return "#"; | |
5915 | } | |
5916 | ||
5917 | if (FPR_P (src_regno)) | |
5918 | { | |
5919 | if (((src_regno - FPR_FIRST) & 1) == 0 | |
5920 | && dbl_memory_one_insn_operand (dest, mode)) | |
5921 | return "stdf%I0%U0 %1, %M0"; | |
5922 | ||
5923 | return "#"; | |
5924 | } | |
5925 | } | |
5926 | ||
5927 | else if (ZERO_P (src)) | |
5928 | { | |
5929 | if (dbl_memory_one_insn_operand (dest, mode)) | |
5930 | return "std%I0%U0 %., %M0"; | |
5931 | ||
5932 | return "#"; | |
5933 | } | |
5934 | } | |
5935 | ||
5936 | fatal_insn ("Bad output_move_double operand", insn); | |
5937 | return ""; | |
5938 | } | |
5939 | ||
5940 | \f | |
5941 | /* Return a string to output a single word conditional move. | |
5942 | Operand0 -- EQ/NE of ccr register and 0 | |
5943 | Operand1 -- CCR register | |
5944 | Operand2 -- destination | |
5945 | Operand3 -- source */ | |
5946 | ||
5947 | const char * | |
f2206911 | 5948 | output_condmove_single (rtx operands[], rtx insn) |
36a05131 BS |
5949 | { |
5950 | rtx dest = operands[2]; | |
5951 | rtx src = operands[3]; | |
5952 | ||
5953 | if (GET_CODE (dest) == REG) | |
5954 | { | |
5955 | int dest_regno = REGNO (dest); | |
5956 | enum machine_mode mode = GET_MODE (dest); | |
5957 | ||
5958 | if (GPR_P (dest_regno)) | |
5959 | { | |
5960 | if (GET_CODE (src) == REG) | |
5961 | { | |
5962 | /* gpr <- some sort of register */ | |
5963 | int src_regno = REGNO (src); | |
5964 | ||
5965 | if (GPR_P (src_regno)) | |
5966 | return "cmov %z3, %2, %1, %e0"; | |
5967 | ||
5968 | else if (FPR_P (src_regno)) | |
5969 | return "cmovfg %3, %2, %1, %e0"; | |
5970 | } | |
5971 | ||
5972 | else if (GET_CODE (src) == MEM) | |
5973 | { | |
5974 | /* gpr <- memory */ | |
5975 | switch (mode) | |
5976 | { | |
5977 | default: | |
5978 | break; | |
5979 | ||
5980 | case QImode: | |
5981 | return "cldsb%I3%U3 %M3, %2, %1, %e0"; | |
5982 | ||
5983 | case HImode: | |
5984 | return "cldsh%I3%U3 %M3, %2, %1, %e0"; | |
5985 | ||
5986 | case SImode: | |
5987 | case SFmode: | |
5988 | return "cld%I3%U3 %M3, %2, %1, %e0"; | |
5989 | } | |
5990 | } | |
5991 | ||
5992 | else if (ZERO_P (src)) | |
5993 | return "cmov %., %2, %1, %e0"; | |
5994 | } | |
5995 | ||
5996 | else if (FPR_P (dest_regno)) | |
5997 | { | |
5998 | if (GET_CODE (src) == REG) | |
5999 | { | |
6000 | /* fpr <- some sort of register */ | |
6001 | int src_regno = REGNO (src); | |
6002 | ||
6003 | if (GPR_P (src_regno)) | |
6004 | return "cmovgf %3, %2, %1, %e0"; | |
6005 | ||
6006 | else if (FPR_P (src_regno)) | |
6007 | { | |
6008 | if (TARGET_HARD_FLOAT) | |
6009 | return "cfmovs %3,%2,%1,%e0"; | |
6010 | else | |
6011 | return "cmor %3, %3, %2, %1, %e0"; | |
6012 | } | |
6013 | } | |
6014 | ||
6015 | else if (GET_CODE (src) == MEM) | |
6016 | { | |
6017 | /* fpr <- memory */ | |
6018 | if (mode == SImode || mode == SFmode) | |
6019 | return "cldf%I3%U3 %M3, %2, %1, %e0"; | |
6020 | } | |
6021 | ||
6022 | else if (ZERO_P (src)) | |
6023 | return "cmovgf %., %2, %1, %e0"; | |
6024 | } | |
6025 | } | |
6026 | ||
6027 | else if (GET_CODE (dest) == MEM) | |
6028 | { | |
6029 | if (GET_CODE (src) == REG) | |
6030 | { | |
6031 | int src_regno = REGNO (src); | |
6032 | enum machine_mode mode = GET_MODE (dest); | |
6033 | ||
6034 | if (GPR_P (src_regno)) | |
6035 | { | |
6036 | switch (mode) | |
6037 | { | |
6038 | default: | |
6039 | break; | |
6040 | ||
6041 | case QImode: | |
6042 | return "cstb%I2%U2 %3, %M2, %1, %e0"; | |
6043 | ||
6044 | case HImode: | |
6045 | return "csth%I2%U2 %3, %M2, %1, %e0"; | |
6046 | ||
6047 | case SImode: | |
6048 | case SFmode: | |
6049 | return "cst%I2%U2 %3, %M2, %1, %e0"; | |
6050 | } | |
6051 | } | |
6052 | ||
6053 | else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode)) | |
6054 | return "cstf%I2%U2 %3, %M2, %1, %e0"; | |
6055 | } | |
6056 | ||
6057 | else if (ZERO_P (src)) | |
6058 | { | |
6059 | enum machine_mode mode = GET_MODE (dest); | |
6060 | switch (mode) | |
6061 | { | |
6062 | default: | |
6063 | break; | |
6064 | ||
6065 | case QImode: | |
6066 | return "cstb%I2%U2 %., %M2, %1, %e0"; | |
6067 | ||
6068 | case HImode: | |
6069 | return "csth%I2%U2 %., %M2, %1, %e0"; | |
6070 | ||
6071 | case SImode: | |
6072 | case SFmode: | |
6073 | return "cst%I2%U2 %., %M2, %1, %e0"; | |
6074 | } | |
6075 | } | |
6076 | } | |
6077 | ||
6078 | fatal_insn ("Bad output_condmove_single operand", insn); | |
6079 | return ""; | |
6080 | } | |
6081 | ||
6082 | \f | |
6083 | /* Emit the appropriate code to do a comparison, returning the register the | |
6084 | comparison was done it. */ | |
6085 | ||
6086 | static rtx | |
f2206911 | 6087 | frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1) |
36a05131 BS |
6088 | { |
6089 | enum machine_mode cc_mode; | |
6090 | rtx cc_reg; | |
6091 | ||
87b483a1 | 6092 | /* Floating point doesn't have comparison against a constant. */ |
36a05131 BS |
6093 | if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG) |
6094 | op1 = force_reg (GET_MODE (op0), op1); | |
6095 | ||
6096 | /* Possibly disable using anything but a fixed register in order to work | |
6097 | around cse moving comparisons past function calls. */ | |
6098 | cc_mode = SELECT_CC_MODE (test, op0, op1); | |
6099 | cc_reg = ((TARGET_ALLOC_CC) | |
6100 | ? gen_reg_rtx (cc_mode) | |
6101 | : gen_rtx_REG (cc_mode, | |
6102 | (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST)); | |
6103 | ||
6104 | emit_insn (gen_rtx_SET (VOIDmode, cc_reg, | |
6105 | gen_rtx_COMPARE (cc_mode, op0, op1))); | |
6106 | ||
6107 | return cc_reg; | |
6108 | } | |
6109 | ||
6110 | \f | |
6111 | /* Emit code for a conditional branch. The comparison operands were previously | |
6112 | stored in frv_compare_op0 and frv_compare_op1. | |
6113 | ||
6114 | XXX: I originally wanted to add a clobber of a CCR register to use in | |
6115 | conditional execution, but that confuses the rest of the compiler. */ | |
6116 | ||
6117 | int | |
f2206911 | 6118 | frv_emit_cond_branch (enum rtx_code test, rtx label) |
36a05131 BS |
6119 | { |
6120 | rtx test_rtx; | |
6121 | rtx label_ref; | |
6122 | rtx if_else; | |
6123 | rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1); | |
6124 | enum machine_mode cc_mode = GET_MODE (cc_reg); | |
6125 | ||
6126 | /* Branches generate: | |
6127 | (set (pc) | |
6128 | (if_then_else (<test>, <cc_reg>, (const_int 0)) | |
6129 | (label_ref <branch_label>) | |
6130 | (pc))) */ | |
6131 | label_ref = gen_rtx_LABEL_REF (VOIDmode, label); | |
1c563bed | 6132 | test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx); |
36a05131 BS |
6133 | if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx); |
6134 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else)); | |
6135 | return TRUE; | |
6136 | } | |
6137 | ||
6138 | \f | |
6139 | /* Emit code to set a gpr to 1/0 based on a comparison. The comparison | |
6140 | operands were previously stored in frv_compare_op0 and frv_compare_op1. */ | |
6141 | ||
6142 | int | |
f2206911 | 6143 | frv_emit_scc (enum rtx_code test, rtx target) |
36a05131 BS |
6144 | { |
6145 | rtx set; | |
6146 | rtx test_rtx; | |
6147 | rtx clobber; | |
6148 | rtx cr_reg; | |
6149 | rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1); | |
6150 | ||
6151 | /* SCC instructions generate: | |
6152 | (parallel [(set <target> (<test>, <cc_reg>, (const_int 0)) | |
6153 | (clobber (<ccr_reg>))]) */ | |
6154 | test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx); | |
6155 | set = gen_rtx_SET (VOIDmode, target, test_rtx); | |
6156 | ||
6157 | cr_reg = ((TARGET_ALLOC_CC) | |
6158 | ? gen_reg_rtx (CC_CCRmode) | |
6159 | : gen_rtx_REG (CC_CCRmode, | |
6160 | ((GET_MODE (cc_reg) == CC_FPmode) | |
6161 | ? FCR_FIRST | |
6162 | : ICR_FIRST))); | |
6163 | ||
6164 | clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg); | |
6165 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber))); | |
6166 | return TRUE; | |
6167 | } | |
6168 | ||
6169 | \f | |
6170 | /* Split a SCC instruction into component parts, returning a SEQUENCE to hold | |
839a4992 | 6171 | the separate insns. */ |
36a05131 BS |
6172 | |
6173 | rtx | |
f2206911 | 6174 | frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value) |
36a05131 BS |
6175 | { |
6176 | rtx ret; | |
6177 | ||
6178 | start_sequence (); | |
6179 | ||
6180 | /* Set the appropriate CCR bit. */ | |
6181 | emit_insn (gen_rtx_SET (VOIDmode, | |
6182 | cr_reg, | |
6183 | gen_rtx_fmt_ee (GET_CODE (test), | |
6184 | GET_MODE (cr_reg), | |
6185 | cc_reg, | |
6186 | const0_rtx))); | |
6187 | ||
6188 | /* Move the value into the destination. */ | |
6189 | emit_move_insn (dest, GEN_INT (value)); | |
6190 | ||
6191 | /* Move 0 into the destination if the test failed */ | |
6192 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
6193 | gen_rtx_EQ (GET_MODE (cr_reg), | |
6194 | cr_reg, | |
6195 | const0_rtx), | |
6196 | gen_rtx_SET (VOIDmode, dest, const0_rtx))); | |
6197 | ||
6198 | /* Finish up, return sequence. */ | |
6199 | ret = get_insns (); | |
6200 | end_sequence (); | |
6201 | return ret; | |
6202 | } | |
6203 | ||
6204 | \f | |
6205 | /* Emit the code for a conditional move, return TRUE if we could do the | |
6206 | move. */ | |
6207 | ||
6208 | int | |
f2206911 | 6209 | frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2) |
36a05131 BS |
6210 | { |
6211 | rtx set; | |
6212 | rtx clobber_cc; | |
6213 | rtx test2; | |
6214 | rtx cr_reg; | |
6215 | rtx if_rtx; | |
6216 | enum rtx_code test = GET_CODE (test_rtx); | |
6217 | rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1); | |
6218 | enum machine_mode cc_mode = GET_MODE (cc_reg); | |
6219 | ||
6220 | /* Conditional move instructions generate: | |
6221 | (parallel [(set <target> | |
6222 | (if_then_else (<test> <cc_reg> (const_int 0)) | |
6223 | <src1> | |
6224 | <src2>)) | |
6225 | (clobber (<ccr_reg>))]) */ | |
6226 | ||
6227 | /* Handle various cases of conditional move involving two constants. */ | |
6228 | if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT) | |
6229 | { | |
6230 | HOST_WIDE_INT value1 = INTVAL (src1); | |
6231 | HOST_WIDE_INT value2 = INTVAL (src2); | |
6232 | ||
87b483a1 | 6233 | /* Having 0 as one of the constants can be done by loading the other |
36a05131 BS |
6234 | constant, and optionally moving in gr0. */ |
6235 | if (value1 == 0 || value2 == 0) | |
6236 | ; | |
6237 | ||
6238 | /* If the first value is within an addi range and also the difference | |
6239 | between the two fits in an addi's range, load up the difference, then | |
6240 | conditionally move in 0, and then unconditionally add the first | |
6241 | value. */ | |
6242 | else if (IN_RANGE_P (value1, -2048, 2047) | |
6243 | && IN_RANGE_P (value2 - value1, -2048, 2047)) | |
6244 | ; | |
6245 | ||
6246 | /* If neither condition holds, just force the constant into a | |
6247 | register. */ | |
6248 | else | |
6249 | { | |
6250 | src1 = force_reg (GET_MODE (dest), src1); | |
6251 | src2 = force_reg (GET_MODE (dest), src2); | |
6252 | } | |
6253 | } | |
6254 | ||
6255 | /* If one value is a register, insure the other value is either 0 or a | |
6256 | register. */ | |
6257 | else | |
6258 | { | |
6259 | if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0) | |
6260 | src1 = force_reg (GET_MODE (dest), src1); | |
6261 | ||
6262 | if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0) | |
6263 | src2 = force_reg (GET_MODE (dest), src2); | |
6264 | } | |
6265 | ||
6266 | test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx); | |
6267 | if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2); | |
6268 | ||
6269 | set = gen_rtx_SET (VOIDmode, dest, if_rtx); | |
6270 | ||
6271 | cr_reg = ((TARGET_ALLOC_CC) | |
6272 | ? gen_reg_rtx (CC_CCRmode) | |
6273 | : gen_rtx_REG (CC_CCRmode, | |
6274 | (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST)); | |
6275 | ||
6276 | clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg); | |
6277 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc))); | |
6278 | return TRUE; | |
6279 | } | |
6280 | ||
6281 | \f | |
839a4992 | 6282 | /* Split a conditional move into constituent parts, returning a SEQUENCE |
36a05131 BS |
6283 | containing all of the insns. */ |
6284 | ||
6285 | rtx | |
f2206911 | 6286 | frv_split_cond_move (rtx operands[]) |
36a05131 BS |
6287 | { |
6288 | rtx dest = operands[0]; | |
6289 | rtx test = operands[1]; | |
6290 | rtx cc_reg = operands[2]; | |
6291 | rtx src1 = operands[3]; | |
6292 | rtx src2 = operands[4]; | |
6293 | rtx cr_reg = operands[5]; | |
6294 | rtx ret; | |
6295 | enum machine_mode cr_mode = GET_MODE (cr_reg); | |
6296 | ||
6297 | start_sequence (); | |
6298 | ||
6299 | /* Set the appropriate CCR bit. */ | |
6300 | emit_insn (gen_rtx_SET (VOIDmode, | |
6301 | cr_reg, | |
6302 | gen_rtx_fmt_ee (GET_CODE (test), | |
6303 | GET_MODE (cr_reg), | |
6304 | cc_reg, | |
6305 | const0_rtx))); | |
6306 | ||
6307 | /* Handle various cases of conditional move involving two constants. */ | |
6308 | if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT) | |
6309 | { | |
6310 | HOST_WIDE_INT value1 = INTVAL (src1); | |
6311 | HOST_WIDE_INT value2 = INTVAL (src2); | |
6312 | ||
87b483a1 | 6313 | /* Having 0 as one of the constants can be done by loading the other |
36a05131 BS |
6314 | constant, and optionally moving in gr0. */ |
6315 | if (value1 == 0) | |
6316 | { | |
6317 | emit_move_insn (dest, src2); | |
6318 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
6319 | gen_rtx_NE (cr_mode, cr_reg, | |
6320 | const0_rtx), | |
6321 | gen_rtx_SET (VOIDmode, dest, src1))); | |
6322 | } | |
6323 | ||
6324 | else if (value2 == 0) | |
6325 | { | |
6326 | emit_move_insn (dest, src1); | |
6327 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
6328 | gen_rtx_EQ (cr_mode, cr_reg, | |
6329 | const0_rtx), | |
6330 | gen_rtx_SET (VOIDmode, dest, src2))); | |
6331 | } | |
6332 | ||
6333 | /* If the first value is within an addi range and also the difference | |
6334 | between the two fits in an addi's range, load up the difference, then | |
6335 | conditionally move in 0, and then unconditionally add the first | |
6336 | value. */ | |
6337 | else if (IN_RANGE_P (value1, -2048, 2047) | |
6338 | && IN_RANGE_P (value2 - value1, -2048, 2047)) | |
6339 | { | |
6340 | rtx dest_si = ((GET_MODE (dest) == SImode) | |
6341 | ? dest | |
6342 | : gen_rtx_SUBREG (SImode, dest, 0)); | |
6343 | ||
6344 | emit_move_insn (dest_si, GEN_INT (value2 - value1)); | |
6345 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
6346 | gen_rtx_NE (cr_mode, cr_reg, | |
6347 | const0_rtx), | |
6348 | gen_rtx_SET (VOIDmode, dest_si, | |
6349 | const0_rtx))); | |
6350 | emit_insn (gen_addsi3 (dest_si, dest_si, src1)); | |
6351 | } | |
6352 | ||
6353 | else | |
6354 | abort (); | |
6355 | } | |
6356 | else | |
6357 | { | |
6358 | /* Emit the conditional move for the test being true if needed. */ | |
6359 | if (! rtx_equal_p (dest, src1)) | |
6360 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
6361 | gen_rtx_NE (cr_mode, cr_reg, const0_rtx), | |
6362 | gen_rtx_SET (VOIDmode, dest, src1))); | |
6363 | ||
6364 | /* Emit the conditional move for the test being false if needed. */ | |
6365 | if (! rtx_equal_p (dest, src2)) | |
6366 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
6367 | gen_rtx_EQ (cr_mode, cr_reg, const0_rtx), | |
6368 | gen_rtx_SET (VOIDmode, dest, src2))); | |
6369 | } | |
6370 | ||
6371 | /* Finish up, return sequence. */ | |
6372 | ret = get_insns (); | |
6373 | end_sequence (); | |
6374 | return ret; | |
6375 | } | |
6376 | ||
6377 | \f | |
6378 | /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a | |
6379 | memory location that is not known to be dword-aligned. */ | |
6380 | void | |
f2206911 | 6381 | frv_split_double_load (rtx dest, rtx source) |
36a05131 BS |
6382 | { |
6383 | int regno = REGNO (dest); | |
6384 | rtx dest1 = gen_highpart (SImode, dest); | |
6385 | rtx dest2 = gen_lowpart (SImode, dest); | |
6386 | rtx address = XEXP (source, 0); | |
6387 | ||
6388 | /* If the address is pre-modified, load the lower-numbered register | |
6389 | first, then load the other register using an integer offset from | |
6390 | the modified base register. This order should always be safe, | |
6391 | since the pre-modification cannot affect the same registers as the | |
6392 | load does. | |
6393 | ||
6394 | The situation for other loads is more complicated. Loading one | |
6395 | of the registers could affect the value of ADDRESS, so we must | |
6396 | be careful which order we do them in. */ | |
6397 | if (GET_CODE (address) == PRE_MODIFY | |
6398 | || ! refers_to_regno_p (regno, regno + 1, address, NULL)) | |
6399 | { | |
6400 | /* It is safe to load the lower-numbered register first. */ | |
6401 | emit_move_insn (dest1, change_address (source, SImode, NULL)); | |
6402 | emit_move_insn (dest2, frv_index_memory (source, SImode, 1)); | |
6403 | } | |
6404 | else | |
6405 | { | |
6406 | /* ADDRESS is not pre-modified and the address depends on the | |
6407 | lower-numbered register. Load the higher-numbered register | |
6408 | first. */ | |
6409 | emit_move_insn (dest2, frv_index_memory (source, SImode, 1)); | |
6410 | emit_move_insn (dest1, change_address (source, SImode, NULL)); | |
6411 | } | |
6412 | } | |
6413 | ||
6414 | /* Split (set DEST SOURCE), where DEST refers to a dword memory location | |
6415 | and SOURCE is either a double register or the constant zero. */ | |
6416 | void | |
f2206911 | 6417 | frv_split_double_store (rtx dest, rtx source) |
36a05131 BS |
6418 | { |
6419 | rtx dest1 = change_address (dest, SImode, NULL); | |
6420 | rtx dest2 = frv_index_memory (dest, SImode, 1); | |
6421 | if (ZERO_P (source)) | |
6422 | { | |
6423 | emit_move_insn (dest1, CONST0_RTX (SImode)); | |
6424 | emit_move_insn (dest2, CONST0_RTX (SImode)); | |
6425 | } | |
6426 | else | |
6427 | { | |
6428 | emit_move_insn (dest1, gen_highpart (SImode, source)); | |
6429 | emit_move_insn (dest2, gen_lowpart (SImode, source)); | |
6430 | } | |
6431 | } | |
6432 | ||
6433 | \f | |
6434 | /* Split a min/max operation returning a SEQUENCE containing all of the | |
6435 | insns. */ | |
6436 | ||
6437 | rtx | |
f2206911 | 6438 | frv_split_minmax (rtx operands[]) |
36a05131 BS |
6439 | { |
6440 | rtx dest = operands[0]; | |
6441 | rtx minmax = operands[1]; | |
6442 | rtx src1 = operands[2]; | |
6443 | rtx src2 = operands[3]; | |
6444 | rtx cc_reg = operands[4]; | |
6445 | rtx cr_reg = operands[5]; | |
6446 | rtx ret; | |
6447 | enum rtx_code test_code; | |
6448 | enum machine_mode cr_mode = GET_MODE (cr_reg); | |
6449 | ||
6450 | start_sequence (); | |
6451 | ||
87b483a1 | 6452 | /* Figure out which test to use. */ |
36a05131 BS |
6453 | switch (GET_CODE (minmax)) |
6454 | { | |
6455 | default: | |
6456 | abort (); | |
6457 | ||
6458 | case SMIN: test_code = LT; break; | |
6459 | case SMAX: test_code = GT; break; | |
6460 | case UMIN: test_code = LTU; break; | |
6461 | case UMAX: test_code = GTU; break; | |
6462 | } | |
6463 | ||
6464 | /* Issue the compare instruction. */ | |
6465 | emit_insn (gen_rtx_SET (VOIDmode, | |
6466 | cc_reg, | |
6467 | gen_rtx_COMPARE (GET_MODE (cc_reg), | |
6468 | src1, src2))); | |
6469 | ||
6470 | /* Set the appropriate CCR bit. */ | |
6471 | emit_insn (gen_rtx_SET (VOIDmode, | |
6472 | cr_reg, | |
6473 | gen_rtx_fmt_ee (test_code, | |
6474 | GET_MODE (cr_reg), | |
6475 | cc_reg, | |
6476 | const0_rtx))); | |
6477 | ||
9cd10576 | 6478 | /* If are taking the min/max of a nonzero constant, load that first, and |
36a05131 BS |
6479 | then do a conditional move of the other value. */ |
6480 | if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0) | |
6481 | { | |
6482 | if (rtx_equal_p (dest, src1)) | |
6483 | abort (); | |
6484 | ||
6485 | emit_move_insn (dest, src2); | |
6486 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
6487 | gen_rtx_NE (cr_mode, cr_reg, const0_rtx), | |
6488 | gen_rtx_SET (VOIDmode, dest, src1))); | |
6489 | } | |
6490 | ||
6491 | /* Otherwise, do each half of the move. */ | |
6492 | else | |
6493 | { | |
6494 | /* Emit the conditional move for the test being true if needed. */ | |
6495 | if (! rtx_equal_p (dest, src1)) | |
6496 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
6497 | gen_rtx_NE (cr_mode, cr_reg, const0_rtx), | |
6498 | gen_rtx_SET (VOIDmode, dest, src1))); | |
6499 | ||
6500 | /* Emit the conditional move for the test being false if needed. */ | |
6501 | if (! rtx_equal_p (dest, src2)) | |
6502 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
6503 | gen_rtx_EQ (cr_mode, cr_reg, const0_rtx), | |
6504 | gen_rtx_SET (VOIDmode, dest, src2))); | |
6505 | } | |
6506 | ||
6507 | /* Finish up, return sequence. */ | |
6508 | ret = get_insns (); | |
6509 | end_sequence (); | |
6510 | return ret; | |
6511 | } | |
6512 | ||
6513 | \f | |
6514 | /* Split an integer abs operation returning a SEQUENCE containing all of the | |
6515 | insns. */ | |
6516 | ||
6517 | rtx | |
f2206911 | 6518 | frv_split_abs (rtx operands[]) |
36a05131 BS |
6519 | { |
6520 | rtx dest = operands[0]; | |
6521 | rtx src = operands[1]; | |
6522 | rtx cc_reg = operands[2]; | |
6523 | rtx cr_reg = operands[3]; | |
6524 | rtx ret; | |
6525 | ||
6526 | start_sequence (); | |
6527 | ||
6528 | /* Issue the compare < 0 instruction. */ | |
6529 | emit_insn (gen_rtx_SET (VOIDmode, | |
6530 | cc_reg, | |
6531 | gen_rtx_COMPARE (CCmode, src, const0_rtx))); | |
6532 | ||
6533 | /* Set the appropriate CCR bit. */ | |
6534 | emit_insn (gen_rtx_SET (VOIDmode, | |
6535 | cr_reg, | |
6536 | gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx))); | |
6537 | ||
87b483a1 | 6538 | /* Emit the conditional negate if the value is negative. */ |
36a05131 BS |
6539 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, |
6540 | gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx), | |
6541 | gen_negsi2 (dest, src))); | |
6542 | ||
6543 | /* Emit the conditional move for the test being false if needed. */ | |
6544 | if (! rtx_equal_p (dest, src)) | |
6545 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
6546 | gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx), | |
6547 | gen_rtx_SET (VOIDmode, dest, src))); | |
6548 | ||
6549 | /* Finish up, return sequence. */ | |
6550 | ret = get_insns (); | |
6551 | end_sequence (); | |
6552 | return ret; | |
6553 | } | |
6554 | ||
6555 | \f | |
6556 | /* An internal function called by for_each_rtx to clear in a hard_reg set each | |
6557 | register used in an insn. */ | |
6558 | ||
6559 | static int | |
f2206911 | 6560 | frv_clear_registers_used (rtx *ptr, void *data) |
36a05131 BS |
6561 | { |
6562 | if (GET_CODE (*ptr) == REG) | |
6563 | { | |
6564 | int regno = REGNO (*ptr); | |
6565 | HARD_REG_SET *p_regs = (HARD_REG_SET *)data; | |
6566 | ||
6567 | if (regno < FIRST_PSEUDO_REGISTER) | |
6568 | { | |
6569 | int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr)); | |
6570 | ||
6571 | while (regno < reg_max) | |
6572 | { | |
6573 | CLEAR_HARD_REG_BIT (*p_regs, regno); | |
6574 | regno++; | |
6575 | } | |
6576 | } | |
6577 | } | |
6578 | ||
6579 | return 0; | |
6580 | } | |
6581 | ||
6582 | \f | |
6583 | /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */ | |
6584 | ||
6585 | /* On the FR-V, we don't have any extra fields per se, but it is useful hook to | |
6586 | initialize the static storage. */ | |
6587 | void | |
f2206911 | 6588 | frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED) |
36a05131 BS |
6589 | { |
6590 | frv_ifcvt.added_insns_list = NULL_RTX; | |
6591 | frv_ifcvt.cur_scratch_regs = 0; | |
6592 | frv_ifcvt.num_nested_cond_exec = 0; | |
6593 | frv_ifcvt.cr_reg = NULL_RTX; | |
6594 | frv_ifcvt.nested_cc_reg = NULL_RTX; | |
6595 | frv_ifcvt.extra_int_cr = NULL_RTX; | |
6596 | frv_ifcvt.extra_fp_cr = NULL_RTX; | |
6597 | frv_ifcvt.last_nested_if_cr = NULL_RTX; | |
6598 | } | |
6599 | ||
6600 | \f | |
1ae58c30 | 6601 | /* Internal function to add a potential insn to the list of insns to be inserted |
36a05131 BS |
6602 | if the conditional execution conversion is successful. */ |
6603 | ||
6604 | static void | |
f2206911 | 6605 | frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p) |
36a05131 BS |
6606 | { |
6607 | rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn); | |
6608 | ||
87b483a1 | 6609 | link->jump = before_p; /* Mark to add this before or after insn. */ |
36a05131 BS |
6610 | frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link, |
6611 | frv_ifcvt.added_insns_list); | |
6612 | ||
6613 | if (TARGET_DEBUG_COND_EXEC) | |
6614 | { | |
6615 | fprintf (stderr, | |
6616 | "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n", | |
6617 | (before_p) ? "before" : "after", | |
6618 | (int)INSN_UID (insn)); | |
6619 | ||
6620 | debug_rtx (pattern); | |
6621 | } | |
6622 | } | |
6623 | ||
6624 | \f | |
6625 | /* A C expression to modify the code described by the conditional if | |
6626 | information CE_INFO, possibly updating the tests in TRUE_EXPR, and | |
6627 | FALSE_EXPR for converting if-then and if-then-else code to conditional | |
6628 | instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the | |
6629 | tests cannot be converted. */ | |
6630 | ||
6631 | void | |
f2206911 | 6632 | frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false) |
36a05131 BS |
6633 | { |
6634 | basic_block test_bb = ce_info->test_bb; /* test basic block */ | |
6635 | basic_block then_bb = ce_info->then_bb; /* THEN */ | |
6636 | basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */ | |
6637 | basic_block join_bb = ce_info->join_bb; /* join block or NULL */ | |
6638 | rtx true_expr = *p_true; | |
6639 | rtx cr; | |
6640 | rtx cc; | |
6641 | rtx nested_cc; | |
6642 | enum machine_mode mode = GET_MODE (true_expr); | |
6643 | int j; | |
6644 | basic_block *bb; | |
6645 | int num_bb; | |
6646 | frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg; | |
6647 | rtx check_insn; | |
6648 | rtx sub_cond_exec_reg; | |
6649 | enum rtx_code code; | |
6650 | enum rtx_code code_true; | |
6651 | enum rtx_code code_false; | |
6652 | enum reg_class cc_class; | |
6653 | enum reg_class cr_class; | |
6654 | int cc_first; | |
6655 | int cc_last; | |
6656 | ||
6657 | /* Make sure we are only dealing with hard registers. Also honor the | |
6658 | -mno-cond-exec switch, and -mno-nested-cond-exec switches if | |
6659 | applicable. */ | |
6660 | if (!reload_completed || TARGET_NO_COND_EXEC | |
6661 | || (TARGET_NO_NESTED_CE && ce_info->pass > 1)) | |
6662 | goto fail; | |
6663 | ||
6664 | /* Figure out which registers we can allocate for our own purposes. Only | |
6665 | consider registers that are not preserved across function calls and are | |
6666 | not fixed. However, allow the ICC/ICR temporary registers to be allocated | |
87b483a1 | 6667 | if we did not need to use them in reloading other registers. */ |
fad205ff | 6668 | memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs)); |
36a05131 BS |
6669 | COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set); |
6670 | AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set); | |
6671 | SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP); | |
6672 | SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP); | |
6673 | ||
6674 | /* If this is a nested IF, we need to discover whether the CC registers that | |
6675 | are set/used inside of the block are used anywhere else. If not, we can | |
6676 | change them to be the CC register that is paired with the CR register that | |
6677 | controls the outermost IF block. */ | |
6678 | if (ce_info->pass > 1) | |
6679 | { | |
6680 | CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite); | |
6681 | for (j = CC_FIRST; j <= CC_LAST; j++) | |
6682 | if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) | |
6683 | { | |
6684 | if (REGNO_REG_SET_P (then_bb->global_live_at_start, j)) | |
6685 | continue; | |
6686 | ||
6687 | if (else_bb && REGNO_REG_SET_P (else_bb->global_live_at_start, j)) | |
6688 | continue; | |
6689 | ||
6690 | if (join_bb && REGNO_REG_SET_P (join_bb->global_live_at_start, j)) | |
6691 | continue; | |
6692 | ||
6693 | SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j); | |
6694 | } | |
6695 | } | |
6696 | ||
6697 | for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++) | |
6698 | frv_ifcvt.scratch_regs[j] = NULL_RTX; | |
6699 | ||
6700 | frv_ifcvt.added_insns_list = NULL_RTX; | |
6701 | frv_ifcvt.cur_scratch_regs = 0; | |
6702 | ||
6703 | bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks) | |
6704 | * sizeof (basic_block)); | |
6705 | ||
6706 | if (join_bb) | |
6707 | { | |
6708 | int regno; | |
6709 | ||
6710 | /* Remove anything live at the beginning of the join block from being | |
6711 | available for allocation. */ | |
6712 | EXECUTE_IF_SET_IN_REG_SET (join_bb->global_live_at_start, 0, regno, | |
6713 | { | |
6714 | if (regno < FIRST_PSEUDO_REGISTER) | |
6715 | CLEAR_HARD_REG_BIT (tmp_reg->regs, regno); | |
6716 | }); | |
6717 | } | |
6718 | ||
6719 | /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */ | |
6720 | num_bb = 0; | |
6721 | if (ce_info->num_multiple_test_blocks) | |
6722 | { | |
6723 | basic_block multiple_test_bb = ce_info->last_test_bb; | |
6724 | ||
6725 | while (multiple_test_bb != test_bb) | |
6726 | { | |
6727 | bb[num_bb++] = multiple_test_bb; | |
6728 | multiple_test_bb = multiple_test_bb->pred->src; | |
6729 | } | |
6730 | } | |
6731 | ||
6732 | /* Add in the THEN and ELSE blocks to be scanned. */ | |
6733 | bb[num_bb++] = then_bb; | |
6734 | if (else_bb) | |
6735 | bb[num_bb++] = else_bb; | |
6736 | ||
6737 | sub_cond_exec_reg = NULL_RTX; | |
6738 | frv_ifcvt.num_nested_cond_exec = 0; | |
6739 | ||
6740 | /* Scan all of the blocks for registers that must not be allocated. */ | |
6741 | for (j = 0; j < num_bb; j++) | |
6742 | { | |
a813c111 SB |
6743 | rtx last_insn = BB_END (bb[j]); |
6744 | rtx insn = BB_HEAD (bb[j]); | |
36a05131 BS |
6745 | int regno; |
6746 | ||
c263766c RH |
6747 | if (dump_file) |
6748 | fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n", | |
36a05131 BS |
6749 | (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"), |
6750 | (int) bb[j]->index, | |
a813c111 SB |
6751 | (int) INSN_UID (BB_HEAD (bb[j])), |
6752 | (int) INSN_UID (BB_END (bb[j]))); | |
36a05131 BS |
6753 | |
6754 | /* Anything live at the beginning of the block is obviously unavailable | |
6755 | for allocation. */ | |
6756 | EXECUTE_IF_SET_IN_REG_SET (bb[j]->global_live_at_start, 0, regno, | |
6757 | { | |
6758 | if (regno < FIRST_PSEUDO_REGISTER) | |
6759 | CLEAR_HARD_REG_BIT (tmp_reg->regs, regno); | |
6760 | }); | |
6761 | ||
87b483a1 | 6762 | /* Loop through the insns in the block. */ |
36a05131 BS |
6763 | for (;;) |
6764 | { | |
6765 | /* Mark any new registers that are created as being unavailable for | |
6766 | allocation. Also see if the CC register used in nested IFs can be | |
6767 | reallocated. */ | |
6768 | if (INSN_P (insn)) | |
6769 | { | |
6770 | rtx pattern; | |
6771 | rtx set; | |
6772 | int skip_nested_if = FALSE; | |
6773 | ||
6774 | for_each_rtx (&PATTERN (insn), frv_clear_registers_used, | |
6775 | (void *)&tmp_reg->regs); | |
6776 | ||
6777 | pattern = PATTERN (insn); | |
6778 | if (GET_CODE (pattern) == COND_EXEC) | |
6779 | { | |
6780 | rtx reg = XEXP (COND_EXEC_TEST (pattern), 0); | |
6781 | ||
6782 | if (reg != sub_cond_exec_reg) | |
6783 | { | |
6784 | sub_cond_exec_reg = reg; | |
6785 | frv_ifcvt.num_nested_cond_exec++; | |
6786 | } | |
6787 | } | |
6788 | ||
6789 | set = single_set_pattern (pattern); | |
6790 | if (set) | |
6791 | { | |
6792 | rtx dest = SET_DEST (set); | |
6793 | rtx src = SET_SRC (set); | |
6794 | ||
6795 | if (GET_CODE (dest) == REG) | |
6796 | { | |
6797 | int regno = REGNO (dest); | |
6798 | enum rtx_code src_code = GET_CODE (src); | |
6799 | ||
6800 | if (CC_P (regno) && src_code == COMPARE) | |
6801 | skip_nested_if = TRUE; | |
6802 | ||
6803 | else if (CR_P (regno) | |
6804 | && (src_code == IF_THEN_ELSE | |
ec8e098d | 6805 | || COMPARISON_P (src))) |
36a05131 BS |
6806 | skip_nested_if = TRUE; |
6807 | } | |
6808 | } | |
6809 | ||
6810 | if (! skip_nested_if) | |
6811 | for_each_rtx (&PATTERN (insn), frv_clear_registers_used, | |
6812 | (void *)&frv_ifcvt.nested_cc_ok_rewrite); | |
6813 | } | |
6814 | ||
6815 | if (insn == last_insn) | |
6816 | break; | |
6817 | ||
6818 | insn = NEXT_INSN (insn); | |
6819 | } | |
6820 | } | |
6821 | ||
6822 | /* If this is a nested if, rewrite the CC registers that are available to | |
6823 | include the ones that can be rewritten, to increase the chance of being | |
6824 | able to allocate a paired CC/CR register combination. */ | |
6825 | if (ce_info->pass > 1) | |
6826 | { | |
6827 | for (j = CC_FIRST; j <= CC_LAST; j++) | |
6828 | if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j)) | |
6829 | SET_HARD_REG_BIT (tmp_reg->regs, j); | |
6830 | else | |
6831 | CLEAR_HARD_REG_BIT (tmp_reg->regs, j); | |
6832 | } | |
6833 | ||
c263766c | 6834 | if (dump_file) |
36a05131 BS |
6835 | { |
6836 | int num_gprs = 0; | |
c263766c | 6837 | fprintf (dump_file, "Available GPRs: "); |
36a05131 BS |
6838 | |
6839 | for (j = GPR_FIRST; j <= GPR_LAST; j++) | |
6840 | if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) | |
6841 | { | |
c263766c | 6842 | fprintf (dump_file, " %d [%s]", j, reg_names[j]); |
36a05131 BS |
6843 | if (++num_gprs > GPR_TEMP_NUM+2) |
6844 | break; | |
6845 | } | |
6846 | ||
c263766c | 6847 | fprintf (dump_file, "%s\nAvailable CRs: ", |
36a05131 BS |
6848 | (num_gprs > GPR_TEMP_NUM+2) ? " ..." : ""); |
6849 | ||
6850 | for (j = CR_FIRST; j <= CR_LAST; j++) | |
6851 | if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) | |
c263766c | 6852 | fprintf (dump_file, " %d [%s]", j, reg_names[j]); |
36a05131 | 6853 | |
c263766c | 6854 | fputs ("\n", dump_file); |
36a05131 BS |
6855 | |
6856 | if (ce_info->pass > 1) | |
6857 | { | |
c263766c | 6858 | fprintf (dump_file, "Modifiable CCs: "); |
36a05131 BS |
6859 | for (j = CC_FIRST; j <= CC_LAST; j++) |
6860 | if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) | |
c263766c | 6861 | fprintf (dump_file, " %d [%s]", j, reg_names[j]); |
36a05131 | 6862 | |
c263766c | 6863 | fprintf (dump_file, "\n%d nested COND_EXEC statements\n", |
36a05131 BS |
6864 | frv_ifcvt.num_nested_cond_exec); |
6865 | } | |
6866 | } | |
6867 | ||
6868 | /* Allocate the appropriate temporary condition code register. Try to | |
6869 | allocate the ICR/FCR register that corresponds to the ICC/FCC register so | |
6870 | that conditional cmp's can be done. */ | |
6871 | if (mode == CCmode || mode == CC_UNSmode) | |
6872 | { | |
6873 | cr_class = ICR_REGS; | |
6874 | cc_class = ICC_REGS; | |
6875 | cc_first = ICC_FIRST; | |
6876 | cc_last = ICC_LAST; | |
6877 | } | |
6878 | else if (mode == CC_FPmode) | |
6879 | { | |
6880 | cr_class = FCR_REGS; | |
6881 | cc_class = FCC_REGS; | |
6882 | cc_first = FCC_FIRST; | |
6883 | cc_last = FCC_LAST; | |
6884 | } | |
6885 | else | |
6886 | { | |
6887 | cc_first = cc_last = 0; | |
6888 | cr_class = cc_class = NO_REGS; | |
6889 | } | |
6890 | ||
6891 | cc = XEXP (true_expr, 0); | |
6892 | nested_cc = cr = NULL_RTX; | |
6893 | if (cc_class != NO_REGS) | |
6894 | { | |
6895 | /* For nested IFs and &&/||, see if we can find a CC and CR register pair | |
6896 | so we can execute a csubcc/caddcc/cfcmps instruction. */ | |
6897 | int cc_regno; | |
6898 | ||
6899 | for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++) | |
6900 | { | |
6901 | int cr_regno = cc_regno - CC_FIRST + CR_FIRST; | |
6902 | ||
6903 | if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno) | |
6904 | && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno)) | |
6905 | { | |
6906 | frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno; | |
6907 | cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE, | |
6908 | TRUE); | |
6909 | ||
6910 | frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno; | |
6911 | nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode, | |
6912 | TRUE, TRUE); | |
6913 | break; | |
6914 | } | |
6915 | } | |
6916 | } | |
6917 | ||
6918 | if (! cr) | |
6919 | { | |
c263766c RH |
6920 | if (dump_file) |
6921 | fprintf (dump_file, "Could not allocate a CR temporary register\n"); | |
36a05131 BS |
6922 | |
6923 | goto fail; | |
6924 | } | |
6925 | ||
c263766c RH |
6926 | if (dump_file) |
6927 | fprintf (dump_file, | |
36a05131 BS |
6928 | "Will use %s for conditional execution, %s for nested comparisons\n", |
6929 | reg_names[ REGNO (cr)], | |
6930 | (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>"); | |
6931 | ||
6932 | /* Set the CCR bit. Note for integer tests, we reverse the condition so that | |
6933 | in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR | |
6934 | bit being true. We don't do this for floating point, because of NaNs. */ | |
6935 | code = GET_CODE (true_expr); | |
6936 | if (GET_MODE (cc) != CC_FPmode) | |
6937 | { | |
6938 | code = reverse_condition (code); | |
6939 | code_true = EQ; | |
6940 | code_false = NE; | |
6941 | } | |
6942 | else | |
6943 | { | |
6944 | code_true = NE; | |
6945 | code_false = EQ; | |
6946 | } | |
6947 | ||
6948 | check_insn = gen_rtx_SET (VOIDmode, cr, | |
6949 | gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx)); | |
6950 | ||
6951 | /* Record the check insn to be inserted later. */ | |
a813c111 | 6952 | frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE); |
36a05131 BS |
6953 | |
6954 | /* Update the tests. */ | |
6955 | frv_ifcvt.cr_reg = cr; | |
6956 | frv_ifcvt.nested_cc_reg = nested_cc; | |
6957 | *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx); | |
6958 | *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx); | |
6959 | return; | |
6960 | ||
6961 | /* Fail, don't do this conditional execution. */ | |
6962 | fail: | |
6963 | *p_true = NULL_RTX; | |
6964 | *p_false = NULL_RTX; | |
c263766c RH |
6965 | if (dump_file) |
6966 | fprintf (dump_file, "Disabling this conditional execution.\n"); | |
36a05131 BS |
6967 | |
6968 | return; | |
6969 | } | |
6970 | ||
6971 | \f | |
6972 | /* A C expression to modify the code described by the conditional if | |
6973 | information CE_INFO, for the basic block BB, possibly updating the tests in | |
6974 | TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or | |
6975 | if-then-else code to conditional instructions. Set either TRUE_EXPR or | |
6976 | FALSE_EXPR to a null pointer if the tests cannot be converted. */ | |
6977 | ||
6978 | /* p_true and p_false are given expressions of the form: | |
6979 | ||
6980 | (and (eq:CC_CCR (reg:CC_CCR) | |
6981 | (const_int 0)) | |
6982 | (eq:CC (reg:CC) | |
6983 | (const_int 0))) */ | |
6984 | ||
6985 | void | |
f2206911 KC |
6986 | frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info, |
6987 | basic_block bb, | |
6988 | rtx *p_true, | |
6989 | rtx *p_false) | |
36a05131 BS |
6990 | { |
6991 | rtx old_true = XEXP (*p_true, 0); | |
6992 | rtx old_false = XEXP (*p_false, 0); | |
6993 | rtx true_expr = XEXP (*p_true, 1); | |
6994 | rtx false_expr = XEXP (*p_false, 1); | |
6995 | rtx test_expr; | |
6996 | rtx old_test; | |
6997 | rtx cr = XEXP (old_true, 0); | |
6998 | rtx check_insn; | |
6999 | rtx new_cr = NULL_RTX; | |
7000 | rtx *p_new_cr = (rtx *)0; | |
7001 | rtx if_else; | |
7002 | rtx compare; | |
7003 | rtx cc; | |
7004 | enum reg_class cr_class; | |
7005 | enum machine_mode mode = GET_MODE (true_expr); | |
7006 | rtx (*logical_func)(rtx, rtx, rtx); | |
7007 | ||
7008 | if (TARGET_DEBUG_COND_EXEC) | |
7009 | { | |
7010 | fprintf (stderr, | |
7011 | "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n", | |
7012 | ce_info->and_and_p ? "&&" : "||"); | |
7013 | ||
7014 | debug_rtx (*p_true); | |
7015 | ||
7016 | fputs ("\nfalse insn:\n", stderr); | |
7017 | debug_rtx (*p_false); | |
7018 | } | |
7019 | ||
7020 | if (TARGET_NO_MULTI_CE) | |
7021 | goto fail; | |
7022 | ||
7023 | if (GET_CODE (cr) != REG) | |
7024 | goto fail; | |
b16c1435 | 7025 | |
36a05131 BS |
7026 | if (mode == CCmode || mode == CC_UNSmode) |
7027 | { | |
7028 | cr_class = ICR_REGS; | |
7029 | p_new_cr = &frv_ifcvt.extra_int_cr; | |
7030 | } | |
7031 | else if (mode == CC_FPmode) | |
7032 | { | |
7033 | cr_class = FCR_REGS; | |
7034 | p_new_cr = &frv_ifcvt.extra_fp_cr; | |
7035 | } | |
7036 | else | |
7037 | goto fail; | |
7038 | ||
7039 | /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or | |
7040 | more &&/|| tests. */ | |
7041 | new_cr = *p_new_cr; | |
7042 | if (! new_cr) | |
7043 | { | |
7044 | new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class, | |
7045 | CC_CCRmode, TRUE, TRUE); | |
7046 | if (! new_cr) | |
7047 | goto fail; | |
7048 | } | |
7049 | ||
7050 | if (ce_info->and_and_p) | |
7051 | { | |
7052 | old_test = old_false; | |
7053 | test_expr = true_expr; | |
7054 | logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr; | |
7055 | *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx); | |
7056 | *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx); | |
7057 | } | |
7058 | else | |
7059 | { | |
7060 | old_test = old_false; | |
7061 | test_expr = false_expr; | |
7062 | logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr; | |
7063 | *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx); | |
7064 | *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx); | |
7065 | } | |
7066 | ||
7067 | /* First add the andcr/andncr/orcr/orncr, which will be added after the | |
7068 | conditional check instruction, due to frv_ifcvt_add_insn being a LIFO | |
7069 | stack. */ | |
a813c111 | 7070 | frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE); |
36a05131 BS |
7071 | |
7072 | /* Now add the conditional check insn. */ | |
7073 | cc = XEXP (test_expr, 0); | |
7074 | compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx); | |
7075 | if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx); | |
7076 | ||
7077 | check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else); | |
7078 | ||
87b483a1 | 7079 | /* Add the new check insn to the list of check insns that need to be |
36a05131 | 7080 | inserted. */ |
a813c111 | 7081 | frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE); |
36a05131 BS |
7082 | |
7083 | if (TARGET_DEBUG_COND_EXEC) | |
7084 | { | |
7085 | fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n", | |
7086 | stderr); | |
7087 | ||
7088 | debug_rtx (*p_true); | |
7089 | ||
7090 | fputs ("\nfalse insn:\n", stderr); | |
7091 | debug_rtx (*p_false); | |
7092 | } | |
7093 | ||
7094 | return; | |
7095 | ||
7096 | fail: | |
7097 | *p_true = *p_false = NULL_RTX; | |
7098 | ||
87b483a1 | 7099 | /* If we allocated a CR register, release it. */ |
36a05131 BS |
7100 | if (new_cr) |
7101 | { | |
7102 | CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr)); | |
7103 | *p_new_cr = NULL_RTX; | |
7104 | } | |
7105 | ||
7106 | if (TARGET_DEBUG_COND_EXEC) | |
7107 | fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr); | |
7108 | ||
7109 | return; | |
7110 | } | |
7111 | ||
7112 | \f | |
7113 | /* Return a register which will be loaded with a value if an IF block is | |
7114 | converted to conditional execution. This is used to rewrite instructions | |
7115 | that use constants to ones that just use registers. */ | |
7116 | ||
7117 | static rtx | |
f2206911 | 7118 | frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED) |
36a05131 BS |
7119 | { |
7120 | int num_alloc = frv_ifcvt.cur_scratch_regs; | |
7121 | int i; | |
7122 | rtx reg; | |
7123 | ||
7124 | /* We know gr0 == 0, so replace any errant uses. */ | |
7125 | if (value == const0_rtx) | |
7126 | return gen_rtx_REG (SImode, GPR_FIRST); | |
7127 | ||
7128 | /* First search all registers currently loaded to see if we have an | |
7129 | applicable constant. */ | |
7130 | if (CONSTANT_P (value) | |
7131 | || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)) | |
7132 | { | |
7133 | for (i = 0; i < num_alloc; i++) | |
7134 | { | |
7135 | if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value)) | |
7136 | return SET_DEST (frv_ifcvt.scratch_regs[i]); | |
7137 | } | |
7138 | } | |
7139 | ||
87b483a1 | 7140 | /* Have we exhausted the number of registers available? */ |
36a05131 BS |
7141 | if (num_alloc >= GPR_TEMP_NUM) |
7142 | { | |
c263766c RH |
7143 | if (dump_file) |
7144 | fprintf (dump_file, "Too many temporary registers allocated\n"); | |
36a05131 BS |
7145 | |
7146 | return NULL_RTX; | |
7147 | } | |
7148 | ||
7149 | /* Allocate the new register. */ | |
7150 | reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE); | |
7151 | if (! reg) | |
7152 | { | |
c263766c RH |
7153 | if (dump_file) |
7154 | fputs ("Could not find a scratch register\n", dump_file); | |
36a05131 BS |
7155 | |
7156 | return NULL_RTX; | |
7157 | } | |
7158 | ||
7159 | frv_ifcvt.cur_scratch_regs++; | |
7160 | frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value); | |
7161 | ||
c263766c | 7162 | if (dump_file) |
36a05131 BS |
7163 | { |
7164 | if (GET_CODE (value) == CONST_INT) | |
c263766c | 7165 | fprintf (dump_file, "Register %s will hold %ld\n", |
36a05131 BS |
7166 | reg_names[ REGNO (reg)], (long)INTVAL (value)); |
7167 | ||
7168 | else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO) | |
c263766c | 7169 | fprintf (dump_file, "Register %s will hold LR\n", |
36a05131 BS |
7170 | reg_names[ REGNO (reg)]); |
7171 | ||
7172 | else | |
c263766c | 7173 | fprintf (dump_file, "Register %s will hold a saved value\n", |
36a05131 BS |
7174 | reg_names[ REGNO (reg)]); |
7175 | } | |
7176 | ||
7177 | return reg; | |
7178 | } | |
7179 | ||
7180 | \f | |
7181 | /* Update a MEM used in conditional code that might contain an offset to put | |
7182 | the offset into a scratch register, so that the conditional load/store | |
7183 | operations can be used. This function returns the original pointer if the | |
7184 | MEM is valid to use in conditional code, NULL if we can't load up the offset | |
7185 | into a temporary register, or the new MEM if we were successful. */ | |
7186 | ||
7187 | static rtx | |
f2206911 | 7188 | frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn) |
36a05131 BS |
7189 | { |
7190 | rtx addr = XEXP (mem, 0); | |
7191 | ||
34208acf | 7192 | if (!frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE)) |
36a05131 BS |
7193 | { |
7194 | if (GET_CODE (addr) == PLUS) | |
7195 | { | |
7196 | rtx addr_op0 = XEXP (addr, 0); | |
7197 | rtx addr_op1 = XEXP (addr, 1); | |
7198 | ||
34208acf | 7199 | if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1)) |
36a05131 BS |
7200 | { |
7201 | rtx reg = frv_ifcvt_load_value (addr_op1, insn); | |
7202 | if (!reg) | |
7203 | return NULL_RTX; | |
7204 | ||
7205 | addr = gen_rtx_PLUS (Pmode, addr_op0, reg); | |
7206 | } | |
7207 | ||
7208 | else | |
7209 | return NULL_RTX; | |
7210 | } | |
7211 | ||
7212 | else if (CONSTANT_P (addr)) | |
7213 | addr = frv_ifcvt_load_value (addr, insn); | |
7214 | ||
7215 | else | |
7216 | return NULL_RTX; | |
7217 | ||
7218 | if (addr == NULL_RTX) | |
7219 | return NULL_RTX; | |
7220 | ||
7221 | else if (XEXP (mem, 0) != addr) | |
7222 | return change_address (mem, mode, addr); | |
7223 | } | |
7224 | ||
7225 | return mem; | |
7226 | } | |
7227 | ||
7228 | \f | |
7229 | /* Given a PATTERN, return a SET expression if this PATTERN has only a single | |
7230 | SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */ | |
7231 | ||
7232 | static rtx | |
f2206911 | 7233 | single_set_pattern (rtx pattern) |
36a05131 BS |
7234 | { |
7235 | rtx set; | |
7236 | int i; | |
7237 | ||
7238 | if (GET_CODE (pattern) == COND_EXEC) | |
7239 | pattern = COND_EXEC_CODE (pattern); | |
7240 | ||
7241 | if (GET_CODE (pattern) == SET) | |
7242 | return pattern; | |
7243 | ||
7244 | else if (GET_CODE (pattern) == PARALLEL) | |
7245 | { | |
7246 | for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++) | |
7247 | { | |
7248 | rtx sub = XVECEXP (pattern, 0, i); | |
7249 | ||
7250 | switch (GET_CODE (sub)) | |
7251 | { | |
7252 | case USE: | |
7253 | case CLOBBER: | |
7254 | break; | |
7255 | ||
7256 | case SET: | |
7257 | if (set) | |
7258 | return 0; | |
7259 | else | |
7260 | set = sub; | |
7261 | break; | |
7262 | ||
7263 | default: | |
7264 | return 0; | |
7265 | } | |
7266 | } | |
7267 | return set; | |
7268 | } | |
7269 | ||
7270 | return 0; | |
7271 | } | |
7272 | ||
7273 | \f | |
7274 | /* A C expression to modify the code described by the conditional if | |
7275 | information CE_INFO with the new PATTERN in INSN. If PATTERN is a null | |
7276 | pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that | |
7277 | insn cannot be converted to be executed conditionally. */ | |
7278 | ||
7279 | rtx | |
5da1fd3d | 7280 | frv_ifcvt_modify_insn (ce_if_block_t *ce_info, |
f2206911 KC |
7281 | rtx pattern, |
7282 | rtx insn) | |
36a05131 BS |
7283 | { |
7284 | rtx orig_ce_pattern = pattern; | |
7285 | rtx set; | |
7286 | rtx op0; | |
7287 | rtx op1; | |
7288 | rtx test; | |
7289 | ||
7290 | if (GET_CODE (pattern) != COND_EXEC) | |
7291 | abort (); | |
7292 | ||
7293 | test = COND_EXEC_TEST (pattern); | |
7294 | if (GET_CODE (test) == AND) | |
7295 | { | |
7296 | rtx cr = frv_ifcvt.cr_reg; | |
7297 | rtx test_reg; | |
7298 | ||
7299 | op0 = XEXP (test, 0); | |
7300 | if (! rtx_equal_p (cr, XEXP (op0, 0))) | |
7301 | goto fail; | |
7302 | ||
7303 | op1 = XEXP (test, 1); | |
7304 | test_reg = XEXP (op1, 0); | |
7305 | if (GET_CODE (test_reg) != REG) | |
7306 | goto fail; | |
7307 | ||
7308 | /* Is this the first nested if block in this sequence? If so, generate | |
7309 | an andcr or andncr. */ | |
7310 | if (! frv_ifcvt.last_nested_if_cr) | |
7311 | { | |
7312 | rtx and_op; | |
7313 | ||
7314 | frv_ifcvt.last_nested_if_cr = test_reg; | |
7315 | if (GET_CODE (op0) == NE) | |
7316 | and_op = gen_andcr (test_reg, cr, test_reg); | |
7317 | else | |
7318 | and_op = gen_andncr (test_reg, cr, test_reg); | |
7319 | ||
7320 | frv_ifcvt_add_insn (and_op, insn, TRUE); | |
7321 | } | |
7322 | ||
7323 | /* If this isn't the first statement in the nested if sequence, see if we | |
7324 | are dealing with the same register. */ | |
7325 | else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr)) | |
7326 | goto fail; | |
7327 | ||
7328 | COND_EXEC_TEST (pattern) = test = op1; | |
7329 | } | |
7330 | ||
7331 | /* If this isn't a nested if, reset state variables. */ | |
7332 | else | |
7333 | { | |
7334 | frv_ifcvt.last_nested_if_cr = NULL_RTX; | |
7335 | } | |
7336 | ||
7337 | set = single_set_pattern (pattern); | |
7338 | if (set) | |
7339 | { | |
7340 | rtx dest = SET_DEST (set); | |
7341 | rtx src = SET_SRC (set); | |
7342 | enum machine_mode mode = GET_MODE (dest); | |
7343 | ||
87b483a1 | 7344 | /* Check for normal binary operators. */ |
ec8e098d | 7345 | if (mode == SImode && ARITHMETIC_P (src)) |
36a05131 BS |
7346 | { |
7347 | op0 = XEXP (src, 0); | |
7348 | op1 = XEXP (src, 1); | |
7349 | ||
34208acf | 7350 | if (integer_register_operand (op0, SImode) && CONSTANT_P (op1)) |
36a05131 BS |
7351 | { |
7352 | op1 = frv_ifcvt_load_value (op1, insn); | |
7353 | if (op1) | |
7354 | COND_EXEC_CODE (pattern) | |
7355 | = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src), | |
7356 | GET_MODE (src), | |
7357 | op0, op1)); | |
7358 | else | |
7359 | goto fail; | |
7360 | } | |
7361 | } | |
7362 | ||
7363 | /* For multiply by a constant, we need to handle the sign extending | |
7364 | correctly. Add a USE of the value after the multiply to prevent flow | |
7365 | from cratering because only one register out of the two were used. */ | |
7366 | else if (mode == DImode && GET_CODE (src) == MULT) | |
7367 | { | |
7368 | op0 = XEXP (src, 0); | |
7369 | op1 = XEXP (src, 1); | |
7370 | if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT) | |
7371 | { | |
7372 | op1 = frv_ifcvt_load_value (op1, insn); | |
7373 | if (op1) | |
7374 | { | |
7375 | op1 = gen_rtx_SIGN_EXTEND (DImode, op1); | |
7376 | COND_EXEC_CODE (pattern) | |
7377 | = gen_rtx_SET (VOIDmode, dest, | |
7378 | gen_rtx_MULT (DImode, op0, op1)); | |
7379 | } | |
7380 | else | |
7381 | goto fail; | |
7382 | } | |
7383 | ||
7384 | frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode, dest), insn, FALSE); | |
7385 | } | |
7386 | ||
7387 | /* If we are just loading a constant created for a nested conditional | |
7388 | execution statement, just load the constant without any conditional | |
7389 | execution, since we know that the constant will not interfere with any | |
7390 | other registers. */ | |
7391 | else if (frv_ifcvt.scratch_insns_bitmap | |
7392 | && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap, | |
5da1fd3d AO |
7393 | INSN_UID (insn)) |
7394 | /* We must not unconditionally set a reg set used as | |
7395 | scratch in the THEN branch if the same reg is live | |
7396 | in the ELSE branch. */ | |
7397 | && REG_P (SET_DEST (set)) | |
7398 | && (! ce_info->else_bb | |
7399 | || BLOCK_FOR_INSN (insn) == ce_info->else_bb | |
7400 | || ! (REGNO_REG_SET_P | |
7401 | (ce_info->else_bb->global_live_at_start, | |
7402 | REGNO (SET_DEST (set)))))) | |
36a05131 BS |
7403 | pattern = set; |
7404 | ||
7405 | else if (mode == QImode || mode == HImode || mode == SImode | |
7406 | || mode == SFmode) | |
7407 | { | |
7408 | int changed_p = FALSE; | |
7409 | ||
7410 | /* Check for just loading up a constant */ | |
7411 | if (CONSTANT_P (src) && integer_register_operand (dest, mode)) | |
7412 | { | |
7413 | src = frv_ifcvt_load_value (src, insn); | |
7414 | if (!src) | |
7415 | goto fail; | |
7416 | ||
7417 | changed_p = TRUE; | |
7418 | } | |
7419 | ||
7420 | /* See if we need to fix up stores */ | |
7421 | if (GET_CODE (dest) == MEM) | |
7422 | { | |
7423 | rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn); | |
7424 | ||
7425 | if (!new_mem) | |
7426 | goto fail; | |
7427 | ||
7428 | else if (new_mem != dest) | |
7429 | { | |
7430 | changed_p = TRUE; | |
7431 | dest = new_mem; | |
7432 | } | |
7433 | } | |
7434 | ||
7435 | /* See if we need to fix up loads */ | |
7436 | if (GET_CODE (src) == MEM) | |
7437 | { | |
7438 | rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn); | |
7439 | ||
7440 | if (!new_mem) | |
7441 | goto fail; | |
7442 | ||
7443 | else if (new_mem != src) | |
7444 | { | |
7445 | changed_p = TRUE; | |
7446 | src = new_mem; | |
7447 | } | |
7448 | } | |
7449 | ||
7450 | /* If either src or destination changed, redo SET. */ | |
7451 | if (changed_p) | |
7452 | COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src); | |
7453 | } | |
7454 | ||
7455 | /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with | |
7456 | rewriting the CC register to be the same as the paired CC/CR register | |
7457 | for nested ifs. */ | |
ec8e098d | 7458 | else if (mode == CC_CCRmode && COMPARISON_P (src)) |
36a05131 BS |
7459 | { |
7460 | int regno = REGNO (XEXP (src, 0)); | |
7461 | rtx if_else; | |
7462 | ||
7463 | if (ce_info->pass > 1 | |
7464 | && regno != (int)REGNO (frv_ifcvt.nested_cc_reg) | |
7465 | && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno)) | |
7466 | { | |
7467 | src = gen_rtx_fmt_ee (GET_CODE (src), | |
7468 | CC_CCRmode, | |
7469 | frv_ifcvt.nested_cc_reg, | |
7470 | XEXP (src, 1)); | |
7471 | } | |
7472 | ||
7473 | if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx); | |
7474 | pattern = gen_rtx_SET (VOIDmode, dest, if_else); | |
7475 | } | |
7476 | ||
7477 | /* Remap a nested compare instruction to use the paired CC/CR reg. */ | |
7478 | else if (ce_info->pass > 1 | |
7479 | && GET_CODE (dest) == REG | |
7480 | && CC_P (REGNO (dest)) | |
7481 | && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg) | |
7482 | && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, | |
7483 | REGNO (dest)) | |
7484 | && GET_CODE (src) == COMPARE) | |
7485 | { | |
7486 | PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest)); | |
7487 | COND_EXEC_CODE (pattern) | |
7488 | = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src)); | |
7489 | } | |
7490 | } | |
7491 | ||
7492 | if (TARGET_DEBUG_COND_EXEC) | |
7493 | { | |
7494 | rtx orig_pattern = PATTERN (insn); | |
7495 | ||
7496 | PATTERN (insn) = pattern; | |
7497 | fprintf (stderr, | |
7498 | "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n", | |
7499 | ce_info->pass); | |
7500 | ||
7501 | debug_rtx (insn); | |
7502 | PATTERN (insn) = orig_pattern; | |
7503 | } | |
7504 | ||
7505 | return pattern; | |
7506 | ||
7507 | fail: | |
7508 | if (TARGET_DEBUG_COND_EXEC) | |
7509 | { | |
7510 | rtx orig_pattern = PATTERN (insn); | |
7511 | ||
7512 | PATTERN (insn) = orig_ce_pattern; | |
7513 | fprintf (stderr, | |
7514 | "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n", | |
7515 | ce_info->pass); | |
7516 | ||
7517 | debug_rtx (insn); | |
7518 | PATTERN (insn) = orig_pattern; | |
7519 | } | |
7520 | ||
7521 | return NULL_RTX; | |
7522 | } | |
7523 | ||
7524 | \f | |
7525 | /* A C expression to perform any final machine dependent modifications in | |
7526 | converting code to conditional execution in the code described by the | |
7527 | conditional if information CE_INFO. */ | |
7528 | ||
7529 | void | |
f2206911 | 7530 | frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED) |
36a05131 BS |
7531 | { |
7532 | rtx existing_insn; | |
7533 | rtx check_insn; | |
7534 | rtx p = frv_ifcvt.added_insns_list; | |
7535 | int i; | |
7536 | ||
7537 | /* Loop inserting the check insns. The last check insn is the first test, | |
7538 | and is the appropriate place to insert constants. */ | |
7539 | if (! p) | |
7540 | abort (); | |
7541 | ||
7542 | do | |
7543 | { | |
7544 | rtx check_and_insert_insns = XEXP (p, 0); | |
7545 | rtx old_p = p; | |
7546 | ||
7547 | check_insn = XEXP (check_and_insert_insns, 0); | |
7548 | existing_insn = XEXP (check_and_insert_insns, 1); | |
7549 | p = XEXP (p, 1); | |
7550 | ||
7551 | /* The jump bit is used to say that the new insn is to be inserted BEFORE | |
7552 | the existing insn, otherwise it is to be inserted AFTER. */ | |
7553 | if (check_and_insert_insns->jump) | |
7554 | { | |
7555 | emit_insn_before (check_insn, existing_insn); | |
7556 | check_and_insert_insns->jump = 0; | |
7557 | } | |
7558 | else | |
7559 | emit_insn_after (check_insn, existing_insn); | |
7560 | ||
7561 | free_EXPR_LIST_node (check_and_insert_insns); | |
7562 | free_EXPR_LIST_node (old_p); | |
7563 | } | |
7564 | while (p != NULL_RTX); | |
7565 | ||
7566 | /* Load up any constants needed into temp gprs */ | |
7567 | for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++) | |
7568 | { | |
7569 | rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn); | |
7570 | if (! frv_ifcvt.scratch_insns_bitmap) | |
7571 | frv_ifcvt.scratch_insns_bitmap = BITMAP_XMALLOC (); | |
7572 | bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn)); | |
7573 | frv_ifcvt.scratch_regs[i] = NULL_RTX; | |
7574 | } | |
7575 | ||
7576 | frv_ifcvt.added_insns_list = NULL_RTX; | |
7577 | frv_ifcvt.cur_scratch_regs = 0; | |
7578 | } | |
7579 | ||
7580 | \f | |
7581 | /* A C expression to cancel any machine dependent modifications in converting | |
7582 | code to conditional execution in the code described by the conditional if | |
7583 | information CE_INFO. */ | |
7584 | ||
7585 | void | |
f2206911 | 7586 | frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED) |
36a05131 BS |
7587 | { |
7588 | int i; | |
7589 | rtx p = frv_ifcvt.added_insns_list; | |
7590 | ||
7591 | /* Loop freeing up the EXPR_LIST's allocated. */ | |
7592 | while (p != NULL_RTX) | |
7593 | { | |
7594 | rtx check_and_jump = XEXP (p, 0); | |
7595 | rtx old_p = p; | |
7596 | ||
7597 | p = XEXP (p, 1); | |
7598 | free_EXPR_LIST_node (check_and_jump); | |
7599 | free_EXPR_LIST_node (old_p); | |
7600 | } | |
7601 | ||
7602 | /* Release any temporary gprs allocated. */ | |
7603 | for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++) | |
7604 | frv_ifcvt.scratch_regs[i] = NULL_RTX; | |
7605 | ||
7606 | frv_ifcvt.added_insns_list = NULL_RTX; | |
7607 | frv_ifcvt.cur_scratch_regs = 0; | |
7608 | return; | |
7609 | } | |
7610 | \f | |
7611 | /* A C expression for the size in bytes of the trampoline, as an integer. | |
7612 | The template is: | |
7613 | ||
7614 | setlo #0, <jmp_reg> | |
7615 | setlo #0, <static_chain> | |
7616 | sethi #0, <jmp_reg> | |
7617 | sethi #0, <static_chain> | |
7618 | jmpl @(gr0,<jmp_reg>) */ | |
7619 | ||
7620 | int | |
f2206911 | 7621 | frv_trampoline_size (void) |
36a05131 | 7622 | { |
34208acf AO |
7623 | if (TARGET_FDPIC) |
7624 | /* Allocate room for the function descriptor and the lddi | |
7625 | instruction. */ | |
7626 | return 8 + 6 * 4; | |
7627 | return 5 /* instructions */ * 4 /* instruction size. */; | |
36a05131 BS |
7628 | } |
7629 | ||
7630 | \f | |
7631 | /* A C statement to initialize the variable parts of a trampoline. ADDR is an | |
7632 | RTX for the address of the trampoline; FNADDR is an RTX for the address of | |
7633 | the nested function; STATIC_CHAIN is an RTX for the static chain value that | |
7634 | should be passed to the function when it is called. | |
7635 | ||
7636 | The template is: | |
7637 | ||
7638 | setlo #0, <jmp_reg> | |
7639 | setlo #0, <static_chain> | |
7640 | sethi #0, <jmp_reg> | |
7641 | sethi #0, <static_chain> | |
7642 | jmpl @(gr0,<jmp_reg>) */ | |
7643 | ||
7644 | void | |
f2206911 | 7645 | frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain) |
36a05131 BS |
7646 | { |
7647 | rtx sc_reg = force_reg (Pmode, static_chain); | |
7648 | ||
7649 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), | |
7650 | FALSE, VOIDmode, 4, | |
7651 | addr, Pmode, | |
7652 | GEN_INT (frv_trampoline_size ()), SImode, | |
7653 | fnaddr, Pmode, | |
7654 | sc_reg, Pmode); | |
7655 | } | |
7656 | ||
7657 | \f | |
7658 | /* Many machines have some registers that cannot be copied directly to or from | |
7659 | memory or even from other types of registers. An example is the `MQ' | |
7660 | register, which on most machines, can only be copied to or from general | |
7661 | registers, but not memory. Some machines allow copying all registers to and | |
7662 | from memory, but require a scratch register for stores to some memory | |
7663 | locations (e.g., those with symbolic address on the RT, and those with | |
981f6289 | 7664 | certain symbolic address on the SPARC when compiling PIC). In some cases, |
36a05131 BS |
7665 | both an intermediate and a scratch register are required. |
7666 | ||
7667 | You should define these macros to indicate to the reload phase that it may | |
7668 | need to allocate at least one register for a reload in addition to the | |
7669 | register to contain the data. Specifically, if copying X to a register | |
7670 | CLASS in MODE requires an intermediate register, you should define | |
7671 | `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of | |
7672 | whose registers can be used as intermediate registers or scratch registers. | |
7673 | ||
7674 | If copying a register CLASS in MODE to X requires an intermediate or scratch | |
7675 | register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the | |
7676 | largest register class required. If the requirements for input and output | |
7677 | reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used | |
7678 | instead of defining both macros identically. | |
7679 | ||
7680 | The values returned by these macros are often `GENERAL_REGS'. Return | |
7681 | `NO_REGS' if no spare register is needed; i.e., if X can be directly copied | |
7682 | to or from a register of CLASS in MODE without requiring a scratch register. | |
7683 | Do not define this macro if it would always return `NO_REGS'. | |
7684 | ||
7685 | If a scratch register is required (either with or without an intermediate | |
7686 | register), you should define patterns for `reload_inM' or `reload_outM', as | |
7687 | required.. These patterns, which will normally be implemented with a | |
7688 | `define_expand', should be similar to the `movM' patterns, except that | |
7689 | operand 2 is the scratch register. | |
7690 | ||
7691 | Define constraints for the reload register and scratch register that contain | |
7692 | a single register class. If the original reload register (whose class is | |
7693 | CLASS) can meet the constraint given in the pattern, the value returned by | |
7694 | these macros is used for the class of the scratch register. Otherwise, two | |
7695 | additional reload registers are required. Their classes are obtained from | |
7696 | the constraints in the insn pattern. | |
7697 | ||
7698 | X might be a pseudo-register or a `subreg' of a pseudo-register, which could | |
7699 | either be in a hard register or in memory. Use `true_regnum' to find out; | |
7700 | it will return -1 if the pseudo is in memory and the hard register number if | |
7701 | it is in a register. | |
7702 | ||
7703 | These macros should not be used in the case where a particular class of | |
7704 | registers can only be copied to memory and not to another class of | |
7705 | registers. In that case, secondary reload registers are not needed and | |
7706 | would not be helpful. Instead, a stack location must be used to perform the | |
43aa4e05 | 7707 | copy and the `movM' pattern should use memory as an intermediate storage. |
36a05131 BS |
7708 | This case often occurs between floating-point and general registers. */ |
7709 | ||
7710 | enum reg_class | |
f2206911 KC |
7711 | frv_secondary_reload_class (enum reg_class class, |
7712 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
7713 | rtx x, | |
7714 | int in_p ATTRIBUTE_UNUSED) | |
36a05131 BS |
7715 | { |
7716 | enum reg_class ret; | |
7717 | ||
7718 | switch (class) | |
7719 | { | |
7720 | default: | |
7721 | ret = NO_REGS; | |
7722 | break; | |
7723 | ||
7724 | /* Accumulators/Accumulator guard registers need to go through floating | |
7725 | point registers. */ | |
7726 | case QUAD_REGS: | |
7727 | case EVEN_REGS: | |
7728 | case GPR_REGS: | |
7729 | ret = NO_REGS; | |
7730 | if (x && GET_CODE (x) == REG) | |
7731 | { | |
7732 | int regno = REGNO (x); | |
7733 | ||
7734 | if (ACC_P (regno) || ACCG_P (regno)) | |
7735 | ret = FPR_REGS; | |
7736 | } | |
7737 | break; | |
7738 | ||
9cd10576 | 7739 | /* Nonzero constants should be loaded into an FPR through a GPR. */ |
36a05131 BS |
7740 | case QUAD_FPR_REGS: |
7741 | case FEVEN_REGS: | |
7742 | case FPR_REGS: | |
7743 | if (x && CONSTANT_P (x) && !ZERO_P (x)) | |
7744 | ret = GPR_REGS; | |
7745 | else | |
7746 | ret = NO_REGS; | |
7747 | break; | |
7748 | ||
7749 | /* All of these types need gpr registers. */ | |
7750 | case ICC_REGS: | |
7751 | case FCC_REGS: | |
7752 | case CC_REGS: | |
7753 | case ICR_REGS: | |
7754 | case FCR_REGS: | |
7755 | case CR_REGS: | |
7756 | case LCR_REG: | |
7757 | case LR_REG: | |
7758 | ret = GPR_REGS; | |
7759 | break; | |
7760 | ||
7761 | /* The accumulators need fpr registers */ | |
7762 | case ACC_REGS: | |
7763 | case EVEN_ACC_REGS: | |
7764 | case QUAD_ACC_REGS: | |
7765 | case ACCG_REGS: | |
7766 | ret = FPR_REGS; | |
7767 | break; | |
7768 | } | |
7769 | ||
7770 | return ret; | |
7771 | } | |
7772 | ||
7773 | \f | |
7774 | /* A C expression whose value is nonzero if pseudos that have been assigned to | |
7775 | registers of class CLASS would likely be spilled because registers of CLASS | |
7776 | are needed for spill registers. | |
7777 | ||
7778 | The default value of this macro returns 1 if CLASS has exactly one register | |
7779 | and zero otherwise. On most machines, this default should be used. Only | |
7780 | define this macro to some other expression if pseudo allocated by | |
7781 | `local-alloc.c' end up in memory because their hard registers were needed | |
7782 | for spill registers. If this macro returns nonzero for those classes, those | |
7783 | pseudos will only be allocated by `global.c', which knows how to reallocate | |
7784 | the pseudo to another register. If there would not be another register | |
7785 | available for reallocation, you should not change the definition of this | |
7786 | macro since the only effect of such a definition would be to slow down | |
7787 | register allocation. */ | |
7788 | ||
7789 | int | |
f2206911 | 7790 | frv_class_likely_spilled_p (enum reg_class class) |
36a05131 BS |
7791 | { |
7792 | switch (class) | |
7793 | { | |
7794 | default: | |
7795 | break; | |
7796 | ||
7797 | case ICC_REGS: | |
7798 | case FCC_REGS: | |
7799 | case CC_REGS: | |
7800 | case ICR_REGS: | |
7801 | case FCR_REGS: | |
7802 | case CR_REGS: | |
7803 | case LCR_REG: | |
7804 | case LR_REG: | |
7805 | case SPR_REGS: | |
7806 | case QUAD_ACC_REGS: | |
7807 | case EVEN_ACC_REGS: | |
7808 | case ACC_REGS: | |
7809 | case ACCG_REGS: | |
7810 | return TRUE; | |
7811 | } | |
7812 | ||
7813 | return FALSE; | |
7814 | } | |
7815 | ||
7816 | \f | |
7817 | /* An expression for the alignment of a structure field FIELD if the | |
7ec022b2 | 7818 | alignment computed in the usual way is COMPUTED. GCC uses this |
36a05131 BS |
7819 | value instead of the value in `BIGGEST_ALIGNMENT' or |
7820 | `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */ | |
7821 | ||
7822 | /* The definition type of the bit field data is either char, short, long or | |
7823 | long long. The maximum bit size is the number of bits of its own type. | |
7824 | ||
7825 | The bit field data is assigned to a storage unit that has an adequate size | |
7826 | for bit field data retention and is located at the smallest address. | |
7827 | ||
7828 | Consecutive bit field data are packed at consecutive bits having the same | |
7829 | storage unit, with regard to the type, beginning with the MSB and continuing | |
7830 | toward the LSB. | |
7831 | ||
7832 | If a field to be assigned lies over a bit field type boundary, its | |
7833 | assignment is completed by aligning it with a boundary suitable for the | |
7834 | type. | |
7835 | ||
7836 | When a bit field having a bit length of 0 is declared, it is forcibly | |
7837 | assigned to the next storage unit. | |
7838 | ||
7839 | e.g) | |
7840 | struct { | |
7841 | int a:2; | |
7842 | int b:6; | |
7843 | char c:4; | |
7844 | int d:10; | |
7845 | int :0; | |
7846 | int f:2; | |
7847 | } x; | |
7848 | ||
7849 | +0 +1 +2 +3 | |
7850 | &x 00000000 00000000 00000000 00000000 | |
7851 | MLM----L | |
7852 | a b | |
7853 | &x+4 00000000 00000000 00000000 00000000 | |
7854 | M--L | |
7855 | c | |
7856 | &x+8 00000000 00000000 00000000 00000000 | |
7857 | M----------L | |
7858 | d | |
7859 | &x+12 00000000 00000000 00000000 00000000 | |
7860 | ML | |
7861 | f | |
7862 | */ | |
7863 | ||
7864 | int | |
f2206911 | 7865 | frv_adjust_field_align (tree field, int computed) |
36a05131 | 7866 | { |
b16c1435 EC |
7867 | /* Make sure that the bitfield is not wider than the type. */ |
7868 | if (DECL_BIT_FIELD (field) | |
25f93e18 | 7869 | && !DECL_ARTIFICIAL (field)) |
36a05131 BS |
7870 | { |
7871 | tree parent = DECL_CONTEXT (field); | |
7872 | tree prev = NULL_TREE; | |
7873 | tree cur; | |
7874 | ||
36a05131 BS |
7875 | for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur)) |
7876 | { | |
7877 | if (TREE_CODE (cur) != FIELD_DECL) | |
7878 | continue; | |
7879 | ||
7880 | prev = cur; | |
7881 | } | |
7882 | ||
7883 | if (!cur) | |
7884 | abort (); | |
7885 | ||
7886 | /* If this isn't a :0 field and if the previous element is a bitfield | |
7887 | also, see if the type is different, if so, we will need to align the | |
87b483a1 | 7888 | bit-field to the next boundary. */ |
36a05131 BS |
7889 | if (prev |
7890 | && ! DECL_PACKED (field) | |
7891 | && ! integer_zerop (DECL_SIZE (field)) | |
7892 | && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev)) | |
7893 | { | |
7894 | int prev_align = TYPE_ALIGN (TREE_TYPE (prev)); | |
7895 | int cur_align = TYPE_ALIGN (TREE_TYPE (field)); | |
7896 | computed = (prev_align > cur_align) ? prev_align : cur_align; | |
7897 | } | |
7898 | } | |
7899 | ||
7900 | return computed; | |
7901 | } | |
7902 | ||
7903 | \f | |
7904 | /* A C expression that is nonzero if it is permissible to store a value of mode | |
7905 | MODE in hard register number REGNO (or in several registers starting with | |
7906 | that one). For a machine where all registers are equivalent, a suitable | |
7907 | definition is | |
7908 | ||
7909 | #define HARD_REGNO_MODE_OK(REGNO, MODE) 1 | |
7910 | ||
7911 | It is not necessary for this macro to check for the numbers of fixed | |
7912 | registers, because the allocation mechanism considers them to be always | |
7913 | occupied. | |
7914 | ||
7915 | On some machines, double-precision values must be kept in even/odd register | |
7916 | pairs. The way to implement that is to define this macro to reject odd | |
7917 | register numbers for such modes. | |
7918 | ||
7919 | The minimum requirement for a mode to be OK in a register is that the | |
7920 | `movMODE' instruction pattern support moves between the register and any | |
7921 | other hard register for which the mode is OK; and that moving a value into | |
7922 | the register and back out not alter it. | |
7923 | ||
7924 | Since the same instruction used to move `SImode' will work for all narrower | |
7925 | integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK' | |
7926 | to distinguish between these modes, provided you define patterns `movhi', | |
7927 | etc., to take advantage of this. This is useful because of the interaction | |
7928 | between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for | |
7929 | all integer modes to be tieable. | |
7930 | ||
7931 | Many machines have special registers for floating point arithmetic. Often | |
7932 | people assume that floating point machine modes are allowed only in floating | |
7933 | point registers. This is not true. Any registers that can hold integers | |
7934 | can safely *hold* a floating point machine mode, whether or not floating | |
7935 | arithmetic can be done on it in those registers. Integer move instructions | |
7936 | can be used to move the values. | |
7937 | ||
7938 | On some machines, though, the converse is true: fixed-point machine modes | |
7939 | may not go in floating registers. This is true if the floating registers | |
7940 | normalize any value stored in them, because storing a non-floating value | |
7941 | there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject | |
7942 | fixed-point machine modes in floating registers. But if the floating | |
7943 | registers do not automatically normalize, if you can store any bit pattern | |
7944 | in one and retrieve it unchanged without a trap, then any machine mode may | |
7945 | go in a floating register, so you can define this macro to say so. | |
7946 | ||
7947 | The primary significance of special floating registers is rather that they | |
7948 | are the registers acceptable in floating point arithmetic instructions. | |
7949 | However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by | |
7950 | writing the proper constraints for those instructions. | |
7951 | ||
7952 | On some machines, the floating registers are especially slow to access, so | |
7953 | that it is better to store a value in a stack frame than in such a register | |
7954 | if floating point arithmetic is not being done. As long as the floating | |
7955 | registers are not in class `GENERAL_REGS', they will not be used unless some | |
7956 | pattern's constraint asks for one. */ | |
7957 | ||
7958 | int | |
f2206911 | 7959 | frv_hard_regno_mode_ok (int regno, enum machine_mode mode) |
36a05131 BS |
7960 | { |
7961 | int base; | |
7962 | int mask; | |
7963 | ||
7964 | switch (mode) | |
7965 | { | |
7966 | case CCmode: | |
7967 | case CC_UNSmode: | |
7968 | return ICC_P (regno) || GPR_P (regno); | |
7969 | ||
7970 | case CC_CCRmode: | |
7971 | return CR_P (regno) || GPR_P (regno); | |
7972 | ||
7973 | case CC_FPmode: | |
7974 | return FCC_P (regno) || GPR_P (regno); | |
7975 | ||
7976 | default: | |
7977 | break; | |
7978 | } | |
7979 | ||
7980 | /* Set BASE to the first register in REGNO's class. Set MASK to the | |
7981 | bits that must be clear in (REGNO - BASE) for the register to be | |
7982 | well-aligned. */ | |
7983 | if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode)) | |
7984 | { | |
7985 | if (ACCG_P (regno)) | |
7986 | { | |
7987 | /* ACCGs store one byte. Two-byte quantities must start in | |
7988 | even-numbered registers, four-byte ones in registers whose | |
7989 | numbers are divisible by four, and so on. */ | |
7990 | base = ACCG_FIRST; | |
7991 | mask = GET_MODE_SIZE (mode) - 1; | |
7992 | } | |
7993 | else | |
7994 | { | |
b16c1435 EC |
7995 | /* The other registers store one word. */ |
7996 | if (GPR_P (regno) || regno == AP_FIRST) | |
36a05131 BS |
7997 | base = GPR_FIRST; |
7998 | ||
7999 | else if (FPR_P (regno)) | |
8000 | base = FPR_FIRST; | |
8001 | ||
8002 | else if (ACC_P (regno)) | |
8003 | base = ACC_FIRST; | |
8004 | ||
b16c1435 EC |
8005 | else if (SPR_P (regno)) |
8006 | return mode == SImode; | |
8007 | ||
87b483a1 | 8008 | /* Fill in the table. */ |
36a05131 BS |
8009 | else |
8010 | return 0; | |
8011 | ||
8012 | /* Anything smaller than an SI is OK in any word-sized register. */ | |
8013 | if (GET_MODE_SIZE (mode) < 4) | |
8014 | return 1; | |
8015 | ||
8016 | mask = (GET_MODE_SIZE (mode) / 4) - 1; | |
8017 | } | |
8018 | return (((regno - base) & mask) == 0); | |
8019 | } | |
8020 | ||
8021 | return 0; | |
8022 | } | |
8023 | ||
8024 | \f | |
8025 | /* A C expression for the number of consecutive hard registers, starting at | |
8026 | register number REGNO, required to hold a value of mode MODE. | |
8027 | ||
8028 | On a machine where all registers are exactly one word, a suitable definition | |
8029 | of this macro is | |
8030 | ||
8031 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
8032 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \ | |
8033 | / UNITS_PER_WORD)) */ | |
8034 | ||
8035 | /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so | |
8036 | that we can build the appropriate instructions to properly reload the | |
8037 | values. Also, make the byte-sized accumulator guards use one guard | |
8038 | for each byte. */ | |
8039 | ||
8040 | int | |
f2206911 | 8041 | frv_hard_regno_nregs (int regno, enum machine_mode mode) |
36a05131 BS |
8042 | { |
8043 | if (ACCG_P (regno)) | |
8044 | return GET_MODE_SIZE (mode); | |
8045 | else | |
8046 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
8047 | } | |
8048 | ||
8049 | \f | |
8050 | /* A C expression for the maximum number of consecutive registers of | |
8051 | class CLASS needed to hold a value of mode MODE. | |
8052 | ||
8053 | This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value | |
8054 | of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of | |
8055 | `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS. | |
8056 | ||
8057 | This macro helps control the handling of multiple-word values in | |
8058 | the reload pass. | |
8059 | ||
8060 | This declaration is required. */ | |
8061 | ||
8062 | int | |
f2206911 | 8063 | frv_class_max_nregs (enum reg_class class, enum machine_mode mode) |
36a05131 BS |
8064 | { |
8065 | if (class == ACCG_REGS) | |
8066 | /* An N-byte value requires N accumulator guards. */ | |
8067 | return GET_MODE_SIZE (mode); | |
8068 | else | |
8069 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
8070 | } | |
8071 | ||
8072 | \f | |
8073 | /* A C expression that is nonzero if X is a legitimate constant for an | |
8074 | immediate operand on the target machine. You can assume that X satisfies | |
8075 | `CONSTANT_P', so you need not check this. In fact, `1' is a suitable | |
8076 | definition for this macro on machines where anything `CONSTANT_P' is valid. */ | |
8077 | ||
8078 | int | |
f2206911 | 8079 | frv_legitimate_constant_p (rtx x) |
36a05131 BS |
8080 | { |
8081 | enum machine_mode mode = GET_MODE (x); | |
8082 | ||
34208acf AO |
8083 | /* frv_cannot_force_const_mem always returns true for FDPIC. This |
8084 | means that the move expanders will be expected to deal with most | |
8085 | kinds of constant, regardless of what we return here. | |
8086 | ||
8087 | However, among its other duties, LEGITIMATE_CONSTANT_P decides whether | |
8088 | a constant can be entered into reg_equiv_constant[]. If we return true, | |
8089 | reload can create new instances of the constant whenever it likes. | |
8090 | ||
8091 | The idea is therefore to accept as many constants as possible (to give | |
8092 | reload more freedom) while rejecting constants that can only be created | |
8093 | at certain times. In particular, anything with a symbolic component will | |
8094 | require use of the pseudo FDPIC register, which is only available before | |
8095 | reload. */ | |
8096 | if (TARGET_FDPIC) | |
8097 | return LEGITIMATE_PIC_OPERAND_P (x); | |
8098 | ||
87b483a1 | 8099 | /* All of the integer constants are ok. */ |
36a05131 BS |
8100 | if (GET_CODE (x) != CONST_DOUBLE) |
8101 | return TRUE; | |
8102 | ||
87b483a1 | 8103 | /* double integer constants are ok. */ |
36a05131 BS |
8104 | if (mode == VOIDmode || mode == DImode) |
8105 | return TRUE; | |
8106 | ||
87b483a1 | 8107 | /* 0 is always ok. */ |
36a05131 BS |
8108 | if (x == CONST0_RTX (mode)) |
8109 | return TRUE; | |
8110 | ||
8111 | /* If floating point is just emulated, allow any constant, since it will be | |
87b483a1 | 8112 | constructed in the GPRs. */ |
36a05131 BS |
8113 | if (!TARGET_HAS_FPRS) |
8114 | return TRUE; | |
8115 | ||
8116 | if (mode == DFmode && !TARGET_DOUBLE) | |
8117 | return TRUE; | |
8118 | ||
8119 | /* Otherwise store the constant away and do a load. */ | |
8120 | return FALSE; | |
8121 | } | |
8122 | \f | |
8123 | /* A C expression for the cost of moving data from a register in class FROM to | |
8124 | one in class TO. The classes are expressed using the enumeration values | |
8125 | such as `GENERAL_REGS'. A value of 4 is the default; other values are | |
8126 | interpreted relative to that. | |
8127 | ||
8128 | It is not required that the cost always equal 2 when FROM is the same as TO; | |
8129 | on some machines it is expensive to move between registers if they are not | |
8130 | general registers. | |
8131 | ||
8132 | If reload sees an insn consisting of a single `set' between two hard | |
8133 | registers, and if `REGISTER_MOVE_COST' applied to their classes returns a | |
8134 | value of 2, reload does not check to ensure that the constraints of the insn | |
8135 | are met. Setting a cost of other than 2 will allow reload to verify that | |
8136 | the constraints are met. You should do this if the `movM' pattern's | |
8137 | constraints do not allow such copying. */ | |
8138 | ||
8139 | #define HIGH_COST 40 | |
8140 | #define MEDIUM_COST 3 | |
8141 | #define LOW_COST 1 | |
8142 | ||
8143 | int | |
f2206911 | 8144 | frv_register_move_cost (enum reg_class from, enum reg_class to) |
36a05131 BS |
8145 | { |
8146 | switch (from) | |
8147 | { | |
8148 | default: | |
8149 | break; | |
8150 | ||
8151 | case QUAD_REGS: | |
8152 | case EVEN_REGS: | |
8153 | case GPR_REGS: | |
8154 | switch (to) | |
8155 | { | |
8156 | default: | |
8157 | break; | |
8158 | ||
8159 | case QUAD_REGS: | |
8160 | case EVEN_REGS: | |
8161 | case GPR_REGS: | |
8162 | return LOW_COST; | |
8163 | ||
8164 | case FEVEN_REGS: | |
8165 | case FPR_REGS: | |
8166 | return LOW_COST; | |
8167 | ||
8168 | case LCR_REG: | |
8169 | case LR_REG: | |
8170 | case SPR_REGS: | |
8171 | return LOW_COST; | |
8172 | } | |
8173 | ||
8174 | case FEVEN_REGS: | |
8175 | case FPR_REGS: | |
8176 | switch (to) | |
8177 | { | |
8178 | default: | |
8179 | break; | |
8180 | ||
8181 | case QUAD_REGS: | |
8182 | case EVEN_REGS: | |
8183 | case GPR_REGS: | |
8184 | case ACC_REGS: | |
8185 | case EVEN_ACC_REGS: | |
8186 | case QUAD_ACC_REGS: | |
8187 | case ACCG_REGS: | |
8188 | return MEDIUM_COST; | |
8189 | ||
8190 | case FEVEN_REGS: | |
8191 | case FPR_REGS: | |
8192 | return LOW_COST; | |
8193 | } | |
8194 | ||
8195 | case LCR_REG: | |
8196 | case LR_REG: | |
8197 | case SPR_REGS: | |
8198 | switch (to) | |
8199 | { | |
8200 | default: | |
8201 | break; | |
8202 | ||
8203 | case QUAD_REGS: | |
8204 | case EVEN_REGS: | |
8205 | case GPR_REGS: | |
8206 | return MEDIUM_COST; | |
8207 | } | |
8208 | ||
8209 | case ACC_REGS: | |
8210 | case EVEN_ACC_REGS: | |
8211 | case QUAD_ACC_REGS: | |
8212 | case ACCG_REGS: | |
8213 | switch (to) | |
8214 | { | |
8215 | default: | |
8216 | break; | |
8217 | ||
8218 | case FEVEN_REGS: | |
8219 | case FPR_REGS: | |
8220 | return MEDIUM_COST; | |
8221 | ||
8222 | } | |
8223 | } | |
8224 | ||
8225 | return HIGH_COST; | |
8226 | } | |
8227 | \f | |
8228 | /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to | |
8229 | use ".picptr" to generate safe relocations for PIC code. We also | |
8230 | need a fixup entry for aligned (non-debugging) code. */ | |
8231 | ||
8232 | static bool | |
f2206911 | 8233 | frv_assemble_integer (rtx value, unsigned int size, int aligned_p) |
36a05131 | 8234 | { |
34208acf | 8235 | if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD) |
36a05131 BS |
8236 | { |
8237 | if (GET_CODE (value) == CONST | |
8238 | || GET_CODE (value) == SYMBOL_REF | |
8239 | || GET_CODE (value) == LABEL_REF) | |
8240 | { | |
34208acf AO |
8241 | if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF |
8242 | && SYMBOL_REF_FUNCTION_P (value)) | |
8243 | { | |
8244 | fputs ("\t.picptr\tfuncdesc(", asm_out_file); | |
8245 | output_addr_const (asm_out_file, value); | |
8246 | fputs (")\n", asm_out_file); | |
8247 | return true; | |
8248 | } | |
8249 | else if (TARGET_FDPIC && GET_CODE (value) == CONST | |
8250 | && frv_function_symbol_referenced_p (value)) | |
8251 | return false; | |
8252 | if (aligned_p && !TARGET_FDPIC) | |
36a05131 BS |
8253 | { |
8254 | static int label_num = 0; | |
8255 | char buf[256]; | |
8256 | const char *p; | |
8257 | ||
8258 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++); | |
14966b94 | 8259 | p = (* targetm.strip_name_encoding) (buf); |
36a05131 BS |
8260 | |
8261 | fprintf (asm_out_file, "%s:\n", p); | |
8262 | fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP); | |
8263 | fprintf (asm_out_file, "\t.picptr\t%s\n", p); | |
8264 | fprintf (asm_out_file, "\t.previous\n"); | |
8265 | } | |
8266 | assemble_integer_with_op ("\t.picptr\t", value); | |
8267 | return true; | |
8268 | } | |
8269 | if (!aligned_p) | |
8270 | { | |
8271 | /* We've set the unaligned SI op to NULL, so we always have to | |
8272 | handle the unaligned case here. */ | |
8273 | assemble_integer_with_op ("\t.4byte\t", value); | |
8274 | return true; | |
8275 | } | |
8276 | } | |
8277 | return default_assemble_integer (value, size, aligned_p); | |
8278 | } | |
8279 | ||
8280 | /* Function to set up the backend function structure. */ | |
8281 | ||
8282 | static struct machine_function * | |
f2206911 | 8283 | frv_init_machine_status (void) |
36a05131 BS |
8284 | { |
8285 | return ggc_alloc_cleared (sizeof (struct machine_function)); | |
8286 | } | |
ffb344c1 | 8287 | \f |
28a60850 RS |
8288 | /* Implement TARGET_SCHED_ISSUE_RATE. */ |
8289 | ||
8290 | static int | |
8291 | frv_issue_rate (void) | |
8292 | { | |
8293 | if (!TARGET_PACK) | |
8294 | return 1; | |
8295 | ||
8296 | switch (frv_cpu_type) | |
8297 | { | |
8298 | default: | |
8299 | case FRV_CPU_FR300: | |
8300 | case FRV_CPU_SIMPLE: | |
8301 | return 1; | |
8302 | ||
8303 | case FRV_CPU_FR400: | |
8304 | return 2; | |
8305 | ||
8306 | case FRV_CPU_GENERIC: | |
8307 | case FRV_CPU_FR500: | |
8308 | case FRV_CPU_TOMCAT: | |
8309 | return 4; | |
8310 | } | |
8311 | } | |
36a05131 BS |
8312 | \f |
8313 | /* Update the register state information, to know about which registers are set | |
8314 | or clobbered. */ | |
8315 | ||
8316 | static void | |
f2206911 KC |
8317 | frv_registers_update (rtx x, |
8318 | unsigned char reg_state[], | |
8319 | int modified[], | |
8320 | int *p_num_mod, | |
8321 | int flag) | |
36a05131 BS |
8322 | { |
8323 | int regno, reg_max; | |
8324 | rtx reg; | |
8325 | rtx cond; | |
8326 | const char *format; | |
8327 | int length; | |
8328 | int j; | |
8329 | ||
8330 | switch (GET_CODE (x)) | |
8331 | { | |
8332 | default: | |
8333 | break; | |
8334 | ||
8335 | /* Clobber just modifies a register, it doesn't make it live. */ | |
8336 | case CLOBBER: | |
8337 | frv_registers_update (XEXP (x, 0), reg_state, modified, p_num_mod, | |
8338 | flag | REGSTATE_MODIFIED); | |
8339 | return; | |
8340 | ||
8341 | /* Pre modify updates the first argument, just references the second. */ | |
8342 | case PRE_MODIFY: | |
8343 | case SET: | |
8344 | frv_registers_update (XEXP (x, 0), reg_state, modified, p_num_mod, | |
8345 | flag | REGSTATE_MODIFIED | REGSTATE_LIVE); | |
8346 | frv_registers_update (XEXP (x, 1), reg_state, modified, p_num_mod, flag); | |
8347 | return; | |
8348 | ||
8349 | /* For COND_EXEC, pass the appropriate flag to evaluate the conditional | |
8350 | statement, but just to be sure, make sure it is the type of cond_exec | |
8351 | we expect. */ | |
8352 | case COND_EXEC: | |
8353 | cond = XEXP (x, 0); | |
8354 | if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE) | |
8355 | && GET_CODE (XEXP (cond, 0)) == REG | |
8356 | && CR_P (REGNO (XEXP (cond, 0))) | |
8357 | && GET_CODE (XEXP (cond, 1)) == CONST_INT | |
8358 | && INTVAL (XEXP (cond, 1)) == 0 | |
8359 | && (flag & (REGSTATE_MODIFIED | REGSTATE_IF_EITHER)) == 0) | |
8360 | { | |
8361 | frv_registers_update (cond, reg_state, modified, p_num_mod, flag); | |
8362 | flag |= ((REGNO (XEXP (cond, 0)) - CR_FIRST) | |
8363 | | ((GET_CODE (cond) == NE) | |
8364 | ? REGSTATE_IF_TRUE | |
8365 | : REGSTATE_IF_FALSE)); | |
8366 | ||
8367 | frv_registers_update (XEXP (x, 1), reg_state, modified, p_num_mod, | |
8368 | flag); | |
8369 | return; | |
8370 | } | |
8371 | else | |
8372 | fatal_insn ("frv_registers_update", x); | |
8373 | ||
8374 | /* MEM resets the modification bits. */ | |
8375 | case MEM: | |
8376 | flag &= ~REGSTATE_MODIFIED; | |
8377 | break; | |
8378 | ||
8379 | /* See if we need to set the modified flag. */ | |
8380 | case SUBREG: | |
8381 | reg = SUBREG_REG (x); | |
8382 | if (GET_CODE (reg) == REG) | |
8383 | { | |
8384 | regno = subreg_regno (x); | |
8385 | reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
8386 | goto reg_common; | |
8387 | } | |
8388 | break; | |
8389 | ||
8390 | case REG: | |
8391 | regno = REGNO (x); | |
8392 | reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
87b483a1 | 8393 | /* Fall through. */ |
36a05131 BS |
8394 | |
8395 | reg_common: | |
8396 | if (flag & REGSTATE_MODIFIED) | |
8397 | { | |
8398 | flag &= REGSTATE_MASK; | |
8399 | while (regno < reg_max) | |
8400 | { | |
8401 | int rs = reg_state[regno]; | |
8402 | ||
8403 | if (flag != rs) | |
8404 | { | |
8405 | if ((rs & REGSTATE_MODIFIED) == 0) | |
8406 | { | |
8407 | modified[ *p_num_mod ] = regno; | |
8408 | (*p_num_mod)++; | |
8409 | } | |
8410 | ||
8411 | /* If the previous register state had the register as | |
8412 | modified, possibly in some conditional execution context, | |
8413 | and the current insn modifies in some other context, or | |
8414 | outside of conditional execution, just mark the variable | |
8415 | as modified. */ | |
8416 | else | |
8417 | flag &= ~(REGSTATE_IF_EITHER | REGSTATE_CC_MASK); | |
8418 | ||
8419 | reg_state[regno] = (rs | flag); | |
8420 | } | |
8421 | regno++; | |
8422 | } | |
8423 | } | |
8424 | return; | |
8425 | } | |
8426 | ||
8427 | ||
8428 | length = GET_RTX_LENGTH (GET_CODE (x)); | |
8429 | format = GET_RTX_FORMAT (GET_CODE (x)); | |
8430 | ||
8431 | for (j = 0; j < length; ++j) | |
8432 | { | |
8433 | switch (format[j]) | |
8434 | { | |
8435 | case 'e': | |
8436 | frv_registers_update (XEXP (x, j), reg_state, modified, p_num_mod, | |
8437 | flag); | |
8438 | break; | |
8439 | ||
8440 | case 'V': | |
8441 | case 'E': | |
8442 | if (XVEC (x, j) != 0) | |
8443 | { | |
8444 | int k; | |
8445 | for (k = 0; k < XVECLEN (x, j); ++k) | |
8446 | frv_registers_update (XVECEXP (x, j, k), reg_state, modified, | |
8447 | p_num_mod, flag); | |
8448 | } | |
8449 | break; | |
8450 | ||
8451 | default: | |
8452 | /* Nothing to do. */ | |
8453 | break; | |
8454 | } | |
8455 | } | |
8456 | ||
8457 | return; | |
8458 | } | |
8459 | ||
8460 | \f | |
8461 | /* Return if any registers in a hard register set were used an insn. */ | |
8462 | ||
8463 | static int | |
f2206911 | 8464 | frv_registers_used_p (rtx x, unsigned char reg_state[], int flag) |
36a05131 BS |
8465 | { |
8466 | int regno, reg_max; | |
8467 | rtx reg; | |
8468 | rtx cond; | |
8469 | rtx dest; | |
8470 | const char *format; | |
8471 | int result; | |
8472 | int length; | |
8473 | int j; | |
8474 | ||
8475 | switch (GET_CODE (x)) | |
8476 | { | |
8477 | default: | |
8478 | break; | |
8479 | ||
87b483a1 | 8480 | /* Skip clobber, that doesn't use the previous value. */ |
36a05131 BS |
8481 | case CLOBBER: |
8482 | return FALSE; | |
8483 | ||
8484 | /* For SET, if a conditional jump has occurred in the same insn, only | |
8485 | allow a set of a CR register if that register is not currently live. | |
8486 | This is because on the FR-V, B0/B1 instructions are always last. | |
8487 | Otherwise, don't look at the result, except within a MEM, but do look | |
8488 | at the source. */ | |
8489 | case SET: | |
8490 | dest = SET_DEST (x); | |
8491 | if (flag & REGSTATE_CONDJUMP | |
8492 | && GET_CODE (dest) == REG && CR_P (REGNO (dest)) | |
8493 | && (reg_state[ REGNO (dest) ] & REGSTATE_LIVE) != 0) | |
8494 | return TRUE; | |
8495 | ||
8496 | if (GET_CODE (dest) == MEM) | |
8497 | { | |
8498 | result = frv_registers_used_p (XEXP (dest, 0), reg_state, flag); | |
8499 | if (result) | |
8500 | return result; | |
8501 | } | |
8502 | ||
8503 | return frv_registers_used_p (SET_SRC (x), reg_state, flag); | |
8504 | ||
8505 | /* For COND_EXEC, pass the appropriate flag to evaluate the conditional | |
8506 | statement, but just to be sure, make sure it is the type of cond_exec | |
8507 | we expect. */ | |
8508 | case COND_EXEC: | |
8509 | cond = XEXP (x, 0); | |
8510 | if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE) | |
8511 | && GET_CODE (XEXP (cond, 0)) == REG | |
8512 | && CR_P (REGNO (XEXP (cond, 0))) | |
8513 | && GET_CODE (XEXP (cond, 1)) == CONST_INT | |
8514 | && INTVAL (XEXP (cond, 1)) == 0 | |
8515 | && (flag & (REGSTATE_MODIFIED | REGSTATE_IF_EITHER)) == 0) | |
8516 | { | |
8517 | result = frv_registers_used_p (cond, reg_state, flag); | |
8518 | if (result) | |
8519 | return result; | |
8520 | ||
8521 | flag |= ((REGNO (XEXP (cond, 0)) - CR_FIRST) | |
8522 | | ((GET_CODE (cond) == NE) | |
8523 | ? REGSTATE_IF_TRUE | |
8524 | : REGSTATE_IF_FALSE)); | |
8525 | ||
8526 | return frv_registers_used_p (XEXP (x, 1), reg_state, flag); | |
8527 | } | |
8528 | else | |
8529 | fatal_insn ("frv_registers_used_p", x); | |
8530 | ||
8531 | /* See if a register or subreg was modified in the same VLIW insn. */ | |
8532 | case SUBREG: | |
8533 | reg = SUBREG_REG (x); | |
8534 | if (GET_CODE (reg) == REG) | |
8535 | { | |
8536 | regno = subreg_regno (x); | |
8537 | reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
8538 | goto reg_common; | |
8539 | } | |
8540 | break; | |
8541 | ||
8542 | case REG: | |
8543 | regno = REGNO (x); | |
8544 | reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
87b483a1 | 8545 | /* Fall through. */ |
36a05131 BS |
8546 | |
8547 | reg_common: | |
8548 | while (regno < reg_max) | |
8549 | { | |
8550 | int rs = reg_state[regno]; | |
8551 | ||
8552 | if (rs & REGSTATE_MODIFIED) | |
8553 | { | |
8554 | int rs_if = rs & REGSTATE_IF_EITHER; | |
8555 | int flag_if = flag & REGSTATE_IF_EITHER; | |
8556 | ||
8557 | /* Simple modification, no conditional execution */ | |
8558 | if ((rs & REGSTATE_IF_EITHER) == 0) | |
8559 | return TRUE; | |
8560 | ||
8561 | /* See if the variable is only modified in a conditional | |
8562 | execution expression opposite to the conditional execution | |
8563 | expression that governs this expression (ie, true vs. false | |
8564 | for the same CC register). If this isn't two halves of the | |
8565 | same conditional expression, consider the register | |
87b483a1 | 8566 | modified. */ |
36a05131 BS |
8567 | if (((rs_if == REGSTATE_IF_TRUE && flag_if == REGSTATE_IF_FALSE) |
8568 | || (rs_if == REGSTATE_IF_FALSE && flag_if == REGSTATE_IF_TRUE)) | |
8569 | && ((rs & REGSTATE_CC_MASK) == (flag & REGSTATE_CC_MASK))) | |
8570 | ; | |
8571 | else | |
8572 | return TRUE; | |
8573 | } | |
8574 | ||
8575 | regno++; | |
8576 | } | |
8577 | return FALSE; | |
8578 | } | |
8579 | ||
8580 | ||
8581 | length = GET_RTX_LENGTH (GET_CODE (x)); | |
8582 | format = GET_RTX_FORMAT (GET_CODE (x)); | |
8583 | ||
8584 | for (j = 0; j < length; ++j) | |
8585 | { | |
8586 | switch (format[j]) | |
8587 | { | |
8588 | case 'e': | |
8589 | result = frv_registers_used_p (XEXP (x, j), reg_state, flag); | |
8590 | if (result != 0) | |
8591 | return result; | |
8592 | break; | |
8593 | ||
8594 | case 'V': | |
8595 | case 'E': | |
8596 | if (XVEC (x, j) != 0) | |
8597 | { | |
8598 | int k; | |
8599 | for (k = 0; k < XVECLEN (x, j); ++k) | |
8600 | { | |
8601 | result = frv_registers_used_p (XVECEXP (x, j, k), reg_state, | |
8602 | flag); | |
8603 | if (result != 0) | |
8604 | return result; | |
8605 | } | |
8606 | } | |
8607 | break; | |
8608 | ||
8609 | default: | |
8610 | /* Nothing to do. */ | |
8611 | break; | |
8612 | } | |
8613 | } | |
8614 | ||
8615 | return 0; | |
8616 | } | |
8617 | ||
8618 | /* Return if any registers in a hard register set were set in an insn. */ | |
8619 | ||
8620 | static int | |
f2206911 | 8621 | frv_registers_set_p (rtx x, unsigned char reg_state[], int modify_p) |
36a05131 BS |
8622 | { |
8623 | int regno, reg_max; | |
8624 | rtx reg; | |
8625 | rtx cond; | |
8626 | const char *format; | |
8627 | int length; | |
8628 | int j; | |
8629 | ||
8630 | switch (GET_CODE (x)) | |
8631 | { | |
8632 | default: | |
8633 | break; | |
8634 | ||
8635 | case CLOBBER: | |
8636 | return frv_registers_set_p (XEXP (x, 0), reg_state, TRUE); | |
8637 | ||
8638 | case PRE_MODIFY: | |
8639 | case SET: | |
8640 | return (frv_registers_set_p (XEXP (x, 0), reg_state, TRUE) | |
8641 | || frv_registers_set_p (XEXP (x, 1), reg_state, FALSE)); | |
8642 | ||
8643 | case COND_EXEC: | |
8644 | cond = XEXP (x, 0); | |
87b483a1 | 8645 | /* Just to be sure, make sure it is the type of cond_exec we |
36a05131 BS |
8646 | expect. */ |
8647 | if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE) | |
8648 | && GET_CODE (XEXP (cond, 0)) == REG | |
8649 | && CR_P (REGNO (XEXP (cond, 0))) | |
8650 | && GET_CODE (XEXP (cond, 1)) == CONST_INT | |
8651 | && INTVAL (XEXP (cond, 1)) == 0 | |
8652 | && !modify_p) | |
8653 | return frv_registers_set_p (XEXP (x, 1), reg_state, modify_p); | |
8654 | else | |
8655 | fatal_insn ("frv_registers_set_p", x); | |
8656 | ||
8657 | /* MEM resets the modification bits. */ | |
8658 | case MEM: | |
8659 | modify_p = FALSE; | |
8660 | break; | |
8661 | ||
8662 | /* See if we need to set the modified modify_p. */ | |
8663 | case SUBREG: | |
8664 | reg = SUBREG_REG (x); | |
8665 | if (GET_CODE (reg) == REG) | |
8666 | { | |
8667 | regno = subreg_regno (x); | |
8668 | reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
8669 | goto reg_common; | |
8670 | } | |
8671 | break; | |
8672 | ||
8673 | case REG: | |
8674 | regno = REGNO (x); | |
8675 | reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
87b483a1 | 8676 | /* Fall through. */ |
36a05131 BS |
8677 | |
8678 | reg_common: | |
8679 | if (modify_p) | |
8680 | while (regno < reg_max) | |
8681 | { | |
8682 | int rs = reg_state[regno]; | |
8683 | ||
8684 | if (rs & REGSTATE_MODIFIED) | |
8685 | return TRUE; | |
8686 | regno++; | |
8687 | } | |
8688 | return FALSE; | |
8689 | } | |
8690 | ||
8691 | ||
8692 | length = GET_RTX_LENGTH (GET_CODE (x)); | |
8693 | format = GET_RTX_FORMAT (GET_CODE (x)); | |
8694 | ||
8695 | for (j = 0; j < length; ++j) | |
8696 | { | |
8697 | switch (format[j]) | |
8698 | { | |
8699 | case 'e': | |
8700 | if (frv_registers_set_p (XEXP (x, j), reg_state, modify_p)) | |
8701 | return TRUE; | |
8702 | break; | |
8703 | ||
8704 | case 'V': | |
8705 | case 'E': | |
8706 | if (XVEC (x, j) != 0) | |
8707 | { | |
8708 | int k; | |
8709 | for (k = 0; k < XVECLEN (x, j); ++k) | |
8710 | if (frv_registers_set_p (XVECEXP (x, j, k), reg_state, | |
8711 | modify_p)) | |
8712 | return TRUE; | |
8713 | } | |
8714 | break; | |
8715 | ||
8716 | default: | |
8717 | /* Nothing to do. */ | |
8718 | break; | |
8719 | } | |
8720 | } | |
8721 | ||
8722 | return FALSE; | |
8723 | } | |
8724 | ||
8725 | \f | |
36a05131 BS |
8726 | /* On the FR-V, this pass is used to rescan the insn chain, and pack |
8727 | conditional branches/calls/jumps, etc. with previous insns where it can. It | |
8728 | does not reorder the instructions. We assume the scheduler left the flow | |
8729 | information in a reasonable state. */ | |
8730 | ||
8731 | static void | |
f2206911 | 8732 | frv_pack_insns (void) |
36a05131 BS |
8733 | { |
8734 | state_t frv_state; /* frv state machine */ | |
8735 | int cur_start_vliw_p; /* current insn starts a VLIW insn */ | |
8736 | int next_start_vliw_p; /* next insn starts a VLIW insn */ | |
8737 | int cur_condjump_p; /* flag if current insn is a cond jump*/ | |
8738 | int next_condjump_p; /* flag if next insn is a cond jump */ | |
8739 | rtx insn; | |
8740 | rtx link; | |
8741 | int j; | |
8742 | int num_mod = 0; /* # of modified registers */ | |
8743 | int modified[FIRST_PSEUDO_REGISTER]; /* registers modified in current VLIW */ | |
8744 | /* register state information */ | |
8745 | unsigned char reg_state[FIRST_PSEUDO_REGISTER]; | |
8746 | ||
8747 | /* If we weren't going to pack the insns, don't bother with this pass. */ | |
28a60850 RS |
8748 | if (!optimize |
8749 | || !flag_schedule_insns_after_reload | |
8750 | || TARGET_NO_VLIW_BRANCH | |
8751 | || frv_issue_rate () == 1) | |
36a05131 BS |
8752 | return; |
8753 | ||
36a05131 BS |
8754 | /* Set up the instruction and register states. */ |
8755 | dfa_start (); | |
8756 | frv_state = (state_t) xmalloc (state_size ()); | |
fad205ff | 8757 | memset (reg_state, REGSTATE_DEAD, sizeof (reg_state)); |
36a05131 BS |
8758 | |
8759 | /* Go through the insns, and repack the insns. */ | |
8760 | state_reset (frv_state); | |
8761 | cur_start_vliw_p = FALSE; | |
8762 | next_start_vliw_p = TRUE; | |
8763 | cur_condjump_p = 0; | |
8764 | next_condjump_p = 0; | |
8765 | ||
8766 | for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn)) | |
8767 | { | |
8768 | enum rtx_code code = GET_CODE (insn); | |
8769 | enum rtx_code pattern_code; | |
8770 | ||
8771 | /* For basic block begin notes redo the live information, and skip other | |
8772 | notes. */ | |
8773 | if (code == NOTE) | |
8774 | { | |
8775 | if (NOTE_LINE_NUMBER (insn) == (int)NOTE_INSN_BASIC_BLOCK) | |
8776 | { | |
8777 | regset live; | |
8778 | ||
8779 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
8780 | reg_state[j] &= ~ REGSTATE_LIVE; | |
8781 | ||
8782 | live = NOTE_BASIC_BLOCK (insn)->global_live_at_start; | |
8783 | EXECUTE_IF_SET_IN_REG_SET(live, 0, j, | |
8784 | { | |
8785 | reg_state[j] |= REGSTATE_LIVE; | |
8786 | }); | |
8787 | } | |
8788 | ||
8789 | continue; | |
8790 | } | |
8791 | ||
87b483a1 | 8792 | /* Things like labels reset everything. */ |
ec8e098d | 8793 | if (!INSN_P (insn)) |
36a05131 BS |
8794 | { |
8795 | next_start_vliw_p = TRUE; | |
8796 | continue; | |
8797 | } | |
8798 | ||
8799 | /* Clear the VLIW start flag on random USE and CLOBBER insns, which is | |
839a4992 | 8800 | set on the USE insn that precedes the return, and potentially on |
36a05131 BS |
8801 | CLOBBERs for setting multiword variables. Also skip the ADDR_VEC |
8802 | holding the case table labels. */ | |
8803 | pattern_code = GET_CODE (PATTERN (insn)); | |
8804 | if (pattern_code == USE || pattern_code == CLOBBER | |
8805 | || pattern_code == ADDR_VEC || pattern_code == ADDR_DIFF_VEC) | |
8806 | { | |
8807 | CLEAR_VLIW_START (insn); | |
8808 | continue; | |
8809 | } | |
8810 | ||
8811 | cur_start_vliw_p = next_start_vliw_p; | |
8812 | next_start_vliw_p = FALSE; | |
8813 | ||
8814 | cur_condjump_p |= next_condjump_p; | |
8815 | next_condjump_p = 0; | |
8816 | ||
8817 | /* Unconditional branches and calls end the current VLIW insn. */ | |
8818 | if (code == CALL_INSN) | |
8819 | { | |
8820 | next_start_vliw_p = TRUE; | |
8821 | ||
8822 | /* On a TOMCAT, calls must be alone in the VLIW insns. */ | |
8823 | if (frv_cpu_type == FRV_CPU_TOMCAT) | |
8824 | cur_start_vliw_p = TRUE; | |
8825 | } | |
8826 | else if (code == JUMP_INSN) | |
8827 | { | |
8828 | if (any_condjump_p (insn)) | |
8829 | next_condjump_p = REGSTATE_CONDJUMP; | |
8830 | else | |
8831 | next_start_vliw_p = TRUE; | |
8832 | } | |
8833 | ||
8834 | /* Only allow setting a CCR register after a conditional branch. */ | |
8835 | else if (((cur_condjump_p & REGSTATE_CONDJUMP) != 0) | |
8836 | && get_attr_type (insn) != TYPE_CCR) | |
8837 | cur_start_vliw_p = TRUE; | |
8838 | ||
8839 | /* Determine if we need to start a new VLIW instruction. */ | |
8840 | if (cur_start_vliw_p | |
8841 | /* Do not check for register conflicts in a setlo instruction | |
8842 | because any output or true dependencies will be with the | |
8843 | partnering sethi instruction, with which it can be packed. | |
8844 | ||
8845 | Although output dependencies are rare they are still | |
87b483a1 | 8846 | possible. So check output dependencies in VLIW insn. */ |
36a05131 BS |
8847 | || (get_attr_type (insn) != TYPE_SETLO |
8848 | && (frv_registers_used_p (PATTERN (insn), | |
8849 | reg_state, | |
8850 | cur_condjump_p) | |
8851 | || frv_registers_set_p (PATTERN (insn), reg_state, FALSE))) | |
8852 | || state_transition (frv_state, insn) >= 0) | |
8853 | { | |
8854 | SET_VLIW_START (insn); | |
8855 | state_reset (frv_state); | |
8856 | state_transition (frv_state, insn); | |
8857 | cur_condjump_p = 0; | |
8858 | ||
8859 | /* Update the modified registers. */ | |
8860 | for (j = 0; j < num_mod; j++) | |
8861 | reg_state[ modified[j] ] &= ~(REGSTATE_CC_MASK | |
8862 | | REGSTATE_IF_EITHER | |
8863 | | REGSTATE_MODIFIED); | |
8864 | ||
8865 | num_mod = 0; | |
8866 | } | |
8867 | else | |
8868 | CLEAR_VLIW_START (insn); | |
8869 | ||
8870 | /* Record which registers are modified. */ | |
8871 | frv_registers_update (PATTERN (insn), reg_state, modified, &num_mod, 0); | |
8872 | ||
87b483a1 | 8873 | /* Process the death notices. */ |
36a05131 BS |
8874 | for (link = REG_NOTES (insn); |
8875 | link != NULL_RTX; | |
8876 | link = XEXP (link, 1)) | |
8877 | { | |
8878 | rtx reg = XEXP (link, 0); | |
8879 | ||
8880 | if (REG_NOTE_KIND (link) == REG_DEAD && GET_CODE (reg) == REG) | |
8881 | { | |
8882 | int regno = REGNO (reg); | |
8883 | int n = regno + HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
8884 | for (; regno < n; regno++) | |
8885 | reg_state[regno] &= ~REGSTATE_LIVE; | |
8886 | } | |
8887 | } | |
8888 | } | |
8889 | ||
fad205ff | 8890 | free (frv_state); |
36a05131 BS |
8891 | dfa_finish (); |
8892 | return; | |
8893 | } | |
8894 | ||
8895 | \f | |
8896 | #define def_builtin(name, type, code) \ | |
8897 | builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL) | |
8898 | ||
8899 | struct builtin_description | |
8900 | { | |
8901 | enum insn_code icode; | |
8902 | const char *name; | |
8903 | enum frv_builtins code; | |
8904 | enum rtx_code comparison; | |
8905 | unsigned int flag; | |
8906 | }; | |
8907 | ||
8908 | /* Media intrinsics that take a single, constant argument. */ | |
8909 | ||
8910 | static struct builtin_description bdesc_set[] = | |
8911 | { | |
8912 | { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 } | |
8913 | }; | |
8914 | ||
87b483a1 | 8915 | /* Media intrinsics that take just one argument. */ |
36a05131 BS |
8916 | |
8917 | static struct builtin_description bdesc_1arg[] = | |
8918 | { | |
8919 | { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 }, | |
8920 | { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 }, | |
8921 | { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 }, | |
8922 | { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 }, | |
8923 | { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 } | |
8924 | }; | |
8925 | ||
87b483a1 | 8926 | /* Media intrinsics that take two arguments. */ |
36a05131 BS |
8927 | |
8928 | static struct builtin_description bdesc_2arg[] = | |
8929 | { | |
8930 | { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 }, | |
8931 | { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 }, | |
8932 | { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 }, | |
8933 | { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 }, | |
8934 | { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 }, | |
8935 | { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 }, | |
8936 | { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 }, | |
8937 | { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 }, | |
8938 | { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 }, | |
8939 | { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 }, | |
8940 | { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 }, | |
8941 | { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 }, | |
8942 | { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 }, | |
8943 | { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 }, | |
8944 | { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 }, | |
8945 | { CODE_FOR_mdpackh, "__MDPACKH", FRV_BUILTIN_MDPACKH, 0, 0 }, | |
8946 | { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 }, | |
8947 | { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 }, | |
8948 | { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 }, | |
8949 | { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 } | |
8950 | }; | |
8951 | ||
8952 | /* Media intrinsics that take two arguments, the first being an ACC number. */ | |
8953 | ||
8954 | static struct builtin_description bdesc_cut[] = | |
8955 | { | |
8956 | { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 }, | |
8957 | { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 }, | |
8958 | { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 } | |
8959 | }; | |
8960 | ||
87b483a1 | 8961 | /* Two-argument media intrinsics with an immediate second argument. */ |
36a05131 BS |
8962 | |
8963 | static struct builtin_description bdesc_2argimm[] = | |
8964 | { | |
8965 | { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 }, | |
8966 | { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 }, | |
8967 | { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 }, | |
8968 | { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 }, | |
8969 | { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 }, | |
8970 | { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 }, | |
8971 | { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 }, | |
8972 | { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 }, | |
8973 | { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 }, | |
8974 | { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 }, | |
8975 | { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 }, | |
8976 | { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 }, | |
8977 | { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 }, | |
8978 | { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 }, | |
8979 | { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 } | |
8980 | }; | |
8981 | ||
8982 | /* Media intrinsics that take two arguments and return void, the first argument | |
87b483a1 | 8983 | being a pointer to 4 words in memory. */ |
36a05131 BS |
8984 | |
8985 | static struct builtin_description bdesc_void2arg[] = | |
8986 | { | |
8987 | { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 }, | |
8988 | { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 }, | |
8989 | }; | |
8990 | ||
8991 | /* Media intrinsics that take three arguments, the first being a const_int that | |
87b483a1 | 8992 | denotes an accumulator, and that return void. */ |
36a05131 BS |
8993 | |
8994 | static struct builtin_description bdesc_void3arg[] = | |
8995 | { | |
8996 | { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 }, | |
8997 | { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 }, | |
8998 | { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 }, | |
8999 | { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 }, | |
9000 | { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 }, | |
9001 | { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 }, | |
9002 | { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 }, | |
9003 | { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 }, | |
9004 | { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 }, | |
9005 | { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 }, | |
9006 | { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 }, | |
9007 | { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 }, | |
9008 | { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 }, | |
9009 | { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 }, | |
9010 | { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 }, | |
9011 | { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 }, | |
9012 | { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 }, | |
9013 | { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 }, | |
9014 | { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 }, | |
9015 | { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 }, | |
9016 | { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 }, | |
9017 | { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 }, | |
9018 | { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 }, | |
9019 | { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 }, | |
9020 | { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 } | |
9021 | }; | |
9022 | ||
9023 | /* Media intrinsics that take two accumulator numbers as argument and | |
9024 | return void. */ | |
9025 | ||
9026 | static struct builtin_description bdesc_voidacc[] = | |
9027 | { | |
9028 | { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 }, | |
9029 | { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 }, | |
9030 | { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 }, | |
9031 | { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 }, | |
9032 | { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 }, | |
9033 | { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 } | |
9034 | }; | |
9035 | ||
87b483a1 | 9036 | /* Initialize media builtins. */ |
36a05131 | 9037 | |
14966b94 | 9038 | static void |
f2206911 | 9039 | frv_init_builtins (void) |
36a05131 BS |
9040 | { |
9041 | tree endlink = void_list_node; | |
9042 | tree accumulator = integer_type_node; | |
9043 | tree integer = integer_type_node; | |
9044 | tree voidt = void_type_node; | |
9045 | tree uhalf = short_unsigned_type_node; | |
9046 | tree sword1 = long_integer_type_node; | |
9047 | tree uword1 = long_unsigned_type_node; | |
9048 | tree sword2 = long_long_integer_type_node; | |
9049 | tree uword2 = long_long_unsigned_type_node; | |
9050 | tree uword4 = build_pointer_type (uword1); | |
9051 | ||
9052 | #define UNARY(RET, T1) \ | |
9053 | build_function_type (RET, tree_cons (NULL_TREE, T1, endlink)) | |
9054 | ||
9055 | #define BINARY(RET, T1, T2) \ | |
9056 | build_function_type (RET, tree_cons (NULL_TREE, T1, \ | |
9057 | tree_cons (NULL_TREE, T2, endlink))) | |
9058 | ||
9059 | #define TRINARY(RET, T1, T2, T3) \ | |
9060 | build_function_type (RET, tree_cons (NULL_TREE, T1, \ | |
9061 | tree_cons (NULL_TREE, T2, \ | |
9062 | tree_cons (NULL_TREE, T3, endlink)))) | |
9063 | ||
9064 | tree void_ftype_void = build_function_type (voidt, endlink); | |
9065 | ||
9066 | tree void_ftype_acc = UNARY (voidt, accumulator); | |
9067 | tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1); | |
9068 | tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2); | |
9069 | tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1); | |
9070 | tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator); | |
9071 | tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1); | |
9072 | tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1); | |
9073 | tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2); | |
9074 | tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2); | |
9075 | ||
9076 | tree uw1_ftype_uw1 = UNARY (uword1, uword1); | |
9077 | tree uw1_ftype_sw1 = UNARY (uword1, sword1); | |
9078 | tree uw1_ftype_uw2 = UNARY (uword1, uword2); | |
9079 | tree uw1_ftype_acc = UNARY (uword1, accumulator); | |
9080 | tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf); | |
9081 | tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1); | |
9082 | tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer); | |
9083 | tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1); | |
9084 | tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1); | |
9085 | tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1); | |
9086 | tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer); | |
9087 | ||
9088 | tree sw1_ftype_int = UNARY (sword1, integer); | |
9089 | tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1); | |
9090 | tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer); | |
9091 | ||
9092 | tree uw2_ftype_uw1 = UNARY (uword2, uword1); | |
9093 | tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer); | |
9094 | tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2); | |
9095 | tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer); | |
9096 | tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer); | |
9097 | ||
9098 | tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2); | |
9099 | ||
9100 | def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND); | |
9101 | def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR); | |
9102 | def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR); | |
9103 | def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT); | |
9104 | def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI); | |
9105 | def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI); | |
9106 | def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT); | |
9107 | def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH); | |
9108 | def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI); | |
9109 | def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI); | |
9110 | def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI); | |
9111 | def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS); | |
9112 | def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU); | |
9113 | def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS); | |
9114 | def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS); | |
9115 | def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS); | |
9116 | def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS); | |
9117 | def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS); | |
9118 | def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU); | |
9119 | def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS); | |
9120 | def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU); | |
9121 | def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS); | |
9122 | def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU); | |
9123 | def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS); | |
9124 | def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU); | |
9125 | def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS); | |
9126 | def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS); | |
9127 | def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS); | |
9128 | def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS); | |
9129 | def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS); | |
9130 | def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU); | |
9131 | def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS); | |
9132 | def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU); | |
9133 | def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS); | |
9134 | def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU); | |
9135 | def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS); | |
9136 | def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU); | |
9137 | def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS); | |
9138 | def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU); | |
9139 | def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS); | |
9140 | def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU); | |
9141 | def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS); | |
9142 | def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU); | |
9143 | def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT); | |
9144 | def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS); | |
9145 | def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW); | |
9146 | def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD); | |
9147 | def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH); | |
9148 | def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH); | |
9149 | def_builtin ("__MDPACKH", uw2_ftype_uw2_uw2, FRV_BUILTIN_MDPACKH); | |
b16c1435 | 9150 | def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH); |
36a05131 BS |
9151 | def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH); |
9152 | def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB); | |
9153 | def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE); | |
9154 | def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC); | |
9155 | def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA); | |
9156 | def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC); | |
9157 | def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG); | |
9158 | def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC); | |
9159 | def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG); | |
9160 | def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1); | |
9161 | def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2); | |
9162 | def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP); | |
9163 | def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS); | |
9164 | def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS); | |
9165 | def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS); | |
9166 | def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS); | |
9167 | def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS); | |
9168 | def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS); | |
9169 | def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS); | |
9170 | def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS); | |
9171 | def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS); | |
9172 | def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS); | |
9173 | def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI); | |
9174 | def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI); | |
9175 | def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI); | |
9176 | def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI); | |
9177 | def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS); | |
9178 | def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS); | |
9179 | def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS); | |
9180 | def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS); | |
9181 | def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH); | |
9182 | def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH); | |
9183 | def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH); | |
9184 | ||
9185 | #undef UNARY | |
9186 | #undef BINARY | |
9187 | #undef TRINARY | |
9188 | } | |
9189 | ||
c15c90bb ZW |
9190 | /* Set the names for various arithmetic operations according to the |
9191 | FRV ABI. */ | |
9192 | static void | |
9193 | frv_init_libfuncs (void) | |
9194 | { | |
9195 | set_optab_libfunc (smod_optab, SImode, "__modi"); | |
9196 | set_optab_libfunc (umod_optab, SImode, "__umodi"); | |
9197 | ||
9198 | set_optab_libfunc (add_optab, DImode, "__addll"); | |
9199 | set_optab_libfunc (sub_optab, DImode, "__subll"); | |
9200 | set_optab_libfunc (smul_optab, DImode, "__mulll"); | |
9201 | set_optab_libfunc (sdiv_optab, DImode, "__divll"); | |
9202 | set_optab_libfunc (smod_optab, DImode, "__modll"); | |
9203 | set_optab_libfunc (umod_optab, DImode, "__umodll"); | |
9204 | set_optab_libfunc (and_optab, DImode, "__andll"); | |
9205 | set_optab_libfunc (ior_optab, DImode, "__orll"); | |
9206 | set_optab_libfunc (xor_optab, DImode, "__xorll"); | |
9207 | set_optab_libfunc (one_cmpl_optab, DImode, "__notll"); | |
9208 | ||
9209 | set_optab_libfunc (add_optab, SFmode, "__addf"); | |
9210 | set_optab_libfunc (sub_optab, SFmode, "__subf"); | |
9211 | set_optab_libfunc (smul_optab, SFmode, "__mulf"); | |
9212 | set_optab_libfunc (sdiv_optab, SFmode, "__divf"); | |
9213 | ||
9214 | set_optab_libfunc (add_optab, DFmode, "__addd"); | |
9215 | set_optab_libfunc (sub_optab, DFmode, "__subd"); | |
9216 | set_optab_libfunc (smul_optab, DFmode, "__muld"); | |
9217 | set_optab_libfunc (sdiv_optab, DFmode, "__divd"); | |
9218 | ||
85363ca0 ZW |
9219 | set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod"); |
9220 | set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof"); | |
9221 | ||
9222 | set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi"); | |
9223 | set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll"); | |
9224 | set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi"); | |
9225 | set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll"); | |
9226 | ||
9227 | set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui"); | |
09c55720 RS |
9228 | set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull"); |
9229 | set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui"); | |
9230 | set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull"); | |
85363ca0 ZW |
9231 | |
9232 | set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof"); | |
9233 | set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof"); | |
9234 | set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod"); | |
9235 | set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod"); | |
c15c90bb ZW |
9236 | } |
9237 | ||
36a05131 BS |
9238 | /* Convert an integer constant to an accumulator register. ICODE is the |
9239 | code of the target instruction, OPNUM is the number of the | |
9240 | accumulator operand and OPVAL is the constant integer. Try both | |
9241 | ACC and ACCG registers; only report an error if neither fit the | |
9242 | instruction. */ | |
9243 | ||
9244 | static rtx | |
f2206911 | 9245 | frv_int_to_acc (enum insn_code icode, int opnum, rtx opval) |
36a05131 BS |
9246 | { |
9247 | rtx reg; | |
9248 | ||
9249 | if (GET_CODE (opval) != CONST_INT) | |
9250 | { | |
9251 | error ("accumulator is not a constant integer"); | |
9252 | return NULL_RTX; | |
9253 | } | |
9254 | if (! IN_RANGE_P (INTVAL (opval), 0, NUM_ACCS - 1)) | |
9255 | { | |
9256 | error ("accumulator number is out of bounds"); | |
9257 | return NULL_RTX; | |
9258 | } | |
9259 | ||
9260 | reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode, | |
9261 | ACC_FIRST + INTVAL (opval)); | |
9262 | if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode)) | |
9263 | REGNO (reg) = ACCG_FIRST + INTVAL (opval); | |
9264 | ||
9265 | if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode)) | |
9266 | { | |
9267 | error ("inappropriate accumulator for `%s'", insn_data[icode].name); | |
9268 | return NULL_RTX; | |
9269 | } | |
9270 | return reg; | |
9271 | } | |
9272 | ||
9273 | /* If an ACC rtx has mode MODE, return the mode that the matching ACCG | |
9274 | should have. */ | |
9275 | ||
9276 | static enum machine_mode | |
f2206911 | 9277 | frv_matching_accg_mode (enum machine_mode mode) |
36a05131 BS |
9278 | { |
9279 | switch (mode) | |
9280 | { | |
9281 | case V4SImode: | |
9282 | return V4QImode; | |
9283 | ||
9284 | case DImode: | |
9285 | return HImode; | |
9286 | ||
9287 | case SImode: | |
9288 | return QImode; | |
9289 | ||
9290 | default: | |
9291 | abort (); | |
9292 | } | |
9293 | } | |
9294 | ||
9295 | /* Return the accumulator guard that should be paired with accumulator | |
9296 | register ACC. The mode of the returned register is in the same | |
9297 | class as ACC, but is four times smaller. */ | |
9298 | ||
9299 | rtx | |
f2206911 | 9300 | frv_matching_accg_for_acc (rtx acc) |
36a05131 BS |
9301 | { |
9302 | return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)), | |
9303 | REGNO (acc) - ACC_FIRST + ACCG_FIRST); | |
9304 | } | |
9305 | ||
9306 | /* Read a value from the head of the tree list pointed to by ARGLISTPTR. | |
9307 | Return the value as an rtx and replace *ARGLISTPTR with the tail of the | |
9308 | list. */ | |
9309 | ||
9310 | static rtx | |
f2206911 | 9311 | frv_read_argument (tree *arglistptr) |
36a05131 BS |
9312 | { |
9313 | tree next = TREE_VALUE (*arglistptr); | |
9314 | *arglistptr = TREE_CHAIN (*arglistptr); | |
9315 | return expand_expr (next, NULL_RTX, VOIDmode, 0); | |
9316 | } | |
9317 | ||
9318 | /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE. | |
9319 | The instruction should require a constant operand of some sort. The | |
9320 | function prints an error if OPVAL is not valid. */ | |
9321 | ||
9322 | static int | |
f2206911 | 9323 | frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval) |
36a05131 BS |
9324 | { |
9325 | if (GET_CODE (opval) != CONST_INT) | |
9326 | { | |
9327 | error ("`%s' expects a constant argument", insn_data[icode].name); | |
9328 | return FALSE; | |
9329 | } | |
9330 | if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode)) | |
9331 | { | |
9332 | error ("constant argument out of range for `%s'", insn_data[icode].name); | |
9333 | return FALSE; | |
9334 | } | |
9335 | return TRUE; | |
9336 | } | |
9337 | ||
9338 | /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET | |
9339 | if it's not null, has the right mode, and satisfies operand 0's | |
9340 | predicate. */ | |
9341 | ||
9342 | static rtx | |
f2206911 | 9343 | frv_legitimize_target (enum insn_code icode, rtx target) |
36a05131 BS |
9344 | { |
9345 | enum machine_mode mode = insn_data[icode].operand[0].mode; | |
9346 | ||
9347 | if (! target | |
9348 | || GET_MODE (target) != mode | |
9349 | || ! (*insn_data[icode].operand[0].predicate) (target, mode)) | |
9350 | return gen_reg_rtx (mode); | |
9351 | else | |
9352 | return target; | |
9353 | } | |
9354 | ||
9355 | /* Given that ARG is being passed as operand OPNUM to instruction ICODE, | |
839a4992 | 9356 | check whether ARG satisfies the operand's constraints. If it doesn't, |
36a05131 BS |
9357 | copy ARG to a temporary register and return that. Otherwise return ARG |
9358 | itself. */ | |
9359 | ||
9360 | static rtx | |
f2206911 | 9361 | frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg) |
36a05131 BS |
9362 | { |
9363 | enum machine_mode mode = insn_data[icode].operand[opnum].mode; | |
9364 | ||
9365 | if ((*insn_data[icode].operand[opnum].predicate) (arg, mode)) | |
9366 | return arg; | |
9367 | else | |
9368 | return copy_to_mode_reg (mode, arg); | |
9369 | } | |
9370 | ||
9371 | /* Expand builtins that take a single, constant argument. At the moment, | |
9372 | only MHDSETS falls into this category. */ | |
9373 | ||
9374 | static rtx | |
f2206911 | 9375 | frv_expand_set_builtin (enum insn_code icode, tree arglist, rtx target) |
36a05131 BS |
9376 | { |
9377 | rtx pat; | |
9378 | rtx op0 = frv_read_argument (&arglist); | |
9379 | ||
9380 | if (! frv_check_constant_argument (icode, 1, op0)) | |
9381 | return NULL_RTX; | |
9382 | ||
9383 | target = frv_legitimize_target (icode, target); | |
9384 | pat = GEN_FCN (icode) (target, op0); | |
9385 | if (! pat) | |
9386 | return NULL_RTX; | |
9387 | ||
9388 | emit_insn (pat); | |
9389 | return target; | |
9390 | } | |
9391 | ||
87b483a1 | 9392 | /* Expand builtins that take one operand. */ |
36a05131 BS |
9393 | |
9394 | static rtx | |
f2206911 | 9395 | frv_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target) |
36a05131 BS |
9396 | { |
9397 | rtx pat; | |
9398 | rtx op0 = frv_read_argument (&arglist); | |
9399 | ||
9400 | target = frv_legitimize_target (icode, target); | |
9401 | op0 = frv_legitimize_argument (icode, 1, op0); | |
9402 | pat = GEN_FCN (icode) (target, op0); | |
9403 | if (! pat) | |
9404 | return NULL_RTX; | |
9405 | ||
9406 | emit_insn (pat); | |
9407 | return target; | |
9408 | } | |
9409 | ||
87b483a1 | 9410 | /* Expand builtins that take two operands. */ |
36a05131 BS |
9411 | |
9412 | static rtx | |
f2206911 | 9413 | frv_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target) |
36a05131 BS |
9414 | { |
9415 | rtx pat; | |
9416 | rtx op0 = frv_read_argument (&arglist); | |
9417 | rtx op1 = frv_read_argument (&arglist); | |
9418 | ||
9419 | target = frv_legitimize_target (icode, target); | |
9420 | op0 = frv_legitimize_argument (icode, 1, op0); | |
9421 | op1 = frv_legitimize_argument (icode, 2, op1); | |
9422 | pat = GEN_FCN (icode) (target, op0, op1); | |
9423 | if (! pat) | |
9424 | return NULL_RTX; | |
9425 | ||
9426 | emit_insn (pat); | |
9427 | return target; | |
9428 | } | |
9429 | ||
9430 | /* Expand cut-style builtins, which take two operands and an implicit ACCG | |
87b483a1 | 9431 | one. */ |
36a05131 BS |
9432 | |
9433 | static rtx | |
f2206911 | 9434 | frv_expand_cut_builtin (enum insn_code icode, tree arglist, rtx target) |
36a05131 BS |
9435 | { |
9436 | rtx pat; | |
9437 | rtx op0 = frv_read_argument (&arglist); | |
9438 | rtx op1 = frv_read_argument (&arglist); | |
9439 | rtx op2; | |
9440 | ||
9441 | target = frv_legitimize_target (icode, target); | |
9442 | op0 = frv_int_to_acc (icode, 1, op0); | |
9443 | if (! op0) | |
9444 | return NULL_RTX; | |
9445 | ||
9446 | if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT) | |
9447 | { | |
9448 | if (! frv_check_constant_argument (icode, 2, op1)) | |
9449 | return NULL_RTX; | |
9450 | } | |
9451 | else | |
9452 | op1 = frv_legitimize_argument (icode, 2, op1); | |
9453 | ||
9454 | op2 = frv_matching_accg_for_acc (op0); | |
9455 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
9456 | if (! pat) | |
9457 | return NULL_RTX; | |
9458 | ||
9459 | emit_insn (pat); | |
9460 | return target; | |
9461 | } | |
9462 | ||
87b483a1 | 9463 | /* Expand builtins that take two operands and the second is immediate. */ |
36a05131 BS |
9464 | |
9465 | static rtx | |
f2206911 | 9466 | frv_expand_binopimm_builtin (enum insn_code icode, tree arglist, rtx target) |
36a05131 BS |
9467 | { |
9468 | rtx pat; | |
9469 | rtx op0 = frv_read_argument (&arglist); | |
9470 | rtx op1 = frv_read_argument (&arglist); | |
9471 | ||
9472 | if (! frv_check_constant_argument (icode, 2, op1)) | |
9473 | return NULL_RTX; | |
9474 | ||
9475 | target = frv_legitimize_target (icode, target); | |
9476 | op0 = frv_legitimize_argument (icode, 1, op0); | |
9477 | pat = GEN_FCN (icode) (target, op0, op1); | |
9478 | if (! pat) | |
9479 | return NULL_RTX; | |
9480 | ||
9481 | emit_insn (pat); | |
9482 | return target; | |
9483 | } | |
9484 | ||
9485 | /* Expand builtins that take two operands, the first operand being a pointer to | |
87b483a1 | 9486 | ints and return void. */ |
36a05131 BS |
9487 | |
9488 | static rtx | |
f2206911 | 9489 | frv_expand_voidbinop_builtin (enum insn_code icode, tree arglist) |
36a05131 BS |
9490 | { |
9491 | rtx pat; | |
9492 | rtx op0 = frv_read_argument (&arglist); | |
9493 | rtx op1 = frv_read_argument (&arglist); | |
9494 | enum machine_mode mode0 = insn_data[icode].operand[0].mode; | |
9495 | rtx addr; | |
9496 | ||
9497 | if (GET_CODE (op0) != MEM) | |
9498 | { | |
9499 | rtx reg = op0; | |
9500 | ||
9501 | if (! offsettable_address_p (0, mode0, op0)) | |
9502 | { | |
9503 | reg = gen_reg_rtx (Pmode); | |
9504 | emit_insn (gen_rtx_SET (VOIDmode, reg, op0)); | |
9505 | } | |
9506 | ||
9507 | op0 = gen_rtx_MEM (SImode, reg); | |
9508 | } | |
9509 | ||
9510 | addr = XEXP (op0, 0); | |
9511 | if (! offsettable_address_p (0, mode0, addr)) | |
9512 | addr = copy_to_mode_reg (Pmode, op0); | |
9513 | ||
9514 | op0 = change_address (op0, V4SImode, addr); | |
9515 | op1 = frv_legitimize_argument (icode, 1, op1); | |
9516 | pat = GEN_FCN (icode) (op0, op1); | |
9517 | if (! pat) | |
9518 | return 0; | |
9519 | ||
9520 | emit_insn (pat); | |
9521 | return 0; | |
9522 | } | |
9523 | ||
9524 | /* Expand builtins that take three operands and return void. The first | |
9525 | argument must be a constant that describes a pair or quad accumulators. A | |
9526 | fourth argument is created that is the accumulator guard register that | |
9527 | corresponds to the accumulator. */ | |
9528 | ||
9529 | static rtx | |
f2206911 | 9530 | frv_expand_voidtriop_builtin (enum insn_code icode, tree arglist) |
36a05131 BS |
9531 | { |
9532 | rtx pat; | |
9533 | rtx op0 = frv_read_argument (&arglist); | |
9534 | rtx op1 = frv_read_argument (&arglist); | |
9535 | rtx op2 = frv_read_argument (&arglist); | |
9536 | rtx op3; | |
9537 | ||
9538 | op0 = frv_int_to_acc (icode, 0, op0); | |
9539 | if (! op0) | |
9540 | return NULL_RTX; | |
9541 | ||
9542 | op1 = frv_legitimize_argument (icode, 1, op1); | |
9543 | op2 = frv_legitimize_argument (icode, 2, op2); | |
9544 | op3 = frv_matching_accg_for_acc (op0); | |
9545 | pat = GEN_FCN (icode) (op0, op1, op2, op3); | |
9546 | if (! pat) | |
9547 | return NULL_RTX; | |
9548 | ||
9549 | emit_insn (pat); | |
9550 | return NULL_RTX; | |
9551 | } | |
9552 | ||
9553 | /* Expand builtins that perform accumulator-to-accumulator operations. | |
9554 | These builtins take two accumulator numbers as argument and return | |
9555 | void. */ | |
9556 | ||
9557 | static rtx | |
f2206911 | 9558 | frv_expand_voidaccop_builtin (enum insn_code icode, tree arglist) |
36a05131 BS |
9559 | { |
9560 | rtx pat; | |
9561 | rtx op0 = frv_read_argument (&arglist); | |
9562 | rtx op1 = frv_read_argument (&arglist); | |
9563 | rtx op2; | |
9564 | rtx op3; | |
9565 | ||
9566 | op0 = frv_int_to_acc (icode, 0, op0); | |
9567 | if (! op0) | |
9568 | return NULL_RTX; | |
9569 | ||
9570 | op1 = frv_int_to_acc (icode, 1, op1); | |
9571 | if (! op1) | |
9572 | return NULL_RTX; | |
9573 | ||
9574 | op2 = frv_matching_accg_for_acc (op0); | |
9575 | op3 = frv_matching_accg_for_acc (op1); | |
9576 | pat = GEN_FCN (icode) (op0, op1, op2, op3); | |
9577 | if (! pat) | |
9578 | return NULL_RTX; | |
9579 | ||
9580 | emit_insn (pat); | |
9581 | return NULL_RTX; | |
9582 | } | |
9583 | ||
9584 | /* Expand the MCLRACC builtin. This builtin takes a single accumulator | |
9585 | number as argument. */ | |
9586 | ||
9587 | static rtx | |
f2206911 | 9588 | frv_expand_mclracc_builtin (tree arglist) |
36a05131 BS |
9589 | { |
9590 | enum insn_code icode = CODE_FOR_mclracc; | |
9591 | rtx pat; | |
9592 | rtx op0 = frv_read_argument (&arglist); | |
9593 | ||
9594 | op0 = frv_int_to_acc (icode, 0, op0); | |
9595 | if (! op0) | |
9596 | return NULL_RTX; | |
9597 | ||
9598 | pat = GEN_FCN (icode) (op0); | |
9599 | if (pat) | |
9600 | emit_insn (pat); | |
9601 | ||
9602 | return NULL_RTX; | |
9603 | } | |
9604 | ||
9605 | /* Expand builtins that take no arguments. */ | |
9606 | ||
9607 | static rtx | |
f2206911 | 9608 | frv_expand_noargs_builtin (enum insn_code icode) |
36a05131 | 9609 | { |
a556fd39 | 9610 | rtx pat = GEN_FCN (icode) (const0_rtx); |
36a05131 BS |
9611 | if (pat) |
9612 | emit_insn (pat); | |
9613 | ||
9614 | return NULL_RTX; | |
9615 | } | |
9616 | ||
9617 | /* Expand MRDACC and MRDACCG. These builtins take a single accumulator | |
9618 | number or accumulator guard number as argument and return an SI integer. */ | |
9619 | ||
9620 | static rtx | |
f2206911 | 9621 | frv_expand_mrdacc_builtin (enum insn_code icode, tree arglist) |
36a05131 BS |
9622 | { |
9623 | rtx pat; | |
9624 | rtx target = gen_reg_rtx (SImode); | |
9625 | rtx op0 = frv_read_argument (&arglist); | |
9626 | ||
9627 | op0 = frv_int_to_acc (icode, 1, op0); | |
9628 | if (! op0) | |
9629 | return NULL_RTX; | |
9630 | ||
9631 | pat = GEN_FCN (icode) (target, op0); | |
9632 | if (! pat) | |
9633 | return NULL_RTX; | |
9634 | ||
9635 | emit_insn (pat); | |
9636 | return target; | |
9637 | } | |
9638 | ||
9639 | /* Expand MWTACC and MWTACCG. These builtins take an accumulator or | |
9640 | accumulator guard as their first argument and an SImode value as their | |
9641 | second. */ | |
9642 | ||
9643 | static rtx | |
f2206911 | 9644 | frv_expand_mwtacc_builtin (enum insn_code icode, tree arglist) |
36a05131 BS |
9645 | { |
9646 | rtx pat; | |
9647 | rtx op0 = frv_read_argument (&arglist); | |
9648 | rtx op1 = frv_read_argument (&arglist); | |
9649 | ||
9650 | op0 = frv_int_to_acc (icode, 0, op0); | |
9651 | if (! op0) | |
9652 | return NULL_RTX; | |
9653 | ||
9654 | op1 = frv_legitimize_argument (icode, 1, op1); | |
9655 | pat = GEN_FCN (icode) (op0, op1); | |
9656 | if (pat) | |
9657 | emit_insn (pat); | |
9658 | ||
9659 | return NULL_RTX; | |
9660 | } | |
9661 | ||
87b483a1 | 9662 | /* Expand builtins. */ |
36a05131 | 9663 | |
14966b94 | 9664 | static rtx |
f2206911 KC |
9665 | frv_expand_builtin (tree exp, |
9666 | rtx target, | |
9667 | rtx subtarget ATTRIBUTE_UNUSED, | |
9668 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
9669 | int ignore ATTRIBUTE_UNUSED) | |
36a05131 BS |
9670 | { |
9671 | tree arglist = TREE_OPERAND (exp, 1); | |
9672 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
9673 | unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl); | |
9674 | unsigned i; | |
9675 | struct builtin_description *d; | |
9676 | ||
9677 | if (! TARGET_MEDIA) | |
9678 | { | |
9679 | error ("media functions are not available unless -mmedia is used"); | |
9680 | return NULL_RTX; | |
9681 | } | |
9682 | ||
9683 | switch (fcode) | |
9684 | { | |
9685 | case FRV_BUILTIN_MCOP1: | |
9686 | case FRV_BUILTIN_MCOP2: | |
9687 | case FRV_BUILTIN_MDUNPACKH: | |
9688 | case FRV_BUILTIN_MBTOHE: | |
9689 | if (! TARGET_MEDIA_REV1) | |
9690 | { | |
9691 | error ("this media function is only available on the fr500"); | |
9692 | return NULL_RTX; | |
9693 | } | |
9694 | break; | |
9695 | ||
9696 | case FRV_BUILTIN_MQXMACHS: | |
9697 | case FRV_BUILTIN_MQXMACXHS: | |
9698 | case FRV_BUILTIN_MQMACXHS: | |
9699 | case FRV_BUILTIN_MADDACCS: | |
9700 | case FRV_BUILTIN_MSUBACCS: | |
9701 | case FRV_BUILTIN_MASACCS: | |
9702 | case FRV_BUILTIN_MDADDACCS: | |
9703 | case FRV_BUILTIN_MDSUBACCS: | |
9704 | case FRV_BUILTIN_MDASACCS: | |
9705 | case FRV_BUILTIN_MABSHS: | |
9706 | case FRV_BUILTIN_MDROTLI: | |
9707 | case FRV_BUILTIN_MCPLHI: | |
9708 | case FRV_BUILTIN_MCPLI: | |
9709 | case FRV_BUILTIN_MDCUTSSI: | |
9710 | case FRV_BUILTIN_MQSATHS: | |
9711 | case FRV_BUILTIN_MHSETLOS: | |
9712 | case FRV_BUILTIN_MHSETLOH: | |
9713 | case FRV_BUILTIN_MHSETHIS: | |
9714 | case FRV_BUILTIN_MHSETHIH: | |
9715 | case FRV_BUILTIN_MHDSETS: | |
9716 | case FRV_BUILTIN_MHDSETH: | |
9717 | if (! TARGET_MEDIA_REV2) | |
9718 | { | |
9719 | error ("this media function is only available on the fr400"); | |
9720 | return NULL_RTX; | |
9721 | } | |
9722 | break; | |
9723 | ||
9724 | default: | |
9725 | break; | |
9726 | } | |
9727 | ||
87b483a1 | 9728 | /* Expand unique builtins. */ |
36a05131 BS |
9729 | |
9730 | switch (fcode) | |
9731 | { | |
9732 | case FRV_BUILTIN_MTRAP: | |
9733 | return frv_expand_noargs_builtin (CODE_FOR_mtrap); | |
9734 | ||
9735 | case FRV_BUILTIN_MCLRACC: | |
9736 | return frv_expand_mclracc_builtin (arglist); | |
9737 | ||
9738 | case FRV_BUILTIN_MCLRACCA: | |
9739 | if (TARGET_ACC_8) | |
9740 | return frv_expand_noargs_builtin (CODE_FOR_mclracca8); | |
9741 | else | |
9742 | return frv_expand_noargs_builtin (CODE_FOR_mclracca4); | |
9743 | ||
9744 | case FRV_BUILTIN_MRDACC: | |
9745 | return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, arglist); | |
9746 | ||
9747 | case FRV_BUILTIN_MRDACCG: | |
9748 | return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, arglist); | |
9749 | ||
9750 | case FRV_BUILTIN_MWTACC: | |
9751 | return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, arglist); | |
9752 | ||
9753 | case FRV_BUILTIN_MWTACCG: | |
9754 | return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, arglist); | |
9755 | ||
9756 | default: | |
9757 | break; | |
9758 | } | |
9759 | ||
87b483a1 | 9760 | /* Expand groups of builtins. */ |
36a05131 | 9761 | |
e97a46ce | 9762 | for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++) |
36a05131 BS |
9763 | if (d->code == fcode) |
9764 | return frv_expand_set_builtin (d->icode, arglist, target); | |
9765 | ||
e97a46ce | 9766 | for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
36a05131 BS |
9767 | if (d->code == fcode) |
9768 | return frv_expand_unop_builtin (d->icode, arglist, target); | |
9769 | ||
e97a46ce | 9770 | for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
36a05131 BS |
9771 | if (d->code == fcode) |
9772 | return frv_expand_binop_builtin (d->icode, arglist, target); | |
9773 | ||
e97a46ce | 9774 | for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++) |
36a05131 BS |
9775 | if (d->code == fcode) |
9776 | return frv_expand_cut_builtin (d->icode, arglist, target); | |
9777 | ||
e97a46ce KG |
9778 | for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++) |
9779 | if (d->code == fcode) | |
9780 | return frv_expand_binopimm_builtin (d->icode, arglist, target); | |
36a05131 | 9781 | |
e97a46ce KG |
9782 | for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++) |
9783 | if (d->code == fcode) | |
9784 | return frv_expand_voidbinop_builtin (d->icode, arglist); | |
36a05131 | 9785 | |
e97a46ce KG |
9786 | for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++) |
9787 | if (d->code == fcode) | |
9788 | return frv_expand_voidtriop_builtin (d->icode, arglist); | |
9789 | ||
9790 | for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++) | |
9791 | if (d->code == fcode) | |
9792 | return frv_expand_voidaccop_builtin (d->icode, arglist); | |
36a05131 | 9793 | |
36a05131 BS |
9794 | return 0; |
9795 | } | |
14966b94 | 9796 | |
b3fbfc07 | 9797 | static bool |
f2206911 | 9798 | frv_in_small_data_p (tree decl) |
b3fbfc07 | 9799 | { |
0f6e5d45 RH |
9800 | HOST_WIDE_INT size; |
9801 | tree section_name; | |
9802 | ||
9803 | /* Don't apply the -G flag to internal compiler structures. We | |
9804 | should leave such structures in the main data section, partly | |
9805 | for efficiency and partly because the size of some of them | |
9806 | (such as C++ typeinfos) is not known until later. */ | |
9807 | if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl)) | |
9808 | return false; | |
9809 | ||
0f6e5d45 RH |
9810 | /* If we already know which section the decl should be in, see if |
9811 | it's a small data section. */ | |
9812 | section_name = DECL_SECTION_NAME (decl); | |
9813 | if (section_name) | |
9814 | { | |
9815 | if (TREE_CODE (section_name) != STRING_CST) | |
9816 | abort (); | |
9817 | if (frv_string_begins_with (section_name, ".sdata")) | |
9818 | return true; | |
9819 | if (frv_string_begins_with (section_name, ".sbss")) | |
9820 | return true; | |
68c0ab4f | 9821 | return false; |
0f6e5d45 | 9822 | } |
b3fbfc07 | 9823 | |
68c0ab4f RS |
9824 | size = int_size_in_bytes (TREE_TYPE (decl)); |
9825 | if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value) | |
9826 | return true; | |
9827 | ||
0f6e5d45 | 9828 | return false; |
b3fbfc07 | 9829 | } |
3c50106f RH |
9830 | \f |
9831 | static bool | |
f2206911 KC |
9832 | frv_rtx_costs (rtx x, |
9833 | int code ATTRIBUTE_UNUSED, | |
9834 | int outer_code ATTRIBUTE_UNUSED, | |
9835 | int *total) | |
3c50106f | 9836 | { |
34208acf AO |
9837 | if (outer_code == MEM) |
9838 | { | |
9839 | /* Don't differentiate between memory addresses. All the ones | |
9840 | we accept have equal cost. */ | |
9841 | *total = COSTS_N_INSNS (0); | |
9842 | return true; | |
9843 | } | |
9844 | ||
3c50106f RH |
9845 | switch (code) |
9846 | { | |
9847 | case CONST_INT: | |
9848 | /* Make 12 bit integers really cheap. */ | |
9849 | if (IN_RANGE_P (INTVAL (x), -2048, 2047)) | |
9850 | { | |
9851 | *total = 0; | |
9852 | return true; | |
9853 | } | |
87b483a1 | 9854 | /* Fall through. */ |
3c50106f RH |
9855 | |
9856 | case CONST: | |
9857 | case LABEL_REF: | |
9858 | case SYMBOL_REF: | |
9859 | case CONST_DOUBLE: | |
9860 | *total = COSTS_N_INSNS (2); | |
9861 | return true; | |
9862 | ||
9863 | case PLUS: | |
9864 | case MINUS: | |
9865 | case AND: | |
9866 | case IOR: | |
9867 | case XOR: | |
9868 | case ASHIFT: | |
9869 | case ASHIFTRT: | |
9870 | case LSHIFTRT: | |
9871 | case NOT: | |
9872 | case NEG: | |
9873 | case COMPARE: | |
9874 | if (GET_MODE (x) == SImode) | |
9875 | *total = COSTS_N_INSNS (1); | |
9876 | else if (GET_MODE (x) == DImode) | |
9877 | *total = COSTS_N_INSNS (2); | |
9878 | else | |
9879 | *total = COSTS_N_INSNS (3); | |
9880 | return true; | |
9881 | ||
9882 | case MULT: | |
9883 | if (GET_MODE (x) == SImode) | |
9884 | *total = COSTS_N_INSNS (2); | |
9885 | else | |
9886 | *total = COSTS_N_INSNS (6); /* guess */ | |
9887 | return true; | |
9888 | ||
9889 | case DIV: | |
9890 | case UDIV: | |
9891 | case MOD: | |
9892 | case UMOD: | |
9893 | *total = COSTS_N_INSNS (18); | |
9894 | return true; | |
9895 | ||
34208acf AO |
9896 | case MEM: |
9897 | *total = COSTS_N_INSNS (3); | |
9898 | return true; | |
9899 | ||
3c50106f RH |
9900 | default: |
9901 | return false; | |
9902 | } | |
9903 | } | |
90a63880 RH |
9904 | \f |
9905 | static void | |
f2206911 | 9906 | frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED) |
90a63880 RH |
9907 | { |
9908 | ctors_section (); | |
9909 | assemble_align (POINTER_SIZE); | |
34208acf AO |
9910 | if (TARGET_FDPIC) |
9911 | { | |
9912 | if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1)) | |
9913 | abort (); | |
9914 | return; | |
9915 | } | |
90a63880 RH |
9916 | assemble_integer_with_op ("\t.picptr\t", symbol); |
9917 | } | |
9918 | ||
9919 | static void | |
f2206911 | 9920 | frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED) |
90a63880 RH |
9921 | { |
9922 | dtors_section (); | |
9923 | assemble_align (POINTER_SIZE); | |
34208acf AO |
9924 | if (TARGET_FDPIC) |
9925 | { | |
9926 | if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1)) | |
9927 | abort (); | |
9928 | return; | |
9929 | } | |
90a63880 RH |
9930 | assemble_integer_with_op ("\t.picptr\t", symbol); |
9931 | } | |
8ac411c7 KH |
9932 | |
9933 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ | |
9934 | ||
9935 | static rtx | |
9936 | frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
9937 | int incoming ATTRIBUTE_UNUSED) | |
9938 | { | |
9939 | return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM); | |
9940 | } |