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34208acf | 1 | /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004 |
8ac411c7 | 2 | Free Software Foundation, Inc. |
36a05131 BS |
3 | Contributed by Red Hat, Inc. |
4 | ||
7ec022b2 | 5 | This file is part of GCC. |
36a05131 | 6 | |
7ec022b2 | 7 | GCC is free software; you can redistribute it and/or modify |
36a05131 BS |
8 | it under the terms of the GNU General Public License as published by |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
7ec022b2 | 12 | GCC is distributed in the hope that it will be useful, |
36a05131 BS |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
7ec022b2 | 18 | along with GCC; see the file COPYING. If not, write to |
36a05131 BS |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #include "config.h" | |
23 | #include "system.h" | |
4977bab6 ZW |
24 | #include "coretypes.h" |
25 | #include "tm.h" | |
36a05131 BS |
26 | #include "rtl.h" |
27 | #include "tree.h" | |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
33 | #include "insn-flags.h" | |
34 | #include "output.h" | |
35 | #include "insn-attr.h" | |
36 | #include "flags.h" | |
37 | #include "recog.h" | |
38 | #include "reload.h" | |
39 | #include "expr.h" | |
40 | #include "obstack.h" | |
41 | #include "except.h" | |
42 | #include "function.h" | |
43 | #include "optabs.h" | |
44 | #include "toplev.h" | |
45 | #include "basic-block.h" | |
46 | #include "tm_p.h" | |
47 | #include "ggc.h" | |
48 | #include <ctype.h> | |
49 | #include "target.h" | |
50 | #include "target-def.h" | |
8cd5a4e0 | 51 | #include "targhooks.h" |
34208acf | 52 | #include "integrate.h" |
6e34d3a3 | 53 | #include "langhooks.h" |
36a05131 BS |
54 | |
55 | #ifndef FRV_INLINE | |
56 | #define FRV_INLINE inline | |
57 | #endif | |
58 | ||
c557edf4 RS |
59 | /* The maximum number of distinct NOP patterns. There are three: |
60 | nop, fnop and mnop. */ | |
61 | #define NUM_NOP_PATTERNS 3 | |
62 | ||
63 | /* Classification of instructions and units: integer, floating-point/media, | |
64 | branch and control. */ | |
65 | enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS }; | |
66 | ||
67 | /* The DFA names of the units, in packet order. */ | |
68 | static const char *const frv_unit_names[] = | |
69 | { | |
70 | "c", | |
71 | "i0", "f0", | |
72 | "i1", "f1", | |
73 | "i2", "f2", | |
74 | "i3", "f3", | |
75 | "b0", "b1" | |
76 | }; | |
77 | ||
78 | /* The classification of each unit in frv_unit_names[]. */ | |
79 | static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] = | |
80 | { | |
81 | GROUP_C, | |
82 | GROUP_I, GROUP_FM, | |
83 | GROUP_I, GROUP_FM, | |
84 | GROUP_I, GROUP_FM, | |
85 | GROUP_I, GROUP_FM, | |
86 | GROUP_B, GROUP_B | |
87 | }; | |
88 | ||
89 | /* Return the DFA unit code associated with the Nth unit of integer | |
90 | or floating-point group GROUP, */ | |
91 | #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1] | |
92 | ||
93 | /* Return the number of integer or floating-point unit UNIT | |
94 | (1 for I1, 2 for F2, etc.). */ | |
95 | #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2) | |
96 | ||
97 | /* The DFA unit number for each unit in frv_unit_names[]. */ | |
98 | static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)]; | |
99 | ||
100 | /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue | |
101 | an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if | |
102 | no instruction of type T has been seen. */ | |
103 | static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1]; | |
104 | ||
105 | /* An array of dummy nop INSNs, one for each type of nop that the | |
106 | target supports. */ | |
107 | static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS]; | |
108 | ||
109 | /* The number of nop instructions in frv_nops[]. */ | |
110 | static unsigned int frv_num_nops; | |
111 | ||
112 | /* Return true if instruction INSN should be packed with the following | |
113 | instruction. */ | |
114 | #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode) | |
115 | ||
116 | /* Set the value of PACKING_FLAG_P(INSN). */ | |
117 | #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode) | |
118 | #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode) | |
119 | ||
120 | /* Loop with REG set to each hard register in rtx X. */ | |
121 | #define FOR_EACH_REGNO(REG, X) \ | |
122 | for (REG = REGNO (X); \ | |
123 | REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \ | |
124 | REG++) | |
125 | ||
34208acf AO |
126 | /* Information about a relocation unspec. SYMBOL is the relocation symbol |
127 | (a SYMBOL_REF or LABEL_REF), RELOC is the type of relocation and OFFSET | |
128 | is the constant addend. */ | |
129 | struct frv_unspec { | |
130 | rtx symbol; | |
131 | int reloc; | |
132 | HOST_WIDE_INT offset; | |
133 | }; | |
134 | ||
36a05131 BS |
135 | /* Temporary register allocation support structure. */ |
136 | typedef struct frv_tmp_reg_struct | |
137 | { | |
138 | HARD_REG_SET regs; /* possible registers to allocate */ | |
139 | int next_reg[N_REG_CLASSES]; /* next register to allocate per class */ | |
140 | } | |
141 | frv_tmp_reg_t; | |
142 | ||
c557edf4 | 143 | /* Register state information for VLIW re-packing phase. */ |
36a05131 | 144 | #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */ |
c557edf4 RS |
145 | #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */ |
146 | #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */ | |
147 | #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */ | |
148 | ||
36a05131 BS |
149 | #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE) |
150 | ||
c557edf4 | 151 | typedef unsigned char regstate_t; |
36a05131 BS |
152 | |
153 | /* Used in frv_frame_accessor_t to indicate the direction of a register-to- | |
154 | memory move. */ | |
155 | enum frv_stack_op | |
156 | { | |
157 | FRV_LOAD, | |
158 | FRV_STORE | |
159 | }; | |
160 | ||
161 | /* Information required by frv_frame_access. */ | |
162 | typedef struct | |
163 | { | |
164 | /* This field is FRV_LOAD if registers are to be loaded from the stack and | |
165 | FRV_STORE if they should be stored onto the stack. FRV_STORE implies | |
166 | the move is being done by the prologue code while FRV_LOAD implies it | |
167 | is being done by the epilogue. */ | |
168 | enum frv_stack_op op; | |
169 | ||
170 | /* The base register to use when accessing the stack. This may be the | |
171 | frame pointer, stack pointer, or a temporary. The choice of register | |
172 | depends on which part of the frame is being accessed and how big the | |
173 | frame is. */ | |
174 | rtx base; | |
175 | ||
176 | /* The offset of BASE from the bottom of the current frame, in bytes. */ | |
177 | int base_offset; | |
178 | } frv_frame_accessor_t; | |
179 | ||
180 | /* Define the information needed to generate branch and scc insns. This is | |
181 | stored from the compare operation. */ | |
182 | rtx frv_compare_op0; | |
183 | rtx frv_compare_op1; | |
184 | ||
87b483a1 | 185 | /* Conditional execution support gathered together in one structure. */ |
36a05131 BS |
186 | typedef struct |
187 | { | |
188 | /* Linked list of insns to add if the conditional execution conversion was | |
189 | successful. Each link points to an EXPR_LIST which points to the pattern | |
190 | of the insn to add, and the insn to be inserted before. */ | |
191 | rtx added_insns_list; | |
192 | ||
193 | /* Identify which registers are safe to allocate for if conversions to | |
194 | conditional execution. We keep the last allocated register in the | |
195 | register classes between COND_EXEC statements. This will mean we allocate | |
196 | different registers for each different COND_EXEC group if we can. This | |
197 | might allow the scheduler to intermix two different COND_EXEC sections. */ | |
198 | frv_tmp_reg_t tmp_reg; | |
199 | ||
200 | /* For nested IFs, identify which CC registers are used outside of setting | |
201 | via a compare isnsn, and using via a check insn. This will allow us to | |
202 | know if we can rewrite the register to use a different register that will | |
203 | be paired with the CR register controlling the nested IF-THEN blocks. */ | |
204 | HARD_REG_SET nested_cc_ok_rewrite; | |
205 | ||
206 | /* Temporary registers allocated to hold constants during conditional | |
207 | execution. */ | |
208 | rtx scratch_regs[FIRST_PSEUDO_REGISTER]; | |
209 | ||
210 | /* Current number of temp registers available. */ | |
211 | int cur_scratch_regs; | |
212 | ||
87b483a1 | 213 | /* Number of nested conditional execution blocks. */ |
36a05131 BS |
214 | int num_nested_cond_exec; |
215 | ||
216 | /* Map of insns that set up constants in scratch registers. */ | |
217 | bitmap scratch_insns_bitmap; | |
218 | ||
87b483a1 | 219 | /* Conditional execution test register (CC0..CC7). */ |
36a05131 BS |
220 | rtx cr_reg; |
221 | ||
222 | /* Conditional execution compare register that is paired with cr_reg, so that | |
223 | nested compares can be done. The csubcc and caddcc instructions don't | |
224 | have enough bits to specify both a CC register to be set and a CR register | |
225 | to do the test on, so the same bit number is used for both. Needless to | |
839a4992 | 226 | say, this is rather inconvenient for GCC. */ |
36a05131 BS |
227 | rtx nested_cc_reg; |
228 | ||
229 | /* Extra CR registers used for &&, ||. */ | |
230 | rtx extra_int_cr; | |
231 | rtx extra_fp_cr; | |
232 | ||
233 | /* Previous CR used in nested if, to make sure we are dealing with the same | |
87b483a1 | 234 | nested if as the previous statement. */ |
36a05131 BS |
235 | rtx last_nested_if_cr; |
236 | } | |
237 | frv_ifcvt_t; | |
238 | ||
239 | static /* GTY(()) */ frv_ifcvt_t frv_ifcvt; | |
240 | ||
241 | /* Map register number to smallest register class. */ | |
242 | enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; | |
243 | ||
87b483a1 | 244 | /* Map class letter into register class. */ |
36a05131 BS |
245 | enum reg_class reg_class_from_letter[256]; |
246 | ||
87b483a1 | 247 | /* Cached value of frv_stack_info. */ |
36a05131 BS |
248 | static frv_stack_t *frv_stack_cache = (frv_stack_t *)0; |
249 | ||
250 | /* -mbranch-cost= support */ | |
251 | const char *frv_branch_cost_string; | |
252 | int frv_branch_cost_int = DEFAULT_BRANCH_COST; | |
253 | ||
254 | /* -mcpu= support */ | |
255 | const char *frv_cpu_string; /* -mcpu= option */ | |
256 | frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */ | |
257 | ||
258 | /* -mcond-exec-insns= support */ | |
259 | const char *frv_condexec_insns_str; /* -mcond-exec-insns= option */ | |
260 | int frv_condexec_insns = DEFAULT_CONDEXEC_INSNS; /* value of -mcond-exec-insns*/ | |
261 | ||
262 | /* -mcond-exec-temps= support */ | |
263 | const char *frv_condexec_temps_str; /* -mcond-exec-temps= option */ | |
264 | int frv_condexec_temps = DEFAULT_CONDEXEC_TEMPS; /* value of -mcond-exec-temps*/ | |
265 | ||
266 | /* -msched-lookahead=n */ | |
267 | const char *frv_sched_lookahead_str; /* -msched-lookahead=n */ | |
268 | int frv_sched_lookahead = 4; /* -msched-lookahead=n */ | |
269 | ||
270 | /* Forward references */ | |
f2206911 KC |
271 | static int frv_default_flags_for_cpu (void); |
272 | static int frv_string_begins_with (tree, const char *); | |
34208acf AO |
273 | static FRV_INLINE bool frv_small_data_reloc_p (rtx, int); |
274 | static FRV_INLINE bool frv_const_unspec_p (rtx, struct frv_unspec *); | |
36a05131 | 275 | static void frv_print_operand_memory_reference_reg |
f2206911 KC |
276 | (FILE *, rtx); |
277 | static void frv_print_operand_memory_reference (FILE *, rtx, int); | |
278 | static int frv_print_operand_jump_hint (rtx); | |
279 | static FRV_INLINE int frv_regno_ok_for_base_p (int, int); | |
280 | static rtx single_set_pattern (rtx); | |
281 | static int frv_function_contains_far_jump (void); | |
282 | static rtx frv_alloc_temp_reg (frv_tmp_reg_t *, | |
283 | enum reg_class, | |
284 | enum machine_mode, | |
285 | int, int); | |
286 | static rtx frv_frame_offset_rtx (int); | |
287 | static rtx frv_frame_mem (enum machine_mode, rtx, int); | |
288 | static rtx frv_dwarf_store (rtx, int); | |
289 | static void frv_frame_insn (rtx, rtx); | |
290 | static void frv_frame_access (frv_frame_accessor_t*, | |
291 | rtx, int); | |
292 | static void frv_frame_access_multi (frv_frame_accessor_t*, | |
293 | frv_stack_t *, int); | |
294 | static void frv_frame_access_standard_regs (enum frv_stack_op, | |
295 | frv_stack_t *); | |
296 | static struct machine_function *frv_init_machine_status (void); | |
297 | static int frv_legitimate_memory_operand (rtx, enum machine_mode, int); | |
298 | static rtx frv_int_to_acc (enum insn_code, int, rtx); | |
299 | static enum machine_mode frv_matching_accg_mode (enum machine_mode); | |
300 | static rtx frv_read_argument (tree *); | |
c557edf4 | 301 | static rtx frv_read_iacc_argument (enum machine_mode, tree *); |
f2206911 KC |
302 | static int frv_check_constant_argument (enum insn_code, int, rtx); |
303 | static rtx frv_legitimize_target (enum insn_code, rtx); | |
304 | static rtx frv_legitimize_argument (enum insn_code, int, rtx); | |
305 | static rtx frv_expand_set_builtin (enum insn_code, tree, rtx); | |
306 | static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx); | |
307 | static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx); | |
308 | static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx); | |
309 | static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx); | |
310 | static rtx frv_expand_voidbinop_builtin (enum insn_code, tree); | |
c557edf4 RS |
311 | static rtx frv_expand_int_void2arg (enum insn_code, tree); |
312 | static rtx frv_expand_prefetches (enum insn_code, tree); | |
f2206911 KC |
313 | static rtx frv_expand_voidtriop_builtin (enum insn_code, tree); |
314 | static rtx frv_expand_voidaccop_builtin (enum insn_code, tree); | |
315 | static rtx frv_expand_mclracc_builtin (tree); | |
316 | static rtx frv_expand_mrdacc_builtin (enum insn_code, tree); | |
317 | static rtx frv_expand_mwtacc_builtin (enum insn_code, tree); | |
318 | static rtx frv_expand_noargs_builtin (enum insn_code); | |
c557edf4 | 319 | static void frv_split_iacc_move (rtx, rtx); |
f2206911 KC |
320 | static rtx frv_emit_comparison (enum rtx_code, rtx, rtx); |
321 | static int frv_clear_registers_used (rtx *, void *); | |
322 | static void frv_ifcvt_add_insn (rtx, rtx, int); | |
323 | static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx); | |
324 | static rtx frv_ifcvt_load_value (rtx, rtx); | |
c557edf4 RS |
325 | static int frv_acc_group_1 (rtx *, void *); |
326 | static unsigned int frv_insn_unit (rtx); | |
327 | static bool frv_issues_to_branch_unit_p (rtx); | |
328 | static int frv_cond_flags (rtx); | |
329 | static bool frv_regstate_conflict_p (regstate_t, regstate_t); | |
330 | static int frv_registers_conflict_p_1 (rtx *, void *); | |
331 | static bool frv_registers_conflict_p (rtx); | |
332 | static void frv_registers_update_1 (rtx, rtx, void *); | |
333 | static void frv_registers_update (rtx); | |
334 | static void frv_start_packet (void); | |
335 | static void frv_start_packet_block (void); | |
336 | static void frv_finish_packet (void (*) (void)); | |
337 | static bool frv_pack_insn_p (rtx); | |
338 | static void frv_add_insn_to_packet (rtx); | |
339 | static void frv_insert_nop_in_packet (rtx); | |
340 | static bool frv_for_each_packet (void (*) (void)); | |
341 | static bool frv_sort_insn_group_1 (enum frv_insn_group, | |
342 | unsigned int, unsigned int, | |
343 | unsigned int, unsigned int, | |
344 | state_t); | |
345 | static int frv_compare_insns (const void *, const void *); | |
346 | static void frv_sort_insn_group (enum frv_insn_group); | |
347 | static void frv_reorder_packet (void); | |
348 | static void frv_fill_unused_units (enum frv_insn_group); | |
349 | static void frv_align_label (void); | |
350 | static void frv_reorg_packet (void); | |
351 | static void frv_register_nop (rtx); | |
352 | static void frv_reorg (void); | |
f2206911 KC |
353 | static void frv_pack_insns (void); |
354 | static void frv_function_prologue (FILE *, HOST_WIDE_INT); | |
355 | static void frv_function_epilogue (FILE *, HOST_WIDE_INT); | |
356 | static bool frv_assemble_integer (rtx, unsigned, int); | |
357 | static void frv_init_builtins (void); | |
358 | static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
359 | static void frv_init_libfuncs (void); | |
360 | static bool frv_in_small_data_p (tree); | |
3961e8fe | 361 | static void frv_asm_output_mi_thunk |
f2206911 | 362 | (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree); |
d8c2bed3 KH |
363 | static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *, |
364 | enum machine_mode, | |
365 | tree, int *, int); | |
8ac411c7 | 366 | static rtx frv_expand_builtin_saveregs (void); |
f2206911 KC |
367 | static bool frv_rtx_costs (rtx, int, int, int*); |
368 | static void frv_asm_out_constructor (rtx, int); | |
369 | static void frv_asm_out_destructor (rtx, int); | |
34208acf AO |
370 | static bool frv_function_symbol_referenced_p (rtx); |
371 | static bool frv_cannot_force_const_mem (rtx); | |
372 | static const char *unspec_got_name (int); | |
373 | static void frv_output_const_unspec (FILE *, | |
374 | const struct frv_unspec *); | |
764678d1 | 375 | static bool frv_function_ok_for_sibcall (tree, tree); |
8ac411c7 | 376 | static rtx frv_struct_value_rtx (tree, int); |
fe984136 | 377 | static bool frv_must_pass_in_stack (enum machine_mode mode, tree type); |
36a05131 BS |
378 | \f |
379 | /* Initialize the GCC target structure. */ | |
380 | #undef TARGET_ASM_FUNCTION_PROLOGUE | |
381 | #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue | |
382 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
383 | #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue | |
384 | #undef TARGET_ASM_INTEGER | |
385 | #define TARGET_ASM_INTEGER frv_assemble_integer | |
14966b94 KG |
386 | #undef TARGET_INIT_BUILTINS |
387 | #define TARGET_INIT_BUILTINS frv_init_builtins | |
388 | #undef TARGET_EXPAND_BUILTIN | |
389 | #define TARGET_EXPAND_BUILTIN frv_expand_builtin | |
c15c90bb ZW |
390 | #undef TARGET_INIT_LIBFUNCS |
391 | #define TARGET_INIT_LIBFUNCS frv_init_libfuncs | |
b3fbfc07 KG |
392 | #undef TARGET_IN_SMALL_DATA_P |
393 | #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p | |
3c50106f RH |
394 | #undef TARGET_RTX_COSTS |
395 | #define TARGET_RTX_COSTS frv_rtx_costs | |
90a63880 RH |
396 | #undef TARGET_ASM_CONSTRUCTOR |
397 | #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor | |
398 | #undef TARGET_ASM_DESTRUCTOR | |
399 | #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor | |
36a05131 | 400 | |
c590b625 RH |
401 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
402 | #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk | |
3961e8fe RH |
403 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
404 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
c590b625 | 405 | |
28a60850 RS |
406 | #undef TARGET_SCHED_ISSUE_RATE |
407 | #define TARGET_SCHED_ISSUE_RATE frv_issue_rate | |
ffb344c1 | 408 | |
764678d1 AO |
409 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
410 | #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall | |
34208acf AO |
411 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
412 | #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem | |
413 | ||
8ac411c7 KH |
414 | #undef TARGET_STRUCT_VALUE_RTX |
415 | #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx | |
fe984136 RH |
416 | #undef TARGET_MUST_PASS_IN_STACK |
417 | #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack | |
8cd5a4e0 RH |
418 | #undef TARGET_PASS_BY_REFERENCE |
419 | #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack | |
8ac411c7 KH |
420 | |
421 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
422 | #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs | |
d8c2bed3 KH |
423 | #undef TARGET_SETUP_INCOMING_VARARGS |
424 | #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs | |
c557edf4 RS |
425 | #undef TARGET_MACHINE_DEPENDENT_REORG |
426 | #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg | |
8ac411c7 | 427 | |
36a05131 BS |
428 | struct gcc_target targetm = TARGET_INITIALIZER; |
429 | \f | |
764678d1 AO |
430 | /* Any function call that satisfies the machine-independent |
431 | requirements is eligible on FR-V. */ | |
432 | ||
433 | static bool | |
434 | frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED, | |
435 | tree exp ATTRIBUTE_UNUSED) | |
436 | { | |
437 | return true; | |
438 | } | |
439 | ||
34208acf AO |
440 | /* Return true if SYMBOL is a small data symbol and relocation RELOC |
441 | can be used to access it directly in a load or store. */ | |
36a05131 | 442 | |
34208acf AO |
443 | static FRV_INLINE bool |
444 | frv_small_data_reloc_p (rtx symbol, int reloc) | |
36a05131 | 445 | { |
34208acf AO |
446 | return (GET_CODE (symbol) == SYMBOL_REF |
447 | && SYMBOL_REF_SMALL_P (symbol) | |
448 | && (!TARGET_FDPIC || flag_pic == 1) | |
449 | && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12)); | |
450 | } | |
36a05131 | 451 | |
34208acf AO |
452 | /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC |
453 | appropriately. */ | |
36a05131 | 454 | |
34208acf AO |
455 | static FRV_INLINE bool |
456 | frv_const_unspec_p (rtx x, struct frv_unspec *unspec) | |
457 | { | |
458 | if (GET_CODE (x) == CONST) | |
459 | { | |
460 | unspec->offset = 0; | |
461 | x = XEXP (x, 0); | |
462 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
463 | { | |
464 | unspec->offset += INTVAL (XEXP (x, 1)); | |
465 | x = XEXP (x, 0); | |
466 | } | |
467 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT) | |
468 | { | |
469 | unspec->symbol = XVECEXP (x, 0, 0); | |
470 | unspec->reloc = INTVAL (XVECEXP (x, 0, 1)); | |
36a05131 | 471 | |
34208acf AO |
472 | if (unspec->offset == 0) |
473 | return true; | |
36a05131 | 474 | |
34208acf AO |
475 | if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc) |
476 | && unspec->offset > 0 | |
477 | && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value) | |
478 | return true; | |
479 | } | |
480 | } | |
481 | return false; | |
36a05131 BS |
482 | } |
483 | ||
34208acf AO |
484 | /* Decide whether we can force certain constants to memory. If we |
485 | decide we can't, the caller should be able to cope with it in | |
486 | another way. | |
36a05131 | 487 | |
34208acf AO |
488 | We never allow constants to be forced into memory for TARGET_FDPIC. |
489 | This is necessary for several reasons: | |
36a05131 | 490 | |
34208acf AO |
491 | 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the |
492 | target-independent code will try to force them into the constant | |
493 | pool, thus leading to infinite recursion. | |
36a05131 | 494 | |
34208acf AO |
495 | 2. We can never introduce new constant pool references during reload. |
496 | Any such reference would require use of the pseudo FDPIC register. | |
36a05131 | 497 | |
34208acf AO |
498 | 3. We can't represent a constant added to a function pointer (which is |
499 | not the same as a pointer to a function+constant). | |
500 | ||
501 | 4. In many cases, it's more efficient to calculate the constant in-line. */ | |
502 | ||
503 | static bool | |
504 | frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED) | |
505 | { | |
506 | return TARGET_FDPIC; | |
507 | } | |
36a05131 BS |
508 | \f |
509 | static int | |
f2206911 | 510 | frv_default_flags_for_cpu (void) |
36a05131 BS |
511 | { |
512 | switch (frv_cpu_type) | |
513 | { | |
514 | case FRV_CPU_GENERIC: | |
515 | return MASK_DEFAULT_FRV; | |
516 | ||
c557edf4 RS |
517 | case FRV_CPU_FR550: |
518 | return MASK_DEFAULT_FR550; | |
519 | ||
36a05131 BS |
520 | case FRV_CPU_FR500: |
521 | case FRV_CPU_TOMCAT: | |
522 | return MASK_DEFAULT_FR500; | |
523 | ||
c557edf4 RS |
524 | case FRV_CPU_FR450: |
525 | return MASK_DEFAULT_FR450; | |
526 | ||
527 | case FRV_CPU_FR405: | |
36a05131 BS |
528 | case FRV_CPU_FR400: |
529 | return MASK_DEFAULT_FR400; | |
530 | ||
531 | case FRV_CPU_FR300: | |
532 | case FRV_CPU_SIMPLE: | |
533 | return MASK_DEFAULT_SIMPLE; | |
534 | } | |
535 | abort (); | |
536 | } | |
537 | ||
538 | /* Sometimes certain combinations of command options do not make | |
539 | sense on a particular target machine. You can define a macro | |
540 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
541 | defined, is executed once just after all the command options have | |
542 | been parsed. | |
543 | ||
544 | Don't use this macro to turn on various extra optimizations for | |
545 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
546 | ||
547 | void | |
f2206911 | 548 | frv_override_options (void) |
36a05131 | 549 | { |
c557edf4 RS |
550 | int regno; |
551 | unsigned int i; | |
36a05131 | 552 | |
87b483a1 | 553 | /* Set the cpu type. */ |
36a05131 BS |
554 | if (frv_cpu_string) |
555 | { | |
556 | if (strcmp (frv_cpu_string, "simple") == 0) | |
557 | frv_cpu_type = FRV_CPU_SIMPLE; | |
558 | ||
559 | else if (strcmp (frv_cpu_string, "tomcat") == 0) | |
560 | frv_cpu_type = FRV_CPU_TOMCAT; | |
561 | ||
562 | else if (strncmp (frv_cpu_string, "fr", sizeof ("fr")-1) != 0) | |
563 | error ("Unknown cpu: -mcpu=%s", frv_cpu_string); | |
564 | ||
565 | else | |
566 | { | |
567 | const char *p = frv_cpu_string + sizeof ("fr") - 1; | |
c557edf4 RS |
568 | if (strcmp (p, "550") == 0) |
569 | frv_cpu_type = FRV_CPU_FR550; | |
570 | ||
571 | else if (strcmp (p, "500") == 0) | |
36a05131 BS |
572 | frv_cpu_type = FRV_CPU_FR500; |
573 | ||
c557edf4 RS |
574 | else if (strcmp (p, "450") == 0) |
575 | frv_cpu_type = FRV_CPU_FR450; | |
576 | ||
577 | else if (strcmp (p, "405") == 0) | |
578 | frv_cpu_type = FRV_CPU_FR405; | |
579 | ||
36a05131 BS |
580 | else if (strcmp (p, "400") == 0) |
581 | frv_cpu_type = FRV_CPU_FR400; | |
582 | ||
583 | else if (strcmp (p, "300") == 0) | |
584 | frv_cpu_type = FRV_CPU_FR300; | |
585 | ||
586 | else if (strcmp (p, "v") == 0) | |
587 | frv_cpu_type = FRV_CPU_GENERIC; | |
588 | ||
589 | else | |
590 | error ("Unknown cpu: -mcpu=%s", frv_cpu_string); | |
591 | } | |
592 | } | |
593 | ||
594 | target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit); | |
595 | ||
596 | /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the | |
597 | linker about linking pic and non-pic code. */ | |
598 | if (TARGET_LIBPIC) | |
599 | { | |
600 | if (!flag_pic) /* -fPIC */ | |
601 | flag_pic = 2; | |
602 | ||
603 | if (! g_switch_set) /* -G0 */ | |
604 | { | |
605 | g_switch_set = 1; | |
606 | g_switch_value = 0; | |
607 | } | |
608 | } | |
609 | ||
87b483a1 | 610 | /* Change the branch cost value. */ |
36a05131 BS |
611 | if (frv_branch_cost_string) |
612 | frv_branch_cost_int = atoi (frv_branch_cost_string); | |
613 | ||
87b483a1 | 614 | /* Change the # of insns to be converted to conditional execution. */ |
36a05131 BS |
615 | if (frv_condexec_insns_str) |
616 | frv_condexec_insns = atoi (frv_condexec_insns_str); | |
617 | ||
87b483a1 | 618 | /* Change # of temporary registers used to hold integer constants. */ |
36a05131 BS |
619 | if (frv_condexec_temps_str) |
620 | frv_condexec_temps = atoi (frv_condexec_temps_str); | |
621 | ||
87b483a1 | 622 | /* Change scheduling look ahead. */ |
36a05131 BS |
623 | if (frv_sched_lookahead_str) |
624 | frv_sched_lookahead = atoi (frv_sched_lookahead_str); | |
625 | ||
626 | /* A C expression whose value is a register class containing hard | |
627 | register REGNO. In general there is more than one such class; | |
628 | choose a class which is "minimal", meaning that no smaller class | |
87b483a1 | 629 | also contains the register. */ |
36a05131 BS |
630 | |
631 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
632 | { | |
633 | enum reg_class class; | |
634 | ||
635 | if (GPR_P (regno)) | |
636 | { | |
637 | int gpr_reg = regno - GPR_FIRST; | |
638 | if ((gpr_reg & 3) == 0) | |
639 | class = QUAD_REGS; | |
640 | ||
641 | else if ((gpr_reg & 1) == 0) | |
642 | class = EVEN_REGS; | |
643 | ||
644 | else | |
645 | class = GPR_REGS; | |
646 | } | |
647 | ||
648 | else if (FPR_P (regno)) | |
649 | { | |
650 | int fpr_reg = regno - GPR_FIRST; | |
651 | if ((fpr_reg & 3) == 0) | |
652 | class = QUAD_FPR_REGS; | |
653 | ||
654 | else if ((fpr_reg & 1) == 0) | |
655 | class = FEVEN_REGS; | |
656 | ||
657 | else | |
658 | class = FPR_REGS; | |
659 | } | |
660 | ||
661 | else if (regno == LR_REGNO) | |
662 | class = LR_REG; | |
663 | ||
664 | else if (regno == LCR_REGNO) | |
665 | class = LCR_REG; | |
666 | ||
667 | else if (ICC_P (regno)) | |
668 | class = ICC_REGS; | |
669 | ||
670 | else if (FCC_P (regno)) | |
671 | class = FCC_REGS; | |
672 | ||
673 | else if (ICR_P (regno)) | |
674 | class = ICR_REGS; | |
675 | ||
676 | else if (FCR_P (regno)) | |
677 | class = FCR_REGS; | |
678 | ||
679 | else if (ACC_P (regno)) | |
680 | { | |
681 | int r = regno - ACC_FIRST; | |
682 | if ((r & 3) == 0) | |
683 | class = QUAD_ACC_REGS; | |
684 | else if ((r & 1) == 0) | |
685 | class = EVEN_ACC_REGS; | |
686 | else | |
687 | class = ACC_REGS; | |
688 | } | |
689 | ||
690 | else if (ACCG_P (regno)) | |
691 | class = ACCG_REGS; | |
692 | ||
693 | else | |
694 | class = NO_REGS; | |
695 | ||
696 | regno_reg_class[regno] = class; | |
697 | } | |
698 | ||
699 | /* Check for small data option */ | |
700 | if (!g_switch_set) | |
701 | g_switch_value = SDATA_DEFAULT_SIZE; | |
702 | ||
703 | /* A C expression which defines the machine-dependent operand | |
704 | constraint letters for register classes. If CHAR is such a | |
705 | letter, the value should be the register class corresponding to | |
706 | it. Otherwise, the value should be `NO_REGS'. The register | |
707 | letter `r', corresponding to class `GENERAL_REGS', will not be | |
708 | passed to this macro; you do not need to handle it. | |
709 | ||
710 | The following letters are unavailable, due to being used as | |
711 | constraints: | |
712 | '0'..'9' | |
713 | '<', '>' | |
714 | 'E', 'F', 'G', 'H' | |
715 | 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P' | |
716 | 'Q', 'R', 'S', 'T', 'U' | |
717 | 'V', 'X' | |
718 | 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */ | |
719 | ||
720 | for (i = 0; i < 256; i++) | |
721 | reg_class_from_letter[i] = NO_REGS; | |
722 | ||
723 | reg_class_from_letter['a'] = ACC_REGS; | |
724 | reg_class_from_letter['b'] = EVEN_ACC_REGS; | |
725 | reg_class_from_letter['c'] = CC_REGS; | |
726 | reg_class_from_letter['d'] = GPR_REGS; | |
727 | reg_class_from_letter['e'] = EVEN_REGS; | |
728 | reg_class_from_letter['f'] = FPR_REGS; | |
729 | reg_class_from_letter['h'] = FEVEN_REGS; | |
730 | reg_class_from_letter['l'] = LR_REG; | |
731 | reg_class_from_letter['q'] = QUAD_REGS; | |
732 | reg_class_from_letter['t'] = ICC_REGS; | |
733 | reg_class_from_letter['u'] = FCC_REGS; | |
734 | reg_class_from_letter['v'] = ICR_REGS; | |
735 | reg_class_from_letter['w'] = FCR_REGS; | |
736 | reg_class_from_letter['x'] = QUAD_FPR_REGS; | |
737 | reg_class_from_letter['y'] = LCR_REG; | |
738 | reg_class_from_letter['z'] = SPR_REGS; | |
739 | reg_class_from_letter['A'] = QUAD_ACC_REGS; | |
740 | reg_class_from_letter['B'] = ACCG_REGS; | |
741 | reg_class_from_letter['C'] = CR_REGS; | |
34208acf AO |
742 | reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */ |
743 | reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */ | |
36a05131 BS |
744 | |
745 | /* There is no single unaligned SI op for PIC code. Sometimes we | |
746 | need to use ".4byte" and sometimes we need to use ".picptr". | |
747 | See frv_assemble_integer for details. */ | |
34208acf | 748 | if (flag_pic || TARGET_FDPIC) |
36a05131 BS |
749 | targetm.asm_out.unaligned_op.si = 0; |
750 | ||
34208acf AO |
751 | if ((target_flags_explicit & MASK_LINKED_FP) == 0) |
752 | target_flags |= MASK_LINKED_FP; | |
753 | ||
c557edf4 RS |
754 | for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++) |
755 | frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]); | |
756 | ||
757 | for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++) | |
758 | frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes); | |
759 | ||
36a05131 BS |
760 | init_machine_status = frv_init_machine_status; |
761 | } | |
762 | ||
763 | \f | |
764 | /* Some machines may desire to change what optimizations are performed for | |
765 | various optimization levels. This macro, if defined, is executed once just | |
766 | after the optimization level is determined and before the remainder of the | |
767 | command options have been parsed. Values set in this macro are used as the | |
768 | default values for the other command line options. | |
769 | ||
770 | LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if | |
771 | `-O' is specified, and 0 if neither is specified. | |
772 | ||
9cd10576 | 773 | SIZE is nonzero if `-Os' is specified, 0 otherwise. |
36a05131 BS |
774 | |
775 | You should not use this macro to change options that are not | |
776 | machine-specific. These should uniformly selected by the same optimization | |
777 | level on all supported machines. Use this macro to enable machbine-specific | |
778 | optimizations. | |
779 | ||
780 | *Do not examine `write_symbols' in this macro!* The debugging options are | |
781 | *not supposed to alter the generated code. */ | |
782 | ||
783 | /* On the FRV, possibly disable VLIW packing which is done by the 2nd | |
784 | scheduling pass at the current time. */ | |
785 | void | |
f2206911 | 786 | frv_optimization_options (int level, int size ATTRIBUTE_UNUSED) |
36a05131 BS |
787 | { |
788 | if (level >= 2) | |
789 | { | |
790 | #ifdef DISABLE_SCHED2 | |
791 | flag_schedule_insns_after_reload = 0; | |
792 | #endif | |
793 | #ifdef ENABLE_RCSP | |
794 | flag_rcsp = 1; | |
795 | #endif | |
796 | } | |
797 | } | |
798 | ||
36a05131 BS |
799 | \f |
800 | /* Return true if NAME (a STRING_CST node) begins with PREFIX. */ | |
801 | ||
802 | static int | |
f2206911 | 803 | frv_string_begins_with (tree name, const char *prefix) |
36a05131 BS |
804 | { |
805 | int prefix_len = strlen (prefix); | |
806 | ||
807 | /* Remember: NAME's length includes the null terminator. */ | |
808 | return (TREE_STRING_LENGTH (name) > prefix_len | |
809 | && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0); | |
810 | } | |
36a05131 BS |
811 | \f |
812 | /* Zero or more C statements that may conditionally modify two variables | |
813 | `fixed_regs' and `call_used_regs' (both of type `char []') after they have | |
814 | been initialized from the two preceding macros. | |
815 | ||
816 | This is necessary in case the fixed or call-clobbered registers depend on | |
817 | target flags. | |
818 | ||
819 | You need not define this macro if it has no work to do. | |
820 | ||
821 | If the usage of an entire class of registers depends on the target flags, | |
822 | you may indicate this to GCC by using this macro to modify `fixed_regs' and | |
823 | `call_used_regs' to 1 for each of the registers in the classes which should | |
824 | not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return | |
825 | `NO_REGS' if it is called with a letter for a class that shouldn't be used. | |
826 | ||
827 | (However, if this class is not included in `GENERAL_REGS' and all of the | |
828 | insn patterns whose constraints permit this class are controlled by target | |
829 | switches, then GCC will automatically avoid using these registers when the | |
830 | target switches are opposed to them.) */ | |
831 | ||
832 | void | |
f2206911 | 833 | frv_conditional_register_usage (void) |
36a05131 BS |
834 | { |
835 | int i; | |
836 | ||
837 | for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++) | |
838 | fixed_regs[i] = call_used_regs[i] = 1; | |
839 | ||
840 | for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++) | |
841 | fixed_regs[i] = call_used_regs[i] = 1; | |
842 | ||
36a05131 BS |
843 | /* Reserve the registers used for conditional execution. At present, we need |
844 | 1 ICC and 1 ICR register. */ | |
845 | fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1; | |
846 | fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1; | |
847 | ||
848 | if (TARGET_FIXED_CC) | |
849 | { | |
850 | fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1; | |
851 | fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1; | |
852 | fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1; | |
853 | fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1; | |
854 | } | |
855 | ||
34208acf AO |
856 | if (TARGET_FDPIC) |
857 | fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] = | |
858 | call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0; | |
859 | ||
36a05131 BS |
860 | #if 0 |
861 | /* If -fpic, SDA_BASE_REG is the PIC register. */ | |
862 | if (g_switch_value == 0 && !flag_pic) | |
863 | fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0; | |
864 | ||
865 | if (!flag_pic) | |
866 | fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0; | |
867 | #endif | |
868 | } | |
869 | ||
870 | \f | |
871 | /* | |
872 | * Compute the stack frame layout | |
873 | * | |
874 | * Register setup: | |
875 | * +---------------+-----------------------+-----------------------+ | |
876 | * |Register |type |caller-save/callee-save| | |
877 | * +---------------+-----------------------+-----------------------+ | |
878 | * |GR0 |Zero register | - | | |
879 | * |GR1 |Stack pointer(SP) | - | | |
880 | * |GR2 |Frame pointer(FP) | - | | |
881 | * |GR3 |Hidden parameter | caller save | | |
882 | * |GR4-GR7 | - | caller save | | |
883 | * |GR8-GR13 |Argument register | caller save | | |
884 | * |GR14-GR15 | - | caller save | | |
885 | * |GR16-GR31 | - | callee save | | |
886 | * |GR32-GR47 | - | caller save | | |
887 | * |GR48-GR63 | - | callee save | | |
888 | * |FR0-FR15 | - | caller save | | |
889 | * |FR16-FR31 | - | callee save | | |
890 | * |FR32-FR47 | - | caller save | | |
891 | * |FR48-FR63 | - | callee save | | |
892 | * +---------------+-----------------------+-----------------------+ | |
893 | * | |
894 | * Stack frame setup: | |
895 | * Low | |
896 | * SP-> |-----------------------------------| | |
897 | * | Argument area | | |
898 | * |-----------------------------------| | |
899 | * | Register save area | | |
900 | * |-----------------------------------| | |
901 | * | Local variable save area | | |
902 | * FP-> |-----------------------------------| | |
903 | * | Old FP | | |
904 | * |-----------------------------------| | |
905 | * | Hidden parameter save area | | |
906 | * |-----------------------------------| | |
907 | * | Return address(LR) storage area | | |
908 | * |-----------------------------------| | |
909 | * | Padding for alignment | | |
910 | * |-----------------------------------| | |
911 | * | Register argument area | | |
912 | * OLD SP-> |-----------------------------------| | |
913 | * | Parameter area | | |
914 | * |-----------------------------------| | |
915 | * High | |
916 | * | |
917 | * Argument area/Parameter area: | |
918 | * | |
919 | * When a function is called, this area is used for argument transfer. When | |
920 | * the argument is set up by the caller function, this area is referred to as | |
921 | * the argument area. When the argument is referenced by the callee function, | |
922 | * this area is referred to as the parameter area. The area is allocated when | |
923 | * all arguments cannot be placed on the argument register at the time of | |
924 | * argument transfer. | |
925 | * | |
926 | * Register save area: | |
927 | * | |
928 | * This is a register save area that must be guaranteed for the caller | |
929 | * function. This area is not secured when the register save operation is not | |
930 | * needed. | |
931 | * | |
932 | * Local variable save area: | |
933 | * | |
934 | * This is the area for local variables and temporary variables. | |
935 | * | |
936 | * Old FP: | |
937 | * | |
938 | * This area stores the FP value of the caller function. | |
939 | * | |
940 | * Hidden parameter save area: | |
941 | * | |
942 | * This area stores the start address of the return value storage | |
943 | * area for a struct/union return function. | |
944 | * When a struct/union is used as the return value, the caller | |
945 | * function stores the return value storage area start address in | |
946 | * register GR3 and passes it to the caller function. | |
947 | * The callee function interprets the address stored in the GR3 | |
948 | * as the return value storage area start address. | |
949 | * When register GR3 needs to be saved into memory, the callee | |
950 | * function saves it in the hidden parameter save area. This | |
951 | * area is not secured when the save operation is not needed. | |
952 | * | |
953 | * Return address(LR) storage area: | |
954 | * | |
955 | * This area saves the LR. The LR stores the address of a return to the caller | |
956 | * function for the purpose of function calling. | |
957 | * | |
958 | * Argument register area: | |
959 | * | |
960 | * This area saves the argument register. This area is not secured when the | |
961 | * save operation is not needed. | |
962 | * | |
963 | * Argument: | |
964 | * | |
965 | * Arguments, the count of which equals the count of argument registers (6 | |
966 | * words), are positioned in registers GR8 to GR13 and delivered to the callee | |
967 | * function. When a struct/union return function is called, the return value | |
968 | * area address is stored in register GR3. Arguments not placed in the | |
969 | * argument registers will be stored in the stack argument area for transfer | |
970 | * purposes. When an 8-byte type argument is to be delivered using registers, | |
971 | * it is divided into two and placed in two registers for transfer. When | |
972 | * argument registers must be saved to memory, the callee function secures an | |
973 | * argument register save area in the stack. In this case, a continuous | |
974 | * argument register save area must be established in the parameter area. The | |
975 | * argument register save area must be allocated as needed to cover the size of | |
976 | * the argument register to be saved. If the function has a variable count of | |
977 | * arguments, it saves all argument registers in the argument register save | |
978 | * area. | |
979 | * | |
980 | * Argument Extension Format: | |
981 | * | |
982 | * When an argument is to be stored in the stack, its type is converted to an | |
983 | * extended type in accordance with the individual argument type. The argument | |
984 | * is freed by the caller function after the return from the callee function is | |
985 | * made. | |
986 | * | |
987 | * +-----------------------+---------------+------------------------+ | |
988 | * | Argument Type |Extended Type |Stack Storage Size(byte)| | |
989 | * +-----------------------+---------------+------------------------+ | |
990 | * |char |int | 4 | | |
991 | * |signed char |int | 4 | | |
992 | * |unsigned char |int | 4 | | |
993 | * |[signed] short int |int | 4 | | |
994 | * |unsigned short int |int | 4 | | |
995 | * |[signed] int |No extension | 4 | | |
996 | * |unsigned int |No extension | 4 | | |
997 | * |[signed] long int |No extension | 4 | | |
998 | * |unsigned long int |No extension | 4 | | |
999 | * |[signed] long long int |No extension | 8 | | |
1000 | * |unsigned long long int |No extension | 8 | | |
1001 | * |float |double | 8 | | |
1002 | * |double |No extension | 8 | | |
1003 | * |long double |No extension | 8 | | |
1004 | * |pointer |No extension | 4 | | |
1005 | * |struct/union |- | 4 (*1) | | |
1006 | * +-----------------------+---------------+------------------------+ | |
1007 | * | |
1008 | * When a struct/union is to be delivered as an argument, the caller copies it | |
1009 | * to the local variable area and delivers the address of that area. | |
1010 | * | |
1011 | * Return Value: | |
1012 | * | |
1013 | * +-------------------------------+----------------------+ | |
1014 | * |Return Value Type |Return Value Interface| | |
1015 | * +-------------------------------+----------------------+ | |
1016 | * |void |None | | |
1017 | * |[signed|unsigned] char |GR8 | | |
1018 | * |[signed|unsigned] short int |GR8 | | |
1019 | * |[signed|unsigned] int |GR8 | | |
1020 | * |[signed|unsigned] long int |GR8 | | |
1021 | * |pointer |GR8 | | |
1022 | * |[signed|unsigned] long long int|GR8 & GR9 | | |
1023 | * |float |GR8 | | |
1024 | * |double |GR8 & GR9 | | |
1025 | * |long double |GR8 & GR9 | | |
1026 | * |struct/union |(*1) | | |
1027 | * +-------------------------------+----------------------+ | |
1028 | * | |
1029 | * When a struct/union is used as the return value, the caller function stores | |
1030 | * the start address of the return value storage area into GR3 and then passes | |
1031 | * it to the callee function. The callee function interprets GR3 as the start | |
1032 | * address of the return value storage area. When this address needs to be | |
1033 | * saved in memory, the callee function secures the hidden parameter save area | |
1034 | * and saves the address in that area. | |
1035 | */ | |
1036 | ||
1037 | frv_stack_t * | |
f2206911 | 1038 | frv_stack_info (void) |
36a05131 BS |
1039 | { |
1040 | static frv_stack_t info, zero_info; | |
1041 | frv_stack_t *info_ptr = &info; | |
1042 | tree fndecl = current_function_decl; | |
1043 | int varargs_p = 0; | |
1044 | tree cur_arg; | |
1045 | tree next_arg; | |
1046 | int range; | |
1047 | int alignment; | |
1048 | int offset; | |
1049 | ||
87b483a1 KH |
1050 | /* If we've already calculated the values and reload is complete, |
1051 | just return now. */ | |
36a05131 BS |
1052 | if (frv_stack_cache) |
1053 | return frv_stack_cache; | |
1054 | ||
87b483a1 | 1055 | /* Zero all fields. */ |
36a05131 BS |
1056 | info = zero_info; |
1057 | ||
87b483a1 | 1058 | /* Set up the register range information. */ |
36a05131 BS |
1059 | info_ptr->regs[STACK_REGS_GPR].name = "gpr"; |
1060 | info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1; | |
1061 | info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST; | |
1062 | info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE; | |
1063 | ||
1064 | info_ptr->regs[STACK_REGS_FPR].name = "fpr"; | |
1065 | info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST; | |
1066 | info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST; | |
1067 | info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE; | |
1068 | ||
1069 | info_ptr->regs[STACK_REGS_LR].name = "lr"; | |
1070 | info_ptr->regs[STACK_REGS_LR].first = LR_REGNO; | |
1071 | info_ptr->regs[STACK_REGS_LR].last = LR_REGNO; | |
1072 | info_ptr->regs[STACK_REGS_LR].special_p = 1; | |
1073 | ||
1074 | info_ptr->regs[STACK_REGS_CC].name = "cc"; | |
1075 | info_ptr->regs[STACK_REGS_CC].first = CC_FIRST; | |
1076 | info_ptr->regs[STACK_REGS_CC].last = CC_LAST; | |
1077 | info_ptr->regs[STACK_REGS_CC].field_p = TRUE; | |
1078 | ||
1079 | info_ptr->regs[STACK_REGS_LCR].name = "lcr"; | |
1080 | info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO; | |
1081 | info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO; | |
1082 | ||
1083 | info_ptr->regs[STACK_REGS_STDARG].name = "stdarg"; | |
1084 | info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM; | |
1085 | info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM; | |
1086 | info_ptr->regs[STACK_REGS_STDARG].dword_p = 1; | |
1087 | info_ptr->regs[STACK_REGS_STDARG].special_p = 1; | |
1088 | ||
1089 | info_ptr->regs[STACK_REGS_STRUCT].name = "struct"; | |
8ac411c7 KH |
1090 | info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM; |
1091 | info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM; | |
36a05131 BS |
1092 | info_ptr->regs[STACK_REGS_STRUCT].special_p = 1; |
1093 | ||
1094 | info_ptr->regs[STACK_REGS_FP].name = "fp"; | |
1095 | info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM; | |
1096 | info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM; | |
1097 | info_ptr->regs[STACK_REGS_FP].special_p = 1; | |
1098 | ||
1099 | /* Determine if this is a stdarg function. If so, allocate space to store | |
1100 | the 6 arguments. */ | |
1101 | if (cfun->stdarg) | |
1102 | varargs_p = 1; | |
1103 | ||
1104 | else | |
1105 | { | |
1106 | /* Find the last argument, and see if it is __builtin_va_alist. */ | |
1107 | for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg) | |
1108 | { | |
1109 | next_arg = TREE_CHAIN (cur_arg); | |
1110 | if (next_arg == (tree)0) | |
1111 | { | |
1112 | if (DECL_NAME (cur_arg) | |
1113 | && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist")) | |
1114 | varargs_p = 1; | |
1115 | ||
1116 | break; | |
1117 | } | |
1118 | } | |
1119 | } | |
1120 | ||
87b483a1 | 1121 | /* Iterate over all of the register ranges. */ |
36a05131 BS |
1122 | for (range = 0; range < STACK_REGS_MAX; range++) |
1123 | { | |
1124 | frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); | |
1125 | int first = reg_ptr->first; | |
1126 | int last = reg_ptr->last; | |
1127 | int size_1word = 0; | |
1128 | int size_2words = 0; | |
1129 | int regno; | |
1130 | ||
87b483a1 | 1131 | /* Calculate which registers need to be saved & save area size. */ |
36a05131 BS |
1132 | switch (range) |
1133 | { | |
1134 | default: | |
1135 | for (regno = first; regno <= last; regno++) | |
1136 | { | |
1137 | if ((regs_ever_live[regno] && !call_used_regs[regno]) | |
1138 | || (current_function_calls_eh_return | |
1139 | && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM)) | |
34208acf AO |
1140 | || (!TARGET_FDPIC && flag_pic |
1141 | && cfun->uses_pic_offset_table && regno == PIC_REGNO)) | |
36a05131 BS |
1142 | { |
1143 | info_ptr->save_p[regno] = REG_SAVE_1WORD; | |
1144 | size_1word += UNITS_PER_WORD; | |
1145 | } | |
1146 | } | |
1147 | break; | |
1148 | ||
1149 | /* Calculate whether we need to create a frame after everything else | |
1150 | has been processed. */ | |
1151 | case STACK_REGS_FP: | |
1152 | break; | |
1153 | ||
1154 | case STACK_REGS_LR: | |
1155 | if (regs_ever_live[LR_REGNO] | |
1156 | || profile_flag | |
34208acf AO |
1157 | /* This is set for __builtin_return_address, etc. */ |
1158 | || cfun->machine->frame_needed | |
1159 | || (TARGET_LINKED_FP && frame_pointer_needed) | |
1160 | || (!TARGET_FDPIC && flag_pic | |
1161 | && cfun->uses_pic_offset_table)) | |
36a05131 BS |
1162 | { |
1163 | info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD; | |
1164 | size_1word += UNITS_PER_WORD; | |
1165 | } | |
1166 | break; | |
1167 | ||
1168 | case STACK_REGS_STDARG: | |
1169 | if (varargs_p) | |
1170 | { | |
87b483a1 KH |
1171 | /* If this is a stdarg function with a non varardic |
1172 | argument split between registers and the stack, | |
1173 | adjust the saved registers downward. */ | |
36a05131 BS |
1174 | last -= (ADDR_ALIGN (cfun->pretend_args_size, UNITS_PER_WORD) |
1175 | / UNITS_PER_WORD); | |
1176 | ||
1177 | for (regno = first; regno <= last; regno++) | |
1178 | { | |
1179 | info_ptr->save_p[regno] = REG_SAVE_1WORD; | |
1180 | size_1word += UNITS_PER_WORD; | |
1181 | } | |
1182 | ||
1183 | info_ptr->stdarg_size = size_1word; | |
1184 | } | |
1185 | break; | |
1186 | ||
1187 | case STACK_REGS_STRUCT: | |
1188 | if (cfun->returns_struct) | |
1189 | { | |
8ac411c7 | 1190 | info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD; |
36a05131 BS |
1191 | size_1word += UNITS_PER_WORD; |
1192 | } | |
1193 | break; | |
1194 | } | |
1195 | ||
1196 | ||
1197 | if (size_1word) | |
1198 | { | |
87b483a1 | 1199 | /* If this is a field, it only takes one word. */ |
36a05131 BS |
1200 | if (reg_ptr->field_p) |
1201 | size_1word = UNITS_PER_WORD; | |
1202 | ||
87b483a1 | 1203 | /* Determine which register pairs can be saved together. */ |
36a05131 BS |
1204 | else if (reg_ptr->dword_p && TARGET_DWORD) |
1205 | { | |
1206 | for (regno = first; regno < last; regno += 2) | |
1207 | { | |
1208 | if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1]) | |
1209 | { | |
1210 | size_2words += 2 * UNITS_PER_WORD; | |
1211 | size_1word -= 2 * UNITS_PER_WORD; | |
1212 | info_ptr->save_p[regno] = REG_SAVE_2WORDS; | |
1213 | info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE; | |
1214 | } | |
1215 | } | |
1216 | } | |
1217 | ||
1218 | reg_ptr->size_1word = size_1word; | |
1219 | reg_ptr->size_2words = size_2words; | |
1220 | ||
1221 | if (! reg_ptr->special_p) | |
1222 | { | |
1223 | info_ptr->regs_size_1word += size_1word; | |
1224 | info_ptr->regs_size_2words += size_2words; | |
1225 | } | |
1226 | } | |
1227 | } | |
1228 | ||
1229 | /* Set up the sizes of each each field in the frame body, making the sizes | |
1230 | of each be divisible by the size of a dword if dword operations might | |
1231 | be used, or the size of a word otherwise. */ | |
1232 | alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD); | |
1233 | ||
1234 | info_ptr->parameter_size = ADDR_ALIGN (cfun->outgoing_args_size, alignment); | |
1235 | info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words | |
1236 | + info_ptr->regs_size_1word, | |
1237 | alignment); | |
1238 | info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment); | |
1239 | ||
1240 | info_ptr->pretend_size = cfun->pretend_args_size; | |
1241 | ||
1242 | /* Work out the size of the frame, excluding the header. Both the frame | |
1243 | body and register parameter area will be dword-aligned. */ | |
1244 | info_ptr->total_size | |
1245 | = (ADDR_ALIGN (info_ptr->parameter_size | |
1246 | + info_ptr->regs_size | |
1247 | + info_ptr->vars_size, | |
1248 | 2 * UNITS_PER_WORD) | |
1249 | + ADDR_ALIGN (info_ptr->pretend_size | |
1250 | + info_ptr->stdarg_size, | |
1251 | 2 * UNITS_PER_WORD)); | |
1252 | ||
1253 | /* See if we need to create a frame at all, if so add header area. */ | |
1254 | if (info_ptr->total_size > 0 | |
34208acf | 1255 | || frame_pointer_needed |
36a05131 BS |
1256 | || info_ptr->regs[STACK_REGS_LR].size_1word > 0 |
1257 | || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0) | |
1258 | { | |
1259 | offset = info_ptr->parameter_size; | |
1260 | info_ptr->header_size = 4 * UNITS_PER_WORD; | |
1261 | info_ptr->total_size += 4 * UNITS_PER_WORD; | |
1262 | ||
87b483a1 | 1263 | /* Calculate the offsets to save normal register pairs. */ |
36a05131 BS |
1264 | for (range = 0; range < STACK_REGS_MAX; range++) |
1265 | { | |
1266 | frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); | |
1267 | if (! reg_ptr->special_p) | |
1268 | { | |
1269 | int first = reg_ptr->first; | |
1270 | int last = reg_ptr->last; | |
1271 | int regno; | |
1272 | ||
1273 | for (regno = first; regno <= last; regno++) | |
1274 | if (info_ptr->save_p[regno] == REG_SAVE_2WORDS | |
1275 | && regno != FRAME_POINTER_REGNUM | |
1276 | && (regno < FIRST_ARG_REGNUM | |
1277 | || regno > LAST_ARG_REGNUM)) | |
1278 | { | |
1279 | info_ptr->reg_offset[regno] = offset; | |
1280 | offset += 2 * UNITS_PER_WORD; | |
1281 | } | |
1282 | } | |
1283 | } | |
1284 | ||
87b483a1 | 1285 | /* Calculate the offsets to save normal single registers. */ |
36a05131 BS |
1286 | for (range = 0; range < STACK_REGS_MAX; range++) |
1287 | { | |
1288 | frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); | |
1289 | if (! reg_ptr->special_p) | |
1290 | { | |
1291 | int first = reg_ptr->first; | |
1292 | int last = reg_ptr->last; | |
1293 | int regno; | |
1294 | ||
1295 | for (regno = first; regno <= last; regno++) | |
1296 | if (info_ptr->save_p[regno] == REG_SAVE_1WORD | |
1297 | && regno != FRAME_POINTER_REGNUM | |
1298 | && (regno < FIRST_ARG_REGNUM | |
1299 | || regno > LAST_ARG_REGNUM)) | |
1300 | { | |
1301 | info_ptr->reg_offset[regno] = offset; | |
1302 | offset += UNITS_PER_WORD; | |
1303 | } | |
1304 | } | |
1305 | } | |
1306 | ||
1307 | /* Calculate the offset to save the local variables at. */ | |
1308 | offset = ADDR_ALIGN (offset, alignment); | |
1309 | if (info_ptr->vars_size) | |
1310 | { | |
1311 | info_ptr->vars_offset = offset; | |
1312 | offset += info_ptr->vars_size; | |
1313 | } | |
1314 | ||
1315 | /* Align header to a dword-boundary. */ | |
1316 | offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD); | |
1317 | ||
1318 | /* Calculate the offsets in the fixed frame. */ | |
1319 | info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD; | |
1320 | info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset; | |
1321 | info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD; | |
1322 | ||
1323 | info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD; | |
1324 | info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD; | |
1325 | info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD; | |
1326 | ||
1327 | if (cfun->returns_struct) | |
1328 | { | |
8ac411c7 KH |
1329 | info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD; |
1330 | info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD; | |
36a05131 BS |
1331 | info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD; |
1332 | } | |
1333 | ||
1334 | /* Calculate the offsets to store the arguments passed in registers | |
1335 | for stdarg functions. The register pairs are first and the single | |
1336 | register if any is last. The register save area starts on a | |
1337 | dword-boundary. */ | |
1338 | if (info_ptr->stdarg_size) | |
1339 | { | |
1340 | int first = info_ptr->regs[STACK_REGS_STDARG].first; | |
1341 | int last = info_ptr->regs[STACK_REGS_STDARG].last; | |
1342 | int regno; | |
1343 | ||
1344 | /* Skip the header. */ | |
1345 | offset += 4 * UNITS_PER_WORD; | |
1346 | for (regno = first; regno <= last; regno++) | |
1347 | { | |
1348 | if (info_ptr->save_p[regno] == REG_SAVE_2WORDS) | |
1349 | { | |
1350 | info_ptr->reg_offset[regno] = offset; | |
1351 | offset += 2 * UNITS_PER_WORD; | |
1352 | } | |
1353 | else if (info_ptr->save_p[regno] == REG_SAVE_1WORD) | |
1354 | { | |
1355 | info_ptr->reg_offset[regno] = offset; | |
1356 | offset += UNITS_PER_WORD; | |
1357 | } | |
1358 | } | |
1359 | } | |
1360 | } | |
1361 | ||
1362 | if (reload_completed) | |
1363 | frv_stack_cache = info_ptr; | |
1364 | ||
1365 | return info_ptr; | |
1366 | } | |
1367 | ||
1368 | \f | |
87b483a1 | 1369 | /* Print the information about the frv stack offsets, etc. when debugging. */ |
36a05131 BS |
1370 | |
1371 | void | |
f2206911 | 1372 | frv_debug_stack (frv_stack_t *info) |
36a05131 BS |
1373 | { |
1374 | int range; | |
1375 | ||
1376 | if (!info) | |
1377 | info = frv_stack_info (); | |
1378 | ||
1379 | fprintf (stderr, "\nStack information for function %s:\n", | |
1380 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
1381 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
1382 | : "<unknown>")); | |
1383 | ||
1384 | fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size); | |
1385 | fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size); | |
1386 | fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size); | |
1387 | fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n", | |
1388 | info->regs_size, info->regs_size_1word, info->regs_size_2words); | |
1389 | ||
1390 | fprintf (stderr, "\theader_size\t= %6d\n", info->header_size); | |
1391 | fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size); | |
1392 | fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset); | |
1393 | fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset); | |
1394 | ||
1395 | for (range = 0; range < STACK_REGS_MAX; range++) | |
1396 | { | |
1397 | frv_stack_regs_t *regs = &(info->regs[range]); | |
1398 | if ((regs->size_1word + regs->size_2words) > 0) | |
1399 | { | |
1400 | int first = regs->first; | |
1401 | int last = regs->last; | |
1402 | int regno; | |
1403 | ||
1404 | fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =", | |
1405 | regs->name, regs->size_1word + regs->size_2words, | |
1406 | regs->size_1word, regs->size_2words); | |
1407 | ||
1408 | for (regno = first; regno <= last; regno++) | |
1409 | { | |
1410 | if (info->save_p[regno] == REG_SAVE_1WORD) | |
1411 | fprintf (stderr, " %s (%d)", reg_names[regno], | |
1412 | info->reg_offset[regno]); | |
1413 | ||
1414 | else if (info->save_p[regno] == REG_SAVE_2WORDS) | |
1415 | fprintf (stderr, " %s-%s (%d)", reg_names[regno], | |
1416 | reg_names[regno+1], info->reg_offset[regno]); | |
1417 | } | |
1418 | ||
1419 | fputc ('\n', stderr); | |
1420 | } | |
1421 | } | |
1422 | ||
1423 | fflush (stderr); | |
1424 | } | |
1425 | ||
1426 | ||
1427 | \f | |
1428 | ||
c557edf4 RS |
1429 | /* Used during final to control the packing of insns. The value is |
1430 | 1 if the current instruction should be packed with the next one, | |
1431 | 0 if it shouldn't or -1 if packing is disabled altogether. */ | |
36a05131 BS |
1432 | |
1433 | static int frv_insn_packing_flag; | |
1434 | ||
1435 | /* True if the current function contains a far jump. */ | |
1436 | ||
1437 | static int | |
f2206911 | 1438 | frv_function_contains_far_jump (void) |
36a05131 BS |
1439 | { |
1440 | rtx insn = get_insns (); | |
1441 | while (insn != NULL | |
1442 | && !(GET_CODE (insn) == JUMP_INSN | |
1443 | /* Ignore tablejump patterns. */ | |
1444 | && GET_CODE (PATTERN (insn)) != ADDR_VEC | |
1445 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC | |
1446 | && get_attr_far_jump (insn) == FAR_JUMP_YES)) | |
1447 | insn = NEXT_INSN (insn); | |
1448 | return (insn != NULL); | |
1449 | } | |
1450 | ||
1451 | /* For the FRV, this function makes sure that a function with far jumps | |
1452 | will return correctly. It also does the VLIW packing. */ | |
1453 | ||
1454 | static void | |
f2206911 | 1455 | frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
36a05131 BS |
1456 | { |
1457 | /* If no frame was created, check whether the function uses a call | |
1458 | instruction to implement a far jump. If so, save the link in gr3 and | |
1459 | replace all returns to LR with returns to GR3. GR3 is used because it | |
1460 | is call-clobbered, because is not available to the register allocator, | |
1461 | and because all functions that take a hidden argument pointer will have | |
1462 | a stack frame. */ | |
1463 | if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ()) | |
1464 | { | |
1465 | rtx insn; | |
1466 | ||
1467 | /* Just to check that the above comment is true. */ | |
1468 | if (regs_ever_live[GPR_FIRST + 3]) | |
1469 | abort (); | |
1470 | ||
1471 | /* Generate the instruction that saves the link register. */ | |
1472 | fprintf (file, "\tmovsg lr,gr3\n"); | |
1473 | ||
1474 | /* Replace the LR with GR3 in *return_internal patterns. The insn | |
1475 | will now return using jmpl @(gr3,0) rather than bralr. We cannot | |
1476 | simply emit a different assembly directive because bralr and jmpl | |
1477 | execute in different units. */ | |
1478 | for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn)) | |
1479 | if (GET_CODE (insn) == JUMP_INSN) | |
1480 | { | |
1481 | rtx pattern = PATTERN (insn); | |
1482 | if (GET_CODE (pattern) == PARALLEL | |
1483 | && XVECLEN (pattern, 0) >= 2 | |
1484 | && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN | |
1485 | && GET_CODE (XVECEXP (pattern, 0, 1)) == USE) | |
1486 | { | |
1487 | rtx address = XEXP (XVECEXP (pattern, 0, 1), 0); | |
1488 | if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO) | |
1489 | REGNO (address) = GPR_FIRST + 3; | |
1490 | } | |
1491 | } | |
1492 | } | |
1493 | ||
1494 | frv_pack_insns (); | |
c557edf4 RS |
1495 | |
1496 | /* Allow the garbage collector to free the nops created by frv_reorg. */ | |
1497 | memset (frv_nops, 0, sizeof (frv_nops)); | |
36a05131 BS |
1498 | } |
1499 | ||
1500 | \f | |
1501 | /* Return the next available temporary register in a given class. */ | |
1502 | ||
1503 | static rtx | |
f2206911 KC |
1504 | frv_alloc_temp_reg ( |
1505 | frv_tmp_reg_t *info, /* which registers are available */ | |
1506 | enum reg_class class, /* register class desired */ | |
1507 | enum machine_mode mode, /* mode to allocate register with */ | |
1508 | int mark_as_used, /* register not available after allocation */ | |
1509 | int no_abort) /* return NULL instead of aborting */ | |
36a05131 BS |
1510 | { |
1511 | int regno = info->next_reg[ (int)class ]; | |
1512 | int orig_regno = regno; | |
1513 | HARD_REG_SET *reg_in_class = ®_class_contents[ (int)class ]; | |
1514 | int i, nr; | |
1515 | ||
1516 | for (;;) | |
1517 | { | |
1518 | if (TEST_HARD_REG_BIT (*reg_in_class, regno) | |
1519 | && TEST_HARD_REG_BIT (info->regs, regno)) | |
1520 | break; | |
1521 | ||
1522 | if (++regno >= FIRST_PSEUDO_REGISTER) | |
1523 | regno = 0; | |
1524 | if (regno == orig_regno) | |
1525 | { | |
1526 | if (no_abort) | |
1527 | return NULL_RTX; | |
1528 | else | |
1529 | abort (); | |
1530 | } | |
1531 | } | |
1532 | ||
1533 | nr = HARD_REGNO_NREGS (regno, mode); | |
1534 | info->next_reg[ (int)class ] = regno + nr; | |
1535 | ||
1536 | if (mark_as_used) | |
1537 | for (i = 0; i < nr; i++) | |
1538 | CLEAR_HARD_REG_BIT (info->regs, regno+i); | |
1539 | ||
1540 | return gen_rtx_REG (mode, regno); | |
1541 | } | |
1542 | ||
1543 | \f | |
1544 | /* Return an rtx with the value OFFSET, which will either be a register or a | |
1545 | signed 12-bit integer. It can be used as the second operand in an "add" | |
1546 | instruction, or as the index in a load or store. | |
1547 | ||
1548 | The function returns a constant rtx if OFFSET is small enough, otherwise | |
1549 | it loads the constant into register OFFSET_REGNO and returns that. */ | |
1550 | static rtx | |
f2206911 | 1551 | frv_frame_offset_rtx (int offset) |
36a05131 BS |
1552 | { |
1553 | rtx offset_rtx = GEN_INT (offset); | |
1554 | if (IN_RANGE_P (offset, -2048, 2047)) | |
1555 | return offset_rtx; | |
1556 | else | |
1557 | { | |
1558 | rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO); | |
1559 | if (IN_RANGE_P (offset, -32768, 32767)) | |
1560 | emit_insn (gen_movsi (reg_rtx, offset_rtx)); | |
1561 | else | |
1562 | { | |
1563 | emit_insn (gen_movsi_high (reg_rtx, offset_rtx)); | |
1564 | emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx)); | |
1565 | } | |
1566 | return reg_rtx; | |
1567 | } | |
1568 | } | |
1569 | ||
1570 | /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The | |
1571 | prologue and epilogue uses such expressions to access the stack. */ | |
1572 | static rtx | |
f2206911 | 1573 | frv_frame_mem (enum machine_mode mode, rtx base, int offset) |
36a05131 BS |
1574 | { |
1575 | return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, | |
1576 | base, | |
1577 | frv_frame_offset_rtx (offset))); | |
1578 | } | |
1579 | ||
1580 | /* Generate a frame-related expression: | |
1581 | ||
1582 | (set REG (mem (plus (sp) (const_int OFFSET)))). | |
1583 | ||
1584 | Such expressions are used in FRAME_RELATED_EXPR notes for more complex | |
1585 | instructions. Marking the expressions as frame-related is superfluous if | |
1586 | the note contains just a single set. But if the note contains a PARALLEL | |
1587 | or SEQUENCE that has several sets, each set must be individually marked | |
1588 | as frame-related. */ | |
1589 | static rtx | |
f2206911 | 1590 | frv_dwarf_store (rtx reg, int offset) |
36a05131 BS |
1591 | { |
1592 | rtx set = gen_rtx_SET (VOIDmode, | |
1593 | gen_rtx_MEM (GET_MODE (reg), | |
1594 | plus_constant (stack_pointer_rtx, | |
1595 | offset)), | |
1596 | reg); | |
1597 | RTX_FRAME_RELATED_P (set) = 1; | |
1598 | return set; | |
1599 | } | |
1600 | ||
1601 | /* Emit a frame-related instruction whose pattern is PATTERN. The | |
1602 | instruction is the last in a sequence that cumulatively performs the | |
1603 | operation described by DWARF_PATTERN. The instruction is marked as | |
1604 | frame-related and has a REG_FRAME_RELATED_EXPR note containing | |
1605 | DWARF_PATTERN. */ | |
1606 | static void | |
f2206911 | 1607 | frv_frame_insn (rtx pattern, rtx dwarf_pattern) |
36a05131 BS |
1608 | { |
1609 | rtx insn = emit_insn (pattern); | |
1610 | RTX_FRAME_RELATED_P (insn) = 1; | |
1611 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
1612 | dwarf_pattern, | |
1613 | REG_NOTES (insn)); | |
1614 | } | |
1615 | ||
1616 | /* Emit instructions that transfer REG to or from the memory location (sp + | |
1617 | STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is | |
1618 | FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this | |
1619 | function to store registers and only the epilogue uses it to load them. | |
1620 | ||
1621 | The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET). | |
1622 | The generated instruction will use BASE as its base register. BASE may | |
1623 | simply be the stack pointer, but if several accesses are being made to a | |
1624 | region far away from the stack pointer, it may be more efficient to set | |
1625 | up a temporary instead. | |
b16c1435 | 1626 | |
36a05131 BS |
1627 | Store instructions will be frame-related and will be annotated with the |
1628 | overall effect of the store. Load instructions will be followed by a | |
1629 | (use) to prevent later optimizations from zapping them. | |
1630 | ||
1631 | The function takes care of the moves to and from SPRs, using TEMP_REGNO | |
1632 | as a temporary in such cases. */ | |
1633 | static void | |
f2206911 | 1634 | frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset) |
36a05131 BS |
1635 | { |
1636 | enum machine_mode mode = GET_MODE (reg); | |
1637 | rtx mem = frv_frame_mem (mode, | |
1638 | accessor->base, | |
1639 | stack_offset - accessor->base_offset); | |
1640 | ||
1641 | if (accessor->op == FRV_LOAD) | |
1642 | { | |
1643 | if (SPR_P (REGNO (reg))) | |
1644 | { | |
1645 | rtx temp = gen_rtx_REG (mode, TEMP_REGNO); | |
1646 | emit_insn (gen_rtx_SET (VOIDmode, temp, mem)); | |
1647 | emit_insn (gen_rtx_SET (VOIDmode, reg, temp)); | |
1648 | } | |
1649 | else | |
1650 | emit_insn (gen_rtx_SET (VOIDmode, reg, mem)); | |
1651 | emit_insn (gen_rtx_USE (VOIDmode, reg)); | |
1652 | } | |
1653 | else | |
1654 | { | |
1655 | if (SPR_P (REGNO (reg))) | |
1656 | { | |
1657 | rtx temp = gen_rtx_REG (mode, TEMP_REGNO); | |
1658 | emit_insn (gen_rtx_SET (VOIDmode, temp, reg)); | |
1659 | frv_frame_insn (gen_rtx_SET (Pmode, mem, temp), | |
1660 | frv_dwarf_store (reg, stack_offset)); | |
1661 | } | |
1662 | else if (GET_MODE (reg) == DImode) | |
1663 | { | |
1664 | /* For DImode saves, the dwarf2 version needs to be a SEQUENCE | |
1665 | with a separate save for each register. */ | |
1666 | rtx reg1 = gen_rtx_REG (SImode, REGNO (reg)); | |
1667 | rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1); | |
1668 | rtx set1 = frv_dwarf_store (reg1, stack_offset); | |
1669 | rtx set2 = frv_dwarf_store (reg2, stack_offset + 4); | |
1670 | frv_frame_insn (gen_rtx_SET (Pmode, mem, reg), | |
1671 | gen_rtx_PARALLEL (VOIDmode, | |
1672 | gen_rtvec (2, set1, set2))); | |
1673 | } | |
1674 | else | |
1675 | frv_frame_insn (gen_rtx_SET (Pmode, mem, reg), | |
1676 | frv_dwarf_store (reg, stack_offset)); | |
1677 | } | |
1678 | } | |
1679 | ||
1680 | /* A function that uses frv_frame_access to transfer a group of registers to | |
1681 | or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO | |
1682 | is the stack information generated by frv_stack_info, and REG_SET is the | |
1683 | number of the register set to transfer. */ | |
1684 | static void | |
f2206911 KC |
1685 | frv_frame_access_multi (frv_frame_accessor_t *accessor, |
1686 | frv_stack_t *info, | |
1687 | int reg_set) | |
36a05131 BS |
1688 | { |
1689 | frv_stack_regs_t *regs_info; | |
1690 | int regno; | |
1691 | ||
1692 | regs_info = &info->regs[reg_set]; | |
1693 | for (regno = regs_info->first; regno <= regs_info->last; regno++) | |
1694 | if (info->save_p[regno]) | |
1695 | frv_frame_access (accessor, | |
1696 | info->save_p[regno] == REG_SAVE_2WORDS | |
1697 | ? gen_rtx_REG (DImode, regno) | |
1698 | : gen_rtx_REG (SImode, regno), | |
1699 | info->reg_offset[regno]); | |
1700 | } | |
1701 | ||
1702 | /* Save or restore callee-saved registers that are kept outside the frame | |
1703 | header. The function saves the registers if OP is FRV_STORE and restores | |
1704 | them if OP is FRV_LOAD. INFO is the stack information generated by | |
1705 | frv_stack_info. */ | |
1706 | static void | |
f2206911 | 1707 | frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info) |
36a05131 BS |
1708 | { |
1709 | frv_frame_accessor_t accessor; | |
1710 | ||
1711 | accessor.op = op; | |
1712 | accessor.base = stack_pointer_rtx; | |
1713 | accessor.base_offset = 0; | |
1714 | frv_frame_access_multi (&accessor, info, STACK_REGS_GPR); | |
1715 | frv_frame_access_multi (&accessor, info, STACK_REGS_FPR); | |
1716 | frv_frame_access_multi (&accessor, info, STACK_REGS_LCR); | |
b16c1435 | 1717 | } |
36a05131 BS |
1718 | |
1719 | ||
1720 | /* Called after register allocation to add any instructions needed for the | |
1721 | prologue. Using a prologue insn is favored compared to putting all of the | |
b88cf82e KH |
1722 | instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since |
1723 | it allows the scheduler to intermix instructions with the saves of | |
1724 | the caller saved registers. In some cases, it might be necessary | |
1725 | to emit a barrier instruction as the last insn to prevent such | |
1726 | scheduling. | |
36a05131 BS |
1727 | |
1728 | Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1 | |
1729 | so that the debug info generation code can handle them properly. */ | |
1730 | void | |
f2206911 | 1731 | frv_expand_prologue (void) |
36a05131 BS |
1732 | { |
1733 | frv_stack_t *info = frv_stack_info (); | |
1734 | rtx sp = stack_pointer_rtx; | |
1735 | rtx fp = frame_pointer_rtx; | |
1736 | frv_frame_accessor_t accessor; | |
1737 | ||
1738 | if (TARGET_DEBUG_STACK) | |
1739 | frv_debug_stack (info); | |
1740 | ||
1741 | if (info->total_size == 0) | |
1742 | return; | |
1743 | ||
1744 | /* We're interested in three areas of the frame here: | |
1745 | ||
1746 | A: the register save area | |
1747 | B: the old FP | |
1748 | C: the header after B | |
1749 | ||
1750 | If the frame pointer isn't used, we'll have to set up A, B and C | |
1751 | using the stack pointer. If the frame pointer is used, we'll access | |
1752 | them as follows: | |
1753 | ||
1754 | A: set up using sp | |
1755 | B: set up using sp or a temporary (see below) | |
1756 | C: set up using fp | |
1757 | ||
1758 | We set up B using the stack pointer if the frame is small enough. | |
1759 | Otherwise, it's more efficient to copy the old stack pointer into a | |
1760 | temporary and use that. | |
1761 | ||
1762 | Note that it's important to make sure the prologue and epilogue use the | |
1763 | same registers to access A and C, since doing otherwise will confuse | |
1764 | the aliasing code. */ | |
1765 | ||
1766 | /* Set up ACCESSOR for accessing region B above. If the frame pointer | |
1767 | isn't used, the same method will serve for C. */ | |
1768 | accessor.op = FRV_STORE; | |
1769 | if (frame_pointer_needed && info->total_size > 2048) | |
1770 | { | |
1771 | rtx insn; | |
1772 | ||
1773 | accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO); | |
1774 | accessor.base_offset = info->total_size; | |
1775 | insn = emit_insn (gen_movsi (accessor.base, sp)); | |
1776 | } | |
1777 | else | |
1778 | { | |
1779 | accessor.base = stack_pointer_rtx; | |
1780 | accessor.base_offset = 0; | |
1781 | } | |
1782 | ||
1783 | /* Allocate the stack space. */ | |
1784 | { | |
1785 | rtx asm_offset = frv_frame_offset_rtx (-info->total_size); | |
1786 | rtx dwarf_offset = GEN_INT (-info->total_size); | |
1787 | ||
1788 | frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset), | |
1789 | gen_rtx_SET (Pmode, | |
1790 | sp, | |
1791 | gen_rtx_PLUS (Pmode, sp, dwarf_offset))); | |
1792 | } | |
1793 | ||
1794 | /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET) | |
1795 | and point the new one to that location. */ | |
1796 | if (frame_pointer_needed) | |
1797 | { | |
1798 | int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM]; | |
1799 | ||
1800 | /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is | |
1801 | based on ACCESSOR.BASE but DWARF_SRC is always based on the stack | |
1802 | pointer. */ | |
1803 | rtx asm_src = plus_constant (accessor.base, | |
1804 | fp_offset - accessor.base_offset); | |
1805 | rtx dwarf_src = plus_constant (sp, fp_offset); | |
1806 | ||
1807 | /* Store the old frame pointer at (sp + FP_OFFSET). */ | |
1808 | frv_frame_access (&accessor, fp, fp_offset); | |
1809 | ||
1810 | /* Set up the new frame pointer. */ | |
1811 | frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src), | |
1812 | gen_rtx_SET (VOIDmode, fp, dwarf_src)); | |
1813 | ||
1814 | /* Access region C from the frame pointer. */ | |
1815 | accessor.base = fp; | |
1816 | accessor.base_offset = fp_offset; | |
1817 | } | |
1818 | ||
1819 | /* Set up region C. */ | |
1820 | frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT); | |
1821 | frv_frame_access_multi (&accessor, info, STACK_REGS_LR); | |
1822 | frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG); | |
1823 | ||
1824 | /* Set up region A. */ | |
1825 | frv_frame_access_standard_regs (FRV_STORE, info); | |
1826 | ||
1827 | /* If this is a varargs/stdarg function, issue a blockage to prevent the | |
1828 | scheduler from moving loads before the stores saving the registers. */ | |
1829 | if (info->stdarg_size > 0) | |
1830 | emit_insn (gen_blockage ()); | |
1831 | ||
87b483a1 | 1832 | /* Set up pic register/small data register for this function. */ |
34208acf | 1833 | if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table) |
36a05131 BS |
1834 | emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO), |
1835 | gen_rtx_REG (Pmode, LR_REGNO), | |
1836 | gen_rtx_REG (SImode, OFFSET_REGNO))); | |
1837 | } | |
1838 | ||
1839 | \f | |
1840 | /* Under frv, all of the work is done via frv_expand_epilogue, but | |
839a4992 | 1841 | this function provides a convenient place to do cleanup. */ |
36a05131 BS |
1842 | |
1843 | static void | |
f2206911 KC |
1844 | frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED, |
1845 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
36a05131 BS |
1846 | { |
1847 | frv_stack_cache = (frv_stack_t *)0; | |
1848 | ||
87b483a1 | 1849 | /* Zap last used registers for conditional execution. */ |
fad205ff | 1850 | memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg)); |
36a05131 | 1851 | |
87b483a1 | 1852 | /* Release the bitmap of created insns. */ |
36a05131 BS |
1853 | BITMAP_XFREE (frv_ifcvt.scratch_insns_bitmap); |
1854 | } | |
1855 | ||
1856 | \f | |
1857 | /* Called after register allocation to add any instructions needed for the | |
43aa4e05 | 1858 | epilogue. Using an epilogue insn is favored compared to putting all of the |
b88cf82e KH |
1859 | instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since |
1860 | it allows the scheduler to intermix instructions with the saves of | |
1861 | the caller saved registers. In some cases, it might be necessary | |
1862 | to emit a barrier instruction as the last insn to prevent such | |
c557edf4 | 1863 | scheduling. */ |
36a05131 BS |
1864 | |
1865 | void | |
764678d1 | 1866 | frv_expand_epilogue (bool emit_return) |
36a05131 BS |
1867 | { |
1868 | frv_stack_t *info = frv_stack_info (); | |
1869 | rtx fp = frame_pointer_rtx; | |
1870 | rtx sp = stack_pointer_rtx; | |
1871 | rtx return_addr; | |
1872 | int fp_offset; | |
1873 | ||
1874 | fp_offset = info->reg_offset[FRAME_POINTER_REGNUM]; | |
1875 | ||
1876 | /* Restore the stack pointer to its original value if alloca or the like | |
1877 | is used. */ | |
1878 | if (! current_function_sp_is_unchanging) | |
1879 | emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset))); | |
1880 | ||
1881 | /* Restore the callee-saved registers that were used in this function. */ | |
1882 | frv_frame_access_standard_regs (FRV_LOAD, info); | |
1883 | ||
1884 | /* Set RETURN_ADDR to the address we should return to. Set it to NULL if | |
1885 | no return instruction should be emitted. */ | |
764678d1 | 1886 | if (info->save_p[LR_REGNO]) |
36a05131 BS |
1887 | { |
1888 | int lr_offset; | |
1889 | rtx mem; | |
1890 | ||
1891 | /* Use the same method to access the link register's slot as we did in | |
1892 | the prologue. In other words, use the frame pointer if available, | |
1893 | otherwise use the stack pointer. | |
1894 | ||
1895 | LR_OFFSET is the offset of the link register's slot from the start | |
1896 | of the frame and MEM is a memory rtx for it. */ | |
1897 | lr_offset = info->reg_offset[LR_REGNO]; | |
1898 | if (frame_pointer_needed) | |
1899 | mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset); | |
1900 | else | |
1901 | mem = frv_frame_mem (Pmode, sp, lr_offset); | |
1902 | ||
1903 | /* Load the old link register into a GPR. */ | |
1904 | return_addr = gen_rtx_REG (Pmode, TEMP_REGNO); | |
1905 | emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem)); | |
1906 | } | |
1907 | else | |
1908 | return_addr = gen_rtx_REG (Pmode, LR_REGNO); | |
1909 | ||
1910 | /* Restore the old frame pointer. Emit a USE afterwards to make sure | |
1911 | the load is preserved. */ | |
1912 | if (frame_pointer_needed) | |
1913 | { | |
1914 | emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp))); | |
1915 | emit_insn (gen_rtx_USE (VOIDmode, fp)); | |
1916 | } | |
1917 | ||
1918 | /* Deallocate the stack frame. */ | |
1919 | if (info->total_size != 0) | |
1920 | { | |
1921 | rtx offset = frv_frame_offset_rtx (info->total_size); | |
1922 | emit_insn (gen_stack_adjust (sp, sp, offset)); | |
1923 | } | |
1924 | ||
1925 | /* If this function uses eh_return, add the final stack adjustment now. */ | |
1926 | if (current_function_calls_eh_return) | |
1927 | emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX)); | |
1928 | ||
764678d1 | 1929 | if (emit_return) |
36a05131 | 1930 | emit_jump_insn (gen_epilogue_return (return_addr)); |
764678d1 AO |
1931 | else |
1932 | { | |
1933 | rtx lr = return_addr; | |
1934 | ||
1935 | if (REGNO (return_addr) != LR_REGNO) | |
1936 | { | |
1937 | lr = gen_rtx_REG (Pmode, LR_REGNO); | |
1938 | emit_move_insn (lr, return_addr); | |
1939 | } | |
1940 | ||
1941 | emit_insn (gen_rtx_USE (VOIDmode, lr)); | |
1942 | } | |
36a05131 BS |
1943 | } |
1944 | ||
1945 | \f | |
b88cf82e | 1946 | /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */ |
36a05131 | 1947 | |
c590b625 | 1948 | static void |
f2206911 KC |
1949 | frv_asm_output_mi_thunk (FILE *file, |
1950 | tree thunk_fndecl ATTRIBUTE_UNUSED, | |
1951 | HOST_WIDE_INT delta, | |
1952 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
1953 | tree function) | |
36a05131 BS |
1954 | { |
1955 | const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0); | |
1956 | const char *name_arg0 = reg_names[FIRST_ARG_REGNUM]; | |
1957 | const char *name_jmp = reg_names[JUMP_REGNO]; | |
c557edf4 | 1958 | const char *parallel = (frv_issue_rate () > 1 ? ".p" : ""); |
36a05131 | 1959 | |
87b483a1 | 1960 | /* Do the add using an addi if possible. */ |
36a05131 | 1961 | if (IN_RANGE_P (delta, -2048, 2047)) |
eb0424da | 1962 | fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0); |
36a05131 BS |
1963 | else |
1964 | { | |
4a0a75dd KG |
1965 | const char *const name_add = reg_names[TEMP_REGNO]; |
1966 | fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n", | |
1967 | parallel, delta, name_add); | |
1968 | fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n", | |
1969 | delta, name_add); | |
36a05131 BS |
1970 | fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0); |
1971 | } | |
1972 | ||
34208acf AO |
1973 | if (TARGET_FDPIC) |
1974 | { | |
1975 | const char *name_pic = reg_names[FDPIC_REGNO]; | |
1976 | name_jmp = reg_names[FDPIC_FPTR_REGNO]; | |
1977 | ||
1978 | if (flag_pic != 1) | |
1979 | { | |
1980 | fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel); | |
1981 | assemble_name (file, name_func); | |
1982 | fprintf (file, "),%s\n", name_jmp); | |
1983 | ||
1984 | fprintf (file, "\tsetlo #gotofffuncdesclo("); | |
1985 | assemble_name (file, name_func); | |
1986 | fprintf (file, "),%s\n", name_jmp); | |
1987 | ||
1988 | fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp); | |
1989 | } | |
1990 | else | |
1991 | { | |
1992 | fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic); | |
1993 | assemble_name (file, name_func); | |
1994 | fprintf (file, "\t)), %s\n", name_jmp); | |
1995 | } | |
1996 | } | |
1997 | else if (!flag_pic) | |
36a05131 BS |
1998 | { |
1999 | fprintf (file, "\tsethi%s #hi(", parallel); | |
2000 | assemble_name (file, name_func); | |
2001 | fprintf (file, "),%s\n", name_jmp); | |
2002 | ||
2003 | fprintf (file, "\tsetlo #lo("); | |
2004 | assemble_name (file, name_func); | |
2005 | fprintf (file, "),%s\n", name_jmp); | |
2006 | } | |
2007 | else | |
2008 | { | |
2009 | /* Use JUMP_REGNO as a temporary PIC register. */ | |
2010 | const char *name_lr = reg_names[LR_REGNO]; | |
2011 | const char *name_gppic = name_jmp; | |
2012 | const char *name_tmp = reg_names[TEMP_REGNO]; | |
2013 | ||
2014 | fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp); | |
2015 | fprintf (file, "\tcall 1f\n"); | |
2016 | fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic); | |
2017 | fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr); | |
2018 | fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp); | |
2019 | fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp); | |
2020 | fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic); | |
2021 | ||
2022 | fprintf (file, "\tsethi%s #gprelhi(", parallel); | |
2023 | assemble_name (file, name_func); | |
2024 | fprintf (file, "),%s\n", name_tmp); | |
2025 | ||
2026 | fprintf (file, "\tsetlo #gprello("); | |
2027 | assemble_name (file, name_func); | |
2028 | fprintf (file, "),%s\n", name_tmp); | |
2029 | ||
2030 | fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp); | |
2031 | } | |
2032 | ||
87b483a1 | 2033 | /* Jump to the function address. */ |
36a05131 BS |
2034 | fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]); |
2035 | } | |
2036 | ||
2037 | \f | |
2038 | /* A C expression which is nonzero if a function must have and use a frame | |
2039 | pointer. This expression is evaluated in the reload pass. If its value is | |
2040 | nonzero the function will have a frame pointer. | |
2041 | ||
2042 | The expression can in principle examine the current function and decide | |
2043 | according to the facts, but on most machines the constant 0 or the constant | |
2044 | 1 suffices. Use 0 when the machine allows code to be generated with no | |
2045 | frame pointer, and doing so saves some time or space. Use 1 when there is | |
2046 | no possible advantage to avoiding a frame pointer. | |
2047 | ||
2048 | In certain cases, the compiler does not know how to produce valid code | |
2049 | without a frame pointer. The compiler recognizes those cases and | |
2050 | automatically gives the function a frame pointer regardless of what | |
2051 | `FRAME_POINTER_REQUIRED' says. You don't need to worry about them. | |
2052 | ||
2053 | In a function that does not require a frame pointer, the frame pointer | |
2054 | register can be allocated for ordinary usage, unless you mark it as a fixed | |
2055 | register. See `FIXED_REGISTERS' for more information. */ | |
2056 | ||
87b483a1 | 2057 | /* On frv, create a frame whenever we need to create stack. */ |
36a05131 BS |
2058 | |
2059 | int | |
f2206911 | 2060 | frv_frame_pointer_required (void) |
36a05131 | 2061 | { |
34208acf AO |
2062 | /* If we forgoing the usual linkage requirements, we only need |
2063 | a frame pointer if the stack pointer might change. */ | |
2064 | if (!TARGET_LINKED_FP) | |
2065 | return !current_function_sp_is_unchanging; | |
2066 | ||
36a05131 BS |
2067 | if (! current_function_is_leaf) |
2068 | return TRUE; | |
2069 | ||
2070 | if (get_frame_size () != 0) | |
2071 | return TRUE; | |
2072 | ||
2073 | if (cfun->stdarg) | |
2074 | return TRUE; | |
2075 | ||
2076 | if (!current_function_sp_is_unchanging) | |
2077 | return TRUE; | |
2078 | ||
34208acf | 2079 | if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table) |
36a05131 BS |
2080 | return TRUE; |
2081 | ||
2082 | if (profile_flag) | |
2083 | return TRUE; | |
2084 | ||
2085 | if (cfun->machine->frame_needed) | |
2086 | return TRUE; | |
2087 | ||
2088 | return FALSE; | |
2089 | } | |
2090 | ||
2091 | \f | |
2092 | /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the | |
2093 | initial difference between the specified pair of registers. This macro must | |
2094 | be defined if `ELIMINABLE_REGS' is defined. */ | |
2095 | ||
2096 | /* See frv_stack_info for more details on the frv stack frame. */ | |
2097 | ||
2098 | int | |
f2206911 | 2099 | frv_initial_elimination_offset (int from, int to) |
36a05131 BS |
2100 | { |
2101 | frv_stack_t *info = frv_stack_info (); | |
2102 | int ret = 0; | |
2103 | ||
2104 | if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM) | |
2105 | ret = info->total_size - info->pretend_size; | |
2106 | ||
2107 | else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM) | |
88d6a75f | 2108 | ret = info->reg_offset[FRAME_POINTER_REGNUM]; |
36a05131 BS |
2109 | |
2110 | else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM) | |
2111 | ret = (info->total_size | |
2112 | - info->reg_offset[FRAME_POINTER_REGNUM] | |
2113 | - info->pretend_size); | |
2114 | ||
2115 | else | |
2116 | abort (); | |
2117 | ||
2118 | if (TARGET_DEBUG_STACK) | |
2119 | fprintf (stderr, "Eliminate %s to %s by adding %d\n", | |
2120 | reg_names [from], reg_names[to], ret); | |
2121 | ||
2122 | return ret; | |
2123 | } | |
2124 | ||
2125 | \f | |
d8c2bed3 | 2126 | /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */ |
36a05131 | 2127 | |
d8c2bed3 | 2128 | static void |
f2206911 KC |
2129 | frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum, |
2130 | enum machine_mode mode, | |
2131 | tree type ATTRIBUTE_UNUSED, | |
2132 | int *pretend_size, | |
2133 | int second_time) | |
36a05131 BS |
2134 | { |
2135 | if (TARGET_DEBUG_ARG) | |
2136 | fprintf (stderr, | |
2137 | "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n", | |
2138 | *cum, GET_MODE_NAME (mode), *pretend_size, second_time); | |
2139 | } | |
2140 | ||
2141 | \f | |
b88cf82e | 2142 | /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */ |
36a05131 | 2143 | |
8ac411c7 | 2144 | static rtx |
f2206911 | 2145 | frv_expand_builtin_saveregs (void) |
36a05131 BS |
2146 | { |
2147 | int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS; | |
2148 | ||
2149 | if (TARGET_DEBUG_ARG) | |
2150 | fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n", | |
2151 | offset); | |
2152 | ||
f1c25d3b | 2153 | return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset)); |
36a05131 BS |
2154 | } |
2155 | ||
2156 | \f | |
2157 | /* Expand __builtin_va_start to do the va_start macro. */ | |
2158 | ||
2159 | void | |
f2206911 | 2160 | frv_expand_builtin_va_start (tree valist, rtx nextarg) |
36a05131 BS |
2161 | { |
2162 | tree t; | |
2163 | int num = cfun->args_info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS; | |
2164 | ||
2165 | nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, | |
2166 | GEN_INT (UNITS_PER_WORD * num)); | |
2167 | ||
2168 | if (TARGET_DEBUG_ARG) | |
2169 | { | |
2170 | fprintf (stderr, "va_start: args_info = %d, num = %d\n", | |
2171 | cfun->args_info, num); | |
2172 | ||
2173 | debug_rtx (nextarg); | |
2174 | } | |
2175 | ||
2176 | t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, | |
2177 | make_tree (ptr_type_node, nextarg)); | |
2178 | TREE_SIDE_EFFECTS (t) = 1; | |
2179 | ||
2180 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2181 | } | |
2182 | ||
36a05131 BS |
2183 | \f |
2184 | /* Expand a block move operation, and return 1 if successful. Return 0 | |
2185 | if we should let the compiler generate normal code. | |
2186 | ||
2187 | operands[0] is the destination | |
2188 | operands[1] is the source | |
2189 | operands[2] is the length | |
2190 | operands[3] is the alignment */ | |
2191 | ||
2192 | /* Maximum number of loads to do before doing the stores */ | |
2193 | #ifndef MAX_MOVE_REG | |
2194 | #define MAX_MOVE_REG 4 | |
2195 | #endif | |
2196 | ||
2197 | /* Maximum number of total loads to do. */ | |
2198 | #ifndef TOTAL_MOVE_REG | |
2199 | #define TOTAL_MOVE_REG 8 | |
2200 | #endif | |
2201 | ||
2202 | int | |
f2206911 | 2203 | frv_expand_block_move (rtx operands[]) |
36a05131 BS |
2204 | { |
2205 | rtx orig_dest = operands[0]; | |
2206 | rtx orig_src = operands[1]; | |
2207 | rtx bytes_rtx = operands[2]; | |
2208 | rtx align_rtx = operands[3]; | |
2209 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); | |
2210 | int align; | |
2211 | int bytes; | |
2212 | int offset; | |
2213 | int num_reg; | |
2214 | int i; | |
2215 | rtx src_reg; | |
2216 | rtx dest_reg; | |
2217 | rtx src_addr; | |
2218 | rtx dest_addr; | |
2219 | rtx src_mem; | |
2220 | rtx dest_mem; | |
2221 | rtx tmp_reg; | |
2222 | rtx stores[MAX_MOVE_REG]; | |
2223 | int move_bytes; | |
2224 | enum machine_mode mode; | |
2225 | ||
87b483a1 | 2226 | /* If this is not a fixed size move, just call memcpy. */ |
36a05131 BS |
2227 | if (! constp) |
2228 | return FALSE; | |
2229 | ||
87b483a1 | 2230 | /* If this is not a fixed size alignment, abort. */ |
36a05131 BS |
2231 | if (GET_CODE (align_rtx) != CONST_INT) |
2232 | abort (); | |
2233 | ||
2234 | align = INTVAL (align_rtx); | |
2235 | ||
2236 | /* Anything to move? */ | |
2237 | bytes = INTVAL (bytes_rtx); | |
2238 | if (bytes <= 0) | |
2239 | return TRUE; | |
2240 | ||
2241 | /* Don't support real large moves. */ | |
2242 | if (bytes > TOTAL_MOVE_REG*align) | |
2243 | return FALSE; | |
2244 | ||
2245 | /* Move the address into scratch registers. */ | |
2246 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); | |
2247 | src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); | |
2248 | ||
2249 | num_reg = offset = 0; | |
2250 | for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) | |
2251 | { | |
87b483a1 | 2252 | /* Calculate the correct offset for src/dest. */ |
36a05131 BS |
2253 | if (offset == 0) |
2254 | { | |
2255 | src_addr = src_reg; | |
2256 | dest_addr = dest_reg; | |
2257 | } | |
2258 | else | |
2259 | { | |
2260 | src_addr = plus_constant (src_reg, offset); | |
2261 | dest_addr = plus_constant (dest_reg, offset); | |
2262 | } | |
2263 | ||
2264 | /* Generate the appropriate load and store, saving the stores | |
2265 | for later. */ | |
2266 | if (bytes >= 4 && align >= 4) | |
2267 | mode = SImode; | |
2268 | else if (bytes >= 2 && align >= 2) | |
2269 | mode = HImode; | |
2270 | else | |
2271 | mode = QImode; | |
2272 | ||
2273 | move_bytes = GET_MODE_SIZE (mode); | |
2274 | tmp_reg = gen_reg_rtx (mode); | |
2275 | src_mem = change_address (orig_src, mode, src_addr); | |
2276 | dest_mem = change_address (orig_dest, mode, dest_addr); | |
2277 | emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem)); | |
2278 | stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg); | |
2279 | ||
2280 | if (num_reg >= MAX_MOVE_REG) | |
2281 | { | |
2282 | for (i = 0; i < num_reg; i++) | |
2283 | emit_insn (stores[i]); | |
2284 | num_reg = 0; | |
2285 | } | |
2286 | } | |
2287 | ||
2288 | for (i = 0; i < num_reg; i++) | |
2289 | emit_insn (stores[i]); | |
2290 | ||
2291 | return TRUE; | |
2292 | } | |
2293 | ||
2294 | \f | |
2295 | /* Expand a block clear operation, and return 1 if successful. Return 0 | |
2296 | if we should let the compiler generate normal code. | |
2297 | ||
2298 | operands[0] is the destination | |
2299 | operands[1] is the length | |
2300 | operands[2] is the alignment */ | |
2301 | ||
2302 | int | |
f2206911 | 2303 | frv_expand_block_clear (rtx operands[]) |
36a05131 BS |
2304 | { |
2305 | rtx orig_dest = operands[0]; | |
2306 | rtx bytes_rtx = operands[1]; | |
2307 | rtx align_rtx = operands[2]; | |
2308 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); | |
2309 | int align; | |
2310 | int bytes; | |
2311 | int offset; | |
2312 | int num_reg; | |
2313 | rtx dest_reg; | |
2314 | rtx dest_addr; | |
2315 | rtx dest_mem; | |
2316 | int clear_bytes; | |
2317 | enum machine_mode mode; | |
2318 | ||
87b483a1 | 2319 | /* If this is not a fixed size move, just call memcpy. */ |
36a05131 BS |
2320 | if (! constp) |
2321 | return FALSE; | |
2322 | ||
87b483a1 | 2323 | /* If this is not a fixed size alignment, abort. */ |
36a05131 BS |
2324 | if (GET_CODE (align_rtx) != CONST_INT) |
2325 | abort (); | |
2326 | ||
2327 | align = INTVAL (align_rtx); | |
2328 | ||
2329 | /* Anything to move? */ | |
2330 | bytes = INTVAL (bytes_rtx); | |
2331 | if (bytes <= 0) | |
2332 | return TRUE; | |
2333 | ||
2334 | /* Don't support real large clears. */ | |
2335 | if (bytes > TOTAL_MOVE_REG*align) | |
2336 | return FALSE; | |
2337 | ||
2338 | /* Move the address into a scratch register. */ | |
2339 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); | |
2340 | ||
2341 | num_reg = offset = 0; | |
2342 | for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes)) | |
2343 | { | |
87b483a1 | 2344 | /* Calculate the correct offset for src/dest. */ |
36a05131 BS |
2345 | dest_addr = ((offset == 0) |
2346 | ? dest_reg | |
2347 | : plus_constant (dest_reg, offset)); | |
2348 | ||
87b483a1 | 2349 | /* Generate the appropriate store of gr0. */ |
36a05131 BS |
2350 | if (bytes >= 4 && align >= 4) |
2351 | mode = SImode; | |
2352 | else if (bytes >= 2 && align >= 2) | |
2353 | mode = HImode; | |
2354 | else | |
2355 | mode = QImode; | |
2356 | ||
2357 | clear_bytes = GET_MODE_SIZE (mode); | |
2358 | dest_mem = change_address (orig_dest, mode, dest_addr); | |
2359 | emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx)); | |
2360 | } | |
2361 | ||
2362 | return TRUE; | |
2363 | } | |
2364 | ||
2365 | \f | |
2366 | /* The following variable is used to output modifiers of assembler | |
87b483a1 | 2367 | code of the current output insn. */ |
36a05131 BS |
2368 | |
2369 | static rtx *frv_insn_operands; | |
2370 | ||
2371 | /* The following function is used to add assembler insn code suffix .p | |
87b483a1 | 2372 | if it is necessary. */ |
36a05131 BS |
2373 | |
2374 | const char * | |
f2206911 | 2375 | frv_asm_output_opcode (FILE *f, const char *ptr) |
36a05131 BS |
2376 | { |
2377 | int c; | |
2378 | ||
c557edf4 | 2379 | if (frv_insn_packing_flag <= 0) |
36a05131 BS |
2380 | return ptr; |
2381 | ||
2382 | for (; *ptr && *ptr != ' ' && *ptr != '\t';) | |
2383 | { | |
2384 | c = *ptr++; | |
2385 | if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z') | |
2386 | || (*ptr >= 'A' && *ptr <= 'Z'))) | |
2387 | { | |
2388 | int letter = *ptr++; | |
2389 | ||
2390 | c = atoi (ptr); | |
2391 | frv_print_operand (f, frv_insn_operands [c], letter); | |
2392 | while ((c = *ptr) >= '0' && c <= '9') | |
2393 | ptr++; | |
2394 | } | |
2395 | else | |
2396 | fputc (c, f); | |
2397 | } | |
2398 | ||
c557edf4 | 2399 | fprintf (f, ".p"); |
36a05131 BS |
2400 | |
2401 | return ptr; | |
2402 | } | |
2403 | ||
c557edf4 RS |
2404 | /* Set up the packing bit for the current output insn. Note that this |
2405 | function is not called for asm insns. */ | |
36a05131 BS |
2406 | |
2407 | void | |
c557edf4 RS |
2408 | frv_final_prescan_insn (rtx insn, rtx *opvec, |
2409 | int noperands ATTRIBUTE_UNUSED) | |
36a05131 | 2410 | { |
c557edf4 | 2411 | if (INSN_P (insn)) |
36a05131 | 2412 | { |
c557edf4 RS |
2413 | if (frv_insn_packing_flag >= 0) |
2414 | { | |
2415 | frv_insn_operands = opvec; | |
2416 | frv_insn_packing_flag = PACKING_FLAG_P (insn); | |
2417 | } | |
2418 | else if (recog_memoized (insn) >= 0 | |
2419 | && get_attr_acc_group (insn) == ACC_GROUP_ODD) | |
2420 | /* Packing optimizations have been disabled, but INSN can only | |
2421 | be issued in M1. Insert an mnop in M0. */ | |
2422 | fprintf (asm_out_file, "\tmnop.p\n"); | |
36a05131 | 2423 | } |
36a05131 BS |
2424 | } |
2425 | ||
2426 | ||
2427 | \f | |
2428 | /* A C expression whose value is RTL representing the address in a stack frame | |
2429 | where the pointer to the caller's frame is stored. Assume that FRAMEADDR is | |
2430 | an RTL expression for the address of the stack frame itself. | |
2431 | ||
2432 | If you don't define this macro, the default is to return the value of | |
2433 | FRAMEADDR--that is, the stack frame address is also the address of the stack | |
2434 | word that points to the previous frame. */ | |
2435 | ||
2436 | /* The default is correct, but we need to make sure the frame gets created. */ | |
2437 | rtx | |
f2206911 | 2438 | frv_dynamic_chain_address (rtx frame) |
36a05131 BS |
2439 | { |
2440 | cfun->machine->frame_needed = 1; | |
2441 | return frame; | |
2442 | } | |
2443 | ||
2444 | ||
2445 | /* A C expression whose value is RTL representing the value of the return | |
2446 | address for the frame COUNT steps up from the current frame, after the | |
2447 | prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame | |
2448 | pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is | |
2449 | defined. | |
2450 | ||
2451 | The value of the expression must always be the correct address when COUNT is | |
2452 | zero, but may be `NULL_RTX' if there is not way to determine the return | |
2453 | address of other frames. */ | |
2454 | ||
2455 | rtx | |
34208acf | 2456 | frv_return_addr_rtx (int count, rtx frame) |
36a05131 | 2457 | { |
34208acf AO |
2458 | if (count != 0) |
2459 | return const0_rtx; | |
36a05131 BS |
2460 | cfun->machine->frame_needed = 1; |
2461 | return gen_rtx_MEM (Pmode, plus_constant (frame, 8)); | |
2462 | } | |
2463 | ||
2464 | /* Given a memory reference MEMREF, interpret the referenced memory as | |
2465 | an array of MODE values, and return a reference to the element | |
2466 | specified by INDEX. Assume that any pre-modification implicit in | |
2467 | MEMREF has already happened. | |
2468 | ||
2469 | MEMREF must be a legitimate operand for modes larger than SImode. | |
2470 | GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which | |
2471 | this function cannot handle. */ | |
2472 | rtx | |
f2206911 | 2473 | frv_index_memory (rtx memref, enum machine_mode mode, int index) |
36a05131 BS |
2474 | { |
2475 | rtx base = XEXP (memref, 0); | |
2476 | if (GET_CODE (base) == PRE_MODIFY) | |
2477 | base = XEXP (base, 0); | |
2478 | return change_address (memref, mode, | |
2479 | plus_constant (base, index * GET_MODE_SIZE (mode))); | |
2480 | } | |
2481 | ||
2482 | \f | |
2483 | /* Print a memory address as an operand to reference that memory location. */ | |
2484 | void | |
f2206911 | 2485 | frv_print_operand_address (FILE * stream, rtx x) |
36a05131 BS |
2486 | { |
2487 | if (GET_CODE (x) == MEM) | |
2488 | x = XEXP (x, 0); | |
2489 | ||
2490 | switch (GET_CODE (x)) | |
2491 | { | |
2492 | case REG: | |
2493 | fputs (reg_names [ REGNO (x)], stream); | |
2494 | return; | |
2495 | ||
2496 | case CONST_INT: | |
2497 | fprintf (stream, "%ld", (long) INTVAL (x)); | |
2498 | return; | |
2499 | ||
2500 | case SYMBOL_REF: | |
2501 | assemble_name (stream, XSTR (x, 0)); | |
2502 | return; | |
2503 | ||
2504 | case LABEL_REF: | |
2505 | case CONST: | |
2506 | output_addr_const (stream, x); | |
2507 | return; | |
2508 | ||
2509 | default: | |
2510 | break; | |
2511 | } | |
2512 | ||
2513 | fatal_insn ("Bad insn to frv_print_operand_address:", x); | |
2514 | } | |
2515 | ||
2516 | \f | |
2517 | static void | |
f2206911 | 2518 | frv_print_operand_memory_reference_reg (FILE * stream, rtx x) |
36a05131 BS |
2519 | { |
2520 | int regno = true_regnum (x); | |
2521 | if (GPR_P (regno)) | |
2522 | fputs (reg_names[regno], stream); | |
2523 | else | |
2524 | fatal_insn ("Bad register to frv_print_operand_memory_reference_reg:", x); | |
2525 | } | |
2526 | ||
2527 | /* Print a memory reference suitable for the ld/st instructions. */ | |
2528 | ||
2529 | static void | |
f2206911 | 2530 | frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset) |
36a05131 | 2531 | { |
34208acf | 2532 | struct frv_unspec unspec; |
36a05131 BS |
2533 | rtx x0 = NULL_RTX; |
2534 | rtx x1 = NULL_RTX; | |
2535 | ||
2536 | switch (GET_CODE (x)) | |
2537 | { | |
2538 | case SUBREG: | |
2539 | case REG: | |
2540 | x0 = x; | |
2541 | break; | |
2542 | ||
2543 | case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */ | |
2544 | x0 = XEXP (x, 0); | |
2545 | x1 = XEXP (XEXP (x, 1), 1); | |
2546 | break; | |
2547 | ||
2548 | case CONST_INT: | |
2549 | x1 = x; | |
2550 | break; | |
2551 | ||
2552 | case PLUS: | |
2553 | x0 = XEXP (x, 0); | |
2554 | x1 = XEXP (x, 1); | |
2555 | if (GET_CODE (x0) == CONST_INT) | |
2556 | { | |
2557 | x0 = XEXP (x, 1); | |
2558 | x1 = XEXP (x, 0); | |
2559 | } | |
2560 | break; | |
2561 | ||
2562 | default: | |
2563 | fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x); | |
2564 | break; | |
2565 | ||
2566 | } | |
2567 | ||
2568 | if (addr_offset) | |
2569 | { | |
2570 | if (!x1) | |
2571 | x1 = const0_rtx; | |
2572 | else if (GET_CODE (x1) != CONST_INT) | |
2573 | fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x); | |
2574 | } | |
2575 | ||
2576 | fputs ("@(", stream); | |
2577 | if (!x0) | |
2578 | fputs (reg_names[GPR_R0], stream); | |
2579 | else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG) | |
2580 | frv_print_operand_memory_reference_reg (stream, x0); | |
2581 | else | |
2582 | fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x); | |
2583 | ||
2584 | fputs (",", stream); | |
2585 | if (!x1) | |
2586 | fputs (reg_names [GPR_R0], stream); | |
2587 | ||
2588 | else | |
2589 | { | |
2590 | switch (GET_CODE (x1)) | |
2591 | { | |
2592 | case SUBREG: | |
2593 | case REG: | |
2594 | frv_print_operand_memory_reference_reg (stream, x1); | |
2595 | break; | |
2596 | ||
2597 | case CONST_INT: | |
2598 | fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset)); | |
2599 | break; | |
2600 | ||
36a05131 | 2601 | case CONST: |
34208acf AO |
2602 | if (!frv_const_unspec_p (x1, &unspec)) |
2603 | fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x1); | |
2604 | frv_output_const_unspec (stream, &unspec); | |
36a05131 BS |
2605 | break; |
2606 | ||
2607 | default: | |
2608 | fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x); | |
2609 | } | |
2610 | } | |
2611 | ||
2612 | fputs (")", stream); | |
2613 | } | |
2614 | ||
2615 | \f | |
2616 | /* Return 2 for likely branches and 0 for non-likely branches */ | |
2617 | ||
2618 | #define FRV_JUMP_LIKELY 2 | |
2619 | #define FRV_JUMP_NOT_LIKELY 0 | |
2620 | ||
2621 | static int | |
f2206911 | 2622 | frv_print_operand_jump_hint (rtx insn) |
36a05131 BS |
2623 | { |
2624 | rtx note; | |
2625 | rtx labelref; | |
2626 | int ret; | |
2627 | HOST_WIDE_INT prob = -1; | |
2628 | enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN; | |
2629 | ||
2630 | if (GET_CODE (insn) != JUMP_INSN) | |
2631 | abort (); | |
2632 | ||
2633 | /* Assume any non-conditional jump is likely. */ | |
2634 | if (! any_condjump_p (insn)) | |
2635 | ret = FRV_JUMP_LIKELY; | |
2636 | ||
2637 | else | |
2638 | { | |
2639 | labelref = condjump_label (insn); | |
2640 | if (labelref) | |
2641 | { | |
2642 | rtx label = XEXP (labelref, 0); | |
2643 | jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label)) | |
2644 | ? BACKWARD | |
2645 | : FORWARD); | |
2646 | } | |
2647 | ||
2648 | note = find_reg_note (insn, REG_BR_PROB, 0); | |
2649 | if (!note) | |
2650 | ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY); | |
2651 | ||
2652 | else | |
2653 | { | |
2654 | prob = INTVAL (XEXP (note, 0)); | |
2655 | ret = ((prob >= (REG_BR_PROB_BASE / 2)) | |
2656 | ? FRV_JUMP_LIKELY | |
2657 | : FRV_JUMP_NOT_LIKELY); | |
2658 | } | |
2659 | } | |
2660 | ||
2661 | #if 0 | |
2662 | if (TARGET_DEBUG) | |
2663 | { | |
2664 | char *direction; | |
2665 | ||
2666 | switch (jump_type) | |
2667 | { | |
2668 | default: | |
2669 | case UNKNOWN: direction = "unknown jump direction"; break; | |
2670 | case BACKWARD: direction = "jump backward"; break; | |
2671 | case FORWARD: direction = "jump forward"; break; | |
2672 | } | |
2673 | ||
2674 | fprintf (stderr, | |
2675 | "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n", | |
2676 | IDENTIFIER_POINTER (DECL_NAME (current_function_decl)), | |
2677 | (long)INSN_UID (insn), direction, (long)prob, | |
2678 | (long)REG_BR_PROB_BASE, ret); | |
2679 | } | |
2680 | #endif | |
2681 | ||
2682 | return ret; | |
2683 | } | |
2684 | ||
2685 | \f | |
43aa4e05 | 2686 | /* Print an operand to an assembler instruction. |
36a05131 BS |
2687 | |
2688 | `%' followed by a letter and a digit says to output an operand in an | |
2689 | alternate fashion. Four letters have standard, built-in meanings described | |
2690 | below. The machine description macro `PRINT_OPERAND' can define additional | |
2691 | letters with nonstandard meanings. | |
2692 | ||
2693 | `%cDIGIT' can be used to substitute an operand that is a constant value | |
2694 | without the syntax that normally indicates an immediate operand. | |
2695 | ||
2696 | `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated | |
2697 | before printing. | |
2698 | ||
2699 | `%aDIGIT' can be used to substitute an operand as if it were a memory | |
2700 | reference, with the actual operand treated as the address. This may be | |
2701 | useful when outputting a "load address" instruction, because often the | |
2702 | assembler syntax for such an instruction requires you to write the operand | |
2703 | as if it were a memory reference. | |
2704 | ||
2705 | `%lDIGIT' is used to substitute a `label_ref' into a jump instruction. | |
2706 | ||
2707 | `%=' outputs a number which is unique to each instruction in the entire | |
2708 | compilation. This is useful for making local labels to be referred to more | |
2709 | than once in a single template that generates multiple assembler | |
2710 | instructions. | |
2711 | ||
2712 | `%' followed by a punctuation character specifies a substitution that does | |
2713 | not use an operand. Only one case is standard: `%%' outputs a `%' into the | |
2714 | assembler code. Other nonstandard cases can be defined in the | |
2715 | `PRINT_OPERAND' macro. You must also define which punctuation characters | |
2716 | are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */ | |
2717 | ||
2718 | void | |
f2206911 | 2719 | frv_print_operand (FILE * file, rtx x, int code) |
36a05131 | 2720 | { |
34208acf | 2721 | struct frv_unspec unspec; |
36a05131 BS |
2722 | HOST_WIDE_INT value; |
2723 | int offset; | |
2724 | ||
2725 | if (code != 0 && !isalpha (code)) | |
2726 | value = 0; | |
2727 | ||
2728 | else if (GET_CODE (x) == CONST_INT) | |
2729 | value = INTVAL (x); | |
2730 | ||
2731 | else if (GET_CODE (x) == CONST_DOUBLE) | |
2732 | { | |
2733 | if (GET_MODE (x) == SFmode) | |
2734 | { | |
2735 | REAL_VALUE_TYPE rv; | |
2736 | long l; | |
2737 | ||
2738 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
2739 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
2740 | value = l; | |
2741 | } | |
2742 | ||
2743 | else if (GET_MODE (x) == VOIDmode) | |
2744 | value = CONST_DOUBLE_LOW (x); | |
2745 | ||
2746 | else | |
2747 | fatal_insn ("Bad insn in frv_print_operand, bad const_double", x); | |
2748 | } | |
2749 | ||
2750 | else | |
2751 | value = 0; | |
2752 | ||
2753 | switch (code) | |
2754 | { | |
2755 | ||
2756 | case '.': | |
87b483a1 | 2757 | /* Output r0. */ |
36a05131 BS |
2758 | fputs (reg_names[GPR_R0], file); |
2759 | break; | |
2760 | ||
2761 | case '#': | |
2762 | fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn)); | |
2763 | break; | |
2764 | ||
0f6e5d45 | 2765 | case '@': |
87b483a1 | 2766 | /* Output small data area base register (gr16). */ |
36a05131 BS |
2767 | fputs (reg_names[SDA_BASE_REG], file); |
2768 | break; | |
2769 | ||
2770 | case '~': | |
87b483a1 | 2771 | /* Output pic register (gr17). */ |
36a05131 BS |
2772 | fputs (reg_names[PIC_REGNO], file); |
2773 | break; | |
2774 | ||
2775 | case '*': | |
87b483a1 | 2776 | /* Output the temporary integer CCR register. */ |
36a05131 BS |
2777 | fputs (reg_names[ICR_TEMP], file); |
2778 | break; | |
2779 | ||
2780 | case '&': | |
87b483a1 | 2781 | /* Output the temporary integer CC register. */ |
36a05131 BS |
2782 | fputs (reg_names[ICC_TEMP], file); |
2783 | break; | |
2784 | ||
87b483a1 | 2785 | /* case 'a': print an address. */ |
36a05131 BS |
2786 | |
2787 | case 'C': | |
87b483a1 | 2788 | /* Print appropriate test for integer branch false operation. */ |
36a05131 BS |
2789 | switch (GET_CODE (x)) |
2790 | { | |
2791 | default: | |
2792 | fatal_insn ("Bad insn to frv_print_operand, 'C' modifier:", x); | |
2793 | ||
2794 | case EQ: fputs ("ne", file); break; | |
2795 | case NE: fputs ("eq", file); break; | |
2796 | case LT: fputs ("ge", file); break; | |
2797 | case LE: fputs ("gt", file); break; | |
2798 | case GT: fputs ("le", file); break; | |
2799 | case GE: fputs ("lt", file); break; | |
2800 | case LTU: fputs ("nc", file); break; | |
2801 | case LEU: fputs ("hi", file); break; | |
2802 | case GTU: fputs ("ls", file); break; | |
2803 | case GEU: fputs ("c", file); break; | |
2804 | } | |
2805 | break; | |
2806 | ||
2807 | /* case 'c': print a constant without the constant prefix. If | |
2808 | CONSTANT_ADDRESS_P(x) is not true, PRINT_OPERAND is called. */ | |
2809 | ||
2810 | case 'c': | |
87b483a1 | 2811 | /* Print appropriate test for integer branch true operation. */ |
36a05131 BS |
2812 | switch (GET_CODE (x)) |
2813 | { | |
2814 | default: | |
2815 | fatal_insn ("Bad insn to frv_print_operand, 'c' modifier:", x); | |
2816 | ||
2817 | case EQ: fputs ("eq", file); break; | |
2818 | case NE: fputs ("ne", file); break; | |
2819 | case LT: fputs ("lt", file); break; | |
2820 | case LE: fputs ("le", file); break; | |
2821 | case GT: fputs ("gt", file); break; | |
2822 | case GE: fputs ("ge", file); break; | |
2823 | case LTU: fputs ("c", file); break; | |
2824 | case LEU: fputs ("ls", file); break; | |
2825 | case GTU: fputs ("hi", file); break; | |
2826 | case GEU: fputs ("nc", file); break; | |
2827 | } | |
2828 | break; | |
2829 | ||
2830 | case 'e': | |
2831 | /* Print 1 for a NE and 0 for an EQ to give the final argument | |
2832 | for a conditional instruction. */ | |
2833 | if (GET_CODE (x) == NE) | |
2834 | fputs ("1", file); | |
2835 | ||
2836 | else if (GET_CODE (x) == EQ) | |
2837 | fputs ("0", file); | |
2838 | ||
2839 | else | |
2840 | fatal_insn ("Bad insn to frv_print_operand, 'e' modifier:", x); | |
2841 | break; | |
2842 | ||
2843 | case 'F': | |
87b483a1 | 2844 | /* Print appropriate test for floating point branch false operation. */ |
36a05131 BS |
2845 | switch (GET_CODE (x)) |
2846 | { | |
2847 | default: | |
2848 | fatal_insn ("Bad insn to frv_print_operand, 'F' modifier:", x); | |
2849 | ||
2850 | case EQ: fputs ("ne", file); break; | |
2851 | case NE: fputs ("eq", file); break; | |
2852 | case LT: fputs ("uge", file); break; | |
2853 | case LE: fputs ("ug", file); break; | |
2854 | case GT: fputs ("ule", file); break; | |
2855 | case GE: fputs ("ul", file); break; | |
2856 | } | |
2857 | break; | |
2858 | ||
2859 | case 'f': | |
87b483a1 | 2860 | /* Print appropriate test for floating point branch true operation. */ |
36a05131 BS |
2861 | switch (GET_CODE (x)) |
2862 | { | |
2863 | default: | |
2864 | fatal_insn ("Bad insn to frv_print_operand, 'f' modifier:", x); | |
2865 | ||
2866 | case EQ: fputs ("eq", file); break; | |
2867 | case NE: fputs ("ne", file); break; | |
2868 | case LT: fputs ("lt", file); break; | |
2869 | case LE: fputs ("le", file); break; | |
2870 | case GT: fputs ("gt", file); break; | |
2871 | case GE: fputs ("ge", file); break; | |
2872 | } | |
2873 | break; | |
2874 | ||
34208acf AO |
2875 | case 'g': |
2876 | /* Print appropriate GOT function. */ | |
2877 | if (GET_CODE (x) != CONST_INT) | |
2878 | fatal_insn ("Bad insn to frv_print_operand, 'g' modifier:", x); | |
2879 | fputs (unspec_got_name (INTVAL (x)), file); | |
2880 | break; | |
2881 | ||
36a05131 BS |
2882 | case 'I': |
2883 | /* Print 'i' if the operand is a constant, or is a memory reference that | |
87b483a1 | 2884 | adds a constant. */ |
36a05131 BS |
2885 | if (GET_CODE (x) == MEM) |
2886 | x = ((GET_CODE (XEXP (x, 0)) == PLUS) | |
2887 | ? XEXP (XEXP (x, 0), 1) | |
2888 | : XEXP (x, 0)); | |
34208acf AO |
2889 | else if (GET_CODE (x) == PLUS) |
2890 | x = XEXP (x, 1); | |
36a05131 BS |
2891 | |
2892 | switch (GET_CODE (x)) | |
2893 | { | |
2894 | default: | |
2895 | break; | |
2896 | ||
2897 | case CONST_INT: | |
2898 | case SYMBOL_REF: | |
2899 | case CONST: | |
2900 | fputs ("i", file); | |
2901 | break; | |
2902 | } | |
2903 | break; | |
2904 | ||
2905 | case 'i': | |
2906 | /* For jump instructions, print 'i' if the operand is a constant or | |
87b483a1 | 2907 | is an expression that adds a constant. */ |
36a05131 BS |
2908 | if (GET_CODE (x) == CONST_INT) |
2909 | fputs ("i", file); | |
2910 | ||
2911 | else | |
2912 | { | |
2913 | if (GET_CODE (x) == CONST_INT | |
2914 | || (GET_CODE (x) == PLUS | |
2915 | && (GET_CODE (XEXP (x, 1)) == CONST_INT | |
2916 | || GET_CODE (XEXP (x, 0)) == CONST_INT))) | |
2917 | fputs ("i", file); | |
2918 | } | |
2919 | break; | |
2920 | ||
2921 | case 'L': | |
2922 | /* Print the lower register of a double word register pair */ | |
2923 | if (GET_CODE (x) == REG) | |
2924 | fputs (reg_names[ REGNO (x)+1 ], file); | |
2925 | else | |
2926 | fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x); | |
2927 | break; | |
2928 | ||
87b483a1 | 2929 | /* case 'l': print a LABEL_REF. */ |
36a05131 BS |
2930 | |
2931 | case 'M': | |
2932 | case 'N': | |
2933 | /* Print a memory reference for ld/st/jmp, %N prints a memory reference | |
2934 | for the second word of double memory operations. */ | |
2935 | offset = (code == 'M') ? 0 : UNITS_PER_WORD; | |
2936 | switch (GET_CODE (x)) | |
2937 | { | |
2938 | default: | |
2939 | fatal_insn ("Bad insn to frv_print_operand, 'M/N' modifier:", x); | |
2940 | ||
2941 | case MEM: | |
2942 | frv_print_operand_memory_reference (file, XEXP (x, 0), offset); | |
2943 | break; | |
2944 | ||
2945 | case REG: | |
2946 | case SUBREG: | |
2947 | case CONST_INT: | |
2948 | case PLUS: | |
2949 | case SYMBOL_REF: | |
2950 | frv_print_operand_memory_reference (file, x, offset); | |
2951 | break; | |
2952 | } | |
2953 | break; | |
2954 | ||
2955 | case 'O': | |
2956 | /* Print the opcode of a command. */ | |
2957 | switch (GET_CODE (x)) | |
2958 | { | |
2959 | default: | |
2960 | fatal_insn ("Bad insn to frv_print_operand, 'O' modifier:", x); | |
2961 | ||
2962 | case PLUS: fputs ("add", file); break; | |
2963 | case MINUS: fputs ("sub", file); break; | |
2964 | case AND: fputs ("and", file); break; | |
2965 | case IOR: fputs ("or", file); break; | |
2966 | case XOR: fputs ("xor", file); break; | |
2967 | case ASHIFT: fputs ("sll", file); break; | |
2968 | case ASHIFTRT: fputs ("sra", file); break; | |
2969 | case LSHIFTRT: fputs ("srl", file); break; | |
2970 | } | |
2971 | break; | |
2972 | ||
87b483a1 | 2973 | /* case 'n': negate and print a constant int. */ |
36a05131 BS |
2974 | |
2975 | case 'P': | |
2976 | /* Print PIC label using operand as the number. */ | |
2977 | if (GET_CODE (x) != CONST_INT) | |
2978 | fatal_insn ("Bad insn to frv_print_operand, P modifier:", x); | |
2979 | ||
2980 | fprintf (file, ".LCF%ld", (long)INTVAL (x)); | |
2981 | break; | |
2982 | ||
2983 | case 'U': | |
87b483a1 | 2984 | /* Print 'u' if the operand is a update load/store. */ |
36a05131 BS |
2985 | if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY) |
2986 | fputs ("u", file); | |
2987 | break; | |
2988 | ||
2989 | case 'z': | |
87b483a1 | 2990 | /* If value is 0, print gr0, otherwise it must be a register. */ |
36a05131 BS |
2991 | if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0) |
2992 | fputs (reg_names[GPR_R0], file); | |
2993 | ||
2994 | else if (GET_CODE (x) == REG) | |
2995 | fputs (reg_names [REGNO (x)], file); | |
2996 | ||
2997 | else | |
2998 | fatal_insn ("Bad insn in frv_print_operand, z case", x); | |
2999 | break; | |
3000 | ||
3001 | case 'x': | |
87b483a1 | 3002 | /* Print constant in hex. */ |
36a05131 BS |
3003 | if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) |
3004 | { | |
3005 | fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value); | |
3006 | break; | |
3007 | } | |
3008 | ||
87b483a1 | 3009 | /* Fall through. */ |
36a05131 BS |
3010 | |
3011 | case '\0': | |
3012 | if (GET_CODE (x) == REG) | |
3013 | fputs (reg_names [REGNO (x)], file); | |
3014 | ||
3015 | else if (GET_CODE (x) == CONST_INT | |
3016 | || GET_CODE (x) == CONST_DOUBLE) | |
3017 | fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value); | |
3018 | ||
34208acf AO |
3019 | else if (frv_const_unspec_p (x, &unspec)) |
3020 | frv_output_const_unspec (file, &unspec); | |
3021 | ||
36a05131 BS |
3022 | else if (GET_CODE (x) == MEM) |
3023 | frv_print_operand_address (file, XEXP (x, 0)); | |
3024 | ||
3025 | else if (CONSTANT_ADDRESS_P (x)) | |
3026 | frv_print_operand_address (file, x); | |
3027 | ||
3028 | else | |
3029 | fatal_insn ("Bad insn in frv_print_operand, 0 case", x); | |
3030 | ||
3031 | break; | |
3032 | ||
3033 | default: | |
3034 | fatal_insn ("frv_print_operand: unknown code", x); | |
3035 | break; | |
3036 | } | |
3037 | ||
3038 | return; | |
3039 | } | |
3040 | ||
3041 | \f | |
3042 | /* A C statement (sans semicolon) for initializing the variable CUM for the | |
3043 | state at the beginning of the argument list. The variable has type | |
3044 | `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type | |
3045 | of the function which will receive the args, or 0 if the args are to a | |
3046 | compiler support library function. The value of INDIRECT is nonzero when | |
3047 | processing an indirect call, for example a call through a function pointer. | |
3048 | The value of INDIRECT is zero for a call to an explicitly named function, a | |
3049 | library function call, or when `INIT_CUMULATIVE_ARGS' is used to find | |
3050 | arguments for the function being compiled. | |
3051 | ||
3052 | When processing a call to a compiler support library function, LIBNAME | |
3053 | identifies which one. It is a `symbol_ref' rtx which contains the name of | |
3054 | the function, as a string. LIBNAME is 0 when an ordinary C function call is | |
3055 | being processed. Thus, each time this macro is called, either LIBNAME or | |
3056 | FNTYPE is nonzero, but never both of them at once. */ | |
3057 | ||
3058 | void | |
f2206911 KC |
3059 | frv_init_cumulative_args (CUMULATIVE_ARGS *cum, |
3060 | tree fntype, | |
3061 | rtx libname, | |
3062 | tree fndecl, | |
3063 | int incoming) | |
36a05131 BS |
3064 | { |
3065 | *cum = FIRST_ARG_REGNUM; | |
3066 | ||
3067 | if (TARGET_DEBUG_ARG) | |
3068 | { | |
3069 | fprintf (stderr, "\ninit_cumulative_args:"); | |
563a317a | 3070 | if (!fndecl && fntype) |
36a05131 BS |
3071 | fputs (" indirect", stderr); |
3072 | ||
3073 | if (incoming) | |
3074 | fputs (" incoming", stderr); | |
3075 | ||
3076 | if (fntype) | |
3077 | { | |
3078 | tree ret_type = TREE_TYPE (fntype); | |
3079 | fprintf (stderr, " return=%s,", | |
3080 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
3081 | } | |
3082 | ||
3083 | if (libname && GET_CODE (libname) == SYMBOL_REF) | |
3084 | fprintf (stderr, " libname=%s", XSTR (libname, 0)); | |
3085 | ||
3086 | if (cfun->returns_struct) | |
3087 | fprintf (stderr, " return-struct"); | |
3088 | ||
3089 | putc ('\n', stderr); | |
3090 | } | |
3091 | } | |
3092 | ||
3093 | \f | |
fe984136 RH |
3094 | /* Return true if we should pass an argument on the stack rather than |
3095 | in registers. */ | |
3096 | ||
3097 | static bool | |
3098 | frv_must_pass_in_stack (enum machine_mode mode, tree type) | |
3099 | { | |
3100 | if (mode == BLKmode) | |
3101 | return true; | |
3102 | if (type == NULL) | |
3103 | return false; | |
3104 | return AGGREGATE_TYPE_P (type); | |
3105 | } | |
3106 | ||
36a05131 BS |
3107 | /* If defined, a C expression that gives the alignment boundary, in bits, of an |
3108 | argument with the specified mode and type. If it is not defined, | |
3109 | `PARM_BOUNDARY' is used for all arguments. */ | |
3110 | ||
3111 | int | |
f2206911 KC |
3112 | frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED, |
3113 | tree type ATTRIBUTE_UNUSED) | |
36a05131 BS |
3114 | { |
3115 | return BITS_PER_WORD; | |
3116 | } | |
3117 | ||
36a05131 | 3118 | rtx |
f2206911 KC |
3119 | frv_function_arg (CUMULATIVE_ARGS *cum, |
3120 | enum machine_mode mode, | |
3121 | tree type ATTRIBUTE_UNUSED, | |
3122 | int named, | |
3123 | int incoming ATTRIBUTE_UNUSED) | |
36a05131 BS |
3124 | { |
3125 | enum machine_mode xmode = (mode == BLKmode) ? SImode : mode; | |
3126 | int arg_num = *cum; | |
3127 | rtx ret; | |
3128 | const char *debstr; | |
3129 | ||
3130 | /* Return a marker for use in the call instruction. */ | |
3131 | if (xmode == VOIDmode) | |
3132 | { | |
3133 | ret = const0_rtx; | |
3134 | debstr = "<0>"; | |
3135 | } | |
3136 | ||
3137 | else if (arg_num <= LAST_ARG_REGNUM) | |
3138 | { | |
f1c25d3b | 3139 | ret = gen_rtx_REG (xmode, arg_num); |
36a05131 BS |
3140 | debstr = reg_names[arg_num]; |
3141 | } | |
3142 | ||
3143 | else | |
3144 | { | |
3145 | ret = NULL_RTX; | |
3146 | debstr = "memory"; | |
3147 | } | |
3148 | ||
3149 | if (TARGET_DEBUG_ARG) | |
3150 | fprintf (stderr, | |
3151 | "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n", | |
3152 | arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr); | |
3153 | ||
3154 | return ret; | |
3155 | } | |
3156 | ||
3157 | \f | |
3158 | /* A C statement (sans semicolon) to update the summarizer variable CUM to | |
3159 | advance past an argument in the argument list. The values MODE, TYPE and | |
3160 | NAMED describe that argument. Once this is done, the variable CUM is | |
3161 | suitable for analyzing the *following* argument with `FUNCTION_ARG', etc. | |
3162 | ||
3163 | This macro need not do anything if the argument in question was passed on | |
3164 | the stack. The compiler knows how to track the amount of stack space used | |
3165 | for arguments without any special help. */ | |
3166 | ||
3167 | void | |
f2206911 KC |
3168 | frv_function_arg_advance (CUMULATIVE_ARGS *cum, |
3169 | enum machine_mode mode, | |
3170 | tree type ATTRIBUTE_UNUSED, | |
3171 | int named) | |
36a05131 BS |
3172 | { |
3173 | enum machine_mode xmode = (mode == BLKmode) ? SImode : mode; | |
3174 | int bytes = GET_MODE_SIZE (xmode); | |
3175 | int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
3176 | int arg_num = *cum; | |
3177 | ||
3178 | *cum = arg_num + words; | |
3179 | ||
3180 | if (TARGET_DEBUG_ARG) | |
3181 | fprintf (stderr, | |
3182 | "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n", | |
3183 | arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD); | |
3184 | } | |
3185 | ||
3186 | \f | |
3187 | /* A C expression for the number of words, at the beginning of an argument, | |
3188 | must be put in registers. The value must be zero for arguments that are | |
3189 | passed entirely in registers or that are entirely pushed on the stack. | |
3190 | ||
3191 | On some machines, certain arguments must be passed partially in registers | |
3192 | and partially in memory. On these machines, typically the first N words of | |
3193 | arguments are passed in registers, and the rest on the stack. If a | |
3194 | multi-word argument (a `double' or a structure) crosses that boundary, its | |
3195 | first few words must be passed in registers and the rest must be pushed. | |
3196 | This macro tells the compiler when this occurs, and how many of the words | |
3197 | should go in registers. | |
3198 | ||
3199 | `FUNCTION_ARG' for these arguments should return the first register to be | |
3200 | used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for | |
3201 | the called function. */ | |
3202 | ||
3203 | int | |
f2206911 KC |
3204 | frv_function_arg_partial_nregs (CUMULATIVE_ARGS *cum, |
3205 | enum machine_mode mode, | |
3206 | tree type ATTRIBUTE_UNUSED, | |
3207 | int named ATTRIBUTE_UNUSED) | |
36a05131 BS |
3208 | { |
3209 | enum machine_mode xmode = (mode == BLKmode) ? SImode : mode; | |
3210 | int bytes = GET_MODE_SIZE (xmode); | |
3211 | int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
3212 | int arg_num = *cum; | |
3213 | int ret; | |
3214 | ||
3215 | ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1) | |
3216 | ? LAST_ARG_REGNUM - arg_num + 1 | |
3217 | : 0); | |
3218 | ||
3219 | if (TARGET_DEBUG_ARG && ret) | |
3220 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
3221 | ||
3222 | return ret; | |
3223 | ||
3224 | } | |
3225 | ||
36a05131 BS |
3226 | \f |
3227 | /* Return true if a register is ok to use as a base or index register. */ | |
3228 | ||
3229 | static FRV_INLINE int | |
f2206911 | 3230 | frv_regno_ok_for_base_p (int regno, int strict_p) |
36a05131 BS |
3231 | { |
3232 | if (GPR_P (regno)) | |
3233 | return TRUE; | |
3234 | ||
3235 | if (strict_p) | |
3236 | return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno])); | |
3237 | ||
3238 | if (regno == ARG_POINTER_REGNUM) | |
3239 | return TRUE; | |
3240 | ||
3241 | return (regno >= FIRST_PSEUDO_REGISTER); | |
3242 | } | |
3243 | ||
3244 | \f | |
3245 | /* A C compound statement with a conditional `goto LABEL;' executed if X (an | |
3246 | RTX) is a legitimate memory address on the target machine for a memory | |
3247 | operand of mode MODE. | |
3248 | ||
3249 | It usually pays to define several simpler macros to serve as subroutines for | |
3250 | this one. Otherwise it may be too complicated to understand. | |
3251 | ||
3252 | This macro must exist in two variants: a strict variant and a non-strict | |
3253 | one. The strict variant is used in the reload pass. It must be defined so | |
3254 | that any pseudo-register that has not been allocated a hard register is | |
3255 | considered a memory reference. In contexts where some kind of register is | |
3256 | required, a pseudo-register with no hard register must be rejected. | |
3257 | ||
3258 | The non-strict variant is used in other passes. It must be defined to | |
3259 | accept all pseudo-registers in every context where some kind of register is | |
3260 | required. | |
3261 | ||
3262 | Compiler source files that want to use the strict variant of this macro | |
3263 | define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT' | |
3264 | conditional to define the strict variant in that case and the non-strict | |
3265 | variant otherwise. | |
3266 | ||
3267 | Subroutines to check for acceptable registers for various purposes (one for | |
3268 | base registers, one for index registers, and so on) are typically among the | |
3269 | subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these | |
3270 | subroutine macros need have two variants; the higher levels of macros may be | |
3271 | the same whether strict or not. | |
3272 | ||
3273 | Normally, constant addresses which are the sum of a `symbol_ref' and an | |
3274 | integer are stored inside a `const' RTX to mark them as constant. | |
3275 | Therefore, there is no need to recognize such sums specifically as | |
3276 | legitimate addresses. Normally you would simply recognize any `const' as | |
3277 | legitimate. | |
3278 | ||
3279 | Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that | |
3280 | are not marked with `const'. It assumes that a naked `plus' indicates | |
3281 | indexing. If so, then you *must* reject such naked constant sums as | |
3282 | illegitimate addresses, so that none of them will be given to | |
3283 | `PRINT_OPERAND_ADDRESS'. | |
3284 | ||
3285 | On some machines, whether a symbolic address is legitimate depends on the | |
3286 | section that the address refers to. On these machines, define the macro | |
3287 | `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and | |
3288 | then check for it here. When you see a `const', you will have to look | |
3289 | inside it to find the `symbol_ref' in order to determine the section. | |
3290 | ||
3291 | The best way to modify the name string is by adding text to the beginning, | |
3292 | with suitable punctuation to prevent any ambiguity. Allocate the new name | |
3293 | in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to | |
3294 | remove and decode the added text and output the name accordingly, and define | |
14966b94 | 3295 | `(* targetm.strip_name_encoding)' to access the original name string. |
36a05131 BS |
3296 | |
3297 | You can check the information stored here into the `symbol_ref' in the | |
3298 | definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and | |
3299 | `PRINT_OPERAND_ADDRESS'. */ | |
3300 | ||
3301 | int | |
f2206911 KC |
3302 | frv_legitimate_address_p (enum machine_mode mode, |
3303 | rtx x, | |
3304 | int strict_p, | |
34208acf AO |
3305 | int condexec_p, |
3306 | int allow_double_reg_p) | |
36a05131 BS |
3307 | { |
3308 | rtx x0, x1; | |
3309 | int ret = 0; | |
3310 | HOST_WIDE_INT value; | |
3311 | unsigned regno0; | |
3312 | ||
3313 | switch (GET_CODE (x)) | |
3314 | { | |
3315 | default: | |
3316 | break; | |
3317 | ||
3318 | case SUBREG: | |
3319 | x = SUBREG_REG (x); | |
3320 | if (GET_CODE (x) != REG) | |
3321 | break; | |
3322 | ||
87b483a1 | 3323 | /* Fall through. */ |
36a05131 BS |
3324 | |
3325 | case REG: | |
3326 | ret = frv_regno_ok_for_base_p (REGNO (x), strict_p); | |
3327 | break; | |
3328 | ||
3329 | case PRE_MODIFY: | |
3330 | x0 = XEXP (x, 0); | |
3331 | x1 = XEXP (x, 1); | |
3332 | if (GET_CODE (x0) != REG | |
3333 | || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p) | |
3334 | || GET_CODE (x1) != PLUS | |
3335 | || ! rtx_equal_p (x0, XEXP (x1, 0)) | |
3336 | || GET_CODE (XEXP (x1, 1)) != REG | |
3337 | || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p)) | |
3338 | break; | |
3339 | ||
3340 | ret = 1; | |
3341 | break; | |
3342 | ||
3343 | case CONST_INT: | |
3344 | /* 12 bit immediate */ | |
3345 | if (condexec_p) | |
3346 | ret = FALSE; | |
3347 | else | |
3348 | { | |
3349 | ret = IN_RANGE_P (INTVAL (x), -2048, 2047); | |
3350 | ||
3351 | /* If we can't use load/store double operations, make sure we can | |
3352 | address the second word. */ | |
3353 | if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
3354 | ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1, | |
3355 | -2048, 2047); | |
3356 | } | |
3357 | break; | |
3358 | ||
3359 | case PLUS: | |
3360 | x0 = XEXP (x, 0); | |
3361 | x1 = XEXP (x, 1); | |
3362 | ||
3363 | if (GET_CODE (x0) == SUBREG) | |
3364 | x0 = SUBREG_REG (x0); | |
3365 | ||
3366 | if (GET_CODE (x0) != REG) | |
3367 | break; | |
3368 | ||
3369 | regno0 = REGNO (x0); | |
3370 | if (!frv_regno_ok_for_base_p (regno0, strict_p)) | |
3371 | break; | |
3372 | ||
3373 | switch (GET_CODE (x1)) | |
3374 | { | |
3375 | default: | |
3376 | break; | |
3377 | ||
3378 | case SUBREG: | |
3379 | x1 = SUBREG_REG (x1); | |
3380 | if (GET_CODE (x1) != REG) | |
3381 | break; | |
3382 | ||
87b483a1 | 3383 | /* Fall through. */ |
36a05131 BS |
3384 | |
3385 | case REG: | |
87b483a1 KH |
3386 | /* Do not allow reg+reg addressing for modes > 1 word if we |
3387 | can't depend on having move double instructions. */ | |
34208acf | 3388 | if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD) |
36a05131 BS |
3389 | ret = FALSE; |
3390 | else | |
3391 | ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p); | |
3392 | break; | |
3393 | ||
3394 | case CONST_INT: | |
3395 | /* 12 bit immediate */ | |
3396 | if (condexec_p) | |
3397 | ret = FALSE; | |
3398 | else | |
3399 | { | |
3400 | value = INTVAL (x1); | |
3401 | ret = IN_RANGE_P (value, -2048, 2047); | |
3402 | ||
3403 | /* If we can't use load/store double operations, make sure we can | |
3404 | address the second word. */ | |
3405 | if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
3406 | ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047); | |
3407 | } | |
3408 | break; | |
3409 | ||
36a05131 | 3410 | case CONST: |
34208acf | 3411 | if (!condexec_p && got12_operand (x1, VOIDmode)) |
36a05131 BS |
3412 | ret = TRUE; |
3413 | break; | |
3414 | ||
3415 | } | |
3416 | break; | |
3417 | } | |
3418 | ||
3419 | if (TARGET_DEBUG_ADDR) | |
3420 | { | |
3421 | fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n", | |
3422 | GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ", | |
3423 | (condexec_p) ? ", inside conditional code" : ""); | |
3424 | debug_rtx (x); | |
3425 | } | |
3426 | ||
3427 | return ret; | |
3428 | } | |
3429 | ||
3430 | \f | |
34208acf AO |
3431 | /* Test whether a local function descriptor is canonical, i.e., |
3432 | whether we can use FUNCDESC_GOTOFF to compute the address of the | |
3433 | function. */ | |
3434 | ||
3435 | static bool | |
3436 | frv_local_funcdesc_p (rtx fnx) | |
3437 | { | |
3438 | tree fn; | |
3439 | enum symbol_visibility vis; | |
3440 | bool ret; | |
36a05131 | 3441 | |
34208acf AO |
3442 | if (! SYMBOL_REF_LOCAL_P (fnx)) |
3443 | return FALSE; | |
3444 | ||
3445 | fn = SYMBOL_REF_DECL (fnx); | |
3446 | ||
3447 | if (! fn) | |
3448 | return FALSE; | |
36a05131 | 3449 | |
34208acf | 3450 | vis = DECL_VISIBILITY (fn); |
36a05131 | 3451 | |
34208acf AO |
3452 | if (vis == VISIBILITY_PROTECTED) |
3453 | /* Private function descriptors for protected functions are not | |
3454 | canonical. Temporarily change the visibility to global. */ | |
3455 | vis = VISIBILITY_DEFAULT; | |
3456 | else if (flag_shlib) | |
3457 | /* If we're already compiling for a shared library (that, unlike | |
3458 | executables, can't assume that the existence of a definition | |
3459 | implies local binding), we can skip the re-testing. */ | |
3460 | return TRUE; | |
36a05131 | 3461 | |
34208acf | 3462 | ret = default_binds_local_p_1 (fn, flag_pic); |
36a05131 | 3463 | |
34208acf AO |
3464 | DECL_VISIBILITY (fn) = vis; |
3465 | ||
3466 | return ret; | |
3467 | } | |
3468 | ||
3469 | /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC | |
3470 | register. */ | |
36a05131 BS |
3471 | |
3472 | rtx | |
34208acf AO |
3473 | frv_gen_GPsym2reg (rtx dest, rtx src) |
3474 | { | |
3475 | tree gp = get_identifier ("_gp"); | |
3476 | rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp)); | |
36a05131 | 3477 | |
34208acf AO |
3478 | return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12)); |
3479 | } | |
3480 | ||
3481 | static const char * | |
3482 | unspec_got_name (int i) | |
3483 | { | |
3484 | switch (i) | |
36a05131 | 3485 | { |
34208acf AO |
3486 | case R_FRV_GOT12: return "got12"; |
3487 | case R_FRV_GOTHI: return "gothi"; | |
3488 | case R_FRV_GOTLO: return "gotlo"; | |
3489 | case R_FRV_FUNCDESC: return "funcdesc"; | |
3490 | case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12"; | |
3491 | case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi"; | |
3492 | case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo"; | |
3493 | case R_FRV_FUNCDESC_VALUE: return "funcdescvalue"; | |
3494 | case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12"; | |
3495 | case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi"; | |
3496 | case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo"; | |
3497 | case R_FRV_GOTOFF12: return "gotoff12"; | |
3498 | case R_FRV_GOTOFFHI: return "gotoffhi"; | |
3499 | case R_FRV_GOTOFFLO: return "gotofflo"; | |
3500 | case R_FRV_GPREL12: return "gprel12"; | |
3501 | case R_FRV_GPRELHI: return "gprelhi"; | |
3502 | case R_FRV_GPRELLO: return "gprello"; | |
3503 | default: abort (); | |
36a05131 | 3504 | } |
34208acf | 3505 | } |
36a05131 | 3506 | |
34208acf AO |
3507 | /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset |
3508 | is added inside the relocation operator. */ | |
3509 | ||
3510 | static void | |
3511 | frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec) | |
3512 | { | |
3513 | fprintf (stream, "#%s(", unspec_got_name (unspec->reloc)); | |
3514 | output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset)); | |
3515 | fputs (")", stream); | |
3516 | } | |
3517 | ||
3518 | /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo) | |
3519 | or #gotoff12(foo) for some small data symbol foo. If so, return foo, | |
3520 | otherwise return ORIG_X. */ | |
3521 | ||
3522 | rtx | |
3523 | frv_find_base_term (rtx x) | |
3524 | { | |
3525 | struct frv_unspec unspec; | |
3526 | ||
3527 | if (frv_const_unspec_p (x, &unspec) | |
3528 | && frv_small_data_reloc_p (unspec.symbol, unspec.reloc)) | |
3529 | return plus_constant (unspec.symbol, unspec.offset); | |
3530 | ||
3531 | return x; | |
36a05131 BS |
3532 | } |
3533 | ||
3534 | /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if | |
3535 | the operand is used by a predicated instruction. */ | |
3536 | ||
3537 | static int | |
f2206911 | 3538 | frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p) |
36a05131 BS |
3539 | { |
3540 | return ((GET_MODE (op) == mode || mode == VOIDmode) | |
3541 | && GET_CODE (op) == MEM | |
3542 | && frv_legitimate_address_p (mode, XEXP (op, 0), | |
34208acf AO |
3543 | reload_completed, condexec_p, FALSE)); |
3544 | } | |
3545 | ||
3546 | void | |
764678d1 | 3547 | frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall) |
34208acf AO |
3548 | { |
3549 | rtx lr = gen_rtx_REG (Pmode, LR_REGNO); | |
3550 | rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG); | |
3551 | rtx c, rvrtx=0; | |
3552 | rtx addr; | |
3553 | ||
3554 | if (ret_value) | |
3555 | { | |
3556 | rvrtx = operands[0]; | |
3557 | operands ++; | |
3558 | } | |
3559 | ||
3560 | addr = XEXP (operands[0], 0); | |
3561 | ||
3562 | /* Inline PLTs if we're optimizing for speed. We'd like to inline | |
3563 | any calls that would involve a PLT, but can't tell, since we | |
3564 | don't know whether an extern function is going to be provided by | |
3565 | a separate translation unit or imported from a separate module. | |
3566 | When compiling for shared libraries, if the function has default | |
3567 | visibility, we assume it's overridable, so we inline the PLT, but | |
3568 | for executables, we don't really have a way to make a good | |
3569 | decision: a function is as likely to be imported from a shared | |
3570 | library as it is to be defined in the executable itself. We | |
3571 | assume executables will get global functions defined locally, | |
3572 | whereas shared libraries will have them potentially overridden, | |
3573 | so we only inline PLTs when compiling for shared libraries. | |
3574 | ||
3575 | In order to mark a function as local to a shared library, any | |
3576 | non-default visibility attribute suffices. Unfortunately, | |
3577 | there's no simple way to tag a function declaration as ``in a | |
3578 | different module'', which we could then use to trigger PLT | |
3579 | inlining on executables. There's -minline-plt, but it affects | |
3580 | all external functions, so one would have to also mark function | |
3581 | declarations available in the same module with non-default | |
3582 | visibility, which is advantageous in itself. */ | |
764678d1 AO |
3583 | if (GET_CODE (addr) == SYMBOL_REF |
3584 | && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT) | |
3585 | || sibcall)) | |
34208acf AO |
3586 | { |
3587 | rtx x, dest; | |
3588 | dest = gen_reg_rtx (SImode); | |
3589 | if (flag_pic != 1) | |
3590 | x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG, | |
3591 | GEN_INT (R_FRV_FUNCDESC_GOTOFF12)); | |
3592 | else | |
3593 | x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG, | |
3594 | GEN_INT (R_FRV_FUNCDESC_GOTOFF12)); | |
3595 | emit_insn (x); | |
3596 | cfun->uses_pic_offset_table = TRUE; | |
3597 | addr = dest; | |
3598 | } | |
3599 | else if (GET_CODE (addr) == SYMBOL_REF) | |
3600 | { | |
3601 | /* These are always either local, or handled through a local | |
3602 | PLT. */ | |
3603 | if (ret_value) | |
3604 | c = gen_call_value_fdpicsi (rvrtx, addr, operands[1], | |
3605 | operands[2], picreg, lr); | |
3606 | else | |
3607 | c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr); | |
3608 | emit_call_insn (c); | |
3609 | return; | |
3610 | } | |
3611 | else if (! ldd_address_operand (addr, Pmode)) | |
3612 | addr = force_reg (Pmode, addr); | |
3613 | ||
3614 | picreg = gen_reg_rtx (DImode); | |
3615 | emit_insn (gen_movdi_ldd (picreg, addr)); | |
3616 | ||
764678d1 AO |
3617 | if (sibcall && ret_value) |
3618 | c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx); | |
3619 | else if (sibcall) | |
3620 | c = gen_sibcall_fdpicdi (picreg, const0_rtx); | |
3621 | else if (ret_value) | |
34208acf AO |
3622 | c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr); |
3623 | else | |
3624 | c = gen_call_fdpicdi (picreg, const0_rtx, lr); | |
3625 | emit_call_insn (c); | |
36a05131 BS |
3626 | } |
3627 | ||
34208acf AO |
3628 | /* An address operand that may use a pair of registers, an addressing |
3629 | mode that we reject in general. */ | |
3630 | ||
3631 | int | |
3632 | ldd_address_operand (rtx x, enum machine_mode mode) | |
3633 | { | |
3634 | if (GET_MODE (x) != mode && GET_MODE (x) != VOIDmode) | |
3635 | return FALSE; | |
3636 | ||
3637 | return frv_legitimate_address_p (DImode, x, reload_completed, FALSE, TRUE); | |
3638 | } | |
3639 | ||
3640 | int | |
3641 | fdpic_fptr_operand (rtx op, enum machine_mode mode) | |
3642 | { | |
3643 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3644 | return FALSE; | |
3645 | if (GET_CODE (op) != REG) | |
3646 | return FALSE; | |
3647 | if (REGNO (op) != FDPIC_FPTR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER) | |
3648 | return FALSE; | |
3649 | return TRUE; | |
3650 | } | |
36a05131 BS |
3651 | \f |
3652 | /* Return 1 is OP is a memory operand, or will be turned into one by | |
3653 | reload. */ | |
3654 | ||
f2206911 KC |
3655 | int |
3656 | frv_load_operand (rtx op, enum machine_mode mode) | |
36a05131 BS |
3657 | { |
3658 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3659 | return FALSE; | |
3660 | ||
3661 | if (reload_in_progress) | |
3662 | { | |
3663 | rtx tmp = op; | |
3664 | if (GET_CODE (tmp) == SUBREG) | |
3665 | tmp = SUBREG_REG (tmp); | |
3666 | if (GET_CODE (tmp) == REG | |
3667 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER) | |
3668 | op = reg_equiv_memory_loc[REGNO (tmp)]; | |
3669 | } | |
3670 | ||
3671 | return op && memory_operand (op, mode); | |
3672 | } | |
3673 | ||
3674 | ||
3675 | /* Return 1 if operand is a GPR register or a FPR register. */ | |
3676 | ||
f2206911 KC |
3677 | int |
3678 | gpr_or_fpr_operand (rtx op, enum machine_mode mode) | |
36a05131 BS |
3679 | { |
3680 | int regno; | |
3681 | ||
3682 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3683 | return FALSE; | |
3684 | ||
3685 | if (GET_CODE (op) == SUBREG) | |
3686 | { | |
3687 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
3688 | return register_operand (op, mode); | |
3689 | ||
3690 | op = SUBREG_REG (op); | |
3691 | } | |
3692 | ||
3693 | if (GET_CODE (op) != REG) | |
3694 | return FALSE; | |
3695 | ||
3696 | regno = REGNO (op); | |
3697 | if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER) | |
3698 | return TRUE; | |
3699 | ||
3700 | return FALSE; | |
3701 | } | |
3702 | ||
3703 | /* Return 1 if operand is a GPR register or 12 bit signed immediate. */ | |
3704 | ||
f2206911 KC |
3705 | int |
3706 | gpr_or_int12_operand (rtx op, enum machine_mode mode) | |
36a05131 BS |
3707 | { |
3708 | if (GET_CODE (op) == CONST_INT) | |
3709 | return IN_RANGE_P (INTVAL (op), -2048, 2047); | |
3710 | ||
34208acf AO |
3711 | if (got12_operand (op, mode)) |
3712 | return true; | |
3713 | ||
36a05131 BS |
3714 | if (GET_MODE (op) != mode && mode != VOIDmode) |
3715 | return FALSE; | |
3716 | ||
3717 | if (GET_CODE (op) == SUBREG) | |
3718 | { | |
3719 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
3720 | return register_operand (op, mode); | |
3721 | ||
3722 | op = SUBREG_REG (op); | |
3723 | } | |
3724 | ||
3725 | if (GET_CODE (op) != REG) | |
3726 | return FALSE; | |
3727 | ||
3728 | return GPR_OR_PSEUDO_P (REGNO (op)); | |
3729 | } | |
3730 | ||
3731 | /* Return 1 if operand is a GPR register, or a FPR register, or a 12 bit | |
3732 | signed immediate. */ | |
3733 | ||
f2206911 KC |
3734 | int |
3735 | gpr_fpr_or_int12_operand (rtx op, enum machine_mode mode) | |
36a05131 BS |
3736 | { |
3737 | int regno; | |
3738 | ||
3739 | if (GET_CODE (op) == CONST_INT) | |
3740 | return IN_RANGE_P (INTVAL (op), -2048, 2047); | |
3741 | ||
3742 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3743 | return FALSE; | |
3744 | ||
3745 | if (GET_CODE (op) == SUBREG) | |
3746 | { | |
3747 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
3748 | return register_operand (op, mode); | |
3749 | ||
3750 | op = SUBREG_REG (op); | |
3751 | } | |
3752 | ||
3753 | if (GET_CODE (op) != REG) | |
3754 | return FALSE; | |
3755 | ||
3756 | regno = REGNO (op); | |
3757 | if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER) | |
3758 | return TRUE; | |
3759 | ||
3760 | return FALSE; | |
3761 | } | |
3762 | ||
3763 | /* Return 1 if operand is a register or 6 bit signed immediate. */ | |
3764 | ||
f2206911 KC |
3765 | int |
3766 | fpr_or_int6_operand (rtx op, enum machine_mode mode) | |
36a05131 BS |
3767 | { |
3768 | if (GET_CODE (op) == CONST_INT) | |
3769 | return IN_RANGE_P (INTVAL (op), -32, 31); | |
3770 | ||
3771 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3772 | return FALSE; | |
3773 | ||
3774 | if (GET_CODE (op) == SUBREG) | |
3775 | { | |
3776 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
3777 | return register_operand (op, mode); | |
3778 | ||
3779 | op = SUBREG_REG (op); | |
3780 | } | |
3781 | ||
3782 | if (GET_CODE (op) != REG) | |
3783 | return FALSE; | |
3784 | ||
3785 | return FPR_OR_PSEUDO_P (REGNO (op)); | |
3786 | } | |
3787 | ||
3788 | /* Return 1 if operand is a register or 10 bit signed immediate. */ | |
3789 | ||
f2206911 KC |
3790 | int |
3791 | gpr_or_int10_operand (rtx op, enum machine_mode mode) | |
36a05131 BS |
3792 | { |
3793 | if (GET_CODE (op) == CONST_INT) | |
3794 | return IN_RANGE_P (INTVAL (op), -512, 511); | |
3795 | ||
3796 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3797 | return FALSE; | |
3798 | ||
3799 | if (GET_CODE (op) == SUBREG) | |
3800 | { | |
3801 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
3802 | return register_operand (op, mode); | |
3803 | ||
3804 | op = SUBREG_REG (op); | |
3805 | } | |
3806 | ||
3807 | if (GET_CODE (op) != REG) | |
3808 | return FALSE; | |
3809 | ||
3810 | return GPR_OR_PSEUDO_P (REGNO (op)); | |
3811 | } | |
3812 | ||
3813 | /* Return 1 if operand is a register or an integer immediate. */ | |
3814 | ||
f2206911 KC |
3815 | int |
3816 | gpr_or_int_operand (rtx op, enum machine_mode mode) | |
36a05131 BS |
3817 | { |
3818 | if (GET_CODE (op) == CONST_INT) | |
3819 | return TRUE; | |
3820 | ||
3821 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3822 | return FALSE; | |
3823 | ||
3824 | if (GET_CODE (op) == SUBREG) | |
3825 | { | |
3826 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
3827 | return register_operand (op, mode); | |
3828 | ||
3829 | op = SUBREG_REG (op); | |
3830 | } | |
3831 | ||
3832 | if (GET_CODE (op) != REG) | |
3833 | return FALSE; | |
3834 | ||
3835 | return GPR_OR_PSEUDO_P (REGNO (op)); | |
3836 | } | |
3837 | ||
3838 | /* Return 1 if operand is a 12 bit signed immediate. */ | |
3839 | ||
f2206911 KC |
3840 | int |
3841 | int12_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
36a05131 BS |
3842 | { |
3843 | if (GET_CODE (op) != CONST_INT) | |
3844 | return FALSE; | |
3845 | ||
3846 | return IN_RANGE_P (INTVAL (op), -2048, 2047); | |
3847 | } | |
3848 | ||
3849 | /* Return 1 if operand is a 6 bit signed immediate. */ | |
3850 | ||
f2206911 KC |
3851 | int |
3852 | int6_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
36a05131 BS |
3853 | { |
3854 | if (GET_CODE (op) != CONST_INT) | |
3855 | return FALSE; | |
3856 | ||
3857 | return IN_RANGE_P (INTVAL (op), -32, 31); | |
3858 | } | |
3859 | ||
3860 | /* Return 1 if operand is a 5 bit signed immediate. */ | |
3861 | ||
f2206911 KC |
3862 | int |
3863 | int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
36a05131 BS |
3864 | { |
3865 | return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), -16, 15); | |
3866 | } | |
3867 | ||
3868 | /* Return 1 if operand is a 5 bit unsigned immediate. */ | |
3869 | ||
f2206911 KC |
3870 | int |
3871 | uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
36a05131 BS |
3872 | { |
3873 | return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 31); | |
3874 | } | |
3875 | ||
3876 | /* Return 1 if operand is a 4 bit unsigned immediate. */ | |
3877 | ||
f2206911 KC |
3878 | int |
3879 | uint4_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
36a05131 BS |
3880 | { |
3881 | return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 15); | |
3882 | } | |
3883 | ||
3884 | /* Return 1 if operand is a 1 bit unsigned immediate (0 or 1). */ | |
3885 | ||
f2206911 KC |
3886 | int |
3887 | uint1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
36a05131 BS |
3888 | { |
3889 | return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 1); | |
3890 | } | |
3891 | ||
3892 | /* Return 1 if operand is an integer constant that takes 2 instructions | |
3893 | to load up and can be split into sethi/setlo instructions.. */ | |
3894 | ||
f2206911 | 3895 | int |
34208acf | 3896 | int_2word_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
36a05131 BS |
3897 | { |
3898 | HOST_WIDE_INT value; | |
3899 | REAL_VALUE_TYPE rv; | |
3900 | long l; | |
3901 | ||
3902 | switch (GET_CODE (op)) | |
3903 | { | |
3904 | default: | |
3905 | break; | |
3906 | ||
3907 | case LABEL_REF: | |
34208acf AO |
3908 | if (TARGET_FDPIC) |
3909 | return FALSE; | |
3910 | ||
36a05131 BS |
3911 | return (flag_pic == 0); |
3912 | ||
3913 | case CONST: | |
34208acf AO |
3914 | if (flag_pic || TARGET_FDPIC) |
3915 | return FALSE; | |
3916 | ||
3917 | op = XEXP (op, 0); | |
3918 | if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT) | |
3919 | op = XEXP (op, 0); | |
3920 | return GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF; | |
36a05131 BS |
3921 | |
3922 | case SYMBOL_REF: | |
34208acf AO |
3923 | if (TARGET_FDPIC) |
3924 | return FALSE; | |
3925 | ||
36a05131 | 3926 | /* small data references are already 1 word */ |
0f6e5d45 | 3927 | return (flag_pic == 0) && (! SYMBOL_REF_SMALL_P (op)); |
36a05131 BS |
3928 | |
3929 | case CONST_INT: | |
3930 | return ! IN_RANGE_P (INTVAL (op), -32768, 32767); | |
3931 | ||
3932 | case CONST_DOUBLE: | |
3933 | if (GET_MODE (op) == SFmode) | |
3934 | { | |
3935 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
3936 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
3937 | value = l; | |
3938 | return ! IN_RANGE_P (value, -32768, 32767); | |
3939 | } | |
3940 | else if (GET_MODE (op) == VOIDmode) | |
3941 | { | |
3942 | value = CONST_DOUBLE_LOW (op); | |
3943 | return ! IN_RANGE_P (value, -32768, 32767); | |
3944 | } | |
3945 | break; | |
3946 | } | |
3947 | ||
3948 | return FALSE; | |
3949 | } | |
3950 | ||
87b483a1 | 3951 | /* Return 1 if operand is a 16 bit unsigned immediate. */ |
36a05131 | 3952 | |
f2206911 KC |
3953 | int |
3954 | uint16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
36a05131 BS |
3955 | { |
3956 | if (GET_CODE (op) != CONST_INT) | |
3957 | return FALSE; | |
3958 | ||
3959 | return IN_RANGE_P (INTVAL (op), 0, 0xffff); | |
3960 | } | |
3961 | ||
87b483a1 KH |
3962 | /* Return 1 if operand is an integer constant with the bottom 16 bits |
3963 | clear. */ | |
36a05131 | 3964 | |
f2206911 KC |
3965 | int |
3966 | upper_int16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
36a05131 BS |
3967 | { |
3968 | if (GET_CODE (op) != CONST_INT) | |
3969 | return FALSE; | |
3970 | ||
3971 | return ((INTVAL (op) & 0xffff) == 0); | |
3972 | } | |
3973 | ||
87b483a1 | 3974 | /* Return true if operand is a GPR register. */ |
36a05131 BS |
3975 | |
3976 | int | |
f2206911 | 3977 | integer_register_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
3978 | { |
3979 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3980 | return FALSE; | |
3981 | ||
3982 | if (GET_CODE (op) == SUBREG) | |
3983 | { | |
3984 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
3985 | return register_operand (op, mode); | |
3986 | ||
3987 | op = SUBREG_REG (op); | |
3988 | } | |
3989 | ||
3990 | if (GET_CODE (op) != REG) | |
3991 | return FALSE; | |
3992 | ||
3993 | return GPR_OR_PSEUDO_P (REGNO (op)); | |
3994 | } | |
3995 | ||
3996 | /* Return true if operand is a GPR register. Do not allow SUBREG's | |
3997 | here, in order to prevent a combine bug. */ | |
3998 | ||
3999 | int | |
f2206911 | 4000 | gpr_no_subreg_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4001 | { |
4002 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4003 | return FALSE; | |
4004 | ||
4005 | if (GET_CODE (op) != REG) | |
4006 | return FALSE; | |
4007 | ||
4008 | return GPR_OR_PSEUDO_P (REGNO (op)); | |
4009 | } | |
4010 | ||
87b483a1 | 4011 | /* Return true if operand is a FPR register. */ |
36a05131 BS |
4012 | |
4013 | int | |
f2206911 | 4014 | fpr_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4015 | { |
4016 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4017 | return FALSE; | |
4018 | ||
4019 | if (GET_CODE (op) == SUBREG) | |
4020 | { | |
4021 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
4022 | return register_operand (op, mode); | |
4023 | ||
4024 | op = SUBREG_REG (op); | |
4025 | } | |
4026 | ||
4027 | if (GET_CODE (op) != REG) | |
4028 | return FALSE; | |
4029 | ||
4030 | return FPR_OR_PSEUDO_P (REGNO (op)); | |
4031 | } | |
4032 | ||
87b483a1 | 4033 | /* Return true if operand is an even GPR or FPR register. */ |
36a05131 BS |
4034 | |
4035 | int | |
f2206911 | 4036 | even_reg_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4037 | { |
4038 | int regno; | |
4039 | ||
4040 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4041 | return FALSE; | |
4042 | ||
4043 | if (GET_CODE (op) == SUBREG) | |
4044 | { | |
4045 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
4046 | return register_operand (op, mode); | |
4047 | ||
4048 | op = SUBREG_REG (op); | |
4049 | } | |
4050 | ||
4051 | if (GET_CODE (op) != REG) | |
4052 | return FALSE; | |
4053 | ||
4054 | regno = REGNO (op); | |
4055 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4056 | return TRUE; | |
4057 | ||
4058 | if (GPR_P (regno)) | |
4059 | return (((regno - GPR_FIRST) & 1) == 0); | |
4060 | ||
4061 | if (FPR_P (regno)) | |
4062 | return (((regno - FPR_FIRST) & 1) == 0); | |
4063 | ||
4064 | return FALSE; | |
4065 | } | |
4066 | ||
87b483a1 | 4067 | /* Return true if operand is an odd GPR register. */ |
36a05131 BS |
4068 | |
4069 | int | |
f2206911 | 4070 | odd_reg_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4071 | { |
4072 | int regno; | |
4073 | ||
4074 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4075 | return FALSE; | |
4076 | ||
4077 | if (GET_CODE (op) == SUBREG) | |
4078 | { | |
4079 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
4080 | return register_operand (op, mode); | |
4081 | ||
4082 | op = SUBREG_REG (op); | |
4083 | } | |
4084 | ||
4085 | if (GET_CODE (op) != REG) | |
4086 | return FALSE; | |
4087 | ||
4088 | regno = REGNO (op); | |
87b483a1 | 4089 | /* Assume that reload will give us an even register. */ |
36a05131 BS |
4090 | if (regno >= FIRST_PSEUDO_REGISTER) |
4091 | return FALSE; | |
4092 | ||
4093 | if (GPR_P (regno)) | |
4094 | return (((regno - GPR_FIRST) & 1) != 0); | |
4095 | ||
4096 | if (FPR_P (regno)) | |
4097 | return (((regno - FPR_FIRST) & 1) != 0); | |
4098 | ||
4099 | return FALSE; | |
4100 | } | |
4101 | ||
87b483a1 | 4102 | /* Return true if operand is an even GPR register. */ |
36a05131 BS |
4103 | |
4104 | int | |
f2206911 | 4105 | even_gpr_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4106 | { |
4107 | int regno; | |
4108 | ||
4109 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4110 | return FALSE; | |
4111 | ||
4112 | if (GET_CODE (op) == SUBREG) | |
4113 | { | |
4114 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
4115 | return register_operand (op, mode); | |
4116 | ||
4117 | op = SUBREG_REG (op); | |
4118 | } | |
4119 | ||
4120 | if (GET_CODE (op) != REG) | |
4121 | return FALSE; | |
4122 | ||
4123 | regno = REGNO (op); | |
4124 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4125 | return TRUE; | |
4126 | ||
4127 | if (! GPR_P (regno)) | |
4128 | return FALSE; | |
4129 | ||
4130 | return (((regno - GPR_FIRST) & 1) == 0); | |
4131 | } | |
4132 | ||
87b483a1 | 4133 | /* Return true if operand is an odd GPR register. */ |
36a05131 BS |
4134 | |
4135 | int | |
f2206911 | 4136 | odd_gpr_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4137 | { |
4138 | int regno; | |
4139 | ||
4140 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4141 | return FALSE; | |
4142 | ||
4143 | if (GET_CODE (op) == SUBREG) | |
4144 | { | |
4145 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
4146 | return register_operand (op, mode); | |
4147 | ||
4148 | op = SUBREG_REG (op); | |
4149 | } | |
4150 | ||
4151 | if (GET_CODE (op) != REG) | |
4152 | return FALSE; | |
4153 | ||
4154 | regno = REGNO (op); | |
87b483a1 | 4155 | /* Assume that reload will give us an even register. */ |
36a05131 BS |
4156 | if (regno >= FIRST_PSEUDO_REGISTER) |
4157 | return FALSE; | |
4158 | ||
4159 | if (! GPR_P (regno)) | |
4160 | return FALSE; | |
4161 | ||
4162 | return (((regno - GPR_FIRST) & 1) != 0); | |
4163 | } | |
4164 | ||
87b483a1 | 4165 | /* Return true if operand is a quad aligned FPR register. */ |
36a05131 BS |
4166 | |
4167 | int | |
f2206911 | 4168 | quad_fpr_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4169 | { |
4170 | int regno; | |
4171 | ||
4172 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4173 | return FALSE; | |
4174 | ||
4175 | if (GET_CODE (op) == SUBREG) | |
4176 | { | |
4177 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
4178 | return register_operand (op, mode); | |
4179 | ||
4180 | op = SUBREG_REG (op); | |
4181 | } | |
4182 | ||
4183 | if (GET_CODE (op) != REG) | |
4184 | return FALSE; | |
4185 | ||
4186 | regno = REGNO (op); | |
4187 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4188 | return TRUE; | |
4189 | ||
4190 | if (! FPR_P (regno)) | |
4191 | return FALSE; | |
4192 | ||
4193 | return (((regno - FPR_FIRST) & 3) == 0); | |
4194 | } | |
4195 | ||
87b483a1 | 4196 | /* Return true if operand is an even FPR register. */ |
36a05131 BS |
4197 | |
4198 | int | |
f2206911 | 4199 | even_fpr_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4200 | { |
4201 | int regno; | |
4202 | ||
4203 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4204 | return FALSE; | |
4205 | ||
4206 | if (GET_CODE (op) == SUBREG) | |
4207 | { | |
4208 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
4209 | return register_operand (op, mode); | |
4210 | ||
4211 | op = SUBREG_REG (op); | |
4212 | } | |
4213 | ||
4214 | if (GET_CODE (op) != REG) | |
4215 | return FALSE; | |
4216 | ||
4217 | regno = REGNO (op); | |
4218 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4219 | return TRUE; | |
4220 | ||
4221 | if (! FPR_P (regno)) | |
4222 | return FALSE; | |
4223 | ||
4224 | return (((regno - FPR_FIRST) & 1) == 0); | |
4225 | } | |
4226 | ||
87b483a1 | 4227 | /* Return true if operand is an odd FPR register. */ |
36a05131 BS |
4228 | |
4229 | int | |
f2206911 | 4230 | odd_fpr_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4231 | { |
4232 | int regno; | |
4233 | ||
4234 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4235 | return FALSE; | |
4236 | ||
4237 | if (GET_CODE (op) == SUBREG) | |
4238 | { | |
4239 | if (GET_CODE (SUBREG_REG (op)) != REG) | |
4240 | return register_operand (op, mode); | |
4241 | ||
4242 | op = SUBREG_REG (op); | |
4243 | } | |
4244 | ||
4245 | if (GET_CODE (op) != REG) | |
4246 | return FALSE; | |
4247 | ||
4248 | regno = REGNO (op); | |
87b483a1 | 4249 | /* Assume that reload will give us an even register. */ |
36a05131 BS |
4250 | if (regno >= FIRST_PSEUDO_REGISTER) |
4251 | return FALSE; | |
4252 | ||
4253 | if (! FPR_P (regno)) | |
4254 | return FALSE; | |
4255 | ||
4256 | return (((regno - FPR_FIRST) & 1) != 0); | |
4257 | } | |
4258 | ||
4259 | /* Return true if operand is a 2 word memory address that can be loaded in one | |
4260 | instruction to load or store. We assume the stack and frame pointers are | |
4261 | suitably aligned, and variables in the small data area. FIXME -- at some we | |
4262 | should recognize other globals and statics. We can't assume that any old | |
4263 | pointer is aligned, given that arguments could be passed on an odd word on | |
4264 | the stack and the address taken and passed through to another function. */ | |
4265 | ||
4266 | int | |
f2206911 | 4267 | dbl_memory_one_insn_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4268 | { |
4269 | rtx addr; | |
4270 | rtx addr_reg; | |
4271 | ||
4272 | if (! TARGET_DWORD) | |
4273 | return FALSE; | |
4274 | ||
4275 | if (GET_CODE (op) != MEM) | |
4276 | return FALSE; | |
4277 | ||
4278 | if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD) | |
4279 | return FALSE; | |
4280 | ||
4281 | addr = XEXP (op, 0); | |
4282 | if (GET_CODE (addr) == REG) | |
4283 | addr_reg = addr; | |
4284 | ||
4285 | else if (GET_CODE (addr) == PLUS) | |
4286 | { | |
4287 | rtx addr0 = XEXP (addr, 0); | |
4288 | rtx addr1 = XEXP (addr, 1); | |
4289 | ||
4290 | if (GET_CODE (addr0) != REG) | |
4291 | return FALSE; | |
4292 | ||
34208acf | 4293 | if (got12_operand (addr1, VOIDmode)) |
36a05131 BS |
4294 | return TRUE; |
4295 | ||
4296 | if (GET_CODE (addr1) != CONST_INT) | |
4297 | return FALSE; | |
4298 | ||
4299 | if ((INTVAL (addr1) & 7) != 0) | |
4300 | return FALSE; | |
4301 | ||
4302 | addr_reg = addr0; | |
4303 | } | |
4304 | ||
4305 | else | |
4306 | return FALSE; | |
4307 | ||
4308 | if (addr_reg == frame_pointer_rtx || addr_reg == stack_pointer_rtx) | |
4309 | return TRUE; | |
4310 | ||
4311 | return FALSE; | |
4312 | } | |
4313 | ||
4314 | /* Return true if operand is a 2 word memory address that needs to | |
4315 | use two instructions to load or store. */ | |
4316 | ||
4317 | int | |
f2206911 | 4318 | dbl_memory_two_insn_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4319 | { |
4320 | if (GET_CODE (op) != MEM) | |
4321 | return FALSE; | |
4322 | ||
4323 | if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD) | |
4324 | return FALSE; | |
4325 | ||
4326 | if (! TARGET_DWORD) | |
4327 | return TRUE; | |
4328 | ||
4329 | return ! dbl_memory_one_insn_operand (op, mode); | |
4330 | } | |
4331 | ||
4332 | /* Return true if operand is something that can be an output for a move | |
4333 | operation. */ | |
4334 | ||
4335 | int | |
f2206911 | 4336 | move_destination_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4337 | { |
4338 | rtx subreg; | |
4339 | enum rtx_code code; | |
4340 | ||
4341 | switch (GET_CODE (op)) | |
4342 | { | |
4343 | default: | |
4344 | break; | |
4345 | ||
4346 | case SUBREG: | |
4347 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4348 | return FALSE; | |
4349 | ||
4350 | subreg = SUBREG_REG (op); | |
4351 | code = GET_CODE (subreg); | |
4352 | if (code == MEM) | |
4353 | return frv_legitimate_address_p (mode, XEXP (subreg, 0), | |
34208acf | 4354 | reload_completed, FALSE, FALSE); |
36a05131 BS |
4355 | |
4356 | return (code == REG); | |
4357 | ||
4358 | case REG: | |
4359 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4360 | return FALSE; | |
4361 | ||
4362 | return TRUE; | |
4363 | ||
4364 | case MEM: | |
36a05131 BS |
4365 | return frv_legitimate_memory_operand (op, mode, FALSE); |
4366 | } | |
4367 | ||
4368 | return FALSE; | |
4369 | } | |
4370 | ||
34208acf AO |
4371 | /* Look for a SYMBOL_REF of a function in an rtx. We always want to |
4372 | process these separately from any offsets, such that we add any | |
4373 | offsets to the function descriptor (the actual pointer), not to the | |
4374 | function address. */ | |
4375 | ||
4376 | static bool | |
4377 | frv_function_symbol_referenced_p (rtx x) | |
4378 | { | |
4379 | const char *format; | |
4380 | int length; | |
4381 | int j; | |
4382 | ||
4383 | if (GET_CODE (x) == SYMBOL_REF) | |
4384 | return SYMBOL_REF_FUNCTION_P (x); | |
4385 | ||
4386 | length = GET_RTX_LENGTH (GET_CODE (x)); | |
4387 | format = GET_RTX_FORMAT (GET_CODE (x)); | |
4388 | ||
4389 | for (j = 0; j < length; ++j) | |
4390 | { | |
4391 | switch (format[j]) | |
4392 | { | |
4393 | case 'e': | |
4394 | if (frv_function_symbol_referenced_p (XEXP (x, j))) | |
4395 | return TRUE; | |
4396 | break; | |
4397 | ||
4398 | case 'V': | |
4399 | case 'E': | |
4400 | if (XVEC (x, j) != 0) | |
4401 | { | |
4402 | int k; | |
4403 | for (k = 0; k < XVECLEN (x, j); ++k) | |
4404 | if (frv_function_symbol_referenced_p (XVECEXP (x, j, k))) | |
4405 | return TRUE; | |
4406 | } | |
4407 | break; | |
4408 | ||
4409 | default: | |
4410 | /* Nothing to do. */ | |
4411 | break; | |
4412 | } | |
4413 | } | |
4414 | ||
4415 | return FALSE; | |
4416 | } | |
4417 | ||
36a05131 BS |
4418 | /* Return true if operand is something that can be an input for a move |
4419 | operation. */ | |
4420 | ||
4421 | int | |
f2206911 | 4422 | move_source_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4423 | { |
4424 | rtx subreg; | |
4425 | enum rtx_code code; | |
4426 | ||
4427 | switch (GET_CODE (op)) | |
4428 | { | |
4429 | default: | |
4430 | break; | |
4431 | ||
4432 | case CONST_INT: | |
4433 | case CONST_DOUBLE: | |
36a05131 BS |
4434 | return immediate_operand (op, mode); |
4435 | ||
4436 | case SUBREG: | |
4437 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4438 | return FALSE; | |
4439 | ||
4440 | subreg = SUBREG_REG (op); | |
4441 | code = GET_CODE (subreg); | |
4442 | if (code == MEM) | |
4443 | return frv_legitimate_address_p (mode, XEXP (subreg, 0), | |
34208acf | 4444 | reload_completed, FALSE, FALSE); |
36a05131 BS |
4445 | |
4446 | return (code == REG); | |
4447 | ||
4448 | case REG: | |
4449 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4450 | return FALSE; | |
4451 | ||
4452 | return TRUE; | |
4453 | ||
4454 | case MEM: | |
36a05131 BS |
4455 | return frv_legitimate_memory_operand (op, mode, FALSE); |
4456 | } | |
4457 | ||
4458 | return FALSE; | |
4459 | } | |
4460 | ||
4461 | /* Return true if operand is something that can be an output for a conditional | |
4462 | move operation. */ | |
4463 | ||
4464 | int | |
f2206911 | 4465 | condexec_dest_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4466 | { |
4467 | rtx subreg; | |
4468 | enum rtx_code code; | |
4469 | ||
4470 | switch (GET_CODE (op)) | |
4471 | { | |
4472 | default: | |
4473 | break; | |
4474 | ||
4475 | case SUBREG: | |
4476 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4477 | return FALSE; | |
4478 | ||
4479 | subreg = SUBREG_REG (op); | |
4480 | code = GET_CODE (subreg); | |
4481 | if (code == MEM) | |
4482 | return frv_legitimate_address_p (mode, XEXP (subreg, 0), | |
34208acf | 4483 | reload_completed, TRUE, FALSE); |
36a05131 BS |
4484 | |
4485 | return (code == REG); | |
4486 | ||
4487 | case REG: | |
4488 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4489 | return FALSE; | |
4490 | ||
4491 | return TRUE; | |
4492 | ||
4493 | case MEM: | |
36a05131 BS |
4494 | return frv_legitimate_memory_operand (op, mode, TRUE); |
4495 | } | |
4496 | ||
4497 | return FALSE; | |
4498 | } | |
4499 | ||
4500 | /* Return true if operand is something that can be an input for a conditional | |
4501 | move operation. */ | |
4502 | ||
4503 | int | |
f2206911 | 4504 | condexec_source_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4505 | { |
4506 | rtx subreg; | |
4507 | enum rtx_code code; | |
4508 | ||
4509 | switch (GET_CODE (op)) | |
4510 | { | |
4511 | default: | |
4512 | break; | |
4513 | ||
4514 | case CONST_INT: | |
4515 | case CONST_DOUBLE: | |
4516 | return ZERO_P (op); | |
4517 | ||
4518 | case SUBREG: | |
4519 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4520 | return FALSE; | |
4521 | ||
4522 | subreg = SUBREG_REG (op); | |
4523 | code = GET_CODE (subreg); | |
4524 | if (code == MEM) | |
4525 | return frv_legitimate_address_p (mode, XEXP (subreg, 0), | |
34208acf | 4526 | reload_completed, TRUE, FALSE); |
36a05131 BS |
4527 | |
4528 | return (code == REG); | |
4529 | ||
4530 | case REG: | |
4531 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4532 | return FALSE; | |
4533 | ||
4534 | return TRUE; | |
4535 | ||
4536 | case MEM: | |
36a05131 BS |
4537 | return frv_legitimate_memory_operand (op, mode, TRUE); |
4538 | } | |
4539 | ||
4540 | return FALSE; | |
4541 | } | |
4542 | ||
4543 | /* Return true if operand is a register of any flavor or a 0 of the | |
4544 | appropriate type. */ | |
4545 | ||
4546 | int | |
f2206911 | 4547 | reg_or_0_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4548 | { |
4549 | switch (GET_CODE (op)) | |
4550 | { | |
4551 | default: | |
4552 | break; | |
4553 | ||
4554 | case REG: | |
4555 | case SUBREG: | |
4556 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4557 | return FALSE; | |
4558 | ||
4559 | return register_operand (op, mode); | |
4560 | ||
4561 | case CONST_INT: | |
4562 | case CONST_DOUBLE: | |
4563 | return ZERO_P (op); | |
4564 | } | |
4565 | ||
4566 | return FALSE; | |
4567 | } | |
4568 | ||
87b483a1 | 4569 | /* Return true if operand is the link register. */ |
36a05131 BS |
4570 | |
4571 | int | |
f2206911 | 4572 | lr_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4573 | { |
4574 | if (GET_CODE (op) != REG) | |
4575 | return FALSE; | |
4576 | ||
4577 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4578 | return FALSE; | |
4579 | ||
4580 | if (REGNO (op) != LR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER) | |
4581 | return FALSE; | |
4582 | ||
4583 | return TRUE; | |
4584 | } | |
4585 | ||
34208acf AO |
4586 | /* Return true if operand is the uClinux PIC register. */ |
4587 | ||
4588 | int | |
4589 | fdpic_operand (rtx op, enum machine_mode mode) | |
4590 | { | |
4591 | if (!TARGET_FDPIC) | |
4592 | return FALSE; | |
4593 | ||
4594 | if (GET_CODE (op) != REG) | |
4595 | return FALSE; | |
4596 | ||
4597 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4598 | return FALSE; | |
4599 | ||
4600 | if (REGNO (op) != FDPIC_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER) | |
4601 | return FALSE; | |
4602 | ||
4603 | return TRUE; | |
4604 | } | |
4605 | ||
4606 | int | |
4607 | got12_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
4608 | { | |
4609 | struct frv_unspec unspec; | |
4610 | ||
4611 | if (frv_const_unspec_p (op, &unspec)) | |
4612 | switch (unspec.reloc) | |
4613 | { | |
4614 | case R_FRV_GOT12: | |
4615 | case R_FRV_GOTOFF12: | |
4616 | case R_FRV_FUNCDESC_GOT12: | |
4617 | case R_FRV_FUNCDESC_GOTOFF12: | |
4618 | case R_FRV_GPREL12: | |
4619 | return true; | |
4620 | } | |
4621 | return false; | |
4622 | } | |
4623 | ||
4624 | /* Return true if OP is a valid const-unspec expression. */ | |
4625 | ||
4626 | int | |
4627 | const_unspec_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
4628 | { | |
4629 | struct frv_unspec unspec; | |
4630 | ||
4631 | return frv_const_unspec_p (op, &unspec); | |
4632 | } | |
36a05131 BS |
4633 | /* Return true if operand is a gpr register or a valid memory operation. */ |
4634 | ||
4635 | int | |
f2206911 | 4636 | gpr_or_memory_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4637 | { |
4638 | return (integer_register_operand (op, mode) | |
4639 | || frv_legitimate_memory_operand (op, mode, FALSE)); | |
4640 | } | |
4641 | ||
4642 | /* Return true if operand is a fpr register or a valid memory operation. */ | |
4643 | ||
4644 | int | |
f2206911 | 4645 | fpr_or_memory_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4646 | { |
4647 | return (fpr_operand (op, mode) | |
4648 | || frv_legitimate_memory_operand (op, mode, FALSE)); | |
4649 | } | |
4650 | ||
87b483a1 | 4651 | /* Return true if operand is an icc register. */ |
36a05131 BS |
4652 | |
4653 | int | |
f2206911 | 4654 | icc_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4655 | { |
4656 | int regno; | |
4657 | ||
4658 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4659 | return FALSE; | |
4660 | ||
4661 | if (GET_CODE (op) != REG) | |
4662 | return FALSE; | |
4663 | ||
4664 | regno = REGNO (op); | |
4665 | return ICC_OR_PSEUDO_P (regno); | |
4666 | } | |
4667 | ||
87b483a1 | 4668 | /* Return true if operand is an fcc register. */ |
36a05131 BS |
4669 | |
4670 | int | |
f2206911 | 4671 | fcc_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4672 | { |
4673 | int regno; | |
4674 | ||
4675 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4676 | return FALSE; | |
4677 | ||
4678 | if (GET_CODE (op) != REG) | |
4679 | return FALSE; | |
4680 | ||
4681 | regno = REGNO (op); | |
4682 | return FCC_OR_PSEUDO_P (regno); | |
4683 | } | |
4684 | ||
87b483a1 | 4685 | /* Return true if operand is either an fcc or icc register. */ |
36a05131 BS |
4686 | |
4687 | int | |
f2206911 | 4688 | cc_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4689 | { |
4690 | int regno; | |
4691 | ||
4692 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4693 | return FALSE; | |
4694 | ||
4695 | if (GET_CODE (op) != REG) | |
4696 | return FALSE; | |
4697 | ||
4698 | regno = REGNO (op); | |
4699 | if (CC_OR_PSEUDO_P (regno)) | |
4700 | return TRUE; | |
4701 | ||
4702 | return FALSE; | |
4703 | } | |
4704 | ||
87b483a1 | 4705 | /* Return true if operand is an integer CCR register. */ |
36a05131 BS |
4706 | |
4707 | int | |
f2206911 | 4708 | icr_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4709 | { |
4710 | int regno; | |
4711 | ||
4712 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4713 | return FALSE; | |
4714 | ||
4715 | if (GET_CODE (op) != REG) | |
4716 | return FALSE; | |
4717 | ||
4718 | regno = REGNO (op); | |
4719 | return ICR_OR_PSEUDO_P (regno); | |
4720 | } | |
4721 | ||
87b483a1 | 4722 | /* Return true if operand is an fcc register. */ |
36a05131 BS |
4723 | |
4724 | int | |
f2206911 | 4725 | fcr_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4726 | { |
4727 | int regno; | |
4728 | ||
4729 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4730 | return FALSE; | |
4731 | ||
4732 | if (GET_CODE (op) != REG) | |
4733 | return FALSE; | |
4734 | ||
4735 | regno = REGNO (op); | |
4736 | return FCR_OR_PSEUDO_P (regno); | |
4737 | } | |
4738 | ||
87b483a1 | 4739 | /* Return true if operand is either an fcc or icc register. */ |
36a05131 BS |
4740 | |
4741 | int | |
f2206911 | 4742 | cr_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4743 | { |
4744 | int regno; | |
4745 | ||
4746 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4747 | return FALSE; | |
4748 | ||
4749 | if (GET_CODE (op) != REG) | |
4750 | return FALSE; | |
4751 | ||
4752 | regno = REGNO (op); | |
4753 | if (CR_OR_PSEUDO_P (regno)) | |
4754 | return TRUE; | |
4755 | ||
4756 | return FALSE; | |
4757 | } | |
4758 | ||
4759 | /* Return true if operand is a memory reference suitable for a call. */ | |
4760 | ||
4761 | int | |
f2206911 | 4762 | call_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
4763 | { |
4764 | if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT) | |
4765 | return FALSE; | |
4766 | ||
4767 | if (GET_CODE (op) == SYMBOL_REF) | |
c557edf4 | 4768 | return !TARGET_LONG_CALLS || SYMBOL_REF_LOCAL_P (op); |
36a05131 BS |
4769 | |
4770 | /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should | |
4771 | never occur anyway), but prevents reload from not handling the case | |
4772 | properly of a call through a pointer on a function that calls | |
4773 | vfork/setjmp, etc. due to the need to flush all of the registers to stack. */ | |
4774 | return gpr_or_int12_operand (op, mode); | |
4775 | } | |
4776 | ||
764678d1 AO |
4777 | /* Return true if operand is a memory reference suitable for a sibcall. */ |
4778 | ||
4779 | int | |
4780 | sibcall_operand (rtx op, enum machine_mode mode) | |
4781 | { | |
4782 | if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT) | |
4783 | return FALSE; | |
4784 | ||
4785 | /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should | |
4786 | never occur anyway), but prevents reload from not handling the case | |
4787 | properly of a call through a pointer on a function that calls | |
4788 | vfork/setjmp, etc. due to the need to flush all of the registers to stack. */ | |
4789 | return gpr_or_int12_operand (op, mode); | |
4790 | } | |
4791 | ||
5bdc5878 | 4792 | /* Return true if operator is a kind of relational operator. */ |
36a05131 BS |
4793 | |
4794 | int | |
f2206911 | 4795 | relational_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
4796 | { |
4797 | rtx op0; | |
4798 | rtx op1; | |
4799 | int regno; | |
4800 | ||
4801 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
4802 | return FALSE; | |
4803 | ||
4804 | switch (GET_CODE (op)) | |
4805 | { | |
4806 | default: | |
4807 | return FALSE; | |
4808 | ||
4809 | case EQ: | |
4810 | case NE: | |
4811 | case LE: | |
4812 | case LT: | |
4813 | case GE: | |
4814 | case GT: | |
4815 | case LEU: | |
4816 | case LTU: | |
4817 | case GEU: | |
4818 | case GTU: | |
4819 | break; | |
4820 | } | |
4821 | ||
4822 | op1 = XEXP (op, 1); | |
4823 | if (op1 != const0_rtx) | |
4824 | return FALSE; | |
4825 | ||
4826 | op0 = XEXP (op, 0); | |
4827 | if (GET_CODE (op0) != REG) | |
4828 | return FALSE; | |
4829 | ||
4830 | regno = REGNO (op0); | |
4831 | switch (GET_MODE (op0)) | |
4832 | { | |
4833 | default: | |
4834 | break; | |
4835 | ||
4836 | case CCmode: | |
4837 | case CC_UNSmode: | |
4838 | return ICC_OR_PSEUDO_P (regno); | |
4839 | ||
4840 | case CC_FPmode: | |
4841 | return FCC_OR_PSEUDO_P (regno); | |
4842 | ||
4843 | case CC_CCRmode: | |
4844 | return CR_OR_PSEUDO_P (regno); | |
4845 | } | |
4846 | ||
4847 | return FALSE; | |
4848 | } | |
4849 | ||
87b483a1 | 4850 | /* Return true if operator is a signed integer relational operator. */ |
36a05131 BS |
4851 | |
4852 | int | |
f2206911 | 4853 | signed_relational_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
4854 | { |
4855 | rtx op0; | |
4856 | rtx op1; | |
4857 | int regno; | |
4858 | ||
4859 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
4860 | return FALSE; | |
4861 | ||
4862 | switch (GET_CODE (op)) | |
4863 | { | |
4864 | default: | |
4865 | return FALSE; | |
4866 | ||
4867 | case EQ: | |
4868 | case NE: | |
4869 | case LE: | |
4870 | case LT: | |
4871 | case GE: | |
4872 | case GT: | |
4873 | break; | |
4874 | } | |
4875 | ||
4876 | op1 = XEXP (op, 1); | |
4877 | if (op1 != const0_rtx) | |
4878 | return FALSE; | |
4879 | ||
4880 | op0 = XEXP (op, 0); | |
4881 | if (GET_CODE (op0) != REG) | |
4882 | return FALSE; | |
4883 | ||
4884 | regno = REGNO (op0); | |
4885 | if (GET_MODE (op0) == CCmode && ICC_OR_PSEUDO_P (regno)) | |
4886 | return TRUE; | |
4887 | ||
4888 | if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno)) | |
4889 | return TRUE; | |
4890 | ||
4891 | return FALSE; | |
4892 | } | |
4893 | ||
87b483a1 | 4894 | /* Return true if operator is a signed integer relational operator. */ |
36a05131 BS |
4895 | |
4896 | int | |
f2206911 | 4897 | unsigned_relational_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
4898 | { |
4899 | rtx op0; | |
4900 | rtx op1; | |
4901 | int regno; | |
4902 | ||
4903 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
4904 | return FALSE; | |
4905 | ||
4906 | switch (GET_CODE (op)) | |
4907 | { | |
4908 | default: | |
4909 | return FALSE; | |
4910 | ||
4911 | case LEU: | |
4912 | case LTU: | |
4913 | case GEU: | |
4914 | case GTU: | |
4915 | break; | |
4916 | } | |
4917 | ||
4918 | op1 = XEXP (op, 1); | |
4919 | if (op1 != const0_rtx) | |
4920 | return FALSE; | |
4921 | ||
4922 | op0 = XEXP (op, 0); | |
4923 | if (GET_CODE (op0) != REG) | |
4924 | return FALSE; | |
4925 | ||
4926 | regno = REGNO (op0); | |
4927 | if (GET_MODE (op0) == CC_UNSmode && ICC_OR_PSEUDO_P (regno)) | |
4928 | return TRUE; | |
4929 | ||
4930 | if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno)) | |
4931 | return TRUE; | |
4932 | ||
4933 | return FALSE; | |
4934 | } | |
4935 | ||
87b483a1 | 4936 | /* Return true if operator is a floating point relational operator. */ |
36a05131 BS |
4937 | |
4938 | int | |
f2206911 | 4939 | float_relational_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
4940 | { |
4941 | rtx op0; | |
4942 | rtx op1; | |
4943 | int regno; | |
4944 | ||
4945 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
4946 | return FALSE; | |
4947 | ||
4948 | switch (GET_CODE (op)) | |
4949 | { | |
4950 | default: | |
4951 | return FALSE; | |
4952 | ||
4953 | case EQ: case NE: | |
4954 | case LE: case LT: | |
4955 | case GE: case GT: | |
4956 | #if 0 | |
4957 | case UEQ: case UNE: | |
4958 | case ULE: case ULT: | |
4959 | case UGE: case UGT: | |
4960 | case ORDERED: | |
4961 | case UNORDERED: | |
4962 | #endif | |
4963 | break; | |
4964 | } | |
4965 | ||
4966 | op1 = XEXP (op, 1); | |
4967 | if (op1 != const0_rtx) | |
4968 | return FALSE; | |
4969 | ||
4970 | op0 = XEXP (op, 0); | |
4971 | if (GET_CODE (op0) != REG) | |
4972 | return FALSE; | |
4973 | ||
4974 | regno = REGNO (op0); | |
4975 | if (GET_MODE (op0) == CC_FPmode && FCC_OR_PSEUDO_P (regno)) | |
4976 | return TRUE; | |
4977 | ||
4978 | if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno)) | |
4979 | return TRUE; | |
4980 | ||
4981 | return FALSE; | |
4982 | } | |
4983 | ||
4984 | /* Return true if operator is EQ/NE of a conditional execution register. */ | |
4985 | ||
4986 | int | |
f2206911 | 4987 | ccr_eqne_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
4988 | { |
4989 | enum machine_mode op_mode = GET_MODE (op); | |
4990 | rtx op0; | |
4991 | rtx op1; | |
4992 | int regno; | |
4993 | ||
4994 | if (mode != VOIDmode && op_mode != mode) | |
4995 | return FALSE; | |
4996 | ||
4997 | switch (GET_CODE (op)) | |
4998 | { | |
4999 | default: | |
5000 | return FALSE; | |
5001 | ||
5002 | case EQ: | |
5003 | case NE: | |
5004 | break; | |
5005 | } | |
5006 | ||
5007 | op1 = XEXP (op, 1); | |
5008 | if (op1 != const0_rtx) | |
5009 | return FALSE; | |
5010 | ||
5011 | op0 = XEXP (op, 0); | |
5012 | if (GET_CODE (op0) != REG) | |
5013 | return FALSE; | |
5014 | ||
5015 | regno = REGNO (op0); | |
5016 | if (op_mode == CC_CCRmode && CR_OR_PSEUDO_P (regno)) | |
5017 | return TRUE; | |
5018 | ||
5019 | return FALSE; | |
5020 | } | |
5021 | ||
5022 | /* Return true if operator is a minimum or maximum operator (both signed and | |
5023 | unsigned). */ | |
5024 | ||
5025 | int | |
f2206911 | 5026 | minmax_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
5027 | { |
5028 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
5029 | return FALSE; | |
5030 | ||
5031 | switch (GET_CODE (op)) | |
5032 | { | |
5033 | default: | |
5034 | return FALSE; | |
5035 | ||
5036 | case SMIN: | |
5037 | case SMAX: | |
5038 | case UMIN: | |
5039 | case UMAX: | |
5040 | break; | |
5041 | } | |
5042 | ||
5043 | if (! integer_register_operand (XEXP (op, 0), mode)) | |
5044 | return FALSE; | |
5045 | ||
5046 | if (! gpr_or_int10_operand (XEXP (op, 1), mode)) | |
5047 | return FALSE; | |
5048 | ||
5049 | return TRUE; | |
5050 | } | |
5051 | ||
5052 | /* Return true if operator is an integer binary operator that can executed | |
5053 | conditionally and takes 1 cycle. */ | |
5054 | ||
5055 | int | |
f2206911 | 5056 | condexec_si_binary_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
5057 | { |
5058 | enum machine_mode op_mode = GET_MODE (op); | |
5059 | ||
5060 | if (mode != VOIDmode && op_mode != mode) | |
5061 | return FALSE; | |
5062 | ||
5063 | switch (GET_CODE (op)) | |
5064 | { | |
5065 | default: | |
5066 | return FALSE; | |
5067 | ||
5068 | case PLUS: | |
5069 | case MINUS: | |
5070 | case AND: | |
5071 | case IOR: | |
5072 | case XOR: | |
5073 | case ASHIFT: | |
5074 | case ASHIFTRT: | |
5075 | case LSHIFTRT: | |
5076 | return TRUE; | |
5077 | } | |
5078 | } | |
5079 | ||
5080 | /* Return true if operator is an integer binary operator that can be | |
5081 | executed conditionally by a media instruction. */ | |
5082 | ||
5083 | int | |
f2206911 | 5084 | condexec_si_media_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
5085 | { |
5086 | enum machine_mode op_mode = GET_MODE (op); | |
5087 | ||
5088 | if (mode != VOIDmode && op_mode != mode) | |
5089 | return FALSE; | |
5090 | ||
5091 | switch (GET_CODE (op)) | |
5092 | { | |
5093 | default: | |
5094 | return FALSE; | |
5095 | ||
5096 | case AND: | |
5097 | case IOR: | |
5098 | case XOR: | |
5099 | return TRUE; | |
5100 | } | |
5101 | } | |
5102 | ||
5103 | /* Return true if operator is an integer division operator that can executed | |
5104 | conditionally. */ | |
5105 | ||
5106 | int | |
f2206911 | 5107 | condexec_si_divide_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
5108 | { |
5109 | enum machine_mode op_mode = GET_MODE (op); | |
5110 | ||
5111 | if (mode != VOIDmode && op_mode != mode) | |
5112 | return FALSE; | |
5113 | ||
5114 | switch (GET_CODE (op)) | |
5115 | { | |
5116 | default: | |
5117 | return FALSE; | |
5118 | ||
5119 | case DIV: | |
5120 | case UDIV: | |
5121 | return TRUE; | |
5122 | } | |
5123 | } | |
5124 | ||
5125 | /* Return true if operator is an integer unary operator that can executed | |
5126 | conditionally. */ | |
5127 | ||
5128 | int | |
f2206911 | 5129 | condexec_si_unary_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
5130 | { |
5131 | enum machine_mode op_mode = GET_MODE (op); | |
5132 | ||
5133 | if (mode != VOIDmode && op_mode != mode) | |
5134 | return FALSE; | |
5135 | ||
5136 | switch (GET_CODE (op)) | |
5137 | { | |
5138 | default: | |
5139 | return FALSE; | |
5140 | ||
5141 | case NEG: | |
5142 | case NOT: | |
5143 | return TRUE; | |
5144 | } | |
5145 | } | |
5146 | ||
5147 | /* Return true if operator is a conversion-type expression that can be | |
5148 | evaluated conditionally by floating-point instructions. */ | |
5149 | ||
5150 | int | |
f2206911 | 5151 | condexec_sf_conv_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
5152 | { |
5153 | enum machine_mode op_mode = GET_MODE (op); | |
5154 | ||
5155 | if (mode != VOIDmode && op_mode != mode) | |
5156 | return FALSE; | |
5157 | ||
5158 | switch (GET_CODE (op)) | |
5159 | { | |
5160 | default: | |
5161 | return FALSE; | |
5162 | ||
5163 | case NEG: | |
5164 | case ABS: | |
5165 | return TRUE; | |
5166 | } | |
5167 | } | |
5168 | ||
5169 | /* Return true if operator is an addition or subtraction expression. | |
5170 | Such expressions can be evaluated conditionally by floating-point | |
5171 | instructions. */ | |
5172 | ||
5173 | int | |
f2206911 | 5174 | condexec_sf_add_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
5175 | { |
5176 | enum machine_mode op_mode = GET_MODE (op); | |
5177 | ||
5178 | if (mode != VOIDmode && op_mode != mode) | |
5179 | return FALSE; | |
5180 | ||
5181 | switch (GET_CODE (op)) | |
5182 | { | |
5183 | default: | |
5184 | return FALSE; | |
5185 | ||
5186 | case PLUS: | |
5187 | case MINUS: | |
5188 | return TRUE; | |
5189 | } | |
5190 | } | |
5191 | ||
5192 | /* Return true if the memory operand is one that can be conditionally | |
5193 | executed. */ | |
5194 | ||
5195 | int | |
f2206911 | 5196 | condexec_memory_operand (rtx op, enum machine_mode mode) |
36a05131 BS |
5197 | { |
5198 | enum machine_mode op_mode = GET_MODE (op); | |
5199 | rtx addr; | |
5200 | ||
5201 | if (mode != VOIDmode && op_mode != mode) | |
5202 | return FALSE; | |
5203 | ||
5204 | switch (op_mode) | |
5205 | { | |
5206 | default: | |
5207 | return FALSE; | |
5208 | ||
5209 | case QImode: | |
5210 | case HImode: | |
5211 | case SImode: | |
5212 | case SFmode: | |
5213 | break; | |
5214 | } | |
5215 | ||
5216 | if (GET_CODE (op) != MEM) | |
5217 | return FALSE; | |
5218 | ||
5219 | addr = XEXP (op, 0); | |
34208acf | 5220 | return frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE); |
36a05131 BS |
5221 | } |
5222 | ||
5223 | /* Return true if operator is an integer binary operator that can be combined | |
5224 | with a setcc operation. Do not allow the arithmetic operations that could | |
5225 | potentially overflow since the FR-V sets the condition code based on the | |
5226 | "true" value of the result, not the result after truncating to a 32-bit | |
5227 | register. */ | |
5228 | ||
5229 | int | |
f2206911 | 5230 | intop_compare_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
5231 | { |
5232 | enum machine_mode op_mode = GET_MODE (op); | |
5233 | ||
5234 | if (mode != VOIDmode && op_mode != mode) | |
5235 | return FALSE; | |
5236 | ||
5237 | switch (GET_CODE (op)) | |
5238 | { | |
5239 | default: | |
5240 | return FALSE; | |
5241 | ||
5242 | case AND: | |
5243 | case IOR: | |
5244 | case XOR: | |
5245 | case ASHIFTRT: | |
5246 | case LSHIFTRT: | |
5247 | break; | |
5248 | } | |
5249 | ||
5250 | if (! integer_register_operand (XEXP (op, 0), SImode)) | |
5251 | return FALSE; | |
5252 | ||
5253 | if (! gpr_or_int10_operand (XEXP (op, 1), SImode)) | |
5254 | return FALSE; | |
5255 | ||
5256 | return TRUE; | |
5257 | } | |
5258 | ||
5259 | /* Return true if operator is an integer binary operator that can be combined | |
5260 | with a setcc operation inside of a conditional execution. */ | |
5261 | ||
5262 | int | |
f2206911 | 5263 | condexec_intop_cmp_operator (rtx op, enum machine_mode mode) |
36a05131 BS |
5264 | { |
5265 | enum machine_mode op_mode = GET_MODE (op); | |
5266 | ||
5267 | if (mode != VOIDmode && op_mode != mode) | |
5268 | return FALSE; | |
5269 | ||
5270 | switch (GET_CODE (op)) | |
5271 | { | |
5272 | default: | |
5273 | return FALSE; | |
5274 | ||
5275 | case AND: | |
5276 | case IOR: | |
5277 | case XOR: | |
5278 | case ASHIFTRT: | |
5279 | case LSHIFTRT: | |
5280 | break; | |
5281 | } | |
5282 | ||
5283 | if (! integer_register_operand (XEXP (op, 0), SImode)) | |
5284 | return FALSE; | |
5285 | ||
5286 | if (! integer_register_operand (XEXP (op, 1), SImode)) | |
5287 | return FALSE; | |
5288 | ||
5289 | return TRUE; | |
5290 | } | |
5291 | ||
87b483a1 | 5292 | /* Return 1 if operand is a valid ACC register number. */ |
36a05131 BS |
5293 | |
5294 | int | |
f2206911 | 5295 | acc_operand (rtx op, enum machine_mode mode) |
36a05131 | 5296 | { |
c557edf4 RS |
5297 | return ((mode == VOIDmode || mode == GET_MODE (op)) |
5298 | && REG_P (op) && ACC_P (REGNO (op)) | |
2a88ebca | 5299 | && ((REGNO (op) - ACC_FIRST) & ~ACC_MASK) == 0); |
36a05131 BS |
5300 | } |
5301 | ||
87b483a1 | 5302 | /* Return 1 if operand is a valid even ACC register number. */ |
36a05131 BS |
5303 | |
5304 | int | |
f2206911 | 5305 | even_acc_operand (rtx op, enum machine_mode mode) |
36a05131 | 5306 | { |
c557edf4 | 5307 | return acc_operand (op, mode) && ((REGNO (op) - ACC_FIRST) & 1) == 0; |
36a05131 BS |
5308 | } |
5309 | ||
87b483a1 | 5310 | /* Return 1 if operand is zero or four. */ |
36a05131 BS |
5311 | |
5312 | int | |
f2206911 | 5313 | quad_acc_operand (rtx op, enum machine_mode mode) |
36a05131 | 5314 | { |
c557edf4 | 5315 | return acc_operand (op, mode) && ((REGNO (op) - ACC_FIRST) & 3) == 0; |
36a05131 BS |
5316 | } |
5317 | ||
87b483a1 | 5318 | /* Return 1 if operand is a valid ACCG register number. */ |
36a05131 BS |
5319 | |
5320 | int | |
f2206911 | 5321 | accg_operand (rtx op, enum machine_mode mode) |
36a05131 | 5322 | { |
c557edf4 RS |
5323 | return ((mode == VOIDmode || mode == GET_MODE (op)) |
5324 | && REG_P (op) && ACCG_P (REGNO (op)) | |
2a88ebca | 5325 | && ((REGNO (op) - ACCG_FIRST) & ~ACC_MASK) == 0); |
36a05131 BS |
5326 | } |
5327 | ||
5328 | \f | |
5329 | /* Return true if the bare return instruction can be used outside of the | |
5330 | epilog code. For frv, we only do it if there was no stack allocation. */ | |
5331 | ||
5332 | int | |
f2206911 | 5333 | direct_return_p (void) |
36a05131 BS |
5334 | { |
5335 | frv_stack_t *info; | |
5336 | ||
5337 | if (!reload_completed) | |
5338 | return FALSE; | |
5339 | ||
5340 | info = frv_stack_info (); | |
5341 | return (info->total_size == 0); | |
5342 | } | |
5343 | ||
5344 | \f | |
5345 | /* Emit code to handle a MOVSI, adding in the small data register or pic | |
5346 | register if needed to load up addresses. Return TRUE if the appropriate | |
5347 | instructions are emitted. */ | |
5348 | ||
5349 | int | |
f2206911 | 5350 | frv_emit_movsi (rtx dest, rtx src) |
36a05131 BS |
5351 | { |
5352 | int base_regno = -1; | |
34208acf AO |
5353 | int unspec = 0; |
5354 | rtx sym = src; | |
5355 | struct frv_unspec old_unspec; | |
36a05131 BS |
5356 | |
5357 | if (!reload_in_progress | |
5358 | && !reload_completed | |
5359 | && !register_operand (dest, SImode) | |
5360 | && (!reg_or_0_operand (src, SImode) | |
5361 | /* Virtual registers will almost always be replaced by an | |
5362 | add instruction, so expose this to CSE by copying to | |
87b483a1 | 5363 | an intermediate register. */ |
36a05131 BS |
5364 | || (GET_CODE (src) == REG |
5365 | && IN_RANGE_P (REGNO (src), | |
5366 | FIRST_VIRTUAL_REGISTER, | |
5367 | LAST_VIRTUAL_REGISTER)))) | |
5368 | { | |
5369 | emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src))); | |
5370 | return TRUE; | |
5371 | } | |
5372 | ||
5373 | /* Explicitly add in the PIC or small data register if needed. */ | |
5374 | switch (GET_CODE (src)) | |
5375 | { | |
5376 | default: | |
5377 | break; | |
5378 | ||
5379 | case LABEL_REF: | |
34208acf AO |
5380 | handle_label: |
5381 | if (TARGET_FDPIC) | |
5382 | { | |
5383 | /* Using GPREL12, we use a single GOT entry for all symbols | |
5384 | in read-only sections, but trade sequences such as: | |
5385 | ||
5386 | sethi #gothi(label), gr# | |
5387 | setlo #gotlo(label), gr# | |
5388 | ld @(gr15,gr#), gr# | |
5389 | ||
5390 | for | |
5391 | ||
5392 | ld @(gr15,#got12(_gp)), gr# | |
5393 | sethi #gprelhi(label), gr## | |
5394 | setlo #gprello(label), gr## | |
5395 | add gr#, gr##, gr## | |
5396 | ||
5397 | We may often be able to share gr# for multiple | |
5398 | computations of GPREL addresses, and we may often fold | |
5399 | the final add into the pair of registers of a load or | |
5400 | store instruction, so it's often profitable. Even when | |
5401 | optimizing for size, we're trading a GOT entry for an | |
5402 | additional instruction, which trades GOT space | |
5403 | (read-write) for code size (read-only, shareable), as | |
5404 | long as the symbol is not used in more than two different | |
5405 | locations. | |
5406 | ||
5407 | With -fpie/-fpic, we'd be trading a single load for a | |
5408 | sequence of 4 instructions, because the offset of the | |
4ee31f1e | 5409 | label can't be assumed to be addressable with 12 bits, so |
34208acf AO |
5410 | we don't do this. */ |
5411 | if (TARGET_GPREL_RO) | |
5412 | unspec = R_FRV_GPREL12; | |
5413 | else | |
5414 | unspec = R_FRV_GOT12; | |
5415 | } | |
5416 | else if (flag_pic) | |
36a05131 BS |
5417 | base_regno = PIC_REGNO; |
5418 | ||
5419 | break; | |
5420 | ||
5421 | case CONST: | |
34208acf AO |
5422 | if (frv_const_unspec_p (src, &old_unspec)) |
5423 | break; | |
36a05131 | 5424 | |
34208acf AO |
5425 | if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0))) |
5426 | { | |
5427 | handle_whatever: | |
5428 | src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0)); | |
5429 | emit_move_insn (dest, src); | |
5430 | return TRUE; | |
5431 | } | |
5432 | else | |
5433 | { | |
5434 | sym = XEXP (sym, 0); | |
5435 | if (GET_CODE (sym) == PLUS | |
5436 | && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF | |
5437 | && GET_CODE (XEXP (sym, 1)) == CONST_INT) | |
5438 | sym = XEXP (sym, 0); | |
5439 | if (GET_CODE (sym) == SYMBOL_REF) | |
5440 | goto handle_sym; | |
5441 | else if (GET_CODE (sym) == LABEL_REF) | |
5442 | goto handle_label; | |
5443 | else | |
5444 | goto handle_whatever; | |
5445 | } | |
36a05131 BS |
5446 | break; |
5447 | ||
5448 | case SYMBOL_REF: | |
34208acf AO |
5449 | handle_sym: |
5450 | if (TARGET_FDPIC) | |
5451 | { | |
5452 | if (SYMBOL_REF_FUNCTION_P (sym)) | |
5453 | { | |
5454 | if (frv_local_funcdesc_p (sym)) | |
5455 | unspec = R_FRV_FUNCDESC_GOTOFF12; | |
5456 | else | |
5457 | unspec = R_FRV_FUNCDESC_GOT12; | |
5458 | } | |
5459 | else | |
5460 | { | |
5461 | if (CONSTANT_POOL_ADDRESS_P (sym)) | |
5462 | switch (GET_CODE (get_pool_constant (sym))) | |
5463 | { | |
5464 | case CONST: | |
5465 | case SYMBOL_REF: | |
5466 | case LABEL_REF: | |
5467 | if (flag_pic) | |
5468 | { | |
5469 | unspec = R_FRV_GOTOFF12; | |
5470 | break; | |
5471 | } | |
5472 | /* Fall through. */ | |
5473 | default: | |
5474 | if (TARGET_GPREL_RO) | |
5475 | unspec = R_FRV_GPREL12; | |
5476 | else | |
5477 | unspec = R_FRV_GOT12; | |
5478 | break; | |
5479 | } | |
5480 | else if (SYMBOL_REF_LOCAL_P (sym) | |
5481 | && !SYMBOL_REF_EXTERNAL_P (sym) | |
5482 | && SYMBOL_REF_DECL (sym) | |
5483 | && (!DECL_P (SYMBOL_REF_DECL (sym)) | |
5484 | || !DECL_COMMON (SYMBOL_REF_DECL (sym)))) | |
5485 | { | |
5486 | tree decl = SYMBOL_REF_DECL (sym); | |
5487 | tree init = TREE_CODE (decl) == VAR_DECL | |
5488 | ? DECL_INITIAL (decl) | |
5489 | : TREE_CODE (decl) == CONSTRUCTOR | |
5490 | ? decl : 0; | |
5491 | int reloc = 0; | |
5492 | bool named_section, readonly; | |
5493 | ||
5494 | if (init && init != error_mark_node) | |
5495 | reloc = compute_reloc_for_constant (init); | |
5496 | ||
5497 | named_section = TREE_CODE (decl) == VAR_DECL | |
5498 | && lookup_attribute ("section", DECL_ATTRIBUTES (decl)); | |
5499 | readonly = decl_readonly_section (decl, reloc); | |
5500 | ||
5501 | if (named_section) | |
5502 | unspec = R_FRV_GOT12; | |
5503 | else if (!readonly) | |
5504 | unspec = R_FRV_GOTOFF12; | |
5505 | else if (readonly && TARGET_GPREL_RO) | |
5506 | unspec = R_FRV_GPREL12; | |
5507 | else | |
5508 | unspec = R_FRV_GOT12; | |
5509 | } | |
5510 | else | |
5511 | unspec = R_FRV_GOT12; | |
5512 | } | |
5513 | } | |
5514 | ||
5515 | else if (SYMBOL_REF_SMALL_P (sym)) | |
36a05131 BS |
5516 | base_regno = SDA_BASE_REG; |
5517 | ||
5518 | else if (flag_pic) | |
5519 | base_regno = PIC_REGNO; | |
5520 | ||
5521 | break; | |
5522 | } | |
5523 | ||
5524 | if (base_regno >= 0) | |
5525 | { | |
34208acf AO |
5526 | if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym)) |
5527 | emit_insn (gen_symGOTOFF2reg (dest, src, | |
5528 | gen_rtx_REG (Pmode, base_regno), | |
5529 | GEN_INT (R_FRV_GPREL12))); | |
5530 | else | |
5531 | emit_insn (gen_symGOTOFF2reg_hilo (dest, src, | |
5532 | gen_rtx_REG (Pmode, base_regno), | |
5533 | GEN_INT (R_FRV_GPREL12))); | |
36a05131 BS |
5534 | if (base_regno == PIC_REGNO) |
5535 | cfun->uses_pic_offset_table = TRUE; | |
34208acf AO |
5536 | return TRUE; |
5537 | } | |
36a05131 | 5538 | |
34208acf AO |
5539 | if (unspec) |
5540 | { | |
5541 | rtx x; | |
5542 | ||
5543 | /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce | |
5544 | new uses of it once reload has begun. */ | |
5545 | if (reload_in_progress || reload_completed) | |
5546 | abort (); | |
5547 | ||
5548 | switch (unspec) | |
5549 | { | |
5550 | case R_FRV_GOTOFF12: | |
5551 | if (!frv_small_data_reloc_p (sym, unspec)) | |
5552 | x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG, | |
5553 | GEN_INT (unspec)); | |
5554 | else | |
5555 | x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); | |
5556 | break; | |
5557 | case R_FRV_GPREL12: | |
5558 | if (!frv_small_data_reloc_p (sym, unspec)) | |
5559 | x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG, | |
5560 | GEN_INT (unspec)); | |
5561 | else | |
5562 | x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); | |
5563 | break; | |
5564 | case R_FRV_FUNCDESC_GOTOFF12: | |
5565 | if (flag_pic != 1) | |
5566 | x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG, | |
5567 | GEN_INT (unspec)); | |
5568 | else | |
5569 | x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); | |
5570 | break; | |
5571 | default: | |
5572 | if (flag_pic != 1) | |
5573 | x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG, | |
5574 | GEN_INT (unspec)); | |
5575 | else | |
5576 | x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); | |
5577 | break; | |
5578 | } | |
5579 | emit_insn (x); | |
5580 | cfun->uses_pic_offset_table = TRUE; | |
36a05131 BS |
5581 | return TRUE; |
5582 | } | |
5583 | ||
34208acf | 5584 | |
36a05131 BS |
5585 | return FALSE; |
5586 | } | |
5587 | ||
5588 | \f | |
5589 | /* Return a string to output a single word move. */ | |
5590 | ||
5591 | const char * | |
f2206911 | 5592 | output_move_single (rtx operands[], rtx insn) |
36a05131 BS |
5593 | { |
5594 | rtx dest = operands[0]; | |
5595 | rtx src = operands[1]; | |
5596 | ||
5597 | if (GET_CODE (dest) == REG) | |
5598 | { | |
5599 | int dest_regno = REGNO (dest); | |
5600 | enum machine_mode mode = GET_MODE (dest); | |
5601 | ||
5602 | if (GPR_P (dest_regno)) | |
5603 | { | |
5604 | if (GET_CODE (src) == REG) | |
5605 | { | |
5606 | /* gpr <- some sort of register */ | |
5607 | int src_regno = REGNO (src); | |
5608 | ||
5609 | if (GPR_P (src_regno)) | |
5610 | return "mov %1, %0"; | |
5611 | ||
5612 | else if (FPR_P (src_regno)) | |
5613 | return "movfg %1, %0"; | |
5614 | ||
5615 | else if (SPR_P (src_regno)) | |
5616 | return "movsg %1, %0"; | |
5617 | } | |
5618 | ||
5619 | else if (GET_CODE (src) == MEM) | |
5620 | { | |
5621 | /* gpr <- memory */ | |
5622 | switch (mode) | |
5623 | { | |
5624 | default: | |
5625 | break; | |
5626 | ||
5627 | case QImode: | |
5628 | return "ldsb%I1%U1 %M1,%0"; | |
5629 | ||
5630 | case HImode: | |
5631 | return "ldsh%I1%U1 %M1,%0"; | |
5632 | ||
5633 | case SImode: | |
5634 | case SFmode: | |
5635 | return "ld%I1%U1 %M1, %0"; | |
5636 | } | |
5637 | } | |
5638 | ||
5639 | else if (GET_CODE (src) == CONST_INT | |
5640 | || GET_CODE (src) == CONST_DOUBLE) | |
5641 | { | |
5642 | /* gpr <- integer/floating constant */ | |
5643 | HOST_WIDE_INT value; | |
5644 | ||
5645 | if (GET_CODE (src) == CONST_INT) | |
5646 | value = INTVAL (src); | |
5647 | ||
5648 | else if (mode == SFmode) | |
5649 | { | |
5650 | REAL_VALUE_TYPE rv; | |
5651 | long l; | |
5652 | ||
5653 | REAL_VALUE_FROM_CONST_DOUBLE (rv, src); | |
5654 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
5655 | value = l; | |
5656 | } | |
5657 | ||
5658 | else | |
5659 | value = CONST_DOUBLE_LOW (src); | |
5660 | ||
5661 | if (IN_RANGE_P (value, -32768, 32767)) | |
5662 | return "setlos %1, %0"; | |
5663 | ||
5664 | return "#"; | |
5665 | } | |
5666 | ||
5667 | else if (GET_CODE (src) == SYMBOL_REF | |
5668 | || GET_CODE (src) == LABEL_REF | |
5669 | || GET_CODE (src) == CONST) | |
5670 | { | |
36a05131 BS |
5671 | return "#"; |
5672 | } | |
5673 | } | |
5674 | ||
5675 | else if (FPR_P (dest_regno)) | |
5676 | { | |
5677 | if (GET_CODE (src) == REG) | |
5678 | { | |
5679 | /* fpr <- some sort of register */ | |
5680 | int src_regno = REGNO (src); | |
5681 | ||
5682 | if (GPR_P (src_regno)) | |
5683 | return "movgf %1, %0"; | |
5684 | ||
5685 | else if (FPR_P (src_regno)) | |
5686 | { | |
5687 | if (TARGET_HARD_FLOAT) | |
5688 | return "fmovs %1, %0"; | |
5689 | else | |
5690 | return "mor %1, %1, %0"; | |
5691 | } | |
5692 | } | |
5693 | ||
5694 | else if (GET_CODE (src) == MEM) | |
5695 | { | |
5696 | /* fpr <- memory */ | |
5697 | switch (mode) | |
5698 | { | |
5699 | default: | |
5700 | break; | |
5701 | ||
5702 | case QImode: | |
5703 | return "ldbf%I1%U1 %M1,%0"; | |
5704 | ||
5705 | case HImode: | |
5706 | return "ldhf%I1%U1 %M1,%0"; | |
5707 | ||
5708 | case SImode: | |
5709 | case SFmode: | |
5710 | return "ldf%I1%U1 %M1, %0"; | |
5711 | } | |
5712 | } | |
5713 | ||
5714 | else if (ZERO_P (src)) | |
5715 | return "movgf %., %0"; | |
5716 | } | |
5717 | ||
5718 | else if (SPR_P (dest_regno)) | |
5719 | { | |
5720 | if (GET_CODE (src) == REG) | |
5721 | { | |
5722 | /* spr <- some sort of register */ | |
5723 | int src_regno = REGNO (src); | |
5724 | ||
5725 | if (GPR_P (src_regno)) | |
5726 | return "movgs %1, %0"; | |
5727 | } | |
c557edf4 RS |
5728 | else if (ZERO_P (src)) |
5729 | return "movgs %., %0"; | |
36a05131 BS |
5730 | } |
5731 | } | |
5732 | ||
5733 | else if (GET_CODE (dest) == MEM) | |
5734 | { | |
5735 | if (GET_CODE (src) == REG) | |
5736 | { | |
5737 | int src_regno = REGNO (src); | |
5738 | enum machine_mode mode = GET_MODE (dest); | |
5739 | ||
5740 | if (GPR_P (src_regno)) | |
5741 | { | |
5742 | switch (mode) | |
5743 | { | |
5744 | default: | |
5745 | break; | |
5746 | ||
5747 | case QImode: | |
5748 | return "stb%I0%U0 %1, %M0"; | |
5749 | ||
5750 | case HImode: | |
5751 | return "sth%I0%U0 %1, %M0"; | |
5752 | ||
5753 | case SImode: | |
5754 | case SFmode: | |
5755 | return "st%I0%U0 %1, %M0"; | |
5756 | } | |
5757 | } | |
5758 | ||
5759 | else if (FPR_P (src_regno)) | |
5760 | { | |
5761 | switch (mode) | |
5762 | { | |
5763 | default: | |
5764 | break; | |
5765 | ||
5766 | case QImode: | |
5767 | return "stbf%I0%U0 %1, %M0"; | |
5768 | ||
5769 | case HImode: | |
5770 | return "sthf%I0%U0 %1, %M0"; | |
5771 | ||
5772 | case SImode: | |
5773 | case SFmode: | |
5774 | return "stf%I0%U0 %1, %M0"; | |
5775 | } | |
5776 | } | |
5777 | } | |
5778 | ||
5779 | else if (ZERO_P (src)) | |
5780 | { | |
5781 | switch (GET_MODE (dest)) | |
5782 | { | |
5783 | default: | |
5784 | break; | |
5785 | ||
5786 | case QImode: | |
5787 | return "stb%I0%U0 %., %M0"; | |
5788 | ||
5789 | case HImode: | |
5790 | return "sth%I0%U0 %., %M0"; | |
5791 | ||
5792 | case SImode: | |
5793 | case SFmode: | |
5794 | return "st%I0%U0 %., %M0"; | |
5795 | } | |
5796 | } | |
5797 | } | |
5798 | ||
5799 | fatal_insn ("Bad output_move_single operand", insn); | |
5800 | return ""; | |
5801 | } | |
5802 | ||
5803 | \f | |
5804 | /* Return a string to output a double word move. */ | |
5805 | ||
5806 | const char * | |
f2206911 | 5807 | output_move_double (rtx operands[], rtx insn) |
36a05131 BS |
5808 | { |
5809 | rtx dest = operands[0]; | |
5810 | rtx src = operands[1]; | |
5811 | enum machine_mode mode = GET_MODE (dest); | |
5812 | ||
5813 | if (GET_CODE (dest) == REG) | |
5814 | { | |
5815 | int dest_regno = REGNO (dest); | |
5816 | ||
5817 | if (GPR_P (dest_regno)) | |
5818 | { | |
5819 | if (GET_CODE (src) == REG) | |
5820 | { | |
5821 | /* gpr <- some sort of register */ | |
5822 | int src_regno = REGNO (src); | |
5823 | ||
5824 | if (GPR_P (src_regno)) | |
5825 | return "#"; | |
5826 | ||
5827 | else if (FPR_P (src_regno)) | |
5828 | { | |
5829 | if (((dest_regno - GPR_FIRST) & 1) == 0 | |
5830 | && ((src_regno - FPR_FIRST) & 1) == 0) | |
5831 | return "movfgd %1, %0"; | |
5832 | ||
5833 | return "#"; | |
5834 | } | |
5835 | } | |
5836 | ||
5837 | else if (GET_CODE (src) == MEM) | |
5838 | { | |
5839 | /* gpr <- memory */ | |
5840 | if (dbl_memory_one_insn_operand (src, mode)) | |
5841 | return "ldd%I1%U1 %M1, %0"; | |
5842 | ||
5843 | return "#"; | |
5844 | } | |
5845 | ||
5846 | else if (GET_CODE (src) == CONST_INT | |
5847 | || GET_CODE (src) == CONST_DOUBLE) | |
5848 | return "#"; | |
5849 | } | |
5850 | ||
5851 | else if (FPR_P (dest_regno)) | |
5852 | { | |
5853 | if (GET_CODE (src) == REG) | |
5854 | { | |
5855 | /* fpr <- some sort of register */ | |
5856 | int src_regno = REGNO (src); | |
5857 | ||
5858 | if (GPR_P (src_regno)) | |
5859 | { | |
5860 | if (((dest_regno - FPR_FIRST) & 1) == 0 | |
5861 | && ((src_regno - GPR_FIRST) & 1) == 0) | |
5862 | return "movgfd %1, %0"; | |
5863 | ||
5864 | return "#"; | |
5865 | } | |
5866 | ||
5867 | else if (FPR_P (src_regno)) | |
5868 | { | |
5869 | if (TARGET_DOUBLE | |
5870 | && ((dest_regno - FPR_FIRST) & 1) == 0 | |
5871 | && ((src_regno - FPR_FIRST) & 1) == 0) | |
5872 | return "fmovd %1, %0"; | |
5873 | ||
5874 | return "#"; | |
5875 | } | |
5876 | } | |
5877 | ||
5878 | else if (GET_CODE (src) == MEM) | |
5879 | { | |
5880 | /* fpr <- memory */ | |
5881 | if (dbl_memory_one_insn_operand (src, mode)) | |
5882 | return "lddf%I1%U1 %M1, %0"; | |
5883 | ||
5884 | return "#"; | |
5885 | } | |
5886 | ||
5887 | else if (ZERO_P (src)) | |
5888 | return "#"; | |
5889 | } | |
5890 | } | |
5891 | ||
5892 | else if (GET_CODE (dest) == MEM) | |
5893 | { | |
5894 | if (GET_CODE (src) == REG) | |
5895 | { | |
5896 | int src_regno = REGNO (src); | |
5897 | ||
5898 | if (GPR_P (src_regno)) | |
5899 | { | |
5900 | if (((src_regno - GPR_FIRST) & 1) == 0 | |
5901 | && dbl_memory_one_insn_operand (dest, mode)) | |
5902 | return "std%I0%U0 %1, %M0"; | |
5903 | ||
5904 | return "#"; | |
5905 | } | |
5906 | ||
5907 | if (FPR_P (src_regno)) | |
5908 | { | |
5909 | if (((src_regno - FPR_FIRST) & 1) == 0 | |
5910 | && dbl_memory_one_insn_operand (dest, mode)) | |
5911 | return "stdf%I0%U0 %1, %M0"; | |
5912 | ||
5913 | return "#"; | |
5914 | } | |
5915 | } | |
5916 | ||
5917 | else if (ZERO_P (src)) | |
5918 | { | |
5919 | if (dbl_memory_one_insn_operand (dest, mode)) | |
5920 | return "std%I0%U0 %., %M0"; | |
5921 | ||
5922 | return "#"; | |
5923 | } | |
5924 | } | |
5925 | ||
5926 | fatal_insn ("Bad output_move_double operand", insn); | |
5927 | return ""; | |
5928 | } | |
5929 | ||
5930 | \f | |
5931 | /* Return a string to output a single word conditional move. | |
5932 | Operand0 -- EQ/NE of ccr register and 0 | |
5933 | Operand1 -- CCR register | |
5934 | Operand2 -- destination | |
5935 | Operand3 -- source */ | |
5936 | ||
5937 | const char * | |
f2206911 | 5938 | output_condmove_single (rtx operands[], rtx insn) |
36a05131 BS |
5939 | { |
5940 | rtx dest = operands[2]; | |
5941 | rtx src = operands[3]; | |
5942 | ||
5943 | if (GET_CODE (dest) == REG) | |
5944 | { | |
5945 | int dest_regno = REGNO (dest); | |
5946 | enum machine_mode mode = GET_MODE (dest); | |
5947 | ||
5948 | if (GPR_P (dest_regno)) | |
5949 | { | |
5950 | if (GET_CODE (src) == REG) | |
5951 | { | |
5952 | /* gpr <- some sort of register */ | |
5953 | int src_regno = REGNO (src); | |
5954 | ||
5955 | if (GPR_P (src_regno)) | |
5956 | return "cmov %z3, %2, %1, %e0"; | |
5957 | ||
5958 | else if (FPR_P (src_regno)) | |
5959 | return "cmovfg %3, %2, %1, %e0"; | |
5960 | } | |
5961 | ||
5962 | else if (GET_CODE (src) == MEM) | |
5963 | { | |
5964 | /* gpr <- memory */ | |
5965 | switch (mode) | |
5966 | { | |
5967 | default: | |
5968 | break; | |
5969 | ||
5970 | case QImode: | |
5971 | return "cldsb%I3%U3 %M3, %2, %1, %e0"; | |
5972 | ||
5973 | case HImode: | |
5974 | return "cldsh%I3%U3 %M3, %2, %1, %e0"; | |
5975 | ||
5976 | case SImode: | |
5977 | case SFmode: | |
5978 | return "cld%I3%U3 %M3, %2, %1, %e0"; | |
5979 | } | |
5980 | } | |
5981 | ||
5982 | else if (ZERO_P (src)) | |
5983 | return "cmov %., %2, %1, %e0"; | |
5984 | } | |
5985 | ||
5986 | else if (FPR_P (dest_regno)) | |
5987 | { | |
5988 | if (GET_CODE (src) == REG) | |
5989 | { | |
5990 | /* fpr <- some sort of register */ | |
5991 | int src_regno = REGNO (src); | |
5992 | ||
5993 | if (GPR_P (src_regno)) | |
5994 | return "cmovgf %3, %2, %1, %e0"; | |
5995 | ||
5996 | else if (FPR_P (src_regno)) | |
5997 | { | |
5998 | if (TARGET_HARD_FLOAT) | |
5999 | return "cfmovs %3,%2,%1,%e0"; | |
6000 | else | |
6001 | return "cmor %3, %3, %2, %1, %e0"; | |
6002 | } | |
6003 | } | |
6004 | ||
6005 | else if (GET_CODE (src) == MEM) | |
6006 | { | |
6007 | /* fpr <- memory */ | |
6008 | if (mode == SImode || mode == SFmode) | |
6009 | return "cldf%I3%U3 %M3, %2, %1, %e0"; | |
6010 | } | |
6011 | ||
6012 | else if (ZERO_P (src)) | |
6013 | return "cmovgf %., %2, %1, %e0"; | |
6014 | } | |
6015 | } | |
6016 | ||
6017 | else if (GET_CODE (dest) == MEM) | |
6018 | { | |
6019 | if (GET_CODE (src) == REG) | |
6020 | { | |
6021 | int src_regno = REGNO (src); | |
6022 | enum machine_mode mode = GET_MODE (dest); | |
6023 | ||
6024 | if (GPR_P (src_regno)) | |
6025 | { | |
6026 | switch (mode) | |
6027 | { | |
6028 | default: | |
6029 | break; | |
6030 | ||
6031 | case QImode: | |
6032 | return "cstb%I2%U2 %3, %M2, %1, %e0"; | |
6033 | ||
6034 | case HImode: | |
6035 | return "csth%I2%U2 %3, %M2, %1, %e0"; | |
6036 | ||
6037 | case SImode: | |
6038 | case SFmode: | |
6039 | return "cst%I2%U2 %3, %M2, %1, %e0"; | |
6040 | } | |
6041 | } | |
6042 | ||
6043 | else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode)) | |
6044 | return "cstf%I2%U2 %3, %M2, %1, %e0"; | |
6045 | } | |
6046 | ||
6047 | else if (ZERO_P (src)) | |
6048 | { | |
6049 | enum machine_mode mode = GET_MODE (dest); | |
6050 | switch (mode) | |
6051 | { | |
6052 | default: | |
6053 | break; | |
6054 | ||
6055 | case QImode: | |
6056 | return "cstb%I2%U2 %., %M2, %1, %e0"; | |
6057 | ||
6058 | case HImode: | |
6059 | return "csth%I2%U2 %., %M2, %1, %e0"; | |
6060 | ||
6061 | case SImode: | |
6062 | case SFmode: | |
6063 | return "cst%I2%U2 %., %M2, %1, %e0"; | |
6064 | } | |
6065 | } | |
6066 | } | |
6067 | ||
6068 | fatal_insn ("Bad output_condmove_single operand", insn); | |
6069 | return ""; | |
6070 | } | |
6071 | ||
6072 | \f | |
6073 | /* Emit the appropriate code to do a comparison, returning the register the | |
6074 | comparison was done it. */ | |
6075 | ||
6076 | static rtx | |
f2206911 | 6077 | frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1) |
36a05131 BS |
6078 | { |
6079 | enum machine_mode cc_mode; | |
6080 | rtx cc_reg; | |
6081 | ||
87b483a1 | 6082 | /* Floating point doesn't have comparison against a constant. */ |
36a05131 BS |
6083 | if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG) |
6084 | op1 = force_reg (GET_MODE (op0), op1); | |
6085 | ||
6086 | /* Possibly disable using anything but a fixed register in order to work | |
6087 | around cse moving comparisons past function calls. */ | |
6088 | cc_mode = SELECT_CC_MODE (test, op0, op1); | |
6089 | cc_reg = ((TARGET_ALLOC_CC) | |
6090 | ? gen_reg_rtx (cc_mode) | |
6091 | : gen_rtx_REG (cc_mode, | |
6092 | (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST)); | |
6093 | ||
6094 | emit_insn (gen_rtx_SET (VOIDmode, cc_reg, | |
6095 | gen_rtx_COMPARE (cc_mode, op0, op1))); | |
6096 | ||
6097 | return cc_reg; | |
6098 | } | |
6099 | ||
6100 | \f | |
6101 | /* Emit code for a conditional branch. The comparison operands were previously | |
6102 | stored in frv_compare_op0 and frv_compare_op1. | |
6103 | ||
6104 | XXX: I originally wanted to add a clobber of a CCR register to use in | |
6105 | conditional execution, but that confuses the rest of the compiler. */ | |
6106 | ||
6107 | int | |
f2206911 | 6108 | frv_emit_cond_branch (enum rtx_code test, rtx label) |
36a05131 BS |
6109 | { |
6110 | rtx test_rtx; | |
6111 | rtx label_ref; | |
6112 | rtx if_else; | |
6113 | rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1); | |
6114 | enum machine_mode cc_mode = GET_MODE (cc_reg); | |
6115 | ||
6116 | /* Branches generate: | |
6117 | (set (pc) | |
6118 | (if_then_else (<test>, <cc_reg>, (const_int 0)) | |
6119 | (label_ref <branch_label>) | |
6120 | (pc))) */ | |
6121 | label_ref = gen_rtx_LABEL_REF (VOIDmode, label); | |
1c563bed | 6122 | test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx); |
36a05131 BS |
6123 | if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx); |
6124 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else)); | |
6125 | return TRUE; | |
6126 | } | |
6127 | ||
6128 | \f | |
6129 | /* Emit code to set a gpr to 1/0 based on a comparison. The comparison | |
6130 | operands were previously stored in frv_compare_op0 and frv_compare_op1. */ | |
6131 | ||
6132 | int | |
f2206911 | 6133 | frv_emit_scc (enum rtx_code test, rtx target) |
36a05131 BS |
6134 | { |
6135 | rtx set; | |
6136 | rtx test_rtx; | |
6137 | rtx clobber; | |
6138 | rtx cr_reg; | |
6139 | rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1); | |
6140 | ||
6141 | /* SCC instructions generate: | |
6142 | (parallel [(set <target> (<test>, <cc_reg>, (const_int 0)) | |
6143 | (clobber (<ccr_reg>))]) */ | |
6144 | test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx); | |
6145 | set = gen_rtx_SET (VOIDmode, target, test_rtx); | |
6146 | ||
6147 | cr_reg = ((TARGET_ALLOC_CC) | |
6148 | ? gen_reg_rtx (CC_CCRmode) | |
6149 | : gen_rtx_REG (CC_CCRmode, | |
6150 | ((GET_MODE (cc_reg) == CC_FPmode) | |
6151 | ? FCR_FIRST | |
6152 | : ICR_FIRST))); | |
6153 | ||
6154 | clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg); | |
6155 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber))); | |
6156 | return TRUE; | |
6157 | } | |
6158 | ||
6159 | \f | |
6160 | /* Split a SCC instruction into component parts, returning a SEQUENCE to hold | |
839a4992 | 6161 | the separate insns. */ |
36a05131 BS |
6162 | |
6163 | rtx | |
f2206911 | 6164 | frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value) |
36a05131 BS |
6165 | { |
6166 | rtx ret; | |
6167 | ||
6168 | start_sequence (); | |
6169 | ||
6170 | /* Set the appropriate CCR bit. */ | |
6171 | emit_insn (gen_rtx_SET (VOIDmode, | |
6172 | cr_reg, | |
6173 | gen_rtx_fmt_ee (GET_CODE (test), | |
6174 | GET_MODE (cr_reg), | |
6175 | cc_reg, | |
6176 | const0_rtx))); | |
6177 | ||
6178 | /* Move the value into the destination. */ | |
6179 | emit_move_insn (dest, GEN_INT (value)); | |
6180 | ||
6181 | /* Move 0 into the destination if the test failed */ | |
6182 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
6183 | gen_rtx_EQ (GET_MODE (cr_reg), | |
6184 | cr_reg, | |
6185 | const0_rtx), | |
6186 | gen_rtx_SET (VOIDmode, dest, const0_rtx))); | |
6187 | ||
6188 | /* Finish up, return sequence. */ | |
6189 | ret = get_insns (); | |
6190 | end_sequence (); | |
6191 | return ret; | |
6192 | } | |
6193 | ||
6194 | \f | |
6195 | /* Emit the code for a conditional move, return TRUE if we could do the | |
6196 | move. */ | |
6197 | ||
6198 | int | |
f2206911 | 6199 | frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2) |
36a05131 BS |
6200 | { |
6201 | rtx set; | |
6202 | rtx clobber_cc; | |
6203 | rtx test2; | |
6204 | rtx cr_reg; | |
6205 | rtx if_rtx; | |
6206 | enum rtx_code test = GET_CODE (test_rtx); | |
6207 | rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1); | |
6208 | enum machine_mode cc_mode = GET_MODE (cc_reg); | |
6209 | ||
6210 | /* Conditional move instructions generate: | |
6211 | (parallel [(set <target> | |
6212 | (if_then_else (<test> <cc_reg> (const_int 0)) | |
6213 | <src1> | |
6214 | <src2>)) | |
6215 | (clobber (<ccr_reg>))]) */ | |
6216 | ||
6217 | /* Handle various cases of conditional move involving two constants. */ | |
6218 | if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT) | |
6219 | { | |
6220 | HOST_WIDE_INT value1 = INTVAL (src1); | |
6221 | HOST_WIDE_INT value2 = INTVAL (src2); | |
6222 | ||
87b483a1 | 6223 | /* Having 0 as one of the constants can be done by loading the other |
36a05131 BS |
6224 | constant, and optionally moving in gr0. */ |
6225 | if (value1 == 0 || value2 == 0) | |
6226 | ; | |
6227 | ||
6228 | /* If the first value is within an addi range and also the difference | |
6229 | between the two fits in an addi's range, load up the difference, then | |
6230 | conditionally move in 0, and then unconditionally add the first | |
6231 | value. */ | |
6232 | else if (IN_RANGE_P (value1, -2048, 2047) | |
6233 | && IN_RANGE_P (value2 - value1, -2048, 2047)) | |
6234 | ; | |
6235 | ||
6236 | /* If neither condition holds, just force the constant into a | |
6237 | register. */ | |
6238 | else | |
6239 | { | |
6240 | src1 = force_reg (GET_MODE (dest), src1); | |
6241 | src2 = force_reg (GET_MODE (dest), src2); | |
6242 | } | |
6243 | } | |
6244 | ||
6245 | /* If one value is a register, insure the other value is either 0 or a | |
6246 | register. */ | |
6247 | else | |
6248 | { | |
6249 | if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0) | |
6250 | src1 = force_reg (GET_MODE (dest), src1); | |
6251 | ||
6252 | if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0) | |
6253 | src2 = force_reg (GET_MODE (dest), src2); | |
6254 | } | |
6255 | ||
6256 | test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx); | |
6257 | if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2); | |
6258 | ||
6259 | set = gen_rtx_SET (VOIDmode, dest, if_rtx); | |
6260 | ||
6261 | cr_reg = ((TARGET_ALLOC_CC) | |
6262 | ? gen_reg_rtx (CC_CCRmode) | |
6263 | : gen_rtx_REG (CC_CCRmode, | |
6264 | (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST)); | |
6265 | ||
6266 | clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg); | |
6267 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc))); | |
6268 | return TRUE; | |
6269 | } | |
6270 | ||
6271 | \f | |
839a4992 | 6272 | /* Split a conditional move into constituent parts, returning a SEQUENCE |
36a05131 BS |
6273 | containing all of the insns. */ |
6274 | ||
6275 | rtx | |
f2206911 | 6276 | frv_split_cond_move (rtx operands[]) |
36a05131 BS |
6277 | { |
6278 | rtx dest = operands[0]; | |
6279 | rtx test = operands[1]; | |
6280 | rtx cc_reg = operands[2]; | |
6281 | rtx src1 = operands[3]; | |
6282 | rtx src2 = operands[4]; | |
6283 | rtx cr_reg = operands[5]; | |
6284 | rtx ret; | |
6285 | enum machine_mode cr_mode = GET_MODE (cr_reg); | |
6286 | ||
6287 | start_sequence (); | |
6288 | ||
6289 | /* Set the appropriate CCR bit. */ | |
6290 | emit_insn (gen_rtx_SET (VOIDmode, | |
6291 | cr_reg, | |
6292 | gen_rtx_fmt_ee (GET_CODE (test), | |
6293 | GET_MODE (cr_reg), | |
6294 | cc_reg, | |
6295 | const0_rtx))); | |
6296 | ||
6297 | /* Handle various cases of conditional move involving two constants. */ | |
6298 | if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT) | |
6299 | { | |
6300 | HOST_WIDE_INT value1 = INTVAL (src1); | |
6301 | HOST_WIDE_INT value2 = INTVAL (src2); | |
6302 | ||
87b483a1 | 6303 | /* Having 0 as one of the constants can be done by loading the other |
36a05131 BS |
6304 | constant, and optionally moving in gr0. */ |
6305 | if (value1 == 0) | |
6306 | { | |
6307 | emit_move_insn (dest, src2); | |
6308 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
6309 | gen_rtx_NE (cr_mode, cr_reg, | |
6310 | const0_rtx), | |
6311 | gen_rtx_SET (VOIDmode, dest, src1))); | |
6312 | } | |
6313 | ||
6314 | else if (value2 == 0) | |
6315 | { | |
6316 | emit_move_insn (dest, src1); | |
6317 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
6318 | gen_rtx_EQ (cr_mode, cr_reg, | |
6319 | const0_rtx), | |
6320 | gen_rtx_SET (VOIDmode, dest, src2))); | |
6321 | } | |
6322 | ||
6323 | /* If the first value is within an addi range and also the difference | |
6324 | between the two fits in an addi's range, load up the difference, then | |
6325 | conditionally move in 0, and then unconditionally add the first | |
6326 | value. */ | |
6327 | else if (IN_RANGE_P (value1, -2048, 2047) | |
6328 | && IN_RANGE_P (value2 - value1, -2048, 2047)) | |
6329 | { | |
6330 | rtx dest_si = ((GET_MODE (dest) == SImode) | |
6331 | ? dest | |
6332 | : gen_rtx_SUBREG (SImode, dest, 0)); | |
6333 | ||
6334 | emit_move_insn (dest_si, GEN_INT (value2 - value1)); | |
6335 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
6336 | gen_rtx_NE (cr_mode, cr_reg, | |
6337 | const0_rtx), | |
6338 | gen_rtx_SET (VOIDmode, dest_si, | |
6339 | const0_rtx))); | |
6340 | emit_insn (gen_addsi3 (dest_si, dest_si, src1)); | |
6341 | } | |
6342 | ||
6343 | else | |
6344 | abort (); | |
6345 | } | |
6346 | else | |
6347 | { | |
6348 | /* Emit the conditional move for the test being true if needed. */ | |
6349 | if (! rtx_equal_p (dest, src1)) | |
6350 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
6351 | gen_rtx_NE (cr_mode, cr_reg, const0_rtx), | |
6352 | gen_rtx_SET (VOIDmode, dest, src1))); | |
6353 | ||
6354 | /* Emit the conditional move for the test being false if needed. */ | |
6355 | if (! rtx_equal_p (dest, src2)) | |
6356 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
6357 | gen_rtx_EQ (cr_mode, cr_reg, const0_rtx), | |
6358 | gen_rtx_SET (VOIDmode, dest, src2))); | |
6359 | } | |
6360 | ||
6361 | /* Finish up, return sequence. */ | |
6362 | ret = get_insns (); | |
6363 | end_sequence (); | |
6364 | return ret; | |
6365 | } | |
6366 | ||
6367 | \f | |
6368 | /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a | |
6369 | memory location that is not known to be dword-aligned. */ | |
6370 | void | |
f2206911 | 6371 | frv_split_double_load (rtx dest, rtx source) |
36a05131 BS |
6372 | { |
6373 | int regno = REGNO (dest); | |
6374 | rtx dest1 = gen_highpart (SImode, dest); | |
6375 | rtx dest2 = gen_lowpart (SImode, dest); | |
6376 | rtx address = XEXP (source, 0); | |
6377 | ||
6378 | /* If the address is pre-modified, load the lower-numbered register | |
6379 | first, then load the other register using an integer offset from | |
6380 | the modified base register. This order should always be safe, | |
6381 | since the pre-modification cannot affect the same registers as the | |
6382 | load does. | |
6383 | ||
6384 | The situation for other loads is more complicated. Loading one | |
6385 | of the registers could affect the value of ADDRESS, so we must | |
6386 | be careful which order we do them in. */ | |
6387 | if (GET_CODE (address) == PRE_MODIFY | |
6388 | || ! refers_to_regno_p (regno, regno + 1, address, NULL)) | |
6389 | { | |
6390 | /* It is safe to load the lower-numbered register first. */ | |
6391 | emit_move_insn (dest1, change_address (source, SImode, NULL)); | |
6392 | emit_move_insn (dest2, frv_index_memory (source, SImode, 1)); | |
6393 | } | |
6394 | else | |
6395 | { | |
6396 | /* ADDRESS is not pre-modified and the address depends on the | |
6397 | lower-numbered register. Load the higher-numbered register | |
6398 | first. */ | |
6399 | emit_move_insn (dest2, frv_index_memory (source, SImode, 1)); | |
6400 | emit_move_insn (dest1, change_address (source, SImode, NULL)); | |
6401 | } | |
6402 | } | |
6403 | ||
6404 | /* Split (set DEST SOURCE), where DEST refers to a dword memory location | |
6405 | and SOURCE is either a double register or the constant zero. */ | |
6406 | void | |
f2206911 | 6407 | frv_split_double_store (rtx dest, rtx source) |
36a05131 BS |
6408 | { |
6409 | rtx dest1 = change_address (dest, SImode, NULL); | |
6410 | rtx dest2 = frv_index_memory (dest, SImode, 1); | |
6411 | if (ZERO_P (source)) | |
6412 | { | |
6413 | emit_move_insn (dest1, CONST0_RTX (SImode)); | |
6414 | emit_move_insn (dest2, CONST0_RTX (SImode)); | |
6415 | } | |
6416 | else | |
6417 | { | |
6418 | emit_move_insn (dest1, gen_highpart (SImode, source)); | |
6419 | emit_move_insn (dest2, gen_lowpart (SImode, source)); | |
6420 | } | |
6421 | } | |
6422 | ||
6423 | \f | |
6424 | /* Split a min/max operation returning a SEQUENCE containing all of the | |
6425 | insns. */ | |
6426 | ||
6427 | rtx | |
f2206911 | 6428 | frv_split_minmax (rtx operands[]) |
36a05131 BS |
6429 | { |
6430 | rtx dest = operands[0]; | |
6431 | rtx minmax = operands[1]; | |
6432 | rtx src1 = operands[2]; | |
6433 | rtx src2 = operands[3]; | |
6434 | rtx cc_reg = operands[4]; | |
6435 | rtx cr_reg = operands[5]; | |
6436 | rtx ret; | |
6437 | enum rtx_code test_code; | |
6438 | enum machine_mode cr_mode = GET_MODE (cr_reg); | |
6439 | ||
6440 | start_sequence (); | |
6441 | ||
87b483a1 | 6442 | /* Figure out which test to use. */ |
36a05131 BS |
6443 | switch (GET_CODE (minmax)) |
6444 | { | |
6445 | default: | |
6446 | abort (); | |
6447 | ||
6448 | case SMIN: test_code = LT; break; | |
6449 | case SMAX: test_code = GT; break; | |
6450 | case UMIN: test_code = LTU; break; | |
6451 | case UMAX: test_code = GTU; break; | |
6452 | } | |
6453 | ||
6454 | /* Issue the compare instruction. */ | |
6455 | emit_insn (gen_rtx_SET (VOIDmode, | |
6456 | cc_reg, | |
6457 | gen_rtx_COMPARE (GET_MODE (cc_reg), | |
6458 | src1, src2))); | |
6459 | ||
6460 | /* Set the appropriate CCR bit. */ | |
6461 | emit_insn (gen_rtx_SET (VOIDmode, | |
6462 | cr_reg, | |
6463 | gen_rtx_fmt_ee (test_code, | |
6464 | GET_MODE (cr_reg), | |
6465 | cc_reg, | |
6466 | const0_rtx))); | |
6467 | ||
9cd10576 | 6468 | /* If are taking the min/max of a nonzero constant, load that first, and |
36a05131 BS |
6469 | then do a conditional move of the other value. */ |
6470 | if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0) | |
6471 | { | |
6472 | if (rtx_equal_p (dest, src1)) | |
6473 | abort (); | |
6474 | ||
6475 | emit_move_insn (dest, src2); | |
6476 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
6477 | gen_rtx_NE (cr_mode, cr_reg, const0_rtx), | |
6478 | gen_rtx_SET (VOIDmode, dest, src1))); | |
6479 | } | |
6480 | ||
6481 | /* Otherwise, do each half of the move. */ | |
6482 | else | |
6483 | { | |
6484 | /* Emit the conditional move for the test being true if needed. */ | |
6485 | if (! rtx_equal_p (dest, src1)) | |
6486 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
6487 | gen_rtx_NE (cr_mode, cr_reg, const0_rtx), | |
6488 | gen_rtx_SET (VOIDmode, dest, src1))); | |
6489 | ||
6490 | /* Emit the conditional move for the test being false if needed. */ | |
6491 | if (! rtx_equal_p (dest, src2)) | |
6492 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
6493 | gen_rtx_EQ (cr_mode, cr_reg, const0_rtx), | |
6494 | gen_rtx_SET (VOIDmode, dest, src2))); | |
6495 | } | |
6496 | ||
6497 | /* Finish up, return sequence. */ | |
6498 | ret = get_insns (); | |
6499 | end_sequence (); | |
6500 | return ret; | |
6501 | } | |
6502 | ||
6503 | \f | |
6504 | /* Split an integer abs operation returning a SEQUENCE containing all of the | |
6505 | insns. */ | |
6506 | ||
6507 | rtx | |
f2206911 | 6508 | frv_split_abs (rtx operands[]) |
36a05131 BS |
6509 | { |
6510 | rtx dest = operands[0]; | |
6511 | rtx src = operands[1]; | |
6512 | rtx cc_reg = operands[2]; | |
6513 | rtx cr_reg = operands[3]; | |
6514 | rtx ret; | |
6515 | ||
6516 | start_sequence (); | |
6517 | ||
6518 | /* Issue the compare < 0 instruction. */ | |
6519 | emit_insn (gen_rtx_SET (VOIDmode, | |
6520 | cc_reg, | |
6521 | gen_rtx_COMPARE (CCmode, src, const0_rtx))); | |
6522 | ||
6523 | /* Set the appropriate CCR bit. */ | |
6524 | emit_insn (gen_rtx_SET (VOIDmode, | |
6525 | cr_reg, | |
6526 | gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx))); | |
6527 | ||
87b483a1 | 6528 | /* Emit the conditional negate if the value is negative. */ |
36a05131 BS |
6529 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, |
6530 | gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx), | |
6531 | gen_negsi2 (dest, src))); | |
6532 | ||
6533 | /* Emit the conditional move for the test being false if needed. */ | |
6534 | if (! rtx_equal_p (dest, src)) | |
6535 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
6536 | gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx), | |
6537 | gen_rtx_SET (VOIDmode, dest, src))); | |
6538 | ||
6539 | /* Finish up, return sequence. */ | |
6540 | ret = get_insns (); | |
6541 | end_sequence (); | |
6542 | return ret; | |
6543 | } | |
6544 | ||
6545 | \f | |
6546 | /* An internal function called by for_each_rtx to clear in a hard_reg set each | |
6547 | register used in an insn. */ | |
6548 | ||
6549 | static int | |
f2206911 | 6550 | frv_clear_registers_used (rtx *ptr, void *data) |
36a05131 BS |
6551 | { |
6552 | if (GET_CODE (*ptr) == REG) | |
6553 | { | |
6554 | int regno = REGNO (*ptr); | |
6555 | HARD_REG_SET *p_regs = (HARD_REG_SET *)data; | |
6556 | ||
6557 | if (regno < FIRST_PSEUDO_REGISTER) | |
6558 | { | |
6559 | int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr)); | |
6560 | ||
6561 | while (regno < reg_max) | |
6562 | { | |
6563 | CLEAR_HARD_REG_BIT (*p_regs, regno); | |
6564 | regno++; | |
6565 | } | |
6566 | } | |
6567 | } | |
6568 | ||
6569 | return 0; | |
6570 | } | |
6571 | ||
6572 | \f | |
6573 | /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */ | |
6574 | ||
6575 | /* On the FR-V, we don't have any extra fields per se, but it is useful hook to | |
6576 | initialize the static storage. */ | |
6577 | void | |
f2206911 | 6578 | frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED) |
36a05131 BS |
6579 | { |
6580 | frv_ifcvt.added_insns_list = NULL_RTX; | |
6581 | frv_ifcvt.cur_scratch_regs = 0; | |
6582 | frv_ifcvt.num_nested_cond_exec = 0; | |
6583 | frv_ifcvt.cr_reg = NULL_RTX; | |
6584 | frv_ifcvt.nested_cc_reg = NULL_RTX; | |
6585 | frv_ifcvt.extra_int_cr = NULL_RTX; | |
6586 | frv_ifcvt.extra_fp_cr = NULL_RTX; | |
6587 | frv_ifcvt.last_nested_if_cr = NULL_RTX; | |
6588 | } | |
6589 | ||
6590 | \f | |
1ae58c30 | 6591 | /* Internal function to add a potential insn to the list of insns to be inserted |
36a05131 BS |
6592 | if the conditional execution conversion is successful. */ |
6593 | ||
6594 | static void | |
f2206911 | 6595 | frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p) |
36a05131 BS |
6596 | { |
6597 | rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn); | |
6598 | ||
87b483a1 | 6599 | link->jump = before_p; /* Mark to add this before or after insn. */ |
36a05131 BS |
6600 | frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link, |
6601 | frv_ifcvt.added_insns_list); | |
6602 | ||
6603 | if (TARGET_DEBUG_COND_EXEC) | |
6604 | { | |
6605 | fprintf (stderr, | |
6606 | "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n", | |
6607 | (before_p) ? "before" : "after", | |
6608 | (int)INSN_UID (insn)); | |
6609 | ||
6610 | debug_rtx (pattern); | |
6611 | } | |
6612 | } | |
6613 | ||
6614 | \f | |
6615 | /* A C expression to modify the code described by the conditional if | |
6616 | information CE_INFO, possibly updating the tests in TRUE_EXPR, and | |
6617 | FALSE_EXPR for converting if-then and if-then-else code to conditional | |
6618 | instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the | |
6619 | tests cannot be converted. */ | |
6620 | ||
6621 | void | |
f2206911 | 6622 | frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false) |
36a05131 BS |
6623 | { |
6624 | basic_block test_bb = ce_info->test_bb; /* test basic block */ | |
6625 | basic_block then_bb = ce_info->then_bb; /* THEN */ | |
6626 | basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */ | |
6627 | basic_block join_bb = ce_info->join_bb; /* join block or NULL */ | |
6628 | rtx true_expr = *p_true; | |
6629 | rtx cr; | |
6630 | rtx cc; | |
6631 | rtx nested_cc; | |
6632 | enum machine_mode mode = GET_MODE (true_expr); | |
6633 | int j; | |
6634 | basic_block *bb; | |
6635 | int num_bb; | |
6636 | frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg; | |
6637 | rtx check_insn; | |
6638 | rtx sub_cond_exec_reg; | |
6639 | enum rtx_code code; | |
6640 | enum rtx_code code_true; | |
6641 | enum rtx_code code_false; | |
6642 | enum reg_class cc_class; | |
6643 | enum reg_class cr_class; | |
6644 | int cc_first; | |
6645 | int cc_last; | |
6646 | ||
6647 | /* Make sure we are only dealing with hard registers. Also honor the | |
6648 | -mno-cond-exec switch, and -mno-nested-cond-exec switches if | |
6649 | applicable. */ | |
6650 | if (!reload_completed || TARGET_NO_COND_EXEC | |
6651 | || (TARGET_NO_NESTED_CE && ce_info->pass > 1)) | |
6652 | goto fail; | |
6653 | ||
6654 | /* Figure out which registers we can allocate for our own purposes. Only | |
6655 | consider registers that are not preserved across function calls and are | |
6656 | not fixed. However, allow the ICC/ICR temporary registers to be allocated | |
87b483a1 | 6657 | if we did not need to use them in reloading other registers. */ |
fad205ff | 6658 | memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs)); |
36a05131 BS |
6659 | COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set); |
6660 | AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set); | |
6661 | SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP); | |
6662 | SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP); | |
6663 | ||
6664 | /* If this is a nested IF, we need to discover whether the CC registers that | |
6665 | are set/used inside of the block are used anywhere else. If not, we can | |
6666 | change them to be the CC register that is paired with the CR register that | |
6667 | controls the outermost IF block. */ | |
6668 | if (ce_info->pass > 1) | |
6669 | { | |
6670 | CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite); | |
6671 | for (j = CC_FIRST; j <= CC_LAST; j++) | |
6672 | if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) | |
6673 | { | |
6674 | if (REGNO_REG_SET_P (then_bb->global_live_at_start, j)) | |
6675 | continue; | |
6676 | ||
6677 | if (else_bb && REGNO_REG_SET_P (else_bb->global_live_at_start, j)) | |
6678 | continue; | |
6679 | ||
6680 | if (join_bb && REGNO_REG_SET_P (join_bb->global_live_at_start, j)) | |
6681 | continue; | |
6682 | ||
6683 | SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j); | |
6684 | } | |
6685 | } | |
6686 | ||
6687 | for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++) | |
6688 | frv_ifcvt.scratch_regs[j] = NULL_RTX; | |
6689 | ||
6690 | frv_ifcvt.added_insns_list = NULL_RTX; | |
6691 | frv_ifcvt.cur_scratch_regs = 0; | |
6692 | ||
6693 | bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks) | |
6694 | * sizeof (basic_block)); | |
6695 | ||
6696 | if (join_bb) | |
6697 | { | |
6698 | int regno; | |
6699 | ||
6700 | /* Remove anything live at the beginning of the join block from being | |
6701 | available for allocation. */ | |
6702 | EXECUTE_IF_SET_IN_REG_SET (join_bb->global_live_at_start, 0, regno, | |
6703 | { | |
6704 | if (regno < FIRST_PSEUDO_REGISTER) | |
6705 | CLEAR_HARD_REG_BIT (tmp_reg->regs, regno); | |
6706 | }); | |
6707 | } | |
6708 | ||
6709 | /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */ | |
6710 | num_bb = 0; | |
6711 | if (ce_info->num_multiple_test_blocks) | |
6712 | { | |
6713 | basic_block multiple_test_bb = ce_info->last_test_bb; | |
6714 | ||
6715 | while (multiple_test_bb != test_bb) | |
6716 | { | |
6717 | bb[num_bb++] = multiple_test_bb; | |
6718 | multiple_test_bb = multiple_test_bb->pred->src; | |
6719 | } | |
6720 | } | |
6721 | ||
6722 | /* Add in the THEN and ELSE blocks to be scanned. */ | |
6723 | bb[num_bb++] = then_bb; | |
6724 | if (else_bb) | |
6725 | bb[num_bb++] = else_bb; | |
6726 | ||
6727 | sub_cond_exec_reg = NULL_RTX; | |
6728 | frv_ifcvt.num_nested_cond_exec = 0; | |
6729 | ||
6730 | /* Scan all of the blocks for registers that must not be allocated. */ | |
6731 | for (j = 0; j < num_bb; j++) | |
6732 | { | |
a813c111 SB |
6733 | rtx last_insn = BB_END (bb[j]); |
6734 | rtx insn = BB_HEAD (bb[j]); | |
36a05131 BS |
6735 | int regno; |
6736 | ||
c263766c RH |
6737 | if (dump_file) |
6738 | fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n", | |
36a05131 BS |
6739 | (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"), |
6740 | (int) bb[j]->index, | |
a813c111 SB |
6741 | (int) INSN_UID (BB_HEAD (bb[j])), |
6742 | (int) INSN_UID (BB_END (bb[j]))); | |
36a05131 BS |
6743 | |
6744 | /* Anything live at the beginning of the block is obviously unavailable | |
6745 | for allocation. */ | |
6746 | EXECUTE_IF_SET_IN_REG_SET (bb[j]->global_live_at_start, 0, regno, | |
6747 | { | |
6748 | if (regno < FIRST_PSEUDO_REGISTER) | |
6749 | CLEAR_HARD_REG_BIT (tmp_reg->regs, regno); | |
6750 | }); | |
6751 | ||
87b483a1 | 6752 | /* Loop through the insns in the block. */ |
36a05131 BS |
6753 | for (;;) |
6754 | { | |
6755 | /* Mark any new registers that are created as being unavailable for | |
6756 | allocation. Also see if the CC register used in nested IFs can be | |
6757 | reallocated. */ | |
6758 | if (INSN_P (insn)) | |
6759 | { | |
6760 | rtx pattern; | |
6761 | rtx set; | |
6762 | int skip_nested_if = FALSE; | |
6763 | ||
6764 | for_each_rtx (&PATTERN (insn), frv_clear_registers_used, | |
6765 | (void *)&tmp_reg->regs); | |
6766 | ||
6767 | pattern = PATTERN (insn); | |
6768 | if (GET_CODE (pattern) == COND_EXEC) | |
6769 | { | |
6770 | rtx reg = XEXP (COND_EXEC_TEST (pattern), 0); | |
6771 | ||
6772 | if (reg != sub_cond_exec_reg) | |
6773 | { | |
6774 | sub_cond_exec_reg = reg; | |
6775 | frv_ifcvt.num_nested_cond_exec++; | |
6776 | } | |
6777 | } | |
6778 | ||
6779 | set = single_set_pattern (pattern); | |
6780 | if (set) | |
6781 | { | |
6782 | rtx dest = SET_DEST (set); | |
6783 | rtx src = SET_SRC (set); | |
6784 | ||
6785 | if (GET_CODE (dest) == REG) | |
6786 | { | |
6787 | int regno = REGNO (dest); | |
6788 | enum rtx_code src_code = GET_CODE (src); | |
6789 | ||
6790 | if (CC_P (regno) && src_code == COMPARE) | |
6791 | skip_nested_if = TRUE; | |
6792 | ||
6793 | else if (CR_P (regno) | |
6794 | && (src_code == IF_THEN_ELSE | |
ec8e098d | 6795 | || COMPARISON_P (src))) |
36a05131 BS |
6796 | skip_nested_if = TRUE; |
6797 | } | |
6798 | } | |
6799 | ||
6800 | if (! skip_nested_if) | |
6801 | for_each_rtx (&PATTERN (insn), frv_clear_registers_used, | |
6802 | (void *)&frv_ifcvt.nested_cc_ok_rewrite); | |
6803 | } | |
6804 | ||
6805 | if (insn == last_insn) | |
6806 | break; | |
6807 | ||
6808 | insn = NEXT_INSN (insn); | |
6809 | } | |
6810 | } | |
6811 | ||
6812 | /* If this is a nested if, rewrite the CC registers that are available to | |
6813 | include the ones that can be rewritten, to increase the chance of being | |
6814 | able to allocate a paired CC/CR register combination. */ | |
6815 | if (ce_info->pass > 1) | |
6816 | { | |
6817 | for (j = CC_FIRST; j <= CC_LAST; j++) | |
6818 | if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j)) | |
6819 | SET_HARD_REG_BIT (tmp_reg->regs, j); | |
6820 | else | |
6821 | CLEAR_HARD_REG_BIT (tmp_reg->regs, j); | |
6822 | } | |
6823 | ||
c263766c | 6824 | if (dump_file) |
36a05131 BS |
6825 | { |
6826 | int num_gprs = 0; | |
c263766c | 6827 | fprintf (dump_file, "Available GPRs: "); |
36a05131 BS |
6828 | |
6829 | for (j = GPR_FIRST; j <= GPR_LAST; j++) | |
6830 | if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) | |
6831 | { | |
c263766c | 6832 | fprintf (dump_file, " %d [%s]", j, reg_names[j]); |
36a05131 BS |
6833 | if (++num_gprs > GPR_TEMP_NUM+2) |
6834 | break; | |
6835 | } | |
6836 | ||
c263766c | 6837 | fprintf (dump_file, "%s\nAvailable CRs: ", |
36a05131 BS |
6838 | (num_gprs > GPR_TEMP_NUM+2) ? " ..." : ""); |
6839 | ||
6840 | for (j = CR_FIRST; j <= CR_LAST; j++) | |
6841 | if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) | |
c263766c | 6842 | fprintf (dump_file, " %d [%s]", j, reg_names[j]); |
36a05131 | 6843 | |
c263766c | 6844 | fputs ("\n", dump_file); |
36a05131 BS |
6845 | |
6846 | if (ce_info->pass > 1) | |
6847 | { | |
c263766c | 6848 | fprintf (dump_file, "Modifiable CCs: "); |
36a05131 BS |
6849 | for (j = CC_FIRST; j <= CC_LAST; j++) |
6850 | if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) | |
c263766c | 6851 | fprintf (dump_file, " %d [%s]", j, reg_names[j]); |
36a05131 | 6852 | |
c263766c | 6853 | fprintf (dump_file, "\n%d nested COND_EXEC statements\n", |
36a05131 BS |
6854 | frv_ifcvt.num_nested_cond_exec); |
6855 | } | |
6856 | } | |
6857 | ||
6858 | /* Allocate the appropriate temporary condition code register. Try to | |
6859 | allocate the ICR/FCR register that corresponds to the ICC/FCC register so | |
6860 | that conditional cmp's can be done. */ | |
6861 | if (mode == CCmode || mode == CC_UNSmode) | |
6862 | { | |
6863 | cr_class = ICR_REGS; | |
6864 | cc_class = ICC_REGS; | |
6865 | cc_first = ICC_FIRST; | |
6866 | cc_last = ICC_LAST; | |
6867 | } | |
6868 | else if (mode == CC_FPmode) | |
6869 | { | |
6870 | cr_class = FCR_REGS; | |
6871 | cc_class = FCC_REGS; | |
6872 | cc_first = FCC_FIRST; | |
6873 | cc_last = FCC_LAST; | |
6874 | } | |
6875 | else | |
6876 | { | |
6877 | cc_first = cc_last = 0; | |
6878 | cr_class = cc_class = NO_REGS; | |
6879 | } | |
6880 | ||
6881 | cc = XEXP (true_expr, 0); | |
6882 | nested_cc = cr = NULL_RTX; | |
6883 | if (cc_class != NO_REGS) | |
6884 | { | |
6885 | /* For nested IFs and &&/||, see if we can find a CC and CR register pair | |
6886 | so we can execute a csubcc/caddcc/cfcmps instruction. */ | |
6887 | int cc_regno; | |
6888 | ||
6889 | for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++) | |
6890 | { | |
6891 | int cr_regno = cc_regno - CC_FIRST + CR_FIRST; | |
6892 | ||
6893 | if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno) | |
6894 | && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno)) | |
6895 | { | |
6896 | frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno; | |
6897 | cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE, | |
6898 | TRUE); | |
6899 | ||
6900 | frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno; | |
6901 | nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode, | |
6902 | TRUE, TRUE); | |
6903 | break; | |
6904 | } | |
6905 | } | |
6906 | } | |
6907 | ||
6908 | if (! cr) | |
6909 | { | |
c263766c RH |
6910 | if (dump_file) |
6911 | fprintf (dump_file, "Could not allocate a CR temporary register\n"); | |
36a05131 BS |
6912 | |
6913 | goto fail; | |
6914 | } | |
6915 | ||
c263766c RH |
6916 | if (dump_file) |
6917 | fprintf (dump_file, | |
36a05131 BS |
6918 | "Will use %s for conditional execution, %s for nested comparisons\n", |
6919 | reg_names[ REGNO (cr)], | |
6920 | (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>"); | |
6921 | ||
6922 | /* Set the CCR bit. Note for integer tests, we reverse the condition so that | |
6923 | in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR | |
6924 | bit being true. We don't do this for floating point, because of NaNs. */ | |
6925 | code = GET_CODE (true_expr); | |
6926 | if (GET_MODE (cc) != CC_FPmode) | |
6927 | { | |
6928 | code = reverse_condition (code); | |
6929 | code_true = EQ; | |
6930 | code_false = NE; | |
6931 | } | |
6932 | else | |
6933 | { | |
6934 | code_true = NE; | |
6935 | code_false = EQ; | |
6936 | } | |
6937 | ||
6938 | check_insn = gen_rtx_SET (VOIDmode, cr, | |
6939 | gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx)); | |
6940 | ||
6941 | /* Record the check insn to be inserted later. */ | |
a813c111 | 6942 | frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE); |
36a05131 BS |
6943 | |
6944 | /* Update the tests. */ | |
6945 | frv_ifcvt.cr_reg = cr; | |
6946 | frv_ifcvt.nested_cc_reg = nested_cc; | |
6947 | *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx); | |
6948 | *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx); | |
6949 | return; | |
6950 | ||
6951 | /* Fail, don't do this conditional execution. */ | |
6952 | fail: | |
6953 | *p_true = NULL_RTX; | |
6954 | *p_false = NULL_RTX; | |
c263766c RH |
6955 | if (dump_file) |
6956 | fprintf (dump_file, "Disabling this conditional execution.\n"); | |
36a05131 BS |
6957 | |
6958 | return; | |
6959 | } | |
6960 | ||
6961 | \f | |
6962 | /* A C expression to modify the code described by the conditional if | |
6963 | information CE_INFO, for the basic block BB, possibly updating the tests in | |
6964 | TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or | |
6965 | if-then-else code to conditional instructions. Set either TRUE_EXPR or | |
6966 | FALSE_EXPR to a null pointer if the tests cannot be converted. */ | |
6967 | ||
6968 | /* p_true and p_false are given expressions of the form: | |
6969 | ||
6970 | (and (eq:CC_CCR (reg:CC_CCR) | |
6971 | (const_int 0)) | |
6972 | (eq:CC (reg:CC) | |
6973 | (const_int 0))) */ | |
6974 | ||
6975 | void | |
f2206911 KC |
6976 | frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info, |
6977 | basic_block bb, | |
6978 | rtx *p_true, | |
6979 | rtx *p_false) | |
36a05131 BS |
6980 | { |
6981 | rtx old_true = XEXP (*p_true, 0); | |
6982 | rtx old_false = XEXP (*p_false, 0); | |
6983 | rtx true_expr = XEXP (*p_true, 1); | |
6984 | rtx false_expr = XEXP (*p_false, 1); | |
6985 | rtx test_expr; | |
6986 | rtx old_test; | |
6987 | rtx cr = XEXP (old_true, 0); | |
6988 | rtx check_insn; | |
6989 | rtx new_cr = NULL_RTX; | |
6990 | rtx *p_new_cr = (rtx *)0; | |
6991 | rtx if_else; | |
6992 | rtx compare; | |
6993 | rtx cc; | |
6994 | enum reg_class cr_class; | |
6995 | enum machine_mode mode = GET_MODE (true_expr); | |
6996 | rtx (*logical_func)(rtx, rtx, rtx); | |
6997 | ||
6998 | if (TARGET_DEBUG_COND_EXEC) | |
6999 | { | |
7000 | fprintf (stderr, | |
7001 | "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n", | |
7002 | ce_info->and_and_p ? "&&" : "||"); | |
7003 | ||
7004 | debug_rtx (*p_true); | |
7005 | ||
7006 | fputs ("\nfalse insn:\n", stderr); | |
7007 | debug_rtx (*p_false); | |
7008 | } | |
7009 | ||
7010 | if (TARGET_NO_MULTI_CE) | |
7011 | goto fail; | |
7012 | ||
7013 | if (GET_CODE (cr) != REG) | |
7014 | goto fail; | |
b16c1435 | 7015 | |
36a05131 BS |
7016 | if (mode == CCmode || mode == CC_UNSmode) |
7017 | { | |
7018 | cr_class = ICR_REGS; | |
7019 | p_new_cr = &frv_ifcvt.extra_int_cr; | |
7020 | } | |
7021 | else if (mode == CC_FPmode) | |
7022 | { | |
7023 | cr_class = FCR_REGS; | |
7024 | p_new_cr = &frv_ifcvt.extra_fp_cr; | |
7025 | } | |
7026 | else | |
7027 | goto fail; | |
7028 | ||
7029 | /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or | |
7030 | more &&/|| tests. */ | |
7031 | new_cr = *p_new_cr; | |
7032 | if (! new_cr) | |
7033 | { | |
7034 | new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class, | |
7035 | CC_CCRmode, TRUE, TRUE); | |
7036 | if (! new_cr) | |
7037 | goto fail; | |
7038 | } | |
7039 | ||
7040 | if (ce_info->and_and_p) | |
7041 | { | |
7042 | old_test = old_false; | |
7043 | test_expr = true_expr; | |
7044 | logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr; | |
7045 | *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx); | |
7046 | *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx); | |
7047 | } | |
7048 | else | |
7049 | { | |
7050 | old_test = old_false; | |
7051 | test_expr = false_expr; | |
7052 | logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr; | |
7053 | *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx); | |
7054 | *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx); | |
7055 | } | |
7056 | ||
7057 | /* First add the andcr/andncr/orcr/orncr, which will be added after the | |
7058 | conditional check instruction, due to frv_ifcvt_add_insn being a LIFO | |
7059 | stack. */ | |
a813c111 | 7060 | frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE); |
36a05131 BS |
7061 | |
7062 | /* Now add the conditional check insn. */ | |
7063 | cc = XEXP (test_expr, 0); | |
7064 | compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx); | |
7065 | if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx); | |
7066 | ||
7067 | check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else); | |
7068 | ||
87b483a1 | 7069 | /* Add the new check insn to the list of check insns that need to be |
36a05131 | 7070 | inserted. */ |
a813c111 | 7071 | frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE); |
36a05131 BS |
7072 | |
7073 | if (TARGET_DEBUG_COND_EXEC) | |
7074 | { | |
7075 | fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n", | |
7076 | stderr); | |
7077 | ||
7078 | debug_rtx (*p_true); | |
7079 | ||
7080 | fputs ("\nfalse insn:\n", stderr); | |
7081 | debug_rtx (*p_false); | |
7082 | } | |
7083 | ||
7084 | return; | |
7085 | ||
7086 | fail: | |
7087 | *p_true = *p_false = NULL_RTX; | |
7088 | ||
87b483a1 | 7089 | /* If we allocated a CR register, release it. */ |
36a05131 BS |
7090 | if (new_cr) |
7091 | { | |
7092 | CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr)); | |
7093 | *p_new_cr = NULL_RTX; | |
7094 | } | |
7095 | ||
7096 | if (TARGET_DEBUG_COND_EXEC) | |
7097 | fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr); | |
7098 | ||
7099 | return; | |
7100 | } | |
7101 | ||
7102 | \f | |
7103 | /* Return a register which will be loaded with a value if an IF block is | |
7104 | converted to conditional execution. This is used to rewrite instructions | |
7105 | that use constants to ones that just use registers. */ | |
7106 | ||
7107 | static rtx | |
f2206911 | 7108 | frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED) |
36a05131 BS |
7109 | { |
7110 | int num_alloc = frv_ifcvt.cur_scratch_regs; | |
7111 | int i; | |
7112 | rtx reg; | |
7113 | ||
7114 | /* We know gr0 == 0, so replace any errant uses. */ | |
7115 | if (value == const0_rtx) | |
7116 | return gen_rtx_REG (SImode, GPR_FIRST); | |
7117 | ||
7118 | /* First search all registers currently loaded to see if we have an | |
7119 | applicable constant. */ | |
7120 | if (CONSTANT_P (value) | |
7121 | || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)) | |
7122 | { | |
7123 | for (i = 0; i < num_alloc; i++) | |
7124 | { | |
7125 | if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value)) | |
7126 | return SET_DEST (frv_ifcvt.scratch_regs[i]); | |
7127 | } | |
7128 | } | |
7129 | ||
87b483a1 | 7130 | /* Have we exhausted the number of registers available? */ |
36a05131 BS |
7131 | if (num_alloc >= GPR_TEMP_NUM) |
7132 | { | |
c263766c RH |
7133 | if (dump_file) |
7134 | fprintf (dump_file, "Too many temporary registers allocated\n"); | |
36a05131 BS |
7135 | |
7136 | return NULL_RTX; | |
7137 | } | |
7138 | ||
7139 | /* Allocate the new register. */ | |
7140 | reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE); | |
7141 | if (! reg) | |
7142 | { | |
c263766c RH |
7143 | if (dump_file) |
7144 | fputs ("Could not find a scratch register\n", dump_file); | |
36a05131 BS |
7145 | |
7146 | return NULL_RTX; | |
7147 | } | |
7148 | ||
7149 | frv_ifcvt.cur_scratch_regs++; | |
7150 | frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value); | |
7151 | ||
c263766c | 7152 | if (dump_file) |
36a05131 BS |
7153 | { |
7154 | if (GET_CODE (value) == CONST_INT) | |
c263766c | 7155 | fprintf (dump_file, "Register %s will hold %ld\n", |
36a05131 BS |
7156 | reg_names[ REGNO (reg)], (long)INTVAL (value)); |
7157 | ||
7158 | else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO) | |
c263766c | 7159 | fprintf (dump_file, "Register %s will hold LR\n", |
36a05131 BS |
7160 | reg_names[ REGNO (reg)]); |
7161 | ||
7162 | else | |
c263766c | 7163 | fprintf (dump_file, "Register %s will hold a saved value\n", |
36a05131 BS |
7164 | reg_names[ REGNO (reg)]); |
7165 | } | |
7166 | ||
7167 | return reg; | |
7168 | } | |
7169 | ||
7170 | \f | |
7171 | /* Update a MEM used in conditional code that might contain an offset to put | |
7172 | the offset into a scratch register, so that the conditional load/store | |
7173 | operations can be used. This function returns the original pointer if the | |
7174 | MEM is valid to use in conditional code, NULL if we can't load up the offset | |
7175 | into a temporary register, or the new MEM if we were successful. */ | |
7176 | ||
7177 | static rtx | |
f2206911 | 7178 | frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn) |
36a05131 BS |
7179 | { |
7180 | rtx addr = XEXP (mem, 0); | |
7181 | ||
34208acf | 7182 | if (!frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE)) |
36a05131 BS |
7183 | { |
7184 | if (GET_CODE (addr) == PLUS) | |
7185 | { | |
7186 | rtx addr_op0 = XEXP (addr, 0); | |
7187 | rtx addr_op1 = XEXP (addr, 1); | |
7188 | ||
34208acf | 7189 | if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1)) |
36a05131 BS |
7190 | { |
7191 | rtx reg = frv_ifcvt_load_value (addr_op1, insn); | |
7192 | if (!reg) | |
7193 | return NULL_RTX; | |
7194 | ||
7195 | addr = gen_rtx_PLUS (Pmode, addr_op0, reg); | |
7196 | } | |
7197 | ||
7198 | else | |
7199 | return NULL_RTX; | |
7200 | } | |
7201 | ||
7202 | else if (CONSTANT_P (addr)) | |
7203 | addr = frv_ifcvt_load_value (addr, insn); | |
7204 | ||
7205 | else | |
7206 | return NULL_RTX; | |
7207 | ||
7208 | if (addr == NULL_RTX) | |
7209 | return NULL_RTX; | |
7210 | ||
7211 | else if (XEXP (mem, 0) != addr) | |
7212 | return change_address (mem, mode, addr); | |
7213 | } | |
7214 | ||
7215 | return mem; | |
7216 | } | |
7217 | ||
7218 | \f | |
7219 | /* Given a PATTERN, return a SET expression if this PATTERN has only a single | |
7220 | SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */ | |
7221 | ||
7222 | static rtx | |
f2206911 | 7223 | single_set_pattern (rtx pattern) |
36a05131 BS |
7224 | { |
7225 | rtx set; | |
7226 | int i; | |
7227 | ||
7228 | if (GET_CODE (pattern) == COND_EXEC) | |
7229 | pattern = COND_EXEC_CODE (pattern); | |
7230 | ||
7231 | if (GET_CODE (pattern) == SET) | |
7232 | return pattern; | |
7233 | ||
7234 | else if (GET_CODE (pattern) == PARALLEL) | |
7235 | { | |
7236 | for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++) | |
7237 | { | |
7238 | rtx sub = XVECEXP (pattern, 0, i); | |
7239 | ||
7240 | switch (GET_CODE (sub)) | |
7241 | { | |
7242 | case USE: | |
7243 | case CLOBBER: | |
7244 | break; | |
7245 | ||
7246 | case SET: | |
7247 | if (set) | |
7248 | return 0; | |
7249 | else | |
7250 | set = sub; | |
7251 | break; | |
7252 | ||
7253 | default: | |
7254 | return 0; | |
7255 | } | |
7256 | } | |
7257 | return set; | |
7258 | } | |
7259 | ||
7260 | return 0; | |
7261 | } | |
7262 | ||
7263 | \f | |
7264 | /* A C expression to modify the code described by the conditional if | |
7265 | information CE_INFO with the new PATTERN in INSN. If PATTERN is a null | |
7266 | pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that | |
7267 | insn cannot be converted to be executed conditionally. */ | |
7268 | ||
7269 | rtx | |
5da1fd3d | 7270 | frv_ifcvt_modify_insn (ce_if_block_t *ce_info, |
f2206911 KC |
7271 | rtx pattern, |
7272 | rtx insn) | |
36a05131 BS |
7273 | { |
7274 | rtx orig_ce_pattern = pattern; | |
7275 | rtx set; | |
7276 | rtx op0; | |
7277 | rtx op1; | |
7278 | rtx test; | |
7279 | ||
7280 | if (GET_CODE (pattern) != COND_EXEC) | |
7281 | abort (); | |
7282 | ||
7283 | test = COND_EXEC_TEST (pattern); | |
7284 | if (GET_CODE (test) == AND) | |
7285 | { | |
7286 | rtx cr = frv_ifcvt.cr_reg; | |
7287 | rtx test_reg; | |
7288 | ||
7289 | op0 = XEXP (test, 0); | |
7290 | if (! rtx_equal_p (cr, XEXP (op0, 0))) | |
7291 | goto fail; | |
7292 | ||
7293 | op1 = XEXP (test, 1); | |
7294 | test_reg = XEXP (op1, 0); | |
7295 | if (GET_CODE (test_reg) != REG) | |
7296 | goto fail; | |
7297 | ||
7298 | /* Is this the first nested if block in this sequence? If so, generate | |
7299 | an andcr or andncr. */ | |
7300 | if (! frv_ifcvt.last_nested_if_cr) | |
7301 | { | |
7302 | rtx and_op; | |
7303 | ||
7304 | frv_ifcvt.last_nested_if_cr = test_reg; | |
7305 | if (GET_CODE (op0) == NE) | |
7306 | and_op = gen_andcr (test_reg, cr, test_reg); | |
7307 | else | |
7308 | and_op = gen_andncr (test_reg, cr, test_reg); | |
7309 | ||
7310 | frv_ifcvt_add_insn (and_op, insn, TRUE); | |
7311 | } | |
7312 | ||
7313 | /* If this isn't the first statement in the nested if sequence, see if we | |
7314 | are dealing with the same register. */ | |
7315 | else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr)) | |
7316 | goto fail; | |
7317 | ||
7318 | COND_EXEC_TEST (pattern) = test = op1; | |
7319 | } | |
7320 | ||
7321 | /* If this isn't a nested if, reset state variables. */ | |
7322 | else | |
7323 | { | |
7324 | frv_ifcvt.last_nested_if_cr = NULL_RTX; | |
7325 | } | |
7326 | ||
7327 | set = single_set_pattern (pattern); | |
7328 | if (set) | |
7329 | { | |
7330 | rtx dest = SET_DEST (set); | |
7331 | rtx src = SET_SRC (set); | |
7332 | enum machine_mode mode = GET_MODE (dest); | |
7333 | ||
87b483a1 | 7334 | /* Check for normal binary operators. */ |
ec8e098d | 7335 | if (mode == SImode && ARITHMETIC_P (src)) |
36a05131 BS |
7336 | { |
7337 | op0 = XEXP (src, 0); | |
7338 | op1 = XEXP (src, 1); | |
7339 | ||
34208acf | 7340 | if (integer_register_operand (op0, SImode) && CONSTANT_P (op1)) |
36a05131 BS |
7341 | { |
7342 | op1 = frv_ifcvt_load_value (op1, insn); | |
7343 | if (op1) | |
7344 | COND_EXEC_CODE (pattern) | |
7345 | = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src), | |
7346 | GET_MODE (src), | |
7347 | op0, op1)); | |
7348 | else | |
7349 | goto fail; | |
7350 | } | |
7351 | } | |
7352 | ||
7353 | /* For multiply by a constant, we need to handle the sign extending | |
7354 | correctly. Add a USE of the value after the multiply to prevent flow | |
7355 | from cratering because only one register out of the two were used. */ | |
7356 | else if (mode == DImode && GET_CODE (src) == MULT) | |
7357 | { | |
7358 | op0 = XEXP (src, 0); | |
7359 | op1 = XEXP (src, 1); | |
7360 | if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT) | |
7361 | { | |
7362 | op1 = frv_ifcvt_load_value (op1, insn); | |
7363 | if (op1) | |
7364 | { | |
7365 | op1 = gen_rtx_SIGN_EXTEND (DImode, op1); | |
7366 | COND_EXEC_CODE (pattern) | |
7367 | = gen_rtx_SET (VOIDmode, dest, | |
7368 | gen_rtx_MULT (DImode, op0, op1)); | |
7369 | } | |
7370 | else | |
7371 | goto fail; | |
7372 | } | |
7373 | ||
7374 | frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode, dest), insn, FALSE); | |
7375 | } | |
7376 | ||
7377 | /* If we are just loading a constant created for a nested conditional | |
7378 | execution statement, just load the constant without any conditional | |
7379 | execution, since we know that the constant will not interfere with any | |
7380 | other registers. */ | |
7381 | else if (frv_ifcvt.scratch_insns_bitmap | |
7382 | && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap, | |
5da1fd3d AO |
7383 | INSN_UID (insn)) |
7384 | /* We must not unconditionally set a reg set used as | |
7385 | scratch in the THEN branch if the same reg is live | |
7386 | in the ELSE branch. */ | |
7387 | && REG_P (SET_DEST (set)) | |
7388 | && (! ce_info->else_bb | |
7389 | || BLOCK_FOR_INSN (insn) == ce_info->else_bb | |
7390 | || ! (REGNO_REG_SET_P | |
7391 | (ce_info->else_bb->global_live_at_start, | |
7392 | REGNO (SET_DEST (set)))))) | |
36a05131 BS |
7393 | pattern = set; |
7394 | ||
7395 | else if (mode == QImode || mode == HImode || mode == SImode | |
7396 | || mode == SFmode) | |
7397 | { | |
7398 | int changed_p = FALSE; | |
7399 | ||
7400 | /* Check for just loading up a constant */ | |
7401 | if (CONSTANT_P (src) && integer_register_operand (dest, mode)) | |
7402 | { | |
7403 | src = frv_ifcvt_load_value (src, insn); | |
7404 | if (!src) | |
7405 | goto fail; | |
7406 | ||
7407 | changed_p = TRUE; | |
7408 | } | |
7409 | ||
7410 | /* See if we need to fix up stores */ | |
7411 | if (GET_CODE (dest) == MEM) | |
7412 | { | |
7413 | rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn); | |
7414 | ||
7415 | if (!new_mem) | |
7416 | goto fail; | |
7417 | ||
7418 | else if (new_mem != dest) | |
7419 | { | |
7420 | changed_p = TRUE; | |
7421 | dest = new_mem; | |
7422 | } | |
7423 | } | |
7424 | ||
7425 | /* See if we need to fix up loads */ | |
7426 | if (GET_CODE (src) == MEM) | |
7427 | { | |
7428 | rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn); | |
7429 | ||
7430 | if (!new_mem) | |
7431 | goto fail; | |
7432 | ||
7433 | else if (new_mem != src) | |
7434 | { | |
7435 | changed_p = TRUE; | |
7436 | src = new_mem; | |
7437 | } | |
7438 | } | |
7439 | ||
7440 | /* If either src or destination changed, redo SET. */ | |
7441 | if (changed_p) | |
7442 | COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src); | |
7443 | } | |
7444 | ||
7445 | /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with | |
7446 | rewriting the CC register to be the same as the paired CC/CR register | |
7447 | for nested ifs. */ | |
ec8e098d | 7448 | else if (mode == CC_CCRmode && COMPARISON_P (src)) |
36a05131 BS |
7449 | { |
7450 | int regno = REGNO (XEXP (src, 0)); | |
7451 | rtx if_else; | |
7452 | ||
7453 | if (ce_info->pass > 1 | |
7454 | && regno != (int)REGNO (frv_ifcvt.nested_cc_reg) | |
7455 | && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno)) | |
7456 | { | |
7457 | src = gen_rtx_fmt_ee (GET_CODE (src), | |
7458 | CC_CCRmode, | |
7459 | frv_ifcvt.nested_cc_reg, | |
7460 | XEXP (src, 1)); | |
7461 | } | |
7462 | ||
7463 | if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx); | |
7464 | pattern = gen_rtx_SET (VOIDmode, dest, if_else); | |
7465 | } | |
7466 | ||
7467 | /* Remap a nested compare instruction to use the paired CC/CR reg. */ | |
7468 | else if (ce_info->pass > 1 | |
7469 | && GET_CODE (dest) == REG | |
7470 | && CC_P (REGNO (dest)) | |
7471 | && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg) | |
7472 | && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, | |
7473 | REGNO (dest)) | |
7474 | && GET_CODE (src) == COMPARE) | |
7475 | { | |
7476 | PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest)); | |
7477 | COND_EXEC_CODE (pattern) | |
7478 | = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src)); | |
7479 | } | |
7480 | } | |
7481 | ||
7482 | if (TARGET_DEBUG_COND_EXEC) | |
7483 | { | |
7484 | rtx orig_pattern = PATTERN (insn); | |
7485 | ||
7486 | PATTERN (insn) = pattern; | |
7487 | fprintf (stderr, | |
7488 | "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n", | |
7489 | ce_info->pass); | |
7490 | ||
7491 | debug_rtx (insn); | |
7492 | PATTERN (insn) = orig_pattern; | |
7493 | } | |
7494 | ||
7495 | return pattern; | |
7496 | ||
7497 | fail: | |
7498 | if (TARGET_DEBUG_COND_EXEC) | |
7499 | { | |
7500 | rtx orig_pattern = PATTERN (insn); | |
7501 | ||
7502 | PATTERN (insn) = orig_ce_pattern; | |
7503 | fprintf (stderr, | |
7504 | "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n", | |
7505 | ce_info->pass); | |
7506 | ||
7507 | debug_rtx (insn); | |
7508 | PATTERN (insn) = orig_pattern; | |
7509 | } | |
7510 | ||
7511 | return NULL_RTX; | |
7512 | } | |
7513 | ||
7514 | \f | |
7515 | /* A C expression to perform any final machine dependent modifications in | |
7516 | converting code to conditional execution in the code described by the | |
7517 | conditional if information CE_INFO. */ | |
7518 | ||
7519 | void | |
f2206911 | 7520 | frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED) |
36a05131 BS |
7521 | { |
7522 | rtx existing_insn; | |
7523 | rtx check_insn; | |
7524 | rtx p = frv_ifcvt.added_insns_list; | |
7525 | int i; | |
7526 | ||
7527 | /* Loop inserting the check insns. The last check insn is the first test, | |
7528 | and is the appropriate place to insert constants. */ | |
7529 | if (! p) | |
7530 | abort (); | |
7531 | ||
7532 | do | |
7533 | { | |
7534 | rtx check_and_insert_insns = XEXP (p, 0); | |
7535 | rtx old_p = p; | |
7536 | ||
7537 | check_insn = XEXP (check_and_insert_insns, 0); | |
7538 | existing_insn = XEXP (check_and_insert_insns, 1); | |
7539 | p = XEXP (p, 1); | |
7540 | ||
7541 | /* The jump bit is used to say that the new insn is to be inserted BEFORE | |
7542 | the existing insn, otherwise it is to be inserted AFTER. */ | |
7543 | if (check_and_insert_insns->jump) | |
7544 | { | |
7545 | emit_insn_before (check_insn, existing_insn); | |
7546 | check_and_insert_insns->jump = 0; | |
7547 | } | |
7548 | else | |
7549 | emit_insn_after (check_insn, existing_insn); | |
7550 | ||
7551 | free_EXPR_LIST_node (check_and_insert_insns); | |
7552 | free_EXPR_LIST_node (old_p); | |
7553 | } | |
7554 | while (p != NULL_RTX); | |
7555 | ||
7556 | /* Load up any constants needed into temp gprs */ | |
7557 | for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++) | |
7558 | { | |
7559 | rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn); | |
7560 | if (! frv_ifcvt.scratch_insns_bitmap) | |
7561 | frv_ifcvt.scratch_insns_bitmap = BITMAP_XMALLOC (); | |
7562 | bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn)); | |
7563 | frv_ifcvt.scratch_regs[i] = NULL_RTX; | |
7564 | } | |
7565 | ||
7566 | frv_ifcvt.added_insns_list = NULL_RTX; | |
7567 | frv_ifcvt.cur_scratch_regs = 0; | |
7568 | } | |
7569 | ||
7570 | \f | |
7571 | /* A C expression to cancel any machine dependent modifications in converting | |
7572 | code to conditional execution in the code described by the conditional if | |
7573 | information CE_INFO. */ | |
7574 | ||
7575 | void | |
f2206911 | 7576 | frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED) |
36a05131 BS |
7577 | { |
7578 | int i; | |
7579 | rtx p = frv_ifcvt.added_insns_list; | |
7580 | ||
7581 | /* Loop freeing up the EXPR_LIST's allocated. */ | |
7582 | while (p != NULL_RTX) | |
7583 | { | |
7584 | rtx check_and_jump = XEXP (p, 0); | |
7585 | rtx old_p = p; | |
7586 | ||
7587 | p = XEXP (p, 1); | |
7588 | free_EXPR_LIST_node (check_and_jump); | |
7589 | free_EXPR_LIST_node (old_p); | |
7590 | } | |
7591 | ||
7592 | /* Release any temporary gprs allocated. */ | |
7593 | for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++) | |
7594 | frv_ifcvt.scratch_regs[i] = NULL_RTX; | |
7595 | ||
7596 | frv_ifcvt.added_insns_list = NULL_RTX; | |
7597 | frv_ifcvt.cur_scratch_regs = 0; | |
7598 | return; | |
7599 | } | |
7600 | \f | |
7601 | /* A C expression for the size in bytes of the trampoline, as an integer. | |
7602 | The template is: | |
7603 | ||
7604 | setlo #0, <jmp_reg> | |
7605 | setlo #0, <static_chain> | |
7606 | sethi #0, <jmp_reg> | |
7607 | sethi #0, <static_chain> | |
7608 | jmpl @(gr0,<jmp_reg>) */ | |
7609 | ||
7610 | int | |
f2206911 | 7611 | frv_trampoline_size (void) |
36a05131 | 7612 | { |
34208acf AO |
7613 | if (TARGET_FDPIC) |
7614 | /* Allocate room for the function descriptor and the lddi | |
7615 | instruction. */ | |
7616 | return 8 + 6 * 4; | |
7617 | return 5 /* instructions */ * 4 /* instruction size. */; | |
36a05131 BS |
7618 | } |
7619 | ||
7620 | \f | |
7621 | /* A C statement to initialize the variable parts of a trampoline. ADDR is an | |
7622 | RTX for the address of the trampoline; FNADDR is an RTX for the address of | |
7623 | the nested function; STATIC_CHAIN is an RTX for the static chain value that | |
7624 | should be passed to the function when it is called. | |
7625 | ||
7626 | The template is: | |
7627 | ||
7628 | setlo #0, <jmp_reg> | |
7629 | setlo #0, <static_chain> | |
7630 | sethi #0, <jmp_reg> | |
7631 | sethi #0, <static_chain> | |
7632 | jmpl @(gr0,<jmp_reg>) */ | |
7633 | ||
7634 | void | |
f2206911 | 7635 | frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain) |
36a05131 BS |
7636 | { |
7637 | rtx sc_reg = force_reg (Pmode, static_chain); | |
7638 | ||
7639 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), | |
7640 | FALSE, VOIDmode, 4, | |
7641 | addr, Pmode, | |
7642 | GEN_INT (frv_trampoline_size ()), SImode, | |
7643 | fnaddr, Pmode, | |
7644 | sc_reg, Pmode); | |
7645 | } | |
7646 | ||
7647 | \f | |
7648 | /* Many machines have some registers that cannot be copied directly to or from | |
7649 | memory or even from other types of registers. An example is the `MQ' | |
7650 | register, which on most machines, can only be copied to or from general | |
7651 | registers, but not memory. Some machines allow copying all registers to and | |
7652 | from memory, but require a scratch register for stores to some memory | |
7653 | locations (e.g., those with symbolic address on the RT, and those with | |
981f6289 | 7654 | certain symbolic address on the SPARC when compiling PIC). In some cases, |
36a05131 BS |
7655 | both an intermediate and a scratch register are required. |
7656 | ||
7657 | You should define these macros to indicate to the reload phase that it may | |
7658 | need to allocate at least one register for a reload in addition to the | |
7659 | register to contain the data. Specifically, if copying X to a register | |
7660 | CLASS in MODE requires an intermediate register, you should define | |
7661 | `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of | |
7662 | whose registers can be used as intermediate registers or scratch registers. | |
7663 | ||
7664 | If copying a register CLASS in MODE to X requires an intermediate or scratch | |
7665 | register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the | |
7666 | largest register class required. If the requirements for input and output | |
7667 | reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used | |
7668 | instead of defining both macros identically. | |
7669 | ||
7670 | The values returned by these macros are often `GENERAL_REGS'. Return | |
7671 | `NO_REGS' if no spare register is needed; i.e., if X can be directly copied | |
7672 | to or from a register of CLASS in MODE without requiring a scratch register. | |
7673 | Do not define this macro if it would always return `NO_REGS'. | |
7674 | ||
7675 | If a scratch register is required (either with or without an intermediate | |
7676 | register), you should define patterns for `reload_inM' or `reload_outM', as | |
7677 | required.. These patterns, which will normally be implemented with a | |
7678 | `define_expand', should be similar to the `movM' patterns, except that | |
7679 | operand 2 is the scratch register. | |
7680 | ||
7681 | Define constraints for the reload register and scratch register that contain | |
7682 | a single register class. If the original reload register (whose class is | |
7683 | CLASS) can meet the constraint given in the pattern, the value returned by | |
7684 | these macros is used for the class of the scratch register. Otherwise, two | |
7685 | additional reload registers are required. Their classes are obtained from | |
7686 | the constraints in the insn pattern. | |
7687 | ||
7688 | X might be a pseudo-register or a `subreg' of a pseudo-register, which could | |
7689 | either be in a hard register or in memory. Use `true_regnum' to find out; | |
7690 | it will return -1 if the pseudo is in memory and the hard register number if | |
7691 | it is in a register. | |
7692 | ||
7693 | These macros should not be used in the case where a particular class of | |
7694 | registers can only be copied to memory and not to another class of | |
7695 | registers. In that case, secondary reload registers are not needed and | |
7696 | would not be helpful. Instead, a stack location must be used to perform the | |
43aa4e05 | 7697 | copy and the `movM' pattern should use memory as an intermediate storage. |
36a05131 BS |
7698 | This case often occurs between floating-point and general registers. */ |
7699 | ||
7700 | enum reg_class | |
f2206911 KC |
7701 | frv_secondary_reload_class (enum reg_class class, |
7702 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
7703 | rtx x, | |
7704 | int in_p ATTRIBUTE_UNUSED) | |
36a05131 BS |
7705 | { |
7706 | enum reg_class ret; | |
7707 | ||
7708 | switch (class) | |
7709 | { | |
7710 | default: | |
7711 | ret = NO_REGS; | |
7712 | break; | |
7713 | ||
7714 | /* Accumulators/Accumulator guard registers need to go through floating | |
7715 | point registers. */ | |
7716 | case QUAD_REGS: | |
7717 | case EVEN_REGS: | |
7718 | case GPR_REGS: | |
7719 | ret = NO_REGS; | |
7720 | if (x && GET_CODE (x) == REG) | |
7721 | { | |
7722 | int regno = REGNO (x); | |
7723 | ||
7724 | if (ACC_P (regno) || ACCG_P (regno)) | |
7725 | ret = FPR_REGS; | |
7726 | } | |
7727 | break; | |
7728 | ||
9cd10576 | 7729 | /* Nonzero constants should be loaded into an FPR through a GPR. */ |
36a05131 BS |
7730 | case QUAD_FPR_REGS: |
7731 | case FEVEN_REGS: | |
7732 | case FPR_REGS: | |
7733 | if (x && CONSTANT_P (x) && !ZERO_P (x)) | |
7734 | ret = GPR_REGS; | |
7735 | else | |
7736 | ret = NO_REGS; | |
7737 | break; | |
7738 | ||
7739 | /* All of these types need gpr registers. */ | |
7740 | case ICC_REGS: | |
7741 | case FCC_REGS: | |
7742 | case CC_REGS: | |
7743 | case ICR_REGS: | |
7744 | case FCR_REGS: | |
7745 | case CR_REGS: | |
7746 | case LCR_REG: | |
7747 | case LR_REG: | |
7748 | ret = GPR_REGS; | |
7749 | break; | |
7750 | ||
7751 | /* The accumulators need fpr registers */ | |
7752 | case ACC_REGS: | |
7753 | case EVEN_ACC_REGS: | |
7754 | case QUAD_ACC_REGS: | |
7755 | case ACCG_REGS: | |
7756 | ret = FPR_REGS; | |
7757 | break; | |
7758 | } | |
7759 | ||
7760 | return ret; | |
7761 | } | |
7762 | ||
7763 | \f | |
7764 | /* A C expression whose value is nonzero if pseudos that have been assigned to | |
7765 | registers of class CLASS would likely be spilled because registers of CLASS | |
7766 | are needed for spill registers. | |
7767 | ||
7768 | The default value of this macro returns 1 if CLASS has exactly one register | |
7769 | and zero otherwise. On most machines, this default should be used. Only | |
7770 | define this macro to some other expression if pseudo allocated by | |
7771 | `local-alloc.c' end up in memory because their hard registers were needed | |
7772 | for spill registers. If this macro returns nonzero for those classes, those | |
7773 | pseudos will only be allocated by `global.c', which knows how to reallocate | |
7774 | the pseudo to another register. If there would not be another register | |
7775 | available for reallocation, you should not change the definition of this | |
7776 | macro since the only effect of such a definition would be to slow down | |
7777 | register allocation. */ | |
7778 | ||
7779 | int | |
f2206911 | 7780 | frv_class_likely_spilled_p (enum reg_class class) |
36a05131 BS |
7781 | { |
7782 | switch (class) | |
7783 | { | |
7784 | default: | |
7785 | break; | |
7786 | ||
7787 | case ICC_REGS: | |
7788 | case FCC_REGS: | |
7789 | case CC_REGS: | |
7790 | case ICR_REGS: | |
7791 | case FCR_REGS: | |
7792 | case CR_REGS: | |
7793 | case LCR_REG: | |
7794 | case LR_REG: | |
7795 | case SPR_REGS: | |
7796 | case QUAD_ACC_REGS: | |
7797 | case EVEN_ACC_REGS: | |
7798 | case ACC_REGS: | |
7799 | case ACCG_REGS: | |
7800 | return TRUE; | |
7801 | } | |
7802 | ||
7803 | return FALSE; | |
7804 | } | |
7805 | ||
7806 | \f | |
7807 | /* An expression for the alignment of a structure field FIELD if the | |
7ec022b2 | 7808 | alignment computed in the usual way is COMPUTED. GCC uses this |
36a05131 BS |
7809 | value instead of the value in `BIGGEST_ALIGNMENT' or |
7810 | `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */ | |
7811 | ||
7812 | /* The definition type of the bit field data is either char, short, long or | |
7813 | long long. The maximum bit size is the number of bits of its own type. | |
7814 | ||
7815 | The bit field data is assigned to a storage unit that has an adequate size | |
7816 | for bit field data retention and is located at the smallest address. | |
7817 | ||
7818 | Consecutive bit field data are packed at consecutive bits having the same | |
7819 | storage unit, with regard to the type, beginning with the MSB and continuing | |
7820 | toward the LSB. | |
7821 | ||
7822 | If a field to be assigned lies over a bit field type boundary, its | |
7823 | assignment is completed by aligning it with a boundary suitable for the | |
7824 | type. | |
7825 | ||
7826 | When a bit field having a bit length of 0 is declared, it is forcibly | |
7827 | assigned to the next storage unit. | |
7828 | ||
7829 | e.g) | |
7830 | struct { | |
7831 | int a:2; | |
7832 | int b:6; | |
7833 | char c:4; | |
7834 | int d:10; | |
7835 | int :0; | |
7836 | int f:2; | |
7837 | } x; | |
7838 | ||
7839 | +0 +1 +2 +3 | |
7840 | &x 00000000 00000000 00000000 00000000 | |
7841 | MLM----L | |
7842 | a b | |
7843 | &x+4 00000000 00000000 00000000 00000000 | |
7844 | M--L | |
7845 | c | |
7846 | &x+8 00000000 00000000 00000000 00000000 | |
7847 | M----------L | |
7848 | d | |
7849 | &x+12 00000000 00000000 00000000 00000000 | |
7850 | ML | |
7851 | f | |
7852 | */ | |
7853 | ||
7854 | int | |
f2206911 | 7855 | frv_adjust_field_align (tree field, int computed) |
36a05131 | 7856 | { |
b16c1435 EC |
7857 | /* Make sure that the bitfield is not wider than the type. */ |
7858 | if (DECL_BIT_FIELD (field) | |
25f93e18 | 7859 | && !DECL_ARTIFICIAL (field)) |
36a05131 BS |
7860 | { |
7861 | tree parent = DECL_CONTEXT (field); | |
7862 | tree prev = NULL_TREE; | |
7863 | tree cur; | |
7864 | ||
36a05131 BS |
7865 | for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur)) |
7866 | { | |
7867 | if (TREE_CODE (cur) != FIELD_DECL) | |
7868 | continue; | |
7869 | ||
7870 | prev = cur; | |
7871 | } | |
7872 | ||
7873 | if (!cur) | |
7874 | abort (); | |
7875 | ||
7876 | /* If this isn't a :0 field and if the previous element is a bitfield | |
7877 | also, see if the type is different, if so, we will need to align the | |
87b483a1 | 7878 | bit-field to the next boundary. */ |
36a05131 BS |
7879 | if (prev |
7880 | && ! DECL_PACKED (field) | |
7881 | && ! integer_zerop (DECL_SIZE (field)) | |
7882 | && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev)) | |
7883 | { | |
7884 | int prev_align = TYPE_ALIGN (TREE_TYPE (prev)); | |
7885 | int cur_align = TYPE_ALIGN (TREE_TYPE (field)); | |
7886 | computed = (prev_align > cur_align) ? prev_align : cur_align; | |
7887 | } | |
7888 | } | |
7889 | ||
7890 | return computed; | |
7891 | } | |
7892 | ||
7893 | \f | |
7894 | /* A C expression that is nonzero if it is permissible to store a value of mode | |
7895 | MODE in hard register number REGNO (or in several registers starting with | |
7896 | that one). For a machine where all registers are equivalent, a suitable | |
7897 | definition is | |
7898 | ||
7899 | #define HARD_REGNO_MODE_OK(REGNO, MODE) 1 | |
7900 | ||
7901 | It is not necessary for this macro to check for the numbers of fixed | |
7902 | registers, because the allocation mechanism considers them to be always | |
7903 | occupied. | |
7904 | ||
7905 | On some machines, double-precision values must be kept in even/odd register | |
7906 | pairs. The way to implement that is to define this macro to reject odd | |
7907 | register numbers for such modes. | |
7908 | ||
7909 | The minimum requirement for a mode to be OK in a register is that the | |
7910 | `movMODE' instruction pattern support moves between the register and any | |
7911 | other hard register for which the mode is OK; and that moving a value into | |
7912 | the register and back out not alter it. | |
7913 | ||
7914 | Since the same instruction used to move `SImode' will work for all narrower | |
7915 | integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK' | |
7916 | to distinguish between these modes, provided you define patterns `movhi', | |
7917 | etc., to take advantage of this. This is useful because of the interaction | |
7918 | between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for | |
7919 | all integer modes to be tieable. | |
7920 | ||
7921 | Many machines have special registers for floating point arithmetic. Often | |
7922 | people assume that floating point machine modes are allowed only in floating | |
7923 | point registers. This is not true. Any registers that can hold integers | |
7924 | can safely *hold* a floating point machine mode, whether or not floating | |
7925 | arithmetic can be done on it in those registers. Integer move instructions | |
7926 | can be used to move the values. | |
7927 | ||
7928 | On some machines, though, the converse is true: fixed-point machine modes | |
7929 | may not go in floating registers. This is true if the floating registers | |
7930 | normalize any value stored in them, because storing a non-floating value | |
7931 | there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject | |
7932 | fixed-point machine modes in floating registers. But if the floating | |
7933 | registers do not automatically normalize, if you can store any bit pattern | |
7934 | in one and retrieve it unchanged without a trap, then any machine mode may | |
7935 | go in a floating register, so you can define this macro to say so. | |
7936 | ||
7937 | The primary significance of special floating registers is rather that they | |
7938 | are the registers acceptable in floating point arithmetic instructions. | |
7939 | However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by | |
7940 | writing the proper constraints for those instructions. | |
7941 | ||
7942 | On some machines, the floating registers are especially slow to access, so | |
7943 | that it is better to store a value in a stack frame than in such a register | |
7944 | if floating point arithmetic is not being done. As long as the floating | |
7945 | registers are not in class `GENERAL_REGS', they will not be used unless some | |
7946 | pattern's constraint asks for one. */ | |
7947 | ||
7948 | int | |
f2206911 | 7949 | frv_hard_regno_mode_ok (int regno, enum machine_mode mode) |
36a05131 BS |
7950 | { |
7951 | int base; | |
7952 | int mask; | |
7953 | ||
7954 | switch (mode) | |
7955 | { | |
7956 | case CCmode: | |
7957 | case CC_UNSmode: | |
7958 | return ICC_P (regno) || GPR_P (regno); | |
7959 | ||
7960 | case CC_CCRmode: | |
7961 | return CR_P (regno) || GPR_P (regno); | |
7962 | ||
7963 | case CC_FPmode: | |
7964 | return FCC_P (regno) || GPR_P (regno); | |
7965 | ||
7966 | default: | |
7967 | break; | |
7968 | } | |
7969 | ||
7970 | /* Set BASE to the first register in REGNO's class. Set MASK to the | |
7971 | bits that must be clear in (REGNO - BASE) for the register to be | |
7972 | well-aligned. */ | |
7973 | if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode)) | |
7974 | { | |
7975 | if (ACCG_P (regno)) | |
7976 | { | |
7977 | /* ACCGs store one byte. Two-byte quantities must start in | |
7978 | even-numbered registers, four-byte ones in registers whose | |
7979 | numbers are divisible by four, and so on. */ | |
7980 | base = ACCG_FIRST; | |
7981 | mask = GET_MODE_SIZE (mode) - 1; | |
7982 | } | |
7983 | else | |
7984 | { | |
b16c1435 EC |
7985 | /* The other registers store one word. */ |
7986 | if (GPR_P (regno) || regno == AP_FIRST) | |
36a05131 BS |
7987 | base = GPR_FIRST; |
7988 | ||
7989 | else if (FPR_P (regno)) | |
7990 | base = FPR_FIRST; | |
7991 | ||
7992 | else if (ACC_P (regno)) | |
7993 | base = ACC_FIRST; | |
7994 | ||
b16c1435 EC |
7995 | else if (SPR_P (regno)) |
7996 | return mode == SImode; | |
7997 | ||
87b483a1 | 7998 | /* Fill in the table. */ |
36a05131 BS |
7999 | else |
8000 | return 0; | |
8001 | ||
8002 | /* Anything smaller than an SI is OK in any word-sized register. */ | |
8003 | if (GET_MODE_SIZE (mode) < 4) | |
8004 | return 1; | |
8005 | ||
8006 | mask = (GET_MODE_SIZE (mode) / 4) - 1; | |
8007 | } | |
8008 | return (((regno - base) & mask) == 0); | |
8009 | } | |
8010 | ||
8011 | return 0; | |
8012 | } | |
8013 | ||
8014 | \f | |
8015 | /* A C expression for the number of consecutive hard registers, starting at | |
8016 | register number REGNO, required to hold a value of mode MODE. | |
8017 | ||
8018 | On a machine where all registers are exactly one word, a suitable definition | |
8019 | of this macro is | |
8020 | ||
8021 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
8022 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \ | |
8023 | / UNITS_PER_WORD)) */ | |
8024 | ||
8025 | /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so | |
8026 | that we can build the appropriate instructions to properly reload the | |
8027 | values. Also, make the byte-sized accumulator guards use one guard | |
8028 | for each byte. */ | |
8029 | ||
8030 | int | |
f2206911 | 8031 | frv_hard_regno_nregs (int regno, enum machine_mode mode) |
36a05131 BS |
8032 | { |
8033 | if (ACCG_P (regno)) | |
8034 | return GET_MODE_SIZE (mode); | |
8035 | else | |
8036 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
8037 | } | |
8038 | ||
8039 | \f | |
8040 | /* A C expression for the maximum number of consecutive registers of | |
8041 | class CLASS needed to hold a value of mode MODE. | |
8042 | ||
8043 | This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value | |
8044 | of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of | |
8045 | `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS. | |
8046 | ||
8047 | This macro helps control the handling of multiple-word values in | |
8048 | the reload pass. | |
8049 | ||
8050 | This declaration is required. */ | |
8051 | ||
8052 | int | |
f2206911 | 8053 | frv_class_max_nregs (enum reg_class class, enum machine_mode mode) |
36a05131 BS |
8054 | { |
8055 | if (class == ACCG_REGS) | |
8056 | /* An N-byte value requires N accumulator guards. */ | |
8057 | return GET_MODE_SIZE (mode); | |
8058 | else | |
8059 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
8060 | } | |
8061 | ||
8062 | \f | |
8063 | /* A C expression that is nonzero if X is a legitimate constant for an | |
8064 | immediate operand on the target machine. You can assume that X satisfies | |
8065 | `CONSTANT_P', so you need not check this. In fact, `1' is a suitable | |
8066 | definition for this macro on machines where anything `CONSTANT_P' is valid. */ | |
8067 | ||
8068 | int | |
f2206911 | 8069 | frv_legitimate_constant_p (rtx x) |
36a05131 BS |
8070 | { |
8071 | enum machine_mode mode = GET_MODE (x); | |
8072 | ||
34208acf AO |
8073 | /* frv_cannot_force_const_mem always returns true for FDPIC. This |
8074 | means that the move expanders will be expected to deal with most | |
8075 | kinds of constant, regardless of what we return here. | |
8076 | ||
8077 | However, among its other duties, LEGITIMATE_CONSTANT_P decides whether | |
8078 | a constant can be entered into reg_equiv_constant[]. If we return true, | |
8079 | reload can create new instances of the constant whenever it likes. | |
8080 | ||
8081 | The idea is therefore to accept as many constants as possible (to give | |
8082 | reload more freedom) while rejecting constants that can only be created | |
8083 | at certain times. In particular, anything with a symbolic component will | |
8084 | require use of the pseudo FDPIC register, which is only available before | |
8085 | reload. */ | |
8086 | if (TARGET_FDPIC) | |
8087 | return LEGITIMATE_PIC_OPERAND_P (x); | |
8088 | ||
87b483a1 | 8089 | /* All of the integer constants are ok. */ |
36a05131 BS |
8090 | if (GET_CODE (x) != CONST_DOUBLE) |
8091 | return TRUE; | |
8092 | ||
87b483a1 | 8093 | /* double integer constants are ok. */ |
36a05131 BS |
8094 | if (mode == VOIDmode || mode == DImode) |
8095 | return TRUE; | |
8096 | ||
87b483a1 | 8097 | /* 0 is always ok. */ |
36a05131 BS |
8098 | if (x == CONST0_RTX (mode)) |
8099 | return TRUE; | |
8100 | ||
8101 | /* If floating point is just emulated, allow any constant, since it will be | |
87b483a1 | 8102 | constructed in the GPRs. */ |
36a05131 BS |
8103 | if (!TARGET_HAS_FPRS) |
8104 | return TRUE; | |
8105 | ||
8106 | if (mode == DFmode && !TARGET_DOUBLE) | |
8107 | return TRUE; | |
8108 | ||
8109 | /* Otherwise store the constant away and do a load. */ | |
8110 | return FALSE; | |
8111 | } | |
8112 | \f | |
8113 | /* A C expression for the cost of moving data from a register in class FROM to | |
8114 | one in class TO. The classes are expressed using the enumeration values | |
8115 | such as `GENERAL_REGS'. A value of 4 is the default; other values are | |
8116 | interpreted relative to that. | |
8117 | ||
8118 | It is not required that the cost always equal 2 when FROM is the same as TO; | |
8119 | on some machines it is expensive to move between registers if they are not | |
8120 | general registers. | |
8121 | ||
8122 | If reload sees an insn consisting of a single `set' between two hard | |
8123 | registers, and if `REGISTER_MOVE_COST' applied to their classes returns a | |
8124 | value of 2, reload does not check to ensure that the constraints of the insn | |
8125 | are met. Setting a cost of other than 2 will allow reload to verify that | |
8126 | the constraints are met. You should do this if the `movM' pattern's | |
8127 | constraints do not allow such copying. */ | |
8128 | ||
8129 | #define HIGH_COST 40 | |
8130 | #define MEDIUM_COST 3 | |
8131 | #define LOW_COST 1 | |
8132 | ||
8133 | int | |
f2206911 | 8134 | frv_register_move_cost (enum reg_class from, enum reg_class to) |
36a05131 BS |
8135 | { |
8136 | switch (from) | |
8137 | { | |
8138 | default: | |
8139 | break; | |
8140 | ||
8141 | case QUAD_REGS: | |
8142 | case EVEN_REGS: | |
8143 | case GPR_REGS: | |
8144 | switch (to) | |
8145 | { | |
8146 | default: | |
8147 | break; | |
8148 | ||
8149 | case QUAD_REGS: | |
8150 | case EVEN_REGS: | |
8151 | case GPR_REGS: | |
8152 | return LOW_COST; | |
8153 | ||
8154 | case FEVEN_REGS: | |
8155 | case FPR_REGS: | |
8156 | return LOW_COST; | |
8157 | ||
8158 | case LCR_REG: | |
8159 | case LR_REG: | |
8160 | case SPR_REGS: | |
8161 | return LOW_COST; | |
8162 | } | |
8163 | ||
8164 | case FEVEN_REGS: | |
8165 | case FPR_REGS: | |
8166 | switch (to) | |
8167 | { | |
8168 | default: | |
8169 | break; | |
8170 | ||
8171 | case QUAD_REGS: | |
8172 | case EVEN_REGS: | |
8173 | case GPR_REGS: | |
8174 | case ACC_REGS: | |
8175 | case EVEN_ACC_REGS: | |
8176 | case QUAD_ACC_REGS: | |
8177 | case ACCG_REGS: | |
8178 | return MEDIUM_COST; | |
8179 | ||
8180 | case FEVEN_REGS: | |
8181 | case FPR_REGS: | |
8182 | return LOW_COST; | |
8183 | } | |
8184 | ||
8185 | case LCR_REG: | |
8186 | case LR_REG: | |
8187 | case SPR_REGS: | |
8188 | switch (to) | |
8189 | { | |
8190 | default: | |
8191 | break; | |
8192 | ||
8193 | case QUAD_REGS: | |
8194 | case EVEN_REGS: | |
8195 | case GPR_REGS: | |
8196 | return MEDIUM_COST; | |
8197 | } | |
8198 | ||
8199 | case ACC_REGS: | |
8200 | case EVEN_ACC_REGS: | |
8201 | case QUAD_ACC_REGS: | |
8202 | case ACCG_REGS: | |
8203 | switch (to) | |
8204 | { | |
8205 | default: | |
8206 | break; | |
8207 | ||
8208 | case FEVEN_REGS: | |
8209 | case FPR_REGS: | |
8210 | return MEDIUM_COST; | |
8211 | ||
8212 | } | |
8213 | } | |
8214 | ||
8215 | return HIGH_COST; | |
8216 | } | |
8217 | \f | |
8218 | /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to | |
8219 | use ".picptr" to generate safe relocations for PIC code. We also | |
8220 | need a fixup entry for aligned (non-debugging) code. */ | |
8221 | ||
8222 | static bool | |
f2206911 | 8223 | frv_assemble_integer (rtx value, unsigned int size, int aligned_p) |
36a05131 | 8224 | { |
34208acf | 8225 | if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD) |
36a05131 BS |
8226 | { |
8227 | if (GET_CODE (value) == CONST | |
8228 | || GET_CODE (value) == SYMBOL_REF | |
8229 | || GET_CODE (value) == LABEL_REF) | |
8230 | { | |
34208acf AO |
8231 | if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF |
8232 | && SYMBOL_REF_FUNCTION_P (value)) | |
8233 | { | |
8234 | fputs ("\t.picptr\tfuncdesc(", asm_out_file); | |
8235 | output_addr_const (asm_out_file, value); | |
8236 | fputs (")\n", asm_out_file); | |
8237 | return true; | |
8238 | } | |
8239 | else if (TARGET_FDPIC && GET_CODE (value) == CONST | |
8240 | && frv_function_symbol_referenced_p (value)) | |
8241 | return false; | |
8242 | if (aligned_p && !TARGET_FDPIC) | |
36a05131 BS |
8243 | { |
8244 | static int label_num = 0; | |
8245 | char buf[256]; | |
8246 | const char *p; | |
8247 | ||
8248 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++); | |
14966b94 | 8249 | p = (* targetm.strip_name_encoding) (buf); |
36a05131 BS |
8250 | |
8251 | fprintf (asm_out_file, "%s:\n", p); | |
8252 | fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP); | |
8253 | fprintf (asm_out_file, "\t.picptr\t%s\n", p); | |
8254 | fprintf (asm_out_file, "\t.previous\n"); | |
8255 | } | |
8256 | assemble_integer_with_op ("\t.picptr\t", value); | |
8257 | return true; | |
8258 | } | |
8259 | if (!aligned_p) | |
8260 | { | |
8261 | /* We've set the unaligned SI op to NULL, so we always have to | |
8262 | handle the unaligned case here. */ | |
8263 | assemble_integer_with_op ("\t.4byte\t", value); | |
8264 | return true; | |
8265 | } | |
8266 | } | |
8267 | return default_assemble_integer (value, size, aligned_p); | |
8268 | } | |
8269 | ||
8270 | /* Function to set up the backend function structure. */ | |
8271 | ||
8272 | static struct machine_function * | |
f2206911 | 8273 | frv_init_machine_status (void) |
36a05131 BS |
8274 | { |
8275 | return ggc_alloc_cleared (sizeof (struct machine_function)); | |
8276 | } | |
ffb344c1 | 8277 | \f |
28a60850 RS |
8278 | /* Implement TARGET_SCHED_ISSUE_RATE. */ |
8279 | ||
c557edf4 | 8280 | int |
28a60850 RS |
8281 | frv_issue_rate (void) |
8282 | { | |
8283 | if (!TARGET_PACK) | |
8284 | return 1; | |
8285 | ||
8286 | switch (frv_cpu_type) | |
8287 | { | |
8288 | default: | |
8289 | case FRV_CPU_FR300: | |
8290 | case FRV_CPU_SIMPLE: | |
8291 | return 1; | |
8292 | ||
8293 | case FRV_CPU_FR400: | |
c557edf4 RS |
8294 | case FRV_CPU_FR405: |
8295 | case FRV_CPU_FR450: | |
28a60850 RS |
8296 | return 2; |
8297 | ||
8298 | case FRV_CPU_GENERIC: | |
8299 | case FRV_CPU_FR500: | |
8300 | case FRV_CPU_TOMCAT: | |
8301 | return 4; | |
c557edf4 RS |
8302 | |
8303 | case FRV_CPU_FR550: | |
8304 | return 8; | |
28a60850 RS |
8305 | } |
8306 | } | |
36a05131 | 8307 | \f |
c557edf4 RS |
8308 | /* A for_each_rtx callback. If X refers to an accumulator, return |
8309 | ACC_GROUP_ODD if the bit 2 of the register number is set and | |
8310 | ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE) | |
8311 | otherwise. */ | |
36a05131 | 8312 | |
c557edf4 RS |
8313 | static int |
8314 | frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED) | |
36a05131 | 8315 | { |
c557edf4 | 8316 | if (REG_P (*x)) |
36a05131 | 8317 | { |
c557edf4 RS |
8318 | if (ACC_P (REGNO (*x))) |
8319 | return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN; | |
8320 | if (ACCG_P (REGNO (*x))) | |
8321 | return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN; | |
8322 | } | |
8323 | return 0; | |
8324 | } | |
36a05131 | 8325 | |
c557edf4 | 8326 | /* Return the value of INSN's acc_group attribute. */ |
36a05131 | 8327 | |
c557edf4 RS |
8328 | int |
8329 | frv_acc_group (rtx insn) | |
8330 | { | |
8331 | /* This distinction only applies to the FR550 packing constraints. */ | |
8332 | if (frv_cpu_type != FRV_CPU_FR550) | |
8333 | return ACC_GROUP_NONE; | |
8334 | return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0); | |
8335 | } | |
36a05131 | 8336 | |
c557edf4 RS |
8337 | /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction |
8338 | INSN will try to claim first. Since this value depends only on the | |
8339 | type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */ | |
36a05131 | 8340 | |
c557edf4 RS |
8341 | static unsigned int |
8342 | frv_insn_unit (rtx insn) | |
8343 | { | |
8344 | enum attr_type type; | |
36a05131 | 8345 | |
c557edf4 RS |
8346 | type = get_attr_type (insn); |
8347 | if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes)) | |
8348 | { | |
8349 | /* We haven't seen this type of instruction before. */ | |
8350 | state_t state; | |
8351 | unsigned int unit; | |
36a05131 | 8352 | |
c557edf4 RS |
8353 | /* Issue the instruction on its own to see which unit it prefers. */ |
8354 | state = alloca (state_size ()); | |
8355 | state_reset (state); | |
8356 | state_transition (state, insn); | |
36a05131 | 8357 | |
c557edf4 RS |
8358 | /* Find out which unit was taken. */ |
8359 | for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++) | |
8360 | if (cpu_unit_reservation_p (state, frv_unit_codes[unit])) | |
8361 | break; | |
36a05131 | 8362 | |
c557edf4 RS |
8363 | if (unit == ARRAY_SIZE (frv_unit_codes)) |
8364 | abort (); | |
36a05131 | 8365 | |
c557edf4 | 8366 | frv_type_to_unit[type] = unit; |
36a05131 | 8367 | } |
c557edf4 RS |
8368 | return frv_type_to_unit[type]; |
8369 | } | |
36a05131 | 8370 | |
c557edf4 | 8371 | /* Return true if INSN issues to a branch unit. */ |
36a05131 | 8372 | |
c557edf4 RS |
8373 | static bool |
8374 | frv_issues_to_branch_unit_p (rtx insn) | |
8375 | { | |
8376 | return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B; | |
8377 | } | |
8378 | \f | |
8379 | /* The current state of the packing pass, implemented by frv_pack_insns. */ | |
8380 | static struct { | |
8381 | /* The state of the pipeline DFA. */ | |
8382 | state_t dfa_state; | |
8383 | ||
8384 | /* Which hardware registers are set within the current packet, | |
8385 | and the conditions under which they are set. */ | |
8386 | regstate_t regstate[FIRST_PSEUDO_REGISTER]; | |
8387 | ||
8388 | /* The memory locations that have been modified so far in this | |
8389 | packet. MEM is the memref and COND is the regstate_t condition | |
8390 | under which it is set. */ | |
8391 | struct { | |
8392 | rtx mem; | |
8393 | regstate_t cond; | |
8394 | } mems[2]; | |
8395 | ||
8396 | /* The number of valid entries in MEMS. The value is larger than | |
8397 | ARRAY_SIZE (mems) if there were too many mems to record. */ | |
8398 | unsigned int num_mems; | |
8399 | ||
8400 | /* The maximum number of instructions that can be packed together. */ | |
8401 | unsigned int issue_rate; | |
8402 | ||
8403 | /* The instructions in the packet, partitioned into groups. */ | |
8404 | struct frv_packet_group { | |
8405 | /* How many instructions in the packet belong to this group. */ | |
8406 | unsigned int num_insns; | |
8407 | ||
8408 | /* A list of the instructions that belong to this group, in the order | |
8409 | they appear in the rtl stream. */ | |
8410 | rtx insns[ARRAY_SIZE (frv_unit_codes)]; | |
8411 | ||
8412 | /* The contents of INSNS after they have been sorted into the correct | |
8413 | assembly-language order. Element X issues to unit X. The list may | |
8414 | contain extra nops. */ | |
8415 | rtx sorted[ARRAY_SIZE (frv_unit_codes)]; | |
8416 | ||
8417 | /* The member of frv_nops[] to use in sorted[]. */ | |
8418 | rtx nop; | |
8419 | } groups[NUM_GROUPS]; | |
8420 | ||
8421 | /* The instructions that make up the current packet. */ | |
8422 | rtx insns[ARRAY_SIZE (frv_unit_codes)]; | |
8423 | unsigned int num_insns; | |
8424 | } frv_packet; | |
8425 | ||
8426 | /* Return the regstate_t flags for the given COND_EXEC condition. | |
8427 | Abort if the condition isn't in the right form. */ | |
36a05131 | 8428 | |
c557edf4 RS |
8429 | static int |
8430 | frv_cond_flags (rtx cond) | |
8431 | { | |
8432 | if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE) | |
8433 | && GET_CODE (XEXP (cond, 0)) == REG | |
8434 | && CR_P (REGNO (XEXP (cond, 0))) | |
8435 | && XEXP (cond, 1) == const0_rtx) | |
8436 | return ((REGNO (XEXP (cond, 0)) - CR_FIRST) | |
8437 | | (GET_CODE (cond) == NE | |
8438 | ? REGSTATE_IF_TRUE | |
8439 | : REGSTATE_IF_FALSE)); | |
8440 | abort (); | |
8441 | } | |
36a05131 | 8442 | |
36a05131 | 8443 | |
c557edf4 RS |
8444 | /* Return true if something accessed under condition COND2 can |
8445 | conflict with something written under condition COND1. */ | |
36a05131 | 8446 | |
c557edf4 RS |
8447 | static bool |
8448 | frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2) | |
8449 | { | |
8450 | /* If either reference was unconditional, we have a conflict. */ | |
8451 | if ((cond1 & REGSTATE_IF_EITHER) == 0 | |
8452 | || (cond2 & REGSTATE_IF_EITHER) == 0) | |
8453 | return true; | |
8454 | ||
8455 | /* The references might conflict if they were controlled by | |
8456 | different CRs. */ | |
8457 | if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK)) | |
8458 | return true; | |
8459 | ||
8460 | /* They definitely conflict if they are controlled by the | |
8461 | same condition. */ | |
8462 | if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0) | |
8463 | return true; | |
8464 | ||
8465 | return false; | |
36a05131 BS |
8466 | } |
8467 | ||
c557edf4 RS |
8468 | |
8469 | /* A for_each_rtx callback. Return 1 if *X depends on an instruction in | |
8470 | the current packet. DATA points to a regstate_t that describes the | |
8471 | condition under which *X might be set or used. */ | |
36a05131 BS |
8472 | |
8473 | static int | |
c557edf4 | 8474 | frv_registers_conflict_p_1 (rtx *x, void *data) |
36a05131 | 8475 | { |
c557edf4 RS |
8476 | unsigned int regno, i; |
8477 | regstate_t cond; | |
36a05131 | 8478 | |
c557edf4 | 8479 | cond = *(regstate_t *) data; |
36a05131 | 8480 | |
c557edf4 RS |
8481 | if (GET_CODE (*x) == REG) |
8482 | FOR_EACH_REGNO (regno, *x) | |
8483 | if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0) | |
8484 | if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond)) | |
8485 | return 1; | |
36a05131 | 8486 | |
c557edf4 RS |
8487 | if (GET_CODE (*x) == MEM) |
8488 | { | |
8489 | /* If we ran out of memory slots, assume a conflict. */ | |
8490 | if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems)) | |
8491 | return 1; | |
36a05131 | 8492 | |
c557edf4 RS |
8493 | /* Check for output or true dependencies with earlier MEMs. */ |
8494 | for (i = 0; i < frv_packet.num_mems; i++) | |
8495 | if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond)) | |
8496 | { | |
8497 | if (true_dependence (frv_packet.mems[i].mem, VOIDmode, | |
8498 | *x, rtx_varies_p)) | |
8499 | return 1; | |
36a05131 | 8500 | |
c557edf4 RS |
8501 | if (output_dependence (frv_packet.mems[i].mem, *x)) |
8502 | return 1; | |
8503 | } | |
8504 | } | |
36a05131 | 8505 | |
c557edf4 RS |
8506 | /* The return values of calls aren't significant: they describe |
8507 | the effect of the call as a whole, not of the insn itself. */ | |
8508 | if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL) | |
8509 | { | |
8510 | if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data)) | |
8511 | return 1; | |
8512 | return -1; | |
8513 | } | |
36a05131 | 8514 | |
c557edf4 RS |
8515 | /* Check subexpressions. */ |
8516 | return 0; | |
8517 | } | |
36a05131 | 8518 | |
36a05131 | 8519 | |
c557edf4 RS |
8520 | /* Return true if something in X might depend on an instruction |
8521 | in the current packet. */ | |
36a05131 | 8522 | |
c557edf4 RS |
8523 | static bool |
8524 | frv_registers_conflict_p (rtx x) | |
8525 | { | |
8526 | regstate_t flags; | |
36a05131 | 8527 | |
c557edf4 RS |
8528 | flags = 0; |
8529 | if (GET_CODE (x) == COND_EXEC) | |
8530 | { | |
8531 | if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags)) | |
8532 | return true; | |
36a05131 | 8533 | |
c557edf4 RS |
8534 | flags |= frv_cond_flags (XEXP (x, 0)); |
8535 | x = XEXP (x, 1); | |
36a05131 | 8536 | } |
c557edf4 RS |
8537 | return for_each_rtx (&x, frv_registers_conflict_p_1, &flags); |
8538 | } | |
36a05131 BS |
8539 | |
8540 | ||
c557edf4 RS |
8541 | /* A note_stores callback. DATA points to the regstate_t condition |
8542 | under which X is modified. Update FRV_PACKET accordingly. */ | |
36a05131 | 8543 | |
c557edf4 RS |
8544 | static void |
8545 | frv_registers_update_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data) | |
8546 | { | |
8547 | unsigned int regno; | |
8548 | ||
8549 | if (GET_CODE (x) == REG) | |
8550 | FOR_EACH_REGNO (regno, x) | |
8551 | frv_packet.regstate[regno] |= *(regstate_t *) data; | |
8552 | ||
8553 | if (GET_CODE (x) == MEM) | |
36a05131 | 8554 | { |
c557edf4 | 8555 | if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems)) |
36a05131 | 8556 | { |
c557edf4 RS |
8557 | frv_packet.mems[frv_packet.num_mems].mem = x; |
8558 | frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data; | |
8559 | } | |
8560 | frv_packet.num_mems++; | |
8561 | } | |
8562 | } | |
36a05131 | 8563 | |
36a05131 | 8564 | |
c557edf4 RS |
8565 | /* Update the register state information for an instruction whose |
8566 | body is X. */ | |
8567 | ||
8568 | static void | |
8569 | frv_registers_update (rtx x) | |
8570 | { | |
8571 | regstate_t flags; | |
8572 | ||
8573 | flags = REGSTATE_MODIFIED; | |
8574 | if (GET_CODE (x) == COND_EXEC) | |
8575 | { | |
8576 | flags |= frv_cond_flags (XEXP (x, 0)); | |
8577 | x = XEXP (x, 1); | |
36a05131 | 8578 | } |
c557edf4 RS |
8579 | note_stores (x, frv_registers_update_1, &flags); |
8580 | } | |
36a05131 | 8581 | |
c557edf4 RS |
8582 | |
8583 | /* Initialize frv_packet for the start of a new packet. */ | |
8584 | ||
8585 | static void | |
8586 | frv_start_packet (void) | |
8587 | { | |
8588 | enum frv_insn_group group; | |
8589 | ||
8590 | memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate)); | |
8591 | frv_packet.num_mems = 0; | |
8592 | frv_packet.num_insns = 0; | |
8593 | for (group = 0; group < NUM_GROUPS; group++) | |
8594 | frv_packet.groups[group].num_insns = 0; | |
36a05131 BS |
8595 | } |
8596 | ||
36a05131 | 8597 | |
c557edf4 RS |
8598 | /* Likewise for the start of a new basic block. */ |
8599 | ||
8600 | static void | |
8601 | frv_start_packet_block (void) | |
36a05131 | 8602 | { |
c557edf4 RS |
8603 | state_reset (frv_packet.dfa_state); |
8604 | frv_start_packet (); | |
8605 | } | |
36a05131 | 8606 | |
c557edf4 RS |
8607 | |
8608 | /* Finish the current packet, if any, and start a new one. Call | |
8609 | HANDLE_PACKET with FRV_PACKET describing the completed packet. */ | |
8610 | ||
8611 | static void | |
8612 | frv_finish_packet (void (*handle_packet) (void)) | |
8613 | { | |
8614 | if (frv_packet.num_insns > 0) | |
36a05131 | 8615 | { |
c557edf4 RS |
8616 | handle_packet (); |
8617 | state_transition (frv_packet.dfa_state, 0); | |
8618 | frv_start_packet (); | |
8619 | } | |
8620 | } | |
36a05131 | 8621 | |
36a05131 | 8622 | |
c557edf4 RS |
8623 | /* Return true if INSN can be added to the current packet. Update |
8624 | the DFA state on success. */ | |
36a05131 | 8625 | |
c557edf4 RS |
8626 | static bool |
8627 | frv_pack_insn_p (rtx insn) | |
8628 | { | |
8629 | /* See if the packet is already as long as it can be. */ | |
8630 | if (frv_packet.num_insns == frv_packet.issue_rate) | |
8631 | return false; | |
36a05131 | 8632 | |
c557edf4 RS |
8633 | /* If the scheduler thought that an instruction should start a packet, |
8634 | it's usually a good idea to believe it. It knows much more about | |
8635 | the latencies than we do. | |
36a05131 | 8636 | |
c557edf4 | 8637 | There are some exceptions though: |
36a05131 | 8638 | |
c557edf4 RS |
8639 | - Conditional instructions are scheduled on the assumption that |
8640 | they will be executed. This is usually a good thing, since it | |
8641 | tends to avoid unncessary stalls in the conditional code. | |
8642 | But we want to pack conditional instructions as tightly as | |
8643 | possible, in order to optimize the case where they aren't | |
8644 | executed. | |
36a05131 | 8645 | |
c557edf4 RS |
8646 | - The scheduler will always put branches on their own, even |
8647 | if there's no real dependency. | |
36a05131 | 8648 | |
c557edf4 RS |
8649 | - There's no point putting a call in its own packet unless |
8650 | we have to. */ | |
8651 | if (frv_packet.num_insns > 0 | |
8652 | && GET_CODE (insn) == INSN | |
8653 | && GET_MODE (insn) == TImode | |
8654 | && GET_CODE (PATTERN (insn)) != COND_EXEC) | |
8655 | return false; | |
36a05131 | 8656 | |
c557edf4 RS |
8657 | /* Check for register conflicts. Don't do this for setlo since any |
8658 | conflict will be with the partnering sethi, with which it can | |
8659 | be packed. */ | |
8660 | if (get_attr_type (insn) != TYPE_SETLO) | |
8661 | if (frv_registers_conflict_p (PATTERN (insn))) | |
8662 | return false; | |
36a05131 | 8663 | |
c557edf4 RS |
8664 | return state_transition (frv_packet.dfa_state, insn) < 0; |
8665 | } | |
36a05131 | 8666 | |
36a05131 | 8667 | |
c557edf4 | 8668 | /* Add instruction INSN to the current packet. */ |
36a05131 | 8669 | |
c557edf4 RS |
8670 | static void |
8671 | frv_add_insn_to_packet (rtx insn) | |
8672 | { | |
8673 | struct frv_packet_group *packet_group; | |
8674 | ||
8675 | packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]]; | |
8676 | packet_group->insns[packet_group->num_insns++] = insn; | |
8677 | frv_packet.insns[frv_packet.num_insns++] = insn; | |
8678 | ||
8679 | frv_registers_update (PATTERN (insn)); | |
36a05131 BS |
8680 | } |
8681 | ||
c557edf4 RS |
8682 | |
8683 | /* Insert INSN (a member of frv_nops[]) into the current packet. If the | |
8684 | packet ends in a branch or call, insert the nop before it, otherwise | |
8685 | add to the end. */ | |
36a05131 BS |
8686 | |
8687 | static void | |
c557edf4 | 8688 | frv_insert_nop_in_packet (rtx insn) |
36a05131 | 8689 | { |
c557edf4 RS |
8690 | struct frv_packet_group *packet_group; |
8691 | rtx last; | |
8692 | ||
8693 | packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]]; | |
8694 | last = frv_packet.insns[frv_packet.num_insns - 1]; | |
8695 | if (GET_CODE (last) != INSN) | |
8696 | { | |
8697 | insn = emit_insn_before (PATTERN (insn), last); | |
8698 | frv_packet.insns[frv_packet.num_insns - 1] = insn; | |
8699 | frv_packet.insns[frv_packet.num_insns++] = last; | |
8700 | } | |
8701 | else | |
8702 | { | |
8703 | insn = emit_insn_after (PATTERN (insn), last); | |
8704 | frv_packet.insns[frv_packet.num_insns++] = insn; | |
8705 | } | |
8706 | packet_group->insns[packet_group->num_insns++] = insn; | |
8707 | } | |
8708 | ||
36a05131 | 8709 | |
c557edf4 RS |
8710 | /* If packing is enabled, divide the instructions into packets and |
8711 | return true. Call HANDLE_PACKET for each complete packet. */ | |
8712 | ||
8713 | static bool | |
8714 | frv_for_each_packet (void (*handle_packet) (void)) | |
8715 | { | |
8716 | rtx insn, next_insn; | |
8717 | ||
8718 | frv_packet.issue_rate = frv_issue_rate (); | |
8719 | ||
8720 | /* Early exit if we don't want to pack insns. */ | |
28a60850 RS |
8721 | if (!optimize |
8722 | || !flag_schedule_insns_after_reload | |
8723 | || TARGET_NO_VLIW_BRANCH | |
c557edf4 RS |
8724 | || frv_packet.issue_rate == 1) |
8725 | return false; | |
36a05131 | 8726 | |
c557edf4 | 8727 | /* Set up the initial packing state. */ |
36a05131 | 8728 | dfa_start (); |
c557edf4 | 8729 | frv_packet.dfa_state = alloca (state_size ()); |
36a05131 | 8730 | |
c557edf4 RS |
8731 | frv_start_packet_block (); |
8732 | for (insn = get_insns (); insn != 0; insn = next_insn) | |
36a05131 | 8733 | { |
c557edf4 RS |
8734 | enum rtx_code code; |
8735 | bool eh_insn_p; | |
36a05131 | 8736 | |
c557edf4 RS |
8737 | code = GET_CODE (insn); |
8738 | next_insn = NEXT_INSN (insn); | |
8739 | ||
8740 | if (code == CODE_LABEL) | |
36a05131 | 8741 | { |
c557edf4 RS |
8742 | frv_finish_packet (handle_packet); |
8743 | frv_start_packet_block (); | |
8744 | } | |
36a05131 | 8745 | |
c557edf4 RS |
8746 | if (INSN_P (insn)) |
8747 | switch (GET_CODE (PATTERN (insn))) | |
8748 | { | |
8749 | case USE: | |
8750 | case CLOBBER: | |
8751 | case ADDR_VEC: | |
8752 | case ADDR_DIFF_VEC: | |
8753 | break; | |
36a05131 | 8754 | |
c557edf4 RS |
8755 | default: |
8756 | /* Calls mustn't be packed on a TOMCAT. */ | |
8757 | if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT) | |
8758 | frv_finish_packet (handle_packet); | |
8759 | ||
8760 | /* Since the last instruction in a packet determines the EH | |
8761 | region, any exception-throwing instruction must come at | |
8762 | the end of reordered packet. Insns that issue to a | |
8763 | branch unit are bound to come last; for others it's | |
8764 | too hard to predict. */ | |
8765 | eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL); | |
8766 | if (eh_insn_p && !frv_issues_to_branch_unit_p (insn)) | |
8767 | frv_finish_packet (handle_packet); | |
8768 | ||
8769 | /* Finish the current packet if we can't add INSN to it. | |
8770 | Simulate cycles until INSN is ready to issue. */ | |
8771 | if (!frv_pack_insn_p (insn)) | |
8772 | { | |
8773 | frv_finish_packet (handle_packet); | |
8774 | while (!frv_pack_insn_p (insn)) | |
8775 | state_transition (frv_packet.dfa_state, 0); | |
8776 | } | |
36a05131 | 8777 | |
c557edf4 RS |
8778 | /* Add the instruction to the packet. */ |
8779 | frv_add_insn_to_packet (insn); | |
8780 | ||
8781 | /* Calls and jumps end a packet, as do insns that throw | |
8782 | an exception. */ | |
8783 | if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p) | |
8784 | frv_finish_packet (handle_packet); | |
8785 | break; | |
8786 | } | |
8787 | } | |
8788 | frv_finish_packet (handle_packet); | |
8789 | dfa_finish (); | |
8790 | return true; | |
8791 | } | |
8792 | \f | |
8793 | /* Subroutine of frv_sort_insn_group. We are trying to sort | |
8794 | frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly | |
8795 | language order. We have already picked a new position for | |
8796 | frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set. | |
8797 | These instructions will occupy elements [0, LOWER_SLOT) and | |
8798 | [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is | |
8799 | the DFA state after issuing these instructions. | |
8800 | ||
8801 | Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation | |
8802 | of the unused instructions. Return true if one such permutation gives | |
8803 | a valid ordering, leaving the successful permutation in sorted[]. | |
8804 | Do not modify sorted[] until a valid permutation is found. */ | |
8805 | ||
8806 | static bool | |
8807 | frv_sort_insn_group_1 (enum frv_insn_group group, | |
8808 | unsigned int lower_slot, unsigned int upper_slot, | |
8809 | unsigned int issued, unsigned int num_insns, | |
8810 | state_t state) | |
8811 | { | |
8812 | struct frv_packet_group *packet_group; | |
8813 | unsigned int i; | |
8814 | state_t test_state; | |
8815 | size_t dfa_size; | |
8816 | rtx insn; | |
8817 | ||
8818 | /* Early success if we've filled all the slots. */ | |
8819 | if (lower_slot == upper_slot) | |
8820 | return true; | |
8821 | ||
8822 | packet_group = &frv_packet.groups[group]; | |
8823 | dfa_size = state_size (); | |
8824 | test_state = alloca (dfa_size); | |
8825 | ||
8826 | /* Try issuing each unused instruction. */ | |
8827 | for (i = num_insns - 1; i + 1 != 0; i--) | |
8828 | if (~issued & (1 << i)) | |
8829 | { | |
8830 | insn = packet_group->sorted[i]; | |
8831 | memcpy (test_state, state, dfa_size); | |
8832 | if (state_transition (test_state, insn) < 0 | |
8833 | && cpu_unit_reservation_p (test_state, | |
8834 | NTH_UNIT (group, upper_slot - 1)) | |
8835 | && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1, | |
8836 | issued | (1 << i), num_insns, | |
8837 | test_state)) | |
8838 | { | |
8839 | packet_group->sorted[upper_slot - 1] = insn; | |
8840 | return true; | |
8841 | } | |
8842 | } | |
8843 | ||
8844 | return false; | |
8845 | } | |
8846 | ||
8847 | /* Compare two instructions by their frv_insn_unit. */ | |
8848 | ||
8849 | static int | |
8850 | frv_compare_insns (const void *first, const void *second) | |
8851 | { | |
8852 | const rtx *insn1 = first, *insn2 = second; | |
8853 | return frv_insn_unit (*insn1) - frv_insn_unit (*insn2); | |
8854 | } | |
8855 | ||
8856 | /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[] | |
8857 | and sort it into assembly language order. See frv.md for a description of | |
8858 | the algorithm. */ | |
8859 | ||
8860 | static void | |
8861 | frv_sort_insn_group (enum frv_insn_group group) | |
8862 | { | |
8863 | struct frv_packet_group *packet_group; | |
8864 | unsigned int first, i, nop, max_unit, num_slots; | |
8865 | state_t state, test_state; | |
8866 | size_t dfa_size; | |
8867 | ||
8868 | packet_group = &frv_packet.groups[group]; | |
8869 | if (packet_group->num_insns == 0) | |
8870 | return; | |
8871 | ||
8872 | /* Copy insns[] to sorted[]. */ | |
8873 | memcpy (packet_group->sorted, packet_group->insns, | |
8874 | sizeof (rtx) * packet_group->num_insns); | |
8875 | ||
8876 | /* Sort sorted[] by the unit that each insn tries to take first. */ | |
8877 | if (packet_group->num_insns > 1) | |
8878 | qsort (packet_group->sorted, packet_group->num_insns, | |
8879 | sizeof (rtx), frv_compare_insns); | |
8880 | ||
8881 | /* That's always enough for branch and control insns. */ | |
8882 | if (group == GROUP_B || group == GROUP_C) | |
8883 | return; | |
8884 | ||
8885 | dfa_size = state_size (); | |
8886 | state = alloca (dfa_size); | |
8887 | test_state = alloca (dfa_size); | |
8888 | ||
8889 | /* Find the highest FIRST such that sorted[0...FIRST-1] can issue | |
8890 | consecutively and such that the DFA takes unit X when sorted[X] | |
8891 | is added. Set STATE to the new DFA state. */ | |
8892 | state_reset (test_state); | |
8893 | for (first = 0; first < packet_group->num_insns; first++) | |
8894 | { | |
8895 | memcpy (state, test_state, dfa_size); | |
8896 | if (state_transition (test_state, packet_group->sorted[first]) >= 0 | |
8897 | || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first))) | |
8898 | break; | |
8899 | } | |
8900 | ||
8901 | /* If all the instructions issued in ascending order, we're done. */ | |
8902 | if (first == packet_group->num_insns) | |
8903 | return; | |
36a05131 | 8904 | |
c557edf4 RS |
8905 | /* Add nops to the end of sorted[] and try each permutation until |
8906 | we find one that works. */ | |
8907 | for (nop = 0; nop < frv_num_nops; nop++) | |
8908 | { | |
8909 | max_unit = frv_insn_unit (frv_nops[nop]); | |
8910 | if (frv_unit_groups[max_unit] == group) | |
36a05131 | 8911 | { |
c557edf4 RS |
8912 | packet_group->nop = frv_nops[nop]; |
8913 | num_slots = UNIT_NUMBER (max_unit) + 1; | |
8914 | for (i = packet_group->num_insns; i < num_slots; i++) | |
8915 | packet_group->sorted[i] = frv_nops[nop]; | |
8916 | if (frv_sort_insn_group_1 (group, first, num_slots, | |
8917 | (1 << first) - 1, num_slots, state)) | |
8918 | return; | |
36a05131 | 8919 | } |
c557edf4 RS |
8920 | } |
8921 | abort (); | |
8922 | } | |
8923 | \f | |
8924 | /* Sort the current packet into assembly-language order. Set packing | |
8925 | flags as appropriate. */ | |
36a05131 | 8926 | |
c557edf4 RS |
8927 | static void |
8928 | frv_reorder_packet (void) | |
8929 | { | |
8930 | unsigned int cursor[NUM_GROUPS]; | |
8931 | rtx insns[ARRAY_SIZE (frv_unit_groups)]; | |
8932 | unsigned int unit, to, from; | |
8933 | enum frv_insn_group group; | |
8934 | struct frv_packet_group *packet_group; | |
8935 | ||
8936 | /* First sort each group individually. */ | |
8937 | for (group = 0; group < NUM_GROUPS; group++) | |
8938 | { | |
8939 | cursor[group] = 0; | |
8940 | frv_sort_insn_group (group); | |
8941 | } | |
8942 | ||
8943 | /* Go through the unit template and try add an instruction from | |
8944 | that unit's group. */ | |
8945 | to = 0; | |
8946 | for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++) | |
8947 | { | |
8948 | group = frv_unit_groups[unit]; | |
8949 | packet_group = &frv_packet.groups[group]; | |
8950 | if (cursor[group] < packet_group->num_insns) | |
36a05131 | 8951 | { |
c557edf4 RS |
8952 | /* frv_reorg should have added nops for us. */ |
8953 | if (packet_group->sorted[cursor[group]] == packet_group->nop) | |
8954 | abort (); | |
8955 | insns[to++] = packet_group->sorted[cursor[group]++]; | |
36a05131 | 8956 | } |
c557edf4 | 8957 | } |
36a05131 | 8958 | |
c557edf4 RS |
8959 | if (to != frv_packet.num_insns) |
8960 | abort (); | |
36a05131 | 8961 | |
c557edf4 RS |
8962 | /* Clear the last instruction's packing flag, thus marking the end of |
8963 | a packet. Reorder the other instructions relative to it. */ | |
8964 | CLEAR_PACKING_FLAG (insns[to - 1]); | |
8965 | for (from = 0; from < to - 1; from++) | |
8966 | { | |
8967 | remove_insn (insns[from]); | |
8968 | add_insn_before (insns[from], insns[to - 1]); | |
8969 | SET_PACKING_FLAG (insns[from]); | |
8970 | } | |
8971 | } | |
36a05131 | 8972 | |
36a05131 | 8973 | |
c557edf4 RS |
8974 | /* Divide instructions into packets. Reorder the contents of each |
8975 | packet so that they are in the correct assembly-language order. | |
8976 | ||
8977 | Since this pass can change the raw meaning of the rtl stream, it must | |
8978 | only be called at the last minute, just before the instructions are | |
8979 | written out. */ | |
8980 | ||
8981 | static void | |
8982 | frv_pack_insns (void) | |
8983 | { | |
8984 | if (frv_for_each_packet (frv_reorder_packet)) | |
8985 | frv_insn_packing_flag = 0; | |
8986 | else | |
8987 | frv_insn_packing_flag = -1; | |
8988 | } | |
8989 | \f | |
8990 | /* See whether we need to add nops to group GROUP in order to | |
8991 | make a valid packet. */ | |
8992 | ||
8993 | static void | |
8994 | frv_fill_unused_units (enum frv_insn_group group) | |
8995 | { | |
8996 | unsigned int non_nops, nops, i; | |
8997 | struct frv_packet_group *packet_group; | |
8998 | ||
8999 | packet_group = &frv_packet.groups[group]; | |
9000 | ||
9001 | /* Sort the instructions into assembly-language order. | |
9002 | Use nops to fill slots that are otherwise unused. */ | |
9003 | frv_sort_insn_group (group); | |
9004 | ||
9005 | /* See how many nops are needed before the final useful instruction. */ | |
9006 | i = nops = 0; | |
9007 | for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++) | |
9008 | while (packet_group->sorted[i++] == packet_group->nop) | |
9009 | nops++; | |
9010 | ||
9011 | /* Insert that many nops into the instruction stream. */ | |
9012 | while (nops-- > 0) | |
9013 | frv_insert_nop_in_packet (packet_group->nop); | |
9014 | } | |
9015 | ||
9016 | /* Used by frv_reorg to keep track of the current packet's address. */ | |
9017 | static unsigned int frv_packet_address; | |
36a05131 | 9018 | |
c557edf4 RS |
9019 | /* If the current packet falls through to a label, try to pad the packet |
9020 | with nops in order to fit the label's alignment requirements. */ | |
9021 | ||
9022 | static void | |
9023 | frv_align_label (void) | |
9024 | { | |
9025 | unsigned int alignment, target, nop; | |
9026 | rtx x, last, barrier, label; | |
9027 | ||
9028 | /* Walk forward to the start of the next packet. Set ALIGNMENT to the | |
9029 | maximum alignment of that packet, LABEL to the last label between | |
9030 | the packets, and BARRIER to the last barrier. */ | |
9031 | last = frv_packet.insns[frv_packet.num_insns - 1]; | |
9032 | label = barrier = 0; | |
9033 | alignment = 4; | |
9034 | for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x)) | |
9035 | { | |
9036 | if (LABEL_P (x)) | |
36a05131 | 9037 | { |
c557edf4 RS |
9038 | unsigned int subalign = 1 << label_to_alignment (x); |
9039 | alignment = MAX (alignment, subalign); | |
9040 | label = x; | |
36a05131 | 9041 | } |
c557edf4 RS |
9042 | if (BARRIER_P (x)) |
9043 | barrier = x; | |
9044 | } | |
36a05131 | 9045 | |
c557edf4 RS |
9046 | /* If -malign-labels, and the packet falls through to an unaligned |
9047 | label, try introducing a nop to align that label to 8 bytes. */ | |
9048 | if (TARGET_ALIGN_LABELS | |
9049 | && label != 0 | |
9050 | && barrier == 0 | |
9051 | && frv_packet.num_insns < frv_packet.issue_rate) | |
9052 | alignment = MAX (alignment, 8); | |
36a05131 | 9053 | |
c557edf4 RS |
9054 | /* Advance the address to the end of the current packet. */ |
9055 | frv_packet_address += frv_packet.num_insns * 4; | |
36a05131 | 9056 | |
c557edf4 RS |
9057 | /* Work out the target address, after alignment. */ |
9058 | target = (frv_packet_address + alignment - 1) & -alignment; | |
9059 | ||
9060 | /* If the packet falls through to the label, try to find an efficient | |
9061 | padding sequence. */ | |
9062 | if (barrier == 0) | |
9063 | { | |
9064 | /* First try adding nops to the current packet. */ | |
9065 | for (nop = 0; nop < frv_num_nops; nop++) | |
9066 | while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop])) | |
9067 | { | |
9068 | frv_insert_nop_in_packet (frv_nops[nop]); | |
9069 | frv_packet_address += 4; | |
9070 | } | |
9071 | ||
9072 | /* If we still haven't reached the target, add some new packets that | |
9073 | contain only nops. If there are two types of nop, insert an | |
9074 | alternating sequence of frv_nops[0] and frv_nops[1], which will | |
9075 | lead to packets like: | |
9076 | ||
9077 | nop.p | |
9078 | mnop.p/fnop.p | |
9079 | nop.p | |
9080 | mnop/fnop | |
9081 | ||
9082 | etc. Just emit frv_nops[0] if that's the only nop we have. */ | |
9083 | last = frv_packet.insns[frv_packet.num_insns - 1]; | |
9084 | nop = 0; | |
9085 | while (frv_packet_address < target) | |
9086 | { | |
9087 | last = emit_insn_after (PATTERN (frv_nops[nop]), last); | |
9088 | frv_packet_address += 4; | |
9089 | if (frv_num_nops > 1) | |
9090 | nop ^= 1; | |
36a05131 BS |
9091 | } |
9092 | } | |
9093 | ||
c557edf4 | 9094 | frv_packet_address = target; |
36a05131 BS |
9095 | } |
9096 | ||
c557edf4 RS |
9097 | /* Subroutine of frv_reorg, called after each packet has been constructed |
9098 | in frv_packet. */ | |
9099 | ||
9100 | static void | |
9101 | frv_reorg_packet (void) | |
9102 | { | |
9103 | frv_fill_unused_units (GROUP_I); | |
9104 | frv_fill_unused_units (GROUP_FM); | |
9105 | frv_align_label (); | |
9106 | } | |
9107 | ||
9108 | /* Add an instruction with pattern NOP to frv_nops[]. */ | |
9109 | ||
9110 | static void | |
9111 | frv_register_nop (rtx nop) | |
9112 | { | |
9113 | nop = make_insn_raw (nop); | |
9114 | NEXT_INSN (nop) = 0; | |
9115 | PREV_INSN (nop) = 0; | |
9116 | frv_nops[frv_num_nops++] = nop; | |
9117 | } | |
9118 | ||
9119 | /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions | |
9120 | into packets and check whether we need to insert nops in order to | |
9121 | fulfill the processor's issue requirements. Also, if the user has | |
9122 | requested a certain alignment for a label, try to meet that alignment | |
9123 | by inserting nops in the previous packet. */ | |
9124 | ||
9125 | static void | |
9126 | frv_reorg (void) | |
9127 | { | |
9128 | frv_num_nops = 0; | |
9129 | frv_register_nop (gen_nop ()); | |
9130 | if (TARGET_MEDIA) | |
9131 | frv_register_nop (gen_mnop ()); | |
9132 | if (TARGET_HARD_FLOAT) | |
9133 | frv_register_nop (gen_fnop ()); | |
9134 | ||
9135 | /* Estimate the length of each branch. Although this may change after | |
9136 | we've inserted nops, it will only do so in big functions. */ | |
9137 | shorten_branches (get_insns ()); | |
9138 | ||
9139 | frv_packet_address = 0; | |
9140 | frv_for_each_packet (frv_reorg_packet); | |
9141 | } | |
36a05131 BS |
9142 | \f |
9143 | #define def_builtin(name, type, code) \ | |
6e34d3a3 | 9144 | lang_hooks.builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL) |
36a05131 BS |
9145 | |
9146 | struct builtin_description | |
9147 | { | |
9148 | enum insn_code icode; | |
9149 | const char *name; | |
9150 | enum frv_builtins code; | |
9151 | enum rtx_code comparison; | |
9152 | unsigned int flag; | |
9153 | }; | |
9154 | ||
9155 | /* Media intrinsics that take a single, constant argument. */ | |
9156 | ||
9157 | static struct builtin_description bdesc_set[] = | |
9158 | { | |
9159 | { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 } | |
9160 | }; | |
9161 | ||
87b483a1 | 9162 | /* Media intrinsics that take just one argument. */ |
36a05131 BS |
9163 | |
9164 | static struct builtin_description bdesc_1arg[] = | |
9165 | { | |
9166 | { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 }, | |
9167 | { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 }, | |
9168 | { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 }, | |
9169 | { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 }, | |
c557edf4 RS |
9170 | { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 }, |
9171 | { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 } | |
36a05131 BS |
9172 | }; |
9173 | ||
87b483a1 | 9174 | /* Media intrinsics that take two arguments. */ |
36a05131 BS |
9175 | |
9176 | static struct builtin_description bdesc_2arg[] = | |
9177 | { | |
9178 | { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 }, | |
9179 | { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 }, | |
9180 | { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 }, | |
9181 | { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 }, | |
9182 | { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 }, | |
9183 | { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 }, | |
9184 | { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 }, | |
9185 | { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 }, | |
9186 | { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 }, | |
9187 | { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 }, | |
9188 | { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 }, | |
9189 | { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 }, | |
9190 | { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 }, | |
9191 | { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 }, | |
9192 | { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 }, | |
9193 | { CODE_FOR_mdpackh, "__MDPACKH", FRV_BUILTIN_MDPACKH, 0, 0 }, | |
9194 | { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 }, | |
9195 | { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 }, | |
9196 | { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 }, | |
c557edf4 RS |
9197 | { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 }, |
9198 | { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 }, | |
9199 | { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 }, | |
9200 | { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 }, | |
9201 | { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 }, | |
9202 | { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 }, | |
9203 | { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 }, | |
9204 | { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 }, | |
9205 | { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 } | |
9206 | }; | |
9207 | ||
9208 | /* Integer intrinsics that take two arguments and have no return value. */ | |
9209 | ||
9210 | static struct builtin_description bdesc_int_void2arg[] = | |
9211 | { | |
9212 | { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 }, | |
9213 | { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 }, | |
9214 | { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 } | |
9215 | }; | |
9216 | ||
9217 | static struct builtin_description bdesc_prefetches[] = | |
9218 | { | |
9219 | { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 }, | |
9220 | { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 } | |
36a05131 BS |
9221 | }; |
9222 | ||
9223 | /* Media intrinsics that take two arguments, the first being an ACC number. */ | |
9224 | ||
9225 | static struct builtin_description bdesc_cut[] = | |
9226 | { | |
9227 | { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 }, | |
9228 | { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 }, | |
9229 | { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 } | |
9230 | }; | |
9231 | ||
87b483a1 | 9232 | /* Two-argument media intrinsics with an immediate second argument. */ |
36a05131 BS |
9233 | |
9234 | static struct builtin_description bdesc_2argimm[] = | |
9235 | { | |
9236 | { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 }, | |
9237 | { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 }, | |
9238 | { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 }, | |
9239 | { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 }, | |
9240 | { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 }, | |
9241 | { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 }, | |
9242 | { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 }, | |
9243 | { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 }, | |
9244 | { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 }, | |
9245 | { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 }, | |
9246 | { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 }, | |
9247 | { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 }, | |
9248 | { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 }, | |
9249 | { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 }, | |
c557edf4 RS |
9250 | { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 }, |
9251 | { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 }, | |
9252 | { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 } | |
36a05131 BS |
9253 | }; |
9254 | ||
9255 | /* Media intrinsics that take two arguments and return void, the first argument | |
87b483a1 | 9256 | being a pointer to 4 words in memory. */ |
36a05131 BS |
9257 | |
9258 | static struct builtin_description bdesc_void2arg[] = | |
9259 | { | |
9260 | { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 }, | |
9261 | { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 }, | |
9262 | }; | |
9263 | ||
9264 | /* Media intrinsics that take three arguments, the first being a const_int that | |
87b483a1 | 9265 | denotes an accumulator, and that return void. */ |
36a05131 BS |
9266 | |
9267 | static struct builtin_description bdesc_void3arg[] = | |
9268 | { | |
9269 | { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 }, | |
9270 | { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 }, | |
9271 | { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 }, | |
9272 | { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 }, | |
9273 | { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 }, | |
9274 | { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 }, | |
9275 | { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 }, | |
9276 | { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 }, | |
9277 | { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 }, | |
9278 | { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 }, | |
9279 | { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 }, | |
9280 | { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 }, | |
9281 | { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 }, | |
9282 | { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 }, | |
9283 | { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 }, | |
9284 | { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 }, | |
9285 | { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 }, | |
9286 | { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 }, | |
9287 | { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 }, | |
9288 | { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 }, | |
9289 | { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 }, | |
9290 | { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 }, | |
9291 | { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 }, | |
9292 | { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 }, | |
9293 | { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 } | |
9294 | }; | |
9295 | ||
9296 | /* Media intrinsics that take two accumulator numbers as argument and | |
9297 | return void. */ | |
9298 | ||
9299 | static struct builtin_description bdesc_voidacc[] = | |
9300 | { | |
9301 | { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 }, | |
9302 | { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 }, | |
9303 | { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 }, | |
9304 | { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 }, | |
9305 | { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 }, | |
9306 | { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 } | |
9307 | }; | |
9308 | ||
87b483a1 | 9309 | /* Initialize media builtins. */ |
36a05131 | 9310 | |
14966b94 | 9311 | static void |
f2206911 | 9312 | frv_init_builtins (void) |
36a05131 BS |
9313 | { |
9314 | tree endlink = void_list_node; | |
9315 | tree accumulator = integer_type_node; | |
9316 | tree integer = integer_type_node; | |
9317 | tree voidt = void_type_node; | |
9318 | tree uhalf = short_unsigned_type_node; | |
9319 | tree sword1 = long_integer_type_node; | |
9320 | tree uword1 = long_unsigned_type_node; | |
9321 | tree sword2 = long_long_integer_type_node; | |
9322 | tree uword2 = long_long_unsigned_type_node; | |
9323 | tree uword4 = build_pointer_type (uword1); | |
c557edf4 | 9324 | tree iacc = integer_type_node; |
36a05131 BS |
9325 | |
9326 | #define UNARY(RET, T1) \ | |
9327 | build_function_type (RET, tree_cons (NULL_TREE, T1, endlink)) | |
9328 | ||
9329 | #define BINARY(RET, T1, T2) \ | |
9330 | build_function_type (RET, tree_cons (NULL_TREE, T1, \ | |
9331 | tree_cons (NULL_TREE, T2, endlink))) | |
9332 | ||
9333 | #define TRINARY(RET, T1, T2, T3) \ | |
9334 | build_function_type (RET, tree_cons (NULL_TREE, T1, \ | |
9335 | tree_cons (NULL_TREE, T2, \ | |
9336 | tree_cons (NULL_TREE, T3, endlink)))) | |
9337 | ||
9338 | tree void_ftype_void = build_function_type (voidt, endlink); | |
9339 | ||
9340 | tree void_ftype_acc = UNARY (voidt, accumulator); | |
9341 | tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1); | |
9342 | tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2); | |
9343 | tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1); | |
9344 | tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator); | |
9345 | tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1); | |
9346 | tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1); | |
9347 | tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2); | |
9348 | tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2); | |
9349 | ||
9350 | tree uw1_ftype_uw1 = UNARY (uword1, uword1); | |
9351 | tree uw1_ftype_sw1 = UNARY (uword1, sword1); | |
9352 | tree uw1_ftype_uw2 = UNARY (uword1, uword2); | |
9353 | tree uw1_ftype_acc = UNARY (uword1, accumulator); | |
9354 | tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf); | |
9355 | tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1); | |
9356 | tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer); | |
9357 | tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1); | |
9358 | tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1); | |
9359 | tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1); | |
9360 | tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer); | |
9361 | ||
9362 | tree sw1_ftype_int = UNARY (sword1, integer); | |
9363 | tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1); | |
9364 | tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer); | |
9365 | ||
9366 | tree uw2_ftype_uw1 = UNARY (uword2, uword1); | |
9367 | tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer); | |
9368 | tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2); | |
9369 | tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer); | |
9370 | tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer); | |
9371 | ||
9372 | tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2); | |
c557edf4 RS |
9373 | tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer); |
9374 | tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1); | |
9375 | tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1); | |
9376 | tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1); | |
9377 | tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2); | |
9378 | tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1); | |
9379 | tree sw1_ftype_sw1 = UNARY (sword1, sword1); | |
9380 | tree sw2_ftype_iacc = UNARY (sword2, iacc); | |
9381 | tree sw1_ftype_iacc = UNARY (sword1, iacc); | |
9382 | tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node); | |
36a05131 BS |
9383 | |
9384 | def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND); | |
9385 | def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR); | |
9386 | def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR); | |
9387 | def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT); | |
9388 | def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI); | |
9389 | def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI); | |
9390 | def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT); | |
9391 | def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH); | |
9392 | def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI); | |
9393 | def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI); | |
9394 | def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI); | |
9395 | def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS); | |
9396 | def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU); | |
9397 | def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS); | |
9398 | def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS); | |
9399 | def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS); | |
9400 | def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS); | |
9401 | def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS); | |
9402 | def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU); | |
9403 | def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS); | |
9404 | def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU); | |
9405 | def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS); | |
9406 | def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU); | |
9407 | def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS); | |
9408 | def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU); | |
9409 | def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS); | |
9410 | def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS); | |
9411 | def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS); | |
9412 | def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS); | |
9413 | def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS); | |
9414 | def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU); | |
9415 | def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS); | |
9416 | def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU); | |
9417 | def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS); | |
9418 | def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU); | |
9419 | def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS); | |
9420 | def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU); | |
9421 | def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS); | |
9422 | def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU); | |
9423 | def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS); | |
9424 | def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU); | |
9425 | def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS); | |
9426 | def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU); | |
9427 | def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT); | |
9428 | def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS); | |
9429 | def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW); | |
9430 | def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD); | |
9431 | def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH); | |
9432 | def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH); | |
9433 | def_builtin ("__MDPACKH", uw2_ftype_uw2_uw2, FRV_BUILTIN_MDPACKH); | |
b16c1435 | 9434 | def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH); |
36a05131 BS |
9435 | def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH); |
9436 | def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB); | |
9437 | def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE); | |
9438 | def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC); | |
9439 | def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA); | |
9440 | def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC); | |
9441 | def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG); | |
9442 | def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC); | |
9443 | def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG); | |
9444 | def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1); | |
9445 | def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2); | |
9446 | def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP); | |
9447 | def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS); | |
9448 | def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS); | |
9449 | def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS); | |
9450 | def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS); | |
9451 | def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS); | |
9452 | def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS); | |
9453 | def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS); | |
9454 | def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS); | |
9455 | def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS); | |
9456 | def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS); | |
9457 | def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI); | |
9458 | def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI); | |
9459 | def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI); | |
9460 | def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI); | |
9461 | def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS); | |
9462 | def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS); | |
9463 | def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS); | |
9464 | def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS); | |
9465 | def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH); | |
9466 | def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH); | |
9467 | def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH); | |
c557edf4 RS |
9468 | def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS); |
9469 | def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS); | |
9470 | def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI); | |
9471 | def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI); | |
9472 | def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL); | |
9473 | def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL); | |
9474 | def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS); | |
9475 | def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS); | |
9476 | def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU); | |
9477 | def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS); | |
9478 | def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS); | |
9479 | def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS); | |
9480 | def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN); | |
9481 | def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS); | |
9482 | def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll); | |
9483 | def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl); | |
9484 | def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll); | |
9485 | def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl); | |
9486 | def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0); | |
9487 | def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH); | |
36a05131 BS |
9488 | |
9489 | #undef UNARY | |
9490 | #undef BINARY | |
9491 | #undef TRINARY | |
9492 | } | |
9493 | ||
c15c90bb ZW |
9494 | /* Set the names for various arithmetic operations according to the |
9495 | FRV ABI. */ | |
9496 | static void | |
9497 | frv_init_libfuncs (void) | |
9498 | { | |
9499 | set_optab_libfunc (smod_optab, SImode, "__modi"); | |
9500 | set_optab_libfunc (umod_optab, SImode, "__umodi"); | |
9501 | ||
9502 | set_optab_libfunc (add_optab, DImode, "__addll"); | |
9503 | set_optab_libfunc (sub_optab, DImode, "__subll"); | |
9504 | set_optab_libfunc (smul_optab, DImode, "__mulll"); | |
9505 | set_optab_libfunc (sdiv_optab, DImode, "__divll"); | |
9506 | set_optab_libfunc (smod_optab, DImode, "__modll"); | |
9507 | set_optab_libfunc (umod_optab, DImode, "__umodll"); | |
9508 | set_optab_libfunc (and_optab, DImode, "__andll"); | |
9509 | set_optab_libfunc (ior_optab, DImode, "__orll"); | |
9510 | set_optab_libfunc (xor_optab, DImode, "__xorll"); | |
9511 | set_optab_libfunc (one_cmpl_optab, DImode, "__notll"); | |
9512 | ||
9513 | set_optab_libfunc (add_optab, SFmode, "__addf"); | |
9514 | set_optab_libfunc (sub_optab, SFmode, "__subf"); | |
9515 | set_optab_libfunc (smul_optab, SFmode, "__mulf"); | |
9516 | set_optab_libfunc (sdiv_optab, SFmode, "__divf"); | |
9517 | ||
9518 | set_optab_libfunc (add_optab, DFmode, "__addd"); | |
9519 | set_optab_libfunc (sub_optab, DFmode, "__subd"); | |
9520 | set_optab_libfunc (smul_optab, DFmode, "__muld"); | |
9521 | set_optab_libfunc (sdiv_optab, DFmode, "__divd"); | |
9522 | ||
85363ca0 ZW |
9523 | set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod"); |
9524 | set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof"); | |
9525 | ||
9526 | set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi"); | |
9527 | set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll"); | |
9528 | set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi"); | |
9529 | set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll"); | |
9530 | ||
9531 | set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui"); | |
09c55720 RS |
9532 | set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull"); |
9533 | set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui"); | |
9534 | set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull"); | |
85363ca0 ZW |
9535 | |
9536 | set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof"); | |
9537 | set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof"); | |
9538 | set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod"); | |
9539 | set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod"); | |
c15c90bb ZW |
9540 | } |
9541 | ||
36a05131 BS |
9542 | /* Convert an integer constant to an accumulator register. ICODE is the |
9543 | code of the target instruction, OPNUM is the number of the | |
9544 | accumulator operand and OPVAL is the constant integer. Try both | |
9545 | ACC and ACCG registers; only report an error if neither fit the | |
9546 | instruction. */ | |
9547 | ||
9548 | static rtx | |
f2206911 | 9549 | frv_int_to_acc (enum insn_code icode, int opnum, rtx opval) |
36a05131 BS |
9550 | { |
9551 | rtx reg; | |
c557edf4 RS |
9552 | int i; |
9553 | ||
9554 | /* ACCs and ACCGs are implicity global registers if media instrinsics | |
9555 | are being used. We set up this lazily to avoid creating lots of | |
9556 | unncessary call_insn rtl in non-media code. */ | |
9557 | for (i = 0; i <= ACC_MASK; i++) | |
9558 | if ((i & ACC_MASK) == i) | |
9559 | global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1; | |
36a05131 BS |
9560 | |
9561 | if (GET_CODE (opval) != CONST_INT) | |
9562 | { | |
9563 | error ("accumulator is not a constant integer"); | |
9564 | return NULL_RTX; | |
9565 | } | |
c557edf4 | 9566 | if ((INTVAL (opval) & ~ACC_MASK) != 0) |
36a05131 BS |
9567 | { |
9568 | error ("accumulator number is out of bounds"); | |
9569 | return NULL_RTX; | |
9570 | } | |
9571 | ||
9572 | reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode, | |
9573 | ACC_FIRST + INTVAL (opval)); | |
9574 | if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode)) | |
9575 | REGNO (reg) = ACCG_FIRST + INTVAL (opval); | |
9576 | ||
9577 | if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode)) | |
9578 | { | |
9579 | error ("inappropriate accumulator for `%s'", insn_data[icode].name); | |
9580 | return NULL_RTX; | |
9581 | } | |
9582 | return reg; | |
9583 | } | |
9584 | ||
9585 | /* If an ACC rtx has mode MODE, return the mode that the matching ACCG | |
9586 | should have. */ | |
9587 | ||
9588 | static enum machine_mode | |
f2206911 | 9589 | frv_matching_accg_mode (enum machine_mode mode) |
36a05131 BS |
9590 | { |
9591 | switch (mode) | |
9592 | { | |
9593 | case V4SImode: | |
9594 | return V4QImode; | |
9595 | ||
9596 | case DImode: | |
9597 | return HImode; | |
9598 | ||
9599 | case SImode: | |
9600 | return QImode; | |
9601 | ||
9602 | default: | |
9603 | abort (); | |
9604 | } | |
9605 | } | |
9606 | ||
9607 | /* Return the accumulator guard that should be paired with accumulator | |
9608 | register ACC. The mode of the returned register is in the same | |
9609 | class as ACC, but is four times smaller. */ | |
9610 | ||
9611 | rtx | |
f2206911 | 9612 | frv_matching_accg_for_acc (rtx acc) |
36a05131 BS |
9613 | { |
9614 | return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)), | |
9615 | REGNO (acc) - ACC_FIRST + ACCG_FIRST); | |
9616 | } | |
9617 | ||
9618 | /* Read a value from the head of the tree list pointed to by ARGLISTPTR. | |
9619 | Return the value as an rtx and replace *ARGLISTPTR with the tail of the | |
9620 | list. */ | |
9621 | ||
9622 | static rtx | |
f2206911 | 9623 | frv_read_argument (tree *arglistptr) |
36a05131 BS |
9624 | { |
9625 | tree next = TREE_VALUE (*arglistptr); | |
9626 | *arglistptr = TREE_CHAIN (*arglistptr); | |
9627 | return expand_expr (next, NULL_RTX, VOIDmode, 0); | |
9628 | } | |
9629 | ||
c557edf4 RS |
9630 | /* Like frv_read_argument, but interpret the argument as the number |
9631 | of an IACC register and return a (reg:MODE ...) rtx for it. */ | |
9632 | ||
9633 | static rtx | |
9634 | frv_read_iacc_argument (enum machine_mode mode, tree *arglistptr) | |
9635 | { | |
9636 | int i, regno; | |
9637 | rtx op; | |
9638 | ||
9639 | op = frv_read_argument (arglistptr); | |
9640 | if (GET_CODE (op) != CONST_INT | |
9641 | || INTVAL (op) < 0 | |
9642 | || INTVAL (op) > IACC_LAST - IACC_FIRST | |
9643 | || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0) | |
9644 | { | |
9645 | error ("invalid IACC argument"); | |
9646 | op = const0_rtx; | |
9647 | } | |
9648 | ||
9649 | /* IACCs are implicity global registers. We set up this lazily to | |
9650 | avoid creating lots of unncessary call_insn rtl when IACCs aren't | |
9651 | being used. */ | |
9652 | regno = INTVAL (op) + IACC_FIRST; | |
9653 | for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++) | |
9654 | global_regs[regno + i] = 1; | |
9655 | ||
9656 | return gen_rtx_REG (mode, regno); | |
9657 | } | |
9658 | ||
36a05131 BS |
9659 | /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE. |
9660 | The instruction should require a constant operand of some sort. The | |
9661 | function prints an error if OPVAL is not valid. */ | |
9662 | ||
9663 | static int | |
f2206911 | 9664 | frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval) |
36a05131 BS |
9665 | { |
9666 | if (GET_CODE (opval) != CONST_INT) | |
9667 | { | |
9668 | error ("`%s' expects a constant argument", insn_data[icode].name); | |
9669 | return FALSE; | |
9670 | } | |
9671 | if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode)) | |
9672 | { | |
9673 | error ("constant argument out of range for `%s'", insn_data[icode].name); | |
9674 | return FALSE; | |
9675 | } | |
9676 | return TRUE; | |
9677 | } | |
9678 | ||
9679 | /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET | |
9680 | if it's not null, has the right mode, and satisfies operand 0's | |
9681 | predicate. */ | |
9682 | ||
9683 | static rtx | |
f2206911 | 9684 | frv_legitimize_target (enum insn_code icode, rtx target) |
36a05131 BS |
9685 | { |
9686 | enum machine_mode mode = insn_data[icode].operand[0].mode; | |
9687 | ||
9688 | if (! target | |
9689 | || GET_MODE (target) != mode | |
9690 | || ! (*insn_data[icode].operand[0].predicate) (target, mode)) | |
9691 | return gen_reg_rtx (mode); | |
9692 | else | |
9693 | return target; | |
9694 | } | |
9695 | ||
9696 | /* Given that ARG is being passed as operand OPNUM to instruction ICODE, | |
839a4992 | 9697 | check whether ARG satisfies the operand's constraints. If it doesn't, |
36a05131 BS |
9698 | copy ARG to a temporary register and return that. Otherwise return ARG |
9699 | itself. */ | |
9700 | ||
9701 | static rtx | |
f2206911 | 9702 | frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg) |
36a05131 BS |
9703 | { |
9704 | enum machine_mode mode = insn_data[icode].operand[opnum].mode; | |
9705 | ||
9706 | if ((*insn_data[icode].operand[opnum].predicate) (arg, mode)) | |
9707 | return arg; | |
9708 | else | |
9709 | return copy_to_mode_reg (mode, arg); | |
9710 | } | |
9711 | ||
9712 | /* Expand builtins that take a single, constant argument. At the moment, | |
9713 | only MHDSETS falls into this category. */ | |
9714 | ||
9715 | static rtx | |
f2206911 | 9716 | frv_expand_set_builtin (enum insn_code icode, tree arglist, rtx target) |
36a05131 BS |
9717 | { |
9718 | rtx pat; | |
9719 | rtx op0 = frv_read_argument (&arglist); | |
9720 | ||
9721 | if (! frv_check_constant_argument (icode, 1, op0)) | |
9722 | return NULL_RTX; | |
9723 | ||
9724 | target = frv_legitimize_target (icode, target); | |
9725 | pat = GEN_FCN (icode) (target, op0); | |
9726 | if (! pat) | |
9727 | return NULL_RTX; | |
9728 | ||
9729 | emit_insn (pat); | |
9730 | return target; | |
9731 | } | |
9732 | ||
87b483a1 | 9733 | /* Expand builtins that take one operand. */ |
36a05131 BS |
9734 | |
9735 | static rtx | |
f2206911 | 9736 | frv_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target) |
36a05131 BS |
9737 | { |
9738 | rtx pat; | |
9739 | rtx op0 = frv_read_argument (&arglist); | |
9740 | ||
9741 | target = frv_legitimize_target (icode, target); | |
9742 | op0 = frv_legitimize_argument (icode, 1, op0); | |
9743 | pat = GEN_FCN (icode) (target, op0); | |
9744 | if (! pat) | |
9745 | return NULL_RTX; | |
9746 | ||
9747 | emit_insn (pat); | |
9748 | return target; | |
9749 | } | |
9750 | ||
87b483a1 | 9751 | /* Expand builtins that take two operands. */ |
36a05131 BS |
9752 | |
9753 | static rtx | |
f2206911 | 9754 | frv_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target) |
36a05131 BS |
9755 | { |
9756 | rtx pat; | |
9757 | rtx op0 = frv_read_argument (&arglist); | |
9758 | rtx op1 = frv_read_argument (&arglist); | |
9759 | ||
9760 | target = frv_legitimize_target (icode, target); | |
9761 | op0 = frv_legitimize_argument (icode, 1, op0); | |
9762 | op1 = frv_legitimize_argument (icode, 2, op1); | |
9763 | pat = GEN_FCN (icode) (target, op0, op1); | |
9764 | if (! pat) | |
9765 | return NULL_RTX; | |
9766 | ||
9767 | emit_insn (pat); | |
9768 | return target; | |
9769 | } | |
9770 | ||
9771 | /* Expand cut-style builtins, which take two operands and an implicit ACCG | |
87b483a1 | 9772 | one. */ |
36a05131 BS |
9773 | |
9774 | static rtx | |
f2206911 | 9775 | frv_expand_cut_builtin (enum insn_code icode, tree arglist, rtx target) |
36a05131 BS |
9776 | { |
9777 | rtx pat; | |
9778 | rtx op0 = frv_read_argument (&arglist); | |
9779 | rtx op1 = frv_read_argument (&arglist); | |
9780 | rtx op2; | |
9781 | ||
9782 | target = frv_legitimize_target (icode, target); | |
9783 | op0 = frv_int_to_acc (icode, 1, op0); | |
9784 | if (! op0) | |
9785 | return NULL_RTX; | |
9786 | ||
9787 | if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT) | |
9788 | { | |
9789 | if (! frv_check_constant_argument (icode, 2, op1)) | |
9790 | return NULL_RTX; | |
9791 | } | |
9792 | else | |
9793 | op1 = frv_legitimize_argument (icode, 2, op1); | |
9794 | ||
9795 | op2 = frv_matching_accg_for_acc (op0); | |
9796 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
9797 | if (! pat) | |
9798 | return NULL_RTX; | |
9799 | ||
9800 | emit_insn (pat); | |
9801 | return target; | |
9802 | } | |
9803 | ||
87b483a1 | 9804 | /* Expand builtins that take two operands and the second is immediate. */ |
36a05131 BS |
9805 | |
9806 | static rtx | |
f2206911 | 9807 | frv_expand_binopimm_builtin (enum insn_code icode, tree arglist, rtx target) |
36a05131 BS |
9808 | { |
9809 | rtx pat; | |
9810 | rtx op0 = frv_read_argument (&arglist); | |
9811 | rtx op1 = frv_read_argument (&arglist); | |
9812 | ||
9813 | if (! frv_check_constant_argument (icode, 2, op1)) | |
9814 | return NULL_RTX; | |
9815 | ||
9816 | target = frv_legitimize_target (icode, target); | |
9817 | op0 = frv_legitimize_argument (icode, 1, op0); | |
9818 | pat = GEN_FCN (icode) (target, op0, op1); | |
9819 | if (! pat) | |
9820 | return NULL_RTX; | |
9821 | ||
9822 | emit_insn (pat); | |
9823 | return target; | |
9824 | } | |
9825 | ||
9826 | /* Expand builtins that take two operands, the first operand being a pointer to | |
87b483a1 | 9827 | ints and return void. */ |
36a05131 BS |
9828 | |
9829 | static rtx | |
f2206911 | 9830 | frv_expand_voidbinop_builtin (enum insn_code icode, tree arglist) |
36a05131 BS |
9831 | { |
9832 | rtx pat; | |
9833 | rtx op0 = frv_read_argument (&arglist); | |
9834 | rtx op1 = frv_read_argument (&arglist); | |
9835 | enum machine_mode mode0 = insn_data[icode].operand[0].mode; | |
9836 | rtx addr; | |
9837 | ||
9838 | if (GET_CODE (op0) != MEM) | |
9839 | { | |
9840 | rtx reg = op0; | |
9841 | ||
9842 | if (! offsettable_address_p (0, mode0, op0)) | |
9843 | { | |
9844 | reg = gen_reg_rtx (Pmode); | |
9845 | emit_insn (gen_rtx_SET (VOIDmode, reg, op0)); | |
9846 | } | |
9847 | ||
9848 | op0 = gen_rtx_MEM (SImode, reg); | |
9849 | } | |
9850 | ||
9851 | addr = XEXP (op0, 0); | |
9852 | if (! offsettable_address_p (0, mode0, addr)) | |
9853 | addr = copy_to_mode_reg (Pmode, op0); | |
9854 | ||
9855 | op0 = change_address (op0, V4SImode, addr); | |
9856 | op1 = frv_legitimize_argument (icode, 1, op1); | |
9857 | pat = GEN_FCN (icode) (op0, op1); | |
9858 | if (! pat) | |
9859 | return 0; | |
9860 | ||
9861 | emit_insn (pat); | |
9862 | return 0; | |
9863 | } | |
9864 | ||
c557edf4 RS |
9865 | /* Expand builtins that take two long operands and return void. */ |
9866 | ||
9867 | static rtx | |
9868 | frv_expand_int_void2arg (enum insn_code icode, tree arglist) | |
9869 | { | |
9870 | rtx pat; | |
9871 | rtx op0 = frv_read_argument (&arglist); | |
9872 | rtx op1 = frv_read_argument (&arglist); | |
9873 | ||
9874 | op0 = frv_legitimize_argument (icode, 1, op0); | |
9875 | op1 = frv_legitimize_argument (icode, 1, op1); | |
9876 | pat = GEN_FCN (icode) (op0, op1); | |
9877 | if (! pat) | |
9878 | return NULL_RTX; | |
9879 | ||
9880 | emit_insn (pat); | |
9881 | return NULL_RTX; | |
9882 | } | |
9883 | ||
9884 | /* Expand prefetch builtins. These take a single address as argument. */ | |
9885 | ||
9886 | static rtx | |
9887 | frv_expand_prefetches (enum insn_code icode, tree arglist) | |
9888 | { | |
9889 | rtx pat; | |
9890 | rtx op0 = frv_read_argument (&arglist); | |
9891 | ||
9892 | pat = GEN_FCN (icode) (force_reg (Pmode, op0)); | |
9893 | if (! pat) | |
9894 | return 0; | |
9895 | ||
9896 | emit_insn (pat); | |
9897 | return 0; | |
9898 | } | |
9899 | ||
36a05131 BS |
9900 | /* Expand builtins that take three operands and return void. The first |
9901 | argument must be a constant that describes a pair or quad accumulators. A | |
9902 | fourth argument is created that is the accumulator guard register that | |
9903 | corresponds to the accumulator. */ | |
9904 | ||
9905 | static rtx | |
f2206911 | 9906 | frv_expand_voidtriop_builtin (enum insn_code icode, tree arglist) |
36a05131 BS |
9907 | { |
9908 | rtx pat; | |
9909 | rtx op0 = frv_read_argument (&arglist); | |
9910 | rtx op1 = frv_read_argument (&arglist); | |
9911 | rtx op2 = frv_read_argument (&arglist); | |
9912 | rtx op3; | |
9913 | ||
9914 | op0 = frv_int_to_acc (icode, 0, op0); | |
9915 | if (! op0) | |
9916 | return NULL_RTX; | |
9917 | ||
9918 | op1 = frv_legitimize_argument (icode, 1, op1); | |
9919 | op2 = frv_legitimize_argument (icode, 2, op2); | |
9920 | op3 = frv_matching_accg_for_acc (op0); | |
9921 | pat = GEN_FCN (icode) (op0, op1, op2, op3); | |
9922 | if (! pat) | |
9923 | return NULL_RTX; | |
9924 | ||
9925 | emit_insn (pat); | |
9926 | return NULL_RTX; | |
9927 | } | |
9928 | ||
9929 | /* Expand builtins that perform accumulator-to-accumulator operations. | |
9930 | These builtins take two accumulator numbers as argument and return | |
9931 | void. */ | |
9932 | ||
9933 | static rtx | |
f2206911 | 9934 | frv_expand_voidaccop_builtin (enum insn_code icode, tree arglist) |
36a05131 BS |
9935 | { |
9936 | rtx pat; | |
9937 | rtx op0 = frv_read_argument (&arglist); | |
9938 | rtx op1 = frv_read_argument (&arglist); | |
9939 | rtx op2; | |
9940 | rtx op3; | |
9941 | ||
9942 | op0 = frv_int_to_acc (icode, 0, op0); | |
9943 | if (! op0) | |
9944 | return NULL_RTX; | |
9945 | ||
9946 | op1 = frv_int_to_acc (icode, 1, op1); | |
9947 | if (! op1) | |
9948 | return NULL_RTX; | |
9949 | ||
9950 | op2 = frv_matching_accg_for_acc (op0); | |
9951 | op3 = frv_matching_accg_for_acc (op1); | |
9952 | pat = GEN_FCN (icode) (op0, op1, op2, op3); | |
9953 | if (! pat) | |
9954 | return NULL_RTX; | |
9955 | ||
9956 | emit_insn (pat); | |
9957 | return NULL_RTX; | |
9958 | } | |
9959 | ||
9960 | /* Expand the MCLRACC builtin. This builtin takes a single accumulator | |
9961 | number as argument. */ | |
9962 | ||
9963 | static rtx | |
f2206911 | 9964 | frv_expand_mclracc_builtin (tree arglist) |
36a05131 BS |
9965 | { |
9966 | enum insn_code icode = CODE_FOR_mclracc; | |
9967 | rtx pat; | |
9968 | rtx op0 = frv_read_argument (&arglist); | |
9969 | ||
9970 | op0 = frv_int_to_acc (icode, 0, op0); | |
9971 | if (! op0) | |
9972 | return NULL_RTX; | |
9973 | ||
9974 | pat = GEN_FCN (icode) (op0); | |
9975 | if (pat) | |
9976 | emit_insn (pat); | |
9977 | ||
9978 | return NULL_RTX; | |
9979 | } | |
9980 | ||
9981 | /* Expand builtins that take no arguments. */ | |
9982 | ||
9983 | static rtx | |
f2206911 | 9984 | frv_expand_noargs_builtin (enum insn_code icode) |
36a05131 | 9985 | { |
a556fd39 | 9986 | rtx pat = GEN_FCN (icode) (const0_rtx); |
36a05131 BS |
9987 | if (pat) |
9988 | emit_insn (pat); | |
9989 | ||
9990 | return NULL_RTX; | |
9991 | } | |
9992 | ||
9993 | /* Expand MRDACC and MRDACCG. These builtins take a single accumulator | |
9994 | number or accumulator guard number as argument and return an SI integer. */ | |
9995 | ||
9996 | static rtx | |
f2206911 | 9997 | frv_expand_mrdacc_builtin (enum insn_code icode, tree arglist) |
36a05131 BS |
9998 | { |
9999 | rtx pat; | |
10000 | rtx target = gen_reg_rtx (SImode); | |
10001 | rtx op0 = frv_read_argument (&arglist); | |
10002 | ||
10003 | op0 = frv_int_to_acc (icode, 1, op0); | |
10004 | if (! op0) | |
10005 | return NULL_RTX; | |
10006 | ||
10007 | pat = GEN_FCN (icode) (target, op0); | |
10008 | if (! pat) | |
10009 | return NULL_RTX; | |
10010 | ||
10011 | emit_insn (pat); | |
10012 | return target; | |
10013 | } | |
10014 | ||
10015 | /* Expand MWTACC and MWTACCG. These builtins take an accumulator or | |
10016 | accumulator guard as their first argument and an SImode value as their | |
10017 | second. */ | |
10018 | ||
10019 | static rtx | |
f2206911 | 10020 | frv_expand_mwtacc_builtin (enum insn_code icode, tree arglist) |
36a05131 BS |
10021 | { |
10022 | rtx pat; | |
10023 | rtx op0 = frv_read_argument (&arglist); | |
10024 | rtx op1 = frv_read_argument (&arglist); | |
10025 | ||
10026 | op0 = frv_int_to_acc (icode, 0, op0); | |
10027 | if (! op0) | |
10028 | return NULL_RTX; | |
10029 | ||
10030 | op1 = frv_legitimize_argument (icode, 1, op1); | |
10031 | pat = GEN_FCN (icode) (op0, op1); | |
10032 | if (pat) | |
10033 | emit_insn (pat); | |
10034 | ||
10035 | return NULL_RTX; | |
10036 | } | |
10037 | ||
c557edf4 RS |
10038 | /* Emit a move from SRC to DEST in SImode chunks. This can be used |
10039 | to move DImode values into and out of IACC0. */ | |
10040 | ||
10041 | static void | |
10042 | frv_split_iacc_move (rtx dest, rtx src) | |
10043 | { | |
10044 | enum machine_mode inner; | |
10045 | int i; | |
10046 | ||
10047 | inner = GET_MODE (dest); | |
10048 | for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode)) | |
10049 | emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i), | |
10050 | simplify_gen_subreg (SImode, src, inner, i)); | |
10051 | } | |
10052 | ||
87b483a1 | 10053 | /* Expand builtins. */ |
36a05131 | 10054 | |
14966b94 | 10055 | static rtx |
f2206911 KC |
10056 | frv_expand_builtin (tree exp, |
10057 | rtx target, | |
10058 | rtx subtarget ATTRIBUTE_UNUSED, | |
10059 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
10060 | int ignore ATTRIBUTE_UNUSED) | |
36a05131 BS |
10061 | { |
10062 | tree arglist = TREE_OPERAND (exp, 1); | |
10063 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
10064 | unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl); | |
10065 | unsigned i; | |
10066 | struct builtin_description *d; | |
10067 | ||
c557edf4 | 10068 | if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA) |
36a05131 BS |
10069 | { |
10070 | error ("media functions are not available unless -mmedia is used"); | |
10071 | return NULL_RTX; | |
10072 | } | |
10073 | ||
10074 | switch (fcode) | |
10075 | { | |
10076 | case FRV_BUILTIN_MCOP1: | |
10077 | case FRV_BUILTIN_MCOP2: | |
10078 | case FRV_BUILTIN_MDUNPACKH: | |
10079 | case FRV_BUILTIN_MBTOHE: | |
10080 | if (! TARGET_MEDIA_REV1) | |
10081 | { | |
10082 | error ("this media function is only available on the fr500"); | |
10083 | return NULL_RTX; | |
10084 | } | |
10085 | break; | |
10086 | ||
10087 | case FRV_BUILTIN_MQXMACHS: | |
10088 | case FRV_BUILTIN_MQXMACXHS: | |
10089 | case FRV_BUILTIN_MQMACXHS: | |
10090 | case FRV_BUILTIN_MADDACCS: | |
10091 | case FRV_BUILTIN_MSUBACCS: | |
10092 | case FRV_BUILTIN_MASACCS: | |
10093 | case FRV_BUILTIN_MDADDACCS: | |
10094 | case FRV_BUILTIN_MDSUBACCS: | |
10095 | case FRV_BUILTIN_MDASACCS: | |
10096 | case FRV_BUILTIN_MABSHS: | |
10097 | case FRV_BUILTIN_MDROTLI: | |
10098 | case FRV_BUILTIN_MCPLHI: | |
10099 | case FRV_BUILTIN_MCPLI: | |
10100 | case FRV_BUILTIN_MDCUTSSI: | |
10101 | case FRV_BUILTIN_MQSATHS: | |
10102 | case FRV_BUILTIN_MHSETLOS: | |
10103 | case FRV_BUILTIN_MHSETLOH: | |
10104 | case FRV_BUILTIN_MHSETHIS: | |
10105 | case FRV_BUILTIN_MHSETHIH: | |
10106 | case FRV_BUILTIN_MHDSETS: | |
10107 | case FRV_BUILTIN_MHDSETH: | |
10108 | if (! TARGET_MEDIA_REV2) | |
10109 | { | |
c557edf4 RS |
10110 | error ("this media function is only available on the fr400" |
10111 | " and fr550"); | |
10112 | return NULL_RTX; | |
10113 | } | |
10114 | break; | |
10115 | ||
10116 | case FRV_BUILTIN_SMASS: | |
10117 | case FRV_BUILTIN_SMSSS: | |
10118 | case FRV_BUILTIN_SMU: | |
10119 | case FRV_BUILTIN_ADDSS: | |
10120 | case FRV_BUILTIN_SUBSS: | |
10121 | case FRV_BUILTIN_SLASS: | |
10122 | case FRV_BUILTIN_SCUTSS: | |
10123 | case FRV_BUILTIN_IACCreadll: | |
10124 | case FRV_BUILTIN_IACCreadl: | |
10125 | case FRV_BUILTIN_IACCsetll: | |
10126 | case FRV_BUILTIN_IACCsetl: | |
10127 | if (!TARGET_FR405_BUILTINS) | |
10128 | { | |
10129 | error ("this builtin function is only available" | |
10130 | " on the fr405 and fr450"); | |
10131 | return NULL_RTX; | |
10132 | } | |
10133 | break; | |
10134 | ||
10135 | case FRV_BUILTIN_PREFETCH: | |
10136 | if (!TARGET_FR500_FR550_BUILTINS) | |
10137 | { | |
10138 | error ("this builtin function is only available on the fr500" | |
10139 | " and fr550"); | |
10140 | return NULL_RTX; | |
10141 | } | |
10142 | break; | |
10143 | ||
10144 | case FRV_BUILTIN_MQLCLRHS: | |
10145 | case FRV_BUILTIN_MQLMTHS: | |
10146 | case FRV_BUILTIN_MQSLLHI: | |
10147 | case FRV_BUILTIN_MQSRAHI: | |
10148 | if (!TARGET_MEDIA_FR450) | |
10149 | { | |
10150 | error ("this builtin function is only available on the fr450"); | |
36a05131 BS |
10151 | return NULL_RTX; |
10152 | } | |
10153 | break; | |
10154 | ||
10155 | default: | |
10156 | break; | |
10157 | } | |
10158 | ||
87b483a1 | 10159 | /* Expand unique builtins. */ |
36a05131 BS |
10160 | |
10161 | switch (fcode) | |
10162 | { | |
10163 | case FRV_BUILTIN_MTRAP: | |
10164 | return frv_expand_noargs_builtin (CODE_FOR_mtrap); | |
10165 | ||
10166 | case FRV_BUILTIN_MCLRACC: | |
10167 | return frv_expand_mclracc_builtin (arglist); | |
10168 | ||
10169 | case FRV_BUILTIN_MCLRACCA: | |
10170 | if (TARGET_ACC_8) | |
10171 | return frv_expand_noargs_builtin (CODE_FOR_mclracca8); | |
10172 | else | |
10173 | return frv_expand_noargs_builtin (CODE_FOR_mclracca4); | |
10174 | ||
10175 | case FRV_BUILTIN_MRDACC: | |
10176 | return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, arglist); | |
10177 | ||
10178 | case FRV_BUILTIN_MRDACCG: | |
10179 | return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, arglist); | |
10180 | ||
10181 | case FRV_BUILTIN_MWTACC: | |
10182 | return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, arglist); | |
10183 | ||
10184 | case FRV_BUILTIN_MWTACCG: | |
10185 | return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, arglist); | |
10186 | ||
c557edf4 RS |
10187 | case FRV_BUILTIN_IACCreadll: |
10188 | { | |
10189 | rtx src = frv_read_iacc_argument (DImode, &arglist); | |
10190 | if (target == 0 || !REG_P (target)) | |
10191 | target = gen_reg_rtx (DImode); | |
10192 | frv_split_iacc_move (target, src); | |
10193 | return target; | |
10194 | } | |
10195 | ||
10196 | case FRV_BUILTIN_IACCreadl: | |
10197 | return frv_read_iacc_argument (SImode, &arglist); | |
10198 | ||
10199 | case FRV_BUILTIN_IACCsetll: | |
10200 | { | |
10201 | rtx dest = frv_read_iacc_argument (DImode, &arglist); | |
10202 | rtx src = frv_read_argument (&arglist); | |
10203 | frv_split_iacc_move (dest, force_reg (DImode, src)); | |
10204 | return 0; | |
10205 | } | |
10206 | ||
10207 | case FRV_BUILTIN_IACCsetl: | |
10208 | { | |
10209 | rtx dest = frv_read_iacc_argument (SImode, &arglist); | |
10210 | rtx src = frv_read_argument (&arglist); | |
10211 | emit_move_insn (dest, force_reg (SImode, src)); | |
10212 | return 0; | |
10213 | } | |
10214 | ||
36a05131 BS |
10215 | default: |
10216 | break; | |
10217 | } | |
10218 | ||
87b483a1 | 10219 | /* Expand groups of builtins. */ |
36a05131 | 10220 | |
e97a46ce | 10221 | for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++) |
36a05131 BS |
10222 | if (d->code == fcode) |
10223 | return frv_expand_set_builtin (d->icode, arglist, target); | |
10224 | ||
e97a46ce | 10225 | for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
36a05131 BS |
10226 | if (d->code == fcode) |
10227 | return frv_expand_unop_builtin (d->icode, arglist, target); | |
10228 | ||
e97a46ce | 10229 | for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
36a05131 BS |
10230 | if (d->code == fcode) |
10231 | return frv_expand_binop_builtin (d->icode, arglist, target); | |
10232 | ||
e97a46ce | 10233 | for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++) |
36a05131 BS |
10234 | if (d->code == fcode) |
10235 | return frv_expand_cut_builtin (d->icode, arglist, target); | |
10236 | ||
e97a46ce KG |
10237 | for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++) |
10238 | if (d->code == fcode) | |
10239 | return frv_expand_binopimm_builtin (d->icode, arglist, target); | |
36a05131 | 10240 | |
e97a46ce KG |
10241 | for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++) |
10242 | if (d->code == fcode) | |
10243 | return frv_expand_voidbinop_builtin (d->icode, arglist); | |
36a05131 | 10244 | |
e97a46ce KG |
10245 | for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++) |
10246 | if (d->code == fcode) | |
10247 | return frv_expand_voidtriop_builtin (d->icode, arglist); | |
10248 | ||
10249 | for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++) | |
10250 | if (d->code == fcode) | |
10251 | return frv_expand_voidaccop_builtin (d->icode, arglist); | |
36a05131 | 10252 | |
c557edf4 RS |
10253 | for (i = 0, d = bdesc_int_void2arg; |
10254 | i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++) | |
10255 | if (d->code == fcode) | |
10256 | return frv_expand_int_void2arg (d->icode, arglist); | |
10257 | ||
10258 | for (i = 0, d = bdesc_prefetches; | |
10259 | i < ARRAY_SIZE (bdesc_prefetches); i++, d++) | |
10260 | if (d->code == fcode) | |
10261 | return frv_expand_prefetches (d->icode, arglist); | |
10262 | ||
36a05131 BS |
10263 | return 0; |
10264 | } | |
14966b94 | 10265 | |
b3fbfc07 | 10266 | static bool |
f2206911 | 10267 | frv_in_small_data_p (tree decl) |
b3fbfc07 | 10268 | { |
0f6e5d45 RH |
10269 | HOST_WIDE_INT size; |
10270 | tree section_name; | |
10271 | ||
10272 | /* Don't apply the -G flag to internal compiler structures. We | |
10273 | should leave such structures in the main data section, partly | |
10274 | for efficiency and partly because the size of some of them | |
10275 | (such as C++ typeinfos) is not known until later. */ | |
10276 | if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl)) | |
10277 | return false; | |
10278 | ||
0f6e5d45 RH |
10279 | /* If we already know which section the decl should be in, see if |
10280 | it's a small data section. */ | |
10281 | section_name = DECL_SECTION_NAME (decl); | |
10282 | if (section_name) | |
10283 | { | |
10284 | if (TREE_CODE (section_name) != STRING_CST) | |
10285 | abort (); | |
10286 | if (frv_string_begins_with (section_name, ".sdata")) | |
10287 | return true; | |
10288 | if (frv_string_begins_with (section_name, ".sbss")) | |
10289 | return true; | |
68c0ab4f | 10290 | return false; |
0f6e5d45 | 10291 | } |
b3fbfc07 | 10292 | |
68c0ab4f RS |
10293 | size = int_size_in_bytes (TREE_TYPE (decl)); |
10294 | if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value) | |
10295 | return true; | |
10296 | ||
0f6e5d45 | 10297 | return false; |
b3fbfc07 | 10298 | } |
3c50106f RH |
10299 | \f |
10300 | static bool | |
f2206911 KC |
10301 | frv_rtx_costs (rtx x, |
10302 | int code ATTRIBUTE_UNUSED, | |
10303 | int outer_code ATTRIBUTE_UNUSED, | |
10304 | int *total) | |
3c50106f | 10305 | { |
34208acf AO |
10306 | if (outer_code == MEM) |
10307 | { | |
10308 | /* Don't differentiate between memory addresses. All the ones | |
10309 | we accept have equal cost. */ | |
10310 | *total = COSTS_N_INSNS (0); | |
10311 | return true; | |
10312 | } | |
10313 | ||
3c50106f RH |
10314 | switch (code) |
10315 | { | |
10316 | case CONST_INT: | |
10317 | /* Make 12 bit integers really cheap. */ | |
10318 | if (IN_RANGE_P (INTVAL (x), -2048, 2047)) | |
10319 | { | |
10320 | *total = 0; | |
10321 | return true; | |
10322 | } | |
87b483a1 | 10323 | /* Fall through. */ |
3c50106f RH |
10324 | |
10325 | case CONST: | |
10326 | case LABEL_REF: | |
10327 | case SYMBOL_REF: | |
10328 | case CONST_DOUBLE: | |
10329 | *total = COSTS_N_INSNS (2); | |
10330 | return true; | |
10331 | ||
10332 | case PLUS: | |
10333 | case MINUS: | |
10334 | case AND: | |
10335 | case IOR: | |
10336 | case XOR: | |
10337 | case ASHIFT: | |
10338 | case ASHIFTRT: | |
10339 | case LSHIFTRT: | |
10340 | case NOT: | |
10341 | case NEG: | |
10342 | case COMPARE: | |
10343 | if (GET_MODE (x) == SImode) | |
10344 | *total = COSTS_N_INSNS (1); | |
10345 | else if (GET_MODE (x) == DImode) | |
10346 | *total = COSTS_N_INSNS (2); | |
10347 | else | |
10348 | *total = COSTS_N_INSNS (3); | |
10349 | return true; | |
10350 | ||
10351 | case MULT: | |
10352 | if (GET_MODE (x) == SImode) | |
10353 | *total = COSTS_N_INSNS (2); | |
10354 | else | |
10355 | *total = COSTS_N_INSNS (6); /* guess */ | |
10356 | return true; | |
10357 | ||
10358 | case DIV: | |
10359 | case UDIV: | |
10360 | case MOD: | |
10361 | case UMOD: | |
10362 | *total = COSTS_N_INSNS (18); | |
10363 | return true; | |
10364 | ||
34208acf AO |
10365 | case MEM: |
10366 | *total = COSTS_N_INSNS (3); | |
10367 | return true; | |
10368 | ||
3c50106f RH |
10369 | default: |
10370 | return false; | |
10371 | } | |
10372 | } | |
90a63880 RH |
10373 | \f |
10374 | static void | |
f2206911 | 10375 | frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED) |
90a63880 RH |
10376 | { |
10377 | ctors_section (); | |
10378 | assemble_align (POINTER_SIZE); | |
34208acf AO |
10379 | if (TARGET_FDPIC) |
10380 | { | |
10381 | if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1)) | |
10382 | abort (); | |
10383 | return; | |
10384 | } | |
90a63880 RH |
10385 | assemble_integer_with_op ("\t.picptr\t", symbol); |
10386 | } | |
10387 | ||
10388 | static void | |
f2206911 | 10389 | frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED) |
90a63880 RH |
10390 | { |
10391 | dtors_section (); | |
10392 | assemble_align (POINTER_SIZE); | |
34208acf AO |
10393 | if (TARGET_FDPIC) |
10394 | { | |
10395 | if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1)) | |
10396 | abort (); | |
10397 | return; | |
10398 | } | |
90a63880 RH |
10399 | assemble_integer_with_op ("\t.picptr\t", symbol); |
10400 | } | |
8ac411c7 KH |
10401 | |
10402 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ | |
10403 | ||
10404 | static rtx | |
10405 | frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
10406 | int incoming ATTRIBUTE_UNUSED) | |
10407 | { | |
10408 | return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM); | |
10409 | } | |
c557edf4 RS |
10410 | |
10411 | #include "gt-frv.h" |