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bef8809e | 1 | /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005 |
8ac411c7 | 2 | Free Software Foundation, Inc. |
36a05131 BS |
3 | Contributed by Red Hat, Inc. |
4 | ||
7ec022b2 | 5 | This file is part of GCC. |
36a05131 | 6 | |
7ec022b2 | 7 | GCC is free software; you can redistribute it and/or modify |
36a05131 BS |
8 | it under the terms of the GNU General Public License as published by |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
7ec022b2 | 12 | GCC is distributed in the hope that it will be useful, |
36a05131 BS |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
7ec022b2 | 18 | along with GCC; see the file COPYING. If not, write to |
39d14dda KC |
19 | the Free Software Foundation, 51 Franklin Street, Fifth Floor, |
20 | Boston, MA 02110-1301, USA. */ | |
36a05131 BS |
21 | |
22 | #include "config.h" | |
23 | #include "system.h" | |
4977bab6 ZW |
24 | #include "coretypes.h" |
25 | #include "tm.h" | |
36a05131 BS |
26 | #include "rtl.h" |
27 | #include "tree.h" | |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
33 | #include "insn-flags.h" | |
34 | #include "output.h" | |
35 | #include "insn-attr.h" | |
36 | #include "flags.h" | |
37 | #include "recog.h" | |
38 | #include "reload.h" | |
39 | #include "expr.h" | |
40 | #include "obstack.h" | |
41 | #include "except.h" | |
42 | #include "function.h" | |
43 | #include "optabs.h" | |
44 | #include "toplev.h" | |
45 | #include "basic-block.h" | |
46 | #include "tm_p.h" | |
47 | #include "ggc.h" | |
48 | #include <ctype.h> | |
49 | #include "target.h" | |
50 | #include "target-def.h" | |
8cd5a4e0 | 51 | #include "targhooks.h" |
34208acf | 52 | #include "integrate.h" |
6e34d3a3 | 53 | #include "langhooks.h" |
36a05131 BS |
54 | |
55 | #ifndef FRV_INLINE | |
56 | #define FRV_INLINE inline | |
57 | #endif | |
58 | ||
c557edf4 RS |
59 | /* The maximum number of distinct NOP patterns. There are three: |
60 | nop, fnop and mnop. */ | |
61 | #define NUM_NOP_PATTERNS 3 | |
62 | ||
63 | /* Classification of instructions and units: integer, floating-point/media, | |
64 | branch and control. */ | |
65 | enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS }; | |
66 | ||
67 | /* The DFA names of the units, in packet order. */ | |
68 | static const char *const frv_unit_names[] = | |
69 | { | |
70 | "c", | |
71 | "i0", "f0", | |
72 | "i1", "f1", | |
73 | "i2", "f2", | |
74 | "i3", "f3", | |
75 | "b0", "b1" | |
76 | }; | |
77 | ||
78 | /* The classification of each unit in frv_unit_names[]. */ | |
79 | static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] = | |
80 | { | |
81 | GROUP_C, | |
82 | GROUP_I, GROUP_FM, | |
83 | GROUP_I, GROUP_FM, | |
84 | GROUP_I, GROUP_FM, | |
85 | GROUP_I, GROUP_FM, | |
86 | GROUP_B, GROUP_B | |
87 | }; | |
88 | ||
89 | /* Return the DFA unit code associated with the Nth unit of integer | |
90 | or floating-point group GROUP, */ | |
91 | #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1] | |
92 | ||
93 | /* Return the number of integer or floating-point unit UNIT | |
94 | (1 for I1, 2 for F2, etc.). */ | |
95 | #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2) | |
96 | ||
97 | /* The DFA unit number for each unit in frv_unit_names[]. */ | |
98 | static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)]; | |
99 | ||
100 | /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue | |
101 | an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if | |
102 | no instruction of type T has been seen. */ | |
103 | static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1]; | |
104 | ||
105 | /* An array of dummy nop INSNs, one for each type of nop that the | |
106 | target supports. */ | |
107 | static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS]; | |
108 | ||
109 | /* The number of nop instructions in frv_nops[]. */ | |
110 | static unsigned int frv_num_nops; | |
111 | ||
112 | /* Return true if instruction INSN should be packed with the following | |
113 | instruction. */ | |
114 | #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode) | |
115 | ||
116 | /* Set the value of PACKING_FLAG_P(INSN). */ | |
117 | #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode) | |
118 | #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode) | |
119 | ||
120 | /* Loop with REG set to each hard register in rtx X. */ | |
121 | #define FOR_EACH_REGNO(REG, X) \ | |
122 | for (REG = REGNO (X); \ | |
123 | REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \ | |
124 | REG++) | |
125 | ||
36a05131 BS |
126 | /* Temporary register allocation support structure. */ |
127 | typedef struct frv_tmp_reg_struct | |
128 | { | |
129 | HARD_REG_SET regs; /* possible registers to allocate */ | |
130 | int next_reg[N_REG_CLASSES]; /* next register to allocate per class */ | |
131 | } | |
132 | frv_tmp_reg_t; | |
133 | ||
c557edf4 | 134 | /* Register state information for VLIW re-packing phase. */ |
36a05131 | 135 | #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */ |
c557edf4 RS |
136 | #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */ |
137 | #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */ | |
138 | #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */ | |
139 | ||
36a05131 BS |
140 | #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE) |
141 | ||
c557edf4 | 142 | typedef unsigned char regstate_t; |
36a05131 BS |
143 | |
144 | /* Used in frv_frame_accessor_t to indicate the direction of a register-to- | |
145 | memory move. */ | |
146 | enum frv_stack_op | |
147 | { | |
148 | FRV_LOAD, | |
149 | FRV_STORE | |
150 | }; | |
151 | ||
152 | /* Information required by frv_frame_access. */ | |
153 | typedef struct | |
154 | { | |
155 | /* This field is FRV_LOAD if registers are to be loaded from the stack and | |
156 | FRV_STORE if they should be stored onto the stack. FRV_STORE implies | |
157 | the move is being done by the prologue code while FRV_LOAD implies it | |
158 | is being done by the epilogue. */ | |
159 | enum frv_stack_op op; | |
160 | ||
161 | /* The base register to use when accessing the stack. This may be the | |
162 | frame pointer, stack pointer, or a temporary. The choice of register | |
163 | depends on which part of the frame is being accessed and how big the | |
164 | frame is. */ | |
165 | rtx base; | |
166 | ||
167 | /* The offset of BASE from the bottom of the current frame, in bytes. */ | |
168 | int base_offset; | |
169 | } frv_frame_accessor_t; | |
170 | ||
171 | /* Define the information needed to generate branch and scc insns. This is | |
172 | stored from the compare operation. */ | |
173 | rtx frv_compare_op0; | |
174 | rtx frv_compare_op1; | |
175 | ||
87b483a1 | 176 | /* Conditional execution support gathered together in one structure. */ |
36a05131 BS |
177 | typedef struct |
178 | { | |
179 | /* Linked list of insns to add if the conditional execution conversion was | |
180 | successful. Each link points to an EXPR_LIST which points to the pattern | |
181 | of the insn to add, and the insn to be inserted before. */ | |
182 | rtx added_insns_list; | |
183 | ||
184 | /* Identify which registers are safe to allocate for if conversions to | |
185 | conditional execution. We keep the last allocated register in the | |
186 | register classes between COND_EXEC statements. This will mean we allocate | |
187 | different registers for each different COND_EXEC group if we can. This | |
188 | might allow the scheduler to intermix two different COND_EXEC sections. */ | |
189 | frv_tmp_reg_t tmp_reg; | |
190 | ||
191 | /* For nested IFs, identify which CC registers are used outside of setting | |
192 | via a compare isnsn, and using via a check insn. This will allow us to | |
193 | know if we can rewrite the register to use a different register that will | |
194 | be paired with the CR register controlling the nested IF-THEN blocks. */ | |
195 | HARD_REG_SET nested_cc_ok_rewrite; | |
196 | ||
197 | /* Temporary registers allocated to hold constants during conditional | |
198 | execution. */ | |
199 | rtx scratch_regs[FIRST_PSEUDO_REGISTER]; | |
200 | ||
201 | /* Current number of temp registers available. */ | |
202 | int cur_scratch_regs; | |
203 | ||
87b483a1 | 204 | /* Number of nested conditional execution blocks. */ |
36a05131 BS |
205 | int num_nested_cond_exec; |
206 | ||
207 | /* Map of insns that set up constants in scratch registers. */ | |
208 | bitmap scratch_insns_bitmap; | |
209 | ||
87b483a1 | 210 | /* Conditional execution test register (CC0..CC7). */ |
36a05131 BS |
211 | rtx cr_reg; |
212 | ||
213 | /* Conditional execution compare register that is paired with cr_reg, so that | |
214 | nested compares can be done. The csubcc and caddcc instructions don't | |
215 | have enough bits to specify both a CC register to be set and a CR register | |
216 | to do the test on, so the same bit number is used for both. Needless to | |
839a4992 | 217 | say, this is rather inconvenient for GCC. */ |
36a05131 BS |
218 | rtx nested_cc_reg; |
219 | ||
220 | /* Extra CR registers used for &&, ||. */ | |
221 | rtx extra_int_cr; | |
222 | rtx extra_fp_cr; | |
223 | ||
224 | /* Previous CR used in nested if, to make sure we are dealing with the same | |
87b483a1 | 225 | nested if as the previous statement. */ |
36a05131 BS |
226 | rtx last_nested_if_cr; |
227 | } | |
228 | frv_ifcvt_t; | |
229 | ||
230 | static /* GTY(()) */ frv_ifcvt_t frv_ifcvt; | |
231 | ||
232 | /* Map register number to smallest register class. */ | |
233 | enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; | |
234 | ||
87b483a1 | 235 | /* Map class letter into register class. */ |
36a05131 BS |
236 | enum reg_class reg_class_from_letter[256]; |
237 | ||
87b483a1 | 238 | /* Cached value of frv_stack_info. */ |
36a05131 BS |
239 | static frv_stack_t *frv_stack_cache = (frv_stack_t *)0; |
240 | ||
36a05131 | 241 | /* -mcpu= support */ |
36a05131 BS |
242 | frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */ |
243 | ||
36a05131 | 244 | /* Forward references */ |
0b2c18fe RS |
245 | |
246 | static bool frv_handle_option (size_t, const char *, int); | |
f2206911 KC |
247 | static int frv_default_flags_for_cpu (void); |
248 | static int frv_string_begins_with (tree, const char *); | |
34208acf | 249 | static FRV_INLINE bool frv_small_data_reloc_p (rtx, int); |
36a05131 | 250 | static void frv_print_operand_memory_reference_reg |
f2206911 KC |
251 | (FILE *, rtx); |
252 | static void frv_print_operand_memory_reference (FILE *, rtx, int); | |
253 | static int frv_print_operand_jump_hint (rtx); | |
036ff63f | 254 | static const char *comparison_string (enum rtx_code, rtx); |
f2206911 KC |
255 | static FRV_INLINE int frv_regno_ok_for_base_p (int, int); |
256 | static rtx single_set_pattern (rtx); | |
257 | static int frv_function_contains_far_jump (void); | |
258 | static rtx frv_alloc_temp_reg (frv_tmp_reg_t *, | |
259 | enum reg_class, | |
260 | enum machine_mode, | |
261 | int, int); | |
262 | static rtx frv_frame_offset_rtx (int); | |
263 | static rtx frv_frame_mem (enum machine_mode, rtx, int); | |
264 | static rtx frv_dwarf_store (rtx, int); | |
265 | static void frv_frame_insn (rtx, rtx); | |
266 | static void frv_frame_access (frv_frame_accessor_t*, | |
267 | rtx, int); | |
268 | static void frv_frame_access_multi (frv_frame_accessor_t*, | |
269 | frv_stack_t *, int); | |
270 | static void frv_frame_access_standard_regs (enum frv_stack_op, | |
271 | frv_stack_t *); | |
272 | static struct machine_function *frv_init_machine_status (void); | |
f2206911 KC |
273 | static rtx frv_int_to_acc (enum insn_code, int, rtx); |
274 | static enum machine_mode frv_matching_accg_mode (enum machine_mode); | |
275 | static rtx frv_read_argument (tree *); | |
c557edf4 | 276 | static rtx frv_read_iacc_argument (enum machine_mode, tree *); |
f2206911 KC |
277 | static int frv_check_constant_argument (enum insn_code, int, rtx); |
278 | static rtx frv_legitimize_target (enum insn_code, rtx); | |
279 | static rtx frv_legitimize_argument (enum insn_code, int, rtx); | |
bef8809e | 280 | static rtx frv_legitimize_tls_address (rtx, enum tls_model); |
f2206911 KC |
281 | static rtx frv_expand_set_builtin (enum insn_code, tree, rtx); |
282 | static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx); | |
283 | static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx); | |
284 | static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx); | |
285 | static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx); | |
286 | static rtx frv_expand_voidbinop_builtin (enum insn_code, tree); | |
c557edf4 RS |
287 | static rtx frv_expand_int_void2arg (enum insn_code, tree); |
288 | static rtx frv_expand_prefetches (enum insn_code, tree); | |
f2206911 KC |
289 | static rtx frv_expand_voidtriop_builtin (enum insn_code, tree); |
290 | static rtx frv_expand_voidaccop_builtin (enum insn_code, tree); | |
291 | static rtx frv_expand_mclracc_builtin (tree); | |
292 | static rtx frv_expand_mrdacc_builtin (enum insn_code, tree); | |
293 | static rtx frv_expand_mwtacc_builtin (enum insn_code, tree); | |
294 | static rtx frv_expand_noargs_builtin (enum insn_code); | |
c557edf4 | 295 | static void frv_split_iacc_move (rtx, rtx); |
f2206911 KC |
296 | static rtx frv_emit_comparison (enum rtx_code, rtx, rtx); |
297 | static int frv_clear_registers_used (rtx *, void *); | |
298 | static void frv_ifcvt_add_insn (rtx, rtx, int); | |
299 | static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx); | |
300 | static rtx frv_ifcvt_load_value (rtx, rtx); | |
c557edf4 RS |
301 | static int frv_acc_group_1 (rtx *, void *); |
302 | static unsigned int frv_insn_unit (rtx); | |
303 | static bool frv_issues_to_branch_unit_p (rtx); | |
304 | static int frv_cond_flags (rtx); | |
305 | static bool frv_regstate_conflict_p (regstate_t, regstate_t); | |
306 | static int frv_registers_conflict_p_1 (rtx *, void *); | |
307 | static bool frv_registers_conflict_p (rtx); | |
308 | static void frv_registers_update_1 (rtx, rtx, void *); | |
309 | static void frv_registers_update (rtx); | |
310 | static void frv_start_packet (void); | |
311 | static void frv_start_packet_block (void); | |
312 | static void frv_finish_packet (void (*) (void)); | |
313 | static bool frv_pack_insn_p (rtx); | |
314 | static void frv_add_insn_to_packet (rtx); | |
315 | static void frv_insert_nop_in_packet (rtx); | |
316 | static bool frv_for_each_packet (void (*) (void)); | |
317 | static bool frv_sort_insn_group_1 (enum frv_insn_group, | |
318 | unsigned int, unsigned int, | |
319 | unsigned int, unsigned int, | |
320 | state_t); | |
321 | static int frv_compare_insns (const void *, const void *); | |
322 | static void frv_sort_insn_group (enum frv_insn_group); | |
323 | static void frv_reorder_packet (void); | |
324 | static void frv_fill_unused_units (enum frv_insn_group); | |
325 | static void frv_align_label (void); | |
326 | static void frv_reorg_packet (void); | |
327 | static void frv_register_nop (rtx); | |
328 | static void frv_reorg (void); | |
f2206911 KC |
329 | static void frv_pack_insns (void); |
330 | static void frv_function_prologue (FILE *, HOST_WIDE_INT); | |
331 | static void frv_function_epilogue (FILE *, HOST_WIDE_INT); | |
332 | static bool frv_assemble_integer (rtx, unsigned, int); | |
333 | static void frv_init_builtins (void); | |
334 | static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
335 | static void frv_init_libfuncs (void); | |
336 | static bool frv_in_small_data_p (tree); | |
3961e8fe | 337 | static void frv_asm_output_mi_thunk |
f2206911 | 338 | (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree); |
d8c2bed3 KH |
339 | static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *, |
340 | enum machine_mode, | |
341 | tree, int *, int); | |
8ac411c7 | 342 | static rtx frv_expand_builtin_saveregs (void); |
f2206911 KC |
343 | static bool frv_rtx_costs (rtx, int, int, int*); |
344 | static void frv_asm_out_constructor (rtx, int); | |
345 | static void frv_asm_out_destructor (rtx, int); | |
34208acf AO |
346 | static bool frv_function_symbol_referenced_p (rtx); |
347 | static bool frv_cannot_force_const_mem (rtx); | |
348 | static const char *unspec_got_name (int); | |
349 | static void frv_output_const_unspec (FILE *, | |
350 | const struct frv_unspec *); | |
764678d1 | 351 | static bool frv_function_ok_for_sibcall (tree, tree); |
8ac411c7 | 352 | static rtx frv_struct_value_rtx (tree, int); |
fe984136 | 353 | static bool frv_must_pass_in_stack (enum machine_mode mode, tree type); |
78a52f11 RH |
354 | static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
355 | tree, bool); | |
fdbe66f2 EB |
356 | static void frv_output_dwarf_dtprel (FILE *, int, rtx) |
357 | ATTRIBUTE_UNUSED; | |
36a05131 | 358 | \f |
0b2c18fe RS |
359 | /* Allow us to easily change the default for -malloc-cc. */ |
360 | #ifndef DEFAULT_NO_ALLOC_CC | |
361 | #define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC | |
362 | #else | |
363 | #define MASK_DEFAULT_ALLOC_CC 0 | |
364 | #endif | |
365 | \f | |
36a05131 BS |
366 | /* Initialize the GCC target structure. */ |
367 | #undef TARGET_ASM_FUNCTION_PROLOGUE | |
368 | #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue | |
369 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
370 | #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue | |
371 | #undef TARGET_ASM_INTEGER | |
372 | #define TARGET_ASM_INTEGER frv_assemble_integer | |
0b2c18fe RS |
373 | #undef TARGET_DEFAULT_TARGET_FLAGS |
374 | #define TARGET_DEFAULT_TARGET_FLAGS \ | |
375 | (MASK_DEFAULT_ALLOC_CC \ | |
376 | | MASK_COND_MOVE \ | |
377 | | MASK_SCC \ | |
378 | | MASK_COND_EXEC \ | |
379 | | MASK_VLIW_BRANCH \ | |
380 | | MASK_MULTI_CE \ | |
381 | | MASK_NESTED_CE) | |
382 | #undef TARGET_HANDLE_OPTION | |
383 | #define TARGET_HANDLE_OPTION frv_handle_option | |
14966b94 KG |
384 | #undef TARGET_INIT_BUILTINS |
385 | #define TARGET_INIT_BUILTINS frv_init_builtins | |
386 | #undef TARGET_EXPAND_BUILTIN | |
387 | #define TARGET_EXPAND_BUILTIN frv_expand_builtin | |
c15c90bb ZW |
388 | #undef TARGET_INIT_LIBFUNCS |
389 | #define TARGET_INIT_LIBFUNCS frv_init_libfuncs | |
b3fbfc07 KG |
390 | #undef TARGET_IN_SMALL_DATA_P |
391 | #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p | |
3c50106f RH |
392 | #undef TARGET_RTX_COSTS |
393 | #define TARGET_RTX_COSTS frv_rtx_costs | |
90a63880 RH |
394 | #undef TARGET_ASM_CONSTRUCTOR |
395 | #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor | |
396 | #undef TARGET_ASM_DESTRUCTOR | |
397 | #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor | |
36a05131 | 398 | |
c590b625 RH |
399 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
400 | #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk | |
3961e8fe RH |
401 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
402 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
c590b625 | 403 | |
28a60850 RS |
404 | #undef TARGET_SCHED_ISSUE_RATE |
405 | #define TARGET_SCHED_ISSUE_RATE frv_issue_rate | |
ffb344c1 | 406 | |
764678d1 AO |
407 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
408 | #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall | |
34208acf AO |
409 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
410 | #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem | |
411 | ||
bef8809e AH |
412 | #undef TARGET_HAVE_TLS |
413 | #define TARGET_HAVE_TLS HAVE_AS_TLS | |
414 | ||
8ac411c7 KH |
415 | #undef TARGET_STRUCT_VALUE_RTX |
416 | #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx | |
fe984136 RH |
417 | #undef TARGET_MUST_PASS_IN_STACK |
418 | #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack | |
8cd5a4e0 RH |
419 | #undef TARGET_PASS_BY_REFERENCE |
420 | #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack | |
78a52f11 RH |
421 | #undef TARGET_ARG_PARTIAL_BYTES |
422 | #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes | |
8ac411c7 KH |
423 | |
424 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
425 | #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs | |
d8c2bed3 KH |
426 | #undef TARGET_SETUP_INCOMING_VARARGS |
427 | #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs | |
c557edf4 RS |
428 | #undef TARGET_MACHINE_DEPENDENT_REORG |
429 | #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg | |
8ac411c7 | 430 | |
fdbe66f2 EB |
431 | #if HAVE_AS_TLS |
432 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
433 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel | |
434 | #endif | |
435 | ||
36a05131 | 436 | struct gcc_target targetm = TARGET_INITIALIZER; |
bef8809e AH |
437 | |
438 | #define FRV_SYMBOL_REF_TLS_P(RTX) \ | |
439 | (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) | |
440 | ||
36a05131 | 441 | \f |
764678d1 AO |
442 | /* Any function call that satisfies the machine-independent |
443 | requirements is eligible on FR-V. */ | |
444 | ||
445 | static bool | |
446 | frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED, | |
447 | tree exp ATTRIBUTE_UNUSED) | |
448 | { | |
449 | return true; | |
450 | } | |
451 | ||
34208acf AO |
452 | /* Return true if SYMBOL is a small data symbol and relocation RELOC |
453 | can be used to access it directly in a load or store. */ | |
36a05131 | 454 | |
34208acf AO |
455 | static FRV_INLINE bool |
456 | frv_small_data_reloc_p (rtx symbol, int reloc) | |
36a05131 | 457 | { |
34208acf AO |
458 | return (GET_CODE (symbol) == SYMBOL_REF |
459 | && SYMBOL_REF_SMALL_P (symbol) | |
460 | && (!TARGET_FDPIC || flag_pic == 1) | |
461 | && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12)); | |
462 | } | |
36a05131 | 463 | |
34208acf AO |
464 | /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC |
465 | appropriately. */ | |
36a05131 | 466 | |
6d26dc3b | 467 | bool |
34208acf AO |
468 | frv_const_unspec_p (rtx x, struct frv_unspec *unspec) |
469 | { | |
470 | if (GET_CODE (x) == CONST) | |
471 | { | |
472 | unspec->offset = 0; | |
473 | x = XEXP (x, 0); | |
474 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
475 | { | |
476 | unspec->offset += INTVAL (XEXP (x, 1)); | |
477 | x = XEXP (x, 0); | |
478 | } | |
479 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT) | |
480 | { | |
481 | unspec->symbol = XVECEXP (x, 0, 0); | |
482 | unspec->reloc = INTVAL (XVECEXP (x, 0, 1)); | |
36a05131 | 483 | |
34208acf AO |
484 | if (unspec->offset == 0) |
485 | return true; | |
36a05131 | 486 | |
34208acf AO |
487 | if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc) |
488 | && unspec->offset > 0 | |
489 | && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value) | |
490 | return true; | |
491 | } | |
492 | } | |
493 | return false; | |
36a05131 BS |
494 | } |
495 | ||
34208acf AO |
496 | /* Decide whether we can force certain constants to memory. If we |
497 | decide we can't, the caller should be able to cope with it in | |
498 | another way. | |
36a05131 | 499 | |
34208acf AO |
500 | We never allow constants to be forced into memory for TARGET_FDPIC. |
501 | This is necessary for several reasons: | |
36a05131 | 502 | |
34208acf AO |
503 | 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the |
504 | target-independent code will try to force them into the constant | |
505 | pool, thus leading to infinite recursion. | |
36a05131 | 506 | |
34208acf AO |
507 | 2. We can never introduce new constant pool references during reload. |
508 | Any such reference would require use of the pseudo FDPIC register. | |
36a05131 | 509 | |
34208acf AO |
510 | 3. We can't represent a constant added to a function pointer (which is |
511 | not the same as a pointer to a function+constant). | |
512 | ||
513 | 4. In many cases, it's more efficient to calculate the constant in-line. */ | |
514 | ||
515 | static bool | |
516 | frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED) | |
517 | { | |
518 | return TARGET_FDPIC; | |
519 | } | |
36a05131 | 520 | \f |
0b2c18fe RS |
521 | /* Implement TARGET_HANDLE_OPTION. */ |
522 | ||
523 | static bool | |
524 | frv_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED) | |
525 | { | |
526 | switch (code) | |
527 | { | |
528 | case OPT_mcpu_: | |
529 | if (strcmp (arg, "simple") == 0) | |
530 | frv_cpu_type = FRV_CPU_SIMPLE; | |
531 | else if (strcmp (arg, "tomcat") == 0) | |
532 | frv_cpu_type = FRV_CPU_TOMCAT; | |
533 | else if (strcmp (arg, "fr550") == 0) | |
534 | frv_cpu_type = FRV_CPU_FR550; | |
535 | else if (strcmp (arg, "fr500") == 0) | |
536 | frv_cpu_type = FRV_CPU_FR500; | |
537 | else if (strcmp (arg, "fr450") == 0) | |
538 | frv_cpu_type = FRV_CPU_FR450; | |
539 | else if (strcmp (arg, "fr405") == 0) | |
540 | frv_cpu_type = FRV_CPU_FR405; | |
541 | else if (strcmp (arg, "fr400") == 0) | |
542 | frv_cpu_type = FRV_CPU_FR400; | |
543 | else if (strcmp (arg, "fr300") == 0) | |
544 | frv_cpu_type = FRV_CPU_FR300; | |
545 | else if (strcmp (arg, "frv") == 0) | |
546 | frv_cpu_type = FRV_CPU_GENERIC; | |
547 | else | |
548 | return false; | |
549 | return true; | |
550 | ||
551 | default: | |
552 | return true; | |
553 | } | |
554 | } | |
555 | ||
36a05131 | 556 | static int |
f2206911 | 557 | frv_default_flags_for_cpu (void) |
36a05131 BS |
558 | { |
559 | switch (frv_cpu_type) | |
560 | { | |
561 | case FRV_CPU_GENERIC: | |
562 | return MASK_DEFAULT_FRV; | |
563 | ||
c557edf4 RS |
564 | case FRV_CPU_FR550: |
565 | return MASK_DEFAULT_FR550; | |
566 | ||
36a05131 BS |
567 | case FRV_CPU_FR500: |
568 | case FRV_CPU_TOMCAT: | |
569 | return MASK_DEFAULT_FR500; | |
570 | ||
c557edf4 RS |
571 | case FRV_CPU_FR450: |
572 | return MASK_DEFAULT_FR450; | |
573 | ||
574 | case FRV_CPU_FR405: | |
36a05131 BS |
575 | case FRV_CPU_FR400: |
576 | return MASK_DEFAULT_FR400; | |
577 | ||
578 | case FRV_CPU_FR300: | |
579 | case FRV_CPU_SIMPLE: | |
580 | return MASK_DEFAULT_SIMPLE; | |
44e91694 NS |
581 | |
582 | default: | |
583 | gcc_unreachable (); | |
36a05131 | 584 | } |
36a05131 BS |
585 | } |
586 | ||
587 | /* Sometimes certain combinations of command options do not make | |
588 | sense on a particular target machine. You can define a macro | |
589 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
590 | defined, is executed once just after all the command options have | |
591 | been parsed. | |
592 | ||
593 | Don't use this macro to turn on various extra optimizations for | |
594 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
595 | ||
596 | void | |
f2206911 | 597 | frv_override_options (void) |
36a05131 | 598 | { |
c557edf4 RS |
599 | int regno; |
600 | unsigned int i; | |
36a05131 | 601 | |
36a05131 BS |
602 | target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit); |
603 | ||
604 | /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the | |
605 | linker about linking pic and non-pic code. */ | |
606 | if (TARGET_LIBPIC) | |
607 | { | |
608 | if (!flag_pic) /* -fPIC */ | |
609 | flag_pic = 2; | |
610 | ||
611 | if (! g_switch_set) /* -G0 */ | |
612 | { | |
613 | g_switch_set = 1; | |
614 | g_switch_value = 0; | |
615 | } | |
616 | } | |
617 | ||
36a05131 BS |
618 | /* A C expression whose value is a register class containing hard |
619 | register REGNO. In general there is more than one such class; | |
620 | choose a class which is "minimal", meaning that no smaller class | |
87b483a1 | 621 | also contains the register. */ |
36a05131 BS |
622 | |
623 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
624 | { | |
625 | enum reg_class class; | |
626 | ||
627 | if (GPR_P (regno)) | |
628 | { | |
629 | int gpr_reg = regno - GPR_FIRST; | |
bef8809e AH |
630 | |
631 | if (gpr_reg == GR8_REG) | |
632 | class = GR8_REGS; | |
633 | ||
634 | else if (gpr_reg == GR9_REG) | |
635 | class = GR9_REGS; | |
636 | ||
637 | else if (gpr_reg == GR14_REG) | |
638 | class = FDPIC_FPTR_REGS; | |
639 | ||
640 | else if (gpr_reg == FDPIC_REGNO) | |
641 | class = FDPIC_REGS; | |
642 | ||
643 | else if ((gpr_reg & 3) == 0) | |
36a05131 BS |
644 | class = QUAD_REGS; |
645 | ||
646 | else if ((gpr_reg & 1) == 0) | |
647 | class = EVEN_REGS; | |
648 | ||
649 | else | |
650 | class = GPR_REGS; | |
651 | } | |
652 | ||
653 | else if (FPR_P (regno)) | |
654 | { | |
655 | int fpr_reg = regno - GPR_FIRST; | |
656 | if ((fpr_reg & 3) == 0) | |
657 | class = QUAD_FPR_REGS; | |
658 | ||
659 | else if ((fpr_reg & 1) == 0) | |
660 | class = FEVEN_REGS; | |
661 | ||
662 | else | |
663 | class = FPR_REGS; | |
664 | } | |
665 | ||
666 | else if (regno == LR_REGNO) | |
667 | class = LR_REG; | |
668 | ||
669 | else if (regno == LCR_REGNO) | |
670 | class = LCR_REG; | |
671 | ||
672 | else if (ICC_P (regno)) | |
673 | class = ICC_REGS; | |
674 | ||
675 | else if (FCC_P (regno)) | |
676 | class = FCC_REGS; | |
677 | ||
678 | else if (ICR_P (regno)) | |
679 | class = ICR_REGS; | |
680 | ||
681 | else if (FCR_P (regno)) | |
682 | class = FCR_REGS; | |
683 | ||
684 | else if (ACC_P (regno)) | |
685 | { | |
686 | int r = regno - ACC_FIRST; | |
687 | if ((r & 3) == 0) | |
688 | class = QUAD_ACC_REGS; | |
689 | else if ((r & 1) == 0) | |
690 | class = EVEN_ACC_REGS; | |
691 | else | |
692 | class = ACC_REGS; | |
693 | } | |
694 | ||
695 | else if (ACCG_P (regno)) | |
696 | class = ACCG_REGS; | |
697 | ||
698 | else | |
699 | class = NO_REGS; | |
700 | ||
701 | regno_reg_class[regno] = class; | |
702 | } | |
703 | ||
704 | /* Check for small data option */ | |
705 | if (!g_switch_set) | |
706 | g_switch_value = SDATA_DEFAULT_SIZE; | |
707 | ||
708 | /* A C expression which defines the machine-dependent operand | |
709 | constraint letters for register classes. If CHAR is such a | |
710 | letter, the value should be the register class corresponding to | |
711 | it. Otherwise, the value should be `NO_REGS'. The register | |
712 | letter `r', corresponding to class `GENERAL_REGS', will not be | |
713 | passed to this macro; you do not need to handle it. | |
714 | ||
715 | The following letters are unavailable, due to being used as | |
716 | constraints: | |
717 | '0'..'9' | |
718 | '<', '>' | |
719 | 'E', 'F', 'G', 'H' | |
720 | 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P' | |
721 | 'Q', 'R', 'S', 'T', 'U' | |
722 | 'V', 'X' | |
723 | 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */ | |
724 | ||
725 | for (i = 0; i < 256; i++) | |
726 | reg_class_from_letter[i] = NO_REGS; | |
727 | ||
728 | reg_class_from_letter['a'] = ACC_REGS; | |
729 | reg_class_from_letter['b'] = EVEN_ACC_REGS; | |
730 | reg_class_from_letter['c'] = CC_REGS; | |
731 | reg_class_from_letter['d'] = GPR_REGS; | |
732 | reg_class_from_letter['e'] = EVEN_REGS; | |
733 | reg_class_from_letter['f'] = FPR_REGS; | |
734 | reg_class_from_letter['h'] = FEVEN_REGS; | |
735 | reg_class_from_letter['l'] = LR_REG; | |
736 | reg_class_from_letter['q'] = QUAD_REGS; | |
737 | reg_class_from_letter['t'] = ICC_REGS; | |
738 | reg_class_from_letter['u'] = FCC_REGS; | |
739 | reg_class_from_letter['v'] = ICR_REGS; | |
740 | reg_class_from_letter['w'] = FCR_REGS; | |
741 | reg_class_from_letter['x'] = QUAD_FPR_REGS; | |
742 | reg_class_from_letter['y'] = LCR_REG; | |
743 | reg_class_from_letter['z'] = SPR_REGS; | |
744 | reg_class_from_letter['A'] = QUAD_ACC_REGS; | |
745 | reg_class_from_letter['B'] = ACCG_REGS; | |
746 | reg_class_from_letter['C'] = CR_REGS; | |
34208acf AO |
747 | reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */ |
748 | reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */ | |
36a05131 BS |
749 | |
750 | /* There is no single unaligned SI op for PIC code. Sometimes we | |
751 | need to use ".4byte" and sometimes we need to use ".picptr". | |
752 | See frv_assemble_integer for details. */ | |
34208acf | 753 | if (flag_pic || TARGET_FDPIC) |
36a05131 BS |
754 | targetm.asm_out.unaligned_op.si = 0; |
755 | ||
34208acf AO |
756 | if ((target_flags_explicit & MASK_LINKED_FP) == 0) |
757 | target_flags |= MASK_LINKED_FP; | |
758 | ||
c557edf4 RS |
759 | for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++) |
760 | frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]); | |
761 | ||
762 | for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++) | |
763 | frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes); | |
764 | ||
36a05131 BS |
765 | init_machine_status = frv_init_machine_status; |
766 | } | |
767 | ||
768 | \f | |
769 | /* Some machines may desire to change what optimizations are performed for | |
770 | various optimization levels. This macro, if defined, is executed once just | |
771 | after the optimization level is determined and before the remainder of the | |
772 | command options have been parsed. Values set in this macro are used as the | |
773 | default values for the other command line options. | |
774 | ||
775 | LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if | |
776 | `-O' is specified, and 0 if neither is specified. | |
777 | ||
9cd10576 | 778 | SIZE is nonzero if `-Os' is specified, 0 otherwise. |
36a05131 BS |
779 | |
780 | You should not use this macro to change options that are not | |
781 | machine-specific. These should uniformly selected by the same optimization | |
aabcd309 | 782 | level on all supported machines. Use this macro to enable machine-specific |
36a05131 BS |
783 | optimizations. |
784 | ||
785 | *Do not examine `write_symbols' in this macro!* The debugging options are | |
786 | *not supposed to alter the generated code. */ | |
787 | ||
788 | /* On the FRV, possibly disable VLIW packing which is done by the 2nd | |
789 | scheduling pass at the current time. */ | |
790 | void | |
f2206911 | 791 | frv_optimization_options (int level, int size ATTRIBUTE_UNUSED) |
36a05131 BS |
792 | { |
793 | if (level >= 2) | |
794 | { | |
795 | #ifdef DISABLE_SCHED2 | |
796 | flag_schedule_insns_after_reload = 0; | |
797 | #endif | |
798 | #ifdef ENABLE_RCSP | |
799 | flag_rcsp = 1; | |
800 | #endif | |
801 | } | |
802 | } | |
803 | ||
36a05131 BS |
804 | \f |
805 | /* Return true if NAME (a STRING_CST node) begins with PREFIX. */ | |
806 | ||
807 | static int | |
f2206911 | 808 | frv_string_begins_with (tree name, const char *prefix) |
36a05131 BS |
809 | { |
810 | int prefix_len = strlen (prefix); | |
811 | ||
812 | /* Remember: NAME's length includes the null terminator. */ | |
813 | return (TREE_STRING_LENGTH (name) > prefix_len | |
814 | && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0); | |
815 | } | |
36a05131 BS |
816 | \f |
817 | /* Zero or more C statements that may conditionally modify two variables | |
818 | `fixed_regs' and `call_used_regs' (both of type `char []') after they have | |
819 | been initialized from the two preceding macros. | |
820 | ||
821 | This is necessary in case the fixed or call-clobbered registers depend on | |
822 | target flags. | |
823 | ||
824 | You need not define this macro if it has no work to do. | |
825 | ||
826 | If the usage of an entire class of registers depends on the target flags, | |
827 | you may indicate this to GCC by using this macro to modify `fixed_regs' and | |
828 | `call_used_regs' to 1 for each of the registers in the classes which should | |
829 | not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return | |
830 | `NO_REGS' if it is called with a letter for a class that shouldn't be used. | |
831 | ||
832 | (However, if this class is not included in `GENERAL_REGS' and all of the | |
833 | insn patterns whose constraints permit this class are controlled by target | |
834 | switches, then GCC will automatically avoid using these registers when the | |
835 | target switches are opposed to them.) */ | |
836 | ||
837 | void | |
f2206911 | 838 | frv_conditional_register_usage (void) |
36a05131 BS |
839 | { |
840 | int i; | |
841 | ||
842 | for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++) | |
843 | fixed_regs[i] = call_used_regs[i] = 1; | |
844 | ||
845 | for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++) | |
846 | fixed_regs[i] = call_used_regs[i] = 1; | |
847 | ||
36a05131 BS |
848 | /* Reserve the registers used for conditional execution. At present, we need |
849 | 1 ICC and 1 ICR register. */ | |
850 | fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1; | |
851 | fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1; | |
852 | ||
853 | if (TARGET_FIXED_CC) | |
854 | { | |
855 | fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1; | |
856 | fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1; | |
857 | fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1; | |
858 | fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1; | |
859 | } | |
860 | ||
34208acf AO |
861 | if (TARGET_FDPIC) |
862 | fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] = | |
863 | call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0; | |
864 | ||
36a05131 BS |
865 | #if 0 |
866 | /* If -fpic, SDA_BASE_REG is the PIC register. */ | |
867 | if (g_switch_value == 0 && !flag_pic) | |
868 | fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0; | |
869 | ||
870 | if (!flag_pic) | |
871 | fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0; | |
872 | #endif | |
873 | } | |
874 | ||
875 | \f | |
876 | /* | |
877 | * Compute the stack frame layout | |
878 | * | |
879 | * Register setup: | |
880 | * +---------------+-----------------------+-----------------------+ | |
881 | * |Register |type |caller-save/callee-save| | |
882 | * +---------------+-----------------------+-----------------------+ | |
883 | * |GR0 |Zero register | - | | |
884 | * |GR1 |Stack pointer(SP) | - | | |
885 | * |GR2 |Frame pointer(FP) | - | | |
886 | * |GR3 |Hidden parameter | caller save | | |
887 | * |GR4-GR7 | - | caller save | | |
888 | * |GR8-GR13 |Argument register | caller save | | |
889 | * |GR14-GR15 | - | caller save | | |
890 | * |GR16-GR31 | - | callee save | | |
891 | * |GR32-GR47 | - | caller save | | |
892 | * |GR48-GR63 | - | callee save | | |
893 | * |FR0-FR15 | - | caller save | | |
894 | * |FR16-FR31 | - | callee save | | |
895 | * |FR32-FR47 | - | caller save | | |
896 | * |FR48-FR63 | - | callee save | | |
897 | * +---------------+-----------------------+-----------------------+ | |
898 | * | |
899 | * Stack frame setup: | |
900 | * Low | |
901 | * SP-> |-----------------------------------| | |
902 | * | Argument area | | |
903 | * |-----------------------------------| | |
904 | * | Register save area | | |
905 | * |-----------------------------------| | |
906 | * | Local variable save area | | |
907 | * FP-> |-----------------------------------| | |
908 | * | Old FP | | |
909 | * |-----------------------------------| | |
910 | * | Hidden parameter save area | | |
911 | * |-----------------------------------| | |
912 | * | Return address(LR) storage area | | |
913 | * |-----------------------------------| | |
914 | * | Padding for alignment | | |
915 | * |-----------------------------------| | |
916 | * | Register argument area | | |
917 | * OLD SP-> |-----------------------------------| | |
918 | * | Parameter area | | |
919 | * |-----------------------------------| | |
920 | * High | |
921 | * | |
922 | * Argument area/Parameter area: | |
923 | * | |
924 | * When a function is called, this area is used for argument transfer. When | |
925 | * the argument is set up by the caller function, this area is referred to as | |
926 | * the argument area. When the argument is referenced by the callee function, | |
927 | * this area is referred to as the parameter area. The area is allocated when | |
928 | * all arguments cannot be placed on the argument register at the time of | |
929 | * argument transfer. | |
930 | * | |
931 | * Register save area: | |
932 | * | |
933 | * This is a register save area that must be guaranteed for the caller | |
934 | * function. This area is not secured when the register save operation is not | |
935 | * needed. | |
936 | * | |
937 | * Local variable save area: | |
938 | * | |
939 | * This is the area for local variables and temporary variables. | |
940 | * | |
941 | * Old FP: | |
942 | * | |
943 | * This area stores the FP value of the caller function. | |
944 | * | |
945 | * Hidden parameter save area: | |
946 | * | |
947 | * This area stores the start address of the return value storage | |
948 | * area for a struct/union return function. | |
949 | * When a struct/union is used as the return value, the caller | |
950 | * function stores the return value storage area start address in | |
951 | * register GR3 and passes it to the caller function. | |
952 | * The callee function interprets the address stored in the GR3 | |
953 | * as the return value storage area start address. | |
954 | * When register GR3 needs to be saved into memory, the callee | |
955 | * function saves it in the hidden parameter save area. This | |
956 | * area is not secured when the save operation is not needed. | |
957 | * | |
958 | * Return address(LR) storage area: | |
959 | * | |
960 | * This area saves the LR. The LR stores the address of a return to the caller | |
961 | * function for the purpose of function calling. | |
962 | * | |
963 | * Argument register area: | |
964 | * | |
965 | * This area saves the argument register. This area is not secured when the | |
966 | * save operation is not needed. | |
967 | * | |
968 | * Argument: | |
969 | * | |
970 | * Arguments, the count of which equals the count of argument registers (6 | |
971 | * words), are positioned in registers GR8 to GR13 and delivered to the callee | |
972 | * function. When a struct/union return function is called, the return value | |
973 | * area address is stored in register GR3. Arguments not placed in the | |
974 | * argument registers will be stored in the stack argument area for transfer | |
975 | * purposes. When an 8-byte type argument is to be delivered using registers, | |
976 | * it is divided into two and placed in two registers for transfer. When | |
977 | * argument registers must be saved to memory, the callee function secures an | |
978 | * argument register save area in the stack. In this case, a continuous | |
979 | * argument register save area must be established in the parameter area. The | |
980 | * argument register save area must be allocated as needed to cover the size of | |
981 | * the argument register to be saved. If the function has a variable count of | |
982 | * arguments, it saves all argument registers in the argument register save | |
983 | * area. | |
984 | * | |
985 | * Argument Extension Format: | |
986 | * | |
987 | * When an argument is to be stored in the stack, its type is converted to an | |
988 | * extended type in accordance with the individual argument type. The argument | |
989 | * is freed by the caller function after the return from the callee function is | |
990 | * made. | |
991 | * | |
992 | * +-----------------------+---------------+------------------------+ | |
993 | * | Argument Type |Extended Type |Stack Storage Size(byte)| | |
994 | * +-----------------------+---------------+------------------------+ | |
995 | * |char |int | 4 | | |
996 | * |signed char |int | 4 | | |
997 | * |unsigned char |int | 4 | | |
998 | * |[signed] short int |int | 4 | | |
999 | * |unsigned short int |int | 4 | | |
1000 | * |[signed] int |No extension | 4 | | |
1001 | * |unsigned int |No extension | 4 | | |
1002 | * |[signed] long int |No extension | 4 | | |
1003 | * |unsigned long int |No extension | 4 | | |
1004 | * |[signed] long long int |No extension | 8 | | |
1005 | * |unsigned long long int |No extension | 8 | | |
1006 | * |float |double | 8 | | |
1007 | * |double |No extension | 8 | | |
1008 | * |long double |No extension | 8 | | |
1009 | * |pointer |No extension | 4 | | |
1010 | * |struct/union |- | 4 (*1) | | |
1011 | * +-----------------------+---------------+------------------------+ | |
1012 | * | |
1013 | * When a struct/union is to be delivered as an argument, the caller copies it | |
1014 | * to the local variable area and delivers the address of that area. | |
1015 | * | |
1016 | * Return Value: | |
1017 | * | |
1018 | * +-------------------------------+----------------------+ | |
1019 | * |Return Value Type |Return Value Interface| | |
1020 | * +-------------------------------+----------------------+ | |
1021 | * |void |None | | |
1022 | * |[signed|unsigned] char |GR8 | | |
1023 | * |[signed|unsigned] short int |GR8 | | |
1024 | * |[signed|unsigned] int |GR8 | | |
1025 | * |[signed|unsigned] long int |GR8 | | |
1026 | * |pointer |GR8 | | |
1027 | * |[signed|unsigned] long long int|GR8 & GR9 | | |
1028 | * |float |GR8 | | |
1029 | * |double |GR8 & GR9 | | |
1030 | * |long double |GR8 & GR9 | | |
1031 | * |struct/union |(*1) | | |
1032 | * +-------------------------------+----------------------+ | |
1033 | * | |
1034 | * When a struct/union is used as the return value, the caller function stores | |
1035 | * the start address of the return value storage area into GR3 and then passes | |
1036 | * it to the callee function. The callee function interprets GR3 as the start | |
1037 | * address of the return value storage area. When this address needs to be | |
1038 | * saved in memory, the callee function secures the hidden parameter save area | |
1039 | * and saves the address in that area. | |
1040 | */ | |
1041 | ||
1042 | frv_stack_t * | |
f2206911 | 1043 | frv_stack_info (void) |
36a05131 BS |
1044 | { |
1045 | static frv_stack_t info, zero_info; | |
1046 | frv_stack_t *info_ptr = &info; | |
1047 | tree fndecl = current_function_decl; | |
1048 | int varargs_p = 0; | |
1049 | tree cur_arg; | |
1050 | tree next_arg; | |
1051 | int range; | |
1052 | int alignment; | |
1053 | int offset; | |
1054 | ||
87b483a1 KH |
1055 | /* If we've already calculated the values and reload is complete, |
1056 | just return now. */ | |
36a05131 BS |
1057 | if (frv_stack_cache) |
1058 | return frv_stack_cache; | |
1059 | ||
87b483a1 | 1060 | /* Zero all fields. */ |
36a05131 BS |
1061 | info = zero_info; |
1062 | ||
87b483a1 | 1063 | /* Set up the register range information. */ |
36a05131 BS |
1064 | info_ptr->regs[STACK_REGS_GPR].name = "gpr"; |
1065 | info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1; | |
1066 | info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST; | |
1067 | info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE; | |
1068 | ||
1069 | info_ptr->regs[STACK_REGS_FPR].name = "fpr"; | |
1070 | info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST; | |
1071 | info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST; | |
1072 | info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE; | |
1073 | ||
1074 | info_ptr->regs[STACK_REGS_LR].name = "lr"; | |
1075 | info_ptr->regs[STACK_REGS_LR].first = LR_REGNO; | |
1076 | info_ptr->regs[STACK_REGS_LR].last = LR_REGNO; | |
1077 | info_ptr->regs[STACK_REGS_LR].special_p = 1; | |
1078 | ||
1079 | info_ptr->regs[STACK_REGS_CC].name = "cc"; | |
1080 | info_ptr->regs[STACK_REGS_CC].first = CC_FIRST; | |
1081 | info_ptr->regs[STACK_REGS_CC].last = CC_LAST; | |
1082 | info_ptr->regs[STACK_REGS_CC].field_p = TRUE; | |
1083 | ||
1084 | info_ptr->regs[STACK_REGS_LCR].name = "lcr"; | |
1085 | info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO; | |
1086 | info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO; | |
1087 | ||
1088 | info_ptr->regs[STACK_REGS_STDARG].name = "stdarg"; | |
1089 | info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM; | |
1090 | info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM; | |
1091 | info_ptr->regs[STACK_REGS_STDARG].dword_p = 1; | |
1092 | info_ptr->regs[STACK_REGS_STDARG].special_p = 1; | |
1093 | ||
1094 | info_ptr->regs[STACK_REGS_STRUCT].name = "struct"; | |
8ac411c7 KH |
1095 | info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM; |
1096 | info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM; | |
36a05131 BS |
1097 | info_ptr->regs[STACK_REGS_STRUCT].special_p = 1; |
1098 | ||
1099 | info_ptr->regs[STACK_REGS_FP].name = "fp"; | |
1100 | info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM; | |
1101 | info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM; | |
1102 | info_ptr->regs[STACK_REGS_FP].special_p = 1; | |
1103 | ||
1104 | /* Determine if this is a stdarg function. If so, allocate space to store | |
1105 | the 6 arguments. */ | |
1106 | if (cfun->stdarg) | |
1107 | varargs_p = 1; | |
1108 | ||
1109 | else | |
1110 | { | |
1111 | /* Find the last argument, and see if it is __builtin_va_alist. */ | |
1112 | for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg) | |
1113 | { | |
1114 | next_arg = TREE_CHAIN (cur_arg); | |
1115 | if (next_arg == (tree)0) | |
1116 | { | |
1117 | if (DECL_NAME (cur_arg) | |
1118 | && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist")) | |
1119 | varargs_p = 1; | |
1120 | ||
1121 | break; | |
1122 | } | |
1123 | } | |
1124 | } | |
1125 | ||
87b483a1 | 1126 | /* Iterate over all of the register ranges. */ |
36a05131 BS |
1127 | for (range = 0; range < STACK_REGS_MAX; range++) |
1128 | { | |
1129 | frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); | |
1130 | int first = reg_ptr->first; | |
1131 | int last = reg_ptr->last; | |
1132 | int size_1word = 0; | |
1133 | int size_2words = 0; | |
1134 | int regno; | |
1135 | ||
87b483a1 | 1136 | /* Calculate which registers need to be saved & save area size. */ |
36a05131 BS |
1137 | switch (range) |
1138 | { | |
1139 | default: | |
1140 | for (regno = first; regno <= last; regno++) | |
1141 | { | |
1142 | if ((regs_ever_live[regno] && !call_used_regs[regno]) | |
1143 | || (current_function_calls_eh_return | |
1144 | && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM)) | |
34208acf AO |
1145 | || (!TARGET_FDPIC && flag_pic |
1146 | && cfun->uses_pic_offset_table && regno == PIC_REGNO)) | |
36a05131 BS |
1147 | { |
1148 | info_ptr->save_p[regno] = REG_SAVE_1WORD; | |
1149 | size_1word += UNITS_PER_WORD; | |
1150 | } | |
1151 | } | |
1152 | break; | |
1153 | ||
1154 | /* Calculate whether we need to create a frame after everything else | |
1155 | has been processed. */ | |
1156 | case STACK_REGS_FP: | |
1157 | break; | |
1158 | ||
1159 | case STACK_REGS_LR: | |
1160 | if (regs_ever_live[LR_REGNO] | |
1161 | || profile_flag | |
34208acf AO |
1162 | /* This is set for __builtin_return_address, etc. */ |
1163 | || cfun->machine->frame_needed | |
1164 | || (TARGET_LINKED_FP && frame_pointer_needed) | |
1165 | || (!TARGET_FDPIC && flag_pic | |
1166 | && cfun->uses_pic_offset_table)) | |
36a05131 BS |
1167 | { |
1168 | info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD; | |
1169 | size_1word += UNITS_PER_WORD; | |
1170 | } | |
1171 | break; | |
1172 | ||
1173 | case STACK_REGS_STDARG: | |
1174 | if (varargs_p) | |
1175 | { | |
87b483a1 KH |
1176 | /* If this is a stdarg function with a non varardic |
1177 | argument split between registers and the stack, | |
1178 | adjust the saved registers downward. */ | |
36a05131 BS |
1179 | last -= (ADDR_ALIGN (cfun->pretend_args_size, UNITS_PER_WORD) |
1180 | / UNITS_PER_WORD); | |
1181 | ||
1182 | for (regno = first; regno <= last; regno++) | |
1183 | { | |
1184 | info_ptr->save_p[regno] = REG_SAVE_1WORD; | |
1185 | size_1word += UNITS_PER_WORD; | |
1186 | } | |
1187 | ||
1188 | info_ptr->stdarg_size = size_1word; | |
1189 | } | |
1190 | break; | |
1191 | ||
1192 | case STACK_REGS_STRUCT: | |
1193 | if (cfun->returns_struct) | |
1194 | { | |
8ac411c7 | 1195 | info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD; |
36a05131 BS |
1196 | size_1word += UNITS_PER_WORD; |
1197 | } | |
1198 | break; | |
1199 | } | |
1200 | ||
1201 | ||
1202 | if (size_1word) | |
1203 | { | |
87b483a1 | 1204 | /* If this is a field, it only takes one word. */ |
36a05131 BS |
1205 | if (reg_ptr->field_p) |
1206 | size_1word = UNITS_PER_WORD; | |
1207 | ||
87b483a1 | 1208 | /* Determine which register pairs can be saved together. */ |
36a05131 BS |
1209 | else if (reg_ptr->dword_p && TARGET_DWORD) |
1210 | { | |
1211 | for (regno = first; regno < last; regno += 2) | |
1212 | { | |
1213 | if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1]) | |
1214 | { | |
1215 | size_2words += 2 * UNITS_PER_WORD; | |
1216 | size_1word -= 2 * UNITS_PER_WORD; | |
1217 | info_ptr->save_p[regno] = REG_SAVE_2WORDS; | |
1218 | info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE; | |
1219 | } | |
1220 | } | |
1221 | } | |
1222 | ||
1223 | reg_ptr->size_1word = size_1word; | |
1224 | reg_ptr->size_2words = size_2words; | |
1225 | ||
1226 | if (! reg_ptr->special_p) | |
1227 | { | |
1228 | info_ptr->regs_size_1word += size_1word; | |
1229 | info_ptr->regs_size_2words += size_2words; | |
1230 | } | |
1231 | } | |
1232 | } | |
1233 | ||
1234 | /* Set up the sizes of each each field in the frame body, making the sizes | |
1235 | of each be divisible by the size of a dword if dword operations might | |
1236 | be used, or the size of a word otherwise. */ | |
1237 | alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD); | |
1238 | ||
1239 | info_ptr->parameter_size = ADDR_ALIGN (cfun->outgoing_args_size, alignment); | |
1240 | info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words | |
1241 | + info_ptr->regs_size_1word, | |
1242 | alignment); | |
1243 | info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment); | |
1244 | ||
1245 | info_ptr->pretend_size = cfun->pretend_args_size; | |
1246 | ||
1247 | /* Work out the size of the frame, excluding the header. Both the frame | |
1248 | body and register parameter area will be dword-aligned. */ | |
1249 | info_ptr->total_size | |
1250 | = (ADDR_ALIGN (info_ptr->parameter_size | |
1251 | + info_ptr->regs_size | |
1252 | + info_ptr->vars_size, | |
1253 | 2 * UNITS_PER_WORD) | |
1254 | + ADDR_ALIGN (info_ptr->pretend_size | |
1255 | + info_ptr->stdarg_size, | |
1256 | 2 * UNITS_PER_WORD)); | |
1257 | ||
1258 | /* See if we need to create a frame at all, if so add header area. */ | |
1259 | if (info_ptr->total_size > 0 | |
34208acf | 1260 | || frame_pointer_needed |
36a05131 BS |
1261 | || info_ptr->regs[STACK_REGS_LR].size_1word > 0 |
1262 | || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0) | |
1263 | { | |
1264 | offset = info_ptr->parameter_size; | |
1265 | info_ptr->header_size = 4 * UNITS_PER_WORD; | |
1266 | info_ptr->total_size += 4 * UNITS_PER_WORD; | |
1267 | ||
87b483a1 | 1268 | /* Calculate the offsets to save normal register pairs. */ |
36a05131 BS |
1269 | for (range = 0; range < STACK_REGS_MAX; range++) |
1270 | { | |
1271 | frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); | |
1272 | if (! reg_ptr->special_p) | |
1273 | { | |
1274 | int first = reg_ptr->first; | |
1275 | int last = reg_ptr->last; | |
1276 | int regno; | |
1277 | ||
1278 | for (regno = first; regno <= last; regno++) | |
1279 | if (info_ptr->save_p[regno] == REG_SAVE_2WORDS | |
1280 | && regno != FRAME_POINTER_REGNUM | |
1281 | && (regno < FIRST_ARG_REGNUM | |
1282 | || regno > LAST_ARG_REGNUM)) | |
1283 | { | |
1284 | info_ptr->reg_offset[regno] = offset; | |
1285 | offset += 2 * UNITS_PER_WORD; | |
1286 | } | |
1287 | } | |
1288 | } | |
1289 | ||
87b483a1 | 1290 | /* Calculate the offsets to save normal single registers. */ |
36a05131 BS |
1291 | for (range = 0; range < STACK_REGS_MAX; range++) |
1292 | { | |
1293 | frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); | |
1294 | if (! reg_ptr->special_p) | |
1295 | { | |
1296 | int first = reg_ptr->first; | |
1297 | int last = reg_ptr->last; | |
1298 | int regno; | |
1299 | ||
1300 | for (regno = first; regno <= last; regno++) | |
1301 | if (info_ptr->save_p[regno] == REG_SAVE_1WORD | |
1302 | && regno != FRAME_POINTER_REGNUM | |
1303 | && (regno < FIRST_ARG_REGNUM | |
1304 | || regno > LAST_ARG_REGNUM)) | |
1305 | { | |
1306 | info_ptr->reg_offset[regno] = offset; | |
1307 | offset += UNITS_PER_WORD; | |
1308 | } | |
1309 | } | |
1310 | } | |
1311 | ||
1312 | /* Calculate the offset to save the local variables at. */ | |
1313 | offset = ADDR_ALIGN (offset, alignment); | |
1314 | if (info_ptr->vars_size) | |
1315 | { | |
1316 | info_ptr->vars_offset = offset; | |
1317 | offset += info_ptr->vars_size; | |
1318 | } | |
1319 | ||
1320 | /* Align header to a dword-boundary. */ | |
1321 | offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD); | |
1322 | ||
1323 | /* Calculate the offsets in the fixed frame. */ | |
1324 | info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD; | |
1325 | info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset; | |
1326 | info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD; | |
1327 | ||
1328 | info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD; | |
1329 | info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD; | |
1330 | info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD; | |
1331 | ||
1332 | if (cfun->returns_struct) | |
1333 | { | |
8ac411c7 KH |
1334 | info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD; |
1335 | info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD; | |
36a05131 BS |
1336 | info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD; |
1337 | } | |
1338 | ||
1339 | /* Calculate the offsets to store the arguments passed in registers | |
1340 | for stdarg functions. The register pairs are first and the single | |
1341 | register if any is last. The register save area starts on a | |
1342 | dword-boundary. */ | |
1343 | if (info_ptr->stdarg_size) | |
1344 | { | |
1345 | int first = info_ptr->regs[STACK_REGS_STDARG].first; | |
1346 | int last = info_ptr->regs[STACK_REGS_STDARG].last; | |
1347 | int regno; | |
1348 | ||
1349 | /* Skip the header. */ | |
1350 | offset += 4 * UNITS_PER_WORD; | |
1351 | for (regno = first; regno <= last; regno++) | |
1352 | { | |
1353 | if (info_ptr->save_p[regno] == REG_SAVE_2WORDS) | |
1354 | { | |
1355 | info_ptr->reg_offset[regno] = offset; | |
1356 | offset += 2 * UNITS_PER_WORD; | |
1357 | } | |
1358 | else if (info_ptr->save_p[regno] == REG_SAVE_1WORD) | |
1359 | { | |
1360 | info_ptr->reg_offset[regno] = offset; | |
1361 | offset += UNITS_PER_WORD; | |
1362 | } | |
1363 | } | |
1364 | } | |
1365 | } | |
1366 | ||
1367 | if (reload_completed) | |
1368 | frv_stack_cache = info_ptr; | |
1369 | ||
1370 | return info_ptr; | |
1371 | } | |
1372 | ||
1373 | \f | |
87b483a1 | 1374 | /* Print the information about the frv stack offsets, etc. when debugging. */ |
36a05131 BS |
1375 | |
1376 | void | |
f2206911 | 1377 | frv_debug_stack (frv_stack_t *info) |
36a05131 BS |
1378 | { |
1379 | int range; | |
1380 | ||
1381 | if (!info) | |
1382 | info = frv_stack_info (); | |
1383 | ||
1384 | fprintf (stderr, "\nStack information for function %s:\n", | |
1385 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
1386 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
1387 | : "<unknown>")); | |
1388 | ||
1389 | fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size); | |
1390 | fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size); | |
1391 | fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size); | |
1392 | fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n", | |
1393 | info->regs_size, info->regs_size_1word, info->regs_size_2words); | |
1394 | ||
1395 | fprintf (stderr, "\theader_size\t= %6d\n", info->header_size); | |
1396 | fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size); | |
1397 | fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset); | |
1398 | fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset); | |
1399 | ||
1400 | for (range = 0; range < STACK_REGS_MAX; range++) | |
1401 | { | |
1402 | frv_stack_regs_t *regs = &(info->regs[range]); | |
1403 | if ((regs->size_1word + regs->size_2words) > 0) | |
1404 | { | |
1405 | int first = regs->first; | |
1406 | int last = regs->last; | |
1407 | int regno; | |
1408 | ||
1409 | fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =", | |
1410 | regs->name, regs->size_1word + regs->size_2words, | |
1411 | regs->size_1word, regs->size_2words); | |
1412 | ||
1413 | for (regno = first; regno <= last; regno++) | |
1414 | { | |
1415 | if (info->save_p[regno] == REG_SAVE_1WORD) | |
1416 | fprintf (stderr, " %s (%d)", reg_names[regno], | |
1417 | info->reg_offset[regno]); | |
1418 | ||
1419 | else if (info->save_p[regno] == REG_SAVE_2WORDS) | |
1420 | fprintf (stderr, " %s-%s (%d)", reg_names[regno], | |
1421 | reg_names[regno+1], info->reg_offset[regno]); | |
1422 | } | |
1423 | ||
1424 | fputc ('\n', stderr); | |
1425 | } | |
1426 | } | |
1427 | ||
1428 | fflush (stderr); | |
1429 | } | |
1430 | ||
1431 | ||
1432 | \f | |
1433 | ||
c557edf4 RS |
1434 | /* Used during final to control the packing of insns. The value is |
1435 | 1 if the current instruction should be packed with the next one, | |
1436 | 0 if it shouldn't or -1 if packing is disabled altogether. */ | |
36a05131 BS |
1437 | |
1438 | static int frv_insn_packing_flag; | |
1439 | ||
1440 | /* True if the current function contains a far jump. */ | |
1441 | ||
1442 | static int | |
f2206911 | 1443 | frv_function_contains_far_jump (void) |
36a05131 BS |
1444 | { |
1445 | rtx insn = get_insns (); | |
1446 | while (insn != NULL | |
1447 | && !(GET_CODE (insn) == JUMP_INSN | |
1448 | /* Ignore tablejump patterns. */ | |
1449 | && GET_CODE (PATTERN (insn)) != ADDR_VEC | |
1450 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC | |
1451 | && get_attr_far_jump (insn) == FAR_JUMP_YES)) | |
1452 | insn = NEXT_INSN (insn); | |
1453 | return (insn != NULL); | |
1454 | } | |
1455 | ||
1456 | /* For the FRV, this function makes sure that a function with far jumps | |
1457 | will return correctly. It also does the VLIW packing. */ | |
1458 | ||
1459 | static void | |
f2206911 | 1460 | frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
36a05131 BS |
1461 | { |
1462 | /* If no frame was created, check whether the function uses a call | |
1463 | instruction to implement a far jump. If so, save the link in gr3 and | |
1464 | replace all returns to LR with returns to GR3. GR3 is used because it | |
1465 | is call-clobbered, because is not available to the register allocator, | |
1466 | and because all functions that take a hidden argument pointer will have | |
1467 | a stack frame. */ | |
1468 | if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ()) | |
1469 | { | |
1470 | rtx insn; | |
1471 | ||
1472 | /* Just to check that the above comment is true. */ | |
44e91694 | 1473 | gcc_assert (!regs_ever_live[GPR_FIRST + 3]); |
36a05131 BS |
1474 | |
1475 | /* Generate the instruction that saves the link register. */ | |
1476 | fprintf (file, "\tmovsg lr,gr3\n"); | |
1477 | ||
1478 | /* Replace the LR with GR3 in *return_internal patterns. The insn | |
1479 | will now return using jmpl @(gr3,0) rather than bralr. We cannot | |
1480 | simply emit a different assembly directive because bralr and jmpl | |
1481 | execute in different units. */ | |
1482 | for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn)) | |
1483 | if (GET_CODE (insn) == JUMP_INSN) | |
1484 | { | |
1485 | rtx pattern = PATTERN (insn); | |
1486 | if (GET_CODE (pattern) == PARALLEL | |
1487 | && XVECLEN (pattern, 0) >= 2 | |
1488 | && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN | |
1489 | && GET_CODE (XVECEXP (pattern, 0, 1)) == USE) | |
1490 | { | |
1491 | rtx address = XEXP (XVECEXP (pattern, 0, 1), 0); | |
1492 | if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO) | |
1493 | REGNO (address) = GPR_FIRST + 3; | |
1494 | } | |
1495 | } | |
1496 | } | |
1497 | ||
1498 | frv_pack_insns (); | |
c557edf4 RS |
1499 | |
1500 | /* Allow the garbage collector to free the nops created by frv_reorg. */ | |
1501 | memset (frv_nops, 0, sizeof (frv_nops)); | |
36a05131 BS |
1502 | } |
1503 | ||
1504 | \f | |
1505 | /* Return the next available temporary register in a given class. */ | |
1506 | ||
1507 | static rtx | |
f2206911 KC |
1508 | frv_alloc_temp_reg ( |
1509 | frv_tmp_reg_t *info, /* which registers are available */ | |
1510 | enum reg_class class, /* register class desired */ | |
1511 | enum machine_mode mode, /* mode to allocate register with */ | |
1512 | int mark_as_used, /* register not available after allocation */ | |
1513 | int no_abort) /* return NULL instead of aborting */ | |
36a05131 BS |
1514 | { |
1515 | int regno = info->next_reg[ (int)class ]; | |
1516 | int orig_regno = regno; | |
1517 | HARD_REG_SET *reg_in_class = ®_class_contents[ (int)class ]; | |
1518 | int i, nr; | |
1519 | ||
1520 | for (;;) | |
1521 | { | |
1522 | if (TEST_HARD_REG_BIT (*reg_in_class, regno) | |
1523 | && TEST_HARD_REG_BIT (info->regs, regno)) | |
1524 | break; | |
1525 | ||
1526 | if (++regno >= FIRST_PSEUDO_REGISTER) | |
1527 | regno = 0; | |
1528 | if (regno == orig_regno) | |
1529 | { | |
44e91694 NS |
1530 | gcc_assert (no_abort); |
1531 | return NULL_RTX; | |
36a05131 BS |
1532 | } |
1533 | } | |
1534 | ||
1535 | nr = HARD_REGNO_NREGS (regno, mode); | |
1536 | info->next_reg[ (int)class ] = regno + nr; | |
1537 | ||
1538 | if (mark_as_used) | |
1539 | for (i = 0; i < nr; i++) | |
1540 | CLEAR_HARD_REG_BIT (info->regs, regno+i); | |
1541 | ||
1542 | return gen_rtx_REG (mode, regno); | |
1543 | } | |
1544 | ||
1545 | \f | |
1546 | /* Return an rtx with the value OFFSET, which will either be a register or a | |
1547 | signed 12-bit integer. It can be used as the second operand in an "add" | |
1548 | instruction, or as the index in a load or store. | |
1549 | ||
1550 | The function returns a constant rtx if OFFSET is small enough, otherwise | |
1551 | it loads the constant into register OFFSET_REGNO and returns that. */ | |
1552 | static rtx | |
f2206911 | 1553 | frv_frame_offset_rtx (int offset) |
36a05131 BS |
1554 | { |
1555 | rtx offset_rtx = GEN_INT (offset); | |
1556 | if (IN_RANGE_P (offset, -2048, 2047)) | |
1557 | return offset_rtx; | |
1558 | else | |
1559 | { | |
1560 | rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO); | |
1561 | if (IN_RANGE_P (offset, -32768, 32767)) | |
1562 | emit_insn (gen_movsi (reg_rtx, offset_rtx)); | |
1563 | else | |
1564 | { | |
1565 | emit_insn (gen_movsi_high (reg_rtx, offset_rtx)); | |
1566 | emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx)); | |
1567 | } | |
1568 | return reg_rtx; | |
1569 | } | |
1570 | } | |
1571 | ||
1572 | /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The | |
1573 | prologue and epilogue uses such expressions to access the stack. */ | |
1574 | static rtx | |
f2206911 | 1575 | frv_frame_mem (enum machine_mode mode, rtx base, int offset) |
36a05131 BS |
1576 | { |
1577 | return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, | |
1578 | base, | |
1579 | frv_frame_offset_rtx (offset))); | |
1580 | } | |
1581 | ||
1582 | /* Generate a frame-related expression: | |
1583 | ||
1584 | (set REG (mem (plus (sp) (const_int OFFSET)))). | |
1585 | ||
1586 | Such expressions are used in FRAME_RELATED_EXPR notes for more complex | |
1587 | instructions. Marking the expressions as frame-related is superfluous if | |
1588 | the note contains just a single set. But if the note contains a PARALLEL | |
1589 | or SEQUENCE that has several sets, each set must be individually marked | |
1590 | as frame-related. */ | |
1591 | static rtx | |
f2206911 | 1592 | frv_dwarf_store (rtx reg, int offset) |
36a05131 BS |
1593 | { |
1594 | rtx set = gen_rtx_SET (VOIDmode, | |
1595 | gen_rtx_MEM (GET_MODE (reg), | |
1596 | plus_constant (stack_pointer_rtx, | |
1597 | offset)), | |
1598 | reg); | |
1599 | RTX_FRAME_RELATED_P (set) = 1; | |
1600 | return set; | |
1601 | } | |
1602 | ||
1603 | /* Emit a frame-related instruction whose pattern is PATTERN. The | |
1604 | instruction is the last in a sequence that cumulatively performs the | |
1605 | operation described by DWARF_PATTERN. The instruction is marked as | |
1606 | frame-related and has a REG_FRAME_RELATED_EXPR note containing | |
1607 | DWARF_PATTERN. */ | |
1608 | static void | |
f2206911 | 1609 | frv_frame_insn (rtx pattern, rtx dwarf_pattern) |
36a05131 BS |
1610 | { |
1611 | rtx insn = emit_insn (pattern); | |
1612 | RTX_FRAME_RELATED_P (insn) = 1; | |
1613 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
1614 | dwarf_pattern, | |
1615 | REG_NOTES (insn)); | |
1616 | } | |
1617 | ||
1618 | /* Emit instructions that transfer REG to or from the memory location (sp + | |
1619 | STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is | |
1620 | FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this | |
1621 | function to store registers and only the epilogue uses it to load them. | |
1622 | ||
1623 | The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET). | |
1624 | The generated instruction will use BASE as its base register. BASE may | |
1625 | simply be the stack pointer, but if several accesses are being made to a | |
1626 | region far away from the stack pointer, it may be more efficient to set | |
1627 | up a temporary instead. | |
b16c1435 | 1628 | |
36a05131 BS |
1629 | Store instructions will be frame-related and will be annotated with the |
1630 | overall effect of the store. Load instructions will be followed by a | |
1631 | (use) to prevent later optimizations from zapping them. | |
1632 | ||
1633 | The function takes care of the moves to and from SPRs, using TEMP_REGNO | |
1634 | as a temporary in such cases. */ | |
1635 | static void | |
f2206911 | 1636 | frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset) |
36a05131 BS |
1637 | { |
1638 | enum machine_mode mode = GET_MODE (reg); | |
1639 | rtx mem = frv_frame_mem (mode, | |
1640 | accessor->base, | |
1641 | stack_offset - accessor->base_offset); | |
1642 | ||
1643 | if (accessor->op == FRV_LOAD) | |
1644 | { | |
1645 | if (SPR_P (REGNO (reg))) | |
1646 | { | |
1647 | rtx temp = gen_rtx_REG (mode, TEMP_REGNO); | |
1648 | emit_insn (gen_rtx_SET (VOIDmode, temp, mem)); | |
1649 | emit_insn (gen_rtx_SET (VOIDmode, reg, temp)); | |
1650 | } | |
1651 | else | |
1652 | emit_insn (gen_rtx_SET (VOIDmode, reg, mem)); | |
1653 | emit_insn (gen_rtx_USE (VOIDmode, reg)); | |
1654 | } | |
1655 | else | |
1656 | { | |
1657 | if (SPR_P (REGNO (reg))) | |
1658 | { | |
1659 | rtx temp = gen_rtx_REG (mode, TEMP_REGNO); | |
1660 | emit_insn (gen_rtx_SET (VOIDmode, temp, reg)); | |
1661 | frv_frame_insn (gen_rtx_SET (Pmode, mem, temp), | |
1662 | frv_dwarf_store (reg, stack_offset)); | |
1663 | } | |
1664 | else if (GET_MODE (reg) == DImode) | |
1665 | { | |
1666 | /* For DImode saves, the dwarf2 version needs to be a SEQUENCE | |
1667 | with a separate save for each register. */ | |
1668 | rtx reg1 = gen_rtx_REG (SImode, REGNO (reg)); | |
1669 | rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1); | |
1670 | rtx set1 = frv_dwarf_store (reg1, stack_offset); | |
1671 | rtx set2 = frv_dwarf_store (reg2, stack_offset + 4); | |
1672 | frv_frame_insn (gen_rtx_SET (Pmode, mem, reg), | |
1673 | gen_rtx_PARALLEL (VOIDmode, | |
1674 | gen_rtvec (2, set1, set2))); | |
1675 | } | |
1676 | else | |
1677 | frv_frame_insn (gen_rtx_SET (Pmode, mem, reg), | |
1678 | frv_dwarf_store (reg, stack_offset)); | |
1679 | } | |
1680 | } | |
1681 | ||
1682 | /* A function that uses frv_frame_access to transfer a group of registers to | |
1683 | or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO | |
1684 | is the stack information generated by frv_stack_info, and REG_SET is the | |
1685 | number of the register set to transfer. */ | |
1686 | static void | |
f2206911 KC |
1687 | frv_frame_access_multi (frv_frame_accessor_t *accessor, |
1688 | frv_stack_t *info, | |
1689 | int reg_set) | |
36a05131 BS |
1690 | { |
1691 | frv_stack_regs_t *regs_info; | |
1692 | int regno; | |
1693 | ||
1694 | regs_info = &info->regs[reg_set]; | |
1695 | for (regno = regs_info->first; regno <= regs_info->last; regno++) | |
1696 | if (info->save_p[regno]) | |
1697 | frv_frame_access (accessor, | |
1698 | info->save_p[regno] == REG_SAVE_2WORDS | |
1699 | ? gen_rtx_REG (DImode, regno) | |
1700 | : gen_rtx_REG (SImode, regno), | |
1701 | info->reg_offset[regno]); | |
1702 | } | |
1703 | ||
1704 | /* Save or restore callee-saved registers that are kept outside the frame | |
1705 | header. The function saves the registers if OP is FRV_STORE and restores | |
1706 | them if OP is FRV_LOAD. INFO is the stack information generated by | |
1707 | frv_stack_info. */ | |
1708 | static void | |
f2206911 | 1709 | frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info) |
36a05131 BS |
1710 | { |
1711 | frv_frame_accessor_t accessor; | |
1712 | ||
1713 | accessor.op = op; | |
1714 | accessor.base = stack_pointer_rtx; | |
1715 | accessor.base_offset = 0; | |
1716 | frv_frame_access_multi (&accessor, info, STACK_REGS_GPR); | |
1717 | frv_frame_access_multi (&accessor, info, STACK_REGS_FPR); | |
1718 | frv_frame_access_multi (&accessor, info, STACK_REGS_LCR); | |
b16c1435 | 1719 | } |
36a05131 BS |
1720 | |
1721 | ||
1722 | /* Called after register allocation to add any instructions needed for the | |
1723 | prologue. Using a prologue insn is favored compared to putting all of the | |
b88cf82e KH |
1724 | instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since |
1725 | it allows the scheduler to intermix instructions with the saves of | |
1726 | the caller saved registers. In some cases, it might be necessary | |
1727 | to emit a barrier instruction as the last insn to prevent such | |
1728 | scheduling. | |
36a05131 BS |
1729 | |
1730 | Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1 | |
1731 | so that the debug info generation code can handle them properly. */ | |
1732 | void | |
f2206911 | 1733 | frv_expand_prologue (void) |
36a05131 BS |
1734 | { |
1735 | frv_stack_t *info = frv_stack_info (); | |
1736 | rtx sp = stack_pointer_rtx; | |
1737 | rtx fp = frame_pointer_rtx; | |
1738 | frv_frame_accessor_t accessor; | |
1739 | ||
1740 | if (TARGET_DEBUG_STACK) | |
1741 | frv_debug_stack (info); | |
1742 | ||
1743 | if (info->total_size == 0) | |
1744 | return; | |
1745 | ||
1746 | /* We're interested in three areas of the frame here: | |
1747 | ||
1748 | A: the register save area | |
1749 | B: the old FP | |
1750 | C: the header after B | |
1751 | ||
1752 | If the frame pointer isn't used, we'll have to set up A, B and C | |
1753 | using the stack pointer. If the frame pointer is used, we'll access | |
1754 | them as follows: | |
1755 | ||
1756 | A: set up using sp | |
1757 | B: set up using sp or a temporary (see below) | |
1758 | C: set up using fp | |
1759 | ||
1760 | We set up B using the stack pointer if the frame is small enough. | |
1761 | Otherwise, it's more efficient to copy the old stack pointer into a | |
1762 | temporary and use that. | |
1763 | ||
1764 | Note that it's important to make sure the prologue and epilogue use the | |
1765 | same registers to access A and C, since doing otherwise will confuse | |
1766 | the aliasing code. */ | |
1767 | ||
1768 | /* Set up ACCESSOR for accessing region B above. If the frame pointer | |
1769 | isn't used, the same method will serve for C. */ | |
1770 | accessor.op = FRV_STORE; | |
1771 | if (frame_pointer_needed && info->total_size > 2048) | |
1772 | { | |
1773 | rtx insn; | |
1774 | ||
1775 | accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO); | |
1776 | accessor.base_offset = info->total_size; | |
1777 | insn = emit_insn (gen_movsi (accessor.base, sp)); | |
1778 | } | |
1779 | else | |
1780 | { | |
1781 | accessor.base = stack_pointer_rtx; | |
1782 | accessor.base_offset = 0; | |
1783 | } | |
1784 | ||
1785 | /* Allocate the stack space. */ | |
1786 | { | |
1787 | rtx asm_offset = frv_frame_offset_rtx (-info->total_size); | |
1788 | rtx dwarf_offset = GEN_INT (-info->total_size); | |
1789 | ||
1790 | frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset), | |
1791 | gen_rtx_SET (Pmode, | |
1792 | sp, | |
1793 | gen_rtx_PLUS (Pmode, sp, dwarf_offset))); | |
1794 | } | |
1795 | ||
1796 | /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET) | |
1797 | and point the new one to that location. */ | |
1798 | if (frame_pointer_needed) | |
1799 | { | |
1800 | int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM]; | |
1801 | ||
1802 | /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is | |
1803 | based on ACCESSOR.BASE but DWARF_SRC is always based on the stack | |
1804 | pointer. */ | |
1805 | rtx asm_src = plus_constant (accessor.base, | |
1806 | fp_offset - accessor.base_offset); | |
1807 | rtx dwarf_src = plus_constant (sp, fp_offset); | |
1808 | ||
1809 | /* Store the old frame pointer at (sp + FP_OFFSET). */ | |
1810 | frv_frame_access (&accessor, fp, fp_offset); | |
1811 | ||
1812 | /* Set up the new frame pointer. */ | |
1813 | frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src), | |
1814 | gen_rtx_SET (VOIDmode, fp, dwarf_src)); | |
1815 | ||
1816 | /* Access region C from the frame pointer. */ | |
1817 | accessor.base = fp; | |
1818 | accessor.base_offset = fp_offset; | |
1819 | } | |
1820 | ||
1821 | /* Set up region C. */ | |
1822 | frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT); | |
1823 | frv_frame_access_multi (&accessor, info, STACK_REGS_LR); | |
1824 | frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG); | |
1825 | ||
1826 | /* Set up region A. */ | |
1827 | frv_frame_access_standard_regs (FRV_STORE, info); | |
1828 | ||
1829 | /* If this is a varargs/stdarg function, issue a blockage to prevent the | |
1830 | scheduler from moving loads before the stores saving the registers. */ | |
1831 | if (info->stdarg_size > 0) | |
1832 | emit_insn (gen_blockage ()); | |
1833 | ||
87b483a1 | 1834 | /* Set up pic register/small data register for this function. */ |
34208acf | 1835 | if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table) |
36a05131 BS |
1836 | emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO), |
1837 | gen_rtx_REG (Pmode, LR_REGNO), | |
1838 | gen_rtx_REG (SImode, OFFSET_REGNO))); | |
1839 | } | |
1840 | ||
1841 | \f | |
1842 | /* Under frv, all of the work is done via frv_expand_epilogue, but | |
839a4992 | 1843 | this function provides a convenient place to do cleanup. */ |
36a05131 BS |
1844 | |
1845 | static void | |
f2206911 KC |
1846 | frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED, |
1847 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
36a05131 BS |
1848 | { |
1849 | frv_stack_cache = (frv_stack_t *)0; | |
1850 | ||
87b483a1 | 1851 | /* Zap last used registers for conditional execution. */ |
fad205ff | 1852 | memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg)); |
36a05131 | 1853 | |
87b483a1 | 1854 | /* Release the bitmap of created insns. */ |
7b210806 | 1855 | BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap); |
36a05131 BS |
1856 | } |
1857 | ||
1858 | \f | |
1859 | /* Called after register allocation to add any instructions needed for the | |
43aa4e05 | 1860 | epilogue. Using an epilogue insn is favored compared to putting all of the |
b88cf82e KH |
1861 | instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since |
1862 | it allows the scheduler to intermix instructions with the saves of | |
1863 | the caller saved registers. In some cases, it might be necessary | |
1864 | to emit a barrier instruction as the last insn to prevent such | |
c557edf4 | 1865 | scheduling. */ |
36a05131 BS |
1866 | |
1867 | void | |
764678d1 | 1868 | frv_expand_epilogue (bool emit_return) |
36a05131 BS |
1869 | { |
1870 | frv_stack_t *info = frv_stack_info (); | |
1871 | rtx fp = frame_pointer_rtx; | |
1872 | rtx sp = stack_pointer_rtx; | |
1873 | rtx return_addr; | |
1874 | int fp_offset; | |
1875 | ||
1876 | fp_offset = info->reg_offset[FRAME_POINTER_REGNUM]; | |
1877 | ||
1878 | /* Restore the stack pointer to its original value if alloca or the like | |
1879 | is used. */ | |
1880 | if (! current_function_sp_is_unchanging) | |
1881 | emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset))); | |
1882 | ||
1883 | /* Restore the callee-saved registers that were used in this function. */ | |
1884 | frv_frame_access_standard_regs (FRV_LOAD, info); | |
1885 | ||
1886 | /* Set RETURN_ADDR to the address we should return to. Set it to NULL if | |
1887 | no return instruction should be emitted. */ | |
764678d1 | 1888 | if (info->save_p[LR_REGNO]) |
36a05131 BS |
1889 | { |
1890 | int lr_offset; | |
1891 | rtx mem; | |
1892 | ||
1893 | /* Use the same method to access the link register's slot as we did in | |
1894 | the prologue. In other words, use the frame pointer if available, | |
1895 | otherwise use the stack pointer. | |
1896 | ||
1897 | LR_OFFSET is the offset of the link register's slot from the start | |
1898 | of the frame and MEM is a memory rtx for it. */ | |
1899 | lr_offset = info->reg_offset[LR_REGNO]; | |
1900 | if (frame_pointer_needed) | |
1901 | mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset); | |
1902 | else | |
1903 | mem = frv_frame_mem (Pmode, sp, lr_offset); | |
1904 | ||
1905 | /* Load the old link register into a GPR. */ | |
1906 | return_addr = gen_rtx_REG (Pmode, TEMP_REGNO); | |
1907 | emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem)); | |
1908 | } | |
1909 | else | |
1910 | return_addr = gen_rtx_REG (Pmode, LR_REGNO); | |
1911 | ||
1912 | /* Restore the old frame pointer. Emit a USE afterwards to make sure | |
1913 | the load is preserved. */ | |
1914 | if (frame_pointer_needed) | |
1915 | { | |
1916 | emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp))); | |
1917 | emit_insn (gen_rtx_USE (VOIDmode, fp)); | |
1918 | } | |
1919 | ||
1920 | /* Deallocate the stack frame. */ | |
1921 | if (info->total_size != 0) | |
1922 | { | |
1923 | rtx offset = frv_frame_offset_rtx (info->total_size); | |
1924 | emit_insn (gen_stack_adjust (sp, sp, offset)); | |
1925 | } | |
1926 | ||
1927 | /* If this function uses eh_return, add the final stack adjustment now. */ | |
1928 | if (current_function_calls_eh_return) | |
1929 | emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX)); | |
1930 | ||
764678d1 | 1931 | if (emit_return) |
36a05131 | 1932 | emit_jump_insn (gen_epilogue_return (return_addr)); |
764678d1 AO |
1933 | else |
1934 | { | |
1935 | rtx lr = return_addr; | |
1936 | ||
1937 | if (REGNO (return_addr) != LR_REGNO) | |
1938 | { | |
1939 | lr = gen_rtx_REG (Pmode, LR_REGNO); | |
1940 | emit_move_insn (lr, return_addr); | |
1941 | } | |
1942 | ||
1943 | emit_insn (gen_rtx_USE (VOIDmode, lr)); | |
1944 | } | |
36a05131 BS |
1945 | } |
1946 | ||
1947 | \f | |
b88cf82e | 1948 | /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */ |
36a05131 | 1949 | |
c590b625 | 1950 | static void |
f2206911 KC |
1951 | frv_asm_output_mi_thunk (FILE *file, |
1952 | tree thunk_fndecl ATTRIBUTE_UNUSED, | |
1953 | HOST_WIDE_INT delta, | |
1954 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
1955 | tree function) | |
36a05131 BS |
1956 | { |
1957 | const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0); | |
1958 | const char *name_arg0 = reg_names[FIRST_ARG_REGNUM]; | |
1959 | const char *name_jmp = reg_names[JUMP_REGNO]; | |
c557edf4 | 1960 | const char *parallel = (frv_issue_rate () > 1 ? ".p" : ""); |
36a05131 | 1961 | |
87b483a1 | 1962 | /* Do the add using an addi if possible. */ |
36a05131 | 1963 | if (IN_RANGE_P (delta, -2048, 2047)) |
eb0424da | 1964 | fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0); |
36a05131 BS |
1965 | else |
1966 | { | |
4a0a75dd KG |
1967 | const char *const name_add = reg_names[TEMP_REGNO]; |
1968 | fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n", | |
1969 | parallel, delta, name_add); | |
1970 | fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n", | |
1971 | delta, name_add); | |
36a05131 BS |
1972 | fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0); |
1973 | } | |
1974 | ||
34208acf AO |
1975 | if (TARGET_FDPIC) |
1976 | { | |
1977 | const char *name_pic = reg_names[FDPIC_REGNO]; | |
1978 | name_jmp = reg_names[FDPIC_FPTR_REGNO]; | |
1979 | ||
1980 | if (flag_pic != 1) | |
1981 | { | |
1982 | fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel); | |
1983 | assemble_name (file, name_func); | |
1984 | fprintf (file, "),%s\n", name_jmp); | |
1985 | ||
1986 | fprintf (file, "\tsetlo #gotofffuncdesclo("); | |
1987 | assemble_name (file, name_func); | |
1988 | fprintf (file, "),%s\n", name_jmp); | |
1989 | ||
1990 | fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp); | |
1991 | } | |
1992 | else | |
1993 | { | |
1994 | fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic); | |
1995 | assemble_name (file, name_func); | |
1996 | fprintf (file, "\t)), %s\n", name_jmp); | |
1997 | } | |
1998 | } | |
1999 | else if (!flag_pic) | |
36a05131 BS |
2000 | { |
2001 | fprintf (file, "\tsethi%s #hi(", parallel); | |
2002 | assemble_name (file, name_func); | |
2003 | fprintf (file, "),%s\n", name_jmp); | |
2004 | ||
2005 | fprintf (file, "\tsetlo #lo("); | |
2006 | assemble_name (file, name_func); | |
2007 | fprintf (file, "),%s\n", name_jmp); | |
2008 | } | |
2009 | else | |
2010 | { | |
2011 | /* Use JUMP_REGNO as a temporary PIC register. */ | |
2012 | const char *name_lr = reg_names[LR_REGNO]; | |
2013 | const char *name_gppic = name_jmp; | |
2014 | const char *name_tmp = reg_names[TEMP_REGNO]; | |
2015 | ||
2016 | fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp); | |
2017 | fprintf (file, "\tcall 1f\n"); | |
2018 | fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic); | |
2019 | fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr); | |
2020 | fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp); | |
2021 | fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp); | |
2022 | fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic); | |
2023 | ||
2024 | fprintf (file, "\tsethi%s #gprelhi(", parallel); | |
2025 | assemble_name (file, name_func); | |
2026 | fprintf (file, "),%s\n", name_tmp); | |
2027 | ||
2028 | fprintf (file, "\tsetlo #gprello("); | |
2029 | assemble_name (file, name_func); | |
2030 | fprintf (file, "),%s\n", name_tmp); | |
2031 | ||
2032 | fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp); | |
2033 | } | |
2034 | ||
87b483a1 | 2035 | /* Jump to the function address. */ |
36a05131 BS |
2036 | fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]); |
2037 | } | |
2038 | ||
2039 | \f | |
2040 | /* A C expression which is nonzero if a function must have and use a frame | |
2041 | pointer. This expression is evaluated in the reload pass. If its value is | |
2042 | nonzero the function will have a frame pointer. | |
2043 | ||
2044 | The expression can in principle examine the current function and decide | |
2045 | according to the facts, but on most machines the constant 0 or the constant | |
2046 | 1 suffices. Use 0 when the machine allows code to be generated with no | |
2047 | frame pointer, and doing so saves some time or space. Use 1 when there is | |
2048 | no possible advantage to avoiding a frame pointer. | |
2049 | ||
2050 | In certain cases, the compiler does not know how to produce valid code | |
2051 | without a frame pointer. The compiler recognizes those cases and | |
2052 | automatically gives the function a frame pointer regardless of what | |
2053 | `FRAME_POINTER_REQUIRED' says. You don't need to worry about them. | |
2054 | ||
2055 | In a function that does not require a frame pointer, the frame pointer | |
2056 | register can be allocated for ordinary usage, unless you mark it as a fixed | |
2057 | register. See `FIXED_REGISTERS' for more information. */ | |
2058 | ||
87b483a1 | 2059 | /* On frv, create a frame whenever we need to create stack. */ |
36a05131 BS |
2060 | |
2061 | int | |
f2206911 | 2062 | frv_frame_pointer_required (void) |
36a05131 | 2063 | { |
34208acf AO |
2064 | /* If we forgoing the usual linkage requirements, we only need |
2065 | a frame pointer if the stack pointer might change. */ | |
2066 | if (!TARGET_LINKED_FP) | |
2067 | return !current_function_sp_is_unchanging; | |
2068 | ||
36a05131 BS |
2069 | if (! current_function_is_leaf) |
2070 | return TRUE; | |
2071 | ||
2072 | if (get_frame_size () != 0) | |
2073 | return TRUE; | |
2074 | ||
2075 | if (cfun->stdarg) | |
2076 | return TRUE; | |
2077 | ||
2078 | if (!current_function_sp_is_unchanging) | |
2079 | return TRUE; | |
2080 | ||
34208acf | 2081 | if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table) |
36a05131 BS |
2082 | return TRUE; |
2083 | ||
2084 | if (profile_flag) | |
2085 | return TRUE; | |
2086 | ||
2087 | if (cfun->machine->frame_needed) | |
2088 | return TRUE; | |
2089 | ||
2090 | return FALSE; | |
2091 | } | |
2092 | ||
2093 | \f | |
2094 | /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the | |
2095 | initial difference between the specified pair of registers. This macro must | |
2096 | be defined if `ELIMINABLE_REGS' is defined. */ | |
2097 | ||
2098 | /* See frv_stack_info for more details on the frv stack frame. */ | |
2099 | ||
2100 | int | |
f2206911 | 2101 | frv_initial_elimination_offset (int from, int to) |
36a05131 BS |
2102 | { |
2103 | frv_stack_t *info = frv_stack_info (); | |
2104 | int ret = 0; | |
2105 | ||
2106 | if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM) | |
2107 | ret = info->total_size - info->pretend_size; | |
2108 | ||
2109 | else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM) | |
88d6a75f | 2110 | ret = info->reg_offset[FRAME_POINTER_REGNUM]; |
36a05131 BS |
2111 | |
2112 | else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM) | |
2113 | ret = (info->total_size | |
2114 | - info->reg_offset[FRAME_POINTER_REGNUM] | |
2115 | - info->pretend_size); | |
2116 | ||
2117 | else | |
44e91694 | 2118 | gcc_unreachable (); |
36a05131 BS |
2119 | |
2120 | if (TARGET_DEBUG_STACK) | |
2121 | fprintf (stderr, "Eliminate %s to %s by adding %d\n", | |
2122 | reg_names [from], reg_names[to], ret); | |
2123 | ||
2124 | return ret; | |
2125 | } | |
2126 | ||
2127 | \f | |
d8c2bed3 | 2128 | /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */ |
36a05131 | 2129 | |
d8c2bed3 | 2130 | static void |
f2206911 KC |
2131 | frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum, |
2132 | enum machine_mode mode, | |
2133 | tree type ATTRIBUTE_UNUSED, | |
2134 | int *pretend_size, | |
2135 | int second_time) | |
36a05131 BS |
2136 | { |
2137 | if (TARGET_DEBUG_ARG) | |
2138 | fprintf (stderr, | |
2139 | "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n", | |
2140 | *cum, GET_MODE_NAME (mode), *pretend_size, second_time); | |
2141 | } | |
2142 | ||
2143 | \f | |
b88cf82e | 2144 | /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */ |
36a05131 | 2145 | |
8ac411c7 | 2146 | static rtx |
f2206911 | 2147 | frv_expand_builtin_saveregs (void) |
36a05131 BS |
2148 | { |
2149 | int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS; | |
2150 | ||
2151 | if (TARGET_DEBUG_ARG) | |
2152 | fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n", | |
2153 | offset); | |
2154 | ||
f1c25d3b | 2155 | return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset)); |
36a05131 BS |
2156 | } |
2157 | ||
2158 | \f | |
2159 | /* Expand __builtin_va_start to do the va_start macro. */ | |
2160 | ||
2161 | void | |
f2206911 | 2162 | frv_expand_builtin_va_start (tree valist, rtx nextarg) |
36a05131 BS |
2163 | { |
2164 | tree t; | |
2165 | int num = cfun->args_info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS; | |
2166 | ||
2167 | nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, | |
2168 | GEN_INT (UNITS_PER_WORD * num)); | |
2169 | ||
2170 | if (TARGET_DEBUG_ARG) | |
2171 | { | |
2172 | fprintf (stderr, "va_start: args_info = %d, num = %d\n", | |
2173 | cfun->args_info, num); | |
2174 | ||
2175 | debug_rtx (nextarg); | |
2176 | } | |
2177 | ||
2178 | t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, | |
2179 | make_tree (ptr_type_node, nextarg)); | |
2180 | TREE_SIDE_EFFECTS (t) = 1; | |
2181 | ||
2182 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2183 | } | |
2184 | ||
36a05131 BS |
2185 | \f |
2186 | /* Expand a block move operation, and return 1 if successful. Return 0 | |
2187 | if we should let the compiler generate normal code. | |
2188 | ||
2189 | operands[0] is the destination | |
2190 | operands[1] is the source | |
2191 | operands[2] is the length | |
2192 | operands[3] is the alignment */ | |
2193 | ||
2194 | /* Maximum number of loads to do before doing the stores */ | |
2195 | #ifndef MAX_MOVE_REG | |
2196 | #define MAX_MOVE_REG 4 | |
2197 | #endif | |
2198 | ||
2199 | /* Maximum number of total loads to do. */ | |
2200 | #ifndef TOTAL_MOVE_REG | |
2201 | #define TOTAL_MOVE_REG 8 | |
2202 | #endif | |
2203 | ||
2204 | int | |
f2206911 | 2205 | frv_expand_block_move (rtx operands[]) |
36a05131 BS |
2206 | { |
2207 | rtx orig_dest = operands[0]; | |
2208 | rtx orig_src = operands[1]; | |
2209 | rtx bytes_rtx = operands[2]; | |
2210 | rtx align_rtx = operands[3]; | |
2211 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); | |
2212 | int align; | |
2213 | int bytes; | |
2214 | int offset; | |
2215 | int num_reg; | |
2216 | int i; | |
2217 | rtx src_reg; | |
2218 | rtx dest_reg; | |
2219 | rtx src_addr; | |
2220 | rtx dest_addr; | |
2221 | rtx src_mem; | |
2222 | rtx dest_mem; | |
2223 | rtx tmp_reg; | |
2224 | rtx stores[MAX_MOVE_REG]; | |
2225 | int move_bytes; | |
2226 | enum machine_mode mode; | |
2227 | ||
87b483a1 | 2228 | /* If this is not a fixed size move, just call memcpy. */ |
36a05131 BS |
2229 | if (! constp) |
2230 | return FALSE; | |
2231 | ||
44e91694 NS |
2232 | /* This should be a fixed size alignment. */ |
2233 | gcc_assert (GET_CODE (align_rtx) == CONST_INT); | |
36a05131 BS |
2234 | |
2235 | align = INTVAL (align_rtx); | |
2236 | ||
2237 | /* Anything to move? */ | |
2238 | bytes = INTVAL (bytes_rtx); | |
2239 | if (bytes <= 0) | |
2240 | return TRUE; | |
2241 | ||
2242 | /* Don't support real large moves. */ | |
2243 | if (bytes > TOTAL_MOVE_REG*align) | |
2244 | return FALSE; | |
2245 | ||
2246 | /* Move the address into scratch registers. */ | |
2247 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); | |
2248 | src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); | |
2249 | ||
2250 | num_reg = offset = 0; | |
2251 | for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) | |
2252 | { | |
87b483a1 | 2253 | /* Calculate the correct offset for src/dest. */ |
36a05131 BS |
2254 | if (offset == 0) |
2255 | { | |
2256 | src_addr = src_reg; | |
2257 | dest_addr = dest_reg; | |
2258 | } | |
2259 | else | |
2260 | { | |
2261 | src_addr = plus_constant (src_reg, offset); | |
2262 | dest_addr = plus_constant (dest_reg, offset); | |
2263 | } | |
2264 | ||
2265 | /* Generate the appropriate load and store, saving the stores | |
2266 | for later. */ | |
2267 | if (bytes >= 4 && align >= 4) | |
2268 | mode = SImode; | |
2269 | else if (bytes >= 2 && align >= 2) | |
2270 | mode = HImode; | |
2271 | else | |
2272 | mode = QImode; | |
2273 | ||
2274 | move_bytes = GET_MODE_SIZE (mode); | |
2275 | tmp_reg = gen_reg_rtx (mode); | |
2276 | src_mem = change_address (orig_src, mode, src_addr); | |
2277 | dest_mem = change_address (orig_dest, mode, dest_addr); | |
2278 | emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem)); | |
2279 | stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg); | |
2280 | ||
2281 | if (num_reg >= MAX_MOVE_REG) | |
2282 | { | |
2283 | for (i = 0; i < num_reg; i++) | |
2284 | emit_insn (stores[i]); | |
2285 | num_reg = 0; | |
2286 | } | |
2287 | } | |
2288 | ||
2289 | for (i = 0; i < num_reg; i++) | |
2290 | emit_insn (stores[i]); | |
2291 | ||
2292 | return TRUE; | |
2293 | } | |
2294 | ||
2295 | \f | |
2296 | /* Expand a block clear operation, and return 1 if successful. Return 0 | |
2297 | if we should let the compiler generate normal code. | |
2298 | ||
2299 | operands[0] is the destination | |
2300 | operands[1] is the length | |
57e84f18 | 2301 | operands[3] is the alignment */ |
36a05131 BS |
2302 | |
2303 | int | |
f2206911 | 2304 | frv_expand_block_clear (rtx operands[]) |
36a05131 BS |
2305 | { |
2306 | rtx orig_dest = operands[0]; | |
2307 | rtx bytes_rtx = operands[1]; | |
57e84f18 | 2308 | rtx align_rtx = operands[3]; |
36a05131 BS |
2309 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
2310 | int align; | |
2311 | int bytes; | |
2312 | int offset; | |
2313 | int num_reg; | |
2314 | rtx dest_reg; | |
2315 | rtx dest_addr; | |
2316 | rtx dest_mem; | |
2317 | int clear_bytes; | |
2318 | enum machine_mode mode; | |
2319 | ||
87b483a1 | 2320 | /* If this is not a fixed size move, just call memcpy. */ |
36a05131 BS |
2321 | if (! constp) |
2322 | return FALSE; | |
2323 | ||
44e91694 NS |
2324 | /* This should be a fixed size alignment. */ |
2325 | gcc_assert (GET_CODE (align_rtx) == CONST_INT); | |
36a05131 BS |
2326 | |
2327 | align = INTVAL (align_rtx); | |
2328 | ||
2329 | /* Anything to move? */ | |
2330 | bytes = INTVAL (bytes_rtx); | |
2331 | if (bytes <= 0) | |
2332 | return TRUE; | |
2333 | ||
2334 | /* Don't support real large clears. */ | |
2335 | if (bytes > TOTAL_MOVE_REG*align) | |
2336 | return FALSE; | |
2337 | ||
2338 | /* Move the address into a scratch register. */ | |
2339 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); | |
2340 | ||
2341 | num_reg = offset = 0; | |
2342 | for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes)) | |
2343 | { | |
87b483a1 | 2344 | /* Calculate the correct offset for src/dest. */ |
36a05131 BS |
2345 | dest_addr = ((offset == 0) |
2346 | ? dest_reg | |
2347 | : plus_constant (dest_reg, offset)); | |
2348 | ||
87b483a1 | 2349 | /* Generate the appropriate store of gr0. */ |
36a05131 BS |
2350 | if (bytes >= 4 && align >= 4) |
2351 | mode = SImode; | |
2352 | else if (bytes >= 2 && align >= 2) | |
2353 | mode = HImode; | |
2354 | else | |
2355 | mode = QImode; | |
2356 | ||
2357 | clear_bytes = GET_MODE_SIZE (mode); | |
2358 | dest_mem = change_address (orig_dest, mode, dest_addr); | |
2359 | emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx)); | |
2360 | } | |
2361 | ||
2362 | return TRUE; | |
2363 | } | |
2364 | ||
2365 | \f | |
2366 | /* The following variable is used to output modifiers of assembler | |
87b483a1 | 2367 | code of the current output insn. */ |
36a05131 BS |
2368 | |
2369 | static rtx *frv_insn_operands; | |
2370 | ||
2371 | /* The following function is used to add assembler insn code suffix .p | |
87b483a1 | 2372 | if it is necessary. */ |
36a05131 BS |
2373 | |
2374 | const char * | |
f2206911 | 2375 | frv_asm_output_opcode (FILE *f, const char *ptr) |
36a05131 BS |
2376 | { |
2377 | int c; | |
2378 | ||
c557edf4 | 2379 | if (frv_insn_packing_flag <= 0) |
36a05131 BS |
2380 | return ptr; |
2381 | ||
2382 | for (; *ptr && *ptr != ' ' && *ptr != '\t';) | |
2383 | { | |
2384 | c = *ptr++; | |
2385 | if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z') | |
2386 | || (*ptr >= 'A' && *ptr <= 'Z'))) | |
2387 | { | |
2388 | int letter = *ptr++; | |
2389 | ||
2390 | c = atoi (ptr); | |
2391 | frv_print_operand (f, frv_insn_operands [c], letter); | |
2392 | while ((c = *ptr) >= '0' && c <= '9') | |
2393 | ptr++; | |
2394 | } | |
2395 | else | |
2396 | fputc (c, f); | |
2397 | } | |
2398 | ||
c557edf4 | 2399 | fprintf (f, ".p"); |
36a05131 BS |
2400 | |
2401 | return ptr; | |
2402 | } | |
2403 | ||
c557edf4 RS |
2404 | /* Set up the packing bit for the current output insn. Note that this |
2405 | function is not called for asm insns. */ | |
36a05131 BS |
2406 | |
2407 | void | |
c557edf4 RS |
2408 | frv_final_prescan_insn (rtx insn, rtx *opvec, |
2409 | int noperands ATTRIBUTE_UNUSED) | |
36a05131 | 2410 | { |
c557edf4 | 2411 | if (INSN_P (insn)) |
36a05131 | 2412 | { |
c557edf4 RS |
2413 | if (frv_insn_packing_flag >= 0) |
2414 | { | |
2415 | frv_insn_operands = opvec; | |
2416 | frv_insn_packing_flag = PACKING_FLAG_P (insn); | |
2417 | } | |
2418 | else if (recog_memoized (insn) >= 0 | |
2419 | && get_attr_acc_group (insn) == ACC_GROUP_ODD) | |
2420 | /* Packing optimizations have been disabled, but INSN can only | |
2421 | be issued in M1. Insert an mnop in M0. */ | |
2422 | fprintf (asm_out_file, "\tmnop.p\n"); | |
36a05131 | 2423 | } |
36a05131 BS |
2424 | } |
2425 | ||
2426 | ||
2427 | \f | |
2428 | /* A C expression whose value is RTL representing the address in a stack frame | |
2429 | where the pointer to the caller's frame is stored. Assume that FRAMEADDR is | |
2430 | an RTL expression for the address of the stack frame itself. | |
2431 | ||
2432 | If you don't define this macro, the default is to return the value of | |
2433 | FRAMEADDR--that is, the stack frame address is also the address of the stack | |
2434 | word that points to the previous frame. */ | |
2435 | ||
2436 | /* The default is correct, but we need to make sure the frame gets created. */ | |
2437 | rtx | |
f2206911 | 2438 | frv_dynamic_chain_address (rtx frame) |
36a05131 BS |
2439 | { |
2440 | cfun->machine->frame_needed = 1; | |
2441 | return frame; | |
2442 | } | |
2443 | ||
2444 | ||
2445 | /* A C expression whose value is RTL representing the value of the return | |
2446 | address for the frame COUNT steps up from the current frame, after the | |
2447 | prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame | |
2448 | pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is | |
2449 | defined. | |
2450 | ||
2451 | The value of the expression must always be the correct address when COUNT is | |
2452 | zero, but may be `NULL_RTX' if there is not way to determine the return | |
2453 | address of other frames. */ | |
2454 | ||
2455 | rtx | |
34208acf | 2456 | frv_return_addr_rtx (int count, rtx frame) |
36a05131 | 2457 | { |
34208acf AO |
2458 | if (count != 0) |
2459 | return const0_rtx; | |
36a05131 BS |
2460 | cfun->machine->frame_needed = 1; |
2461 | return gen_rtx_MEM (Pmode, plus_constant (frame, 8)); | |
2462 | } | |
2463 | ||
2464 | /* Given a memory reference MEMREF, interpret the referenced memory as | |
2465 | an array of MODE values, and return a reference to the element | |
2466 | specified by INDEX. Assume that any pre-modification implicit in | |
2467 | MEMREF has already happened. | |
2468 | ||
2469 | MEMREF must be a legitimate operand for modes larger than SImode. | |
2470 | GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which | |
2471 | this function cannot handle. */ | |
2472 | rtx | |
f2206911 | 2473 | frv_index_memory (rtx memref, enum machine_mode mode, int index) |
36a05131 BS |
2474 | { |
2475 | rtx base = XEXP (memref, 0); | |
2476 | if (GET_CODE (base) == PRE_MODIFY) | |
2477 | base = XEXP (base, 0); | |
2478 | return change_address (memref, mode, | |
2479 | plus_constant (base, index * GET_MODE_SIZE (mode))); | |
2480 | } | |
2481 | ||
2482 | \f | |
2483 | /* Print a memory address as an operand to reference that memory location. */ | |
2484 | void | |
f2206911 | 2485 | frv_print_operand_address (FILE * stream, rtx x) |
36a05131 BS |
2486 | { |
2487 | if (GET_CODE (x) == MEM) | |
2488 | x = XEXP (x, 0); | |
2489 | ||
2490 | switch (GET_CODE (x)) | |
2491 | { | |
2492 | case REG: | |
2493 | fputs (reg_names [ REGNO (x)], stream); | |
2494 | return; | |
2495 | ||
2496 | case CONST_INT: | |
2497 | fprintf (stream, "%ld", (long) INTVAL (x)); | |
2498 | return; | |
2499 | ||
2500 | case SYMBOL_REF: | |
2501 | assemble_name (stream, XSTR (x, 0)); | |
2502 | return; | |
2503 | ||
2504 | case LABEL_REF: | |
2505 | case CONST: | |
2506 | output_addr_const (stream, x); | |
2507 | return; | |
2508 | ||
2509 | default: | |
2510 | break; | |
2511 | } | |
2512 | ||
2513 | fatal_insn ("Bad insn to frv_print_operand_address:", x); | |
2514 | } | |
2515 | ||
2516 | \f | |
2517 | static void | |
f2206911 | 2518 | frv_print_operand_memory_reference_reg (FILE * stream, rtx x) |
36a05131 BS |
2519 | { |
2520 | int regno = true_regnum (x); | |
2521 | if (GPR_P (regno)) | |
2522 | fputs (reg_names[regno], stream); | |
2523 | else | |
2524 | fatal_insn ("Bad register to frv_print_operand_memory_reference_reg:", x); | |
2525 | } | |
2526 | ||
2527 | /* Print a memory reference suitable for the ld/st instructions. */ | |
2528 | ||
2529 | static void | |
f2206911 | 2530 | frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset) |
36a05131 | 2531 | { |
34208acf | 2532 | struct frv_unspec unspec; |
36a05131 BS |
2533 | rtx x0 = NULL_RTX; |
2534 | rtx x1 = NULL_RTX; | |
2535 | ||
2536 | switch (GET_CODE (x)) | |
2537 | { | |
2538 | case SUBREG: | |
2539 | case REG: | |
2540 | x0 = x; | |
2541 | break; | |
2542 | ||
2543 | case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */ | |
2544 | x0 = XEXP (x, 0); | |
2545 | x1 = XEXP (XEXP (x, 1), 1); | |
2546 | break; | |
2547 | ||
2548 | case CONST_INT: | |
2549 | x1 = x; | |
2550 | break; | |
2551 | ||
2552 | case PLUS: | |
2553 | x0 = XEXP (x, 0); | |
2554 | x1 = XEXP (x, 1); | |
2555 | if (GET_CODE (x0) == CONST_INT) | |
2556 | { | |
2557 | x0 = XEXP (x, 1); | |
2558 | x1 = XEXP (x, 0); | |
2559 | } | |
2560 | break; | |
2561 | ||
2562 | default: | |
2563 | fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x); | |
2564 | break; | |
2565 | ||
2566 | } | |
2567 | ||
2568 | if (addr_offset) | |
2569 | { | |
2570 | if (!x1) | |
2571 | x1 = const0_rtx; | |
2572 | else if (GET_CODE (x1) != CONST_INT) | |
2573 | fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x); | |
2574 | } | |
2575 | ||
2576 | fputs ("@(", stream); | |
2577 | if (!x0) | |
2578 | fputs (reg_names[GPR_R0], stream); | |
2579 | else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG) | |
2580 | frv_print_operand_memory_reference_reg (stream, x0); | |
2581 | else | |
2582 | fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x); | |
2583 | ||
2584 | fputs (",", stream); | |
2585 | if (!x1) | |
2586 | fputs (reg_names [GPR_R0], stream); | |
2587 | ||
2588 | else | |
2589 | { | |
2590 | switch (GET_CODE (x1)) | |
2591 | { | |
2592 | case SUBREG: | |
2593 | case REG: | |
2594 | frv_print_operand_memory_reference_reg (stream, x1); | |
2595 | break; | |
2596 | ||
2597 | case CONST_INT: | |
2598 | fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset)); | |
2599 | break; | |
2600 | ||
36a05131 | 2601 | case CONST: |
34208acf AO |
2602 | if (!frv_const_unspec_p (x1, &unspec)) |
2603 | fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x1); | |
2604 | frv_output_const_unspec (stream, &unspec); | |
36a05131 BS |
2605 | break; |
2606 | ||
2607 | default: | |
2608 | fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x); | |
2609 | } | |
2610 | } | |
2611 | ||
2612 | fputs (")", stream); | |
2613 | } | |
2614 | ||
2615 | \f | |
2616 | /* Return 2 for likely branches and 0 for non-likely branches */ | |
2617 | ||
2618 | #define FRV_JUMP_LIKELY 2 | |
2619 | #define FRV_JUMP_NOT_LIKELY 0 | |
2620 | ||
2621 | static int | |
f2206911 | 2622 | frv_print_operand_jump_hint (rtx insn) |
36a05131 BS |
2623 | { |
2624 | rtx note; | |
2625 | rtx labelref; | |
2626 | int ret; | |
2627 | HOST_WIDE_INT prob = -1; | |
2628 | enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN; | |
2629 | ||
44e91694 | 2630 | gcc_assert (GET_CODE (insn) == JUMP_INSN); |
36a05131 BS |
2631 | |
2632 | /* Assume any non-conditional jump is likely. */ | |
2633 | if (! any_condjump_p (insn)) | |
2634 | ret = FRV_JUMP_LIKELY; | |
2635 | ||
2636 | else | |
2637 | { | |
2638 | labelref = condjump_label (insn); | |
2639 | if (labelref) | |
2640 | { | |
2641 | rtx label = XEXP (labelref, 0); | |
2642 | jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label)) | |
2643 | ? BACKWARD | |
2644 | : FORWARD); | |
2645 | } | |
2646 | ||
2647 | note = find_reg_note (insn, REG_BR_PROB, 0); | |
2648 | if (!note) | |
2649 | ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY); | |
2650 | ||
2651 | else | |
2652 | { | |
2653 | prob = INTVAL (XEXP (note, 0)); | |
2654 | ret = ((prob >= (REG_BR_PROB_BASE / 2)) | |
2655 | ? FRV_JUMP_LIKELY | |
2656 | : FRV_JUMP_NOT_LIKELY); | |
2657 | } | |
2658 | } | |
2659 | ||
2660 | #if 0 | |
2661 | if (TARGET_DEBUG) | |
2662 | { | |
2663 | char *direction; | |
2664 | ||
2665 | switch (jump_type) | |
2666 | { | |
2667 | default: | |
2668 | case UNKNOWN: direction = "unknown jump direction"; break; | |
2669 | case BACKWARD: direction = "jump backward"; break; | |
2670 | case FORWARD: direction = "jump forward"; break; | |
2671 | } | |
2672 | ||
2673 | fprintf (stderr, | |
2674 | "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n", | |
2675 | IDENTIFIER_POINTER (DECL_NAME (current_function_decl)), | |
2676 | (long)INSN_UID (insn), direction, (long)prob, | |
2677 | (long)REG_BR_PROB_BASE, ret); | |
2678 | } | |
2679 | #endif | |
2680 | ||
2681 | return ret; | |
2682 | } | |
2683 | ||
2684 | \f | |
036ff63f RS |
2685 | /* Return the comparison operator to use for CODE given that the ICC |
2686 | register is OP0. */ | |
2687 | ||
2688 | static const char * | |
2689 | comparison_string (enum rtx_code code, rtx op0) | |
2690 | { | |
2691 | bool is_nz_p = GET_MODE (op0) == CC_NZmode; | |
2692 | switch (code) | |
2693 | { | |
2694 | default: output_operand_lossage ("bad condition code"); | |
2695 | case EQ: return "eq"; | |
2696 | case NE: return "ne"; | |
2697 | case LT: return is_nz_p ? "n" : "lt"; | |
2698 | case LE: return "le"; | |
2699 | case GT: return "gt"; | |
2700 | case GE: return is_nz_p ? "p" : "ge"; | |
2701 | case LTU: return is_nz_p ? "no" : "c"; | |
2702 | case LEU: return is_nz_p ? "eq" : "ls"; | |
2703 | case GTU: return is_nz_p ? "ne" : "hi"; | |
2704 | case GEU: return is_nz_p ? "ra" : "nc"; | |
2705 | } | |
2706 | } | |
2707 | ||
43aa4e05 | 2708 | /* Print an operand to an assembler instruction. |
36a05131 BS |
2709 | |
2710 | `%' followed by a letter and a digit says to output an operand in an | |
2711 | alternate fashion. Four letters have standard, built-in meanings described | |
2712 | below. The machine description macro `PRINT_OPERAND' can define additional | |
2713 | letters with nonstandard meanings. | |
2714 | ||
2715 | `%cDIGIT' can be used to substitute an operand that is a constant value | |
2716 | without the syntax that normally indicates an immediate operand. | |
2717 | ||
2718 | `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated | |
2719 | before printing. | |
2720 | ||
2721 | `%aDIGIT' can be used to substitute an operand as if it were a memory | |
2722 | reference, with the actual operand treated as the address. This may be | |
2723 | useful when outputting a "load address" instruction, because often the | |
2724 | assembler syntax for such an instruction requires you to write the operand | |
2725 | as if it were a memory reference. | |
2726 | ||
2727 | `%lDIGIT' is used to substitute a `label_ref' into a jump instruction. | |
2728 | ||
2729 | `%=' outputs a number which is unique to each instruction in the entire | |
2730 | compilation. This is useful for making local labels to be referred to more | |
2731 | than once in a single template that generates multiple assembler | |
2732 | instructions. | |
2733 | ||
2734 | `%' followed by a punctuation character specifies a substitution that does | |
2735 | not use an operand. Only one case is standard: `%%' outputs a `%' into the | |
2736 | assembler code. Other nonstandard cases can be defined in the | |
2737 | `PRINT_OPERAND' macro. You must also define which punctuation characters | |
2738 | are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */ | |
2739 | ||
2740 | void | |
f2206911 | 2741 | frv_print_operand (FILE * file, rtx x, int code) |
36a05131 | 2742 | { |
34208acf | 2743 | struct frv_unspec unspec; |
36a05131 BS |
2744 | HOST_WIDE_INT value; |
2745 | int offset; | |
2746 | ||
2747 | if (code != 0 && !isalpha (code)) | |
2748 | value = 0; | |
2749 | ||
2750 | else if (GET_CODE (x) == CONST_INT) | |
2751 | value = INTVAL (x); | |
2752 | ||
2753 | else if (GET_CODE (x) == CONST_DOUBLE) | |
2754 | { | |
2755 | if (GET_MODE (x) == SFmode) | |
2756 | { | |
2757 | REAL_VALUE_TYPE rv; | |
2758 | long l; | |
2759 | ||
2760 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
2761 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
2762 | value = l; | |
2763 | } | |
2764 | ||
2765 | else if (GET_MODE (x) == VOIDmode) | |
2766 | value = CONST_DOUBLE_LOW (x); | |
2767 | ||
2768 | else | |
2769 | fatal_insn ("Bad insn in frv_print_operand, bad const_double", x); | |
2770 | } | |
2771 | ||
2772 | else | |
2773 | value = 0; | |
2774 | ||
2775 | switch (code) | |
2776 | { | |
2777 | ||
2778 | case '.': | |
87b483a1 | 2779 | /* Output r0. */ |
36a05131 BS |
2780 | fputs (reg_names[GPR_R0], file); |
2781 | break; | |
2782 | ||
2783 | case '#': | |
2784 | fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn)); | |
2785 | break; | |
2786 | ||
0f6e5d45 | 2787 | case '@': |
87b483a1 | 2788 | /* Output small data area base register (gr16). */ |
36a05131 BS |
2789 | fputs (reg_names[SDA_BASE_REG], file); |
2790 | break; | |
2791 | ||
2792 | case '~': | |
87b483a1 | 2793 | /* Output pic register (gr17). */ |
36a05131 BS |
2794 | fputs (reg_names[PIC_REGNO], file); |
2795 | break; | |
2796 | ||
2797 | case '*': | |
87b483a1 | 2798 | /* Output the temporary integer CCR register. */ |
36a05131 BS |
2799 | fputs (reg_names[ICR_TEMP], file); |
2800 | break; | |
2801 | ||
2802 | case '&': | |
87b483a1 | 2803 | /* Output the temporary integer CC register. */ |
36a05131 BS |
2804 | fputs (reg_names[ICC_TEMP], file); |
2805 | break; | |
2806 | ||
87b483a1 | 2807 | /* case 'a': print an address. */ |
36a05131 BS |
2808 | |
2809 | case 'C': | |
87b483a1 | 2810 | /* Print appropriate test for integer branch false operation. */ |
036ff63f RS |
2811 | fputs (comparison_string (reverse_condition (GET_CODE (x)), |
2812 | XEXP (x, 0)), file); | |
36a05131 BS |
2813 | break; |
2814 | ||
36a05131 | 2815 | case 'c': |
87b483a1 | 2816 | /* Print appropriate test for integer branch true operation. */ |
036ff63f | 2817 | fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file); |
36a05131 BS |
2818 | break; |
2819 | ||
2820 | case 'e': | |
2821 | /* Print 1 for a NE and 0 for an EQ to give the final argument | |
2822 | for a conditional instruction. */ | |
2823 | if (GET_CODE (x) == NE) | |
2824 | fputs ("1", file); | |
2825 | ||
2826 | else if (GET_CODE (x) == EQ) | |
2827 | fputs ("0", file); | |
2828 | ||
2829 | else | |
2830 | fatal_insn ("Bad insn to frv_print_operand, 'e' modifier:", x); | |
2831 | break; | |
2832 | ||
2833 | case 'F': | |
87b483a1 | 2834 | /* Print appropriate test for floating point branch false operation. */ |
36a05131 BS |
2835 | switch (GET_CODE (x)) |
2836 | { | |
2837 | default: | |
2838 | fatal_insn ("Bad insn to frv_print_operand, 'F' modifier:", x); | |
2839 | ||
2840 | case EQ: fputs ("ne", file); break; | |
2841 | case NE: fputs ("eq", file); break; | |
2842 | case LT: fputs ("uge", file); break; | |
2843 | case LE: fputs ("ug", file); break; | |
2844 | case GT: fputs ("ule", file); break; | |
2845 | case GE: fputs ("ul", file); break; | |
2846 | } | |
2847 | break; | |
2848 | ||
2849 | case 'f': | |
87b483a1 | 2850 | /* Print appropriate test for floating point branch true operation. */ |
36a05131 BS |
2851 | switch (GET_CODE (x)) |
2852 | { | |
2853 | default: | |
2854 | fatal_insn ("Bad insn to frv_print_operand, 'f' modifier:", x); | |
2855 | ||
2856 | case EQ: fputs ("eq", file); break; | |
2857 | case NE: fputs ("ne", file); break; | |
2858 | case LT: fputs ("lt", file); break; | |
2859 | case LE: fputs ("le", file); break; | |
2860 | case GT: fputs ("gt", file); break; | |
2861 | case GE: fputs ("ge", file); break; | |
2862 | } | |
2863 | break; | |
2864 | ||
34208acf AO |
2865 | case 'g': |
2866 | /* Print appropriate GOT function. */ | |
2867 | if (GET_CODE (x) != CONST_INT) | |
2868 | fatal_insn ("Bad insn to frv_print_operand, 'g' modifier:", x); | |
2869 | fputs (unspec_got_name (INTVAL (x)), file); | |
2870 | break; | |
2871 | ||
36a05131 BS |
2872 | case 'I': |
2873 | /* Print 'i' if the operand is a constant, or is a memory reference that | |
87b483a1 | 2874 | adds a constant. */ |
36a05131 BS |
2875 | if (GET_CODE (x) == MEM) |
2876 | x = ((GET_CODE (XEXP (x, 0)) == PLUS) | |
2877 | ? XEXP (XEXP (x, 0), 1) | |
2878 | : XEXP (x, 0)); | |
34208acf AO |
2879 | else if (GET_CODE (x) == PLUS) |
2880 | x = XEXP (x, 1); | |
36a05131 BS |
2881 | |
2882 | switch (GET_CODE (x)) | |
2883 | { | |
2884 | default: | |
2885 | break; | |
2886 | ||
2887 | case CONST_INT: | |
2888 | case SYMBOL_REF: | |
2889 | case CONST: | |
2890 | fputs ("i", file); | |
2891 | break; | |
2892 | } | |
2893 | break; | |
2894 | ||
2895 | case 'i': | |
2896 | /* For jump instructions, print 'i' if the operand is a constant or | |
87b483a1 | 2897 | is an expression that adds a constant. */ |
36a05131 BS |
2898 | if (GET_CODE (x) == CONST_INT) |
2899 | fputs ("i", file); | |
2900 | ||
2901 | else | |
2902 | { | |
2903 | if (GET_CODE (x) == CONST_INT | |
2904 | || (GET_CODE (x) == PLUS | |
2905 | && (GET_CODE (XEXP (x, 1)) == CONST_INT | |
2906 | || GET_CODE (XEXP (x, 0)) == CONST_INT))) | |
2907 | fputs ("i", file); | |
2908 | } | |
2909 | break; | |
2910 | ||
2911 | case 'L': | |
2912 | /* Print the lower register of a double word register pair */ | |
2913 | if (GET_CODE (x) == REG) | |
2914 | fputs (reg_names[ REGNO (x)+1 ], file); | |
2915 | else | |
2916 | fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x); | |
2917 | break; | |
2918 | ||
87b483a1 | 2919 | /* case 'l': print a LABEL_REF. */ |
36a05131 BS |
2920 | |
2921 | case 'M': | |
2922 | case 'N': | |
2923 | /* Print a memory reference for ld/st/jmp, %N prints a memory reference | |
2924 | for the second word of double memory operations. */ | |
2925 | offset = (code == 'M') ? 0 : UNITS_PER_WORD; | |
2926 | switch (GET_CODE (x)) | |
2927 | { | |
2928 | default: | |
2929 | fatal_insn ("Bad insn to frv_print_operand, 'M/N' modifier:", x); | |
2930 | ||
2931 | case MEM: | |
2932 | frv_print_operand_memory_reference (file, XEXP (x, 0), offset); | |
2933 | break; | |
2934 | ||
2935 | case REG: | |
2936 | case SUBREG: | |
2937 | case CONST_INT: | |
2938 | case PLUS: | |
2939 | case SYMBOL_REF: | |
2940 | frv_print_operand_memory_reference (file, x, offset); | |
2941 | break; | |
2942 | } | |
2943 | break; | |
2944 | ||
2945 | case 'O': | |
2946 | /* Print the opcode of a command. */ | |
2947 | switch (GET_CODE (x)) | |
2948 | { | |
2949 | default: | |
2950 | fatal_insn ("Bad insn to frv_print_operand, 'O' modifier:", x); | |
2951 | ||
2952 | case PLUS: fputs ("add", file); break; | |
2953 | case MINUS: fputs ("sub", file); break; | |
2954 | case AND: fputs ("and", file); break; | |
2955 | case IOR: fputs ("or", file); break; | |
2956 | case XOR: fputs ("xor", file); break; | |
2957 | case ASHIFT: fputs ("sll", file); break; | |
2958 | case ASHIFTRT: fputs ("sra", file); break; | |
2959 | case LSHIFTRT: fputs ("srl", file); break; | |
2960 | } | |
2961 | break; | |
2962 | ||
87b483a1 | 2963 | /* case 'n': negate and print a constant int. */ |
36a05131 BS |
2964 | |
2965 | case 'P': | |
2966 | /* Print PIC label using operand as the number. */ | |
2967 | if (GET_CODE (x) != CONST_INT) | |
2968 | fatal_insn ("Bad insn to frv_print_operand, P modifier:", x); | |
2969 | ||
2970 | fprintf (file, ".LCF%ld", (long)INTVAL (x)); | |
2971 | break; | |
2972 | ||
2973 | case 'U': | |
87b483a1 | 2974 | /* Print 'u' if the operand is a update load/store. */ |
36a05131 BS |
2975 | if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY) |
2976 | fputs ("u", file); | |
2977 | break; | |
2978 | ||
2979 | case 'z': | |
87b483a1 | 2980 | /* If value is 0, print gr0, otherwise it must be a register. */ |
36a05131 BS |
2981 | if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0) |
2982 | fputs (reg_names[GPR_R0], file); | |
2983 | ||
2984 | else if (GET_CODE (x) == REG) | |
2985 | fputs (reg_names [REGNO (x)], file); | |
2986 | ||
2987 | else | |
2988 | fatal_insn ("Bad insn in frv_print_operand, z case", x); | |
2989 | break; | |
2990 | ||
2991 | case 'x': | |
87b483a1 | 2992 | /* Print constant in hex. */ |
36a05131 BS |
2993 | if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) |
2994 | { | |
2995 | fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value); | |
2996 | break; | |
2997 | } | |
2998 | ||
87b483a1 | 2999 | /* Fall through. */ |
36a05131 BS |
3000 | |
3001 | case '\0': | |
3002 | if (GET_CODE (x) == REG) | |
3003 | fputs (reg_names [REGNO (x)], file); | |
3004 | ||
3005 | else if (GET_CODE (x) == CONST_INT | |
3006 | || GET_CODE (x) == CONST_DOUBLE) | |
3007 | fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value); | |
3008 | ||
34208acf AO |
3009 | else if (frv_const_unspec_p (x, &unspec)) |
3010 | frv_output_const_unspec (file, &unspec); | |
3011 | ||
36a05131 BS |
3012 | else if (GET_CODE (x) == MEM) |
3013 | frv_print_operand_address (file, XEXP (x, 0)); | |
3014 | ||
3015 | else if (CONSTANT_ADDRESS_P (x)) | |
3016 | frv_print_operand_address (file, x); | |
3017 | ||
3018 | else | |
3019 | fatal_insn ("Bad insn in frv_print_operand, 0 case", x); | |
3020 | ||
3021 | break; | |
3022 | ||
3023 | default: | |
3024 | fatal_insn ("frv_print_operand: unknown code", x); | |
3025 | break; | |
3026 | } | |
3027 | ||
3028 | return; | |
3029 | } | |
3030 | ||
3031 | \f | |
3032 | /* A C statement (sans semicolon) for initializing the variable CUM for the | |
3033 | state at the beginning of the argument list. The variable has type | |
3034 | `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type | |
3035 | of the function which will receive the args, or 0 if the args are to a | |
3036 | compiler support library function. The value of INDIRECT is nonzero when | |
3037 | processing an indirect call, for example a call through a function pointer. | |
3038 | The value of INDIRECT is zero for a call to an explicitly named function, a | |
3039 | library function call, or when `INIT_CUMULATIVE_ARGS' is used to find | |
3040 | arguments for the function being compiled. | |
3041 | ||
3042 | When processing a call to a compiler support library function, LIBNAME | |
3043 | identifies which one. It is a `symbol_ref' rtx which contains the name of | |
3044 | the function, as a string. LIBNAME is 0 when an ordinary C function call is | |
3045 | being processed. Thus, each time this macro is called, either LIBNAME or | |
3046 | FNTYPE is nonzero, but never both of them at once. */ | |
3047 | ||
3048 | void | |
f2206911 KC |
3049 | frv_init_cumulative_args (CUMULATIVE_ARGS *cum, |
3050 | tree fntype, | |
3051 | rtx libname, | |
3052 | tree fndecl, | |
3053 | int incoming) | |
36a05131 BS |
3054 | { |
3055 | *cum = FIRST_ARG_REGNUM; | |
3056 | ||
3057 | if (TARGET_DEBUG_ARG) | |
3058 | { | |
3059 | fprintf (stderr, "\ninit_cumulative_args:"); | |
563a317a | 3060 | if (!fndecl && fntype) |
36a05131 BS |
3061 | fputs (" indirect", stderr); |
3062 | ||
3063 | if (incoming) | |
3064 | fputs (" incoming", stderr); | |
3065 | ||
3066 | if (fntype) | |
3067 | { | |
3068 | tree ret_type = TREE_TYPE (fntype); | |
3069 | fprintf (stderr, " return=%s,", | |
3070 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
3071 | } | |
3072 | ||
3073 | if (libname && GET_CODE (libname) == SYMBOL_REF) | |
3074 | fprintf (stderr, " libname=%s", XSTR (libname, 0)); | |
3075 | ||
3076 | if (cfun->returns_struct) | |
3077 | fprintf (stderr, " return-struct"); | |
3078 | ||
3079 | putc ('\n', stderr); | |
3080 | } | |
3081 | } | |
3082 | ||
3083 | \f | |
fe984136 RH |
3084 | /* Return true if we should pass an argument on the stack rather than |
3085 | in registers. */ | |
3086 | ||
3087 | static bool | |
3088 | frv_must_pass_in_stack (enum machine_mode mode, tree type) | |
3089 | { | |
3090 | if (mode == BLKmode) | |
3091 | return true; | |
3092 | if (type == NULL) | |
3093 | return false; | |
3094 | return AGGREGATE_TYPE_P (type); | |
3095 | } | |
3096 | ||
36a05131 BS |
3097 | /* If defined, a C expression that gives the alignment boundary, in bits, of an |
3098 | argument with the specified mode and type. If it is not defined, | |
3099 | `PARM_BOUNDARY' is used for all arguments. */ | |
3100 | ||
3101 | int | |
f2206911 KC |
3102 | frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED, |
3103 | tree type ATTRIBUTE_UNUSED) | |
36a05131 BS |
3104 | { |
3105 | return BITS_PER_WORD; | |
3106 | } | |
3107 | ||
36a05131 | 3108 | rtx |
f2206911 KC |
3109 | frv_function_arg (CUMULATIVE_ARGS *cum, |
3110 | enum machine_mode mode, | |
3111 | tree type ATTRIBUTE_UNUSED, | |
3112 | int named, | |
3113 | int incoming ATTRIBUTE_UNUSED) | |
36a05131 BS |
3114 | { |
3115 | enum machine_mode xmode = (mode == BLKmode) ? SImode : mode; | |
3116 | int arg_num = *cum; | |
3117 | rtx ret; | |
3118 | const char *debstr; | |
3119 | ||
3120 | /* Return a marker for use in the call instruction. */ | |
3121 | if (xmode == VOIDmode) | |
3122 | { | |
3123 | ret = const0_rtx; | |
3124 | debstr = "<0>"; | |
3125 | } | |
3126 | ||
3127 | else if (arg_num <= LAST_ARG_REGNUM) | |
3128 | { | |
f1c25d3b | 3129 | ret = gen_rtx_REG (xmode, arg_num); |
36a05131 BS |
3130 | debstr = reg_names[arg_num]; |
3131 | } | |
3132 | ||
3133 | else | |
3134 | { | |
3135 | ret = NULL_RTX; | |
3136 | debstr = "memory"; | |
3137 | } | |
3138 | ||
3139 | if (TARGET_DEBUG_ARG) | |
3140 | fprintf (stderr, | |
3141 | "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n", | |
3142 | arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr); | |
3143 | ||
3144 | return ret; | |
3145 | } | |
3146 | ||
3147 | \f | |
3148 | /* A C statement (sans semicolon) to update the summarizer variable CUM to | |
3149 | advance past an argument in the argument list. The values MODE, TYPE and | |
3150 | NAMED describe that argument. Once this is done, the variable CUM is | |
3151 | suitable for analyzing the *following* argument with `FUNCTION_ARG', etc. | |
3152 | ||
3153 | This macro need not do anything if the argument in question was passed on | |
3154 | the stack. The compiler knows how to track the amount of stack space used | |
3155 | for arguments without any special help. */ | |
3156 | ||
3157 | void | |
f2206911 KC |
3158 | frv_function_arg_advance (CUMULATIVE_ARGS *cum, |
3159 | enum machine_mode mode, | |
3160 | tree type ATTRIBUTE_UNUSED, | |
3161 | int named) | |
36a05131 BS |
3162 | { |
3163 | enum machine_mode xmode = (mode == BLKmode) ? SImode : mode; | |
3164 | int bytes = GET_MODE_SIZE (xmode); | |
3165 | int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
3166 | int arg_num = *cum; | |
3167 | ||
3168 | *cum = arg_num + words; | |
3169 | ||
3170 | if (TARGET_DEBUG_ARG) | |
3171 | fprintf (stderr, | |
3172 | "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n", | |
3173 | arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD); | |
3174 | } | |
3175 | ||
3176 | \f | |
3177 | /* A C expression for the number of words, at the beginning of an argument, | |
3178 | must be put in registers. The value must be zero for arguments that are | |
3179 | passed entirely in registers or that are entirely pushed on the stack. | |
3180 | ||
3181 | On some machines, certain arguments must be passed partially in registers | |
3182 | and partially in memory. On these machines, typically the first N words of | |
3183 | arguments are passed in registers, and the rest on the stack. If a | |
3184 | multi-word argument (a `double' or a structure) crosses that boundary, its | |
3185 | first few words must be passed in registers and the rest must be pushed. | |
3186 | This macro tells the compiler when this occurs, and how many of the words | |
3187 | should go in registers. | |
3188 | ||
3189 | `FUNCTION_ARG' for these arguments should return the first register to be | |
3190 | used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for | |
3191 | the called function. */ | |
3192 | ||
78a52f11 RH |
3193 | static int |
3194 | frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
3195 | tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED) | |
36a05131 BS |
3196 | { |
3197 | enum machine_mode xmode = (mode == BLKmode) ? SImode : mode; | |
3198 | int bytes = GET_MODE_SIZE (xmode); | |
3199 | int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
3200 | int arg_num = *cum; | |
3201 | int ret; | |
3202 | ||
3203 | ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1) | |
3204 | ? LAST_ARG_REGNUM - arg_num + 1 | |
3205 | : 0); | |
78a52f11 | 3206 | ret *= UNITS_PER_WORD; |
36a05131 BS |
3207 | |
3208 | if (TARGET_DEBUG_ARG && ret) | |
78a52f11 | 3209 | fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret); |
36a05131 BS |
3210 | |
3211 | return ret; | |
36a05131 BS |
3212 | } |
3213 | ||
36a05131 BS |
3214 | \f |
3215 | /* Return true if a register is ok to use as a base or index register. */ | |
3216 | ||
3217 | static FRV_INLINE int | |
f2206911 | 3218 | frv_regno_ok_for_base_p (int regno, int strict_p) |
36a05131 BS |
3219 | { |
3220 | if (GPR_P (regno)) | |
3221 | return TRUE; | |
3222 | ||
3223 | if (strict_p) | |
3224 | return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno])); | |
3225 | ||
3226 | if (regno == ARG_POINTER_REGNUM) | |
3227 | return TRUE; | |
3228 | ||
3229 | return (regno >= FIRST_PSEUDO_REGISTER); | |
3230 | } | |
3231 | ||
3232 | \f | |
3233 | /* A C compound statement with a conditional `goto LABEL;' executed if X (an | |
3234 | RTX) is a legitimate memory address on the target machine for a memory | |
3235 | operand of mode MODE. | |
3236 | ||
3237 | It usually pays to define several simpler macros to serve as subroutines for | |
3238 | this one. Otherwise it may be too complicated to understand. | |
3239 | ||
3240 | This macro must exist in two variants: a strict variant and a non-strict | |
3241 | one. The strict variant is used in the reload pass. It must be defined so | |
3242 | that any pseudo-register that has not been allocated a hard register is | |
3243 | considered a memory reference. In contexts where some kind of register is | |
3244 | required, a pseudo-register with no hard register must be rejected. | |
3245 | ||
3246 | The non-strict variant is used in other passes. It must be defined to | |
3247 | accept all pseudo-registers in every context where some kind of register is | |
3248 | required. | |
3249 | ||
3250 | Compiler source files that want to use the strict variant of this macro | |
3251 | define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT' | |
3252 | conditional to define the strict variant in that case and the non-strict | |
3253 | variant otherwise. | |
3254 | ||
3255 | Subroutines to check for acceptable registers for various purposes (one for | |
3256 | base registers, one for index registers, and so on) are typically among the | |
3257 | subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these | |
3258 | subroutine macros need have two variants; the higher levels of macros may be | |
3259 | the same whether strict or not. | |
3260 | ||
3261 | Normally, constant addresses which are the sum of a `symbol_ref' and an | |
3262 | integer are stored inside a `const' RTX to mark them as constant. | |
3263 | Therefore, there is no need to recognize such sums specifically as | |
3264 | legitimate addresses. Normally you would simply recognize any `const' as | |
3265 | legitimate. | |
3266 | ||
3267 | Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that | |
3268 | are not marked with `const'. It assumes that a naked `plus' indicates | |
3269 | indexing. If so, then you *must* reject such naked constant sums as | |
3270 | illegitimate addresses, so that none of them will be given to | |
3271 | `PRINT_OPERAND_ADDRESS'. | |
3272 | ||
3273 | On some machines, whether a symbolic address is legitimate depends on the | |
3274 | section that the address refers to. On these machines, define the macro | |
3275 | `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and | |
3276 | then check for it here. When you see a `const', you will have to look | |
3277 | inside it to find the `symbol_ref' in order to determine the section. | |
3278 | ||
3279 | The best way to modify the name string is by adding text to the beginning, | |
3280 | with suitable punctuation to prevent any ambiguity. Allocate the new name | |
3281 | in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to | |
3282 | remove and decode the added text and output the name accordingly, and define | |
14966b94 | 3283 | `(* targetm.strip_name_encoding)' to access the original name string. |
36a05131 BS |
3284 | |
3285 | You can check the information stored here into the `symbol_ref' in the | |
3286 | definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and | |
3287 | `PRINT_OPERAND_ADDRESS'. */ | |
3288 | ||
3289 | int | |
f2206911 KC |
3290 | frv_legitimate_address_p (enum machine_mode mode, |
3291 | rtx x, | |
3292 | int strict_p, | |
34208acf AO |
3293 | int condexec_p, |
3294 | int allow_double_reg_p) | |
36a05131 BS |
3295 | { |
3296 | rtx x0, x1; | |
3297 | int ret = 0; | |
3298 | HOST_WIDE_INT value; | |
3299 | unsigned regno0; | |
3300 | ||
bef8809e AH |
3301 | if (FRV_SYMBOL_REF_TLS_P (x)) |
3302 | return 0; | |
3303 | ||
36a05131 BS |
3304 | switch (GET_CODE (x)) |
3305 | { | |
3306 | default: | |
3307 | break; | |
3308 | ||
3309 | case SUBREG: | |
3310 | x = SUBREG_REG (x); | |
3311 | if (GET_CODE (x) != REG) | |
3312 | break; | |
3313 | ||
87b483a1 | 3314 | /* Fall through. */ |
36a05131 BS |
3315 | |
3316 | case REG: | |
3317 | ret = frv_regno_ok_for_base_p (REGNO (x), strict_p); | |
3318 | break; | |
3319 | ||
3320 | case PRE_MODIFY: | |
3321 | x0 = XEXP (x, 0); | |
3322 | x1 = XEXP (x, 1); | |
3323 | if (GET_CODE (x0) != REG | |
3324 | || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p) | |
3325 | || GET_CODE (x1) != PLUS | |
3326 | || ! rtx_equal_p (x0, XEXP (x1, 0)) | |
3327 | || GET_CODE (XEXP (x1, 1)) != REG | |
3328 | || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p)) | |
3329 | break; | |
3330 | ||
3331 | ret = 1; | |
3332 | break; | |
3333 | ||
3334 | case CONST_INT: | |
3335 | /* 12 bit immediate */ | |
3336 | if (condexec_p) | |
3337 | ret = FALSE; | |
3338 | else | |
3339 | { | |
3340 | ret = IN_RANGE_P (INTVAL (x), -2048, 2047); | |
3341 | ||
3342 | /* If we can't use load/store double operations, make sure we can | |
3343 | address the second word. */ | |
3344 | if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
3345 | ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1, | |
3346 | -2048, 2047); | |
3347 | } | |
3348 | break; | |
3349 | ||
3350 | case PLUS: | |
3351 | x0 = XEXP (x, 0); | |
3352 | x1 = XEXP (x, 1); | |
3353 | ||
3354 | if (GET_CODE (x0) == SUBREG) | |
3355 | x0 = SUBREG_REG (x0); | |
3356 | ||
3357 | if (GET_CODE (x0) != REG) | |
3358 | break; | |
3359 | ||
3360 | regno0 = REGNO (x0); | |
3361 | if (!frv_regno_ok_for_base_p (regno0, strict_p)) | |
3362 | break; | |
3363 | ||
3364 | switch (GET_CODE (x1)) | |
3365 | { | |
3366 | default: | |
3367 | break; | |
3368 | ||
3369 | case SUBREG: | |
3370 | x1 = SUBREG_REG (x1); | |
3371 | if (GET_CODE (x1) != REG) | |
3372 | break; | |
3373 | ||
87b483a1 | 3374 | /* Fall through. */ |
36a05131 BS |
3375 | |
3376 | case REG: | |
87b483a1 KH |
3377 | /* Do not allow reg+reg addressing for modes > 1 word if we |
3378 | can't depend on having move double instructions. */ | |
34208acf | 3379 | if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD) |
36a05131 BS |
3380 | ret = FALSE; |
3381 | else | |
3382 | ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p); | |
3383 | break; | |
3384 | ||
3385 | case CONST_INT: | |
3386 | /* 12 bit immediate */ | |
3387 | if (condexec_p) | |
3388 | ret = FALSE; | |
3389 | else | |
3390 | { | |
3391 | value = INTVAL (x1); | |
3392 | ret = IN_RANGE_P (value, -2048, 2047); | |
3393 | ||
3394 | /* If we can't use load/store double operations, make sure we can | |
3395 | address the second word. */ | |
3396 | if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
3397 | ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047); | |
3398 | } | |
3399 | break; | |
3400 | ||
36a05131 | 3401 | case CONST: |
34208acf | 3402 | if (!condexec_p && got12_operand (x1, VOIDmode)) |
36a05131 BS |
3403 | ret = TRUE; |
3404 | break; | |
3405 | ||
3406 | } | |
3407 | break; | |
3408 | } | |
3409 | ||
3410 | if (TARGET_DEBUG_ADDR) | |
3411 | { | |
3412 | fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n", | |
3413 | GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ", | |
3414 | (condexec_p) ? ", inside conditional code" : ""); | |
3415 | debug_rtx (x); | |
3416 | } | |
3417 | ||
3418 | return ret; | |
3419 | } | |
3420 | ||
bef8809e AH |
3421 | /* Given an ADDR, generate code to inline the PLT. */ |
3422 | static rtx | |
3423 | gen_inlined_tls_plt (rtx addr) | |
3424 | { | |
fdbe66f2 | 3425 | rtx retval, dest; |
bef8809e AH |
3426 | rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG); |
3427 | ||
3428 | ||
3429 | dest = gen_reg_rtx (DImode); | |
3430 | ||
3431 | if (flag_pic == 1) | |
3432 | { | |
3433 | /* | |
3434 | -fpic version: | |
3435 | ||
3436 | lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8 | |
3437 | calll #gettlsoff(ADDR)@(gr8, gr0) | |
3438 | */ | |
3439 | emit_insn (gen_tls_lddi (dest, addr, picreg)); | |
3440 | } | |
3441 | else | |
3442 | { | |
3443 | /* | |
3444 | -fPIC version: | |
3445 | ||
3446 | sethi.p #gottlsdeschi(ADDR), gr8 | |
3447 | setlo #gottlsdesclo(ADDR), gr8 | |
3448 | ldd #tlsdesc(ADDR)@(gr15, gr8), gr8 | |
3449 | calll #gettlsoff(ADDR)@(gr8, gr0) | |
3450 | */ | |
3451 | rtx reguse = gen_reg_rtx (Pmode); | |
3452 | emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI))); | |
3453 | emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr)); | |
3454 | } | |
3455 | ||
3456 | retval = gen_reg_rtx (Pmode); | |
a701780f | 3457 | emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg)); |
bef8809e AH |
3458 | return retval; |
3459 | } | |
3460 | ||
3461 | /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns | |
3462 | the destination address. */ | |
3463 | static rtx | |
3464 | gen_tlsmoff (rtx addr, rtx reg) | |
3465 | { | |
3466 | rtx dest = gen_reg_rtx (Pmode); | |
3467 | ||
3468 | if (TARGET_BIG_TLS) | |
3469 | { | |
3470 | /* sethi.p #tlsmoffhi(x), grA | |
3471 | setlo #tlsmofflo(x), grA | |
3472 | */ | |
3473 | dest = gen_reg_rtx (Pmode); | |
3474 | emit_insn (gen_tlsoff_hilo (dest, addr, | |
3475 | GEN_INT (R_FRV_TLSMOFFHI))); | |
3476 | dest = gen_rtx_PLUS (Pmode, dest, reg); | |
3477 | } | |
3478 | else | |
3479 | { | |
3480 | /* addi grB, #tlsmoff12(x), grC | |
3481 | -or- | |
3482 | ld/st @(grB, #tlsmoff12(x)), grC | |
3483 | */ | |
3484 | dest = gen_reg_rtx (Pmode); | |
3485 | emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg, | |
3486 | GEN_INT (R_FRV_TLSMOFF12))); | |
3487 | } | |
3488 | return dest; | |
3489 | } | |
3490 | ||
3491 | /* Generate code for a TLS address. */ | |
3492 | static rtx | |
3493 | frv_legitimize_tls_address (rtx addr, enum tls_model model) | |
3494 | { | |
3495 | rtx dest, tp = gen_rtx_REG (Pmode, 29); | |
3496 | rtx picreg = get_hard_reg_initial_val (Pmode, 15); | |
3497 | ||
3498 | switch (model) | |
3499 | { | |
3500 | case TLS_MODEL_INITIAL_EXEC: | |
3501 | if (flag_pic == 1) | |
3502 | { | |
3503 | /* -fpic version. | |
3504 | ldi @(gr15, #gottlsoff12(x)), gr5 | |
3505 | */ | |
3506 | dest = gen_reg_rtx (Pmode); | |
3507 | emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg)); | |
3508 | dest = gen_rtx_PLUS (Pmode, tp, dest); | |
3509 | } | |
3510 | else | |
3511 | { | |
3512 | /* -fPIC or anything else. | |
3513 | ||
3514 | sethi.p #gottlsoffhi(x), gr14 | |
3515 | setlo #gottlsofflo(x), gr14 | |
3516 | ld #tlsoff(x)@(gr15, gr14), gr9 | |
3517 | */ | |
3518 | rtx tmp = gen_reg_rtx (Pmode); | |
3519 | dest = gen_reg_rtx (Pmode); | |
3520 | emit_insn (gen_tlsoff_hilo (tmp, addr, | |
3521 | GEN_INT (R_FRV_GOTTLSOFF_HI))); | |
3522 | ||
3523 | emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr)); | |
3524 | dest = gen_rtx_PLUS (Pmode, tp, dest); | |
3525 | } | |
3526 | break; | |
3527 | case TLS_MODEL_LOCAL_DYNAMIC: | |
3528 | { | |
3529 | rtx reg, retval; | |
3530 | ||
3531 | if (TARGET_INLINE_PLT) | |
3532 | retval = gen_inlined_tls_plt (GEN_INT (0)); | |
3533 | else | |
3534 | { | |
3535 | /* call #gettlsoff(0) */ | |
3536 | retval = gen_reg_rtx (Pmode); | |
3537 | emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg)); | |
3538 | } | |
3539 | ||
3540 | reg = gen_reg_rtx (Pmode); | |
3541 | emit_insn (gen_rtx_SET (VOIDmode, reg, | |
3542 | gen_rtx_PLUS (Pmode, | |
3543 | retval, tp))); | |
3544 | ||
3545 | dest = gen_tlsmoff (addr, reg); | |
3546 | ||
3547 | /* | |
3548 | dest = gen_reg_rtx (Pmode); | |
3549 | emit_insn (gen_tlsoff_hilo (dest, addr, | |
3550 | GEN_INT (R_FRV_TLSMOFFHI))); | |
3551 | dest = gen_rtx_PLUS (Pmode, dest, reg); | |
3552 | */ | |
3553 | break; | |
3554 | } | |
3555 | case TLS_MODEL_LOCAL_EXEC: | |
3556 | dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29)); | |
3557 | break; | |
3558 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
3559 | { | |
3560 | rtx retval; | |
3561 | ||
3562 | if (TARGET_INLINE_PLT) | |
3563 | retval = gen_inlined_tls_plt (addr); | |
3564 | else | |
3565 | { | |
3566 | /* call #gettlsoff(x) */ | |
3567 | retval = gen_reg_rtx (Pmode); | |
3568 | emit_insn (gen_call_gettlsoff (retval, addr, picreg)); | |
3569 | } | |
3570 | dest = gen_rtx_PLUS (Pmode, retval, tp); | |
3571 | break; | |
3572 | } | |
3573 | default: | |
44e91694 | 3574 | gcc_unreachable (); |
bef8809e AH |
3575 | } |
3576 | ||
3577 | return dest; | |
3578 | } | |
3579 | ||
2a2e3f05 | 3580 | rtx |
bef8809e | 3581 | frv_legitimize_address (rtx x, |
2a2e3f05 AH |
3582 | rtx oldx ATTRIBUTE_UNUSED, |
3583 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
3584 | { | |
bef8809e AH |
3585 | if (GET_CODE (x) == SYMBOL_REF) |
3586 | { | |
3587 | enum tls_model model = SYMBOL_REF_TLS_MODEL (x); | |
3588 | if (model != 0) | |
3589 | return frv_legitimize_tls_address (x, model); | |
3590 | } | |
3591 | ||
2a2e3f05 AH |
3592 | return NULL_RTX; |
3593 | } | |
36a05131 | 3594 | \f |
34208acf AO |
3595 | /* Test whether a local function descriptor is canonical, i.e., |
3596 | whether we can use FUNCDESC_GOTOFF to compute the address of the | |
3597 | function. */ | |
3598 | ||
3599 | static bool | |
3600 | frv_local_funcdesc_p (rtx fnx) | |
3601 | { | |
3602 | tree fn; | |
3603 | enum symbol_visibility vis; | |
3604 | bool ret; | |
36a05131 | 3605 | |
34208acf AO |
3606 | if (! SYMBOL_REF_LOCAL_P (fnx)) |
3607 | return FALSE; | |
3608 | ||
3609 | fn = SYMBOL_REF_DECL (fnx); | |
3610 | ||
3611 | if (! fn) | |
3612 | return FALSE; | |
36a05131 | 3613 | |
34208acf | 3614 | vis = DECL_VISIBILITY (fn); |
36a05131 | 3615 | |
34208acf AO |
3616 | if (vis == VISIBILITY_PROTECTED) |
3617 | /* Private function descriptors for protected functions are not | |
3618 | canonical. Temporarily change the visibility to global. */ | |
3619 | vis = VISIBILITY_DEFAULT; | |
3620 | else if (flag_shlib) | |
3621 | /* If we're already compiling for a shared library (that, unlike | |
3622 | executables, can't assume that the existence of a definition | |
3623 | implies local binding), we can skip the re-testing. */ | |
3624 | return TRUE; | |
36a05131 | 3625 | |
34208acf | 3626 | ret = default_binds_local_p_1 (fn, flag_pic); |
36a05131 | 3627 | |
34208acf AO |
3628 | DECL_VISIBILITY (fn) = vis; |
3629 | ||
3630 | return ret; | |
3631 | } | |
3632 | ||
3633 | /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC | |
3634 | register. */ | |
36a05131 BS |
3635 | |
3636 | rtx | |
34208acf AO |
3637 | frv_gen_GPsym2reg (rtx dest, rtx src) |
3638 | { | |
3639 | tree gp = get_identifier ("_gp"); | |
3640 | rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp)); | |
36a05131 | 3641 | |
34208acf AO |
3642 | return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12)); |
3643 | } | |
3644 | ||
3645 | static const char * | |
3646 | unspec_got_name (int i) | |
3647 | { | |
3648 | switch (i) | |
36a05131 | 3649 | { |
34208acf AO |
3650 | case R_FRV_GOT12: return "got12"; |
3651 | case R_FRV_GOTHI: return "gothi"; | |
3652 | case R_FRV_GOTLO: return "gotlo"; | |
3653 | case R_FRV_FUNCDESC: return "funcdesc"; | |
3654 | case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12"; | |
3655 | case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi"; | |
3656 | case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo"; | |
3657 | case R_FRV_FUNCDESC_VALUE: return "funcdescvalue"; | |
3658 | case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12"; | |
3659 | case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi"; | |
3660 | case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo"; | |
3661 | case R_FRV_GOTOFF12: return "gotoff12"; | |
3662 | case R_FRV_GOTOFFHI: return "gotoffhi"; | |
3663 | case R_FRV_GOTOFFLO: return "gotofflo"; | |
3664 | case R_FRV_GPREL12: return "gprel12"; | |
3665 | case R_FRV_GPRELHI: return "gprelhi"; | |
3666 | case R_FRV_GPRELLO: return "gprello"; | |
bef8809e AH |
3667 | case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi"; |
3668 | case R_FRV_GOTTLSOFF_LO: return "gottlsofflo"; | |
3669 | case R_FRV_TLSMOFFHI: return "tlsmoffhi"; | |
3670 | case R_FRV_TLSMOFFLO: return "tlsmofflo"; | |
3671 | case R_FRV_TLSMOFF12: return "tlsmoff12"; | |
3672 | case R_FRV_TLSDESCHI: return "tlsdeschi"; | |
3673 | case R_FRV_TLSDESCLO: return "tlsdesclo"; | |
3674 | case R_FRV_GOTTLSDESCHI: return "gottlsdeschi"; | |
3675 | case R_FRV_GOTTLSDESCLO: return "gottlsdesclo"; | |
44e91694 | 3676 | default: gcc_unreachable (); |
36a05131 | 3677 | } |
34208acf | 3678 | } |
36a05131 | 3679 | |
34208acf AO |
3680 | /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset |
3681 | is added inside the relocation operator. */ | |
3682 | ||
3683 | static void | |
3684 | frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec) | |
3685 | { | |
3686 | fprintf (stream, "#%s(", unspec_got_name (unspec->reloc)); | |
3687 | output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset)); | |
3688 | fputs (")", stream); | |
3689 | } | |
3690 | ||
3691 | /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo) | |
3692 | or #gotoff12(foo) for some small data symbol foo. If so, return foo, | |
3693 | otherwise return ORIG_X. */ | |
3694 | ||
3695 | rtx | |
3696 | frv_find_base_term (rtx x) | |
3697 | { | |
3698 | struct frv_unspec unspec; | |
3699 | ||
3700 | if (frv_const_unspec_p (x, &unspec) | |
3701 | && frv_small_data_reloc_p (unspec.symbol, unspec.reloc)) | |
3702 | return plus_constant (unspec.symbol, unspec.offset); | |
3703 | ||
3704 | return x; | |
36a05131 BS |
3705 | } |
3706 | ||
3707 | /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if | |
3708 | the operand is used by a predicated instruction. */ | |
3709 | ||
6d26dc3b | 3710 | int |
f2206911 | 3711 | frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p) |
36a05131 BS |
3712 | { |
3713 | return ((GET_MODE (op) == mode || mode == VOIDmode) | |
3714 | && GET_CODE (op) == MEM | |
3715 | && frv_legitimate_address_p (mode, XEXP (op, 0), | |
34208acf AO |
3716 | reload_completed, condexec_p, FALSE)); |
3717 | } | |
3718 | ||
3719 | void | |
764678d1 | 3720 | frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall) |
34208acf AO |
3721 | { |
3722 | rtx lr = gen_rtx_REG (Pmode, LR_REGNO); | |
3723 | rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG); | |
3724 | rtx c, rvrtx=0; | |
3725 | rtx addr; | |
3726 | ||
3727 | if (ret_value) | |
3728 | { | |
3729 | rvrtx = operands[0]; | |
3730 | operands ++; | |
3731 | } | |
3732 | ||
3733 | addr = XEXP (operands[0], 0); | |
3734 | ||
3735 | /* Inline PLTs if we're optimizing for speed. We'd like to inline | |
3736 | any calls that would involve a PLT, but can't tell, since we | |
3737 | don't know whether an extern function is going to be provided by | |
3738 | a separate translation unit or imported from a separate module. | |
3739 | When compiling for shared libraries, if the function has default | |
3740 | visibility, we assume it's overridable, so we inline the PLT, but | |
3741 | for executables, we don't really have a way to make a good | |
3742 | decision: a function is as likely to be imported from a shared | |
3743 | library as it is to be defined in the executable itself. We | |
3744 | assume executables will get global functions defined locally, | |
3745 | whereas shared libraries will have them potentially overridden, | |
3746 | so we only inline PLTs when compiling for shared libraries. | |
3747 | ||
3748 | In order to mark a function as local to a shared library, any | |
3749 | non-default visibility attribute suffices. Unfortunately, | |
3750 | there's no simple way to tag a function declaration as ``in a | |
3751 | different module'', which we could then use to trigger PLT | |
3752 | inlining on executables. There's -minline-plt, but it affects | |
3753 | all external functions, so one would have to also mark function | |
3754 | declarations available in the same module with non-default | |
3755 | visibility, which is advantageous in itself. */ | |
764678d1 AO |
3756 | if (GET_CODE (addr) == SYMBOL_REF |
3757 | && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT) | |
3758 | || sibcall)) | |
34208acf AO |
3759 | { |
3760 | rtx x, dest; | |
3761 | dest = gen_reg_rtx (SImode); | |
3762 | if (flag_pic != 1) | |
3763 | x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG, | |
3764 | GEN_INT (R_FRV_FUNCDESC_GOTOFF12)); | |
3765 | else | |
3766 | x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG, | |
3767 | GEN_INT (R_FRV_FUNCDESC_GOTOFF12)); | |
3768 | emit_insn (x); | |
3769 | cfun->uses_pic_offset_table = TRUE; | |
3770 | addr = dest; | |
3771 | } | |
3772 | else if (GET_CODE (addr) == SYMBOL_REF) | |
3773 | { | |
3774 | /* These are always either local, or handled through a local | |
3775 | PLT. */ | |
3776 | if (ret_value) | |
3777 | c = gen_call_value_fdpicsi (rvrtx, addr, operands[1], | |
3778 | operands[2], picreg, lr); | |
3779 | else | |
3780 | c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr); | |
3781 | emit_call_insn (c); | |
3782 | return; | |
3783 | } | |
3784 | else if (! ldd_address_operand (addr, Pmode)) | |
3785 | addr = force_reg (Pmode, addr); | |
3786 | ||
3787 | picreg = gen_reg_rtx (DImode); | |
3788 | emit_insn (gen_movdi_ldd (picreg, addr)); | |
3789 | ||
764678d1 AO |
3790 | if (sibcall && ret_value) |
3791 | c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx); | |
3792 | else if (sibcall) | |
3793 | c = gen_sibcall_fdpicdi (picreg, const0_rtx); | |
3794 | else if (ret_value) | |
34208acf AO |
3795 | c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr); |
3796 | else | |
3797 | c = gen_call_fdpicdi (picreg, const0_rtx, lr); | |
3798 | emit_call_insn (c); | |
36a05131 | 3799 | } |
36a05131 | 3800 | \f |
6d26dc3b KH |
3801 | /* Look for a SYMBOL_REF of a function in an rtx. We always want to |
3802 | process these separately from any offsets, such that we add any | |
3803 | offsets to the function descriptor (the actual pointer), not to the | |
3804 | function address. */ | |
36a05131 | 3805 | |
6d26dc3b KH |
3806 | static bool |
3807 | frv_function_symbol_referenced_p (rtx x) | |
36a05131 | 3808 | { |
6d26dc3b KH |
3809 | const char *format; |
3810 | int length; | |
3811 | int j; | |
36a05131 | 3812 | |
6d26dc3b KH |
3813 | if (GET_CODE (x) == SYMBOL_REF) |
3814 | return SYMBOL_REF_FUNCTION_P (x); | |
34208acf | 3815 | |
6d26dc3b KH |
3816 | length = GET_RTX_LENGTH (GET_CODE (x)); |
3817 | format = GET_RTX_FORMAT (GET_CODE (x)); | |
36a05131 | 3818 | |
6d26dc3b | 3819 | for (j = 0; j < length; ++j) |
36a05131 | 3820 | { |
6d26dc3b KH |
3821 | switch (format[j]) |
3822 | { | |
3823 | case 'e': | |
3824 | if (frv_function_symbol_referenced_p (XEXP (x, j))) | |
3825 | return TRUE; | |
3826 | break; | |
36a05131 | 3827 | |
6d26dc3b KH |
3828 | case 'V': |
3829 | case 'E': | |
3830 | if (XVEC (x, j) != 0) | |
3831 | { | |
3832 | int k; | |
3833 | for (k = 0; k < XVECLEN (x, j); ++k) | |
3834 | if (frv_function_symbol_referenced_p (XVECEXP (x, j, k))) | |
3835 | return TRUE; | |
3836 | } | |
3837 | break; | |
36a05131 | 3838 | |
6d26dc3b KH |
3839 | default: |
3840 | /* Nothing to do. */ | |
3841 | break; | |
3842 | } | |
36a05131 BS |
3843 | } |
3844 | ||
36a05131 BS |
3845 | return FALSE; |
3846 | } | |
3847 | ||
6d26dc3b KH |
3848 | /* Return true if the memory operand is one that can be conditionally |
3849 | executed. */ | |
36a05131 | 3850 | |
f2206911 | 3851 | int |
6d26dc3b | 3852 | condexec_memory_operand (rtx op, enum machine_mode mode) |
36a05131 | 3853 | { |
6d26dc3b KH |
3854 | enum machine_mode op_mode = GET_MODE (op); |
3855 | rtx addr; | |
36a05131 | 3856 | |
6d26dc3b | 3857 | if (mode != VOIDmode && op_mode != mode) |
36a05131 BS |
3858 | return FALSE; |
3859 | ||
6d26dc3b | 3860 | switch (op_mode) |
36a05131 BS |
3861 | { |
3862 | default: | |
6d26dc3b | 3863 | return FALSE; |
36a05131 | 3864 | |
6d26dc3b KH |
3865 | case QImode: |
3866 | case HImode: | |
3867 | case SImode: | |
3868 | case SFmode: | |
36a05131 BS |
3869 | break; |
3870 | } | |
3871 | ||
6d26dc3b | 3872 | if (GET_CODE (op) != MEM) |
36a05131 BS |
3873 | return FALSE; |
3874 | ||
6d26dc3b KH |
3875 | addr = XEXP (op, 0); |
3876 | return frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE); | |
36a05131 | 3877 | } |
36a05131 BS |
3878 | \f |
3879 | /* Return true if the bare return instruction can be used outside of the | |
3880 | epilog code. For frv, we only do it if there was no stack allocation. */ | |
3881 | ||
3882 | int | |
f2206911 | 3883 | direct_return_p (void) |
36a05131 BS |
3884 | { |
3885 | frv_stack_t *info; | |
3886 | ||
3887 | if (!reload_completed) | |
3888 | return FALSE; | |
3889 | ||
3890 | info = frv_stack_info (); | |
3891 | return (info->total_size == 0); | |
3892 | } | |
3893 | ||
3894 | \f | |
2a2e3f05 AH |
3895 | void |
3896 | frv_emit_move (enum machine_mode mode, rtx dest, rtx src) | |
3897 | { | |
bef8809e AH |
3898 | if (GET_CODE (src) == SYMBOL_REF) |
3899 | { | |
3900 | enum tls_model model = SYMBOL_REF_TLS_MODEL (src); | |
3901 | if (model != 0) | |
3902 | src = frv_legitimize_tls_address (src, model); | |
3903 | } | |
3904 | ||
2a2e3f05 AH |
3905 | switch (mode) |
3906 | { | |
3907 | case SImode: | |
3908 | if (frv_emit_movsi (dest, src)) | |
3909 | return; | |
3910 | break; | |
3911 | ||
3912 | case QImode: | |
3913 | case HImode: | |
3914 | case DImode: | |
3915 | case SFmode: | |
3916 | case DFmode: | |
3917 | if (!reload_in_progress | |
3918 | && !reload_completed | |
3919 | && !register_operand (dest, mode) | |
3920 | && !reg_or_0_operand (src, mode)) | |
3921 | src = copy_to_mode_reg (mode, src); | |
3922 | break; | |
3923 | ||
3924 | default: | |
44e91694 | 3925 | gcc_unreachable (); |
2a2e3f05 AH |
3926 | } |
3927 | ||
3928 | emit_insn (gen_rtx_SET (VOIDmode, dest, src)); | |
3929 | } | |
3930 | ||
36a05131 BS |
3931 | /* Emit code to handle a MOVSI, adding in the small data register or pic |
3932 | register if needed to load up addresses. Return TRUE if the appropriate | |
3933 | instructions are emitted. */ | |
3934 | ||
3935 | int | |
f2206911 | 3936 | frv_emit_movsi (rtx dest, rtx src) |
36a05131 BS |
3937 | { |
3938 | int base_regno = -1; | |
34208acf AO |
3939 | int unspec = 0; |
3940 | rtx sym = src; | |
3941 | struct frv_unspec old_unspec; | |
36a05131 BS |
3942 | |
3943 | if (!reload_in_progress | |
3944 | && !reload_completed | |
3945 | && !register_operand (dest, SImode) | |
3946 | && (!reg_or_0_operand (src, SImode) | |
3947 | /* Virtual registers will almost always be replaced by an | |
3948 | add instruction, so expose this to CSE by copying to | |
87b483a1 | 3949 | an intermediate register. */ |
36a05131 BS |
3950 | || (GET_CODE (src) == REG |
3951 | && IN_RANGE_P (REGNO (src), | |
3952 | FIRST_VIRTUAL_REGISTER, | |
3953 | LAST_VIRTUAL_REGISTER)))) | |
3954 | { | |
3955 | emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src))); | |
3956 | return TRUE; | |
3957 | } | |
3958 | ||
3959 | /* Explicitly add in the PIC or small data register if needed. */ | |
3960 | switch (GET_CODE (src)) | |
3961 | { | |
3962 | default: | |
3963 | break; | |
3964 | ||
3965 | case LABEL_REF: | |
34208acf AO |
3966 | handle_label: |
3967 | if (TARGET_FDPIC) | |
3968 | { | |
3969 | /* Using GPREL12, we use a single GOT entry for all symbols | |
3970 | in read-only sections, but trade sequences such as: | |
3971 | ||
3972 | sethi #gothi(label), gr# | |
3973 | setlo #gotlo(label), gr# | |
3974 | ld @(gr15,gr#), gr# | |
3975 | ||
3976 | for | |
3977 | ||
3978 | ld @(gr15,#got12(_gp)), gr# | |
3979 | sethi #gprelhi(label), gr## | |
3980 | setlo #gprello(label), gr## | |
3981 | add gr#, gr##, gr## | |
3982 | ||
3983 | We may often be able to share gr# for multiple | |
3984 | computations of GPREL addresses, and we may often fold | |
3985 | the final add into the pair of registers of a load or | |
3986 | store instruction, so it's often profitable. Even when | |
3987 | optimizing for size, we're trading a GOT entry for an | |
3988 | additional instruction, which trades GOT space | |
3989 | (read-write) for code size (read-only, shareable), as | |
3990 | long as the symbol is not used in more than two different | |
3991 | locations. | |
3992 | ||
3993 | With -fpie/-fpic, we'd be trading a single load for a | |
3994 | sequence of 4 instructions, because the offset of the | |
4ee31f1e | 3995 | label can't be assumed to be addressable with 12 bits, so |
34208acf AO |
3996 | we don't do this. */ |
3997 | if (TARGET_GPREL_RO) | |
3998 | unspec = R_FRV_GPREL12; | |
3999 | else | |
4000 | unspec = R_FRV_GOT12; | |
4001 | } | |
4002 | else if (flag_pic) | |
36a05131 BS |
4003 | base_regno = PIC_REGNO; |
4004 | ||
4005 | break; | |
4006 | ||
4007 | case CONST: | |
34208acf AO |
4008 | if (frv_const_unspec_p (src, &old_unspec)) |
4009 | break; | |
36a05131 | 4010 | |
34208acf AO |
4011 | if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0))) |
4012 | { | |
4013 | handle_whatever: | |
4014 | src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0)); | |
4015 | emit_move_insn (dest, src); | |
4016 | return TRUE; | |
4017 | } | |
4018 | else | |
4019 | { | |
4020 | sym = XEXP (sym, 0); | |
4021 | if (GET_CODE (sym) == PLUS | |
4022 | && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF | |
4023 | && GET_CODE (XEXP (sym, 1)) == CONST_INT) | |
4024 | sym = XEXP (sym, 0); | |
4025 | if (GET_CODE (sym) == SYMBOL_REF) | |
4026 | goto handle_sym; | |
4027 | else if (GET_CODE (sym) == LABEL_REF) | |
4028 | goto handle_label; | |
4029 | else | |
4030 | goto handle_whatever; | |
4031 | } | |
36a05131 BS |
4032 | break; |
4033 | ||
4034 | case SYMBOL_REF: | |
34208acf AO |
4035 | handle_sym: |
4036 | if (TARGET_FDPIC) | |
4037 | { | |
bef8809e AH |
4038 | enum tls_model model = SYMBOL_REF_TLS_MODEL (sym); |
4039 | ||
4040 | if (model != 0) | |
4041 | { | |
4042 | src = frv_legitimize_tls_address (src, model); | |
4043 | emit_move_insn (dest, src); | |
4044 | return TRUE; | |
4045 | } | |
4046 | ||
34208acf AO |
4047 | if (SYMBOL_REF_FUNCTION_P (sym)) |
4048 | { | |
4049 | if (frv_local_funcdesc_p (sym)) | |
4050 | unspec = R_FRV_FUNCDESC_GOTOFF12; | |
4051 | else | |
4052 | unspec = R_FRV_FUNCDESC_GOT12; | |
4053 | } | |
4054 | else | |
4055 | { | |
4056 | if (CONSTANT_POOL_ADDRESS_P (sym)) | |
4057 | switch (GET_CODE (get_pool_constant (sym))) | |
4058 | { | |
4059 | case CONST: | |
4060 | case SYMBOL_REF: | |
4061 | case LABEL_REF: | |
4062 | if (flag_pic) | |
4063 | { | |
4064 | unspec = R_FRV_GOTOFF12; | |
4065 | break; | |
4066 | } | |
4067 | /* Fall through. */ | |
4068 | default: | |
4069 | if (TARGET_GPREL_RO) | |
4070 | unspec = R_FRV_GPREL12; | |
4071 | else | |
4072 | unspec = R_FRV_GOT12; | |
4073 | break; | |
4074 | } | |
4075 | else if (SYMBOL_REF_LOCAL_P (sym) | |
4076 | && !SYMBOL_REF_EXTERNAL_P (sym) | |
4077 | && SYMBOL_REF_DECL (sym) | |
4078 | && (!DECL_P (SYMBOL_REF_DECL (sym)) | |
4079 | || !DECL_COMMON (SYMBOL_REF_DECL (sym)))) | |
4080 | { | |
4081 | tree decl = SYMBOL_REF_DECL (sym); | |
4082 | tree init = TREE_CODE (decl) == VAR_DECL | |
4083 | ? DECL_INITIAL (decl) | |
4084 | : TREE_CODE (decl) == CONSTRUCTOR | |
4085 | ? decl : 0; | |
4086 | int reloc = 0; | |
4087 | bool named_section, readonly; | |
4088 | ||
4089 | if (init && init != error_mark_node) | |
4090 | reloc = compute_reloc_for_constant (init); | |
4091 | ||
4092 | named_section = TREE_CODE (decl) == VAR_DECL | |
4093 | && lookup_attribute ("section", DECL_ATTRIBUTES (decl)); | |
4094 | readonly = decl_readonly_section (decl, reloc); | |
4095 | ||
4096 | if (named_section) | |
4097 | unspec = R_FRV_GOT12; | |
4098 | else if (!readonly) | |
4099 | unspec = R_FRV_GOTOFF12; | |
4100 | else if (readonly && TARGET_GPREL_RO) | |
4101 | unspec = R_FRV_GPREL12; | |
4102 | else | |
4103 | unspec = R_FRV_GOT12; | |
4104 | } | |
4105 | else | |
4106 | unspec = R_FRV_GOT12; | |
4107 | } | |
4108 | } | |
4109 | ||
4110 | else if (SYMBOL_REF_SMALL_P (sym)) | |
36a05131 BS |
4111 | base_regno = SDA_BASE_REG; |
4112 | ||
4113 | else if (flag_pic) | |
4114 | base_regno = PIC_REGNO; | |
4115 | ||
4116 | break; | |
4117 | } | |
4118 | ||
4119 | if (base_regno >= 0) | |
4120 | { | |
34208acf AO |
4121 | if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym)) |
4122 | emit_insn (gen_symGOTOFF2reg (dest, src, | |
4123 | gen_rtx_REG (Pmode, base_regno), | |
4124 | GEN_INT (R_FRV_GPREL12))); | |
4125 | else | |
4126 | emit_insn (gen_symGOTOFF2reg_hilo (dest, src, | |
4127 | gen_rtx_REG (Pmode, base_regno), | |
4128 | GEN_INT (R_FRV_GPREL12))); | |
36a05131 BS |
4129 | if (base_regno == PIC_REGNO) |
4130 | cfun->uses_pic_offset_table = TRUE; | |
34208acf AO |
4131 | return TRUE; |
4132 | } | |
36a05131 | 4133 | |
34208acf AO |
4134 | if (unspec) |
4135 | { | |
4136 | rtx x; | |
4137 | ||
4138 | /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce | |
4139 | new uses of it once reload has begun. */ | |
44e91694 | 4140 | gcc_assert (!reload_in_progress && !reload_completed); |
34208acf AO |
4141 | |
4142 | switch (unspec) | |
4143 | { | |
4144 | case R_FRV_GOTOFF12: | |
4145 | if (!frv_small_data_reloc_p (sym, unspec)) | |
4146 | x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG, | |
4147 | GEN_INT (unspec)); | |
4148 | else | |
4149 | x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); | |
4150 | break; | |
4151 | case R_FRV_GPREL12: | |
4152 | if (!frv_small_data_reloc_p (sym, unspec)) | |
4153 | x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG, | |
4154 | GEN_INT (unspec)); | |
4155 | else | |
4156 | x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); | |
4157 | break; | |
4158 | case R_FRV_FUNCDESC_GOTOFF12: | |
4159 | if (flag_pic != 1) | |
4160 | x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG, | |
4161 | GEN_INT (unspec)); | |
4162 | else | |
4163 | x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); | |
4164 | break; | |
4165 | default: | |
4166 | if (flag_pic != 1) | |
4167 | x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG, | |
4168 | GEN_INT (unspec)); | |
4169 | else | |
4170 | x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); | |
4171 | break; | |
4172 | } | |
4173 | emit_insn (x); | |
4174 | cfun->uses_pic_offset_table = TRUE; | |
36a05131 BS |
4175 | return TRUE; |
4176 | } | |
4177 | ||
34208acf | 4178 | |
36a05131 BS |
4179 | return FALSE; |
4180 | } | |
4181 | ||
4182 | \f | |
4183 | /* Return a string to output a single word move. */ | |
4184 | ||
4185 | const char * | |
f2206911 | 4186 | output_move_single (rtx operands[], rtx insn) |
36a05131 BS |
4187 | { |
4188 | rtx dest = operands[0]; | |
4189 | rtx src = operands[1]; | |
4190 | ||
4191 | if (GET_CODE (dest) == REG) | |
4192 | { | |
4193 | int dest_regno = REGNO (dest); | |
4194 | enum machine_mode mode = GET_MODE (dest); | |
4195 | ||
4196 | if (GPR_P (dest_regno)) | |
4197 | { | |
4198 | if (GET_CODE (src) == REG) | |
4199 | { | |
4200 | /* gpr <- some sort of register */ | |
4201 | int src_regno = REGNO (src); | |
4202 | ||
4203 | if (GPR_P (src_regno)) | |
4204 | return "mov %1, %0"; | |
4205 | ||
4206 | else if (FPR_P (src_regno)) | |
4207 | return "movfg %1, %0"; | |
4208 | ||
4209 | else if (SPR_P (src_regno)) | |
4210 | return "movsg %1, %0"; | |
4211 | } | |
4212 | ||
4213 | else if (GET_CODE (src) == MEM) | |
4214 | { | |
4215 | /* gpr <- memory */ | |
4216 | switch (mode) | |
4217 | { | |
4218 | default: | |
4219 | break; | |
4220 | ||
4221 | case QImode: | |
4222 | return "ldsb%I1%U1 %M1,%0"; | |
4223 | ||
4224 | case HImode: | |
4225 | return "ldsh%I1%U1 %M1,%0"; | |
4226 | ||
4227 | case SImode: | |
4228 | case SFmode: | |
4229 | return "ld%I1%U1 %M1, %0"; | |
4230 | } | |
4231 | } | |
4232 | ||
4233 | else if (GET_CODE (src) == CONST_INT | |
4234 | || GET_CODE (src) == CONST_DOUBLE) | |
4235 | { | |
4236 | /* gpr <- integer/floating constant */ | |
4237 | HOST_WIDE_INT value; | |
4238 | ||
4239 | if (GET_CODE (src) == CONST_INT) | |
4240 | value = INTVAL (src); | |
4241 | ||
4242 | else if (mode == SFmode) | |
4243 | { | |
4244 | REAL_VALUE_TYPE rv; | |
4245 | long l; | |
4246 | ||
4247 | REAL_VALUE_FROM_CONST_DOUBLE (rv, src); | |
4248 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
4249 | value = l; | |
4250 | } | |
4251 | ||
4252 | else | |
4253 | value = CONST_DOUBLE_LOW (src); | |
4254 | ||
4255 | if (IN_RANGE_P (value, -32768, 32767)) | |
4256 | return "setlos %1, %0"; | |
4257 | ||
4258 | return "#"; | |
4259 | } | |
4260 | ||
4261 | else if (GET_CODE (src) == SYMBOL_REF | |
4262 | || GET_CODE (src) == LABEL_REF | |
4263 | || GET_CODE (src) == CONST) | |
4264 | { | |
36a05131 BS |
4265 | return "#"; |
4266 | } | |
4267 | } | |
4268 | ||
4269 | else if (FPR_P (dest_regno)) | |
4270 | { | |
4271 | if (GET_CODE (src) == REG) | |
4272 | { | |
4273 | /* fpr <- some sort of register */ | |
4274 | int src_regno = REGNO (src); | |
4275 | ||
4276 | if (GPR_P (src_regno)) | |
4277 | return "movgf %1, %0"; | |
4278 | ||
4279 | else if (FPR_P (src_regno)) | |
4280 | { | |
4281 | if (TARGET_HARD_FLOAT) | |
4282 | return "fmovs %1, %0"; | |
4283 | else | |
4284 | return "mor %1, %1, %0"; | |
4285 | } | |
4286 | } | |
4287 | ||
4288 | else if (GET_CODE (src) == MEM) | |
4289 | { | |
4290 | /* fpr <- memory */ | |
4291 | switch (mode) | |
4292 | { | |
4293 | default: | |
4294 | break; | |
4295 | ||
4296 | case QImode: | |
4297 | return "ldbf%I1%U1 %M1,%0"; | |
4298 | ||
4299 | case HImode: | |
4300 | return "ldhf%I1%U1 %M1,%0"; | |
4301 | ||
4302 | case SImode: | |
4303 | case SFmode: | |
4304 | return "ldf%I1%U1 %M1, %0"; | |
4305 | } | |
4306 | } | |
4307 | ||
4308 | else if (ZERO_P (src)) | |
4309 | return "movgf %., %0"; | |
4310 | } | |
4311 | ||
4312 | else if (SPR_P (dest_regno)) | |
4313 | { | |
4314 | if (GET_CODE (src) == REG) | |
4315 | { | |
4316 | /* spr <- some sort of register */ | |
4317 | int src_regno = REGNO (src); | |
4318 | ||
4319 | if (GPR_P (src_regno)) | |
4320 | return "movgs %1, %0"; | |
4321 | } | |
c557edf4 RS |
4322 | else if (ZERO_P (src)) |
4323 | return "movgs %., %0"; | |
36a05131 BS |
4324 | } |
4325 | } | |
4326 | ||
4327 | else if (GET_CODE (dest) == MEM) | |
4328 | { | |
4329 | if (GET_CODE (src) == REG) | |
4330 | { | |
4331 | int src_regno = REGNO (src); | |
4332 | enum machine_mode mode = GET_MODE (dest); | |
4333 | ||
4334 | if (GPR_P (src_regno)) | |
4335 | { | |
4336 | switch (mode) | |
4337 | { | |
4338 | default: | |
4339 | break; | |
4340 | ||
4341 | case QImode: | |
4342 | return "stb%I0%U0 %1, %M0"; | |
4343 | ||
4344 | case HImode: | |
4345 | return "sth%I0%U0 %1, %M0"; | |
4346 | ||
4347 | case SImode: | |
4348 | case SFmode: | |
4349 | return "st%I0%U0 %1, %M0"; | |
4350 | } | |
4351 | } | |
4352 | ||
4353 | else if (FPR_P (src_regno)) | |
4354 | { | |
4355 | switch (mode) | |
4356 | { | |
4357 | default: | |
4358 | break; | |
4359 | ||
4360 | case QImode: | |
4361 | return "stbf%I0%U0 %1, %M0"; | |
4362 | ||
4363 | case HImode: | |
4364 | return "sthf%I0%U0 %1, %M0"; | |
4365 | ||
4366 | case SImode: | |
4367 | case SFmode: | |
4368 | return "stf%I0%U0 %1, %M0"; | |
4369 | } | |
4370 | } | |
4371 | } | |
4372 | ||
4373 | else if (ZERO_P (src)) | |
4374 | { | |
4375 | switch (GET_MODE (dest)) | |
4376 | { | |
4377 | default: | |
4378 | break; | |
4379 | ||
4380 | case QImode: | |
4381 | return "stb%I0%U0 %., %M0"; | |
4382 | ||
4383 | case HImode: | |
4384 | return "sth%I0%U0 %., %M0"; | |
4385 | ||
4386 | case SImode: | |
4387 | case SFmode: | |
4388 | return "st%I0%U0 %., %M0"; | |
4389 | } | |
4390 | } | |
4391 | } | |
4392 | ||
4393 | fatal_insn ("Bad output_move_single operand", insn); | |
4394 | return ""; | |
4395 | } | |
4396 | ||
4397 | \f | |
4398 | /* Return a string to output a double word move. */ | |
4399 | ||
4400 | const char * | |
f2206911 | 4401 | output_move_double (rtx operands[], rtx insn) |
36a05131 BS |
4402 | { |
4403 | rtx dest = operands[0]; | |
4404 | rtx src = operands[1]; | |
4405 | enum machine_mode mode = GET_MODE (dest); | |
4406 | ||
4407 | if (GET_CODE (dest) == REG) | |
4408 | { | |
4409 | int dest_regno = REGNO (dest); | |
4410 | ||
4411 | if (GPR_P (dest_regno)) | |
4412 | { | |
4413 | if (GET_CODE (src) == REG) | |
4414 | { | |
4415 | /* gpr <- some sort of register */ | |
4416 | int src_regno = REGNO (src); | |
4417 | ||
4418 | if (GPR_P (src_regno)) | |
4419 | return "#"; | |
4420 | ||
4421 | else if (FPR_P (src_regno)) | |
4422 | { | |
4423 | if (((dest_regno - GPR_FIRST) & 1) == 0 | |
4424 | && ((src_regno - FPR_FIRST) & 1) == 0) | |
4425 | return "movfgd %1, %0"; | |
4426 | ||
4427 | return "#"; | |
4428 | } | |
4429 | } | |
4430 | ||
4431 | else if (GET_CODE (src) == MEM) | |
4432 | { | |
4433 | /* gpr <- memory */ | |
4434 | if (dbl_memory_one_insn_operand (src, mode)) | |
4435 | return "ldd%I1%U1 %M1, %0"; | |
4436 | ||
4437 | return "#"; | |
4438 | } | |
4439 | ||
4440 | else if (GET_CODE (src) == CONST_INT | |
4441 | || GET_CODE (src) == CONST_DOUBLE) | |
4442 | return "#"; | |
4443 | } | |
4444 | ||
4445 | else if (FPR_P (dest_regno)) | |
4446 | { | |
4447 | if (GET_CODE (src) == REG) | |
4448 | { | |
4449 | /* fpr <- some sort of register */ | |
4450 | int src_regno = REGNO (src); | |
4451 | ||
4452 | if (GPR_P (src_regno)) | |
4453 | { | |
4454 | if (((dest_regno - FPR_FIRST) & 1) == 0 | |
4455 | && ((src_regno - GPR_FIRST) & 1) == 0) | |
4456 | return "movgfd %1, %0"; | |
4457 | ||
4458 | return "#"; | |
4459 | } | |
4460 | ||
4461 | else if (FPR_P (src_regno)) | |
4462 | { | |
4463 | if (TARGET_DOUBLE | |
4464 | && ((dest_regno - FPR_FIRST) & 1) == 0 | |
4465 | && ((src_regno - FPR_FIRST) & 1) == 0) | |
4466 | return "fmovd %1, %0"; | |
4467 | ||
4468 | return "#"; | |
4469 | } | |
4470 | } | |
4471 | ||
4472 | else if (GET_CODE (src) == MEM) | |
4473 | { | |
4474 | /* fpr <- memory */ | |
4475 | if (dbl_memory_one_insn_operand (src, mode)) | |
4476 | return "lddf%I1%U1 %M1, %0"; | |
4477 | ||
4478 | return "#"; | |
4479 | } | |
4480 | ||
4481 | else if (ZERO_P (src)) | |
4482 | return "#"; | |
4483 | } | |
4484 | } | |
4485 | ||
4486 | else if (GET_CODE (dest) == MEM) | |
4487 | { | |
4488 | if (GET_CODE (src) == REG) | |
4489 | { | |
4490 | int src_regno = REGNO (src); | |
4491 | ||
4492 | if (GPR_P (src_regno)) | |
4493 | { | |
4494 | if (((src_regno - GPR_FIRST) & 1) == 0 | |
4495 | && dbl_memory_one_insn_operand (dest, mode)) | |
4496 | return "std%I0%U0 %1, %M0"; | |
4497 | ||
4498 | return "#"; | |
4499 | } | |
4500 | ||
4501 | if (FPR_P (src_regno)) | |
4502 | { | |
4503 | if (((src_regno - FPR_FIRST) & 1) == 0 | |
4504 | && dbl_memory_one_insn_operand (dest, mode)) | |
4505 | return "stdf%I0%U0 %1, %M0"; | |
4506 | ||
4507 | return "#"; | |
4508 | } | |
4509 | } | |
4510 | ||
4511 | else if (ZERO_P (src)) | |
4512 | { | |
4513 | if (dbl_memory_one_insn_operand (dest, mode)) | |
4514 | return "std%I0%U0 %., %M0"; | |
4515 | ||
4516 | return "#"; | |
4517 | } | |
4518 | } | |
4519 | ||
4520 | fatal_insn ("Bad output_move_double operand", insn); | |
4521 | return ""; | |
4522 | } | |
4523 | ||
4524 | \f | |
4525 | /* Return a string to output a single word conditional move. | |
4526 | Operand0 -- EQ/NE of ccr register and 0 | |
4527 | Operand1 -- CCR register | |
4528 | Operand2 -- destination | |
4529 | Operand3 -- source */ | |
4530 | ||
4531 | const char * | |
f2206911 | 4532 | output_condmove_single (rtx operands[], rtx insn) |
36a05131 BS |
4533 | { |
4534 | rtx dest = operands[2]; | |
4535 | rtx src = operands[3]; | |
4536 | ||
4537 | if (GET_CODE (dest) == REG) | |
4538 | { | |
4539 | int dest_regno = REGNO (dest); | |
4540 | enum machine_mode mode = GET_MODE (dest); | |
4541 | ||
4542 | if (GPR_P (dest_regno)) | |
4543 | { | |
4544 | if (GET_CODE (src) == REG) | |
4545 | { | |
4546 | /* gpr <- some sort of register */ | |
4547 | int src_regno = REGNO (src); | |
4548 | ||
4549 | if (GPR_P (src_regno)) | |
4550 | return "cmov %z3, %2, %1, %e0"; | |
4551 | ||
4552 | else if (FPR_P (src_regno)) | |
4553 | return "cmovfg %3, %2, %1, %e0"; | |
4554 | } | |
4555 | ||
4556 | else if (GET_CODE (src) == MEM) | |
4557 | { | |
4558 | /* gpr <- memory */ | |
4559 | switch (mode) | |
4560 | { | |
4561 | default: | |
4562 | break; | |
4563 | ||
4564 | case QImode: | |
4565 | return "cldsb%I3%U3 %M3, %2, %1, %e0"; | |
4566 | ||
4567 | case HImode: | |
4568 | return "cldsh%I3%U3 %M3, %2, %1, %e0"; | |
4569 | ||
4570 | case SImode: | |
4571 | case SFmode: | |
4572 | return "cld%I3%U3 %M3, %2, %1, %e0"; | |
4573 | } | |
4574 | } | |
4575 | ||
4576 | else if (ZERO_P (src)) | |
4577 | return "cmov %., %2, %1, %e0"; | |
4578 | } | |
4579 | ||
4580 | else if (FPR_P (dest_regno)) | |
4581 | { | |
4582 | if (GET_CODE (src) == REG) | |
4583 | { | |
4584 | /* fpr <- some sort of register */ | |
4585 | int src_regno = REGNO (src); | |
4586 | ||
4587 | if (GPR_P (src_regno)) | |
4588 | return "cmovgf %3, %2, %1, %e0"; | |
4589 | ||
4590 | else if (FPR_P (src_regno)) | |
4591 | { | |
4592 | if (TARGET_HARD_FLOAT) | |
4593 | return "cfmovs %3,%2,%1,%e0"; | |
4594 | else | |
4595 | return "cmor %3, %3, %2, %1, %e0"; | |
4596 | } | |
4597 | } | |
4598 | ||
4599 | else if (GET_CODE (src) == MEM) | |
4600 | { | |
4601 | /* fpr <- memory */ | |
4602 | if (mode == SImode || mode == SFmode) | |
4603 | return "cldf%I3%U3 %M3, %2, %1, %e0"; | |
4604 | } | |
4605 | ||
4606 | else if (ZERO_P (src)) | |
4607 | return "cmovgf %., %2, %1, %e0"; | |
4608 | } | |
4609 | } | |
4610 | ||
4611 | else if (GET_CODE (dest) == MEM) | |
4612 | { | |
4613 | if (GET_CODE (src) == REG) | |
4614 | { | |
4615 | int src_regno = REGNO (src); | |
4616 | enum machine_mode mode = GET_MODE (dest); | |
4617 | ||
4618 | if (GPR_P (src_regno)) | |
4619 | { | |
4620 | switch (mode) | |
4621 | { | |
4622 | default: | |
4623 | break; | |
4624 | ||
4625 | case QImode: | |
4626 | return "cstb%I2%U2 %3, %M2, %1, %e0"; | |
4627 | ||
4628 | case HImode: | |
4629 | return "csth%I2%U2 %3, %M2, %1, %e0"; | |
4630 | ||
4631 | case SImode: | |
4632 | case SFmode: | |
4633 | return "cst%I2%U2 %3, %M2, %1, %e0"; | |
4634 | } | |
4635 | } | |
4636 | ||
4637 | else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode)) | |
4638 | return "cstf%I2%U2 %3, %M2, %1, %e0"; | |
4639 | } | |
4640 | ||
4641 | else if (ZERO_P (src)) | |
4642 | { | |
4643 | enum machine_mode mode = GET_MODE (dest); | |
4644 | switch (mode) | |
4645 | { | |
4646 | default: | |
4647 | break; | |
4648 | ||
4649 | case QImode: | |
4650 | return "cstb%I2%U2 %., %M2, %1, %e0"; | |
4651 | ||
4652 | case HImode: | |
4653 | return "csth%I2%U2 %., %M2, %1, %e0"; | |
4654 | ||
4655 | case SImode: | |
4656 | case SFmode: | |
4657 | return "cst%I2%U2 %., %M2, %1, %e0"; | |
4658 | } | |
4659 | } | |
4660 | } | |
4661 | ||
4662 | fatal_insn ("Bad output_condmove_single operand", insn); | |
4663 | return ""; | |
4664 | } | |
4665 | ||
4666 | \f | |
4667 | /* Emit the appropriate code to do a comparison, returning the register the | |
4668 | comparison was done it. */ | |
4669 | ||
4670 | static rtx | |
f2206911 | 4671 | frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1) |
36a05131 BS |
4672 | { |
4673 | enum machine_mode cc_mode; | |
4674 | rtx cc_reg; | |
4675 | ||
87b483a1 | 4676 | /* Floating point doesn't have comparison against a constant. */ |
36a05131 BS |
4677 | if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG) |
4678 | op1 = force_reg (GET_MODE (op0), op1); | |
4679 | ||
4680 | /* Possibly disable using anything but a fixed register in order to work | |
4681 | around cse moving comparisons past function calls. */ | |
4682 | cc_mode = SELECT_CC_MODE (test, op0, op1); | |
4683 | cc_reg = ((TARGET_ALLOC_CC) | |
4684 | ? gen_reg_rtx (cc_mode) | |
4685 | : gen_rtx_REG (cc_mode, | |
4686 | (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST)); | |
4687 | ||
4688 | emit_insn (gen_rtx_SET (VOIDmode, cc_reg, | |
4689 | gen_rtx_COMPARE (cc_mode, op0, op1))); | |
4690 | ||
4691 | return cc_reg; | |
4692 | } | |
4693 | ||
4694 | \f | |
4695 | /* Emit code for a conditional branch. The comparison operands were previously | |
4696 | stored in frv_compare_op0 and frv_compare_op1. | |
4697 | ||
4698 | XXX: I originally wanted to add a clobber of a CCR register to use in | |
4699 | conditional execution, but that confuses the rest of the compiler. */ | |
4700 | ||
4701 | int | |
f2206911 | 4702 | frv_emit_cond_branch (enum rtx_code test, rtx label) |
36a05131 BS |
4703 | { |
4704 | rtx test_rtx; | |
4705 | rtx label_ref; | |
4706 | rtx if_else; | |
4707 | rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1); | |
4708 | enum machine_mode cc_mode = GET_MODE (cc_reg); | |
4709 | ||
4710 | /* Branches generate: | |
4711 | (set (pc) | |
4712 | (if_then_else (<test>, <cc_reg>, (const_int 0)) | |
4713 | (label_ref <branch_label>) | |
4714 | (pc))) */ | |
4715 | label_ref = gen_rtx_LABEL_REF (VOIDmode, label); | |
1c563bed | 4716 | test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx); |
36a05131 BS |
4717 | if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx); |
4718 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else)); | |
4719 | return TRUE; | |
4720 | } | |
4721 | ||
4722 | \f | |
4723 | /* Emit code to set a gpr to 1/0 based on a comparison. The comparison | |
4724 | operands were previously stored in frv_compare_op0 and frv_compare_op1. */ | |
4725 | ||
4726 | int | |
f2206911 | 4727 | frv_emit_scc (enum rtx_code test, rtx target) |
36a05131 BS |
4728 | { |
4729 | rtx set; | |
4730 | rtx test_rtx; | |
4731 | rtx clobber; | |
4732 | rtx cr_reg; | |
4733 | rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1); | |
4734 | ||
4735 | /* SCC instructions generate: | |
4736 | (parallel [(set <target> (<test>, <cc_reg>, (const_int 0)) | |
4737 | (clobber (<ccr_reg>))]) */ | |
4738 | test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx); | |
4739 | set = gen_rtx_SET (VOIDmode, target, test_rtx); | |
4740 | ||
4741 | cr_reg = ((TARGET_ALLOC_CC) | |
4742 | ? gen_reg_rtx (CC_CCRmode) | |
4743 | : gen_rtx_REG (CC_CCRmode, | |
4744 | ((GET_MODE (cc_reg) == CC_FPmode) | |
4745 | ? FCR_FIRST | |
4746 | : ICR_FIRST))); | |
4747 | ||
4748 | clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg); | |
4749 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber))); | |
4750 | return TRUE; | |
4751 | } | |
4752 | ||
4753 | \f | |
4754 | /* Split a SCC instruction into component parts, returning a SEQUENCE to hold | |
839a4992 | 4755 | the separate insns. */ |
36a05131 BS |
4756 | |
4757 | rtx | |
f2206911 | 4758 | frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value) |
36a05131 BS |
4759 | { |
4760 | rtx ret; | |
4761 | ||
4762 | start_sequence (); | |
4763 | ||
4764 | /* Set the appropriate CCR bit. */ | |
4765 | emit_insn (gen_rtx_SET (VOIDmode, | |
4766 | cr_reg, | |
4767 | gen_rtx_fmt_ee (GET_CODE (test), | |
4768 | GET_MODE (cr_reg), | |
4769 | cc_reg, | |
4770 | const0_rtx))); | |
4771 | ||
4772 | /* Move the value into the destination. */ | |
4773 | emit_move_insn (dest, GEN_INT (value)); | |
4774 | ||
4775 | /* Move 0 into the destination if the test failed */ | |
4776 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
4777 | gen_rtx_EQ (GET_MODE (cr_reg), | |
4778 | cr_reg, | |
4779 | const0_rtx), | |
4780 | gen_rtx_SET (VOIDmode, dest, const0_rtx))); | |
4781 | ||
4782 | /* Finish up, return sequence. */ | |
4783 | ret = get_insns (); | |
4784 | end_sequence (); | |
4785 | return ret; | |
4786 | } | |
4787 | ||
4788 | \f | |
4789 | /* Emit the code for a conditional move, return TRUE if we could do the | |
4790 | move. */ | |
4791 | ||
4792 | int | |
f2206911 | 4793 | frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2) |
36a05131 BS |
4794 | { |
4795 | rtx set; | |
4796 | rtx clobber_cc; | |
4797 | rtx test2; | |
4798 | rtx cr_reg; | |
4799 | rtx if_rtx; | |
4800 | enum rtx_code test = GET_CODE (test_rtx); | |
4801 | rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1); | |
4802 | enum machine_mode cc_mode = GET_MODE (cc_reg); | |
4803 | ||
4804 | /* Conditional move instructions generate: | |
4805 | (parallel [(set <target> | |
4806 | (if_then_else (<test> <cc_reg> (const_int 0)) | |
4807 | <src1> | |
4808 | <src2>)) | |
4809 | (clobber (<ccr_reg>))]) */ | |
4810 | ||
4811 | /* Handle various cases of conditional move involving two constants. */ | |
4812 | if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT) | |
4813 | { | |
4814 | HOST_WIDE_INT value1 = INTVAL (src1); | |
4815 | HOST_WIDE_INT value2 = INTVAL (src2); | |
4816 | ||
87b483a1 | 4817 | /* Having 0 as one of the constants can be done by loading the other |
36a05131 BS |
4818 | constant, and optionally moving in gr0. */ |
4819 | if (value1 == 0 || value2 == 0) | |
4820 | ; | |
4821 | ||
4822 | /* If the first value is within an addi range and also the difference | |
4823 | between the two fits in an addi's range, load up the difference, then | |
4824 | conditionally move in 0, and then unconditionally add the first | |
4825 | value. */ | |
4826 | else if (IN_RANGE_P (value1, -2048, 2047) | |
4827 | && IN_RANGE_P (value2 - value1, -2048, 2047)) | |
4828 | ; | |
4829 | ||
4830 | /* If neither condition holds, just force the constant into a | |
4831 | register. */ | |
4832 | else | |
4833 | { | |
4834 | src1 = force_reg (GET_MODE (dest), src1); | |
4835 | src2 = force_reg (GET_MODE (dest), src2); | |
4836 | } | |
4837 | } | |
4838 | ||
4839 | /* If one value is a register, insure the other value is either 0 or a | |
4840 | register. */ | |
4841 | else | |
4842 | { | |
4843 | if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0) | |
4844 | src1 = force_reg (GET_MODE (dest), src1); | |
4845 | ||
4846 | if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0) | |
4847 | src2 = force_reg (GET_MODE (dest), src2); | |
4848 | } | |
4849 | ||
4850 | test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx); | |
4851 | if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2); | |
4852 | ||
4853 | set = gen_rtx_SET (VOIDmode, dest, if_rtx); | |
4854 | ||
4855 | cr_reg = ((TARGET_ALLOC_CC) | |
4856 | ? gen_reg_rtx (CC_CCRmode) | |
4857 | : gen_rtx_REG (CC_CCRmode, | |
4858 | (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST)); | |
4859 | ||
4860 | clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg); | |
4861 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc))); | |
4862 | return TRUE; | |
4863 | } | |
4864 | ||
4865 | \f | |
839a4992 | 4866 | /* Split a conditional move into constituent parts, returning a SEQUENCE |
36a05131 BS |
4867 | containing all of the insns. */ |
4868 | ||
4869 | rtx | |
f2206911 | 4870 | frv_split_cond_move (rtx operands[]) |
36a05131 BS |
4871 | { |
4872 | rtx dest = operands[0]; | |
4873 | rtx test = operands[1]; | |
4874 | rtx cc_reg = operands[2]; | |
4875 | rtx src1 = operands[3]; | |
4876 | rtx src2 = operands[4]; | |
4877 | rtx cr_reg = operands[5]; | |
4878 | rtx ret; | |
4879 | enum machine_mode cr_mode = GET_MODE (cr_reg); | |
4880 | ||
4881 | start_sequence (); | |
4882 | ||
4883 | /* Set the appropriate CCR bit. */ | |
4884 | emit_insn (gen_rtx_SET (VOIDmode, | |
4885 | cr_reg, | |
4886 | gen_rtx_fmt_ee (GET_CODE (test), | |
4887 | GET_MODE (cr_reg), | |
4888 | cc_reg, | |
4889 | const0_rtx))); | |
4890 | ||
4891 | /* Handle various cases of conditional move involving two constants. */ | |
4892 | if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT) | |
4893 | { | |
4894 | HOST_WIDE_INT value1 = INTVAL (src1); | |
4895 | HOST_WIDE_INT value2 = INTVAL (src2); | |
4896 | ||
87b483a1 | 4897 | /* Having 0 as one of the constants can be done by loading the other |
36a05131 BS |
4898 | constant, and optionally moving in gr0. */ |
4899 | if (value1 == 0) | |
4900 | { | |
4901 | emit_move_insn (dest, src2); | |
4902 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
4903 | gen_rtx_NE (cr_mode, cr_reg, | |
4904 | const0_rtx), | |
4905 | gen_rtx_SET (VOIDmode, dest, src1))); | |
4906 | } | |
4907 | ||
4908 | else if (value2 == 0) | |
4909 | { | |
4910 | emit_move_insn (dest, src1); | |
4911 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
4912 | gen_rtx_EQ (cr_mode, cr_reg, | |
4913 | const0_rtx), | |
4914 | gen_rtx_SET (VOIDmode, dest, src2))); | |
4915 | } | |
4916 | ||
4917 | /* If the first value is within an addi range and also the difference | |
4918 | between the two fits in an addi's range, load up the difference, then | |
4919 | conditionally move in 0, and then unconditionally add the first | |
4920 | value. */ | |
4921 | else if (IN_RANGE_P (value1, -2048, 2047) | |
4922 | && IN_RANGE_P (value2 - value1, -2048, 2047)) | |
4923 | { | |
4924 | rtx dest_si = ((GET_MODE (dest) == SImode) | |
4925 | ? dest | |
4926 | : gen_rtx_SUBREG (SImode, dest, 0)); | |
4927 | ||
4928 | emit_move_insn (dest_si, GEN_INT (value2 - value1)); | |
4929 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
4930 | gen_rtx_NE (cr_mode, cr_reg, | |
4931 | const0_rtx), | |
4932 | gen_rtx_SET (VOIDmode, dest_si, | |
4933 | const0_rtx))); | |
4934 | emit_insn (gen_addsi3 (dest_si, dest_si, src1)); | |
4935 | } | |
4936 | ||
4937 | else | |
44e91694 | 4938 | gcc_unreachable (); |
36a05131 BS |
4939 | } |
4940 | else | |
4941 | { | |
4942 | /* Emit the conditional move for the test being true if needed. */ | |
4943 | if (! rtx_equal_p (dest, src1)) | |
4944 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
4945 | gen_rtx_NE (cr_mode, cr_reg, const0_rtx), | |
4946 | gen_rtx_SET (VOIDmode, dest, src1))); | |
4947 | ||
4948 | /* Emit the conditional move for the test being false if needed. */ | |
4949 | if (! rtx_equal_p (dest, src2)) | |
4950 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
4951 | gen_rtx_EQ (cr_mode, cr_reg, const0_rtx), | |
4952 | gen_rtx_SET (VOIDmode, dest, src2))); | |
4953 | } | |
4954 | ||
4955 | /* Finish up, return sequence. */ | |
4956 | ret = get_insns (); | |
4957 | end_sequence (); | |
4958 | return ret; | |
4959 | } | |
4960 | ||
4961 | \f | |
4962 | /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a | |
4963 | memory location that is not known to be dword-aligned. */ | |
4964 | void | |
f2206911 | 4965 | frv_split_double_load (rtx dest, rtx source) |
36a05131 BS |
4966 | { |
4967 | int regno = REGNO (dest); | |
4968 | rtx dest1 = gen_highpart (SImode, dest); | |
4969 | rtx dest2 = gen_lowpart (SImode, dest); | |
4970 | rtx address = XEXP (source, 0); | |
4971 | ||
4972 | /* If the address is pre-modified, load the lower-numbered register | |
4973 | first, then load the other register using an integer offset from | |
4974 | the modified base register. This order should always be safe, | |
4975 | since the pre-modification cannot affect the same registers as the | |
4976 | load does. | |
4977 | ||
4978 | The situation for other loads is more complicated. Loading one | |
4979 | of the registers could affect the value of ADDRESS, so we must | |
4980 | be careful which order we do them in. */ | |
4981 | if (GET_CODE (address) == PRE_MODIFY | |
4982 | || ! refers_to_regno_p (regno, regno + 1, address, NULL)) | |
4983 | { | |
4984 | /* It is safe to load the lower-numbered register first. */ | |
4985 | emit_move_insn (dest1, change_address (source, SImode, NULL)); | |
4986 | emit_move_insn (dest2, frv_index_memory (source, SImode, 1)); | |
4987 | } | |
4988 | else | |
4989 | { | |
4990 | /* ADDRESS is not pre-modified and the address depends on the | |
4991 | lower-numbered register. Load the higher-numbered register | |
4992 | first. */ | |
4993 | emit_move_insn (dest2, frv_index_memory (source, SImode, 1)); | |
4994 | emit_move_insn (dest1, change_address (source, SImode, NULL)); | |
4995 | } | |
4996 | } | |
4997 | ||
4998 | /* Split (set DEST SOURCE), where DEST refers to a dword memory location | |
4999 | and SOURCE is either a double register or the constant zero. */ | |
5000 | void | |
f2206911 | 5001 | frv_split_double_store (rtx dest, rtx source) |
36a05131 BS |
5002 | { |
5003 | rtx dest1 = change_address (dest, SImode, NULL); | |
5004 | rtx dest2 = frv_index_memory (dest, SImode, 1); | |
5005 | if (ZERO_P (source)) | |
5006 | { | |
5007 | emit_move_insn (dest1, CONST0_RTX (SImode)); | |
5008 | emit_move_insn (dest2, CONST0_RTX (SImode)); | |
5009 | } | |
5010 | else | |
5011 | { | |
5012 | emit_move_insn (dest1, gen_highpart (SImode, source)); | |
5013 | emit_move_insn (dest2, gen_lowpart (SImode, source)); | |
5014 | } | |
5015 | } | |
5016 | ||
5017 | \f | |
5018 | /* Split a min/max operation returning a SEQUENCE containing all of the | |
5019 | insns. */ | |
5020 | ||
5021 | rtx | |
f2206911 | 5022 | frv_split_minmax (rtx operands[]) |
36a05131 BS |
5023 | { |
5024 | rtx dest = operands[0]; | |
5025 | rtx minmax = operands[1]; | |
5026 | rtx src1 = operands[2]; | |
5027 | rtx src2 = operands[3]; | |
5028 | rtx cc_reg = operands[4]; | |
5029 | rtx cr_reg = operands[5]; | |
5030 | rtx ret; | |
5031 | enum rtx_code test_code; | |
5032 | enum machine_mode cr_mode = GET_MODE (cr_reg); | |
5033 | ||
5034 | start_sequence (); | |
5035 | ||
87b483a1 | 5036 | /* Figure out which test to use. */ |
36a05131 BS |
5037 | switch (GET_CODE (minmax)) |
5038 | { | |
5039 | default: | |
44e91694 | 5040 | gcc_unreachable (); |
36a05131 BS |
5041 | |
5042 | case SMIN: test_code = LT; break; | |
5043 | case SMAX: test_code = GT; break; | |
5044 | case UMIN: test_code = LTU; break; | |
5045 | case UMAX: test_code = GTU; break; | |
5046 | } | |
5047 | ||
5048 | /* Issue the compare instruction. */ | |
5049 | emit_insn (gen_rtx_SET (VOIDmode, | |
5050 | cc_reg, | |
5051 | gen_rtx_COMPARE (GET_MODE (cc_reg), | |
5052 | src1, src2))); | |
5053 | ||
5054 | /* Set the appropriate CCR bit. */ | |
5055 | emit_insn (gen_rtx_SET (VOIDmode, | |
5056 | cr_reg, | |
5057 | gen_rtx_fmt_ee (test_code, | |
5058 | GET_MODE (cr_reg), | |
5059 | cc_reg, | |
5060 | const0_rtx))); | |
5061 | ||
9cd10576 | 5062 | /* If are taking the min/max of a nonzero constant, load that first, and |
36a05131 BS |
5063 | then do a conditional move of the other value. */ |
5064 | if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0) | |
5065 | { | |
44e91694 | 5066 | gcc_assert (!rtx_equal_p (dest, src1)); |
36a05131 BS |
5067 | |
5068 | emit_move_insn (dest, src2); | |
5069 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
5070 | gen_rtx_NE (cr_mode, cr_reg, const0_rtx), | |
5071 | gen_rtx_SET (VOIDmode, dest, src1))); | |
5072 | } | |
5073 | ||
5074 | /* Otherwise, do each half of the move. */ | |
5075 | else | |
5076 | { | |
5077 | /* Emit the conditional move for the test being true if needed. */ | |
5078 | if (! rtx_equal_p (dest, src1)) | |
5079 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
5080 | gen_rtx_NE (cr_mode, cr_reg, const0_rtx), | |
5081 | gen_rtx_SET (VOIDmode, dest, src1))); | |
5082 | ||
5083 | /* Emit the conditional move for the test being false if needed. */ | |
5084 | if (! rtx_equal_p (dest, src2)) | |
5085 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
5086 | gen_rtx_EQ (cr_mode, cr_reg, const0_rtx), | |
5087 | gen_rtx_SET (VOIDmode, dest, src2))); | |
5088 | } | |
5089 | ||
5090 | /* Finish up, return sequence. */ | |
5091 | ret = get_insns (); | |
5092 | end_sequence (); | |
5093 | return ret; | |
5094 | } | |
5095 | ||
5096 | \f | |
5097 | /* Split an integer abs operation returning a SEQUENCE containing all of the | |
5098 | insns. */ | |
5099 | ||
5100 | rtx | |
f2206911 | 5101 | frv_split_abs (rtx operands[]) |
36a05131 BS |
5102 | { |
5103 | rtx dest = operands[0]; | |
5104 | rtx src = operands[1]; | |
5105 | rtx cc_reg = operands[2]; | |
5106 | rtx cr_reg = operands[3]; | |
5107 | rtx ret; | |
5108 | ||
5109 | start_sequence (); | |
5110 | ||
5111 | /* Issue the compare < 0 instruction. */ | |
5112 | emit_insn (gen_rtx_SET (VOIDmode, | |
5113 | cc_reg, | |
5114 | gen_rtx_COMPARE (CCmode, src, const0_rtx))); | |
5115 | ||
5116 | /* Set the appropriate CCR bit. */ | |
5117 | emit_insn (gen_rtx_SET (VOIDmode, | |
5118 | cr_reg, | |
5119 | gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx))); | |
5120 | ||
87b483a1 | 5121 | /* Emit the conditional negate if the value is negative. */ |
36a05131 BS |
5122 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, |
5123 | gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx), | |
5124 | gen_negsi2 (dest, src))); | |
5125 | ||
5126 | /* Emit the conditional move for the test being false if needed. */ | |
5127 | if (! rtx_equal_p (dest, src)) | |
5128 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
5129 | gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx), | |
5130 | gen_rtx_SET (VOIDmode, dest, src))); | |
5131 | ||
5132 | /* Finish up, return sequence. */ | |
5133 | ret = get_insns (); | |
5134 | end_sequence (); | |
5135 | return ret; | |
5136 | } | |
5137 | ||
5138 | \f | |
5139 | /* An internal function called by for_each_rtx to clear in a hard_reg set each | |
5140 | register used in an insn. */ | |
5141 | ||
5142 | static int | |
f2206911 | 5143 | frv_clear_registers_used (rtx *ptr, void *data) |
36a05131 BS |
5144 | { |
5145 | if (GET_CODE (*ptr) == REG) | |
5146 | { | |
5147 | int regno = REGNO (*ptr); | |
5148 | HARD_REG_SET *p_regs = (HARD_REG_SET *)data; | |
5149 | ||
5150 | if (regno < FIRST_PSEUDO_REGISTER) | |
5151 | { | |
5152 | int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr)); | |
5153 | ||
5154 | while (regno < reg_max) | |
5155 | { | |
5156 | CLEAR_HARD_REG_BIT (*p_regs, regno); | |
5157 | regno++; | |
5158 | } | |
5159 | } | |
5160 | } | |
5161 | ||
5162 | return 0; | |
5163 | } | |
5164 | ||
5165 | \f | |
5166 | /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */ | |
5167 | ||
5168 | /* On the FR-V, we don't have any extra fields per se, but it is useful hook to | |
5169 | initialize the static storage. */ | |
5170 | void | |
f2206911 | 5171 | frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED) |
36a05131 BS |
5172 | { |
5173 | frv_ifcvt.added_insns_list = NULL_RTX; | |
5174 | frv_ifcvt.cur_scratch_regs = 0; | |
5175 | frv_ifcvt.num_nested_cond_exec = 0; | |
5176 | frv_ifcvt.cr_reg = NULL_RTX; | |
5177 | frv_ifcvt.nested_cc_reg = NULL_RTX; | |
5178 | frv_ifcvt.extra_int_cr = NULL_RTX; | |
5179 | frv_ifcvt.extra_fp_cr = NULL_RTX; | |
5180 | frv_ifcvt.last_nested_if_cr = NULL_RTX; | |
5181 | } | |
5182 | ||
5183 | \f | |
1ae58c30 | 5184 | /* Internal function to add a potential insn to the list of insns to be inserted |
36a05131 BS |
5185 | if the conditional execution conversion is successful. */ |
5186 | ||
5187 | static void | |
f2206911 | 5188 | frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p) |
36a05131 BS |
5189 | { |
5190 | rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn); | |
5191 | ||
87b483a1 | 5192 | link->jump = before_p; /* Mark to add this before or after insn. */ |
36a05131 BS |
5193 | frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link, |
5194 | frv_ifcvt.added_insns_list); | |
5195 | ||
5196 | if (TARGET_DEBUG_COND_EXEC) | |
5197 | { | |
5198 | fprintf (stderr, | |
5199 | "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n", | |
5200 | (before_p) ? "before" : "after", | |
5201 | (int)INSN_UID (insn)); | |
5202 | ||
5203 | debug_rtx (pattern); | |
5204 | } | |
5205 | } | |
5206 | ||
5207 | \f | |
5208 | /* A C expression to modify the code described by the conditional if | |
5209 | information CE_INFO, possibly updating the tests in TRUE_EXPR, and | |
5210 | FALSE_EXPR for converting if-then and if-then-else code to conditional | |
5211 | instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the | |
5212 | tests cannot be converted. */ | |
5213 | ||
5214 | void | |
f2206911 | 5215 | frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false) |
36a05131 BS |
5216 | { |
5217 | basic_block test_bb = ce_info->test_bb; /* test basic block */ | |
5218 | basic_block then_bb = ce_info->then_bb; /* THEN */ | |
5219 | basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */ | |
5220 | basic_block join_bb = ce_info->join_bb; /* join block or NULL */ | |
5221 | rtx true_expr = *p_true; | |
5222 | rtx cr; | |
5223 | rtx cc; | |
5224 | rtx nested_cc; | |
5225 | enum machine_mode mode = GET_MODE (true_expr); | |
5226 | int j; | |
5227 | basic_block *bb; | |
5228 | int num_bb; | |
5229 | frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg; | |
5230 | rtx check_insn; | |
5231 | rtx sub_cond_exec_reg; | |
5232 | enum rtx_code code; | |
5233 | enum rtx_code code_true; | |
5234 | enum rtx_code code_false; | |
5235 | enum reg_class cc_class; | |
5236 | enum reg_class cr_class; | |
5237 | int cc_first; | |
5238 | int cc_last; | |
a2041967 | 5239 | reg_set_iterator rsi; |
36a05131 BS |
5240 | |
5241 | /* Make sure we are only dealing with hard registers. Also honor the | |
5242 | -mno-cond-exec switch, and -mno-nested-cond-exec switches if | |
5243 | applicable. */ | |
0b2c18fe RS |
5244 | if (!reload_completed || !TARGET_COND_EXEC |
5245 | || (!TARGET_NESTED_CE && ce_info->pass > 1)) | |
36a05131 BS |
5246 | goto fail; |
5247 | ||
5248 | /* Figure out which registers we can allocate for our own purposes. Only | |
5249 | consider registers that are not preserved across function calls and are | |
5250 | not fixed. However, allow the ICC/ICR temporary registers to be allocated | |
87b483a1 | 5251 | if we did not need to use them in reloading other registers. */ |
fad205ff | 5252 | memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs)); |
36a05131 BS |
5253 | COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set); |
5254 | AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set); | |
5255 | SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP); | |
5256 | SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP); | |
5257 | ||
5258 | /* If this is a nested IF, we need to discover whether the CC registers that | |
5259 | are set/used inside of the block are used anywhere else. If not, we can | |
5260 | change them to be the CC register that is paired with the CR register that | |
5261 | controls the outermost IF block. */ | |
5262 | if (ce_info->pass > 1) | |
5263 | { | |
5264 | CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite); | |
5265 | for (j = CC_FIRST; j <= CC_LAST; j++) | |
5266 | if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) | |
5267 | { | |
5e2d947c | 5268 | if (REGNO_REG_SET_P (then_bb->il.rtl->global_live_at_start, j)) |
36a05131 BS |
5269 | continue; |
5270 | ||
5e2d947c JH |
5271 | if (else_bb |
5272 | && REGNO_REG_SET_P (else_bb->il.rtl->global_live_at_start, j)) | |
36a05131 BS |
5273 | continue; |
5274 | ||
5e2d947c JH |
5275 | if (join_bb |
5276 | && REGNO_REG_SET_P (join_bb->il.rtl->global_live_at_start, j)) | |
36a05131 BS |
5277 | continue; |
5278 | ||
5279 | SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j); | |
5280 | } | |
5281 | } | |
5282 | ||
5283 | for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++) | |
5284 | frv_ifcvt.scratch_regs[j] = NULL_RTX; | |
5285 | ||
5286 | frv_ifcvt.added_insns_list = NULL_RTX; | |
5287 | frv_ifcvt.cur_scratch_regs = 0; | |
5288 | ||
5289 | bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks) | |
5290 | * sizeof (basic_block)); | |
5291 | ||
5292 | if (join_bb) | |
5293 | { | |
5294 | int regno; | |
5295 | ||
5296 | /* Remove anything live at the beginning of the join block from being | |
5297 | available for allocation. */ | |
5e2d947c | 5298 | EXECUTE_IF_SET_IN_REG_SET (join_bb->il.rtl->global_live_at_start, 0, regno, rsi) |
a2041967 KH |
5299 | { |
5300 | if (regno < FIRST_PSEUDO_REGISTER) | |
5301 | CLEAR_HARD_REG_BIT (tmp_reg->regs, regno); | |
5302 | } | |
36a05131 BS |
5303 | } |
5304 | ||
5305 | /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */ | |
5306 | num_bb = 0; | |
5307 | if (ce_info->num_multiple_test_blocks) | |
5308 | { | |
5309 | basic_block multiple_test_bb = ce_info->last_test_bb; | |
5310 | ||
5311 | while (multiple_test_bb != test_bb) | |
5312 | { | |
5313 | bb[num_bb++] = multiple_test_bb; | |
628f6a4e | 5314 | multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src; |
36a05131 BS |
5315 | } |
5316 | } | |
5317 | ||
5318 | /* Add in the THEN and ELSE blocks to be scanned. */ | |
5319 | bb[num_bb++] = then_bb; | |
5320 | if (else_bb) | |
5321 | bb[num_bb++] = else_bb; | |
5322 | ||
5323 | sub_cond_exec_reg = NULL_RTX; | |
5324 | frv_ifcvt.num_nested_cond_exec = 0; | |
5325 | ||
5326 | /* Scan all of the blocks for registers that must not be allocated. */ | |
5327 | for (j = 0; j < num_bb; j++) | |
5328 | { | |
a813c111 SB |
5329 | rtx last_insn = BB_END (bb[j]); |
5330 | rtx insn = BB_HEAD (bb[j]); | |
36a05131 BS |
5331 | int regno; |
5332 | ||
c263766c RH |
5333 | if (dump_file) |
5334 | fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n", | |
36a05131 BS |
5335 | (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"), |
5336 | (int) bb[j]->index, | |
a813c111 SB |
5337 | (int) INSN_UID (BB_HEAD (bb[j])), |
5338 | (int) INSN_UID (BB_END (bb[j]))); | |
36a05131 BS |
5339 | |
5340 | /* Anything live at the beginning of the block is obviously unavailable | |
5341 | for allocation. */ | |
5e2d947c | 5342 | EXECUTE_IF_SET_IN_REG_SET (bb[j]->il.rtl->global_live_at_start, 0, regno, rsi) |
a2041967 KH |
5343 | { |
5344 | if (regno < FIRST_PSEUDO_REGISTER) | |
5345 | CLEAR_HARD_REG_BIT (tmp_reg->regs, regno); | |
5346 | } | |
36a05131 | 5347 | |
87b483a1 | 5348 | /* Loop through the insns in the block. */ |
36a05131 BS |
5349 | for (;;) |
5350 | { | |
5351 | /* Mark any new registers that are created as being unavailable for | |
5352 | allocation. Also see if the CC register used in nested IFs can be | |
5353 | reallocated. */ | |
5354 | if (INSN_P (insn)) | |
5355 | { | |
5356 | rtx pattern; | |
5357 | rtx set; | |
5358 | int skip_nested_if = FALSE; | |
5359 | ||
5360 | for_each_rtx (&PATTERN (insn), frv_clear_registers_used, | |
5361 | (void *)&tmp_reg->regs); | |
5362 | ||
5363 | pattern = PATTERN (insn); | |
5364 | if (GET_CODE (pattern) == COND_EXEC) | |
5365 | { | |
5366 | rtx reg = XEXP (COND_EXEC_TEST (pattern), 0); | |
5367 | ||
5368 | if (reg != sub_cond_exec_reg) | |
5369 | { | |
5370 | sub_cond_exec_reg = reg; | |
5371 | frv_ifcvt.num_nested_cond_exec++; | |
5372 | } | |
5373 | } | |
5374 | ||
5375 | set = single_set_pattern (pattern); | |
5376 | if (set) | |
5377 | { | |
5378 | rtx dest = SET_DEST (set); | |
5379 | rtx src = SET_SRC (set); | |
5380 | ||
5381 | if (GET_CODE (dest) == REG) | |
5382 | { | |
5383 | int regno = REGNO (dest); | |
5384 | enum rtx_code src_code = GET_CODE (src); | |
5385 | ||
5386 | if (CC_P (regno) && src_code == COMPARE) | |
5387 | skip_nested_if = TRUE; | |
5388 | ||
5389 | else if (CR_P (regno) | |
5390 | && (src_code == IF_THEN_ELSE | |
ec8e098d | 5391 | || COMPARISON_P (src))) |
36a05131 BS |
5392 | skip_nested_if = TRUE; |
5393 | } | |
5394 | } | |
5395 | ||
5396 | if (! skip_nested_if) | |
5397 | for_each_rtx (&PATTERN (insn), frv_clear_registers_used, | |
5398 | (void *)&frv_ifcvt.nested_cc_ok_rewrite); | |
5399 | } | |
5400 | ||
5401 | if (insn == last_insn) | |
5402 | break; | |
5403 | ||
5404 | insn = NEXT_INSN (insn); | |
5405 | } | |
5406 | } | |
5407 | ||
5408 | /* If this is a nested if, rewrite the CC registers that are available to | |
5409 | include the ones that can be rewritten, to increase the chance of being | |
5410 | able to allocate a paired CC/CR register combination. */ | |
5411 | if (ce_info->pass > 1) | |
5412 | { | |
5413 | for (j = CC_FIRST; j <= CC_LAST; j++) | |
5414 | if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j)) | |
5415 | SET_HARD_REG_BIT (tmp_reg->regs, j); | |
5416 | else | |
5417 | CLEAR_HARD_REG_BIT (tmp_reg->regs, j); | |
5418 | } | |
5419 | ||
c263766c | 5420 | if (dump_file) |
36a05131 BS |
5421 | { |
5422 | int num_gprs = 0; | |
c263766c | 5423 | fprintf (dump_file, "Available GPRs: "); |
36a05131 BS |
5424 | |
5425 | for (j = GPR_FIRST; j <= GPR_LAST; j++) | |
5426 | if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) | |
5427 | { | |
c263766c | 5428 | fprintf (dump_file, " %d [%s]", j, reg_names[j]); |
36a05131 BS |
5429 | if (++num_gprs > GPR_TEMP_NUM+2) |
5430 | break; | |
5431 | } | |
5432 | ||
c263766c | 5433 | fprintf (dump_file, "%s\nAvailable CRs: ", |
36a05131 BS |
5434 | (num_gprs > GPR_TEMP_NUM+2) ? " ..." : ""); |
5435 | ||
5436 | for (j = CR_FIRST; j <= CR_LAST; j++) | |
5437 | if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) | |
c263766c | 5438 | fprintf (dump_file, " %d [%s]", j, reg_names[j]); |
36a05131 | 5439 | |
c263766c | 5440 | fputs ("\n", dump_file); |
36a05131 BS |
5441 | |
5442 | if (ce_info->pass > 1) | |
5443 | { | |
c263766c | 5444 | fprintf (dump_file, "Modifiable CCs: "); |
36a05131 BS |
5445 | for (j = CC_FIRST; j <= CC_LAST; j++) |
5446 | if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) | |
c263766c | 5447 | fprintf (dump_file, " %d [%s]", j, reg_names[j]); |
36a05131 | 5448 | |
c263766c | 5449 | fprintf (dump_file, "\n%d nested COND_EXEC statements\n", |
36a05131 BS |
5450 | frv_ifcvt.num_nested_cond_exec); |
5451 | } | |
5452 | } | |
5453 | ||
5454 | /* Allocate the appropriate temporary condition code register. Try to | |
5455 | allocate the ICR/FCR register that corresponds to the ICC/FCC register so | |
5456 | that conditional cmp's can be done. */ | |
036ff63f | 5457 | if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode) |
36a05131 BS |
5458 | { |
5459 | cr_class = ICR_REGS; | |
5460 | cc_class = ICC_REGS; | |
5461 | cc_first = ICC_FIRST; | |
5462 | cc_last = ICC_LAST; | |
5463 | } | |
5464 | else if (mode == CC_FPmode) | |
5465 | { | |
5466 | cr_class = FCR_REGS; | |
5467 | cc_class = FCC_REGS; | |
5468 | cc_first = FCC_FIRST; | |
5469 | cc_last = FCC_LAST; | |
5470 | } | |
5471 | else | |
5472 | { | |
5473 | cc_first = cc_last = 0; | |
5474 | cr_class = cc_class = NO_REGS; | |
5475 | } | |
5476 | ||
5477 | cc = XEXP (true_expr, 0); | |
5478 | nested_cc = cr = NULL_RTX; | |
5479 | if (cc_class != NO_REGS) | |
5480 | { | |
5481 | /* For nested IFs and &&/||, see if we can find a CC and CR register pair | |
5482 | so we can execute a csubcc/caddcc/cfcmps instruction. */ | |
5483 | int cc_regno; | |
5484 | ||
5485 | for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++) | |
5486 | { | |
5487 | int cr_regno = cc_regno - CC_FIRST + CR_FIRST; | |
5488 | ||
5489 | if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno) | |
5490 | && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno)) | |
5491 | { | |
5492 | frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno; | |
5493 | cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE, | |
5494 | TRUE); | |
5495 | ||
5496 | frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno; | |
5497 | nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode, | |
5498 | TRUE, TRUE); | |
5499 | break; | |
5500 | } | |
5501 | } | |
5502 | } | |
5503 | ||
5504 | if (! cr) | |
5505 | { | |
c263766c RH |
5506 | if (dump_file) |
5507 | fprintf (dump_file, "Could not allocate a CR temporary register\n"); | |
36a05131 BS |
5508 | |
5509 | goto fail; | |
5510 | } | |
5511 | ||
c263766c RH |
5512 | if (dump_file) |
5513 | fprintf (dump_file, | |
36a05131 BS |
5514 | "Will use %s for conditional execution, %s for nested comparisons\n", |
5515 | reg_names[ REGNO (cr)], | |
5516 | (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>"); | |
5517 | ||
5518 | /* Set the CCR bit. Note for integer tests, we reverse the condition so that | |
5519 | in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR | |
5520 | bit being true. We don't do this for floating point, because of NaNs. */ | |
5521 | code = GET_CODE (true_expr); | |
5522 | if (GET_MODE (cc) != CC_FPmode) | |
5523 | { | |
5524 | code = reverse_condition (code); | |
5525 | code_true = EQ; | |
5526 | code_false = NE; | |
5527 | } | |
5528 | else | |
5529 | { | |
5530 | code_true = NE; | |
5531 | code_false = EQ; | |
5532 | } | |
5533 | ||
5534 | check_insn = gen_rtx_SET (VOIDmode, cr, | |
5535 | gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx)); | |
5536 | ||
5537 | /* Record the check insn to be inserted later. */ | |
a813c111 | 5538 | frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE); |
36a05131 BS |
5539 | |
5540 | /* Update the tests. */ | |
5541 | frv_ifcvt.cr_reg = cr; | |
5542 | frv_ifcvt.nested_cc_reg = nested_cc; | |
5543 | *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx); | |
5544 | *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx); | |
5545 | return; | |
5546 | ||
5547 | /* Fail, don't do this conditional execution. */ | |
5548 | fail: | |
5549 | *p_true = NULL_RTX; | |
5550 | *p_false = NULL_RTX; | |
c263766c RH |
5551 | if (dump_file) |
5552 | fprintf (dump_file, "Disabling this conditional execution.\n"); | |
36a05131 BS |
5553 | |
5554 | return; | |
5555 | } | |
5556 | ||
5557 | \f | |
5558 | /* A C expression to modify the code described by the conditional if | |
5559 | information CE_INFO, for the basic block BB, possibly updating the tests in | |
5560 | TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or | |
5561 | if-then-else code to conditional instructions. Set either TRUE_EXPR or | |
5562 | FALSE_EXPR to a null pointer if the tests cannot be converted. */ | |
5563 | ||
5564 | /* p_true and p_false are given expressions of the form: | |
5565 | ||
5566 | (and (eq:CC_CCR (reg:CC_CCR) | |
5567 | (const_int 0)) | |
5568 | (eq:CC (reg:CC) | |
5569 | (const_int 0))) */ | |
5570 | ||
5571 | void | |
f2206911 KC |
5572 | frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info, |
5573 | basic_block bb, | |
5574 | rtx *p_true, | |
5575 | rtx *p_false) | |
36a05131 BS |
5576 | { |
5577 | rtx old_true = XEXP (*p_true, 0); | |
5578 | rtx old_false = XEXP (*p_false, 0); | |
5579 | rtx true_expr = XEXP (*p_true, 1); | |
5580 | rtx false_expr = XEXP (*p_false, 1); | |
5581 | rtx test_expr; | |
5582 | rtx old_test; | |
5583 | rtx cr = XEXP (old_true, 0); | |
5584 | rtx check_insn; | |
5585 | rtx new_cr = NULL_RTX; | |
5586 | rtx *p_new_cr = (rtx *)0; | |
5587 | rtx if_else; | |
5588 | rtx compare; | |
5589 | rtx cc; | |
5590 | enum reg_class cr_class; | |
5591 | enum machine_mode mode = GET_MODE (true_expr); | |
5592 | rtx (*logical_func)(rtx, rtx, rtx); | |
5593 | ||
5594 | if (TARGET_DEBUG_COND_EXEC) | |
5595 | { | |
5596 | fprintf (stderr, | |
5597 | "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n", | |
5598 | ce_info->and_and_p ? "&&" : "||"); | |
5599 | ||
5600 | debug_rtx (*p_true); | |
5601 | ||
5602 | fputs ("\nfalse insn:\n", stderr); | |
5603 | debug_rtx (*p_false); | |
5604 | } | |
5605 | ||
0b2c18fe | 5606 | if (!TARGET_MULTI_CE) |
36a05131 BS |
5607 | goto fail; |
5608 | ||
5609 | if (GET_CODE (cr) != REG) | |
5610 | goto fail; | |
b16c1435 | 5611 | |
036ff63f | 5612 | if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode) |
36a05131 BS |
5613 | { |
5614 | cr_class = ICR_REGS; | |
5615 | p_new_cr = &frv_ifcvt.extra_int_cr; | |
5616 | } | |
5617 | else if (mode == CC_FPmode) | |
5618 | { | |
5619 | cr_class = FCR_REGS; | |
5620 | p_new_cr = &frv_ifcvt.extra_fp_cr; | |
5621 | } | |
5622 | else | |
5623 | goto fail; | |
5624 | ||
5625 | /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or | |
5626 | more &&/|| tests. */ | |
5627 | new_cr = *p_new_cr; | |
5628 | if (! new_cr) | |
5629 | { | |
5630 | new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class, | |
5631 | CC_CCRmode, TRUE, TRUE); | |
5632 | if (! new_cr) | |
5633 | goto fail; | |
5634 | } | |
5635 | ||
5636 | if (ce_info->and_and_p) | |
5637 | { | |
5638 | old_test = old_false; | |
5639 | test_expr = true_expr; | |
5640 | logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr; | |
5641 | *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx); | |
5642 | *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx); | |
5643 | } | |
5644 | else | |
5645 | { | |
5646 | old_test = old_false; | |
5647 | test_expr = false_expr; | |
5648 | logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr; | |
5649 | *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx); | |
5650 | *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx); | |
5651 | } | |
5652 | ||
5653 | /* First add the andcr/andncr/orcr/orncr, which will be added after the | |
5654 | conditional check instruction, due to frv_ifcvt_add_insn being a LIFO | |
5655 | stack. */ | |
a813c111 | 5656 | frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE); |
36a05131 BS |
5657 | |
5658 | /* Now add the conditional check insn. */ | |
5659 | cc = XEXP (test_expr, 0); | |
5660 | compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx); | |
5661 | if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx); | |
5662 | ||
5663 | check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else); | |
5664 | ||
87b483a1 | 5665 | /* Add the new check insn to the list of check insns that need to be |
36a05131 | 5666 | inserted. */ |
a813c111 | 5667 | frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE); |
36a05131 BS |
5668 | |
5669 | if (TARGET_DEBUG_COND_EXEC) | |
5670 | { | |
5671 | fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n", | |
5672 | stderr); | |
5673 | ||
5674 | debug_rtx (*p_true); | |
5675 | ||
5676 | fputs ("\nfalse insn:\n", stderr); | |
5677 | debug_rtx (*p_false); | |
5678 | } | |
5679 | ||
5680 | return; | |
5681 | ||
5682 | fail: | |
5683 | *p_true = *p_false = NULL_RTX; | |
5684 | ||
87b483a1 | 5685 | /* If we allocated a CR register, release it. */ |
36a05131 BS |
5686 | if (new_cr) |
5687 | { | |
5688 | CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr)); | |
5689 | *p_new_cr = NULL_RTX; | |
5690 | } | |
5691 | ||
5692 | if (TARGET_DEBUG_COND_EXEC) | |
5693 | fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr); | |
5694 | ||
5695 | return; | |
5696 | } | |
5697 | ||
5698 | \f | |
5699 | /* Return a register which will be loaded with a value if an IF block is | |
5700 | converted to conditional execution. This is used to rewrite instructions | |
5701 | that use constants to ones that just use registers. */ | |
5702 | ||
5703 | static rtx | |
f2206911 | 5704 | frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED) |
36a05131 BS |
5705 | { |
5706 | int num_alloc = frv_ifcvt.cur_scratch_regs; | |
5707 | int i; | |
5708 | rtx reg; | |
5709 | ||
5710 | /* We know gr0 == 0, so replace any errant uses. */ | |
5711 | if (value == const0_rtx) | |
5712 | return gen_rtx_REG (SImode, GPR_FIRST); | |
5713 | ||
5714 | /* First search all registers currently loaded to see if we have an | |
5715 | applicable constant. */ | |
5716 | if (CONSTANT_P (value) | |
5717 | || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)) | |
5718 | { | |
5719 | for (i = 0; i < num_alloc; i++) | |
5720 | { | |
5721 | if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value)) | |
5722 | return SET_DEST (frv_ifcvt.scratch_regs[i]); | |
5723 | } | |
5724 | } | |
5725 | ||
87b483a1 | 5726 | /* Have we exhausted the number of registers available? */ |
36a05131 BS |
5727 | if (num_alloc >= GPR_TEMP_NUM) |
5728 | { | |
c263766c RH |
5729 | if (dump_file) |
5730 | fprintf (dump_file, "Too many temporary registers allocated\n"); | |
36a05131 BS |
5731 | |
5732 | return NULL_RTX; | |
5733 | } | |
5734 | ||
5735 | /* Allocate the new register. */ | |
5736 | reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE); | |
5737 | if (! reg) | |
5738 | { | |
c263766c RH |
5739 | if (dump_file) |
5740 | fputs ("Could not find a scratch register\n", dump_file); | |
36a05131 BS |
5741 | |
5742 | return NULL_RTX; | |
5743 | } | |
5744 | ||
5745 | frv_ifcvt.cur_scratch_regs++; | |
5746 | frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value); | |
5747 | ||
c263766c | 5748 | if (dump_file) |
36a05131 BS |
5749 | { |
5750 | if (GET_CODE (value) == CONST_INT) | |
c263766c | 5751 | fprintf (dump_file, "Register %s will hold %ld\n", |
36a05131 BS |
5752 | reg_names[ REGNO (reg)], (long)INTVAL (value)); |
5753 | ||
5754 | else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO) | |
c263766c | 5755 | fprintf (dump_file, "Register %s will hold LR\n", |
36a05131 BS |
5756 | reg_names[ REGNO (reg)]); |
5757 | ||
5758 | else | |
c263766c | 5759 | fprintf (dump_file, "Register %s will hold a saved value\n", |
36a05131 BS |
5760 | reg_names[ REGNO (reg)]); |
5761 | } | |
5762 | ||
5763 | return reg; | |
5764 | } | |
5765 | ||
5766 | \f | |
5767 | /* Update a MEM used in conditional code that might contain an offset to put | |
5768 | the offset into a scratch register, so that the conditional load/store | |
5769 | operations can be used. This function returns the original pointer if the | |
5770 | MEM is valid to use in conditional code, NULL if we can't load up the offset | |
5771 | into a temporary register, or the new MEM if we were successful. */ | |
5772 | ||
5773 | static rtx | |
f2206911 | 5774 | frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn) |
36a05131 BS |
5775 | { |
5776 | rtx addr = XEXP (mem, 0); | |
5777 | ||
34208acf | 5778 | if (!frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE)) |
36a05131 BS |
5779 | { |
5780 | if (GET_CODE (addr) == PLUS) | |
5781 | { | |
5782 | rtx addr_op0 = XEXP (addr, 0); | |
5783 | rtx addr_op1 = XEXP (addr, 1); | |
5784 | ||
34208acf | 5785 | if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1)) |
36a05131 BS |
5786 | { |
5787 | rtx reg = frv_ifcvt_load_value (addr_op1, insn); | |
5788 | if (!reg) | |
5789 | return NULL_RTX; | |
5790 | ||
5791 | addr = gen_rtx_PLUS (Pmode, addr_op0, reg); | |
5792 | } | |
5793 | ||
5794 | else | |
5795 | return NULL_RTX; | |
5796 | } | |
5797 | ||
5798 | else if (CONSTANT_P (addr)) | |
5799 | addr = frv_ifcvt_load_value (addr, insn); | |
5800 | ||
5801 | else | |
5802 | return NULL_RTX; | |
5803 | ||
5804 | if (addr == NULL_RTX) | |
5805 | return NULL_RTX; | |
5806 | ||
5807 | else if (XEXP (mem, 0) != addr) | |
5808 | return change_address (mem, mode, addr); | |
5809 | } | |
5810 | ||
5811 | return mem; | |
5812 | } | |
5813 | ||
5814 | \f | |
5815 | /* Given a PATTERN, return a SET expression if this PATTERN has only a single | |
5816 | SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */ | |
5817 | ||
5818 | static rtx | |
f2206911 | 5819 | single_set_pattern (rtx pattern) |
36a05131 BS |
5820 | { |
5821 | rtx set; | |
5822 | int i; | |
5823 | ||
5824 | if (GET_CODE (pattern) == COND_EXEC) | |
5825 | pattern = COND_EXEC_CODE (pattern); | |
5826 | ||
5827 | if (GET_CODE (pattern) == SET) | |
5828 | return pattern; | |
5829 | ||
5830 | else if (GET_CODE (pattern) == PARALLEL) | |
5831 | { | |
5832 | for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++) | |
5833 | { | |
5834 | rtx sub = XVECEXP (pattern, 0, i); | |
5835 | ||
5836 | switch (GET_CODE (sub)) | |
5837 | { | |
5838 | case USE: | |
5839 | case CLOBBER: | |
5840 | break; | |
5841 | ||
5842 | case SET: | |
5843 | if (set) | |
5844 | return 0; | |
5845 | else | |
5846 | set = sub; | |
5847 | break; | |
5848 | ||
5849 | default: | |
5850 | return 0; | |
5851 | } | |
5852 | } | |
5853 | return set; | |
5854 | } | |
5855 | ||
5856 | return 0; | |
5857 | } | |
5858 | ||
5859 | \f | |
5860 | /* A C expression to modify the code described by the conditional if | |
5861 | information CE_INFO with the new PATTERN in INSN. If PATTERN is a null | |
5862 | pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that | |
5863 | insn cannot be converted to be executed conditionally. */ | |
5864 | ||
5865 | rtx | |
5da1fd3d | 5866 | frv_ifcvt_modify_insn (ce_if_block_t *ce_info, |
f2206911 KC |
5867 | rtx pattern, |
5868 | rtx insn) | |
36a05131 BS |
5869 | { |
5870 | rtx orig_ce_pattern = pattern; | |
5871 | rtx set; | |
5872 | rtx op0; | |
5873 | rtx op1; | |
5874 | rtx test; | |
5875 | ||
44e91694 | 5876 | gcc_assert (GET_CODE (pattern) == COND_EXEC); |
36a05131 BS |
5877 | |
5878 | test = COND_EXEC_TEST (pattern); | |
5879 | if (GET_CODE (test) == AND) | |
5880 | { | |
5881 | rtx cr = frv_ifcvt.cr_reg; | |
5882 | rtx test_reg; | |
5883 | ||
5884 | op0 = XEXP (test, 0); | |
5885 | if (! rtx_equal_p (cr, XEXP (op0, 0))) | |
5886 | goto fail; | |
5887 | ||
5888 | op1 = XEXP (test, 1); | |
5889 | test_reg = XEXP (op1, 0); | |
5890 | if (GET_CODE (test_reg) != REG) | |
5891 | goto fail; | |
5892 | ||
5893 | /* Is this the first nested if block in this sequence? If so, generate | |
5894 | an andcr or andncr. */ | |
5895 | if (! frv_ifcvt.last_nested_if_cr) | |
5896 | { | |
5897 | rtx and_op; | |
5898 | ||
5899 | frv_ifcvt.last_nested_if_cr = test_reg; | |
5900 | if (GET_CODE (op0) == NE) | |
5901 | and_op = gen_andcr (test_reg, cr, test_reg); | |
5902 | else | |
5903 | and_op = gen_andncr (test_reg, cr, test_reg); | |
5904 | ||
5905 | frv_ifcvt_add_insn (and_op, insn, TRUE); | |
5906 | } | |
5907 | ||
5908 | /* If this isn't the first statement in the nested if sequence, see if we | |
5909 | are dealing with the same register. */ | |
5910 | else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr)) | |
5911 | goto fail; | |
5912 | ||
5913 | COND_EXEC_TEST (pattern) = test = op1; | |
5914 | } | |
5915 | ||
5916 | /* If this isn't a nested if, reset state variables. */ | |
5917 | else | |
5918 | { | |
5919 | frv_ifcvt.last_nested_if_cr = NULL_RTX; | |
5920 | } | |
5921 | ||
5922 | set = single_set_pattern (pattern); | |
5923 | if (set) | |
5924 | { | |
5925 | rtx dest = SET_DEST (set); | |
5926 | rtx src = SET_SRC (set); | |
5927 | enum machine_mode mode = GET_MODE (dest); | |
5928 | ||
87b483a1 | 5929 | /* Check for normal binary operators. */ |
ec8e098d | 5930 | if (mode == SImode && ARITHMETIC_P (src)) |
36a05131 BS |
5931 | { |
5932 | op0 = XEXP (src, 0); | |
5933 | op1 = XEXP (src, 1); | |
5934 | ||
34208acf | 5935 | if (integer_register_operand (op0, SImode) && CONSTANT_P (op1)) |
36a05131 BS |
5936 | { |
5937 | op1 = frv_ifcvt_load_value (op1, insn); | |
5938 | if (op1) | |
5939 | COND_EXEC_CODE (pattern) | |
5940 | = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src), | |
5941 | GET_MODE (src), | |
5942 | op0, op1)); | |
5943 | else | |
5944 | goto fail; | |
5945 | } | |
5946 | } | |
5947 | ||
5948 | /* For multiply by a constant, we need to handle the sign extending | |
5949 | correctly. Add a USE of the value after the multiply to prevent flow | |
5950 | from cratering because only one register out of the two were used. */ | |
5951 | else if (mode == DImode && GET_CODE (src) == MULT) | |
5952 | { | |
5953 | op0 = XEXP (src, 0); | |
5954 | op1 = XEXP (src, 1); | |
5955 | if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT) | |
5956 | { | |
5957 | op1 = frv_ifcvt_load_value (op1, insn); | |
5958 | if (op1) | |
5959 | { | |
5960 | op1 = gen_rtx_SIGN_EXTEND (DImode, op1); | |
5961 | COND_EXEC_CODE (pattern) | |
5962 | = gen_rtx_SET (VOIDmode, dest, | |
5963 | gen_rtx_MULT (DImode, op0, op1)); | |
5964 | } | |
5965 | else | |
5966 | goto fail; | |
5967 | } | |
5968 | ||
5969 | frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode, dest), insn, FALSE); | |
5970 | } | |
5971 | ||
5972 | /* If we are just loading a constant created for a nested conditional | |
5973 | execution statement, just load the constant without any conditional | |
5974 | execution, since we know that the constant will not interfere with any | |
5975 | other registers. */ | |
5976 | else if (frv_ifcvt.scratch_insns_bitmap | |
5977 | && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap, | |
5da1fd3d | 5978 | INSN_UID (insn)) |
5da1fd3d | 5979 | && REG_P (SET_DEST (set)) |
9a228f09 AO |
5980 | /* We must not unconditionally set a scratch reg chosen |
5981 | for a nested if-converted block if its incoming | |
5982 | value from the TEST block (or the result of the THEN | |
5983 | branch) could/should propagate to the JOIN block. | |
5984 | It suffices to test whether the register is live at | |
5985 | the JOIN point: if it's live there, we can infer | |
5986 | that we set it in the former JOIN block of the | |
5987 | nested if-converted block (otherwise it wouldn't | |
5988 | have been available as a scratch register), and it | |
5989 | is either propagated through or set in the other | |
5990 | conditional block. It's probably not worth trying | |
5991 | to catch the latter case, and it could actually | |
5992 | limit scheduling of the combined block quite | |
5993 | severely. */ | |
5994 | && ce_info->join_bb | |
5995 | && ! (REGNO_REG_SET_P | |
5e2d947c | 5996 | (ce_info->join_bb->il.rtl->global_live_at_start, |
9a228f09 AO |
5997 | REGNO (SET_DEST (set)))) |
5998 | /* Similarly, we must not unconditionally set a reg | |
5999 | used as scratch in the THEN branch if the same reg | |
6000 | is live in the ELSE branch. */ | |
5da1fd3d AO |
6001 | && (! ce_info->else_bb |
6002 | || BLOCK_FOR_INSN (insn) == ce_info->else_bb | |
6003 | || ! (REGNO_REG_SET_P | |
5e2d947c | 6004 | (ce_info->else_bb->il.rtl->global_live_at_start, |
5da1fd3d | 6005 | REGNO (SET_DEST (set)))))) |
36a05131 BS |
6006 | pattern = set; |
6007 | ||
6008 | else if (mode == QImode || mode == HImode || mode == SImode | |
6009 | || mode == SFmode) | |
6010 | { | |
6011 | int changed_p = FALSE; | |
6012 | ||
6013 | /* Check for just loading up a constant */ | |
6014 | if (CONSTANT_P (src) && integer_register_operand (dest, mode)) | |
6015 | { | |
6016 | src = frv_ifcvt_load_value (src, insn); | |
6017 | if (!src) | |
6018 | goto fail; | |
6019 | ||
6020 | changed_p = TRUE; | |
6021 | } | |
6022 | ||
6023 | /* See if we need to fix up stores */ | |
6024 | if (GET_CODE (dest) == MEM) | |
6025 | { | |
6026 | rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn); | |
6027 | ||
6028 | if (!new_mem) | |
6029 | goto fail; | |
6030 | ||
6031 | else if (new_mem != dest) | |
6032 | { | |
6033 | changed_p = TRUE; | |
6034 | dest = new_mem; | |
6035 | } | |
6036 | } | |
6037 | ||
6038 | /* See if we need to fix up loads */ | |
6039 | if (GET_CODE (src) == MEM) | |
6040 | { | |
6041 | rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn); | |
6042 | ||
6043 | if (!new_mem) | |
6044 | goto fail; | |
6045 | ||
6046 | else if (new_mem != src) | |
6047 | { | |
6048 | changed_p = TRUE; | |
6049 | src = new_mem; | |
6050 | } | |
6051 | } | |
6052 | ||
6053 | /* If either src or destination changed, redo SET. */ | |
6054 | if (changed_p) | |
6055 | COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src); | |
6056 | } | |
6057 | ||
6058 | /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with | |
6059 | rewriting the CC register to be the same as the paired CC/CR register | |
6060 | for nested ifs. */ | |
ec8e098d | 6061 | else if (mode == CC_CCRmode && COMPARISON_P (src)) |
36a05131 BS |
6062 | { |
6063 | int regno = REGNO (XEXP (src, 0)); | |
6064 | rtx if_else; | |
6065 | ||
6066 | if (ce_info->pass > 1 | |
6067 | && regno != (int)REGNO (frv_ifcvt.nested_cc_reg) | |
6068 | && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno)) | |
6069 | { | |
6070 | src = gen_rtx_fmt_ee (GET_CODE (src), | |
6071 | CC_CCRmode, | |
6072 | frv_ifcvt.nested_cc_reg, | |
6073 | XEXP (src, 1)); | |
6074 | } | |
6075 | ||
6076 | if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx); | |
6077 | pattern = gen_rtx_SET (VOIDmode, dest, if_else); | |
6078 | } | |
6079 | ||
6080 | /* Remap a nested compare instruction to use the paired CC/CR reg. */ | |
6081 | else if (ce_info->pass > 1 | |
6082 | && GET_CODE (dest) == REG | |
6083 | && CC_P (REGNO (dest)) | |
6084 | && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg) | |
6085 | && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, | |
6086 | REGNO (dest)) | |
6087 | && GET_CODE (src) == COMPARE) | |
6088 | { | |
6089 | PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest)); | |
6090 | COND_EXEC_CODE (pattern) | |
6091 | = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src)); | |
6092 | } | |
6093 | } | |
6094 | ||
6095 | if (TARGET_DEBUG_COND_EXEC) | |
6096 | { | |
6097 | rtx orig_pattern = PATTERN (insn); | |
6098 | ||
6099 | PATTERN (insn) = pattern; | |
6100 | fprintf (stderr, | |
6101 | "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n", | |
6102 | ce_info->pass); | |
6103 | ||
6104 | debug_rtx (insn); | |
6105 | PATTERN (insn) = orig_pattern; | |
6106 | } | |
6107 | ||
6108 | return pattern; | |
6109 | ||
6110 | fail: | |
6111 | if (TARGET_DEBUG_COND_EXEC) | |
6112 | { | |
6113 | rtx orig_pattern = PATTERN (insn); | |
6114 | ||
6115 | PATTERN (insn) = orig_ce_pattern; | |
6116 | fprintf (stderr, | |
6117 | "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n", | |
6118 | ce_info->pass); | |
6119 | ||
6120 | debug_rtx (insn); | |
6121 | PATTERN (insn) = orig_pattern; | |
6122 | } | |
6123 | ||
6124 | return NULL_RTX; | |
6125 | } | |
6126 | ||
6127 | \f | |
6128 | /* A C expression to perform any final machine dependent modifications in | |
6129 | converting code to conditional execution in the code described by the | |
6130 | conditional if information CE_INFO. */ | |
6131 | ||
6132 | void | |
f2206911 | 6133 | frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED) |
36a05131 BS |
6134 | { |
6135 | rtx existing_insn; | |
6136 | rtx check_insn; | |
6137 | rtx p = frv_ifcvt.added_insns_list; | |
6138 | int i; | |
6139 | ||
6140 | /* Loop inserting the check insns. The last check insn is the first test, | |
6141 | and is the appropriate place to insert constants. */ | |
44e91694 | 6142 | gcc_assert (p); |
36a05131 BS |
6143 | |
6144 | do | |
6145 | { | |
6146 | rtx check_and_insert_insns = XEXP (p, 0); | |
6147 | rtx old_p = p; | |
6148 | ||
6149 | check_insn = XEXP (check_and_insert_insns, 0); | |
6150 | existing_insn = XEXP (check_and_insert_insns, 1); | |
6151 | p = XEXP (p, 1); | |
6152 | ||
6153 | /* The jump bit is used to say that the new insn is to be inserted BEFORE | |
6154 | the existing insn, otherwise it is to be inserted AFTER. */ | |
6155 | if (check_and_insert_insns->jump) | |
6156 | { | |
6157 | emit_insn_before (check_insn, existing_insn); | |
6158 | check_and_insert_insns->jump = 0; | |
6159 | } | |
6160 | else | |
6161 | emit_insn_after (check_insn, existing_insn); | |
6162 | ||
6163 | free_EXPR_LIST_node (check_and_insert_insns); | |
6164 | free_EXPR_LIST_node (old_p); | |
6165 | } | |
6166 | while (p != NULL_RTX); | |
6167 | ||
6168 | /* Load up any constants needed into temp gprs */ | |
6169 | for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++) | |
6170 | { | |
6171 | rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn); | |
6172 | if (! frv_ifcvt.scratch_insns_bitmap) | |
7b210806 | 6173 | frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL); |
36a05131 BS |
6174 | bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn)); |
6175 | frv_ifcvt.scratch_regs[i] = NULL_RTX; | |
6176 | } | |
6177 | ||
6178 | frv_ifcvt.added_insns_list = NULL_RTX; | |
6179 | frv_ifcvt.cur_scratch_regs = 0; | |
6180 | } | |
6181 | ||
6182 | \f | |
6183 | /* A C expression to cancel any machine dependent modifications in converting | |
6184 | code to conditional execution in the code described by the conditional if | |
6185 | information CE_INFO. */ | |
6186 | ||
6187 | void | |
f2206911 | 6188 | frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED) |
36a05131 BS |
6189 | { |
6190 | int i; | |
6191 | rtx p = frv_ifcvt.added_insns_list; | |
6192 | ||
6193 | /* Loop freeing up the EXPR_LIST's allocated. */ | |
6194 | while (p != NULL_RTX) | |
6195 | { | |
6196 | rtx check_and_jump = XEXP (p, 0); | |
6197 | rtx old_p = p; | |
6198 | ||
6199 | p = XEXP (p, 1); | |
6200 | free_EXPR_LIST_node (check_and_jump); | |
6201 | free_EXPR_LIST_node (old_p); | |
6202 | } | |
6203 | ||
6204 | /* Release any temporary gprs allocated. */ | |
6205 | for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++) | |
6206 | frv_ifcvt.scratch_regs[i] = NULL_RTX; | |
6207 | ||
6208 | frv_ifcvt.added_insns_list = NULL_RTX; | |
6209 | frv_ifcvt.cur_scratch_regs = 0; | |
6210 | return; | |
6211 | } | |
6212 | \f | |
6213 | /* A C expression for the size in bytes of the trampoline, as an integer. | |
6214 | The template is: | |
6215 | ||
6216 | setlo #0, <jmp_reg> | |
6217 | setlo #0, <static_chain> | |
6218 | sethi #0, <jmp_reg> | |
6219 | sethi #0, <static_chain> | |
6220 | jmpl @(gr0,<jmp_reg>) */ | |
6221 | ||
6222 | int | |
f2206911 | 6223 | frv_trampoline_size (void) |
36a05131 | 6224 | { |
34208acf AO |
6225 | if (TARGET_FDPIC) |
6226 | /* Allocate room for the function descriptor and the lddi | |
6227 | instruction. */ | |
6228 | return 8 + 6 * 4; | |
6229 | return 5 /* instructions */ * 4 /* instruction size. */; | |
36a05131 BS |
6230 | } |
6231 | ||
6232 | \f | |
6233 | /* A C statement to initialize the variable parts of a trampoline. ADDR is an | |
6234 | RTX for the address of the trampoline; FNADDR is an RTX for the address of | |
6235 | the nested function; STATIC_CHAIN is an RTX for the static chain value that | |
6236 | should be passed to the function when it is called. | |
6237 | ||
6238 | The template is: | |
6239 | ||
6240 | setlo #0, <jmp_reg> | |
6241 | setlo #0, <static_chain> | |
6242 | sethi #0, <jmp_reg> | |
6243 | sethi #0, <static_chain> | |
6244 | jmpl @(gr0,<jmp_reg>) */ | |
6245 | ||
6246 | void | |
f2206911 | 6247 | frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain) |
36a05131 BS |
6248 | { |
6249 | rtx sc_reg = force_reg (Pmode, static_chain); | |
6250 | ||
6251 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), | |
6252 | FALSE, VOIDmode, 4, | |
6253 | addr, Pmode, | |
6254 | GEN_INT (frv_trampoline_size ()), SImode, | |
6255 | fnaddr, Pmode, | |
6256 | sc_reg, Pmode); | |
6257 | } | |
6258 | ||
6259 | \f | |
6260 | /* Many machines have some registers that cannot be copied directly to or from | |
6261 | memory or even from other types of registers. An example is the `MQ' | |
6262 | register, which on most machines, can only be copied to or from general | |
6263 | registers, but not memory. Some machines allow copying all registers to and | |
6264 | from memory, but require a scratch register for stores to some memory | |
6265 | locations (e.g., those with symbolic address on the RT, and those with | |
981f6289 | 6266 | certain symbolic address on the SPARC when compiling PIC). In some cases, |
36a05131 BS |
6267 | both an intermediate and a scratch register are required. |
6268 | ||
6269 | You should define these macros to indicate to the reload phase that it may | |
6270 | need to allocate at least one register for a reload in addition to the | |
6271 | register to contain the data. Specifically, if copying X to a register | |
6272 | CLASS in MODE requires an intermediate register, you should define | |
6273 | `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of | |
6274 | whose registers can be used as intermediate registers or scratch registers. | |
6275 | ||
6276 | If copying a register CLASS in MODE to X requires an intermediate or scratch | |
6277 | register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the | |
6278 | largest register class required. If the requirements for input and output | |
6279 | reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used | |
6280 | instead of defining both macros identically. | |
6281 | ||
6282 | The values returned by these macros are often `GENERAL_REGS'. Return | |
6283 | `NO_REGS' if no spare register is needed; i.e., if X can be directly copied | |
6284 | to or from a register of CLASS in MODE without requiring a scratch register. | |
6285 | Do not define this macro if it would always return `NO_REGS'. | |
6286 | ||
6287 | If a scratch register is required (either with or without an intermediate | |
6288 | register), you should define patterns for `reload_inM' or `reload_outM', as | |
6289 | required.. These patterns, which will normally be implemented with a | |
6290 | `define_expand', should be similar to the `movM' patterns, except that | |
6291 | operand 2 is the scratch register. | |
6292 | ||
6293 | Define constraints for the reload register and scratch register that contain | |
6294 | a single register class. If the original reload register (whose class is | |
6295 | CLASS) can meet the constraint given in the pattern, the value returned by | |
6296 | these macros is used for the class of the scratch register. Otherwise, two | |
6297 | additional reload registers are required. Their classes are obtained from | |
6298 | the constraints in the insn pattern. | |
6299 | ||
6300 | X might be a pseudo-register or a `subreg' of a pseudo-register, which could | |
6301 | either be in a hard register or in memory. Use `true_regnum' to find out; | |
6302 | it will return -1 if the pseudo is in memory and the hard register number if | |
6303 | it is in a register. | |
6304 | ||
6305 | These macros should not be used in the case where a particular class of | |
6306 | registers can only be copied to memory and not to another class of | |
6307 | registers. In that case, secondary reload registers are not needed and | |
6308 | would not be helpful. Instead, a stack location must be used to perform the | |
43aa4e05 | 6309 | copy and the `movM' pattern should use memory as an intermediate storage. |
36a05131 BS |
6310 | This case often occurs between floating-point and general registers. */ |
6311 | ||
6312 | enum reg_class | |
f2206911 KC |
6313 | frv_secondary_reload_class (enum reg_class class, |
6314 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
6315 | rtx x, | |
6316 | int in_p ATTRIBUTE_UNUSED) | |
36a05131 BS |
6317 | { |
6318 | enum reg_class ret; | |
6319 | ||
6320 | switch (class) | |
6321 | { | |
6322 | default: | |
6323 | ret = NO_REGS; | |
6324 | break; | |
6325 | ||
6326 | /* Accumulators/Accumulator guard registers need to go through floating | |
6327 | point registers. */ | |
6328 | case QUAD_REGS: | |
6329 | case EVEN_REGS: | |
6330 | case GPR_REGS: | |
6331 | ret = NO_REGS; | |
6332 | if (x && GET_CODE (x) == REG) | |
6333 | { | |
6334 | int regno = REGNO (x); | |
6335 | ||
6336 | if (ACC_P (regno) || ACCG_P (regno)) | |
6337 | ret = FPR_REGS; | |
6338 | } | |
6339 | break; | |
6340 | ||
9cd10576 | 6341 | /* Nonzero constants should be loaded into an FPR through a GPR. */ |
36a05131 BS |
6342 | case QUAD_FPR_REGS: |
6343 | case FEVEN_REGS: | |
6344 | case FPR_REGS: | |
6345 | if (x && CONSTANT_P (x) && !ZERO_P (x)) | |
6346 | ret = GPR_REGS; | |
6347 | else | |
6348 | ret = NO_REGS; | |
6349 | break; | |
6350 | ||
6351 | /* All of these types need gpr registers. */ | |
6352 | case ICC_REGS: | |
6353 | case FCC_REGS: | |
6354 | case CC_REGS: | |
6355 | case ICR_REGS: | |
6356 | case FCR_REGS: | |
6357 | case CR_REGS: | |
6358 | case LCR_REG: | |
6359 | case LR_REG: | |
6360 | ret = GPR_REGS; | |
6361 | break; | |
6362 | ||
6363 | /* The accumulators need fpr registers */ | |
6364 | case ACC_REGS: | |
6365 | case EVEN_ACC_REGS: | |
6366 | case QUAD_ACC_REGS: | |
6367 | case ACCG_REGS: | |
6368 | ret = FPR_REGS; | |
6369 | break; | |
6370 | } | |
6371 | ||
6372 | return ret; | |
6373 | } | |
6374 | ||
6375 | \f | |
6376 | /* A C expression whose value is nonzero if pseudos that have been assigned to | |
6377 | registers of class CLASS would likely be spilled because registers of CLASS | |
6378 | are needed for spill registers. | |
6379 | ||
6380 | The default value of this macro returns 1 if CLASS has exactly one register | |
6381 | and zero otherwise. On most machines, this default should be used. Only | |
6382 | define this macro to some other expression if pseudo allocated by | |
6383 | `local-alloc.c' end up in memory because their hard registers were needed | |
6384 | for spill registers. If this macro returns nonzero for those classes, those | |
6385 | pseudos will only be allocated by `global.c', which knows how to reallocate | |
6386 | the pseudo to another register. If there would not be another register | |
6387 | available for reallocation, you should not change the definition of this | |
6388 | macro since the only effect of such a definition would be to slow down | |
6389 | register allocation. */ | |
6390 | ||
6391 | int | |
f2206911 | 6392 | frv_class_likely_spilled_p (enum reg_class class) |
36a05131 BS |
6393 | { |
6394 | switch (class) | |
6395 | { | |
6396 | default: | |
6397 | break; | |
6398 | ||
17c21957 AO |
6399 | case GR8_REGS: |
6400 | case GR9_REGS: | |
6401 | case GR89_REGS: | |
6402 | case FDPIC_FPTR_REGS: | |
6403 | case FDPIC_REGS: | |
36a05131 BS |
6404 | case ICC_REGS: |
6405 | case FCC_REGS: | |
6406 | case CC_REGS: | |
6407 | case ICR_REGS: | |
6408 | case FCR_REGS: | |
6409 | case CR_REGS: | |
6410 | case LCR_REG: | |
6411 | case LR_REG: | |
6412 | case SPR_REGS: | |
6413 | case QUAD_ACC_REGS: | |
6414 | case EVEN_ACC_REGS: | |
6415 | case ACC_REGS: | |
6416 | case ACCG_REGS: | |
6417 | return TRUE; | |
6418 | } | |
6419 | ||
6420 | return FALSE; | |
6421 | } | |
6422 | ||
6423 | \f | |
6424 | /* An expression for the alignment of a structure field FIELD if the | |
7ec022b2 | 6425 | alignment computed in the usual way is COMPUTED. GCC uses this |
36a05131 BS |
6426 | value instead of the value in `BIGGEST_ALIGNMENT' or |
6427 | `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */ | |
6428 | ||
6429 | /* The definition type of the bit field data is either char, short, long or | |
6430 | long long. The maximum bit size is the number of bits of its own type. | |
6431 | ||
6432 | The bit field data is assigned to a storage unit that has an adequate size | |
6433 | for bit field data retention and is located at the smallest address. | |
6434 | ||
6435 | Consecutive bit field data are packed at consecutive bits having the same | |
6436 | storage unit, with regard to the type, beginning with the MSB and continuing | |
6437 | toward the LSB. | |
6438 | ||
6439 | If a field to be assigned lies over a bit field type boundary, its | |
6440 | assignment is completed by aligning it with a boundary suitable for the | |
6441 | type. | |
6442 | ||
6443 | When a bit field having a bit length of 0 is declared, it is forcibly | |
6444 | assigned to the next storage unit. | |
6445 | ||
6446 | e.g) | |
6447 | struct { | |
6448 | int a:2; | |
6449 | int b:6; | |
6450 | char c:4; | |
6451 | int d:10; | |
6452 | int :0; | |
6453 | int f:2; | |
6454 | } x; | |
6455 | ||
6456 | +0 +1 +2 +3 | |
6457 | &x 00000000 00000000 00000000 00000000 | |
6458 | MLM----L | |
6459 | a b | |
6460 | &x+4 00000000 00000000 00000000 00000000 | |
6461 | M--L | |
6462 | c | |
6463 | &x+8 00000000 00000000 00000000 00000000 | |
6464 | M----------L | |
6465 | d | |
6466 | &x+12 00000000 00000000 00000000 00000000 | |
6467 | ML | |
6468 | f | |
6469 | */ | |
6470 | ||
6471 | int | |
f2206911 | 6472 | frv_adjust_field_align (tree field, int computed) |
36a05131 | 6473 | { |
b16c1435 EC |
6474 | /* Make sure that the bitfield is not wider than the type. */ |
6475 | if (DECL_BIT_FIELD (field) | |
25f93e18 | 6476 | && !DECL_ARTIFICIAL (field)) |
36a05131 BS |
6477 | { |
6478 | tree parent = DECL_CONTEXT (field); | |
6479 | tree prev = NULL_TREE; | |
6480 | tree cur; | |
6481 | ||
36a05131 BS |
6482 | for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur)) |
6483 | { | |
6484 | if (TREE_CODE (cur) != FIELD_DECL) | |
6485 | continue; | |
6486 | ||
6487 | prev = cur; | |
6488 | } | |
6489 | ||
44e91694 | 6490 | gcc_assert (cur); |
36a05131 BS |
6491 | |
6492 | /* If this isn't a :0 field and if the previous element is a bitfield | |
6493 | also, see if the type is different, if so, we will need to align the | |
87b483a1 | 6494 | bit-field to the next boundary. */ |
36a05131 BS |
6495 | if (prev |
6496 | && ! DECL_PACKED (field) | |
6497 | && ! integer_zerop (DECL_SIZE (field)) | |
6498 | && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev)) | |
6499 | { | |
6500 | int prev_align = TYPE_ALIGN (TREE_TYPE (prev)); | |
6501 | int cur_align = TYPE_ALIGN (TREE_TYPE (field)); | |
6502 | computed = (prev_align > cur_align) ? prev_align : cur_align; | |
6503 | } | |
6504 | } | |
6505 | ||
6506 | return computed; | |
6507 | } | |
6508 | ||
6509 | \f | |
6510 | /* A C expression that is nonzero if it is permissible to store a value of mode | |
6511 | MODE in hard register number REGNO (or in several registers starting with | |
6512 | that one). For a machine where all registers are equivalent, a suitable | |
6513 | definition is | |
6514 | ||
6515 | #define HARD_REGNO_MODE_OK(REGNO, MODE) 1 | |
6516 | ||
6517 | It is not necessary for this macro to check for the numbers of fixed | |
6518 | registers, because the allocation mechanism considers them to be always | |
6519 | occupied. | |
6520 | ||
6521 | On some machines, double-precision values must be kept in even/odd register | |
6522 | pairs. The way to implement that is to define this macro to reject odd | |
6523 | register numbers for such modes. | |
6524 | ||
6525 | The minimum requirement for a mode to be OK in a register is that the | |
6526 | `movMODE' instruction pattern support moves between the register and any | |
6527 | other hard register for which the mode is OK; and that moving a value into | |
6528 | the register and back out not alter it. | |
6529 | ||
6530 | Since the same instruction used to move `SImode' will work for all narrower | |
6531 | integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK' | |
6532 | to distinguish between these modes, provided you define patterns `movhi', | |
6533 | etc., to take advantage of this. This is useful because of the interaction | |
6534 | between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for | |
6535 | all integer modes to be tieable. | |
6536 | ||
6537 | Many machines have special registers for floating point arithmetic. Often | |
6538 | people assume that floating point machine modes are allowed only in floating | |
6539 | point registers. This is not true. Any registers that can hold integers | |
6540 | can safely *hold* a floating point machine mode, whether or not floating | |
6541 | arithmetic can be done on it in those registers. Integer move instructions | |
6542 | can be used to move the values. | |
6543 | ||
6544 | On some machines, though, the converse is true: fixed-point machine modes | |
6545 | may not go in floating registers. This is true if the floating registers | |
6546 | normalize any value stored in them, because storing a non-floating value | |
6547 | there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject | |
6548 | fixed-point machine modes in floating registers. But if the floating | |
6549 | registers do not automatically normalize, if you can store any bit pattern | |
6550 | in one and retrieve it unchanged without a trap, then any machine mode may | |
6551 | go in a floating register, so you can define this macro to say so. | |
6552 | ||
6553 | The primary significance of special floating registers is rather that they | |
6554 | are the registers acceptable in floating point arithmetic instructions. | |
6555 | However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by | |
6556 | writing the proper constraints for those instructions. | |
6557 | ||
6558 | On some machines, the floating registers are especially slow to access, so | |
6559 | that it is better to store a value in a stack frame than in such a register | |
6560 | if floating point arithmetic is not being done. As long as the floating | |
6561 | registers are not in class `GENERAL_REGS', they will not be used unless some | |
6562 | pattern's constraint asks for one. */ | |
6563 | ||
6564 | int | |
f2206911 | 6565 | frv_hard_regno_mode_ok (int regno, enum machine_mode mode) |
36a05131 BS |
6566 | { |
6567 | int base; | |
6568 | int mask; | |
6569 | ||
6570 | switch (mode) | |
6571 | { | |
6572 | case CCmode: | |
6573 | case CC_UNSmode: | |
036ff63f | 6574 | case CC_NZmode: |
36a05131 BS |
6575 | return ICC_P (regno) || GPR_P (regno); |
6576 | ||
6577 | case CC_CCRmode: | |
6578 | return CR_P (regno) || GPR_P (regno); | |
6579 | ||
6580 | case CC_FPmode: | |
6581 | return FCC_P (regno) || GPR_P (regno); | |
6582 | ||
6583 | default: | |
6584 | break; | |
6585 | } | |
6586 | ||
6587 | /* Set BASE to the first register in REGNO's class. Set MASK to the | |
6588 | bits that must be clear in (REGNO - BASE) for the register to be | |
6589 | well-aligned. */ | |
6590 | if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode)) | |
6591 | { | |
6592 | if (ACCG_P (regno)) | |
6593 | { | |
6594 | /* ACCGs store one byte. Two-byte quantities must start in | |
6595 | even-numbered registers, four-byte ones in registers whose | |
6596 | numbers are divisible by four, and so on. */ | |
6597 | base = ACCG_FIRST; | |
6598 | mask = GET_MODE_SIZE (mode) - 1; | |
6599 | } | |
6600 | else | |
6601 | { | |
b16c1435 EC |
6602 | /* The other registers store one word. */ |
6603 | if (GPR_P (regno) || regno == AP_FIRST) | |
36a05131 BS |
6604 | base = GPR_FIRST; |
6605 | ||
6606 | else if (FPR_P (regno)) | |
6607 | base = FPR_FIRST; | |
6608 | ||
6609 | else if (ACC_P (regno)) | |
6610 | base = ACC_FIRST; | |
6611 | ||
b16c1435 EC |
6612 | else if (SPR_P (regno)) |
6613 | return mode == SImode; | |
6614 | ||
87b483a1 | 6615 | /* Fill in the table. */ |
36a05131 BS |
6616 | else |
6617 | return 0; | |
6618 | ||
6619 | /* Anything smaller than an SI is OK in any word-sized register. */ | |
6620 | if (GET_MODE_SIZE (mode) < 4) | |
6621 | return 1; | |
6622 | ||
6623 | mask = (GET_MODE_SIZE (mode) / 4) - 1; | |
6624 | } | |
6625 | return (((regno - base) & mask) == 0); | |
6626 | } | |
6627 | ||
6628 | return 0; | |
6629 | } | |
6630 | ||
6631 | \f | |
6632 | /* A C expression for the number of consecutive hard registers, starting at | |
6633 | register number REGNO, required to hold a value of mode MODE. | |
6634 | ||
6635 | On a machine where all registers are exactly one word, a suitable definition | |
6636 | of this macro is | |
6637 | ||
6638 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
6639 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \ | |
6640 | / UNITS_PER_WORD)) */ | |
6641 | ||
6642 | /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so | |
6643 | that we can build the appropriate instructions to properly reload the | |
6644 | values. Also, make the byte-sized accumulator guards use one guard | |
6645 | for each byte. */ | |
6646 | ||
6647 | int | |
f2206911 | 6648 | frv_hard_regno_nregs (int regno, enum machine_mode mode) |
36a05131 BS |
6649 | { |
6650 | if (ACCG_P (regno)) | |
6651 | return GET_MODE_SIZE (mode); | |
6652 | else | |
6653 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
6654 | } | |
6655 | ||
6656 | \f | |
6657 | /* A C expression for the maximum number of consecutive registers of | |
6658 | class CLASS needed to hold a value of mode MODE. | |
6659 | ||
6660 | This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value | |
6661 | of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of | |
6662 | `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS. | |
6663 | ||
6664 | This macro helps control the handling of multiple-word values in | |
6665 | the reload pass. | |
6666 | ||
6667 | This declaration is required. */ | |
6668 | ||
6669 | int | |
f2206911 | 6670 | frv_class_max_nregs (enum reg_class class, enum machine_mode mode) |
36a05131 BS |
6671 | { |
6672 | if (class == ACCG_REGS) | |
6673 | /* An N-byte value requires N accumulator guards. */ | |
6674 | return GET_MODE_SIZE (mode); | |
6675 | else | |
6676 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
6677 | } | |
6678 | ||
6679 | \f | |
6680 | /* A C expression that is nonzero if X is a legitimate constant for an | |
6681 | immediate operand on the target machine. You can assume that X satisfies | |
6682 | `CONSTANT_P', so you need not check this. In fact, `1' is a suitable | |
6683 | definition for this macro on machines where anything `CONSTANT_P' is valid. */ | |
6684 | ||
6685 | int | |
f2206911 | 6686 | frv_legitimate_constant_p (rtx x) |
36a05131 BS |
6687 | { |
6688 | enum machine_mode mode = GET_MODE (x); | |
6689 | ||
34208acf AO |
6690 | /* frv_cannot_force_const_mem always returns true for FDPIC. This |
6691 | means that the move expanders will be expected to deal with most | |
6692 | kinds of constant, regardless of what we return here. | |
6693 | ||
6694 | However, among its other duties, LEGITIMATE_CONSTANT_P decides whether | |
6695 | a constant can be entered into reg_equiv_constant[]. If we return true, | |
6696 | reload can create new instances of the constant whenever it likes. | |
6697 | ||
6698 | The idea is therefore to accept as many constants as possible (to give | |
6699 | reload more freedom) while rejecting constants that can only be created | |
6700 | at certain times. In particular, anything with a symbolic component will | |
6701 | require use of the pseudo FDPIC register, which is only available before | |
6702 | reload. */ | |
6703 | if (TARGET_FDPIC) | |
6704 | return LEGITIMATE_PIC_OPERAND_P (x); | |
6705 | ||
87b483a1 | 6706 | /* All of the integer constants are ok. */ |
36a05131 BS |
6707 | if (GET_CODE (x) != CONST_DOUBLE) |
6708 | return TRUE; | |
6709 | ||
87b483a1 | 6710 | /* double integer constants are ok. */ |
36a05131 BS |
6711 | if (mode == VOIDmode || mode == DImode) |
6712 | return TRUE; | |
6713 | ||
87b483a1 | 6714 | /* 0 is always ok. */ |
36a05131 BS |
6715 | if (x == CONST0_RTX (mode)) |
6716 | return TRUE; | |
6717 | ||
6718 | /* If floating point is just emulated, allow any constant, since it will be | |
87b483a1 | 6719 | constructed in the GPRs. */ |
36a05131 BS |
6720 | if (!TARGET_HAS_FPRS) |
6721 | return TRUE; | |
6722 | ||
6723 | if (mode == DFmode && !TARGET_DOUBLE) | |
6724 | return TRUE; | |
6725 | ||
6726 | /* Otherwise store the constant away and do a load. */ | |
6727 | return FALSE; | |
6728 | } | |
036ff63f RS |
6729 | |
6730 | /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons, | |
6731 | CC_NZ for comparisons against zero in which a single Z or N flag test | |
6732 | is enough, CC_UNS for other unsigned comparisons, and CC for other | |
6733 | signed comparisons. */ | |
6734 | ||
6735 | enum machine_mode | |
6736 | frv_select_cc_mode (enum rtx_code code, rtx x, rtx y) | |
6737 | { | |
6738 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
6739 | return CC_FPmode; | |
6740 | ||
6741 | switch (code) | |
6742 | { | |
6743 | case EQ: | |
6744 | case NE: | |
6745 | case LT: | |
6746 | case GE: | |
6747 | return y == const0_rtx ? CC_NZmode : CCmode; | |
6748 | ||
6749 | case GTU: | |
6750 | case GEU: | |
6751 | case LTU: | |
6752 | case LEU: | |
6753 | return y == const0_rtx ? CC_NZmode : CC_UNSmode; | |
6754 | ||
6755 | default: | |
6756 | return CCmode; | |
6757 | } | |
6758 | } | |
36a05131 BS |
6759 | \f |
6760 | /* A C expression for the cost of moving data from a register in class FROM to | |
6761 | one in class TO. The classes are expressed using the enumeration values | |
6762 | such as `GENERAL_REGS'. A value of 4 is the default; other values are | |
6763 | interpreted relative to that. | |
6764 | ||
6765 | It is not required that the cost always equal 2 when FROM is the same as TO; | |
6766 | on some machines it is expensive to move between registers if they are not | |
6767 | general registers. | |
6768 | ||
6769 | If reload sees an insn consisting of a single `set' between two hard | |
6770 | registers, and if `REGISTER_MOVE_COST' applied to their classes returns a | |
6771 | value of 2, reload does not check to ensure that the constraints of the insn | |
6772 | are met. Setting a cost of other than 2 will allow reload to verify that | |
6773 | the constraints are met. You should do this if the `movM' pattern's | |
6774 | constraints do not allow such copying. */ | |
6775 | ||
6776 | #define HIGH_COST 40 | |
6777 | #define MEDIUM_COST 3 | |
6778 | #define LOW_COST 1 | |
6779 | ||
6780 | int | |
f2206911 | 6781 | frv_register_move_cost (enum reg_class from, enum reg_class to) |
36a05131 BS |
6782 | { |
6783 | switch (from) | |
6784 | { | |
6785 | default: | |
6786 | break; | |
6787 | ||
6788 | case QUAD_REGS: | |
6789 | case EVEN_REGS: | |
6790 | case GPR_REGS: | |
6791 | switch (to) | |
6792 | { | |
6793 | default: | |
6794 | break; | |
6795 | ||
6796 | case QUAD_REGS: | |
6797 | case EVEN_REGS: | |
6798 | case GPR_REGS: | |
6799 | return LOW_COST; | |
6800 | ||
6801 | case FEVEN_REGS: | |
6802 | case FPR_REGS: | |
6803 | return LOW_COST; | |
6804 | ||
6805 | case LCR_REG: | |
6806 | case LR_REG: | |
6807 | case SPR_REGS: | |
6808 | return LOW_COST; | |
6809 | } | |
6810 | ||
6811 | case FEVEN_REGS: | |
6812 | case FPR_REGS: | |
6813 | switch (to) | |
6814 | { | |
6815 | default: | |
6816 | break; | |
6817 | ||
6818 | case QUAD_REGS: | |
6819 | case EVEN_REGS: | |
6820 | case GPR_REGS: | |
6821 | case ACC_REGS: | |
6822 | case EVEN_ACC_REGS: | |
6823 | case QUAD_ACC_REGS: | |
6824 | case ACCG_REGS: | |
6825 | return MEDIUM_COST; | |
6826 | ||
6827 | case FEVEN_REGS: | |
6828 | case FPR_REGS: | |
6829 | return LOW_COST; | |
6830 | } | |
6831 | ||
6832 | case LCR_REG: | |
6833 | case LR_REG: | |
6834 | case SPR_REGS: | |
6835 | switch (to) | |
6836 | { | |
6837 | default: | |
6838 | break; | |
6839 | ||
6840 | case QUAD_REGS: | |
6841 | case EVEN_REGS: | |
6842 | case GPR_REGS: | |
6843 | return MEDIUM_COST; | |
6844 | } | |
6845 | ||
6846 | case ACC_REGS: | |
6847 | case EVEN_ACC_REGS: | |
6848 | case QUAD_ACC_REGS: | |
6849 | case ACCG_REGS: | |
6850 | switch (to) | |
6851 | { | |
6852 | default: | |
6853 | break; | |
6854 | ||
6855 | case FEVEN_REGS: | |
6856 | case FPR_REGS: | |
6857 | return MEDIUM_COST; | |
6858 | ||
6859 | } | |
6860 | } | |
6861 | ||
6862 | return HIGH_COST; | |
6863 | } | |
6864 | \f | |
6865 | /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to | |
6866 | use ".picptr" to generate safe relocations for PIC code. We also | |
6867 | need a fixup entry for aligned (non-debugging) code. */ | |
6868 | ||
6869 | static bool | |
f2206911 | 6870 | frv_assemble_integer (rtx value, unsigned int size, int aligned_p) |
36a05131 | 6871 | { |
34208acf | 6872 | if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD) |
36a05131 BS |
6873 | { |
6874 | if (GET_CODE (value) == CONST | |
6875 | || GET_CODE (value) == SYMBOL_REF | |
6876 | || GET_CODE (value) == LABEL_REF) | |
6877 | { | |
34208acf AO |
6878 | if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF |
6879 | && SYMBOL_REF_FUNCTION_P (value)) | |
6880 | { | |
6881 | fputs ("\t.picptr\tfuncdesc(", asm_out_file); | |
6882 | output_addr_const (asm_out_file, value); | |
6883 | fputs (")\n", asm_out_file); | |
6884 | return true; | |
6885 | } | |
6886 | else if (TARGET_FDPIC && GET_CODE (value) == CONST | |
6887 | && frv_function_symbol_referenced_p (value)) | |
6888 | return false; | |
6889 | if (aligned_p && !TARGET_FDPIC) | |
36a05131 BS |
6890 | { |
6891 | static int label_num = 0; | |
6892 | char buf[256]; | |
6893 | const char *p; | |
6894 | ||
6895 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++); | |
14966b94 | 6896 | p = (* targetm.strip_name_encoding) (buf); |
36a05131 BS |
6897 | |
6898 | fprintf (asm_out_file, "%s:\n", p); | |
6899 | fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP); | |
6900 | fprintf (asm_out_file, "\t.picptr\t%s\n", p); | |
6901 | fprintf (asm_out_file, "\t.previous\n"); | |
6902 | } | |
6903 | assemble_integer_with_op ("\t.picptr\t", value); | |
6904 | return true; | |
6905 | } | |
6906 | if (!aligned_p) | |
6907 | { | |
6908 | /* We've set the unaligned SI op to NULL, so we always have to | |
6909 | handle the unaligned case here. */ | |
6910 | assemble_integer_with_op ("\t.4byte\t", value); | |
6911 | return true; | |
6912 | } | |
6913 | } | |
6914 | return default_assemble_integer (value, size, aligned_p); | |
6915 | } | |
6916 | ||
6917 | /* Function to set up the backend function structure. */ | |
6918 | ||
6919 | static struct machine_function * | |
f2206911 | 6920 | frv_init_machine_status (void) |
36a05131 BS |
6921 | { |
6922 | return ggc_alloc_cleared (sizeof (struct machine_function)); | |
6923 | } | |
ffb344c1 | 6924 | \f |
28a60850 RS |
6925 | /* Implement TARGET_SCHED_ISSUE_RATE. */ |
6926 | ||
c557edf4 | 6927 | int |
28a60850 RS |
6928 | frv_issue_rate (void) |
6929 | { | |
6930 | if (!TARGET_PACK) | |
6931 | return 1; | |
6932 | ||
6933 | switch (frv_cpu_type) | |
6934 | { | |
6935 | default: | |
6936 | case FRV_CPU_FR300: | |
6937 | case FRV_CPU_SIMPLE: | |
6938 | return 1; | |
6939 | ||
6940 | case FRV_CPU_FR400: | |
c557edf4 RS |
6941 | case FRV_CPU_FR405: |
6942 | case FRV_CPU_FR450: | |
28a60850 RS |
6943 | return 2; |
6944 | ||
6945 | case FRV_CPU_GENERIC: | |
6946 | case FRV_CPU_FR500: | |
6947 | case FRV_CPU_TOMCAT: | |
6948 | return 4; | |
c557edf4 RS |
6949 | |
6950 | case FRV_CPU_FR550: | |
6951 | return 8; | |
28a60850 RS |
6952 | } |
6953 | } | |
36a05131 | 6954 | \f |
c557edf4 RS |
6955 | /* A for_each_rtx callback. If X refers to an accumulator, return |
6956 | ACC_GROUP_ODD if the bit 2 of the register number is set and | |
6957 | ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE) | |
6958 | otherwise. */ | |
36a05131 | 6959 | |
c557edf4 RS |
6960 | static int |
6961 | frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED) | |
36a05131 | 6962 | { |
c557edf4 | 6963 | if (REG_P (*x)) |
36a05131 | 6964 | { |
c557edf4 RS |
6965 | if (ACC_P (REGNO (*x))) |
6966 | return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN; | |
6967 | if (ACCG_P (REGNO (*x))) | |
6968 | return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN; | |
6969 | } | |
6970 | return 0; | |
6971 | } | |
36a05131 | 6972 | |
c557edf4 | 6973 | /* Return the value of INSN's acc_group attribute. */ |
36a05131 | 6974 | |
c557edf4 RS |
6975 | int |
6976 | frv_acc_group (rtx insn) | |
6977 | { | |
6978 | /* This distinction only applies to the FR550 packing constraints. */ | |
6979 | if (frv_cpu_type != FRV_CPU_FR550) | |
6980 | return ACC_GROUP_NONE; | |
6981 | return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0); | |
6982 | } | |
36a05131 | 6983 | |
c557edf4 RS |
6984 | /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction |
6985 | INSN will try to claim first. Since this value depends only on the | |
6986 | type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */ | |
36a05131 | 6987 | |
c557edf4 RS |
6988 | static unsigned int |
6989 | frv_insn_unit (rtx insn) | |
6990 | { | |
6991 | enum attr_type type; | |
36a05131 | 6992 | |
c557edf4 RS |
6993 | type = get_attr_type (insn); |
6994 | if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes)) | |
6995 | { | |
6996 | /* We haven't seen this type of instruction before. */ | |
6997 | state_t state; | |
6998 | unsigned int unit; | |
36a05131 | 6999 | |
c557edf4 RS |
7000 | /* Issue the instruction on its own to see which unit it prefers. */ |
7001 | state = alloca (state_size ()); | |
7002 | state_reset (state); | |
7003 | state_transition (state, insn); | |
36a05131 | 7004 | |
c557edf4 RS |
7005 | /* Find out which unit was taken. */ |
7006 | for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++) | |
7007 | if (cpu_unit_reservation_p (state, frv_unit_codes[unit])) | |
7008 | break; | |
36a05131 | 7009 | |
44e91694 | 7010 | gcc_assert (unit != ARRAY_SIZE (frv_unit_codes)); |
36a05131 | 7011 | |
c557edf4 | 7012 | frv_type_to_unit[type] = unit; |
36a05131 | 7013 | } |
c557edf4 RS |
7014 | return frv_type_to_unit[type]; |
7015 | } | |
36a05131 | 7016 | |
c557edf4 | 7017 | /* Return true if INSN issues to a branch unit. */ |
36a05131 | 7018 | |
c557edf4 RS |
7019 | static bool |
7020 | frv_issues_to_branch_unit_p (rtx insn) | |
7021 | { | |
7022 | return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B; | |
7023 | } | |
7024 | \f | |
7025 | /* The current state of the packing pass, implemented by frv_pack_insns. */ | |
7026 | static struct { | |
7027 | /* The state of the pipeline DFA. */ | |
7028 | state_t dfa_state; | |
7029 | ||
7030 | /* Which hardware registers are set within the current packet, | |
7031 | and the conditions under which they are set. */ | |
7032 | regstate_t regstate[FIRST_PSEUDO_REGISTER]; | |
7033 | ||
7034 | /* The memory locations that have been modified so far in this | |
7035 | packet. MEM is the memref and COND is the regstate_t condition | |
7036 | under which it is set. */ | |
7037 | struct { | |
7038 | rtx mem; | |
7039 | regstate_t cond; | |
7040 | } mems[2]; | |
7041 | ||
7042 | /* The number of valid entries in MEMS. The value is larger than | |
7043 | ARRAY_SIZE (mems) if there were too many mems to record. */ | |
7044 | unsigned int num_mems; | |
7045 | ||
7046 | /* The maximum number of instructions that can be packed together. */ | |
7047 | unsigned int issue_rate; | |
7048 | ||
7049 | /* The instructions in the packet, partitioned into groups. */ | |
7050 | struct frv_packet_group { | |
7051 | /* How many instructions in the packet belong to this group. */ | |
7052 | unsigned int num_insns; | |
7053 | ||
7054 | /* A list of the instructions that belong to this group, in the order | |
7055 | they appear in the rtl stream. */ | |
7056 | rtx insns[ARRAY_SIZE (frv_unit_codes)]; | |
7057 | ||
7058 | /* The contents of INSNS after they have been sorted into the correct | |
7059 | assembly-language order. Element X issues to unit X. The list may | |
7060 | contain extra nops. */ | |
7061 | rtx sorted[ARRAY_SIZE (frv_unit_codes)]; | |
7062 | ||
7063 | /* The member of frv_nops[] to use in sorted[]. */ | |
7064 | rtx nop; | |
7065 | } groups[NUM_GROUPS]; | |
7066 | ||
7067 | /* The instructions that make up the current packet. */ | |
7068 | rtx insns[ARRAY_SIZE (frv_unit_codes)]; | |
7069 | unsigned int num_insns; | |
7070 | } frv_packet; | |
7071 | ||
7072 | /* Return the regstate_t flags for the given COND_EXEC condition. | |
7073 | Abort if the condition isn't in the right form. */ | |
36a05131 | 7074 | |
c557edf4 RS |
7075 | static int |
7076 | frv_cond_flags (rtx cond) | |
7077 | { | |
44e91694 NS |
7078 | gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE) |
7079 | && GET_CODE (XEXP (cond, 0)) == REG | |
7080 | && CR_P (REGNO (XEXP (cond, 0))) | |
7081 | && XEXP (cond, 1) == const0_rtx); | |
7082 | return ((REGNO (XEXP (cond, 0)) - CR_FIRST) | |
7083 | | (GET_CODE (cond) == NE | |
7084 | ? REGSTATE_IF_TRUE | |
7085 | : REGSTATE_IF_FALSE)); | |
c557edf4 | 7086 | } |
36a05131 | 7087 | |
36a05131 | 7088 | |
c557edf4 RS |
7089 | /* Return true if something accessed under condition COND2 can |
7090 | conflict with something written under condition COND1. */ | |
36a05131 | 7091 | |
c557edf4 RS |
7092 | static bool |
7093 | frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2) | |
7094 | { | |
7095 | /* If either reference was unconditional, we have a conflict. */ | |
7096 | if ((cond1 & REGSTATE_IF_EITHER) == 0 | |
7097 | || (cond2 & REGSTATE_IF_EITHER) == 0) | |
7098 | return true; | |
7099 | ||
7100 | /* The references might conflict if they were controlled by | |
7101 | different CRs. */ | |
7102 | if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK)) | |
7103 | return true; | |
7104 | ||
7105 | /* They definitely conflict if they are controlled by the | |
7106 | same condition. */ | |
7107 | if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0) | |
7108 | return true; | |
7109 | ||
7110 | return false; | |
36a05131 BS |
7111 | } |
7112 | ||
c557edf4 RS |
7113 | |
7114 | /* A for_each_rtx callback. Return 1 if *X depends on an instruction in | |
7115 | the current packet. DATA points to a regstate_t that describes the | |
7116 | condition under which *X might be set or used. */ | |
36a05131 BS |
7117 | |
7118 | static int | |
c557edf4 | 7119 | frv_registers_conflict_p_1 (rtx *x, void *data) |
36a05131 | 7120 | { |
c557edf4 RS |
7121 | unsigned int regno, i; |
7122 | regstate_t cond; | |
36a05131 | 7123 | |
c557edf4 | 7124 | cond = *(regstate_t *) data; |
36a05131 | 7125 | |
c557edf4 RS |
7126 | if (GET_CODE (*x) == REG) |
7127 | FOR_EACH_REGNO (regno, *x) | |
7128 | if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0) | |
7129 | if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond)) | |
7130 | return 1; | |
36a05131 | 7131 | |
c557edf4 RS |
7132 | if (GET_CODE (*x) == MEM) |
7133 | { | |
7134 | /* If we ran out of memory slots, assume a conflict. */ | |
7135 | if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems)) | |
7136 | return 1; | |
36a05131 | 7137 | |
c557edf4 RS |
7138 | /* Check for output or true dependencies with earlier MEMs. */ |
7139 | for (i = 0; i < frv_packet.num_mems; i++) | |
7140 | if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond)) | |
7141 | { | |
7142 | if (true_dependence (frv_packet.mems[i].mem, VOIDmode, | |
7143 | *x, rtx_varies_p)) | |
7144 | return 1; | |
36a05131 | 7145 | |
c557edf4 RS |
7146 | if (output_dependence (frv_packet.mems[i].mem, *x)) |
7147 | return 1; | |
7148 | } | |
7149 | } | |
36a05131 | 7150 | |
c557edf4 RS |
7151 | /* The return values of calls aren't significant: they describe |
7152 | the effect of the call as a whole, not of the insn itself. */ | |
7153 | if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL) | |
7154 | { | |
7155 | if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data)) | |
7156 | return 1; | |
7157 | return -1; | |
7158 | } | |
36a05131 | 7159 | |
c557edf4 RS |
7160 | /* Check subexpressions. */ |
7161 | return 0; | |
7162 | } | |
36a05131 | 7163 | |
36a05131 | 7164 | |
c557edf4 RS |
7165 | /* Return true if something in X might depend on an instruction |
7166 | in the current packet. */ | |
36a05131 | 7167 | |
c557edf4 RS |
7168 | static bool |
7169 | frv_registers_conflict_p (rtx x) | |
7170 | { | |
7171 | regstate_t flags; | |
36a05131 | 7172 | |
c557edf4 RS |
7173 | flags = 0; |
7174 | if (GET_CODE (x) == COND_EXEC) | |
7175 | { | |
7176 | if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags)) | |
7177 | return true; | |
36a05131 | 7178 | |
c557edf4 RS |
7179 | flags |= frv_cond_flags (XEXP (x, 0)); |
7180 | x = XEXP (x, 1); | |
36a05131 | 7181 | } |
c557edf4 RS |
7182 | return for_each_rtx (&x, frv_registers_conflict_p_1, &flags); |
7183 | } | |
36a05131 BS |
7184 | |
7185 | ||
c557edf4 RS |
7186 | /* A note_stores callback. DATA points to the regstate_t condition |
7187 | under which X is modified. Update FRV_PACKET accordingly. */ | |
36a05131 | 7188 | |
c557edf4 RS |
7189 | static void |
7190 | frv_registers_update_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data) | |
7191 | { | |
7192 | unsigned int regno; | |
7193 | ||
7194 | if (GET_CODE (x) == REG) | |
7195 | FOR_EACH_REGNO (regno, x) | |
7196 | frv_packet.regstate[regno] |= *(regstate_t *) data; | |
7197 | ||
7198 | if (GET_CODE (x) == MEM) | |
36a05131 | 7199 | { |
c557edf4 | 7200 | if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems)) |
36a05131 | 7201 | { |
c557edf4 RS |
7202 | frv_packet.mems[frv_packet.num_mems].mem = x; |
7203 | frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data; | |
7204 | } | |
7205 | frv_packet.num_mems++; | |
7206 | } | |
7207 | } | |
36a05131 | 7208 | |
36a05131 | 7209 | |
c557edf4 RS |
7210 | /* Update the register state information for an instruction whose |
7211 | body is X. */ | |
7212 | ||
7213 | static void | |
7214 | frv_registers_update (rtx x) | |
7215 | { | |
7216 | regstate_t flags; | |
7217 | ||
7218 | flags = REGSTATE_MODIFIED; | |
7219 | if (GET_CODE (x) == COND_EXEC) | |
7220 | { | |
7221 | flags |= frv_cond_flags (XEXP (x, 0)); | |
7222 | x = XEXP (x, 1); | |
36a05131 | 7223 | } |
c557edf4 RS |
7224 | note_stores (x, frv_registers_update_1, &flags); |
7225 | } | |
36a05131 | 7226 | |
c557edf4 RS |
7227 | |
7228 | /* Initialize frv_packet for the start of a new packet. */ | |
7229 | ||
7230 | static void | |
7231 | frv_start_packet (void) | |
7232 | { | |
7233 | enum frv_insn_group group; | |
7234 | ||
7235 | memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate)); | |
7236 | frv_packet.num_mems = 0; | |
7237 | frv_packet.num_insns = 0; | |
7238 | for (group = 0; group < NUM_GROUPS; group++) | |
7239 | frv_packet.groups[group].num_insns = 0; | |
36a05131 BS |
7240 | } |
7241 | ||
36a05131 | 7242 | |
c557edf4 RS |
7243 | /* Likewise for the start of a new basic block. */ |
7244 | ||
7245 | static void | |
7246 | frv_start_packet_block (void) | |
36a05131 | 7247 | { |
c557edf4 RS |
7248 | state_reset (frv_packet.dfa_state); |
7249 | frv_start_packet (); | |
7250 | } | |
36a05131 | 7251 | |
c557edf4 RS |
7252 | |
7253 | /* Finish the current packet, if any, and start a new one. Call | |
7254 | HANDLE_PACKET with FRV_PACKET describing the completed packet. */ | |
7255 | ||
7256 | static void | |
7257 | frv_finish_packet (void (*handle_packet) (void)) | |
7258 | { | |
7259 | if (frv_packet.num_insns > 0) | |
36a05131 | 7260 | { |
c557edf4 RS |
7261 | handle_packet (); |
7262 | state_transition (frv_packet.dfa_state, 0); | |
7263 | frv_start_packet (); | |
7264 | } | |
7265 | } | |
36a05131 | 7266 | |
36a05131 | 7267 | |
c557edf4 RS |
7268 | /* Return true if INSN can be added to the current packet. Update |
7269 | the DFA state on success. */ | |
36a05131 | 7270 | |
c557edf4 RS |
7271 | static bool |
7272 | frv_pack_insn_p (rtx insn) | |
7273 | { | |
7274 | /* See if the packet is already as long as it can be. */ | |
7275 | if (frv_packet.num_insns == frv_packet.issue_rate) | |
7276 | return false; | |
36a05131 | 7277 | |
c557edf4 RS |
7278 | /* If the scheduler thought that an instruction should start a packet, |
7279 | it's usually a good idea to believe it. It knows much more about | |
7280 | the latencies than we do. | |
36a05131 | 7281 | |
c557edf4 | 7282 | There are some exceptions though: |
36a05131 | 7283 | |
c557edf4 RS |
7284 | - Conditional instructions are scheduled on the assumption that |
7285 | they will be executed. This is usually a good thing, since it | |
c112cf2b | 7286 | tends to avoid unnecessary stalls in the conditional code. |
c557edf4 RS |
7287 | But we want to pack conditional instructions as tightly as |
7288 | possible, in order to optimize the case where they aren't | |
7289 | executed. | |
36a05131 | 7290 | |
c557edf4 RS |
7291 | - The scheduler will always put branches on their own, even |
7292 | if there's no real dependency. | |
36a05131 | 7293 | |
c557edf4 RS |
7294 | - There's no point putting a call in its own packet unless |
7295 | we have to. */ | |
7296 | if (frv_packet.num_insns > 0 | |
7297 | && GET_CODE (insn) == INSN | |
7298 | && GET_MODE (insn) == TImode | |
7299 | && GET_CODE (PATTERN (insn)) != COND_EXEC) | |
7300 | return false; | |
36a05131 | 7301 | |
c557edf4 RS |
7302 | /* Check for register conflicts. Don't do this for setlo since any |
7303 | conflict will be with the partnering sethi, with which it can | |
7304 | be packed. */ | |
7305 | if (get_attr_type (insn) != TYPE_SETLO) | |
7306 | if (frv_registers_conflict_p (PATTERN (insn))) | |
7307 | return false; | |
36a05131 | 7308 | |
c557edf4 RS |
7309 | return state_transition (frv_packet.dfa_state, insn) < 0; |
7310 | } | |
36a05131 | 7311 | |
36a05131 | 7312 | |
c557edf4 | 7313 | /* Add instruction INSN to the current packet. */ |
36a05131 | 7314 | |
c557edf4 RS |
7315 | static void |
7316 | frv_add_insn_to_packet (rtx insn) | |
7317 | { | |
7318 | struct frv_packet_group *packet_group; | |
7319 | ||
7320 | packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]]; | |
7321 | packet_group->insns[packet_group->num_insns++] = insn; | |
7322 | frv_packet.insns[frv_packet.num_insns++] = insn; | |
7323 | ||
7324 | frv_registers_update (PATTERN (insn)); | |
36a05131 BS |
7325 | } |
7326 | ||
c557edf4 RS |
7327 | |
7328 | /* Insert INSN (a member of frv_nops[]) into the current packet. If the | |
7329 | packet ends in a branch or call, insert the nop before it, otherwise | |
7330 | add to the end. */ | |
36a05131 BS |
7331 | |
7332 | static void | |
c557edf4 | 7333 | frv_insert_nop_in_packet (rtx insn) |
36a05131 | 7334 | { |
c557edf4 RS |
7335 | struct frv_packet_group *packet_group; |
7336 | rtx last; | |
7337 | ||
7338 | packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]]; | |
7339 | last = frv_packet.insns[frv_packet.num_insns - 1]; | |
7340 | if (GET_CODE (last) != INSN) | |
7341 | { | |
7342 | insn = emit_insn_before (PATTERN (insn), last); | |
7343 | frv_packet.insns[frv_packet.num_insns - 1] = insn; | |
7344 | frv_packet.insns[frv_packet.num_insns++] = last; | |
7345 | } | |
7346 | else | |
7347 | { | |
7348 | insn = emit_insn_after (PATTERN (insn), last); | |
7349 | frv_packet.insns[frv_packet.num_insns++] = insn; | |
7350 | } | |
7351 | packet_group->insns[packet_group->num_insns++] = insn; | |
7352 | } | |
7353 | ||
36a05131 | 7354 | |
c557edf4 RS |
7355 | /* If packing is enabled, divide the instructions into packets and |
7356 | return true. Call HANDLE_PACKET for each complete packet. */ | |
7357 | ||
7358 | static bool | |
7359 | frv_for_each_packet (void (*handle_packet) (void)) | |
7360 | { | |
7361 | rtx insn, next_insn; | |
7362 | ||
7363 | frv_packet.issue_rate = frv_issue_rate (); | |
7364 | ||
7365 | /* Early exit if we don't want to pack insns. */ | |
28a60850 RS |
7366 | if (!optimize |
7367 | || !flag_schedule_insns_after_reload | |
0b2c18fe | 7368 | || !TARGET_VLIW_BRANCH |
c557edf4 RS |
7369 | || frv_packet.issue_rate == 1) |
7370 | return false; | |
36a05131 | 7371 | |
c557edf4 | 7372 | /* Set up the initial packing state. */ |
36a05131 | 7373 | dfa_start (); |
c557edf4 | 7374 | frv_packet.dfa_state = alloca (state_size ()); |
36a05131 | 7375 | |
c557edf4 RS |
7376 | frv_start_packet_block (); |
7377 | for (insn = get_insns (); insn != 0; insn = next_insn) | |
36a05131 | 7378 | { |
c557edf4 RS |
7379 | enum rtx_code code; |
7380 | bool eh_insn_p; | |
36a05131 | 7381 | |
c557edf4 RS |
7382 | code = GET_CODE (insn); |
7383 | next_insn = NEXT_INSN (insn); | |
7384 | ||
7385 | if (code == CODE_LABEL) | |
36a05131 | 7386 | { |
c557edf4 RS |
7387 | frv_finish_packet (handle_packet); |
7388 | frv_start_packet_block (); | |
7389 | } | |
36a05131 | 7390 | |
c557edf4 RS |
7391 | if (INSN_P (insn)) |
7392 | switch (GET_CODE (PATTERN (insn))) | |
7393 | { | |
7394 | case USE: | |
7395 | case CLOBBER: | |
7396 | case ADDR_VEC: | |
7397 | case ADDR_DIFF_VEC: | |
7398 | break; | |
36a05131 | 7399 | |
c557edf4 RS |
7400 | default: |
7401 | /* Calls mustn't be packed on a TOMCAT. */ | |
7402 | if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT) | |
7403 | frv_finish_packet (handle_packet); | |
7404 | ||
7405 | /* Since the last instruction in a packet determines the EH | |
7406 | region, any exception-throwing instruction must come at | |
7407 | the end of reordered packet. Insns that issue to a | |
7408 | branch unit are bound to come last; for others it's | |
7409 | too hard to predict. */ | |
7410 | eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL); | |
7411 | if (eh_insn_p && !frv_issues_to_branch_unit_p (insn)) | |
7412 | frv_finish_packet (handle_packet); | |
7413 | ||
7414 | /* Finish the current packet if we can't add INSN to it. | |
7415 | Simulate cycles until INSN is ready to issue. */ | |
7416 | if (!frv_pack_insn_p (insn)) | |
7417 | { | |
7418 | frv_finish_packet (handle_packet); | |
7419 | while (!frv_pack_insn_p (insn)) | |
7420 | state_transition (frv_packet.dfa_state, 0); | |
7421 | } | |
36a05131 | 7422 | |
c557edf4 RS |
7423 | /* Add the instruction to the packet. */ |
7424 | frv_add_insn_to_packet (insn); | |
7425 | ||
7426 | /* Calls and jumps end a packet, as do insns that throw | |
7427 | an exception. */ | |
7428 | if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p) | |
7429 | frv_finish_packet (handle_packet); | |
7430 | break; | |
7431 | } | |
7432 | } | |
7433 | frv_finish_packet (handle_packet); | |
7434 | dfa_finish (); | |
7435 | return true; | |
7436 | } | |
7437 | \f | |
7438 | /* Subroutine of frv_sort_insn_group. We are trying to sort | |
7439 | frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly | |
7440 | language order. We have already picked a new position for | |
7441 | frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set. | |
7442 | These instructions will occupy elements [0, LOWER_SLOT) and | |
7443 | [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is | |
7444 | the DFA state after issuing these instructions. | |
7445 | ||
7446 | Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation | |
7447 | of the unused instructions. Return true if one such permutation gives | |
7448 | a valid ordering, leaving the successful permutation in sorted[]. | |
7449 | Do not modify sorted[] until a valid permutation is found. */ | |
7450 | ||
7451 | static bool | |
7452 | frv_sort_insn_group_1 (enum frv_insn_group group, | |
7453 | unsigned int lower_slot, unsigned int upper_slot, | |
7454 | unsigned int issued, unsigned int num_insns, | |
7455 | state_t state) | |
7456 | { | |
7457 | struct frv_packet_group *packet_group; | |
7458 | unsigned int i; | |
7459 | state_t test_state; | |
7460 | size_t dfa_size; | |
7461 | rtx insn; | |
7462 | ||
7463 | /* Early success if we've filled all the slots. */ | |
7464 | if (lower_slot == upper_slot) | |
7465 | return true; | |
7466 | ||
7467 | packet_group = &frv_packet.groups[group]; | |
7468 | dfa_size = state_size (); | |
7469 | test_state = alloca (dfa_size); | |
7470 | ||
7471 | /* Try issuing each unused instruction. */ | |
7472 | for (i = num_insns - 1; i + 1 != 0; i--) | |
7473 | if (~issued & (1 << i)) | |
7474 | { | |
7475 | insn = packet_group->sorted[i]; | |
7476 | memcpy (test_state, state, dfa_size); | |
7477 | if (state_transition (test_state, insn) < 0 | |
7478 | && cpu_unit_reservation_p (test_state, | |
7479 | NTH_UNIT (group, upper_slot - 1)) | |
7480 | && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1, | |
7481 | issued | (1 << i), num_insns, | |
7482 | test_state)) | |
7483 | { | |
7484 | packet_group->sorted[upper_slot - 1] = insn; | |
7485 | return true; | |
7486 | } | |
7487 | } | |
7488 | ||
7489 | return false; | |
7490 | } | |
7491 | ||
7492 | /* Compare two instructions by their frv_insn_unit. */ | |
7493 | ||
7494 | static int | |
7495 | frv_compare_insns (const void *first, const void *second) | |
7496 | { | |
7497 | const rtx *insn1 = first, *insn2 = second; | |
7498 | return frv_insn_unit (*insn1) - frv_insn_unit (*insn2); | |
7499 | } | |
7500 | ||
7501 | /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[] | |
7502 | and sort it into assembly language order. See frv.md for a description of | |
7503 | the algorithm. */ | |
7504 | ||
7505 | static void | |
7506 | frv_sort_insn_group (enum frv_insn_group group) | |
7507 | { | |
7508 | struct frv_packet_group *packet_group; | |
7509 | unsigned int first, i, nop, max_unit, num_slots; | |
7510 | state_t state, test_state; | |
7511 | size_t dfa_size; | |
7512 | ||
7513 | packet_group = &frv_packet.groups[group]; | |
75d0ac8d RS |
7514 | |
7515 | /* Assume no nop is needed. */ | |
7516 | packet_group->nop = 0; | |
7517 | ||
c557edf4 RS |
7518 | if (packet_group->num_insns == 0) |
7519 | return; | |
7520 | ||
7521 | /* Copy insns[] to sorted[]. */ | |
7522 | memcpy (packet_group->sorted, packet_group->insns, | |
7523 | sizeof (rtx) * packet_group->num_insns); | |
7524 | ||
7525 | /* Sort sorted[] by the unit that each insn tries to take first. */ | |
7526 | if (packet_group->num_insns > 1) | |
7527 | qsort (packet_group->sorted, packet_group->num_insns, | |
7528 | sizeof (rtx), frv_compare_insns); | |
7529 | ||
7530 | /* That's always enough for branch and control insns. */ | |
7531 | if (group == GROUP_B || group == GROUP_C) | |
7532 | return; | |
7533 | ||
7534 | dfa_size = state_size (); | |
7535 | state = alloca (dfa_size); | |
7536 | test_state = alloca (dfa_size); | |
7537 | ||
7538 | /* Find the highest FIRST such that sorted[0...FIRST-1] can issue | |
7539 | consecutively and such that the DFA takes unit X when sorted[X] | |
7540 | is added. Set STATE to the new DFA state. */ | |
7541 | state_reset (test_state); | |
7542 | for (first = 0; first < packet_group->num_insns; first++) | |
7543 | { | |
7544 | memcpy (state, test_state, dfa_size); | |
7545 | if (state_transition (test_state, packet_group->sorted[first]) >= 0 | |
7546 | || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first))) | |
7547 | break; | |
7548 | } | |
7549 | ||
7550 | /* If all the instructions issued in ascending order, we're done. */ | |
7551 | if (first == packet_group->num_insns) | |
7552 | return; | |
36a05131 | 7553 | |
c557edf4 RS |
7554 | /* Add nops to the end of sorted[] and try each permutation until |
7555 | we find one that works. */ | |
7556 | for (nop = 0; nop < frv_num_nops; nop++) | |
7557 | { | |
7558 | max_unit = frv_insn_unit (frv_nops[nop]); | |
7559 | if (frv_unit_groups[max_unit] == group) | |
36a05131 | 7560 | { |
c557edf4 RS |
7561 | packet_group->nop = frv_nops[nop]; |
7562 | num_slots = UNIT_NUMBER (max_unit) + 1; | |
7563 | for (i = packet_group->num_insns; i < num_slots; i++) | |
7564 | packet_group->sorted[i] = frv_nops[nop]; | |
7565 | if (frv_sort_insn_group_1 (group, first, num_slots, | |
7566 | (1 << first) - 1, num_slots, state)) | |
7567 | return; | |
36a05131 | 7568 | } |
c557edf4 | 7569 | } |
44e91694 | 7570 | gcc_unreachable (); |
c557edf4 RS |
7571 | } |
7572 | \f | |
7573 | /* Sort the current packet into assembly-language order. Set packing | |
7574 | flags as appropriate. */ | |
36a05131 | 7575 | |
c557edf4 RS |
7576 | static void |
7577 | frv_reorder_packet (void) | |
7578 | { | |
7579 | unsigned int cursor[NUM_GROUPS]; | |
7580 | rtx insns[ARRAY_SIZE (frv_unit_groups)]; | |
7581 | unsigned int unit, to, from; | |
7582 | enum frv_insn_group group; | |
7583 | struct frv_packet_group *packet_group; | |
7584 | ||
7585 | /* First sort each group individually. */ | |
7586 | for (group = 0; group < NUM_GROUPS; group++) | |
7587 | { | |
7588 | cursor[group] = 0; | |
7589 | frv_sort_insn_group (group); | |
7590 | } | |
7591 | ||
7592 | /* Go through the unit template and try add an instruction from | |
7593 | that unit's group. */ | |
7594 | to = 0; | |
7595 | for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++) | |
7596 | { | |
7597 | group = frv_unit_groups[unit]; | |
7598 | packet_group = &frv_packet.groups[group]; | |
7599 | if (cursor[group] < packet_group->num_insns) | |
36a05131 | 7600 | { |
c557edf4 | 7601 | /* frv_reorg should have added nops for us. */ |
44e91694 NS |
7602 | gcc_assert (packet_group->sorted[cursor[group]] |
7603 | != packet_group->nop); | |
c557edf4 | 7604 | insns[to++] = packet_group->sorted[cursor[group]++]; |
36a05131 | 7605 | } |
c557edf4 | 7606 | } |
36a05131 | 7607 | |
44e91694 | 7608 | gcc_assert (to == frv_packet.num_insns); |
36a05131 | 7609 | |
c557edf4 RS |
7610 | /* Clear the last instruction's packing flag, thus marking the end of |
7611 | a packet. Reorder the other instructions relative to it. */ | |
7612 | CLEAR_PACKING_FLAG (insns[to - 1]); | |
7613 | for (from = 0; from < to - 1; from++) | |
7614 | { | |
7615 | remove_insn (insns[from]); | |
7616 | add_insn_before (insns[from], insns[to - 1]); | |
7617 | SET_PACKING_FLAG (insns[from]); | |
7618 | } | |
7619 | } | |
36a05131 | 7620 | |
36a05131 | 7621 | |
c557edf4 RS |
7622 | /* Divide instructions into packets. Reorder the contents of each |
7623 | packet so that they are in the correct assembly-language order. | |
7624 | ||
7625 | Since this pass can change the raw meaning of the rtl stream, it must | |
7626 | only be called at the last minute, just before the instructions are | |
7627 | written out. */ | |
7628 | ||
7629 | static void | |
7630 | frv_pack_insns (void) | |
7631 | { | |
7632 | if (frv_for_each_packet (frv_reorder_packet)) | |
7633 | frv_insn_packing_flag = 0; | |
7634 | else | |
7635 | frv_insn_packing_flag = -1; | |
7636 | } | |
7637 | \f | |
7638 | /* See whether we need to add nops to group GROUP in order to | |
7639 | make a valid packet. */ | |
7640 | ||
7641 | static void | |
7642 | frv_fill_unused_units (enum frv_insn_group group) | |
7643 | { | |
7644 | unsigned int non_nops, nops, i; | |
7645 | struct frv_packet_group *packet_group; | |
7646 | ||
7647 | packet_group = &frv_packet.groups[group]; | |
7648 | ||
7649 | /* Sort the instructions into assembly-language order. | |
7650 | Use nops to fill slots that are otherwise unused. */ | |
7651 | frv_sort_insn_group (group); | |
7652 | ||
7653 | /* See how many nops are needed before the final useful instruction. */ | |
7654 | i = nops = 0; | |
7655 | for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++) | |
7656 | while (packet_group->sorted[i++] == packet_group->nop) | |
7657 | nops++; | |
7658 | ||
7659 | /* Insert that many nops into the instruction stream. */ | |
7660 | while (nops-- > 0) | |
7661 | frv_insert_nop_in_packet (packet_group->nop); | |
7662 | } | |
7663 | ||
7664 | /* Used by frv_reorg to keep track of the current packet's address. */ | |
7665 | static unsigned int frv_packet_address; | |
36a05131 | 7666 | |
c557edf4 RS |
7667 | /* If the current packet falls through to a label, try to pad the packet |
7668 | with nops in order to fit the label's alignment requirements. */ | |
7669 | ||
7670 | static void | |
7671 | frv_align_label (void) | |
7672 | { | |
7673 | unsigned int alignment, target, nop; | |
7674 | rtx x, last, barrier, label; | |
7675 | ||
7676 | /* Walk forward to the start of the next packet. Set ALIGNMENT to the | |
7677 | maximum alignment of that packet, LABEL to the last label between | |
7678 | the packets, and BARRIER to the last barrier. */ | |
7679 | last = frv_packet.insns[frv_packet.num_insns - 1]; | |
7680 | label = barrier = 0; | |
7681 | alignment = 4; | |
7682 | for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x)) | |
7683 | { | |
7684 | if (LABEL_P (x)) | |
36a05131 | 7685 | { |
c557edf4 RS |
7686 | unsigned int subalign = 1 << label_to_alignment (x); |
7687 | alignment = MAX (alignment, subalign); | |
7688 | label = x; | |
36a05131 | 7689 | } |
c557edf4 RS |
7690 | if (BARRIER_P (x)) |
7691 | barrier = x; | |
7692 | } | |
36a05131 | 7693 | |
c557edf4 RS |
7694 | /* If -malign-labels, and the packet falls through to an unaligned |
7695 | label, try introducing a nop to align that label to 8 bytes. */ | |
7696 | if (TARGET_ALIGN_LABELS | |
7697 | && label != 0 | |
7698 | && barrier == 0 | |
7699 | && frv_packet.num_insns < frv_packet.issue_rate) | |
7700 | alignment = MAX (alignment, 8); | |
36a05131 | 7701 | |
c557edf4 RS |
7702 | /* Advance the address to the end of the current packet. */ |
7703 | frv_packet_address += frv_packet.num_insns * 4; | |
36a05131 | 7704 | |
c557edf4 RS |
7705 | /* Work out the target address, after alignment. */ |
7706 | target = (frv_packet_address + alignment - 1) & -alignment; | |
7707 | ||
7708 | /* If the packet falls through to the label, try to find an efficient | |
7709 | padding sequence. */ | |
7710 | if (barrier == 0) | |
7711 | { | |
7712 | /* First try adding nops to the current packet. */ | |
7713 | for (nop = 0; nop < frv_num_nops; nop++) | |
7714 | while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop])) | |
7715 | { | |
7716 | frv_insert_nop_in_packet (frv_nops[nop]); | |
7717 | frv_packet_address += 4; | |
7718 | } | |
7719 | ||
7720 | /* If we still haven't reached the target, add some new packets that | |
7721 | contain only nops. If there are two types of nop, insert an | |
7722 | alternating sequence of frv_nops[0] and frv_nops[1], which will | |
7723 | lead to packets like: | |
7724 | ||
7725 | nop.p | |
7726 | mnop.p/fnop.p | |
7727 | nop.p | |
7728 | mnop/fnop | |
7729 | ||
7730 | etc. Just emit frv_nops[0] if that's the only nop we have. */ | |
7731 | last = frv_packet.insns[frv_packet.num_insns - 1]; | |
7732 | nop = 0; | |
7733 | while (frv_packet_address < target) | |
7734 | { | |
7735 | last = emit_insn_after (PATTERN (frv_nops[nop]), last); | |
7736 | frv_packet_address += 4; | |
7737 | if (frv_num_nops > 1) | |
7738 | nop ^= 1; | |
36a05131 BS |
7739 | } |
7740 | } | |
7741 | ||
c557edf4 | 7742 | frv_packet_address = target; |
36a05131 BS |
7743 | } |
7744 | ||
c557edf4 RS |
7745 | /* Subroutine of frv_reorg, called after each packet has been constructed |
7746 | in frv_packet. */ | |
7747 | ||
7748 | static void | |
7749 | frv_reorg_packet (void) | |
7750 | { | |
7751 | frv_fill_unused_units (GROUP_I); | |
7752 | frv_fill_unused_units (GROUP_FM); | |
7753 | frv_align_label (); | |
7754 | } | |
7755 | ||
7756 | /* Add an instruction with pattern NOP to frv_nops[]. */ | |
7757 | ||
7758 | static void | |
7759 | frv_register_nop (rtx nop) | |
7760 | { | |
7761 | nop = make_insn_raw (nop); | |
7762 | NEXT_INSN (nop) = 0; | |
7763 | PREV_INSN (nop) = 0; | |
7764 | frv_nops[frv_num_nops++] = nop; | |
7765 | } | |
7766 | ||
7767 | /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions | |
7768 | into packets and check whether we need to insert nops in order to | |
7769 | fulfill the processor's issue requirements. Also, if the user has | |
7770 | requested a certain alignment for a label, try to meet that alignment | |
7771 | by inserting nops in the previous packet. */ | |
7772 | ||
7773 | static void | |
7774 | frv_reorg (void) | |
7775 | { | |
7776 | frv_num_nops = 0; | |
7777 | frv_register_nop (gen_nop ()); | |
7778 | if (TARGET_MEDIA) | |
7779 | frv_register_nop (gen_mnop ()); | |
7780 | if (TARGET_HARD_FLOAT) | |
7781 | frv_register_nop (gen_fnop ()); | |
7782 | ||
7783 | /* Estimate the length of each branch. Although this may change after | |
7784 | we've inserted nops, it will only do so in big functions. */ | |
7785 | shorten_branches (get_insns ()); | |
7786 | ||
7787 | frv_packet_address = 0; | |
7788 | frv_for_each_packet (frv_reorg_packet); | |
7789 | } | |
36a05131 BS |
7790 | \f |
7791 | #define def_builtin(name, type, code) \ | |
6e34d3a3 | 7792 | lang_hooks.builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL) |
36a05131 BS |
7793 | |
7794 | struct builtin_description | |
7795 | { | |
7796 | enum insn_code icode; | |
7797 | const char *name; | |
7798 | enum frv_builtins code; | |
7799 | enum rtx_code comparison; | |
7800 | unsigned int flag; | |
7801 | }; | |
7802 | ||
7803 | /* Media intrinsics that take a single, constant argument. */ | |
7804 | ||
7805 | static struct builtin_description bdesc_set[] = | |
7806 | { | |
7807 | { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 } | |
7808 | }; | |
7809 | ||
87b483a1 | 7810 | /* Media intrinsics that take just one argument. */ |
36a05131 BS |
7811 | |
7812 | static struct builtin_description bdesc_1arg[] = | |
7813 | { | |
7814 | { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 }, | |
7815 | { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 }, | |
7816 | { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 }, | |
7817 | { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 }, | |
c557edf4 RS |
7818 | { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 }, |
7819 | { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 } | |
36a05131 BS |
7820 | }; |
7821 | ||
87b483a1 | 7822 | /* Media intrinsics that take two arguments. */ |
36a05131 BS |
7823 | |
7824 | static struct builtin_description bdesc_2arg[] = | |
7825 | { | |
7826 | { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 }, | |
7827 | { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 }, | |
7828 | { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 }, | |
7829 | { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 }, | |
7830 | { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 }, | |
7831 | { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 }, | |
7832 | { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 }, | |
7833 | { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 }, | |
7834 | { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 }, | |
7835 | { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 }, | |
7836 | { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 }, | |
7837 | { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 }, | |
7838 | { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 }, | |
7839 | { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 }, | |
7840 | { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 }, | |
36a05131 BS |
7841 | { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 }, |
7842 | { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 }, | |
7843 | { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 }, | |
c557edf4 RS |
7844 | { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 }, |
7845 | { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 }, | |
7846 | { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 }, | |
7847 | { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 }, | |
7848 | { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 }, | |
7849 | { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 }, | |
7850 | { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 }, | |
7851 | { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 }, | |
7852 | { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 } | |
7853 | }; | |
7854 | ||
7855 | /* Integer intrinsics that take two arguments and have no return value. */ | |
7856 | ||
7857 | static struct builtin_description bdesc_int_void2arg[] = | |
7858 | { | |
7859 | { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 }, | |
7860 | { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 }, | |
7861 | { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 } | |
7862 | }; | |
7863 | ||
7864 | static struct builtin_description bdesc_prefetches[] = | |
7865 | { | |
7866 | { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 }, | |
7867 | { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 } | |
36a05131 BS |
7868 | }; |
7869 | ||
7870 | /* Media intrinsics that take two arguments, the first being an ACC number. */ | |
7871 | ||
7872 | static struct builtin_description bdesc_cut[] = | |
7873 | { | |
7874 | { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 }, | |
7875 | { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 }, | |
7876 | { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 } | |
7877 | }; | |
7878 | ||
87b483a1 | 7879 | /* Two-argument media intrinsics with an immediate second argument. */ |
36a05131 BS |
7880 | |
7881 | static struct builtin_description bdesc_2argimm[] = | |
7882 | { | |
7883 | { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 }, | |
7884 | { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 }, | |
7885 | { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 }, | |
7886 | { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 }, | |
7887 | { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 }, | |
7888 | { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 }, | |
7889 | { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 }, | |
7890 | { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 }, | |
7891 | { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 }, | |
7892 | { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 }, | |
7893 | { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 }, | |
7894 | { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 }, | |
7895 | { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 }, | |
7896 | { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 }, | |
c557edf4 RS |
7897 | { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 }, |
7898 | { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 }, | |
7899 | { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 } | |
36a05131 BS |
7900 | }; |
7901 | ||
7902 | /* Media intrinsics that take two arguments and return void, the first argument | |
87b483a1 | 7903 | being a pointer to 4 words in memory. */ |
36a05131 BS |
7904 | |
7905 | static struct builtin_description bdesc_void2arg[] = | |
7906 | { | |
7907 | { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 }, | |
7908 | { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 }, | |
7909 | }; | |
7910 | ||
7911 | /* Media intrinsics that take three arguments, the first being a const_int that | |
87b483a1 | 7912 | denotes an accumulator, and that return void. */ |
36a05131 BS |
7913 | |
7914 | static struct builtin_description bdesc_void3arg[] = | |
7915 | { | |
7916 | { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 }, | |
7917 | { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 }, | |
7918 | { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 }, | |
7919 | { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 }, | |
7920 | { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 }, | |
7921 | { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 }, | |
7922 | { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 }, | |
7923 | { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 }, | |
7924 | { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 }, | |
7925 | { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 }, | |
7926 | { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 }, | |
7927 | { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 }, | |
7928 | { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 }, | |
7929 | { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 }, | |
7930 | { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 }, | |
7931 | { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 }, | |
7932 | { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 }, | |
7933 | { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 }, | |
7934 | { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 }, | |
7935 | { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 }, | |
7936 | { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 }, | |
7937 | { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 }, | |
7938 | { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 }, | |
7939 | { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 }, | |
7940 | { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 } | |
7941 | }; | |
7942 | ||
7943 | /* Media intrinsics that take two accumulator numbers as argument and | |
7944 | return void. */ | |
7945 | ||
7946 | static struct builtin_description bdesc_voidacc[] = | |
7947 | { | |
7948 | { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 }, | |
7949 | { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 }, | |
7950 | { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 }, | |
7951 | { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 }, | |
7952 | { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 }, | |
7953 | { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 } | |
7954 | }; | |
7955 | ||
87b483a1 | 7956 | /* Initialize media builtins. */ |
36a05131 | 7957 | |
14966b94 | 7958 | static void |
f2206911 | 7959 | frv_init_builtins (void) |
36a05131 BS |
7960 | { |
7961 | tree endlink = void_list_node; | |
7962 | tree accumulator = integer_type_node; | |
7963 | tree integer = integer_type_node; | |
7964 | tree voidt = void_type_node; | |
7965 | tree uhalf = short_unsigned_type_node; | |
7966 | tree sword1 = long_integer_type_node; | |
7967 | tree uword1 = long_unsigned_type_node; | |
7968 | tree sword2 = long_long_integer_type_node; | |
7969 | tree uword2 = long_long_unsigned_type_node; | |
7970 | tree uword4 = build_pointer_type (uword1); | |
c557edf4 | 7971 | tree iacc = integer_type_node; |
36a05131 BS |
7972 | |
7973 | #define UNARY(RET, T1) \ | |
7974 | build_function_type (RET, tree_cons (NULL_TREE, T1, endlink)) | |
7975 | ||
7976 | #define BINARY(RET, T1, T2) \ | |
7977 | build_function_type (RET, tree_cons (NULL_TREE, T1, \ | |
7978 | tree_cons (NULL_TREE, T2, endlink))) | |
7979 | ||
7980 | #define TRINARY(RET, T1, T2, T3) \ | |
7981 | build_function_type (RET, tree_cons (NULL_TREE, T1, \ | |
7982 | tree_cons (NULL_TREE, T2, \ | |
7983 | tree_cons (NULL_TREE, T3, endlink)))) | |
7984 | ||
a738d848 RS |
7985 | #define QUAD(RET, T1, T2, T3, T4) \ |
7986 | build_function_type (RET, tree_cons (NULL_TREE, T1, \ | |
7987 | tree_cons (NULL_TREE, T2, \ | |
7988 | tree_cons (NULL_TREE, T3, \ | |
7989 | tree_cons (NULL_TREE, T4, endlink))))) | |
7990 | ||
36a05131 BS |
7991 | tree void_ftype_void = build_function_type (voidt, endlink); |
7992 | ||
7993 | tree void_ftype_acc = UNARY (voidt, accumulator); | |
7994 | tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1); | |
7995 | tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2); | |
7996 | tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1); | |
7997 | tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator); | |
7998 | tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1); | |
7999 | tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1); | |
8000 | tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2); | |
8001 | tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2); | |
8002 | ||
8003 | tree uw1_ftype_uw1 = UNARY (uword1, uword1); | |
8004 | tree uw1_ftype_sw1 = UNARY (uword1, sword1); | |
8005 | tree uw1_ftype_uw2 = UNARY (uword1, uword2); | |
8006 | tree uw1_ftype_acc = UNARY (uword1, accumulator); | |
8007 | tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf); | |
8008 | tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1); | |
8009 | tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer); | |
8010 | tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1); | |
8011 | tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1); | |
8012 | tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1); | |
8013 | tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer); | |
8014 | ||
8015 | tree sw1_ftype_int = UNARY (sword1, integer); | |
8016 | tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1); | |
8017 | tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer); | |
8018 | ||
8019 | tree uw2_ftype_uw1 = UNARY (uword2, uword1); | |
8020 | tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer); | |
8021 | tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2); | |
8022 | tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer); | |
8023 | tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer); | |
a738d848 | 8024 | tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf); |
36a05131 BS |
8025 | |
8026 | tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2); | |
c557edf4 RS |
8027 | tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer); |
8028 | tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1); | |
8029 | tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1); | |
8030 | tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1); | |
8031 | tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2); | |
8032 | tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1); | |
8033 | tree sw1_ftype_sw1 = UNARY (sword1, sword1); | |
8034 | tree sw2_ftype_iacc = UNARY (sword2, iacc); | |
8035 | tree sw1_ftype_iacc = UNARY (sword1, iacc); | |
8036 | tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node); | |
36a05131 BS |
8037 | |
8038 | def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND); | |
8039 | def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR); | |
8040 | def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR); | |
8041 | def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT); | |
8042 | def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI); | |
8043 | def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI); | |
8044 | def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT); | |
8045 | def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH); | |
8046 | def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI); | |
8047 | def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI); | |
8048 | def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI); | |
8049 | def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS); | |
8050 | def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU); | |
8051 | def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS); | |
8052 | def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS); | |
8053 | def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS); | |
8054 | def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS); | |
8055 | def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS); | |
8056 | def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU); | |
8057 | def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS); | |
8058 | def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU); | |
8059 | def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS); | |
8060 | def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU); | |
8061 | def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS); | |
8062 | def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU); | |
8063 | def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS); | |
8064 | def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS); | |
8065 | def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS); | |
8066 | def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS); | |
8067 | def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS); | |
8068 | def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU); | |
8069 | def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS); | |
8070 | def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU); | |
8071 | def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS); | |
8072 | def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU); | |
8073 | def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS); | |
8074 | def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU); | |
8075 | def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS); | |
8076 | def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU); | |
8077 | def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS); | |
8078 | def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU); | |
8079 | def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS); | |
8080 | def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU); | |
8081 | def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT); | |
8082 | def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS); | |
8083 | def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW); | |
8084 | def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD); | |
8085 | def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH); | |
8086 | def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH); | |
a738d848 | 8087 | def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH); |
b16c1435 | 8088 | def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH); |
36a05131 BS |
8089 | def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH); |
8090 | def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB); | |
8091 | def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE); | |
8092 | def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC); | |
8093 | def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA); | |
8094 | def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC); | |
8095 | def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG); | |
8096 | def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC); | |
8097 | def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG); | |
8098 | def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1); | |
8099 | def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2); | |
8100 | def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP); | |
8101 | def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS); | |
8102 | def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS); | |
8103 | def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS); | |
8104 | def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS); | |
8105 | def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS); | |
8106 | def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS); | |
8107 | def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS); | |
8108 | def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS); | |
8109 | def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS); | |
8110 | def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS); | |
8111 | def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI); | |
8112 | def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI); | |
8113 | def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI); | |
8114 | def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI); | |
8115 | def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS); | |
8116 | def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS); | |
8117 | def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS); | |
8118 | def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS); | |
8119 | def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH); | |
8120 | def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH); | |
8121 | def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH); | |
c557edf4 RS |
8122 | def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS); |
8123 | def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS); | |
8124 | def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI); | |
8125 | def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI); | |
8126 | def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL); | |
8127 | def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL); | |
8128 | def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS); | |
8129 | def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS); | |
8130 | def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU); | |
8131 | def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS); | |
8132 | def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS); | |
8133 | def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS); | |
8134 | def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN); | |
8135 | def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS); | |
8136 | def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll); | |
8137 | def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl); | |
8138 | def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll); | |
8139 | def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl); | |
8140 | def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0); | |
8141 | def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH); | |
36a05131 BS |
8142 | |
8143 | #undef UNARY | |
8144 | #undef BINARY | |
8145 | #undef TRINARY | |
a738d848 | 8146 | #undef QUAD |
36a05131 BS |
8147 | } |
8148 | ||
c15c90bb ZW |
8149 | /* Set the names for various arithmetic operations according to the |
8150 | FRV ABI. */ | |
8151 | static void | |
8152 | frv_init_libfuncs (void) | |
8153 | { | |
8154 | set_optab_libfunc (smod_optab, SImode, "__modi"); | |
8155 | set_optab_libfunc (umod_optab, SImode, "__umodi"); | |
8156 | ||
8157 | set_optab_libfunc (add_optab, DImode, "__addll"); | |
8158 | set_optab_libfunc (sub_optab, DImode, "__subll"); | |
8159 | set_optab_libfunc (smul_optab, DImode, "__mulll"); | |
8160 | set_optab_libfunc (sdiv_optab, DImode, "__divll"); | |
8161 | set_optab_libfunc (smod_optab, DImode, "__modll"); | |
8162 | set_optab_libfunc (umod_optab, DImode, "__umodll"); | |
8163 | set_optab_libfunc (and_optab, DImode, "__andll"); | |
8164 | set_optab_libfunc (ior_optab, DImode, "__orll"); | |
8165 | set_optab_libfunc (xor_optab, DImode, "__xorll"); | |
8166 | set_optab_libfunc (one_cmpl_optab, DImode, "__notll"); | |
8167 | ||
8168 | set_optab_libfunc (add_optab, SFmode, "__addf"); | |
8169 | set_optab_libfunc (sub_optab, SFmode, "__subf"); | |
8170 | set_optab_libfunc (smul_optab, SFmode, "__mulf"); | |
8171 | set_optab_libfunc (sdiv_optab, SFmode, "__divf"); | |
8172 | ||
8173 | set_optab_libfunc (add_optab, DFmode, "__addd"); | |
8174 | set_optab_libfunc (sub_optab, DFmode, "__subd"); | |
8175 | set_optab_libfunc (smul_optab, DFmode, "__muld"); | |
8176 | set_optab_libfunc (sdiv_optab, DFmode, "__divd"); | |
8177 | ||
85363ca0 ZW |
8178 | set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod"); |
8179 | set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof"); | |
8180 | ||
8181 | set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi"); | |
8182 | set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll"); | |
8183 | set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi"); | |
8184 | set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll"); | |
8185 | ||
8186 | set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui"); | |
09c55720 RS |
8187 | set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull"); |
8188 | set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui"); | |
8189 | set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull"); | |
85363ca0 ZW |
8190 | |
8191 | set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof"); | |
8192 | set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof"); | |
8193 | set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod"); | |
8194 | set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod"); | |
c15c90bb ZW |
8195 | } |
8196 | ||
36a05131 BS |
8197 | /* Convert an integer constant to an accumulator register. ICODE is the |
8198 | code of the target instruction, OPNUM is the number of the | |
8199 | accumulator operand and OPVAL is the constant integer. Try both | |
8200 | ACC and ACCG registers; only report an error if neither fit the | |
8201 | instruction. */ | |
8202 | ||
8203 | static rtx | |
f2206911 | 8204 | frv_int_to_acc (enum insn_code icode, int opnum, rtx opval) |
36a05131 BS |
8205 | { |
8206 | rtx reg; | |
c557edf4 RS |
8207 | int i; |
8208 | ||
0fa2e4df | 8209 | /* ACCs and ACCGs are implicit global registers if media intrinsics |
c557edf4 | 8210 | are being used. We set up this lazily to avoid creating lots of |
c112cf2b | 8211 | unnecessary call_insn rtl in non-media code. */ |
c557edf4 RS |
8212 | for (i = 0; i <= ACC_MASK; i++) |
8213 | if ((i & ACC_MASK) == i) | |
8214 | global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1; | |
36a05131 BS |
8215 | |
8216 | if (GET_CODE (opval) != CONST_INT) | |
8217 | { | |
8218 | error ("accumulator is not a constant integer"); | |
8219 | return NULL_RTX; | |
8220 | } | |
c557edf4 | 8221 | if ((INTVAL (opval) & ~ACC_MASK) != 0) |
36a05131 BS |
8222 | { |
8223 | error ("accumulator number is out of bounds"); | |
8224 | return NULL_RTX; | |
8225 | } | |
8226 | ||
8227 | reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode, | |
8228 | ACC_FIRST + INTVAL (opval)); | |
8229 | if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode)) | |
8230 | REGNO (reg) = ACCG_FIRST + INTVAL (opval); | |
8231 | ||
8232 | if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode)) | |
8233 | { | |
9e637a26 | 8234 | error ("inappropriate accumulator for %qs", insn_data[icode].name); |
36a05131 BS |
8235 | return NULL_RTX; |
8236 | } | |
8237 | return reg; | |
8238 | } | |
8239 | ||
8240 | /* If an ACC rtx has mode MODE, return the mode that the matching ACCG | |
8241 | should have. */ | |
8242 | ||
8243 | static enum machine_mode | |
f2206911 | 8244 | frv_matching_accg_mode (enum machine_mode mode) |
36a05131 BS |
8245 | { |
8246 | switch (mode) | |
8247 | { | |
8248 | case V4SImode: | |
8249 | return V4QImode; | |
8250 | ||
8251 | case DImode: | |
8252 | return HImode; | |
8253 | ||
8254 | case SImode: | |
8255 | return QImode; | |
8256 | ||
8257 | default: | |
44e91694 | 8258 | gcc_unreachable (); |
36a05131 BS |
8259 | } |
8260 | } | |
8261 | ||
8262 | /* Return the accumulator guard that should be paired with accumulator | |
8263 | register ACC. The mode of the returned register is in the same | |
8264 | class as ACC, but is four times smaller. */ | |
8265 | ||
8266 | rtx | |
f2206911 | 8267 | frv_matching_accg_for_acc (rtx acc) |
36a05131 BS |
8268 | { |
8269 | return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)), | |
8270 | REGNO (acc) - ACC_FIRST + ACCG_FIRST); | |
8271 | } | |
8272 | ||
8273 | /* Read a value from the head of the tree list pointed to by ARGLISTPTR. | |
8274 | Return the value as an rtx and replace *ARGLISTPTR with the tail of the | |
8275 | list. */ | |
8276 | ||
8277 | static rtx | |
f2206911 | 8278 | frv_read_argument (tree *arglistptr) |
36a05131 BS |
8279 | { |
8280 | tree next = TREE_VALUE (*arglistptr); | |
8281 | *arglistptr = TREE_CHAIN (*arglistptr); | |
8282 | return expand_expr (next, NULL_RTX, VOIDmode, 0); | |
8283 | } | |
8284 | ||
c557edf4 RS |
8285 | /* Like frv_read_argument, but interpret the argument as the number |
8286 | of an IACC register and return a (reg:MODE ...) rtx for it. */ | |
8287 | ||
8288 | static rtx | |
8289 | frv_read_iacc_argument (enum machine_mode mode, tree *arglistptr) | |
8290 | { | |
8291 | int i, regno; | |
8292 | rtx op; | |
8293 | ||
8294 | op = frv_read_argument (arglistptr); | |
8295 | if (GET_CODE (op) != CONST_INT | |
8296 | || INTVAL (op) < 0 | |
8297 | || INTVAL (op) > IACC_LAST - IACC_FIRST | |
8298 | || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0) | |
8299 | { | |
8300 | error ("invalid IACC argument"); | |
8301 | op = const0_rtx; | |
8302 | } | |
8303 | ||
0fa2e4df | 8304 | /* IACCs are implicit global registers. We set up this lazily to |
c112cf2b | 8305 | avoid creating lots of unnecessary call_insn rtl when IACCs aren't |
c557edf4 RS |
8306 | being used. */ |
8307 | regno = INTVAL (op) + IACC_FIRST; | |
8308 | for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++) | |
8309 | global_regs[regno + i] = 1; | |
8310 | ||
8311 | return gen_rtx_REG (mode, regno); | |
8312 | } | |
8313 | ||
36a05131 BS |
8314 | /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE. |
8315 | The instruction should require a constant operand of some sort. The | |
8316 | function prints an error if OPVAL is not valid. */ | |
8317 | ||
8318 | static int | |
f2206911 | 8319 | frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval) |
36a05131 BS |
8320 | { |
8321 | if (GET_CODE (opval) != CONST_INT) | |
8322 | { | |
9e637a26 | 8323 | error ("%qs expects a constant argument", insn_data[icode].name); |
36a05131 BS |
8324 | return FALSE; |
8325 | } | |
8326 | if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode)) | |
8327 | { | |
9e637a26 | 8328 | error ("constant argument out of range for %qs", insn_data[icode].name); |
36a05131 BS |
8329 | return FALSE; |
8330 | } | |
8331 | return TRUE; | |
8332 | } | |
8333 | ||
8334 | /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET | |
8335 | if it's not null, has the right mode, and satisfies operand 0's | |
8336 | predicate. */ | |
8337 | ||
8338 | static rtx | |
f2206911 | 8339 | frv_legitimize_target (enum insn_code icode, rtx target) |
36a05131 BS |
8340 | { |
8341 | enum machine_mode mode = insn_data[icode].operand[0].mode; | |
8342 | ||
8343 | if (! target | |
8344 | || GET_MODE (target) != mode | |
8345 | || ! (*insn_data[icode].operand[0].predicate) (target, mode)) | |
8346 | return gen_reg_rtx (mode); | |
8347 | else | |
8348 | return target; | |
8349 | } | |
8350 | ||
8351 | /* Given that ARG is being passed as operand OPNUM to instruction ICODE, | |
839a4992 | 8352 | check whether ARG satisfies the operand's constraints. If it doesn't, |
36a05131 BS |
8353 | copy ARG to a temporary register and return that. Otherwise return ARG |
8354 | itself. */ | |
8355 | ||
8356 | static rtx | |
f2206911 | 8357 | frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg) |
36a05131 BS |
8358 | { |
8359 | enum machine_mode mode = insn_data[icode].operand[opnum].mode; | |
8360 | ||
8361 | if ((*insn_data[icode].operand[opnum].predicate) (arg, mode)) | |
8362 | return arg; | |
8363 | else | |
8364 | return copy_to_mode_reg (mode, arg); | |
8365 | } | |
8366 | ||
8367 | /* Expand builtins that take a single, constant argument. At the moment, | |
8368 | only MHDSETS falls into this category. */ | |
8369 | ||
8370 | static rtx | |
f2206911 | 8371 | frv_expand_set_builtin (enum insn_code icode, tree arglist, rtx target) |
36a05131 BS |
8372 | { |
8373 | rtx pat; | |
8374 | rtx op0 = frv_read_argument (&arglist); | |
8375 | ||
8376 | if (! frv_check_constant_argument (icode, 1, op0)) | |
8377 | return NULL_RTX; | |
8378 | ||
8379 | target = frv_legitimize_target (icode, target); | |
8380 | pat = GEN_FCN (icode) (target, op0); | |
8381 | if (! pat) | |
8382 | return NULL_RTX; | |
8383 | ||
8384 | emit_insn (pat); | |
8385 | return target; | |
8386 | } | |
8387 | ||
87b483a1 | 8388 | /* Expand builtins that take one operand. */ |
36a05131 BS |
8389 | |
8390 | static rtx | |
f2206911 | 8391 | frv_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target) |
36a05131 BS |
8392 | { |
8393 | rtx pat; | |
8394 | rtx op0 = frv_read_argument (&arglist); | |
8395 | ||
8396 | target = frv_legitimize_target (icode, target); | |
8397 | op0 = frv_legitimize_argument (icode, 1, op0); | |
8398 | pat = GEN_FCN (icode) (target, op0); | |
8399 | if (! pat) | |
8400 | return NULL_RTX; | |
8401 | ||
8402 | emit_insn (pat); | |
8403 | return target; | |
8404 | } | |
8405 | ||
87b483a1 | 8406 | /* Expand builtins that take two operands. */ |
36a05131 BS |
8407 | |
8408 | static rtx | |
f2206911 | 8409 | frv_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target) |
36a05131 BS |
8410 | { |
8411 | rtx pat; | |
8412 | rtx op0 = frv_read_argument (&arglist); | |
8413 | rtx op1 = frv_read_argument (&arglist); | |
8414 | ||
8415 | target = frv_legitimize_target (icode, target); | |
8416 | op0 = frv_legitimize_argument (icode, 1, op0); | |
8417 | op1 = frv_legitimize_argument (icode, 2, op1); | |
8418 | pat = GEN_FCN (icode) (target, op0, op1); | |
8419 | if (! pat) | |
8420 | return NULL_RTX; | |
8421 | ||
8422 | emit_insn (pat); | |
8423 | return target; | |
8424 | } | |
8425 | ||
8426 | /* Expand cut-style builtins, which take two operands and an implicit ACCG | |
87b483a1 | 8427 | one. */ |
36a05131 BS |
8428 | |
8429 | static rtx | |
f2206911 | 8430 | frv_expand_cut_builtin (enum insn_code icode, tree arglist, rtx target) |
36a05131 BS |
8431 | { |
8432 | rtx pat; | |
8433 | rtx op0 = frv_read_argument (&arglist); | |
8434 | rtx op1 = frv_read_argument (&arglist); | |
8435 | rtx op2; | |
8436 | ||
8437 | target = frv_legitimize_target (icode, target); | |
8438 | op0 = frv_int_to_acc (icode, 1, op0); | |
8439 | if (! op0) | |
8440 | return NULL_RTX; | |
8441 | ||
8442 | if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT) | |
8443 | { | |
8444 | if (! frv_check_constant_argument (icode, 2, op1)) | |
8445 | return NULL_RTX; | |
8446 | } | |
8447 | else | |
8448 | op1 = frv_legitimize_argument (icode, 2, op1); | |
8449 | ||
8450 | op2 = frv_matching_accg_for_acc (op0); | |
8451 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
8452 | if (! pat) | |
8453 | return NULL_RTX; | |
8454 | ||
8455 | emit_insn (pat); | |
8456 | return target; | |
8457 | } | |
8458 | ||
87b483a1 | 8459 | /* Expand builtins that take two operands and the second is immediate. */ |
36a05131 BS |
8460 | |
8461 | static rtx | |
f2206911 | 8462 | frv_expand_binopimm_builtin (enum insn_code icode, tree arglist, rtx target) |
36a05131 BS |
8463 | { |
8464 | rtx pat; | |
8465 | rtx op0 = frv_read_argument (&arglist); | |
8466 | rtx op1 = frv_read_argument (&arglist); | |
8467 | ||
8468 | if (! frv_check_constant_argument (icode, 2, op1)) | |
8469 | return NULL_RTX; | |
8470 | ||
8471 | target = frv_legitimize_target (icode, target); | |
8472 | op0 = frv_legitimize_argument (icode, 1, op0); | |
8473 | pat = GEN_FCN (icode) (target, op0, op1); | |
8474 | if (! pat) | |
8475 | return NULL_RTX; | |
8476 | ||
8477 | emit_insn (pat); | |
8478 | return target; | |
8479 | } | |
8480 | ||
8481 | /* Expand builtins that take two operands, the first operand being a pointer to | |
87b483a1 | 8482 | ints and return void. */ |
36a05131 BS |
8483 | |
8484 | static rtx | |
f2206911 | 8485 | frv_expand_voidbinop_builtin (enum insn_code icode, tree arglist) |
36a05131 BS |
8486 | { |
8487 | rtx pat; | |
8488 | rtx op0 = frv_read_argument (&arglist); | |
8489 | rtx op1 = frv_read_argument (&arglist); | |
8490 | enum machine_mode mode0 = insn_data[icode].operand[0].mode; | |
8491 | rtx addr; | |
8492 | ||
8493 | if (GET_CODE (op0) != MEM) | |
8494 | { | |
8495 | rtx reg = op0; | |
8496 | ||
8497 | if (! offsettable_address_p (0, mode0, op0)) | |
8498 | { | |
8499 | reg = gen_reg_rtx (Pmode); | |
8500 | emit_insn (gen_rtx_SET (VOIDmode, reg, op0)); | |
8501 | } | |
8502 | ||
8503 | op0 = gen_rtx_MEM (SImode, reg); | |
8504 | } | |
8505 | ||
8506 | addr = XEXP (op0, 0); | |
8507 | if (! offsettable_address_p (0, mode0, addr)) | |
8508 | addr = copy_to_mode_reg (Pmode, op0); | |
8509 | ||
8510 | op0 = change_address (op0, V4SImode, addr); | |
8511 | op1 = frv_legitimize_argument (icode, 1, op1); | |
8512 | pat = GEN_FCN (icode) (op0, op1); | |
8513 | if (! pat) | |
8514 | return 0; | |
8515 | ||
8516 | emit_insn (pat); | |
8517 | return 0; | |
8518 | } | |
8519 | ||
c557edf4 RS |
8520 | /* Expand builtins that take two long operands and return void. */ |
8521 | ||
8522 | static rtx | |
8523 | frv_expand_int_void2arg (enum insn_code icode, tree arglist) | |
8524 | { | |
8525 | rtx pat; | |
8526 | rtx op0 = frv_read_argument (&arglist); | |
8527 | rtx op1 = frv_read_argument (&arglist); | |
8528 | ||
8529 | op0 = frv_legitimize_argument (icode, 1, op0); | |
8530 | op1 = frv_legitimize_argument (icode, 1, op1); | |
8531 | pat = GEN_FCN (icode) (op0, op1); | |
8532 | if (! pat) | |
8533 | return NULL_RTX; | |
8534 | ||
8535 | emit_insn (pat); | |
8536 | return NULL_RTX; | |
8537 | } | |
8538 | ||
8539 | /* Expand prefetch builtins. These take a single address as argument. */ | |
8540 | ||
8541 | static rtx | |
8542 | frv_expand_prefetches (enum insn_code icode, tree arglist) | |
8543 | { | |
8544 | rtx pat; | |
8545 | rtx op0 = frv_read_argument (&arglist); | |
8546 | ||
8547 | pat = GEN_FCN (icode) (force_reg (Pmode, op0)); | |
8548 | if (! pat) | |
8549 | return 0; | |
8550 | ||
8551 | emit_insn (pat); | |
8552 | return 0; | |
8553 | } | |
8554 | ||
36a05131 BS |
8555 | /* Expand builtins that take three operands and return void. The first |
8556 | argument must be a constant that describes a pair or quad accumulators. A | |
8557 | fourth argument is created that is the accumulator guard register that | |
8558 | corresponds to the accumulator. */ | |
8559 | ||
8560 | static rtx | |
f2206911 | 8561 | frv_expand_voidtriop_builtin (enum insn_code icode, tree arglist) |
36a05131 BS |
8562 | { |
8563 | rtx pat; | |
8564 | rtx op0 = frv_read_argument (&arglist); | |
8565 | rtx op1 = frv_read_argument (&arglist); | |
8566 | rtx op2 = frv_read_argument (&arglist); | |
8567 | rtx op3; | |
8568 | ||
8569 | op0 = frv_int_to_acc (icode, 0, op0); | |
8570 | if (! op0) | |
8571 | return NULL_RTX; | |
8572 | ||
8573 | op1 = frv_legitimize_argument (icode, 1, op1); | |
8574 | op2 = frv_legitimize_argument (icode, 2, op2); | |
8575 | op3 = frv_matching_accg_for_acc (op0); | |
8576 | pat = GEN_FCN (icode) (op0, op1, op2, op3); | |
8577 | if (! pat) | |
8578 | return NULL_RTX; | |
8579 | ||
8580 | emit_insn (pat); | |
8581 | return NULL_RTX; | |
8582 | } | |
8583 | ||
8584 | /* Expand builtins that perform accumulator-to-accumulator operations. | |
8585 | These builtins take two accumulator numbers as argument and return | |
8586 | void. */ | |
8587 | ||
8588 | static rtx | |
f2206911 | 8589 | frv_expand_voidaccop_builtin (enum insn_code icode, tree arglist) |
36a05131 BS |
8590 | { |
8591 | rtx pat; | |
8592 | rtx op0 = frv_read_argument (&arglist); | |
8593 | rtx op1 = frv_read_argument (&arglist); | |
8594 | rtx op2; | |
8595 | rtx op3; | |
8596 | ||
8597 | op0 = frv_int_to_acc (icode, 0, op0); | |
8598 | if (! op0) | |
8599 | return NULL_RTX; | |
8600 | ||
8601 | op1 = frv_int_to_acc (icode, 1, op1); | |
8602 | if (! op1) | |
8603 | return NULL_RTX; | |
8604 | ||
8605 | op2 = frv_matching_accg_for_acc (op0); | |
8606 | op3 = frv_matching_accg_for_acc (op1); | |
8607 | pat = GEN_FCN (icode) (op0, op1, op2, op3); | |
8608 | if (! pat) | |
8609 | return NULL_RTX; | |
8610 | ||
8611 | emit_insn (pat); | |
8612 | return NULL_RTX; | |
8613 | } | |
8614 | ||
a738d848 RS |
8615 | /* Expand the MDPACKH builtin. It takes four unsigned short arguments and |
8616 | each argument forms one word of the two double-word input registers. | |
8617 | ARGLIST is a TREE_LIST of the arguments and TARGET, if nonnull, | |
8618 | suggests a good place to put the return value. */ | |
8619 | ||
8620 | static rtx | |
8621 | frv_expand_mdpackh_builtin (tree arglist, rtx target) | |
8622 | { | |
8623 | enum insn_code icode = CODE_FOR_mdpackh; | |
8624 | rtx pat, op0, op1; | |
8625 | rtx arg1 = frv_read_argument (&arglist); | |
8626 | rtx arg2 = frv_read_argument (&arglist); | |
8627 | rtx arg3 = frv_read_argument (&arglist); | |
8628 | rtx arg4 = frv_read_argument (&arglist); | |
8629 | ||
8630 | target = frv_legitimize_target (icode, target); | |
8631 | op0 = gen_reg_rtx (DImode); | |
8632 | op1 = gen_reg_rtx (DImode); | |
8633 | ||
0fa2e4df | 8634 | /* The high half of each word is not explicitly initialized, so indicate |
a738d848 RS |
8635 | that the input operands are not live before this point. */ |
8636 | emit_insn (gen_rtx_CLOBBER (DImode, op0)); | |
8637 | emit_insn (gen_rtx_CLOBBER (DImode, op1)); | |
8638 | ||
8639 | /* Move each argument into the low half of its associated input word. */ | |
8640 | emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1); | |
8641 | emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2); | |
8642 | emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3); | |
8643 | emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4); | |
8644 | ||
8645 | pat = GEN_FCN (icode) (target, op0, op1); | |
8646 | if (! pat) | |
8647 | return NULL_RTX; | |
8648 | ||
8649 | emit_insn (pat); | |
8650 | return target; | |
8651 | } | |
8652 | ||
36a05131 BS |
8653 | /* Expand the MCLRACC builtin. This builtin takes a single accumulator |
8654 | number as argument. */ | |
8655 | ||
8656 | static rtx | |
f2206911 | 8657 | frv_expand_mclracc_builtin (tree arglist) |
36a05131 BS |
8658 | { |
8659 | enum insn_code icode = CODE_FOR_mclracc; | |
8660 | rtx pat; | |
8661 | rtx op0 = frv_read_argument (&arglist); | |
8662 | ||
8663 | op0 = frv_int_to_acc (icode, 0, op0); | |
8664 | if (! op0) | |
8665 | return NULL_RTX; | |
8666 | ||
8667 | pat = GEN_FCN (icode) (op0); | |
8668 | if (pat) | |
8669 | emit_insn (pat); | |
8670 | ||
8671 | return NULL_RTX; | |
8672 | } | |
8673 | ||
8674 | /* Expand builtins that take no arguments. */ | |
8675 | ||
8676 | static rtx | |
f2206911 | 8677 | frv_expand_noargs_builtin (enum insn_code icode) |
36a05131 | 8678 | { |
a556fd39 | 8679 | rtx pat = GEN_FCN (icode) (const0_rtx); |
36a05131 BS |
8680 | if (pat) |
8681 | emit_insn (pat); | |
8682 | ||
8683 | return NULL_RTX; | |
8684 | } | |
8685 | ||
8686 | /* Expand MRDACC and MRDACCG. These builtins take a single accumulator | |
8687 | number or accumulator guard number as argument and return an SI integer. */ | |
8688 | ||
8689 | static rtx | |
f2206911 | 8690 | frv_expand_mrdacc_builtin (enum insn_code icode, tree arglist) |
36a05131 BS |
8691 | { |
8692 | rtx pat; | |
8693 | rtx target = gen_reg_rtx (SImode); | |
8694 | rtx op0 = frv_read_argument (&arglist); | |
8695 | ||
8696 | op0 = frv_int_to_acc (icode, 1, op0); | |
8697 | if (! op0) | |
8698 | return NULL_RTX; | |
8699 | ||
8700 | pat = GEN_FCN (icode) (target, op0); | |
8701 | if (! pat) | |
8702 | return NULL_RTX; | |
8703 | ||
8704 | emit_insn (pat); | |
8705 | return target; | |
8706 | } | |
8707 | ||
8708 | /* Expand MWTACC and MWTACCG. These builtins take an accumulator or | |
8709 | accumulator guard as their first argument and an SImode value as their | |
8710 | second. */ | |
8711 | ||
8712 | static rtx | |
f2206911 | 8713 | frv_expand_mwtacc_builtin (enum insn_code icode, tree arglist) |
36a05131 BS |
8714 | { |
8715 | rtx pat; | |
8716 | rtx op0 = frv_read_argument (&arglist); | |
8717 | rtx op1 = frv_read_argument (&arglist); | |
8718 | ||
8719 | op0 = frv_int_to_acc (icode, 0, op0); | |
8720 | if (! op0) | |
8721 | return NULL_RTX; | |
8722 | ||
8723 | op1 = frv_legitimize_argument (icode, 1, op1); | |
8724 | pat = GEN_FCN (icode) (op0, op1); | |
8725 | if (pat) | |
8726 | emit_insn (pat); | |
8727 | ||
8728 | return NULL_RTX; | |
8729 | } | |
8730 | ||
c557edf4 RS |
8731 | /* Emit a move from SRC to DEST in SImode chunks. This can be used |
8732 | to move DImode values into and out of IACC0. */ | |
8733 | ||
8734 | static void | |
8735 | frv_split_iacc_move (rtx dest, rtx src) | |
8736 | { | |
8737 | enum machine_mode inner; | |
8738 | int i; | |
8739 | ||
8740 | inner = GET_MODE (dest); | |
8741 | for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode)) | |
8742 | emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i), | |
8743 | simplify_gen_subreg (SImode, src, inner, i)); | |
8744 | } | |
8745 | ||
87b483a1 | 8746 | /* Expand builtins. */ |
36a05131 | 8747 | |
14966b94 | 8748 | static rtx |
f2206911 KC |
8749 | frv_expand_builtin (tree exp, |
8750 | rtx target, | |
8751 | rtx subtarget ATTRIBUTE_UNUSED, | |
8752 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
8753 | int ignore ATTRIBUTE_UNUSED) | |
36a05131 BS |
8754 | { |
8755 | tree arglist = TREE_OPERAND (exp, 1); | |
8756 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
8757 | unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl); | |
8758 | unsigned i; | |
8759 | struct builtin_description *d; | |
8760 | ||
c557edf4 | 8761 | if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA) |
36a05131 BS |
8762 | { |
8763 | error ("media functions are not available unless -mmedia is used"); | |
8764 | return NULL_RTX; | |
8765 | } | |
8766 | ||
8767 | switch (fcode) | |
8768 | { | |
8769 | case FRV_BUILTIN_MCOP1: | |
8770 | case FRV_BUILTIN_MCOP2: | |
8771 | case FRV_BUILTIN_MDUNPACKH: | |
8772 | case FRV_BUILTIN_MBTOHE: | |
8773 | if (! TARGET_MEDIA_REV1) | |
8774 | { | |
8775 | error ("this media function is only available on the fr500"); | |
8776 | return NULL_RTX; | |
8777 | } | |
8778 | break; | |
8779 | ||
8780 | case FRV_BUILTIN_MQXMACHS: | |
8781 | case FRV_BUILTIN_MQXMACXHS: | |
8782 | case FRV_BUILTIN_MQMACXHS: | |
8783 | case FRV_BUILTIN_MADDACCS: | |
8784 | case FRV_BUILTIN_MSUBACCS: | |
8785 | case FRV_BUILTIN_MASACCS: | |
8786 | case FRV_BUILTIN_MDADDACCS: | |
8787 | case FRV_BUILTIN_MDSUBACCS: | |
8788 | case FRV_BUILTIN_MDASACCS: | |
8789 | case FRV_BUILTIN_MABSHS: | |
8790 | case FRV_BUILTIN_MDROTLI: | |
8791 | case FRV_BUILTIN_MCPLHI: | |
8792 | case FRV_BUILTIN_MCPLI: | |
8793 | case FRV_BUILTIN_MDCUTSSI: | |
8794 | case FRV_BUILTIN_MQSATHS: | |
8795 | case FRV_BUILTIN_MHSETLOS: | |
8796 | case FRV_BUILTIN_MHSETLOH: | |
8797 | case FRV_BUILTIN_MHSETHIS: | |
8798 | case FRV_BUILTIN_MHSETHIH: | |
8799 | case FRV_BUILTIN_MHDSETS: | |
8800 | case FRV_BUILTIN_MHDSETH: | |
8801 | if (! TARGET_MEDIA_REV2) | |
8802 | { | |
c557edf4 RS |
8803 | error ("this media function is only available on the fr400" |
8804 | " and fr550"); | |
8805 | return NULL_RTX; | |
8806 | } | |
8807 | break; | |
8808 | ||
8809 | case FRV_BUILTIN_SMASS: | |
8810 | case FRV_BUILTIN_SMSSS: | |
8811 | case FRV_BUILTIN_SMU: | |
8812 | case FRV_BUILTIN_ADDSS: | |
8813 | case FRV_BUILTIN_SUBSS: | |
8814 | case FRV_BUILTIN_SLASS: | |
8815 | case FRV_BUILTIN_SCUTSS: | |
8816 | case FRV_BUILTIN_IACCreadll: | |
8817 | case FRV_BUILTIN_IACCreadl: | |
8818 | case FRV_BUILTIN_IACCsetll: | |
8819 | case FRV_BUILTIN_IACCsetl: | |
8820 | if (!TARGET_FR405_BUILTINS) | |
8821 | { | |
8822 | error ("this builtin function is only available" | |
8823 | " on the fr405 and fr450"); | |
8824 | return NULL_RTX; | |
8825 | } | |
8826 | break; | |
8827 | ||
8828 | case FRV_BUILTIN_PREFETCH: | |
8829 | if (!TARGET_FR500_FR550_BUILTINS) | |
8830 | { | |
8831 | error ("this builtin function is only available on the fr500" | |
8832 | " and fr550"); | |
8833 | return NULL_RTX; | |
8834 | } | |
8835 | break; | |
8836 | ||
8837 | case FRV_BUILTIN_MQLCLRHS: | |
8838 | case FRV_BUILTIN_MQLMTHS: | |
8839 | case FRV_BUILTIN_MQSLLHI: | |
8840 | case FRV_BUILTIN_MQSRAHI: | |
8841 | if (!TARGET_MEDIA_FR450) | |
8842 | { | |
8843 | error ("this builtin function is only available on the fr450"); | |
36a05131 BS |
8844 | return NULL_RTX; |
8845 | } | |
8846 | break; | |
8847 | ||
8848 | default: | |
8849 | break; | |
8850 | } | |
8851 | ||
87b483a1 | 8852 | /* Expand unique builtins. */ |
36a05131 BS |
8853 | |
8854 | switch (fcode) | |
8855 | { | |
8856 | case FRV_BUILTIN_MTRAP: | |
8857 | return frv_expand_noargs_builtin (CODE_FOR_mtrap); | |
8858 | ||
8859 | case FRV_BUILTIN_MCLRACC: | |
8860 | return frv_expand_mclracc_builtin (arglist); | |
8861 | ||
8862 | case FRV_BUILTIN_MCLRACCA: | |
8863 | if (TARGET_ACC_8) | |
8864 | return frv_expand_noargs_builtin (CODE_FOR_mclracca8); | |
8865 | else | |
8866 | return frv_expand_noargs_builtin (CODE_FOR_mclracca4); | |
8867 | ||
8868 | case FRV_BUILTIN_MRDACC: | |
8869 | return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, arglist); | |
8870 | ||
8871 | case FRV_BUILTIN_MRDACCG: | |
8872 | return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, arglist); | |
8873 | ||
8874 | case FRV_BUILTIN_MWTACC: | |
8875 | return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, arglist); | |
8876 | ||
8877 | case FRV_BUILTIN_MWTACCG: | |
8878 | return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, arglist); | |
8879 | ||
a738d848 RS |
8880 | case FRV_BUILTIN_MDPACKH: |
8881 | return frv_expand_mdpackh_builtin (arglist, target); | |
8882 | ||
c557edf4 RS |
8883 | case FRV_BUILTIN_IACCreadll: |
8884 | { | |
8885 | rtx src = frv_read_iacc_argument (DImode, &arglist); | |
8886 | if (target == 0 || !REG_P (target)) | |
8887 | target = gen_reg_rtx (DImode); | |
8888 | frv_split_iacc_move (target, src); | |
8889 | return target; | |
8890 | } | |
8891 | ||
8892 | case FRV_BUILTIN_IACCreadl: | |
8893 | return frv_read_iacc_argument (SImode, &arglist); | |
8894 | ||
8895 | case FRV_BUILTIN_IACCsetll: | |
8896 | { | |
8897 | rtx dest = frv_read_iacc_argument (DImode, &arglist); | |
8898 | rtx src = frv_read_argument (&arglist); | |
8899 | frv_split_iacc_move (dest, force_reg (DImode, src)); | |
8900 | return 0; | |
8901 | } | |
8902 | ||
8903 | case FRV_BUILTIN_IACCsetl: | |
8904 | { | |
8905 | rtx dest = frv_read_iacc_argument (SImode, &arglist); | |
8906 | rtx src = frv_read_argument (&arglist); | |
8907 | emit_move_insn (dest, force_reg (SImode, src)); | |
8908 | return 0; | |
8909 | } | |
8910 | ||
36a05131 BS |
8911 | default: |
8912 | break; | |
8913 | } | |
8914 | ||
87b483a1 | 8915 | /* Expand groups of builtins. */ |
36a05131 | 8916 | |
e97a46ce | 8917 | for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++) |
36a05131 BS |
8918 | if (d->code == fcode) |
8919 | return frv_expand_set_builtin (d->icode, arglist, target); | |
8920 | ||
e97a46ce | 8921 | for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
36a05131 BS |
8922 | if (d->code == fcode) |
8923 | return frv_expand_unop_builtin (d->icode, arglist, target); | |
8924 | ||
e97a46ce | 8925 | for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
36a05131 BS |
8926 | if (d->code == fcode) |
8927 | return frv_expand_binop_builtin (d->icode, arglist, target); | |
8928 | ||
e97a46ce | 8929 | for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++) |
36a05131 BS |
8930 | if (d->code == fcode) |
8931 | return frv_expand_cut_builtin (d->icode, arglist, target); | |
8932 | ||
e97a46ce KG |
8933 | for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++) |
8934 | if (d->code == fcode) | |
8935 | return frv_expand_binopimm_builtin (d->icode, arglist, target); | |
36a05131 | 8936 | |
e97a46ce KG |
8937 | for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++) |
8938 | if (d->code == fcode) | |
8939 | return frv_expand_voidbinop_builtin (d->icode, arglist); | |
36a05131 | 8940 | |
e97a46ce KG |
8941 | for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++) |
8942 | if (d->code == fcode) | |
8943 | return frv_expand_voidtriop_builtin (d->icode, arglist); | |
8944 | ||
8945 | for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++) | |
8946 | if (d->code == fcode) | |
8947 | return frv_expand_voidaccop_builtin (d->icode, arglist); | |
36a05131 | 8948 | |
c557edf4 RS |
8949 | for (i = 0, d = bdesc_int_void2arg; |
8950 | i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++) | |
8951 | if (d->code == fcode) | |
8952 | return frv_expand_int_void2arg (d->icode, arglist); | |
8953 | ||
8954 | for (i = 0, d = bdesc_prefetches; | |
8955 | i < ARRAY_SIZE (bdesc_prefetches); i++, d++) | |
8956 | if (d->code == fcode) | |
8957 | return frv_expand_prefetches (d->icode, arglist); | |
8958 | ||
36a05131 BS |
8959 | return 0; |
8960 | } | |
14966b94 | 8961 | |
b3fbfc07 | 8962 | static bool |
f2206911 | 8963 | frv_in_small_data_p (tree decl) |
b3fbfc07 | 8964 | { |
0f6e5d45 RH |
8965 | HOST_WIDE_INT size; |
8966 | tree section_name; | |
8967 | ||
8968 | /* Don't apply the -G flag to internal compiler structures. We | |
8969 | should leave such structures in the main data section, partly | |
8970 | for efficiency and partly because the size of some of them | |
8971 | (such as C++ typeinfos) is not known until later. */ | |
8972 | if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl)) | |
8973 | return false; | |
8974 | ||
0f6e5d45 RH |
8975 | /* If we already know which section the decl should be in, see if |
8976 | it's a small data section. */ | |
8977 | section_name = DECL_SECTION_NAME (decl); | |
8978 | if (section_name) | |
8979 | { | |
44e91694 | 8980 | gcc_assert (TREE_CODE (section_name) == STRING_CST); |
0f6e5d45 RH |
8981 | if (frv_string_begins_with (section_name, ".sdata")) |
8982 | return true; | |
8983 | if (frv_string_begins_with (section_name, ".sbss")) | |
8984 | return true; | |
68c0ab4f | 8985 | return false; |
0f6e5d45 | 8986 | } |
b3fbfc07 | 8987 | |
68c0ab4f RS |
8988 | size = int_size_in_bytes (TREE_TYPE (decl)); |
8989 | if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value) | |
8990 | return true; | |
8991 | ||
0f6e5d45 | 8992 | return false; |
b3fbfc07 | 8993 | } |
3c50106f RH |
8994 | \f |
8995 | static bool | |
f2206911 KC |
8996 | frv_rtx_costs (rtx x, |
8997 | int code ATTRIBUTE_UNUSED, | |
8998 | int outer_code ATTRIBUTE_UNUSED, | |
8999 | int *total) | |
3c50106f | 9000 | { |
34208acf AO |
9001 | if (outer_code == MEM) |
9002 | { | |
9003 | /* Don't differentiate between memory addresses. All the ones | |
9004 | we accept have equal cost. */ | |
9005 | *total = COSTS_N_INSNS (0); | |
9006 | return true; | |
9007 | } | |
9008 | ||
3c50106f RH |
9009 | switch (code) |
9010 | { | |
9011 | case CONST_INT: | |
9012 | /* Make 12 bit integers really cheap. */ | |
9013 | if (IN_RANGE_P (INTVAL (x), -2048, 2047)) | |
9014 | { | |
9015 | *total = 0; | |
9016 | return true; | |
9017 | } | |
87b483a1 | 9018 | /* Fall through. */ |
3c50106f RH |
9019 | |
9020 | case CONST: | |
9021 | case LABEL_REF: | |
9022 | case SYMBOL_REF: | |
9023 | case CONST_DOUBLE: | |
9024 | *total = COSTS_N_INSNS (2); | |
9025 | return true; | |
9026 | ||
9027 | case PLUS: | |
9028 | case MINUS: | |
9029 | case AND: | |
9030 | case IOR: | |
9031 | case XOR: | |
9032 | case ASHIFT: | |
9033 | case ASHIFTRT: | |
9034 | case LSHIFTRT: | |
9035 | case NOT: | |
9036 | case NEG: | |
9037 | case COMPARE: | |
9038 | if (GET_MODE (x) == SImode) | |
9039 | *total = COSTS_N_INSNS (1); | |
9040 | else if (GET_MODE (x) == DImode) | |
9041 | *total = COSTS_N_INSNS (2); | |
9042 | else | |
9043 | *total = COSTS_N_INSNS (3); | |
9044 | return true; | |
9045 | ||
9046 | case MULT: | |
9047 | if (GET_MODE (x) == SImode) | |
9048 | *total = COSTS_N_INSNS (2); | |
9049 | else | |
9050 | *total = COSTS_N_INSNS (6); /* guess */ | |
9051 | return true; | |
9052 | ||
9053 | case DIV: | |
9054 | case UDIV: | |
9055 | case MOD: | |
9056 | case UMOD: | |
9057 | *total = COSTS_N_INSNS (18); | |
9058 | return true; | |
9059 | ||
34208acf AO |
9060 | case MEM: |
9061 | *total = COSTS_N_INSNS (3); | |
9062 | return true; | |
9063 | ||
3c50106f RH |
9064 | default: |
9065 | return false; | |
9066 | } | |
9067 | } | |
90a63880 RH |
9068 | \f |
9069 | static void | |
f2206911 | 9070 | frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED) |
90a63880 RH |
9071 | { |
9072 | ctors_section (); | |
9073 | assemble_align (POINTER_SIZE); | |
34208acf AO |
9074 | if (TARGET_FDPIC) |
9075 | { | |
44e91694 NS |
9076 | int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1); |
9077 | ||
9078 | gcc_assert (ok); | |
34208acf AO |
9079 | return; |
9080 | } | |
90a63880 RH |
9081 | assemble_integer_with_op ("\t.picptr\t", symbol); |
9082 | } | |
9083 | ||
9084 | static void | |
f2206911 | 9085 | frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED) |
90a63880 RH |
9086 | { |
9087 | dtors_section (); | |
9088 | assemble_align (POINTER_SIZE); | |
34208acf AO |
9089 | if (TARGET_FDPIC) |
9090 | { | |
44e91694 NS |
9091 | int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1); |
9092 | ||
9093 | gcc_assert (ok); | |
34208acf AO |
9094 | return; |
9095 | } | |
90a63880 RH |
9096 | assemble_integer_with_op ("\t.picptr\t", symbol); |
9097 | } | |
8ac411c7 KH |
9098 | |
9099 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ | |
9100 | ||
9101 | static rtx | |
9102 | frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
9103 | int incoming ATTRIBUTE_UNUSED) | |
9104 | { | |
9105 | return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM); | |
9106 | } | |
c557edf4 | 9107 | |
bef8809e AH |
9108 | #define TLS_BIAS (2048 - 16) |
9109 | ||
fdbe66f2 | 9110 | /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. |
bef8809e AH |
9111 | We need to emit DTP-relative relocations. */ |
9112 | ||
fdbe66f2 | 9113 | static void |
bef8809e AH |
9114 | frv_output_dwarf_dtprel (FILE *file, int size, rtx x) |
9115 | { | |
44e91694 | 9116 | gcc_assert (size == 4); |
bef8809e AH |
9117 | fputs ("\t.picptr\ttlsmoff(", file); |
9118 | /* We want the unbiased TLS offset, so add the bias to the | |
9119 | expression, such that the implicit biasing cancels out. */ | |
9120 | output_addr_const (file, plus_constant (x, TLS_BIAS)); | |
9121 | fputs (")", file); | |
9122 | } | |
9123 | ||
c557edf4 | 9124 | #include "gt-frv.h" |