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cbe34bb5 | 1 | /* Copyright (C) 1997-2017 Free Software Foundation, Inc. |
36a05131 BS |
2 | Contributed by Red Hat, Inc. |
3 | ||
7ec022b2 | 4 | This file is part of GCC. |
36a05131 | 5 | |
7ec022b2 | 6 | GCC is free software; you can redistribute it and/or modify |
36a05131 | 7 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
36a05131 BS |
9 | any later version. |
10 | ||
7ec022b2 | 11 | GCC is distributed in the hope that it will be useful, |
36a05131 BS |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
36a05131 BS |
19 | |
20 | #include "config.h" | |
21 | #include "system.h" | |
4977bab6 | 22 | #include "coretypes.h" |
c7131fb2 | 23 | #include "backend.h" |
e11c4407 | 24 | #include "target.h" |
c7131fb2 | 25 | #include "rtl.h" |
e11c4407 | 26 | #include "tree.h" |
c7131fb2 | 27 | #include "df.h" |
4d0cdd0c | 28 | #include "memmodel.h" |
e11c4407 AM |
29 | #include "tm_p.h" |
30 | #include "stringpool.h" | |
314e6352 | 31 | #include "attribs.h" |
e11c4407 AM |
32 | #include "optabs.h" |
33 | #include "regs.h" | |
34 | #include "emit-rtl.h" | |
35 | #include "recog.h" | |
36 | #include "diagnostic-core.h" | |
40e23961 | 37 | #include "fold-const.h" |
d8a2d370 DN |
38 | #include "varasm.h" |
39 | #include "stor-layout.h" | |
36a05131 BS |
40 | #include "output.h" |
41 | #include "insn-attr.h" | |
36566b39 | 42 | #include "explow.h" |
36a05131 | 43 | #include "expr.h" |
60393bbc | 44 | #include "cfgrtl.h" |
6e34d3a3 | 45 | #include "langhooks.h" |
7ee2468b | 46 | #include "dumpfile.h" |
9b2b7279 | 47 | #include "builtins.h" |
893479de | 48 | #include "ifcvt.h" |
cc665e56 | 49 | #include "rtl-iter.h" |
36a05131 | 50 | |
994c5d85 | 51 | /* This file should be included last. */ |
d58627a0 RS |
52 | #include "target-def.h" |
53 | ||
36a05131 BS |
54 | #ifndef FRV_INLINE |
55 | #define FRV_INLINE inline | |
56 | #endif | |
57 | ||
c557edf4 RS |
58 | /* The maximum number of distinct NOP patterns. There are three: |
59 | nop, fnop and mnop. */ | |
60 | #define NUM_NOP_PATTERNS 3 | |
61 | ||
62 | /* Classification of instructions and units: integer, floating-point/media, | |
63 | branch and control. */ | |
64 | enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS }; | |
65 | ||
66 | /* The DFA names of the units, in packet order. */ | |
67 | static const char *const frv_unit_names[] = | |
68 | { | |
69 | "c", | |
70 | "i0", "f0", | |
71 | "i1", "f1", | |
72 | "i2", "f2", | |
73 | "i3", "f3", | |
74 | "b0", "b1" | |
75 | }; | |
76 | ||
77 | /* The classification of each unit in frv_unit_names[]. */ | |
78 | static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] = | |
79 | { | |
80 | GROUP_C, | |
81 | GROUP_I, GROUP_FM, | |
82 | GROUP_I, GROUP_FM, | |
83 | GROUP_I, GROUP_FM, | |
84 | GROUP_I, GROUP_FM, | |
85 | GROUP_B, GROUP_B | |
86 | }; | |
87 | ||
88 | /* Return the DFA unit code associated with the Nth unit of integer | |
89 | or floating-point group GROUP, */ | |
90 | #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1] | |
91 | ||
92 | /* Return the number of integer or floating-point unit UNIT | |
93 | (1 for I1, 2 for F2, etc.). */ | |
94 | #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2) | |
95 | ||
96 | /* The DFA unit number for each unit in frv_unit_names[]. */ | |
97 | static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)]; | |
98 | ||
99 | /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue | |
100 | an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if | |
101 | no instruction of type T has been seen. */ | |
102 | static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1]; | |
103 | ||
104 | /* An array of dummy nop INSNs, one for each type of nop that the | |
105 | target supports. */ | |
e6eda746 | 106 | static GTY(()) rtx_insn *frv_nops[NUM_NOP_PATTERNS]; |
c557edf4 RS |
107 | |
108 | /* The number of nop instructions in frv_nops[]. */ | |
109 | static unsigned int frv_num_nops; | |
110 | ||
5c5e8419 JR |
111 | /* The type of access. FRV_IO_UNKNOWN means the access can be either |
112 | a read or a write. */ | |
113 | enum frv_io_type { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE }; | |
114 | ||
38c28a25 AH |
115 | /* Information about one __builtin_read or __builtin_write access, or |
116 | the combination of several such accesses. The most general value | |
117 | is all-zeros (an unknown access to an unknown address). */ | |
118 | struct frv_io { | |
5c5e8419 | 119 | enum frv_io_type type; |
38c28a25 AH |
120 | |
121 | /* The constant address being accessed, or zero if not known. */ | |
122 | HOST_WIDE_INT const_address; | |
123 | ||
124 | /* The run-time address, as used in operand 0 of the membar pattern. */ | |
125 | rtx var_address; | |
126 | }; | |
127 | ||
c557edf4 RS |
128 | /* Return true if instruction INSN should be packed with the following |
129 | instruction. */ | |
130 | #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode) | |
131 | ||
132 | /* Set the value of PACKING_FLAG_P(INSN). */ | |
133 | #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode) | |
134 | #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode) | |
135 | ||
136 | /* Loop with REG set to each hard register in rtx X. */ | |
137 | #define FOR_EACH_REGNO(REG, X) \ | |
036620db | 138 | for (REG = REGNO (X); REG < END_REGNO (X); REG++) |
c557edf4 | 139 | |
38c28a25 | 140 | /* This structure contains machine specific function data. */ |
d1b38208 | 141 | struct GTY(()) machine_function |
38c28a25 AH |
142 | { |
143 | /* True if we have created an rtx that relies on the stack frame. */ | |
144 | int frame_needed; | |
145 | ||
146 | /* True if this function contains at least one __builtin_{read,write}*. */ | |
147 | bool has_membar_p; | |
148 | }; | |
149 | ||
36a05131 BS |
150 | /* Temporary register allocation support structure. */ |
151 | typedef struct frv_tmp_reg_struct | |
152 | { | |
153 | HARD_REG_SET regs; /* possible registers to allocate */ | |
154 | int next_reg[N_REG_CLASSES]; /* next register to allocate per class */ | |
155 | } | |
156 | frv_tmp_reg_t; | |
157 | ||
c557edf4 | 158 | /* Register state information for VLIW re-packing phase. */ |
36a05131 | 159 | #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */ |
c557edf4 RS |
160 | #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */ |
161 | #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */ | |
162 | #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */ | |
163 | ||
36a05131 BS |
164 | #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE) |
165 | ||
c557edf4 | 166 | typedef unsigned char regstate_t; |
36a05131 BS |
167 | |
168 | /* Used in frv_frame_accessor_t to indicate the direction of a register-to- | |
169 | memory move. */ | |
170 | enum frv_stack_op | |
171 | { | |
172 | FRV_LOAD, | |
173 | FRV_STORE | |
174 | }; | |
175 | ||
176 | /* Information required by frv_frame_access. */ | |
177 | typedef struct | |
178 | { | |
179 | /* This field is FRV_LOAD if registers are to be loaded from the stack and | |
180 | FRV_STORE if they should be stored onto the stack. FRV_STORE implies | |
181 | the move is being done by the prologue code while FRV_LOAD implies it | |
182 | is being done by the epilogue. */ | |
183 | enum frv_stack_op op; | |
184 | ||
185 | /* The base register to use when accessing the stack. This may be the | |
186 | frame pointer, stack pointer, or a temporary. The choice of register | |
187 | depends on which part of the frame is being accessed and how big the | |
188 | frame is. */ | |
189 | rtx base; | |
190 | ||
191 | /* The offset of BASE from the bottom of the current frame, in bytes. */ | |
192 | int base_offset; | |
193 | } frv_frame_accessor_t; | |
194 | ||
87b483a1 | 195 | /* Conditional execution support gathered together in one structure. */ |
36a05131 BS |
196 | typedef struct |
197 | { | |
198 | /* Linked list of insns to add if the conditional execution conversion was | |
199 | successful. Each link points to an EXPR_LIST which points to the pattern | |
200 | of the insn to add, and the insn to be inserted before. */ | |
201 | rtx added_insns_list; | |
202 | ||
203 | /* Identify which registers are safe to allocate for if conversions to | |
204 | conditional execution. We keep the last allocated register in the | |
205 | register classes between COND_EXEC statements. This will mean we allocate | |
206 | different registers for each different COND_EXEC group if we can. This | |
207 | might allow the scheduler to intermix two different COND_EXEC sections. */ | |
208 | frv_tmp_reg_t tmp_reg; | |
209 | ||
210 | /* For nested IFs, identify which CC registers are used outside of setting | |
211 | via a compare isnsn, and using via a check insn. This will allow us to | |
212 | know if we can rewrite the register to use a different register that will | |
213 | be paired with the CR register controlling the nested IF-THEN blocks. */ | |
214 | HARD_REG_SET nested_cc_ok_rewrite; | |
215 | ||
216 | /* Temporary registers allocated to hold constants during conditional | |
217 | execution. */ | |
218 | rtx scratch_regs[FIRST_PSEUDO_REGISTER]; | |
219 | ||
220 | /* Current number of temp registers available. */ | |
221 | int cur_scratch_regs; | |
222 | ||
87b483a1 | 223 | /* Number of nested conditional execution blocks. */ |
36a05131 BS |
224 | int num_nested_cond_exec; |
225 | ||
226 | /* Map of insns that set up constants in scratch registers. */ | |
227 | bitmap scratch_insns_bitmap; | |
228 | ||
87b483a1 | 229 | /* Conditional execution test register (CC0..CC7). */ |
36a05131 BS |
230 | rtx cr_reg; |
231 | ||
232 | /* Conditional execution compare register that is paired with cr_reg, so that | |
233 | nested compares can be done. The csubcc and caddcc instructions don't | |
234 | have enough bits to specify both a CC register to be set and a CR register | |
235 | to do the test on, so the same bit number is used for both. Needless to | |
839a4992 | 236 | say, this is rather inconvenient for GCC. */ |
36a05131 BS |
237 | rtx nested_cc_reg; |
238 | ||
239 | /* Extra CR registers used for &&, ||. */ | |
240 | rtx extra_int_cr; | |
241 | rtx extra_fp_cr; | |
242 | ||
243 | /* Previous CR used in nested if, to make sure we are dealing with the same | |
87b483a1 | 244 | nested if as the previous statement. */ |
36a05131 BS |
245 | rtx last_nested_if_cr; |
246 | } | |
247 | frv_ifcvt_t; | |
248 | ||
249 | static /* GTY(()) */ frv_ifcvt_t frv_ifcvt; | |
250 | ||
251 | /* Map register number to smallest register class. */ | |
252 | enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; | |
253 | ||
87b483a1 | 254 | /* Cached value of frv_stack_info. */ |
36a05131 BS |
255 | static frv_stack_t *frv_stack_cache = (frv_stack_t *)0; |
256 | ||
36a05131 | 257 | /* Forward references */ |
0b2c18fe | 258 | |
c5387660 | 259 | static void frv_option_override (void); |
ef4bddc2 | 260 | static bool frv_legitimate_address_p (machine_mode, rtx, bool); |
f2206911 | 261 | static int frv_default_flags_for_cpu (void); |
f961457f | 262 | static int frv_string_begins_with (const char *, const char *); |
34208acf | 263 | static FRV_INLINE bool frv_small_data_reloc_p (rtx, int); |
0fb30cb7 | 264 | static void frv_print_operand (FILE *, rtx, int); |
cc8ca59e | 265 | static void frv_print_operand_address (FILE *, machine_mode, rtx); |
0fb30cb7 | 266 | static bool frv_print_operand_punct_valid_p (unsigned char code); |
36a05131 | 267 | static void frv_print_operand_memory_reference_reg |
f2206911 KC |
268 | (FILE *, rtx); |
269 | static void frv_print_operand_memory_reference (FILE *, rtx, int); | |
68a1a6c0 | 270 | static int frv_print_operand_jump_hint (rtx_insn *); |
036ff63f | 271 | static const char *comparison_string (enum rtx_code, rtx); |
219d92a4 AS |
272 | static rtx frv_function_value (const_tree, const_tree, |
273 | bool); | |
ef4bddc2 | 274 | static rtx frv_libcall_value (machine_mode, |
219d92a4 | 275 | const_rtx); |
f2206911 KC |
276 | static FRV_INLINE int frv_regno_ok_for_base_p (int, int); |
277 | static rtx single_set_pattern (rtx); | |
278 | static int frv_function_contains_far_jump (void); | |
279 | static rtx frv_alloc_temp_reg (frv_tmp_reg_t *, | |
280 | enum reg_class, | |
ef4bddc2 | 281 | machine_mode, |
f2206911 KC |
282 | int, int); |
283 | static rtx frv_frame_offset_rtx (int); | |
ef4bddc2 | 284 | static rtx frv_frame_mem (machine_mode, rtx, int); |
f2206911 KC |
285 | static rtx frv_dwarf_store (rtx, int); |
286 | static void frv_frame_insn (rtx, rtx); | |
287 | static void frv_frame_access (frv_frame_accessor_t*, | |
288 | rtx, int); | |
289 | static void frv_frame_access_multi (frv_frame_accessor_t*, | |
290 | frv_stack_t *, int); | |
291 | static void frv_frame_access_standard_regs (enum frv_stack_op, | |
292 | frv_stack_t *); | |
293 | static struct machine_function *frv_init_machine_status (void); | |
f2206911 | 294 | static rtx frv_int_to_acc (enum insn_code, int, rtx); |
ef4bddc2 | 295 | static machine_mode frv_matching_accg_mode (machine_mode); |
2396bce1 | 296 | static rtx frv_read_argument (tree, unsigned int); |
ef4bddc2 | 297 | static rtx frv_read_iacc_argument (machine_mode, tree, unsigned int); |
f2206911 KC |
298 | static int frv_check_constant_argument (enum insn_code, int, rtx); |
299 | static rtx frv_legitimize_target (enum insn_code, rtx); | |
300 | static rtx frv_legitimize_argument (enum insn_code, int, rtx); | |
bef8809e | 301 | static rtx frv_legitimize_tls_address (rtx, enum tls_model); |
ef4bddc2 | 302 | static rtx frv_legitimize_address (rtx, rtx, machine_mode); |
f2206911 KC |
303 | static rtx frv_expand_set_builtin (enum insn_code, tree, rtx); |
304 | static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx); | |
305 | static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx); | |
306 | static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx); | |
307 | static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx); | |
308 | static rtx frv_expand_voidbinop_builtin (enum insn_code, tree); | |
c557edf4 RS |
309 | static rtx frv_expand_int_void2arg (enum insn_code, tree); |
310 | static rtx frv_expand_prefetches (enum insn_code, tree); | |
f2206911 KC |
311 | static rtx frv_expand_voidtriop_builtin (enum insn_code, tree); |
312 | static rtx frv_expand_voidaccop_builtin (enum insn_code, tree); | |
313 | static rtx frv_expand_mclracc_builtin (tree); | |
314 | static rtx frv_expand_mrdacc_builtin (enum insn_code, tree); | |
315 | static rtx frv_expand_mwtacc_builtin (enum insn_code, tree); | |
316 | static rtx frv_expand_noargs_builtin (enum insn_code); | |
c557edf4 | 317 | static void frv_split_iacc_move (rtx, rtx); |
f2206911 | 318 | static rtx frv_emit_comparison (enum rtx_code, rtx, rtx); |
f2206911 | 319 | static void frv_ifcvt_add_insn (rtx, rtx, int); |
ef4bddc2 | 320 | static rtx frv_ifcvt_rewrite_mem (rtx, machine_mode, rtx); |
f2206911 | 321 | static rtx frv_ifcvt_load_value (rtx, rtx); |
84034c69 DM |
322 | static unsigned int frv_insn_unit (rtx_insn *); |
323 | static bool frv_issues_to_branch_unit_p (rtx_insn *); | |
c557edf4 RS |
324 | static int frv_cond_flags (rtx); |
325 | static bool frv_regstate_conflict_p (regstate_t, regstate_t); | |
c557edf4 | 326 | static bool frv_registers_conflict_p (rtx); |
7bc980e1 | 327 | static void frv_registers_update_1 (rtx, const_rtx, void *); |
c557edf4 RS |
328 | static void frv_registers_update (rtx); |
329 | static void frv_start_packet (void); | |
330 | static void frv_start_packet_block (void); | |
331 | static void frv_finish_packet (void (*) (void)); | |
84034c69 | 332 | static bool frv_pack_insn_p (rtx_insn *); |
b32d5189 DM |
333 | static void frv_add_insn_to_packet (rtx_insn *); |
334 | static void frv_insert_nop_in_packet (rtx_insn *); | |
c557edf4 RS |
335 | static bool frv_for_each_packet (void (*) (void)); |
336 | static bool frv_sort_insn_group_1 (enum frv_insn_group, | |
337 | unsigned int, unsigned int, | |
338 | unsigned int, unsigned int, | |
339 | state_t); | |
340 | static int frv_compare_insns (const void *, const void *); | |
341 | static void frv_sort_insn_group (enum frv_insn_group); | |
342 | static void frv_reorder_packet (void); | |
343 | static void frv_fill_unused_units (enum frv_insn_group); | |
344 | static void frv_align_label (void); | |
345 | static void frv_reorg_packet (void); | |
346 | static void frv_register_nop (rtx); | |
347 | static void frv_reorg (void); | |
f2206911 | 348 | static void frv_pack_insns (void); |
42776416 RS |
349 | static void frv_function_prologue (FILE *); |
350 | static void frv_function_epilogue (FILE *); | |
f2206911 KC |
351 | static bool frv_assemble_integer (rtx, unsigned, int); |
352 | static void frv_init_builtins (void); | |
ef4bddc2 | 353 | static rtx frv_expand_builtin (tree, rtx, rtx, machine_mode, int); |
f2206911 | 354 | static void frv_init_libfuncs (void); |
3101faab | 355 | static bool frv_in_small_data_p (const_tree); |
3961e8fe | 356 | static void frv_asm_output_mi_thunk |
f2206911 | 357 | (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree); |
d5cc9181 | 358 | static void frv_setup_incoming_varargs (cumulative_args_t, |
ef4bddc2 | 359 | machine_mode, |
d8c2bed3 | 360 | tree, int *, int); |
8ac411c7 | 361 | static rtx frv_expand_builtin_saveregs (void); |
d7bd8aeb | 362 | static void frv_expand_builtin_va_start (tree, rtx); |
e548c9df AM |
363 | static bool frv_rtx_costs (rtx, machine_mode, int, int, |
364 | int*, bool); | |
ef4bddc2 | 365 | static int frv_register_move_cost (machine_mode, |
33124e84 | 366 | reg_class_t, reg_class_t); |
ef4bddc2 | 367 | static int frv_memory_move_cost (machine_mode, |
33124e84 | 368 | reg_class_t, bool); |
f2206911 KC |
369 | static void frv_asm_out_constructor (rtx, int); |
370 | static void frv_asm_out_destructor (rtx, int); | |
34208acf | 371 | static bool frv_function_symbol_referenced_p (rtx); |
ef4bddc2 RS |
372 | static bool frv_legitimate_constant_p (machine_mode, rtx); |
373 | static bool frv_cannot_force_const_mem (machine_mode, rtx); | |
34208acf AO |
374 | static const char *unspec_got_name (int); |
375 | static void frv_output_const_unspec (FILE *, | |
376 | const struct frv_unspec *); | |
764678d1 | 377 | static bool frv_function_ok_for_sibcall (tree, tree); |
8ac411c7 | 378 | static rtx frv_struct_value_rtx (tree, int); |
ef4bddc2 RS |
379 | static bool frv_must_pass_in_stack (machine_mode mode, const_tree type); |
380 | static int frv_arg_partial_bytes (cumulative_args_t, machine_mode, | |
78a52f11 | 381 | tree, bool); |
ef4bddc2 | 382 | static rtx frv_function_arg (cumulative_args_t, machine_mode, |
88a1f47f | 383 | const_tree, bool); |
ef4bddc2 | 384 | static rtx frv_function_incoming_arg (cumulative_args_t, machine_mode, |
88a1f47f | 385 | const_tree, bool); |
ef4bddc2 | 386 | static void frv_function_arg_advance (cumulative_args_t, machine_mode, |
88a1f47f | 387 | const_tree, bool); |
ef4bddc2 | 388 | static unsigned int frv_function_arg_boundary (machine_mode, |
c2ed6cf8 | 389 | const_tree); |
fdbe66f2 EB |
390 | static void frv_output_dwarf_dtprel (FILE *, int, rtx) |
391 | ATTRIBUTE_UNUSED; | |
a87cf97e | 392 | static reg_class_t frv_secondary_reload (bool, rtx, reg_class_t, |
ef4bddc2 | 393 | machine_mode, |
35f2d8ef | 394 | secondary_reload_info *); |
b52b1749 | 395 | static bool frv_frame_pointer_required (void); |
7b5cbb57 | 396 | static bool frv_can_eliminate (const int, const int); |
5efd84c5 | 397 | static void frv_conditional_register_usage (void); |
e9d5fdb2 | 398 | static void frv_trampoline_init (rtx, tree, rtx); |
c28350ab | 399 | static bool frv_class_likely_spilled_p (reg_class_t); |
f939c3e6 | 400 | static bool frv_hard_regno_mode_ok (unsigned int, machine_mode); |
99e1629f | 401 | static bool frv_modes_tieable_p (machine_mode, machine_mode); |
0b2c18fe | 402 | \f |
36a05131 | 403 | /* Initialize the GCC target structure. */ |
0fb30cb7 NF |
404 | #undef TARGET_PRINT_OPERAND |
405 | #define TARGET_PRINT_OPERAND frv_print_operand | |
406 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
407 | #define TARGET_PRINT_OPERAND_ADDRESS frv_print_operand_address | |
408 | #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P | |
409 | #define TARGET_PRINT_OPERAND_PUNCT_VALID_P frv_print_operand_punct_valid_p | |
36a05131 BS |
410 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
411 | #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue | |
412 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
413 | #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue | |
414 | #undef TARGET_ASM_INTEGER | |
415 | #define TARGET_ASM_INTEGER frv_assemble_integer | |
c5387660 JM |
416 | #undef TARGET_OPTION_OVERRIDE |
417 | #define TARGET_OPTION_OVERRIDE frv_option_override | |
14966b94 KG |
418 | #undef TARGET_INIT_BUILTINS |
419 | #define TARGET_INIT_BUILTINS frv_init_builtins | |
420 | #undef TARGET_EXPAND_BUILTIN | |
421 | #define TARGET_EXPAND_BUILTIN frv_expand_builtin | |
c15c90bb ZW |
422 | #undef TARGET_INIT_LIBFUNCS |
423 | #define TARGET_INIT_LIBFUNCS frv_init_libfuncs | |
b3fbfc07 KG |
424 | #undef TARGET_IN_SMALL_DATA_P |
425 | #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p | |
33124e84 AS |
426 | #undef TARGET_REGISTER_MOVE_COST |
427 | #define TARGET_REGISTER_MOVE_COST frv_register_move_cost | |
428 | #undef TARGET_MEMORY_MOVE_COST | |
429 | #define TARGET_MEMORY_MOVE_COST frv_memory_move_cost | |
3c50106f RH |
430 | #undef TARGET_RTX_COSTS |
431 | #define TARGET_RTX_COSTS frv_rtx_costs | |
90a63880 RH |
432 | #undef TARGET_ASM_CONSTRUCTOR |
433 | #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor | |
434 | #undef TARGET_ASM_DESTRUCTOR | |
435 | #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor | |
36a05131 | 436 | |
c590b625 RH |
437 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
438 | #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk | |
3961e8fe RH |
439 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
440 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
c590b625 | 441 | |
28a60850 RS |
442 | #undef TARGET_SCHED_ISSUE_RATE |
443 | #define TARGET_SCHED_ISSUE_RATE frv_issue_rate | |
ffb344c1 | 444 | |
506d7b68 PB |
445 | #undef TARGET_LEGITIMIZE_ADDRESS |
446 | #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address | |
447 | ||
764678d1 AO |
448 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
449 | #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall | |
1a627b35 RS |
450 | #undef TARGET_LEGITIMATE_CONSTANT_P |
451 | #define TARGET_LEGITIMATE_CONSTANT_P frv_legitimate_constant_p | |
34208acf AO |
452 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
453 | #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem | |
454 | ||
bef8809e AH |
455 | #undef TARGET_HAVE_TLS |
456 | #define TARGET_HAVE_TLS HAVE_AS_TLS | |
457 | ||
8ac411c7 KH |
458 | #undef TARGET_STRUCT_VALUE_RTX |
459 | #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx | |
fe984136 RH |
460 | #undef TARGET_MUST_PASS_IN_STACK |
461 | #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack | |
8cd5a4e0 RH |
462 | #undef TARGET_PASS_BY_REFERENCE |
463 | #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack | |
78a52f11 RH |
464 | #undef TARGET_ARG_PARTIAL_BYTES |
465 | #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes | |
88a1f47f NF |
466 | #undef TARGET_FUNCTION_ARG |
467 | #define TARGET_FUNCTION_ARG frv_function_arg | |
468 | #undef TARGET_FUNCTION_INCOMING_ARG | |
469 | #define TARGET_FUNCTION_INCOMING_ARG frv_function_incoming_arg | |
470 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
471 | #define TARGET_FUNCTION_ARG_ADVANCE frv_function_arg_advance | |
c2ed6cf8 NF |
472 | #undef TARGET_FUNCTION_ARG_BOUNDARY |
473 | #define TARGET_FUNCTION_ARG_BOUNDARY frv_function_arg_boundary | |
8ac411c7 KH |
474 | |
475 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
476 | #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs | |
d8c2bed3 KH |
477 | #undef TARGET_SETUP_INCOMING_VARARGS |
478 | #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs | |
c557edf4 RS |
479 | #undef TARGET_MACHINE_DEPENDENT_REORG |
480 | #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg | |
8ac411c7 | 481 | |
d7bd8aeb JJ |
482 | #undef TARGET_EXPAND_BUILTIN_VA_START |
483 | #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start | |
484 | ||
fdbe66f2 EB |
485 | #if HAVE_AS_TLS |
486 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
487 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel | |
488 | #endif | |
489 | ||
c28350ab AS |
490 | #undef TARGET_CLASS_LIKELY_SPILLED_P |
491 | #define TARGET_CLASS_LIKELY_SPILLED_P frv_class_likely_spilled_p | |
492 | ||
35f2d8ef NC |
493 | #undef TARGET_SECONDARY_RELOAD |
494 | #define TARGET_SECONDARY_RELOAD frv_secondary_reload | |
495 | ||
d81db636 SB |
496 | #undef TARGET_LRA_P |
497 | #define TARGET_LRA_P hook_bool_void_false | |
498 | ||
c6c3dba9 PB |
499 | #undef TARGET_LEGITIMATE_ADDRESS_P |
500 | #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p | |
501 | ||
b52b1749 AS |
502 | #undef TARGET_FRAME_POINTER_REQUIRED |
503 | #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required | |
504 | ||
7b5cbb57 AS |
505 | #undef TARGET_CAN_ELIMINATE |
506 | #define TARGET_CAN_ELIMINATE frv_can_eliminate | |
507 | ||
5efd84c5 NF |
508 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
509 | #define TARGET_CONDITIONAL_REGISTER_USAGE frv_conditional_register_usage | |
510 | ||
e9d5fdb2 RH |
511 | #undef TARGET_TRAMPOLINE_INIT |
512 | #define TARGET_TRAMPOLINE_INIT frv_trampoline_init | |
513 | ||
219d92a4 AS |
514 | #undef TARGET_FUNCTION_VALUE |
515 | #define TARGET_FUNCTION_VALUE frv_function_value | |
516 | #undef TARGET_LIBCALL_VALUE | |
517 | #define TARGET_LIBCALL_VALUE frv_libcall_value | |
518 | ||
f939c3e6 RS |
519 | #undef TARGET_HARD_REGNO_MODE_OK |
520 | #define TARGET_HARD_REGNO_MODE_OK frv_hard_regno_mode_ok | |
99e1629f RS |
521 | #undef TARGET_MODES_TIEABLE_P |
522 | #define TARGET_MODES_TIEABLE_P frv_modes_tieable_p | |
f939c3e6 | 523 | |
36a05131 | 524 | struct gcc_target targetm = TARGET_INITIALIZER; |
bef8809e AH |
525 | |
526 | #define FRV_SYMBOL_REF_TLS_P(RTX) \ | |
527 | (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) | |
528 | ||
36a05131 | 529 | \f |
764678d1 AO |
530 | /* Any function call that satisfies the machine-independent |
531 | requirements is eligible on FR-V. */ | |
532 | ||
533 | static bool | |
534 | frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED, | |
535 | tree exp ATTRIBUTE_UNUSED) | |
536 | { | |
537 | return true; | |
538 | } | |
539 | ||
34208acf AO |
540 | /* Return true if SYMBOL is a small data symbol and relocation RELOC |
541 | can be used to access it directly in a load or store. */ | |
36a05131 | 542 | |
34208acf AO |
543 | static FRV_INLINE bool |
544 | frv_small_data_reloc_p (rtx symbol, int reloc) | |
36a05131 | 545 | { |
34208acf AO |
546 | return (GET_CODE (symbol) == SYMBOL_REF |
547 | && SYMBOL_REF_SMALL_P (symbol) | |
548 | && (!TARGET_FDPIC || flag_pic == 1) | |
549 | && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12)); | |
550 | } | |
36a05131 | 551 | |
34208acf AO |
552 | /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC |
553 | appropriately. */ | |
36a05131 | 554 | |
6d26dc3b | 555 | bool |
34208acf AO |
556 | frv_const_unspec_p (rtx x, struct frv_unspec *unspec) |
557 | { | |
558 | if (GET_CODE (x) == CONST) | |
559 | { | |
560 | unspec->offset = 0; | |
561 | x = XEXP (x, 0); | |
562 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
563 | { | |
564 | unspec->offset += INTVAL (XEXP (x, 1)); | |
565 | x = XEXP (x, 0); | |
566 | } | |
567 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT) | |
568 | { | |
569 | unspec->symbol = XVECEXP (x, 0, 0); | |
570 | unspec->reloc = INTVAL (XVECEXP (x, 0, 1)); | |
36a05131 | 571 | |
34208acf AO |
572 | if (unspec->offset == 0) |
573 | return true; | |
36a05131 | 574 | |
34208acf AO |
575 | if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc) |
576 | && unspec->offset > 0 | |
fa37ed29 | 577 | && unspec->offset < g_switch_value) |
34208acf AO |
578 | return true; |
579 | } | |
580 | } | |
581 | return false; | |
36a05131 BS |
582 | } |
583 | ||
34208acf AO |
584 | /* Decide whether we can force certain constants to memory. If we |
585 | decide we can't, the caller should be able to cope with it in | |
586 | another way. | |
36a05131 | 587 | |
34208acf AO |
588 | We never allow constants to be forced into memory for TARGET_FDPIC. |
589 | This is necessary for several reasons: | |
36a05131 | 590 | |
1a627b35 | 591 | 1. Since frv_legitimate_constant_p rejects constant pool addresses, the |
34208acf AO |
592 | target-independent code will try to force them into the constant |
593 | pool, thus leading to infinite recursion. | |
36a05131 | 594 | |
34208acf AO |
595 | 2. We can never introduce new constant pool references during reload. |
596 | Any such reference would require use of the pseudo FDPIC register. | |
36a05131 | 597 | |
34208acf AO |
598 | 3. We can't represent a constant added to a function pointer (which is |
599 | not the same as a pointer to a function+constant). | |
600 | ||
601 | 4. In many cases, it's more efficient to calculate the constant in-line. */ | |
602 | ||
603 | static bool | |
ef4bddc2 | 604 | frv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, |
fbbf66e7 | 605 | rtx x ATTRIBUTE_UNUSED) |
34208acf AO |
606 | { |
607 | return TARGET_FDPIC; | |
608 | } | |
36a05131 BS |
609 | \f |
610 | static int | |
f2206911 | 611 | frv_default_flags_for_cpu (void) |
36a05131 BS |
612 | { |
613 | switch (frv_cpu_type) | |
614 | { | |
615 | case FRV_CPU_GENERIC: | |
616 | return MASK_DEFAULT_FRV; | |
617 | ||
c557edf4 RS |
618 | case FRV_CPU_FR550: |
619 | return MASK_DEFAULT_FR550; | |
620 | ||
36a05131 BS |
621 | case FRV_CPU_FR500: |
622 | case FRV_CPU_TOMCAT: | |
623 | return MASK_DEFAULT_FR500; | |
624 | ||
c557edf4 RS |
625 | case FRV_CPU_FR450: |
626 | return MASK_DEFAULT_FR450; | |
627 | ||
628 | case FRV_CPU_FR405: | |
36a05131 BS |
629 | case FRV_CPU_FR400: |
630 | return MASK_DEFAULT_FR400; | |
631 | ||
632 | case FRV_CPU_FR300: | |
633 | case FRV_CPU_SIMPLE: | |
634 | return MASK_DEFAULT_SIMPLE; | |
44e91694 NS |
635 | |
636 | default: | |
637 | gcc_unreachable (); | |
36a05131 | 638 | } |
36a05131 BS |
639 | } |
640 | ||
c5387660 | 641 | /* Implement TARGET_OPTION_OVERRIDE. */ |
36a05131 | 642 | |
c5387660 JM |
643 | static void |
644 | frv_option_override (void) | |
36a05131 | 645 | { |
c557edf4 RS |
646 | int regno; |
647 | unsigned int i; | |
36a05131 | 648 | |
36a05131 BS |
649 | target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit); |
650 | ||
651 | /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the | |
652 | linker about linking pic and non-pic code. */ | |
653 | if (TARGET_LIBPIC) | |
654 | { | |
655 | if (!flag_pic) /* -fPIC */ | |
656 | flag_pic = 2; | |
657 | ||
fa37ed29 | 658 | if (!global_options_set.x_g_switch_value) /* -G0 */ |
36a05131 | 659 | { |
36a05131 BS |
660 | g_switch_value = 0; |
661 | } | |
662 | } | |
663 | ||
36a05131 BS |
664 | /* A C expression whose value is a register class containing hard |
665 | register REGNO. In general there is more than one such class; | |
666 | choose a class which is "minimal", meaning that no smaller class | |
87b483a1 | 667 | also contains the register. */ |
36a05131 BS |
668 | |
669 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
670 | { | |
0a2aaacc | 671 | enum reg_class rclass; |
36a05131 BS |
672 | |
673 | if (GPR_P (regno)) | |
674 | { | |
675 | int gpr_reg = regno - GPR_FIRST; | |
bef8809e AH |
676 | |
677 | if (gpr_reg == GR8_REG) | |
0a2aaacc | 678 | rclass = GR8_REGS; |
bef8809e AH |
679 | |
680 | else if (gpr_reg == GR9_REG) | |
0a2aaacc | 681 | rclass = GR9_REGS; |
bef8809e AH |
682 | |
683 | else if (gpr_reg == GR14_REG) | |
0a2aaacc | 684 | rclass = FDPIC_FPTR_REGS; |
bef8809e AH |
685 | |
686 | else if (gpr_reg == FDPIC_REGNO) | |
0a2aaacc | 687 | rclass = FDPIC_REGS; |
bef8809e AH |
688 | |
689 | else if ((gpr_reg & 3) == 0) | |
0a2aaacc | 690 | rclass = QUAD_REGS; |
36a05131 BS |
691 | |
692 | else if ((gpr_reg & 1) == 0) | |
0a2aaacc | 693 | rclass = EVEN_REGS; |
36a05131 BS |
694 | |
695 | else | |
0a2aaacc | 696 | rclass = GPR_REGS; |
36a05131 BS |
697 | } |
698 | ||
699 | else if (FPR_P (regno)) | |
700 | { | |
701 | int fpr_reg = regno - GPR_FIRST; | |
702 | if ((fpr_reg & 3) == 0) | |
0a2aaacc | 703 | rclass = QUAD_FPR_REGS; |
36a05131 BS |
704 | |
705 | else if ((fpr_reg & 1) == 0) | |
0a2aaacc | 706 | rclass = FEVEN_REGS; |
36a05131 BS |
707 | |
708 | else | |
0a2aaacc | 709 | rclass = FPR_REGS; |
36a05131 BS |
710 | } |
711 | ||
712 | else if (regno == LR_REGNO) | |
0a2aaacc | 713 | rclass = LR_REG; |
36a05131 BS |
714 | |
715 | else if (regno == LCR_REGNO) | |
0a2aaacc | 716 | rclass = LCR_REG; |
36a05131 BS |
717 | |
718 | else if (ICC_P (regno)) | |
0a2aaacc | 719 | rclass = ICC_REGS; |
36a05131 BS |
720 | |
721 | else if (FCC_P (regno)) | |
0a2aaacc | 722 | rclass = FCC_REGS; |
36a05131 BS |
723 | |
724 | else if (ICR_P (regno)) | |
0a2aaacc | 725 | rclass = ICR_REGS; |
36a05131 BS |
726 | |
727 | else if (FCR_P (regno)) | |
0a2aaacc | 728 | rclass = FCR_REGS; |
36a05131 BS |
729 | |
730 | else if (ACC_P (regno)) | |
731 | { | |
732 | int r = regno - ACC_FIRST; | |
733 | if ((r & 3) == 0) | |
0a2aaacc | 734 | rclass = QUAD_ACC_REGS; |
36a05131 | 735 | else if ((r & 1) == 0) |
0a2aaacc | 736 | rclass = EVEN_ACC_REGS; |
36a05131 | 737 | else |
0a2aaacc | 738 | rclass = ACC_REGS; |
36a05131 BS |
739 | } |
740 | ||
741 | else if (ACCG_P (regno)) | |
0a2aaacc | 742 | rclass = ACCG_REGS; |
36a05131 BS |
743 | |
744 | else | |
0a2aaacc | 745 | rclass = NO_REGS; |
36a05131 | 746 | |
0a2aaacc | 747 | regno_reg_class[regno] = rclass; |
36a05131 BS |
748 | } |
749 | ||
750 | /* Check for small data option */ | |
fa37ed29 | 751 | if (!global_options_set.x_g_switch_value && !TARGET_LIBPIC) |
36a05131 BS |
752 | g_switch_value = SDATA_DEFAULT_SIZE; |
753 | ||
36a05131 BS |
754 | /* There is no single unaligned SI op for PIC code. Sometimes we |
755 | need to use ".4byte" and sometimes we need to use ".picptr". | |
756 | See frv_assemble_integer for details. */ | |
34208acf | 757 | if (flag_pic || TARGET_FDPIC) |
36a05131 BS |
758 | targetm.asm_out.unaligned_op.si = 0; |
759 | ||
34208acf AO |
760 | if ((target_flags_explicit & MASK_LINKED_FP) == 0) |
761 | target_flags |= MASK_LINKED_FP; | |
762 | ||
38c28a25 AH |
763 | if ((target_flags_explicit & MASK_OPTIMIZE_MEMBAR) == 0) |
764 | target_flags |= MASK_OPTIMIZE_MEMBAR; | |
765 | ||
c557edf4 RS |
766 | for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++) |
767 | frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]); | |
768 | ||
769 | for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++) | |
770 | frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes); | |
771 | ||
36a05131 BS |
772 | init_machine_status = frv_init_machine_status; |
773 | } | |
774 | ||
36a05131 BS |
775 | \f |
776 | /* Return true if NAME (a STRING_CST node) begins with PREFIX. */ | |
777 | ||
778 | static int | |
f961457f | 779 | frv_string_begins_with (const char *name, const char *prefix) |
36a05131 | 780 | { |
3101faab | 781 | const int prefix_len = strlen (prefix); |
36a05131 BS |
782 | |
783 | /* Remember: NAME's length includes the null terminator. */ | |
f961457f | 784 | return (strncmp (name, prefix, prefix_len) == 0); |
36a05131 | 785 | } |
36a05131 | 786 | \f |
b48e9677 | 787 | /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */ |
36a05131 | 788 | |
5efd84c5 | 789 | static void |
f2206911 | 790 | frv_conditional_register_usage (void) |
36a05131 BS |
791 | { |
792 | int i; | |
793 | ||
794 | for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++) | |
795 | fixed_regs[i] = call_used_regs[i] = 1; | |
796 | ||
797 | for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++) | |
798 | fixed_regs[i] = call_used_regs[i] = 1; | |
799 | ||
36a05131 BS |
800 | /* Reserve the registers used for conditional execution. At present, we need |
801 | 1 ICC and 1 ICR register. */ | |
802 | fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1; | |
803 | fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1; | |
804 | ||
805 | if (TARGET_FIXED_CC) | |
806 | { | |
807 | fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1; | |
808 | fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1; | |
809 | fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1; | |
810 | fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1; | |
811 | } | |
812 | ||
34208acf AO |
813 | if (TARGET_FDPIC) |
814 | fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] = | |
815 | call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0; | |
816 | ||
36a05131 BS |
817 | #if 0 |
818 | /* If -fpic, SDA_BASE_REG is the PIC register. */ | |
819 | if (g_switch_value == 0 && !flag_pic) | |
820 | fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0; | |
821 | ||
822 | if (!flag_pic) | |
823 | fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0; | |
824 | #endif | |
825 | } | |
826 | ||
827 | \f | |
828 | /* | |
829 | * Compute the stack frame layout | |
830 | * | |
831 | * Register setup: | |
832 | * +---------------+-----------------------+-----------------------+ | |
833 | * |Register |type |caller-save/callee-save| | |
834 | * +---------------+-----------------------+-----------------------+ | |
835 | * |GR0 |Zero register | - | | |
836 | * |GR1 |Stack pointer(SP) | - | | |
837 | * |GR2 |Frame pointer(FP) | - | | |
838 | * |GR3 |Hidden parameter | caller save | | |
839 | * |GR4-GR7 | - | caller save | | |
840 | * |GR8-GR13 |Argument register | caller save | | |
841 | * |GR14-GR15 | - | caller save | | |
842 | * |GR16-GR31 | - | callee save | | |
843 | * |GR32-GR47 | - | caller save | | |
844 | * |GR48-GR63 | - | callee save | | |
845 | * |FR0-FR15 | - | caller save | | |
846 | * |FR16-FR31 | - | callee save | | |
847 | * |FR32-FR47 | - | caller save | | |
848 | * |FR48-FR63 | - | callee save | | |
849 | * +---------------+-----------------------+-----------------------+ | |
850 | * | |
851 | * Stack frame setup: | |
852 | * Low | |
853 | * SP-> |-----------------------------------| | |
854 | * | Argument area | | |
855 | * |-----------------------------------| | |
856 | * | Register save area | | |
857 | * |-----------------------------------| | |
858 | * | Local variable save area | | |
859 | * FP-> |-----------------------------------| | |
860 | * | Old FP | | |
861 | * |-----------------------------------| | |
862 | * | Hidden parameter save area | | |
863 | * |-----------------------------------| | |
864 | * | Return address(LR) storage area | | |
865 | * |-----------------------------------| | |
866 | * | Padding for alignment | | |
867 | * |-----------------------------------| | |
868 | * | Register argument area | | |
869 | * OLD SP-> |-----------------------------------| | |
870 | * | Parameter area | | |
871 | * |-----------------------------------| | |
872 | * High | |
873 | * | |
874 | * Argument area/Parameter area: | |
875 | * | |
876 | * When a function is called, this area is used for argument transfer. When | |
877 | * the argument is set up by the caller function, this area is referred to as | |
878 | * the argument area. When the argument is referenced by the callee function, | |
879 | * this area is referred to as the parameter area. The area is allocated when | |
880 | * all arguments cannot be placed on the argument register at the time of | |
881 | * argument transfer. | |
882 | * | |
883 | * Register save area: | |
884 | * | |
885 | * This is a register save area that must be guaranteed for the caller | |
886 | * function. This area is not secured when the register save operation is not | |
887 | * needed. | |
888 | * | |
889 | * Local variable save area: | |
890 | * | |
891 | * This is the area for local variables and temporary variables. | |
892 | * | |
893 | * Old FP: | |
894 | * | |
895 | * This area stores the FP value of the caller function. | |
896 | * | |
897 | * Hidden parameter save area: | |
898 | * | |
899 | * This area stores the start address of the return value storage | |
900 | * area for a struct/union return function. | |
901 | * When a struct/union is used as the return value, the caller | |
902 | * function stores the return value storage area start address in | |
903 | * register GR3 and passes it to the caller function. | |
904 | * The callee function interprets the address stored in the GR3 | |
905 | * as the return value storage area start address. | |
906 | * When register GR3 needs to be saved into memory, the callee | |
907 | * function saves it in the hidden parameter save area. This | |
908 | * area is not secured when the save operation is not needed. | |
909 | * | |
910 | * Return address(LR) storage area: | |
911 | * | |
912 | * This area saves the LR. The LR stores the address of a return to the caller | |
913 | * function for the purpose of function calling. | |
914 | * | |
915 | * Argument register area: | |
916 | * | |
917 | * This area saves the argument register. This area is not secured when the | |
918 | * save operation is not needed. | |
919 | * | |
920 | * Argument: | |
921 | * | |
922 | * Arguments, the count of which equals the count of argument registers (6 | |
923 | * words), are positioned in registers GR8 to GR13 and delivered to the callee | |
924 | * function. When a struct/union return function is called, the return value | |
925 | * area address is stored in register GR3. Arguments not placed in the | |
926 | * argument registers will be stored in the stack argument area for transfer | |
927 | * purposes. When an 8-byte type argument is to be delivered using registers, | |
928 | * it is divided into two and placed in two registers for transfer. When | |
929 | * argument registers must be saved to memory, the callee function secures an | |
930 | * argument register save area in the stack. In this case, a continuous | |
931 | * argument register save area must be established in the parameter area. The | |
932 | * argument register save area must be allocated as needed to cover the size of | |
933 | * the argument register to be saved. If the function has a variable count of | |
934 | * arguments, it saves all argument registers in the argument register save | |
935 | * area. | |
936 | * | |
937 | * Argument Extension Format: | |
938 | * | |
939 | * When an argument is to be stored in the stack, its type is converted to an | |
940 | * extended type in accordance with the individual argument type. The argument | |
941 | * is freed by the caller function after the return from the callee function is | |
942 | * made. | |
943 | * | |
944 | * +-----------------------+---------------+------------------------+ | |
945 | * | Argument Type |Extended Type |Stack Storage Size(byte)| | |
946 | * +-----------------------+---------------+------------------------+ | |
947 | * |char |int | 4 | | |
948 | * |signed char |int | 4 | | |
949 | * |unsigned char |int | 4 | | |
950 | * |[signed] short int |int | 4 | | |
951 | * |unsigned short int |int | 4 | | |
952 | * |[signed] int |No extension | 4 | | |
953 | * |unsigned int |No extension | 4 | | |
954 | * |[signed] long int |No extension | 4 | | |
955 | * |unsigned long int |No extension | 4 | | |
956 | * |[signed] long long int |No extension | 8 | | |
957 | * |unsigned long long int |No extension | 8 | | |
958 | * |float |double | 8 | | |
959 | * |double |No extension | 8 | | |
960 | * |long double |No extension | 8 | | |
961 | * |pointer |No extension | 4 | | |
962 | * |struct/union |- | 4 (*1) | | |
963 | * +-----------------------+---------------+------------------------+ | |
964 | * | |
965 | * When a struct/union is to be delivered as an argument, the caller copies it | |
966 | * to the local variable area and delivers the address of that area. | |
967 | * | |
968 | * Return Value: | |
969 | * | |
970 | * +-------------------------------+----------------------+ | |
971 | * |Return Value Type |Return Value Interface| | |
972 | * +-------------------------------+----------------------+ | |
973 | * |void |None | | |
974 | * |[signed|unsigned] char |GR8 | | |
975 | * |[signed|unsigned] short int |GR8 | | |
976 | * |[signed|unsigned] int |GR8 | | |
977 | * |[signed|unsigned] long int |GR8 | | |
978 | * |pointer |GR8 | | |
979 | * |[signed|unsigned] long long int|GR8 & GR9 | | |
980 | * |float |GR8 | | |
981 | * |double |GR8 & GR9 | | |
982 | * |long double |GR8 & GR9 | | |
983 | * |struct/union |(*1) | | |
984 | * +-------------------------------+----------------------+ | |
985 | * | |
986 | * When a struct/union is used as the return value, the caller function stores | |
987 | * the start address of the return value storage area into GR3 and then passes | |
988 | * it to the callee function. The callee function interprets GR3 as the start | |
989 | * address of the return value storage area. When this address needs to be | |
990 | * saved in memory, the callee function secures the hidden parameter save area | |
991 | * and saves the address in that area. | |
992 | */ | |
993 | ||
994 | frv_stack_t * | |
f2206911 | 995 | frv_stack_info (void) |
36a05131 BS |
996 | { |
997 | static frv_stack_t info, zero_info; | |
998 | frv_stack_t *info_ptr = &info; | |
999 | tree fndecl = current_function_decl; | |
1000 | int varargs_p = 0; | |
1001 | tree cur_arg; | |
1002 | tree next_arg; | |
1003 | int range; | |
1004 | int alignment; | |
1005 | int offset; | |
1006 | ||
87b483a1 KH |
1007 | /* If we've already calculated the values and reload is complete, |
1008 | just return now. */ | |
36a05131 BS |
1009 | if (frv_stack_cache) |
1010 | return frv_stack_cache; | |
1011 | ||
87b483a1 | 1012 | /* Zero all fields. */ |
36a05131 BS |
1013 | info = zero_info; |
1014 | ||
87b483a1 | 1015 | /* Set up the register range information. */ |
36a05131 BS |
1016 | info_ptr->regs[STACK_REGS_GPR].name = "gpr"; |
1017 | info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1; | |
1018 | info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST; | |
1019 | info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE; | |
1020 | ||
1021 | info_ptr->regs[STACK_REGS_FPR].name = "fpr"; | |
1022 | info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST; | |
1023 | info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST; | |
1024 | info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE; | |
1025 | ||
1026 | info_ptr->regs[STACK_REGS_LR].name = "lr"; | |
1027 | info_ptr->regs[STACK_REGS_LR].first = LR_REGNO; | |
1028 | info_ptr->regs[STACK_REGS_LR].last = LR_REGNO; | |
1029 | info_ptr->regs[STACK_REGS_LR].special_p = 1; | |
1030 | ||
1031 | info_ptr->regs[STACK_REGS_CC].name = "cc"; | |
1032 | info_ptr->regs[STACK_REGS_CC].first = CC_FIRST; | |
1033 | info_ptr->regs[STACK_REGS_CC].last = CC_LAST; | |
1034 | info_ptr->regs[STACK_REGS_CC].field_p = TRUE; | |
1035 | ||
1036 | info_ptr->regs[STACK_REGS_LCR].name = "lcr"; | |
1037 | info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO; | |
1038 | info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO; | |
1039 | ||
1040 | info_ptr->regs[STACK_REGS_STDARG].name = "stdarg"; | |
1041 | info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM; | |
1042 | info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM; | |
1043 | info_ptr->regs[STACK_REGS_STDARG].dword_p = 1; | |
1044 | info_ptr->regs[STACK_REGS_STDARG].special_p = 1; | |
1045 | ||
1046 | info_ptr->regs[STACK_REGS_STRUCT].name = "struct"; | |
8ac411c7 KH |
1047 | info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM; |
1048 | info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM; | |
36a05131 BS |
1049 | info_ptr->regs[STACK_REGS_STRUCT].special_p = 1; |
1050 | ||
1051 | info_ptr->regs[STACK_REGS_FP].name = "fp"; | |
1052 | info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM; | |
1053 | info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM; | |
1054 | info_ptr->regs[STACK_REGS_FP].special_p = 1; | |
1055 | ||
1056 | /* Determine if this is a stdarg function. If so, allocate space to store | |
1057 | the 6 arguments. */ | |
1058 | if (cfun->stdarg) | |
1059 | varargs_p = 1; | |
1060 | ||
1061 | else | |
1062 | { | |
1063 | /* Find the last argument, and see if it is __builtin_va_alist. */ | |
1064 | for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg) | |
1065 | { | |
910ad8de | 1066 | next_arg = DECL_CHAIN (cur_arg); |
36a05131 BS |
1067 | if (next_arg == (tree)0) |
1068 | { | |
1069 | if (DECL_NAME (cur_arg) | |
1070 | && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist")) | |
1071 | varargs_p = 1; | |
1072 | ||
1073 | break; | |
1074 | } | |
1075 | } | |
1076 | } | |
1077 | ||
87b483a1 | 1078 | /* Iterate over all of the register ranges. */ |
36a05131 BS |
1079 | for (range = 0; range < STACK_REGS_MAX; range++) |
1080 | { | |
1081 | frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); | |
1082 | int first = reg_ptr->first; | |
1083 | int last = reg_ptr->last; | |
1084 | int size_1word = 0; | |
1085 | int size_2words = 0; | |
1086 | int regno; | |
1087 | ||
87b483a1 | 1088 | /* Calculate which registers need to be saved & save area size. */ |
36a05131 BS |
1089 | switch (range) |
1090 | { | |
1091 | default: | |
1092 | for (regno = first; regno <= last; regno++) | |
1093 | { | |
6fb5fa3c | 1094 | if ((df_regs_ever_live_p (regno) && !call_used_regs[regno]) |
e3b5732b | 1095 | || (crtl->calls_eh_return |
36a05131 | 1096 | && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM)) |
34208acf | 1097 | || (!TARGET_FDPIC && flag_pic |
ad516a74 | 1098 | && crtl->uses_pic_offset_table && regno == PIC_REGNO)) |
36a05131 BS |
1099 | { |
1100 | info_ptr->save_p[regno] = REG_SAVE_1WORD; | |
1101 | size_1word += UNITS_PER_WORD; | |
1102 | } | |
1103 | } | |
1104 | break; | |
1105 | ||
1106 | /* Calculate whether we need to create a frame after everything else | |
1107 | has been processed. */ | |
1108 | case STACK_REGS_FP: | |
1109 | break; | |
1110 | ||
1111 | case STACK_REGS_LR: | |
6fb5fa3c | 1112 | if (df_regs_ever_live_p (LR_REGNO) |
36a05131 | 1113 | || profile_flag |
34208acf AO |
1114 | /* This is set for __builtin_return_address, etc. */ |
1115 | || cfun->machine->frame_needed | |
1116 | || (TARGET_LINKED_FP && frame_pointer_needed) | |
1117 | || (!TARGET_FDPIC && flag_pic | |
ad516a74 | 1118 | && crtl->uses_pic_offset_table)) |
36a05131 BS |
1119 | { |
1120 | info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD; | |
1121 | size_1word += UNITS_PER_WORD; | |
1122 | } | |
1123 | break; | |
1124 | ||
1125 | case STACK_REGS_STDARG: | |
1126 | if (varargs_p) | |
1127 | { | |
87b483a1 KH |
1128 | /* If this is a stdarg function with a non varardic |
1129 | argument split between registers and the stack, | |
1130 | adjust the saved registers downward. */ | |
7dd68986 | 1131 | last -= (ADDR_ALIGN (crtl->args.pretend_args_size, UNITS_PER_WORD) |
36a05131 BS |
1132 | / UNITS_PER_WORD); |
1133 | ||
1134 | for (regno = first; regno <= last; regno++) | |
1135 | { | |
1136 | info_ptr->save_p[regno] = REG_SAVE_1WORD; | |
1137 | size_1word += UNITS_PER_WORD; | |
1138 | } | |
1139 | ||
1140 | info_ptr->stdarg_size = size_1word; | |
1141 | } | |
1142 | break; | |
1143 | ||
1144 | case STACK_REGS_STRUCT: | |
1145 | if (cfun->returns_struct) | |
1146 | { | |
8ac411c7 | 1147 | info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD; |
36a05131 BS |
1148 | size_1word += UNITS_PER_WORD; |
1149 | } | |
1150 | break; | |
1151 | } | |
1152 | ||
1153 | ||
1154 | if (size_1word) | |
1155 | { | |
87b483a1 | 1156 | /* If this is a field, it only takes one word. */ |
36a05131 BS |
1157 | if (reg_ptr->field_p) |
1158 | size_1word = UNITS_PER_WORD; | |
1159 | ||
87b483a1 | 1160 | /* Determine which register pairs can be saved together. */ |
36a05131 BS |
1161 | else if (reg_ptr->dword_p && TARGET_DWORD) |
1162 | { | |
1163 | for (regno = first; regno < last; regno += 2) | |
1164 | { | |
1165 | if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1]) | |
1166 | { | |
1167 | size_2words += 2 * UNITS_PER_WORD; | |
1168 | size_1word -= 2 * UNITS_PER_WORD; | |
1169 | info_ptr->save_p[regno] = REG_SAVE_2WORDS; | |
1170 | info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE; | |
1171 | } | |
1172 | } | |
1173 | } | |
1174 | ||
1175 | reg_ptr->size_1word = size_1word; | |
1176 | reg_ptr->size_2words = size_2words; | |
1177 | ||
1178 | if (! reg_ptr->special_p) | |
1179 | { | |
1180 | info_ptr->regs_size_1word += size_1word; | |
1181 | info_ptr->regs_size_2words += size_2words; | |
1182 | } | |
1183 | } | |
1184 | } | |
1185 | ||
026c3cfd | 1186 | /* Set up the sizes of each field in the frame body, making the sizes |
36a05131 BS |
1187 | of each be divisible by the size of a dword if dword operations might |
1188 | be used, or the size of a word otherwise. */ | |
1189 | alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD); | |
1190 | ||
7dd68986 | 1191 | info_ptr->parameter_size = ADDR_ALIGN (crtl->outgoing_args_size, alignment); |
36a05131 BS |
1192 | info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words |
1193 | + info_ptr->regs_size_1word, | |
1194 | alignment); | |
1195 | info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment); | |
1196 | ||
7dd68986 | 1197 | info_ptr->pretend_size = crtl->args.pretend_args_size; |
36a05131 BS |
1198 | |
1199 | /* Work out the size of the frame, excluding the header. Both the frame | |
1200 | body and register parameter area will be dword-aligned. */ | |
1201 | info_ptr->total_size | |
1202 | = (ADDR_ALIGN (info_ptr->parameter_size | |
1203 | + info_ptr->regs_size | |
1204 | + info_ptr->vars_size, | |
1205 | 2 * UNITS_PER_WORD) | |
1206 | + ADDR_ALIGN (info_ptr->pretend_size | |
1207 | + info_ptr->stdarg_size, | |
1208 | 2 * UNITS_PER_WORD)); | |
1209 | ||
1210 | /* See if we need to create a frame at all, if so add header area. */ | |
1211 | if (info_ptr->total_size > 0 | |
34208acf | 1212 | || frame_pointer_needed |
36a05131 BS |
1213 | || info_ptr->regs[STACK_REGS_LR].size_1word > 0 |
1214 | || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0) | |
1215 | { | |
1216 | offset = info_ptr->parameter_size; | |
1217 | info_ptr->header_size = 4 * UNITS_PER_WORD; | |
1218 | info_ptr->total_size += 4 * UNITS_PER_WORD; | |
1219 | ||
87b483a1 | 1220 | /* Calculate the offsets to save normal register pairs. */ |
36a05131 BS |
1221 | for (range = 0; range < STACK_REGS_MAX; range++) |
1222 | { | |
1223 | frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); | |
1224 | if (! reg_ptr->special_p) | |
1225 | { | |
1226 | int first = reg_ptr->first; | |
1227 | int last = reg_ptr->last; | |
1228 | int regno; | |
1229 | ||
1230 | for (regno = first; regno <= last; regno++) | |
1231 | if (info_ptr->save_p[regno] == REG_SAVE_2WORDS | |
1232 | && regno != FRAME_POINTER_REGNUM | |
1233 | && (regno < FIRST_ARG_REGNUM | |
1234 | || regno > LAST_ARG_REGNUM)) | |
1235 | { | |
1236 | info_ptr->reg_offset[regno] = offset; | |
1237 | offset += 2 * UNITS_PER_WORD; | |
1238 | } | |
1239 | } | |
1240 | } | |
1241 | ||
87b483a1 | 1242 | /* Calculate the offsets to save normal single registers. */ |
36a05131 BS |
1243 | for (range = 0; range < STACK_REGS_MAX; range++) |
1244 | { | |
1245 | frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); | |
1246 | if (! reg_ptr->special_p) | |
1247 | { | |
1248 | int first = reg_ptr->first; | |
1249 | int last = reg_ptr->last; | |
1250 | int regno; | |
1251 | ||
1252 | for (regno = first; regno <= last; regno++) | |
1253 | if (info_ptr->save_p[regno] == REG_SAVE_1WORD | |
1254 | && regno != FRAME_POINTER_REGNUM | |
1255 | && (regno < FIRST_ARG_REGNUM | |
1256 | || regno > LAST_ARG_REGNUM)) | |
1257 | { | |
1258 | info_ptr->reg_offset[regno] = offset; | |
1259 | offset += UNITS_PER_WORD; | |
1260 | } | |
1261 | } | |
1262 | } | |
1263 | ||
1264 | /* Calculate the offset to save the local variables at. */ | |
1265 | offset = ADDR_ALIGN (offset, alignment); | |
1266 | if (info_ptr->vars_size) | |
1267 | { | |
1268 | info_ptr->vars_offset = offset; | |
1269 | offset += info_ptr->vars_size; | |
1270 | } | |
1271 | ||
1272 | /* Align header to a dword-boundary. */ | |
1273 | offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD); | |
1274 | ||
1275 | /* Calculate the offsets in the fixed frame. */ | |
1276 | info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD; | |
1277 | info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset; | |
1278 | info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD; | |
1279 | ||
1280 | info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD; | |
1281 | info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD; | |
1282 | info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD; | |
1283 | ||
1284 | if (cfun->returns_struct) | |
1285 | { | |
8ac411c7 KH |
1286 | info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD; |
1287 | info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD; | |
36a05131 BS |
1288 | info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD; |
1289 | } | |
1290 | ||
1291 | /* Calculate the offsets to store the arguments passed in registers | |
1292 | for stdarg functions. The register pairs are first and the single | |
1293 | register if any is last. The register save area starts on a | |
1294 | dword-boundary. */ | |
1295 | if (info_ptr->stdarg_size) | |
1296 | { | |
1297 | int first = info_ptr->regs[STACK_REGS_STDARG].first; | |
1298 | int last = info_ptr->regs[STACK_REGS_STDARG].last; | |
1299 | int regno; | |
1300 | ||
1301 | /* Skip the header. */ | |
1302 | offset += 4 * UNITS_PER_WORD; | |
1303 | for (regno = first; regno <= last; regno++) | |
1304 | { | |
1305 | if (info_ptr->save_p[regno] == REG_SAVE_2WORDS) | |
1306 | { | |
1307 | info_ptr->reg_offset[regno] = offset; | |
1308 | offset += 2 * UNITS_PER_WORD; | |
1309 | } | |
1310 | else if (info_ptr->save_p[regno] == REG_SAVE_1WORD) | |
1311 | { | |
1312 | info_ptr->reg_offset[regno] = offset; | |
1313 | offset += UNITS_PER_WORD; | |
1314 | } | |
1315 | } | |
1316 | } | |
1317 | } | |
1318 | ||
1319 | if (reload_completed) | |
1320 | frv_stack_cache = info_ptr; | |
1321 | ||
1322 | return info_ptr; | |
1323 | } | |
1324 | ||
1325 | \f | |
87b483a1 | 1326 | /* Print the information about the frv stack offsets, etc. when debugging. */ |
36a05131 BS |
1327 | |
1328 | void | |
f2206911 | 1329 | frv_debug_stack (frv_stack_t *info) |
36a05131 BS |
1330 | { |
1331 | int range; | |
1332 | ||
1333 | if (!info) | |
1334 | info = frv_stack_info (); | |
1335 | ||
1336 | fprintf (stderr, "\nStack information for function %s:\n", | |
1337 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
1338 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
1339 | : "<unknown>")); | |
1340 | ||
1341 | fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size); | |
1342 | fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size); | |
1343 | fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size); | |
1344 | fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n", | |
1345 | info->regs_size, info->regs_size_1word, info->regs_size_2words); | |
1346 | ||
1347 | fprintf (stderr, "\theader_size\t= %6d\n", info->header_size); | |
1348 | fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size); | |
1349 | fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset); | |
1350 | fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset); | |
1351 | ||
1352 | for (range = 0; range < STACK_REGS_MAX; range++) | |
1353 | { | |
1354 | frv_stack_regs_t *regs = &(info->regs[range]); | |
1355 | if ((regs->size_1word + regs->size_2words) > 0) | |
1356 | { | |
1357 | int first = regs->first; | |
1358 | int last = regs->last; | |
1359 | int regno; | |
1360 | ||
1361 | fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =", | |
1362 | regs->name, regs->size_1word + regs->size_2words, | |
1363 | regs->size_1word, regs->size_2words); | |
1364 | ||
1365 | for (regno = first; regno <= last; regno++) | |
1366 | { | |
1367 | if (info->save_p[regno] == REG_SAVE_1WORD) | |
1368 | fprintf (stderr, " %s (%d)", reg_names[regno], | |
1369 | info->reg_offset[regno]); | |
1370 | ||
1371 | else if (info->save_p[regno] == REG_SAVE_2WORDS) | |
1372 | fprintf (stderr, " %s-%s (%d)", reg_names[regno], | |
1373 | reg_names[regno+1], info->reg_offset[regno]); | |
1374 | } | |
1375 | ||
1376 | fputc ('\n', stderr); | |
1377 | } | |
1378 | } | |
1379 | ||
1380 | fflush (stderr); | |
1381 | } | |
1382 | ||
1383 | ||
1384 | \f | |
1385 | ||
c557edf4 RS |
1386 | /* Used during final to control the packing of insns. The value is |
1387 | 1 if the current instruction should be packed with the next one, | |
1388 | 0 if it shouldn't or -1 if packing is disabled altogether. */ | |
36a05131 BS |
1389 | |
1390 | static int frv_insn_packing_flag; | |
1391 | ||
1392 | /* True if the current function contains a far jump. */ | |
1393 | ||
1394 | static int | |
f2206911 | 1395 | frv_function_contains_far_jump (void) |
36a05131 | 1396 | { |
b32d5189 | 1397 | rtx_insn *insn = get_insns (); |
36a05131 | 1398 | while (insn != NULL |
b64925dc | 1399 | && !(JUMP_P (insn) |
36a05131 BS |
1400 | && get_attr_far_jump (insn) == FAR_JUMP_YES)) |
1401 | insn = NEXT_INSN (insn); | |
1402 | return (insn != NULL); | |
1403 | } | |
1404 | ||
1405 | /* For the FRV, this function makes sure that a function with far jumps | |
1406 | will return correctly. It also does the VLIW packing. */ | |
1407 | ||
1408 | static void | |
42776416 | 1409 | frv_function_prologue (FILE *file) |
36a05131 | 1410 | { |
e6eda746 | 1411 | rtx_insn *insn, *next, *last_call; |
0fad9ab9 | 1412 | |
36a05131 BS |
1413 | /* If no frame was created, check whether the function uses a call |
1414 | instruction to implement a far jump. If so, save the link in gr3 and | |
1415 | replace all returns to LR with returns to GR3. GR3 is used because it | |
1416 | is call-clobbered, because is not available to the register allocator, | |
1417 | and because all functions that take a hidden argument pointer will have | |
1418 | a stack frame. */ | |
1419 | if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ()) | |
1420 | { | |
e6eda746 | 1421 | rtx_insn *insn; |
36a05131 BS |
1422 | |
1423 | /* Just to check that the above comment is true. */ | |
6fb5fa3c | 1424 | gcc_assert (!df_regs_ever_live_p (GPR_FIRST + 3)); |
36a05131 BS |
1425 | |
1426 | /* Generate the instruction that saves the link register. */ | |
1427 | fprintf (file, "\tmovsg lr,gr3\n"); | |
1428 | ||
1429 | /* Replace the LR with GR3 in *return_internal patterns. The insn | |
1430 | will now return using jmpl @(gr3,0) rather than bralr. We cannot | |
1431 | simply emit a different assembly directive because bralr and jmpl | |
1432 | execute in different units. */ | |
1433 | for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn)) | |
b64925dc | 1434 | if (JUMP_P (insn)) |
36a05131 BS |
1435 | { |
1436 | rtx pattern = PATTERN (insn); | |
1437 | if (GET_CODE (pattern) == PARALLEL | |
1438 | && XVECLEN (pattern, 0) >= 2 | |
1439 | && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN | |
1440 | && GET_CODE (XVECEXP (pattern, 0, 1)) == USE) | |
1441 | { | |
1442 | rtx address = XEXP (XVECEXP (pattern, 0, 1), 0); | |
1443 | if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO) | |
6fb5fa3c | 1444 | SET_REGNO (address, GPR_FIRST + 3); |
36a05131 BS |
1445 | } |
1446 | } | |
1447 | } | |
1448 | ||
1449 | frv_pack_insns (); | |
c557edf4 RS |
1450 | |
1451 | /* Allow the garbage collector to free the nops created by frv_reorg. */ | |
1452 | memset (frv_nops, 0, sizeof (frv_nops)); | |
0fad9ab9 NC |
1453 | |
1454 | /* Locate CALL_ARG_LOCATION notes that have been misplaced | |
1455 | and move them back to where they should be located. */ | |
e6eda746 | 1456 | last_call = NULL; |
0fad9ab9 NC |
1457 | for (insn = get_insns (); insn; insn = next) |
1458 | { | |
1459 | next = NEXT_INSN (insn); | |
1460 | if (CALL_P (insn) | |
1461 | || (INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE | |
1462 | && CALL_P (XVECEXP (PATTERN (insn), 0, 0)))) | |
1463 | last_call = insn; | |
1464 | ||
1465 | if (!NOTE_P (insn) || NOTE_KIND (insn) != NOTE_INSN_CALL_ARG_LOCATION) | |
1466 | continue; | |
1467 | ||
1468 | if (NEXT_INSN (last_call) == insn) | |
1469 | continue; | |
1470 | ||
0f82e5c9 DM |
1471 | SET_NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn); |
1472 | SET_PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn); | |
1473 | SET_PREV_INSN (insn) = last_call; | |
1474 | SET_NEXT_INSN (insn) = NEXT_INSN (last_call); | |
1475 | SET_PREV_INSN (NEXT_INSN (insn)) = insn; | |
1476 | SET_NEXT_INSN (PREV_INSN (insn)) = insn; | |
0fad9ab9 NC |
1477 | last_call = insn; |
1478 | } | |
36a05131 BS |
1479 | } |
1480 | ||
1481 | \f | |
1482 | /* Return the next available temporary register in a given class. */ | |
1483 | ||
1484 | static rtx | |
f2206911 KC |
1485 | frv_alloc_temp_reg ( |
1486 | frv_tmp_reg_t *info, /* which registers are available */ | |
0a2aaacc | 1487 | enum reg_class rclass, /* register class desired */ |
ef4bddc2 | 1488 | machine_mode mode, /* mode to allocate register with */ |
f2206911 KC |
1489 | int mark_as_used, /* register not available after allocation */ |
1490 | int no_abort) /* return NULL instead of aborting */ | |
36a05131 | 1491 | { |
0a2aaacc | 1492 | int regno = info->next_reg[ (int)rclass ]; |
36a05131 | 1493 | int orig_regno = regno; |
0a2aaacc | 1494 | HARD_REG_SET *reg_in_class = ®_class_contents[ (int)rclass ]; |
36a05131 BS |
1495 | int i, nr; |
1496 | ||
1497 | for (;;) | |
1498 | { | |
1499 | if (TEST_HARD_REG_BIT (*reg_in_class, regno) | |
1500 | && TEST_HARD_REG_BIT (info->regs, regno)) | |
1501 | break; | |
1502 | ||
1503 | if (++regno >= FIRST_PSEUDO_REGISTER) | |
1504 | regno = 0; | |
1505 | if (regno == orig_regno) | |
1506 | { | |
44e91694 NS |
1507 | gcc_assert (no_abort); |
1508 | return NULL_RTX; | |
36a05131 BS |
1509 | } |
1510 | } | |
1511 | ||
1512 | nr = HARD_REGNO_NREGS (regno, mode); | |
0a2aaacc | 1513 | info->next_reg[ (int)rclass ] = regno + nr; |
36a05131 BS |
1514 | |
1515 | if (mark_as_used) | |
1516 | for (i = 0; i < nr; i++) | |
1517 | CLEAR_HARD_REG_BIT (info->regs, regno+i); | |
1518 | ||
1519 | return gen_rtx_REG (mode, regno); | |
1520 | } | |
1521 | ||
1522 | \f | |
1523 | /* Return an rtx with the value OFFSET, which will either be a register or a | |
1524 | signed 12-bit integer. It can be used as the second operand in an "add" | |
1525 | instruction, or as the index in a load or store. | |
1526 | ||
1527 | The function returns a constant rtx if OFFSET is small enough, otherwise | |
1528 | it loads the constant into register OFFSET_REGNO and returns that. */ | |
1529 | static rtx | |
f2206911 | 1530 | frv_frame_offset_rtx (int offset) |
36a05131 BS |
1531 | { |
1532 | rtx offset_rtx = GEN_INT (offset); | |
2f5b1308 | 1533 | if (IN_RANGE (offset, -2048, 2047)) |
36a05131 BS |
1534 | return offset_rtx; |
1535 | else | |
1536 | { | |
1537 | rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO); | |
2f5b1308 | 1538 | if (IN_RANGE (offset, -32768, 32767)) |
36a05131 BS |
1539 | emit_insn (gen_movsi (reg_rtx, offset_rtx)); |
1540 | else | |
1541 | { | |
1542 | emit_insn (gen_movsi_high (reg_rtx, offset_rtx)); | |
1543 | emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx)); | |
1544 | } | |
1545 | return reg_rtx; | |
1546 | } | |
1547 | } | |
1548 | ||
1549 | /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The | |
1550 | prologue and epilogue uses such expressions to access the stack. */ | |
1551 | static rtx | |
ef4bddc2 | 1552 | frv_frame_mem (machine_mode mode, rtx base, int offset) |
36a05131 BS |
1553 | { |
1554 | return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, | |
1555 | base, | |
1556 | frv_frame_offset_rtx (offset))); | |
1557 | } | |
1558 | ||
1559 | /* Generate a frame-related expression: | |
1560 | ||
1561 | (set REG (mem (plus (sp) (const_int OFFSET)))). | |
1562 | ||
1563 | Such expressions are used in FRAME_RELATED_EXPR notes for more complex | |
1564 | instructions. Marking the expressions as frame-related is superfluous if | |
1565 | the note contains just a single set. But if the note contains a PARALLEL | |
1566 | or SEQUENCE that has several sets, each set must be individually marked | |
1567 | as frame-related. */ | |
1568 | static rtx | |
f2206911 | 1569 | frv_dwarf_store (rtx reg, int offset) |
36a05131 | 1570 | { |
f7df4a84 | 1571 | rtx set = gen_rtx_SET (gen_rtx_MEM (GET_MODE (reg), |
0a81f074 | 1572 | plus_constant (Pmode, stack_pointer_rtx, |
36a05131 BS |
1573 | offset)), |
1574 | reg); | |
1575 | RTX_FRAME_RELATED_P (set) = 1; | |
1576 | return set; | |
1577 | } | |
1578 | ||
1579 | /* Emit a frame-related instruction whose pattern is PATTERN. The | |
1580 | instruction is the last in a sequence that cumulatively performs the | |
1581 | operation described by DWARF_PATTERN. The instruction is marked as | |
1582 | frame-related and has a REG_FRAME_RELATED_EXPR note containing | |
1583 | DWARF_PATTERN. */ | |
1584 | static void | |
f2206911 | 1585 | frv_frame_insn (rtx pattern, rtx dwarf_pattern) |
36a05131 BS |
1586 | { |
1587 | rtx insn = emit_insn (pattern); | |
1588 | RTX_FRAME_RELATED_P (insn) = 1; | |
1589 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
1590 | dwarf_pattern, | |
1591 | REG_NOTES (insn)); | |
1592 | } | |
1593 | ||
1594 | /* Emit instructions that transfer REG to or from the memory location (sp + | |
1595 | STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is | |
1596 | FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this | |
1597 | function to store registers and only the epilogue uses it to load them. | |
1598 | ||
1599 | The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET). | |
1600 | The generated instruction will use BASE as its base register. BASE may | |
1601 | simply be the stack pointer, but if several accesses are being made to a | |
1602 | region far away from the stack pointer, it may be more efficient to set | |
1603 | up a temporary instead. | |
b16c1435 | 1604 | |
36a05131 BS |
1605 | Store instructions will be frame-related and will be annotated with the |
1606 | overall effect of the store. Load instructions will be followed by a | |
1607 | (use) to prevent later optimizations from zapping them. | |
1608 | ||
1609 | The function takes care of the moves to and from SPRs, using TEMP_REGNO | |
1610 | as a temporary in such cases. */ | |
1611 | static void | |
f2206911 | 1612 | frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset) |
36a05131 | 1613 | { |
ef4bddc2 | 1614 | machine_mode mode = GET_MODE (reg); |
36a05131 BS |
1615 | rtx mem = frv_frame_mem (mode, |
1616 | accessor->base, | |
1617 | stack_offset - accessor->base_offset); | |
1618 | ||
1619 | if (accessor->op == FRV_LOAD) | |
1620 | { | |
1621 | if (SPR_P (REGNO (reg))) | |
1622 | { | |
1623 | rtx temp = gen_rtx_REG (mode, TEMP_REGNO); | |
f7df4a84 RS |
1624 | emit_insn (gen_rtx_SET (temp, mem)); |
1625 | emit_insn (gen_rtx_SET (reg, temp)); | |
36a05131 BS |
1626 | } |
1627 | else | |
8d8256c1 NC |
1628 | { |
1629 | /* We cannot use reg+reg addressing for DImode access. */ | |
1630 | if (mode == DImode | |
1631 | && GET_CODE (XEXP (mem, 0)) == PLUS | |
1632 | && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG | |
1633 | && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG) | |
1634 | { | |
1635 | rtx temp = gen_rtx_REG (SImode, TEMP_REGNO); | |
5c5e8419 JR |
1636 | |
1637 | emit_move_insn (temp, | |
1638 | gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0), | |
1639 | XEXP (XEXP (mem, 0), 1))); | |
8d8256c1 NC |
1640 | mem = gen_rtx_MEM (DImode, temp); |
1641 | } | |
f7df4a84 | 1642 | emit_insn (gen_rtx_SET (reg, mem)); |
8d8256c1 | 1643 | } |
c41c1387 | 1644 | emit_use (reg); |
36a05131 BS |
1645 | } |
1646 | else | |
1647 | { | |
1648 | if (SPR_P (REGNO (reg))) | |
1649 | { | |
1650 | rtx temp = gen_rtx_REG (mode, TEMP_REGNO); | |
f7df4a84 RS |
1651 | emit_insn (gen_rtx_SET (temp, reg)); |
1652 | frv_frame_insn (gen_rtx_SET (mem, temp), | |
36a05131 BS |
1653 | frv_dwarf_store (reg, stack_offset)); |
1654 | } | |
8d8256c1 | 1655 | else if (mode == DImode) |
36a05131 BS |
1656 | { |
1657 | /* For DImode saves, the dwarf2 version needs to be a SEQUENCE | |
1658 | with a separate save for each register. */ | |
1659 | rtx reg1 = gen_rtx_REG (SImode, REGNO (reg)); | |
1660 | rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1); | |
1661 | rtx set1 = frv_dwarf_store (reg1, stack_offset); | |
1662 | rtx set2 = frv_dwarf_store (reg2, stack_offset + 4); | |
8d8256c1 NC |
1663 | |
1664 | /* Also we cannot use reg+reg addressing. */ | |
1665 | if (GET_CODE (XEXP (mem, 0)) == PLUS | |
1666 | && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG | |
1667 | && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG) | |
1668 | { | |
1669 | rtx temp = gen_rtx_REG (SImode, TEMP_REGNO); | |
5c5e8419 JR |
1670 | emit_move_insn (temp, |
1671 | gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0), | |
1672 | XEXP (XEXP (mem, 0), 1))); | |
8d8256c1 NC |
1673 | mem = gen_rtx_MEM (DImode, temp); |
1674 | } | |
1675 | ||
f7df4a84 | 1676 | frv_frame_insn (gen_rtx_SET (mem, reg), |
36a05131 BS |
1677 | gen_rtx_PARALLEL (VOIDmode, |
1678 | gen_rtvec (2, set1, set2))); | |
1679 | } | |
1680 | else | |
f7df4a84 | 1681 | frv_frame_insn (gen_rtx_SET (mem, reg), |
36a05131 BS |
1682 | frv_dwarf_store (reg, stack_offset)); |
1683 | } | |
1684 | } | |
1685 | ||
1686 | /* A function that uses frv_frame_access to transfer a group of registers to | |
1687 | or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO | |
1688 | is the stack information generated by frv_stack_info, and REG_SET is the | |
1689 | number of the register set to transfer. */ | |
1690 | static void | |
f2206911 KC |
1691 | frv_frame_access_multi (frv_frame_accessor_t *accessor, |
1692 | frv_stack_t *info, | |
1693 | int reg_set) | |
36a05131 BS |
1694 | { |
1695 | frv_stack_regs_t *regs_info; | |
1696 | int regno; | |
1697 | ||
1698 | regs_info = &info->regs[reg_set]; | |
1699 | for (regno = regs_info->first; regno <= regs_info->last; regno++) | |
1700 | if (info->save_p[regno]) | |
1701 | frv_frame_access (accessor, | |
1702 | info->save_p[regno] == REG_SAVE_2WORDS | |
1703 | ? gen_rtx_REG (DImode, regno) | |
1704 | : gen_rtx_REG (SImode, regno), | |
1705 | info->reg_offset[regno]); | |
1706 | } | |
1707 | ||
1708 | /* Save or restore callee-saved registers that are kept outside the frame | |
1709 | header. The function saves the registers if OP is FRV_STORE and restores | |
1710 | them if OP is FRV_LOAD. INFO is the stack information generated by | |
1711 | frv_stack_info. */ | |
1712 | static void | |
f2206911 | 1713 | frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info) |
36a05131 BS |
1714 | { |
1715 | frv_frame_accessor_t accessor; | |
1716 | ||
1717 | accessor.op = op; | |
1718 | accessor.base = stack_pointer_rtx; | |
1719 | accessor.base_offset = 0; | |
1720 | frv_frame_access_multi (&accessor, info, STACK_REGS_GPR); | |
1721 | frv_frame_access_multi (&accessor, info, STACK_REGS_FPR); | |
1722 | frv_frame_access_multi (&accessor, info, STACK_REGS_LCR); | |
b16c1435 | 1723 | } |
36a05131 BS |
1724 | |
1725 | ||
1726 | /* Called after register allocation to add any instructions needed for the | |
1727 | prologue. Using a prologue insn is favored compared to putting all of the | |
b88cf82e KH |
1728 | instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since |
1729 | it allows the scheduler to intermix instructions with the saves of | |
1730 | the caller saved registers. In some cases, it might be necessary | |
1731 | to emit a barrier instruction as the last insn to prevent such | |
1732 | scheduling. | |
36a05131 BS |
1733 | |
1734 | Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1 | |
1735 | so that the debug info generation code can handle them properly. */ | |
1736 | void | |
f2206911 | 1737 | frv_expand_prologue (void) |
36a05131 BS |
1738 | { |
1739 | frv_stack_t *info = frv_stack_info (); | |
1740 | rtx sp = stack_pointer_rtx; | |
1741 | rtx fp = frame_pointer_rtx; | |
1742 | frv_frame_accessor_t accessor; | |
1743 | ||
1744 | if (TARGET_DEBUG_STACK) | |
1745 | frv_debug_stack (info); | |
1746 | ||
7027164c NC |
1747 | if (flag_stack_usage_info) |
1748 | current_function_static_stack_size = info->total_size; | |
1749 | ||
36a05131 BS |
1750 | if (info->total_size == 0) |
1751 | return; | |
1752 | ||
1753 | /* We're interested in three areas of the frame here: | |
1754 | ||
1755 | A: the register save area | |
1756 | B: the old FP | |
1757 | C: the header after B | |
1758 | ||
1759 | If the frame pointer isn't used, we'll have to set up A, B and C | |
1760 | using the stack pointer. If the frame pointer is used, we'll access | |
1761 | them as follows: | |
1762 | ||
1763 | A: set up using sp | |
1764 | B: set up using sp or a temporary (see below) | |
1765 | C: set up using fp | |
1766 | ||
1767 | We set up B using the stack pointer if the frame is small enough. | |
1768 | Otherwise, it's more efficient to copy the old stack pointer into a | |
1769 | temporary and use that. | |
1770 | ||
1771 | Note that it's important to make sure the prologue and epilogue use the | |
1772 | same registers to access A and C, since doing otherwise will confuse | |
1773 | the aliasing code. */ | |
1774 | ||
1775 | /* Set up ACCESSOR for accessing region B above. If the frame pointer | |
1776 | isn't used, the same method will serve for C. */ | |
1777 | accessor.op = FRV_STORE; | |
1778 | if (frame_pointer_needed && info->total_size > 2048) | |
1779 | { | |
36a05131 BS |
1780 | accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO); |
1781 | accessor.base_offset = info->total_size; | |
5c5e8419 | 1782 | emit_insn (gen_movsi (accessor.base, sp)); |
36a05131 BS |
1783 | } |
1784 | else | |
1785 | { | |
1786 | accessor.base = stack_pointer_rtx; | |
1787 | accessor.base_offset = 0; | |
1788 | } | |
1789 | ||
1790 | /* Allocate the stack space. */ | |
1791 | { | |
1792 | rtx asm_offset = frv_frame_offset_rtx (-info->total_size); | |
1793 | rtx dwarf_offset = GEN_INT (-info->total_size); | |
1794 | ||
1795 | frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset), | |
f7df4a84 | 1796 | gen_rtx_SET (sp, gen_rtx_PLUS (Pmode, sp, dwarf_offset))); |
36a05131 BS |
1797 | } |
1798 | ||
1799 | /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET) | |
1800 | and point the new one to that location. */ | |
1801 | if (frame_pointer_needed) | |
1802 | { | |
1803 | int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM]; | |
1804 | ||
1805 | /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is | |
1806 | based on ACCESSOR.BASE but DWARF_SRC is always based on the stack | |
1807 | pointer. */ | |
0a81f074 | 1808 | rtx asm_src = plus_constant (Pmode, accessor.base, |
36a05131 | 1809 | fp_offset - accessor.base_offset); |
0a81f074 | 1810 | rtx dwarf_src = plus_constant (Pmode, sp, fp_offset); |
36a05131 BS |
1811 | |
1812 | /* Store the old frame pointer at (sp + FP_OFFSET). */ | |
1813 | frv_frame_access (&accessor, fp, fp_offset); | |
1814 | ||
1815 | /* Set up the new frame pointer. */ | |
f7df4a84 RS |
1816 | frv_frame_insn (gen_rtx_SET (fp, asm_src), |
1817 | gen_rtx_SET (fp, dwarf_src)); | |
36a05131 BS |
1818 | |
1819 | /* Access region C from the frame pointer. */ | |
1820 | accessor.base = fp; | |
1821 | accessor.base_offset = fp_offset; | |
1822 | } | |
1823 | ||
1824 | /* Set up region C. */ | |
1825 | frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT); | |
1826 | frv_frame_access_multi (&accessor, info, STACK_REGS_LR); | |
1827 | frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG); | |
1828 | ||
1829 | /* Set up region A. */ | |
1830 | frv_frame_access_standard_regs (FRV_STORE, info); | |
1831 | ||
1832 | /* If this is a varargs/stdarg function, issue a blockage to prevent the | |
1833 | scheduler from moving loads before the stores saving the registers. */ | |
1834 | if (info->stdarg_size > 0) | |
1835 | emit_insn (gen_blockage ()); | |
1836 | ||
87b483a1 | 1837 | /* Set up pic register/small data register for this function. */ |
ad516a74 | 1838 | if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table) |
36a05131 BS |
1839 | emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO), |
1840 | gen_rtx_REG (Pmode, LR_REGNO), | |
1841 | gen_rtx_REG (SImode, OFFSET_REGNO))); | |
1842 | } | |
1843 | ||
1844 | \f | |
1845 | /* Under frv, all of the work is done via frv_expand_epilogue, but | |
839a4992 | 1846 | this function provides a convenient place to do cleanup. */ |
36a05131 BS |
1847 | |
1848 | static void | |
42776416 | 1849 | frv_function_epilogue (FILE *) |
36a05131 BS |
1850 | { |
1851 | frv_stack_cache = (frv_stack_t *)0; | |
1852 | ||
87b483a1 | 1853 | /* Zap last used registers for conditional execution. */ |
fad205ff | 1854 | memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg)); |
36a05131 | 1855 | |
87b483a1 | 1856 | /* Release the bitmap of created insns. */ |
7b210806 | 1857 | BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap); |
36a05131 BS |
1858 | } |
1859 | ||
1860 | \f | |
1861 | /* Called after register allocation to add any instructions needed for the | |
43aa4e05 | 1862 | epilogue. Using an epilogue insn is favored compared to putting all of the |
b88cf82e KH |
1863 | instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since |
1864 | it allows the scheduler to intermix instructions with the saves of | |
1865 | the caller saved registers. In some cases, it might be necessary | |
1866 | to emit a barrier instruction as the last insn to prevent such | |
c557edf4 | 1867 | scheduling. */ |
36a05131 BS |
1868 | |
1869 | void | |
764678d1 | 1870 | frv_expand_epilogue (bool emit_return) |
36a05131 BS |
1871 | { |
1872 | frv_stack_t *info = frv_stack_info (); | |
1873 | rtx fp = frame_pointer_rtx; | |
1874 | rtx sp = stack_pointer_rtx; | |
1875 | rtx return_addr; | |
1876 | int fp_offset; | |
1877 | ||
1878 | fp_offset = info->reg_offset[FRAME_POINTER_REGNUM]; | |
1879 | ||
1880 | /* Restore the stack pointer to its original value if alloca or the like | |
1881 | is used. */ | |
416ff32e | 1882 | if (! crtl->sp_is_unchanging) |
36a05131 BS |
1883 | emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset))); |
1884 | ||
1885 | /* Restore the callee-saved registers that were used in this function. */ | |
1886 | frv_frame_access_standard_regs (FRV_LOAD, info); | |
1887 | ||
1888 | /* Set RETURN_ADDR to the address we should return to. Set it to NULL if | |
1889 | no return instruction should be emitted. */ | |
764678d1 | 1890 | if (info->save_p[LR_REGNO]) |
36a05131 BS |
1891 | { |
1892 | int lr_offset; | |
1893 | rtx mem; | |
1894 | ||
1895 | /* Use the same method to access the link register's slot as we did in | |
1896 | the prologue. In other words, use the frame pointer if available, | |
1897 | otherwise use the stack pointer. | |
1898 | ||
1899 | LR_OFFSET is the offset of the link register's slot from the start | |
1900 | of the frame and MEM is a memory rtx for it. */ | |
1901 | lr_offset = info->reg_offset[LR_REGNO]; | |
1902 | if (frame_pointer_needed) | |
1903 | mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset); | |
1904 | else | |
1905 | mem = frv_frame_mem (Pmode, sp, lr_offset); | |
1906 | ||
1907 | /* Load the old link register into a GPR. */ | |
1908 | return_addr = gen_rtx_REG (Pmode, TEMP_REGNO); | |
f7df4a84 | 1909 | emit_insn (gen_rtx_SET (return_addr, mem)); |
36a05131 BS |
1910 | } |
1911 | else | |
1912 | return_addr = gen_rtx_REG (Pmode, LR_REGNO); | |
1913 | ||
1914 | /* Restore the old frame pointer. Emit a USE afterwards to make sure | |
1915 | the load is preserved. */ | |
1916 | if (frame_pointer_needed) | |
1917 | { | |
f7df4a84 | 1918 | emit_insn (gen_rtx_SET (fp, gen_rtx_MEM (Pmode, fp))); |
c41c1387 | 1919 | emit_use (fp); |
36a05131 BS |
1920 | } |
1921 | ||
1922 | /* Deallocate the stack frame. */ | |
1923 | if (info->total_size != 0) | |
1924 | { | |
1925 | rtx offset = frv_frame_offset_rtx (info->total_size); | |
1926 | emit_insn (gen_stack_adjust (sp, sp, offset)); | |
1927 | } | |
1928 | ||
1929 | /* If this function uses eh_return, add the final stack adjustment now. */ | |
e3b5732b | 1930 | if (crtl->calls_eh_return) |
36a05131 BS |
1931 | emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX)); |
1932 | ||
764678d1 | 1933 | if (emit_return) |
36a05131 | 1934 | emit_jump_insn (gen_epilogue_return (return_addr)); |
764678d1 AO |
1935 | else |
1936 | { | |
1937 | rtx lr = return_addr; | |
1938 | ||
1939 | if (REGNO (return_addr) != LR_REGNO) | |
1940 | { | |
1941 | lr = gen_rtx_REG (Pmode, LR_REGNO); | |
1942 | emit_move_insn (lr, return_addr); | |
1943 | } | |
1944 | ||
c41c1387 | 1945 | emit_use (lr); |
764678d1 | 1946 | } |
36a05131 BS |
1947 | } |
1948 | ||
1949 | \f | |
b88cf82e | 1950 | /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */ |
36a05131 | 1951 | |
c590b625 | 1952 | static void |
f2206911 KC |
1953 | frv_asm_output_mi_thunk (FILE *file, |
1954 | tree thunk_fndecl ATTRIBUTE_UNUSED, | |
1955 | HOST_WIDE_INT delta, | |
1956 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
1957 | tree function) | |
36a05131 BS |
1958 | { |
1959 | const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0); | |
1960 | const char *name_arg0 = reg_names[FIRST_ARG_REGNUM]; | |
1961 | const char *name_jmp = reg_names[JUMP_REGNO]; | |
c557edf4 | 1962 | const char *parallel = (frv_issue_rate () > 1 ? ".p" : ""); |
36a05131 | 1963 | |
87b483a1 | 1964 | /* Do the add using an addi if possible. */ |
2f5b1308 | 1965 | if (IN_RANGE (delta, -2048, 2047)) |
eb0424da | 1966 | fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0); |
36a05131 BS |
1967 | else |
1968 | { | |
4a0a75dd KG |
1969 | const char *const name_add = reg_names[TEMP_REGNO]; |
1970 | fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n", | |
1971 | parallel, delta, name_add); | |
1972 | fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n", | |
1973 | delta, name_add); | |
36a05131 BS |
1974 | fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0); |
1975 | } | |
1976 | ||
34208acf AO |
1977 | if (TARGET_FDPIC) |
1978 | { | |
1979 | const char *name_pic = reg_names[FDPIC_REGNO]; | |
1980 | name_jmp = reg_names[FDPIC_FPTR_REGNO]; | |
1981 | ||
1982 | if (flag_pic != 1) | |
1983 | { | |
1984 | fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel); | |
1985 | assemble_name (file, name_func); | |
1986 | fprintf (file, "),%s\n", name_jmp); | |
1987 | ||
1988 | fprintf (file, "\tsetlo #gotofffuncdesclo("); | |
1989 | assemble_name (file, name_func); | |
1990 | fprintf (file, "),%s\n", name_jmp); | |
1991 | ||
1992 | fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp); | |
1993 | } | |
1994 | else | |
1995 | { | |
1996 | fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic); | |
1997 | assemble_name (file, name_func); | |
1998 | fprintf (file, "\t)), %s\n", name_jmp); | |
1999 | } | |
2000 | } | |
2001 | else if (!flag_pic) | |
36a05131 BS |
2002 | { |
2003 | fprintf (file, "\tsethi%s #hi(", parallel); | |
2004 | assemble_name (file, name_func); | |
2005 | fprintf (file, "),%s\n", name_jmp); | |
2006 | ||
2007 | fprintf (file, "\tsetlo #lo("); | |
2008 | assemble_name (file, name_func); | |
2009 | fprintf (file, "),%s\n", name_jmp); | |
2010 | } | |
2011 | else | |
2012 | { | |
2013 | /* Use JUMP_REGNO as a temporary PIC register. */ | |
2014 | const char *name_lr = reg_names[LR_REGNO]; | |
2015 | const char *name_gppic = name_jmp; | |
2016 | const char *name_tmp = reg_names[TEMP_REGNO]; | |
2017 | ||
2018 | fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp); | |
2019 | fprintf (file, "\tcall 1f\n"); | |
2020 | fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic); | |
2021 | fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr); | |
2022 | fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp); | |
2023 | fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp); | |
2024 | fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic); | |
2025 | ||
2026 | fprintf (file, "\tsethi%s #gprelhi(", parallel); | |
2027 | assemble_name (file, name_func); | |
2028 | fprintf (file, "),%s\n", name_tmp); | |
2029 | ||
2030 | fprintf (file, "\tsetlo #gprello("); | |
2031 | assemble_name (file, name_func); | |
2032 | fprintf (file, "),%s\n", name_tmp); | |
2033 | ||
2034 | fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp); | |
2035 | } | |
2036 | ||
87b483a1 | 2037 | /* Jump to the function address. */ |
36a05131 BS |
2038 | fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]); |
2039 | } | |
2040 | ||
2041 | \f | |
36a05131 | 2042 | |
87b483a1 | 2043 | /* On frv, create a frame whenever we need to create stack. */ |
36a05131 | 2044 | |
b52b1749 | 2045 | static bool |
f2206911 | 2046 | frv_frame_pointer_required (void) |
36a05131 | 2047 | { |
34208acf AO |
2048 | /* If we forgoing the usual linkage requirements, we only need |
2049 | a frame pointer if the stack pointer might change. */ | |
2050 | if (!TARGET_LINKED_FP) | |
416ff32e | 2051 | return !crtl->sp_is_unchanging; |
34208acf | 2052 | |
416ff32e | 2053 | if (! crtl->is_leaf) |
b52b1749 | 2054 | return true; |
36a05131 BS |
2055 | |
2056 | if (get_frame_size () != 0) | |
b52b1749 | 2057 | return true; |
36a05131 BS |
2058 | |
2059 | if (cfun->stdarg) | |
b52b1749 | 2060 | return true; |
36a05131 | 2061 | |
416ff32e | 2062 | if (!crtl->sp_is_unchanging) |
b52b1749 | 2063 | return true; |
36a05131 | 2064 | |
ad516a74 | 2065 | if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table) |
b52b1749 | 2066 | return true; |
36a05131 BS |
2067 | |
2068 | if (profile_flag) | |
b52b1749 | 2069 | return true; |
36a05131 BS |
2070 | |
2071 | if (cfun->machine->frame_needed) | |
b52b1749 | 2072 | return true; |
36a05131 | 2073 | |
b52b1749 | 2074 | return false; |
36a05131 BS |
2075 | } |
2076 | ||
2077 | \f | |
7b5cbb57 AS |
2078 | /* Worker function for TARGET_CAN_ELIMINATE. */ |
2079 | ||
2080 | bool | |
2081 | frv_can_eliminate (const int from, const int to) | |
2082 | { | |
2083 | return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM | |
2084 | ? ! frame_pointer_needed | |
2085 | : true); | |
2086 | } | |
2087 | ||
53680238 BE |
2088 | /* This function returns the initial difference between the specified |
2089 | pair of registers. */ | |
36a05131 BS |
2090 | |
2091 | /* See frv_stack_info for more details on the frv stack frame. */ | |
2092 | ||
2093 | int | |
f2206911 | 2094 | frv_initial_elimination_offset (int from, int to) |
36a05131 BS |
2095 | { |
2096 | frv_stack_t *info = frv_stack_info (); | |
2097 | int ret = 0; | |
2098 | ||
2099 | if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM) | |
2100 | ret = info->total_size - info->pretend_size; | |
2101 | ||
2102 | else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM) | |
88d6a75f | 2103 | ret = info->reg_offset[FRAME_POINTER_REGNUM]; |
36a05131 BS |
2104 | |
2105 | else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM) | |
2106 | ret = (info->total_size | |
2107 | - info->reg_offset[FRAME_POINTER_REGNUM] | |
2108 | - info->pretend_size); | |
2109 | ||
2110 | else | |
44e91694 | 2111 | gcc_unreachable (); |
36a05131 BS |
2112 | |
2113 | if (TARGET_DEBUG_STACK) | |
2114 | fprintf (stderr, "Eliminate %s to %s by adding %d\n", | |
2115 | reg_names [from], reg_names[to], ret); | |
2116 | ||
2117 | return ret; | |
2118 | } | |
2119 | ||
2120 | \f | |
d8c2bed3 | 2121 | /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */ |
36a05131 | 2122 | |
d8c2bed3 | 2123 | static void |
d5cc9181 | 2124 | frv_setup_incoming_varargs (cumulative_args_t cum_v, |
ef4bddc2 | 2125 | machine_mode mode, |
f2206911 KC |
2126 | tree type ATTRIBUTE_UNUSED, |
2127 | int *pretend_size, | |
2128 | int second_time) | |
36a05131 | 2129 | { |
d5cc9181 JR |
2130 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
2131 | ||
36a05131 BS |
2132 | if (TARGET_DEBUG_ARG) |
2133 | fprintf (stderr, | |
2134 | "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n", | |
2135 | *cum, GET_MODE_NAME (mode), *pretend_size, second_time); | |
2136 | } | |
2137 | ||
2138 | \f | |
b88cf82e | 2139 | /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */ |
36a05131 | 2140 | |
8ac411c7 | 2141 | static rtx |
f2206911 | 2142 | frv_expand_builtin_saveregs (void) |
36a05131 BS |
2143 | { |
2144 | int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS; | |
2145 | ||
2146 | if (TARGET_DEBUG_ARG) | |
2147 | fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n", | |
2148 | offset); | |
2149 | ||
f1c25d3b | 2150 | return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset)); |
36a05131 BS |
2151 | } |
2152 | ||
2153 | \f | |
2154 | /* Expand __builtin_va_start to do the va_start macro. */ | |
2155 | ||
d7bd8aeb | 2156 | static void |
f2206911 | 2157 | frv_expand_builtin_va_start (tree valist, rtx nextarg) |
36a05131 BS |
2158 | { |
2159 | tree t; | |
7dd68986 | 2160 | int num = crtl->args.info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS; |
36a05131 BS |
2161 | |
2162 | nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, | |
2163 | GEN_INT (UNITS_PER_WORD * num)); | |
2164 | ||
2165 | if (TARGET_DEBUG_ARG) | |
2166 | { | |
2167 | fprintf (stderr, "va_start: args_info = %d, num = %d\n", | |
7dd68986 | 2168 | crtl->args.info, num); |
36a05131 BS |
2169 | |
2170 | debug_rtx (nextarg); | |
2171 | } | |
2172 | ||
726a989a | 2173 | t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, |
5be014d5 AP |
2174 | fold_convert (TREE_TYPE (valist), |
2175 | make_tree (sizetype, nextarg))); | |
36a05131 BS |
2176 | TREE_SIDE_EFFECTS (t) = 1; |
2177 | ||
2178 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2179 | } | |
2180 | ||
36a05131 BS |
2181 | \f |
2182 | /* Expand a block move operation, and return 1 if successful. Return 0 | |
2183 | if we should let the compiler generate normal code. | |
2184 | ||
2185 | operands[0] is the destination | |
2186 | operands[1] is the source | |
2187 | operands[2] is the length | |
2188 | operands[3] is the alignment */ | |
2189 | ||
2190 | /* Maximum number of loads to do before doing the stores */ | |
2191 | #ifndef MAX_MOVE_REG | |
2192 | #define MAX_MOVE_REG 4 | |
2193 | #endif | |
2194 | ||
2195 | /* Maximum number of total loads to do. */ | |
2196 | #ifndef TOTAL_MOVE_REG | |
2197 | #define TOTAL_MOVE_REG 8 | |
2198 | #endif | |
2199 | ||
2200 | int | |
f2206911 | 2201 | frv_expand_block_move (rtx operands[]) |
36a05131 BS |
2202 | { |
2203 | rtx orig_dest = operands[0]; | |
2204 | rtx orig_src = operands[1]; | |
2205 | rtx bytes_rtx = operands[2]; | |
2206 | rtx align_rtx = operands[3]; | |
2207 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); | |
2208 | int align; | |
2209 | int bytes; | |
2210 | int offset; | |
2211 | int num_reg; | |
2212 | int i; | |
2213 | rtx src_reg; | |
2214 | rtx dest_reg; | |
2215 | rtx src_addr; | |
2216 | rtx dest_addr; | |
2217 | rtx src_mem; | |
2218 | rtx dest_mem; | |
2219 | rtx tmp_reg; | |
2220 | rtx stores[MAX_MOVE_REG]; | |
2221 | int move_bytes; | |
ef4bddc2 | 2222 | machine_mode mode; |
36a05131 | 2223 | |
87b483a1 | 2224 | /* If this is not a fixed size move, just call memcpy. */ |
36a05131 BS |
2225 | if (! constp) |
2226 | return FALSE; | |
2227 | ||
44e91694 NS |
2228 | /* This should be a fixed size alignment. */ |
2229 | gcc_assert (GET_CODE (align_rtx) == CONST_INT); | |
36a05131 BS |
2230 | |
2231 | align = INTVAL (align_rtx); | |
2232 | ||
2233 | /* Anything to move? */ | |
2234 | bytes = INTVAL (bytes_rtx); | |
2235 | if (bytes <= 0) | |
2236 | return TRUE; | |
2237 | ||
2238 | /* Don't support real large moves. */ | |
2239 | if (bytes > TOTAL_MOVE_REG*align) | |
2240 | return FALSE; | |
2241 | ||
2242 | /* Move the address into scratch registers. */ | |
2243 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); | |
2244 | src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); | |
2245 | ||
2246 | num_reg = offset = 0; | |
2247 | for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) | |
2248 | { | |
87b483a1 | 2249 | /* Calculate the correct offset for src/dest. */ |
36a05131 BS |
2250 | if (offset == 0) |
2251 | { | |
2252 | src_addr = src_reg; | |
2253 | dest_addr = dest_reg; | |
2254 | } | |
2255 | else | |
2256 | { | |
0a81f074 RS |
2257 | src_addr = plus_constant (Pmode, src_reg, offset); |
2258 | dest_addr = plus_constant (Pmode, dest_reg, offset); | |
36a05131 BS |
2259 | } |
2260 | ||
2261 | /* Generate the appropriate load and store, saving the stores | |
2262 | for later. */ | |
2263 | if (bytes >= 4 && align >= 4) | |
2264 | mode = SImode; | |
2265 | else if (bytes >= 2 && align >= 2) | |
2266 | mode = HImode; | |
2267 | else | |
2268 | mode = QImode; | |
2269 | ||
2270 | move_bytes = GET_MODE_SIZE (mode); | |
2271 | tmp_reg = gen_reg_rtx (mode); | |
2272 | src_mem = change_address (orig_src, mode, src_addr); | |
2273 | dest_mem = change_address (orig_dest, mode, dest_addr); | |
f7df4a84 RS |
2274 | emit_insn (gen_rtx_SET (tmp_reg, src_mem)); |
2275 | stores[num_reg++] = gen_rtx_SET (dest_mem, tmp_reg); | |
36a05131 BS |
2276 | |
2277 | if (num_reg >= MAX_MOVE_REG) | |
2278 | { | |
2279 | for (i = 0; i < num_reg; i++) | |
2280 | emit_insn (stores[i]); | |
2281 | num_reg = 0; | |
2282 | } | |
2283 | } | |
2284 | ||
2285 | for (i = 0; i < num_reg; i++) | |
2286 | emit_insn (stores[i]); | |
2287 | ||
2288 | return TRUE; | |
2289 | } | |
2290 | ||
2291 | \f | |
2292 | /* Expand a block clear operation, and return 1 if successful. Return 0 | |
2293 | if we should let the compiler generate normal code. | |
2294 | ||
2295 | operands[0] is the destination | |
2296 | operands[1] is the length | |
57e84f18 | 2297 | operands[3] is the alignment */ |
36a05131 BS |
2298 | |
2299 | int | |
f2206911 | 2300 | frv_expand_block_clear (rtx operands[]) |
36a05131 BS |
2301 | { |
2302 | rtx orig_dest = operands[0]; | |
2303 | rtx bytes_rtx = operands[1]; | |
57e84f18 | 2304 | rtx align_rtx = operands[3]; |
36a05131 BS |
2305 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
2306 | int align; | |
2307 | int bytes; | |
2308 | int offset; | |
36a05131 BS |
2309 | rtx dest_reg; |
2310 | rtx dest_addr; | |
2311 | rtx dest_mem; | |
2312 | int clear_bytes; | |
ef4bddc2 | 2313 | machine_mode mode; |
36a05131 | 2314 | |
87b483a1 | 2315 | /* If this is not a fixed size move, just call memcpy. */ |
36a05131 BS |
2316 | if (! constp) |
2317 | return FALSE; | |
2318 | ||
44e91694 NS |
2319 | /* This should be a fixed size alignment. */ |
2320 | gcc_assert (GET_CODE (align_rtx) == CONST_INT); | |
36a05131 BS |
2321 | |
2322 | align = INTVAL (align_rtx); | |
2323 | ||
2324 | /* Anything to move? */ | |
2325 | bytes = INTVAL (bytes_rtx); | |
2326 | if (bytes <= 0) | |
2327 | return TRUE; | |
2328 | ||
2329 | /* Don't support real large clears. */ | |
2330 | if (bytes > TOTAL_MOVE_REG*align) | |
2331 | return FALSE; | |
2332 | ||
2333 | /* Move the address into a scratch register. */ | |
2334 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); | |
2335 | ||
5c5e8419 | 2336 | offset = 0; |
36a05131 BS |
2337 | for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes)) |
2338 | { | |
87b483a1 | 2339 | /* Calculate the correct offset for src/dest. */ |
36a05131 BS |
2340 | dest_addr = ((offset == 0) |
2341 | ? dest_reg | |
0a81f074 | 2342 | : plus_constant (Pmode, dest_reg, offset)); |
36a05131 | 2343 | |
87b483a1 | 2344 | /* Generate the appropriate store of gr0. */ |
36a05131 BS |
2345 | if (bytes >= 4 && align >= 4) |
2346 | mode = SImode; | |
2347 | else if (bytes >= 2 && align >= 2) | |
2348 | mode = HImode; | |
2349 | else | |
2350 | mode = QImode; | |
2351 | ||
2352 | clear_bytes = GET_MODE_SIZE (mode); | |
2353 | dest_mem = change_address (orig_dest, mode, dest_addr); | |
f7df4a84 | 2354 | emit_insn (gen_rtx_SET (dest_mem, const0_rtx)); |
36a05131 BS |
2355 | } |
2356 | ||
2357 | return TRUE; | |
2358 | } | |
2359 | ||
2360 | \f | |
2361 | /* The following variable is used to output modifiers of assembler | |
87b483a1 | 2362 | code of the current output insn. */ |
36a05131 BS |
2363 | |
2364 | static rtx *frv_insn_operands; | |
2365 | ||
2366 | /* The following function is used to add assembler insn code suffix .p | |
87b483a1 | 2367 | if it is necessary. */ |
36a05131 BS |
2368 | |
2369 | const char * | |
f2206911 | 2370 | frv_asm_output_opcode (FILE *f, const char *ptr) |
36a05131 BS |
2371 | { |
2372 | int c; | |
2373 | ||
c557edf4 | 2374 | if (frv_insn_packing_flag <= 0) |
36a05131 BS |
2375 | return ptr; |
2376 | ||
2377 | for (; *ptr && *ptr != ' ' && *ptr != '\t';) | |
2378 | { | |
2379 | c = *ptr++; | |
2380 | if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z') | |
2381 | || (*ptr >= 'A' && *ptr <= 'Z'))) | |
2382 | { | |
2383 | int letter = *ptr++; | |
2384 | ||
2385 | c = atoi (ptr); | |
2386 | frv_print_operand (f, frv_insn_operands [c], letter); | |
2387 | while ((c = *ptr) >= '0' && c <= '9') | |
2388 | ptr++; | |
2389 | } | |
2390 | else | |
2391 | fputc (c, f); | |
2392 | } | |
2393 | ||
c557edf4 | 2394 | fprintf (f, ".p"); |
36a05131 BS |
2395 | |
2396 | return ptr; | |
2397 | } | |
2398 | ||
c557edf4 RS |
2399 | /* Set up the packing bit for the current output insn. Note that this |
2400 | function is not called for asm insns. */ | |
36a05131 BS |
2401 | |
2402 | void | |
647d790d | 2403 | frv_final_prescan_insn (rtx_insn *insn, rtx *opvec, |
c557edf4 | 2404 | int noperands ATTRIBUTE_UNUSED) |
36a05131 | 2405 | { |
c557edf4 | 2406 | if (INSN_P (insn)) |
36a05131 | 2407 | { |
c557edf4 RS |
2408 | if (frv_insn_packing_flag >= 0) |
2409 | { | |
2410 | frv_insn_operands = opvec; | |
2411 | frv_insn_packing_flag = PACKING_FLAG_P (insn); | |
2412 | } | |
2413 | else if (recog_memoized (insn) >= 0 | |
2414 | && get_attr_acc_group (insn) == ACC_GROUP_ODD) | |
2415 | /* Packing optimizations have been disabled, but INSN can only | |
2416 | be issued in M1. Insert an mnop in M0. */ | |
2417 | fprintf (asm_out_file, "\tmnop.p\n"); | |
36a05131 | 2418 | } |
36a05131 BS |
2419 | } |
2420 | ||
2421 | ||
2422 | \f | |
2423 | /* A C expression whose value is RTL representing the address in a stack frame | |
2424 | where the pointer to the caller's frame is stored. Assume that FRAMEADDR is | |
2425 | an RTL expression for the address of the stack frame itself. | |
2426 | ||
2427 | If you don't define this macro, the default is to return the value of | |
2428 | FRAMEADDR--that is, the stack frame address is also the address of the stack | |
2429 | word that points to the previous frame. */ | |
2430 | ||
2431 | /* The default is correct, but we need to make sure the frame gets created. */ | |
2432 | rtx | |
f2206911 | 2433 | frv_dynamic_chain_address (rtx frame) |
36a05131 BS |
2434 | { |
2435 | cfun->machine->frame_needed = 1; | |
2436 | return frame; | |
2437 | } | |
2438 | ||
2439 | ||
2440 | /* A C expression whose value is RTL representing the value of the return | |
2441 | address for the frame COUNT steps up from the current frame, after the | |
2442 | prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame | |
2443 | pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is | |
2444 | defined. | |
2445 | ||
2446 | The value of the expression must always be the correct address when COUNT is | |
2447 | zero, but may be `NULL_RTX' if there is not way to determine the return | |
2448 | address of other frames. */ | |
2449 | ||
2450 | rtx | |
34208acf | 2451 | frv_return_addr_rtx (int count, rtx frame) |
36a05131 | 2452 | { |
34208acf AO |
2453 | if (count != 0) |
2454 | return const0_rtx; | |
36a05131 | 2455 | cfun->machine->frame_needed = 1; |
0a81f074 | 2456 | return gen_rtx_MEM (Pmode, plus_constant (Pmode, frame, 8)); |
36a05131 BS |
2457 | } |
2458 | ||
2459 | /* Given a memory reference MEMREF, interpret the referenced memory as | |
2460 | an array of MODE values, and return a reference to the element | |
2461 | specified by INDEX. Assume that any pre-modification implicit in | |
2462 | MEMREF has already happened. | |
2463 | ||
2464 | MEMREF must be a legitimate operand for modes larger than SImode. | |
c6c3dba9 | 2465 | frv_legitimate_address_p forbids register+register addresses, which |
36a05131 BS |
2466 | this function cannot handle. */ |
2467 | rtx | |
ef4bddc2 | 2468 | frv_index_memory (rtx memref, machine_mode mode, int index) |
36a05131 BS |
2469 | { |
2470 | rtx base = XEXP (memref, 0); | |
2471 | if (GET_CODE (base) == PRE_MODIFY) | |
2472 | base = XEXP (base, 0); | |
2473 | return change_address (memref, mode, | |
0a81f074 RS |
2474 | plus_constant (Pmode, base, |
2475 | index * GET_MODE_SIZE (mode))); | |
36a05131 BS |
2476 | } |
2477 | ||
2478 | \f | |
2479 | /* Print a memory address as an operand to reference that memory location. */ | |
0fb30cb7 | 2480 | static void |
cc8ca59e | 2481 | frv_print_operand_address (FILE * stream, machine_mode /* mode */, rtx x) |
36a05131 BS |
2482 | { |
2483 | if (GET_CODE (x) == MEM) | |
2484 | x = XEXP (x, 0); | |
2485 | ||
2486 | switch (GET_CODE (x)) | |
2487 | { | |
2488 | case REG: | |
2489 | fputs (reg_names [ REGNO (x)], stream); | |
2490 | return; | |
2491 | ||
2492 | case CONST_INT: | |
2493 | fprintf (stream, "%ld", (long) INTVAL (x)); | |
2494 | return; | |
2495 | ||
2496 | case SYMBOL_REF: | |
2497 | assemble_name (stream, XSTR (x, 0)); | |
2498 | return; | |
2499 | ||
2500 | case LABEL_REF: | |
2501 | case CONST: | |
2502 | output_addr_const (stream, x); | |
2503 | return; | |
2504 | ||
8d8256c1 NC |
2505 | case PLUS: |
2506 | /* Poorly constructed asm statements can trigger this alternative. | |
2507 | See gcc/testsuite/gcc.dg/asm-4.c for an example. */ | |
2508 | frv_print_operand_memory_reference (stream, x, 0); | |
2509 | return; | |
2510 | ||
36a05131 BS |
2511 | default: |
2512 | break; | |
2513 | } | |
2514 | ||
ab532386 | 2515 | fatal_insn ("bad insn to frv_print_operand_address:", x); |
36a05131 BS |
2516 | } |
2517 | ||
2518 | \f | |
2519 | static void | |
f2206911 | 2520 | frv_print_operand_memory_reference_reg (FILE * stream, rtx x) |
36a05131 BS |
2521 | { |
2522 | int regno = true_regnum (x); | |
2523 | if (GPR_P (regno)) | |
2524 | fputs (reg_names[regno], stream); | |
2525 | else | |
ab532386 | 2526 | fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x); |
36a05131 BS |
2527 | } |
2528 | ||
2529 | /* Print a memory reference suitable for the ld/st instructions. */ | |
2530 | ||
2531 | static void | |
f2206911 | 2532 | frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset) |
36a05131 | 2533 | { |
34208acf | 2534 | struct frv_unspec unspec; |
36a05131 BS |
2535 | rtx x0 = NULL_RTX; |
2536 | rtx x1 = NULL_RTX; | |
2537 | ||
2538 | switch (GET_CODE (x)) | |
2539 | { | |
2540 | case SUBREG: | |
2541 | case REG: | |
2542 | x0 = x; | |
2543 | break; | |
2544 | ||
2545 | case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */ | |
2546 | x0 = XEXP (x, 0); | |
2547 | x1 = XEXP (XEXP (x, 1), 1); | |
2548 | break; | |
2549 | ||
2550 | case CONST_INT: | |
2551 | x1 = x; | |
2552 | break; | |
2553 | ||
2554 | case PLUS: | |
2555 | x0 = XEXP (x, 0); | |
2556 | x1 = XEXP (x, 1); | |
2557 | if (GET_CODE (x0) == CONST_INT) | |
2558 | { | |
2559 | x0 = XEXP (x, 1); | |
2560 | x1 = XEXP (x, 0); | |
2561 | } | |
2562 | break; | |
2563 | ||
2564 | default: | |
ab532386 | 2565 | fatal_insn ("bad insn to frv_print_operand_memory_reference:", x); |
36a05131 BS |
2566 | break; |
2567 | ||
2568 | } | |
2569 | ||
2570 | if (addr_offset) | |
2571 | { | |
2572 | if (!x1) | |
2573 | x1 = const0_rtx; | |
2574 | else if (GET_CODE (x1) != CONST_INT) | |
ab532386 | 2575 | fatal_insn ("bad insn to frv_print_operand_memory_reference:", x); |
36a05131 BS |
2576 | } |
2577 | ||
2578 | fputs ("@(", stream); | |
2579 | if (!x0) | |
2580 | fputs (reg_names[GPR_R0], stream); | |
2581 | else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG) | |
2582 | frv_print_operand_memory_reference_reg (stream, x0); | |
2583 | else | |
ab532386 | 2584 | fatal_insn ("bad insn to frv_print_operand_memory_reference:", x); |
36a05131 BS |
2585 | |
2586 | fputs (",", stream); | |
2587 | if (!x1) | |
2588 | fputs (reg_names [GPR_R0], stream); | |
2589 | ||
2590 | else | |
2591 | { | |
2592 | switch (GET_CODE (x1)) | |
2593 | { | |
2594 | case SUBREG: | |
2595 | case REG: | |
2596 | frv_print_operand_memory_reference_reg (stream, x1); | |
2597 | break; | |
2598 | ||
2599 | case CONST_INT: | |
2600 | fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset)); | |
2601 | break; | |
2602 | ||
36a05131 | 2603 | case CONST: |
34208acf | 2604 | if (!frv_const_unspec_p (x1, &unspec)) |
ab532386 | 2605 | fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1); |
34208acf | 2606 | frv_output_const_unspec (stream, &unspec); |
36a05131 BS |
2607 | break; |
2608 | ||
2609 | default: | |
ab532386 | 2610 | fatal_insn ("bad insn to frv_print_operand_memory_reference:", x); |
36a05131 BS |
2611 | } |
2612 | } | |
2613 | ||
2614 | fputs (")", stream); | |
2615 | } | |
2616 | ||
2617 | \f | |
2618 | /* Return 2 for likely branches and 0 for non-likely branches */ | |
2619 | ||
2620 | #define FRV_JUMP_LIKELY 2 | |
2621 | #define FRV_JUMP_NOT_LIKELY 0 | |
2622 | ||
2623 | static int | |
68a1a6c0 | 2624 | frv_print_operand_jump_hint (rtx_insn *insn) |
36a05131 BS |
2625 | { |
2626 | rtx note; | |
2627 | rtx labelref; | |
2628 | int ret; | |
36a05131 BS |
2629 | enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN; |
2630 | ||
b64925dc | 2631 | gcc_assert (JUMP_P (insn)); |
36a05131 BS |
2632 | |
2633 | /* Assume any non-conditional jump is likely. */ | |
2634 | if (! any_condjump_p (insn)) | |
2635 | ret = FRV_JUMP_LIKELY; | |
2636 | ||
2637 | else | |
2638 | { | |
2639 | labelref = condjump_label (insn); | |
2640 | if (labelref) | |
2641 | { | |
2642 | rtx label = XEXP (labelref, 0); | |
2643 | jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label)) | |
2644 | ? BACKWARD | |
2645 | : FORWARD); | |
2646 | } | |
2647 | ||
2648 | note = find_reg_note (insn, REG_BR_PROB, 0); | |
2649 | if (!note) | |
2650 | ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY); | |
2651 | ||
2652 | else | |
2653 | { | |
5fa396ad JH |
2654 | ret = ((profile_probability::from_reg_br_prob_note (XINT (note, 0)) |
2655 | >= profile_probability::even ()) | |
36a05131 BS |
2656 | ? FRV_JUMP_LIKELY |
2657 | : FRV_JUMP_NOT_LIKELY); | |
2658 | } | |
2659 | } | |
2660 | ||
2661 | #if 0 | |
2662 | if (TARGET_DEBUG) | |
2663 | { | |
2664 | char *direction; | |
2665 | ||
2666 | switch (jump_type) | |
2667 | { | |
2668 | default: | |
2669 | case UNKNOWN: direction = "unknown jump direction"; break; | |
2670 | case BACKWARD: direction = "jump backward"; break; | |
2671 | case FORWARD: direction = "jump forward"; break; | |
2672 | } | |
2673 | ||
2674 | fprintf (stderr, | |
e5af9ddd | 2675 | "%s: uid %ld, %s, probability = %d, max prob. = %d, hint = %d\n", |
36a05131 | 2676 | IDENTIFIER_POINTER (DECL_NAME (current_function_decl)), |
e5af9ddd RS |
2677 | (long)INSN_UID (insn), direction, prob, |
2678 | REG_BR_PROB_BASE, ret); | |
36a05131 BS |
2679 | } |
2680 | #endif | |
2681 | ||
2682 | return ret; | |
2683 | } | |
2684 | ||
2685 | \f | |
036ff63f RS |
2686 | /* Return the comparison operator to use for CODE given that the ICC |
2687 | register is OP0. */ | |
2688 | ||
2689 | static const char * | |
2690 | comparison_string (enum rtx_code code, rtx op0) | |
2691 | { | |
2692 | bool is_nz_p = GET_MODE (op0) == CC_NZmode; | |
2693 | switch (code) | |
2694 | { | |
4f4bf94e | 2695 | default: output_operand_lossage ("bad condition code"); return ""; |
036ff63f RS |
2696 | case EQ: return "eq"; |
2697 | case NE: return "ne"; | |
2698 | case LT: return is_nz_p ? "n" : "lt"; | |
2699 | case LE: return "le"; | |
2700 | case GT: return "gt"; | |
2701 | case GE: return is_nz_p ? "p" : "ge"; | |
2702 | case LTU: return is_nz_p ? "no" : "c"; | |
2703 | case LEU: return is_nz_p ? "eq" : "ls"; | |
2704 | case GTU: return is_nz_p ? "ne" : "hi"; | |
2705 | case GEU: return is_nz_p ? "ra" : "nc"; | |
2706 | } | |
2707 | } | |
2708 | ||
43aa4e05 | 2709 | /* Print an operand to an assembler instruction. |
36a05131 BS |
2710 | |
2711 | `%' followed by a letter and a digit says to output an operand in an | |
0fb30cb7 NF |
2712 | alternate fashion. Four letters have standard, built-in meanings |
2713 | described below. The hook `TARGET_PRINT_OPERAND' can define | |
2714 | additional letters with nonstandard meanings. | |
36a05131 BS |
2715 | |
2716 | `%cDIGIT' can be used to substitute an operand that is a constant value | |
2717 | without the syntax that normally indicates an immediate operand. | |
2718 | ||
2719 | `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated | |
2720 | before printing. | |
2721 | ||
2722 | `%aDIGIT' can be used to substitute an operand as if it were a memory | |
2723 | reference, with the actual operand treated as the address. This may be | |
2724 | useful when outputting a "load address" instruction, because often the | |
2725 | assembler syntax for such an instruction requires you to write the operand | |
2726 | as if it were a memory reference. | |
2727 | ||
2728 | `%lDIGIT' is used to substitute a `label_ref' into a jump instruction. | |
2729 | ||
2730 | `%=' outputs a number which is unique to each instruction in the entire | |
2731 | compilation. This is useful for making local labels to be referred to more | |
2732 | than once in a single template that generates multiple assembler | |
2733 | instructions. | |
2734 | ||
0fb30cb7 NF |
2735 | `%' followed by a punctuation character specifies a substitution that |
2736 | does not use an operand. Only one case is standard: `%%' outputs a | |
2737 | `%' into the assembler code. Other nonstandard cases can be defined | |
2738 | in the `TARGET_PRINT_OPERAND' hook. You must also define which | |
2739 | punctuation characters are valid with the | |
2740 | `TARGET_PRINT_OPERAND_PUNCT_VALID_P' hook. */ | |
36a05131 | 2741 | |
0fb30cb7 | 2742 | static void |
f2206911 | 2743 | frv_print_operand (FILE * file, rtx x, int code) |
36a05131 | 2744 | { |
34208acf | 2745 | struct frv_unspec unspec; |
36a05131 BS |
2746 | HOST_WIDE_INT value; |
2747 | int offset; | |
2748 | ||
0a2aaacc | 2749 | if (code != 0 && !ISALPHA (code)) |
36a05131 BS |
2750 | value = 0; |
2751 | ||
2752 | else if (GET_CODE (x) == CONST_INT) | |
2753 | value = INTVAL (x); | |
2754 | ||
2755 | else if (GET_CODE (x) == CONST_DOUBLE) | |
2756 | { | |
2757 | if (GET_MODE (x) == SFmode) | |
2758 | { | |
36a05131 BS |
2759 | long l; |
2760 | ||
34a72c33 | 2761 | REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), l); |
36a05131 BS |
2762 | value = l; |
2763 | } | |
2764 | ||
2765 | else if (GET_MODE (x) == VOIDmode) | |
2766 | value = CONST_DOUBLE_LOW (x); | |
2767 | ||
2768 | else | |
ab532386 | 2769 | fatal_insn ("bad insn in frv_print_operand, bad const_double", x); |
36a05131 BS |
2770 | } |
2771 | ||
2772 | else | |
2773 | value = 0; | |
2774 | ||
2775 | switch (code) | |
2776 | { | |
2777 | ||
2778 | case '.': | |
87b483a1 | 2779 | /* Output r0. */ |
36a05131 BS |
2780 | fputs (reg_names[GPR_R0], file); |
2781 | break; | |
2782 | ||
2783 | case '#': | |
2784 | fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn)); | |
2785 | break; | |
2786 | ||
0f6e5d45 | 2787 | case '@': |
87b483a1 | 2788 | /* Output small data area base register (gr16). */ |
36a05131 BS |
2789 | fputs (reg_names[SDA_BASE_REG], file); |
2790 | break; | |
2791 | ||
2792 | case '~': | |
87b483a1 | 2793 | /* Output pic register (gr17). */ |
36a05131 BS |
2794 | fputs (reg_names[PIC_REGNO], file); |
2795 | break; | |
2796 | ||
2797 | case '*': | |
87b483a1 | 2798 | /* Output the temporary integer CCR register. */ |
36a05131 BS |
2799 | fputs (reg_names[ICR_TEMP], file); |
2800 | break; | |
2801 | ||
2802 | case '&': | |
87b483a1 | 2803 | /* Output the temporary integer CC register. */ |
36a05131 BS |
2804 | fputs (reg_names[ICC_TEMP], file); |
2805 | break; | |
2806 | ||
87b483a1 | 2807 | /* case 'a': print an address. */ |
36a05131 BS |
2808 | |
2809 | case 'C': | |
87b483a1 | 2810 | /* Print appropriate test for integer branch false operation. */ |
036ff63f RS |
2811 | fputs (comparison_string (reverse_condition (GET_CODE (x)), |
2812 | XEXP (x, 0)), file); | |
36a05131 BS |
2813 | break; |
2814 | ||
36a05131 | 2815 | case 'c': |
87b483a1 | 2816 | /* Print appropriate test for integer branch true operation. */ |
036ff63f | 2817 | fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file); |
36a05131 BS |
2818 | break; |
2819 | ||
2820 | case 'e': | |
2821 | /* Print 1 for a NE and 0 for an EQ to give the final argument | |
2822 | for a conditional instruction. */ | |
2823 | if (GET_CODE (x) == NE) | |
2824 | fputs ("1", file); | |
2825 | ||
2826 | else if (GET_CODE (x) == EQ) | |
2827 | fputs ("0", file); | |
2828 | ||
2829 | else | |
ab532386 | 2830 | fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x); |
36a05131 BS |
2831 | break; |
2832 | ||
2833 | case 'F': | |
87b483a1 | 2834 | /* Print appropriate test for floating point branch false operation. */ |
36a05131 BS |
2835 | switch (GET_CODE (x)) |
2836 | { | |
2837 | default: | |
ab532386 | 2838 | fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x); |
36a05131 BS |
2839 | |
2840 | case EQ: fputs ("ne", file); break; | |
2841 | case NE: fputs ("eq", file); break; | |
2842 | case LT: fputs ("uge", file); break; | |
2843 | case LE: fputs ("ug", file); break; | |
2844 | case GT: fputs ("ule", file); break; | |
2845 | case GE: fputs ("ul", file); break; | |
2846 | } | |
2847 | break; | |
2848 | ||
2849 | case 'f': | |
87b483a1 | 2850 | /* Print appropriate test for floating point branch true operation. */ |
36a05131 BS |
2851 | switch (GET_CODE (x)) |
2852 | { | |
2853 | default: | |
ab532386 | 2854 | fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x); |
36a05131 BS |
2855 | |
2856 | case EQ: fputs ("eq", file); break; | |
2857 | case NE: fputs ("ne", file); break; | |
2858 | case LT: fputs ("lt", file); break; | |
2859 | case LE: fputs ("le", file); break; | |
2860 | case GT: fputs ("gt", file); break; | |
2861 | case GE: fputs ("ge", file); break; | |
2862 | } | |
2863 | break; | |
2864 | ||
34208acf AO |
2865 | case 'g': |
2866 | /* Print appropriate GOT function. */ | |
2867 | if (GET_CODE (x) != CONST_INT) | |
ab532386 | 2868 | fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x); |
34208acf AO |
2869 | fputs (unspec_got_name (INTVAL (x)), file); |
2870 | break; | |
2871 | ||
36a05131 BS |
2872 | case 'I': |
2873 | /* Print 'i' if the operand is a constant, or is a memory reference that | |
87b483a1 | 2874 | adds a constant. */ |
36a05131 BS |
2875 | if (GET_CODE (x) == MEM) |
2876 | x = ((GET_CODE (XEXP (x, 0)) == PLUS) | |
2877 | ? XEXP (XEXP (x, 0), 1) | |
2878 | : XEXP (x, 0)); | |
34208acf AO |
2879 | else if (GET_CODE (x) == PLUS) |
2880 | x = XEXP (x, 1); | |
36a05131 BS |
2881 | |
2882 | switch (GET_CODE (x)) | |
2883 | { | |
2884 | default: | |
2885 | break; | |
2886 | ||
2887 | case CONST_INT: | |
2888 | case SYMBOL_REF: | |
2889 | case CONST: | |
2890 | fputs ("i", file); | |
2891 | break; | |
2892 | } | |
2893 | break; | |
2894 | ||
2895 | case 'i': | |
2896 | /* For jump instructions, print 'i' if the operand is a constant or | |
87b483a1 | 2897 | is an expression that adds a constant. */ |
36a05131 BS |
2898 | if (GET_CODE (x) == CONST_INT) |
2899 | fputs ("i", file); | |
2900 | ||
2901 | else | |
2902 | { | |
2903 | if (GET_CODE (x) == CONST_INT | |
2904 | || (GET_CODE (x) == PLUS | |
2905 | && (GET_CODE (XEXP (x, 1)) == CONST_INT | |
2906 | || GET_CODE (XEXP (x, 0)) == CONST_INT))) | |
2907 | fputs ("i", file); | |
2908 | } | |
2909 | break; | |
2910 | ||
2911 | case 'L': | |
2912 | /* Print the lower register of a double word register pair */ | |
2913 | if (GET_CODE (x) == REG) | |
2914 | fputs (reg_names[ REGNO (x)+1 ], file); | |
2915 | else | |
ab532386 | 2916 | fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x); |
36a05131 BS |
2917 | break; |
2918 | ||
87b483a1 | 2919 | /* case 'l': print a LABEL_REF. */ |
36a05131 BS |
2920 | |
2921 | case 'M': | |
2922 | case 'N': | |
2923 | /* Print a memory reference for ld/st/jmp, %N prints a memory reference | |
2924 | for the second word of double memory operations. */ | |
2925 | offset = (code == 'M') ? 0 : UNITS_PER_WORD; | |
2926 | switch (GET_CODE (x)) | |
2927 | { | |
2928 | default: | |
ab532386 | 2929 | fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x); |
36a05131 BS |
2930 | |
2931 | case MEM: | |
2932 | frv_print_operand_memory_reference (file, XEXP (x, 0), offset); | |
2933 | break; | |
2934 | ||
2935 | case REG: | |
2936 | case SUBREG: | |
2937 | case CONST_INT: | |
2938 | case PLUS: | |
2939 | case SYMBOL_REF: | |
2940 | frv_print_operand_memory_reference (file, x, offset); | |
2941 | break; | |
2942 | } | |
2943 | break; | |
2944 | ||
2945 | case 'O': | |
2946 | /* Print the opcode of a command. */ | |
2947 | switch (GET_CODE (x)) | |
2948 | { | |
2949 | default: | |
ab532386 | 2950 | fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x); |
36a05131 BS |
2951 | |
2952 | case PLUS: fputs ("add", file); break; | |
2953 | case MINUS: fputs ("sub", file); break; | |
2954 | case AND: fputs ("and", file); break; | |
2955 | case IOR: fputs ("or", file); break; | |
2956 | case XOR: fputs ("xor", file); break; | |
2957 | case ASHIFT: fputs ("sll", file); break; | |
2958 | case ASHIFTRT: fputs ("sra", file); break; | |
2959 | case LSHIFTRT: fputs ("srl", file); break; | |
2960 | } | |
2961 | break; | |
2962 | ||
87b483a1 | 2963 | /* case 'n': negate and print a constant int. */ |
36a05131 BS |
2964 | |
2965 | case 'P': | |
2966 | /* Print PIC label using operand as the number. */ | |
2967 | if (GET_CODE (x) != CONST_INT) | |
ab532386 | 2968 | fatal_insn ("bad insn to frv_print_operand, P modifier:", x); |
36a05131 BS |
2969 | |
2970 | fprintf (file, ".LCF%ld", (long)INTVAL (x)); | |
2971 | break; | |
2972 | ||
2973 | case 'U': | |
87b483a1 | 2974 | /* Print 'u' if the operand is a update load/store. */ |
36a05131 BS |
2975 | if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY) |
2976 | fputs ("u", file); | |
2977 | break; | |
2978 | ||
2979 | case 'z': | |
87b483a1 | 2980 | /* If value is 0, print gr0, otherwise it must be a register. */ |
36a05131 BS |
2981 | if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0) |
2982 | fputs (reg_names[GPR_R0], file); | |
2983 | ||
2984 | else if (GET_CODE (x) == REG) | |
2985 | fputs (reg_names [REGNO (x)], file); | |
2986 | ||
2987 | else | |
ab532386 | 2988 | fatal_insn ("bad insn in frv_print_operand, z case", x); |
36a05131 BS |
2989 | break; |
2990 | ||
2991 | case 'x': | |
87b483a1 | 2992 | /* Print constant in hex. */ |
36a05131 BS |
2993 | if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) |
2994 | { | |
2995 | fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value); | |
2996 | break; | |
2997 | } | |
2998 | ||
87b483a1 | 2999 | /* Fall through. */ |
36a05131 BS |
3000 | |
3001 | case '\0': | |
3002 | if (GET_CODE (x) == REG) | |
3003 | fputs (reg_names [REGNO (x)], file); | |
3004 | ||
3005 | else if (GET_CODE (x) == CONST_INT | |
3006 | || GET_CODE (x) == CONST_DOUBLE) | |
3007 | fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value); | |
3008 | ||
34208acf AO |
3009 | else if (frv_const_unspec_p (x, &unspec)) |
3010 | frv_output_const_unspec (file, &unspec); | |
3011 | ||
36a05131 | 3012 | else if (GET_CODE (x) == MEM) |
cc8ca59e | 3013 | frv_print_operand_address (file, GET_MODE (x), XEXP (x, 0)); |
36a05131 BS |
3014 | |
3015 | else if (CONSTANT_ADDRESS_P (x)) | |
cc8ca59e | 3016 | frv_print_operand_address (file, VOIDmode, x); |
36a05131 BS |
3017 | |
3018 | else | |
ab532386 | 3019 | fatal_insn ("bad insn in frv_print_operand, 0 case", x); |
36a05131 BS |
3020 | |
3021 | break; | |
3022 | ||
3023 | default: | |
3024 | fatal_insn ("frv_print_operand: unknown code", x); | |
3025 | break; | |
3026 | } | |
3027 | ||
3028 | return; | |
3029 | } | |
3030 | ||
0fb30cb7 NF |
3031 | static bool |
3032 | frv_print_operand_punct_valid_p (unsigned char code) | |
3033 | { | |
3034 | return (code == '.' || code == '#' || code == '@' || code == '~' | |
3035 | || code == '*' || code == '&'); | |
3036 | } | |
3037 | ||
36a05131 BS |
3038 | \f |
3039 | /* A C statement (sans semicolon) for initializing the variable CUM for the | |
3040 | state at the beginning of the argument list. The variable has type | |
3041 | `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type | |
3042 | of the function which will receive the args, or 0 if the args are to a | |
3043 | compiler support library function. The value of INDIRECT is nonzero when | |
3044 | processing an indirect call, for example a call through a function pointer. | |
3045 | The value of INDIRECT is zero for a call to an explicitly named function, a | |
3046 | library function call, or when `INIT_CUMULATIVE_ARGS' is used to find | |
3047 | arguments for the function being compiled. | |
3048 | ||
3049 | When processing a call to a compiler support library function, LIBNAME | |
3050 | identifies which one. It is a `symbol_ref' rtx which contains the name of | |
3051 | the function, as a string. LIBNAME is 0 when an ordinary C function call is | |
3052 | being processed. Thus, each time this macro is called, either LIBNAME or | |
3053 | FNTYPE is nonzero, but never both of them at once. */ | |
3054 | ||
3055 | void | |
f2206911 KC |
3056 | frv_init_cumulative_args (CUMULATIVE_ARGS *cum, |
3057 | tree fntype, | |
3058 | rtx libname, | |
3059 | tree fndecl, | |
3060 | int incoming) | |
36a05131 BS |
3061 | { |
3062 | *cum = FIRST_ARG_REGNUM; | |
3063 | ||
3064 | if (TARGET_DEBUG_ARG) | |
3065 | { | |
3066 | fprintf (stderr, "\ninit_cumulative_args:"); | |
563a317a | 3067 | if (!fndecl && fntype) |
36a05131 BS |
3068 | fputs (" indirect", stderr); |
3069 | ||
3070 | if (incoming) | |
3071 | fputs (" incoming", stderr); | |
3072 | ||
3073 | if (fntype) | |
3074 | { | |
3075 | tree ret_type = TREE_TYPE (fntype); | |
3076 | fprintf (stderr, " return=%s,", | |
8ad8afaf | 3077 | get_tree_code_name (TREE_CODE (ret_type))); |
36a05131 BS |
3078 | } |
3079 | ||
3080 | if (libname && GET_CODE (libname) == SYMBOL_REF) | |
3081 | fprintf (stderr, " libname=%s", XSTR (libname, 0)); | |
3082 | ||
3083 | if (cfun->returns_struct) | |
3084 | fprintf (stderr, " return-struct"); | |
3085 | ||
3086 | putc ('\n', stderr); | |
3087 | } | |
3088 | } | |
3089 | ||
3090 | \f | |
fe984136 RH |
3091 | /* Return true if we should pass an argument on the stack rather than |
3092 | in registers. */ | |
3093 | ||
3094 | static bool | |
ef4bddc2 | 3095 | frv_must_pass_in_stack (machine_mode mode, const_tree type) |
fe984136 RH |
3096 | { |
3097 | if (mode == BLKmode) | |
3098 | return true; | |
3099 | if (type == NULL) | |
3100 | return false; | |
3101 | return AGGREGATE_TYPE_P (type); | |
3102 | } | |
3103 | ||
36a05131 BS |
3104 | /* If defined, a C expression that gives the alignment boundary, in bits, of an |
3105 | argument with the specified mode and type. If it is not defined, | |
3106 | `PARM_BOUNDARY' is used for all arguments. */ | |
3107 | ||
c2ed6cf8 | 3108 | static unsigned int |
ef4bddc2 | 3109 | frv_function_arg_boundary (machine_mode mode ATTRIBUTE_UNUSED, |
c2ed6cf8 | 3110 | const_tree type ATTRIBUTE_UNUSED) |
36a05131 BS |
3111 | { |
3112 | return BITS_PER_WORD; | |
3113 | } | |
3114 | ||
88a1f47f | 3115 | static rtx |
ef4bddc2 | 3116 | frv_function_arg_1 (cumulative_args_t cum_v, machine_mode mode, |
88a1f47f NF |
3117 | const_tree type ATTRIBUTE_UNUSED, bool named, |
3118 | bool incoming ATTRIBUTE_UNUSED) | |
36a05131 | 3119 | { |
d5cc9181 JR |
3120 | const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
3121 | ||
ef4bddc2 | 3122 | machine_mode xmode = (mode == BLKmode) ? SImode : mode; |
36a05131 BS |
3123 | int arg_num = *cum; |
3124 | rtx ret; | |
3125 | const char *debstr; | |
3126 | ||
3127 | /* Return a marker for use in the call instruction. */ | |
3128 | if (xmode == VOIDmode) | |
3129 | { | |
3130 | ret = const0_rtx; | |
3131 | debstr = "<0>"; | |
3132 | } | |
3133 | ||
3134 | else if (arg_num <= LAST_ARG_REGNUM) | |
3135 | { | |
f1c25d3b | 3136 | ret = gen_rtx_REG (xmode, arg_num); |
36a05131 BS |
3137 | debstr = reg_names[arg_num]; |
3138 | } | |
3139 | ||
3140 | else | |
3141 | { | |
3142 | ret = NULL_RTX; | |
3143 | debstr = "memory"; | |
3144 | } | |
3145 | ||
3146 | if (TARGET_DEBUG_ARG) | |
3147 | fprintf (stderr, | |
3148 | "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n", | |
3149 | arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr); | |
3150 | ||
3151 | return ret; | |
3152 | } | |
3153 | ||
88a1f47f | 3154 | static rtx |
ef4bddc2 | 3155 | frv_function_arg (cumulative_args_t cum, machine_mode mode, |
88a1f47f NF |
3156 | const_tree type, bool named) |
3157 | { | |
3158 | return frv_function_arg_1 (cum, mode, type, named, false); | |
3159 | } | |
3160 | ||
3161 | static rtx | |
ef4bddc2 | 3162 | frv_function_incoming_arg (cumulative_args_t cum, machine_mode mode, |
88a1f47f NF |
3163 | const_tree type, bool named) |
3164 | { | |
3165 | return frv_function_arg_1 (cum, mode, type, named, true); | |
3166 | } | |
3167 | ||
36a05131 BS |
3168 | \f |
3169 | /* A C statement (sans semicolon) to update the summarizer variable CUM to | |
3170 | advance past an argument in the argument list. The values MODE, TYPE and | |
3171 | NAMED describe that argument. Once this is done, the variable CUM is | |
3172 | suitable for analyzing the *following* argument with `FUNCTION_ARG', etc. | |
3173 | ||
3174 | This macro need not do anything if the argument in question was passed on | |
3175 | the stack. The compiler knows how to track the amount of stack space used | |
3176 | for arguments without any special help. */ | |
3177 | ||
88a1f47f | 3178 | static void |
d5cc9181 | 3179 | frv_function_arg_advance (cumulative_args_t cum_v, |
ef4bddc2 | 3180 | machine_mode mode, |
88a1f47f NF |
3181 | const_tree type ATTRIBUTE_UNUSED, |
3182 | bool named) | |
36a05131 | 3183 | { |
d5cc9181 JR |
3184 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
3185 | ||
ef4bddc2 | 3186 | machine_mode xmode = (mode == BLKmode) ? SImode : mode; |
36a05131 BS |
3187 | int bytes = GET_MODE_SIZE (xmode); |
3188 | int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
3189 | int arg_num = *cum; | |
3190 | ||
3191 | *cum = arg_num + words; | |
3192 | ||
3193 | if (TARGET_DEBUG_ARG) | |
3194 | fprintf (stderr, | |
3195 | "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n", | |
3196 | arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD); | |
3197 | } | |
3198 | ||
3199 | \f | |
3200 | /* A C expression for the number of words, at the beginning of an argument, | |
3201 | must be put in registers. The value must be zero for arguments that are | |
3202 | passed entirely in registers or that are entirely pushed on the stack. | |
3203 | ||
3204 | On some machines, certain arguments must be passed partially in registers | |
3205 | and partially in memory. On these machines, typically the first N words of | |
3206 | arguments are passed in registers, and the rest on the stack. If a | |
3207 | multi-word argument (a `double' or a structure) crosses that boundary, its | |
3208 | first few words must be passed in registers and the rest must be pushed. | |
3209 | This macro tells the compiler when this occurs, and how many of the words | |
3210 | should go in registers. | |
3211 | ||
3212 | `FUNCTION_ARG' for these arguments should return the first register to be | |
3213 | used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for | |
3214 | the called function. */ | |
3215 | ||
78a52f11 | 3216 | static int |
ef4bddc2 | 3217 | frv_arg_partial_bytes (cumulative_args_t cum, machine_mode mode, |
78a52f11 | 3218 | tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED) |
36a05131 | 3219 | { |
d5cc9181 | 3220 | |
ef4bddc2 | 3221 | machine_mode xmode = (mode == BLKmode) ? SImode : mode; |
36a05131 BS |
3222 | int bytes = GET_MODE_SIZE (xmode); |
3223 | int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
d5cc9181 | 3224 | int arg_num = *get_cumulative_args (cum); |
36a05131 BS |
3225 | int ret; |
3226 | ||
3227 | ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1) | |
3228 | ? LAST_ARG_REGNUM - arg_num + 1 | |
3229 | : 0); | |
78a52f11 | 3230 | ret *= UNITS_PER_WORD; |
36a05131 BS |
3231 | |
3232 | if (TARGET_DEBUG_ARG && ret) | |
78a52f11 | 3233 | fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret); |
36a05131 BS |
3234 | |
3235 | return ret; | |
36a05131 BS |
3236 | } |
3237 | ||
219d92a4 AS |
3238 | \f |
3239 | /* Implements TARGET_FUNCTION_VALUE. */ | |
3240 | ||
3241 | static rtx | |
3242 | frv_function_value (const_tree valtype, | |
3243 | const_tree fn_decl_or_type ATTRIBUTE_UNUSED, | |
3244 | bool outgoing ATTRIBUTE_UNUSED) | |
3245 | { | |
3246 | return gen_rtx_REG (TYPE_MODE (valtype), RETURN_VALUE_REGNUM); | |
3247 | } | |
3248 | ||
3249 | \f | |
3250 | /* Implements TARGET_LIBCALL_VALUE. */ | |
3251 | ||
3252 | static rtx | |
ef4bddc2 | 3253 | frv_libcall_value (machine_mode mode, |
219d92a4 AS |
3254 | const_rtx fun ATTRIBUTE_UNUSED) |
3255 | { | |
3256 | return gen_rtx_REG (mode, RETURN_VALUE_REGNUM); | |
3257 | } | |
3258 | ||
3259 | \f | |
3260 | /* Implements FUNCTION_VALUE_REGNO_P. */ | |
3261 | ||
3262 | bool | |
3263 | frv_function_value_regno_p (const unsigned int regno) | |
3264 | { | |
3265 | return (regno == RETURN_VALUE_REGNUM); | |
3266 | } | |
36a05131 BS |
3267 | \f |
3268 | /* Return true if a register is ok to use as a base or index register. */ | |
3269 | ||
3270 | static FRV_INLINE int | |
f2206911 | 3271 | frv_regno_ok_for_base_p (int regno, int strict_p) |
36a05131 BS |
3272 | { |
3273 | if (GPR_P (regno)) | |
3274 | return TRUE; | |
3275 | ||
3276 | if (strict_p) | |
3277 | return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno])); | |
3278 | ||
3279 | if (regno == ARG_POINTER_REGNUM) | |
3280 | return TRUE; | |
3281 | ||
3282 | return (regno >= FIRST_PSEUDO_REGISTER); | |
3283 | } | |
3284 | ||
3285 | \f | |
3286 | /* A C compound statement with a conditional `goto LABEL;' executed if X (an | |
3287 | RTX) is a legitimate memory address on the target machine for a memory | |
3288 | operand of mode MODE. | |
3289 | ||
3290 | It usually pays to define several simpler macros to serve as subroutines for | |
3291 | this one. Otherwise it may be too complicated to understand. | |
3292 | ||
3293 | This macro must exist in two variants: a strict variant and a non-strict | |
3294 | one. The strict variant is used in the reload pass. It must be defined so | |
3295 | that any pseudo-register that has not been allocated a hard register is | |
3296 | considered a memory reference. In contexts where some kind of register is | |
3297 | required, a pseudo-register with no hard register must be rejected. | |
3298 | ||
3299 | The non-strict variant is used in other passes. It must be defined to | |
3300 | accept all pseudo-registers in every context where some kind of register is | |
3301 | required. | |
3302 | ||
3303 | Compiler source files that want to use the strict variant of this macro | |
3304 | define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT' | |
3305 | conditional to define the strict variant in that case and the non-strict | |
3306 | variant otherwise. | |
3307 | ||
36a05131 BS |
3308 | Normally, constant addresses which are the sum of a `symbol_ref' and an |
3309 | integer are stored inside a `const' RTX to mark them as constant. | |
3310 | Therefore, there is no need to recognize such sums specifically as | |
3311 | legitimate addresses. Normally you would simply recognize any `const' as | |
3312 | legitimate. | |
3313 | ||
0fb30cb7 NF |
3314 | Usually `TARGET_PRINT_OPERAND_ADDRESS' is not prepared to handle |
3315 | constant sums that are not marked with `const'. It assumes that a | |
3316 | naked `plus' indicates indexing. If so, then you *must* reject such | |
3317 | naked constant sums as illegitimate addresses, so that none of them | |
3318 | will be given to `TARGET_PRINT_OPERAND_ADDRESS'. */ | |
36a05131 BS |
3319 | |
3320 | int | |
ef4bddc2 | 3321 | frv_legitimate_address_p_1 (machine_mode mode, |
c6c3dba9 PB |
3322 | rtx x, |
3323 | int strict_p, | |
3324 | int condexec_p, | |
3325 | int allow_double_reg_p) | |
36a05131 BS |
3326 | { |
3327 | rtx x0, x1; | |
3328 | int ret = 0; | |
3329 | HOST_WIDE_INT value; | |
3330 | unsigned regno0; | |
3331 | ||
bef8809e AH |
3332 | if (FRV_SYMBOL_REF_TLS_P (x)) |
3333 | return 0; | |
3334 | ||
36a05131 BS |
3335 | switch (GET_CODE (x)) |
3336 | { | |
3337 | default: | |
3338 | break; | |
3339 | ||
3340 | case SUBREG: | |
3341 | x = SUBREG_REG (x); | |
3342 | if (GET_CODE (x) != REG) | |
3343 | break; | |
3344 | ||
87b483a1 | 3345 | /* Fall through. */ |
36a05131 BS |
3346 | |
3347 | case REG: | |
3348 | ret = frv_regno_ok_for_base_p (REGNO (x), strict_p); | |
3349 | break; | |
3350 | ||
3351 | case PRE_MODIFY: | |
3352 | x0 = XEXP (x, 0); | |
3353 | x1 = XEXP (x, 1); | |
3354 | if (GET_CODE (x0) != REG | |
3355 | || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p) | |
3356 | || GET_CODE (x1) != PLUS | |
3357 | || ! rtx_equal_p (x0, XEXP (x1, 0)) | |
3358 | || GET_CODE (XEXP (x1, 1)) != REG | |
3359 | || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p)) | |
3360 | break; | |
3361 | ||
3362 | ret = 1; | |
3363 | break; | |
3364 | ||
3365 | case CONST_INT: | |
2300b9dd | 3366 | /* 12-bit immediate */ |
36a05131 BS |
3367 | if (condexec_p) |
3368 | ret = FALSE; | |
3369 | else | |
3370 | { | |
2f5b1308 | 3371 | ret = IN_RANGE (INTVAL (x), -2048, 2047); |
36a05131 BS |
3372 | |
3373 | /* If we can't use load/store double operations, make sure we can | |
3374 | address the second word. */ | |
3375 | if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
2f5b1308 JR |
3376 | ret = IN_RANGE (INTVAL (x) + GET_MODE_SIZE (mode) - 1, |
3377 | -2048, 2047); | |
36a05131 BS |
3378 | } |
3379 | break; | |
3380 | ||
3381 | case PLUS: | |
3382 | x0 = XEXP (x, 0); | |
3383 | x1 = XEXP (x, 1); | |
3384 | ||
3385 | if (GET_CODE (x0) == SUBREG) | |
3386 | x0 = SUBREG_REG (x0); | |
3387 | ||
3388 | if (GET_CODE (x0) != REG) | |
3389 | break; | |
3390 | ||
3391 | regno0 = REGNO (x0); | |
3392 | if (!frv_regno_ok_for_base_p (regno0, strict_p)) | |
3393 | break; | |
3394 | ||
3395 | switch (GET_CODE (x1)) | |
3396 | { | |
3397 | default: | |
3398 | break; | |
3399 | ||
3400 | case SUBREG: | |
3401 | x1 = SUBREG_REG (x1); | |
3402 | if (GET_CODE (x1) != REG) | |
3403 | break; | |
3404 | ||
87b483a1 | 3405 | /* Fall through. */ |
36a05131 BS |
3406 | |
3407 | case REG: | |
87b483a1 KH |
3408 | /* Do not allow reg+reg addressing for modes > 1 word if we |
3409 | can't depend on having move double instructions. */ | |
34208acf | 3410 | if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD) |
36a05131 BS |
3411 | ret = FALSE; |
3412 | else | |
3413 | ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p); | |
3414 | break; | |
3415 | ||
3416 | case CONST_INT: | |
2300b9dd | 3417 | /* 12-bit immediate */ |
36a05131 BS |
3418 | if (condexec_p) |
3419 | ret = FALSE; | |
3420 | else | |
3421 | { | |
3422 | value = INTVAL (x1); | |
2f5b1308 | 3423 | ret = IN_RANGE (value, -2048, 2047); |
36a05131 BS |
3424 | |
3425 | /* If we can't use load/store double operations, make sure we can | |
3426 | address the second word. */ | |
3427 | if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
2f5b1308 | 3428 | ret = IN_RANGE (value + GET_MODE_SIZE (mode) - 1, -2048, 2047); |
36a05131 BS |
3429 | } |
3430 | break; | |
3431 | ||
36a05131 | 3432 | case CONST: |
34208acf | 3433 | if (!condexec_p && got12_operand (x1, VOIDmode)) |
36a05131 BS |
3434 | ret = TRUE; |
3435 | break; | |
3436 | ||
3437 | } | |
3438 | break; | |
3439 | } | |
3440 | ||
3441 | if (TARGET_DEBUG_ADDR) | |
3442 | { | |
331d9186 | 3443 | fprintf (stderr, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n", |
36a05131 BS |
3444 | GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ", |
3445 | (condexec_p) ? ", inside conditional code" : ""); | |
3446 | debug_rtx (x); | |
3447 | } | |
3448 | ||
3449 | return ret; | |
3450 | } | |
3451 | ||
c6c3dba9 | 3452 | bool |
ef4bddc2 | 3453 | frv_legitimate_address_p (machine_mode mode, rtx x, bool strict_p) |
c6c3dba9 PB |
3454 | { |
3455 | return frv_legitimate_address_p_1 (mode, x, strict_p, FALSE, FALSE); | |
3456 | } | |
3457 | ||
bef8809e AH |
3458 | /* Given an ADDR, generate code to inline the PLT. */ |
3459 | static rtx | |
3460 | gen_inlined_tls_plt (rtx addr) | |
3461 | { | |
fdbe66f2 | 3462 | rtx retval, dest; |
bef8809e AH |
3463 | rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG); |
3464 | ||
3465 | ||
3466 | dest = gen_reg_rtx (DImode); | |
3467 | ||
3468 | if (flag_pic == 1) | |
3469 | { | |
3470 | /* | |
3471 | -fpic version: | |
3472 | ||
3473 | lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8 | |
3474 | calll #gettlsoff(ADDR)@(gr8, gr0) | |
3475 | */ | |
3476 | emit_insn (gen_tls_lddi (dest, addr, picreg)); | |
3477 | } | |
3478 | else | |
3479 | { | |
3480 | /* | |
3481 | -fPIC version: | |
3482 | ||
3483 | sethi.p #gottlsdeschi(ADDR), gr8 | |
3484 | setlo #gottlsdesclo(ADDR), gr8 | |
3485 | ldd #tlsdesc(ADDR)@(gr15, gr8), gr8 | |
3486 | calll #gettlsoff(ADDR)@(gr8, gr0) | |
3487 | */ | |
3488 | rtx reguse = gen_reg_rtx (Pmode); | |
3489 | emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI))); | |
3490 | emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr)); | |
3491 | } | |
3492 | ||
3493 | retval = gen_reg_rtx (Pmode); | |
a701780f | 3494 | emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg)); |
bef8809e AH |
3495 | return retval; |
3496 | } | |
3497 | ||
3498 | /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns | |
3499 | the destination address. */ | |
3500 | static rtx | |
3501 | gen_tlsmoff (rtx addr, rtx reg) | |
3502 | { | |
3503 | rtx dest = gen_reg_rtx (Pmode); | |
3504 | ||
3505 | if (TARGET_BIG_TLS) | |
3506 | { | |
3507 | /* sethi.p #tlsmoffhi(x), grA | |
3508 | setlo #tlsmofflo(x), grA | |
3509 | */ | |
3510 | dest = gen_reg_rtx (Pmode); | |
3511 | emit_insn (gen_tlsoff_hilo (dest, addr, | |
3512 | GEN_INT (R_FRV_TLSMOFFHI))); | |
3513 | dest = gen_rtx_PLUS (Pmode, dest, reg); | |
3514 | } | |
3515 | else | |
3516 | { | |
3517 | /* addi grB, #tlsmoff12(x), grC | |
3518 | -or- | |
3519 | ld/st @(grB, #tlsmoff12(x)), grC | |
3520 | */ | |
3521 | dest = gen_reg_rtx (Pmode); | |
3522 | emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg, | |
3523 | GEN_INT (R_FRV_TLSMOFF12))); | |
3524 | } | |
3525 | return dest; | |
3526 | } | |
3527 | ||
3528 | /* Generate code for a TLS address. */ | |
3529 | static rtx | |
3530 | frv_legitimize_tls_address (rtx addr, enum tls_model model) | |
3531 | { | |
3532 | rtx dest, tp = gen_rtx_REG (Pmode, 29); | |
3533 | rtx picreg = get_hard_reg_initial_val (Pmode, 15); | |
3534 | ||
3535 | switch (model) | |
3536 | { | |
3537 | case TLS_MODEL_INITIAL_EXEC: | |
3538 | if (flag_pic == 1) | |
3539 | { | |
3540 | /* -fpic version. | |
3541 | ldi @(gr15, #gottlsoff12(x)), gr5 | |
3542 | */ | |
3543 | dest = gen_reg_rtx (Pmode); | |
3544 | emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg)); | |
3545 | dest = gen_rtx_PLUS (Pmode, tp, dest); | |
3546 | } | |
3547 | else | |
3548 | { | |
3549 | /* -fPIC or anything else. | |
3550 | ||
3551 | sethi.p #gottlsoffhi(x), gr14 | |
3552 | setlo #gottlsofflo(x), gr14 | |
3553 | ld #tlsoff(x)@(gr15, gr14), gr9 | |
3554 | */ | |
3555 | rtx tmp = gen_reg_rtx (Pmode); | |
3556 | dest = gen_reg_rtx (Pmode); | |
3557 | emit_insn (gen_tlsoff_hilo (tmp, addr, | |
3558 | GEN_INT (R_FRV_GOTTLSOFF_HI))); | |
3559 | ||
3560 | emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr)); | |
3561 | dest = gen_rtx_PLUS (Pmode, tp, dest); | |
3562 | } | |
3563 | break; | |
3564 | case TLS_MODEL_LOCAL_DYNAMIC: | |
3565 | { | |
3566 | rtx reg, retval; | |
3567 | ||
3568 | if (TARGET_INLINE_PLT) | |
3569 | retval = gen_inlined_tls_plt (GEN_INT (0)); | |
3570 | else | |
3571 | { | |
3572 | /* call #gettlsoff(0) */ | |
3573 | retval = gen_reg_rtx (Pmode); | |
3574 | emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg)); | |
3575 | } | |
3576 | ||
3577 | reg = gen_reg_rtx (Pmode); | |
f7df4a84 | 3578 | emit_insn (gen_rtx_SET (reg, gen_rtx_PLUS (Pmode, retval, tp))); |
bef8809e AH |
3579 | |
3580 | dest = gen_tlsmoff (addr, reg); | |
3581 | ||
3582 | /* | |
3583 | dest = gen_reg_rtx (Pmode); | |
3584 | emit_insn (gen_tlsoff_hilo (dest, addr, | |
3585 | GEN_INT (R_FRV_TLSMOFFHI))); | |
3586 | dest = gen_rtx_PLUS (Pmode, dest, reg); | |
3587 | */ | |
3588 | break; | |
3589 | } | |
3590 | case TLS_MODEL_LOCAL_EXEC: | |
3591 | dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29)); | |
3592 | break; | |
3593 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
3594 | { | |
3595 | rtx retval; | |
3596 | ||
3597 | if (TARGET_INLINE_PLT) | |
3598 | retval = gen_inlined_tls_plt (addr); | |
3599 | else | |
3600 | { | |
3601 | /* call #gettlsoff(x) */ | |
3602 | retval = gen_reg_rtx (Pmode); | |
3603 | emit_insn (gen_call_gettlsoff (retval, addr, picreg)); | |
3604 | } | |
3605 | dest = gen_rtx_PLUS (Pmode, retval, tp); | |
3606 | break; | |
3607 | } | |
3608 | default: | |
44e91694 | 3609 | gcc_unreachable (); |
bef8809e AH |
3610 | } |
3611 | ||
3612 | return dest; | |
3613 | } | |
3614 | ||
2a2e3f05 | 3615 | rtx |
bef8809e | 3616 | frv_legitimize_address (rtx x, |
2a2e3f05 | 3617 | rtx oldx ATTRIBUTE_UNUSED, |
ef4bddc2 | 3618 | machine_mode mode ATTRIBUTE_UNUSED) |
2a2e3f05 | 3619 | { |
bef8809e AH |
3620 | if (GET_CODE (x) == SYMBOL_REF) |
3621 | { | |
3622 | enum tls_model model = SYMBOL_REF_TLS_MODEL (x); | |
3623 | if (model != 0) | |
3624 | return frv_legitimize_tls_address (x, model); | |
3625 | } | |
3626 | ||
506d7b68 | 3627 | return x; |
2a2e3f05 | 3628 | } |
36a05131 | 3629 | \f |
34208acf AO |
3630 | /* Test whether a local function descriptor is canonical, i.e., |
3631 | whether we can use FUNCDESC_GOTOFF to compute the address of the | |
3632 | function. */ | |
3633 | ||
3634 | static bool | |
3635 | frv_local_funcdesc_p (rtx fnx) | |
3636 | { | |
3637 | tree fn; | |
3638 | enum symbol_visibility vis; | |
3639 | bool ret; | |
36a05131 | 3640 | |
34208acf AO |
3641 | if (! SYMBOL_REF_LOCAL_P (fnx)) |
3642 | return FALSE; | |
3643 | ||
3644 | fn = SYMBOL_REF_DECL (fnx); | |
3645 | ||
3646 | if (! fn) | |
3647 | return FALSE; | |
36a05131 | 3648 | |
34208acf | 3649 | vis = DECL_VISIBILITY (fn); |
36a05131 | 3650 | |
34208acf AO |
3651 | if (vis == VISIBILITY_PROTECTED) |
3652 | /* Private function descriptors for protected functions are not | |
3653 | canonical. Temporarily change the visibility to global. */ | |
3654 | vis = VISIBILITY_DEFAULT; | |
3655 | else if (flag_shlib) | |
3656 | /* If we're already compiling for a shared library (that, unlike | |
3657 | executables, can't assume that the existence of a definition | |
3658 | implies local binding), we can skip the re-testing. */ | |
3659 | return TRUE; | |
36a05131 | 3660 | |
34208acf | 3661 | ret = default_binds_local_p_1 (fn, flag_pic); |
36a05131 | 3662 | |
34208acf AO |
3663 | DECL_VISIBILITY (fn) = vis; |
3664 | ||
3665 | return ret; | |
3666 | } | |
3667 | ||
3668 | /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC | |
3669 | register. */ | |
36a05131 BS |
3670 | |
3671 | rtx | |
34208acf AO |
3672 | frv_gen_GPsym2reg (rtx dest, rtx src) |
3673 | { | |
3674 | tree gp = get_identifier ("_gp"); | |
3675 | rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp)); | |
36a05131 | 3676 | |
34208acf AO |
3677 | return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12)); |
3678 | } | |
3679 | ||
3680 | static const char * | |
3681 | unspec_got_name (int i) | |
3682 | { | |
3683 | switch (i) | |
36a05131 | 3684 | { |
34208acf AO |
3685 | case R_FRV_GOT12: return "got12"; |
3686 | case R_FRV_GOTHI: return "gothi"; | |
3687 | case R_FRV_GOTLO: return "gotlo"; | |
3688 | case R_FRV_FUNCDESC: return "funcdesc"; | |
3689 | case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12"; | |
3690 | case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi"; | |
3691 | case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo"; | |
3692 | case R_FRV_FUNCDESC_VALUE: return "funcdescvalue"; | |
3693 | case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12"; | |
3694 | case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi"; | |
3695 | case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo"; | |
3696 | case R_FRV_GOTOFF12: return "gotoff12"; | |
3697 | case R_FRV_GOTOFFHI: return "gotoffhi"; | |
3698 | case R_FRV_GOTOFFLO: return "gotofflo"; | |
3699 | case R_FRV_GPREL12: return "gprel12"; | |
3700 | case R_FRV_GPRELHI: return "gprelhi"; | |
3701 | case R_FRV_GPRELLO: return "gprello"; | |
bef8809e AH |
3702 | case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi"; |
3703 | case R_FRV_GOTTLSOFF_LO: return "gottlsofflo"; | |
3704 | case R_FRV_TLSMOFFHI: return "tlsmoffhi"; | |
3705 | case R_FRV_TLSMOFFLO: return "tlsmofflo"; | |
3706 | case R_FRV_TLSMOFF12: return "tlsmoff12"; | |
3707 | case R_FRV_TLSDESCHI: return "tlsdeschi"; | |
3708 | case R_FRV_TLSDESCLO: return "tlsdesclo"; | |
3709 | case R_FRV_GOTTLSDESCHI: return "gottlsdeschi"; | |
3710 | case R_FRV_GOTTLSDESCLO: return "gottlsdesclo"; | |
44e91694 | 3711 | default: gcc_unreachable (); |
36a05131 | 3712 | } |
34208acf | 3713 | } |
36a05131 | 3714 | |
34208acf AO |
3715 | /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset |
3716 | is added inside the relocation operator. */ | |
3717 | ||
3718 | static void | |
3719 | frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec) | |
3720 | { | |
3721 | fprintf (stream, "#%s(", unspec_got_name (unspec->reloc)); | |
0a81f074 RS |
3722 | output_addr_const (stream, plus_constant (Pmode, unspec->symbol, |
3723 | unspec->offset)); | |
34208acf AO |
3724 | fputs (")", stream); |
3725 | } | |
3726 | ||
3727 | /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo) | |
3728 | or #gotoff12(foo) for some small data symbol foo. If so, return foo, | |
3729 | otherwise return ORIG_X. */ | |
3730 | ||
3731 | rtx | |
3732 | frv_find_base_term (rtx x) | |
3733 | { | |
3734 | struct frv_unspec unspec; | |
3735 | ||
3736 | if (frv_const_unspec_p (x, &unspec) | |
3737 | && frv_small_data_reloc_p (unspec.symbol, unspec.reloc)) | |
0a81f074 | 3738 | return plus_constant (Pmode, unspec.symbol, unspec.offset); |
34208acf AO |
3739 | |
3740 | return x; | |
36a05131 BS |
3741 | } |
3742 | ||
3743 | /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if | |
3744 | the operand is used by a predicated instruction. */ | |
3745 | ||
6d26dc3b | 3746 | int |
ef4bddc2 | 3747 | frv_legitimate_memory_operand (rtx op, machine_mode mode, int condexec_p) |
36a05131 BS |
3748 | { |
3749 | return ((GET_MODE (op) == mode || mode == VOIDmode) | |
3750 | && GET_CODE (op) == MEM | |
c6c3dba9 PB |
3751 | && frv_legitimate_address_p_1 (mode, XEXP (op, 0), |
3752 | reload_completed, condexec_p, FALSE)); | |
34208acf AO |
3753 | } |
3754 | ||
3755 | void | |
764678d1 | 3756 | frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall) |
34208acf AO |
3757 | { |
3758 | rtx lr = gen_rtx_REG (Pmode, LR_REGNO); | |
3759 | rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG); | |
3760 | rtx c, rvrtx=0; | |
3761 | rtx addr; | |
3762 | ||
3763 | if (ret_value) | |
3764 | { | |
3765 | rvrtx = operands[0]; | |
3766 | operands ++; | |
3767 | } | |
3768 | ||
3769 | addr = XEXP (operands[0], 0); | |
3770 | ||
3771 | /* Inline PLTs if we're optimizing for speed. We'd like to inline | |
3772 | any calls that would involve a PLT, but can't tell, since we | |
3773 | don't know whether an extern function is going to be provided by | |
3774 | a separate translation unit or imported from a separate module. | |
3775 | When compiling for shared libraries, if the function has default | |
3776 | visibility, we assume it's overridable, so we inline the PLT, but | |
3777 | for executables, we don't really have a way to make a good | |
3778 | decision: a function is as likely to be imported from a shared | |
3779 | library as it is to be defined in the executable itself. We | |
3780 | assume executables will get global functions defined locally, | |
3781 | whereas shared libraries will have them potentially overridden, | |
3782 | so we only inline PLTs when compiling for shared libraries. | |
3783 | ||
3784 | In order to mark a function as local to a shared library, any | |
3785 | non-default visibility attribute suffices. Unfortunately, | |
3786 | there's no simple way to tag a function declaration as ``in a | |
3787 | different module'', which we could then use to trigger PLT | |
3788 | inlining on executables. There's -minline-plt, but it affects | |
3789 | all external functions, so one would have to also mark function | |
3790 | declarations available in the same module with non-default | |
3791 | visibility, which is advantageous in itself. */ | |
764678d1 AO |
3792 | if (GET_CODE (addr) == SYMBOL_REF |
3793 | && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT) | |
3794 | || sibcall)) | |
34208acf AO |
3795 | { |
3796 | rtx x, dest; | |
3797 | dest = gen_reg_rtx (SImode); | |
3798 | if (flag_pic != 1) | |
3799 | x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG, | |
3800 | GEN_INT (R_FRV_FUNCDESC_GOTOFF12)); | |
3801 | else | |
3802 | x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG, | |
3803 | GEN_INT (R_FRV_FUNCDESC_GOTOFF12)); | |
3804 | emit_insn (x); | |
ad516a74 | 3805 | crtl->uses_pic_offset_table = TRUE; |
34208acf | 3806 | addr = dest; |
2396bce1 | 3807 | } |
34208acf AO |
3808 | else if (GET_CODE (addr) == SYMBOL_REF) |
3809 | { | |
3810 | /* These are always either local, or handled through a local | |
3811 | PLT. */ | |
3812 | if (ret_value) | |
3813 | c = gen_call_value_fdpicsi (rvrtx, addr, operands[1], | |
3814 | operands[2], picreg, lr); | |
3815 | else | |
3816 | c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr); | |
3817 | emit_call_insn (c); | |
3818 | return; | |
3819 | } | |
3820 | else if (! ldd_address_operand (addr, Pmode)) | |
3821 | addr = force_reg (Pmode, addr); | |
3822 | ||
3823 | picreg = gen_reg_rtx (DImode); | |
3824 | emit_insn (gen_movdi_ldd (picreg, addr)); | |
3825 | ||
764678d1 AO |
3826 | if (sibcall && ret_value) |
3827 | c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx); | |
3828 | else if (sibcall) | |
3829 | c = gen_sibcall_fdpicdi (picreg, const0_rtx); | |
3830 | else if (ret_value) | |
34208acf AO |
3831 | c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr); |
3832 | else | |
3833 | c = gen_call_fdpicdi (picreg, const0_rtx, lr); | |
3834 | emit_call_insn (c); | |
36a05131 | 3835 | } |
36a05131 | 3836 | \f |
6d26dc3b KH |
3837 | /* Look for a SYMBOL_REF of a function in an rtx. We always want to |
3838 | process these separately from any offsets, such that we add any | |
3839 | offsets to the function descriptor (the actual pointer), not to the | |
3840 | function address. */ | |
36a05131 | 3841 | |
6d26dc3b KH |
3842 | static bool |
3843 | frv_function_symbol_referenced_p (rtx x) | |
36a05131 | 3844 | { |
6d26dc3b KH |
3845 | const char *format; |
3846 | int length; | |
3847 | int j; | |
36a05131 | 3848 | |
6d26dc3b KH |
3849 | if (GET_CODE (x) == SYMBOL_REF) |
3850 | return SYMBOL_REF_FUNCTION_P (x); | |
34208acf | 3851 | |
6d26dc3b KH |
3852 | length = GET_RTX_LENGTH (GET_CODE (x)); |
3853 | format = GET_RTX_FORMAT (GET_CODE (x)); | |
36a05131 | 3854 | |
6d26dc3b | 3855 | for (j = 0; j < length; ++j) |
36a05131 | 3856 | { |
6d26dc3b KH |
3857 | switch (format[j]) |
3858 | { | |
3859 | case 'e': | |
3860 | if (frv_function_symbol_referenced_p (XEXP (x, j))) | |
3861 | return TRUE; | |
3862 | break; | |
36a05131 | 3863 | |
6d26dc3b KH |
3864 | case 'V': |
3865 | case 'E': | |
3866 | if (XVEC (x, j) != 0) | |
3867 | { | |
3868 | int k; | |
3869 | for (k = 0; k < XVECLEN (x, j); ++k) | |
3870 | if (frv_function_symbol_referenced_p (XVECEXP (x, j, k))) | |
3871 | return TRUE; | |
3872 | } | |
3873 | break; | |
36a05131 | 3874 | |
6d26dc3b KH |
3875 | default: |
3876 | /* Nothing to do. */ | |
3877 | break; | |
3878 | } | |
36a05131 BS |
3879 | } |
3880 | ||
36a05131 BS |
3881 | return FALSE; |
3882 | } | |
3883 | ||
6d26dc3b KH |
3884 | /* Return true if the memory operand is one that can be conditionally |
3885 | executed. */ | |
36a05131 | 3886 | |
f2206911 | 3887 | int |
ef4bddc2 | 3888 | condexec_memory_operand (rtx op, machine_mode mode) |
36a05131 | 3889 | { |
ef4bddc2 | 3890 | machine_mode op_mode = GET_MODE (op); |
6d26dc3b | 3891 | rtx addr; |
36a05131 | 3892 | |
6d26dc3b | 3893 | if (mode != VOIDmode && op_mode != mode) |
36a05131 BS |
3894 | return FALSE; |
3895 | ||
6d26dc3b | 3896 | switch (op_mode) |
36a05131 BS |
3897 | { |
3898 | default: | |
6d26dc3b | 3899 | return FALSE; |
36a05131 | 3900 | |
4e10a5a7 RS |
3901 | case E_QImode: |
3902 | case E_HImode: | |
3903 | case E_SImode: | |
3904 | case E_SFmode: | |
36a05131 BS |
3905 | break; |
3906 | } | |
3907 | ||
6d26dc3b | 3908 | if (GET_CODE (op) != MEM) |
36a05131 BS |
3909 | return FALSE; |
3910 | ||
6d26dc3b | 3911 | addr = XEXP (op, 0); |
c6c3dba9 | 3912 | return frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE); |
36a05131 | 3913 | } |
36a05131 BS |
3914 | \f |
3915 | /* Return true if the bare return instruction can be used outside of the | |
3916 | epilog code. For frv, we only do it if there was no stack allocation. */ | |
3917 | ||
3918 | int | |
f2206911 | 3919 | direct_return_p (void) |
36a05131 BS |
3920 | { |
3921 | frv_stack_t *info; | |
3922 | ||
3923 | if (!reload_completed) | |
3924 | return FALSE; | |
3925 | ||
3926 | info = frv_stack_info (); | |
3927 | return (info->total_size == 0); | |
3928 | } | |
3929 | ||
3930 | \f | |
2a2e3f05 | 3931 | void |
ef4bddc2 | 3932 | frv_emit_move (machine_mode mode, rtx dest, rtx src) |
2a2e3f05 | 3933 | { |
bef8809e AH |
3934 | if (GET_CODE (src) == SYMBOL_REF) |
3935 | { | |
3936 | enum tls_model model = SYMBOL_REF_TLS_MODEL (src); | |
3937 | if (model != 0) | |
3938 | src = frv_legitimize_tls_address (src, model); | |
3939 | } | |
3940 | ||
2a2e3f05 AH |
3941 | switch (mode) |
3942 | { | |
4e10a5a7 | 3943 | case E_SImode: |
2a2e3f05 AH |
3944 | if (frv_emit_movsi (dest, src)) |
3945 | return; | |
3946 | break; | |
3947 | ||
4e10a5a7 RS |
3948 | case E_QImode: |
3949 | case E_HImode: | |
3950 | case E_DImode: | |
3951 | case E_SFmode: | |
3952 | case E_DFmode: | |
2a2e3f05 AH |
3953 | if (!reload_in_progress |
3954 | && !reload_completed | |
3955 | && !register_operand (dest, mode) | |
3956 | && !reg_or_0_operand (src, mode)) | |
3957 | src = copy_to_mode_reg (mode, src); | |
3958 | break; | |
3959 | ||
3960 | default: | |
44e91694 | 3961 | gcc_unreachable (); |
2a2e3f05 AH |
3962 | } |
3963 | ||
f7df4a84 | 3964 | emit_insn (gen_rtx_SET (dest, src)); |
2a2e3f05 AH |
3965 | } |
3966 | ||
36a05131 BS |
3967 | /* Emit code to handle a MOVSI, adding in the small data register or pic |
3968 | register if needed to load up addresses. Return TRUE if the appropriate | |
3969 | instructions are emitted. */ | |
3970 | ||
3971 | int | |
f2206911 | 3972 | frv_emit_movsi (rtx dest, rtx src) |
36a05131 BS |
3973 | { |
3974 | int base_regno = -1; | |
34208acf AO |
3975 | int unspec = 0; |
3976 | rtx sym = src; | |
3977 | struct frv_unspec old_unspec; | |
36a05131 BS |
3978 | |
3979 | if (!reload_in_progress | |
3980 | && !reload_completed | |
3981 | && !register_operand (dest, SImode) | |
3982 | && (!reg_or_0_operand (src, SImode) | |
3983 | /* Virtual registers will almost always be replaced by an | |
3984 | add instruction, so expose this to CSE by copying to | |
87b483a1 | 3985 | an intermediate register. */ |
36a05131 | 3986 | || (GET_CODE (src) == REG |
2f5b1308 JR |
3987 | && IN_RANGE (REGNO (src), |
3988 | FIRST_VIRTUAL_REGISTER, | |
3989 | LAST_VIRTUAL_POINTER_REGISTER)))) | |
36a05131 | 3990 | { |
f7df4a84 | 3991 | emit_insn (gen_rtx_SET (dest, copy_to_mode_reg (SImode, src))); |
36a05131 BS |
3992 | return TRUE; |
3993 | } | |
3994 | ||
3995 | /* Explicitly add in the PIC or small data register if needed. */ | |
3996 | switch (GET_CODE (src)) | |
3997 | { | |
3998 | default: | |
3999 | break; | |
4000 | ||
4001 | case LABEL_REF: | |
34208acf AO |
4002 | handle_label: |
4003 | if (TARGET_FDPIC) | |
4004 | { | |
4005 | /* Using GPREL12, we use a single GOT entry for all symbols | |
4006 | in read-only sections, but trade sequences such as: | |
4007 | ||
4008 | sethi #gothi(label), gr# | |
4009 | setlo #gotlo(label), gr# | |
4010 | ld @(gr15,gr#), gr# | |
4011 | ||
4012 | for | |
4013 | ||
4014 | ld @(gr15,#got12(_gp)), gr# | |
4015 | sethi #gprelhi(label), gr## | |
4016 | setlo #gprello(label), gr## | |
4017 | add gr#, gr##, gr## | |
4018 | ||
4019 | We may often be able to share gr# for multiple | |
4020 | computations of GPREL addresses, and we may often fold | |
4021 | the final add into the pair of registers of a load or | |
4022 | store instruction, so it's often profitable. Even when | |
4023 | optimizing for size, we're trading a GOT entry for an | |
4024 | additional instruction, which trades GOT space | |
4025 | (read-write) for code size (read-only, shareable), as | |
4026 | long as the symbol is not used in more than two different | |
4027 | locations. | |
2396bce1 | 4028 | |
34208acf AO |
4029 | With -fpie/-fpic, we'd be trading a single load for a |
4030 | sequence of 4 instructions, because the offset of the | |
4ee31f1e | 4031 | label can't be assumed to be addressable with 12 bits, so |
34208acf AO |
4032 | we don't do this. */ |
4033 | if (TARGET_GPREL_RO) | |
4034 | unspec = R_FRV_GPREL12; | |
4035 | else | |
4036 | unspec = R_FRV_GOT12; | |
4037 | } | |
4038 | else if (flag_pic) | |
36a05131 BS |
4039 | base_regno = PIC_REGNO; |
4040 | ||
4041 | break; | |
4042 | ||
4043 | case CONST: | |
34208acf AO |
4044 | if (frv_const_unspec_p (src, &old_unspec)) |
4045 | break; | |
36a05131 | 4046 | |
34208acf AO |
4047 | if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0))) |
4048 | { | |
4049 | handle_whatever: | |
4050 | src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0)); | |
4051 | emit_move_insn (dest, src); | |
4052 | return TRUE; | |
4053 | } | |
4054 | else | |
4055 | { | |
4056 | sym = XEXP (sym, 0); | |
4057 | if (GET_CODE (sym) == PLUS | |
4058 | && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF | |
4059 | && GET_CODE (XEXP (sym, 1)) == CONST_INT) | |
4060 | sym = XEXP (sym, 0); | |
4061 | if (GET_CODE (sym) == SYMBOL_REF) | |
4062 | goto handle_sym; | |
4063 | else if (GET_CODE (sym) == LABEL_REF) | |
4064 | goto handle_label; | |
4065 | else | |
4066 | goto handle_whatever; | |
4067 | } | |
36a05131 BS |
4068 | break; |
4069 | ||
4070 | case SYMBOL_REF: | |
34208acf AO |
4071 | handle_sym: |
4072 | if (TARGET_FDPIC) | |
4073 | { | |
bef8809e AH |
4074 | enum tls_model model = SYMBOL_REF_TLS_MODEL (sym); |
4075 | ||
4076 | if (model != 0) | |
4077 | { | |
4078 | src = frv_legitimize_tls_address (src, model); | |
4079 | emit_move_insn (dest, src); | |
4080 | return TRUE; | |
4081 | } | |
4082 | ||
34208acf AO |
4083 | if (SYMBOL_REF_FUNCTION_P (sym)) |
4084 | { | |
4085 | if (frv_local_funcdesc_p (sym)) | |
4086 | unspec = R_FRV_FUNCDESC_GOTOFF12; | |
4087 | else | |
4088 | unspec = R_FRV_FUNCDESC_GOT12; | |
4089 | } | |
4090 | else | |
4091 | { | |
4092 | if (CONSTANT_POOL_ADDRESS_P (sym)) | |
4093 | switch (GET_CODE (get_pool_constant (sym))) | |
4094 | { | |
4095 | case CONST: | |
4096 | case SYMBOL_REF: | |
4097 | case LABEL_REF: | |
4098 | if (flag_pic) | |
4099 | { | |
4100 | unspec = R_FRV_GOTOFF12; | |
4101 | break; | |
4102 | } | |
4103 | /* Fall through. */ | |
4104 | default: | |
4105 | if (TARGET_GPREL_RO) | |
4106 | unspec = R_FRV_GPREL12; | |
4107 | else | |
4108 | unspec = R_FRV_GOT12; | |
4109 | break; | |
4110 | } | |
4111 | else if (SYMBOL_REF_LOCAL_P (sym) | |
4112 | && !SYMBOL_REF_EXTERNAL_P (sym) | |
4113 | && SYMBOL_REF_DECL (sym) | |
4114 | && (!DECL_P (SYMBOL_REF_DECL (sym)) | |
4115 | || !DECL_COMMON (SYMBOL_REF_DECL (sym)))) | |
4116 | { | |
4117 | tree decl = SYMBOL_REF_DECL (sym); | |
4118 | tree init = TREE_CODE (decl) == VAR_DECL | |
4119 | ? DECL_INITIAL (decl) | |
4120 | : TREE_CODE (decl) == CONSTRUCTOR | |
4121 | ? decl : 0; | |
4122 | int reloc = 0; | |
4123 | bool named_section, readonly; | |
4124 | ||
4125 | if (init && init != error_mark_node) | |
4126 | reloc = compute_reloc_for_constant (init); | |
2396bce1 | 4127 | |
34208acf AO |
4128 | named_section = TREE_CODE (decl) == VAR_DECL |
4129 | && lookup_attribute ("section", DECL_ATTRIBUTES (decl)); | |
4130 | readonly = decl_readonly_section (decl, reloc); | |
2396bce1 | 4131 | |
34208acf AO |
4132 | if (named_section) |
4133 | unspec = R_FRV_GOT12; | |
4134 | else if (!readonly) | |
4135 | unspec = R_FRV_GOTOFF12; | |
4136 | else if (readonly && TARGET_GPREL_RO) | |
4137 | unspec = R_FRV_GPREL12; | |
4138 | else | |
4139 | unspec = R_FRV_GOT12; | |
4140 | } | |
4141 | else | |
4142 | unspec = R_FRV_GOT12; | |
4143 | } | |
4144 | } | |
4145 | ||
4146 | else if (SYMBOL_REF_SMALL_P (sym)) | |
36a05131 BS |
4147 | base_regno = SDA_BASE_REG; |
4148 | ||
4149 | else if (flag_pic) | |
4150 | base_regno = PIC_REGNO; | |
4151 | ||
4152 | break; | |
4153 | } | |
4154 | ||
4155 | if (base_regno >= 0) | |
4156 | { | |
34208acf AO |
4157 | if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym)) |
4158 | emit_insn (gen_symGOTOFF2reg (dest, src, | |
4159 | gen_rtx_REG (Pmode, base_regno), | |
4160 | GEN_INT (R_FRV_GPREL12))); | |
4161 | else | |
4162 | emit_insn (gen_symGOTOFF2reg_hilo (dest, src, | |
4163 | gen_rtx_REG (Pmode, base_regno), | |
4164 | GEN_INT (R_FRV_GPREL12))); | |
36a05131 | 4165 | if (base_regno == PIC_REGNO) |
ad516a74 | 4166 | crtl->uses_pic_offset_table = TRUE; |
34208acf AO |
4167 | return TRUE; |
4168 | } | |
36a05131 | 4169 | |
34208acf AO |
4170 | if (unspec) |
4171 | { | |
4172 | rtx x; | |
4173 | ||
4174 | /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce | |
4175 | new uses of it once reload has begun. */ | |
44e91694 | 4176 | gcc_assert (!reload_in_progress && !reload_completed); |
34208acf AO |
4177 | |
4178 | switch (unspec) | |
4179 | { | |
4180 | case R_FRV_GOTOFF12: | |
4181 | if (!frv_small_data_reloc_p (sym, unspec)) | |
4182 | x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG, | |
4183 | GEN_INT (unspec)); | |
4184 | else | |
4185 | x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); | |
4186 | break; | |
4187 | case R_FRV_GPREL12: | |
4188 | if (!frv_small_data_reloc_p (sym, unspec)) | |
4189 | x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG, | |
4190 | GEN_INT (unspec)); | |
4191 | else | |
4192 | x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); | |
4193 | break; | |
4194 | case R_FRV_FUNCDESC_GOTOFF12: | |
4195 | if (flag_pic != 1) | |
4196 | x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG, | |
4197 | GEN_INT (unspec)); | |
4198 | else | |
4199 | x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); | |
4200 | break; | |
4201 | default: | |
4202 | if (flag_pic != 1) | |
4203 | x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG, | |
4204 | GEN_INT (unspec)); | |
4205 | else | |
4206 | x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); | |
4207 | break; | |
4208 | } | |
4209 | emit_insn (x); | |
ad516a74 | 4210 | crtl->uses_pic_offset_table = TRUE; |
36a05131 BS |
4211 | return TRUE; |
4212 | } | |
4213 | ||
34208acf | 4214 | |
36a05131 BS |
4215 | return FALSE; |
4216 | } | |
4217 | ||
4218 | \f | |
4219 | /* Return a string to output a single word move. */ | |
4220 | ||
4221 | const char * | |
f2206911 | 4222 | output_move_single (rtx operands[], rtx insn) |
36a05131 BS |
4223 | { |
4224 | rtx dest = operands[0]; | |
4225 | rtx src = operands[1]; | |
4226 | ||
4227 | if (GET_CODE (dest) == REG) | |
4228 | { | |
4229 | int dest_regno = REGNO (dest); | |
ef4bddc2 | 4230 | machine_mode mode = GET_MODE (dest); |
36a05131 BS |
4231 | |
4232 | if (GPR_P (dest_regno)) | |
4233 | { | |
4234 | if (GET_CODE (src) == REG) | |
4235 | { | |
4236 | /* gpr <- some sort of register */ | |
4237 | int src_regno = REGNO (src); | |
4238 | ||
4239 | if (GPR_P (src_regno)) | |
4240 | return "mov %1, %0"; | |
4241 | ||
4242 | else if (FPR_P (src_regno)) | |
4243 | return "movfg %1, %0"; | |
4244 | ||
4245 | else if (SPR_P (src_regno)) | |
4246 | return "movsg %1, %0"; | |
4247 | } | |
4248 | ||
4249 | else if (GET_CODE (src) == MEM) | |
4250 | { | |
4251 | /* gpr <- memory */ | |
4252 | switch (mode) | |
4253 | { | |
4254 | default: | |
4255 | break; | |
4256 | ||
4e10a5a7 | 4257 | case E_QImode: |
36a05131 BS |
4258 | return "ldsb%I1%U1 %M1,%0"; |
4259 | ||
4e10a5a7 | 4260 | case E_HImode: |
36a05131 BS |
4261 | return "ldsh%I1%U1 %M1,%0"; |
4262 | ||
4e10a5a7 RS |
4263 | case E_SImode: |
4264 | case E_SFmode: | |
36a05131 BS |
4265 | return "ld%I1%U1 %M1, %0"; |
4266 | } | |
4267 | } | |
4268 | ||
4269 | else if (GET_CODE (src) == CONST_INT | |
4270 | || GET_CODE (src) == CONST_DOUBLE) | |
4271 | { | |
4272 | /* gpr <- integer/floating constant */ | |
4273 | HOST_WIDE_INT value; | |
4274 | ||
4275 | if (GET_CODE (src) == CONST_INT) | |
4276 | value = INTVAL (src); | |
4277 | ||
4278 | else if (mode == SFmode) | |
4279 | { | |
36a05131 BS |
4280 | long l; |
4281 | ||
34a72c33 RS |
4282 | REAL_VALUE_TO_TARGET_SINGLE |
4283 | (*CONST_DOUBLE_REAL_VALUE (src), l); | |
36a05131 BS |
4284 | value = l; |
4285 | } | |
4286 | ||
4287 | else | |
4288 | value = CONST_DOUBLE_LOW (src); | |
4289 | ||
2f5b1308 | 4290 | if (IN_RANGE (value, -32768, 32767)) |
36a05131 BS |
4291 | return "setlos %1, %0"; |
4292 | ||
4293 | return "#"; | |
4294 | } | |
4295 | ||
4296 | else if (GET_CODE (src) == SYMBOL_REF | |
4297 | || GET_CODE (src) == LABEL_REF | |
4298 | || GET_CODE (src) == CONST) | |
4299 | { | |
36a05131 BS |
4300 | return "#"; |
4301 | } | |
4302 | } | |
4303 | ||
4304 | else if (FPR_P (dest_regno)) | |
4305 | { | |
4306 | if (GET_CODE (src) == REG) | |
4307 | { | |
4308 | /* fpr <- some sort of register */ | |
4309 | int src_regno = REGNO (src); | |
4310 | ||
4311 | if (GPR_P (src_regno)) | |
4312 | return "movgf %1, %0"; | |
4313 | ||
4314 | else if (FPR_P (src_regno)) | |
4315 | { | |
4316 | if (TARGET_HARD_FLOAT) | |
4317 | return "fmovs %1, %0"; | |
4318 | else | |
4319 | return "mor %1, %1, %0"; | |
4320 | } | |
4321 | } | |
4322 | ||
4323 | else if (GET_CODE (src) == MEM) | |
4324 | { | |
4325 | /* fpr <- memory */ | |
4326 | switch (mode) | |
4327 | { | |
4328 | default: | |
4329 | break; | |
4330 | ||
4e10a5a7 | 4331 | case E_QImode: |
36a05131 BS |
4332 | return "ldbf%I1%U1 %M1,%0"; |
4333 | ||
4e10a5a7 | 4334 | case E_HImode: |
36a05131 BS |
4335 | return "ldhf%I1%U1 %M1,%0"; |
4336 | ||
4e10a5a7 RS |
4337 | case E_SImode: |
4338 | case E_SFmode: | |
36a05131 BS |
4339 | return "ldf%I1%U1 %M1, %0"; |
4340 | } | |
4341 | } | |
4342 | ||
4343 | else if (ZERO_P (src)) | |
4344 | return "movgf %., %0"; | |
4345 | } | |
4346 | ||
4347 | else if (SPR_P (dest_regno)) | |
4348 | { | |
4349 | if (GET_CODE (src) == REG) | |
4350 | { | |
4351 | /* spr <- some sort of register */ | |
4352 | int src_regno = REGNO (src); | |
4353 | ||
4354 | if (GPR_P (src_regno)) | |
4355 | return "movgs %1, %0"; | |
4356 | } | |
c557edf4 RS |
4357 | else if (ZERO_P (src)) |
4358 | return "movgs %., %0"; | |
36a05131 BS |
4359 | } |
4360 | } | |
4361 | ||
4362 | else if (GET_CODE (dest) == MEM) | |
4363 | { | |
4364 | if (GET_CODE (src) == REG) | |
4365 | { | |
4366 | int src_regno = REGNO (src); | |
ef4bddc2 | 4367 | machine_mode mode = GET_MODE (dest); |
36a05131 BS |
4368 | |
4369 | if (GPR_P (src_regno)) | |
4370 | { | |
4371 | switch (mode) | |
4372 | { | |
4373 | default: | |
4374 | break; | |
4375 | ||
4e10a5a7 | 4376 | case E_QImode: |
36a05131 BS |
4377 | return "stb%I0%U0 %1, %M0"; |
4378 | ||
4e10a5a7 | 4379 | case E_HImode: |
36a05131 BS |
4380 | return "sth%I0%U0 %1, %M0"; |
4381 | ||
4e10a5a7 RS |
4382 | case E_SImode: |
4383 | case E_SFmode: | |
36a05131 BS |
4384 | return "st%I0%U0 %1, %M0"; |
4385 | } | |
4386 | } | |
4387 | ||
4388 | else if (FPR_P (src_regno)) | |
4389 | { | |
4390 | switch (mode) | |
4391 | { | |
4392 | default: | |
4393 | break; | |
4394 | ||
4e10a5a7 | 4395 | case E_QImode: |
36a05131 BS |
4396 | return "stbf%I0%U0 %1, %M0"; |
4397 | ||
4e10a5a7 | 4398 | case E_HImode: |
36a05131 BS |
4399 | return "sthf%I0%U0 %1, %M0"; |
4400 | ||
4e10a5a7 RS |
4401 | case E_SImode: |
4402 | case E_SFmode: | |
36a05131 BS |
4403 | return "stf%I0%U0 %1, %M0"; |
4404 | } | |
4405 | } | |
4406 | } | |
4407 | ||
4408 | else if (ZERO_P (src)) | |
4409 | { | |
4410 | switch (GET_MODE (dest)) | |
4411 | { | |
4412 | default: | |
4413 | break; | |
4414 | ||
4e10a5a7 | 4415 | case E_QImode: |
36a05131 BS |
4416 | return "stb%I0%U0 %., %M0"; |
4417 | ||
4e10a5a7 | 4418 | case E_HImode: |
36a05131 BS |
4419 | return "sth%I0%U0 %., %M0"; |
4420 | ||
4e10a5a7 RS |
4421 | case E_SImode: |
4422 | case E_SFmode: | |
36a05131 BS |
4423 | return "st%I0%U0 %., %M0"; |
4424 | } | |
4425 | } | |
4426 | } | |
4427 | ||
ab532386 | 4428 | fatal_insn ("bad output_move_single operand", insn); |
36a05131 BS |
4429 | return ""; |
4430 | } | |
4431 | ||
4432 | \f | |
4433 | /* Return a string to output a double word move. */ | |
4434 | ||
4435 | const char * | |
f2206911 | 4436 | output_move_double (rtx operands[], rtx insn) |
36a05131 BS |
4437 | { |
4438 | rtx dest = operands[0]; | |
4439 | rtx src = operands[1]; | |
ef4bddc2 | 4440 | machine_mode mode = GET_MODE (dest); |
36a05131 BS |
4441 | |
4442 | if (GET_CODE (dest) == REG) | |
4443 | { | |
4444 | int dest_regno = REGNO (dest); | |
4445 | ||
4446 | if (GPR_P (dest_regno)) | |
4447 | { | |
4448 | if (GET_CODE (src) == REG) | |
4449 | { | |
4450 | /* gpr <- some sort of register */ | |
4451 | int src_regno = REGNO (src); | |
4452 | ||
4453 | if (GPR_P (src_regno)) | |
4454 | return "#"; | |
4455 | ||
4456 | else if (FPR_P (src_regno)) | |
4457 | { | |
4458 | if (((dest_regno - GPR_FIRST) & 1) == 0 | |
4459 | && ((src_regno - FPR_FIRST) & 1) == 0) | |
4460 | return "movfgd %1, %0"; | |
4461 | ||
4462 | return "#"; | |
4463 | } | |
4464 | } | |
4465 | ||
4466 | else if (GET_CODE (src) == MEM) | |
4467 | { | |
4468 | /* gpr <- memory */ | |
4469 | if (dbl_memory_one_insn_operand (src, mode)) | |
4470 | return "ldd%I1%U1 %M1, %0"; | |
4471 | ||
4472 | return "#"; | |
4473 | } | |
4474 | ||
4475 | else if (GET_CODE (src) == CONST_INT | |
4476 | || GET_CODE (src) == CONST_DOUBLE) | |
4477 | return "#"; | |
4478 | } | |
4479 | ||
4480 | else if (FPR_P (dest_regno)) | |
4481 | { | |
4482 | if (GET_CODE (src) == REG) | |
4483 | { | |
4484 | /* fpr <- some sort of register */ | |
4485 | int src_regno = REGNO (src); | |
4486 | ||
4487 | if (GPR_P (src_regno)) | |
4488 | { | |
4489 | if (((dest_regno - FPR_FIRST) & 1) == 0 | |
4490 | && ((src_regno - GPR_FIRST) & 1) == 0) | |
4491 | return "movgfd %1, %0"; | |
4492 | ||
4493 | return "#"; | |
4494 | } | |
4495 | ||
4496 | else if (FPR_P (src_regno)) | |
4497 | { | |
4498 | if (TARGET_DOUBLE | |
4499 | && ((dest_regno - FPR_FIRST) & 1) == 0 | |
4500 | && ((src_regno - FPR_FIRST) & 1) == 0) | |
4501 | return "fmovd %1, %0"; | |
4502 | ||
4503 | return "#"; | |
4504 | } | |
4505 | } | |
4506 | ||
4507 | else if (GET_CODE (src) == MEM) | |
4508 | { | |
4509 | /* fpr <- memory */ | |
4510 | if (dbl_memory_one_insn_operand (src, mode)) | |
4511 | return "lddf%I1%U1 %M1, %0"; | |
4512 | ||
4513 | return "#"; | |
4514 | } | |
4515 | ||
4516 | else if (ZERO_P (src)) | |
4517 | return "#"; | |
4518 | } | |
4519 | } | |
4520 | ||
4521 | else if (GET_CODE (dest) == MEM) | |
4522 | { | |
4523 | if (GET_CODE (src) == REG) | |
4524 | { | |
4525 | int src_regno = REGNO (src); | |
4526 | ||
4527 | if (GPR_P (src_regno)) | |
4528 | { | |
4529 | if (((src_regno - GPR_FIRST) & 1) == 0 | |
4530 | && dbl_memory_one_insn_operand (dest, mode)) | |
4531 | return "std%I0%U0 %1, %M0"; | |
4532 | ||
4533 | return "#"; | |
4534 | } | |
4535 | ||
4536 | if (FPR_P (src_regno)) | |
4537 | { | |
4538 | if (((src_regno - FPR_FIRST) & 1) == 0 | |
4539 | && dbl_memory_one_insn_operand (dest, mode)) | |
4540 | return "stdf%I0%U0 %1, %M0"; | |
4541 | ||
4542 | return "#"; | |
4543 | } | |
4544 | } | |
4545 | ||
4546 | else if (ZERO_P (src)) | |
4547 | { | |
4548 | if (dbl_memory_one_insn_operand (dest, mode)) | |
4549 | return "std%I0%U0 %., %M0"; | |
4550 | ||
4551 | return "#"; | |
4552 | } | |
4553 | } | |
4554 | ||
ab532386 | 4555 | fatal_insn ("bad output_move_double operand", insn); |
36a05131 BS |
4556 | return ""; |
4557 | } | |
4558 | ||
4559 | \f | |
4560 | /* Return a string to output a single word conditional move. | |
4561 | Operand0 -- EQ/NE of ccr register and 0 | |
4562 | Operand1 -- CCR register | |
4563 | Operand2 -- destination | |
4564 | Operand3 -- source */ | |
4565 | ||
4566 | const char * | |
f2206911 | 4567 | output_condmove_single (rtx operands[], rtx insn) |
36a05131 BS |
4568 | { |
4569 | rtx dest = operands[2]; | |
4570 | rtx src = operands[3]; | |
4571 | ||
4572 | if (GET_CODE (dest) == REG) | |
4573 | { | |
4574 | int dest_regno = REGNO (dest); | |
ef4bddc2 | 4575 | machine_mode mode = GET_MODE (dest); |
36a05131 BS |
4576 | |
4577 | if (GPR_P (dest_regno)) | |
4578 | { | |
4579 | if (GET_CODE (src) == REG) | |
4580 | { | |
4581 | /* gpr <- some sort of register */ | |
4582 | int src_regno = REGNO (src); | |
4583 | ||
4584 | if (GPR_P (src_regno)) | |
4585 | return "cmov %z3, %2, %1, %e0"; | |
4586 | ||
4587 | else if (FPR_P (src_regno)) | |
4588 | return "cmovfg %3, %2, %1, %e0"; | |
4589 | } | |
4590 | ||
4591 | else if (GET_CODE (src) == MEM) | |
4592 | { | |
4593 | /* gpr <- memory */ | |
4594 | switch (mode) | |
4595 | { | |
4596 | default: | |
4597 | break; | |
4598 | ||
4e10a5a7 | 4599 | case E_QImode: |
36a05131 BS |
4600 | return "cldsb%I3%U3 %M3, %2, %1, %e0"; |
4601 | ||
4e10a5a7 | 4602 | case E_HImode: |
36a05131 BS |
4603 | return "cldsh%I3%U3 %M3, %2, %1, %e0"; |
4604 | ||
4e10a5a7 RS |
4605 | case E_SImode: |
4606 | case E_SFmode: | |
36a05131 BS |
4607 | return "cld%I3%U3 %M3, %2, %1, %e0"; |
4608 | } | |
4609 | } | |
4610 | ||
4611 | else if (ZERO_P (src)) | |
4612 | return "cmov %., %2, %1, %e0"; | |
4613 | } | |
4614 | ||
4615 | else if (FPR_P (dest_regno)) | |
4616 | { | |
4617 | if (GET_CODE (src) == REG) | |
4618 | { | |
4619 | /* fpr <- some sort of register */ | |
4620 | int src_regno = REGNO (src); | |
4621 | ||
4622 | if (GPR_P (src_regno)) | |
4623 | return "cmovgf %3, %2, %1, %e0"; | |
4624 | ||
4625 | else if (FPR_P (src_regno)) | |
4626 | { | |
4627 | if (TARGET_HARD_FLOAT) | |
4628 | return "cfmovs %3,%2,%1,%e0"; | |
4629 | else | |
4630 | return "cmor %3, %3, %2, %1, %e0"; | |
4631 | } | |
4632 | } | |
4633 | ||
4634 | else if (GET_CODE (src) == MEM) | |
4635 | { | |
4636 | /* fpr <- memory */ | |
4637 | if (mode == SImode || mode == SFmode) | |
4638 | return "cldf%I3%U3 %M3, %2, %1, %e0"; | |
4639 | } | |
4640 | ||
4641 | else if (ZERO_P (src)) | |
4642 | return "cmovgf %., %2, %1, %e0"; | |
4643 | } | |
4644 | } | |
4645 | ||
4646 | else if (GET_CODE (dest) == MEM) | |
4647 | { | |
4648 | if (GET_CODE (src) == REG) | |
4649 | { | |
4650 | int src_regno = REGNO (src); | |
ef4bddc2 | 4651 | machine_mode mode = GET_MODE (dest); |
36a05131 BS |
4652 | |
4653 | if (GPR_P (src_regno)) | |
4654 | { | |
4655 | switch (mode) | |
4656 | { | |
4657 | default: | |
4658 | break; | |
4659 | ||
4e10a5a7 | 4660 | case E_QImode: |
36a05131 BS |
4661 | return "cstb%I2%U2 %3, %M2, %1, %e0"; |
4662 | ||
4e10a5a7 | 4663 | case E_HImode: |
36a05131 BS |
4664 | return "csth%I2%U2 %3, %M2, %1, %e0"; |
4665 | ||
4e10a5a7 RS |
4666 | case E_SImode: |
4667 | case E_SFmode: | |
36a05131 BS |
4668 | return "cst%I2%U2 %3, %M2, %1, %e0"; |
4669 | } | |
4670 | } | |
4671 | ||
4672 | else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode)) | |
4673 | return "cstf%I2%U2 %3, %M2, %1, %e0"; | |
4674 | } | |
4675 | ||
4676 | else if (ZERO_P (src)) | |
4677 | { | |
ef4bddc2 | 4678 | machine_mode mode = GET_MODE (dest); |
36a05131 BS |
4679 | switch (mode) |
4680 | { | |
4681 | default: | |
4682 | break; | |
4683 | ||
4e10a5a7 | 4684 | case E_QImode: |
36a05131 BS |
4685 | return "cstb%I2%U2 %., %M2, %1, %e0"; |
4686 | ||
4e10a5a7 | 4687 | case E_HImode: |
36a05131 BS |
4688 | return "csth%I2%U2 %., %M2, %1, %e0"; |
4689 | ||
4e10a5a7 RS |
4690 | case E_SImode: |
4691 | case E_SFmode: | |
36a05131 BS |
4692 | return "cst%I2%U2 %., %M2, %1, %e0"; |
4693 | } | |
4694 | } | |
4695 | } | |
4696 | ||
ab532386 | 4697 | fatal_insn ("bad output_condmove_single operand", insn); |
36a05131 BS |
4698 | return ""; |
4699 | } | |
4700 | ||
4701 | \f | |
4702 | /* Emit the appropriate code to do a comparison, returning the register the | |
4703 | comparison was done it. */ | |
4704 | ||
4705 | static rtx | |
f2206911 | 4706 | frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1) |
36a05131 | 4707 | { |
ef4bddc2 | 4708 | machine_mode cc_mode; |
36a05131 BS |
4709 | rtx cc_reg; |
4710 | ||
87b483a1 | 4711 | /* Floating point doesn't have comparison against a constant. */ |
36a05131 BS |
4712 | if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG) |
4713 | op1 = force_reg (GET_MODE (op0), op1); | |
4714 | ||
4715 | /* Possibly disable using anything but a fixed register in order to work | |
4716 | around cse moving comparisons past function calls. */ | |
4717 | cc_mode = SELECT_CC_MODE (test, op0, op1); | |
4718 | cc_reg = ((TARGET_ALLOC_CC) | |
4719 | ? gen_reg_rtx (cc_mode) | |
4720 | : gen_rtx_REG (cc_mode, | |
4721 | (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST)); | |
4722 | ||
f7df4a84 | 4723 | emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (cc_mode, op0, op1))); |
36a05131 BS |
4724 | |
4725 | return cc_reg; | |
4726 | } | |
4727 | ||
4728 | \f | |
f90b7a5a | 4729 | /* Emit code for a conditional branch. |
36a05131 BS |
4730 | XXX: I originally wanted to add a clobber of a CCR register to use in |
4731 | conditional execution, but that confuses the rest of the compiler. */ | |
4732 | ||
4733 | int | |
f90b7a5a | 4734 | frv_emit_cond_branch (rtx operands[]) |
36a05131 BS |
4735 | { |
4736 | rtx test_rtx; | |
4737 | rtx label_ref; | |
4738 | rtx if_else; | |
f90b7a5a PB |
4739 | enum rtx_code test = GET_CODE (operands[0]); |
4740 | rtx cc_reg = frv_emit_comparison (test, operands[1], operands[2]); | |
ef4bddc2 | 4741 | machine_mode cc_mode = GET_MODE (cc_reg); |
36a05131 BS |
4742 | |
4743 | /* Branches generate: | |
4744 | (set (pc) | |
4745 | (if_then_else (<test>, <cc_reg>, (const_int 0)) | |
4746 | (label_ref <branch_label>) | |
4747 | (pc))) */ | |
f90b7a5a | 4748 | label_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]); |
1c563bed | 4749 | test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx); |
36a05131 | 4750 | if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx); |
f7df4a84 | 4751 | emit_jump_insn (gen_rtx_SET (pc_rtx, if_else)); |
36a05131 BS |
4752 | return TRUE; |
4753 | } | |
4754 | ||
4755 | \f | |
f90b7a5a | 4756 | /* Emit code to set a gpr to 1/0 based on a comparison. */ |
36a05131 BS |
4757 | |
4758 | int | |
f90b7a5a | 4759 | frv_emit_scc (rtx operands[]) |
36a05131 BS |
4760 | { |
4761 | rtx set; | |
4762 | rtx test_rtx; | |
4763 | rtx clobber; | |
4764 | rtx cr_reg; | |
f90b7a5a PB |
4765 | enum rtx_code test = GET_CODE (operands[1]); |
4766 | rtx cc_reg = frv_emit_comparison (test, operands[2], operands[3]); | |
36a05131 BS |
4767 | |
4768 | /* SCC instructions generate: | |
4769 | (parallel [(set <target> (<test>, <cc_reg>, (const_int 0)) | |
4770 | (clobber (<ccr_reg>))]) */ | |
4771 | test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx); | |
f7df4a84 | 4772 | set = gen_rtx_SET (operands[0], test_rtx); |
36a05131 BS |
4773 | |
4774 | cr_reg = ((TARGET_ALLOC_CC) | |
4775 | ? gen_reg_rtx (CC_CCRmode) | |
4776 | : gen_rtx_REG (CC_CCRmode, | |
4777 | ((GET_MODE (cc_reg) == CC_FPmode) | |
4778 | ? FCR_FIRST | |
4779 | : ICR_FIRST))); | |
4780 | ||
4781 | clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg); | |
4782 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber))); | |
4783 | return TRUE; | |
4784 | } | |
4785 | ||
4786 | \f | |
4787 | /* Split a SCC instruction into component parts, returning a SEQUENCE to hold | |
839a4992 | 4788 | the separate insns. */ |
36a05131 BS |
4789 | |
4790 | rtx | |
f2206911 | 4791 | frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value) |
36a05131 BS |
4792 | { |
4793 | rtx ret; | |
4794 | ||
4795 | start_sequence (); | |
4796 | ||
4797 | /* Set the appropriate CCR bit. */ | |
f7df4a84 | 4798 | emit_insn (gen_rtx_SET (cr_reg, |
36a05131 BS |
4799 | gen_rtx_fmt_ee (GET_CODE (test), |
4800 | GET_MODE (cr_reg), | |
4801 | cc_reg, | |
4802 | const0_rtx))); | |
4803 | ||
4804 | /* Move the value into the destination. */ | |
4805 | emit_move_insn (dest, GEN_INT (value)); | |
4806 | ||
4807 | /* Move 0 into the destination if the test failed */ | |
4808 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
4809 | gen_rtx_EQ (GET_MODE (cr_reg), | |
4810 | cr_reg, | |
4811 | const0_rtx), | |
f7df4a84 | 4812 | gen_rtx_SET (dest, const0_rtx))); |
36a05131 BS |
4813 | |
4814 | /* Finish up, return sequence. */ | |
4815 | ret = get_insns (); | |
4816 | end_sequence (); | |
4817 | return ret; | |
4818 | } | |
4819 | ||
4820 | \f | |
4821 | /* Emit the code for a conditional move, return TRUE if we could do the | |
4822 | move. */ | |
4823 | ||
4824 | int | |
f2206911 | 4825 | frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2) |
36a05131 BS |
4826 | { |
4827 | rtx set; | |
4828 | rtx clobber_cc; | |
4829 | rtx test2; | |
4830 | rtx cr_reg; | |
4831 | rtx if_rtx; | |
4832 | enum rtx_code test = GET_CODE (test_rtx); | |
f90b7a5a PB |
4833 | rtx cc_reg = frv_emit_comparison (test, |
4834 | XEXP (test_rtx, 0), XEXP (test_rtx, 1)); | |
ef4bddc2 | 4835 | machine_mode cc_mode = GET_MODE (cc_reg); |
36a05131 BS |
4836 | |
4837 | /* Conditional move instructions generate: | |
4838 | (parallel [(set <target> | |
4839 | (if_then_else (<test> <cc_reg> (const_int 0)) | |
4840 | <src1> | |
4841 | <src2>)) | |
4842 | (clobber (<ccr_reg>))]) */ | |
4843 | ||
4844 | /* Handle various cases of conditional move involving two constants. */ | |
4845 | if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT) | |
4846 | { | |
4847 | HOST_WIDE_INT value1 = INTVAL (src1); | |
4848 | HOST_WIDE_INT value2 = INTVAL (src2); | |
4849 | ||
87b483a1 | 4850 | /* Having 0 as one of the constants can be done by loading the other |
36a05131 BS |
4851 | constant, and optionally moving in gr0. */ |
4852 | if (value1 == 0 || value2 == 0) | |
4853 | ; | |
4854 | ||
4855 | /* If the first value is within an addi range and also the difference | |
4856 | between the two fits in an addi's range, load up the difference, then | |
4857 | conditionally move in 0, and then unconditionally add the first | |
4858 | value. */ | |
2f5b1308 JR |
4859 | else if (IN_RANGE (value1, -2048, 2047) |
4860 | && IN_RANGE (value2 - value1, -2048, 2047)) | |
36a05131 BS |
4861 | ; |
4862 | ||
4863 | /* If neither condition holds, just force the constant into a | |
4864 | register. */ | |
4865 | else | |
4866 | { | |
4867 | src1 = force_reg (GET_MODE (dest), src1); | |
4868 | src2 = force_reg (GET_MODE (dest), src2); | |
4869 | } | |
4870 | } | |
4871 | ||
4872 | /* If one value is a register, insure the other value is either 0 or a | |
4873 | register. */ | |
4874 | else | |
4875 | { | |
4876 | if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0) | |
4877 | src1 = force_reg (GET_MODE (dest), src1); | |
4878 | ||
4879 | if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0) | |
4880 | src2 = force_reg (GET_MODE (dest), src2); | |
4881 | } | |
4882 | ||
4883 | test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx); | |
4884 | if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2); | |
4885 | ||
f7df4a84 | 4886 | set = gen_rtx_SET (dest, if_rtx); |
36a05131 BS |
4887 | |
4888 | cr_reg = ((TARGET_ALLOC_CC) | |
4889 | ? gen_reg_rtx (CC_CCRmode) | |
4890 | : gen_rtx_REG (CC_CCRmode, | |
4891 | (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST)); | |
4892 | ||
4893 | clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg); | |
4894 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc))); | |
4895 | return TRUE; | |
4896 | } | |
4897 | ||
4898 | \f | |
839a4992 | 4899 | /* Split a conditional move into constituent parts, returning a SEQUENCE |
36a05131 BS |
4900 | containing all of the insns. */ |
4901 | ||
4902 | rtx | |
f2206911 | 4903 | frv_split_cond_move (rtx operands[]) |
36a05131 BS |
4904 | { |
4905 | rtx dest = operands[0]; | |
4906 | rtx test = operands[1]; | |
4907 | rtx cc_reg = operands[2]; | |
4908 | rtx src1 = operands[3]; | |
4909 | rtx src2 = operands[4]; | |
4910 | rtx cr_reg = operands[5]; | |
4911 | rtx ret; | |
ef4bddc2 | 4912 | machine_mode cr_mode = GET_MODE (cr_reg); |
36a05131 BS |
4913 | |
4914 | start_sequence (); | |
4915 | ||
4916 | /* Set the appropriate CCR bit. */ | |
f7df4a84 | 4917 | emit_insn (gen_rtx_SET (cr_reg, |
36a05131 BS |
4918 | gen_rtx_fmt_ee (GET_CODE (test), |
4919 | GET_MODE (cr_reg), | |
4920 | cc_reg, | |
4921 | const0_rtx))); | |
4922 | ||
4923 | /* Handle various cases of conditional move involving two constants. */ | |
4924 | if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT) | |
4925 | { | |
4926 | HOST_WIDE_INT value1 = INTVAL (src1); | |
4927 | HOST_WIDE_INT value2 = INTVAL (src2); | |
4928 | ||
87b483a1 | 4929 | /* Having 0 as one of the constants can be done by loading the other |
36a05131 BS |
4930 | constant, and optionally moving in gr0. */ |
4931 | if (value1 == 0) | |
4932 | { | |
4933 | emit_move_insn (dest, src2); | |
4934 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
4935 | gen_rtx_NE (cr_mode, cr_reg, | |
4936 | const0_rtx), | |
f7df4a84 | 4937 | gen_rtx_SET (dest, src1))); |
36a05131 BS |
4938 | } |
4939 | ||
4940 | else if (value2 == 0) | |
4941 | { | |
4942 | emit_move_insn (dest, src1); | |
4943 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
4944 | gen_rtx_EQ (cr_mode, cr_reg, | |
4945 | const0_rtx), | |
f7df4a84 | 4946 | gen_rtx_SET (dest, src2))); |
36a05131 BS |
4947 | } |
4948 | ||
4949 | /* If the first value is within an addi range and also the difference | |
4950 | between the two fits in an addi's range, load up the difference, then | |
4951 | conditionally move in 0, and then unconditionally add the first | |
4952 | value. */ | |
2f5b1308 JR |
4953 | else if (IN_RANGE (value1, -2048, 2047) |
4954 | && IN_RANGE (value2 - value1, -2048, 2047)) | |
36a05131 BS |
4955 | { |
4956 | rtx dest_si = ((GET_MODE (dest) == SImode) | |
4957 | ? dest | |
4958 | : gen_rtx_SUBREG (SImode, dest, 0)); | |
4959 | ||
4960 | emit_move_insn (dest_si, GEN_INT (value2 - value1)); | |
4961 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
4962 | gen_rtx_NE (cr_mode, cr_reg, | |
4963 | const0_rtx), | |
f7df4a84 | 4964 | gen_rtx_SET (dest_si, const0_rtx))); |
36a05131 BS |
4965 | emit_insn (gen_addsi3 (dest_si, dest_si, src1)); |
4966 | } | |
4967 | ||
4968 | else | |
44e91694 | 4969 | gcc_unreachable (); |
36a05131 BS |
4970 | } |
4971 | else | |
4972 | { | |
4973 | /* Emit the conditional move for the test being true if needed. */ | |
4974 | if (! rtx_equal_p (dest, src1)) | |
4975 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
4976 | gen_rtx_NE (cr_mode, cr_reg, const0_rtx), | |
f7df4a84 | 4977 | gen_rtx_SET (dest, src1))); |
36a05131 BS |
4978 | |
4979 | /* Emit the conditional move for the test being false if needed. */ | |
4980 | if (! rtx_equal_p (dest, src2)) | |
4981 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
4982 | gen_rtx_EQ (cr_mode, cr_reg, const0_rtx), | |
f7df4a84 | 4983 | gen_rtx_SET (dest, src2))); |
36a05131 BS |
4984 | } |
4985 | ||
4986 | /* Finish up, return sequence. */ | |
4987 | ret = get_insns (); | |
4988 | end_sequence (); | |
4989 | return ret; | |
4990 | } | |
4991 | ||
4992 | \f | |
4993 | /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a | |
4994 | memory location that is not known to be dword-aligned. */ | |
4995 | void | |
f2206911 | 4996 | frv_split_double_load (rtx dest, rtx source) |
36a05131 BS |
4997 | { |
4998 | int regno = REGNO (dest); | |
4999 | rtx dest1 = gen_highpart (SImode, dest); | |
5000 | rtx dest2 = gen_lowpart (SImode, dest); | |
5001 | rtx address = XEXP (source, 0); | |
5002 | ||
5003 | /* If the address is pre-modified, load the lower-numbered register | |
5004 | first, then load the other register using an integer offset from | |
5005 | the modified base register. This order should always be safe, | |
5006 | since the pre-modification cannot affect the same registers as the | |
5007 | load does. | |
5008 | ||
5009 | The situation for other loads is more complicated. Loading one | |
5010 | of the registers could affect the value of ADDRESS, so we must | |
5011 | be careful which order we do them in. */ | |
5012 | if (GET_CODE (address) == PRE_MODIFY | |
c9bd6bcd | 5013 | || ! refers_to_regno_p (regno, address)) |
36a05131 BS |
5014 | { |
5015 | /* It is safe to load the lower-numbered register first. */ | |
5016 | emit_move_insn (dest1, change_address (source, SImode, NULL)); | |
5017 | emit_move_insn (dest2, frv_index_memory (source, SImode, 1)); | |
5018 | } | |
5019 | else | |
5020 | { | |
5021 | /* ADDRESS is not pre-modified and the address depends on the | |
5022 | lower-numbered register. Load the higher-numbered register | |
5023 | first. */ | |
5024 | emit_move_insn (dest2, frv_index_memory (source, SImode, 1)); | |
5025 | emit_move_insn (dest1, change_address (source, SImode, NULL)); | |
5026 | } | |
5027 | } | |
5028 | ||
5029 | /* Split (set DEST SOURCE), where DEST refers to a dword memory location | |
5030 | and SOURCE is either a double register or the constant zero. */ | |
5031 | void | |
f2206911 | 5032 | frv_split_double_store (rtx dest, rtx source) |
36a05131 BS |
5033 | { |
5034 | rtx dest1 = change_address (dest, SImode, NULL); | |
5035 | rtx dest2 = frv_index_memory (dest, SImode, 1); | |
5036 | if (ZERO_P (source)) | |
5037 | { | |
5038 | emit_move_insn (dest1, CONST0_RTX (SImode)); | |
5039 | emit_move_insn (dest2, CONST0_RTX (SImode)); | |
5040 | } | |
5041 | else | |
5042 | { | |
5043 | emit_move_insn (dest1, gen_highpart (SImode, source)); | |
5044 | emit_move_insn (dest2, gen_lowpart (SImode, source)); | |
5045 | } | |
5046 | } | |
5047 | ||
5048 | \f | |
5049 | /* Split a min/max operation returning a SEQUENCE containing all of the | |
5050 | insns. */ | |
5051 | ||
5052 | rtx | |
f2206911 | 5053 | frv_split_minmax (rtx operands[]) |
36a05131 BS |
5054 | { |
5055 | rtx dest = operands[0]; | |
5056 | rtx minmax = operands[1]; | |
5057 | rtx src1 = operands[2]; | |
5058 | rtx src2 = operands[3]; | |
5059 | rtx cc_reg = operands[4]; | |
5060 | rtx cr_reg = operands[5]; | |
5061 | rtx ret; | |
5062 | enum rtx_code test_code; | |
ef4bddc2 | 5063 | machine_mode cr_mode = GET_MODE (cr_reg); |
36a05131 BS |
5064 | |
5065 | start_sequence (); | |
5066 | ||
87b483a1 | 5067 | /* Figure out which test to use. */ |
36a05131 BS |
5068 | switch (GET_CODE (minmax)) |
5069 | { | |
5070 | default: | |
44e91694 | 5071 | gcc_unreachable (); |
36a05131 BS |
5072 | |
5073 | case SMIN: test_code = LT; break; | |
5074 | case SMAX: test_code = GT; break; | |
5075 | case UMIN: test_code = LTU; break; | |
5076 | case UMAX: test_code = GTU; break; | |
5077 | } | |
5078 | ||
5079 | /* Issue the compare instruction. */ | |
f7df4a84 RS |
5080 | emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (GET_MODE (cc_reg), |
5081 | src1, src2))); | |
36a05131 BS |
5082 | |
5083 | /* Set the appropriate CCR bit. */ | |
f7df4a84 RS |
5084 | emit_insn (gen_rtx_SET (cr_reg, gen_rtx_fmt_ee (test_code, |
5085 | GET_MODE (cr_reg), | |
5086 | cc_reg, | |
5087 | const0_rtx))); | |
36a05131 | 5088 | |
9cd10576 | 5089 | /* If are taking the min/max of a nonzero constant, load that first, and |
36a05131 BS |
5090 | then do a conditional move of the other value. */ |
5091 | if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0) | |
5092 | { | |
44e91694 | 5093 | gcc_assert (!rtx_equal_p (dest, src1)); |
36a05131 BS |
5094 | |
5095 | emit_move_insn (dest, src2); | |
5096 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
5097 | gen_rtx_NE (cr_mode, cr_reg, const0_rtx), | |
f7df4a84 | 5098 | gen_rtx_SET (dest, src1))); |
36a05131 BS |
5099 | } |
5100 | ||
5101 | /* Otherwise, do each half of the move. */ | |
5102 | else | |
5103 | { | |
5104 | /* Emit the conditional move for the test being true if needed. */ | |
5105 | if (! rtx_equal_p (dest, src1)) | |
5106 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
5107 | gen_rtx_NE (cr_mode, cr_reg, const0_rtx), | |
f7df4a84 | 5108 | gen_rtx_SET (dest, src1))); |
36a05131 BS |
5109 | |
5110 | /* Emit the conditional move for the test being false if needed. */ | |
5111 | if (! rtx_equal_p (dest, src2)) | |
5112 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
5113 | gen_rtx_EQ (cr_mode, cr_reg, const0_rtx), | |
f7df4a84 | 5114 | gen_rtx_SET (dest, src2))); |
36a05131 BS |
5115 | } |
5116 | ||
5117 | /* Finish up, return sequence. */ | |
5118 | ret = get_insns (); | |
5119 | end_sequence (); | |
5120 | return ret; | |
5121 | } | |
5122 | ||
5123 | \f | |
5124 | /* Split an integer abs operation returning a SEQUENCE containing all of the | |
5125 | insns. */ | |
5126 | ||
5127 | rtx | |
f2206911 | 5128 | frv_split_abs (rtx operands[]) |
36a05131 BS |
5129 | { |
5130 | rtx dest = operands[0]; | |
5131 | rtx src = operands[1]; | |
5132 | rtx cc_reg = operands[2]; | |
5133 | rtx cr_reg = operands[3]; | |
5134 | rtx ret; | |
5135 | ||
5136 | start_sequence (); | |
5137 | ||
5138 | /* Issue the compare < 0 instruction. */ | |
f7df4a84 | 5139 | emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (CCmode, src, const0_rtx))); |
36a05131 BS |
5140 | |
5141 | /* Set the appropriate CCR bit. */ | |
f7df4a84 RS |
5142 | emit_insn (gen_rtx_SET (cr_reg, gen_rtx_fmt_ee (LT, CC_CCRmode, |
5143 | cc_reg, const0_rtx))); | |
36a05131 | 5144 | |
87b483a1 | 5145 | /* Emit the conditional negate if the value is negative. */ |
36a05131 BS |
5146 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, |
5147 | gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx), | |
5148 | gen_negsi2 (dest, src))); | |
5149 | ||
5150 | /* Emit the conditional move for the test being false if needed. */ | |
5151 | if (! rtx_equal_p (dest, src)) | |
5152 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
5153 | gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx), | |
f7df4a84 | 5154 | gen_rtx_SET (dest, src))); |
36a05131 BS |
5155 | |
5156 | /* Finish up, return sequence. */ | |
5157 | ret = get_insns (); | |
5158 | end_sequence (); | |
5159 | return ret; | |
5160 | } | |
5161 | ||
36a05131 | 5162 | \f |
67a0732f SB |
5163 | /* Initialize machine-specific if-conversion data. |
5164 | On the FR-V, we don't have any extra fields per se, but it is useful hook to | |
36a05131 BS |
5165 | initialize the static storage. */ |
5166 | void | |
afa63532 | 5167 | frv_ifcvt_machdep_init (void *ce_info ATTRIBUTE_UNUSED) |
36a05131 BS |
5168 | { |
5169 | frv_ifcvt.added_insns_list = NULL_RTX; | |
5170 | frv_ifcvt.cur_scratch_regs = 0; | |
5171 | frv_ifcvt.num_nested_cond_exec = 0; | |
5172 | frv_ifcvt.cr_reg = NULL_RTX; | |
5173 | frv_ifcvt.nested_cc_reg = NULL_RTX; | |
5174 | frv_ifcvt.extra_int_cr = NULL_RTX; | |
5175 | frv_ifcvt.extra_fp_cr = NULL_RTX; | |
5176 | frv_ifcvt.last_nested_if_cr = NULL_RTX; | |
5177 | } | |
5178 | ||
5179 | \f | |
1ae58c30 | 5180 | /* Internal function to add a potential insn to the list of insns to be inserted |
36a05131 BS |
5181 | if the conditional execution conversion is successful. */ |
5182 | ||
5183 | static void | |
f2206911 | 5184 | frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p) |
36a05131 BS |
5185 | { |
5186 | rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn); | |
5187 | ||
87b483a1 | 5188 | link->jump = before_p; /* Mark to add this before or after insn. */ |
36a05131 BS |
5189 | frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link, |
5190 | frv_ifcvt.added_insns_list); | |
5191 | ||
5192 | if (TARGET_DEBUG_COND_EXEC) | |
5193 | { | |
5194 | fprintf (stderr, | |
5195 | "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n", | |
5196 | (before_p) ? "before" : "after", | |
5197 | (int)INSN_UID (insn)); | |
5198 | ||
5199 | debug_rtx (pattern); | |
5200 | } | |
5201 | } | |
5202 | ||
5203 | \f | |
5204 | /* A C expression to modify the code described by the conditional if | |
5205 | information CE_INFO, possibly updating the tests in TRUE_EXPR, and | |
5206 | FALSE_EXPR for converting if-then and if-then-else code to conditional | |
5207 | instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the | |
5208 | tests cannot be converted. */ | |
5209 | ||
5210 | void | |
84562394 | 5211 | frv_ifcvt_modify_tests (ce_if_block *ce_info, rtx *p_true, rtx *p_false) |
36a05131 BS |
5212 | { |
5213 | basic_block test_bb = ce_info->test_bb; /* test basic block */ | |
5214 | basic_block then_bb = ce_info->then_bb; /* THEN */ | |
5215 | basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */ | |
5216 | basic_block join_bb = ce_info->join_bb; /* join block or NULL */ | |
5217 | rtx true_expr = *p_true; | |
5218 | rtx cr; | |
5219 | rtx cc; | |
5220 | rtx nested_cc; | |
ef4bddc2 | 5221 | machine_mode mode = GET_MODE (true_expr); |
36a05131 BS |
5222 | int j; |
5223 | basic_block *bb; | |
5224 | int num_bb; | |
5225 | frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg; | |
5226 | rtx check_insn; | |
5227 | rtx sub_cond_exec_reg; | |
5228 | enum rtx_code code; | |
5229 | enum rtx_code code_true; | |
5230 | enum rtx_code code_false; | |
5231 | enum reg_class cc_class; | |
5232 | enum reg_class cr_class; | |
5233 | int cc_first; | |
5234 | int cc_last; | |
a2041967 | 5235 | reg_set_iterator rsi; |
36a05131 BS |
5236 | |
5237 | /* Make sure we are only dealing with hard registers. Also honor the | |
5238 | -mno-cond-exec switch, and -mno-nested-cond-exec switches if | |
5239 | applicable. */ | |
0b2c18fe RS |
5240 | if (!reload_completed || !TARGET_COND_EXEC |
5241 | || (!TARGET_NESTED_CE && ce_info->pass > 1)) | |
36a05131 BS |
5242 | goto fail; |
5243 | ||
5244 | /* Figure out which registers we can allocate for our own purposes. Only | |
5245 | consider registers that are not preserved across function calls and are | |
5246 | not fixed. However, allow the ICC/ICR temporary registers to be allocated | |
87b483a1 | 5247 | if we did not need to use them in reloading other registers. */ |
fad205ff | 5248 | memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs)); |
36a05131 BS |
5249 | COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set); |
5250 | AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set); | |
5251 | SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP); | |
5252 | SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP); | |
5253 | ||
5254 | /* If this is a nested IF, we need to discover whether the CC registers that | |
5255 | are set/used inside of the block are used anywhere else. If not, we can | |
5256 | change them to be the CC register that is paired with the CR register that | |
5257 | controls the outermost IF block. */ | |
5258 | if (ce_info->pass > 1) | |
5259 | { | |
5260 | CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite); | |
5261 | for (j = CC_FIRST; j <= CC_LAST; j++) | |
5262 | if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) | |
5263 | { | |
eedd7243 | 5264 | if (REGNO_REG_SET_P (df_get_live_in (then_bb), j)) |
36a05131 BS |
5265 | continue; |
5266 | ||
5e2d947c | 5267 | if (else_bb |
eedd7243 | 5268 | && REGNO_REG_SET_P (df_get_live_in (else_bb), j)) |
36a05131 BS |
5269 | continue; |
5270 | ||
5e2d947c | 5271 | if (join_bb |
eedd7243 | 5272 | && REGNO_REG_SET_P (df_get_live_in (join_bb), j)) |
36a05131 BS |
5273 | continue; |
5274 | ||
5275 | SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j); | |
5276 | } | |
5277 | } | |
5278 | ||
5279 | for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++) | |
5280 | frv_ifcvt.scratch_regs[j] = NULL_RTX; | |
5281 | ||
5282 | frv_ifcvt.added_insns_list = NULL_RTX; | |
5283 | frv_ifcvt.cur_scratch_regs = 0; | |
5284 | ||
5285 | bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks) | |
5286 | * sizeof (basic_block)); | |
5287 | ||
5288 | if (join_bb) | |
5289 | { | |
38c28a25 | 5290 | unsigned int regno; |
36a05131 BS |
5291 | |
5292 | /* Remove anything live at the beginning of the join block from being | |
5293 | available for allocation. */ | |
eedd7243 | 5294 | EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb), 0, regno, rsi) |
a2041967 KH |
5295 | { |
5296 | if (regno < FIRST_PSEUDO_REGISTER) | |
5297 | CLEAR_HARD_REG_BIT (tmp_reg->regs, regno); | |
5298 | } | |
36a05131 BS |
5299 | } |
5300 | ||
5301 | /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */ | |
5302 | num_bb = 0; | |
5303 | if (ce_info->num_multiple_test_blocks) | |
5304 | { | |
5305 | basic_block multiple_test_bb = ce_info->last_test_bb; | |
5306 | ||
5307 | while (multiple_test_bb != test_bb) | |
5308 | { | |
5309 | bb[num_bb++] = multiple_test_bb; | |
628f6a4e | 5310 | multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src; |
36a05131 BS |
5311 | } |
5312 | } | |
5313 | ||
5314 | /* Add in the THEN and ELSE blocks to be scanned. */ | |
5315 | bb[num_bb++] = then_bb; | |
5316 | if (else_bb) | |
5317 | bb[num_bb++] = else_bb; | |
5318 | ||
5319 | sub_cond_exec_reg = NULL_RTX; | |
5320 | frv_ifcvt.num_nested_cond_exec = 0; | |
5321 | ||
5322 | /* Scan all of the blocks for registers that must not be allocated. */ | |
5323 | for (j = 0; j < num_bb; j++) | |
5324 | { | |
b32d5189 DM |
5325 | rtx_insn *last_insn = BB_END (bb[j]); |
5326 | rtx_insn *insn = BB_HEAD (bb[j]); | |
38c28a25 | 5327 | unsigned int regno; |
36a05131 | 5328 | |
c263766c RH |
5329 | if (dump_file) |
5330 | fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n", | |
36a05131 BS |
5331 | (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"), |
5332 | (int) bb[j]->index, | |
a813c111 SB |
5333 | (int) INSN_UID (BB_HEAD (bb[j])), |
5334 | (int) INSN_UID (BB_END (bb[j]))); | |
36a05131 BS |
5335 | |
5336 | /* Anything live at the beginning of the block is obviously unavailable | |
5337 | for allocation. */ | |
eedd7243 | 5338 | EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb[j]), 0, regno, rsi) |
a2041967 KH |
5339 | { |
5340 | if (regno < FIRST_PSEUDO_REGISTER) | |
5341 | CLEAR_HARD_REG_BIT (tmp_reg->regs, regno); | |
5342 | } | |
36a05131 | 5343 | |
87b483a1 | 5344 | /* Loop through the insns in the block. */ |
36a05131 BS |
5345 | for (;;) |
5346 | { | |
5347 | /* Mark any new registers that are created as being unavailable for | |
5348 | allocation. Also see if the CC register used in nested IFs can be | |
5349 | reallocated. */ | |
5350 | if (INSN_P (insn)) | |
5351 | { | |
5352 | rtx pattern; | |
5353 | rtx set; | |
5354 | int skip_nested_if = FALSE; | |
7e8e4cf9 | 5355 | HARD_REG_SET mentioned_regs; |
36a05131 | 5356 | |
7e8e4cf9 RS |
5357 | CLEAR_HARD_REG_SET (mentioned_regs); |
5358 | find_all_hard_regs (PATTERN (insn), &mentioned_regs); | |
5359 | AND_COMPL_HARD_REG_SET (tmp_reg->regs, mentioned_regs); | |
36a05131 BS |
5360 | |
5361 | pattern = PATTERN (insn); | |
5362 | if (GET_CODE (pattern) == COND_EXEC) | |
5363 | { | |
5364 | rtx reg = XEXP (COND_EXEC_TEST (pattern), 0); | |
5365 | ||
5366 | if (reg != sub_cond_exec_reg) | |
5367 | { | |
5368 | sub_cond_exec_reg = reg; | |
5369 | frv_ifcvt.num_nested_cond_exec++; | |
5370 | } | |
5371 | } | |
5372 | ||
5373 | set = single_set_pattern (pattern); | |
5374 | if (set) | |
5375 | { | |
5376 | rtx dest = SET_DEST (set); | |
5377 | rtx src = SET_SRC (set); | |
5378 | ||
5379 | if (GET_CODE (dest) == REG) | |
5380 | { | |
5381 | int regno = REGNO (dest); | |
5382 | enum rtx_code src_code = GET_CODE (src); | |
5383 | ||
5384 | if (CC_P (regno) && src_code == COMPARE) | |
5385 | skip_nested_if = TRUE; | |
5386 | ||
5387 | else if (CR_P (regno) | |
5388 | && (src_code == IF_THEN_ELSE | |
ec8e098d | 5389 | || COMPARISON_P (src))) |
36a05131 BS |
5390 | skip_nested_if = TRUE; |
5391 | } | |
5392 | } | |
5393 | ||
5394 | if (! skip_nested_if) | |
7e8e4cf9 RS |
5395 | AND_COMPL_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite, |
5396 | mentioned_regs); | |
36a05131 BS |
5397 | } |
5398 | ||
5399 | if (insn == last_insn) | |
5400 | break; | |
5401 | ||
5402 | insn = NEXT_INSN (insn); | |
5403 | } | |
5404 | } | |
5405 | ||
5406 | /* If this is a nested if, rewrite the CC registers that are available to | |
5407 | include the ones that can be rewritten, to increase the chance of being | |
5408 | able to allocate a paired CC/CR register combination. */ | |
5409 | if (ce_info->pass > 1) | |
5410 | { | |
5411 | for (j = CC_FIRST; j <= CC_LAST; j++) | |
5412 | if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j)) | |
5413 | SET_HARD_REG_BIT (tmp_reg->regs, j); | |
5414 | else | |
5415 | CLEAR_HARD_REG_BIT (tmp_reg->regs, j); | |
5416 | } | |
5417 | ||
c263766c | 5418 | if (dump_file) |
36a05131 BS |
5419 | { |
5420 | int num_gprs = 0; | |
c263766c | 5421 | fprintf (dump_file, "Available GPRs: "); |
36a05131 BS |
5422 | |
5423 | for (j = GPR_FIRST; j <= GPR_LAST; j++) | |
5424 | if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) | |
5425 | { | |
c263766c | 5426 | fprintf (dump_file, " %d [%s]", j, reg_names[j]); |
36a05131 BS |
5427 | if (++num_gprs > GPR_TEMP_NUM+2) |
5428 | break; | |
5429 | } | |
5430 | ||
c263766c | 5431 | fprintf (dump_file, "%s\nAvailable CRs: ", |
36a05131 BS |
5432 | (num_gprs > GPR_TEMP_NUM+2) ? " ..." : ""); |
5433 | ||
5434 | for (j = CR_FIRST; j <= CR_LAST; j++) | |
5435 | if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) | |
c263766c | 5436 | fprintf (dump_file, " %d [%s]", j, reg_names[j]); |
36a05131 | 5437 | |
c263766c | 5438 | fputs ("\n", dump_file); |
36a05131 BS |
5439 | |
5440 | if (ce_info->pass > 1) | |
5441 | { | |
c263766c | 5442 | fprintf (dump_file, "Modifiable CCs: "); |
36a05131 BS |
5443 | for (j = CC_FIRST; j <= CC_LAST; j++) |
5444 | if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) | |
c263766c | 5445 | fprintf (dump_file, " %d [%s]", j, reg_names[j]); |
36a05131 | 5446 | |
c263766c | 5447 | fprintf (dump_file, "\n%d nested COND_EXEC statements\n", |
36a05131 BS |
5448 | frv_ifcvt.num_nested_cond_exec); |
5449 | } | |
5450 | } | |
5451 | ||
5452 | /* Allocate the appropriate temporary condition code register. Try to | |
5453 | allocate the ICR/FCR register that corresponds to the ICC/FCC register so | |
5454 | that conditional cmp's can be done. */ | |
036ff63f | 5455 | if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode) |
36a05131 BS |
5456 | { |
5457 | cr_class = ICR_REGS; | |
5458 | cc_class = ICC_REGS; | |
5459 | cc_first = ICC_FIRST; | |
5460 | cc_last = ICC_LAST; | |
5461 | } | |
5462 | else if (mode == CC_FPmode) | |
5463 | { | |
5464 | cr_class = FCR_REGS; | |
5465 | cc_class = FCC_REGS; | |
5466 | cc_first = FCC_FIRST; | |
5467 | cc_last = FCC_LAST; | |
5468 | } | |
5469 | else | |
5470 | { | |
5471 | cc_first = cc_last = 0; | |
5472 | cr_class = cc_class = NO_REGS; | |
5473 | } | |
5474 | ||
5475 | cc = XEXP (true_expr, 0); | |
5476 | nested_cc = cr = NULL_RTX; | |
5477 | if (cc_class != NO_REGS) | |
5478 | { | |
5479 | /* For nested IFs and &&/||, see if we can find a CC and CR register pair | |
5480 | so we can execute a csubcc/caddcc/cfcmps instruction. */ | |
5481 | int cc_regno; | |
5482 | ||
5483 | for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++) | |
5484 | { | |
5485 | int cr_regno = cc_regno - CC_FIRST + CR_FIRST; | |
5486 | ||
5487 | if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno) | |
5488 | && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno)) | |
5489 | { | |
5490 | frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno; | |
5491 | cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE, | |
5492 | TRUE); | |
5493 | ||
5494 | frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno; | |
5495 | nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode, | |
5496 | TRUE, TRUE); | |
5497 | break; | |
5498 | } | |
5499 | } | |
5500 | } | |
5501 | ||
5502 | if (! cr) | |
5503 | { | |
c263766c RH |
5504 | if (dump_file) |
5505 | fprintf (dump_file, "Could not allocate a CR temporary register\n"); | |
36a05131 BS |
5506 | |
5507 | goto fail; | |
5508 | } | |
5509 | ||
c263766c RH |
5510 | if (dump_file) |
5511 | fprintf (dump_file, | |
36a05131 BS |
5512 | "Will use %s for conditional execution, %s for nested comparisons\n", |
5513 | reg_names[ REGNO (cr)], | |
5514 | (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>"); | |
5515 | ||
5516 | /* Set the CCR bit. Note for integer tests, we reverse the condition so that | |
5517 | in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR | |
5518 | bit being true. We don't do this for floating point, because of NaNs. */ | |
5519 | code = GET_CODE (true_expr); | |
5520 | if (GET_MODE (cc) != CC_FPmode) | |
5521 | { | |
5522 | code = reverse_condition (code); | |
5523 | code_true = EQ; | |
5524 | code_false = NE; | |
5525 | } | |
5526 | else | |
5527 | { | |
5528 | code_true = NE; | |
5529 | code_false = EQ; | |
5530 | } | |
5531 | ||
f7df4a84 RS |
5532 | check_insn = gen_rtx_SET (cr, gen_rtx_fmt_ee (code, CC_CCRmode, |
5533 | cc, const0_rtx)); | |
36a05131 BS |
5534 | |
5535 | /* Record the check insn to be inserted later. */ | |
a813c111 | 5536 | frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE); |
36a05131 BS |
5537 | |
5538 | /* Update the tests. */ | |
5539 | frv_ifcvt.cr_reg = cr; | |
5540 | frv_ifcvt.nested_cc_reg = nested_cc; | |
5541 | *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx); | |
5542 | *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx); | |
5543 | return; | |
5544 | ||
5545 | /* Fail, don't do this conditional execution. */ | |
5546 | fail: | |
5547 | *p_true = NULL_RTX; | |
5548 | *p_false = NULL_RTX; | |
c263766c RH |
5549 | if (dump_file) |
5550 | fprintf (dump_file, "Disabling this conditional execution.\n"); | |
36a05131 BS |
5551 | |
5552 | return; | |
5553 | } | |
5554 | ||
5555 | \f | |
5556 | /* A C expression to modify the code described by the conditional if | |
5557 | information CE_INFO, for the basic block BB, possibly updating the tests in | |
5558 | TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or | |
5559 | if-then-else code to conditional instructions. Set either TRUE_EXPR or | |
5560 | FALSE_EXPR to a null pointer if the tests cannot be converted. */ | |
5561 | ||
5562 | /* p_true and p_false are given expressions of the form: | |
5563 | ||
5564 | (and (eq:CC_CCR (reg:CC_CCR) | |
5565 | (const_int 0)) | |
5566 | (eq:CC (reg:CC) | |
5567 | (const_int 0))) */ | |
5568 | ||
5569 | void | |
84562394 | 5570 | frv_ifcvt_modify_multiple_tests (ce_if_block *ce_info, |
f2206911 KC |
5571 | basic_block bb, |
5572 | rtx *p_true, | |
5573 | rtx *p_false) | |
36a05131 BS |
5574 | { |
5575 | rtx old_true = XEXP (*p_true, 0); | |
5576 | rtx old_false = XEXP (*p_false, 0); | |
5577 | rtx true_expr = XEXP (*p_true, 1); | |
5578 | rtx false_expr = XEXP (*p_false, 1); | |
5579 | rtx test_expr; | |
5580 | rtx old_test; | |
5581 | rtx cr = XEXP (old_true, 0); | |
5582 | rtx check_insn; | |
5583 | rtx new_cr = NULL_RTX; | |
5584 | rtx *p_new_cr = (rtx *)0; | |
5585 | rtx if_else; | |
5586 | rtx compare; | |
5587 | rtx cc; | |
5588 | enum reg_class cr_class; | |
ef4bddc2 | 5589 | machine_mode mode = GET_MODE (true_expr); |
36a05131 BS |
5590 | rtx (*logical_func)(rtx, rtx, rtx); |
5591 | ||
5592 | if (TARGET_DEBUG_COND_EXEC) | |
5593 | { | |
5594 | fprintf (stderr, | |
5595 | "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n", | |
5596 | ce_info->and_and_p ? "&&" : "||"); | |
5597 | ||
5598 | debug_rtx (*p_true); | |
5599 | ||
5600 | fputs ("\nfalse insn:\n", stderr); | |
5601 | debug_rtx (*p_false); | |
5602 | } | |
5603 | ||
0b2c18fe | 5604 | if (!TARGET_MULTI_CE) |
36a05131 BS |
5605 | goto fail; |
5606 | ||
5607 | if (GET_CODE (cr) != REG) | |
5608 | goto fail; | |
b16c1435 | 5609 | |
036ff63f | 5610 | if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode) |
36a05131 BS |
5611 | { |
5612 | cr_class = ICR_REGS; | |
5613 | p_new_cr = &frv_ifcvt.extra_int_cr; | |
5614 | } | |
5615 | else if (mode == CC_FPmode) | |
5616 | { | |
5617 | cr_class = FCR_REGS; | |
5618 | p_new_cr = &frv_ifcvt.extra_fp_cr; | |
5619 | } | |
5620 | else | |
5621 | goto fail; | |
5622 | ||
5623 | /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or | |
5624 | more &&/|| tests. */ | |
5625 | new_cr = *p_new_cr; | |
5626 | if (! new_cr) | |
5627 | { | |
5628 | new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class, | |
5629 | CC_CCRmode, TRUE, TRUE); | |
5630 | if (! new_cr) | |
5631 | goto fail; | |
5632 | } | |
5633 | ||
5634 | if (ce_info->and_and_p) | |
5635 | { | |
5636 | old_test = old_false; | |
5637 | test_expr = true_expr; | |
5638 | logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr; | |
5639 | *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx); | |
5640 | *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx); | |
5641 | } | |
5642 | else | |
5643 | { | |
5644 | old_test = old_false; | |
5645 | test_expr = false_expr; | |
5646 | logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr; | |
5647 | *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx); | |
5648 | *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx); | |
5649 | } | |
5650 | ||
5651 | /* First add the andcr/andncr/orcr/orncr, which will be added after the | |
5652 | conditional check instruction, due to frv_ifcvt_add_insn being a LIFO | |
5653 | stack. */ | |
a813c111 | 5654 | frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE); |
36a05131 BS |
5655 | |
5656 | /* Now add the conditional check insn. */ | |
5657 | cc = XEXP (test_expr, 0); | |
5658 | compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx); | |
5659 | if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx); | |
5660 | ||
f7df4a84 | 5661 | check_insn = gen_rtx_SET (new_cr, if_else); |
36a05131 | 5662 | |
87b483a1 | 5663 | /* Add the new check insn to the list of check insns that need to be |
36a05131 | 5664 | inserted. */ |
a813c111 | 5665 | frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE); |
36a05131 BS |
5666 | |
5667 | if (TARGET_DEBUG_COND_EXEC) | |
5668 | { | |
5669 | fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n", | |
5670 | stderr); | |
5671 | ||
5672 | debug_rtx (*p_true); | |
5673 | ||
5674 | fputs ("\nfalse insn:\n", stderr); | |
5675 | debug_rtx (*p_false); | |
5676 | } | |
5677 | ||
5678 | return; | |
5679 | ||
5680 | fail: | |
5681 | *p_true = *p_false = NULL_RTX; | |
5682 | ||
87b483a1 | 5683 | /* If we allocated a CR register, release it. */ |
36a05131 BS |
5684 | if (new_cr) |
5685 | { | |
5686 | CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr)); | |
5687 | *p_new_cr = NULL_RTX; | |
5688 | } | |
5689 | ||
5690 | if (TARGET_DEBUG_COND_EXEC) | |
5691 | fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr); | |
5692 | ||
5693 | return; | |
5694 | } | |
5695 | ||
5696 | \f | |
5697 | /* Return a register which will be loaded with a value if an IF block is | |
5698 | converted to conditional execution. This is used to rewrite instructions | |
5699 | that use constants to ones that just use registers. */ | |
5700 | ||
5701 | static rtx | |
f2206911 | 5702 | frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED) |
36a05131 BS |
5703 | { |
5704 | int num_alloc = frv_ifcvt.cur_scratch_regs; | |
5705 | int i; | |
5706 | rtx reg; | |
5707 | ||
5708 | /* We know gr0 == 0, so replace any errant uses. */ | |
5709 | if (value == const0_rtx) | |
5710 | return gen_rtx_REG (SImode, GPR_FIRST); | |
5711 | ||
5712 | /* First search all registers currently loaded to see if we have an | |
5713 | applicable constant. */ | |
5714 | if (CONSTANT_P (value) | |
5715 | || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)) | |
5716 | { | |
5717 | for (i = 0; i < num_alloc; i++) | |
5718 | { | |
5719 | if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value)) | |
5720 | return SET_DEST (frv_ifcvt.scratch_regs[i]); | |
5721 | } | |
5722 | } | |
5723 | ||
87b483a1 | 5724 | /* Have we exhausted the number of registers available? */ |
36a05131 BS |
5725 | if (num_alloc >= GPR_TEMP_NUM) |
5726 | { | |
c263766c RH |
5727 | if (dump_file) |
5728 | fprintf (dump_file, "Too many temporary registers allocated\n"); | |
36a05131 BS |
5729 | |
5730 | return NULL_RTX; | |
5731 | } | |
5732 | ||
5733 | /* Allocate the new register. */ | |
5734 | reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE); | |
5735 | if (! reg) | |
5736 | { | |
c263766c RH |
5737 | if (dump_file) |
5738 | fputs ("Could not find a scratch register\n", dump_file); | |
36a05131 BS |
5739 | |
5740 | return NULL_RTX; | |
5741 | } | |
5742 | ||
5743 | frv_ifcvt.cur_scratch_regs++; | |
f7df4a84 | 5744 | frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (reg, value); |
36a05131 | 5745 | |
c263766c | 5746 | if (dump_file) |
36a05131 BS |
5747 | { |
5748 | if (GET_CODE (value) == CONST_INT) | |
c263766c | 5749 | fprintf (dump_file, "Register %s will hold %ld\n", |
36a05131 BS |
5750 | reg_names[ REGNO (reg)], (long)INTVAL (value)); |
5751 | ||
5752 | else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO) | |
c263766c | 5753 | fprintf (dump_file, "Register %s will hold LR\n", |
36a05131 BS |
5754 | reg_names[ REGNO (reg)]); |
5755 | ||
5756 | else | |
c263766c | 5757 | fprintf (dump_file, "Register %s will hold a saved value\n", |
36a05131 BS |
5758 | reg_names[ REGNO (reg)]); |
5759 | } | |
5760 | ||
5761 | return reg; | |
5762 | } | |
5763 | ||
5764 | \f | |
5765 | /* Update a MEM used in conditional code that might contain an offset to put | |
5766 | the offset into a scratch register, so that the conditional load/store | |
5767 | operations can be used. This function returns the original pointer if the | |
5768 | MEM is valid to use in conditional code, NULL if we can't load up the offset | |
5769 | into a temporary register, or the new MEM if we were successful. */ | |
5770 | ||
5771 | static rtx | |
ef4bddc2 | 5772 | frv_ifcvt_rewrite_mem (rtx mem, machine_mode mode, rtx insn) |
36a05131 BS |
5773 | { |
5774 | rtx addr = XEXP (mem, 0); | |
5775 | ||
c6c3dba9 | 5776 | if (!frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE)) |
36a05131 BS |
5777 | { |
5778 | if (GET_CODE (addr) == PLUS) | |
5779 | { | |
5780 | rtx addr_op0 = XEXP (addr, 0); | |
5781 | rtx addr_op1 = XEXP (addr, 1); | |
5782 | ||
34208acf | 5783 | if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1)) |
36a05131 BS |
5784 | { |
5785 | rtx reg = frv_ifcvt_load_value (addr_op1, insn); | |
5786 | if (!reg) | |
5787 | return NULL_RTX; | |
5788 | ||
5789 | addr = gen_rtx_PLUS (Pmode, addr_op0, reg); | |
5790 | } | |
5791 | ||
5792 | else | |
5793 | return NULL_RTX; | |
5794 | } | |
5795 | ||
5796 | else if (CONSTANT_P (addr)) | |
5797 | addr = frv_ifcvt_load_value (addr, insn); | |
5798 | ||
5799 | else | |
5800 | return NULL_RTX; | |
5801 | ||
5802 | if (addr == NULL_RTX) | |
5803 | return NULL_RTX; | |
5804 | ||
5805 | else if (XEXP (mem, 0) != addr) | |
5806 | return change_address (mem, mode, addr); | |
5807 | } | |
5808 | ||
5809 | return mem; | |
5810 | } | |
5811 | ||
5812 | \f | |
5813 | /* Given a PATTERN, return a SET expression if this PATTERN has only a single | |
5814 | SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */ | |
5815 | ||
5816 | static rtx | |
f2206911 | 5817 | single_set_pattern (rtx pattern) |
36a05131 BS |
5818 | { |
5819 | rtx set; | |
5820 | int i; | |
5821 | ||
5822 | if (GET_CODE (pattern) == COND_EXEC) | |
5823 | pattern = COND_EXEC_CODE (pattern); | |
5824 | ||
5825 | if (GET_CODE (pattern) == SET) | |
5826 | return pattern; | |
5827 | ||
5828 | else if (GET_CODE (pattern) == PARALLEL) | |
5829 | { | |
5830 | for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++) | |
5831 | { | |
5832 | rtx sub = XVECEXP (pattern, 0, i); | |
5833 | ||
5834 | switch (GET_CODE (sub)) | |
5835 | { | |
5836 | case USE: | |
5837 | case CLOBBER: | |
5838 | break; | |
5839 | ||
5840 | case SET: | |
5841 | if (set) | |
5842 | return 0; | |
5843 | else | |
5844 | set = sub; | |
5845 | break; | |
5846 | ||
5847 | default: | |
5848 | return 0; | |
5849 | } | |
5850 | } | |
5851 | return set; | |
5852 | } | |
5853 | ||
5854 | return 0; | |
5855 | } | |
5856 | ||
5857 | \f | |
5858 | /* A C expression to modify the code described by the conditional if | |
5859 | information CE_INFO with the new PATTERN in INSN. If PATTERN is a null | |
5860 | pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that | |
5861 | insn cannot be converted to be executed conditionally. */ | |
5862 | ||
5863 | rtx | |
84562394 | 5864 | frv_ifcvt_modify_insn (ce_if_block *ce_info, |
f2206911 KC |
5865 | rtx pattern, |
5866 | rtx insn) | |
36a05131 BS |
5867 | { |
5868 | rtx orig_ce_pattern = pattern; | |
5869 | rtx set; | |
5870 | rtx op0; | |
5871 | rtx op1; | |
5872 | rtx test; | |
5873 | ||
44e91694 | 5874 | gcc_assert (GET_CODE (pattern) == COND_EXEC); |
36a05131 BS |
5875 | |
5876 | test = COND_EXEC_TEST (pattern); | |
5877 | if (GET_CODE (test) == AND) | |
5878 | { | |
5879 | rtx cr = frv_ifcvt.cr_reg; | |
5880 | rtx test_reg; | |
5881 | ||
5882 | op0 = XEXP (test, 0); | |
5883 | if (! rtx_equal_p (cr, XEXP (op0, 0))) | |
5884 | goto fail; | |
5885 | ||
5886 | op1 = XEXP (test, 1); | |
5887 | test_reg = XEXP (op1, 0); | |
5888 | if (GET_CODE (test_reg) != REG) | |
5889 | goto fail; | |
5890 | ||
5891 | /* Is this the first nested if block in this sequence? If so, generate | |
5892 | an andcr or andncr. */ | |
5893 | if (! frv_ifcvt.last_nested_if_cr) | |
5894 | { | |
5895 | rtx and_op; | |
5896 | ||
5897 | frv_ifcvt.last_nested_if_cr = test_reg; | |
5898 | if (GET_CODE (op0) == NE) | |
5899 | and_op = gen_andcr (test_reg, cr, test_reg); | |
5900 | else | |
5901 | and_op = gen_andncr (test_reg, cr, test_reg); | |
5902 | ||
5903 | frv_ifcvt_add_insn (and_op, insn, TRUE); | |
5904 | } | |
5905 | ||
5906 | /* If this isn't the first statement in the nested if sequence, see if we | |
5907 | are dealing with the same register. */ | |
5908 | else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr)) | |
5909 | goto fail; | |
5910 | ||
5911 | COND_EXEC_TEST (pattern) = test = op1; | |
5912 | } | |
5913 | ||
5914 | /* If this isn't a nested if, reset state variables. */ | |
5915 | else | |
5916 | { | |
5917 | frv_ifcvt.last_nested_if_cr = NULL_RTX; | |
5918 | } | |
5919 | ||
5920 | set = single_set_pattern (pattern); | |
5921 | if (set) | |
5922 | { | |
5923 | rtx dest = SET_DEST (set); | |
5924 | rtx src = SET_SRC (set); | |
ef4bddc2 | 5925 | machine_mode mode = GET_MODE (dest); |
36a05131 | 5926 | |
87b483a1 | 5927 | /* Check for normal binary operators. */ |
ec8e098d | 5928 | if (mode == SImode && ARITHMETIC_P (src)) |
36a05131 BS |
5929 | { |
5930 | op0 = XEXP (src, 0); | |
5931 | op1 = XEXP (src, 1); | |
5932 | ||
34208acf | 5933 | if (integer_register_operand (op0, SImode) && CONSTANT_P (op1)) |
36a05131 BS |
5934 | { |
5935 | op1 = frv_ifcvt_load_value (op1, insn); | |
5936 | if (op1) | |
5937 | COND_EXEC_CODE (pattern) | |
f7df4a84 RS |
5938 | = gen_rtx_SET (dest, gen_rtx_fmt_ee (GET_CODE (src), |
5939 | GET_MODE (src), | |
5940 | op0, op1)); | |
36a05131 BS |
5941 | else |
5942 | goto fail; | |
5943 | } | |
5944 | } | |
5945 | ||
5946 | /* For multiply by a constant, we need to handle the sign extending | |
5947 | correctly. Add a USE of the value after the multiply to prevent flow | |
5948 | from cratering because only one register out of the two were used. */ | |
5949 | else if (mode == DImode && GET_CODE (src) == MULT) | |
5950 | { | |
5951 | op0 = XEXP (src, 0); | |
5952 | op1 = XEXP (src, 1); | |
5953 | if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT) | |
5954 | { | |
5955 | op1 = frv_ifcvt_load_value (op1, insn); | |
5956 | if (op1) | |
5957 | { | |
5958 | op1 = gen_rtx_SIGN_EXTEND (DImode, op1); | |
5959 | COND_EXEC_CODE (pattern) | |
f7df4a84 | 5960 | = gen_rtx_SET (dest, gen_rtx_MULT (DImode, op0, op1)); |
36a05131 BS |
5961 | } |
5962 | else | |
5963 | goto fail; | |
5964 | } | |
5965 | ||
c41c1387 | 5966 | frv_ifcvt_add_insn (gen_use (dest), insn, FALSE); |
36a05131 BS |
5967 | } |
5968 | ||
5969 | /* If we are just loading a constant created for a nested conditional | |
5970 | execution statement, just load the constant without any conditional | |
5971 | execution, since we know that the constant will not interfere with any | |
5972 | other registers. */ | |
5973 | else if (frv_ifcvt.scratch_insns_bitmap | |
5974 | && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap, | |
5da1fd3d | 5975 | INSN_UID (insn)) |
5da1fd3d | 5976 | && REG_P (SET_DEST (set)) |
9a228f09 AO |
5977 | /* We must not unconditionally set a scratch reg chosen |
5978 | for a nested if-converted block if its incoming | |
5979 | value from the TEST block (or the result of the THEN | |
5980 | branch) could/should propagate to the JOIN block. | |
5981 | It suffices to test whether the register is live at | |
5982 | the JOIN point: if it's live there, we can infer | |
5983 | that we set it in the former JOIN block of the | |
5984 | nested if-converted block (otherwise it wouldn't | |
5985 | have been available as a scratch register), and it | |
5986 | is either propagated through or set in the other | |
5987 | conditional block. It's probably not worth trying | |
5988 | to catch the latter case, and it could actually | |
5989 | limit scheduling of the combined block quite | |
5990 | severely. */ | |
5991 | && ce_info->join_bb | |
eedd7243 RIL |
5992 | && ! (REGNO_REG_SET_P (df_get_live_in (ce_info->join_bb), |
5993 | REGNO (SET_DEST (set)))) | |
9a228f09 AO |
5994 | /* Similarly, we must not unconditionally set a reg |
5995 | used as scratch in the THEN branch if the same reg | |
5996 | is live in the ELSE branch. */ | |
5da1fd3d AO |
5997 | && (! ce_info->else_bb |
5998 | || BLOCK_FOR_INSN (insn) == ce_info->else_bb | |
eedd7243 RIL |
5999 | || ! (REGNO_REG_SET_P (df_get_live_in (ce_info->else_bb), |
6000 | REGNO (SET_DEST (set)))))) | |
36a05131 BS |
6001 | pattern = set; |
6002 | ||
6003 | else if (mode == QImode || mode == HImode || mode == SImode | |
6004 | || mode == SFmode) | |
6005 | { | |
6006 | int changed_p = FALSE; | |
6007 | ||
6008 | /* Check for just loading up a constant */ | |
6009 | if (CONSTANT_P (src) && integer_register_operand (dest, mode)) | |
6010 | { | |
6011 | src = frv_ifcvt_load_value (src, insn); | |
6012 | if (!src) | |
6013 | goto fail; | |
6014 | ||
6015 | changed_p = TRUE; | |
6016 | } | |
6017 | ||
6018 | /* See if we need to fix up stores */ | |
6019 | if (GET_CODE (dest) == MEM) | |
6020 | { | |
6021 | rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn); | |
6022 | ||
6023 | if (!new_mem) | |
6024 | goto fail; | |
6025 | ||
6026 | else if (new_mem != dest) | |
6027 | { | |
6028 | changed_p = TRUE; | |
6029 | dest = new_mem; | |
6030 | } | |
6031 | } | |
6032 | ||
6033 | /* See if we need to fix up loads */ | |
6034 | if (GET_CODE (src) == MEM) | |
6035 | { | |
6036 | rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn); | |
6037 | ||
6038 | if (!new_mem) | |
6039 | goto fail; | |
6040 | ||
6041 | else if (new_mem != src) | |
6042 | { | |
6043 | changed_p = TRUE; | |
6044 | src = new_mem; | |
6045 | } | |
6046 | } | |
6047 | ||
6048 | /* If either src or destination changed, redo SET. */ | |
6049 | if (changed_p) | |
f7df4a84 | 6050 | COND_EXEC_CODE (pattern) = gen_rtx_SET (dest, src); |
36a05131 BS |
6051 | } |
6052 | ||
6053 | /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with | |
6054 | rewriting the CC register to be the same as the paired CC/CR register | |
6055 | for nested ifs. */ | |
ec8e098d | 6056 | else if (mode == CC_CCRmode && COMPARISON_P (src)) |
36a05131 BS |
6057 | { |
6058 | int regno = REGNO (XEXP (src, 0)); | |
6059 | rtx if_else; | |
6060 | ||
6061 | if (ce_info->pass > 1 | |
6062 | && regno != (int)REGNO (frv_ifcvt.nested_cc_reg) | |
6063 | && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno)) | |
6064 | { | |
6065 | src = gen_rtx_fmt_ee (GET_CODE (src), | |
6066 | CC_CCRmode, | |
6067 | frv_ifcvt.nested_cc_reg, | |
6068 | XEXP (src, 1)); | |
6069 | } | |
6070 | ||
6071 | if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx); | |
f7df4a84 | 6072 | pattern = gen_rtx_SET (dest, if_else); |
36a05131 BS |
6073 | } |
6074 | ||
6075 | /* Remap a nested compare instruction to use the paired CC/CR reg. */ | |
6076 | else if (ce_info->pass > 1 | |
6077 | && GET_CODE (dest) == REG | |
6078 | && CC_P (REGNO (dest)) | |
6079 | && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg) | |
6080 | && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, | |
6081 | REGNO (dest)) | |
6082 | && GET_CODE (src) == COMPARE) | |
6083 | { | |
6084 | PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest)); | |
6085 | COND_EXEC_CODE (pattern) | |
f7df4a84 | 6086 | = gen_rtx_SET (frv_ifcvt.nested_cc_reg, copy_rtx (src)); |
36a05131 BS |
6087 | } |
6088 | } | |
6089 | ||
6090 | if (TARGET_DEBUG_COND_EXEC) | |
6091 | { | |
6092 | rtx orig_pattern = PATTERN (insn); | |
6093 | ||
6094 | PATTERN (insn) = pattern; | |
6095 | fprintf (stderr, | |
6096 | "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n", | |
6097 | ce_info->pass); | |
6098 | ||
6099 | debug_rtx (insn); | |
6100 | PATTERN (insn) = orig_pattern; | |
6101 | } | |
6102 | ||
6103 | return pattern; | |
6104 | ||
6105 | fail: | |
6106 | if (TARGET_DEBUG_COND_EXEC) | |
6107 | { | |
6108 | rtx orig_pattern = PATTERN (insn); | |
6109 | ||
6110 | PATTERN (insn) = orig_ce_pattern; | |
6111 | fprintf (stderr, | |
6112 | "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n", | |
6113 | ce_info->pass); | |
6114 | ||
6115 | debug_rtx (insn); | |
6116 | PATTERN (insn) = orig_pattern; | |
6117 | } | |
6118 | ||
6119 | return NULL_RTX; | |
6120 | } | |
6121 | ||
6122 | \f | |
6123 | /* A C expression to perform any final machine dependent modifications in | |
6124 | converting code to conditional execution in the code described by the | |
6125 | conditional if information CE_INFO. */ | |
6126 | ||
6127 | void | |
84562394 | 6128 | frv_ifcvt_modify_final (ce_if_block *ce_info ATTRIBUTE_UNUSED) |
36a05131 BS |
6129 | { |
6130 | rtx existing_insn; | |
6131 | rtx check_insn; | |
6132 | rtx p = frv_ifcvt.added_insns_list; | |
6133 | int i; | |
6134 | ||
6135 | /* Loop inserting the check insns. The last check insn is the first test, | |
6136 | and is the appropriate place to insert constants. */ | |
44e91694 | 6137 | gcc_assert (p); |
36a05131 BS |
6138 | |
6139 | do | |
6140 | { | |
6141 | rtx check_and_insert_insns = XEXP (p, 0); | |
6142 | rtx old_p = p; | |
6143 | ||
6144 | check_insn = XEXP (check_and_insert_insns, 0); | |
6145 | existing_insn = XEXP (check_and_insert_insns, 1); | |
6146 | p = XEXP (p, 1); | |
6147 | ||
6148 | /* The jump bit is used to say that the new insn is to be inserted BEFORE | |
6149 | the existing insn, otherwise it is to be inserted AFTER. */ | |
6150 | if (check_and_insert_insns->jump) | |
6151 | { | |
6152 | emit_insn_before (check_insn, existing_insn); | |
6153 | check_and_insert_insns->jump = 0; | |
6154 | } | |
6155 | else | |
6156 | emit_insn_after (check_insn, existing_insn); | |
6157 | ||
6158 | free_EXPR_LIST_node (check_and_insert_insns); | |
6159 | free_EXPR_LIST_node (old_p); | |
6160 | } | |
6161 | while (p != NULL_RTX); | |
6162 | ||
6163 | /* Load up any constants needed into temp gprs */ | |
6164 | for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++) | |
6165 | { | |
6166 | rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn); | |
6167 | if (! frv_ifcvt.scratch_insns_bitmap) | |
7b210806 | 6168 | frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL); |
36a05131 BS |
6169 | bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn)); |
6170 | frv_ifcvt.scratch_regs[i] = NULL_RTX; | |
6171 | } | |
6172 | ||
6173 | frv_ifcvt.added_insns_list = NULL_RTX; | |
6174 | frv_ifcvt.cur_scratch_regs = 0; | |
6175 | } | |
6176 | ||
6177 | \f | |
6178 | /* A C expression to cancel any machine dependent modifications in converting | |
6179 | code to conditional execution in the code described by the conditional if | |
6180 | information CE_INFO. */ | |
6181 | ||
6182 | void | |
84562394 | 6183 | frv_ifcvt_modify_cancel (ce_if_block *ce_info ATTRIBUTE_UNUSED) |
36a05131 BS |
6184 | { |
6185 | int i; | |
6186 | rtx p = frv_ifcvt.added_insns_list; | |
6187 | ||
6188 | /* Loop freeing up the EXPR_LIST's allocated. */ | |
6189 | while (p != NULL_RTX) | |
6190 | { | |
6191 | rtx check_and_jump = XEXP (p, 0); | |
6192 | rtx old_p = p; | |
6193 | ||
6194 | p = XEXP (p, 1); | |
6195 | free_EXPR_LIST_node (check_and_jump); | |
6196 | free_EXPR_LIST_node (old_p); | |
6197 | } | |
6198 | ||
6199 | /* Release any temporary gprs allocated. */ | |
6200 | for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++) | |
6201 | frv_ifcvt.scratch_regs[i] = NULL_RTX; | |
6202 | ||
6203 | frv_ifcvt.added_insns_list = NULL_RTX; | |
6204 | frv_ifcvt.cur_scratch_regs = 0; | |
6205 | return; | |
6206 | } | |
6207 | \f | |
6208 | /* A C expression for the size in bytes of the trampoline, as an integer. | |
6209 | The template is: | |
6210 | ||
6211 | setlo #0, <jmp_reg> | |
6212 | setlo #0, <static_chain> | |
6213 | sethi #0, <jmp_reg> | |
6214 | sethi #0, <static_chain> | |
6215 | jmpl @(gr0,<jmp_reg>) */ | |
6216 | ||
6217 | int | |
f2206911 | 6218 | frv_trampoline_size (void) |
36a05131 | 6219 | { |
34208acf AO |
6220 | if (TARGET_FDPIC) |
6221 | /* Allocate room for the function descriptor and the lddi | |
6222 | instruction. */ | |
6223 | return 8 + 6 * 4; | |
6224 | return 5 /* instructions */ * 4 /* instruction size. */; | |
36a05131 BS |
6225 | } |
6226 | ||
6227 | \f | |
6228 | /* A C statement to initialize the variable parts of a trampoline. ADDR is an | |
6229 | RTX for the address of the trampoline; FNADDR is an RTX for the address of | |
6230 | the nested function; STATIC_CHAIN is an RTX for the static chain value that | |
6231 | should be passed to the function when it is called. | |
6232 | ||
6233 | The template is: | |
6234 | ||
6235 | setlo #0, <jmp_reg> | |
6236 | setlo #0, <static_chain> | |
6237 | sethi #0, <jmp_reg> | |
6238 | sethi #0, <static_chain> | |
6239 | jmpl @(gr0,<jmp_reg>) */ | |
6240 | ||
e9d5fdb2 RH |
6241 | static void |
6242 | frv_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain) | |
36a05131 | 6243 | { |
e9d5fdb2 RH |
6244 | rtx addr = XEXP (m_tramp, 0); |
6245 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
36a05131 BS |
6246 | rtx sc_reg = force_reg (Pmode, static_chain); |
6247 | ||
6248 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), | |
db69559b | 6249 | LCT_NORMAL, VOIDmode, |
36a05131 BS |
6250 | addr, Pmode, |
6251 | GEN_INT (frv_trampoline_size ()), SImode, | |
6252 | fnaddr, Pmode, | |
6253 | sc_reg, Pmode); | |
6254 | } | |
6255 | ||
6256 | \f | |
6257 | /* Many machines have some registers that cannot be copied directly to or from | |
6258 | memory or even from other types of registers. An example is the `MQ' | |
6259 | register, which on most machines, can only be copied to or from general | |
6260 | registers, but not memory. Some machines allow copying all registers to and | |
6261 | from memory, but require a scratch register for stores to some memory | |
6262 | locations (e.g., those with symbolic address on the RT, and those with | |
981f6289 | 6263 | certain symbolic address on the SPARC when compiling PIC). In some cases, |
36a05131 BS |
6264 | both an intermediate and a scratch register are required. |
6265 | ||
6266 | You should define these macros to indicate to the reload phase that it may | |
6267 | need to allocate at least one register for a reload in addition to the | |
6268 | register to contain the data. Specifically, if copying X to a register | |
0a2aaacc | 6269 | RCLASS in MODE requires an intermediate register, you should define |
36a05131 BS |
6270 | `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of |
6271 | whose registers can be used as intermediate registers or scratch registers. | |
6272 | ||
0a2aaacc | 6273 | If copying a register RCLASS in MODE to X requires an intermediate or scratch |
36a05131 BS |
6274 | register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the |
6275 | largest register class required. If the requirements for input and output | |
6276 | reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used | |
6277 | instead of defining both macros identically. | |
6278 | ||
6279 | The values returned by these macros are often `GENERAL_REGS'. Return | |
6280 | `NO_REGS' if no spare register is needed; i.e., if X can be directly copied | |
0a2aaacc | 6281 | to or from a register of RCLASS in MODE without requiring a scratch register. |
36a05131 BS |
6282 | Do not define this macro if it would always return `NO_REGS'. |
6283 | ||
6284 | If a scratch register is required (either with or without an intermediate | |
6285 | register), you should define patterns for `reload_inM' or `reload_outM', as | |
6286 | required.. These patterns, which will normally be implemented with a | |
6287 | `define_expand', should be similar to the `movM' patterns, except that | |
6288 | operand 2 is the scratch register. | |
6289 | ||
6290 | Define constraints for the reload register and scratch register that contain | |
6291 | a single register class. If the original reload register (whose class is | |
0a2aaacc | 6292 | RCLASS) can meet the constraint given in the pattern, the value returned by |
36a05131 BS |
6293 | these macros is used for the class of the scratch register. Otherwise, two |
6294 | additional reload registers are required. Their classes are obtained from | |
6295 | the constraints in the insn pattern. | |
6296 | ||
6297 | X might be a pseudo-register or a `subreg' of a pseudo-register, which could | |
6298 | either be in a hard register or in memory. Use `true_regnum' to find out; | |
6299 | it will return -1 if the pseudo is in memory and the hard register number if | |
6300 | it is in a register. | |
6301 | ||
6302 | These macros should not be used in the case where a particular class of | |
6303 | registers can only be copied to memory and not to another class of | |
6304 | registers. In that case, secondary reload registers are not needed and | |
6305 | would not be helpful. Instead, a stack location must be used to perform the | |
43aa4e05 | 6306 | copy and the `movM' pattern should use memory as an intermediate storage. |
36a05131 BS |
6307 | This case often occurs between floating-point and general registers. */ |
6308 | ||
6309 | enum reg_class | |
0a2aaacc | 6310 | frv_secondary_reload_class (enum reg_class rclass, |
ef4bddc2 | 6311 | machine_mode mode ATTRIBUTE_UNUSED, |
35f2d8ef | 6312 | rtx x) |
36a05131 BS |
6313 | { |
6314 | enum reg_class ret; | |
6315 | ||
0a2aaacc | 6316 | switch (rclass) |
36a05131 BS |
6317 | { |
6318 | default: | |
6319 | ret = NO_REGS; | |
6320 | break; | |
6321 | ||
6322 | /* Accumulators/Accumulator guard registers need to go through floating | |
6323 | point registers. */ | |
6324 | case QUAD_REGS: | |
36a05131 BS |
6325 | case GPR_REGS: |
6326 | ret = NO_REGS; | |
6327 | if (x && GET_CODE (x) == REG) | |
6328 | { | |
6329 | int regno = REGNO (x); | |
6330 | ||
6331 | if (ACC_P (regno) || ACCG_P (regno)) | |
6332 | ret = FPR_REGS; | |
6333 | } | |
6334 | break; | |
6335 | ||
9cd10576 | 6336 | /* Nonzero constants should be loaded into an FPR through a GPR. */ |
36a05131 | 6337 | case QUAD_FPR_REGS: |
36a05131 BS |
6338 | if (x && CONSTANT_P (x) && !ZERO_P (x)) |
6339 | ret = GPR_REGS; | |
6340 | else | |
6341 | ret = NO_REGS; | |
6342 | break; | |
6343 | ||
6344 | /* All of these types need gpr registers. */ | |
6345 | case ICC_REGS: | |
6346 | case FCC_REGS: | |
6347 | case CC_REGS: | |
6348 | case ICR_REGS: | |
6349 | case FCR_REGS: | |
6350 | case CR_REGS: | |
6351 | case LCR_REG: | |
6352 | case LR_REG: | |
6353 | ret = GPR_REGS; | |
6354 | break; | |
6355 | ||
35f2d8ef | 6356 | /* The accumulators need fpr registers. */ |
36a05131 BS |
6357 | case QUAD_ACC_REGS: |
6358 | case ACCG_REGS: | |
6359 | ret = FPR_REGS; | |
6360 | break; | |
6361 | } | |
6362 | ||
6363 | return ret; | |
6364 | } | |
6365 | ||
35f2d8ef NC |
6366 | /* This hook exists to catch the case where secondary_reload_class() is |
6367 | called from init_reg_autoinc() in regclass.c - before the reload optabs | |
6368 | have been initialised. */ | |
6369 | ||
a87cf97e JR |
6370 | static reg_class_t |
6371 | frv_secondary_reload (bool in_p, rtx x, reg_class_t reload_class_i, | |
ef4bddc2 | 6372 | machine_mode reload_mode, |
35f2d8ef NC |
6373 | secondary_reload_info * sri) |
6374 | { | |
6375 | enum reg_class rclass = NO_REGS; | |
a87cf97e | 6376 | enum reg_class reload_class = (enum reg_class) reload_class_i; |
35f2d8ef NC |
6377 | |
6378 | if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing) | |
6379 | { | |
6380 | sri->icode = sri->prev_sri->t_icode; | |
6381 | return NO_REGS; | |
6382 | } | |
6383 | ||
6384 | rclass = frv_secondary_reload_class (reload_class, reload_mode, x); | |
6385 | ||
6386 | if (rclass != NO_REGS) | |
6387 | { | |
f9621cc4 RS |
6388 | enum insn_code icode |
6389 | = direct_optab_handler (in_p ? reload_in_optab : reload_out_optab, | |
6390 | reload_mode); | |
35f2d8ef NC |
6391 | if (icode == 0) |
6392 | { | |
6393 | /* This happens when then the reload_[in|out]_optabs have | |
6394 | not been initialised. */ | |
6395 | sri->t_icode = CODE_FOR_nothing; | |
6396 | return rclass; | |
6397 | } | |
6398 | } | |
6399 | ||
6400 | /* Fall back to the default secondary reload handler. */ | |
6401 | return default_secondary_reload (in_p, x, reload_class, reload_mode, sri); | |
6402 | ||
6403 | } | |
36a05131 | 6404 | \f |
c28350ab | 6405 | /* Worker function for TARGET_CLASS_LIKELY_SPILLED_P. */ |
36a05131 | 6406 | |
c28350ab AS |
6407 | static bool |
6408 | frv_class_likely_spilled_p (reg_class_t rclass) | |
36a05131 | 6409 | { |
0a2aaacc | 6410 | switch (rclass) |
36a05131 BS |
6411 | { |
6412 | default: | |
6413 | break; | |
6414 | ||
17c21957 AO |
6415 | case GR8_REGS: |
6416 | case GR9_REGS: | |
6417 | case GR89_REGS: | |
6418 | case FDPIC_FPTR_REGS: | |
6419 | case FDPIC_REGS: | |
36a05131 BS |
6420 | case ICC_REGS: |
6421 | case FCC_REGS: | |
6422 | case CC_REGS: | |
6423 | case ICR_REGS: | |
6424 | case FCR_REGS: | |
6425 | case CR_REGS: | |
6426 | case LCR_REG: | |
6427 | case LR_REG: | |
6428 | case SPR_REGS: | |
6429 | case QUAD_ACC_REGS: | |
36a05131 | 6430 | case ACCG_REGS: |
c28350ab | 6431 | return true; |
36a05131 BS |
6432 | } |
6433 | ||
c28350ab | 6434 | return false; |
36a05131 BS |
6435 | } |
6436 | ||
6437 | \f | |
6438 | /* An expression for the alignment of a structure field FIELD if the | |
7ec022b2 | 6439 | alignment computed in the usual way is COMPUTED. GCC uses this |
36a05131 BS |
6440 | value instead of the value in `BIGGEST_ALIGNMENT' or |
6441 | `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */ | |
6442 | ||
6443 | /* The definition type of the bit field data is either char, short, long or | |
6444 | long long. The maximum bit size is the number of bits of its own type. | |
6445 | ||
6446 | The bit field data is assigned to a storage unit that has an adequate size | |
6447 | for bit field data retention and is located at the smallest address. | |
6448 | ||
6449 | Consecutive bit field data are packed at consecutive bits having the same | |
6450 | storage unit, with regard to the type, beginning with the MSB and continuing | |
6451 | toward the LSB. | |
6452 | ||
6453 | If a field to be assigned lies over a bit field type boundary, its | |
6454 | assignment is completed by aligning it with a boundary suitable for the | |
6455 | type. | |
6456 | ||
6457 | When a bit field having a bit length of 0 is declared, it is forcibly | |
6458 | assigned to the next storage unit. | |
6459 | ||
6460 | e.g) | |
6461 | struct { | |
6462 | int a:2; | |
6463 | int b:6; | |
6464 | char c:4; | |
6465 | int d:10; | |
6466 | int :0; | |
6467 | int f:2; | |
6468 | } x; | |
6469 | ||
6470 | +0 +1 +2 +3 | |
6471 | &x 00000000 00000000 00000000 00000000 | |
6472 | MLM----L | |
6473 | a b | |
6474 | &x+4 00000000 00000000 00000000 00000000 | |
6475 | M--L | |
6476 | c | |
6477 | &x+8 00000000 00000000 00000000 00000000 | |
6478 | M----------L | |
6479 | d | |
6480 | &x+12 00000000 00000000 00000000 00000000 | |
6481 | ML | |
6482 | f | |
6483 | */ | |
6484 | ||
6485 | int | |
f2206911 | 6486 | frv_adjust_field_align (tree field, int computed) |
36a05131 | 6487 | { |
b16c1435 | 6488 | /* Make sure that the bitfield is not wider than the type. */ |
a4cf4b64 RB |
6489 | if (field |
6490 | && DECL_BIT_FIELD (field) | |
25f93e18 | 6491 | && !DECL_ARTIFICIAL (field)) |
36a05131 BS |
6492 | { |
6493 | tree parent = DECL_CONTEXT (field); | |
6494 | tree prev = NULL_TREE; | |
6495 | tree cur; | |
6496 | ||
910ad8de | 6497 | for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = DECL_CHAIN (cur)) |
36a05131 BS |
6498 | { |
6499 | if (TREE_CODE (cur) != FIELD_DECL) | |
6500 | continue; | |
6501 | ||
6502 | prev = cur; | |
6503 | } | |
6504 | ||
44e91694 | 6505 | gcc_assert (cur); |
36a05131 BS |
6506 | |
6507 | /* If this isn't a :0 field and if the previous element is a bitfield | |
6508 | also, see if the type is different, if so, we will need to align the | |
87b483a1 | 6509 | bit-field to the next boundary. */ |
36a05131 BS |
6510 | if (prev |
6511 | && ! DECL_PACKED (field) | |
6512 | && ! integer_zerop (DECL_SIZE (field)) | |
6513 | && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev)) | |
6514 | { | |
6515 | int prev_align = TYPE_ALIGN (TREE_TYPE (prev)); | |
6516 | int cur_align = TYPE_ALIGN (TREE_TYPE (field)); | |
6517 | computed = (prev_align > cur_align) ? prev_align : cur_align; | |
6518 | } | |
6519 | } | |
6520 | ||
6521 | return computed; | |
6522 | } | |
6523 | ||
6524 | \f | |
f939c3e6 | 6525 | /* Implement TARGET_HARD_REGNO_MODE_OK. */ |
36a05131 | 6526 | |
f939c3e6 RS |
6527 | static bool |
6528 | frv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) | |
36a05131 BS |
6529 | { |
6530 | int base; | |
6531 | int mask; | |
6532 | ||
6533 | switch (mode) | |
6534 | { | |
4e10a5a7 RS |
6535 | case E_CCmode: |
6536 | case E_CC_UNSmode: | |
6537 | case E_CC_NZmode: | |
36a05131 BS |
6538 | return ICC_P (regno) || GPR_P (regno); |
6539 | ||
4e10a5a7 | 6540 | case E_CC_CCRmode: |
36a05131 BS |
6541 | return CR_P (regno) || GPR_P (regno); |
6542 | ||
4e10a5a7 | 6543 | case E_CC_FPmode: |
36a05131 BS |
6544 | return FCC_P (regno) || GPR_P (regno); |
6545 | ||
6546 | default: | |
6547 | break; | |
6548 | } | |
6549 | ||
6550 | /* Set BASE to the first register in REGNO's class. Set MASK to the | |
6551 | bits that must be clear in (REGNO - BASE) for the register to be | |
6552 | well-aligned. */ | |
6553 | if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode)) | |
6554 | { | |
6555 | if (ACCG_P (regno)) | |
6556 | { | |
6557 | /* ACCGs store one byte. Two-byte quantities must start in | |
6558 | even-numbered registers, four-byte ones in registers whose | |
6559 | numbers are divisible by four, and so on. */ | |
6560 | base = ACCG_FIRST; | |
6561 | mask = GET_MODE_SIZE (mode) - 1; | |
6562 | } | |
6563 | else | |
6564 | { | |
b16c1435 EC |
6565 | /* The other registers store one word. */ |
6566 | if (GPR_P (regno) || regno == AP_FIRST) | |
36a05131 BS |
6567 | base = GPR_FIRST; |
6568 | ||
6569 | else if (FPR_P (regno)) | |
6570 | base = FPR_FIRST; | |
6571 | ||
6572 | else if (ACC_P (regno)) | |
6573 | base = ACC_FIRST; | |
6574 | ||
b16c1435 EC |
6575 | else if (SPR_P (regno)) |
6576 | return mode == SImode; | |
6577 | ||
87b483a1 | 6578 | /* Fill in the table. */ |
36a05131 | 6579 | else |
f939c3e6 | 6580 | return false; |
36a05131 BS |
6581 | |
6582 | /* Anything smaller than an SI is OK in any word-sized register. */ | |
6583 | if (GET_MODE_SIZE (mode) < 4) | |
f939c3e6 | 6584 | return true; |
36a05131 BS |
6585 | |
6586 | mask = (GET_MODE_SIZE (mode) / 4) - 1; | |
6587 | } | |
6588 | return (((regno - base) & mask) == 0); | |
6589 | } | |
6590 | ||
f939c3e6 | 6591 | return false; |
36a05131 BS |
6592 | } |
6593 | ||
99e1629f RS |
6594 | /* Implement TARGET_MODES_TIEABLE_P. */ |
6595 | ||
6596 | static bool | |
6597 | frv_modes_tieable_p (machine_mode mode1, machine_mode mode2) | |
6598 | { | |
6599 | return mode1 == mode2; | |
6600 | } | |
6601 | ||
36a05131 BS |
6602 | \f |
6603 | /* A C expression for the number of consecutive hard registers, starting at | |
6604 | register number REGNO, required to hold a value of mode MODE. | |
6605 | ||
6606 | On a machine where all registers are exactly one word, a suitable definition | |
6607 | of this macro is | |
6608 | ||
6609 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
6610 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \ | |
6611 | / UNITS_PER_WORD)) */ | |
6612 | ||
6613 | /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so | |
6614 | that we can build the appropriate instructions to properly reload the | |
6615 | values. Also, make the byte-sized accumulator guards use one guard | |
6616 | for each byte. */ | |
6617 | ||
6618 | int | |
ef4bddc2 | 6619 | frv_hard_regno_nregs (int regno, machine_mode mode) |
36a05131 BS |
6620 | { |
6621 | if (ACCG_P (regno)) | |
6622 | return GET_MODE_SIZE (mode); | |
6623 | else | |
6624 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
6625 | } | |
6626 | ||
6627 | \f | |
6628 | /* A C expression for the maximum number of consecutive registers of | |
0a2aaacc | 6629 | class RCLASS needed to hold a value of mode MODE. |
36a05131 BS |
6630 | |
6631 | This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value | |
0a2aaacc KG |
6632 | of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of |
6633 | `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS. | |
36a05131 BS |
6634 | |
6635 | This macro helps control the handling of multiple-word values in | |
6636 | the reload pass. | |
6637 | ||
6638 | This declaration is required. */ | |
6639 | ||
6640 | int | |
ef4bddc2 | 6641 | frv_class_max_nregs (enum reg_class rclass, machine_mode mode) |
36a05131 | 6642 | { |
0a2aaacc | 6643 | if (rclass == ACCG_REGS) |
36a05131 BS |
6644 | /* An N-byte value requires N accumulator guards. */ |
6645 | return GET_MODE_SIZE (mode); | |
6646 | else | |
6647 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
6648 | } | |
6649 | ||
6650 | \f | |
6651 | /* A C expression that is nonzero if X is a legitimate constant for an | |
6652 | immediate operand on the target machine. You can assume that X satisfies | |
6653 | `CONSTANT_P', so you need not check this. In fact, `1' is a suitable | |
6654 | definition for this macro on machines where anything `CONSTANT_P' is valid. */ | |
6655 | ||
1a627b35 | 6656 | static bool |
ef4bddc2 | 6657 | frv_legitimate_constant_p (machine_mode mode, rtx x) |
36a05131 | 6658 | { |
34208acf AO |
6659 | /* frv_cannot_force_const_mem always returns true for FDPIC. This |
6660 | means that the move expanders will be expected to deal with most | |
6661 | kinds of constant, regardless of what we return here. | |
6662 | ||
1a627b35 | 6663 | However, among its other duties, frv_legitimate_constant_p decides whether |
34208acf AO |
6664 | a constant can be entered into reg_equiv_constant[]. If we return true, |
6665 | reload can create new instances of the constant whenever it likes. | |
6666 | ||
6667 | The idea is therefore to accept as many constants as possible (to give | |
6668 | reload more freedom) while rejecting constants that can only be created | |
6669 | at certain times. In particular, anything with a symbolic component will | |
6670 | require use of the pseudo FDPIC register, which is only available before | |
6671 | reload. */ | |
6672 | if (TARGET_FDPIC) | |
6673 | return LEGITIMATE_PIC_OPERAND_P (x); | |
6674 | ||
87b483a1 | 6675 | /* All of the integer constants are ok. */ |
36a05131 BS |
6676 | if (GET_CODE (x) != CONST_DOUBLE) |
6677 | return TRUE; | |
6678 | ||
87b483a1 | 6679 | /* double integer constants are ok. */ |
1a627b35 | 6680 | if (GET_MODE (x) == VOIDmode || mode == DImode) |
36a05131 BS |
6681 | return TRUE; |
6682 | ||
87b483a1 | 6683 | /* 0 is always ok. */ |
36a05131 BS |
6684 | if (x == CONST0_RTX (mode)) |
6685 | return TRUE; | |
6686 | ||
6687 | /* If floating point is just emulated, allow any constant, since it will be | |
87b483a1 | 6688 | constructed in the GPRs. */ |
36a05131 BS |
6689 | if (!TARGET_HAS_FPRS) |
6690 | return TRUE; | |
6691 | ||
6692 | if (mode == DFmode && !TARGET_DOUBLE) | |
6693 | return TRUE; | |
6694 | ||
6695 | /* Otherwise store the constant away and do a load. */ | |
6696 | return FALSE; | |
6697 | } | |
036ff63f RS |
6698 | |
6699 | /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons, | |
6700 | CC_NZ for comparisons against zero in which a single Z or N flag test | |
6701 | is enough, CC_UNS for other unsigned comparisons, and CC for other | |
6702 | signed comparisons. */ | |
6703 | ||
ef4bddc2 | 6704 | machine_mode |
036ff63f RS |
6705 | frv_select_cc_mode (enum rtx_code code, rtx x, rtx y) |
6706 | { | |
6707 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
6708 | return CC_FPmode; | |
6709 | ||
6710 | switch (code) | |
6711 | { | |
6712 | case EQ: | |
6713 | case NE: | |
6714 | case LT: | |
6715 | case GE: | |
6716 | return y == const0_rtx ? CC_NZmode : CCmode; | |
6717 | ||
6718 | case GTU: | |
6719 | case GEU: | |
6720 | case LTU: | |
6721 | case LEU: | |
6722 | return y == const0_rtx ? CC_NZmode : CC_UNSmode; | |
6723 | ||
6724 | default: | |
6725 | return CCmode; | |
6726 | } | |
6727 | } | |
36a05131 | 6728 | \f |
33124e84 AS |
6729 | |
6730 | /* Worker function for TARGET_REGISTER_MOVE_COST. */ | |
36a05131 BS |
6731 | |
6732 | #define HIGH_COST 40 | |
6733 | #define MEDIUM_COST 3 | |
6734 | #define LOW_COST 1 | |
6735 | ||
33124e84 | 6736 | static int |
ef4bddc2 | 6737 | frv_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, |
33124e84 | 6738 | reg_class_t from, reg_class_t to) |
36a05131 BS |
6739 | { |
6740 | switch (from) | |
6741 | { | |
6742 | default: | |
6743 | break; | |
6744 | ||
6745 | case QUAD_REGS: | |
36a05131 | 6746 | case GPR_REGS: |
73d7e266 VM |
6747 | case GR8_REGS: |
6748 | case GR9_REGS: | |
6749 | case GR89_REGS: | |
6750 | case FDPIC_REGS: | |
6751 | case FDPIC_FPTR_REGS: | |
6752 | case FDPIC_CALL_REGS: | |
6753 | ||
36a05131 BS |
6754 | switch (to) |
6755 | { | |
6756 | default: | |
6757 | break; | |
6758 | ||
9b5db25d | 6759 | case QUAD_REGS: |
36a05131 | 6760 | case GPR_REGS: |
73d7e266 VM |
6761 | case GR8_REGS: |
6762 | case GR9_REGS: | |
6763 | case GR89_REGS: | |
6764 | case FDPIC_REGS: | |
6765 | case FDPIC_FPTR_REGS: | |
6766 | case FDPIC_CALL_REGS: | |
6767 | ||
36a05131 BS |
6768 | return LOW_COST; |
6769 | ||
36a05131 BS |
6770 | case FPR_REGS: |
6771 | return LOW_COST; | |
6772 | ||
6773 | case LCR_REG: | |
6774 | case LR_REG: | |
6775 | case SPR_REGS: | |
6776 | return LOW_COST; | |
6777 | } | |
6778 | ||
9b5db25d | 6779 | case QUAD_FPR_REGS: |
36a05131 BS |
6780 | switch (to) |
6781 | { | |
6782 | default: | |
6783 | break; | |
6784 | ||
6785 | case QUAD_REGS: | |
36a05131 | 6786 | case GPR_REGS: |
73d7e266 VM |
6787 | case GR8_REGS: |
6788 | case GR9_REGS: | |
6789 | case GR89_REGS: | |
6790 | case FDPIC_REGS: | |
6791 | case FDPIC_FPTR_REGS: | |
6792 | case FDPIC_CALL_REGS: | |
6793 | ||
36a05131 BS |
6794 | case QUAD_ACC_REGS: |
6795 | case ACCG_REGS: | |
6796 | return MEDIUM_COST; | |
6797 | ||
9b5db25d | 6798 | case QUAD_FPR_REGS: |
36a05131 BS |
6799 | return LOW_COST; |
6800 | } | |
6801 | ||
6802 | case LCR_REG: | |
6803 | case LR_REG: | |
6804 | case SPR_REGS: | |
6805 | switch (to) | |
6806 | { | |
6807 | default: | |
6808 | break; | |
6809 | ||
6810 | case QUAD_REGS: | |
36a05131 | 6811 | case GPR_REGS: |
73d7e266 VM |
6812 | case GR8_REGS: |
6813 | case GR9_REGS: | |
6814 | case GR89_REGS: | |
6815 | case FDPIC_REGS: | |
6816 | case FDPIC_FPTR_REGS: | |
6817 | case FDPIC_CALL_REGS: | |
6818 | ||
36a05131 BS |
6819 | return MEDIUM_COST; |
6820 | } | |
6821 | ||
36a05131 BS |
6822 | case QUAD_ACC_REGS: |
6823 | case ACCG_REGS: | |
6824 | switch (to) | |
6825 | { | |
6826 | default: | |
6827 | break; | |
6828 | ||
9b5db25d | 6829 | case QUAD_FPR_REGS: |
36a05131 BS |
6830 | return MEDIUM_COST; |
6831 | ||
6832 | } | |
6833 | } | |
6834 | ||
6835 | return HIGH_COST; | |
6836 | } | |
33124e84 AS |
6837 | |
6838 | /* Worker function for TARGET_MEMORY_MOVE_COST. */ | |
6839 | ||
6840 | static int | |
ef4bddc2 | 6841 | frv_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED, |
33124e84 AS |
6842 | reg_class_t rclass ATTRIBUTE_UNUSED, |
6843 | bool in ATTRIBUTE_UNUSED) | |
6844 | { | |
6845 | return 4; | |
6846 | } | |
6847 | ||
36a05131 BS |
6848 | \f |
6849 | /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to | |
6850 | use ".picptr" to generate safe relocations for PIC code. We also | |
6851 | need a fixup entry for aligned (non-debugging) code. */ | |
6852 | ||
6853 | static bool | |
f2206911 | 6854 | frv_assemble_integer (rtx value, unsigned int size, int aligned_p) |
36a05131 | 6855 | { |
34208acf | 6856 | if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD) |
36a05131 BS |
6857 | { |
6858 | if (GET_CODE (value) == CONST | |
6859 | || GET_CODE (value) == SYMBOL_REF | |
6860 | || GET_CODE (value) == LABEL_REF) | |
6861 | { | |
34208acf AO |
6862 | if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF |
6863 | && SYMBOL_REF_FUNCTION_P (value)) | |
6864 | { | |
6865 | fputs ("\t.picptr\tfuncdesc(", asm_out_file); | |
6866 | output_addr_const (asm_out_file, value); | |
6867 | fputs (")\n", asm_out_file); | |
6868 | return true; | |
6869 | } | |
6870 | else if (TARGET_FDPIC && GET_CODE (value) == CONST | |
6871 | && frv_function_symbol_referenced_p (value)) | |
6872 | return false; | |
6873 | if (aligned_p && !TARGET_FDPIC) | |
36a05131 BS |
6874 | { |
6875 | static int label_num = 0; | |
6876 | char buf[256]; | |
6877 | const char *p; | |
6878 | ||
6879 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++); | |
14966b94 | 6880 | p = (* targetm.strip_name_encoding) (buf); |
36a05131 BS |
6881 | |
6882 | fprintf (asm_out_file, "%s:\n", p); | |
6883 | fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP); | |
6884 | fprintf (asm_out_file, "\t.picptr\t%s\n", p); | |
6885 | fprintf (asm_out_file, "\t.previous\n"); | |
6886 | } | |
6887 | assemble_integer_with_op ("\t.picptr\t", value); | |
6888 | return true; | |
6889 | } | |
6890 | if (!aligned_p) | |
6891 | { | |
6892 | /* We've set the unaligned SI op to NULL, so we always have to | |
6893 | handle the unaligned case here. */ | |
6894 | assemble_integer_with_op ("\t.4byte\t", value); | |
6895 | return true; | |
6896 | } | |
6897 | } | |
6898 | return default_assemble_integer (value, size, aligned_p); | |
6899 | } | |
6900 | ||
6901 | /* Function to set up the backend function structure. */ | |
6902 | ||
6903 | static struct machine_function * | |
f2206911 | 6904 | frv_init_machine_status (void) |
36a05131 | 6905 | { |
766090c2 | 6906 | return ggc_cleared_alloc<machine_function> (); |
36a05131 | 6907 | } |
ffb344c1 | 6908 | \f |
28a60850 RS |
6909 | /* Implement TARGET_SCHED_ISSUE_RATE. */ |
6910 | ||
c557edf4 | 6911 | int |
28a60850 RS |
6912 | frv_issue_rate (void) |
6913 | { | |
6914 | if (!TARGET_PACK) | |
6915 | return 1; | |
6916 | ||
6917 | switch (frv_cpu_type) | |
6918 | { | |
6919 | default: | |
6920 | case FRV_CPU_FR300: | |
6921 | case FRV_CPU_SIMPLE: | |
6922 | return 1; | |
6923 | ||
6924 | case FRV_CPU_FR400: | |
c557edf4 RS |
6925 | case FRV_CPU_FR405: |
6926 | case FRV_CPU_FR450: | |
28a60850 RS |
6927 | return 2; |
6928 | ||
6929 | case FRV_CPU_GENERIC: | |
6930 | case FRV_CPU_FR500: | |
6931 | case FRV_CPU_TOMCAT: | |
6932 | return 4; | |
c557edf4 RS |
6933 | |
6934 | case FRV_CPU_FR550: | |
6935 | return 8; | |
28a60850 RS |
6936 | } |
6937 | } | |
36a05131 | 6938 | \f |
c557edf4 | 6939 | /* Return the value of INSN's acc_group attribute. */ |
36a05131 | 6940 | |
c557edf4 RS |
6941 | int |
6942 | frv_acc_group (rtx insn) | |
6943 | { | |
6944 | /* This distinction only applies to the FR550 packing constraints. */ | |
cc665e56 RS |
6945 | if (frv_cpu_type == FRV_CPU_FR550) |
6946 | { | |
6947 | subrtx_iterator::array_type array; | |
6948 | FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST) | |
6949 | if (REG_P (*iter)) | |
6950 | { | |
6951 | unsigned int regno = REGNO (*iter); | |
6952 | /* If REGNO refers to an accumulator, return ACC_GROUP_ODD if | |
6953 | the bit 2 of the register number is set and ACC_GROUP_EVEN if | |
6954 | it is clear. */ | |
6955 | if (ACC_P (regno)) | |
6956 | return (regno - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN; | |
6957 | if (ACCG_P (regno)) | |
6958 | return (regno - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN; | |
6959 | } | |
6960 | } | |
6961 | return ACC_GROUP_NONE; | |
c557edf4 | 6962 | } |
36a05131 | 6963 | |
c557edf4 RS |
6964 | /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction |
6965 | INSN will try to claim first. Since this value depends only on the | |
6966 | type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */ | |
36a05131 | 6967 | |
c557edf4 | 6968 | static unsigned int |
84034c69 | 6969 | frv_insn_unit (rtx_insn *insn) |
c557edf4 RS |
6970 | { |
6971 | enum attr_type type; | |
36a05131 | 6972 | |
c557edf4 RS |
6973 | type = get_attr_type (insn); |
6974 | if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes)) | |
6975 | { | |
6976 | /* We haven't seen this type of instruction before. */ | |
6977 | state_t state; | |
6978 | unsigned int unit; | |
36a05131 | 6979 | |
c557edf4 RS |
6980 | /* Issue the instruction on its own to see which unit it prefers. */ |
6981 | state = alloca (state_size ()); | |
6982 | state_reset (state); | |
6983 | state_transition (state, insn); | |
36a05131 | 6984 | |
c557edf4 RS |
6985 | /* Find out which unit was taken. */ |
6986 | for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++) | |
6987 | if (cpu_unit_reservation_p (state, frv_unit_codes[unit])) | |
6988 | break; | |
36a05131 | 6989 | |
44e91694 | 6990 | gcc_assert (unit != ARRAY_SIZE (frv_unit_codes)); |
36a05131 | 6991 | |
c557edf4 | 6992 | frv_type_to_unit[type] = unit; |
36a05131 | 6993 | } |
c557edf4 RS |
6994 | return frv_type_to_unit[type]; |
6995 | } | |
36a05131 | 6996 | |
c557edf4 | 6997 | /* Return true if INSN issues to a branch unit. */ |
36a05131 | 6998 | |
c557edf4 | 6999 | static bool |
84034c69 | 7000 | frv_issues_to_branch_unit_p (rtx_insn *insn) |
c557edf4 RS |
7001 | { |
7002 | return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B; | |
7003 | } | |
7004 | \f | |
5c5e8419 JR |
7005 | /* The instructions in the packet, partitioned into groups. */ |
7006 | struct frv_packet_group { | |
7007 | /* How many instructions in the packet belong to this group. */ | |
7008 | unsigned int num_insns; | |
7009 | ||
7010 | /* A list of the instructions that belong to this group, in the order | |
7011 | they appear in the rtl stream. */ | |
b32d5189 | 7012 | rtx_insn *insns[ARRAY_SIZE (frv_unit_codes)]; |
5c5e8419 JR |
7013 | |
7014 | /* The contents of INSNS after they have been sorted into the correct | |
7015 | assembly-language order. Element X issues to unit X. The list may | |
7016 | contain extra nops. */ | |
b32d5189 | 7017 | rtx_insn *sorted[ARRAY_SIZE (frv_unit_codes)]; |
5c5e8419 JR |
7018 | |
7019 | /* The member of frv_nops[] to use in sorted[]. */ | |
b32d5189 | 7020 | rtx_insn *nop; |
5c5e8419 JR |
7021 | }; |
7022 | ||
c557edf4 RS |
7023 | /* The current state of the packing pass, implemented by frv_pack_insns. */ |
7024 | static struct { | |
7025 | /* The state of the pipeline DFA. */ | |
7026 | state_t dfa_state; | |
7027 | ||
7028 | /* Which hardware registers are set within the current packet, | |
7029 | and the conditions under which they are set. */ | |
7030 | regstate_t regstate[FIRST_PSEUDO_REGISTER]; | |
7031 | ||
7032 | /* The memory locations that have been modified so far in this | |
7033 | packet. MEM is the memref and COND is the regstate_t condition | |
7034 | under which it is set. */ | |
7035 | struct { | |
7036 | rtx mem; | |
7037 | regstate_t cond; | |
7038 | } mems[2]; | |
7039 | ||
7040 | /* The number of valid entries in MEMS. The value is larger than | |
7041 | ARRAY_SIZE (mems) if there were too many mems to record. */ | |
7042 | unsigned int num_mems; | |
7043 | ||
7044 | /* The maximum number of instructions that can be packed together. */ | |
7045 | unsigned int issue_rate; | |
7046 | ||
7047 | /* The instructions in the packet, partitioned into groups. */ | |
5c5e8419 | 7048 | struct frv_packet_group groups[NUM_GROUPS]; |
c557edf4 RS |
7049 | |
7050 | /* The instructions that make up the current packet. */ | |
b32d5189 | 7051 | rtx_insn *insns[ARRAY_SIZE (frv_unit_codes)]; |
c557edf4 RS |
7052 | unsigned int num_insns; |
7053 | } frv_packet; | |
7054 | ||
7055 | /* Return the regstate_t flags for the given COND_EXEC condition. | |
7056 | Abort if the condition isn't in the right form. */ | |
36a05131 | 7057 | |
c557edf4 RS |
7058 | static int |
7059 | frv_cond_flags (rtx cond) | |
7060 | { | |
44e91694 NS |
7061 | gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE) |
7062 | && GET_CODE (XEXP (cond, 0)) == REG | |
7063 | && CR_P (REGNO (XEXP (cond, 0))) | |
7064 | && XEXP (cond, 1) == const0_rtx); | |
7065 | return ((REGNO (XEXP (cond, 0)) - CR_FIRST) | |
7066 | | (GET_CODE (cond) == NE | |
7067 | ? REGSTATE_IF_TRUE | |
7068 | : REGSTATE_IF_FALSE)); | |
c557edf4 | 7069 | } |
36a05131 | 7070 | |
36a05131 | 7071 | |
c557edf4 RS |
7072 | /* Return true if something accessed under condition COND2 can |
7073 | conflict with something written under condition COND1. */ | |
36a05131 | 7074 | |
c557edf4 RS |
7075 | static bool |
7076 | frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2) | |
7077 | { | |
7078 | /* If either reference was unconditional, we have a conflict. */ | |
7079 | if ((cond1 & REGSTATE_IF_EITHER) == 0 | |
7080 | || (cond2 & REGSTATE_IF_EITHER) == 0) | |
7081 | return true; | |
7082 | ||
7083 | /* The references might conflict if they were controlled by | |
7084 | different CRs. */ | |
7085 | if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK)) | |
7086 | return true; | |
7087 | ||
7088 | /* They definitely conflict if they are controlled by the | |
7089 | same condition. */ | |
7090 | if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0) | |
7091 | return true; | |
7092 | ||
7093 | return false; | |
36a05131 BS |
7094 | } |
7095 | ||
c557edf4 | 7096 | |
cc6b9196 RS |
7097 | /* Return true if an instruction with pattern PAT depends on an |
7098 | instruction in the current packet. COND describes the condition | |
7099 | under which PAT might be set or used. */ | |
36a05131 | 7100 | |
cc6b9196 RS |
7101 | static bool |
7102 | frv_registers_conflict_p_1 (rtx pat, regstate_t cond) | |
36a05131 | 7103 | { |
cc6b9196 RS |
7104 | subrtx_var_iterator::array_type array; |
7105 | FOR_EACH_SUBRTX_VAR (iter, array, pat, NONCONST) | |
c557edf4 | 7106 | { |
cc6b9196 RS |
7107 | rtx x = *iter; |
7108 | if (GET_CODE (x) == REG) | |
7109 | { | |
7110 | unsigned int regno; | |
7111 | FOR_EACH_REGNO (regno, x) | |
7112 | if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0) | |
7113 | if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond)) | |
7114 | return true; | |
7115 | } | |
7116 | else if (GET_CODE (x) == MEM) | |
7117 | { | |
7118 | /* If we ran out of memory slots, assume a conflict. */ | |
7119 | if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems)) | |
7120 | return 1; | |
36a05131 | 7121 | |
cc6b9196 RS |
7122 | /* Check for output or true dependencies with earlier MEMs. */ |
7123 | for (unsigned int i = 0; i < frv_packet.num_mems; i++) | |
7124 | if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond)) | |
7125 | { | |
7126 | if (true_dependence (frv_packet.mems[i].mem, VOIDmode, x)) | |
7127 | return true; | |
36a05131 | 7128 | |
cc6b9196 RS |
7129 | if (output_dependence (frv_packet.mems[i].mem, x)) |
7130 | return true; | |
7131 | } | |
7132 | } | |
36a05131 | 7133 | |
cc6b9196 RS |
7134 | /* The return values of calls aren't significant: they describe |
7135 | the effect of the call as a whole, not of the insn itself. */ | |
7136 | else if (GET_CODE (x) == SET && GET_CODE (SET_SRC (x)) == CALL) | |
7137 | iter.substitute (SET_SRC (x)); | |
c557edf4 | 7138 | } |
cc6b9196 | 7139 | return false; |
c557edf4 | 7140 | } |
36a05131 | 7141 | |
36a05131 | 7142 | |
c557edf4 RS |
7143 | /* Return true if something in X might depend on an instruction |
7144 | in the current packet. */ | |
36a05131 | 7145 | |
c557edf4 RS |
7146 | static bool |
7147 | frv_registers_conflict_p (rtx x) | |
7148 | { | |
7149 | regstate_t flags; | |
36a05131 | 7150 | |
c557edf4 RS |
7151 | flags = 0; |
7152 | if (GET_CODE (x) == COND_EXEC) | |
7153 | { | |
cc6b9196 | 7154 | if (frv_registers_conflict_p_1 (XEXP (x, 0), flags)) |
c557edf4 | 7155 | return true; |
36a05131 | 7156 | |
c557edf4 RS |
7157 | flags |= frv_cond_flags (XEXP (x, 0)); |
7158 | x = XEXP (x, 1); | |
36a05131 | 7159 | } |
cc6b9196 | 7160 | return frv_registers_conflict_p_1 (x, flags); |
c557edf4 | 7161 | } |
36a05131 BS |
7162 | |
7163 | ||
c557edf4 RS |
7164 | /* A note_stores callback. DATA points to the regstate_t condition |
7165 | under which X is modified. Update FRV_PACKET accordingly. */ | |
36a05131 | 7166 | |
c557edf4 | 7167 | static void |
7bc980e1 | 7168 | frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) |
c557edf4 RS |
7169 | { |
7170 | unsigned int regno; | |
7171 | ||
7172 | if (GET_CODE (x) == REG) | |
7173 | FOR_EACH_REGNO (regno, x) | |
7174 | frv_packet.regstate[regno] |= *(regstate_t *) data; | |
7175 | ||
7176 | if (GET_CODE (x) == MEM) | |
36a05131 | 7177 | { |
c557edf4 | 7178 | if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems)) |
36a05131 | 7179 | { |
c557edf4 RS |
7180 | frv_packet.mems[frv_packet.num_mems].mem = x; |
7181 | frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data; | |
7182 | } | |
7183 | frv_packet.num_mems++; | |
7184 | } | |
7185 | } | |
36a05131 | 7186 | |
36a05131 | 7187 | |
c557edf4 RS |
7188 | /* Update the register state information for an instruction whose |
7189 | body is X. */ | |
7190 | ||
7191 | static void | |
7192 | frv_registers_update (rtx x) | |
7193 | { | |
7194 | regstate_t flags; | |
7195 | ||
7196 | flags = REGSTATE_MODIFIED; | |
7197 | if (GET_CODE (x) == COND_EXEC) | |
7198 | { | |
7199 | flags |= frv_cond_flags (XEXP (x, 0)); | |
7200 | x = XEXP (x, 1); | |
36a05131 | 7201 | } |
c557edf4 RS |
7202 | note_stores (x, frv_registers_update_1, &flags); |
7203 | } | |
36a05131 | 7204 | |
c557edf4 RS |
7205 | |
7206 | /* Initialize frv_packet for the start of a new packet. */ | |
7207 | ||
7208 | static void | |
7209 | frv_start_packet (void) | |
7210 | { | |
7211 | enum frv_insn_group group; | |
7212 | ||
7213 | memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate)); | |
7214 | frv_packet.num_mems = 0; | |
7215 | frv_packet.num_insns = 0; | |
5c5e8419 JR |
7216 | for (group = GROUP_I; group < NUM_GROUPS; |
7217 | group = (enum frv_insn_group) (group + 1)) | |
c557edf4 | 7218 | frv_packet.groups[group].num_insns = 0; |
36a05131 BS |
7219 | } |
7220 | ||
36a05131 | 7221 | |
c557edf4 RS |
7222 | /* Likewise for the start of a new basic block. */ |
7223 | ||
7224 | static void | |
7225 | frv_start_packet_block (void) | |
36a05131 | 7226 | { |
c557edf4 RS |
7227 | state_reset (frv_packet.dfa_state); |
7228 | frv_start_packet (); | |
7229 | } | |
36a05131 | 7230 | |
c557edf4 RS |
7231 | |
7232 | /* Finish the current packet, if any, and start a new one. Call | |
7233 | HANDLE_PACKET with FRV_PACKET describing the completed packet. */ | |
7234 | ||
7235 | static void | |
7236 | frv_finish_packet (void (*handle_packet) (void)) | |
7237 | { | |
7238 | if (frv_packet.num_insns > 0) | |
36a05131 | 7239 | { |
c557edf4 RS |
7240 | handle_packet (); |
7241 | state_transition (frv_packet.dfa_state, 0); | |
7242 | frv_start_packet (); | |
7243 | } | |
7244 | } | |
36a05131 | 7245 | |
36a05131 | 7246 | |
c557edf4 RS |
7247 | /* Return true if INSN can be added to the current packet. Update |
7248 | the DFA state on success. */ | |
36a05131 | 7249 | |
c557edf4 | 7250 | static bool |
84034c69 | 7251 | frv_pack_insn_p (rtx_insn *insn) |
c557edf4 RS |
7252 | { |
7253 | /* See if the packet is already as long as it can be. */ | |
7254 | if (frv_packet.num_insns == frv_packet.issue_rate) | |
7255 | return false; | |
36a05131 | 7256 | |
c557edf4 RS |
7257 | /* If the scheduler thought that an instruction should start a packet, |
7258 | it's usually a good idea to believe it. It knows much more about | |
7259 | the latencies than we do. | |
36a05131 | 7260 | |
c557edf4 | 7261 | There are some exceptions though: |
36a05131 | 7262 | |
c557edf4 RS |
7263 | - Conditional instructions are scheduled on the assumption that |
7264 | they will be executed. This is usually a good thing, since it | |
c112cf2b | 7265 | tends to avoid unnecessary stalls in the conditional code. |
c557edf4 RS |
7266 | But we want to pack conditional instructions as tightly as |
7267 | possible, in order to optimize the case where they aren't | |
7268 | executed. | |
36a05131 | 7269 | |
c557edf4 RS |
7270 | - The scheduler will always put branches on their own, even |
7271 | if there's no real dependency. | |
36a05131 | 7272 | |
c557edf4 RS |
7273 | - There's no point putting a call in its own packet unless |
7274 | we have to. */ | |
7275 | if (frv_packet.num_insns > 0 | |
b64925dc | 7276 | && NONJUMP_INSN_P (insn) |
c557edf4 RS |
7277 | && GET_MODE (insn) == TImode |
7278 | && GET_CODE (PATTERN (insn)) != COND_EXEC) | |
7279 | return false; | |
36a05131 | 7280 | |
c557edf4 RS |
7281 | /* Check for register conflicts. Don't do this for setlo since any |
7282 | conflict will be with the partnering sethi, with which it can | |
7283 | be packed. */ | |
7284 | if (get_attr_type (insn) != TYPE_SETLO) | |
7285 | if (frv_registers_conflict_p (PATTERN (insn))) | |
7286 | return false; | |
36a05131 | 7287 | |
c557edf4 RS |
7288 | return state_transition (frv_packet.dfa_state, insn) < 0; |
7289 | } | |
36a05131 | 7290 | |
36a05131 | 7291 | |
c557edf4 | 7292 | /* Add instruction INSN to the current packet. */ |
36a05131 | 7293 | |
c557edf4 | 7294 | static void |
b32d5189 | 7295 | frv_add_insn_to_packet (rtx_insn *insn) |
c557edf4 RS |
7296 | { |
7297 | struct frv_packet_group *packet_group; | |
7298 | ||
7299 | packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]]; | |
7300 | packet_group->insns[packet_group->num_insns++] = insn; | |
7301 | frv_packet.insns[frv_packet.num_insns++] = insn; | |
7302 | ||
7303 | frv_registers_update (PATTERN (insn)); | |
36a05131 BS |
7304 | } |
7305 | ||
c557edf4 RS |
7306 | |
7307 | /* Insert INSN (a member of frv_nops[]) into the current packet. If the | |
7308 | packet ends in a branch or call, insert the nop before it, otherwise | |
7309 | add to the end. */ | |
36a05131 BS |
7310 | |
7311 | static void | |
b32d5189 | 7312 | frv_insert_nop_in_packet (rtx_insn *insn) |
36a05131 | 7313 | { |
c557edf4 | 7314 | struct frv_packet_group *packet_group; |
b32d5189 | 7315 | rtx_insn *last; |
c557edf4 RS |
7316 | |
7317 | packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]]; | |
7318 | last = frv_packet.insns[frv_packet.num_insns - 1]; | |
b64925dc | 7319 | if (! NONJUMP_INSN_P (last)) |
c557edf4 RS |
7320 | { |
7321 | insn = emit_insn_before (PATTERN (insn), last); | |
7322 | frv_packet.insns[frv_packet.num_insns - 1] = insn; | |
7323 | frv_packet.insns[frv_packet.num_insns++] = last; | |
7324 | } | |
7325 | else | |
7326 | { | |
7327 | insn = emit_insn_after (PATTERN (insn), last); | |
7328 | frv_packet.insns[frv_packet.num_insns++] = insn; | |
7329 | } | |
7330 | packet_group->insns[packet_group->num_insns++] = insn; | |
7331 | } | |
7332 | ||
36a05131 | 7333 | |
c557edf4 RS |
7334 | /* If packing is enabled, divide the instructions into packets and |
7335 | return true. Call HANDLE_PACKET for each complete packet. */ | |
7336 | ||
7337 | static bool | |
7338 | frv_for_each_packet (void (*handle_packet) (void)) | |
7339 | { | |
b32d5189 | 7340 | rtx_insn *insn, *next_insn; |
c557edf4 RS |
7341 | |
7342 | frv_packet.issue_rate = frv_issue_rate (); | |
7343 | ||
7344 | /* Early exit if we don't want to pack insns. */ | |
28a60850 RS |
7345 | if (!optimize |
7346 | || !flag_schedule_insns_after_reload | |
0b2c18fe | 7347 | || !TARGET_VLIW_BRANCH |
c557edf4 RS |
7348 | || frv_packet.issue_rate == 1) |
7349 | return false; | |
36a05131 | 7350 | |
c557edf4 | 7351 | /* Set up the initial packing state. */ |
36a05131 | 7352 | dfa_start (); |
c557edf4 | 7353 | frv_packet.dfa_state = alloca (state_size ()); |
36a05131 | 7354 | |
c557edf4 RS |
7355 | frv_start_packet_block (); |
7356 | for (insn = get_insns (); insn != 0; insn = next_insn) | |
36a05131 | 7357 | { |
c557edf4 RS |
7358 | enum rtx_code code; |
7359 | bool eh_insn_p; | |
36a05131 | 7360 | |
c557edf4 RS |
7361 | code = GET_CODE (insn); |
7362 | next_insn = NEXT_INSN (insn); | |
7363 | ||
7364 | if (code == CODE_LABEL) | |
36a05131 | 7365 | { |
c557edf4 RS |
7366 | frv_finish_packet (handle_packet); |
7367 | frv_start_packet_block (); | |
7368 | } | |
36a05131 | 7369 | |
39718607 | 7370 | if (INSN_P (insn)) |
c557edf4 RS |
7371 | switch (GET_CODE (PATTERN (insn))) |
7372 | { | |
7373 | case USE: | |
7374 | case CLOBBER: | |
c557edf4 | 7375 | break; |
36a05131 | 7376 | |
c557edf4 RS |
7377 | default: |
7378 | /* Calls mustn't be packed on a TOMCAT. */ | |
b64925dc | 7379 | if (CALL_P (insn) && frv_cpu_type == FRV_CPU_TOMCAT) |
c557edf4 RS |
7380 | frv_finish_packet (handle_packet); |
7381 | ||
7382 | /* Since the last instruction in a packet determines the EH | |
7383 | region, any exception-throwing instruction must come at | |
7384 | the end of reordered packet. Insns that issue to a | |
7385 | branch unit are bound to come last; for others it's | |
7386 | too hard to predict. */ | |
7387 | eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL); | |
7388 | if (eh_insn_p && !frv_issues_to_branch_unit_p (insn)) | |
7389 | frv_finish_packet (handle_packet); | |
7390 | ||
7391 | /* Finish the current packet if we can't add INSN to it. | |
7392 | Simulate cycles until INSN is ready to issue. */ | |
7393 | if (!frv_pack_insn_p (insn)) | |
7394 | { | |
7395 | frv_finish_packet (handle_packet); | |
7396 | while (!frv_pack_insn_p (insn)) | |
7397 | state_transition (frv_packet.dfa_state, 0); | |
7398 | } | |
36a05131 | 7399 | |
c557edf4 RS |
7400 | /* Add the instruction to the packet. */ |
7401 | frv_add_insn_to_packet (insn); | |
7402 | ||
7403 | /* Calls and jumps end a packet, as do insns that throw | |
7404 | an exception. */ | |
7405 | if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p) | |
7406 | frv_finish_packet (handle_packet); | |
7407 | break; | |
7408 | } | |
7409 | } | |
7410 | frv_finish_packet (handle_packet); | |
7411 | dfa_finish (); | |
7412 | return true; | |
7413 | } | |
7414 | \f | |
7415 | /* Subroutine of frv_sort_insn_group. We are trying to sort | |
7416 | frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly | |
7417 | language order. We have already picked a new position for | |
7418 | frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set. | |
7419 | These instructions will occupy elements [0, LOWER_SLOT) and | |
7420 | [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is | |
7421 | the DFA state after issuing these instructions. | |
7422 | ||
7423 | Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation | |
7424 | of the unused instructions. Return true if one such permutation gives | |
7425 | a valid ordering, leaving the successful permutation in sorted[]. | |
7426 | Do not modify sorted[] until a valid permutation is found. */ | |
7427 | ||
7428 | static bool | |
7429 | frv_sort_insn_group_1 (enum frv_insn_group group, | |
7430 | unsigned int lower_slot, unsigned int upper_slot, | |
7431 | unsigned int issued, unsigned int num_insns, | |
7432 | state_t state) | |
7433 | { | |
7434 | struct frv_packet_group *packet_group; | |
7435 | unsigned int i; | |
7436 | state_t test_state; | |
7437 | size_t dfa_size; | |
b32d5189 | 7438 | rtx_insn *insn; |
c557edf4 RS |
7439 | |
7440 | /* Early success if we've filled all the slots. */ | |
7441 | if (lower_slot == upper_slot) | |
7442 | return true; | |
7443 | ||
7444 | packet_group = &frv_packet.groups[group]; | |
7445 | dfa_size = state_size (); | |
7446 | test_state = alloca (dfa_size); | |
7447 | ||
7448 | /* Try issuing each unused instruction. */ | |
7449 | for (i = num_insns - 1; i + 1 != 0; i--) | |
7450 | if (~issued & (1 << i)) | |
7451 | { | |
7452 | insn = packet_group->sorted[i]; | |
7453 | memcpy (test_state, state, dfa_size); | |
7454 | if (state_transition (test_state, insn) < 0 | |
7455 | && cpu_unit_reservation_p (test_state, | |
7456 | NTH_UNIT (group, upper_slot - 1)) | |
7457 | && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1, | |
7458 | issued | (1 << i), num_insns, | |
7459 | test_state)) | |
7460 | { | |
7461 | packet_group->sorted[upper_slot - 1] = insn; | |
7462 | return true; | |
7463 | } | |
7464 | } | |
7465 | ||
7466 | return false; | |
7467 | } | |
7468 | ||
7469 | /* Compare two instructions by their frv_insn_unit. */ | |
7470 | ||
7471 | static int | |
7472 | frv_compare_insns (const void *first, const void *second) | |
7473 | { | |
84034c69 DM |
7474 | rtx_insn * const *insn1 = (rtx_insn * const *) first; |
7475 | rtx_insn * const *insn2 = (rtx_insn * const *) second; | |
c557edf4 RS |
7476 | return frv_insn_unit (*insn1) - frv_insn_unit (*insn2); |
7477 | } | |
7478 | ||
7479 | /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[] | |
7480 | and sort it into assembly language order. See frv.md for a description of | |
7481 | the algorithm. */ | |
7482 | ||
7483 | static void | |
7484 | frv_sort_insn_group (enum frv_insn_group group) | |
7485 | { | |
7486 | struct frv_packet_group *packet_group; | |
7487 | unsigned int first, i, nop, max_unit, num_slots; | |
7488 | state_t state, test_state; | |
7489 | size_t dfa_size; | |
7490 | ||
7491 | packet_group = &frv_packet.groups[group]; | |
75d0ac8d RS |
7492 | |
7493 | /* Assume no nop is needed. */ | |
7494 | packet_group->nop = 0; | |
7495 | ||
c557edf4 RS |
7496 | if (packet_group->num_insns == 0) |
7497 | return; | |
7498 | ||
7499 | /* Copy insns[] to sorted[]. */ | |
7500 | memcpy (packet_group->sorted, packet_group->insns, | |
7501 | sizeof (rtx) * packet_group->num_insns); | |
7502 | ||
7503 | /* Sort sorted[] by the unit that each insn tries to take first. */ | |
7504 | if (packet_group->num_insns > 1) | |
7505 | qsort (packet_group->sorted, packet_group->num_insns, | |
7506 | sizeof (rtx), frv_compare_insns); | |
7507 | ||
7508 | /* That's always enough for branch and control insns. */ | |
7509 | if (group == GROUP_B || group == GROUP_C) | |
7510 | return; | |
7511 | ||
7512 | dfa_size = state_size (); | |
7513 | state = alloca (dfa_size); | |
7514 | test_state = alloca (dfa_size); | |
7515 | ||
7516 | /* Find the highest FIRST such that sorted[0...FIRST-1] can issue | |
7517 | consecutively and such that the DFA takes unit X when sorted[X] | |
7518 | is added. Set STATE to the new DFA state. */ | |
7519 | state_reset (test_state); | |
7520 | for (first = 0; first < packet_group->num_insns; first++) | |
7521 | { | |
7522 | memcpy (state, test_state, dfa_size); | |
7523 | if (state_transition (test_state, packet_group->sorted[first]) >= 0 | |
7524 | || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first))) | |
7525 | break; | |
7526 | } | |
7527 | ||
7528 | /* If all the instructions issued in ascending order, we're done. */ | |
7529 | if (first == packet_group->num_insns) | |
7530 | return; | |
36a05131 | 7531 | |
c557edf4 RS |
7532 | /* Add nops to the end of sorted[] and try each permutation until |
7533 | we find one that works. */ | |
7534 | for (nop = 0; nop < frv_num_nops; nop++) | |
7535 | { | |
7536 | max_unit = frv_insn_unit (frv_nops[nop]); | |
7537 | if (frv_unit_groups[max_unit] == group) | |
36a05131 | 7538 | { |
c557edf4 RS |
7539 | packet_group->nop = frv_nops[nop]; |
7540 | num_slots = UNIT_NUMBER (max_unit) + 1; | |
7541 | for (i = packet_group->num_insns; i < num_slots; i++) | |
7542 | packet_group->sorted[i] = frv_nops[nop]; | |
7543 | if (frv_sort_insn_group_1 (group, first, num_slots, | |
7544 | (1 << first) - 1, num_slots, state)) | |
7545 | return; | |
36a05131 | 7546 | } |
c557edf4 | 7547 | } |
44e91694 | 7548 | gcc_unreachable (); |
c557edf4 RS |
7549 | } |
7550 | \f | |
7551 | /* Sort the current packet into assembly-language order. Set packing | |
7552 | flags as appropriate. */ | |
36a05131 | 7553 | |
c557edf4 RS |
7554 | static void |
7555 | frv_reorder_packet (void) | |
7556 | { | |
7557 | unsigned int cursor[NUM_GROUPS]; | |
9b2ea071 | 7558 | rtx_insn *insns[ARRAY_SIZE (frv_unit_groups)]; |
c557edf4 RS |
7559 | unsigned int unit, to, from; |
7560 | enum frv_insn_group group; | |
7561 | struct frv_packet_group *packet_group; | |
7562 | ||
7563 | /* First sort each group individually. */ | |
5c5e8419 JR |
7564 | for (group = GROUP_I; group < NUM_GROUPS; |
7565 | group = (enum frv_insn_group) (group + 1)) | |
c557edf4 RS |
7566 | { |
7567 | cursor[group] = 0; | |
7568 | frv_sort_insn_group (group); | |
7569 | } | |
7570 | ||
7571 | /* Go through the unit template and try add an instruction from | |
7572 | that unit's group. */ | |
7573 | to = 0; | |
7574 | for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++) | |
7575 | { | |
7576 | group = frv_unit_groups[unit]; | |
7577 | packet_group = &frv_packet.groups[group]; | |
7578 | if (cursor[group] < packet_group->num_insns) | |
36a05131 | 7579 | { |
c557edf4 | 7580 | /* frv_reorg should have added nops for us. */ |
44e91694 NS |
7581 | gcc_assert (packet_group->sorted[cursor[group]] |
7582 | != packet_group->nop); | |
c557edf4 | 7583 | insns[to++] = packet_group->sorted[cursor[group]++]; |
36a05131 | 7584 | } |
c557edf4 | 7585 | } |
36a05131 | 7586 | |
44e91694 | 7587 | gcc_assert (to == frv_packet.num_insns); |
36a05131 | 7588 | |
c557edf4 RS |
7589 | /* Clear the last instruction's packing flag, thus marking the end of |
7590 | a packet. Reorder the other instructions relative to it. */ | |
7591 | CLEAR_PACKING_FLAG (insns[to - 1]); | |
7592 | for (from = 0; from < to - 1; from++) | |
7593 | { | |
7594 | remove_insn (insns[from]); | |
6fb5fa3c | 7595 | add_insn_before (insns[from], insns[to - 1], NULL); |
c557edf4 RS |
7596 | SET_PACKING_FLAG (insns[from]); |
7597 | } | |
7598 | } | |
36a05131 | 7599 | |
36a05131 | 7600 | |
c557edf4 RS |
7601 | /* Divide instructions into packets. Reorder the contents of each |
7602 | packet so that they are in the correct assembly-language order. | |
7603 | ||
7604 | Since this pass can change the raw meaning of the rtl stream, it must | |
7605 | only be called at the last minute, just before the instructions are | |
7606 | written out. */ | |
7607 | ||
7608 | static void | |
7609 | frv_pack_insns (void) | |
7610 | { | |
7611 | if (frv_for_each_packet (frv_reorder_packet)) | |
7612 | frv_insn_packing_flag = 0; | |
7613 | else | |
7614 | frv_insn_packing_flag = -1; | |
7615 | } | |
7616 | \f | |
7617 | /* See whether we need to add nops to group GROUP in order to | |
7618 | make a valid packet. */ | |
7619 | ||
7620 | static void | |
7621 | frv_fill_unused_units (enum frv_insn_group group) | |
7622 | { | |
7623 | unsigned int non_nops, nops, i; | |
7624 | struct frv_packet_group *packet_group; | |
7625 | ||
7626 | packet_group = &frv_packet.groups[group]; | |
7627 | ||
7628 | /* Sort the instructions into assembly-language order. | |
7629 | Use nops to fill slots that are otherwise unused. */ | |
7630 | frv_sort_insn_group (group); | |
7631 | ||
7632 | /* See how many nops are needed before the final useful instruction. */ | |
7633 | i = nops = 0; | |
7634 | for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++) | |
7635 | while (packet_group->sorted[i++] == packet_group->nop) | |
7636 | nops++; | |
7637 | ||
7638 | /* Insert that many nops into the instruction stream. */ | |
7639 | while (nops-- > 0) | |
7640 | frv_insert_nop_in_packet (packet_group->nop); | |
7641 | } | |
7642 | ||
38c28a25 AH |
7643 | /* Return true if accesses IO1 and IO2 refer to the same doubleword. */ |
7644 | ||
7645 | static bool | |
7646 | frv_same_doubleword_p (const struct frv_io *io1, const struct frv_io *io2) | |
7647 | { | |
7648 | if (io1->const_address != 0 && io2->const_address != 0) | |
7649 | return io1->const_address == io2->const_address; | |
7650 | ||
7651 | if (io1->var_address != 0 && io2->var_address != 0) | |
7652 | return rtx_equal_p (io1->var_address, io2->var_address); | |
7653 | ||
7654 | return false; | |
7655 | } | |
7656 | ||
7657 | /* Return true if operations IO1 and IO2 are guaranteed to complete | |
7658 | in order. */ | |
7659 | ||
7660 | static bool | |
7661 | frv_io_fixed_order_p (const struct frv_io *io1, const struct frv_io *io2) | |
7662 | { | |
7663 | /* The order of writes is always preserved. */ | |
7664 | if (io1->type == FRV_IO_WRITE && io2->type == FRV_IO_WRITE) | |
7665 | return true; | |
7666 | ||
7667 | /* The order of reads isn't preserved. */ | |
7668 | if (io1->type != FRV_IO_WRITE && io2->type != FRV_IO_WRITE) | |
7669 | return false; | |
7670 | ||
7671 | /* One operation is a write and the other is (or could be) a read. | |
7672 | The order is only guaranteed if the accesses are to the same | |
7673 | doubleword. */ | |
7674 | return frv_same_doubleword_p (io1, io2); | |
7675 | } | |
7676 | ||
7677 | /* Generalize I/O operation X so that it covers both X and Y. */ | |
7678 | ||
7679 | static void | |
7680 | frv_io_union (struct frv_io *x, const struct frv_io *y) | |
7681 | { | |
7682 | if (x->type != y->type) | |
7683 | x->type = FRV_IO_UNKNOWN; | |
7684 | if (!frv_same_doubleword_p (x, y)) | |
7685 | { | |
7686 | x->const_address = 0; | |
7687 | x->var_address = 0; | |
7688 | } | |
7689 | } | |
7690 | ||
7691 | /* Fill IO with information about the load or store associated with | |
7692 | membar instruction INSN. */ | |
7693 | ||
7694 | static void | |
647d790d | 7695 | frv_extract_membar (struct frv_io *io, rtx_insn *insn) |
38c28a25 AH |
7696 | { |
7697 | extract_insn (insn); | |
5c5e8419 | 7698 | io->type = (enum frv_io_type) INTVAL (recog_data.operand[2]); |
38c28a25 AH |
7699 | io->const_address = INTVAL (recog_data.operand[1]); |
7700 | io->var_address = XEXP (recog_data.operand[0], 0); | |
7701 | } | |
7702 | ||
7703 | /* A note_stores callback for which DATA points to an rtx. Nullify *DATA | |
7704 | if X is a register and *DATA depends on X. */ | |
7705 | ||
7706 | static void | |
7bc980e1 | 7707 | frv_io_check_address (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) |
38c28a25 | 7708 | { |
5ead67f6 | 7709 | rtx *other = (rtx *) data; |
38c28a25 AH |
7710 | |
7711 | if (REG_P (x) && *other != 0 && reg_overlap_mentioned_p (x, *other)) | |
7712 | *other = 0; | |
7713 | } | |
7714 | ||
7715 | /* A note_stores callback for which DATA points to a HARD_REG_SET. | |
7716 | Remove every modified register from the set. */ | |
7717 | ||
7718 | static void | |
7bc980e1 | 7719 | frv_io_handle_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) |
38c28a25 | 7720 | { |
5ead67f6 | 7721 | HARD_REG_SET *set = (HARD_REG_SET *) data; |
38c28a25 AH |
7722 | unsigned int regno; |
7723 | ||
7724 | if (REG_P (x)) | |
7725 | FOR_EACH_REGNO (regno, x) | |
7726 | CLEAR_HARD_REG_BIT (*set, regno); | |
7727 | } | |
7728 | ||
de2b09ec RS |
7729 | /* A note_uses callback that adds all registers in *X to hard register |
7730 | set *DATA. */ | |
38c28a25 AH |
7731 | |
7732 | static void | |
7733 | frv_io_handle_use (rtx *x, void *data) | |
7734 | { | |
de2b09ec | 7735 | find_all_hard_regs (*x, (HARD_REG_SET *) data); |
38c28a25 AH |
7736 | } |
7737 | ||
7738 | /* Go through block BB looking for membars to remove. There are two | |
7739 | cases where intra-block analysis is enough: | |
7740 | ||
7741 | - a membar is redundant if it occurs between two consecutive I/O | |
7742 | operations and if those operations are guaranteed to complete | |
7743 | in order. | |
7744 | ||
7745 | - a membar for a __builtin_read is redundant if the result is | |
7746 | used before the next I/O operation is issued. | |
7747 | ||
7748 | If the last membar in the block could not be removed, and there | |
7749 | are guaranteed to be no I/O operations between that membar and | |
7750 | the end of the block, store the membar in *LAST_MEMBAR, otherwise | |
7751 | store null. | |
7752 | ||
7753 | Describe the block's first I/O operation in *NEXT_IO. Describe | |
7754 | an unknown operation if the block doesn't do any I/O. */ | |
7755 | ||
7756 | static void | |
7757 | frv_optimize_membar_local (basic_block bb, struct frv_io *next_io, | |
647d790d | 7758 | rtx_insn **last_membar) |
38c28a25 AH |
7759 | { |
7760 | HARD_REG_SET used_regs; | |
d8485bdb TS |
7761 | rtx set; |
7762 | rtx_insn *insn, *next_membar; | |
38c28a25 AH |
7763 | bool next_is_end_p; |
7764 | ||
7765 | /* NEXT_IO is the next I/O operation to be performed after the current | |
7766 | instruction. It starts off as being an unknown operation. */ | |
7767 | memset (next_io, 0, sizeof (*next_io)); | |
7768 | ||
7769 | /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */ | |
7770 | next_is_end_p = true; | |
7771 | ||
7772 | /* If the current instruction is a __builtin_read or __builtin_write, | |
7773 | NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR | |
7774 | is null if the membar has already been deleted. | |
7775 | ||
7776 | Note that the initialization here should only be needed to | |
536fa7b7 | 7777 | suppress warnings. */ |
38c28a25 AH |
7778 | next_membar = 0; |
7779 | ||
7780 | /* USED_REGS is the set of registers that are used before the | |
7781 | next I/O instruction. */ | |
7782 | CLEAR_HARD_REG_SET (used_regs); | |
7783 | ||
7784 | for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn)) | |
b64925dc | 7785 | if (CALL_P (insn)) |
38c28a25 AH |
7786 | { |
7787 | /* We can't predict what a call will do to volatile memory. */ | |
7788 | memset (next_io, 0, sizeof (struct frv_io)); | |
7789 | next_is_end_p = false; | |
7790 | CLEAR_HARD_REG_SET (used_regs); | |
7791 | } | |
7792 | else if (INSN_P (insn)) | |
7793 | switch (recog_memoized (insn)) | |
7794 | { | |
7795 | case CODE_FOR_optional_membar_qi: | |
7796 | case CODE_FOR_optional_membar_hi: | |
7797 | case CODE_FOR_optional_membar_si: | |
7798 | case CODE_FOR_optional_membar_di: | |
7799 | next_membar = insn; | |
7800 | if (next_is_end_p) | |
7801 | { | |
7802 | /* Local information isn't enough to decide whether this | |
7803 | membar is needed. Stash it away for later. */ | |
7804 | *last_membar = insn; | |
7805 | frv_extract_membar (next_io, insn); | |
7806 | next_is_end_p = false; | |
7807 | } | |
7808 | else | |
7809 | { | |
7810 | /* Check whether the I/O operation before INSN could be | |
7811 | reordered with one described by NEXT_IO. If it can't, | |
7812 | INSN will not be needed. */ | |
7813 | struct frv_io prev_io; | |
7814 | ||
7815 | frv_extract_membar (&prev_io, insn); | |
7816 | if (frv_io_fixed_order_p (&prev_io, next_io)) | |
7817 | { | |
7818 | if (dump_file) | |
7819 | fprintf (dump_file, | |
7820 | ";; [Local] Removing membar %d since order" | |
7821 | " of accesses is guaranteed\n", | |
7822 | INSN_UID (next_membar)); | |
7823 | ||
7824 | insn = NEXT_INSN (insn); | |
7825 | delete_insn (next_membar); | |
7826 | next_membar = 0; | |
7827 | } | |
7828 | *next_io = prev_io; | |
7829 | } | |
7830 | break; | |
7831 | ||
7832 | default: | |
7833 | /* Invalidate NEXT_IO's address if it depends on something that | |
7834 | is clobbered by INSN. */ | |
7835 | if (next_io->var_address) | |
7836 | note_stores (PATTERN (insn), frv_io_check_address, | |
7837 | &next_io->var_address); | |
7838 | ||
7839 | /* If the next membar is associated with a __builtin_read, | |
7840 | see if INSN reads from that address. If it does, and if | |
7841 | the destination register is used before the next I/O access, | |
7842 | there is no need for the membar. */ | |
7843 | set = PATTERN (insn); | |
7844 | if (next_io->type == FRV_IO_READ | |
7845 | && next_io->var_address != 0 | |
7846 | && next_membar != 0 | |
7847 | && GET_CODE (set) == SET | |
7848 | && GET_CODE (SET_DEST (set)) == REG | |
7849 | && TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set)))) | |
7850 | { | |
7851 | rtx src; | |
7852 | ||
7853 | src = SET_SRC (set); | |
7854 | if (GET_CODE (src) == ZERO_EXTEND) | |
7855 | src = XEXP (src, 0); | |
7856 | ||
7857 | if (GET_CODE (src) == MEM | |
7858 | && rtx_equal_p (XEXP (src, 0), next_io->var_address)) | |
7859 | { | |
7860 | if (dump_file) | |
7861 | fprintf (dump_file, | |
7862 | ";; [Local] Removing membar %d since the target" | |
7863 | " of %d is used before the I/O operation\n", | |
7864 | INSN_UID (next_membar), INSN_UID (insn)); | |
7865 | ||
7866 | if (next_membar == *last_membar) | |
7867 | *last_membar = 0; | |
7868 | ||
7869 | delete_insn (next_membar); | |
7870 | next_membar = 0; | |
7871 | } | |
7872 | } | |
7873 | ||
7874 | /* If INSN has volatile references, forget about any registers | |
7875 | that are used after it. Otherwise forget about uses that | |
7876 | are (or might be) defined by INSN. */ | |
7877 | if (volatile_refs_p (PATTERN (insn))) | |
7878 | CLEAR_HARD_REG_SET (used_regs); | |
7879 | else | |
7880 | note_stores (PATTERN (insn), frv_io_handle_set, &used_regs); | |
7881 | ||
7882 | note_uses (&PATTERN (insn), frv_io_handle_use, &used_regs); | |
7883 | break; | |
7884 | } | |
7885 | } | |
7886 | ||
7887 | /* See if MEMBAR, the last membar instruction in BB, can be removed. | |
7888 | FIRST_IO[X] describes the first operation performed by basic block X. */ | |
7889 | ||
7890 | static void | |
7891 | frv_optimize_membar_global (basic_block bb, struct frv_io *first_io, | |
647d790d | 7892 | rtx_insn *membar) |
38c28a25 AH |
7893 | { |
7894 | struct frv_io this_io, next_io; | |
7895 | edge succ; | |
7896 | edge_iterator ei; | |
7897 | ||
7898 | /* We need to keep the membar if there is an edge to the exit block. */ | |
7899 | FOR_EACH_EDGE (succ, ei, bb->succs) | |
7900 | /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */ | |
fefa31b5 | 7901 | if (succ->dest == EXIT_BLOCK_PTR_FOR_FN (cfun)) |
38c28a25 AH |
7902 | return; |
7903 | ||
7904 | /* Work out the union of all successor blocks. */ | |
7905 | ei = ei_start (bb->succs); | |
7906 | ei_cond (ei, &succ); | |
7907 | /* next_io = first_io[bb->succ->dest->index]; */ | |
7908 | next_io = first_io[succ->dest->index]; | |
7909 | ei = ei_start (bb->succs); | |
7910 | if (ei_cond (ei, &succ)) | |
7911 | { | |
7912 | for (ei_next (&ei); ei_cond (ei, &succ); ei_next (&ei)) | |
7913 | /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/ | |
7914 | frv_io_union (&next_io, &first_io[succ->dest->index]); | |
7915 | } | |
7916 | else | |
7917 | gcc_unreachable (); | |
7918 | ||
7919 | frv_extract_membar (&this_io, membar); | |
7920 | if (frv_io_fixed_order_p (&this_io, &next_io)) | |
7921 | { | |
7922 | if (dump_file) | |
7923 | fprintf (dump_file, | |
7924 | ";; [Global] Removing membar %d since order of accesses" | |
7925 | " is guaranteed\n", INSN_UID (membar)); | |
7926 | ||
7927 | delete_insn (membar); | |
7928 | } | |
7929 | } | |
7930 | ||
7931 | /* Remove redundant membars from the current function. */ | |
7932 | ||
7933 | static void | |
7934 | frv_optimize_membar (void) | |
7935 | { | |
7936 | basic_block bb; | |
7937 | struct frv_io *first_io; | |
647d790d | 7938 | rtx_insn **last_membar; |
38c28a25 AH |
7939 | |
7940 | compute_bb_for_insn (); | |
8b1c6fd7 | 7941 | first_io = XCNEWVEC (struct frv_io, last_basic_block_for_fn (cfun)); |
647d790d | 7942 | last_membar = XCNEWVEC (rtx_insn *, last_basic_block_for_fn (cfun)); |
38c28a25 | 7943 | |
11cd3bed | 7944 | FOR_EACH_BB_FN (bb, cfun) |
38c28a25 AH |
7945 | frv_optimize_membar_local (bb, &first_io[bb->index], |
7946 | &last_membar[bb->index]); | |
7947 | ||
11cd3bed | 7948 | FOR_EACH_BB_FN (bb, cfun) |
38c28a25 AH |
7949 | if (last_membar[bb->index] != 0) |
7950 | frv_optimize_membar_global (bb, first_io, last_membar[bb->index]); | |
7951 | ||
7952 | free (first_io); | |
7953 | free (last_membar); | |
7954 | } | |
7955 | \f | |
c557edf4 RS |
7956 | /* Used by frv_reorg to keep track of the current packet's address. */ |
7957 | static unsigned int frv_packet_address; | |
36a05131 | 7958 | |
c557edf4 RS |
7959 | /* If the current packet falls through to a label, try to pad the packet |
7960 | with nops in order to fit the label's alignment requirements. */ | |
7961 | ||
7962 | static void | |
7963 | frv_align_label (void) | |
7964 | { | |
7965 | unsigned int alignment, target, nop; | |
b32d5189 | 7966 | rtx_insn *x, *last, *barrier, *label; |
c557edf4 RS |
7967 | |
7968 | /* Walk forward to the start of the next packet. Set ALIGNMENT to the | |
7969 | maximum alignment of that packet, LABEL to the last label between | |
7970 | the packets, and BARRIER to the last barrier. */ | |
7971 | last = frv_packet.insns[frv_packet.num_insns - 1]; | |
7972 | label = barrier = 0; | |
7973 | alignment = 4; | |
7974 | for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x)) | |
7975 | { | |
7976 | if (LABEL_P (x)) | |
36a05131 | 7977 | { |
c557edf4 RS |
7978 | unsigned int subalign = 1 << label_to_alignment (x); |
7979 | alignment = MAX (alignment, subalign); | |
7980 | label = x; | |
36a05131 | 7981 | } |
c557edf4 RS |
7982 | if (BARRIER_P (x)) |
7983 | barrier = x; | |
7984 | } | |
36a05131 | 7985 | |
c557edf4 RS |
7986 | /* If -malign-labels, and the packet falls through to an unaligned |
7987 | label, try introducing a nop to align that label to 8 bytes. */ | |
7988 | if (TARGET_ALIGN_LABELS | |
7989 | && label != 0 | |
7990 | && barrier == 0 | |
7991 | && frv_packet.num_insns < frv_packet.issue_rate) | |
7992 | alignment = MAX (alignment, 8); | |
36a05131 | 7993 | |
c557edf4 RS |
7994 | /* Advance the address to the end of the current packet. */ |
7995 | frv_packet_address += frv_packet.num_insns * 4; | |
36a05131 | 7996 | |
c557edf4 RS |
7997 | /* Work out the target address, after alignment. */ |
7998 | target = (frv_packet_address + alignment - 1) & -alignment; | |
7999 | ||
8000 | /* If the packet falls through to the label, try to find an efficient | |
8001 | padding sequence. */ | |
8002 | if (barrier == 0) | |
8003 | { | |
8004 | /* First try adding nops to the current packet. */ | |
8005 | for (nop = 0; nop < frv_num_nops; nop++) | |
8006 | while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop])) | |
8007 | { | |
8008 | frv_insert_nop_in_packet (frv_nops[nop]); | |
8009 | frv_packet_address += 4; | |
8010 | } | |
8011 | ||
8012 | /* If we still haven't reached the target, add some new packets that | |
8013 | contain only nops. If there are two types of nop, insert an | |
8014 | alternating sequence of frv_nops[0] and frv_nops[1], which will | |
8015 | lead to packets like: | |
8016 | ||
8017 | nop.p | |
8018 | mnop.p/fnop.p | |
8019 | nop.p | |
8020 | mnop/fnop | |
8021 | ||
8022 | etc. Just emit frv_nops[0] if that's the only nop we have. */ | |
8023 | last = frv_packet.insns[frv_packet.num_insns - 1]; | |
8024 | nop = 0; | |
8025 | while (frv_packet_address < target) | |
8026 | { | |
8027 | last = emit_insn_after (PATTERN (frv_nops[nop]), last); | |
8028 | frv_packet_address += 4; | |
8029 | if (frv_num_nops > 1) | |
8030 | nop ^= 1; | |
36a05131 BS |
8031 | } |
8032 | } | |
8033 | ||
c557edf4 | 8034 | frv_packet_address = target; |
36a05131 BS |
8035 | } |
8036 | ||
c557edf4 RS |
8037 | /* Subroutine of frv_reorg, called after each packet has been constructed |
8038 | in frv_packet. */ | |
8039 | ||
8040 | static void | |
8041 | frv_reorg_packet (void) | |
8042 | { | |
8043 | frv_fill_unused_units (GROUP_I); | |
8044 | frv_fill_unused_units (GROUP_FM); | |
8045 | frv_align_label (); | |
8046 | } | |
8047 | ||
8048 | /* Add an instruction with pattern NOP to frv_nops[]. */ | |
8049 | ||
8050 | static void | |
8051 | frv_register_nop (rtx nop) | |
8052 | { | |
e6eda746 DM |
8053 | rtx_insn *nop_insn = make_insn_raw (nop); |
8054 | SET_NEXT_INSN (nop_insn) = 0; | |
8055 | SET_PREV_INSN (nop_insn) = 0; | |
8056 | frv_nops[frv_num_nops++] = nop_insn; | |
c557edf4 RS |
8057 | } |
8058 | ||
8059 | /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions | |
8060 | into packets and check whether we need to insert nops in order to | |
8061 | fulfill the processor's issue requirements. Also, if the user has | |
8062 | requested a certain alignment for a label, try to meet that alignment | |
8063 | by inserting nops in the previous packet. */ | |
8064 | ||
8065 | static void | |
8066 | frv_reorg (void) | |
8067 | { | |
38c28a25 AH |
8068 | if (optimize > 0 && TARGET_OPTIMIZE_MEMBAR && cfun->machine->has_membar_p) |
8069 | frv_optimize_membar (); | |
8070 | ||
c557edf4 RS |
8071 | frv_num_nops = 0; |
8072 | frv_register_nop (gen_nop ()); | |
8073 | if (TARGET_MEDIA) | |
8074 | frv_register_nop (gen_mnop ()); | |
8075 | if (TARGET_HARD_FLOAT) | |
8076 | frv_register_nop (gen_fnop ()); | |
8077 | ||
8078 | /* Estimate the length of each branch. Although this may change after | |
8079 | we've inserted nops, it will only do so in big functions. */ | |
8080 | shorten_branches (get_insns ()); | |
8081 | ||
8082 | frv_packet_address = 0; | |
8083 | frv_for_each_packet (frv_reorg_packet); | |
8084 | } | |
36a05131 BS |
8085 | \f |
8086 | #define def_builtin(name, type, code) \ | |
c79efc4d | 8087 | add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL) |
36a05131 BS |
8088 | |
8089 | struct builtin_description | |
8090 | { | |
8091 | enum insn_code icode; | |
8092 | const char *name; | |
8093 | enum frv_builtins code; | |
8094 | enum rtx_code comparison; | |
8095 | unsigned int flag; | |
8096 | }; | |
8097 | ||
8098 | /* Media intrinsics that take a single, constant argument. */ | |
8099 | ||
8100 | static struct builtin_description bdesc_set[] = | |
8101 | { | |
5c5e8419 | 8102 | { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, UNKNOWN, 0 } |
36a05131 BS |
8103 | }; |
8104 | ||
87b483a1 | 8105 | /* Media intrinsics that take just one argument. */ |
36a05131 BS |
8106 | |
8107 | static struct builtin_description bdesc_1arg[] = | |
8108 | { | |
5c5e8419 JR |
8109 | { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, UNKNOWN, 0 }, |
8110 | { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, UNKNOWN, 0 }, | |
8111 | { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, UNKNOWN, 0 }, | |
8112 | { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, UNKNOWN, 0}, | |
8113 | { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, UNKNOWN, 0 }, | |
8114 | { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, UNKNOWN, 0 } | |
36a05131 BS |
8115 | }; |
8116 | ||
87b483a1 | 8117 | /* Media intrinsics that take two arguments. */ |
36a05131 BS |
8118 | |
8119 | static struct builtin_description bdesc_2arg[] = | |
8120 | { | |
5c5e8419 JR |
8121 | { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, UNKNOWN, 0}, |
8122 | { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, UNKNOWN, 0}, | |
8123 | { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, UNKNOWN, 0}, | |
8124 | { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, UNKNOWN, 0}, | |
8125 | { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, UNKNOWN, 0}, | |
8126 | { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, UNKNOWN, 0}, | |
8127 | { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, UNKNOWN, 0}, | |
8128 | { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, UNKNOWN, 0}, | |
8129 | { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, UNKNOWN, 0}, | |
8130 | { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, UNKNOWN, 0}, | |
8131 | { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, UNKNOWN, 0}, | |
8132 | { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, UNKNOWN, 0}, | |
8133 | { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, UNKNOWN, 0}, | |
8134 | { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, UNKNOWN, 0}, | |
8135 | { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, UNKNOWN, 0}, | |
8136 | { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, UNKNOWN, 0}, | |
8137 | { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, UNKNOWN, 0}, | |
8138 | { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, UNKNOWN, 0}, | |
8139 | { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, UNKNOWN, 0}, | |
8140 | { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, UNKNOWN, 0}, | |
8141 | { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, UNKNOWN, 0}, | |
8142 | { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, UNKNOWN, 0}, | |
8143 | { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, UNKNOWN, 0}, | |
8144 | { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, UNKNOWN, 0}, | |
8145 | { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, UNKNOWN, 0}, | |
8146 | { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, UNKNOWN, 0}, | |
8147 | { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, UNKNOWN, 0} | |
c557edf4 RS |
8148 | }; |
8149 | ||
8150 | /* Integer intrinsics that take two arguments and have no return value. */ | |
8151 | ||
8152 | static struct builtin_description bdesc_int_void2arg[] = | |
8153 | { | |
5c5e8419 JR |
8154 | { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, UNKNOWN, 0}, |
8155 | { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, UNKNOWN, 0}, | |
8156 | { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, UNKNOWN, 0} | |
c557edf4 RS |
8157 | }; |
8158 | ||
8159 | static struct builtin_description bdesc_prefetches[] = | |
8160 | { | |
5c5e8419 JR |
8161 | { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, UNKNOWN, |
8162 | 0}, | |
8163 | { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, UNKNOWN, 0} | |
36a05131 BS |
8164 | }; |
8165 | ||
8166 | /* Media intrinsics that take two arguments, the first being an ACC number. */ | |
8167 | ||
8168 | static struct builtin_description bdesc_cut[] = | |
8169 | { | |
5c5e8419 JR |
8170 | { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, UNKNOWN, 0}, |
8171 | { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, UNKNOWN, 0}, | |
8172 | { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, UNKNOWN, 0} | |
36a05131 BS |
8173 | }; |
8174 | ||
87b483a1 | 8175 | /* Two-argument media intrinsics with an immediate second argument. */ |
36a05131 BS |
8176 | |
8177 | static struct builtin_description bdesc_2argimm[] = | |
8178 | { | |
5c5e8419 JR |
8179 | { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, UNKNOWN, 0}, |
8180 | { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, UNKNOWN, 0}, | |
8181 | { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, UNKNOWN, 0}, | |
8182 | { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, UNKNOWN, 0}, | |
8183 | { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, UNKNOWN, 0}, | |
8184 | { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, UNKNOWN, 0}, | |
8185 | { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, UNKNOWN, 0}, | |
8186 | { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, UNKNOWN, 0}, | |
8187 | { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, UNKNOWN, 0}, | |
8188 | { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, UNKNOWN, 0}, | |
8189 | { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, UNKNOWN, 0}, | |
8190 | { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, UNKNOWN, 0}, | |
8191 | { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, UNKNOWN, 0}, | |
8192 | { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, UNKNOWN, 0}, | |
8193 | { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, UNKNOWN, 0}, | |
8194 | { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, UNKNOWN, 0}, | |
8195 | { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, UNKNOWN, 0} | |
36a05131 BS |
8196 | }; |
8197 | ||
8198 | /* Media intrinsics that take two arguments and return void, the first argument | |
87b483a1 | 8199 | being a pointer to 4 words in memory. */ |
36a05131 BS |
8200 | |
8201 | static struct builtin_description bdesc_void2arg[] = | |
8202 | { | |
5c5e8419 JR |
8203 | { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, UNKNOWN, 0}, |
8204 | { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, UNKNOWN, 0}, | |
36a05131 BS |
8205 | }; |
8206 | ||
8207 | /* Media intrinsics that take three arguments, the first being a const_int that | |
87b483a1 | 8208 | denotes an accumulator, and that return void. */ |
36a05131 BS |
8209 | |
8210 | static struct builtin_description bdesc_void3arg[] = | |
8211 | { | |
5c5e8419 JR |
8212 | { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, UNKNOWN, 0}, |
8213 | { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, UNKNOWN, 0}, | |
8214 | { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, UNKNOWN, 0}, | |
8215 | { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, UNKNOWN, 0}, | |
8216 | { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, UNKNOWN, 0}, | |
8217 | { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, UNKNOWN, 0}, | |
8218 | { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, UNKNOWN, 0}, | |
8219 | { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, UNKNOWN, 0}, | |
8220 | { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, UNKNOWN, 0}, | |
8221 | { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, UNKNOWN, 0}, | |
8222 | { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, UNKNOWN, 0}, | |
8223 | { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, UNKNOWN, 0}, | |
8224 | { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, UNKNOWN, 0}, | |
8225 | { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, UNKNOWN, 0}, | |
8226 | { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, UNKNOWN, 0}, | |
8227 | { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, UNKNOWN, 0}, | |
8228 | { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, UNKNOWN, 0}, | |
8229 | { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, UNKNOWN, 0}, | |
8230 | { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, UNKNOWN, 0}, | |
8231 | { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, UNKNOWN, 0}, | |
8232 | { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, UNKNOWN, 0}, | |
8233 | { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, UNKNOWN, 0}, | |
8234 | { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, UNKNOWN, 0}, | |
8235 | { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, UNKNOWN, 0}, | |
8236 | { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, UNKNOWN, 0} | |
36a05131 BS |
8237 | }; |
8238 | ||
8239 | /* Media intrinsics that take two accumulator numbers as argument and | |
8240 | return void. */ | |
8241 | ||
8242 | static struct builtin_description bdesc_voidacc[] = | |
8243 | { | |
5c5e8419 JR |
8244 | { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, UNKNOWN, 0}, |
8245 | { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, UNKNOWN, 0}, | |
8246 | { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, UNKNOWN, 0}, | |
8247 | { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, UNKNOWN, 0}, | |
8248 | { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, UNKNOWN, 0}, | |
8249 | { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, UNKNOWN, 0} | |
36a05131 BS |
8250 | }; |
8251 | ||
38c28a25 AH |
8252 | /* Intrinsics that load a value and then issue a MEMBAR. The load is |
8253 | a normal move and the ICODE is for the membar. */ | |
c14ff86e AH |
8254 | |
8255 | static struct builtin_description bdesc_loads[] = | |
8256 | { | |
38c28a25 | 8257 | { CODE_FOR_optional_membar_qi, "__builtin_read8", |
5c5e8419 | 8258 | FRV_BUILTIN_READ8, UNKNOWN, 0}, |
38c28a25 | 8259 | { CODE_FOR_optional_membar_hi, "__builtin_read16", |
5c5e8419 | 8260 | FRV_BUILTIN_READ16, UNKNOWN, 0}, |
38c28a25 | 8261 | { CODE_FOR_optional_membar_si, "__builtin_read32", |
5c5e8419 | 8262 | FRV_BUILTIN_READ32, UNKNOWN, 0}, |
38c28a25 | 8263 | { CODE_FOR_optional_membar_di, "__builtin_read64", |
5c5e8419 | 8264 | FRV_BUILTIN_READ64, UNKNOWN, 0} |
c14ff86e AH |
8265 | }; |
8266 | ||
8267 | /* Likewise stores. */ | |
8268 | ||
8269 | static struct builtin_description bdesc_stores[] = | |
8270 | { | |
38c28a25 | 8271 | { CODE_FOR_optional_membar_qi, "__builtin_write8", |
5c5e8419 | 8272 | FRV_BUILTIN_WRITE8, UNKNOWN, 0}, |
38c28a25 | 8273 | { CODE_FOR_optional_membar_hi, "__builtin_write16", |
5c5e8419 | 8274 | FRV_BUILTIN_WRITE16, UNKNOWN, 0}, |
38c28a25 | 8275 | { CODE_FOR_optional_membar_si, "__builtin_write32", |
5c5e8419 | 8276 | FRV_BUILTIN_WRITE32, UNKNOWN, 0}, |
38c28a25 | 8277 | { CODE_FOR_optional_membar_di, "__builtin_write64", |
5c5e8419 | 8278 | FRV_BUILTIN_WRITE64, UNKNOWN, 0}, |
c14ff86e AH |
8279 | }; |
8280 | ||
87b483a1 | 8281 | /* Initialize media builtins. */ |
36a05131 | 8282 | |
14966b94 | 8283 | static void |
f2206911 | 8284 | frv_init_builtins (void) |
36a05131 | 8285 | { |
36a05131 BS |
8286 | tree accumulator = integer_type_node; |
8287 | tree integer = integer_type_node; | |
8288 | tree voidt = void_type_node; | |
8289 | tree uhalf = short_unsigned_type_node; | |
8290 | tree sword1 = long_integer_type_node; | |
8291 | tree uword1 = long_unsigned_type_node; | |
8292 | tree sword2 = long_long_integer_type_node; | |
8293 | tree uword2 = long_long_unsigned_type_node; | |
8294 | tree uword4 = build_pointer_type (uword1); | |
c14ff86e AH |
8295 | tree vptr = build_pointer_type (build_type_variant (void_type_node, 0, 1)); |
8296 | tree ubyte = unsigned_char_type_node; | |
c557edf4 | 8297 | tree iacc = integer_type_node; |
36a05131 BS |
8298 | |
8299 | #define UNARY(RET, T1) \ | |
e84a6fcf | 8300 | build_function_type_list (RET, T1, NULL_TREE) |
36a05131 BS |
8301 | |
8302 | #define BINARY(RET, T1, T2) \ | |
e84a6fcf | 8303 | build_function_type_list (RET, T1, T2, NULL_TREE) |
36a05131 BS |
8304 | |
8305 | #define TRINARY(RET, T1, T2, T3) \ | |
e84a6fcf | 8306 | build_function_type_list (RET, T1, T2, T3, NULL_TREE) |
36a05131 | 8307 | |
a738d848 | 8308 | #define QUAD(RET, T1, T2, T3, T4) \ |
4adf72f1 | 8309 | build_function_type_list (RET, T1, T2, T3, T4, NULL_TREE) |
a738d848 | 8310 | |
e84a6fcf | 8311 | tree void_ftype_void = build_function_type_list (voidt, NULL_TREE); |
36a05131 BS |
8312 | |
8313 | tree void_ftype_acc = UNARY (voidt, accumulator); | |
8314 | tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1); | |
8315 | tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2); | |
8316 | tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1); | |
8317 | tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator); | |
8318 | tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1); | |
8319 | tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1); | |
8320 | tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2); | |
8321 | tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2); | |
8322 | ||
8323 | tree uw1_ftype_uw1 = UNARY (uword1, uword1); | |
8324 | tree uw1_ftype_sw1 = UNARY (uword1, sword1); | |
8325 | tree uw1_ftype_uw2 = UNARY (uword1, uword2); | |
8326 | tree uw1_ftype_acc = UNARY (uword1, accumulator); | |
8327 | tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf); | |
8328 | tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1); | |
8329 | tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer); | |
8330 | tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1); | |
8331 | tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1); | |
8332 | tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1); | |
8333 | tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer); | |
8334 | ||
8335 | tree sw1_ftype_int = UNARY (sword1, integer); | |
8336 | tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1); | |
8337 | tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer); | |
8338 | ||
8339 | tree uw2_ftype_uw1 = UNARY (uword2, uword1); | |
8340 | tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer); | |
8341 | tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2); | |
8342 | tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer); | |
8343 | tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer); | |
a738d848 | 8344 | tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf); |
36a05131 BS |
8345 | |
8346 | tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2); | |
c557edf4 RS |
8347 | tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer); |
8348 | tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1); | |
8349 | tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1); | |
8350 | tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1); | |
8351 | tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2); | |
8352 | tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1); | |
8353 | tree sw1_ftype_sw1 = UNARY (sword1, sword1); | |
8354 | tree sw2_ftype_iacc = UNARY (sword2, iacc); | |
8355 | tree sw1_ftype_iacc = UNARY (sword1, iacc); | |
8356 | tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node); | |
c14ff86e AH |
8357 | tree uw1_ftype_vptr = UNARY (uword1, vptr); |
8358 | tree uw2_ftype_vptr = UNARY (uword2, vptr); | |
8359 | tree void_ftype_vptr_ub = BINARY (voidt, vptr, ubyte); | |
8360 | tree void_ftype_vptr_uh = BINARY (voidt, vptr, uhalf); | |
8361 | tree void_ftype_vptr_uw1 = BINARY (voidt, vptr, uword1); | |
8362 | tree void_ftype_vptr_uw2 = BINARY (voidt, vptr, uword2); | |
36a05131 BS |
8363 | |
8364 | def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND); | |
8365 | def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR); | |
8366 | def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR); | |
8367 | def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT); | |
8368 | def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI); | |
8369 | def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI); | |
8370 | def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT); | |
8371 | def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH); | |
8372 | def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI); | |
8373 | def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI); | |
8374 | def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI); | |
8375 | def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS); | |
8376 | def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU); | |
8377 | def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS); | |
8378 | def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS); | |
8379 | def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS); | |
8380 | def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS); | |
8381 | def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS); | |
8382 | def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU); | |
8383 | def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS); | |
8384 | def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU); | |
8385 | def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS); | |
8386 | def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU); | |
8387 | def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS); | |
8388 | def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU); | |
8389 | def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS); | |
8390 | def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS); | |
8391 | def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS); | |
8392 | def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS); | |
8393 | def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS); | |
8394 | def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU); | |
8395 | def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS); | |
8396 | def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU); | |
8397 | def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS); | |
8398 | def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU); | |
8399 | def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS); | |
8400 | def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU); | |
8401 | def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS); | |
8402 | def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU); | |
8403 | def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS); | |
8404 | def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU); | |
8405 | def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS); | |
8406 | def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU); | |
8407 | def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT); | |
8408 | def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS); | |
8409 | def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW); | |
8410 | def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD); | |
8411 | def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH); | |
8412 | def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH); | |
a738d848 | 8413 | def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH); |
b16c1435 | 8414 | def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH); |
36a05131 BS |
8415 | def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH); |
8416 | def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB); | |
8417 | def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE); | |
8418 | def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC); | |
8419 | def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA); | |
8420 | def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC); | |
8421 | def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG); | |
8422 | def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC); | |
8423 | def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG); | |
8424 | def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1); | |
8425 | def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2); | |
8426 | def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP); | |
8427 | def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS); | |
8428 | def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS); | |
8429 | def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS); | |
8430 | def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS); | |
8431 | def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS); | |
8432 | def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS); | |
8433 | def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS); | |
8434 | def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS); | |
8435 | def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS); | |
8436 | def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS); | |
8437 | def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI); | |
8438 | def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI); | |
8439 | def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI); | |
8440 | def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI); | |
8441 | def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS); | |
8442 | def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS); | |
8443 | def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS); | |
8444 | def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS); | |
8445 | def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH); | |
8446 | def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH); | |
8447 | def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH); | |
c557edf4 RS |
8448 | def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS); |
8449 | def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS); | |
8450 | def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI); | |
8451 | def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI); | |
8452 | def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL); | |
8453 | def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL); | |
8454 | def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS); | |
8455 | def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS); | |
8456 | def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU); | |
8457 | def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS); | |
8458 | def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS); | |
8459 | def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS); | |
8460 | def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN); | |
8461 | def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS); | |
8462 | def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll); | |
8463 | def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl); | |
8464 | def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll); | |
8465 | def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl); | |
8466 | def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0); | |
8467 | def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH); | |
c14ff86e AH |
8468 | def_builtin ("__builtin_read8", uw1_ftype_vptr, FRV_BUILTIN_READ8); |
8469 | def_builtin ("__builtin_read16", uw1_ftype_vptr, FRV_BUILTIN_READ16); | |
8470 | def_builtin ("__builtin_read32", uw1_ftype_vptr, FRV_BUILTIN_READ32); | |
8471 | def_builtin ("__builtin_read64", uw2_ftype_vptr, FRV_BUILTIN_READ64); | |
8472 | ||
8473 | def_builtin ("__builtin_write8", void_ftype_vptr_ub, FRV_BUILTIN_WRITE8); | |
8474 | def_builtin ("__builtin_write16", void_ftype_vptr_uh, FRV_BUILTIN_WRITE16); | |
8475 | def_builtin ("__builtin_write32", void_ftype_vptr_uw1, FRV_BUILTIN_WRITE32); | |
8476 | def_builtin ("__builtin_write64", void_ftype_vptr_uw2, FRV_BUILTIN_WRITE64); | |
36a05131 BS |
8477 | |
8478 | #undef UNARY | |
8479 | #undef BINARY | |
8480 | #undef TRINARY | |
a738d848 | 8481 | #undef QUAD |
36a05131 BS |
8482 | } |
8483 | ||
c15c90bb ZW |
8484 | /* Set the names for various arithmetic operations according to the |
8485 | FRV ABI. */ | |
8486 | static void | |
8487 | frv_init_libfuncs (void) | |
8488 | { | |
8489 | set_optab_libfunc (smod_optab, SImode, "__modi"); | |
8490 | set_optab_libfunc (umod_optab, SImode, "__umodi"); | |
8491 | ||
8492 | set_optab_libfunc (add_optab, DImode, "__addll"); | |
8493 | set_optab_libfunc (sub_optab, DImode, "__subll"); | |
8494 | set_optab_libfunc (smul_optab, DImode, "__mulll"); | |
8495 | set_optab_libfunc (sdiv_optab, DImode, "__divll"); | |
8496 | set_optab_libfunc (smod_optab, DImode, "__modll"); | |
8497 | set_optab_libfunc (umod_optab, DImode, "__umodll"); | |
8498 | set_optab_libfunc (and_optab, DImode, "__andll"); | |
8499 | set_optab_libfunc (ior_optab, DImode, "__orll"); | |
8500 | set_optab_libfunc (xor_optab, DImode, "__xorll"); | |
8501 | set_optab_libfunc (one_cmpl_optab, DImode, "__notll"); | |
8502 | ||
8503 | set_optab_libfunc (add_optab, SFmode, "__addf"); | |
8504 | set_optab_libfunc (sub_optab, SFmode, "__subf"); | |
8505 | set_optab_libfunc (smul_optab, SFmode, "__mulf"); | |
8506 | set_optab_libfunc (sdiv_optab, SFmode, "__divf"); | |
8507 | ||
8508 | set_optab_libfunc (add_optab, DFmode, "__addd"); | |
8509 | set_optab_libfunc (sub_optab, DFmode, "__subd"); | |
8510 | set_optab_libfunc (smul_optab, DFmode, "__muld"); | |
8511 | set_optab_libfunc (sdiv_optab, DFmode, "__divd"); | |
8512 | ||
85363ca0 ZW |
8513 | set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod"); |
8514 | set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof"); | |
8515 | ||
8516 | set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi"); | |
8517 | set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll"); | |
8518 | set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi"); | |
8519 | set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll"); | |
8520 | ||
8521 | set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui"); | |
09c55720 RS |
8522 | set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull"); |
8523 | set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui"); | |
8524 | set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull"); | |
85363ca0 ZW |
8525 | |
8526 | set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof"); | |
8527 | set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof"); | |
8528 | set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod"); | |
8529 | set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod"); | |
c15c90bb ZW |
8530 | } |
8531 | ||
36a05131 BS |
8532 | /* Convert an integer constant to an accumulator register. ICODE is the |
8533 | code of the target instruction, OPNUM is the number of the | |
8534 | accumulator operand and OPVAL is the constant integer. Try both | |
8535 | ACC and ACCG registers; only report an error if neither fit the | |
8536 | instruction. */ | |
8537 | ||
8538 | static rtx | |
f2206911 | 8539 | frv_int_to_acc (enum insn_code icode, int opnum, rtx opval) |
36a05131 BS |
8540 | { |
8541 | rtx reg; | |
c557edf4 RS |
8542 | int i; |
8543 | ||
0fa2e4df | 8544 | /* ACCs and ACCGs are implicit global registers if media intrinsics |
c557edf4 | 8545 | are being used. We set up this lazily to avoid creating lots of |
c112cf2b | 8546 | unnecessary call_insn rtl in non-media code. */ |
c557edf4 RS |
8547 | for (i = 0; i <= ACC_MASK; i++) |
8548 | if ((i & ACC_MASK) == i) | |
8549 | global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1; | |
36a05131 BS |
8550 | |
8551 | if (GET_CODE (opval) != CONST_INT) | |
8552 | { | |
8553 | error ("accumulator is not a constant integer"); | |
8554 | return NULL_RTX; | |
8555 | } | |
c557edf4 | 8556 | if ((INTVAL (opval) & ~ACC_MASK) != 0) |
36a05131 BS |
8557 | { |
8558 | error ("accumulator number is out of bounds"); | |
8559 | return NULL_RTX; | |
8560 | } | |
8561 | ||
8562 | reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode, | |
8563 | ACC_FIRST + INTVAL (opval)); | |
8564 | if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode)) | |
6fb5fa3c | 8565 | SET_REGNO (reg, ACCG_FIRST + INTVAL (opval)); |
36a05131 BS |
8566 | |
8567 | if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode)) | |
8568 | { | |
9e637a26 | 8569 | error ("inappropriate accumulator for %qs", insn_data[icode].name); |
36a05131 BS |
8570 | return NULL_RTX; |
8571 | } | |
8572 | return reg; | |
8573 | } | |
8574 | ||
8575 | /* If an ACC rtx has mode MODE, return the mode that the matching ACCG | |
8576 | should have. */ | |
8577 | ||
ef4bddc2 RS |
8578 | static machine_mode |
8579 | frv_matching_accg_mode (machine_mode mode) | |
36a05131 BS |
8580 | { |
8581 | switch (mode) | |
8582 | { | |
4e10a5a7 | 8583 | case E_V4SImode: |
36a05131 BS |
8584 | return V4QImode; |
8585 | ||
4e10a5a7 | 8586 | case E_DImode: |
36a05131 BS |
8587 | return HImode; |
8588 | ||
4e10a5a7 | 8589 | case E_SImode: |
36a05131 BS |
8590 | return QImode; |
8591 | ||
8592 | default: | |
44e91694 | 8593 | gcc_unreachable (); |
36a05131 BS |
8594 | } |
8595 | } | |
8596 | ||
38c28a25 AH |
8597 | /* Given that a __builtin_read or __builtin_write function is accessing |
8598 | address ADDRESS, return the value that should be used as operand 1 | |
8599 | of the membar. */ | |
8600 | ||
8601 | static rtx | |
8602 | frv_io_address_cookie (rtx address) | |
8603 | { | |
8604 | return (GET_CODE (address) == CONST_INT | |
8605 | ? GEN_INT (INTVAL (address) / 8 * 8) | |
8606 | : const0_rtx); | |
8607 | } | |
8608 | ||
36a05131 BS |
8609 | /* Return the accumulator guard that should be paired with accumulator |
8610 | register ACC. The mode of the returned register is in the same | |
8611 | class as ACC, but is four times smaller. */ | |
8612 | ||
8613 | rtx | |
f2206911 | 8614 | frv_matching_accg_for_acc (rtx acc) |
36a05131 BS |
8615 | { |
8616 | return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)), | |
8617 | REGNO (acc) - ACC_FIRST + ACCG_FIRST); | |
8618 | } | |
8619 | ||
2396bce1 EC |
8620 | /* Read the requested argument from the call EXP given by INDEX. |
8621 | Return the value as an rtx. */ | |
36a05131 BS |
8622 | |
8623 | static rtx | |
2396bce1 | 8624 | frv_read_argument (tree exp, unsigned int index) |
36a05131 | 8625 | { |
5c5e8419 | 8626 | return expand_normal (CALL_EXPR_ARG (exp, index)); |
36a05131 BS |
8627 | } |
8628 | ||
c557edf4 RS |
8629 | /* Like frv_read_argument, but interpret the argument as the number |
8630 | of an IACC register and return a (reg:MODE ...) rtx for it. */ | |
8631 | ||
8632 | static rtx | |
ef4bddc2 | 8633 | frv_read_iacc_argument (machine_mode mode, tree call, |
2396bce1 | 8634 | unsigned int index) |
c557edf4 RS |
8635 | { |
8636 | int i, regno; | |
8637 | rtx op; | |
8638 | ||
2396bce1 | 8639 | op = frv_read_argument (call, index); |
c557edf4 RS |
8640 | if (GET_CODE (op) != CONST_INT |
8641 | || INTVAL (op) < 0 | |
8642 | || INTVAL (op) > IACC_LAST - IACC_FIRST | |
8643 | || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0) | |
8644 | { | |
8645 | error ("invalid IACC argument"); | |
8646 | op = const0_rtx; | |
8647 | } | |
8648 | ||
0fa2e4df | 8649 | /* IACCs are implicit global registers. We set up this lazily to |
c112cf2b | 8650 | avoid creating lots of unnecessary call_insn rtl when IACCs aren't |
c557edf4 RS |
8651 | being used. */ |
8652 | regno = INTVAL (op) + IACC_FIRST; | |
8653 | for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++) | |
8654 | global_regs[regno + i] = 1; | |
8655 | ||
8656 | return gen_rtx_REG (mode, regno); | |
8657 | } | |
8658 | ||
36a05131 BS |
8659 | /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE. |
8660 | The instruction should require a constant operand of some sort. The | |
8661 | function prints an error if OPVAL is not valid. */ | |
8662 | ||
8663 | static int | |
f2206911 | 8664 | frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval) |
36a05131 BS |
8665 | { |
8666 | if (GET_CODE (opval) != CONST_INT) | |
8667 | { | |
9e637a26 | 8668 | error ("%qs expects a constant argument", insn_data[icode].name); |
36a05131 BS |
8669 | return FALSE; |
8670 | } | |
8671 | if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode)) | |
8672 | { | |
9e637a26 | 8673 | error ("constant argument out of range for %qs", insn_data[icode].name); |
36a05131 BS |
8674 | return FALSE; |
8675 | } | |
8676 | return TRUE; | |
8677 | } | |
8678 | ||
8679 | /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET | |
8680 | if it's not null, has the right mode, and satisfies operand 0's | |
8681 | predicate. */ | |
8682 | ||
8683 | static rtx | |
f2206911 | 8684 | frv_legitimize_target (enum insn_code icode, rtx target) |
36a05131 | 8685 | { |
ef4bddc2 | 8686 | machine_mode mode = insn_data[icode].operand[0].mode; |
36a05131 BS |
8687 | |
8688 | if (! target | |
8689 | || GET_MODE (target) != mode | |
8690 | || ! (*insn_data[icode].operand[0].predicate) (target, mode)) | |
8691 | return gen_reg_rtx (mode); | |
8692 | else | |
8693 | return target; | |
8694 | } | |
8695 | ||
8696 | /* Given that ARG is being passed as operand OPNUM to instruction ICODE, | |
839a4992 | 8697 | check whether ARG satisfies the operand's constraints. If it doesn't, |
36a05131 BS |
8698 | copy ARG to a temporary register and return that. Otherwise return ARG |
8699 | itself. */ | |
8700 | ||
8701 | static rtx | |
f2206911 | 8702 | frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg) |
36a05131 | 8703 | { |
ef4bddc2 | 8704 | machine_mode mode = insn_data[icode].operand[opnum].mode; |
36a05131 BS |
8705 | |
8706 | if ((*insn_data[icode].operand[opnum].predicate) (arg, mode)) | |
8707 | return arg; | |
8708 | else | |
8709 | return copy_to_mode_reg (mode, arg); | |
8710 | } | |
8711 | ||
c14ff86e AH |
8712 | /* Return a volatile memory reference of mode MODE whose address is ARG. */ |
8713 | ||
8714 | static rtx | |
ef4bddc2 | 8715 | frv_volatile_memref (machine_mode mode, rtx arg) |
c14ff86e AH |
8716 | { |
8717 | rtx mem; | |
8718 | ||
8719 | mem = gen_rtx_MEM (mode, memory_address (mode, arg)); | |
8720 | MEM_VOLATILE_P (mem) = 1; | |
8721 | return mem; | |
8722 | } | |
8723 | ||
36a05131 BS |
8724 | /* Expand builtins that take a single, constant argument. At the moment, |
8725 | only MHDSETS falls into this category. */ | |
8726 | ||
8727 | static rtx | |
2396bce1 | 8728 | frv_expand_set_builtin (enum insn_code icode, tree call, rtx target) |
36a05131 BS |
8729 | { |
8730 | rtx pat; | |
2396bce1 | 8731 | rtx op0 = frv_read_argument (call, 0); |
36a05131 BS |
8732 | |
8733 | if (! frv_check_constant_argument (icode, 1, op0)) | |
8734 | return NULL_RTX; | |
8735 | ||
8736 | target = frv_legitimize_target (icode, target); | |
8737 | pat = GEN_FCN (icode) (target, op0); | |
8738 | if (! pat) | |
8739 | return NULL_RTX; | |
8740 | ||
8741 | emit_insn (pat); | |
8742 | return target; | |
8743 | } | |
8744 | ||
87b483a1 | 8745 | /* Expand builtins that take one operand. */ |
36a05131 BS |
8746 | |
8747 | static rtx | |
2396bce1 | 8748 | frv_expand_unop_builtin (enum insn_code icode, tree call, rtx target) |
36a05131 BS |
8749 | { |
8750 | rtx pat; | |
2396bce1 | 8751 | rtx op0 = frv_read_argument (call, 0); |
36a05131 BS |
8752 | |
8753 | target = frv_legitimize_target (icode, target); | |
8754 | op0 = frv_legitimize_argument (icode, 1, op0); | |
8755 | pat = GEN_FCN (icode) (target, op0); | |
8756 | if (! pat) | |
8757 | return NULL_RTX; | |
8758 | ||
8759 | emit_insn (pat); | |
8760 | return target; | |
8761 | } | |
8762 | ||
87b483a1 | 8763 | /* Expand builtins that take two operands. */ |
36a05131 BS |
8764 | |
8765 | static rtx | |
2396bce1 | 8766 | frv_expand_binop_builtin (enum insn_code icode, tree call, rtx target) |
36a05131 BS |
8767 | { |
8768 | rtx pat; | |
2396bce1 EC |
8769 | rtx op0 = frv_read_argument (call, 0); |
8770 | rtx op1 = frv_read_argument (call, 1); | |
36a05131 BS |
8771 | |
8772 | target = frv_legitimize_target (icode, target); | |
8773 | op0 = frv_legitimize_argument (icode, 1, op0); | |
8774 | op1 = frv_legitimize_argument (icode, 2, op1); | |
8775 | pat = GEN_FCN (icode) (target, op0, op1); | |
8776 | if (! pat) | |
8777 | return NULL_RTX; | |
8778 | ||
8779 | emit_insn (pat); | |
8780 | return target; | |
8781 | } | |
8782 | ||
8783 | /* Expand cut-style builtins, which take two operands and an implicit ACCG | |
87b483a1 | 8784 | one. */ |
36a05131 BS |
8785 | |
8786 | static rtx | |
2396bce1 | 8787 | frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target) |
36a05131 BS |
8788 | { |
8789 | rtx pat; | |
2396bce1 EC |
8790 | rtx op0 = frv_read_argument (call, 0); |
8791 | rtx op1 = frv_read_argument (call, 1); | |
36a05131 BS |
8792 | rtx op2; |
8793 | ||
8794 | target = frv_legitimize_target (icode, target); | |
8795 | op0 = frv_int_to_acc (icode, 1, op0); | |
8796 | if (! op0) | |
8797 | return NULL_RTX; | |
8798 | ||
8799 | if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT) | |
8800 | { | |
8801 | if (! frv_check_constant_argument (icode, 2, op1)) | |
8802 | return NULL_RTX; | |
8803 | } | |
8804 | else | |
8805 | op1 = frv_legitimize_argument (icode, 2, op1); | |
8806 | ||
8807 | op2 = frv_matching_accg_for_acc (op0); | |
8808 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
8809 | if (! pat) | |
8810 | return NULL_RTX; | |
8811 | ||
8812 | emit_insn (pat); | |
8813 | return target; | |
8814 | } | |
8815 | ||
87b483a1 | 8816 | /* Expand builtins that take two operands and the second is immediate. */ |
36a05131 BS |
8817 | |
8818 | static rtx | |
2396bce1 | 8819 | frv_expand_binopimm_builtin (enum insn_code icode, tree call, rtx target) |
36a05131 BS |
8820 | { |
8821 | rtx pat; | |
2396bce1 EC |
8822 | rtx op0 = frv_read_argument (call, 0); |
8823 | rtx op1 = frv_read_argument (call, 1); | |
36a05131 BS |
8824 | |
8825 | if (! frv_check_constant_argument (icode, 2, op1)) | |
8826 | return NULL_RTX; | |
8827 | ||
8828 | target = frv_legitimize_target (icode, target); | |
8829 | op0 = frv_legitimize_argument (icode, 1, op0); | |
8830 | pat = GEN_FCN (icode) (target, op0, op1); | |
8831 | if (! pat) | |
8832 | return NULL_RTX; | |
8833 | ||
8834 | emit_insn (pat); | |
8835 | return target; | |
8836 | } | |
8837 | ||
8838 | /* Expand builtins that take two operands, the first operand being a pointer to | |
87b483a1 | 8839 | ints and return void. */ |
36a05131 BS |
8840 | |
8841 | static rtx | |
2396bce1 | 8842 | frv_expand_voidbinop_builtin (enum insn_code icode, tree call) |
36a05131 BS |
8843 | { |
8844 | rtx pat; | |
2396bce1 EC |
8845 | rtx op0 = frv_read_argument (call, 0); |
8846 | rtx op1 = frv_read_argument (call, 1); | |
ef4bddc2 | 8847 | machine_mode mode0 = insn_data[icode].operand[0].mode; |
36a05131 BS |
8848 | rtx addr; |
8849 | ||
8850 | if (GET_CODE (op0) != MEM) | |
8851 | { | |
8852 | rtx reg = op0; | |
8853 | ||
8854 | if (! offsettable_address_p (0, mode0, op0)) | |
8855 | { | |
8856 | reg = gen_reg_rtx (Pmode); | |
f7df4a84 | 8857 | emit_insn (gen_rtx_SET (reg, op0)); |
36a05131 BS |
8858 | } |
8859 | ||
8860 | op0 = gen_rtx_MEM (SImode, reg); | |
8861 | } | |
8862 | ||
8863 | addr = XEXP (op0, 0); | |
8864 | if (! offsettable_address_p (0, mode0, addr)) | |
8865 | addr = copy_to_mode_reg (Pmode, op0); | |
8866 | ||
8867 | op0 = change_address (op0, V4SImode, addr); | |
8868 | op1 = frv_legitimize_argument (icode, 1, op1); | |
8869 | pat = GEN_FCN (icode) (op0, op1); | |
8870 | if (! pat) | |
8871 | return 0; | |
8872 | ||
8873 | emit_insn (pat); | |
8874 | return 0; | |
8875 | } | |
8876 | ||
c557edf4 RS |
8877 | /* Expand builtins that take two long operands and return void. */ |
8878 | ||
8879 | static rtx | |
2396bce1 | 8880 | frv_expand_int_void2arg (enum insn_code icode, tree call) |
c557edf4 RS |
8881 | { |
8882 | rtx pat; | |
2396bce1 EC |
8883 | rtx op0 = frv_read_argument (call, 0); |
8884 | rtx op1 = frv_read_argument (call, 1); | |
c557edf4 RS |
8885 | |
8886 | op0 = frv_legitimize_argument (icode, 1, op0); | |
8887 | op1 = frv_legitimize_argument (icode, 1, op1); | |
8888 | pat = GEN_FCN (icode) (op0, op1); | |
8889 | if (! pat) | |
8890 | return NULL_RTX; | |
8891 | ||
8892 | emit_insn (pat); | |
8893 | return NULL_RTX; | |
8894 | } | |
8895 | ||
8896 | /* Expand prefetch builtins. These take a single address as argument. */ | |
8897 | ||
8898 | static rtx | |
2396bce1 | 8899 | frv_expand_prefetches (enum insn_code icode, tree call) |
c557edf4 RS |
8900 | { |
8901 | rtx pat; | |
2396bce1 | 8902 | rtx op0 = frv_read_argument (call, 0); |
c557edf4 RS |
8903 | |
8904 | pat = GEN_FCN (icode) (force_reg (Pmode, op0)); | |
8905 | if (! pat) | |
8906 | return 0; | |
8907 | ||
8908 | emit_insn (pat); | |
8909 | return 0; | |
8910 | } | |
8911 | ||
36a05131 BS |
8912 | /* Expand builtins that take three operands and return void. The first |
8913 | argument must be a constant that describes a pair or quad accumulators. A | |
8914 | fourth argument is created that is the accumulator guard register that | |
8915 | corresponds to the accumulator. */ | |
8916 | ||
8917 | static rtx | |
2396bce1 | 8918 | frv_expand_voidtriop_builtin (enum insn_code icode, tree call) |
36a05131 BS |
8919 | { |
8920 | rtx pat; | |
2396bce1 EC |
8921 | rtx op0 = frv_read_argument (call, 0); |
8922 | rtx op1 = frv_read_argument (call, 1); | |
8923 | rtx op2 = frv_read_argument (call, 2); | |
36a05131 BS |
8924 | rtx op3; |
8925 | ||
8926 | op0 = frv_int_to_acc (icode, 0, op0); | |
8927 | if (! op0) | |
8928 | return NULL_RTX; | |
8929 | ||
8930 | op1 = frv_legitimize_argument (icode, 1, op1); | |
8931 | op2 = frv_legitimize_argument (icode, 2, op2); | |
8932 | op3 = frv_matching_accg_for_acc (op0); | |
8933 | pat = GEN_FCN (icode) (op0, op1, op2, op3); | |
8934 | if (! pat) | |
8935 | return NULL_RTX; | |
8936 | ||
8937 | emit_insn (pat); | |
8938 | return NULL_RTX; | |
8939 | } | |
8940 | ||
8941 | /* Expand builtins that perform accumulator-to-accumulator operations. | |
8942 | These builtins take two accumulator numbers as argument and return | |
8943 | void. */ | |
8944 | ||
8945 | static rtx | |
2396bce1 | 8946 | frv_expand_voidaccop_builtin (enum insn_code icode, tree call) |
36a05131 BS |
8947 | { |
8948 | rtx pat; | |
2396bce1 EC |
8949 | rtx op0 = frv_read_argument (call, 0); |
8950 | rtx op1 = frv_read_argument (call, 1); | |
36a05131 BS |
8951 | rtx op2; |
8952 | rtx op3; | |
8953 | ||
8954 | op0 = frv_int_to_acc (icode, 0, op0); | |
8955 | if (! op0) | |
8956 | return NULL_RTX; | |
8957 | ||
8958 | op1 = frv_int_to_acc (icode, 1, op1); | |
8959 | if (! op1) | |
8960 | return NULL_RTX; | |
8961 | ||
8962 | op2 = frv_matching_accg_for_acc (op0); | |
8963 | op3 = frv_matching_accg_for_acc (op1); | |
8964 | pat = GEN_FCN (icode) (op0, op1, op2, op3); | |
8965 | if (! pat) | |
8966 | return NULL_RTX; | |
8967 | ||
8968 | emit_insn (pat); | |
8969 | return NULL_RTX; | |
8970 | } | |
8971 | ||
38c28a25 AH |
8972 | /* Expand a __builtin_read* function. ICODE is the instruction code for the |
8973 | membar and TARGET_MODE is the mode that the loaded value should have. */ | |
c14ff86e AH |
8974 | |
8975 | static rtx | |
ef4bddc2 | 8976 | frv_expand_load_builtin (enum insn_code icode, machine_mode target_mode, |
2396bce1 | 8977 | tree call, rtx target) |
c14ff86e | 8978 | { |
2396bce1 | 8979 | rtx op0 = frv_read_argument (call, 0); |
38c28a25 AH |
8980 | rtx cookie = frv_io_address_cookie (op0); |
8981 | ||
8982 | if (target == 0 || !REG_P (target)) | |
8983 | target = gen_reg_rtx (target_mode); | |
8984 | op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0); | |
8985 | convert_move (target, op0, 1); | |
8986 | emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ))); | |
8987 | cfun->machine->has_membar_p = 1; | |
c14ff86e AH |
8988 | return target; |
8989 | } | |
8990 | ||
38c28a25 | 8991 | /* Likewise __builtin_write* functions. */ |
c14ff86e AH |
8992 | |
8993 | static rtx | |
2396bce1 | 8994 | frv_expand_store_builtin (enum insn_code icode, tree call) |
c14ff86e | 8995 | { |
2396bce1 EC |
8996 | rtx op0 = frv_read_argument (call, 0); |
8997 | rtx op1 = frv_read_argument (call, 1); | |
38c28a25 | 8998 | rtx cookie = frv_io_address_cookie (op0); |
c14ff86e | 8999 | |
38c28a25 AH |
9000 | op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0); |
9001 | convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1); | |
9002 | emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE))); | |
9003 | cfun->machine->has_membar_p = 1; | |
c14ff86e AH |
9004 | return NULL_RTX; |
9005 | } | |
9006 | ||
a738d848 RS |
9007 | /* Expand the MDPACKH builtin. It takes four unsigned short arguments and |
9008 | each argument forms one word of the two double-word input registers. | |
2396bce1 EC |
9009 | CALL is the tree for the call and TARGET, if nonnull, suggests a good place |
9010 | to put the return value. */ | |
a738d848 RS |
9011 | |
9012 | static rtx | |
2396bce1 | 9013 | frv_expand_mdpackh_builtin (tree call, rtx target) |
a738d848 RS |
9014 | { |
9015 | enum insn_code icode = CODE_FOR_mdpackh; | |
9016 | rtx pat, op0, op1; | |
2396bce1 EC |
9017 | rtx arg1 = frv_read_argument (call, 0); |
9018 | rtx arg2 = frv_read_argument (call, 1); | |
9019 | rtx arg3 = frv_read_argument (call, 2); | |
9020 | rtx arg4 = frv_read_argument (call, 3); | |
a738d848 RS |
9021 | |
9022 | target = frv_legitimize_target (icode, target); | |
9023 | op0 = gen_reg_rtx (DImode); | |
9024 | op1 = gen_reg_rtx (DImode); | |
9025 | ||
0fa2e4df | 9026 | /* The high half of each word is not explicitly initialized, so indicate |
a738d848 | 9027 | that the input operands are not live before this point. */ |
c41c1387 RS |
9028 | emit_clobber (op0); |
9029 | emit_clobber (op1); | |
a738d848 RS |
9030 | |
9031 | /* Move each argument into the low half of its associated input word. */ | |
9032 | emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1); | |
9033 | emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2); | |
9034 | emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3); | |
9035 | emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4); | |
9036 | ||
9037 | pat = GEN_FCN (icode) (target, op0, op1); | |
9038 | if (! pat) | |
9039 | return NULL_RTX; | |
9040 | ||
9041 | emit_insn (pat); | |
9042 | return target; | |
9043 | } | |
9044 | ||
36a05131 BS |
9045 | /* Expand the MCLRACC builtin. This builtin takes a single accumulator |
9046 | number as argument. */ | |
9047 | ||
9048 | static rtx | |
2396bce1 | 9049 | frv_expand_mclracc_builtin (tree call) |
36a05131 BS |
9050 | { |
9051 | enum insn_code icode = CODE_FOR_mclracc; | |
9052 | rtx pat; | |
2396bce1 | 9053 | rtx op0 = frv_read_argument (call, 0); |
36a05131 BS |
9054 | |
9055 | op0 = frv_int_to_acc (icode, 0, op0); | |
9056 | if (! op0) | |
9057 | return NULL_RTX; | |
9058 | ||
9059 | pat = GEN_FCN (icode) (op0); | |
9060 | if (pat) | |
9061 | emit_insn (pat); | |
9062 | ||
9063 | return NULL_RTX; | |
9064 | } | |
9065 | ||
9066 | /* Expand builtins that take no arguments. */ | |
9067 | ||
9068 | static rtx | |
f2206911 | 9069 | frv_expand_noargs_builtin (enum insn_code icode) |
36a05131 | 9070 | { |
a556fd39 | 9071 | rtx pat = GEN_FCN (icode) (const0_rtx); |
36a05131 BS |
9072 | if (pat) |
9073 | emit_insn (pat); | |
9074 | ||
9075 | return NULL_RTX; | |
9076 | } | |
9077 | ||
9078 | /* Expand MRDACC and MRDACCG. These builtins take a single accumulator | |
9079 | number or accumulator guard number as argument and return an SI integer. */ | |
9080 | ||
9081 | static rtx | |
2396bce1 | 9082 | frv_expand_mrdacc_builtin (enum insn_code icode, tree call) |
36a05131 BS |
9083 | { |
9084 | rtx pat; | |
9085 | rtx target = gen_reg_rtx (SImode); | |
2396bce1 | 9086 | rtx op0 = frv_read_argument (call, 0); |
36a05131 BS |
9087 | |
9088 | op0 = frv_int_to_acc (icode, 1, op0); | |
9089 | if (! op0) | |
9090 | return NULL_RTX; | |
9091 | ||
9092 | pat = GEN_FCN (icode) (target, op0); | |
9093 | if (! pat) | |
9094 | return NULL_RTX; | |
9095 | ||
9096 | emit_insn (pat); | |
9097 | return target; | |
9098 | } | |
9099 | ||
9100 | /* Expand MWTACC and MWTACCG. These builtins take an accumulator or | |
9101 | accumulator guard as their first argument and an SImode value as their | |
9102 | second. */ | |
9103 | ||
9104 | static rtx | |
2396bce1 | 9105 | frv_expand_mwtacc_builtin (enum insn_code icode, tree call) |
36a05131 BS |
9106 | { |
9107 | rtx pat; | |
2396bce1 EC |
9108 | rtx op0 = frv_read_argument (call, 0); |
9109 | rtx op1 = frv_read_argument (call, 1); | |
36a05131 BS |
9110 | |
9111 | op0 = frv_int_to_acc (icode, 0, op0); | |
9112 | if (! op0) | |
9113 | return NULL_RTX; | |
9114 | ||
9115 | op1 = frv_legitimize_argument (icode, 1, op1); | |
9116 | pat = GEN_FCN (icode) (op0, op1); | |
9117 | if (pat) | |
9118 | emit_insn (pat); | |
9119 | ||
9120 | return NULL_RTX; | |
9121 | } | |
9122 | ||
c557edf4 RS |
9123 | /* Emit a move from SRC to DEST in SImode chunks. This can be used |
9124 | to move DImode values into and out of IACC0. */ | |
9125 | ||
9126 | static void | |
9127 | frv_split_iacc_move (rtx dest, rtx src) | |
9128 | { | |
ef4bddc2 | 9129 | machine_mode inner; |
c557edf4 RS |
9130 | int i; |
9131 | ||
9132 | inner = GET_MODE (dest); | |
9133 | for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode)) | |
9134 | emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i), | |
9135 | simplify_gen_subreg (SImode, src, inner, i)); | |
9136 | } | |
9137 | ||
87b483a1 | 9138 | /* Expand builtins. */ |
36a05131 | 9139 | |
14966b94 | 9140 | static rtx |
f2206911 KC |
9141 | frv_expand_builtin (tree exp, |
9142 | rtx target, | |
9143 | rtx subtarget ATTRIBUTE_UNUSED, | |
ef4bddc2 | 9144 | machine_mode mode ATTRIBUTE_UNUSED, |
f2206911 | 9145 | int ignore ATTRIBUTE_UNUSED) |
36a05131 | 9146 | { |
5039610b | 9147 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
36a05131 BS |
9148 | unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl); |
9149 | unsigned i; | |
9150 | struct builtin_description *d; | |
9151 | ||
c557edf4 | 9152 | if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA) |
36a05131 BS |
9153 | { |
9154 | error ("media functions are not available unless -mmedia is used"); | |
9155 | return NULL_RTX; | |
9156 | } | |
9157 | ||
9158 | switch (fcode) | |
9159 | { | |
9160 | case FRV_BUILTIN_MCOP1: | |
9161 | case FRV_BUILTIN_MCOP2: | |
9162 | case FRV_BUILTIN_MDUNPACKH: | |
9163 | case FRV_BUILTIN_MBTOHE: | |
9164 | if (! TARGET_MEDIA_REV1) | |
9165 | { | |
9166 | error ("this media function is only available on the fr500"); | |
9167 | return NULL_RTX; | |
9168 | } | |
9169 | break; | |
9170 | ||
9171 | case FRV_BUILTIN_MQXMACHS: | |
9172 | case FRV_BUILTIN_MQXMACXHS: | |
9173 | case FRV_BUILTIN_MQMACXHS: | |
9174 | case FRV_BUILTIN_MADDACCS: | |
9175 | case FRV_BUILTIN_MSUBACCS: | |
9176 | case FRV_BUILTIN_MASACCS: | |
9177 | case FRV_BUILTIN_MDADDACCS: | |
9178 | case FRV_BUILTIN_MDSUBACCS: | |
9179 | case FRV_BUILTIN_MDASACCS: | |
9180 | case FRV_BUILTIN_MABSHS: | |
9181 | case FRV_BUILTIN_MDROTLI: | |
9182 | case FRV_BUILTIN_MCPLHI: | |
9183 | case FRV_BUILTIN_MCPLI: | |
9184 | case FRV_BUILTIN_MDCUTSSI: | |
9185 | case FRV_BUILTIN_MQSATHS: | |
9186 | case FRV_BUILTIN_MHSETLOS: | |
9187 | case FRV_BUILTIN_MHSETLOH: | |
9188 | case FRV_BUILTIN_MHSETHIS: | |
9189 | case FRV_BUILTIN_MHSETHIH: | |
9190 | case FRV_BUILTIN_MHDSETS: | |
9191 | case FRV_BUILTIN_MHDSETH: | |
9192 | if (! TARGET_MEDIA_REV2) | |
9193 | { | |
c557edf4 RS |
9194 | error ("this media function is only available on the fr400" |
9195 | " and fr550"); | |
9196 | return NULL_RTX; | |
9197 | } | |
9198 | break; | |
9199 | ||
9200 | case FRV_BUILTIN_SMASS: | |
9201 | case FRV_BUILTIN_SMSSS: | |
9202 | case FRV_BUILTIN_SMU: | |
9203 | case FRV_BUILTIN_ADDSS: | |
9204 | case FRV_BUILTIN_SUBSS: | |
9205 | case FRV_BUILTIN_SLASS: | |
9206 | case FRV_BUILTIN_SCUTSS: | |
9207 | case FRV_BUILTIN_IACCreadll: | |
9208 | case FRV_BUILTIN_IACCreadl: | |
9209 | case FRV_BUILTIN_IACCsetll: | |
9210 | case FRV_BUILTIN_IACCsetl: | |
9211 | if (!TARGET_FR405_BUILTINS) | |
9212 | { | |
9213 | error ("this builtin function is only available" | |
9214 | " on the fr405 and fr450"); | |
9215 | return NULL_RTX; | |
9216 | } | |
9217 | break; | |
9218 | ||
9219 | case FRV_BUILTIN_PREFETCH: | |
9220 | if (!TARGET_FR500_FR550_BUILTINS) | |
9221 | { | |
9222 | error ("this builtin function is only available on the fr500" | |
9223 | " and fr550"); | |
9224 | return NULL_RTX; | |
9225 | } | |
9226 | break; | |
9227 | ||
9228 | case FRV_BUILTIN_MQLCLRHS: | |
9229 | case FRV_BUILTIN_MQLMTHS: | |
9230 | case FRV_BUILTIN_MQSLLHI: | |
9231 | case FRV_BUILTIN_MQSRAHI: | |
9232 | if (!TARGET_MEDIA_FR450) | |
9233 | { | |
9234 | error ("this builtin function is only available on the fr450"); | |
36a05131 BS |
9235 | return NULL_RTX; |
9236 | } | |
9237 | break; | |
9238 | ||
9239 | default: | |
9240 | break; | |
9241 | } | |
9242 | ||
87b483a1 | 9243 | /* Expand unique builtins. */ |
36a05131 BS |
9244 | |
9245 | switch (fcode) | |
9246 | { | |
9247 | case FRV_BUILTIN_MTRAP: | |
9248 | return frv_expand_noargs_builtin (CODE_FOR_mtrap); | |
9249 | ||
9250 | case FRV_BUILTIN_MCLRACC: | |
2396bce1 | 9251 | return frv_expand_mclracc_builtin (exp); |
36a05131 BS |
9252 | |
9253 | case FRV_BUILTIN_MCLRACCA: | |
9254 | if (TARGET_ACC_8) | |
9255 | return frv_expand_noargs_builtin (CODE_FOR_mclracca8); | |
9256 | else | |
9257 | return frv_expand_noargs_builtin (CODE_FOR_mclracca4); | |
9258 | ||
9259 | case FRV_BUILTIN_MRDACC: | |
2396bce1 | 9260 | return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, exp); |
36a05131 BS |
9261 | |
9262 | case FRV_BUILTIN_MRDACCG: | |
2396bce1 | 9263 | return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, exp); |
36a05131 BS |
9264 | |
9265 | case FRV_BUILTIN_MWTACC: | |
2396bce1 | 9266 | return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, exp); |
36a05131 BS |
9267 | |
9268 | case FRV_BUILTIN_MWTACCG: | |
2396bce1 | 9269 | return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, exp); |
36a05131 | 9270 | |
a738d848 | 9271 | case FRV_BUILTIN_MDPACKH: |
2396bce1 | 9272 | return frv_expand_mdpackh_builtin (exp, target); |
a738d848 | 9273 | |
c557edf4 RS |
9274 | case FRV_BUILTIN_IACCreadll: |
9275 | { | |
2396bce1 | 9276 | rtx src = frv_read_iacc_argument (DImode, exp, 0); |
c557edf4 RS |
9277 | if (target == 0 || !REG_P (target)) |
9278 | target = gen_reg_rtx (DImode); | |
9279 | frv_split_iacc_move (target, src); | |
9280 | return target; | |
9281 | } | |
9282 | ||
9283 | case FRV_BUILTIN_IACCreadl: | |
2396bce1 | 9284 | return frv_read_iacc_argument (SImode, exp, 0); |
c557edf4 RS |
9285 | |
9286 | case FRV_BUILTIN_IACCsetll: | |
9287 | { | |
2396bce1 EC |
9288 | rtx dest = frv_read_iacc_argument (DImode, exp, 0); |
9289 | rtx src = frv_read_argument (exp, 1); | |
c557edf4 RS |
9290 | frv_split_iacc_move (dest, force_reg (DImode, src)); |
9291 | return 0; | |
9292 | } | |
9293 | ||
9294 | case FRV_BUILTIN_IACCsetl: | |
9295 | { | |
2396bce1 EC |
9296 | rtx dest = frv_read_iacc_argument (SImode, exp, 0); |
9297 | rtx src = frv_read_argument (exp, 1); | |
c557edf4 RS |
9298 | emit_move_insn (dest, force_reg (SImode, src)); |
9299 | return 0; | |
9300 | } | |
9301 | ||
36a05131 BS |
9302 | default: |
9303 | break; | |
9304 | } | |
9305 | ||
87b483a1 | 9306 | /* Expand groups of builtins. */ |
36a05131 | 9307 | |
e97a46ce | 9308 | for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++) |
36a05131 | 9309 | if (d->code == fcode) |
2396bce1 | 9310 | return frv_expand_set_builtin (d->icode, exp, target); |
36a05131 | 9311 | |
e97a46ce | 9312 | for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
36a05131 | 9313 | if (d->code == fcode) |
2396bce1 | 9314 | return frv_expand_unop_builtin (d->icode, exp, target); |
36a05131 | 9315 | |
e97a46ce | 9316 | for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
36a05131 | 9317 | if (d->code == fcode) |
2396bce1 | 9318 | return frv_expand_binop_builtin (d->icode, exp, target); |
36a05131 | 9319 | |
e97a46ce | 9320 | for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++) |
36a05131 | 9321 | if (d->code == fcode) |
2396bce1 | 9322 | return frv_expand_cut_builtin (d->icode, exp, target); |
36a05131 | 9323 | |
e97a46ce KG |
9324 | for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++) |
9325 | if (d->code == fcode) | |
2396bce1 | 9326 | return frv_expand_binopimm_builtin (d->icode, exp, target); |
36a05131 | 9327 | |
e97a46ce KG |
9328 | for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++) |
9329 | if (d->code == fcode) | |
2396bce1 | 9330 | return frv_expand_voidbinop_builtin (d->icode, exp); |
36a05131 | 9331 | |
e97a46ce KG |
9332 | for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++) |
9333 | if (d->code == fcode) | |
2396bce1 | 9334 | return frv_expand_voidtriop_builtin (d->icode, exp); |
e97a46ce KG |
9335 | |
9336 | for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++) | |
9337 | if (d->code == fcode) | |
2396bce1 | 9338 | return frv_expand_voidaccop_builtin (d->icode, exp); |
36a05131 | 9339 | |
c557edf4 RS |
9340 | for (i = 0, d = bdesc_int_void2arg; |
9341 | i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++) | |
9342 | if (d->code == fcode) | |
2396bce1 | 9343 | return frv_expand_int_void2arg (d->icode, exp); |
c557edf4 RS |
9344 | |
9345 | for (i = 0, d = bdesc_prefetches; | |
9346 | i < ARRAY_SIZE (bdesc_prefetches); i++, d++) | |
9347 | if (d->code == fcode) | |
2396bce1 | 9348 | return frv_expand_prefetches (d->icode, exp); |
c557edf4 | 9349 | |
c14ff86e AH |
9350 | for (i = 0, d = bdesc_loads; i < ARRAY_SIZE (bdesc_loads); i++, d++) |
9351 | if (d->code == fcode) | |
38c28a25 | 9352 | return frv_expand_load_builtin (d->icode, TYPE_MODE (TREE_TYPE (exp)), |
2396bce1 | 9353 | exp, target); |
c14ff86e AH |
9354 | |
9355 | for (i = 0, d = bdesc_stores; i < ARRAY_SIZE (bdesc_stores); i++, d++) | |
9356 | if (d->code == fcode) | |
2396bce1 | 9357 | return frv_expand_store_builtin (d->icode, exp); |
c14ff86e | 9358 | |
36a05131 BS |
9359 | return 0; |
9360 | } | |
14966b94 | 9361 | |
b3fbfc07 | 9362 | static bool |
3101faab | 9363 | frv_in_small_data_p (const_tree decl) |
b3fbfc07 | 9364 | { |
0f6e5d45 | 9365 | HOST_WIDE_INT size; |
f961457f | 9366 | const char *section_name; |
0f6e5d45 RH |
9367 | |
9368 | /* Don't apply the -G flag to internal compiler structures. We | |
9369 | should leave such structures in the main data section, partly | |
9370 | for efficiency and partly because the size of some of them | |
9371 | (such as C++ typeinfos) is not known until later. */ | |
9372 | if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl)) | |
9373 | return false; | |
9374 | ||
0f6e5d45 RH |
9375 | /* If we already know which section the decl should be in, see if |
9376 | it's a small data section. */ | |
9377 | section_name = DECL_SECTION_NAME (decl); | |
9378 | if (section_name) | |
9379 | { | |
0f6e5d45 RH |
9380 | if (frv_string_begins_with (section_name, ".sdata")) |
9381 | return true; | |
9382 | if (frv_string_begins_with (section_name, ".sbss")) | |
9383 | return true; | |
68c0ab4f | 9384 | return false; |
0f6e5d45 | 9385 | } |
b3fbfc07 | 9386 | |
68c0ab4f | 9387 | size = int_size_in_bytes (TREE_TYPE (decl)); |
fa37ed29 | 9388 | if (size > 0 && size <= g_switch_value) |
68c0ab4f RS |
9389 | return true; |
9390 | ||
0f6e5d45 | 9391 | return false; |
b3fbfc07 | 9392 | } |
3c50106f RH |
9393 | \f |
9394 | static bool | |
f2206911 | 9395 | frv_rtx_costs (rtx x, |
e548c9df AM |
9396 | machine_mode mode, |
9397 | int outer_code, | |
68f932c4 | 9398 | int opno ATTRIBUTE_UNUSED, |
f40751dd JH |
9399 | int *total, |
9400 | bool speed ATTRIBUTE_UNUSED) | |
3c50106f | 9401 | { |
e548c9df AM |
9402 | int code = GET_CODE (x); |
9403 | ||
34208acf AO |
9404 | if (outer_code == MEM) |
9405 | { | |
9406 | /* Don't differentiate between memory addresses. All the ones | |
9407 | we accept have equal cost. */ | |
9408 | *total = COSTS_N_INSNS (0); | |
9409 | return true; | |
9410 | } | |
9411 | ||
3c50106f RH |
9412 | switch (code) |
9413 | { | |
9414 | case CONST_INT: | |
2300b9dd | 9415 | /* Make 12-bit integers really cheap. */ |
2f5b1308 | 9416 | if (IN_RANGE (INTVAL (x), -2048, 2047)) |
3c50106f RH |
9417 | { |
9418 | *total = 0; | |
9419 | return true; | |
9420 | } | |
87b483a1 | 9421 | /* Fall through. */ |
3c50106f RH |
9422 | |
9423 | case CONST: | |
9424 | case LABEL_REF: | |
9425 | case SYMBOL_REF: | |
9426 | case CONST_DOUBLE: | |
9427 | *total = COSTS_N_INSNS (2); | |
9428 | return true; | |
9429 | ||
9430 | case PLUS: | |
9431 | case MINUS: | |
9432 | case AND: | |
9433 | case IOR: | |
9434 | case XOR: | |
9435 | case ASHIFT: | |
9436 | case ASHIFTRT: | |
9437 | case LSHIFTRT: | |
9438 | case NOT: | |
9439 | case NEG: | |
9440 | case COMPARE: | |
e548c9df | 9441 | if (mode == SImode) |
3c50106f | 9442 | *total = COSTS_N_INSNS (1); |
e548c9df | 9443 | else if (mode == DImode) |
3c50106f RH |
9444 | *total = COSTS_N_INSNS (2); |
9445 | else | |
9446 | *total = COSTS_N_INSNS (3); | |
9447 | return true; | |
9448 | ||
9449 | case MULT: | |
e548c9df | 9450 | if (mode == SImode) |
3c50106f RH |
9451 | *total = COSTS_N_INSNS (2); |
9452 | else | |
9453 | *total = COSTS_N_INSNS (6); /* guess */ | |
9454 | return true; | |
9455 | ||
9456 | case DIV: | |
9457 | case UDIV: | |
9458 | case MOD: | |
9459 | case UMOD: | |
9460 | *total = COSTS_N_INSNS (18); | |
9461 | return true; | |
9462 | ||
34208acf AO |
9463 | case MEM: |
9464 | *total = COSTS_N_INSNS (3); | |
9465 | return true; | |
9466 | ||
3c50106f RH |
9467 | default: |
9468 | return false; | |
9469 | } | |
9470 | } | |
90a63880 RH |
9471 | \f |
9472 | static void | |
f2206911 | 9473 | frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED) |
90a63880 | 9474 | { |
d6b5193b | 9475 | switch_to_section (ctors_section); |
90a63880 | 9476 | assemble_align (POINTER_SIZE); |
34208acf AO |
9477 | if (TARGET_FDPIC) |
9478 | { | |
44e91694 NS |
9479 | int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1); |
9480 | ||
9481 | gcc_assert (ok); | |
34208acf AO |
9482 | return; |
9483 | } | |
90a63880 RH |
9484 | assemble_integer_with_op ("\t.picptr\t", symbol); |
9485 | } | |
9486 | ||
9487 | static void | |
f2206911 | 9488 | frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED) |
90a63880 | 9489 | { |
d6b5193b | 9490 | switch_to_section (dtors_section); |
90a63880 | 9491 | assemble_align (POINTER_SIZE); |
34208acf AO |
9492 | if (TARGET_FDPIC) |
9493 | { | |
44e91694 | 9494 | int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1); |
2396bce1 | 9495 | |
44e91694 | 9496 | gcc_assert (ok); |
34208acf AO |
9497 | return; |
9498 | } | |
90a63880 RH |
9499 | assemble_integer_with_op ("\t.picptr\t", symbol); |
9500 | } | |
8ac411c7 KH |
9501 | |
9502 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ | |
9503 | ||
9504 | static rtx | |
9505 | frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
9506 | int incoming ATTRIBUTE_UNUSED) | |
9507 | { | |
9508 | return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM); | |
9509 | } | |
c557edf4 | 9510 | |
bef8809e AH |
9511 | #define TLS_BIAS (2048 - 16) |
9512 | ||
fdbe66f2 | 9513 | /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. |
bef8809e AH |
9514 | We need to emit DTP-relative relocations. */ |
9515 | ||
fdbe66f2 | 9516 | static void |
bef8809e AH |
9517 | frv_output_dwarf_dtprel (FILE *file, int size, rtx x) |
9518 | { | |
44e91694 | 9519 | gcc_assert (size == 4); |
bef8809e AH |
9520 | fputs ("\t.picptr\ttlsmoff(", file); |
9521 | /* We want the unbiased TLS offset, so add the bias to the | |
9522 | expression, such that the implicit biasing cancels out. */ | |
0a81f074 | 9523 | output_addr_const (file, plus_constant (Pmode, x, TLS_BIAS)); |
bef8809e AH |
9524 | fputs (")", file); |
9525 | } | |
9526 | ||
c557edf4 | 9527 | #include "gt-frv.h" |