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66647d44 | 1 | /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007, |
a87cf97e | 2 | 2008, 2009, 2010 Free Software Foundation, Inc. |
36a05131 BS |
3 | Contributed by Red Hat, Inc. |
4 | ||
7ec022b2 | 5 | This file is part of GCC. |
36a05131 | 6 | |
7ec022b2 | 7 | GCC is free software; you can redistribute it and/or modify |
36a05131 | 8 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 9 | the Free Software Foundation; either version 3, or (at your option) |
36a05131 BS |
10 | any later version. |
11 | ||
7ec022b2 | 12 | GCC is distributed in the hope that it will be useful, |
36a05131 BS |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
36a05131 BS |
20 | |
21 | #include "config.h" | |
22 | #include "system.h" | |
4977bab6 ZW |
23 | #include "coretypes.h" |
24 | #include "tm.h" | |
36a05131 BS |
25 | #include "rtl.h" |
26 | #include "tree.h" | |
27 | #include "regs.h" | |
28 | #include "hard-reg-set.h" | |
36a05131 BS |
29 | #include "insn-config.h" |
30 | #include "conditions.h" | |
31 | #include "insn-flags.h" | |
32 | #include "output.h" | |
33 | #include "insn-attr.h" | |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
36 | #include "reload.h" | |
37 | #include "expr.h" | |
38 | #include "obstack.h" | |
39 | #include "except.h" | |
40 | #include "function.h" | |
41 | #include "optabs.h" | |
718f9c0f | 42 | #include "diagnostic-core.h" |
36a05131 BS |
43 | #include "toplev.h" |
44 | #include "basic-block.h" | |
45 | #include "tm_p.h" | |
46 | #include "ggc.h" | |
47 | #include <ctype.h> | |
48 | #include "target.h" | |
49 | #include "target-def.h" | |
8cd5a4e0 | 50 | #include "targhooks.h" |
34208acf | 51 | #include "integrate.h" |
6e34d3a3 | 52 | #include "langhooks.h" |
6fb5fa3c | 53 | #include "df.h" |
36a05131 BS |
54 | |
55 | #ifndef FRV_INLINE | |
56 | #define FRV_INLINE inline | |
57 | #endif | |
58 | ||
c557edf4 RS |
59 | /* The maximum number of distinct NOP patterns. There are three: |
60 | nop, fnop and mnop. */ | |
61 | #define NUM_NOP_PATTERNS 3 | |
62 | ||
63 | /* Classification of instructions and units: integer, floating-point/media, | |
64 | branch and control. */ | |
65 | enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS }; | |
66 | ||
67 | /* The DFA names of the units, in packet order. */ | |
68 | static const char *const frv_unit_names[] = | |
69 | { | |
70 | "c", | |
71 | "i0", "f0", | |
72 | "i1", "f1", | |
73 | "i2", "f2", | |
74 | "i3", "f3", | |
75 | "b0", "b1" | |
76 | }; | |
77 | ||
78 | /* The classification of each unit in frv_unit_names[]. */ | |
79 | static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] = | |
80 | { | |
81 | GROUP_C, | |
82 | GROUP_I, GROUP_FM, | |
83 | GROUP_I, GROUP_FM, | |
84 | GROUP_I, GROUP_FM, | |
85 | GROUP_I, GROUP_FM, | |
86 | GROUP_B, GROUP_B | |
87 | }; | |
88 | ||
89 | /* Return the DFA unit code associated with the Nth unit of integer | |
90 | or floating-point group GROUP, */ | |
91 | #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1] | |
92 | ||
93 | /* Return the number of integer or floating-point unit UNIT | |
94 | (1 for I1, 2 for F2, etc.). */ | |
95 | #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2) | |
96 | ||
97 | /* The DFA unit number for each unit in frv_unit_names[]. */ | |
98 | static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)]; | |
99 | ||
100 | /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue | |
101 | an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if | |
102 | no instruction of type T has been seen. */ | |
103 | static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1]; | |
104 | ||
105 | /* An array of dummy nop INSNs, one for each type of nop that the | |
106 | target supports. */ | |
107 | static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS]; | |
108 | ||
109 | /* The number of nop instructions in frv_nops[]. */ | |
110 | static unsigned int frv_num_nops; | |
111 | ||
38c28a25 AH |
112 | /* Information about one __builtin_read or __builtin_write access, or |
113 | the combination of several such accesses. The most general value | |
114 | is all-zeros (an unknown access to an unknown address). */ | |
115 | struct frv_io { | |
116 | /* The type of access. FRV_IO_UNKNOWN means the access can be either | |
117 | a read or a write. */ | |
118 | enum { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE } type; | |
119 | ||
120 | /* The constant address being accessed, or zero if not known. */ | |
121 | HOST_WIDE_INT const_address; | |
122 | ||
123 | /* The run-time address, as used in operand 0 of the membar pattern. */ | |
124 | rtx var_address; | |
125 | }; | |
126 | ||
c557edf4 RS |
127 | /* Return true if instruction INSN should be packed with the following |
128 | instruction. */ | |
129 | #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode) | |
130 | ||
131 | /* Set the value of PACKING_FLAG_P(INSN). */ | |
132 | #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode) | |
133 | #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode) | |
134 | ||
135 | /* Loop with REG set to each hard register in rtx X. */ | |
136 | #define FOR_EACH_REGNO(REG, X) \ | |
137 | for (REG = REGNO (X); \ | |
138 | REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \ | |
139 | REG++) | |
140 | ||
38c28a25 | 141 | /* This structure contains machine specific function data. */ |
d1b38208 | 142 | struct GTY(()) machine_function |
38c28a25 AH |
143 | { |
144 | /* True if we have created an rtx that relies on the stack frame. */ | |
145 | int frame_needed; | |
146 | ||
147 | /* True if this function contains at least one __builtin_{read,write}*. */ | |
148 | bool has_membar_p; | |
149 | }; | |
150 | ||
36a05131 BS |
151 | /* Temporary register allocation support structure. */ |
152 | typedef struct frv_tmp_reg_struct | |
153 | { | |
154 | HARD_REG_SET regs; /* possible registers to allocate */ | |
155 | int next_reg[N_REG_CLASSES]; /* next register to allocate per class */ | |
156 | } | |
157 | frv_tmp_reg_t; | |
158 | ||
c557edf4 | 159 | /* Register state information for VLIW re-packing phase. */ |
36a05131 | 160 | #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */ |
c557edf4 RS |
161 | #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */ |
162 | #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */ | |
163 | #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */ | |
164 | ||
36a05131 BS |
165 | #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE) |
166 | ||
c557edf4 | 167 | typedef unsigned char regstate_t; |
36a05131 BS |
168 | |
169 | /* Used in frv_frame_accessor_t to indicate the direction of a register-to- | |
170 | memory move. */ | |
171 | enum frv_stack_op | |
172 | { | |
173 | FRV_LOAD, | |
174 | FRV_STORE | |
175 | }; | |
176 | ||
177 | /* Information required by frv_frame_access. */ | |
178 | typedef struct | |
179 | { | |
180 | /* This field is FRV_LOAD if registers are to be loaded from the stack and | |
181 | FRV_STORE if they should be stored onto the stack. FRV_STORE implies | |
182 | the move is being done by the prologue code while FRV_LOAD implies it | |
183 | is being done by the epilogue. */ | |
184 | enum frv_stack_op op; | |
185 | ||
186 | /* The base register to use when accessing the stack. This may be the | |
187 | frame pointer, stack pointer, or a temporary. The choice of register | |
188 | depends on which part of the frame is being accessed and how big the | |
189 | frame is. */ | |
190 | rtx base; | |
191 | ||
192 | /* The offset of BASE from the bottom of the current frame, in bytes. */ | |
193 | int base_offset; | |
194 | } frv_frame_accessor_t; | |
195 | ||
87b483a1 | 196 | /* Conditional execution support gathered together in one structure. */ |
36a05131 BS |
197 | typedef struct |
198 | { | |
199 | /* Linked list of insns to add if the conditional execution conversion was | |
200 | successful. Each link points to an EXPR_LIST which points to the pattern | |
201 | of the insn to add, and the insn to be inserted before. */ | |
202 | rtx added_insns_list; | |
203 | ||
204 | /* Identify which registers are safe to allocate for if conversions to | |
205 | conditional execution. We keep the last allocated register in the | |
206 | register classes between COND_EXEC statements. This will mean we allocate | |
207 | different registers for each different COND_EXEC group if we can. This | |
208 | might allow the scheduler to intermix two different COND_EXEC sections. */ | |
209 | frv_tmp_reg_t tmp_reg; | |
210 | ||
211 | /* For nested IFs, identify which CC registers are used outside of setting | |
212 | via a compare isnsn, and using via a check insn. This will allow us to | |
213 | know if we can rewrite the register to use a different register that will | |
214 | be paired with the CR register controlling the nested IF-THEN blocks. */ | |
215 | HARD_REG_SET nested_cc_ok_rewrite; | |
216 | ||
217 | /* Temporary registers allocated to hold constants during conditional | |
218 | execution. */ | |
219 | rtx scratch_regs[FIRST_PSEUDO_REGISTER]; | |
220 | ||
221 | /* Current number of temp registers available. */ | |
222 | int cur_scratch_regs; | |
223 | ||
87b483a1 | 224 | /* Number of nested conditional execution blocks. */ |
36a05131 BS |
225 | int num_nested_cond_exec; |
226 | ||
227 | /* Map of insns that set up constants in scratch registers. */ | |
228 | bitmap scratch_insns_bitmap; | |
229 | ||
87b483a1 | 230 | /* Conditional execution test register (CC0..CC7). */ |
36a05131 BS |
231 | rtx cr_reg; |
232 | ||
233 | /* Conditional execution compare register that is paired with cr_reg, so that | |
234 | nested compares can be done. The csubcc and caddcc instructions don't | |
235 | have enough bits to specify both a CC register to be set and a CR register | |
236 | to do the test on, so the same bit number is used for both. Needless to | |
839a4992 | 237 | say, this is rather inconvenient for GCC. */ |
36a05131 BS |
238 | rtx nested_cc_reg; |
239 | ||
240 | /* Extra CR registers used for &&, ||. */ | |
241 | rtx extra_int_cr; | |
242 | rtx extra_fp_cr; | |
243 | ||
244 | /* Previous CR used in nested if, to make sure we are dealing with the same | |
87b483a1 | 245 | nested if as the previous statement. */ |
36a05131 BS |
246 | rtx last_nested_if_cr; |
247 | } | |
248 | frv_ifcvt_t; | |
249 | ||
250 | static /* GTY(()) */ frv_ifcvt_t frv_ifcvt; | |
251 | ||
252 | /* Map register number to smallest register class. */ | |
253 | enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; | |
254 | ||
87b483a1 | 255 | /* Map class letter into register class. */ |
36a05131 BS |
256 | enum reg_class reg_class_from_letter[256]; |
257 | ||
87b483a1 | 258 | /* Cached value of frv_stack_info. */ |
36a05131 BS |
259 | static frv_stack_t *frv_stack_cache = (frv_stack_t *)0; |
260 | ||
36a05131 | 261 | /* -mcpu= support */ |
36a05131 BS |
262 | frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */ |
263 | ||
36a05131 | 264 | /* Forward references */ |
0b2c18fe RS |
265 | |
266 | static bool frv_handle_option (size_t, const char *, int); | |
c5387660 | 267 | static void frv_option_override (void); |
c6c3dba9 | 268 | static bool frv_legitimate_address_p (enum machine_mode, rtx, bool); |
f2206911 | 269 | static int frv_default_flags_for_cpu (void); |
3101faab | 270 | static int frv_string_begins_with (const_tree, const char *); |
34208acf | 271 | static FRV_INLINE bool frv_small_data_reloc_p (rtx, int); |
0fb30cb7 NF |
272 | static void frv_print_operand (FILE *, rtx, int); |
273 | static void frv_print_operand_address (FILE *, rtx); | |
274 | static bool frv_print_operand_punct_valid_p (unsigned char code); | |
36a05131 | 275 | static void frv_print_operand_memory_reference_reg |
f2206911 KC |
276 | (FILE *, rtx); |
277 | static void frv_print_operand_memory_reference (FILE *, rtx, int); | |
278 | static int frv_print_operand_jump_hint (rtx); | |
036ff63f | 279 | static const char *comparison_string (enum rtx_code, rtx); |
219d92a4 AS |
280 | static rtx frv_function_value (const_tree, const_tree, |
281 | bool); | |
282 | static rtx frv_libcall_value (enum machine_mode, | |
283 | const_rtx); | |
f2206911 KC |
284 | static FRV_INLINE int frv_regno_ok_for_base_p (int, int); |
285 | static rtx single_set_pattern (rtx); | |
286 | static int frv_function_contains_far_jump (void); | |
287 | static rtx frv_alloc_temp_reg (frv_tmp_reg_t *, | |
288 | enum reg_class, | |
289 | enum machine_mode, | |
290 | int, int); | |
291 | static rtx frv_frame_offset_rtx (int); | |
292 | static rtx frv_frame_mem (enum machine_mode, rtx, int); | |
293 | static rtx frv_dwarf_store (rtx, int); | |
294 | static void frv_frame_insn (rtx, rtx); | |
295 | static void frv_frame_access (frv_frame_accessor_t*, | |
296 | rtx, int); | |
297 | static void frv_frame_access_multi (frv_frame_accessor_t*, | |
298 | frv_stack_t *, int); | |
299 | static void frv_frame_access_standard_regs (enum frv_stack_op, | |
300 | frv_stack_t *); | |
301 | static struct machine_function *frv_init_machine_status (void); | |
f2206911 KC |
302 | static rtx frv_int_to_acc (enum insn_code, int, rtx); |
303 | static enum machine_mode frv_matching_accg_mode (enum machine_mode); | |
2396bce1 EC |
304 | static rtx frv_read_argument (tree, unsigned int); |
305 | static rtx frv_read_iacc_argument (enum machine_mode, tree, unsigned int); | |
f2206911 KC |
306 | static int frv_check_constant_argument (enum insn_code, int, rtx); |
307 | static rtx frv_legitimize_target (enum insn_code, rtx); | |
308 | static rtx frv_legitimize_argument (enum insn_code, int, rtx); | |
bef8809e | 309 | static rtx frv_legitimize_tls_address (rtx, enum tls_model); |
506d7b68 | 310 | static rtx frv_legitimize_address (rtx, rtx, enum machine_mode); |
f2206911 KC |
311 | static rtx frv_expand_set_builtin (enum insn_code, tree, rtx); |
312 | static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx); | |
313 | static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx); | |
314 | static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx); | |
315 | static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx); | |
316 | static rtx frv_expand_voidbinop_builtin (enum insn_code, tree); | |
c557edf4 RS |
317 | static rtx frv_expand_int_void2arg (enum insn_code, tree); |
318 | static rtx frv_expand_prefetches (enum insn_code, tree); | |
f2206911 KC |
319 | static rtx frv_expand_voidtriop_builtin (enum insn_code, tree); |
320 | static rtx frv_expand_voidaccop_builtin (enum insn_code, tree); | |
321 | static rtx frv_expand_mclracc_builtin (tree); | |
322 | static rtx frv_expand_mrdacc_builtin (enum insn_code, tree); | |
323 | static rtx frv_expand_mwtacc_builtin (enum insn_code, tree); | |
324 | static rtx frv_expand_noargs_builtin (enum insn_code); | |
c557edf4 | 325 | static void frv_split_iacc_move (rtx, rtx); |
f2206911 KC |
326 | static rtx frv_emit_comparison (enum rtx_code, rtx, rtx); |
327 | static int frv_clear_registers_used (rtx *, void *); | |
328 | static void frv_ifcvt_add_insn (rtx, rtx, int); | |
329 | static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx); | |
330 | static rtx frv_ifcvt_load_value (rtx, rtx); | |
c557edf4 RS |
331 | static int frv_acc_group_1 (rtx *, void *); |
332 | static unsigned int frv_insn_unit (rtx); | |
333 | static bool frv_issues_to_branch_unit_p (rtx); | |
334 | static int frv_cond_flags (rtx); | |
335 | static bool frv_regstate_conflict_p (regstate_t, regstate_t); | |
336 | static int frv_registers_conflict_p_1 (rtx *, void *); | |
337 | static bool frv_registers_conflict_p (rtx); | |
7bc980e1 | 338 | static void frv_registers_update_1 (rtx, const_rtx, void *); |
c557edf4 RS |
339 | static void frv_registers_update (rtx); |
340 | static void frv_start_packet (void); | |
341 | static void frv_start_packet_block (void); | |
342 | static void frv_finish_packet (void (*) (void)); | |
343 | static bool frv_pack_insn_p (rtx); | |
344 | static void frv_add_insn_to_packet (rtx); | |
345 | static void frv_insert_nop_in_packet (rtx); | |
346 | static bool frv_for_each_packet (void (*) (void)); | |
347 | static bool frv_sort_insn_group_1 (enum frv_insn_group, | |
348 | unsigned int, unsigned int, | |
349 | unsigned int, unsigned int, | |
350 | state_t); | |
351 | static int frv_compare_insns (const void *, const void *); | |
352 | static void frv_sort_insn_group (enum frv_insn_group); | |
353 | static void frv_reorder_packet (void); | |
354 | static void frv_fill_unused_units (enum frv_insn_group); | |
355 | static void frv_align_label (void); | |
356 | static void frv_reorg_packet (void); | |
357 | static void frv_register_nop (rtx); | |
358 | static void frv_reorg (void); | |
f2206911 KC |
359 | static void frv_pack_insns (void); |
360 | static void frv_function_prologue (FILE *, HOST_WIDE_INT); | |
361 | static void frv_function_epilogue (FILE *, HOST_WIDE_INT); | |
362 | static bool frv_assemble_integer (rtx, unsigned, int); | |
363 | static void frv_init_builtins (void); | |
364 | static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
365 | static void frv_init_libfuncs (void); | |
3101faab | 366 | static bool frv_in_small_data_p (const_tree); |
3961e8fe | 367 | static void frv_asm_output_mi_thunk |
f2206911 | 368 | (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree); |
d8c2bed3 KH |
369 | static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *, |
370 | enum machine_mode, | |
371 | tree, int *, int); | |
8ac411c7 | 372 | static rtx frv_expand_builtin_saveregs (void); |
d7bd8aeb | 373 | static void frv_expand_builtin_va_start (tree, rtx); |
899cc0f4 | 374 | static bool frv_rtx_costs (rtx, int, int, int*, bool); |
33124e84 AS |
375 | static int frv_register_move_cost (enum machine_mode, |
376 | reg_class_t, reg_class_t); | |
377 | static int frv_memory_move_cost (enum machine_mode, | |
378 | reg_class_t, bool); | |
f2206911 KC |
379 | static void frv_asm_out_constructor (rtx, int); |
380 | static void frv_asm_out_destructor (rtx, int); | |
34208acf AO |
381 | static bool frv_function_symbol_referenced_p (rtx); |
382 | static bool frv_cannot_force_const_mem (rtx); | |
383 | static const char *unspec_got_name (int); | |
384 | static void frv_output_const_unspec (FILE *, | |
385 | const struct frv_unspec *); | |
764678d1 | 386 | static bool frv_function_ok_for_sibcall (tree, tree); |
8ac411c7 | 387 | static rtx frv_struct_value_rtx (tree, int); |
586de218 | 388 | static bool frv_must_pass_in_stack (enum machine_mode mode, const_tree type); |
78a52f11 RH |
389 | static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
390 | tree, bool); | |
88a1f47f NF |
391 | static rtx frv_function_arg (CUMULATIVE_ARGS *, enum machine_mode, |
392 | const_tree, bool); | |
393 | static rtx frv_function_incoming_arg (CUMULATIVE_ARGS *, enum machine_mode, | |
394 | const_tree, bool); | |
395 | static void frv_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode, | |
396 | const_tree, bool); | |
fdbe66f2 EB |
397 | static void frv_output_dwarf_dtprel (FILE *, int, rtx) |
398 | ATTRIBUTE_UNUSED; | |
a87cf97e | 399 | static reg_class_t frv_secondary_reload (bool, rtx, reg_class_t, |
35f2d8ef NC |
400 | enum machine_mode, |
401 | secondary_reload_info *); | |
b52b1749 | 402 | static bool frv_frame_pointer_required (void); |
7b5cbb57 | 403 | static bool frv_can_eliminate (const int, const int); |
e9d5fdb2 | 404 | static void frv_trampoline_init (rtx, tree, rtx); |
c28350ab | 405 | static bool frv_class_likely_spilled_p (reg_class_t); |
3020190e JM |
406 | |
407 | /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ | |
408 | static const struct default_options frv_option_optimization_table[] = | |
409 | { | |
410 | { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, | |
411 | { OPT_LEVELS_NONE, 0, NULL, 0 } | |
412 | }; | |
36a05131 | 413 | \f |
0b2c18fe RS |
414 | /* Allow us to easily change the default for -malloc-cc. */ |
415 | #ifndef DEFAULT_NO_ALLOC_CC | |
416 | #define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC | |
417 | #else | |
418 | #define MASK_DEFAULT_ALLOC_CC 0 | |
419 | #endif | |
420 | \f | |
36a05131 | 421 | /* Initialize the GCC target structure. */ |
0fb30cb7 NF |
422 | #undef TARGET_PRINT_OPERAND |
423 | #define TARGET_PRINT_OPERAND frv_print_operand | |
424 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
425 | #define TARGET_PRINT_OPERAND_ADDRESS frv_print_operand_address | |
426 | #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P | |
427 | #define TARGET_PRINT_OPERAND_PUNCT_VALID_P frv_print_operand_punct_valid_p | |
36a05131 BS |
428 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
429 | #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue | |
430 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
431 | #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue | |
432 | #undef TARGET_ASM_INTEGER | |
433 | #define TARGET_ASM_INTEGER frv_assemble_integer | |
0b2c18fe RS |
434 | #undef TARGET_DEFAULT_TARGET_FLAGS |
435 | #define TARGET_DEFAULT_TARGET_FLAGS \ | |
436 | (MASK_DEFAULT_ALLOC_CC \ | |
437 | | MASK_COND_MOVE \ | |
438 | | MASK_SCC \ | |
439 | | MASK_COND_EXEC \ | |
440 | | MASK_VLIW_BRANCH \ | |
441 | | MASK_MULTI_CE \ | |
442 | | MASK_NESTED_CE) | |
443 | #undef TARGET_HANDLE_OPTION | |
444 | #define TARGET_HANDLE_OPTION frv_handle_option | |
c5387660 JM |
445 | #undef TARGET_OPTION_OVERRIDE |
446 | #define TARGET_OPTION_OVERRIDE frv_option_override | |
3020190e JM |
447 | #undef TARGET_OPTION_OPTIMIZATION_TABLE |
448 | #define TARGET_OPTION_OPTIMIZATION_TABLE frv_option_optimization_table | |
14966b94 KG |
449 | #undef TARGET_INIT_BUILTINS |
450 | #define TARGET_INIT_BUILTINS frv_init_builtins | |
451 | #undef TARGET_EXPAND_BUILTIN | |
452 | #define TARGET_EXPAND_BUILTIN frv_expand_builtin | |
c15c90bb ZW |
453 | #undef TARGET_INIT_LIBFUNCS |
454 | #define TARGET_INIT_LIBFUNCS frv_init_libfuncs | |
b3fbfc07 KG |
455 | #undef TARGET_IN_SMALL_DATA_P |
456 | #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p | |
33124e84 AS |
457 | #undef TARGET_REGISTER_MOVE_COST |
458 | #define TARGET_REGISTER_MOVE_COST frv_register_move_cost | |
459 | #undef TARGET_MEMORY_MOVE_COST | |
460 | #define TARGET_MEMORY_MOVE_COST frv_memory_move_cost | |
3c50106f RH |
461 | #undef TARGET_RTX_COSTS |
462 | #define TARGET_RTX_COSTS frv_rtx_costs | |
90a63880 RH |
463 | #undef TARGET_ASM_CONSTRUCTOR |
464 | #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor | |
465 | #undef TARGET_ASM_DESTRUCTOR | |
466 | #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor | |
36a05131 | 467 | |
c590b625 RH |
468 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
469 | #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk | |
3961e8fe RH |
470 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
471 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
c590b625 | 472 | |
28a60850 RS |
473 | #undef TARGET_SCHED_ISSUE_RATE |
474 | #define TARGET_SCHED_ISSUE_RATE frv_issue_rate | |
ffb344c1 | 475 | |
506d7b68 PB |
476 | #undef TARGET_LEGITIMIZE_ADDRESS |
477 | #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address | |
478 | ||
764678d1 AO |
479 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
480 | #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall | |
34208acf AO |
481 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
482 | #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem | |
483 | ||
bef8809e AH |
484 | #undef TARGET_HAVE_TLS |
485 | #define TARGET_HAVE_TLS HAVE_AS_TLS | |
486 | ||
8ac411c7 KH |
487 | #undef TARGET_STRUCT_VALUE_RTX |
488 | #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx | |
fe984136 RH |
489 | #undef TARGET_MUST_PASS_IN_STACK |
490 | #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack | |
8cd5a4e0 RH |
491 | #undef TARGET_PASS_BY_REFERENCE |
492 | #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack | |
78a52f11 RH |
493 | #undef TARGET_ARG_PARTIAL_BYTES |
494 | #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes | |
88a1f47f NF |
495 | #undef TARGET_FUNCTION_ARG |
496 | #define TARGET_FUNCTION_ARG frv_function_arg | |
497 | #undef TARGET_FUNCTION_INCOMING_ARG | |
498 | #define TARGET_FUNCTION_INCOMING_ARG frv_function_incoming_arg | |
499 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
500 | #define TARGET_FUNCTION_ARG_ADVANCE frv_function_arg_advance | |
8ac411c7 KH |
501 | |
502 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
503 | #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs | |
d8c2bed3 KH |
504 | #undef TARGET_SETUP_INCOMING_VARARGS |
505 | #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs | |
c557edf4 RS |
506 | #undef TARGET_MACHINE_DEPENDENT_REORG |
507 | #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg | |
8ac411c7 | 508 | |
d7bd8aeb JJ |
509 | #undef TARGET_EXPAND_BUILTIN_VA_START |
510 | #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start | |
511 | ||
fdbe66f2 EB |
512 | #if HAVE_AS_TLS |
513 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
514 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel | |
515 | #endif | |
516 | ||
c28350ab AS |
517 | #undef TARGET_CLASS_LIKELY_SPILLED_P |
518 | #define TARGET_CLASS_LIKELY_SPILLED_P frv_class_likely_spilled_p | |
519 | ||
35f2d8ef NC |
520 | #undef TARGET_SECONDARY_RELOAD |
521 | #define TARGET_SECONDARY_RELOAD frv_secondary_reload | |
522 | ||
c6c3dba9 PB |
523 | #undef TARGET_LEGITIMATE_ADDRESS_P |
524 | #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p | |
525 | ||
b52b1749 AS |
526 | #undef TARGET_FRAME_POINTER_REQUIRED |
527 | #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required | |
528 | ||
7b5cbb57 AS |
529 | #undef TARGET_CAN_ELIMINATE |
530 | #define TARGET_CAN_ELIMINATE frv_can_eliminate | |
531 | ||
e9d5fdb2 RH |
532 | #undef TARGET_TRAMPOLINE_INIT |
533 | #define TARGET_TRAMPOLINE_INIT frv_trampoline_init | |
534 | ||
219d92a4 AS |
535 | #undef TARGET_FUNCTION_VALUE |
536 | #define TARGET_FUNCTION_VALUE frv_function_value | |
537 | #undef TARGET_LIBCALL_VALUE | |
538 | #define TARGET_LIBCALL_VALUE frv_libcall_value | |
539 | ||
36a05131 | 540 | struct gcc_target targetm = TARGET_INITIALIZER; |
bef8809e AH |
541 | |
542 | #define FRV_SYMBOL_REF_TLS_P(RTX) \ | |
543 | (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) | |
544 | ||
36a05131 | 545 | \f |
764678d1 AO |
546 | /* Any function call that satisfies the machine-independent |
547 | requirements is eligible on FR-V. */ | |
548 | ||
549 | static bool | |
550 | frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED, | |
551 | tree exp ATTRIBUTE_UNUSED) | |
552 | { | |
553 | return true; | |
554 | } | |
555 | ||
34208acf AO |
556 | /* Return true if SYMBOL is a small data symbol and relocation RELOC |
557 | can be used to access it directly in a load or store. */ | |
36a05131 | 558 | |
34208acf AO |
559 | static FRV_INLINE bool |
560 | frv_small_data_reloc_p (rtx symbol, int reloc) | |
36a05131 | 561 | { |
34208acf AO |
562 | return (GET_CODE (symbol) == SYMBOL_REF |
563 | && SYMBOL_REF_SMALL_P (symbol) | |
564 | && (!TARGET_FDPIC || flag_pic == 1) | |
565 | && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12)); | |
566 | } | |
36a05131 | 567 | |
34208acf AO |
568 | /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC |
569 | appropriately. */ | |
36a05131 | 570 | |
6d26dc3b | 571 | bool |
34208acf AO |
572 | frv_const_unspec_p (rtx x, struct frv_unspec *unspec) |
573 | { | |
574 | if (GET_CODE (x) == CONST) | |
575 | { | |
576 | unspec->offset = 0; | |
577 | x = XEXP (x, 0); | |
578 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
579 | { | |
580 | unspec->offset += INTVAL (XEXP (x, 1)); | |
581 | x = XEXP (x, 0); | |
582 | } | |
583 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT) | |
584 | { | |
585 | unspec->symbol = XVECEXP (x, 0, 0); | |
586 | unspec->reloc = INTVAL (XVECEXP (x, 0, 1)); | |
36a05131 | 587 | |
34208acf AO |
588 | if (unspec->offset == 0) |
589 | return true; | |
36a05131 | 590 | |
34208acf AO |
591 | if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc) |
592 | && unspec->offset > 0 | |
fa37ed29 | 593 | && unspec->offset < g_switch_value) |
34208acf AO |
594 | return true; |
595 | } | |
596 | } | |
597 | return false; | |
36a05131 BS |
598 | } |
599 | ||
34208acf AO |
600 | /* Decide whether we can force certain constants to memory. If we |
601 | decide we can't, the caller should be able to cope with it in | |
602 | another way. | |
36a05131 | 603 | |
34208acf AO |
604 | We never allow constants to be forced into memory for TARGET_FDPIC. |
605 | This is necessary for several reasons: | |
36a05131 | 606 | |
34208acf AO |
607 | 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the |
608 | target-independent code will try to force them into the constant | |
609 | pool, thus leading to infinite recursion. | |
36a05131 | 610 | |
34208acf AO |
611 | 2. We can never introduce new constant pool references during reload. |
612 | Any such reference would require use of the pseudo FDPIC register. | |
36a05131 | 613 | |
34208acf AO |
614 | 3. We can't represent a constant added to a function pointer (which is |
615 | not the same as a pointer to a function+constant). | |
616 | ||
617 | 4. In many cases, it's more efficient to calculate the constant in-line. */ | |
618 | ||
619 | static bool | |
620 | frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED) | |
621 | { | |
622 | return TARGET_FDPIC; | |
623 | } | |
36a05131 | 624 | \f |
0b2c18fe RS |
625 | /* Implement TARGET_HANDLE_OPTION. */ |
626 | ||
627 | static bool | |
34251c0e | 628 | frv_handle_option (size_t code, const char *arg, int value) |
0b2c18fe RS |
629 | { |
630 | switch (code) | |
631 | { | |
632 | case OPT_mcpu_: | |
633 | if (strcmp (arg, "simple") == 0) | |
634 | frv_cpu_type = FRV_CPU_SIMPLE; | |
635 | else if (strcmp (arg, "tomcat") == 0) | |
636 | frv_cpu_type = FRV_CPU_TOMCAT; | |
637 | else if (strcmp (arg, "fr550") == 0) | |
638 | frv_cpu_type = FRV_CPU_FR550; | |
639 | else if (strcmp (arg, "fr500") == 0) | |
640 | frv_cpu_type = FRV_CPU_FR500; | |
641 | else if (strcmp (arg, "fr450") == 0) | |
642 | frv_cpu_type = FRV_CPU_FR450; | |
643 | else if (strcmp (arg, "fr405") == 0) | |
644 | frv_cpu_type = FRV_CPU_FR405; | |
645 | else if (strcmp (arg, "fr400") == 0) | |
646 | frv_cpu_type = FRV_CPU_FR400; | |
647 | else if (strcmp (arg, "fr300") == 0) | |
648 | frv_cpu_type = FRV_CPU_FR300; | |
649 | else if (strcmp (arg, "frv") == 0) | |
650 | frv_cpu_type = FRV_CPU_GENERIC; | |
651 | else | |
652 | return false; | |
653 | return true; | |
654 | ||
655 | default: | |
656 | return true; | |
657 | } | |
658 | } | |
659 | ||
36a05131 | 660 | static int |
f2206911 | 661 | frv_default_flags_for_cpu (void) |
36a05131 BS |
662 | { |
663 | switch (frv_cpu_type) | |
664 | { | |
665 | case FRV_CPU_GENERIC: | |
666 | return MASK_DEFAULT_FRV; | |
667 | ||
c557edf4 RS |
668 | case FRV_CPU_FR550: |
669 | return MASK_DEFAULT_FR550; | |
670 | ||
36a05131 BS |
671 | case FRV_CPU_FR500: |
672 | case FRV_CPU_TOMCAT: | |
673 | return MASK_DEFAULT_FR500; | |
674 | ||
c557edf4 RS |
675 | case FRV_CPU_FR450: |
676 | return MASK_DEFAULT_FR450; | |
677 | ||
678 | case FRV_CPU_FR405: | |
36a05131 BS |
679 | case FRV_CPU_FR400: |
680 | return MASK_DEFAULT_FR400; | |
681 | ||
682 | case FRV_CPU_FR300: | |
683 | case FRV_CPU_SIMPLE: | |
684 | return MASK_DEFAULT_SIMPLE; | |
44e91694 NS |
685 | |
686 | default: | |
687 | gcc_unreachable (); | |
36a05131 | 688 | } |
36a05131 BS |
689 | } |
690 | ||
c5387660 | 691 | /* Implement TARGET_OPTION_OVERRIDE. */ |
36a05131 | 692 | |
c5387660 JM |
693 | static void |
694 | frv_option_override (void) | |
36a05131 | 695 | { |
c557edf4 RS |
696 | int regno; |
697 | unsigned int i; | |
36a05131 | 698 | |
36a05131 BS |
699 | target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit); |
700 | ||
701 | /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the | |
702 | linker about linking pic and non-pic code. */ | |
703 | if (TARGET_LIBPIC) | |
704 | { | |
705 | if (!flag_pic) /* -fPIC */ | |
706 | flag_pic = 2; | |
707 | ||
fa37ed29 | 708 | if (!global_options_set.x_g_switch_value) /* -G0 */ |
36a05131 | 709 | { |
36a05131 BS |
710 | g_switch_value = 0; |
711 | } | |
712 | } | |
713 | ||
36a05131 BS |
714 | /* A C expression whose value is a register class containing hard |
715 | register REGNO. In general there is more than one such class; | |
716 | choose a class which is "minimal", meaning that no smaller class | |
87b483a1 | 717 | also contains the register. */ |
36a05131 BS |
718 | |
719 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
720 | { | |
0a2aaacc | 721 | enum reg_class rclass; |
36a05131 BS |
722 | |
723 | if (GPR_P (regno)) | |
724 | { | |
725 | int gpr_reg = regno - GPR_FIRST; | |
bef8809e AH |
726 | |
727 | if (gpr_reg == GR8_REG) | |
0a2aaacc | 728 | rclass = GR8_REGS; |
bef8809e AH |
729 | |
730 | else if (gpr_reg == GR9_REG) | |
0a2aaacc | 731 | rclass = GR9_REGS; |
bef8809e AH |
732 | |
733 | else if (gpr_reg == GR14_REG) | |
0a2aaacc | 734 | rclass = FDPIC_FPTR_REGS; |
bef8809e AH |
735 | |
736 | else if (gpr_reg == FDPIC_REGNO) | |
0a2aaacc | 737 | rclass = FDPIC_REGS; |
bef8809e AH |
738 | |
739 | else if ((gpr_reg & 3) == 0) | |
0a2aaacc | 740 | rclass = QUAD_REGS; |
36a05131 BS |
741 | |
742 | else if ((gpr_reg & 1) == 0) | |
0a2aaacc | 743 | rclass = EVEN_REGS; |
36a05131 BS |
744 | |
745 | else | |
0a2aaacc | 746 | rclass = GPR_REGS; |
36a05131 BS |
747 | } |
748 | ||
749 | else if (FPR_P (regno)) | |
750 | { | |
751 | int fpr_reg = regno - GPR_FIRST; | |
752 | if ((fpr_reg & 3) == 0) | |
0a2aaacc | 753 | rclass = QUAD_FPR_REGS; |
36a05131 BS |
754 | |
755 | else if ((fpr_reg & 1) == 0) | |
0a2aaacc | 756 | rclass = FEVEN_REGS; |
36a05131 BS |
757 | |
758 | else | |
0a2aaacc | 759 | rclass = FPR_REGS; |
36a05131 BS |
760 | } |
761 | ||
762 | else if (regno == LR_REGNO) | |
0a2aaacc | 763 | rclass = LR_REG; |
36a05131 BS |
764 | |
765 | else if (regno == LCR_REGNO) | |
0a2aaacc | 766 | rclass = LCR_REG; |
36a05131 BS |
767 | |
768 | else if (ICC_P (regno)) | |
0a2aaacc | 769 | rclass = ICC_REGS; |
36a05131 BS |
770 | |
771 | else if (FCC_P (regno)) | |
0a2aaacc | 772 | rclass = FCC_REGS; |
36a05131 BS |
773 | |
774 | else if (ICR_P (regno)) | |
0a2aaacc | 775 | rclass = ICR_REGS; |
36a05131 BS |
776 | |
777 | else if (FCR_P (regno)) | |
0a2aaacc | 778 | rclass = FCR_REGS; |
36a05131 BS |
779 | |
780 | else if (ACC_P (regno)) | |
781 | { | |
782 | int r = regno - ACC_FIRST; | |
783 | if ((r & 3) == 0) | |
0a2aaacc | 784 | rclass = QUAD_ACC_REGS; |
36a05131 | 785 | else if ((r & 1) == 0) |
0a2aaacc | 786 | rclass = EVEN_ACC_REGS; |
36a05131 | 787 | else |
0a2aaacc | 788 | rclass = ACC_REGS; |
36a05131 BS |
789 | } |
790 | ||
791 | else if (ACCG_P (regno)) | |
0a2aaacc | 792 | rclass = ACCG_REGS; |
36a05131 BS |
793 | |
794 | else | |
0a2aaacc | 795 | rclass = NO_REGS; |
36a05131 | 796 | |
0a2aaacc | 797 | regno_reg_class[regno] = rclass; |
36a05131 BS |
798 | } |
799 | ||
800 | /* Check for small data option */ | |
fa37ed29 | 801 | if (!global_options_set.x_g_switch_value && !TARGET_LIBPIC) |
36a05131 BS |
802 | g_switch_value = SDATA_DEFAULT_SIZE; |
803 | ||
804 | /* A C expression which defines the machine-dependent operand | |
805 | constraint letters for register classes. If CHAR is such a | |
806 | letter, the value should be the register class corresponding to | |
807 | it. Otherwise, the value should be `NO_REGS'. The register | |
808 | letter `r', corresponding to class `GENERAL_REGS', will not be | |
809 | passed to this macro; you do not need to handle it. | |
810 | ||
811 | The following letters are unavailable, due to being used as | |
812 | constraints: | |
813 | '0'..'9' | |
814 | '<', '>' | |
815 | 'E', 'F', 'G', 'H' | |
816 | 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P' | |
817 | 'Q', 'R', 'S', 'T', 'U' | |
818 | 'V', 'X' | |
819 | 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */ | |
820 | ||
821 | for (i = 0; i < 256; i++) | |
822 | reg_class_from_letter[i] = NO_REGS; | |
823 | ||
824 | reg_class_from_letter['a'] = ACC_REGS; | |
825 | reg_class_from_letter['b'] = EVEN_ACC_REGS; | |
826 | reg_class_from_letter['c'] = CC_REGS; | |
827 | reg_class_from_letter['d'] = GPR_REGS; | |
828 | reg_class_from_letter['e'] = EVEN_REGS; | |
829 | reg_class_from_letter['f'] = FPR_REGS; | |
830 | reg_class_from_letter['h'] = FEVEN_REGS; | |
831 | reg_class_from_letter['l'] = LR_REG; | |
832 | reg_class_from_letter['q'] = QUAD_REGS; | |
833 | reg_class_from_letter['t'] = ICC_REGS; | |
834 | reg_class_from_letter['u'] = FCC_REGS; | |
835 | reg_class_from_letter['v'] = ICR_REGS; | |
836 | reg_class_from_letter['w'] = FCR_REGS; | |
837 | reg_class_from_letter['x'] = QUAD_FPR_REGS; | |
838 | reg_class_from_letter['y'] = LCR_REG; | |
839 | reg_class_from_letter['z'] = SPR_REGS; | |
840 | reg_class_from_letter['A'] = QUAD_ACC_REGS; | |
841 | reg_class_from_letter['B'] = ACCG_REGS; | |
842 | reg_class_from_letter['C'] = CR_REGS; | |
34208acf AO |
843 | reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */ |
844 | reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */ | |
36a05131 BS |
845 | |
846 | /* There is no single unaligned SI op for PIC code. Sometimes we | |
847 | need to use ".4byte" and sometimes we need to use ".picptr". | |
848 | See frv_assemble_integer for details. */ | |
34208acf | 849 | if (flag_pic || TARGET_FDPIC) |
36a05131 BS |
850 | targetm.asm_out.unaligned_op.si = 0; |
851 | ||
34208acf AO |
852 | if ((target_flags_explicit & MASK_LINKED_FP) == 0) |
853 | target_flags |= MASK_LINKED_FP; | |
854 | ||
38c28a25 AH |
855 | if ((target_flags_explicit & MASK_OPTIMIZE_MEMBAR) == 0) |
856 | target_flags |= MASK_OPTIMIZE_MEMBAR; | |
857 | ||
c557edf4 RS |
858 | for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++) |
859 | frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]); | |
860 | ||
861 | for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++) | |
862 | frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes); | |
863 | ||
36a05131 BS |
864 | init_machine_status = frv_init_machine_status; |
865 | } | |
866 | ||
36a05131 BS |
867 | \f |
868 | /* Return true if NAME (a STRING_CST node) begins with PREFIX. */ | |
869 | ||
870 | static int | |
3101faab | 871 | frv_string_begins_with (const_tree name, const char *prefix) |
36a05131 | 872 | { |
3101faab | 873 | const int prefix_len = strlen (prefix); |
36a05131 BS |
874 | |
875 | /* Remember: NAME's length includes the null terminator. */ | |
876 | return (TREE_STRING_LENGTH (name) > prefix_len | |
877 | && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0); | |
878 | } | |
36a05131 BS |
879 | \f |
880 | /* Zero or more C statements that may conditionally modify two variables | |
881 | `fixed_regs' and `call_used_regs' (both of type `char []') after they have | |
882 | been initialized from the two preceding macros. | |
883 | ||
884 | This is necessary in case the fixed or call-clobbered registers depend on | |
885 | target flags. | |
886 | ||
887 | You need not define this macro if it has no work to do. | |
888 | ||
889 | If the usage of an entire class of registers depends on the target flags, | |
890 | you may indicate this to GCC by using this macro to modify `fixed_regs' and | |
891 | `call_used_regs' to 1 for each of the registers in the classes which should | |
892 | not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return | |
893 | `NO_REGS' if it is called with a letter for a class that shouldn't be used. | |
894 | ||
895 | (However, if this class is not included in `GENERAL_REGS' and all of the | |
896 | insn patterns whose constraints permit this class are controlled by target | |
897 | switches, then GCC will automatically avoid using these registers when the | |
898 | target switches are opposed to them.) */ | |
899 | ||
900 | void | |
f2206911 | 901 | frv_conditional_register_usage (void) |
36a05131 BS |
902 | { |
903 | int i; | |
904 | ||
905 | for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++) | |
906 | fixed_regs[i] = call_used_regs[i] = 1; | |
907 | ||
908 | for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++) | |
909 | fixed_regs[i] = call_used_regs[i] = 1; | |
910 | ||
36a05131 BS |
911 | /* Reserve the registers used for conditional execution. At present, we need |
912 | 1 ICC and 1 ICR register. */ | |
913 | fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1; | |
914 | fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1; | |
915 | ||
916 | if (TARGET_FIXED_CC) | |
917 | { | |
918 | fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1; | |
919 | fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1; | |
920 | fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1; | |
921 | fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1; | |
922 | } | |
923 | ||
34208acf AO |
924 | if (TARGET_FDPIC) |
925 | fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] = | |
926 | call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0; | |
927 | ||
36a05131 BS |
928 | #if 0 |
929 | /* If -fpic, SDA_BASE_REG is the PIC register. */ | |
930 | if (g_switch_value == 0 && !flag_pic) | |
931 | fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0; | |
932 | ||
933 | if (!flag_pic) | |
934 | fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0; | |
935 | #endif | |
936 | } | |
937 | ||
938 | \f | |
939 | /* | |
940 | * Compute the stack frame layout | |
941 | * | |
942 | * Register setup: | |
943 | * +---------------+-----------------------+-----------------------+ | |
944 | * |Register |type |caller-save/callee-save| | |
945 | * +---------------+-----------------------+-----------------------+ | |
946 | * |GR0 |Zero register | - | | |
947 | * |GR1 |Stack pointer(SP) | - | | |
948 | * |GR2 |Frame pointer(FP) | - | | |
949 | * |GR3 |Hidden parameter | caller save | | |
950 | * |GR4-GR7 | - | caller save | | |
951 | * |GR8-GR13 |Argument register | caller save | | |
952 | * |GR14-GR15 | - | caller save | | |
953 | * |GR16-GR31 | - | callee save | | |
954 | * |GR32-GR47 | - | caller save | | |
955 | * |GR48-GR63 | - | callee save | | |
956 | * |FR0-FR15 | - | caller save | | |
957 | * |FR16-FR31 | - | callee save | | |
958 | * |FR32-FR47 | - | caller save | | |
959 | * |FR48-FR63 | - | callee save | | |
960 | * +---------------+-----------------------+-----------------------+ | |
961 | * | |
962 | * Stack frame setup: | |
963 | * Low | |
964 | * SP-> |-----------------------------------| | |
965 | * | Argument area | | |
966 | * |-----------------------------------| | |
967 | * | Register save area | | |
968 | * |-----------------------------------| | |
969 | * | Local variable save area | | |
970 | * FP-> |-----------------------------------| | |
971 | * | Old FP | | |
972 | * |-----------------------------------| | |
973 | * | Hidden parameter save area | | |
974 | * |-----------------------------------| | |
975 | * | Return address(LR) storage area | | |
976 | * |-----------------------------------| | |
977 | * | Padding for alignment | | |
978 | * |-----------------------------------| | |
979 | * | Register argument area | | |
980 | * OLD SP-> |-----------------------------------| | |
981 | * | Parameter area | | |
982 | * |-----------------------------------| | |
983 | * High | |
984 | * | |
985 | * Argument area/Parameter area: | |
986 | * | |
987 | * When a function is called, this area is used for argument transfer. When | |
988 | * the argument is set up by the caller function, this area is referred to as | |
989 | * the argument area. When the argument is referenced by the callee function, | |
990 | * this area is referred to as the parameter area. The area is allocated when | |
991 | * all arguments cannot be placed on the argument register at the time of | |
992 | * argument transfer. | |
993 | * | |
994 | * Register save area: | |
995 | * | |
996 | * This is a register save area that must be guaranteed for the caller | |
997 | * function. This area is not secured when the register save operation is not | |
998 | * needed. | |
999 | * | |
1000 | * Local variable save area: | |
1001 | * | |
1002 | * This is the area for local variables and temporary variables. | |
1003 | * | |
1004 | * Old FP: | |
1005 | * | |
1006 | * This area stores the FP value of the caller function. | |
1007 | * | |
1008 | * Hidden parameter save area: | |
1009 | * | |
1010 | * This area stores the start address of the return value storage | |
1011 | * area for a struct/union return function. | |
1012 | * When a struct/union is used as the return value, the caller | |
1013 | * function stores the return value storage area start address in | |
1014 | * register GR3 and passes it to the caller function. | |
1015 | * The callee function interprets the address stored in the GR3 | |
1016 | * as the return value storage area start address. | |
1017 | * When register GR3 needs to be saved into memory, the callee | |
1018 | * function saves it in the hidden parameter save area. This | |
1019 | * area is not secured when the save operation is not needed. | |
1020 | * | |
1021 | * Return address(LR) storage area: | |
1022 | * | |
1023 | * This area saves the LR. The LR stores the address of a return to the caller | |
1024 | * function for the purpose of function calling. | |
1025 | * | |
1026 | * Argument register area: | |
1027 | * | |
1028 | * This area saves the argument register. This area is not secured when the | |
1029 | * save operation is not needed. | |
1030 | * | |
1031 | * Argument: | |
1032 | * | |
1033 | * Arguments, the count of which equals the count of argument registers (6 | |
1034 | * words), are positioned in registers GR8 to GR13 and delivered to the callee | |
1035 | * function. When a struct/union return function is called, the return value | |
1036 | * area address is stored in register GR3. Arguments not placed in the | |
1037 | * argument registers will be stored in the stack argument area for transfer | |
1038 | * purposes. When an 8-byte type argument is to be delivered using registers, | |
1039 | * it is divided into two and placed in two registers for transfer. When | |
1040 | * argument registers must be saved to memory, the callee function secures an | |
1041 | * argument register save area in the stack. In this case, a continuous | |
1042 | * argument register save area must be established in the parameter area. The | |
1043 | * argument register save area must be allocated as needed to cover the size of | |
1044 | * the argument register to be saved. If the function has a variable count of | |
1045 | * arguments, it saves all argument registers in the argument register save | |
1046 | * area. | |
1047 | * | |
1048 | * Argument Extension Format: | |
1049 | * | |
1050 | * When an argument is to be stored in the stack, its type is converted to an | |
1051 | * extended type in accordance with the individual argument type. The argument | |
1052 | * is freed by the caller function after the return from the callee function is | |
1053 | * made. | |
1054 | * | |
1055 | * +-----------------------+---------------+------------------------+ | |
1056 | * | Argument Type |Extended Type |Stack Storage Size(byte)| | |
1057 | * +-----------------------+---------------+------------------------+ | |
1058 | * |char |int | 4 | | |
1059 | * |signed char |int | 4 | | |
1060 | * |unsigned char |int | 4 | | |
1061 | * |[signed] short int |int | 4 | | |
1062 | * |unsigned short int |int | 4 | | |
1063 | * |[signed] int |No extension | 4 | | |
1064 | * |unsigned int |No extension | 4 | | |
1065 | * |[signed] long int |No extension | 4 | | |
1066 | * |unsigned long int |No extension | 4 | | |
1067 | * |[signed] long long int |No extension | 8 | | |
1068 | * |unsigned long long int |No extension | 8 | | |
1069 | * |float |double | 8 | | |
1070 | * |double |No extension | 8 | | |
1071 | * |long double |No extension | 8 | | |
1072 | * |pointer |No extension | 4 | | |
1073 | * |struct/union |- | 4 (*1) | | |
1074 | * +-----------------------+---------------+------------------------+ | |
1075 | * | |
1076 | * When a struct/union is to be delivered as an argument, the caller copies it | |
1077 | * to the local variable area and delivers the address of that area. | |
1078 | * | |
1079 | * Return Value: | |
1080 | * | |
1081 | * +-------------------------------+----------------------+ | |
1082 | * |Return Value Type |Return Value Interface| | |
1083 | * +-------------------------------+----------------------+ | |
1084 | * |void |None | | |
1085 | * |[signed|unsigned] char |GR8 | | |
1086 | * |[signed|unsigned] short int |GR8 | | |
1087 | * |[signed|unsigned] int |GR8 | | |
1088 | * |[signed|unsigned] long int |GR8 | | |
1089 | * |pointer |GR8 | | |
1090 | * |[signed|unsigned] long long int|GR8 & GR9 | | |
1091 | * |float |GR8 | | |
1092 | * |double |GR8 & GR9 | | |
1093 | * |long double |GR8 & GR9 | | |
1094 | * |struct/union |(*1) | | |
1095 | * +-------------------------------+----------------------+ | |
1096 | * | |
1097 | * When a struct/union is used as the return value, the caller function stores | |
1098 | * the start address of the return value storage area into GR3 and then passes | |
1099 | * it to the callee function. The callee function interprets GR3 as the start | |
1100 | * address of the return value storage area. When this address needs to be | |
1101 | * saved in memory, the callee function secures the hidden parameter save area | |
1102 | * and saves the address in that area. | |
1103 | */ | |
1104 | ||
1105 | frv_stack_t * | |
f2206911 | 1106 | frv_stack_info (void) |
36a05131 BS |
1107 | { |
1108 | static frv_stack_t info, zero_info; | |
1109 | frv_stack_t *info_ptr = &info; | |
1110 | tree fndecl = current_function_decl; | |
1111 | int varargs_p = 0; | |
1112 | tree cur_arg; | |
1113 | tree next_arg; | |
1114 | int range; | |
1115 | int alignment; | |
1116 | int offset; | |
1117 | ||
87b483a1 KH |
1118 | /* If we've already calculated the values and reload is complete, |
1119 | just return now. */ | |
36a05131 BS |
1120 | if (frv_stack_cache) |
1121 | return frv_stack_cache; | |
1122 | ||
87b483a1 | 1123 | /* Zero all fields. */ |
36a05131 BS |
1124 | info = zero_info; |
1125 | ||
87b483a1 | 1126 | /* Set up the register range information. */ |
36a05131 BS |
1127 | info_ptr->regs[STACK_REGS_GPR].name = "gpr"; |
1128 | info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1; | |
1129 | info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST; | |
1130 | info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE; | |
1131 | ||
1132 | info_ptr->regs[STACK_REGS_FPR].name = "fpr"; | |
1133 | info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST; | |
1134 | info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST; | |
1135 | info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE; | |
1136 | ||
1137 | info_ptr->regs[STACK_REGS_LR].name = "lr"; | |
1138 | info_ptr->regs[STACK_REGS_LR].first = LR_REGNO; | |
1139 | info_ptr->regs[STACK_REGS_LR].last = LR_REGNO; | |
1140 | info_ptr->regs[STACK_REGS_LR].special_p = 1; | |
1141 | ||
1142 | info_ptr->regs[STACK_REGS_CC].name = "cc"; | |
1143 | info_ptr->regs[STACK_REGS_CC].first = CC_FIRST; | |
1144 | info_ptr->regs[STACK_REGS_CC].last = CC_LAST; | |
1145 | info_ptr->regs[STACK_REGS_CC].field_p = TRUE; | |
1146 | ||
1147 | info_ptr->regs[STACK_REGS_LCR].name = "lcr"; | |
1148 | info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO; | |
1149 | info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO; | |
1150 | ||
1151 | info_ptr->regs[STACK_REGS_STDARG].name = "stdarg"; | |
1152 | info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM; | |
1153 | info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM; | |
1154 | info_ptr->regs[STACK_REGS_STDARG].dword_p = 1; | |
1155 | info_ptr->regs[STACK_REGS_STDARG].special_p = 1; | |
1156 | ||
1157 | info_ptr->regs[STACK_REGS_STRUCT].name = "struct"; | |
8ac411c7 KH |
1158 | info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM; |
1159 | info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM; | |
36a05131 BS |
1160 | info_ptr->regs[STACK_REGS_STRUCT].special_p = 1; |
1161 | ||
1162 | info_ptr->regs[STACK_REGS_FP].name = "fp"; | |
1163 | info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM; | |
1164 | info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM; | |
1165 | info_ptr->regs[STACK_REGS_FP].special_p = 1; | |
1166 | ||
1167 | /* Determine if this is a stdarg function. If so, allocate space to store | |
1168 | the 6 arguments. */ | |
1169 | if (cfun->stdarg) | |
1170 | varargs_p = 1; | |
1171 | ||
1172 | else | |
1173 | { | |
1174 | /* Find the last argument, and see if it is __builtin_va_alist. */ | |
1175 | for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg) | |
1176 | { | |
910ad8de | 1177 | next_arg = DECL_CHAIN (cur_arg); |
36a05131 BS |
1178 | if (next_arg == (tree)0) |
1179 | { | |
1180 | if (DECL_NAME (cur_arg) | |
1181 | && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist")) | |
1182 | varargs_p = 1; | |
1183 | ||
1184 | break; | |
1185 | } | |
1186 | } | |
1187 | } | |
1188 | ||
87b483a1 | 1189 | /* Iterate over all of the register ranges. */ |
36a05131 BS |
1190 | for (range = 0; range < STACK_REGS_MAX; range++) |
1191 | { | |
1192 | frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); | |
1193 | int first = reg_ptr->first; | |
1194 | int last = reg_ptr->last; | |
1195 | int size_1word = 0; | |
1196 | int size_2words = 0; | |
1197 | int regno; | |
1198 | ||
87b483a1 | 1199 | /* Calculate which registers need to be saved & save area size. */ |
36a05131 BS |
1200 | switch (range) |
1201 | { | |
1202 | default: | |
1203 | for (regno = first; regno <= last; regno++) | |
1204 | { | |
6fb5fa3c | 1205 | if ((df_regs_ever_live_p (regno) && !call_used_regs[regno]) |
e3b5732b | 1206 | || (crtl->calls_eh_return |
36a05131 | 1207 | && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM)) |
34208acf | 1208 | || (!TARGET_FDPIC && flag_pic |
ad516a74 | 1209 | && crtl->uses_pic_offset_table && regno == PIC_REGNO)) |
36a05131 BS |
1210 | { |
1211 | info_ptr->save_p[regno] = REG_SAVE_1WORD; | |
1212 | size_1word += UNITS_PER_WORD; | |
1213 | } | |
1214 | } | |
1215 | break; | |
1216 | ||
1217 | /* Calculate whether we need to create a frame after everything else | |
1218 | has been processed. */ | |
1219 | case STACK_REGS_FP: | |
1220 | break; | |
1221 | ||
1222 | case STACK_REGS_LR: | |
6fb5fa3c | 1223 | if (df_regs_ever_live_p (LR_REGNO) |
36a05131 | 1224 | || profile_flag |
34208acf AO |
1225 | /* This is set for __builtin_return_address, etc. */ |
1226 | || cfun->machine->frame_needed | |
1227 | || (TARGET_LINKED_FP && frame_pointer_needed) | |
1228 | || (!TARGET_FDPIC && flag_pic | |
ad516a74 | 1229 | && crtl->uses_pic_offset_table)) |
36a05131 BS |
1230 | { |
1231 | info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD; | |
1232 | size_1word += UNITS_PER_WORD; | |
1233 | } | |
1234 | break; | |
1235 | ||
1236 | case STACK_REGS_STDARG: | |
1237 | if (varargs_p) | |
1238 | { | |
87b483a1 KH |
1239 | /* If this is a stdarg function with a non varardic |
1240 | argument split between registers and the stack, | |
1241 | adjust the saved registers downward. */ | |
7dd68986 | 1242 | last -= (ADDR_ALIGN (crtl->args.pretend_args_size, UNITS_PER_WORD) |
36a05131 BS |
1243 | / UNITS_PER_WORD); |
1244 | ||
1245 | for (regno = first; regno <= last; regno++) | |
1246 | { | |
1247 | info_ptr->save_p[regno] = REG_SAVE_1WORD; | |
1248 | size_1word += UNITS_PER_WORD; | |
1249 | } | |
1250 | ||
1251 | info_ptr->stdarg_size = size_1word; | |
1252 | } | |
1253 | break; | |
1254 | ||
1255 | case STACK_REGS_STRUCT: | |
1256 | if (cfun->returns_struct) | |
1257 | { | |
8ac411c7 | 1258 | info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD; |
36a05131 BS |
1259 | size_1word += UNITS_PER_WORD; |
1260 | } | |
1261 | break; | |
1262 | } | |
1263 | ||
1264 | ||
1265 | if (size_1word) | |
1266 | { | |
87b483a1 | 1267 | /* If this is a field, it only takes one word. */ |
36a05131 BS |
1268 | if (reg_ptr->field_p) |
1269 | size_1word = UNITS_PER_WORD; | |
1270 | ||
87b483a1 | 1271 | /* Determine which register pairs can be saved together. */ |
36a05131 BS |
1272 | else if (reg_ptr->dword_p && TARGET_DWORD) |
1273 | { | |
1274 | for (regno = first; regno < last; regno += 2) | |
1275 | { | |
1276 | if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1]) | |
1277 | { | |
1278 | size_2words += 2 * UNITS_PER_WORD; | |
1279 | size_1word -= 2 * UNITS_PER_WORD; | |
1280 | info_ptr->save_p[regno] = REG_SAVE_2WORDS; | |
1281 | info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE; | |
1282 | } | |
1283 | } | |
1284 | } | |
1285 | ||
1286 | reg_ptr->size_1word = size_1word; | |
1287 | reg_ptr->size_2words = size_2words; | |
1288 | ||
1289 | if (! reg_ptr->special_p) | |
1290 | { | |
1291 | info_ptr->regs_size_1word += size_1word; | |
1292 | info_ptr->regs_size_2words += size_2words; | |
1293 | } | |
1294 | } | |
1295 | } | |
1296 | ||
1297 | /* Set up the sizes of each each field in the frame body, making the sizes | |
1298 | of each be divisible by the size of a dword if dword operations might | |
1299 | be used, or the size of a word otherwise. */ | |
1300 | alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD); | |
1301 | ||
7dd68986 | 1302 | info_ptr->parameter_size = ADDR_ALIGN (crtl->outgoing_args_size, alignment); |
36a05131 BS |
1303 | info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words |
1304 | + info_ptr->regs_size_1word, | |
1305 | alignment); | |
1306 | info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment); | |
1307 | ||
7dd68986 | 1308 | info_ptr->pretend_size = crtl->args.pretend_args_size; |
36a05131 BS |
1309 | |
1310 | /* Work out the size of the frame, excluding the header. Both the frame | |
1311 | body and register parameter area will be dword-aligned. */ | |
1312 | info_ptr->total_size | |
1313 | = (ADDR_ALIGN (info_ptr->parameter_size | |
1314 | + info_ptr->regs_size | |
1315 | + info_ptr->vars_size, | |
1316 | 2 * UNITS_PER_WORD) | |
1317 | + ADDR_ALIGN (info_ptr->pretend_size | |
1318 | + info_ptr->stdarg_size, | |
1319 | 2 * UNITS_PER_WORD)); | |
1320 | ||
1321 | /* See if we need to create a frame at all, if so add header area. */ | |
1322 | if (info_ptr->total_size > 0 | |
34208acf | 1323 | || frame_pointer_needed |
36a05131 BS |
1324 | || info_ptr->regs[STACK_REGS_LR].size_1word > 0 |
1325 | || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0) | |
1326 | { | |
1327 | offset = info_ptr->parameter_size; | |
1328 | info_ptr->header_size = 4 * UNITS_PER_WORD; | |
1329 | info_ptr->total_size += 4 * UNITS_PER_WORD; | |
1330 | ||
87b483a1 | 1331 | /* Calculate the offsets to save normal register pairs. */ |
36a05131 BS |
1332 | for (range = 0; range < STACK_REGS_MAX; range++) |
1333 | { | |
1334 | frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); | |
1335 | if (! reg_ptr->special_p) | |
1336 | { | |
1337 | int first = reg_ptr->first; | |
1338 | int last = reg_ptr->last; | |
1339 | int regno; | |
1340 | ||
1341 | for (regno = first; regno <= last; regno++) | |
1342 | if (info_ptr->save_p[regno] == REG_SAVE_2WORDS | |
1343 | && regno != FRAME_POINTER_REGNUM | |
1344 | && (regno < FIRST_ARG_REGNUM | |
1345 | || regno > LAST_ARG_REGNUM)) | |
1346 | { | |
1347 | info_ptr->reg_offset[regno] = offset; | |
1348 | offset += 2 * UNITS_PER_WORD; | |
1349 | } | |
1350 | } | |
1351 | } | |
1352 | ||
87b483a1 | 1353 | /* Calculate the offsets to save normal single registers. */ |
36a05131 BS |
1354 | for (range = 0; range < STACK_REGS_MAX; range++) |
1355 | { | |
1356 | frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); | |
1357 | if (! reg_ptr->special_p) | |
1358 | { | |
1359 | int first = reg_ptr->first; | |
1360 | int last = reg_ptr->last; | |
1361 | int regno; | |
1362 | ||
1363 | for (regno = first; regno <= last; regno++) | |
1364 | if (info_ptr->save_p[regno] == REG_SAVE_1WORD | |
1365 | && regno != FRAME_POINTER_REGNUM | |
1366 | && (regno < FIRST_ARG_REGNUM | |
1367 | || regno > LAST_ARG_REGNUM)) | |
1368 | { | |
1369 | info_ptr->reg_offset[regno] = offset; | |
1370 | offset += UNITS_PER_WORD; | |
1371 | } | |
1372 | } | |
1373 | } | |
1374 | ||
1375 | /* Calculate the offset to save the local variables at. */ | |
1376 | offset = ADDR_ALIGN (offset, alignment); | |
1377 | if (info_ptr->vars_size) | |
1378 | { | |
1379 | info_ptr->vars_offset = offset; | |
1380 | offset += info_ptr->vars_size; | |
1381 | } | |
1382 | ||
1383 | /* Align header to a dword-boundary. */ | |
1384 | offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD); | |
1385 | ||
1386 | /* Calculate the offsets in the fixed frame. */ | |
1387 | info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD; | |
1388 | info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset; | |
1389 | info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD; | |
1390 | ||
1391 | info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD; | |
1392 | info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD; | |
1393 | info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD; | |
1394 | ||
1395 | if (cfun->returns_struct) | |
1396 | { | |
8ac411c7 KH |
1397 | info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD; |
1398 | info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD; | |
36a05131 BS |
1399 | info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD; |
1400 | } | |
1401 | ||
1402 | /* Calculate the offsets to store the arguments passed in registers | |
1403 | for stdarg functions. The register pairs are first and the single | |
1404 | register if any is last. The register save area starts on a | |
1405 | dword-boundary. */ | |
1406 | if (info_ptr->stdarg_size) | |
1407 | { | |
1408 | int first = info_ptr->regs[STACK_REGS_STDARG].first; | |
1409 | int last = info_ptr->regs[STACK_REGS_STDARG].last; | |
1410 | int regno; | |
1411 | ||
1412 | /* Skip the header. */ | |
1413 | offset += 4 * UNITS_PER_WORD; | |
1414 | for (regno = first; regno <= last; regno++) | |
1415 | { | |
1416 | if (info_ptr->save_p[regno] == REG_SAVE_2WORDS) | |
1417 | { | |
1418 | info_ptr->reg_offset[regno] = offset; | |
1419 | offset += 2 * UNITS_PER_WORD; | |
1420 | } | |
1421 | else if (info_ptr->save_p[regno] == REG_SAVE_1WORD) | |
1422 | { | |
1423 | info_ptr->reg_offset[regno] = offset; | |
1424 | offset += UNITS_PER_WORD; | |
1425 | } | |
1426 | } | |
1427 | } | |
1428 | } | |
1429 | ||
1430 | if (reload_completed) | |
1431 | frv_stack_cache = info_ptr; | |
1432 | ||
1433 | return info_ptr; | |
1434 | } | |
1435 | ||
1436 | \f | |
87b483a1 | 1437 | /* Print the information about the frv stack offsets, etc. when debugging. */ |
36a05131 BS |
1438 | |
1439 | void | |
f2206911 | 1440 | frv_debug_stack (frv_stack_t *info) |
36a05131 BS |
1441 | { |
1442 | int range; | |
1443 | ||
1444 | if (!info) | |
1445 | info = frv_stack_info (); | |
1446 | ||
1447 | fprintf (stderr, "\nStack information for function %s:\n", | |
1448 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
1449 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
1450 | : "<unknown>")); | |
1451 | ||
1452 | fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size); | |
1453 | fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size); | |
1454 | fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size); | |
1455 | fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n", | |
1456 | info->regs_size, info->regs_size_1word, info->regs_size_2words); | |
1457 | ||
1458 | fprintf (stderr, "\theader_size\t= %6d\n", info->header_size); | |
1459 | fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size); | |
1460 | fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset); | |
1461 | fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset); | |
1462 | ||
1463 | for (range = 0; range < STACK_REGS_MAX; range++) | |
1464 | { | |
1465 | frv_stack_regs_t *regs = &(info->regs[range]); | |
1466 | if ((regs->size_1word + regs->size_2words) > 0) | |
1467 | { | |
1468 | int first = regs->first; | |
1469 | int last = regs->last; | |
1470 | int regno; | |
1471 | ||
1472 | fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =", | |
1473 | regs->name, regs->size_1word + regs->size_2words, | |
1474 | regs->size_1word, regs->size_2words); | |
1475 | ||
1476 | for (regno = first; regno <= last; regno++) | |
1477 | { | |
1478 | if (info->save_p[regno] == REG_SAVE_1WORD) | |
1479 | fprintf (stderr, " %s (%d)", reg_names[regno], | |
1480 | info->reg_offset[regno]); | |
1481 | ||
1482 | else if (info->save_p[regno] == REG_SAVE_2WORDS) | |
1483 | fprintf (stderr, " %s-%s (%d)", reg_names[regno], | |
1484 | reg_names[regno+1], info->reg_offset[regno]); | |
1485 | } | |
1486 | ||
1487 | fputc ('\n', stderr); | |
1488 | } | |
1489 | } | |
1490 | ||
1491 | fflush (stderr); | |
1492 | } | |
1493 | ||
1494 | ||
1495 | \f | |
1496 | ||
c557edf4 RS |
1497 | /* Used during final to control the packing of insns. The value is |
1498 | 1 if the current instruction should be packed with the next one, | |
1499 | 0 if it shouldn't or -1 if packing is disabled altogether. */ | |
36a05131 BS |
1500 | |
1501 | static int frv_insn_packing_flag; | |
1502 | ||
1503 | /* True if the current function contains a far jump. */ | |
1504 | ||
1505 | static int | |
f2206911 | 1506 | frv_function_contains_far_jump (void) |
36a05131 BS |
1507 | { |
1508 | rtx insn = get_insns (); | |
1509 | while (insn != NULL | |
1510 | && !(GET_CODE (insn) == JUMP_INSN | |
1511 | /* Ignore tablejump patterns. */ | |
1512 | && GET_CODE (PATTERN (insn)) != ADDR_VEC | |
1513 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC | |
1514 | && get_attr_far_jump (insn) == FAR_JUMP_YES)) | |
1515 | insn = NEXT_INSN (insn); | |
1516 | return (insn != NULL); | |
1517 | } | |
1518 | ||
1519 | /* For the FRV, this function makes sure that a function with far jumps | |
1520 | will return correctly. It also does the VLIW packing. */ | |
1521 | ||
1522 | static void | |
f2206911 | 1523 | frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
36a05131 BS |
1524 | { |
1525 | /* If no frame was created, check whether the function uses a call | |
1526 | instruction to implement a far jump. If so, save the link in gr3 and | |
1527 | replace all returns to LR with returns to GR3. GR3 is used because it | |
1528 | is call-clobbered, because is not available to the register allocator, | |
1529 | and because all functions that take a hidden argument pointer will have | |
1530 | a stack frame. */ | |
1531 | if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ()) | |
1532 | { | |
1533 | rtx insn; | |
1534 | ||
1535 | /* Just to check that the above comment is true. */ | |
6fb5fa3c | 1536 | gcc_assert (!df_regs_ever_live_p (GPR_FIRST + 3)); |
36a05131 BS |
1537 | |
1538 | /* Generate the instruction that saves the link register. */ | |
1539 | fprintf (file, "\tmovsg lr,gr3\n"); | |
1540 | ||
1541 | /* Replace the LR with GR3 in *return_internal patterns. The insn | |
1542 | will now return using jmpl @(gr3,0) rather than bralr. We cannot | |
1543 | simply emit a different assembly directive because bralr and jmpl | |
1544 | execute in different units. */ | |
1545 | for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn)) | |
1546 | if (GET_CODE (insn) == JUMP_INSN) | |
1547 | { | |
1548 | rtx pattern = PATTERN (insn); | |
1549 | if (GET_CODE (pattern) == PARALLEL | |
1550 | && XVECLEN (pattern, 0) >= 2 | |
1551 | && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN | |
1552 | && GET_CODE (XVECEXP (pattern, 0, 1)) == USE) | |
1553 | { | |
1554 | rtx address = XEXP (XVECEXP (pattern, 0, 1), 0); | |
1555 | if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO) | |
6fb5fa3c | 1556 | SET_REGNO (address, GPR_FIRST + 3); |
36a05131 BS |
1557 | } |
1558 | } | |
1559 | } | |
1560 | ||
1561 | frv_pack_insns (); | |
c557edf4 RS |
1562 | |
1563 | /* Allow the garbage collector to free the nops created by frv_reorg. */ | |
1564 | memset (frv_nops, 0, sizeof (frv_nops)); | |
36a05131 BS |
1565 | } |
1566 | ||
1567 | \f | |
1568 | /* Return the next available temporary register in a given class. */ | |
1569 | ||
1570 | static rtx | |
f2206911 KC |
1571 | frv_alloc_temp_reg ( |
1572 | frv_tmp_reg_t *info, /* which registers are available */ | |
0a2aaacc | 1573 | enum reg_class rclass, /* register class desired */ |
f2206911 KC |
1574 | enum machine_mode mode, /* mode to allocate register with */ |
1575 | int mark_as_used, /* register not available after allocation */ | |
1576 | int no_abort) /* return NULL instead of aborting */ | |
36a05131 | 1577 | { |
0a2aaacc | 1578 | int regno = info->next_reg[ (int)rclass ]; |
36a05131 | 1579 | int orig_regno = regno; |
0a2aaacc | 1580 | HARD_REG_SET *reg_in_class = ®_class_contents[ (int)rclass ]; |
36a05131 BS |
1581 | int i, nr; |
1582 | ||
1583 | for (;;) | |
1584 | { | |
1585 | if (TEST_HARD_REG_BIT (*reg_in_class, regno) | |
1586 | && TEST_HARD_REG_BIT (info->regs, regno)) | |
1587 | break; | |
1588 | ||
1589 | if (++regno >= FIRST_PSEUDO_REGISTER) | |
1590 | regno = 0; | |
1591 | if (regno == orig_regno) | |
1592 | { | |
44e91694 NS |
1593 | gcc_assert (no_abort); |
1594 | return NULL_RTX; | |
36a05131 BS |
1595 | } |
1596 | } | |
1597 | ||
1598 | nr = HARD_REGNO_NREGS (regno, mode); | |
0a2aaacc | 1599 | info->next_reg[ (int)rclass ] = regno + nr; |
36a05131 BS |
1600 | |
1601 | if (mark_as_used) | |
1602 | for (i = 0; i < nr; i++) | |
1603 | CLEAR_HARD_REG_BIT (info->regs, regno+i); | |
1604 | ||
1605 | return gen_rtx_REG (mode, regno); | |
1606 | } | |
1607 | ||
1608 | \f | |
1609 | /* Return an rtx with the value OFFSET, which will either be a register or a | |
1610 | signed 12-bit integer. It can be used as the second operand in an "add" | |
1611 | instruction, or as the index in a load or store. | |
1612 | ||
1613 | The function returns a constant rtx if OFFSET is small enough, otherwise | |
1614 | it loads the constant into register OFFSET_REGNO and returns that. */ | |
1615 | static rtx | |
f2206911 | 1616 | frv_frame_offset_rtx (int offset) |
36a05131 BS |
1617 | { |
1618 | rtx offset_rtx = GEN_INT (offset); | |
1619 | if (IN_RANGE_P (offset, -2048, 2047)) | |
1620 | return offset_rtx; | |
1621 | else | |
1622 | { | |
1623 | rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO); | |
1624 | if (IN_RANGE_P (offset, -32768, 32767)) | |
1625 | emit_insn (gen_movsi (reg_rtx, offset_rtx)); | |
1626 | else | |
1627 | { | |
1628 | emit_insn (gen_movsi_high (reg_rtx, offset_rtx)); | |
1629 | emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx)); | |
1630 | } | |
1631 | return reg_rtx; | |
1632 | } | |
1633 | } | |
1634 | ||
1635 | /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The | |
1636 | prologue and epilogue uses such expressions to access the stack. */ | |
1637 | static rtx | |
f2206911 | 1638 | frv_frame_mem (enum machine_mode mode, rtx base, int offset) |
36a05131 BS |
1639 | { |
1640 | return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, | |
1641 | base, | |
1642 | frv_frame_offset_rtx (offset))); | |
1643 | } | |
1644 | ||
1645 | /* Generate a frame-related expression: | |
1646 | ||
1647 | (set REG (mem (plus (sp) (const_int OFFSET)))). | |
1648 | ||
1649 | Such expressions are used in FRAME_RELATED_EXPR notes for more complex | |
1650 | instructions. Marking the expressions as frame-related is superfluous if | |
1651 | the note contains just a single set. But if the note contains a PARALLEL | |
1652 | or SEQUENCE that has several sets, each set must be individually marked | |
1653 | as frame-related. */ | |
1654 | static rtx | |
f2206911 | 1655 | frv_dwarf_store (rtx reg, int offset) |
36a05131 BS |
1656 | { |
1657 | rtx set = gen_rtx_SET (VOIDmode, | |
1658 | gen_rtx_MEM (GET_MODE (reg), | |
1659 | plus_constant (stack_pointer_rtx, | |
1660 | offset)), | |
1661 | reg); | |
1662 | RTX_FRAME_RELATED_P (set) = 1; | |
1663 | return set; | |
1664 | } | |
1665 | ||
1666 | /* Emit a frame-related instruction whose pattern is PATTERN. The | |
1667 | instruction is the last in a sequence that cumulatively performs the | |
1668 | operation described by DWARF_PATTERN. The instruction is marked as | |
1669 | frame-related and has a REG_FRAME_RELATED_EXPR note containing | |
1670 | DWARF_PATTERN. */ | |
1671 | static void | |
f2206911 | 1672 | frv_frame_insn (rtx pattern, rtx dwarf_pattern) |
36a05131 BS |
1673 | { |
1674 | rtx insn = emit_insn (pattern); | |
1675 | RTX_FRAME_RELATED_P (insn) = 1; | |
1676 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
1677 | dwarf_pattern, | |
1678 | REG_NOTES (insn)); | |
1679 | } | |
1680 | ||
1681 | /* Emit instructions that transfer REG to or from the memory location (sp + | |
1682 | STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is | |
1683 | FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this | |
1684 | function to store registers and only the epilogue uses it to load them. | |
1685 | ||
1686 | The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET). | |
1687 | The generated instruction will use BASE as its base register. BASE may | |
1688 | simply be the stack pointer, but if several accesses are being made to a | |
1689 | region far away from the stack pointer, it may be more efficient to set | |
1690 | up a temporary instead. | |
b16c1435 | 1691 | |
36a05131 BS |
1692 | Store instructions will be frame-related and will be annotated with the |
1693 | overall effect of the store. Load instructions will be followed by a | |
1694 | (use) to prevent later optimizations from zapping them. | |
1695 | ||
1696 | The function takes care of the moves to and from SPRs, using TEMP_REGNO | |
1697 | as a temporary in such cases. */ | |
1698 | static void | |
f2206911 | 1699 | frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset) |
36a05131 BS |
1700 | { |
1701 | enum machine_mode mode = GET_MODE (reg); | |
1702 | rtx mem = frv_frame_mem (mode, | |
1703 | accessor->base, | |
1704 | stack_offset - accessor->base_offset); | |
1705 | ||
1706 | if (accessor->op == FRV_LOAD) | |
1707 | { | |
1708 | if (SPR_P (REGNO (reg))) | |
1709 | { | |
1710 | rtx temp = gen_rtx_REG (mode, TEMP_REGNO); | |
1711 | emit_insn (gen_rtx_SET (VOIDmode, temp, mem)); | |
1712 | emit_insn (gen_rtx_SET (VOIDmode, reg, temp)); | |
1713 | } | |
1714 | else | |
8d8256c1 NC |
1715 | { |
1716 | /* We cannot use reg+reg addressing for DImode access. */ | |
1717 | if (mode == DImode | |
1718 | && GET_CODE (XEXP (mem, 0)) == PLUS | |
1719 | && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG | |
1720 | && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG) | |
1721 | { | |
1722 | rtx temp = gen_rtx_REG (SImode, TEMP_REGNO); | |
1723 | rtx insn = emit_move_insn (temp, | |
1724 | gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0), | |
1725 | XEXP (XEXP (mem, 0), 1))); | |
1726 | mem = gen_rtx_MEM (DImode, temp); | |
1727 | } | |
1728 | emit_insn (gen_rtx_SET (VOIDmode, reg, mem)); | |
1729 | } | |
c41c1387 | 1730 | emit_use (reg); |
36a05131 BS |
1731 | } |
1732 | else | |
1733 | { | |
1734 | if (SPR_P (REGNO (reg))) | |
1735 | { | |
1736 | rtx temp = gen_rtx_REG (mode, TEMP_REGNO); | |
1737 | emit_insn (gen_rtx_SET (VOIDmode, temp, reg)); | |
1738 | frv_frame_insn (gen_rtx_SET (Pmode, mem, temp), | |
1739 | frv_dwarf_store (reg, stack_offset)); | |
1740 | } | |
8d8256c1 | 1741 | else if (mode == DImode) |
36a05131 BS |
1742 | { |
1743 | /* For DImode saves, the dwarf2 version needs to be a SEQUENCE | |
1744 | with a separate save for each register. */ | |
1745 | rtx reg1 = gen_rtx_REG (SImode, REGNO (reg)); | |
1746 | rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1); | |
1747 | rtx set1 = frv_dwarf_store (reg1, stack_offset); | |
1748 | rtx set2 = frv_dwarf_store (reg2, stack_offset + 4); | |
8d8256c1 NC |
1749 | |
1750 | /* Also we cannot use reg+reg addressing. */ | |
1751 | if (GET_CODE (XEXP (mem, 0)) == PLUS | |
1752 | && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG | |
1753 | && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG) | |
1754 | { | |
1755 | rtx temp = gen_rtx_REG (SImode, TEMP_REGNO); | |
1756 | rtx insn = emit_move_insn (temp, | |
1757 | gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0), | |
1758 | XEXP (XEXP (mem, 0), 1))); | |
1759 | mem = gen_rtx_MEM (DImode, temp); | |
1760 | } | |
1761 | ||
36a05131 BS |
1762 | frv_frame_insn (gen_rtx_SET (Pmode, mem, reg), |
1763 | gen_rtx_PARALLEL (VOIDmode, | |
1764 | gen_rtvec (2, set1, set2))); | |
1765 | } | |
1766 | else | |
1767 | frv_frame_insn (gen_rtx_SET (Pmode, mem, reg), | |
1768 | frv_dwarf_store (reg, stack_offset)); | |
1769 | } | |
1770 | } | |
1771 | ||
1772 | /* A function that uses frv_frame_access to transfer a group of registers to | |
1773 | or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO | |
1774 | is the stack information generated by frv_stack_info, and REG_SET is the | |
1775 | number of the register set to transfer. */ | |
1776 | static void | |
f2206911 KC |
1777 | frv_frame_access_multi (frv_frame_accessor_t *accessor, |
1778 | frv_stack_t *info, | |
1779 | int reg_set) | |
36a05131 BS |
1780 | { |
1781 | frv_stack_regs_t *regs_info; | |
1782 | int regno; | |
1783 | ||
1784 | regs_info = &info->regs[reg_set]; | |
1785 | for (regno = regs_info->first; regno <= regs_info->last; regno++) | |
1786 | if (info->save_p[regno]) | |
1787 | frv_frame_access (accessor, | |
1788 | info->save_p[regno] == REG_SAVE_2WORDS | |
1789 | ? gen_rtx_REG (DImode, regno) | |
1790 | : gen_rtx_REG (SImode, regno), | |
1791 | info->reg_offset[regno]); | |
1792 | } | |
1793 | ||
1794 | /* Save or restore callee-saved registers that are kept outside the frame | |
1795 | header. The function saves the registers if OP is FRV_STORE and restores | |
1796 | them if OP is FRV_LOAD. INFO is the stack information generated by | |
1797 | frv_stack_info. */ | |
1798 | static void | |
f2206911 | 1799 | frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info) |
36a05131 BS |
1800 | { |
1801 | frv_frame_accessor_t accessor; | |
1802 | ||
1803 | accessor.op = op; | |
1804 | accessor.base = stack_pointer_rtx; | |
1805 | accessor.base_offset = 0; | |
1806 | frv_frame_access_multi (&accessor, info, STACK_REGS_GPR); | |
1807 | frv_frame_access_multi (&accessor, info, STACK_REGS_FPR); | |
1808 | frv_frame_access_multi (&accessor, info, STACK_REGS_LCR); | |
b16c1435 | 1809 | } |
36a05131 BS |
1810 | |
1811 | ||
1812 | /* Called after register allocation to add any instructions needed for the | |
1813 | prologue. Using a prologue insn is favored compared to putting all of the | |
b88cf82e KH |
1814 | instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since |
1815 | it allows the scheduler to intermix instructions with the saves of | |
1816 | the caller saved registers. In some cases, it might be necessary | |
1817 | to emit a barrier instruction as the last insn to prevent such | |
1818 | scheduling. | |
36a05131 BS |
1819 | |
1820 | Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1 | |
1821 | so that the debug info generation code can handle them properly. */ | |
1822 | void | |
f2206911 | 1823 | frv_expand_prologue (void) |
36a05131 BS |
1824 | { |
1825 | frv_stack_t *info = frv_stack_info (); | |
1826 | rtx sp = stack_pointer_rtx; | |
1827 | rtx fp = frame_pointer_rtx; | |
1828 | frv_frame_accessor_t accessor; | |
1829 | ||
1830 | if (TARGET_DEBUG_STACK) | |
1831 | frv_debug_stack (info); | |
1832 | ||
1833 | if (info->total_size == 0) | |
1834 | return; | |
1835 | ||
1836 | /* We're interested in three areas of the frame here: | |
1837 | ||
1838 | A: the register save area | |
1839 | B: the old FP | |
1840 | C: the header after B | |
1841 | ||
1842 | If the frame pointer isn't used, we'll have to set up A, B and C | |
1843 | using the stack pointer. If the frame pointer is used, we'll access | |
1844 | them as follows: | |
1845 | ||
1846 | A: set up using sp | |
1847 | B: set up using sp or a temporary (see below) | |
1848 | C: set up using fp | |
1849 | ||
1850 | We set up B using the stack pointer if the frame is small enough. | |
1851 | Otherwise, it's more efficient to copy the old stack pointer into a | |
1852 | temporary and use that. | |
1853 | ||
1854 | Note that it's important to make sure the prologue and epilogue use the | |
1855 | same registers to access A and C, since doing otherwise will confuse | |
1856 | the aliasing code. */ | |
1857 | ||
1858 | /* Set up ACCESSOR for accessing region B above. If the frame pointer | |
1859 | isn't used, the same method will serve for C. */ | |
1860 | accessor.op = FRV_STORE; | |
1861 | if (frame_pointer_needed && info->total_size > 2048) | |
1862 | { | |
1863 | rtx insn; | |
1864 | ||
1865 | accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO); | |
1866 | accessor.base_offset = info->total_size; | |
1867 | insn = emit_insn (gen_movsi (accessor.base, sp)); | |
1868 | } | |
1869 | else | |
1870 | { | |
1871 | accessor.base = stack_pointer_rtx; | |
1872 | accessor.base_offset = 0; | |
1873 | } | |
1874 | ||
1875 | /* Allocate the stack space. */ | |
1876 | { | |
1877 | rtx asm_offset = frv_frame_offset_rtx (-info->total_size); | |
1878 | rtx dwarf_offset = GEN_INT (-info->total_size); | |
1879 | ||
1880 | frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset), | |
1881 | gen_rtx_SET (Pmode, | |
1882 | sp, | |
1883 | gen_rtx_PLUS (Pmode, sp, dwarf_offset))); | |
1884 | } | |
1885 | ||
1886 | /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET) | |
1887 | and point the new one to that location. */ | |
1888 | if (frame_pointer_needed) | |
1889 | { | |
1890 | int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM]; | |
1891 | ||
1892 | /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is | |
1893 | based on ACCESSOR.BASE but DWARF_SRC is always based on the stack | |
1894 | pointer. */ | |
1895 | rtx asm_src = plus_constant (accessor.base, | |
1896 | fp_offset - accessor.base_offset); | |
1897 | rtx dwarf_src = plus_constant (sp, fp_offset); | |
1898 | ||
1899 | /* Store the old frame pointer at (sp + FP_OFFSET). */ | |
1900 | frv_frame_access (&accessor, fp, fp_offset); | |
1901 | ||
1902 | /* Set up the new frame pointer. */ | |
1903 | frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src), | |
1904 | gen_rtx_SET (VOIDmode, fp, dwarf_src)); | |
1905 | ||
1906 | /* Access region C from the frame pointer. */ | |
1907 | accessor.base = fp; | |
1908 | accessor.base_offset = fp_offset; | |
1909 | } | |
1910 | ||
1911 | /* Set up region C. */ | |
1912 | frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT); | |
1913 | frv_frame_access_multi (&accessor, info, STACK_REGS_LR); | |
1914 | frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG); | |
1915 | ||
1916 | /* Set up region A. */ | |
1917 | frv_frame_access_standard_regs (FRV_STORE, info); | |
1918 | ||
1919 | /* If this is a varargs/stdarg function, issue a blockage to prevent the | |
1920 | scheduler from moving loads before the stores saving the registers. */ | |
1921 | if (info->stdarg_size > 0) | |
1922 | emit_insn (gen_blockage ()); | |
1923 | ||
87b483a1 | 1924 | /* Set up pic register/small data register for this function. */ |
ad516a74 | 1925 | if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table) |
36a05131 BS |
1926 | emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO), |
1927 | gen_rtx_REG (Pmode, LR_REGNO), | |
1928 | gen_rtx_REG (SImode, OFFSET_REGNO))); | |
1929 | } | |
1930 | ||
1931 | \f | |
1932 | /* Under frv, all of the work is done via frv_expand_epilogue, but | |
839a4992 | 1933 | this function provides a convenient place to do cleanup. */ |
36a05131 BS |
1934 | |
1935 | static void | |
f2206911 KC |
1936 | frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED, |
1937 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
36a05131 BS |
1938 | { |
1939 | frv_stack_cache = (frv_stack_t *)0; | |
1940 | ||
87b483a1 | 1941 | /* Zap last used registers for conditional execution. */ |
fad205ff | 1942 | memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg)); |
36a05131 | 1943 | |
87b483a1 | 1944 | /* Release the bitmap of created insns. */ |
7b210806 | 1945 | BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap); |
36a05131 BS |
1946 | } |
1947 | ||
1948 | \f | |
1949 | /* Called after register allocation to add any instructions needed for the | |
43aa4e05 | 1950 | epilogue. Using an epilogue insn is favored compared to putting all of the |
b88cf82e KH |
1951 | instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since |
1952 | it allows the scheduler to intermix instructions with the saves of | |
1953 | the caller saved registers. In some cases, it might be necessary | |
1954 | to emit a barrier instruction as the last insn to prevent such | |
c557edf4 | 1955 | scheduling. */ |
36a05131 BS |
1956 | |
1957 | void | |
764678d1 | 1958 | frv_expand_epilogue (bool emit_return) |
36a05131 BS |
1959 | { |
1960 | frv_stack_t *info = frv_stack_info (); | |
1961 | rtx fp = frame_pointer_rtx; | |
1962 | rtx sp = stack_pointer_rtx; | |
1963 | rtx return_addr; | |
1964 | int fp_offset; | |
1965 | ||
1966 | fp_offset = info->reg_offset[FRAME_POINTER_REGNUM]; | |
1967 | ||
1968 | /* Restore the stack pointer to its original value if alloca or the like | |
1969 | is used. */ | |
1970 | if (! current_function_sp_is_unchanging) | |
1971 | emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset))); | |
1972 | ||
1973 | /* Restore the callee-saved registers that were used in this function. */ | |
1974 | frv_frame_access_standard_regs (FRV_LOAD, info); | |
1975 | ||
1976 | /* Set RETURN_ADDR to the address we should return to. Set it to NULL if | |
1977 | no return instruction should be emitted. */ | |
764678d1 | 1978 | if (info->save_p[LR_REGNO]) |
36a05131 BS |
1979 | { |
1980 | int lr_offset; | |
1981 | rtx mem; | |
1982 | ||
1983 | /* Use the same method to access the link register's slot as we did in | |
1984 | the prologue. In other words, use the frame pointer if available, | |
1985 | otherwise use the stack pointer. | |
1986 | ||
1987 | LR_OFFSET is the offset of the link register's slot from the start | |
1988 | of the frame and MEM is a memory rtx for it. */ | |
1989 | lr_offset = info->reg_offset[LR_REGNO]; | |
1990 | if (frame_pointer_needed) | |
1991 | mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset); | |
1992 | else | |
1993 | mem = frv_frame_mem (Pmode, sp, lr_offset); | |
1994 | ||
1995 | /* Load the old link register into a GPR. */ | |
1996 | return_addr = gen_rtx_REG (Pmode, TEMP_REGNO); | |
1997 | emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem)); | |
1998 | } | |
1999 | else | |
2000 | return_addr = gen_rtx_REG (Pmode, LR_REGNO); | |
2001 | ||
2002 | /* Restore the old frame pointer. Emit a USE afterwards to make sure | |
2003 | the load is preserved. */ | |
2004 | if (frame_pointer_needed) | |
2005 | { | |
2006 | emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp))); | |
c41c1387 | 2007 | emit_use (fp); |
36a05131 BS |
2008 | } |
2009 | ||
2010 | /* Deallocate the stack frame. */ | |
2011 | if (info->total_size != 0) | |
2012 | { | |
2013 | rtx offset = frv_frame_offset_rtx (info->total_size); | |
2014 | emit_insn (gen_stack_adjust (sp, sp, offset)); | |
2015 | } | |
2016 | ||
2017 | /* If this function uses eh_return, add the final stack adjustment now. */ | |
e3b5732b | 2018 | if (crtl->calls_eh_return) |
36a05131 BS |
2019 | emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX)); |
2020 | ||
764678d1 | 2021 | if (emit_return) |
36a05131 | 2022 | emit_jump_insn (gen_epilogue_return (return_addr)); |
764678d1 AO |
2023 | else |
2024 | { | |
2025 | rtx lr = return_addr; | |
2026 | ||
2027 | if (REGNO (return_addr) != LR_REGNO) | |
2028 | { | |
2029 | lr = gen_rtx_REG (Pmode, LR_REGNO); | |
2030 | emit_move_insn (lr, return_addr); | |
2031 | } | |
2032 | ||
c41c1387 | 2033 | emit_use (lr); |
764678d1 | 2034 | } |
36a05131 BS |
2035 | } |
2036 | ||
2037 | \f | |
b88cf82e | 2038 | /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */ |
36a05131 | 2039 | |
c590b625 | 2040 | static void |
f2206911 KC |
2041 | frv_asm_output_mi_thunk (FILE *file, |
2042 | tree thunk_fndecl ATTRIBUTE_UNUSED, | |
2043 | HOST_WIDE_INT delta, | |
2044 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
2045 | tree function) | |
36a05131 BS |
2046 | { |
2047 | const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0); | |
2048 | const char *name_arg0 = reg_names[FIRST_ARG_REGNUM]; | |
2049 | const char *name_jmp = reg_names[JUMP_REGNO]; | |
c557edf4 | 2050 | const char *parallel = (frv_issue_rate () > 1 ? ".p" : ""); |
36a05131 | 2051 | |
87b483a1 | 2052 | /* Do the add using an addi if possible. */ |
36a05131 | 2053 | if (IN_RANGE_P (delta, -2048, 2047)) |
eb0424da | 2054 | fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0); |
36a05131 BS |
2055 | else |
2056 | { | |
4a0a75dd KG |
2057 | const char *const name_add = reg_names[TEMP_REGNO]; |
2058 | fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n", | |
2059 | parallel, delta, name_add); | |
2060 | fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n", | |
2061 | delta, name_add); | |
36a05131 BS |
2062 | fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0); |
2063 | } | |
2064 | ||
34208acf AO |
2065 | if (TARGET_FDPIC) |
2066 | { | |
2067 | const char *name_pic = reg_names[FDPIC_REGNO]; | |
2068 | name_jmp = reg_names[FDPIC_FPTR_REGNO]; | |
2069 | ||
2070 | if (flag_pic != 1) | |
2071 | { | |
2072 | fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel); | |
2073 | assemble_name (file, name_func); | |
2074 | fprintf (file, "),%s\n", name_jmp); | |
2075 | ||
2076 | fprintf (file, "\tsetlo #gotofffuncdesclo("); | |
2077 | assemble_name (file, name_func); | |
2078 | fprintf (file, "),%s\n", name_jmp); | |
2079 | ||
2080 | fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp); | |
2081 | } | |
2082 | else | |
2083 | { | |
2084 | fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic); | |
2085 | assemble_name (file, name_func); | |
2086 | fprintf (file, "\t)), %s\n", name_jmp); | |
2087 | } | |
2088 | } | |
2089 | else if (!flag_pic) | |
36a05131 BS |
2090 | { |
2091 | fprintf (file, "\tsethi%s #hi(", parallel); | |
2092 | assemble_name (file, name_func); | |
2093 | fprintf (file, "),%s\n", name_jmp); | |
2094 | ||
2095 | fprintf (file, "\tsetlo #lo("); | |
2096 | assemble_name (file, name_func); | |
2097 | fprintf (file, "),%s\n", name_jmp); | |
2098 | } | |
2099 | else | |
2100 | { | |
2101 | /* Use JUMP_REGNO as a temporary PIC register. */ | |
2102 | const char *name_lr = reg_names[LR_REGNO]; | |
2103 | const char *name_gppic = name_jmp; | |
2104 | const char *name_tmp = reg_names[TEMP_REGNO]; | |
2105 | ||
2106 | fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp); | |
2107 | fprintf (file, "\tcall 1f\n"); | |
2108 | fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic); | |
2109 | fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr); | |
2110 | fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp); | |
2111 | fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp); | |
2112 | fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic); | |
2113 | ||
2114 | fprintf (file, "\tsethi%s #gprelhi(", parallel); | |
2115 | assemble_name (file, name_func); | |
2116 | fprintf (file, "),%s\n", name_tmp); | |
2117 | ||
2118 | fprintf (file, "\tsetlo #gprello("); | |
2119 | assemble_name (file, name_func); | |
2120 | fprintf (file, "),%s\n", name_tmp); | |
2121 | ||
2122 | fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp); | |
2123 | } | |
2124 | ||
87b483a1 | 2125 | /* Jump to the function address. */ |
36a05131 BS |
2126 | fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]); |
2127 | } | |
2128 | ||
2129 | \f | |
36a05131 | 2130 | |
87b483a1 | 2131 | /* On frv, create a frame whenever we need to create stack. */ |
36a05131 | 2132 | |
b52b1749 | 2133 | static bool |
f2206911 | 2134 | frv_frame_pointer_required (void) |
36a05131 | 2135 | { |
34208acf AO |
2136 | /* If we forgoing the usual linkage requirements, we only need |
2137 | a frame pointer if the stack pointer might change. */ | |
2138 | if (!TARGET_LINKED_FP) | |
2139 | return !current_function_sp_is_unchanging; | |
2140 | ||
36a05131 | 2141 | if (! current_function_is_leaf) |
b52b1749 | 2142 | return true; |
36a05131 BS |
2143 | |
2144 | if (get_frame_size () != 0) | |
b52b1749 | 2145 | return true; |
36a05131 BS |
2146 | |
2147 | if (cfun->stdarg) | |
b52b1749 | 2148 | return true; |
36a05131 BS |
2149 | |
2150 | if (!current_function_sp_is_unchanging) | |
b52b1749 | 2151 | return true; |
36a05131 | 2152 | |
ad516a74 | 2153 | if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table) |
b52b1749 | 2154 | return true; |
36a05131 BS |
2155 | |
2156 | if (profile_flag) | |
b52b1749 | 2157 | return true; |
36a05131 BS |
2158 | |
2159 | if (cfun->machine->frame_needed) | |
b52b1749 | 2160 | return true; |
36a05131 | 2161 | |
b52b1749 | 2162 | return false; |
36a05131 BS |
2163 | } |
2164 | ||
2165 | \f | |
7b5cbb57 AS |
2166 | /* Worker function for TARGET_CAN_ELIMINATE. */ |
2167 | ||
2168 | bool | |
2169 | frv_can_eliminate (const int from, const int to) | |
2170 | { | |
2171 | return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM | |
2172 | ? ! frame_pointer_needed | |
2173 | : true); | |
2174 | } | |
2175 | ||
36a05131 BS |
2176 | /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the |
2177 | initial difference between the specified pair of registers. This macro must | |
2178 | be defined if `ELIMINABLE_REGS' is defined. */ | |
2179 | ||
2180 | /* See frv_stack_info for more details on the frv stack frame. */ | |
2181 | ||
2182 | int | |
f2206911 | 2183 | frv_initial_elimination_offset (int from, int to) |
36a05131 BS |
2184 | { |
2185 | frv_stack_t *info = frv_stack_info (); | |
2186 | int ret = 0; | |
2187 | ||
2188 | if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM) | |
2189 | ret = info->total_size - info->pretend_size; | |
2190 | ||
2191 | else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM) | |
88d6a75f | 2192 | ret = info->reg_offset[FRAME_POINTER_REGNUM]; |
36a05131 BS |
2193 | |
2194 | else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM) | |
2195 | ret = (info->total_size | |
2196 | - info->reg_offset[FRAME_POINTER_REGNUM] | |
2197 | - info->pretend_size); | |
2198 | ||
2199 | else | |
44e91694 | 2200 | gcc_unreachable (); |
36a05131 BS |
2201 | |
2202 | if (TARGET_DEBUG_STACK) | |
2203 | fprintf (stderr, "Eliminate %s to %s by adding %d\n", | |
2204 | reg_names [from], reg_names[to], ret); | |
2205 | ||
2206 | return ret; | |
2207 | } | |
2208 | ||
2209 | \f | |
d8c2bed3 | 2210 | /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */ |
36a05131 | 2211 | |
d8c2bed3 | 2212 | static void |
f2206911 KC |
2213 | frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum, |
2214 | enum machine_mode mode, | |
2215 | tree type ATTRIBUTE_UNUSED, | |
2216 | int *pretend_size, | |
2217 | int second_time) | |
36a05131 BS |
2218 | { |
2219 | if (TARGET_DEBUG_ARG) | |
2220 | fprintf (stderr, | |
2221 | "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n", | |
2222 | *cum, GET_MODE_NAME (mode), *pretend_size, second_time); | |
2223 | } | |
2224 | ||
2225 | \f | |
b88cf82e | 2226 | /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */ |
36a05131 | 2227 | |
8ac411c7 | 2228 | static rtx |
f2206911 | 2229 | frv_expand_builtin_saveregs (void) |
36a05131 BS |
2230 | { |
2231 | int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS; | |
2232 | ||
2233 | if (TARGET_DEBUG_ARG) | |
2234 | fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n", | |
2235 | offset); | |
2236 | ||
f1c25d3b | 2237 | return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset)); |
36a05131 BS |
2238 | } |
2239 | ||
2240 | \f | |
2241 | /* Expand __builtin_va_start to do the va_start macro. */ | |
2242 | ||
d7bd8aeb | 2243 | static void |
f2206911 | 2244 | frv_expand_builtin_va_start (tree valist, rtx nextarg) |
36a05131 BS |
2245 | { |
2246 | tree t; | |
7dd68986 | 2247 | int num = crtl->args.info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS; |
36a05131 BS |
2248 | |
2249 | nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, | |
2250 | GEN_INT (UNITS_PER_WORD * num)); | |
2251 | ||
2252 | if (TARGET_DEBUG_ARG) | |
2253 | { | |
2254 | fprintf (stderr, "va_start: args_info = %d, num = %d\n", | |
7dd68986 | 2255 | crtl->args.info, num); |
36a05131 BS |
2256 | |
2257 | debug_rtx (nextarg); | |
2258 | } | |
2259 | ||
726a989a | 2260 | t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, |
5be014d5 AP |
2261 | fold_convert (TREE_TYPE (valist), |
2262 | make_tree (sizetype, nextarg))); | |
36a05131 BS |
2263 | TREE_SIDE_EFFECTS (t) = 1; |
2264 | ||
2265 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2266 | } | |
2267 | ||
36a05131 BS |
2268 | \f |
2269 | /* Expand a block move operation, and return 1 if successful. Return 0 | |
2270 | if we should let the compiler generate normal code. | |
2271 | ||
2272 | operands[0] is the destination | |
2273 | operands[1] is the source | |
2274 | operands[2] is the length | |
2275 | operands[3] is the alignment */ | |
2276 | ||
2277 | /* Maximum number of loads to do before doing the stores */ | |
2278 | #ifndef MAX_MOVE_REG | |
2279 | #define MAX_MOVE_REG 4 | |
2280 | #endif | |
2281 | ||
2282 | /* Maximum number of total loads to do. */ | |
2283 | #ifndef TOTAL_MOVE_REG | |
2284 | #define TOTAL_MOVE_REG 8 | |
2285 | #endif | |
2286 | ||
2287 | int | |
f2206911 | 2288 | frv_expand_block_move (rtx operands[]) |
36a05131 BS |
2289 | { |
2290 | rtx orig_dest = operands[0]; | |
2291 | rtx orig_src = operands[1]; | |
2292 | rtx bytes_rtx = operands[2]; | |
2293 | rtx align_rtx = operands[3]; | |
2294 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); | |
2295 | int align; | |
2296 | int bytes; | |
2297 | int offset; | |
2298 | int num_reg; | |
2299 | int i; | |
2300 | rtx src_reg; | |
2301 | rtx dest_reg; | |
2302 | rtx src_addr; | |
2303 | rtx dest_addr; | |
2304 | rtx src_mem; | |
2305 | rtx dest_mem; | |
2306 | rtx tmp_reg; | |
2307 | rtx stores[MAX_MOVE_REG]; | |
2308 | int move_bytes; | |
2309 | enum machine_mode mode; | |
2310 | ||
87b483a1 | 2311 | /* If this is not a fixed size move, just call memcpy. */ |
36a05131 BS |
2312 | if (! constp) |
2313 | return FALSE; | |
2314 | ||
44e91694 NS |
2315 | /* This should be a fixed size alignment. */ |
2316 | gcc_assert (GET_CODE (align_rtx) == CONST_INT); | |
36a05131 BS |
2317 | |
2318 | align = INTVAL (align_rtx); | |
2319 | ||
2320 | /* Anything to move? */ | |
2321 | bytes = INTVAL (bytes_rtx); | |
2322 | if (bytes <= 0) | |
2323 | return TRUE; | |
2324 | ||
2325 | /* Don't support real large moves. */ | |
2326 | if (bytes > TOTAL_MOVE_REG*align) | |
2327 | return FALSE; | |
2328 | ||
2329 | /* Move the address into scratch registers. */ | |
2330 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); | |
2331 | src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); | |
2332 | ||
2333 | num_reg = offset = 0; | |
2334 | for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) | |
2335 | { | |
87b483a1 | 2336 | /* Calculate the correct offset for src/dest. */ |
36a05131 BS |
2337 | if (offset == 0) |
2338 | { | |
2339 | src_addr = src_reg; | |
2340 | dest_addr = dest_reg; | |
2341 | } | |
2342 | else | |
2343 | { | |
2344 | src_addr = plus_constant (src_reg, offset); | |
2345 | dest_addr = plus_constant (dest_reg, offset); | |
2346 | } | |
2347 | ||
2348 | /* Generate the appropriate load and store, saving the stores | |
2349 | for later. */ | |
2350 | if (bytes >= 4 && align >= 4) | |
2351 | mode = SImode; | |
2352 | else if (bytes >= 2 && align >= 2) | |
2353 | mode = HImode; | |
2354 | else | |
2355 | mode = QImode; | |
2356 | ||
2357 | move_bytes = GET_MODE_SIZE (mode); | |
2358 | tmp_reg = gen_reg_rtx (mode); | |
2359 | src_mem = change_address (orig_src, mode, src_addr); | |
2360 | dest_mem = change_address (orig_dest, mode, dest_addr); | |
2361 | emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem)); | |
2362 | stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg); | |
2363 | ||
2364 | if (num_reg >= MAX_MOVE_REG) | |
2365 | { | |
2366 | for (i = 0; i < num_reg; i++) | |
2367 | emit_insn (stores[i]); | |
2368 | num_reg = 0; | |
2369 | } | |
2370 | } | |
2371 | ||
2372 | for (i = 0; i < num_reg; i++) | |
2373 | emit_insn (stores[i]); | |
2374 | ||
2375 | return TRUE; | |
2376 | } | |
2377 | ||
2378 | \f | |
2379 | /* Expand a block clear operation, and return 1 if successful. Return 0 | |
2380 | if we should let the compiler generate normal code. | |
2381 | ||
2382 | operands[0] is the destination | |
2383 | operands[1] is the length | |
57e84f18 | 2384 | operands[3] is the alignment */ |
36a05131 BS |
2385 | |
2386 | int | |
f2206911 | 2387 | frv_expand_block_clear (rtx operands[]) |
36a05131 BS |
2388 | { |
2389 | rtx orig_dest = operands[0]; | |
2390 | rtx bytes_rtx = operands[1]; | |
57e84f18 | 2391 | rtx align_rtx = operands[3]; |
36a05131 BS |
2392 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
2393 | int align; | |
2394 | int bytes; | |
2395 | int offset; | |
2396 | int num_reg; | |
2397 | rtx dest_reg; | |
2398 | rtx dest_addr; | |
2399 | rtx dest_mem; | |
2400 | int clear_bytes; | |
2401 | enum machine_mode mode; | |
2402 | ||
87b483a1 | 2403 | /* If this is not a fixed size move, just call memcpy. */ |
36a05131 BS |
2404 | if (! constp) |
2405 | return FALSE; | |
2406 | ||
44e91694 NS |
2407 | /* This should be a fixed size alignment. */ |
2408 | gcc_assert (GET_CODE (align_rtx) == CONST_INT); | |
36a05131 BS |
2409 | |
2410 | align = INTVAL (align_rtx); | |
2411 | ||
2412 | /* Anything to move? */ | |
2413 | bytes = INTVAL (bytes_rtx); | |
2414 | if (bytes <= 0) | |
2415 | return TRUE; | |
2416 | ||
2417 | /* Don't support real large clears. */ | |
2418 | if (bytes > TOTAL_MOVE_REG*align) | |
2419 | return FALSE; | |
2420 | ||
2421 | /* Move the address into a scratch register. */ | |
2422 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); | |
2423 | ||
2424 | num_reg = offset = 0; | |
2425 | for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes)) | |
2426 | { | |
87b483a1 | 2427 | /* Calculate the correct offset for src/dest. */ |
36a05131 BS |
2428 | dest_addr = ((offset == 0) |
2429 | ? dest_reg | |
2430 | : plus_constant (dest_reg, offset)); | |
2431 | ||
87b483a1 | 2432 | /* Generate the appropriate store of gr0. */ |
36a05131 BS |
2433 | if (bytes >= 4 && align >= 4) |
2434 | mode = SImode; | |
2435 | else if (bytes >= 2 && align >= 2) | |
2436 | mode = HImode; | |
2437 | else | |
2438 | mode = QImode; | |
2439 | ||
2440 | clear_bytes = GET_MODE_SIZE (mode); | |
2441 | dest_mem = change_address (orig_dest, mode, dest_addr); | |
2442 | emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx)); | |
2443 | } | |
2444 | ||
2445 | return TRUE; | |
2446 | } | |
2447 | ||
2448 | \f | |
2449 | /* The following variable is used to output modifiers of assembler | |
87b483a1 | 2450 | code of the current output insn. */ |
36a05131 BS |
2451 | |
2452 | static rtx *frv_insn_operands; | |
2453 | ||
2454 | /* The following function is used to add assembler insn code suffix .p | |
87b483a1 | 2455 | if it is necessary. */ |
36a05131 BS |
2456 | |
2457 | const char * | |
f2206911 | 2458 | frv_asm_output_opcode (FILE *f, const char *ptr) |
36a05131 BS |
2459 | { |
2460 | int c; | |
2461 | ||
c557edf4 | 2462 | if (frv_insn_packing_flag <= 0) |
36a05131 BS |
2463 | return ptr; |
2464 | ||
2465 | for (; *ptr && *ptr != ' ' && *ptr != '\t';) | |
2466 | { | |
2467 | c = *ptr++; | |
2468 | if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z') | |
2469 | || (*ptr >= 'A' && *ptr <= 'Z'))) | |
2470 | { | |
2471 | int letter = *ptr++; | |
2472 | ||
2473 | c = atoi (ptr); | |
2474 | frv_print_operand (f, frv_insn_operands [c], letter); | |
2475 | while ((c = *ptr) >= '0' && c <= '9') | |
2476 | ptr++; | |
2477 | } | |
2478 | else | |
2479 | fputc (c, f); | |
2480 | } | |
2481 | ||
c557edf4 | 2482 | fprintf (f, ".p"); |
36a05131 BS |
2483 | |
2484 | return ptr; | |
2485 | } | |
2486 | ||
c557edf4 RS |
2487 | /* Set up the packing bit for the current output insn. Note that this |
2488 | function is not called for asm insns. */ | |
36a05131 BS |
2489 | |
2490 | void | |
c557edf4 RS |
2491 | frv_final_prescan_insn (rtx insn, rtx *opvec, |
2492 | int noperands ATTRIBUTE_UNUSED) | |
36a05131 | 2493 | { |
c557edf4 | 2494 | if (INSN_P (insn)) |
36a05131 | 2495 | { |
c557edf4 RS |
2496 | if (frv_insn_packing_flag >= 0) |
2497 | { | |
2498 | frv_insn_operands = opvec; | |
2499 | frv_insn_packing_flag = PACKING_FLAG_P (insn); | |
2500 | } | |
2501 | else if (recog_memoized (insn) >= 0 | |
2502 | && get_attr_acc_group (insn) == ACC_GROUP_ODD) | |
2503 | /* Packing optimizations have been disabled, but INSN can only | |
2504 | be issued in M1. Insert an mnop in M0. */ | |
2505 | fprintf (asm_out_file, "\tmnop.p\n"); | |
36a05131 | 2506 | } |
36a05131 BS |
2507 | } |
2508 | ||
2509 | ||
2510 | \f | |
2511 | /* A C expression whose value is RTL representing the address in a stack frame | |
2512 | where the pointer to the caller's frame is stored. Assume that FRAMEADDR is | |
2513 | an RTL expression for the address of the stack frame itself. | |
2514 | ||
2515 | If you don't define this macro, the default is to return the value of | |
2516 | FRAMEADDR--that is, the stack frame address is also the address of the stack | |
2517 | word that points to the previous frame. */ | |
2518 | ||
2519 | /* The default is correct, but we need to make sure the frame gets created. */ | |
2520 | rtx | |
f2206911 | 2521 | frv_dynamic_chain_address (rtx frame) |
36a05131 BS |
2522 | { |
2523 | cfun->machine->frame_needed = 1; | |
2524 | return frame; | |
2525 | } | |
2526 | ||
2527 | ||
2528 | /* A C expression whose value is RTL representing the value of the return | |
2529 | address for the frame COUNT steps up from the current frame, after the | |
2530 | prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame | |
2531 | pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is | |
2532 | defined. | |
2533 | ||
2534 | The value of the expression must always be the correct address when COUNT is | |
2535 | zero, but may be `NULL_RTX' if there is not way to determine the return | |
2536 | address of other frames. */ | |
2537 | ||
2538 | rtx | |
34208acf | 2539 | frv_return_addr_rtx (int count, rtx frame) |
36a05131 | 2540 | { |
34208acf AO |
2541 | if (count != 0) |
2542 | return const0_rtx; | |
36a05131 BS |
2543 | cfun->machine->frame_needed = 1; |
2544 | return gen_rtx_MEM (Pmode, plus_constant (frame, 8)); | |
2545 | } | |
2546 | ||
2547 | /* Given a memory reference MEMREF, interpret the referenced memory as | |
2548 | an array of MODE values, and return a reference to the element | |
2549 | specified by INDEX. Assume that any pre-modification implicit in | |
2550 | MEMREF has already happened. | |
2551 | ||
2552 | MEMREF must be a legitimate operand for modes larger than SImode. | |
c6c3dba9 | 2553 | frv_legitimate_address_p forbids register+register addresses, which |
36a05131 BS |
2554 | this function cannot handle. */ |
2555 | rtx | |
f2206911 | 2556 | frv_index_memory (rtx memref, enum machine_mode mode, int index) |
36a05131 BS |
2557 | { |
2558 | rtx base = XEXP (memref, 0); | |
2559 | if (GET_CODE (base) == PRE_MODIFY) | |
2560 | base = XEXP (base, 0); | |
2561 | return change_address (memref, mode, | |
2562 | plus_constant (base, index * GET_MODE_SIZE (mode))); | |
2563 | } | |
2564 | ||
2565 | \f | |
2566 | /* Print a memory address as an operand to reference that memory location. */ | |
0fb30cb7 | 2567 | static void |
f2206911 | 2568 | frv_print_operand_address (FILE * stream, rtx x) |
36a05131 BS |
2569 | { |
2570 | if (GET_CODE (x) == MEM) | |
2571 | x = XEXP (x, 0); | |
2572 | ||
2573 | switch (GET_CODE (x)) | |
2574 | { | |
2575 | case REG: | |
2576 | fputs (reg_names [ REGNO (x)], stream); | |
2577 | return; | |
2578 | ||
2579 | case CONST_INT: | |
2580 | fprintf (stream, "%ld", (long) INTVAL (x)); | |
2581 | return; | |
2582 | ||
2583 | case SYMBOL_REF: | |
2584 | assemble_name (stream, XSTR (x, 0)); | |
2585 | return; | |
2586 | ||
2587 | case LABEL_REF: | |
2588 | case CONST: | |
2589 | output_addr_const (stream, x); | |
2590 | return; | |
2591 | ||
8d8256c1 NC |
2592 | case PLUS: |
2593 | /* Poorly constructed asm statements can trigger this alternative. | |
2594 | See gcc/testsuite/gcc.dg/asm-4.c for an example. */ | |
2595 | frv_print_operand_memory_reference (stream, x, 0); | |
2596 | return; | |
2597 | ||
36a05131 BS |
2598 | default: |
2599 | break; | |
2600 | } | |
2601 | ||
ab532386 | 2602 | fatal_insn ("bad insn to frv_print_operand_address:", x); |
36a05131 BS |
2603 | } |
2604 | ||
2605 | \f | |
2606 | static void | |
f2206911 | 2607 | frv_print_operand_memory_reference_reg (FILE * stream, rtx x) |
36a05131 BS |
2608 | { |
2609 | int regno = true_regnum (x); | |
2610 | if (GPR_P (regno)) | |
2611 | fputs (reg_names[regno], stream); | |
2612 | else | |
ab532386 | 2613 | fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x); |
36a05131 BS |
2614 | } |
2615 | ||
2616 | /* Print a memory reference suitable for the ld/st instructions. */ | |
2617 | ||
2618 | static void | |
f2206911 | 2619 | frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset) |
36a05131 | 2620 | { |
34208acf | 2621 | struct frv_unspec unspec; |
36a05131 BS |
2622 | rtx x0 = NULL_RTX; |
2623 | rtx x1 = NULL_RTX; | |
2624 | ||
2625 | switch (GET_CODE (x)) | |
2626 | { | |
2627 | case SUBREG: | |
2628 | case REG: | |
2629 | x0 = x; | |
2630 | break; | |
2631 | ||
2632 | case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */ | |
2633 | x0 = XEXP (x, 0); | |
2634 | x1 = XEXP (XEXP (x, 1), 1); | |
2635 | break; | |
2636 | ||
2637 | case CONST_INT: | |
2638 | x1 = x; | |
2639 | break; | |
2640 | ||
2641 | case PLUS: | |
2642 | x0 = XEXP (x, 0); | |
2643 | x1 = XEXP (x, 1); | |
2644 | if (GET_CODE (x0) == CONST_INT) | |
2645 | { | |
2646 | x0 = XEXP (x, 1); | |
2647 | x1 = XEXP (x, 0); | |
2648 | } | |
2649 | break; | |
2650 | ||
2651 | default: | |
ab532386 | 2652 | fatal_insn ("bad insn to frv_print_operand_memory_reference:", x); |
36a05131 BS |
2653 | break; |
2654 | ||
2655 | } | |
2656 | ||
2657 | if (addr_offset) | |
2658 | { | |
2659 | if (!x1) | |
2660 | x1 = const0_rtx; | |
2661 | else if (GET_CODE (x1) != CONST_INT) | |
ab532386 | 2662 | fatal_insn ("bad insn to frv_print_operand_memory_reference:", x); |
36a05131 BS |
2663 | } |
2664 | ||
2665 | fputs ("@(", stream); | |
2666 | if (!x0) | |
2667 | fputs (reg_names[GPR_R0], stream); | |
2668 | else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG) | |
2669 | frv_print_operand_memory_reference_reg (stream, x0); | |
2670 | else | |
ab532386 | 2671 | fatal_insn ("bad insn to frv_print_operand_memory_reference:", x); |
36a05131 BS |
2672 | |
2673 | fputs (",", stream); | |
2674 | if (!x1) | |
2675 | fputs (reg_names [GPR_R0], stream); | |
2676 | ||
2677 | else | |
2678 | { | |
2679 | switch (GET_CODE (x1)) | |
2680 | { | |
2681 | case SUBREG: | |
2682 | case REG: | |
2683 | frv_print_operand_memory_reference_reg (stream, x1); | |
2684 | break; | |
2685 | ||
2686 | case CONST_INT: | |
2687 | fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset)); | |
2688 | break; | |
2689 | ||
36a05131 | 2690 | case CONST: |
34208acf | 2691 | if (!frv_const_unspec_p (x1, &unspec)) |
ab532386 | 2692 | fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1); |
34208acf | 2693 | frv_output_const_unspec (stream, &unspec); |
36a05131 BS |
2694 | break; |
2695 | ||
2696 | default: | |
ab532386 | 2697 | fatal_insn ("bad insn to frv_print_operand_memory_reference:", x); |
36a05131 BS |
2698 | } |
2699 | } | |
2700 | ||
2701 | fputs (")", stream); | |
2702 | } | |
2703 | ||
2704 | \f | |
2705 | /* Return 2 for likely branches and 0 for non-likely branches */ | |
2706 | ||
2707 | #define FRV_JUMP_LIKELY 2 | |
2708 | #define FRV_JUMP_NOT_LIKELY 0 | |
2709 | ||
2710 | static int | |
f2206911 | 2711 | frv_print_operand_jump_hint (rtx insn) |
36a05131 BS |
2712 | { |
2713 | rtx note; | |
2714 | rtx labelref; | |
2715 | int ret; | |
2716 | HOST_WIDE_INT prob = -1; | |
2717 | enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN; | |
2718 | ||
44e91694 | 2719 | gcc_assert (GET_CODE (insn) == JUMP_INSN); |
36a05131 BS |
2720 | |
2721 | /* Assume any non-conditional jump is likely. */ | |
2722 | if (! any_condjump_p (insn)) | |
2723 | ret = FRV_JUMP_LIKELY; | |
2724 | ||
2725 | else | |
2726 | { | |
2727 | labelref = condjump_label (insn); | |
2728 | if (labelref) | |
2729 | { | |
2730 | rtx label = XEXP (labelref, 0); | |
2731 | jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label)) | |
2732 | ? BACKWARD | |
2733 | : FORWARD); | |
2734 | } | |
2735 | ||
2736 | note = find_reg_note (insn, REG_BR_PROB, 0); | |
2737 | if (!note) | |
2738 | ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY); | |
2739 | ||
2740 | else | |
2741 | { | |
2742 | prob = INTVAL (XEXP (note, 0)); | |
2743 | ret = ((prob >= (REG_BR_PROB_BASE / 2)) | |
2744 | ? FRV_JUMP_LIKELY | |
2745 | : FRV_JUMP_NOT_LIKELY); | |
2746 | } | |
2747 | } | |
2748 | ||
2749 | #if 0 | |
2750 | if (TARGET_DEBUG) | |
2751 | { | |
2752 | char *direction; | |
2753 | ||
2754 | switch (jump_type) | |
2755 | { | |
2756 | default: | |
2757 | case UNKNOWN: direction = "unknown jump direction"; break; | |
2758 | case BACKWARD: direction = "jump backward"; break; | |
2759 | case FORWARD: direction = "jump forward"; break; | |
2760 | } | |
2761 | ||
2762 | fprintf (stderr, | |
2763 | "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n", | |
2764 | IDENTIFIER_POINTER (DECL_NAME (current_function_decl)), | |
2765 | (long)INSN_UID (insn), direction, (long)prob, | |
2766 | (long)REG_BR_PROB_BASE, ret); | |
2767 | } | |
2768 | #endif | |
2769 | ||
2770 | return ret; | |
2771 | } | |
2772 | ||
2773 | \f | |
036ff63f RS |
2774 | /* Return the comparison operator to use for CODE given that the ICC |
2775 | register is OP0. */ | |
2776 | ||
2777 | static const char * | |
2778 | comparison_string (enum rtx_code code, rtx op0) | |
2779 | { | |
2780 | bool is_nz_p = GET_MODE (op0) == CC_NZmode; | |
2781 | switch (code) | |
2782 | { | |
2783 | default: output_operand_lossage ("bad condition code"); | |
2784 | case EQ: return "eq"; | |
2785 | case NE: return "ne"; | |
2786 | case LT: return is_nz_p ? "n" : "lt"; | |
2787 | case LE: return "le"; | |
2788 | case GT: return "gt"; | |
2789 | case GE: return is_nz_p ? "p" : "ge"; | |
2790 | case LTU: return is_nz_p ? "no" : "c"; | |
2791 | case LEU: return is_nz_p ? "eq" : "ls"; | |
2792 | case GTU: return is_nz_p ? "ne" : "hi"; | |
2793 | case GEU: return is_nz_p ? "ra" : "nc"; | |
2794 | } | |
2795 | } | |
2796 | ||
43aa4e05 | 2797 | /* Print an operand to an assembler instruction. |
36a05131 BS |
2798 | |
2799 | `%' followed by a letter and a digit says to output an operand in an | |
0fb30cb7 NF |
2800 | alternate fashion. Four letters have standard, built-in meanings |
2801 | described below. The hook `TARGET_PRINT_OPERAND' can define | |
2802 | additional letters with nonstandard meanings. | |
36a05131 BS |
2803 | |
2804 | `%cDIGIT' can be used to substitute an operand that is a constant value | |
2805 | without the syntax that normally indicates an immediate operand. | |
2806 | ||
2807 | `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated | |
2808 | before printing. | |
2809 | ||
2810 | `%aDIGIT' can be used to substitute an operand as if it were a memory | |
2811 | reference, with the actual operand treated as the address. This may be | |
2812 | useful when outputting a "load address" instruction, because often the | |
2813 | assembler syntax for such an instruction requires you to write the operand | |
2814 | as if it were a memory reference. | |
2815 | ||
2816 | `%lDIGIT' is used to substitute a `label_ref' into a jump instruction. | |
2817 | ||
2818 | `%=' outputs a number which is unique to each instruction in the entire | |
2819 | compilation. This is useful for making local labels to be referred to more | |
2820 | than once in a single template that generates multiple assembler | |
2821 | instructions. | |
2822 | ||
0fb30cb7 NF |
2823 | `%' followed by a punctuation character specifies a substitution that |
2824 | does not use an operand. Only one case is standard: `%%' outputs a | |
2825 | `%' into the assembler code. Other nonstandard cases can be defined | |
2826 | in the `TARGET_PRINT_OPERAND' hook. You must also define which | |
2827 | punctuation characters are valid with the | |
2828 | `TARGET_PRINT_OPERAND_PUNCT_VALID_P' hook. */ | |
36a05131 | 2829 | |
0fb30cb7 | 2830 | static void |
f2206911 | 2831 | frv_print_operand (FILE * file, rtx x, int code) |
36a05131 | 2832 | { |
34208acf | 2833 | struct frv_unspec unspec; |
36a05131 BS |
2834 | HOST_WIDE_INT value; |
2835 | int offset; | |
2836 | ||
0a2aaacc | 2837 | if (code != 0 && !ISALPHA (code)) |
36a05131 BS |
2838 | value = 0; |
2839 | ||
2840 | else if (GET_CODE (x) == CONST_INT) | |
2841 | value = INTVAL (x); | |
2842 | ||
2843 | else if (GET_CODE (x) == CONST_DOUBLE) | |
2844 | { | |
2845 | if (GET_MODE (x) == SFmode) | |
2846 | { | |
2847 | REAL_VALUE_TYPE rv; | |
2848 | long l; | |
2849 | ||
2850 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
2851 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
2852 | value = l; | |
2853 | } | |
2854 | ||
2855 | else if (GET_MODE (x) == VOIDmode) | |
2856 | value = CONST_DOUBLE_LOW (x); | |
2857 | ||
2858 | else | |
ab532386 | 2859 | fatal_insn ("bad insn in frv_print_operand, bad const_double", x); |
36a05131 BS |
2860 | } |
2861 | ||
2862 | else | |
2863 | value = 0; | |
2864 | ||
2865 | switch (code) | |
2866 | { | |
2867 | ||
2868 | case '.': | |
87b483a1 | 2869 | /* Output r0. */ |
36a05131 BS |
2870 | fputs (reg_names[GPR_R0], file); |
2871 | break; | |
2872 | ||
2873 | case '#': | |
2874 | fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn)); | |
2875 | break; | |
2876 | ||
0f6e5d45 | 2877 | case '@': |
87b483a1 | 2878 | /* Output small data area base register (gr16). */ |
36a05131 BS |
2879 | fputs (reg_names[SDA_BASE_REG], file); |
2880 | break; | |
2881 | ||
2882 | case '~': | |
87b483a1 | 2883 | /* Output pic register (gr17). */ |
36a05131 BS |
2884 | fputs (reg_names[PIC_REGNO], file); |
2885 | break; | |
2886 | ||
2887 | case '*': | |
87b483a1 | 2888 | /* Output the temporary integer CCR register. */ |
36a05131 BS |
2889 | fputs (reg_names[ICR_TEMP], file); |
2890 | break; | |
2891 | ||
2892 | case '&': | |
87b483a1 | 2893 | /* Output the temporary integer CC register. */ |
36a05131 BS |
2894 | fputs (reg_names[ICC_TEMP], file); |
2895 | break; | |
2896 | ||
87b483a1 | 2897 | /* case 'a': print an address. */ |
36a05131 BS |
2898 | |
2899 | case 'C': | |
87b483a1 | 2900 | /* Print appropriate test for integer branch false operation. */ |
036ff63f RS |
2901 | fputs (comparison_string (reverse_condition (GET_CODE (x)), |
2902 | XEXP (x, 0)), file); | |
36a05131 BS |
2903 | break; |
2904 | ||
36a05131 | 2905 | case 'c': |
87b483a1 | 2906 | /* Print appropriate test for integer branch true operation. */ |
036ff63f | 2907 | fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file); |
36a05131 BS |
2908 | break; |
2909 | ||
2910 | case 'e': | |
2911 | /* Print 1 for a NE and 0 for an EQ to give the final argument | |
2912 | for a conditional instruction. */ | |
2913 | if (GET_CODE (x) == NE) | |
2914 | fputs ("1", file); | |
2915 | ||
2916 | else if (GET_CODE (x) == EQ) | |
2917 | fputs ("0", file); | |
2918 | ||
2919 | else | |
ab532386 | 2920 | fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x); |
36a05131 BS |
2921 | break; |
2922 | ||
2923 | case 'F': | |
87b483a1 | 2924 | /* Print appropriate test for floating point branch false operation. */ |
36a05131 BS |
2925 | switch (GET_CODE (x)) |
2926 | { | |
2927 | default: | |
ab532386 | 2928 | fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x); |
36a05131 BS |
2929 | |
2930 | case EQ: fputs ("ne", file); break; | |
2931 | case NE: fputs ("eq", file); break; | |
2932 | case LT: fputs ("uge", file); break; | |
2933 | case LE: fputs ("ug", file); break; | |
2934 | case GT: fputs ("ule", file); break; | |
2935 | case GE: fputs ("ul", file); break; | |
2936 | } | |
2937 | break; | |
2938 | ||
2939 | case 'f': | |
87b483a1 | 2940 | /* Print appropriate test for floating point branch true operation. */ |
36a05131 BS |
2941 | switch (GET_CODE (x)) |
2942 | { | |
2943 | default: | |
ab532386 | 2944 | fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x); |
36a05131 BS |
2945 | |
2946 | case EQ: fputs ("eq", file); break; | |
2947 | case NE: fputs ("ne", file); break; | |
2948 | case LT: fputs ("lt", file); break; | |
2949 | case LE: fputs ("le", file); break; | |
2950 | case GT: fputs ("gt", file); break; | |
2951 | case GE: fputs ("ge", file); break; | |
2952 | } | |
2953 | break; | |
2954 | ||
34208acf AO |
2955 | case 'g': |
2956 | /* Print appropriate GOT function. */ | |
2957 | if (GET_CODE (x) != CONST_INT) | |
ab532386 | 2958 | fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x); |
34208acf AO |
2959 | fputs (unspec_got_name (INTVAL (x)), file); |
2960 | break; | |
2961 | ||
36a05131 BS |
2962 | case 'I': |
2963 | /* Print 'i' if the operand is a constant, or is a memory reference that | |
87b483a1 | 2964 | adds a constant. */ |
36a05131 BS |
2965 | if (GET_CODE (x) == MEM) |
2966 | x = ((GET_CODE (XEXP (x, 0)) == PLUS) | |
2967 | ? XEXP (XEXP (x, 0), 1) | |
2968 | : XEXP (x, 0)); | |
34208acf AO |
2969 | else if (GET_CODE (x) == PLUS) |
2970 | x = XEXP (x, 1); | |
36a05131 BS |
2971 | |
2972 | switch (GET_CODE (x)) | |
2973 | { | |
2974 | default: | |
2975 | break; | |
2976 | ||
2977 | case CONST_INT: | |
2978 | case SYMBOL_REF: | |
2979 | case CONST: | |
2980 | fputs ("i", file); | |
2981 | break; | |
2982 | } | |
2983 | break; | |
2984 | ||
2985 | case 'i': | |
2986 | /* For jump instructions, print 'i' if the operand is a constant or | |
87b483a1 | 2987 | is an expression that adds a constant. */ |
36a05131 BS |
2988 | if (GET_CODE (x) == CONST_INT) |
2989 | fputs ("i", file); | |
2990 | ||
2991 | else | |
2992 | { | |
2993 | if (GET_CODE (x) == CONST_INT | |
2994 | || (GET_CODE (x) == PLUS | |
2995 | && (GET_CODE (XEXP (x, 1)) == CONST_INT | |
2996 | || GET_CODE (XEXP (x, 0)) == CONST_INT))) | |
2997 | fputs ("i", file); | |
2998 | } | |
2999 | break; | |
3000 | ||
3001 | case 'L': | |
3002 | /* Print the lower register of a double word register pair */ | |
3003 | if (GET_CODE (x) == REG) | |
3004 | fputs (reg_names[ REGNO (x)+1 ], file); | |
3005 | else | |
ab532386 | 3006 | fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x); |
36a05131 BS |
3007 | break; |
3008 | ||
87b483a1 | 3009 | /* case 'l': print a LABEL_REF. */ |
36a05131 BS |
3010 | |
3011 | case 'M': | |
3012 | case 'N': | |
3013 | /* Print a memory reference for ld/st/jmp, %N prints a memory reference | |
3014 | for the second word of double memory operations. */ | |
3015 | offset = (code == 'M') ? 0 : UNITS_PER_WORD; | |
3016 | switch (GET_CODE (x)) | |
3017 | { | |
3018 | default: | |
ab532386 | 3019 | fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x); |
36a05131 BS |
3020 | |
3021 | case MEM: | |
3022 | frv_print_operand_memory_reference (file, XEXP (x, 0), offset); | |
3023 | break; | |
3024 | ||
3025 | case REG: | |
3026 | case SUBREG: | |
3027 | case CONST_INT: | |
3028 | case PLUS: | |
3029 | case SYMBOL_REF: | |
3030 | frv_print_operand_memory_reference (file, x, offset); | |
3031 | break; | |
3032 | } | |
3033 | break; | |
3034 | ||
3035 | case 'O': | |
3036 | /* Print the opcode of a command. */ | |
3037 | switch (GET_CODE (x)) | |
3038 | { | |
3039 | default: | |
ab532386 | 3040 | fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x); |
36a05131 BS |
3041 | |
3042 | case PLUS: fputs ("add", file); break; | |
3043 | case MINUS: fputs ("sub", file); break; | |
3044 | case AND: fputs ("and", file); break; | |
3045 | case IOR: fputs ("or", file); break; | |
3046 | case XOR: fputs ("xor", file); break; | |
3047 | case ASHIFT: fputs ("sll", file); break; | |
3048 | case ASHIFTRT: fputs ("sra", file); break; | |
3049 | case LSHIFTRT: fputs ("srl", file); break; | |
3050 | } | |
3051 | break; | |
3052 | ||
87b483a1 | 3053 | /* case 'n': negate and print a constant int. */ |
36a05131 BS |
3054 | |
3055 | case 'P': | |
3056 | /* Print PIC label using operand as the number. */ | |
3057 | if (GET_CODE (x) != CONST_INT) | |
ab532386 | 3058 | fatal_insn ("bad insn to frv_print_operand, P modifier:", x); |
36a05131 BS |
3059 | |
3060 | fprintf (file, ".LCF%ld", (long)INTVAL (x)); | |
3061 | break; | |
3062 | ||
3063 | case 'U': | |
87b483a1 | 3064 | /* Print 'u' if the operand is a update load/store. */ |
36a05131 BS |
3065 | if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY) |
3066 | fputs ("u", file); | |
3067 | break; | |
3068 | ||
3069 | case 'z': | |
87b483a1 | 3070 | /* If value is 0, print gr0, otherwise it must be a register. */ |
36a05131 BS |
3071 | if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0) |
3072 | fputs (reg_names[GPR_R0], file); | |
3073 | ||
3074 | else if (GET_CODE (x) == REG) | |
3075 | fputs (reg_names [REGNO (x)], file); | |
3076 | ||
3077 | else | |
ab532386 | 3078 | fatal_insn ("bad insn in frv_print_operand, z case", x); |
36a05131 BS |
3079 | break; |
3080 | ||
3081 | case 'x': | |
87b483a1 | 3082 | /* Print constant in hex. */ |
36a05131 BS |
3083 | if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) |
3084 | { | |
3085 | fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value); | |
3086 | break; | |
3087 | } | |
3088 | ||
87b483a1 | 3089 | /* Fall through. */ |
36a05131 BS |
3090 | |
3091 | case '\0': | |
3092 | if (GET_CODE (x) == REG) | |
3093 | fputs (reg_names [REGNO (x)], file); | |
3094 | ||
3095 | else if (GET_CODE (x) == CONST_INT | |
3096 | || GET_CODE (x) == CONST_DOUBLE) | |
3097 | fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value); | |
3098 | ||
34208acf AO |
3099 | else if (frv_const_unspec_p (x, &unspec)) |
3100 | frv_output_const_unspec (file, &unspec); | |
3101 | ||
36a05131 BS |
3102 | else if (GET_CODE (x) == MEM) |
3103 | frv_print_operand_address (file, XEXP (x, 0)); | |
3104 | ||
3105 | else if (CONSTANT_ADDRESS_P (x)) | |
3106 | frv_print_operand_address (file, x); | |
3107 | ||
3108 | else | |
ab532386 | 3109 | fatal_insn ("bad insn in frv_print_operand, 0 case", x); |
36a05131 BS |
3110 | |
3111 | break; | |
3112 | ||
3113 | default: | |
3114 | fatal_insn ("frv_print_operand: unknown code", x); | |
3115 | break; | |
3116 | } | |
3117 | ||
3118 | return; | |
3119 | } | |
3120 | ||
0fb30cb7 NF |
3121 | static bool |
3122 | frv_print_operand_punct_valid_p (unsigned char code) | |
3123 | { | |
3124 | return (code == '.' || code == '#' || code == '@' || code == '~' | |
3125 | || code == '*' || code == '&'); | |
3126 | } | |
3127 | ||
36a05131 BS |
3128 | \f |
3129 | /* A C statement (sans semicolon) for initializing the variable CUM for the | |
3130 | state at the beginning of the argument list. The variable has type | |
3131 | `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type | |
3132 | of the function which will receive the args, or 0 if the args are to a | |
3133 | compiler support library function. The value of INDIRECT is nonzero when | |
3134 | processing an indirect call, for example a call through a function pointer. | |
3135 | The value of INDIRECT is zero for a call to an explicitly named function, a | |
3136 | library function call, or when `INIT_CUMULATIVE_ARGS' is used to find | |
3137 | arguments for the function being compiled. | |
3138 | ||
3139 | When processing a call to a compiler support library function, LIBNAME | |
3140 | identifies which one. It is a `symbol_ref' rtx which contains the name of | |
3141 | the function, as a string. LIBNAME is 0 when an ordinary C function call is | |
3142 | being processed. Thus, each time this macro is called, either LIBNAME or | |
3143 | FNTYPE is nonzero, but never both of them at once. */ | |
3144 | ||
3145 | void | |
f2206911 KC |
3146 | frv_init_cumulative_args (CUMULATIVE_ARGS *cum, |
3147 | tree fntype, | |
3148 | rtx libname, | |
3149 | tree fndecl, | |
3150 | int incoming) | |
36a05131 BS |
3151 | { |
3152 | *cum = FIRST_ARG_REGNUM; | |
3153 | ||
3154 | if (TARGET_DEBUG_ARG) | |
3155 | { | |
3156 | fprintf (stderr, "\ninit_cumulative_args:"); | |
563a317a | 3157 | if (!fndecl && fntype) |
36a05131 BS |
3158 | fputs (" indirect", stderr); |
3159 | ||
3160 | if (incoming) | |
3161 | fputs (" incoming", stderr); | |
3162 | ||
3163 | if (fntype) | |
3164 | { | |
3165 | tree ret_type = TREE_TYPE (fntype); | |
3166 | fprintf (stderr, " return=%s,", | |
3167 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
3168 | } | |
3169 | ||
3170 | if (libname && GET_CODE (libname) == SYMBOL_REF) | |
3171 | fprintf (stderr, " libname=%s", XSTR (libname, 0)); | |
3172 | ||
3173 | if (cfun->returns_struct) | |
3174 | fprintf (stderr, " return-struct"); | |
3175 | ||
3176 | putc ('\n', stderr); | |
3177 | } | |
3178 | } | |
3179 | ||
3180 | \f | |
fe984136 RH |
3181 | /* Return true if we should pass an argument on the stack rather than |
3182 | in registers. */ | |
3183 | ||
3184 | static bool | |
586de218 | 3185 | frv_must_pass_in_stack (enum machine_mode mode, const_tree type) |
fe984136 RH |
3186 | { |
3187 | if (mode == BLKmode) | |
3188 | return true; | |
3189 | if (type == NULL) | |
3190 | return false; | |
3191 | return AGGREGATE_TYPE_P (type); | |
3192 | } | |
3193 | ||
36a05131 BS |
3194 | /* If defined, a C expression that gives the alignment boundary, in bits, of an |
3195 | argument with the specified mode and type. If it is not defined, | |
3196 | `PARM_BOUNDARY' is used for all arguments. */ | |
3197 | ||
3198 | int | |
f2206911 KC |
3199 | frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED, |
3200 | tree type ATTRIBUTE_UNUSED) | |
36a05131 BS |
3201 | { |
3202 | return BITS_PER_WORD; | |
3203 | } | |
3204 | ||
88a1f47f NF |
3205 | static rtx |
3206 | frv_function_arg_1 (const CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
3207 | const_tree type ATTRIBUTE_UNUSED, bool named, | |
3208 | bool incoming ATTRIBUTE_UNUSED) | |
36a05131 BS |
3209 | { |
3210 | enum machine_mode xmode = (mode == BLKmode) ? SImode : mode; | |
3211 | int arg_num = *cum; | |
3212 | rtx ret; | |
3213 | const char *debstr; | |
3214 | ||
3215 | /* Return a marker for use in the call instruction. */ | |
3216 | if (xmode == VOIDmode) | |
3217 | { | |
3218 | ret = const0_rtx; | |
3219 | debstr = "<0>"; | |
3220 | } | |
3221 | ||
3222 | else if (arg_num <= LAST_ARG_REGNUM) | |
3223 | { | |
f1c25d3b | 3224 | ret = gen_rtx_REG (xmode, arg_num); |
36a05131 BS |
3225 | debstr = reg_names[arg_num]; |
3226 | } | |
3227 | ||
3228 | else | |
3229 | { | |
3230 | ret = NULL_RTX; | |
3231 | debstr = "memory"; | |
3232 | } | |
3233 | ||
3234 | if (TARGET_DEBUG_ARG) | |
3235 | fprintf (stderr, | |
3236 | "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n", | |
3237 | arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr); | |
3238 | ||
3239 | return ret; | |
3240 | } | |
3241 | ||
88a1f47f NF |
3242 | static rtx |
3243 | frv_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
3244 | const_tree type, bool named) | |
3245 | { | |
3246 | return frv_function_arg_1 (cum, mode, type, named, false); | |
3247 | } | |
3248 | ||
3249 | static rtx | |
3250 | frv_function_incoming_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
3251 | const_tree type, bool named) | |
3252 | { | |
3253 | return frv_function_arg_1 (cum, mode, type, named, true); | |
3254 | } | |
3255 | ||
36a05131 BS |
3256 | \f |
3257 | /* A C statement (sans semicolon) to update the summarizer variable CUM to | |
3258 | advance past an argument in the argument list. The values MODE, TYPE and | |
3259 | NAMED describe that argument. Once this is done, the variable CUM is | |
3260 | suitable for analyzing the *following* argument with `FUNCTION_ARG', etc. | |
3261 | ||
3262 | This macro need not do anything if the argument in question was passed on | |
3263 | the stack. The compiler knows how to track the amount of stack space used | |
3264 | for arguments without any special help. */ | |
3265 | ||
88a1f47f | 3266 | static void |
f2206911 KC |
3267 | frv_function_arg_advance (CUMULATIVE_ARGS *cum, |
3268 | enum machine_mode mode, | |
88a1f47f NF |
3269 | const_tree type ATTRIBUTE_UNUSED, |
3270 | bool named) | |
36a05131 BS |
3271 | { |
3272 | enum machine_mode xmode = (mode == BLKmode) ? SImode : mode; | |
3273 | int bytes = GET_MODE_SIZE (xmode); | |
3274 | int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
3275 | int arg_num = *cum; | |
3276 | ||
3277 | *cum = arg_num + words; | |
3278 | ||
3279 | if (TARGET_DEBUG_ARG) | |
3280 | fprintf (stderr, | |
3281 | "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n", | |
3282 | arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD); | |
3283 | } | |
3284 | ||
3285 | \f | |
3286 | /* A C expression for the number of words, at the beginning of an argument, | |
3287 | must be put in registers. The value must be zero for arguments that are | |
3288 | passed entirely in registers or that are entirely pushed on the stack. | |
3289 | ||
3290 | On some machines, certain arguments must be passed partially in registers | |
3291 | and partially in memory. On these machines, typically the first N words of | |
3292 | arguments are passed in registers, and the rest on the stack. If a | |
3293 | multi-word argument (a `double' or a structure) crosses that boundary, its | |
3294 | first few words must be passed in registers and the rest must be pushed. | |
3295 | This macro tells the compiler when this occurs, and how many of the words | |
3296 | should go in registers. | |
3297 | ||
3298 | `FUNCTION_ARG' for these arguments should return the first register to be | |
3299 | used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for | |
3300 | the called function. */ | |
3301 | ||
78a52f11 RH |
3302 | static int |
3303 | frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
3304 | tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED) | |
36a05131 BS |
3305 | { |
3306 | enum machine_mode xmode = (mode == BLKmode) ? SImode : mode; | |
3307 | int bytes = GET_MODE_SIZE (xmode); | |
3308 | int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
3309 | int arg_num = *cum; | |
3310 | int ret; | |
3311 | ||
3312 | ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1) | |
3313 | ? LAST_ARG_REGNUM - arg_num + 1 | |
3314 | : 0); | |
78a52f11 | 3315 | ret *= UNITS_PER_WORD; |
36a05131 BS |
3316 | |
3317 | if (TARGET_DEBUG_ARG && ret) | |
78a52f11 | 3318 | fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret); |
36a05131 BS |
3319 | |
3320 | return ret; | |
36a05131 BS |
3321 | } |
3322 | ||
219d92a4 AS |
3323 | \f |
3324 | /* Implements TARGET_FUNCTION_VALUE. */ | |
3325 | ||
3326 | static rtx | |
3327 | frv_function_value (const_tree valtype, | |
3328 | const_tree fn_decl_or_type ATTRIBUTE_UNUSED, | |
3329 | bool outgoing ATTRIBUTE_UNUSED) | |
3330 | { | |
3331 | return gen_rtx_REG (TYPE_MODE (valtype), RETURN_VALUE_REGNUM); | |
3332 | } | |
3333 | ||
3334 | \f | |
3335 | /* Implements TARGET_LIBCALL_VALUE. */ | |
3336 | ||
3337 | static rtx | |
3338 | frv_libcall_value (enum machine_mode mode, | |
3339 | const_rtx fun ATTRIBUTE_UNUSED) | |
3340 | { | |
3341 | return gen_rtx_REG (mode, RETURN_VALUE_REGNUM); | |
3342 | } | |
3343 | ||
3344 | \f | |
3345 | /* Implements FUNCTION_VALUE_REGNO_P. */ | |
3346 | ||
3347 | bool | |
3348 | frv_function_value_regno_p (const unsigned int regno) | |
3349 | { | |
3350 | return (regno == RETURN_VALUE_REGNUM); | |
3351 | } | |
36a05131 BS |
3352 | \f |
3353 | /* Return true if a register is ok to use as a base or index register. */ | |
3354 | ||
3355 | static FRV_INLINE int | |
f2206911 | 3356 | frv_regno_ok_for_base_p (int regno, int strict_p) |
36a05131 BS |
3357 | { |
3358 | if (GPR_P (regno)) | |
3359 | return TRUE; | |
3360 | ||
3361 | if (strict_p) | |
3362 | return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno])); | |
3363 | ||
3364 | if (regno == ARG_POINTER_REGNUM) | |
3365 | return TRUE; | |
3366 | ||
3367 | return (regno >= FIRST_PSEUDO_REGISTER); | |
3368 | } | |
3369 | ||
3370 | \f | |
3371 | /* A C compound statement with a conditional `goto LABEL;' executed if X (an | |
3372 | RTX) is a legitimate memory address on the target machine for a memory | |
3373 | operand of mode MODE. | |
3374 | ||
3375 | It usually pays to define several simpler macros to serve as subroutines for | |
3376 | this one. Otherwise it may be too complicated to understand. | |
3377 | ||
3378 | This macro must exist in two variants: a strict variant and a non-strict | |
3379 | one. The strict variant is used in the reload pass. It must be defined so | |
3380 | that any pseudo-register that has not been allocated a hard register is | |
3381 | considered a memory reference. In contexts where some kind of register is | |
3382 | required, a pseudo-register with no hard register must be rejected. | |
3383 | ||
3384 | The non-strict variant is used in other passes. It must be defined to | |
3385 | accept all pseudo-registers in every context where some kind of register is | |
3386 | required. | |
3387 | ||
3388 | Compiler source files that want to use the strict variant of this macro | |
3389 | define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT' | |
3390 | conditional to define the strict variant in that case and the non-strict | |
3391 | variant otherwise. | |
3392 | ||
36a05131 BS |
3393 | Normally, constant addresses which are the sum of a `symbol_ref' and an |
3394 | integer are stored inside a `const' RTX to mark them as constant. | |
3395 | Therefore, there is no need to recognize such sums specifically as | |
3396 | legitimate addresses. Normally you would simply recognize any `const' as | |
3397 | legitimate. | |
3398 | ||
0fb30cb7 NF |
3399 | Usually `TARGET_PRINT_OPERAND_ADDRESS' is not prepared to handle |
3400 | constant sums that are not marked with `const'. It assumes that a | |
3401 | naked `plus' indicates indexing. If so, then you *must* reject such | |
3402 | naked constant sums as illegitimate addresses, so that none of them | |
3403 | will be given to `TARGET_PRINT_OPERAND_ADDRESS'. */ | |
36a05131 BS |
3404 | |
3405 | int | |
c6c3dba9 PB |
3406 | frv_legitimate_address_p_1 (enum machine_mode mode, |
3407 | rtx x, | |
3408 | int strict_p, | |
3409 | int condexec_p, | |
3410 | int allow_double_reg_p) | |
36a05131 BS |
3411 | { |
3412 | rtx x0, x1; | |
3413 | int ret = 0; | |
3414 | HOST_WIDE_INT value; | |
3415 | unsigned regno0; | |
3416 | ||
bef8809e AH |
3417 | if (FRV_SYMBOL_REF_TLS_P (x)) |
3418 | return 0; | |
3419 | ||
36a05131 BS |
3420 | switch (GET_CODE (x)) |
3421 | { | |
3422 | default: | |
3423 | break; | |
3424 | ||
3425 | case SUBREG: | |
3426 | x = SUBREG_REG (x); | |
3427 | if (GET_CODE (x) != REG) | |
3428 | break; | |
3429 | ||
87b483a1 | 3430 | /* Fall through. */ |
36a05131 BS |
3431 | |
3432 | case REG: | |
3433 | ret = frv_regno_ok_for_base_p (REGNO (x), strict_p); | |
3434 | break; | |
3435 | ||
3436 | case PRE_MODIFY: | |
3437 | x0 = XEXP (x, 0); | |
3438 | x1 = XEXP (x, 1); | |
3439 | if (GET_CODE (x0) != REG | |
3440 | || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p) | |
3441 | || GET_CODE (x1) != PLUS | |
3442 | || ! rtx_equal_p (x0, XEXP (x1, 0)) | |
3443 | || GET_CODE (XEXP (x1, 1)) != REG | |
3444 | || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p)) | |
3445 | break; | |
3446 | ||
3447 | ret = 1; | |
3448 | break; | |
3449 | ||
3450 | case CONST_INT: | |
2300b9dd | 3451 | /* 12-bit immediate */ |
36a05131 BS |
3452 | if (condexec_p) |
3453 | ret = FALSE; | |
3454 | else | |
3455 | { | |
3456 | ret = IN_RANGE_P (INTVAL (x), -2048, 2047); | |
3457 | ||
3458 | /* If we can't use load/store double operations, make sure we can | |
3459 | address the second word. */ | |
3460 | if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
3461 | ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1, | |
3462 | -2048, 2047); | |
3463 | } | |
3464 | break; | |
3465 | ||
3466 | case PLUS: | |
3467 | x0 = XEXP (x, 0); | |
3468 | x1 = XEXP (x, 1); | |
3469 | ||
3470 | if (GET_CODE (x0) == SUBREG) | |
3471 | x0 = SUBREG_REG (x0); | |
3472 | ||
3473 | if (GET_CODE (x0) != REG) | |
3474 | break; | |
3475 | ||
3476 | regno0 = REGNO (x0); | |
3477 | if (!frv_regno_ok_for_base_p (regno0, strict_p)) | |
3478 | break; | |
3479 | ||
3480 | switch (GET_CODE (x1)) | |
3481 | { | |
3482 | default: | |
3483 | break; | |
3484 | ||
3485 | case SUBREG: | |
3486 | x1 = SUBREG_REG (x1); | |
3487 | if (GET_CODE (x1) != REG) | |
3488 | break; | |
3489 | ||
87b483a1 | 3490 | /* Fall through. */ |
36a05131 BS |
3491 | |
3492 | case REG: | |
87b483a1 KH |
3493 | /* Do not allow reg+reg addressing for modes > 1 word if we |
3494 | can't depend on having move double instructions. */ | |
34208acf | 3495 | if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD) |
36a05131 BS |
3496 | ret = FALSE; |
3497 | else | |
3498 | ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p); | |
3499 | break; | |
3500 | ||
3501 | case CONST_INT: | |
2300b9dd | 3502 | /* 12-bit immediate */ |
36a05131 BS |
3503 | if (condexec_p) |
3504 | ret = FALSE; | |
3505 | else | |
3506 | { | |
3507 | value = INTVAL (x1); | |
3508 | ret = IN_RANGE_P (value, -2048, 2047); | |
3509 | ||
3510 | /* If we can't use load/store double operations, make sure we can | |
3511 | address the second word. */ | |
3512 | if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
3513 | ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047); | |
3514 | } | |
3515 | break; | |
3516 | ||
36a05131 | 3517 | case CONST: |
34208acf | 3518 | if (!condexec_p && got12_operand (x1, VOIDmode)) |
36a05131 BS |
3519 | ret = TRUE; |
3520 | break; | |
3521 | ||
3522 | } | |
3523 | break; | |
3524 | } | |
3525 | ||
3526 | if (TARGET_DEBUG_ADDR) | |
3527 | { | |
331d9186 | 3528 | fprintf (stderr, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n", |
36a05131 BS |
3529 | GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ", |
3530 | (condexec_p) ? ", inside conditional code" : ""); | |
3531 | debug_rtx (x); | |
3532 | } | |
3533 | ||
3534 | return ret; | |
3535 | } | |
3536 | ||
c6c3dba9 PB |
3537 | bool |
3538 | frv_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p) | |
3539 | { | |
3540 | return frv_legitimate_address_p_1 (mode, x, strict_p, FALSE, FALSE); | |
3541 | } | |
3542 | ||
bef8809e AH |
3543 | /* Given an ADDR, generate code to inline the PLT. */ |
3544 | static rtx | |
3545 | gen_inlined_tls_plt (rtx addr) | |
3546 | { | |
fdbe66f2 | 3547 | rtx retval, dest; |
bef8809e AH |
3548 | rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG); |
3549 | ||
3550 | ||
3551 | dest = gen_reg_rtx (DImode); | |
3552 | ||
3553 | if (flag_pic == 1) | |
3554 | { | |
3555 | /* | |
3556 | -fpic version: | |
3557 | ||
3558 | lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8 | |
3559 | calll #gettlsoff(ADDR)@(gr8, gr0) | |
3560 | */ | |
3561 | emit_insn (gen_tls_lddi (dest, addr, picreg)); | |
3562 | } | |
3563 | else | |
3564 | { | |
3565 | /* | |
3566 | -fPIC version: | |
3567 | ||
3568 | sethi.p #gottlsdeschi(ADDR), gr8 | |
3569 | setlo #gottlsdesclo(ADDR), gr8 | |
3570 | ldd #tlsdesc(ADDR)@(gr15, gr8), gr8 | |
3571 | calll #gettlsoff(ADDR)@(gr8, gr0) | |
3572 | */ | |
3573 | rtx reguse = gen_reg_rtx (Pmode); | |
3574 | emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI))); | |
3575 | emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr)); | |
3576 | } | |
3577 | ||
3578 | retval = gen_reg_rtx (Pmode); | |
a701780f | 3579 | emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg)); |
bef8809e AH |
3580 | return retval; |
3581 | } | |
3582 | ||
3583 | /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns | |
3584 | the destination address. */ | |
3585 | static rtx | |
3586 | gen_tlsmoff (rtx addr, rtx reg) | |
3587 | { | |
3588 | rtx dest = gen_reg_rtx (Pmode); | |
3589 | ||
3590 | if (TARGET_BIG_TLS) | |
3591 | { | |
3592 | /* sethi.p #tlsmoffhi(x), grA | |
3593 | setlo #tlsmofflo(x), grA | |
3594 | */ | |
3595 | dest = gen_reg_rtx (Pmode); | |
3596 | emit_insn (gen_tlsoff_hilo (dest, addr, | |
3597 | GEN_INT (R_FRV_TLSMOFFHI))); | |
3598 | dest = gen_rtx_PLUS (Pmode, dest, reg); | |
3599 | } | |
3600 | else | |
3601 | { | |
3602 | /* addi grB, #tlsmoff12(x), grC | |
3603 | -or- | |
3604 | ld/st @(grB, #tlsmoff12(x)), grC | |
3605 | */ | |
3606 | dest = gen_reg_rtx (Pmode); | |
3607 | emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg, | |
3608 | GEN_INT (R_FRV_TLSMOFF12))); | |
3609 | } | |
3610 | return dest; | |
3611 | } | |
3612 | ||
3613 | /* Generate code for a TLS address. */ | |
3614 | static rtx | |
3615 | frv_legitimize_tls_address (rtx addr, enum tls_model model) | |
3616 | { | |
3617 | rtx dest, tp = gen_rtx_REG (Pmode, 29); | |
3618 | rtx picreg = get_hard_reg_initial_val (Pmode, 15); | |
3619 | ||
3620 | switch (model) | |
3621 | { | |
3622 | case TLS_MODEL_INITIAL_EXEC: | |
3623 | if (flag_pic == 1) | |
3624 | { | |
3625 | /* -fpic version. | |
3626 | ldi @(gr15, #gottlsoff12(x)), gr5 | |
3627 | */ | |
3628 | dest = gen_reg_rtx (Pmode); | |
3629 | emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg)); | |
3630 | dest = gen_rtx_PLUS (Pmode, tp, dest); | |
3631 | } | |
3632 | else | |
3633 | { | |
3634 | /* -fPIC or anything else. | |
3635 | ||
3636 | sethi.p #gottlsoffhi(x), gr14 | |
3637 | setlo #gottlsofflo(x), gr14 | |
3638 | ld #tlsoff(x)@(gr15, gr14), gr9 | |
3639 | */ | |
3640 | rtx tmp = gen_reg_rtx (Pmode); | |
3641 | dest = gen_reg_rtx (Pmode); | |
3642 | emit_insn (gen_tlsoff_hilo (tmp, addr, | |
3643 | GEN_INT (R_FRV_GOTTLSOFF_HI))); | |
3644 | ||
3645 | emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr)); | |
3646 | dest = gen_rtx_PLUS (Pmode, tp, dest); | |
3647 | } | |
3648 | break; | |
3649 | case TLS_MODEL_LOCAL_DYNAMIC: | |
3650 | { | |
3651 | rtx reg, retval; | |
3652 | ||
3653 | if (TARGET_INLINE_PLT) | |
3654 | retval = gen_inlined_tls_plt (GEN_INT (0)); | |
3655 | else | |
3656 | { | |
3657 | /* call #gettlsoff(0) */ | |
3658 | retval = gen_reg_rtx (Pmode); | |
3659 | emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg)); | |
3660 | } | |
3661 | ||
3662 | reg = gen_reg_rtx (Pmode); | |
3663 | emit_insn (gen_rtx_SET (VOIDmode, reg, | |
3664 | gen_rtx_PLUS (Pmode, | |
3665 | retval, tp))); | |
3666 | ||
3667 | dest = gen_tlsmoff (addr, reg); | |
3668 | ||
3669 | /* | |
3670 | dest = gen_reg_rtx (Pmode); | |
3671 | emit_insn (gen_tlsoff_hilo (dest, addr, | |
3672 | GEN_INT (R_FRV_TLSMOFFHI))); | |
3673 | dest = gen_rtx_PLUS (Pmode, dest, reg); | |
3674 | */ | |
3675 | break; | |
3676 | } | |
3677 | case TLS_MODEL_LOCAL_EXEC: | |
3678 | dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29)); | |
3679 | break; | |
3680 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
3681 | { | |
3682 | rtx retval; | |
3683 | ||
3684 | if (TARGET_INLINE_PLT) | |
3685 | retval = gen_inlined_tls_plt (addr); | |
3686 | else | |
3687 | { | |
3688 | /* call #gettlsoff(x) */ | |
3689 | retval = gen_reg_rtx (Pmode); | |
3690 | emit_insn (gen_call_gettlsoff (retval, addr, picreg)); | |
3691 | } | |
3692 | dest = gen_rtx_PLUS (Pmode, retval, tp); | |
3693 | break; | |
3694 | } | |
3695 | default: | |
44e91694 | 3696 | gcc_unreachable (); |
bef8809e AH |
3697 | } |
3698 | ||
3699 | return dest; | |
3700 | } | |
3701 | ||
2a2e3f05 | 3702 | rtx |
bef8809e | 3703 | frv_legitimize_address (rtx x, |
2a2e3f05 AH |
3704 | rtx oldx ATTRIBUTE_UNUSED, |
3705 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
3706 | { | |
bef8809e AH |
3707 | if (GET_CODE (x) == SYMBOL_REF) |
3708 | { | |
3709 | enum tls_model model = SYMBOL_REF_TLS_MODEL (x); | |
3710 | if (model != 0) | |
3711 | return frv_legitimize_tls_address (x, model); | |
3712 | } | |
3713 | ||
506d7b68 | 3714 | return x; |
2a2e3f05 | 3715 | } |
36a05131 | 3716 | \f |
34208acf AO |
3717 | /* Test whether a local function descriptor is canonical, i.e., |
3718 | whether we can use FUNCDESC_GOTOFF to compute the address of the | |
3719 | function. */ | |
3720 | ||
3721 | static bool | |
3722 | frv_local_funcdesc_p (rtx fnx) | |
3723 | { | |
3724 | tree fn; | |
3725 | enum symbol_visibility vis; | |
3726 | bool ret; | |
36a05131 | 3727 | |
34208acf AO |
3728 | if (! SYMBOL_REF_LOCAL_P (fnx)) |
3729 | return FALSE; | |
3730 | ||
3731 | fn = SYMBOL_REF_DECL (fnx); | |
3732 | ||
3733 | if (! fn) | |
3734 | return FALSE; | |
36a05131 | 3735 | |
34208acf | 3736 | vis = DECL_VISIBILITY (fn); |
36a05131 | 3737 | |
34208acf AO |
3738 | if (vis == VISIBILITY_PROTECTED) |
3739 | /* Private function descriptors for protected functions are not | |
3740 | canonical. Temporarily change the visibility to global. */ | |
3741 | vis = VISIBILITY_DEFAULT; | |
3742 | else if (flag_shlib) | |
3743 | /* If we're already compiling for a shared library (that, unlike | |
3744 | executables, can't assume that the existence of a definition | |
3745 | implies local binding), we can skip the re-testing. */ | |
3746 | return TRUE; | |
36a05131 | 3747 | |
34208acf | 3748 | ret = default_binds_local_p_1 (fn, flag_pic); |
36a05131 | 3749 | |
34208acf AO |
3750 | DECL_VISIBILITY (fn) = vis; |
3751 | ||
3752 | return ret; | |
3753 | } | |
3754 | ||
3755 | /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC | |
3756 | register. */ | |
36a05131 BS |
3757 | |
3758 | rtx | |
34208acf AO |
3759 | frv_gen_GPsym2reg (rtx dest, rtx src) |
3760 | { | |
3761 | tree gp = get_identifier ("_gp"); | |
3762 | rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp)); | |
36a05131 | 3763 | |
34208acf AO |
3764 | return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12)); |
3765 | } | |
3766 | ||
3767 | static const char * | |
3768 | unspec_got_name (int i) | |
3769 | { | |
3770 | switch (i) | |
36a05131 | 3771 | { |
34208acf AO |
3772 | case R_FRV_GOT12: return "got12"; |
3773 | case R_FRV_GOTHI: return "gothi"; | |
3774 | case R_FRV_GOTLO: return "gotlo"; | |
3775 | case R_FRV_FUNCDESC: return "funcdesc"; | |
3776 | case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12"; | |
3777 | case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi"; | |
3778 | case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo"; | |
3779 | case R_FRV_FUNCDESC_VALUE: return "funcdescvalue"; | |
3780 | case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12"; | |
3781 | case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi"; | |
3782 | case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo"; | |
3783 | case R_FRV_GOTOFF12: return "gotoff12"; | |
3784 | case R_FRV_GOTOFFHI: return "gotoffhi"; | |
3785 | case R_FRV_GOTOFFLO: return "gotofflo"; | |
3786 | case R_FRV_GPREL12: return "gprel12"; | |
3787 | case R_FRV_GPRELHI: return "gprelhi"; | |
3788 | case R_FRV_GPRELLO: return "gprello"; | |
bef8809e AH |
3789 | case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi"; |
3790 | case R_FRV_GOTTLSOFF_LO: return "gottlsofflo"; | |
3791 | case R_FRV_TLSMOFFHI: return "tlsmoffhi"; | |
3792 | case R_FRV_TLSMOFFLO: return "tlsmofflo"; | |
3793 | case R_FRV_TLSMOFF12: return "tlsmoff12"; | |
3794 | case R_FRV_TLSDESCHI: return "tlsdeschi"; | |
3795 | case R_FRV_TLSDESCLO: return "tlsdesclo"; | |
3796 | case R_FRV_GOTTLSDESCHI: return "gottlsdeschi"; | |
3797 | case R_FRV_GOTTLSDESCLO: return "gottlsdesclo"; | |
44e91694 | 3798 | default: gcc_unreachable (); |
36a05131 | 3799 | } |
34208acf | 3800 | } |
36a05131 | 3801 | |
34208acf AO |
3802 | /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset |
3803 | is added inside the relocation operator. */ | |
3804 | ||
3805 | static void | |
3806 | frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec) | |
3807 | { | |
3808 | fprintf (stream, "#%s(", unspec_got_name (unspec->reloc)); | |
3809 | output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset)); | |
3810 | fputs (")", stream); | |
3811 | } | |
3812 | ||
3813 | /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo) | |
3814 | or #gotoff12(foo) for some small data symbol foo. If so, return foo, | |
3815 | otherwise return ORIG_X. */ | |
3816 | ||
3817 | rtx | |
3818 | frv_find_base_term (rtx x) | |
3819 | { | |
3820 | struct frv_unspec unspec; | |
3821 | ||
3822 | if (frv_const_unspec_p (x, &unspec) | |
3823 | && frv_small_data_reloc_p (unspec.symbol, unspec.reloc)) | |
3824 | return plus_constant (unspec.symbol, unspec.offset); | |
3825 | ||
3826 | return x; | |
36a05131 BS |
3827 | } |
3828 | ||
3829 | /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if | |
3830 | the operand is used by a predicated instruction. */ | |
3831 | ||
6d26dc3b | 3832 | int |
f2206911 | 3833 | frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p) |
36a05131 BS |
3834 | { |
3835 | return ((GET_MODE (op) == mode || mode == VOIDmode) | |
3836 | && GET_CODE (op) == MEM | |
c6c3dba9 PB |
3837 | && frv_legitimate_address_p_1 (mode, XEXP (op, 0), |
3838 | reload_completed, condexec_p, FALSE)); | |
34208acf AO |
3839 | } |
3840 | ||
3841 | void | |
764678d1 | 3842 | frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall) |
34208acf AO |
3843 | { |
3844 | rtx lr = gen_rtx_REG (Pmode, LR_REGNO); | |
3845 | rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG); | |
3846 | rtx c, rvrtx=0; | |
3847 | rtx addr; | |
3848 | ||
3849 | if (ret_value) | |
3850 | { | |
3851 | rvrtx = operands[0]; | |
3852 | operands ++; | |
3853 | } | |
3854 | ||
3855 | addr = XEXP (operands[0], 0); | |
3856 | ||
3857 | /* Inline PLTs if we're optimizing for speed. We'd like to inline | |
3858 | any calls that would involve a PLT, but can't tell, since we | |
3859 | don't know whether an extern function is going to be provided by | |
3860 | a separate translation unit or imported from a separate module. | |
3861 | When compiling for shared libraries, if the function has default | |
3862 | visibility, we assume it's overridable, so we inline the PLT, but | |
3863 | for executables, we don't really have a way to make a good | |
3864 | decision: a function is as likely to be imported from a shared | |
3865 | library as it is to be defined in the executable itself. We | |
3866 | assume executables will get global functions defined locally, | |
3867 | whereas shared libraries will have them potentially overridden, | |
3868 | so we only inline PLTs when compiling for shared libraries. | |
3869 | ||
3870 | In order to mark a function as local to a shared library, any | |
3871 | non-default visibility attribute suffices. Unfortunately, | |
3872 | there's no simple way to tag a function declaration as ``in a | |
3873 | different module'', which we could then use to trigger PLT | |
3874 | inlining on executables. There's -minline-plt, but it affects | |
3875 | all external functions, so one would have to also mark function | |
3876 | declarations available in the same module with non-default | |
3877 | visibility, which is advantageous in itself. */ | |
764678d1 AO |
3878 | if (GET_CODE (addr) == SYMBOL_REF |
3879 | && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT) | |
3880 | || sibcall)) | |
34208acf AO |
3881 | { |
3882 | rtx x, dest; | |
3883 | dest = gen_reg_rtx (SImode); | |
3884 | if (flag_pic != 1) | |
3885 | x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG, | |
3886 | GEN_INT (R_FRV_FUNCDESC_GOTOFF12)); | |
3887 | else | |
3888 | x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG, | |
3889 | GEN_INT (R_FRV_FUNCDESC_GOTOFF12)); | |
3890 | emit_insn (x); | |
ad516a74 | 3891 | crtl->uses_pic_offset_table = TRUE; |
34208acf | 3892 | addr = dest; |
2396bce1 | 3893 | } |
34208acf AO |
3894 | else if (GET_CODE (addr) == SYMBOL_REF) |
3895 | { | |
3896 | /* These are always either local, or handled through a local | |
3897 | PLT. */ | |
3898 | if (ret_value) | |
3899 | c = gen_call_value_fdpicsi (rvrtx, addr, operands[1], | |
3900 | operands[2], picreg, lr); | |
3901 | else | |
3902 | c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr); | |
3903 | emit_call_insn (c); | |
3904 | return; | |
3905 | } | |
3906 | else if (! ldd_address_operand (addr, Pmode)) | |
3907 | addr = force_reg (Pmode, addr); | |
3908 | ||
3909 | picreg = gen_reg_rtx (DImode); | |
3910 | emit_insn (gen_movdi_ldd (picreg, addr)); | |
3911 | ||
764678d1 AO |
3912 | if (sibcall && ret_value) |
3913 | c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx); | |
3914 | else if (sibcall) | |
3915 | c = gen_sibcall_fdpicdi (picreg, const0_rtx); | |
3916 | else if (ret_value) | |
34208acf AO |
3917 | c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr); |
3918 | else | |
3919 | c = gen_call_fdpicdi (picreg, const0_rtx, lr); | |
3920 | emit_call_insn (c); | |
36a05131 | 3921 | } |
36a05131 | 3922 | \f |
6d26dc3b KH |
3923 | /* Look for a SYMBOL_REF of a function in an rtx. We always want to |
3924 | process these separately from any offsets, such that we add any | |
3925 | offsets to the function descriptor (the actual pointer), not to the | |
3926 | function address. */ | |
36a05131 | 3927 | |
6d26dc3b KH |
3928 | static bool |
3929 | frv_function_symbol_referenced_p (rtx x) | |
36a05131 | 3930 | { |
6d26dc3b KH |
3931 | const char *format; |
3932 | int length; | |
3933 | int j; | |
36a05131 | 3934 | |
6d26dc3b KH |
3935 | if (GET_CODE (x) == SYMBOL_REF) |
3936 | return SYMBOL_REF_FUNCTION_P (x); | |
34208acf | 3937 | |
6d26dc3b KH |
3938 | length = GET_RTX_LENGTH (GET_CODE (x)); |
3939 | format = GET_RTX_FORMAT (GET_CODE (x)); | |
36a05131 | 3940 | |
6d26dc3b | 3941 | for (j = 0; j < length; ++j) |
36a05131 | 3942 | { |
6d26dc3b KH |
3943 | switch (format[j]) |
3944 | { | |
3945 | case 'e': | |
3946 | if (frv_function_symbol_referenced_p (XEXP (x, j))) | |
3947 | return TRUE; | |
3948 | break; | |
36a05131 | 3949 | |
6d26dc3b KH |
3950 | case 'V': |
3951 | case 'E': | |
3952 | if (XVEC (x, j) != 0) | |
3953 | { | |
3954 | int k; | |
3955 | for (k = 0; k < XVECLEN (x, j); ++k) | |
3956 | if (frv_function_symbol_referenced_p (XVECEXP (x, j, k))) | |
3957 | return TRUE; | |
3958 | } | |
3959 | break; | |
36a05131 | 3960 | |
6d26dc3b KH |
3961 | default: |
3962 | /* Nothing to do. */ | |
3963 | break; | |
3964 | } | |
36a05131 BS |
3965 | } |
3966 | ||
36a05131 BS |
3967 | return FALSE; |
3968 | } | |
3969 | ||
6d26dc3b KH |
3970 | /* Return true if the memory operand is one that can be conditionally |
3971 | executed. */ | |
36a05131 | 3972 | |
f2206911 | 3973 | int |
6d26dc3b | 3974 | condexec_memory_operand (rtx op, enum machine_mode mode) |
36a05131 | 3975 | { |
6d26dc3b KH |
3976 | enum machine_mode op_mode = GET_MODE (op); |
3977 | rtx addr; | |
36a05131 | 3978 | |
6d26dc3b | 3979 | if (mode != VOIDmode && op_mode != mode) |
36a05131 BS |
3980 | return FALSE; |
3981 | ||
6d26dc3b | 3982 | switch (op_mode) |
36a05131 BS |
3983 | { |
3984 | default: | |
6d26dc3b | 3985 | return FALSE; |
36a05131 | 3986 | |
6d26dc3b KH |
3987 | case QImode: |
3988 | case HImode: | |
3989 | case SImode: | |
3990 | case SFmode: | |
36a05131 BS |
3991 | break; |
3992 | } | |
3993 | ||
6d26dc3b | 3994 | if (GET_CODE (op) != MEM) |
36a05131 BS |
3995 | return FALSE; |
3996 | ||
6d26dc3b | 3997 | addr = XEXP (op, 0); |
c6c3dba9 | 3998 | return frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE); |
36a05131 | 3999 | } |
36a05131 BS |
4000 | \f |
4001 | /* Return true if the bare return instruction can be used outside of the | |
4002 | epilog code. For frv, we only do it if there was no stack allocation. */ | |
4003 | ||
4004 | int | |
f2206911 | 4005 | direct_return_p (void) |
36a05131 BS |
4006 | { |
4007 | frv_stack_t *info; | |
4008 | ||
4009 | if (!reload_completed) | |
4010 | return FALSE; | |
4011 | ||
4012 | info = frv_stack_info (); | |
4013 | return (info->total_size == 0); | |
4014 | } | |
4015 | ||
4016 | \f | |
2a2e3f05 AH |
4017 | void |
4018 | frv_emit_move (enum machine_mode mode, rtx dest, rtx src) | |
4019 | { | |
bef8809e AH |
4020 | if (GET_CODE (src) == SYMBOL_REF) |
4021 | { | |
4022 | enum tls_model model = SYMBOL_REF_TLS_MODEL (src); | |
4023 | if (model != 0) | |
4024 | src = frv_legitimize_tls_address (src, model); | |
4025 | } | |
4026 | ||
2a2e3f05 AH |
4027 | switch (mode) |
4028 | { | |
4029 | case SImode: | |
4030 | if (frv_emit_movsi (dest, src)) | |
4031 | return; | |
4032 | break; | |
4033 | ||
4034 | case QImode: | |
4035 | case HImode: | |
4036 | case DImode: | |
4037 | case SFmode: | |
4038 | case DFmode: | |
4039 | if (!reload_in_progress | |
4040 | && !reload_completed | |
4041 | && !register_operand (dest, mode) | |
4042 | && !reg_or_0_operand (src, mode)) | |
4043 | src = copy_to_mode_reg (mode, src); | |
4044 | break; | |
4045 | ||
4046 | default: | |
44e91694 | 4047 | gcc_unreachable (); |
2a2e3f05 AH |
4048 | } |
4049 | ||
4050 | emit_insn (gen_rtx_SET (VOIDmode, dest, src)); | |
4051 | } | |
4052 | ||
36a05131 BS |
4053 | /* Emit code to handle a MOVSI, adding in the small data register or pic |
4054 | register if needed to load up addresses. Return TRUE if the appropriate | |
4055 | instructions are emitted. */ | |
4056 | ||
4057 | int | |
f2206911 | 4058 | frv_emit_movsi (rtx dest, rtx src) |
36a05131 BS |
4059 | { |
4060 | int base_regno = -1; | |
34208acf AO |
4061 | int unspec = 0; |
4062 | rtx sym = src; | |
4063 | struct frv_unspec old_unspec; | |
36a05131 BS |
4064 | |
4065 | if (!reload_in_progress | |
4066 | && !reload_completed | |
4067 | && !register_operand (dest, SImode) | |
4068 | && (!reg_or_0_operand (src, SImode) | |
4069 | /* Virtual registers will almost always be replaced by an | |
4070 | add instruction, so expose this to CSE by copying to | |
87b483a1 | 4071 | an intermediate register. */ |
36a05131 BS |
4072 | || (GET_CODE (src) == REG |
4073 | && IN_RANGE_P (REGNO (src), | |
4074 | FIRST_VIRTUAL_REGISTER, | |
32990d5b | 4075 | LAST_VIRTUAL_POINTER_REGISTER)))) |
36a05131 BS |
4076 | { |
4077 | emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src))); | |
4078 | return TRUE; | |
4079 | } | |
4080 | ||
4081 | /* Explicitly add in the PIC or small data register if needed. */ | |
4082 | switch (GET_CODE (src)) | |
4083 | { | |
4084 | default: | |
4085 | break; | |
4086 | ||
4087 | case LABEL_REF: | |
34208acf AO |
4088 | handle_label: |
4089 | if (TARGET_FDPIC) | |
4090 | { | |
4091 | /* Using GPREL12, we use a single GOT entry for all symbols | |
4092 | in read-only sections, but trade sequences such as: | |
4093 | ||
4094 | sethi #gothi(label), gr# | |
4095 | setlo #gotlo(label), gr# | |
4096 | ld @(gr15,gr#), gr# | |
4097 | ||
4098 | for | |
4099 | ||
4100 | ld @(gr15,#got12(_gp)), gr# | |
4101 | sethi #gprelhi(label), gr## | |
4102 | setlo #gprello(label), gr## | |
4103 | add gr#, gr##, gr## | |
4104 | ||
4105 | We may often be able to share gr# for multiple | |
4106 | computations of GPREL addresses, and we may often fold | |
4107 | the final add into the pair of registers of a load or | |
4108 | store instruction, so it's often profitable. Even when | |
4109 | optimizing for size, we're trading a GOT entry for an | |
4110 | additional instruction, which trades GOT space | |
4111 | (read-write) for code size (read-only, shareable), as | |
4112 | long as the symbol is not used in more than two different | |
4113 | locations. | |
2396bce1 | 4114 | |
34208acf AO |
4115 | With -fpie/-fpic, we'd be trading a single load for a |
4116 | sequence of 4 instructions, because the offset of the | |
4ee31f1e | 4117 | label can't be assumed to be addressable with 12 bits, so |
34208acf AO |
4118 | we don't do this. */ |
4119 | if (TARGET_GPREL_RO) | |
4120 | unspec = R_FRV_GPREL12; | |
4121 | else | |
4122 | unspec = R_FRV_GOT12; | |
4123 | } | |
4124 | else if (flag_pic) | |
36a05131 BS |
4125 | base_regno = PIC_REGNO; |
4126 | ||
4127 | break; | |
4128 | ||
4129 | case CONST: | |
34208acf AO |
4130 | if (frv_const_unspec_p (src, &old_unspec)) |
4131 | break; | |
36a05131 | 4132 | |
34208acf AO |
4133 | if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0))) |
4134 | { | |
4135 | handle_whatever: | |
4136 | src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0)); | |
4137 | emit_move_insn (dest, src); | |
4138 | return TRUE; | |
4139 | } | |
4140 | else | |
4141 | { | |
4142 | sym = XEXP (sym, 0); | |
4143 | if (GET_CODE (sym) == PLUS | |
4144 | && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF | |
4145 | && GET_CODE (XEXP (sym, 1)) == CONST_INT) | |
4146 | sym = XEXP (sym, 0); | |
4147 | if (GET_CODE (sym) == SYMBOL_REF) | |
4148 | goto handle_sym; | |
4149 | else if (GET_CODE (sym) == LABEL_REF) | |
4150 | goto handle_label; | |
4151 | else | |
4152 | goto handle_whatever; | |
4153 | } | |
36a05131 BS |
4154 | break; |
4155 | ||
4156 | case SYMBOL_REF: | |
34208acf AO |
4157 | handle_sym: |
4158 | if (TARGET_FDPIC) | |
4159 | { | |
bef8809e AH |
4160 | enum tls_model model = SYMBOL_REF_TLS_MODEL (sym); |
4161 | ||
4162 | if (model != 0) | |
4163 | { | |
4164 | src = frv_legitimize_tls_address (src, model); | |
4165 | emit_move_insn (dest, src); | |
4166 | return TRUE; | |
4167 | } | |
4168 | ||
34208acf AO |
4169 | if (SYMBOL_REF_FUNCTION_P (sym)) |
4170 | { | |
4171 | if (frv_local_funcdesc_p (sym)) | |
4172 | unspec = R_FRV_FUNCDESC_GOTOFF12; | |
4173 | else | |
4174 | unspec = R_FRV_FUNCDESC_GOT12; | |
4175 | } | |
4176 | else | |
4177 | { | |
4178 | if (CONSTANT_POOL_ADDRESS_P (sym)) | |
4179 | switch (GET_CODE (get_pool_constant (sym))) | |
4180 | { | |
4181 | case CONST: | |
4182 | case SYMBOL_REF: | |
4183 | case LABEL_REF: | |
4184 | if (flag_pic) | |
4185 | { | |
4186 | unspec = R_FRV_GOTOFF12; | |
4187 | break; | |
4188 | } | |
4189 | /* Fall through. */ | |
4190 | default: | |
4191 | if (TARGET_GPREL_RO) | |
4192 | unspec = R_FRV_GPREL12; | |
4193 | else | |
4194 | unspec = R_FRV_GOT12; | |
4195 | break; | |
4196 | } | |
4197 | else if (SYMBOL_REF_LOCAL_P (sym) | |
4198 | && !SYMBOL_REF_EXTERNAL_P (sym) | |
4199 | && SYMBOL_REF_DECL (sym) | |
4200 | && (!DECL_P (SYMBOL_REF_DECL (sym)) | |
4201 | || !DECL_COMMON (SYMBOL_REF_DECL (sym)))) | |
4202 | { | |
4203 | tree decl = SYMBOL_REF_DECL (sym); | |
4204 | tree init = TREE_CODE (decl) == VAR_DECL | |
4205 | ? DECL_INITIAL (decl) | |
4206 | : TREE_CODE (decl) == CONSTRUCTOR | |
4207 | ? decl : 0; | |
4208 | int reloc = 0; | |
4209 | bool named_section, readonly; | |
4210 | ||
4211 | if (init && init != error_mark_node) | |
4212 | reloc = compute_reloc_for_constant (init); | |
2396bce1 | 4213 | |
34208acf AO |
4214 | named_section = TREE_CODE (decl) == VAR_DECL |
4215 | && lookup_attribute ("section", DECL_ATTRIBUTES (decl)); | |
4216 | readonly = decl_readonly_section (decl, reloc); | |
2396bce1 | 4217 | |
34208acf AO |
4218 | if (named_section) |
4219 | unspec = R_FRV_GOT12; | |
4220 | else if (!readonly) | |
4221 | unspec = R_FRV_GOTOFF12; | |
4222 | else if (readonly && TARGET_GPREL_RO) | |
4223 | unspec = R_FRV_GPREL12; | |
4224 | else | |
4225 | unspec = R_FRV_GOT12; | |
4226 | } | |
4227 | else | |
4228 | unspec = R_FRV_GOT12; | |
4229 | } | |
4230 | } | |
4231 | ||
4232 | else if (SYMBOL_REF_SMALL_P (sym)) | |
36a05131 BS |
4233 | base_regno = SDA_BASE_REG; |
4234 | ||
4235 | else if (flag_pic) | |
4236 | base_regno = PIC_REGNO; | |
4237 | ||
4238 | break; | |
4239 | } | |
4240 | ||
4241 | if (base_regno >= 0) | |
4242 | { | |
34208acf AO |
4243 | if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym)) |
4244 | emit_insn (gen_symGOTOFF2reg (dest, src, | |
4245 | gen_rtx_REG (Pmode, base_regno), | |
4246 | GEN_INT (R_FRV_GPREL12))); | |
4247 | else | |
4248 | emit_insn (gen_symGOTOFF2reg_hilo (dest, src, | |
4249 | gen_rtx_REG (Pmode, base_regno), | |
4250 | GEN_INT (R_FRV_GPREL12))); | |
36a05131 | 4251 | if (base_regno == PIC_REGNO) |
ad516a74 | 4252 | crtl->uses_pic_offset_table = TRUE; |
34208acf AO |
4253 | return TRUE; |
4254 | } | |
36a05131 | 4255 | |
34208acf AO |
4256 | if (unspec) |
4257 | { | |
4258 | rtx x; | |
4259 | ||
4260 | /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce | |
4261 | new uses of it once reload has begun. */ | |
44e91694 | 4262 | gcc_assert (!reload_in_progress && !reload_completed); |
34208acf AO |
4263 | |
4264 | switch (unspec) | |
4265 | { | |
4266 | case R_FRV_GOTOFF12: | |
4267 | if (!frv_small_data_reloc_p (sym, unspec)) | |
4268 | x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG, | |
4269 | GEN_INT (unspec)); | |
4270 | else | |
4271 | x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); | |
4272 | break; | |
4273 | case R_FRV_GPREL12: | |
4274 | if (!frv_small_data_reloc_p (sym, unspec)) | |
4275 | x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG, | |
4276 | GEN_INT (unspec)); | |
4277 | else | |
4278 | x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); | |
4279 | break; | |
4280 | case R_FRV_FUNCDESC_GOTOFF12: | |
4281 | if (flag_pic != 1) | |
4282 | x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG, | |
4283 | GEN_INT (unspec)); | |
4284 | else | |
4285 | x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); | |
4286 | break; | |
4287 | default: | |
4288 | if (flag_pic != 1) | |
4289 | x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG, | |
4290 | GEN_INT (unspec)); | |
4291 | else | |
4292 | x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); | |
4293 | break; | |
4294 | } | |
4295 | emit_insn (x); | |
ad516a74 | 4296 | crtl->uses_pic_offset_table = TRUE; |
36a05131 BS |
4297 | return TRUE; |
4298 | } | |
4299 | ||
34208acf | 4300 | |
36a05131 BS |
4301 | return FALSE; |
4302 | } | |
4303 | ||
4304 | \f | |
4305 | /* Return a string to output a single word move. */ | |
4306 | ||
4307 | const char * | |
f2206911 | 4308 | output_move_single (rtx operands[], rtx insn) |
36a05131 BS |
4309 | { |
4310 | rtx dest = operands[0]; | |
4311 | rtx src = operands[1]; | |
4312 | ||
4313 | if (GET_CODE (dest) == REG) | |
4314 | { | |
4315 | int dest_regno = REGNO (dest); | |
4316 | enum machine_mode mode = GET_MODE (dest); | |
4317 | ||
4318 | if (GPR_P (dest_regno)) | |
4319 | { | |
4320 | if (GET_CODE (src) == REG) | |
4321 | { | |
4322 | /* gpr <- some sort of register */ | |
4323 | int src_regno = REGNO (src); | |
4324 | ||
4325 | if (GPR_P (src_regno)) | |
4326 | return "mov %1, %0"; | |
4327 | ||
4328 | else if (FPR_P (src_regno)) | |
4329 | return "movfg %1, %0"; | |
4330 | ||
4331 | else if (SPR_P (src_regno)) | |
4332 | return "movsg %1, %0"; | |
4333 | } | |
4334 | ||
4335 | else if (GET_CODE (src) == MEM) | |
4336 | { | |
4337 | /* gpr <- memory */ | |
4338 | switch (mode) | |
4339 | { | |
4340 | default: | |
4341 | break; | |
4342 | ||
4343 | case QImode: | |
4344 | return "ldsb%I1%U1 %M1,%0"; | |
4345 | ||
4346 | case HImode: | |
4347 | return "ldsh%I1%U1 %M1,%0"; | |
4348 | ||
4349 | case SImode: | |
4350 | case SFmode: | |
4351 | return "ld%I1%U1 %M1, %0"; | |
4352 | } | |
4353 | } | |
4354 | ||
4355 | else if (GET_CODE (src) == CONST_INT | |
4356 | || GET_CODE (src) == CONST_DOUBLE) | |
4357 | { | |
4358 | /* gpr <- integer/floating constant */ | |
4359 | HOST_WIDE_INT value; | |
4360 | ||
4361 | if (GET_CODE (src) == CONST_INT) | |
4362 | value = INTVAL (src); | |
4363 | ||
4364 | else if (mode == SFmode) | |
4365 | { | |
4366 | REAL_VALUE_TYPE rv; | |
4367 | long l; | |
4368 | ||
4369 | REAL_VALUE_FROM_CONST_DOUBLE (rv, src); | |
4370 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
4371 | value = l; | |
4372 | } | |
4373 | ||
4374 | else | |
4375 | value = CONST_DOUBLE_LOW (src); | |
4376 | ||
4377 | if (IN_RANGE_P (value, -32768, 32767)) | |
4378 | return "setlos %1, %0"; | |
4379 | ||
4380 | return "#"; | |
4381 | } | |
4382 | ||
4383 | else if (GET_CODE (src) == SYMBOL_REF | |
4384 | || GET_CODE (src) == LABEL_REF | |
4385 | || GET_CODE (src) == CONST) | |
4386 | { | |
36a05131 BS |
4387 | return "#"; |
4388 | } | |
4389 | } | |
4390 | ||
4391 | else if (FPR_P (dest_regno)) | |
4392 | { | |
4393 | if (GET_CODE (src) == REG) | |
4394 | { | |
4395 | /* fpr <- some sort of register */ | |
4396 | int src_regno = REGNO (src); | |
4397 | ||
4398 | if (GPR_P (src_regno)) | |
4399 | return "movgf %1, %0"; | |
4400 | ||
4401 | else if (FPR_P (src_regno)) | |
4402 | { | |
4403 | if (TARGET_HARD_FLOAT) | |
4404 | return "fmovs %1, %0"; | |
4405 | else | |
4406 | return "mor %1, %1, %0"; | |
4407 | } | |
4408 | } | |
4409 | ||
4410 | else if (GET_CODE (src) == MEM) | |
4411 | { | |
4412 | /* fpr <- memory */ | |
4413 | switch (mode) | |
4414 | { | |
4415 | default: | |
4416 | break; | |
4417 | ||
4418 | case QImode: | |
4419 | return "ldbf%I1%U1 %M1,%0"; | |
4420 | ||
4421 | case HImode: | |
4422 | return "ldhf%I1%U1 %M1,%0"; | |
4423 | ||
4424 | case SImode: | |
4425 | case SFmode: | |
4426 | return "ldf%I1%U1 %M1, %0"; | |
4427 | } | |
4428 | } | |
4429 | ||
4430 | else if (ZERO_P (src)) | |
4431 | return "movgf %., %0"; | |
4432 | } | |
4433 | ||
4434 | else if (SPR_P (dest_regno)) | |
4435 | { | |
4436 | if (GET_CODE (src) == REG) | |
4437 | { | |
4438 | /* spr <- some sort of register */ | |
4439 | int src_regno = REGNO (src); | |
4440 | ||
4441 | if (GPR_P (src_regno)) | |
4442 | return "movgs %1, %0"; | |
4443 | } | |
c557edf4 RS |
4444 | else if (ZERO_P (src)) |
4445 | return "movgs %., %0"; | |
36a05131 BS |
4446 | } |
4447 | } | |
4448 | ||
4449 | else if (GET_CODE (dest) == MEM) | |
4450 | { | |
4451 | if (GET_CODE (src) == REG) | |
4452 | { | |
4453 | int src_regno = REGNO (src); | |
4454 | enum machine_mode mode = GET_MODE (dest); | |
4455 | ||
4456 | if (GPR_P (src_regno)) | |
4457 | { | |
4458 | switch (mode) | |
4459 | { | |
4460 | default: | |
4461 | break; | |
4462 | ||
4463 | case QImode: | |
4464 | return "stb%I0%U0 %1, %M0"; | |
4465 | ||
4466 | case HImode: | |
4467 | return "sth%I0%U0 %1, %M0"; | |
4468 | ||
4469 | case SImode: | |
4470 | case SFmode: | |
4471 | return "st%I0%U0 %1, %M0"; | |
4472 | } | |
4473 | } | |
4474 | ||
4475 | else if (FPR_P (src_regno)) | |
4476 | { | |
4477 | switch (mode) | |
4478 | { | |
4479 | default: | |
4480 | break; | |
4481 | ||
4482 | case QImode: | |
4483 | return "stbf%I0%U0 %1, %M0"; | |
4484 | ||
4485 | case HImode: | |
4486 | return "sthf%I0%U0 %1, %M0"; | |
4487 | ||
4488 | case SImode: | |
4489 | case SFmode: | |
4490 | return "stf%I0%U0 %1, %M0"; | |
4491 | } | |
4492 | } | |
4493 | } | |
4494 | ||
4495 | else if (ZERO_P (src)) | |
4496 | { | |
4497 | switch (GET_MODE (dest)) | |
4498 | { | |
4499 | default: | |
4500 | break; | |
4501 | ||
4502 | case QImode: | |
4503 | return "stb%I0%U0 %., %M0"; | |
4504 | ||
4505 | case HImode: | |
4506 | return "sth%I0%U0 %., %M0"; | |
4507 | ||
4508 | case SImode: | |
4509 | case SFmode: | |
4510 | return "st%I0%U0 %., %M0"; | |
4511 | } | |
4512 | } | |
4513 | } | |
4514 | ||
ab532386 | 4515 | fatal_insn ("bad output_move_single operand", insn); |
36a05131 BS |
4516 | return ""; |
4517 | } | |
4518 | ||
4519 | \f | |
4520 | /* Return a string to output a double word move. */ | |
4521 | ||
4522 | const char * | |
f2206911 | 4523 | output_move_double (rtx operands[], rtx insn) |
36a05131 BS |
4524 | { |
4525 | rtx dest = operands[0]; | |
4526 | rtx src = operands[1]; | |
4527 | enum machine_mode mode = GET_MODE (dest); | |
4528 | ||
4529 | if (GET_CODE (dest) == REG) | |
4530 | { | |
4531 | int dest_regno = REGNO (dest); | |
4532 | ||
4533 | if (GPR_P (dest_regno)) | |
4534 | { | |
4535 | if (GET_CODE (src) == REG) | |
4536 | { | |
4537 | /* gpr <- some sort of register */ | |
4538 | int src_regno = REGNO (src); | |
4539 | ||
4540 | if (GPR_P (src_regno)) | |
4541 | return "#"; | |
4542 | ||
4543 | else if (FPR_P (src_regno)) | |
4544 | { | |
4545 | if (((dest_regno - GPR_FIRST) & 1) == 0 | |
4546 | && ((src_regno - FPR_FIRST) & 1) == 0) | |
4547 | return "movfgd %1, %0"; | |
4548 | ||
4549 | return "#"; | |
4550 | } | |
4551 | } | |
4552 | ||
4553 | else if (GET_CODE (src) == MEM) | |
4554 | { | |
4555 | /* gpr <- memory */ | |
4556 | if (dbl_memory_one_insn_operand (src, mode)) | |
4557 | return "ldd%I1%U1 %M1, %0"; | |
4558 | ||
4559 | return "#"; | |
4560 | } | |
4561 | ||
4562 | else if (GET_CODE (src) == CONST_INT | |
4563 | || GET_CODE (src) == CONST_DOUBLE) | |
4564 | return "#"; | |
4565 | } | |
4566 | ||
4567 | else if (FPR_P (dest_regno)) | |
4568 | { | |
4569 | if (GET_CODE (src) == REG) | |
4570 | { | |
4571 | /* fpr <- some sort of register */ | |
4572 | int src_regno = REGNO (src); | |
4573 | ||
4574 | if (GPR_P (src_regno)) | |
4575 | { | |
4576 | if (((dest_regno - FPR_FIRST) & 1) == 0 | |
4577 | && ((src_regno - GPR_FIRST) & 1) == 0) | |
4578 | return "movgfd %1, %0"; | |
4579 | ||
4580 | return "#"; | |
4581 | } | |
4582 | ||
4583 | else if (FPR_P (src_regno)) | |
4584 | { | |
4585 | if (TARGET_DOUBLE | |
4586 | && ((dest_regno - FPR_FIRST) & 1) == 0 | |
4587 | && ((src_regno - FPR_FIRST) & 1) == 0) | |
4588 | return "fmovd %1, %0"; | |
4589 | ||
4590 | return "#"; | |
4591 | } | |
4592 | } | |
4593 | ||
4594 | else if (GET_CODE (src) == MEM) | |
4595 | { | |
4596 | /* fpr <- memory */ | |
4597 | if (dbl_memory_one_insn_operand (src, mode)) | |
4598 | return "lddf%I1%U1 %M1, %0"; | |
4599 | ||
4600 | return "#"; | |
4601 | } | |
4602 | ||
4603 | else if (ZERO_P (src)) | |
4604 | return "#"; | |
4605 | } | |
4606 | } | |
4607 | ||
4608 | else if (GET_CODE (dest) == MEM) | |
4609 | { | |
4610 | if (GET_CODE (src) == REG) | |
4611 | { | |
4612 | int src_regno = REGNO (src); | |
4613 | ||
4614 | if (GPR_P (src_regno)) | |
4615 | { | |
4616 | if (((src_regno - GPR_FIRST) & 1) == 0 | |
4617 | && dbl_memory_one_insn_operand (dest, mode)) | |
4618 | return "std%I0%U0 %1, %M0"; | |
4619 | ||
4620 | return "#"; | |
4621 | } | |
4622 | ||
4623 | if (FPR_P (src_regno)) | |
4624 | { | |
4625 | if (((src_regno - FPR_FIRST) & 1) == 0 | |
4626 | && dbl_memory_one_insn_operand (dest, mode)) | |
4627 | return "stdf%I0%U0 %1, %M0"; | |
4628 | ||
4629 | return "#"; | |
4630 | } | |
4631 | } | |
4632 | ||
4633 | else if (ZERO_P (src)) | |
4634 | { | |
4635 | if (dbl_memory_one_insn_operand (dest, mode)) | |
4636 | return "std%I0%U0 %., %M0"; | |
4637 | ||
4638 | return "#"; | |
4639 | } | |
4640 | } | |
4641 | ||
ab532386 | 4642 | fatal_insn ("bad output_move_double operand", insn); |
36a05131 BS |
4643 | return ""; |
4644 | } | |
4645 | ||
4646 | \f | |
4647 | /* Return a string to output a single word conditional move. | |
4648 | Operand0 -- EQ/NE of ccr register and 0 | |
4649 | Operand1 -- CCR register | |
4650 | Operand2 -- destination | |
4651 | Operand3 -- source */ | |
4652 | ||
4653 | const char * | |
f2206911 | 4654 | output_condmove_single (rtx operands[], rtx insn) |
36a05131 BS |
4655 | { |
4656 | rtx dest = operands[2]; | |
4657 | rtx src = operands[3]; | |
4658 | ||
4659 | if (GET_CODE (dest) == REG) | |
4660 | { | |
4661 | int dest_regno = REGNO (dest); | |
4662 | enum machine_mode mode = GET_MODE (dest); | |
4663 | ||
4664 | if (GPR_P (dest_regno)) | |
4665 | { | |
4666 | if (GET_CODE (src) == REG) | |
4667 | { | |
4668 | /* gpr <- some sort of register */ | |
4669 | int src_regno = REGNO (src); | |
4670 | ||
4671 | if (GPR_P (src_regno)) | |
4672 | return "cmov %z3, %2, %1, %e0"; | |
4673 | ||
4674 | else if (FPR_P (src_regno)) | |
4675 | return "cmovfg %3, %2, %1, %e0"; | |
4676 | } | |
4677 | ||
4678 | else if (GET_CODE (src) == MEM) | |
4679 | { | |
4680 | /* gpr <- memory */ | |
4681 | switch (mode) | |
4682 | { | |
4683 | default: | |
4684 | break; | |
4685 | ||
4686 | case QImode: | |
4687 | return "cldsb%I3%U3 %M3, %2, %1, %e0"; | |
4688 | ||
4689 | case HImode: | |
4690 | return "cldsh%I3%U3 %M3, %2, %1, %e0"; | |
4691 | ||
4692 | case SImode: | |
4693 | case SFmode: | |
4694 | return "cld%I3%U3 %M3, %2, %1, %e0"; | |
4695 | } | |
4696 | } | |
4697 | ||
4698 | else if (ZERO_P (src)) | |
4699 | return "cmov %., %2, %1, %e0"; | |
4700 | } | |
4701 | ||
4702 | else if (FPR_P (dest_regno)) | |
4703 | { | |
4704 | if (GET_CODE (src) == REG) | |
4705 | { | |
4706 | /* fpr <- some sort of register */ | |
4707 | int src_regno = REGNO (src); | |
4708 | ||
4709 | if (GPR_P (src_regno)) | |
4710 | return "cmovgf %3, %2, %1, %e0"; | |
4711 | ||
4712 | else if (FPR_P (src_regno)) | |
4713 | { | |
4714 | if (TARGET_HARD_FLOAT) | |
4715 | return "cfmovs %3,%2,%1,%e0"; | |
4716 | else | |
4717 | return "cmor %3, %3, %2, %1, %e0"; | |
4718 | } | |
4719 | } | |
4720 | ||
4721 | else if (GET_CODE (src) == MEM) | |
4722 | { | |
4723 | /* fpr <- memory */ | |
4724 | if (mode == SImode || mode == SFmode) | |
4725 | return "cldf%I3%U3 %M3, %2, %1, %e0"; | |
4726 | } | |
4727 | ||
4728 | else if (ZERO_P (src)) | |
4729 | return "cmovgf %., %2, %1, %e0"; | |
4730 | } | |
4731 | } | |
4732 | ||
4733 | else if (GET_CODE (dest) == MEM) | |
4734 | { | |
4735 | if (GET_CODE (src) == REG) | |
4736 | { | |
4737 | int src_regno = REGNO (src); | |
4738 | enum machine_mode mode = GET_MODE (dest); | |
4739 | ||
4740 | if (GPR_P (src_regno)) | |
4741 | { | |
4742 | switch (mode) | |
4743 | { | |
4744 | default: | |
4745 | break; | |
4746 | ||
4747 | case QImode: | |
4748 | return "cstb%I2%U2 %3, %M2, %1, %e0"; | |
4749 | ||
4750 | case HImode: | |
4751 | return "csth%I2%U2 %3, %M2, %1, %e0"; | |
4752 | ||
4753 | case SImode: | |
4754 | case SFmode: | |
4755 | return "cst%I2%U2 %3, %M2, %1, %e0"; | |
4756 | } | |
4757 | } | |
4758 | ||
4759 | else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode)) | |
4760 | return "cstf%I2%U2 %3, %M2, %1, %e0"; | |
4761 | } | |
4762 | ||
4763 | else if (ZERO_P (src)) | |
4764 | { | |
4765 | enum machine_mode mode = GET_MODE (dest); | |
4766 | switch (mode) | |
4767 | { | |
4768 | default: | |
4769 | break; | |
4770 | ||
4771 | case QImode: | |
4772 | return "cstb%I2%U2 %., %M2, %1, %e0"; | |
4773 | ||
4774 | case HImode: | |
4775 | return "csth%I2%U2 %., %M2, %1, %e0"; | |
4776 | ||
4777 | case SImode: | |
4778 | case SFmode: | |
4779 | return "cst%I2%U2 %., %M2, %1, %e0"; | |
4780 | } | |
4781 | } | |
4782 | } | |
4783 | ||
ab532386 | 4784 | fatal_insn ("bad output_condmove_single operand", insn); |
36a05131 BS |
4785 | return ""; |
4786 | } | |
4787 | ||
4788 | \f | |
4789 | /* Emit the appropriate code to do a comparison, returning the register the | |
4790 | comparison was done it. */ | |
4791 | ||
4792 | static rtx | |
f2206911 | 4793 | frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1) |
36a05131 BS |
4794 | { |
4795 | enum machine_mode cc_mode; | |
4796 | rtx cc_reg; | |
4797 | ||
87b483a1 | 4798 | /* Floating point doesn't have comparison against a constant. */ |
36a05131 BS |
4799 | if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG) |
4800 | op1 = force_reg (GET_MODE (op0), op1); | |
4801 | ||
4802 | /* Possibly disable using anything but a fixed register in order to work | |
4803 | around cse moving comparisons past function calls. */ | |
4804 | cc_mode = SELECT_CC_MODE (test, op0, op1); | |
4805 | cc_reg = ((TARGET_ALLOC_CC) | |
4806 | ? gen_reg_rtx (cc_mode) | |
4807 | : gen_rtx_REG (cc_mode, | |
4808 | (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST)); | |
4809 | ||
4810 | emit_insn (gen_rtx_SET (VOIDmode, cc_reg, | |
4811 | gen_rtx_COMPARE (cc_mode, op0, op1))); | |
4812 | ||
4813 | return cc_reg; | |
4814 | } | |
4815 | ||
4816 | \f | |
f90b7a5a | 4817 | /* Emit code for a conditional branch. |
36a05131 BS |
4818 | XXX: I originally wanted to add a clobber of a CCR register to use in |
4819 | conditional execution, but that confuses the rest of the compiler. */ | |
4820 | ||
4821 | int | |
f90b7a5a | 4822 | frv_emit_cond_branch (rtx operands[]) |
36a05131 BS |
4823 | { |
4824 | rtx test_rtx; | |
4825 | rtx label_ref; | |
4826 | rtx if_else; | |
f90b7a5a PB |
4827 | enum rtx_code test = GET_CODE (operands[0]); |
4828 | rtx cc_reg = frv_emit_comparison (test, operands[1], operands[2]); | |
36a05131 BS |
4829 | enum machine_mode cc_mode = GET_MODE (cc_reg); |
4830 | ||
4831 | /* Branches generate: | |
4832 | (set (pc) | |
4833 | (if_then_else (<test>, <cc_reg>, (const_int 0)) | |
4834 | (label_ref <branch_label>) | |
4835 | (pc))) */ | |
f90b7a5a | 4836 | label_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]); |
1c563bed | 4837 | test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx); |
36a05131 BS |
4838 | if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx); |
4839 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else)); | |
4840 | return TRUE; | |
4841 | } | |
4842 | ||
4843 | \f | |
f90b7a5a | 4844 | /* Emit code to set a gpr to 1/0 based on a comparison. */ |
36a05131 BS |
4845 | |
4846 | int | |
f90b7a5a | 4847 | frv_emit_scc (rtx operands[]) |
36a05131 BS |
4848 | { |
4849 | rtx set; | |
4850 | rtx test_rtx; | |
4851 | rtx clobber; | |
4852 | rtx cr_reg; | |
f90b7a5a PB |
4853 | enum rtx_code test = GET_CODE (operands[1]); |
4854 | rtx cc_reg = frv_emit_comparison (test, operands[2], operands[3]); | |
36a05131 BS |
4855 | |
4856 | /* SCC instructions generate: | |
4857 | (parallel [(set <target> (<test>, <cc_reg>, (const_int 0)) | |
4858 | (clobber (<ccr_reg>))]) */ | |
4859 | test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx); | |
f90b7a5a | 4860 | set = gen_rtx_SET (VOIDmode, operands[0], test_rtx); |
36a05131 BS |
4861 | |
4862 | cr_reg = ((TARGET_ALLOC_CC) | |
4863 | ? gen_reg_rtx (CC_CCRmode) | |
4864 | : gen_rtx_REG (CC_CCRmode, | |
4865 | ((GET_MODE (cc_reg) == CC_FPmode) | |
4866 | ? FCR_FIRST | |
4867 | : ICR_FIRST))); | |
4868 | ||
4869 | clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg); | |
4870 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber))); | |
4871 | return TRUE; | |
4872 | } | |
4873 | ||
4874 | \f | |
4875 | /* Split a SCC instruction into component parts, returning a SEQUENCE to hold | |
839a4992 | 4876 | the separate insns. */ |
36a05131 BS |
4877 | |
4878 | rtx | |
f2206911 | 4879 | frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value) |
36a05131 BS |
4880 | { |
4881 | rtx ret; | |
4882 | ||
4883 | start_sequence (); | |
4884 | ||
4885 | /* Set the appropriate CCR bit. */ | |
4886 | emit_insn (gen_rtx_SET (VOIDmode, | |
4887 | cr_reg, | |
4888 | gen_rtx_fmt_ee (GET_CODE (test), | |
4889 | GET_MODE (cr_reg), | |
4890 | cc_reg, | |
4891 | const0_rtx))); | |
4892 | ||
4893 | /* Move the value into the destination. */ | |
4894 | emit_move_insn (dest, GEN_INT (value)); | |
4895 | ||
4896 | /* Move 0 into the destination if the test failed */ | |
4897 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
4898 | gen_rtx_EQ (GET_MODE (cr_reg), | |
4899 | cr_reg, | |
4900 | const0_rtx), | |
4901 | gen_rtx_SET (VOIDmode, dest, const0_rtx))); | |
4902 | ||
4903 | /* Finish up, return sequence. */ | |
4904 | ret = get_insns (); | |
4905 | end_sequence (); | |
4906 | return ret; | |
4907 | } | |
4908 | ||
4909 | \f | |
4910 | /* Emit the code for a conditional move, return TRUE if we could do the | |
4911 | move. */ | |
4912 | ||
4913 | int | |
f2206911 | 4914 | frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2) |
36a05131 BS |
4915 | { |
4916 | rtx set; | |
4917 | rtx clobber_cc; | |
4918 | rtx test2; | |
4919 | rtx cr_reg; | |
4920 | rtx if_rtx; | |
4921 | enum rtx_code test = GET_CODE (test_rtx); | |
f90b7a5a PB |
4922 | rtx cc_reg = frv_emit_comparison (test, |
4923 | XEXP (test_rtx, 0), XEXP (test_rtx, 1)); | |
36a05131 BS |
4924 | enum machine_mode cc_mode = GET_MODE (cc_reg); |
4925 | ||
4926 | /* Conditional move instructions generate: | |
4927 | (parallel [(set <target> | |
4928 | (if_then_else (<test> <cc_reg> (const_int 0)) | |
4929 | <src1> | |
4930 | <src2>)) | |
4931 | (clobber (<ccr_reg>))]) */ | |
4932 | ||
4933 | /* Handle various cases of conditional move involving two constants. */ | |
4934 | if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT) | |
4935 | { | |
4936 | HOST_WIDE_INT value1 = INTVAL (src1); | |
4937 | HOST_WIDE_INT value2 = INTVAL (src2); | |
4938 | ||
87b483a1 | 4939 | /* Having 0 as one of the constants can be done by loading the other |
36a05131 BS |
4940 | constant, and optionally moving in gr0. */ |
4941 | if (value1 == 0 || value2 == 0) | |
4942 | ; | |
4943 | ||
4944 | /* If the first value is within an addi range and also the difference | |
4945 | between the two fits in an addi's range, load up the difference, then | |
4946 | conditionally move in 0, and then unconditionally add the first | |
4947 | value. */ | |
4948 | else if (IN_RANGE_P (value1, -2048, 2047) | |
4949 | && IN_RANGE_P (value2 - value1, -2048, 2047)) | |
4950 | ; | |
4951 | ||
4952 | /* If neither condition holds, just force the constant into a | |
4953 | register. */ | |
4954 | else | |
4955 | { | |
4956 | src1 = force_reg (GET_MODE (dest), src1); | |
4957 | src2 = force_reg (GET_MODE (dest), src2); | |
4958 | } | |
4959 | } | |
4960 | ||
4961 | /* If one value is a register, insure the other value is either 0 or a | |
4962 | register. */ | |
4963 | else | |
4964 | { | |
4965 | if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0) | |
4966 | src1 = force_reg (GET_MODE (dest), src1); | |
4967 | ||
4968 | if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0) | |
4969 | src2 = force_reg (GET_MODE (dest), src2); | |
4970 | } | |
4971 | ||
4972 | test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx); | |
4973 | if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2); | |
4974 | ||
4975 | set = gen_rtx_SET (VOIDmode, dest, if_rtx); | |
4976 | ||
4977 | cr_reg = ((TARGET_ALLOC_CC) | |
4978 | ? gen_reg_rtx (CC_CCRmode) | |
4979 | : gen_rtx_REG (CC_CCRmode, | |
4980 | (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST)); | |
4981 | ||
4982 | clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg); | |
4983 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc))); | |
4984 | return TRUE; | |
4985 | } | |
4986 | ||
4987 | \f | |
839a4992 | 4988 | /* Split a conditional move into constituent parts, returning a SEQUENCE |
36a05131 BS |
4989 | containing all of the insns. */ |
4990 | ||
4991 | rtx | |
f2206911 | 4992 | frv_split_cond_move (rtx operands[]) |
36a05131 BS |
4993 | { |
4994 | rtx dest = operands[0]; | |
4995 | rtx test = operands[1]; | |
4996 | rtx cc_reg = operands[2]; | |
4997 | rtx src1 = operands[3]; | |
4998 | rtx src2 = operands[4]; | |
4999 | rtx cr_reg = operands[5]; | |
5000 | rtx ret; | |
5001 | enum machine_mode cr_mode = GET_MODE (cr_reg); | |
5002 | ||
5003 | start_sequence (); | |
5004 | ||
5005 | /* Set the appropriate CCR bit. */ | |
5006 | emit_insn (gen_rtx_SET (VOIDmode, | |
5007 | cr_reg, | |
5008 | gen_rtx_fmt_ee (GET_CODE (test), | |
5009 | GET_MODE (cr_reg), | |
5010 | cc_reg, | |
5011 | const0_rtx))); | |
5012 | ||
5013 | /* Handle various cases of conditional move involving two constants. */ | |
5014 | if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT) | |
5015 | { | |
5016 | HOST_WIDE_INT value1 = INTVAL (src1); | |
5017 | HOST_WIDE_INT value2 = INTVAL (src2); | |
5018 | ||
87b483a1 | 5019 | /* Having 0 as one of the constants can be done by loading the other |
36a05131 BS |
5020 | constant, and optionally moving in gr0. */ |
5021 | if (value1 == 0) | |
5022 | { | |
5023 | emit_move_insn (dest, src2); | |
5024 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
5025 | gen_rtx_NE (cr_mode, cr_reg, | |
5026 | const0_rtx), | |
5027 | gen_rtx_SET (VOIDmode, dest, src1))); | |
5028 | } | |
5029 | ||
5030 | else if (value2 == 0) | |
5031 | { | |
5032 | emit_move_insn (dest, src1); | |
5033 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
5034 | gen_rtx_EQ (cr_mode, cr_reg, | |
5035 | const0_rtx), | |
5036 | gen_rtx_SET (VOIDmode, dest, src2))); | |
5037 | } | |
5038 | ||
5039 | /* If the first value is within an addi range and also the difference | |
5040 | between the two fits in an addi's range, load up the difference, then | |
5041 | conditionally move in 0, and then unconditionally add the first | |
5042 | value. */ | |
5043 | else if (IN_RANGE_P (value1, -2048, 2047) | |
5044 | && IN_RANGE_P (value2 - value1, -2048, 2047)) | |
5045 | { | |
5046 | rtx dest_si = ((GET_MODE (dest) == SImode) | |
5047 | ? dest | |
5048 | : gen_rtx_SUBREG (SImode, dest, 0)); | |
5049 | ||
5050 | emit_move_insn (dest_si, GEN_INT (value2 - value1)); | |
5051 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
5052 | gen_rtx_NE (cr_mode, cr_reg, | |
5053 | const0_rtx), | |
5054 | gen_rtx_SET (VOIDmode, dest_si, | |
5055 | const0_rtx))); | |
5056 | emit_insn (gen_addsi3 (dest_si, dest_si, src1)); | |
5057 | } | |
5058 | ||
5059 | else | |
44e91694 | 5060 | gcc_unreachable (); |
36a05131 BS |
5061 | } |
5062 | else | |
5063 | { | |
5064 | /* Emit the conditional move for the test being true if needed. */ | |
5065 | if (! rtx_equal_p (dest, src1)) | |
5066 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
5067 | gen_rtx_NE (cr_mode, cr_reg, const0_rtx), | |
5068 | gen_rtx_SET (VOIDmode, dest, src1))); | |
5069 | ||
5070 | /* Emit the conditional move for the test being false if needed. */ | |
5071 | if (! rtx_equal_p (dest, src2)) | |
5072 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
5073 | gen_rtx_EQ (cr_mode, cr_reg, const0_rtx), | |
5074 | gen_rtx_SET (VOIDmode, dest, src2))); | |
5075 | } | |
5076 | ||
5077 | /* Finish up, return sequence. */ | |
5078 | ret = get_insns (); | |
5079 | end_sequence (); | |
5080 | return ret; | |
5081 | } | |
5082 | ||
5083 | \f | |
5084 | /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a | |
5085 | memory location that is not known to be dword-aligned. */ | |
5086 | void | |
f2206911 | 5087 | frv_split_double_load (rtx dest, rtx source) |
36a05131 BS |
5088 | { |
5089 | int regno = REGNO (dest); | |
5090 | rtx dest1 = gen_highpart (SImode, dest); | |
5091 | rtx dest2 = gen_lowpart (SImode, dest); | |
5092 | rtx address = XEXP (source, 0); | |
5093 | ||
5094 | /* If the address is pre-modified, load the lower-numbered register | |
5095 | first, then load the other register using an integer offset from | |
5096 | the modified base register. This order should always be safe, | |
5097 | since the pre-modification cannot affect the same registers as the | |
5098 | load does. | |
5099 | ||
5100 | The situation for other loads is more complicated. Loading one | |
5101 | of the registers could affect the value of ADDRESS, so we must | |
5102 | be careful which order we do them in. */ | |
5103 | if (GET_CODE (address) == PRE_MODIFY | |
5104 | || ! refers_to_regno_p (regno, regno + 1, address, NULL)) | |
5105 | { | |
5106 | /* It is safe to load the lower-numbered register first. */ | |
5107 | emit_move_insn (dest1, change_address (source, SImode, NULL)); | |
5108 | emit_move_insn (dest2, frv_index_memory (source, SImode, 1)); | |
5109 | } | |
5110 | else | |
5111 | { | |
5112 | /* ADDRESS is not pre-modified and the address depends on the | |
5113 | lower-numbered register. Load the higher-numbered register | |
5114 | first. */ | |
5115 | emit_move_insn (dest2, frv_index_memory (source, SImode, 1)); | |
5116 | emit_move_insn (dest1, change_address (source, SImode, NULL)); | |
5117 | } | |
5118 | } | |
5119 | ||
5120 | /* Split (set DEST SOURCE), where DEST refers to a dword memory location | |
5121 | and SOURCE is either a double register or the constant zero. */ | |
5122 | void | |
f2206911 | 5123 | frv_split_double_store (rtx dest, rtx source) |
36a05131 BS |
5124 | { |
5125 | rtx dest1 = change_address (dest, SImode, NULL); | |
5126 | rtx dest2 = frv_index_memory (dest, SImode, 1); | |
5127 | if (ZERO_P (source)) | |
5128 | { | |
5129 | emit_move_insn (dest1, CONST0_RTX (SImode)); | |
5130 | emit_move_insn (dest2, CONST0_RTX (SImode)); | |
5131 | } | |
5132 | else | |
5133 | { | |
5134 | emit_move_insn (dest1, gen_highpart (SImode, source)); | |
5135 | emit_move_insn (dest2, gen_lowpart (SImode, source)); | |
5136 | } | |
5137 | } | |
5138 | ||
5139 | \f | |
5140 | /* Split a min/max operation returning a SEQUENCE containing all of the | |
5141 | insns. */ | |
5142 | ||
5143 | rtx | |
f2206911 | 5144 | frv_split_minmax (rtx operands[]) |
36a05131 BS |
5145 | { |
5146 | rtx dest = operands[0]; | |
5147 | rtx minmax = operands[1]; | |
5148 | rtx src1 = operands[2]; | |
5149 | rtx src2 = operands[3]; | |
5150 | rtx cc_reg = operands[4]; | |
5151 | rtx cr_reg = operands[5]; | |
5152 | rtx ret; | |
5153 | enum rtx_code test_code; | |
5154 | enum machine_mode cr_mode = GET_MODE (cr_reg); | |
5155 | ||
5156 | start_sequence (); | |
5157 | ||
87b483a1 | 5158 | /* Figure out which test to use. */ |
36a05131 BS |
5159 | switch (GET_CODE (minmax)) |
5160 | { | |
5161 | default: | |
44e91694 | 5162 | gcc_unreachable (); |
36a05131 BS |
5163 | |
5164 | case SMIN: test_code = LT; break; | |
5165 | case SMAX: test_code = GT; break; | |
5166 | case UMIN: test_code = LTU; break; | |
5167 | case UMAX: test_code = GTU; break; | |
5168 | } | |
5169 | ||
5170 | /* Issue the compare instruction. */ | |
5171 | emit_insn (gen_rtx_SET (VOIDmode, | |
5172 | cc_reg, | |
5173 | gen_rtx_COMPARE (GET_MODE (cc_reg), | |
5174 | src1, src2))); | |
5175 | ||
5176 | /* Set the appropriate CCR bit. */ | |
5177 | emit_insn (gen_rtx_SET (VOIDmode, | |
5178 | cr_reg, | |
5179 | gen_rtx_fmt_ee (test_code, | |
5180 | GET_MODE (cr_reg), | |
5181 | cc_reg, | |
5182 | const0_rtx))); | |
5183 | ||
9cd10576 | 5184 | /* If are taking the min/max of a nonzero constant, load that first, and |
36a05131 BS |
5185 | then do a conditional move of the other value. */ |
5186 | if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0) | |
5187 | { | |
44e91694 | 5188 | gcc_assert (!rtx_equal_p (dest, src1)); |
36a05131 BS |
5189 | |
5190 | emit_move_insn (dest, src2); | |
5191 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
5192 | gen_rtx_NE (cr_mode, cr_reg, const0_rtx), | |
5193 | gen_rtx_SET (VOIDmode, dest, src1))); | |
5194 | } | |
5195 | ||
5196 | /* Otherwise, do each half of the move. */ | |
5197 | else | |
5198 | { | |
5199 | /* Emit the conditional move for the test being true if needed. */ | |
5200 | if (! rtx_equal_p (dest, src1)) | |
5201 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
5202 | gen_rtx_NE (cr_mode, cr_reg, const0_rtx), | |
5203 | gen_rtx_SET (VOIDmode, dest, src1))); | |
5204 | ||
5205 | /* Emit the conditional move for the test being false if needed. */ | |
5206 | if (! rtx_equal_p (dest, src2)) | |
5207 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
5208 | gen_rtx_EQ (cr_mode, cr_reg, const0_rtx), | |
5209 | gen_rtx_SET (VOIDmode, dest, src2))); | |
5210 | } | |
5211 | ||
5212 | /* Finish up, return sequence. */ | |
5213 | ret = get_insns (); | |
5214 | end_sequence (); | |
5215 | return ret; | |
5216 | } | |
5217 | ||
5218 | \f | |
5219 | /* Split an integer abs operation returning a SEQUENCE containing all of the | |
5220 | insns. */ | |
5221 | ||
5222 | rtx | |
f2206911 | 5223 | frv_split_abs (rtx operands[]) |
36a05131 BS |
5224 | { |
5225 | rtx dest = operands[0]; | |
5226 | rtx src = operands[1]; | |
5227 | rtx cc_reg = operands[2]; | |
5228 | rtx cr_reg = operands[3]; | |
5229 | rtx ret; | |
5230 | ||
5231 | start_sequence (); | |
5232 | ||
5233 | /* Issue the compare < 0 instruction. */ | |
5234 | emit_insn (gen_rtx_SET (VOIDmode, | |
5235 | cc_reg, | |
5236 | gen_rtx_COMPARE (CCmode, src, const0_rtx))); | |
5237 | ||
5238 | /* Set the appropriate CCR bit. */ | |
5239 | emit_insn (gen_rtx_SET (VOIDmode, | |
5240 | cr_reg, | |
5241 | gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx))); | |
5242 | ||
87b483a1 | 5243 | /* Emit the conditional negate if the value is negative. */ |
36a05131 BS |
5244 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, |
5245 | gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx), | |
5246 | gen_negsi2 (dest, src))); | |
5247 | ||
5248 | /* Emit the conditional move for the test being false if needed. */ | |
5249 | if (! rtx_equal_p (dest, src)) | |
5250 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
5251 | gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx), | |
5252 | gen_rtx_SET (VOIDmode, dest, src))); | |
5253 | ||
5254 | /* Finish up, return sequence. */ | |
5255 | ret = get_insns (); | |
5256 | end_sequence (); | |
5257 | return ret; | |
5258 | } | |
5259 | ||
5260 | \f | |
5261 | /* An internal function called by for_each_rtx to clear in a hard_reg set each | |
5262 | register used in an insn. */ | |
5263 | ||
5264 | static int | |
f2206911 | 5265 | frv_clear_registers_used (rtx *ptr, void *data) |
36a05131 BS |
5266 | { |
5267 | if (GET_CODE (*ptr) == REG) | |
5268 | { | |
5269 | int regno = REGNO (*ptr); | |
5270 | HARD_REG_SET *p_regs = (HARD_REG_SET *)data; | |
5271 | ||
5272 | if (regno < FIRST_PSEUDO_REGISTER) | |
5273 | { | |
5274 | int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr)); | |
5275 | ||
5276 | while (regno < reg_max) | |
5277 | { | |
5278 | CLEAR_HARD_REG_BIT (*p_regs, regno); | |
5279 | regno++; | |
5280 | } | |
5281 | } | |
5282 | } | |
5283 | ||
5284 | return 0; | |
5285 | } | |
5286 | ||
5287 | \f | |
5288 | /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */ | |
5289 | ||
5290 | /* On the FR-V, we don't have any extra fields per se, but it is useful hook to | |
5291 | initialize the static storage. */ | |
5292 | void | |
f2206911 | 5293 | frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED) |
36a05131 BS |
5294 | { |
5295 | frv_ifcvt.added_insns_list = NULL_RTX; | |
5296 | frv_ifcvt.cur_scratch_regs = 0; | |
5297 | frv_ifcvt.num_nested_cond_exec = 0; | |
5298 | frv_ifcvt.cr_reg = NULL_RTX; | |
5299 | frv_ifcvt.nested_cc_reg = NULL_RTX; | |
5300 | frv_ifcvt.extra_int_cr = NULL_RTX; | |
5301 | frv_ifcvt.extra_fp_cr = NULL_RTX; | |
5302 | frv_ifcvt.last_nested_if_cr = NULL_RTX; | |
5303 | } | |
5304 | ||
5305 | \f | |
1ae58c30 | 5306 | /* Internal function to add a potential insn to the list of insns to be inserted |
36a05131 BS |
5307 | if the conditional execution conversion is successful. */ |
5308 | ||
5309 | static void | |
f2206911 | 5310 | frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p) |
36a05131 BS |
5311 | { |
5312 | rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn); | |
5313 | ||
87b483a1 | 5314 | link->jump = before_p; /* Mark to add this before or after insn. */ |
36a05131 BS |
5315 | frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link, |
5316 | frv_ifcvt.added_insns_list); | |
5317 | ||
5318 | if (TARGET_DEBUG_COND_EXEC) | |
5319 | { | |
5320 | fprintf (stderr, | |
5321 | "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n", | |
5322 | (before_p) ? "before" : "after", | |
5323 | (int)INSN_UID (insn)); | |
5324 | ||
5325 | debug_rtx (pattern); | |
5326 | } | |
5327 | } | |
5328 | ||
5329 | \f | |
5330 | /* A C expression to modify the code described by the conditional if | |
5331 | information CE_INFO, possibly updating the tests in TRUE_EXPR, and | |
5332 | FALSE_EXPR for converting if-then and if-then-else code to conditional | |
5333 | instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the | |
5334 | tests cannot be converted. */ | |
5335 | ||
5336 | void | |
f2206911 | 5337 | frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false) |
36a05131 BS |
5338 | { |
5339 | basic_block test_bb = ce_info->test_bb; /* test basic block */ | |
5340 | basic_block then_bb = ce_info->then_bb; /* THEN */ | |
5341 | basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */ | |
5342 | basic_block join_bb = ce_info->join_bb; /* join block or NULL */ | |
5343 | rtx true_expr = *p_true; | |
5344 | rtx cr; | |
5345 | rtx cc; | |
5346 | rtx nested_cc; | |
5347 | enum machine_mode mode = GET_MODE (true_expr); | |
5348 | int j; | |
5349 | basic_block *bb; | |
5350 | int num_bb; | |
5351 | frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg; | |
5352 | rtx check_insn; | |
5353 | rtx sub_cond_exec_reg; | |
5354 | enum rtx_code code; | |
5355 | enum rtx_code code_true; | |
5356 | enum rtx_code code_false; | |
5357 | enum reg_class cc_class; | |
5358 | enum reg_class cr_class; | |
5359 | int cc_first; | |
5360 | int cc_last; | |
a2041967 | 5361 | reg_set_iterator rsi; |
36a05131 BS |
5362 | |
5363 | /* Make sure we are only dealing with hard registers. Also honor the | |
5364 | -mno-cond-exec switch, and -mno-nested-cond-exec switches if | |
5365 | applicable. */ | |
0b2c18fe RS |
5366 | if (!reload_completed || !TARGET_COND_EXEC |
5367 | || (!TARGET_NESTED_CE && ce_info->pass > 1)) | |
36a05131 BS |
5368 | goto fail; |
5369 | ||
5370 | /* Figure out which registers we can allocate for our own purposes. Only | |
5371 | consider registers that are not preserved across function calls and are | |
5372 | not fixed. However, allow the ICC/ICR temporary registers to be allocated | |
87b483a1 | 5373 | if we did not need to use them in reloading other registers. */ |
fad205ff | 5374 | memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs)); |
36a05131 BS |
5375 | COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set); |
5376 | AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set); | |
5377 | SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP); | |
5378 | SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP); | |
5379 | ||
5380 | /* If this is a nested IF, we need to discover whether the CC registers that | |
5381 | are set/used inside of the block are used anywhere else. If not, we can | |
5382 | change them to be the CC register that is paired with the CR register that | |
5383 | controls the outermost IF block. */ | |
5384 | if (ce_info->pass > 1) | |
5385 | { | |
5386 | CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite); | |
5387 | for (j = CC_FIRST; j <= CC_LAST; j++) | |
5388 | if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) | |
5389 | { | |
eedd7243 | 5390 | if (REGNO_REG_SET_P (df_get_live_in (then_bb), j)) |
36a05131 BS |
5391 | continue; |
5392 | ||
5e2d947c | 5393 | if (else_bb |
eedd7243 | 5394 | && REGNO_REG_SET_P (df_get_live_in (else_bb), j)) |
36a05131 BS |
5395 | continue; |
5396 | ||
5e2d947c | 5397 | if (join_bb |
eedd7243 | 5398 | && REGNO_REG_SET_P (df_get_live_in (join_bb), j)) |
36a05131 BS |
5399 | continue; |
5400 | ||
5401 | SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j); | |
5402 | } | |
5403 | } | |
5404 | ||
5405 | for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++) | |
5406 | frv_ifcvt.scratch_regs[j] = NULL_RTX; | |
5407 | ||
5408 | frv_ifcvt.added_insns_list = NULL_RTX; | |
5409 | frv_ifcvt.cur_scratch_regs = 0; | |
5410 | ||
5411 | bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks) | |
5412 | * sizeof (basic_block)); | |
5413 | ||
5414 | if (join_bb) | |
5415 | { | |
38c28a25 | 5416 | unsigned int regno; |
36a05131 BS |
5417 | |
5418 | /* Remove anything live at the beginning of the join block from being | |
5419 | available for allocation. */ | |
eedd7243 | 5420 | EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb), 0, regno, rsi) |
a2041967 KH |
5421 | { |
5422 | if (regno < FIRST_PSEUDO_REGISTER) | |
5423 | CLEAR_HARD_REG_BIT (tmp_reg->regs, regno); | |
5424 | } | |
36a05131 BS |
5425 | } |
5426 | ||
5427 | /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */ | |
5428 | num_bb = 0; | |
5429 | if (ce_info->num_multiple_test_blocks) | |
5430 | { | |
5431 | basic_block multiple_test_bb = ce_info->last_test_bb; | |
5432 | ||
5433 | while (multiple_test_bb != test_bb) | |
5434 | { | |
5435 | bb[num_bb++] = multiple_test_bb; | |
628f6a4e | 5436 | multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src; |
36a05131 BS |
5437 | } |
5438 | } | |
5439 | ||
5440 | /* Add in the THEN and ELSE blocks to be scanned. */ | |
5441 | bb[num_bb++] = then_bb; | |
5442 | if (else_bb) | |
5443 | bb[num_bb++] = else_bb; | |
5444 | ||
5445 | sub_cond_exec_reg = NULL_RTX; | |
5446 | frv_ifcvt.num_nested_cond_exec = 0; | |
5447 | ||
5448 | /* Scan all of the blocks for registers that must not be allocated. */ | |
5449 | for (j = 0; j < num_bb; j++) | |
5450 | { | |
a813c111 SB |
5451 | rtx last_insn = BB_END (bb[j]); |
5452 | rtx insn = BB_HEAD (bb[j]); | |
38c28a25 | 5453 | unsigned int regno; |
36a05131 | 5454 | |
c263766c RH |
5455 | if (dump_file) |
5456 | fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n", | |
36a05131 BS |
5457 | (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"), |
5458 | (int) bb[j]->index, | |
a813c111 SB |
5459 | (int) INSN_UID (BB_HEAD (bb[j])), |
5460 | (int) INSN_UID (BB_END (bb[j]))); | |
36a05131 BS |
5461 | |
5462 | /* Anything live at the beginning of the block is obviously unavailable | |
5463 | for allocation. */ | |
eedd7243 | 5464 | EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb[j]), 0, regno, rsi) |
a2041967 KH |
5465 | { |
5466 | if (regno < FIRST_PSEUDO_REGISTER) | |
5467 | CLEAR_HARD_REG_BIT (tmp_reg->regs, regno); | |
5468 | } | |
36a05131 | 5469 | |
87b483a1 | 5470 | /* Loop through the insns in the block. */ |
36a05131 BS |
5471 | for (;;) |
5472 | { | |
5473 | /* Mark any new registers that are created as being unavailable for | |
5474 | allocation. Also see if the CC register used in nested IFs can be | |
5475 | reallocated. */ | |
5476 | if (INSN_P (insn)) | |
5477 | { | |
5478 | rtx pattern; | |
5479 | rtx set; | |
5480 | int skip_nested_if = FALSE; | |
5481 | ||
5482 | for_each_rtx (&PATTERN (insn), frv_clear_registers_used, | |
5483 | (void *)&tmp_reg->regs); | |
5484 | ||
5485 | pattern = PATTERN (insn); | |
5486 | if (GET_CODE (pattern) == COND_EXEC) | |
5487 | { | |
5488 | rtx reg = XEXP (COND_EXEC_TEST (pattern), 0); | |
5489 | ||
5490 | if (reg != sub_cond_exec_reg) | |
5491 | { | |
5492 | sub_cond_exec_reg = reg; | |
5493 | frv_ifcvt.num_nested_cond_exec++; | |
5494 | } | |
5495 | } | |
5496 | ||
5497 | set = single_set_pattern (pattern); | |
5498 | if (set) | |
5499 | { | |
5500 | rtx dest = SET_DEST (set); | |
5501 | rtx src = SET_SRC (set); | |
5502 | ||
5503 | if (GET_CODE (dest) == REG) | |
5504 | { | |
5505 | int regno = REGNO (dest); | |
5506 | enum rtx_code src_code = GET_CODE (src); | |
5507 | ||
5508 | if (CC_P (regno) && src_code == COMPARE) | |
5509 | skip_nested_if = TRUE; | |
5510 | ||
5511 | else if (CR_P (regno) | |
5512 | && (src_code == IF_THEN_ELSE | |
ec8e098d | 5513 | || COMPARISON_P (src))) |
36a05131 BS |
5514 | skip_nested_if = TRUE; |
5515 | } | |
5516 | } | |
5517 | ||
5518 | if (! skip_nested_if) | |
5519 | for_each_rtx (&PATTERN (insn), frv_clear_registers_used, | |
5520 | (void *)&frv_ifcvt.nested_cc_ok_rewrite); | |
5521 | } | |
5522 | ||
5523 | if (insn == last_insn) | |
5524 | break; | |
5525 | ||
5526 | insn = NEXT_INSN (insn); | |
5527 | } | |
5528 | } | |
5529 | ||
5530 | /* If this is a nested if, rewrite the CC registers that are available to | |
5531 | include the ones that can be rewritten, to increase the chance of being | |
5532 | able to allocate a paired CC/CR register combination. */ | |
5533 | if (ce_info->pass > 1) | |
5534 | { | |
5535 | for (j = CC_FIRST; j <= CC_LAST; j++) | |
5536 | if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j)) | |
5537 | SET_HARD_REG_BIT (tmp_reg->regs, j); | |
5538 | else | |
5539 | CLEAR_HARD_REG_BIT (tmp_reg->regs, j); | |
5540 | } | |
5541 | ||
c263766c | 5542 | if (dump_file) |
36a05131 BS |
5543 | { |
5544 | int num_gprs = 0; | |
c263766c | 5545 | fprintf (dump_file, "Available GPRs: "); |
36a05131 BS |
5546 | |
5547 | for (j = GPR_FIRST; j <= GPR_LAST; j++) | |
5548 | if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) | |
5549 | { | |
c263766c | 5550 | fprintf (dump_file, " %d [%s]", j, reg_names[j]); |
36a05131 BS |
5551 | if (++num_gprs > GPR_TEMP_NUM+2) |
5552 | break; | |
5553 | } | |
5554 | ||
c263766c | 5555 | fprintf (dump_file, "%s\nAvailable CRs: ", |
36a05131 BS |
5556 | (num_gprs > GPR_TEMP_NUM+2) ? " ..." : ""); |
5557 | ||
5558 | for (j = CR_FIRST; j <= CR_LAST; j++) | |
5559 | if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) | |
c263766c | 5560 | fprintf (dump_file, " %d [%s]", j, reg_names[j]); |
36a05131 | 5561 | |
c263766c | 5562 | fputs ("\n", dump_file); |
36a05131 BS |
5563 | |
5564 | if (ce_info->pass > 1) | |
5565 | { | |
c263766c | 5566 | fprintf (dump_file, "Modifiable CCs: "); |
36a05131 BS |
5567 | for (j = CC_FIRST; j <= CC_LAST; j++) |
5568 | if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) | |
c263766c | 5569 | fprintf (dump_file, " %d [%s]", j, reg_names[j]); |
36a05131 | 5570 | |
c263766c | 5571 | fprintf (dump_file, "\n%d nested COND_EXEC statements\n", |
36a05131 BS |
5572 | frv_ifcvt.num_nested_cond_exec); |
5573 | } | |
5574 | } | |
5575 | ||
5576 | /* Allocate the appropriate temporary condition code register. Try to | |
5577 | allocate the ICR/FCR register that corresponds to the ICC/FCC register so | |
5578 | that conditional cmp's can be done. */ | |
036ff63f | 5579 | if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode) |
36a05131 BS |
5580 | { |
5581 | cr_class = ICR_REGS; | |
5582 | cc_class = ICC_REGS; | |
5583 | cc_first = ICC_FIRST; | |
5584 | cc_last = ICC_LAST; | |
5585 | } | |
5586 | else if (mode == CC_FPmode) | |
5587 | { | |
5588 | cr_class = FCR_REGS; | |
5589 | cc_class = FCC_REGS; | |
5590 | cc_first = FCC_FIRST; | |
5591 | cc_last = FCC_LAST; | |
5592 | } | |
5593 | else | |
5594 | { | |
5595 | cc_first = cc_last = 0; | |
5596 | cr_class = cc_class = NO_REGS; | |
5597 | } | |
5598 | ||
5599 | cc = XEXP (true_expr, 0); | |
5600 | nested_cc = cr = NULL_RTX; | |
5601 | if (cc_class != NO_REGS) | |
5602 | { | |
5603 | /* For nested IFs and &&/||, see if we can find a CC and CR register pair | |
5604 | so we can execute a csubcc/caddcc/cfcmps instruction. */ | |
5605 | int cc_regno; | |
5606 | ||
5607 | for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++) | |
5608 | { | |
5609 | int cr_regno = cc_regno - CC_FIRST + CR_FIRST; | |
5610 | ||
5611 | if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno) | |
5612 | && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno)) | |
5613 | { | |
5614 | frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno; | |
5615 | cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE, | |
5616 | TRUE); | |
5617 | ||
5618 | frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno; | |
5619 | nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode, | |
5620 | TRUE, TRUE); | |
5621 | break; | |
5622 | } | |
5623 | } | |
5624 | } | |
5625 | ||
5626 | if (! cr) | |
5627 | { | |
c263766c RH |
5628 | if (dump_file) |
5629 | fprintf (dump_file, "Could not allocate a CR temporary register\n"); | |
36a05131 BS |
5630 | |
5631 | goto fail; | |
5632 | } | |
5633 | ||
c263766c RH |
5634 | if (dump_file) |
5635 | fprintf (dump_file, | |
36a05131 BS |
5636 | "Will use %s for conditional execution, %s for nested comparisons\n", |
5637 | reg_names[ REGNO (cr)], | |
5638 | (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>"); | |
5639 | ||
5640 | /* Set the CCR bit. Note for integer tests, we reverse the condition so that | |
5641 | in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR | |
5642 | bit being true. We don't do this for floating point, because of NaNs. */ | |
5643 | code = GET_CODE (true_expr); | |
5644 | if (GET_MODE (cc) != CC_FPmode) | |
5645 | { | |
5646 | code = reverse_condition (code); | |
5647 | code_true = EQ; | |
5648 | code_false = NE; | |
5649 | } | |
5650 | else | |
5651 | { | |
5652 | code_true = NE; | |
5653 | code_false = EQ; | |
5654 | } | |
5655 | ||
5656 | check_insn = gen_rtx_SET (VOIDmode, cr, | |
5657 | gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx)); | |
5658 | ||
5659 | /* Record the check insn to be inserted later. */ | |
a813c111 | 5660 | frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE); |
36a05131 BS |
5661 | |
5662 | /* Update the tests. */ | |
5663 | frv_ifcvt.cr_reg = cr; | |
5664 | frv_ifcvt.nested_cc_reg = nested_cc; | |
5665 | *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx); | |
5666 | *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx); | |
5667 | return; | |
5668 | ||
5669 | /* Fail, don't do this conditional execution. */ | |
5670 | fail: | |
5671 | *p_true = NULL_RTX; | |
5672 | *p_false = NULL_RTX; | |
c263766c RH |
5673 | if (dump_file) |
5674 | fprintf (dump_file, "Disabling this conditional execution.\n"); | |
36a05131 BS |
5675 | |
5676 | return; | |
5677 | } | |
5678 | ||
5679 | \f | |
5680 | /* A C expression to modify the code described by the conditional if | |
5681 | information CE_INFO, for the basic block BB, possibly updating the tests in | |
5682 | TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or | |
5683 | if-then-else code to conditional instructions. Set either TRUE_EXPR or | |
5684 | FALSE_EXPR to a null pointer if the tests cannot be converted. */ | |
5685 | ||
5686 | /* p_true and p_false are given expressions of the form: | |
5687 | ||
5688 | (and (eq:CC_CCR (reg:CC_CCR) | |
5689 | (const_int 0)) | |
5690 | (eq:CC (reg:CC) | |
5691 | (const_int 0))) */ | |
5692 | ||
5693 | void | |
f2206911 KC |
5694 | frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info, |
5695 | basic_block bb, | |
5696 | rtx *p_true, | |
5697 | rtx *p_false) | |
36a05131 BS |
5698 | { |
5699 | rtx old_true = XEXP (*p_true, 0); | |
5700 | rtx old_false = XEXP (*p_false, 0); | |
5701 | rtx true_expr = XEXP (*p_true, 1); | |
5702 | rtx false_expr = XEXP (*p_false, 1); | |
5703 | rtx test_expr; | |
5704 | rtx old_test; | |
5705 | rtx cr = XEXP (old_true, 0); | |
5706 | rtx check_insn; | |
5707 | rtx new_cr = NULL_RTX; | |
5708 | rtx *p_new_cr = (rtx *)0; | |
5709 | rtx if_else; | |
5710 | rtx compare; | |
5711 | rtx cc; | |
5712 | enum reg_class cr_class; | |
5713 | enum machine_mode mode = GET_MODE (true_expr); | |
5714 | rtx (*logical_func)(rtx, rtx, rtx); | |
5715 | ||
5716 | if (TARGET_DEBUG_COND_EXEC) | |
5717 | { | |
5718 | fprintf (stderr, | |
5719 | "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n", | |
5720 | ce_info->and_and_p ? "&&" : "||"); | |
5721 | ||
5722 | debug_rtx (*p_true); | |
5723 | ||
5724 | fputs ("\nfalse insn:\n", stderr); | |
5725 | debug_rtx (*p_false); | |
5726 | } | |
5727 | ||
0b2c18fe | 5728 | if (!TARGET_MULTI_CE) |
36a05131 BS |
5729 | goto fail; |
5730 | ||
5731 | if (GET_CODE (cr) != REG) | |
5732 | goto fail; | |
b16c1435 | 5733 | |
036ff63f | 5734 | if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode) |
36a05131 BS |
5735 | { |
5736 | cr_class = ICR_REGS; | |
5737 | p_new_cr = &frv_ifcvt.extra_int_cr; | |
5738 | } | |
5739 | else if (mode == CC_FPmode) | |
5740 | { | |
5741 | cr_class = FCR_REGS; | |
5742 | p_new_cr = &frv_ifcvt.extra_fp_cr; | |
5743 | } | |
5744 | else | |
5745 | goto fail; | |
5746 | ||
5747 | /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or | |
5748 | more &&/|| tests. */ | |
5749 | new_cr = *p_new_cr; | |
5750 | if (! new_cr) | |
5751 | { | |
5752 | new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class, | |
5753 | CC_CCRmode, TRUE, TRUE); | |
5754 | if (! new_cr) | |
5755 | goto fail; | |
5756 | } | |
5757 | ||
5758 | if (ce_info->and_and_p) | |
5759 | { | |
5760 | old_test = old_false; | |
5761 | test_expr = true_expr; | |
5762 | logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr; | |
5763 | *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx); | |
5764 | *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx); | |
5765 | } | |
5766 | else | |
5767 | { | |
5768 | old_test = old_false; | |
5769 | test_expr = false_expr; | |
5770 | logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr; | |
5771 | *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx); | |
5772 | *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx); | |
5773 | } | |
5774 | ||
5775 | /* First add the andcr/andncr/orcr/orncr, which will be added after the | |
5776 | conditional check instruction, due to frv_ifcvt_add_insn being a LIFO | |
5777 | stack. */ | |
a813c111 | 5778 | frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE); |
36a05131 BS |
5779 | |
5780 | /* Now add the conditional check insn. */ | |
5781 | cc = XEXP (test_expr, 0); | |
5782 | compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx); | |
5783 | if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx); | |
5784 | ||
5785 | check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else); | |
5786 | ||
87b483a1 | 5787 | /* Add the new check insn to the list of check insns that need to be |
36a05131 | 5788 | inserted. */ |
a813c111 | 5789 | frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE); |
36a05131 BS |
5790 | |
5791 | if (TARGET_DEBUG_COND_EXEC) | |
5792 | { | |
5793 | fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n", | |
5794 | stderr); | |
5795 | ||
5796 | debug_rtx (*p_true); | |
5797 | ||
5798 | fputs ("\nfalse insn:\n", stderr); | |
5799 | debug_rtx (*p_false); | |
5800 | } | |
5801 | ||
5802 | return; | |
5803 | ||
5804 | fail: | |
5805 | *p_true = *p_false = NULL_RTX; | |
5806 | ||
87b483a1 | 5807 | /* If we allocated a CR register, release it. */ |
36a05131 BS |
5808 | if (new_cr) |
5809 | { | |
5810 | CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr)); | |
5811 | *p_new_cr = NULL_RTX; | |
5812 | } | |
5813 | ||
5814 | if (TARGET_DEBUG_COND_EXEC) | |
5815 | fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr); | |
5816 | ||
5817 | return; | |
5818 | } | |
5819 | ||
5820 | \f | |
5821 | /* Return a register which will be loaded with a value if an IF block is | |
5822 | converted to conditional execution. This is used to rewrite instructions | |
5823 | that use constants to ones that just use registers. */ | |
5824 | ||
5825 | static rtx | |
f2206911 | 5826 | frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED) |
36a05131 BS |
5827 | { |
5828 | int num_alloc = frv_ifcvt.cur_scratch_regs; | |
5829 | int i; | |
5830 | rtx reg; | |
5831 | ||
5832 | /* We know gr0 == 0, so replace any errant uses. */ | |
5833 | if (value == const0_rtx) | |
5834 | return gen_rtx_REG (SImode, GPR_FIRST); | |
5835 | ||
5836 | /* First search all registers currently loaded to see if we have an | |
5837 | applicable constant. */ | |
5838 | if (CONSTANT_P (value) | |
5839 | || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)) | |
5840 | { | |
5841 | for (i = 0; i < num_alloc; i++) | |
5842 | { | |
5843 | if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value)) | |
5844 | return SET_DEST (frv_ifcvt.scratch_regs[i]); | |
5845 | } | |
5846 | } | |
5847 | ||
87b483a1 | 5848 | /* Have we exhausted the number of registers available? */ |
36a05131 BS |
5849 | if (num_alloc >= GPR_TEMP_NUM) |
5850 | { | |
c263766c RH |
5851 | if (dump_file) |
5852 | fprintf (dump_file, "Too many temporary registers allocated\n"); | |
36a05131 BS |
5853 | |
5854 | return NULL_RTX; | |
5855 | } | |
5856 | ||
5857 | /* Allocate the new register. */ | |
5858 | reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE); | |
5859 | if (! reg) | |
5860 | { | |
c263766c RH |
5861 | if (dump_file) |
5862 | fputs ("Could not find a scratch register\n", dump_file); | |
36a05131 BS |
5863 | |
5864 | return NULL_RTX; | |
5865 | } | |
5866 | ||
5867 | frv_ifcvt.cur_scratch_regs++; | |
5868 | frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value); | |
5869 | ||
c263766c | 5870 | if (dump_file) |
36a05131 BS |
5871 | { |
5872 | if (GET_CODE (value) == CONST_INT) | |
c263766c | 5873 | fprintf (dump_file, "Register %s will hold %ld\n", |
36a05131 BS |
5874 | reg_names[ REGNO (reg)], (long)INTVAL (value)); |
5875 | ||
5876 | else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO) | |
c263766c | 5877 | fprintf (dump_file, "Register %s will hold LR\n", |
36a05131 BS |
5878 | reg_names[ REGNO (reg)]); |
5879 | ||
5880 | else | |
c263766c | 5881 | fprintf (dump_file, "Register %s will hold a saved value\n", |
36a05131 BS |
5882 | reg_names[ REGNO (reg)]); |
5883 | } | |
5884 | ||
5885 | return reg; | |
5886 | } | |
5887 | ||
5888 | \f | |
5889 | /* Update a MEM used in conditional code that might contain an offset to put | |
5890 | the offset into a scratch register, so that the conditional load/store | |
5891 | operations can be used. This function returns the original pointer if the | |
5892 | MEM is valid to use in conditional code, NULL if we can't load up the offset | |
5893 | into a temporary register, or the new MEM if we were successful. */ | |
5894 | ||
5895 | static rtx | |
f2206911 | 5896 | frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn) |
36a05131 BS |
5897 | { |
5898 | rtx addr = XEXP (mem, 0); | |
5899 | ||
c6c3dba9 | 5900 | if (!frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE)) |
36a05131 BS |
5901 | { |
5902 | if (GET_CODE (addr) == PLUS) | |
5903 | { | |
5904 | rtx addr_op0 = XEXP (addr, 0); | |
5905 | rtx addr_op1 = XEXP (addr, 1); | |
5906 | ||
34208acf | 5907 | if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1)) |
36a05131 BS |
5908 | { |
5909 | rtx reg = frv_ifcvt_load_value (addr_op1, insn); | |
5910 | if (!reg) | |
5911 | return NULL_RTX; | |
5912 | ||
5913 | addr = gen_rtx_PLUS (Pmode, addr_op0, reg); | |
5914 | } | |
5915 | ||
5916 | else | |
5917 | return NULL_RTX; | |
5918 | } | |
5919 | ||
5920 | else if (CONSTANT_P (addr)) | |
5921 | addr = frv_ifcvt_load_value (addr, insn); | |
5922 | ||
5923 | else | |
5924 | return NULL_RTX; | |
5925 | ||
5926 | if (addr == NULL_RTX) | |
5927 | return NULL_RTX; | |
5928 | ||
5929 | else if (XEXP (mem, 0) != addr) | |
5930 | return change_address (mem, mode, addr); | |
5931 | } | |
5932 | ||
5933 | return mem; | |
5934 | } | |
5935 | ||
5936 | \f | |
5937 | /* Given a PATTERN, return a SET expression if this PATTERN has only a single | |
5938 | SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */ | |
5939 | ||
5940 | static rtx | |
f2206911 | 5941 | single_set_pattern (rtx pattern) |
36a05131 BS |
5942 | { |
5943 | rtx set; | |
5944 | int i; | |
5945 | ||
5946 | if (GET_CODE (pattern) == COND_EXEC) | |
5947 | pattern = COND_EXEC_CODE (pattern); | |
5948 | ||
5949 | if (GET_CODE (pattern) == SET) | |
5950 | return pattern; | |
5951 | ||
5952 | else if (GET_CODE (pattern) == PARALLEL) | |
5953 | { | |
5954 | for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++) | |
5955 | { | |
5956 | rtx sub = XVECEXP (pattern, 0, i); | |
5957 | ||
5958 | switch (GET_CODE (sub)) | |
5959 | { | |
5960 | case USE: | |
5961 | case CLOBBER: | |
5962 | break; | |
5963 | ||
5964 | case SET: | |
5965 | if (set) | |
5966 | return 0; | |
5967 | else | |
5968 | set = sub; | |
5969 | break; | |
5970 | ||
5971 | default: | |
5972 | return 0; | |
5973 | } | |
5974 | } | |
5975 | return set; | |
5976 | } | |
5977 | ||
5978 | return 0; | |
5979 | } | |
5980 | ||
5981 | \f | |
5982 | /* A C expression to modify the code described by the conditional if | |
5983 | information CE_INFO with the new PATTERN in INSN. If PATTERN is a null | |
5984 | pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that | |
5985 | insn cannot be converted to be executed conditionally. */ | |
5986 | ||
5987 | rtx | |
5da1fd3d | 5988 | frv_ifcvt_modify_insn (ce_if_block_t *ce_info, |
f2206911 KC |
5989 | rtx pattern, |
5990 | rtx insn) | |
36a05131 BS |
5991 | { |
5992 | rtx orig_ce_pattern = pattern; | |
5993 | rtx set; | |
5994 | rtx op0; | |
5995 | rtx op1; | |
5996 | rtx test; | |
5997 | ||
44e91694 | 5998 | gcc_assert (GET_CODE (pattern) == COND_EXEC); |
36a05131 BS |
5999 | |
6000 | test = COND_EXEC_TEST (pattern); | |
6001 | if (GET_CODE (test) == AND) | |
6002 | { | |
6003 | rtx cr = frv_ifcvt.cr_reg; | |
6004 | rtx test_reg; | |
6005 | ||
6006 | op0 = XEXP (test, 0); | |
6007 | if (! rtx_equal_p (cr, XEXP (op0, 0))) | |
6008 | goto fail; | |
6009 | ||
6010 | op1 = XEXP (test, 1); | |
6011 | test_reg = XEXP (op1, 0); | |
6012 | if (GET_CODE (test_reg) != REG) | |
6013 | goto fail; | |
6014 | ||
6015 | /* Is this the first nested if block in this sequence? If so, generate | |
6016 | an andcr or andncr. */ | |
6017 | if (! frv_ifcvt.last_nested_if_cr) | |
6018 | { | |
6019 | rtx and_op; | |
6020 | ||
6021 | frv_ifcvt.last_nested_if_cr = test_reg; | |
6022 | if (GET_CODE (op0) == NE) | |
6023 | and_op = gen_andcr (test_reg, cr, test_reg); | |
6024 | else | |
6025 | and_op = gen_andncr (test_reg, cr, test_reg); | |
6026 | ||
6027 | frv_ifcvt_add_insn (and_op, insn, TRUE); | |
6028 | } | |
6029 | ||
6030 | /* If this isn't the first statement in the nested if sequence, see if we | |
6031 | are dealing with the same register. */ | |
6032 | else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr)) | |
6033 | goto fail; | |
6034 | ||
6035 | COND_EXEC_TEST (pattern) = test = op1; | |
6036 | } | |
6037 | ||
6038 | /* If this isn't a nested if, reset state variables. */ | |
6039 | else | |
6040 | { | |
6041 | frv_ifcvt.last_nested_if_cr = NULL_RTX; | |
6042 | } | |
6043 | ||
6044 | set = single_set_pattern (pattern); | |
6045 | if (set) | |
6046 | { | |
6047 | rtx dest = SET_DEST (set); | |
6048 | rtx src = SET_SRC (set); | |
6049 | enum machine_mode mode = GET_MODE (dest); | |
6050 | ||
87b483a1 | 6051 | /* Check for normal binary operators. */ |
ec8e098d | 6052 | if (mode == SImode && ARITHMETIC_P (src)) |
36a05131 BS |
6053 | { |
6054 | op0 = XEXP (src, 0); | |
6055 | op1 = XEXP (src, 1); | |
6056 | ||
34208acf | 6057 | if (integer_register_operand (op0, SImode) && CONSTANT_P (op1)) |
36a05131 BS |
6058 | { |
6059 | op1 = frv_ifcvt_load_value (op1, insn); | |
6060 | if (op1) | |
6061 | COND_EXEC_CODE (pattern) | |
6062 | = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src), | |
6063 | GET_MODE (src), | |
6064 | op0, op1)); | |
6065 | else | |
6066 | goto fail; | |
6067 | } | |
6068 | } | |
6069 | ||
6070 | /* For multiply by a constant, we need to handle the sign extending | |
6071 | correctly. Add a USE of the value after the multiply to prevent flow | |
6072 | from cratering because only one register out of the two were used. */ | |
6073 | else if (mode == DImode && GET_CODE (src) == MULT) | |
6074 | { | |
6075 | op0 = XEXP (src, 0); | |
6076 | op1 = XEXP (src, 1); | |
6077 | if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT) | |
6078 | { | |
6079 | op1 = frv_ifcvt_load_value (op1, insn); | |
6080 | if (op1) | |
6081 | { | |
6082 | op1 = gen_rtx_SIGN_EXTEND (DImode, op1); | |
6083 | COND_EXEC_CODE (pattern) | |
6084 | = gen_rtx_SET (VOIDmode, dest, | |
6085 | gen_rtx_MULT (DImode, op0, op1)); | |
6086 | } | |
6087 | else | |
6088 | goto fail; | |
6089 | } | |
6090 | ||
c41c1387 | 6091 | frv_ifcvt_add_insn (gen_use (dest), insn, FALSE); |
36a05131 BS |
6092 | } |
6093 | ||
6094 | /* If we are just loading a constant created for a nested conditional | |
6095 | execution statement, just load the constant without any conditional | |
6096 | execution, since we know that the constant will not interfere with any | |
6097 | other registers. */ | |
6098 | else if (frv_ifcvt.scratch_insns_bitmap | |
6099 | && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap, | |
5da1fd3d | 6100 | INSN_UID (insn)) |
5da1fd3d | 6101 | && REG_P (SET_DEST (set)) |
9a228f09 AO |
6102 | /* We must not unconditionally set a scratch reg chosen |
6103 | for a nested if-converted block if its incoming | |
6104 | value from the TEST block (or the result of the THEN | |
6105 | branch) could/should propagate to the JOIN block. | |
6106 | It suffices to test whether the register is live at | |
6107 | the JOIN point: if it's live there, we can infer | |
6108 | that we set it in the former JOIN block of the | |
6109 | nested if-converted block (otherwise it wouldn't | |
6110 | have been available as a scratch register), and it | |
6111 | is either propagated through or set in the other | |
6112 | conditional block. It's probably not worth trying | |
6113 | to catch the latter case, and it could actually | |
6114 | limit scheduling of the combined block quite | |
6115 | severely. */ | |
6116 | && ce_info->join_bb | |
eedd7243 RIL |
6117 | && ! (REGNO_REG_SET_P (df_get_live_in (ce_info->join_bb), |
6118 | REGNO (SET_DEST (set)))) | |
9a228f09 AO |
6119 | /* Similarly, we must not unconditionally set a reg |
6120 | used as scratch in the THEN branch if the same reg | |
6121 | is live in the ELSE branch. */ | |
5da1fd3d AO |
6122 | && (! ce_info->else_bb |
6123 | || BLOCK_FOR_INSN (insn) == ce_info->else_bb | |
eedd7243 RIL |
6124 | || ! (REGNO_REG_SET_P (df_get_live_in (ce_info->else_bb), |
6125 | REGNO (SET_DEST (set)))))) | |
36a05131 BS |
6126 | pattern = set; |
6127 | ||
6128 | else if (mode == QImode || mode == HImode || mode == SImode | |
6129 | || mode == SFmode) | |
6130 | { | |
6131 | int changed_p = FALSE; | |
6132 | ||
6133 | /* Check for just loading up a constant */ | |
6134 | if (CONSTANT_P (src) && integer_register_operand (dest, mode)) | |
6135 | { | |
6136 | src = frv_ifcvt_load_value (src, insn); | |
6137 | if (!src) | |
6138 | goto fail; | |
6139 | ||
6140 | changed_p = TRUE; | |
6141 | } | |
6142 | ||
6143 | /* See if we need to fix up stores */ | |
6144 | if (GET_CODE (dest) == MEM) | |
6145 | { | |
6146 | rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn); | |
6147 | ||
6148 | if (!new_mem) | |
6149 | goto fail; | |
6150 | ||
6151 | else if (new_mem != dest) | |
6152 | { | |
6153 | changed_p = TRUE; | |
6154 | dest = new_mem; | |
6155 | } | |
6156 | } | |
6157 | ||
6158 | /* See if we need to fix up loads */ | |
6159 | if (GET_CODE (src) == MEM) | |
6160 | { | |
6161 | rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn); | |
6162 | ||
6163 | if (!new_mem) | |
6164 | goto fail; | |
6165 | ||
6166 | else if (new_mem != src) | |
6167 | { | |
6168 | changed_p = TRUE; | |
6169 | src = new_mem; | |
6170 | } | |
6171 | } | |
6172 | ||
6173 | /* If either src or destination changed, redo SET. */ | |
6174 | if (changed_p) | |
6175 | COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src); | |
6176 | } | |
6177 | ||
6178 | /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with | |
6179 | rewriting the CC register to be the same as the paired CC/CR register | |
6180 | for nested ifs. */ | |
ec8e098d | 6181 | else if (mode == CC_CCRmode && COMPARISON_P (src)) |
36a05131 BS |
6182 | { |
6183 | int regno = REGNO (XEXP (src, 0)); | |
6184 | rtx if_else; | |
6185 | ||
6186 | if (ce_info->pass > 1 | |
6187 | && regno != (int)REGNO (frv_ifcvt.nested_cc_reg) | |
6188 | && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno)) | |
6189 | { | |
6190 | src = gen_rtx_fmt_ee (GET_CODE (src), | |
6191 | CC_CCRmode, | |
6192 | frv_ifcvt.nested_cc_reg, | |
6193 | XEXP (src, 1)); | |
6194 | } | |
6195 | ||
6196 | if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx); | |
6197 | pattern = gen_rtx_SET (VOIDmode, dest, if_else); | |
6198 | } | |
6199 | ||
6200 | /* Remap a nested compare instruction to use the paired CC/CR reg. */ | |
6201 | else if (ce_info->pass > 1 | |
6202 | && GET_CODE (dest) == REG | |
6203 | && CC_P (REGNO (dest)) | |
6204 | && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg) | |
6205 | && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, | |
6206 | REGNO (dest)) | |
6207 | && GET_CODE (src) == COMPARE) | |
6208 | { | |
6209 | PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest)); | |
6210 | COND_EXEC_CODE (pattern) | |
6211 | = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src)); | |
6212 | } | |
6213 | } | |
6214 | ||
6215 | if (TARGET_DEBUG_COND_EXEC) | |
6216 | { | |
6217 | rtx orig_pattern = PATTERN (insn); | |
6218 | ||
6219 | PATTERN (insn) = pattern; | |
6220 | fprintf (stderr, | |
6221 | "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n", | |
6222 | ce_info->pass); | |
6223 | ||
6224 | debug_rtx (insn); | |
6225 | PATTERN (insn) = orig_pattern; | |
6226 | } | |
6227 | ||
6228 | return pattern; | |
6229 | ||
6230 | fail: | |
6231 | if (TARGET_DEBUG_COND_EXEC) | |
6232 | { | |
6233 | rtx orig_pattern = PATTERN (insn); | |
6234 | ||
6235 | PATTERN (insn) = orig_ce_pattern; | |
6236 | fprintf (stderr, | |
6237 | "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n", | |
6238 | ce_info->pass); | |
6239 | ||
6240 | debug_rtx (insn); | |
6241 | PATTERN (insn) = orig_pattern; | |
6242 | } | |
6243 | ||
6244 | return NULL_RTX; | |
6245 | } | |
6246 | ||
6247 | \f | |
6248 | /* A C expression to perform any final machine dependent modifications in | |
6249 | converting code to conditional execution in the code described by the | |
6250 | conditional if information CE_INFO. */ | |
6251 | ||
6252 | void | |
f2206911 | 6253 | frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED) |
36a05131 BS |
6254 | { |
6255 | rtx existing_insn; | |
6256 | rtx check_insn; | |
6257 | rtx p = frv_ifcvt.added_insns_list; | |
6258 | int i; | |
6259 | ||
6260 | /* Loop inserting the check insns. The last check insn is the first test, | |
6261 | and is the appropriate place to insert constants. */ | |
44e91694 | 6262 | gcc_assert (p); |
36a05131 BS |
6263 | |
6264 | do | |
6265 | { | |
6266 | rtx check_and_insert_insns = XEXP (p, 0); | |
6267 | rtx old_p = p; | |
6268 | ||
6269 | check_insn = XEXP (check_and_insert_insns, 0); | |
6270 | existing_insn = XEXP (check_and_insert_insns, 1); | |
6271 | p = XEXP (p, 1); | |
6272 | ||
6273 | /* The jump bit is used to say that the new insn is to be inserted BEFORE | |
6274 | the existing insn, otherwise it is to be inserted AFTER. */ | |
6275 | if (check_and_insert_insns->jump) | |
6276 | { | |
6277 | emit_insn_before (check_insn, existing_insn); | |
6278 | check_and_insert_insns->jump = 0; | |
6279 | } | |
6280 | else | |
6281 | emit_insn_after (check_insn, existing_insn); | |
6282 | ||
6283 | free_EXPR_LIST_node (check_and_insert_insns); | |
6284 | free_EXPR_LIST_node (old_p); | |
6285 | } | |
6286 | while (p != NULL_RTX); | |
6287 | ||
6288 | /* Load up any constants needed into temp gprs */ | |
6289 | for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++) | |
6290 | { | |
6291 | rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn); | |
6292 | if (! frv_ifcvt.scratch_insns_bitmap) | |
7b210806 | 6293 | frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL); |
36a05131 BS |
6294 | bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn)); |
6295 | frv_ifcvt.scratch_regs[i] = NULL_RTX; | |
6296 | } | |
6297 | ||
6298 | frv_ifcvt.added_insns_list = NULL_RTX; | |
6299 | frv_ifcvt.cur_scratch_regs = 0; | |
6300 | } | |
6301 | ||
6302 | \f | |
6303 | /* A C expression to cancel any machine dependent modifications in converting | |
6304 | code to conditional execution in the code described by the conditional if | |
6305 | information CE_INFO. */ | |
6306 | ||
6307 | void | |
f2206911 | 6308 | frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED) |
36a05131 BS |
6309 | { |
6310 | int i; | |
6311 | rtx p = frv_ifcvt.added_insns_list; | |
6312 | ||
6313 | /* Loop freeing up the EXPR_LIST's allocated. */ | |
6314 | while (p != NULL_RTX) | |
6315 | { | |
6316 | rtx check_and_jump = XEXP (p, 0); | |
6317 | rtx old_p = p; | |
6318 | ||
6319 | p = XEXP (p, 1); | |
6320 | free_EXPR_LIST_node (check_and_jump); | |
6321 | free_EXPR_LIST_node (old_p); | |
6322 | } | |
6323 | ||
6324 | /* Release any temporary gprs allocated. */ | |
6325 | for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++) | |
6326 | frv_ifcvt.scratch_regs[i] = NULL_RTX; | |
6327 | ||
6328 | frv_ifcvt.added_insns_list = NULL_RTX; | |
6329 | frv_ifcvt.cur_scratch_regs = 0; | |
6330 | return; | |
6331 | } | |
6332 | \f | |
6333 | /* A C expression for the size in bytes of the trampoline, as an integer. | |
6334 | The template is: | |
6335 | ||
6336 | setlo #0, <jmp_reg> | |
6337 | setlo #0, <static_chain> | |
6338 | sethi #0, <jmp_reg> | |
6339 | sethi #0, <static_chain> | |
6340 | jmpl @(gr0,<jmp_reg>) */ | |
6341 | ||
6342 | int | |
f2206911 | 6343 | frv_trampoline_size (void) |
36a05131 | 6344 | { |
34208acf AO |
6345 | if (TARGET_FDPIC) |
6346 | /* Allocate room for the function descriptor and the lddi | |
6347 | instruction. */ | |
6348 | return 8 + 6 * 4; | |
6349 | return 5 /* instructions */ * 4 /* instruction size. */; | |
36a05131 BS |
6350 | } |
6351 | ||
6352 | \f | |
6353 | /* A C statement to initialize the variable parts of a trampoline. ADDR is an | |
6354 | RTX for the address of the trampoline; FNADDR is an RTX for the address of | |
6355 | the nested function; STATIC_CHAIN is an RTX for the static chain value that | |
6356 | should be passed to the function when it is called. | |
6357 | ||
6358 | The template is: | |
6359 | ||
6360 | setlo #0, <jmp_reg> | |
6361 | setlo #0, <static_chain> | |
6362 | sethi #0, <jmp_reg> | |
6363 | sethi #0, <static_chain> | |
6364 | jmpl @(gr0,<jmp_reg>) */ | |
6365 | ||
e9d5fdb2 RH |
6366 | static void |
6367 | frv_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain) | |
36a05131 | 6368 | { |
e9d5fdb2 RH |
6369 | rtx addr = XEXP (m_tramp, 0); |
6370 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
36a05131 BS |
6371 | rtx sc_reg = force_reg (Pmode, static_chain); |
6372 | ||
6373 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), | |
6374 | FALSE, VOIDmode, 4, | |
6375 | addr, Pmode, | |
6376 | GEN_INT (frv_trampoline_size ()), SImode, | |
6377 | fnaddr, Pmode, | |
6378 | sc_reg, Pmode); | |
6379 | } | |
6380 | ||
6381 | \f | |
6382 | /* Many machines have some registers that cannot be copied directly to or from | |
6383 | memory or even from other types of registers. An example is the `MQ' | |
6384 | register, which on most machines, can only be copied to or from general | |
6385 | registers, but not memory. Some machines allow copying all registers to and | |
6386 | from memory, but require a scratch register for stores to some memory | |
6387 | locations (e.g., those with symbolic address on the RT, and those with | |
981f6289 | 6388 | certain symbolic address on the SPARC when compiling PIC). In some cases, |
36a05131 BS |
6389 | both an intermediate and a scratch register are required. |
6390 | ||
6391 | You should define these macros to indicate to the reload phase that it may | |
6392 | need to allocate at least one register for a reload in addition to the | |
6393 | register to contain the data. Specifically, if copying X to a register | |
0a2aaacc | 6394 | RCLASS in MODE requires an intermediate register, you should define |
36a05131 BS |
6395 | `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of |
6396 | whose registers can be used as intermediate registers or scratch registers. | |
6397 | ||
0a2aaacc | 6398 | If copying a register RCLASS in MODE to X requires an intermediate or scratch |
36a05131 BS |
6399 | register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the |
6400 | largest register class required. If the requirements for input and output | |
6401 | reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used | |
6402 | instead of defining both macros identically. | |
6403 | ||
6404 | The values returned by these macros are often `GENERAL_REGS'. Return | |
6405 | `NO_REGS' if no spare register is needed; i.e., if X can be directly copied | |
0a2aaacc | 6406 | to or from a register of RCLASS in MODE without requiring a scratch register. |
36a05131 BS |
6407 | Do not define this macro if it would always return `NO_REGS'. |
6408 | ||
6409 | If a scratch register is required (either with or without an intermediate | |
6410 | register), you should define patterns for `reload_inM' or `reload_outM', as | |
6411 | required.. These patterns, which will normally be implemented with a | |
6412 | `define_expand', should be similar to the `movM' patterns, except that | |
6413 | operand 2 is the scratch register. | |
6414 | ||
6415 | Define constraints for the reload register and scratch register that contain | |
6416 | a single register class. If the original reload register (whose class is | |
0a2aaacc | 6417 | RCLASS) can meet the constraint given in the pattern, the value returned by |
36a05131 BS |
6418 | these macros is used for the class of the scratch register. Otherwise, two |
6419 | additional reload registers are required. Their classes are obtained from | |
6420 | the constraints in the insn pattern. | |
6421 | ||
6422 | X might be a pseudo-register or a `subreg' of a pseudo-register, which could | |
6423 | either be in a hard register or in memory. Use `true_regnum' to find out; | |
6424 | it will return -1 if the pseudo is in memory and the hard register number if | |
6425 | it is in a register. | |
6426 | ||
6427 | These macros should not be used in the case where a particular class of | |
6428 | registers can only be copied to memory and not to another class of | |
6429 | registers. In that case, secondary reload registers are not needed and | |
6430 | would not be helpful. Instead, a stack location must be used to perform the | |
43aa4e05 | 6431 | copy and the `movM' pattern should use memory as an intermediate storage. |
36a05131 BS |
6432 | This case often occurs between floating-point and general registers. */ |
6433 | ||
6434 | enum reg_class | |
0a2aaacc | 6435 | frv_secondary_reload_class (enum reg_class rclass, |
f2206911 | 6436 | enum machine_mode mode ATTRIBUTE_UNUSED, |
35f2d8ef | 6437 | rtx x) |
36a05131 BS |
6438 | { |
6439 | enum reg_class ret; | |
6440 | ||
0a2aaacc | 6441 | switch (rclass) |
36a05131 BS |
6442 | { |
6443 | default: | |
6444 | ret = NO_REGS; | |
6445 | break; | |
6446 | ||
6447 | /* Accumulators/Accumulator guard registers need to go through floating | |
6448 | point registers. */ | |
6449 | case QUAD_REGS: | |
6450 | case EVEN_REGS: | |
6451 | case GPR_REGS: | |
6452 | ret = NO_REGS; | |
6453 | if (x && GET_CODE (x) == REG) | |
6454 | { | |
6455 | int regno = REGNO (x); | |
6456 | ||
6457 | if (ACC_P (regno) || ACCG_P (regno)) | |
6458 | ret = FPR_REGS; | |
6459 | } | |
6460 | break; | |
6461 | ||
9cd10576 | 6462 | /* Nonzero constants should be loaded into an FPR through a GPR. */ |
36a05131 BS |
6463 | case QUAD_FPR_REGS: |
6464 | case FEVEN_REGS: | |
6465 | case FPR_REGS: | |
6466 | if (x && CONSTANT_P (x) && !ZERO_P (x)) | |
6467 | ret = GPR_REGS; | |
6468 | else | |
6469 | ret = NO_REGS; | |
6470 | break; | |
6471 | ||
6472 | /* All of these types need gpr registers. */ | |
6473 | case ICC_REGS: | |
6474 | case FCC_REGS: | |
6475 | case CC_REGS: | |
6476 | case ICR_REGS: | |
6477 | case FCR_REGS: | |
6478 | case CR_REGS: | |
6479 | case LCR_REG: | |
6480 | case LR_REG: | |
6481 | ret = GPR_REGS; | |
6482 | break; | |
6483 | ||
35f2d8ef | 6484 | /* The accumulators need fpr registers. */ |
36a05131 BS |
6485 | case ACC_REGS: |
6486 | case EVEN_ACC_REGS: | |
6487 | case QUAD_ACC_REGS: | |
6488 | case ACCG_REGS: | |
6489 | ret = FPR_REGS; | |
6490 | break; | |
6491 | } | |
6492 | ||
6493 | return ret; | |
6494 | } | |
6495 | ||
35f2d8ef NC |
6496 | /* This hook exists to catch the case where secondary_reload_class() is |
6497 | called from init_reg_autoinc() in regclass.c - before the reload optabs | |
6498 | have been initialised. */ | |
6499 | ||
a87cf97e JR |
6500 | static reg_class_t |
6501 | frv_secondary_reload (bool in_p, rtx x, reg_class_t reload_class_i, | |
35f2d8ef NC |
6502 | enum machine_mode reload_mode, |
6503 | secondary_reload_info * sri) | |
6504 | { | |
6505 | enum reg_class rclass = NO_REGS; | |
a87cf97e | 6506 | enum reg_class reload_class = (enum reg_class) reload_class_i; |
35f2d8ef NC |
6507 | |
6508 | if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing) | |
6509 | { | |
6510 | sri->icode = sri->prev_sri->t_icode; | |
6511 | return NO_REGS; | |
6512 | } | |
6513 | ||
6514 | rclass = frv_secondary_reload_class (reload_class, reload_mode, x); | |
6515 | ||
6516 | if (rclass != NO_REGS) | |
6517 | { | |
f9621cc4 RS |
6518 | enum insn_code icode |
6519 | = direct_optab_handler (in_p ? reload_in_optab : reload_out_optab, | |
6520 | reload_mode); | |
35f2d8ef NC |
6521 | if (icode == 0) |
6522 | { | |
6523 | /* This happens when then the reload_[in|out]_optabs have | |
6524 | not been initialised. */ | |
6525 | sri->t_icode = CODE_FOR_nothing; | |
6526 | return rclass; | |
6527 | } | |
6528 | } | |
6529 | ||
6530 | /* Fall back to the default secondary reload handler. */ | |
6531 | return default_secondary_reload (in_p, x, reload_class, reload_mode, sri); | |
6532 | ||
6533 | } | |
36a05131 | 6534 | \f |
c28350ab | 6535 | /* Worker function for TARGET_CLASS_LIKELY_SPILLED_P. */ |
36a05131 | 6536 | |
c28350ab AS |
6537 | static bool |
6538 | frv_class_likely_spilled_p (reg_class_t rclass) | |
36a05131 | 6539 | { |
0a2aaacc | 6540 | switch (rclass) |
36a05131 BS |
6541 | { |
6542 | default: | |
6543 | break; | |
6544 | ||
17c21957 AO |
6545 | case GR8_REGS: |
6546 | case GR9_REGS: | |
6547 | case GR89_REGS: | |
6548 | case FDPIC_FPTR_REGS: | |
6549 | case FDPIC_REGS: | |
36a05131 BS |
6550 | case ICC_REGS: |
6551 | case FCC_REGS: | |
6552 | case CC_REGS: | |
6553 | case ICR_REGS: | |
6554 | case FCR_REGS: | |
6555 | case CR_REGS: | |
6556 | case LCR_REG: | |
6557 | case LR_REG: | |
6558 | case SPR_REGS: | |
6559 | case QUAD_ACC_REGS: | |
6560 | case EVEN_ACC_REGS: | |
6561 | case ACC_REGS: | |
6562 | case ACCG_REGS: | |
c28350ab | 6563 | return true; |
36a05131 BS |
6564 | } |
6565 | ||
c28350ab | 6566 | return false; |
36a05131 BS |
6567 | } |
6568 | ||
6569 | \f | |
6570 | /* An expression for the alignment of a structure field FIELD if the | |
7ec022b2 | 6571 | alignment computed in the usual way is COMPUTED. GCC uses this |
36a05131 BS |
6572 | value instead of the value in `BIGGEST_ALIGNMENT' or |
6573 | `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */ | |
6574 | ||
6575 | /* The definition type of the bit field data is either char, short, long or | |
6576 | long long. The maximum bit size is the number of bits of its own type. | |
6577 | ||
6578 | The bit field data is assigned to a storage unit that has an adequate size | |
6579 | for bit field data retention and is located at the smallest address. | |
6580 | ||
6581 | Consecutive bit field data are packed at consecutive bits having the same | |
6582 | storage unit, with regard to the type, beginning with the MSB and continuing | |
6583 | toward the LSB. | |
6584 | ||
6585 | If a field to be assigned lies over a bit field type boundary, its | |
6586 | assignment is completed by aligning it with a boundary suitable for the | |
6587 | type. | |
6588 | ||
6589 | When a bit field having a bit length of 0 is declared, it is forcibly | |
6590 | assigned to the next storage unit. | |
6591 | ||
6592 | e.g) | |
6593 | struct { | |
6594 | int a:2; | |
6595 | int b:6; | |
6596 | char c:4; | |
6597 | int d:10; | |
6598 | int :0; | |
6599 | int f:2; | |
6600 | } x; | |
6601 | ||
6602 | +0 +1 +2 +3 | |
6603 | &x 00000000 00000000 00000000 00000000 | |
6604 | MLM----L | |
6605 | a b | |
6606 | &x+4 00000000 00000000 00000000 00000000 | |
6607 | M--L | |
6608 | c | |
6609 | &x+8 00000000 00000000 00000000 00000000 | |
6610 | M----------L | |
6611 | d | |
6612 | &x+12 00000000 00000000 00000000 00000000 | |
6613 | ML | |
6614 | f | |
6615 | */ | |
6616 | ||
6617 | int | |
f2206911 | 6618 | frv_adjust_field_align (tree field, int computed) |
36a05131 | 6619 | { |
b16c1435 EC |
6620 | /* Make sure that the bitfield is not wider than the type. */ |
6621 | if (DECL_BIT_FIELD (field) | |
25f93e18 | 6622 | && !DECL_ARTIFICIAL (field)) |
36a05131 BS |
6623 | { |
6624 | tree parent = DECL_CONTEXT (field); | |
6625 | tree prev = NULL_TREE; | |
6626 | tree cur; | |
6627 | ||
910ad8de | 6628 | for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = DECL_CHAIN (cur)) |
36a05131 BS |
6629 | { |
6630 | if (TREE_CODE (cur) != FIELD_DECL) | |
6631 | continue; | |
6632 | ||
6633 | prev = cur; | |
6634 | } | |
6635 | ||
44e91694 | 6636 | gcc_assert (cur); |
36a05131 BS |
6637 | |
6638 | /* If this isn't a :0 field and if the previous element is a bitfield | |
6639 | also, see if the type is different, if so, we will need to align the | |
87b483a1 | 6640 | bit-field to the next boundary. */ |
36a05131 BS |
6641 | if (prev |
6642 | && ! DECL_PACKED (field) | |
6643 | && ! integer_zerop (DECL_SIZE (field)) | |
6644 | && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev)) | |
6645 | { | |
6646 | int prev_align = TYPE_ALIGN (TREE_TYPE (prev)); | |
6647 | int cur_align = TYPE_ALIGN (TREE_TYPE (field)); | |
6648 | computed = (prev_align > cur_align) ? prev_align : cur_align; | |
6649 | } | |
6650 | } | |
6651 | ||
6652 | return computed; | |
6653 | } | |
6654 | ||
6655 | \f | |
6656 | /* A C expression that is nonzero if it is permissible to store a value of mode | |
6657 | MODE in hard register number REGNO (or in several registers starting with | |
6658 | that one). For a machine where all registers are equivalent, a suitable | |
6659 | definition is | |
6660 | ||
6661 | #define HARD_REGNO_MODE_OK(REGNO, MODE) 1 | |
6662 | ||
6663 | It is not necessary for this macro to check for the numbers of fixed | |
6664 | registers, because the allocation mechanism considers them to be always | |
6665 | occupied. | |
6666 | ||
6667 | On some machines, double-precision values must be kept in even/odd register | |
6668 | pairs. The way to implement that is to define this macro to reject odd | |
6669 | register numbers for such modes. | |
6670 | ||
6671 | The minimum requirement for a mode to be OK in a register is that the | |
6672 | `movMODE' instruction pattern support moves between the register and any | |
6673 | other hard register for which the mode is OK; and that moving a value into | |
6674 | the register and back out not alter it. | |
6675 | ||
6676 | Since the same instruction used to move `SImode' will work for all narrower | |
6677 | integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK' | |
6678 | to distinguish between these modes, provided you define patterns `movhi', | |
6679 | etc., to take advantage of this. This is useful because of the interaction | |
6680 | between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for | |
6681 | all integer modes to be tieable. | |
6682 | ||
6683 | Many machines have special registers for floating point arithmetic. Often | |
6684 | people assume that floating point machine modes are allowed only in floating | |
6685 | point registers. This is not true. Any registers that can hold integers | |
6686 | can safely *hold* a floating point machine mode, whether or not floating | |
6687 | arithmetic can be done on it in those registers. Integer move instructions | |
6688 | can be used to move the values. | |
6689 | ||
6690 | On some machines, though, the converse is true: fixed-point machine modes | |
6691 | may not go in floating registers. This is true if the floating registers | |
6692 | normalize any value stored in them, because storing a non-floating value | |
6693 | there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject | |
6694 | fixed-point machine modes in floating registers. But if the floating | |
6695 | registers do not automatically normalize, if you can store any bit pattern | |
6696 | in one and retrieve it unchanged without a trap, then any machine mode may | |
6697 | go in a floating register, so you can define this macro to say so. | |
6698 | ||
6699 | The primary significance of special floating registers is rather that they | |
6700 | are the registers acceptable in floating point arithmetic instructions. | |
6701 | However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by | |
6702 | writing the proper constraints for those instructions. | |
6703 | ||
6704 | On some machines, the floating registers are especially slow to access, so | |
6705 | that it is better to store a value in a stack frame than in such a register | |
6706 | if floating point arithmetic is not being done. As long as the floating | |
6707 | registers are not in class `GENERAL_REGS', they will not be used unless some | |
6708 | pattern's constraint asks for one. */ | |
6709 | ||
6710 | int | |
f2206911 | 6711 | frv_hard_regno_mode_ok (int regno, enum machine_mode mode) |
36a05131 BS |
6712 | { |
6713 | int base; | |
6714 | int mask; | |
6715 | ||
6716 | switch (mode) | |
6717 | { | |
6718 | case CCmode: | |
6719 | case CC_UNSmode: | |
036ff63f | 6720 | case CC_NZmode: |
36a05131 BS |
6721 | return ICC_P (regno) || GPR_P (regno); |
6722 | ||
6723 | case CC_CCRmode: | |
6724 | return CR_P (regno) || GPR_P (regno); | |
6725 | ||
6726 | case CC_FPmode: | |
6727 | return FCC_P (regno) || GPR_P (regno); | |
6728 | ||
6729 | default: | |
6730 | break; | |
6731 | } | |
6732 | ||
6733 | /* Set BASE to the first register in REGNO's class. Set MASK to the | |
6734 | bits that must be clear in (REGNO - BASE) for the register to be | |
6735 | well-aligned. */ | |
6736 | if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode)) | |
6737 | { | |
6738 | if (ACCG_P (regno)) | |
6739 | { | |
6740 | /* ACCGs store one byte. Two-byte quantities must start in | |
6741 | even-numbered registers, four-byte ones in registers whose | |
6742 | numbers are divisible by four, and so on. */ | |
6743 | base = ACCG_FIRST; | |
6744 | mask = GET_MODE_SIZE (mode) - 1; | |
6745 | } | |
6746 | else | |
6747 | { | |
b16c1435 EC |
6748 | /* The other registers store one word. */ |
6749 | if (GPR_P (regno) || regno == AP_FIRST) | |
36a05131 BS |
6750 | base = GPR_FIRST; |
6751 | ||
6752 | else if (FPR_P (regno)) | |
6753 | base = FPR_FIRST; | |
6754 | ||
6755 | else if (ACC_P (regno)) | |
6756 | base = ACC_FIRST; | |
6757 | ||
b16c1435 EC |
6758 | else if (SPR_P (regno)) |
6759 | return mode == SImode; | |
6760 | ||
87b483a1 | 6761 | /* Fill in the table. */ |
36a05131 BS |
6762 | else |
6763 | return 0; | |
6764 | ||
6765 | /* Anything smaller than an SI is OK in any word-sized register. */ | |
6766 | if (GET_MODE_SIZE (mode) < 4) | |
6767 | return 1; | |
6768 | ||
6769 | mask = (GET_MODE_SIZE (mode) / 4) - 1; | |
6770 | } | |
6771 | return (((regno - base) & mask) == 0); | |
6772 | } | |
6773 | ||
6774 | return 0; | |
6775 | } | |
6776 | ||
6777 | \f | |
6778 | /* A C expression for the number of consecutive hard registers, starting at | |
6779 | register number REGNO, required to hold a value of mode MODE. | |
6780 | ||
6781 | On a machine where all registers are exactly one word, a suitable definition | |
6782 | of this macro is | |
6783 | ||
6784 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
6785 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \ | |
6786 | / UNITS_PER_WORD)) */ | |
6787 | ||
6788 | /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so | |
6789 | that we can build the appropriate instructions to properly reload the | |
6790 | values. Also, make the byte-sized accumulator guards use one guard | |
6791 | for each byte. */ | |
6792 | ||
6793 | int | |
f2206911 | 6794 | frv_hard_regno_nregs (int regno, enum machine_mode mode) |
36a05131 BS |
6795 | { |
6796 | if (ACCG_P (regno)) | |
6797 | return GET_MODE_SIZE (mode); | |
6798 | else | |
6799 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
6800 | } | |
6801 | ||
6802 | \f | |
6803 | /* A C expression for the maximum number of consecutive registers of | |
0a2aaacc | 6804 | class RCLASS needed to hold a value of mode MODE. |
36a05131 BS |
6805 | |
6806 | This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value | |
0a2aaacc KG |
6807 | of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of |
6808 | `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS. | |
36a05131 BS |
6809 | |
6810 | This macro helps control the handling of multiple-word values in | |
6811 | the reload pass. | |
6812 | ||
6813 | This declaration is required. */ | |
6814 | ||
6815 | int | |
0a2aaacc | 6816 | frv_class_max_nregs (enum reg_class rclass, enum machine_mode mode) |
36a05131 | 6817 | { |
0a2aaacc | 6818 | if (rclass == ACCG_REGS) |
36a05131 BS |
6819 | /* An N-byte value requires N accumulator guards. */ |
6820 | return GET_MODE_SIZE (mode); | |
6821 | else | |
6822 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
6823 | } | |
6824 | ||
6825 | \f | |
6826 | /* A C expression that is nonzero if X is a legitimate constant for an | |
6827 | immediate operand on the target machine. You can assume that X satisfies | |
6828 | `CONSTANT_P', so you need not check this. In fact, `1' is a suitable | |
6829 | definition for this macro on machines where anything `CONSTANT_P' is valid. */ | |
6830 | ||
6831 | int | |
f2206911 | 6832 | frv_legitimate_constant_p (rtx x) |
36a05131 BS |
6833 | { |
6834 | enum machine_mode mode = GET_MODE (x); | |
6835 | ||
34208acf AO |
6836 | /* frv_cannot_force_const_mem always returns true for FDPIC. This |
6837 | means that the move expanders will be expected to deal with most | |
6838 | kinds of constant, regardless of what we return here. | |
6839 | ||
6840 | However, among its other duties, LEGITIMATE_CONSTANT_P decides whether | |
6841 | a constant can be entered into reg_equiv_constant[]. If we return true, | |
6842 | reload can create new instances of the constant whenever it likes. | |
6843 | ||
6844 | The idea is therefore to accept as many constants as possible (to give | |
6845 | reload more freedom) while rejecting constants that can only be created | |
6846 | at certain times. In particular, anything with a symbolic component will | |
6847 | require use of the pseudo FDPIC register, which is only available before | |
6848 | reload. */ | |
6849 | if (TARGET_FDPIC) | |
6850 | return LEGITIMATE_PIC_OPERAND_P (x); | |
6851 | ||
87b483a1 | 6852 | /* All of the integer constants are ok. */ |
36a05131 BS |
6853 | if (GET_CODE (x) != CONST_DOUBLE) |
6854 | return TRUE; | |
6855 | ||
87b483a1 | 6856 | /* double integer constants are ok. */ |
36a05131 BS |
6857 | if (mode == VOIDmode || mode == DImode) |
6858 | return TRUE; | |
6859 | ||
87b483a1 | 6860 | /* 0 is always ok. */ |
36a05131 BS |
6861 | if (x == CONST0_RTX (mode)) |
6862 | return TRUE; | |
6863 | ||
6864 | /* If floating point is just emulated, allow any constant, since it will be | |
87b483a1 | 6865 | constructed in the GPRs. */ |
36a05131 BS |
6866 | if (!TARGET_HAS_FPRS) |
6867 | return TRUE; | |
6868 | ||
6869 | if (mode == DFmode && !TARGET_DOUBLE) | |
6870 | return TRUE; | |
6871 | ||
6872 | /* Otherwise store the constant away and do a load. */ | |
6873 | return FALSE; | |
6874 | } | |
036ff63f RS |
6875 | |
6876 | /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons, | |
6877 | CC_NZ for comparisons against zero in which a single Z or N flag test | |
6878 | is enough, CC_UNS for other unsigned comparisons, and CC for other | |
6879 | signed comparisons. */ | |
6880 | ||
6881 | enum machine_mode | |
6882 | frv_select_cc_mode (enum rtx_code code, rtx x, rtx y) | |
6883 | { | |
6884 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
6885 | return CC_FPmode; | |
6886 | ||
6887 | switch (code) | |
6888 | { | |
6889 | case EQ: | |
6890 | case NE: | |
6891 | case LT: | |
6892 | case GE: | |
6893 | return y == const0_rtx ? CC_NZmode : CCmode; | |
6894 | ||
6895 | case GTU: | |
6896 | case GEU: | |
6897 | case LTU: | |
6898 | case LEU: | |
6899 | return y == const0_rtx ? CC_NZmode : CC_UNSmode; | |
6900 | ||
6901 | default: | |
6902 | return CCmode; | |
6903 | } | |
6904 | } | |
36a05131 | 6905 | \f |
33124e84 AS |
6906 | |
6907 | /* Worker function for TARGET_REGISTER_MOVE_COST. */ | |
36a05131 BS |
6908 | |
6909 | #define HIGH_COST 40 | |
6910 | #define MEDIUM_COST 3 | |
6911 | #define LOW_COST 1 | |
6912 | ||
33124e84 AS |
6913 | static int |
6914 | frv_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, | |
6915 | reg_class_t from, reg_class_t to) | |
36a05131 BS |
6916 | { |
6917 | switch (from) | |
6918 | { | |
6919 | default: | |
6920 | break; | |
6921 | ||
6922 | case QUAD_REGS: | |
6923 | case EVEN_REGS: | |
6924 | case GPR_REGS: | |
6925 | switch (to) | |
6926 | { | |
6927 | default: | |
6928 | break; | |
6929 | ||
6930 | case QUAD_REGS: | |
6931 | case EVEN_REGS: | |
6932 | case GPR_REGS: | |
6933 | return LOW_COST; | |
6934 | ||
6935 | case FEVEN_REGS: | |
6936 | case FPR_REGS: | |
6937 | return LOW_COST; | |
6938 | ||
6939 | case LCR_REG: | |
6940 | case LR_REG: | |
6941 | case SPR_REGS: | |
6942 | return LOW_COST; | |
6943 | } | |
6944 | ||
6945 | case FEVEN_REGS: | |
6946 | case FPR_REGS: | |
6947 | switch (to) | |
6948 | { | |
6949 | default: | |
6950 | break; | |
6951 | ||
6952 | case QUAD_REGS: | |
6953 | case EVEN_REGS: | |
6954 | case GPR_REGS: | |
6955 | case ACC_REGS: | |
6956 | case EVEN_ACC_REGS: | |
6957 | case QUAD_ACC_REGS: | |
6958 | case ACCG_REGS: | |
6959 | return MEDIUM_COST; | |
6960 | ||
6961 | case FEVEN_REGS: | |
6962 | case FPR_REGS: | |
6963 | return LOW_COST; | |
6964 | } | |
6965 | ||
6966 | case LCR_REG: | |
6967 | case LR_REG: | |
6968 | case SPR_REGS: | |
6969 | switch (to) | |
6970 | { | |
6971 | default: | |
6972 | break; | |
6973 | ||
6974 | case QUAD_REGS: | |
6975 | case EVEN_REGS: | |
6976 | case GPR_REGS: | |
6977 | return MEDIUM_COST; | |
6978 | } | |
6979 | ||
6980 | case ACC_REGS: | |
6981 | case EVEN_ACC_REGS: | |
6982 | case QUAD_ACC_REGS: | |
6983 | case ACCG_REGS: | |
6984 | switch (to) | |
6985 | { | |
6986 | default: | |
6987 | break; | |
6988 | ||
6989 | case FEVEN_REGS: | |
6990 | case FPR_REGS: | |
6991 | return MEDIUM_COST; | |
6992 | ||
6993 | } | |
6994 | } | |
6995 | ||
6996 | return HIGH_COST; | |
6997 | } | |
33124e84 AS |
6998 | |
6999 | /* Worker function for TARGET_MEMORY_MOVE_COST. */ | |
7000 | ||
7001 | static int | |
7002 | frv_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, | |
7003 | reg_class_t rclass ATTRIBUTE_UNUSED, | |
7004 | bool in ATTRIBUTE_UNUSED) | |
7005 | { | |
7006 | return 4; | |
7007 | } | |
7008 | ||
36a05131 BS |
7009 | \f |
7010 | /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to | |
7011 | use ".picptr" to generate safe relocations for PIC code. We also | |
7012 | need a fixup entry for aligned (non-debugging) code. */ | |
7013 | ||
7014 | static bool | |
f2206911 | 7015 | frv_assemble_integer (rtx value, unsigned int size, int aligned_p) |
36a05131 | 7016 | { |
34208acf | 7017 | if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD) |
36a05131 BS |
7018 | { |
7019 | if (GET_CODE (value) == CONST | |
7020 | || GET_CODE (value) == SYMBOL_REF | |
7021 | || GET_CODE (value) == LABEL_REF) | |
7022 | { | |
34208acf AO |
7023 | if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF |
7024 | && SYMBOL_REF_FUNCTION_P (value)) | |
7025 | { | |
7026 | fputs ("\t.picptr\tfuncdesc(", asm_out_file); | |
7027 | output_addr_const (asm_out_file, value); | |
7028 | fputs (")\n", asm_out_file); | |
7029 | return true; | |
7030 | } | |
7031 | else if (TARGET_FDPIC && GET_CODE (value) == CONST | |
7032 | && frv_function_symbol_referenced_p (value)) | |
7033 | return false; | |
7034 | if (aligned_p && !TARGET_FDPIC) | |
36a05131 BS |
7035 | { |
7036 | static int label_num = 0; | |
7037 | char buf[256]; | |
7038 | const char *p; | |
7039 | ||
7040 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++); | |
14966b94 | 7041 | p = (* targetm.strip_name_encoding) (buf); |
36a05131 BS |
7042 | |
7043 | fprintf (asm_out_file, "%s:\n", p); | |
7044 | fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP); | |
7045 | fprintf (asm_out_file, "\t.picptr\t%s\n", p); | |
7046 | fprintf (asm_out_file, "\t.previous\n"); | |
7047 | } | |
7048 | assemble_integer_with_op ("\t.picptr\t", value); | |
7049 | return true; | |
7050 | } | |
7051 | if (!aligned_p) | |
7052 | { | |
7053 | /* We've set the unaligned SI op to NULL, so we always have to | |
7054 | handle the unaligned case here. */ | |
7055 | assemble_integer_with_op ("\t.4byte\t", value); | |
7056 | return true; | |
7057 | } | |
7058 | } | |
7059 | return default_assemble_integer (value, size, aligned_p); | |
7060 | } | |
7061 | ||
7062 | /* Function to set up the backend function structure. */ | |
7063 | ||
7064 | static struct machine_function * | |
f2206911 | 7065 | frv_init_machine_status (void) |
36a05131 | 7066 | { |
a9429e29 | 7067 | return ggc_alloc_cleared_machine_function (); |
36a05131 | 7068 | } |
ffb344c1 | 7069 | \f |
28a60850 RS |
7070 | /* Implement TARGET_SCHED_ISSUE_RATE. */ |
7071 | ||
c557edf4 | 7072 | int |
28a60850 RS |
7073 | frv_issue_rate (void) |
7074 | { | |
7075 | if (!TARGET_PACK) | |
7076 | return 1; | |
7077 | ||
7078 | switch (frv_cpu_type) | |
7079 | { | |
7080 | default: | |
7081 | case FRV_CPU_FR300: | |
7082 | case FRV_CPU_SIMPLE: | |
7083 | return 1; | |
7084 | ||
7085 | case FRV_CPU_FR400: | |
c557edf4 RS |
7086 | case FRV_CPU_FR405: |
7087 | case FRV_CPU_FR450: | |
28a60850 RS |
7088 | return 2; |
7089 | ||
7090 | case FRV_CPU_GENERIC: | |
7091 | case FRV_CPU_FR500: | |
7092 | case FRV_CPU_TOMCAT: | |
7093 | return 4; | |
c557edf4 RS |
7094 | |
7095 | case FRV_CPU_FR550: | |
7096 | return 8; | |
28a60850 RS |
7097 | } |
7098 | } | |
36a05131 | 7099 | \f |
c557edf4 RS |
7100 | /* A for_each_rtx callback. If X refers to an accumulator, return |
7101 | ACC_GROUP_ODD if the bit 2 of the register number is set and | |
7102 | ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE) | |
7103 | otherwise. */ | |
36a05131 | 7104 | |
c557edf4 RS |
7105 | static int |
7106 | frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED) | |
36a05131 | 7107 | { |
c557edf4 | 7108 | if (REG_P (*x)) |
36a05131 | 7109 | { |
c557edf4 RS |
7110 | if (ACC_P (REGNO (*x))) |
7111 | return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN; | |
7112 | if (ACCG_P (REGNO (*x))) | |
7113 | return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN; | |
7114 | } | |
7115 | return 0; | |
7116 | } | |
36a05131 | 7117 | |
c557edf4 | 7118 | /* Return the value of INSN's acc_group attribute. */ |
36a05131 | 7119 | |
c557edf4 RS |
7120 | int |
7121 | frv_acc_group (rtx insn) | |
7122 | { | |
7123 | /* This distinction only applies to the FR550 packing constraints. */ | |
7124 | if (frv_cpu_type != FRV_CPU_FR550) | |
7125 | return ACC_GROUP_NONE; | |
7126 | return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0); | |
7127 | } | |
36a05131 | 7128 | |
c557edf4 RS |
7129 | /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction |
7130 | INSN will try to claim first. Since this value depends only on the | |
7131 | type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */ | |
36a05131 | 7132 | |
c557edf4 RS |
7133 | static unsigned int |
7134 | frv_insn_unit (rtx insn) | |
7135 | { | |
7136 | enum attr_type type; | |
36a05131 | 7137 | |
c557edf4 RS |
7138 | type = get_attr_type (insn); |
7139 | if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes)) | |
7140 | { | |
7141 | /* We haven't seen this type of instruction before. */ | |
7142 | state_t state; | |
7143 | unsigned int unit; | |
36a05131 | 7144 | |
c557edf4 RS |
7145 | /* Issue the instruction on its own to see which unit it prefers. */ |
7146 | state = alloca (state_size ()); | |
7147 | state_reset (state); | |
7148 | state_transition (state, insn); | |
36a05131 | 7149 | |
c557edf4 RS |
7150 | /* Find out which unit was taken. */ |
7151 | for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++) | |
7152 | if (cpu_unit_reservation_p (state, frv_unit_codes[unit])) | |
7153 | break; | |
36a05131 | 7154 | |
44e91694 | 7155 | gcc_assert (unit != ARRAY_SIZE (frv_unit_codes)); |
36a05131 | 7156 | |
c557edf4 | 7157 | frv_type_to_unit[type] = unit; |
36a05131 | 7158 | } |
c557edf4 RS |
7159 | return frv_type_to_unit[type]; |
7160 | } | |
36a05131 | 7161 | |
c557edf4 | 7162 | /* Return true if INSN issues to a branch unit. */ |
36a05131 | 7163 | |
c557edf4 RS |
7164 | static bool |
7165 | frv_issues_to_branch_unit_p (rtx insn) | |
7166 | { | |
7167 | return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B; | |
7168 | } | |
7169 | \f | |
7170 | /* The current state of the packing pass, implemented by frv_pack_insns. */ | |
7171 | static struct { | |
7172 | /* The state of the pipeline DFA. */ | |
7173 | state_t dfa_state; | |
7174 | ||
7175 | /* Which hardware registers are set within the current packet, | |
7176 | and the conditions under which they are set. */ | |
7177 | regstate_t regstate[FIRST_PSEUDO_REGISTER]; | |
7178 | ||
7179 | /* The memory locations that have been modified so far in this | |
7180 | packet. MEM is the memref and COND is the regstate_t condition | |
7181 | under which it is set. */ | |
7182 | struct { | |
7183 | rtx mem; | |
7184 | regstate_t cond; | |
7185 | } mems[2]; | |
7186 | ||
7187 | /* The number of valid entries in MEMS. The value is larger than | |
7188 | ARRAY_SIZE (mems) if there were too many mems to record. */ | |
7189 | unsigned int num_mems; | |
7190 | ||
7191 | /* The maximum number of instructions that can be packed together. */ | |
7192 | unsigned int issue_rate; | |
7193 | ||
7194 | /* The instructions in the packet, partitioned into groups. */ | |
7195 | struct frv_packet_group { | |
7196 | /* How many instructions in the packet belong to this group. */ | |
7197 | unsigned int num_insns; | |
7198 | ||
7199 | /* A list of the instructions that belong to this group, in the order | |
7200 | they appear in the rtl stream. */ | |
7201 | rtx insns[ARRAY_SIZE (frv_unit_codes)]; | |
7202 | ||
7203 | /* The contents of INSNS after they have been sorted into the correct | |
7204 | assembly-language order. Element X issues to unit X. The list may | |
7205 | contain extra nops. */ | |
7206 | rtx sorted[ARRAY_SIZE (frv_unit_codes)]; | |
7207 | ||
7208 | /* The member of frv_nops[] to use in sorted[]. */ | |
7209 | rtx nop; | |
7210 | } groups[NUM_GROUPS]; | |
7211 | ||
7212 | /* The instructions that make up the current packet. */ | |
7213 | rtx insns[ARRAY_SIZE (frv_unit_codes)]; | |
7214 | unsigned int num_insns; | |
7215 | } frv_packet; | |
7216 | ||
7217 | /* Return the regstate_t flags for the given COND_EXEC condition. | |
7218 | Abort if the condition isn't in the right form. */ | |
36a05131 | 7219 | |
c557edf4 RS |
7220 | static int |
7221 | frv_cond_flags (rtx cond) | |
7222 | { | |
44e91694 NS |
7223 | gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE) |
7224 | && GET_CODE (XEXP (cond, 0)) == REG | |
7225 | && CR_P (REGNO (XEXP (cond, 0))) | |
7226 | && XEXP (cond, 1) == const0_rtx); | |
7227 | return ((REGNO (XEXP (cond, 0)) - CR_FIRST) | |
7228 | | (GET_CODE (cond) == NE | |
7229 | ? REGSTATE_IF_TRUE | |
7230 | : REGSTATE_IF_FALSE)); | |
c557edf4 | 7231 | } |
36a05131 | 7232 | |
36a05131 | 7233 | |
c557edf4 RS |
7234 | /* Return true if something accessed under condition COND2 can |
7235 | conflict with something written under condition COND1. */ | |
36a05131 | 7236 | |
c557edf4 RS |
7237 | static bool |
7238 | frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2) | |
7239 | { | |
7240 | /* If either reference was unconditional, we have a conflict. */ | |
7241 | if ((cond1 & REGSTATE_IF_EITHER) == 0 | |
7242 | || (cond2 & REGSTATE_IF_EITHER) == 0) | |
7243 | return true; | |
7244 | ||
7245 | /* The references might conflict if they were controlled by | |
7246 | different CRs. */ | |
7247 | if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK)) | |
7248 | return true; | |
7249 | ||
7250 | /* They definitely conflict if they are controlled by the | |
7251 | same condition. */ | |
7252 | if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0) | |
7253 | return true; | |
7254 | ||
7255 | return false; | |
36a05131 BS |
7256 | } |
7257 | ||
c557edf4 RS |
7258 | |
7259 | /* A for_each_rtx callback. Return 1 if *X depends on an instruction in | |
7260 | the current packet. DATA points to a regstate_t that describes the | |
7261 | condition under which *X might be set or used. */ | |
36a05131 BS |
7262 | |
7263 | static int | |
c557edf4 | 7264 | frv_registers_conflict_p_1 (rtx *x, void *data) |
36a05131 | 7265 | { |
c557edf4 RS |
7266 | unsigned int regno, i; |
7267 | regstate_t cond; | |
36a05131 | 7268 | |
c557edf4 | 7269 | cond = *(regstate_t *) data; |
36a05131 | 7270 | |
c557edf4 RS |
7271 | if (GET_CODE (*x) == REG) |
7272 | FOR_EACH_REGNO (regno, *x) | |
7273 | if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0) | |
7274 | if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond)) | |
7275 | return 1; | |
36a05131 | 7276 | |
c557edf4 RS |
7277 | if (GET_CODE (*x) == MEM) |
7278 | { | |
7279 | /* If we ran out of memory slots, assume a conflict. */ | |
7280 | if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems)) | |
7281 | return 1; | |
36a05131 | 7282 | |
c557edf4 RS |
7283 | /* Check for output or true dependencies with earlier MEMs. */ |
7284 | for (i = 0; i < frv_packet.num_mems; i++) | |
7285 | if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond)) | |
7286 | { | |
7287 | if (true_dependence (frv_packet.mems[i].mem, VOIDmode, | |
7288 | *x, rtx_varies_p)) | |
7289 | return 1; | |
36a05131 | 7290 | |
c557edf4 RS |
7291 | if (output_dependence (frv_packet.mems[i].mem, *x)) |
7292 | return 1; | |
7293 | } | |
7294 | } | |
36a05131 | 7295 | |
c557edf4 RS |
7296 | /* The return values of calls aren't significant: they describe |
7297 | the effect of the call as a whole, not of the insn itself. */ | |
7298 | if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL) | |
7299 | { | |
7300 | if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data)) | |
7301 | return 1; | |
7302 | return -1; | |
7303 | } | |
36a05131 | 7304 | |
c557edf4 RS |
7305 | /* Check subexpressions. */ |
7306 | return 0; | |
7307 | } | |
36a05131 | 7308 | |
36a05131 | 7309 | |
c557edf4 RS |
7310 | /* Return true if something in X might depend on an instruction |
7311 | in the current packet. */ | |
36a05131 | 7312 | |
c557edf4 RS |
7313 | static bool |
7314 | frv_registers_conflict_p (rtx x) | |
7315 | { | |
7316 | regstate_t flags; | |
36a05131 | 7317 | |
c557edf4 RS |
7318 | flags = 0; |
7319 | if (GET_CODE (x) == COND_EXEC) | |
7320 | { | |
7321 | if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags)) | |
7322 | return true; | |
36a05131 | 7323 | |
c557edf4 RS |
7324 | flags |= frv_cond_flags (XEXP (x, 0)); |
7325 | x = XEXP (x, 1); | |
36a05131 | 7326 | } |
c557edf4 RS |
7327 | return for_each_rtx (&x, frv_registers_conflict_p_1, &flags); |
7328 | } | |
36a05131 BS |
7329 | |
7330 | ||
c557edf4 RS |
7331 | /* A note_stores callback. DATA points to the regstate_t condition |
7332 | under which X is modified. Update FRV_PACKET accordingly. */ | |
36a05131 | 7333 | |
c557edf4 | 7334 | static void |
7bc980e1 | 7335 | frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) |
c557edf4 RS |
7336 | { |
7337 | unsigned int regno; | |
7338 | ||
7339 | if (GET_CODE (x) == REG) | |
7340 | FOR_EACH_REGNO (regno, x) | |
7341 | frv_packet.regstate[regno] |= *(regstate_t *) data; | |
7342 | ||
7343 | if (GET_CODE (x) == MEM) | |
36a05131 | 7344 | { |
c557edf4 | 7345 | if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems)) |
36a05131 | 7346 | { |
c557edf4 RS |
7347 | frv_packet.mems[frv_packet.num_mems].mem = x; |
7348 | frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data; | |
7349 | } | |
7350 | frv_packet.num_mems++; | |
7351 | } | |
7352 | } | |
36a05131 | 7353 | |
36a05131 | 7354 | |
c557edf4 RS |
7355 | /* Update the register state information for an instruction whose |
7356 | body is X. */ | |
7357 | ||
7358 | static void | |
7359 | frv_registers_update (rtx x) | |
7360 | { | |
7361 | regstate_t flags; | |
7362 | ||
7363 | flags = REGSTATE_MODIFIED; | |
7364 | if (GET_CODE (x) == COND_EXEC) | |
7365 | { | |
7366 | flags |= frv_cond_flags (XEXP (x, 0)); | |
7367 | x = XEXP (x, 1); | |
36a05131 | 7368 | } |
c557edf4 RS |
7369 | note_stores (x, frv_registers_update_1, &flags); |
7370 | } | |
36a05131 | 7371 | |
c557edf4 RS |
7372 | |
7373 | /* Initialize frv_packet for the start of a new packet. */ | |
7374 | ||
7375 | static void | |
7376 | frv_start_packet (void) | |
7377 | { | |
7378 | enum frv_insn_group group; | |
7379 | ||
7380 | memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate)); | |
7381 | frv_packet.num_mems = 0; | |
7382 | frv_packet.num_insns = 0; | |
7383 | for (group = 0; group < NUM_GROUPS; group++) | |
7384 | frv_packet.groups[group].num_insns = 0; | |
36a05131 BS |
7385 | } |
7386 | ||
36a05131 | 7387 | |
c557edf4 RS |
7388 | /* Likewise for the start of a new basic block. */ |
7389 | ||
7390 | static void | |
7391 | frv_start_packet_block (void) | |
36a05131 | 7392 | { |
c557edf4 RS |
7393 | state_reset (frv_packet.dfa_state); |
7394 | frv_start_packet (); | |
7395 | } | |
36a05131 | 7396 | |
c557edf4 RS |
7397 | |
7398 | /* Finish the current packet, if any, and start a new one. Call | |
7399 | HANDLE_PACKET with FRV_PACKET describing the completed packet. */ | |
7400 | ||
7401 | static void | |
7402 | frv_finish_packet (void (*handle_packet) (void)) | |
7403 | { | |
7404 | if (frv_packet.num_insns > 0) | |
36a05131 | 7405 | { |
c557edf4 RS |
7406 | handle_packet (); |
7407 | state_transition (frv_packet.dfa_state, 0); | |
7408 | frv_start_packet (); | |
7409 | } | |
7410 | } | |
36a05131 | 7411 | |
36a05131 | 7412 | |
c557edf4 RS |
7413 | /* Return true if INSN can be added to the current packet. Update |
7414 | the DFA state on success. */ | |
36a05131 | 7415 | |
c557edf4 RS |
7416 | static bool |
7417 | frv_pack_insn_p (rtx insn) | |
7418 | { | |
7419 | /* See if the packet is already as long as it can be. */ | |
7420 | if (frv_packet.num_insns == frv_packet.issue_rate) | |
7421 | return false; | |
36a05131 | 7422 | |
c557edf4 RS |
7423 | /* If the scheduler thought that an instruction should start a packet, |
7424 | it's usually a good idea to believe it. It knows much more about | |
7425 | the latencies than we do. | |
36a05131 | 7426 | |
c557edf4 | 7427 | There are some exceptions though: |
36a05131 | 7428 | |
c557edf4 RS |
7429 | - Conditional instructions are scheduled on the assumption that |
7430 | they will be executed. This is usually a good thing, since it | |
c112cf2b | 7431 | tends to avoid unnecessary stalls in the conditional code. |
c557edf4 RS |
7432 | But we want to pack conditional instructions as tightly as |
7433 | possible, in order to optimize the case where they aren't | |
7434 | executed. | |
36a05131 | 7435 | |
c557edf4 RS |
7436 | - The scheduler will always put branches on their own, even |
7437 | if there's no real dependency. | |
36a05131 | 7438 | |
c557edf4 RS |
7439 | - There's no point putting a call in its own packet unless |
7440 | we have to. */ | |
7441 | if (frv_packet.num_insns > 0 | |
7442 | && GET_CODE (insn) == INSN | |
7443 | && GET_MODE (insn) == TImode | |
7444 | && GET_CODE (PATTERN (insn)) != COND_EXEC) | |
7445 | return false; | |
36a05131 | 7446 | |
c557edf4 RS |
7447 | /* Check for register conflicts. Don't do this for setlo since any |
7448 | conflict will be with the partnering sethi, with which it can | |
7449 | be packed. */ | |
7450 | if (get_attr_type (insn) != TYPE_SETLO) | |
7451 | if (frv_registers_conflict_p (PATTERN (insn))) | |
7452 | return false; | |
36a05131 | 7453 | |
c557edf4 RS |
7454 | return state_transition (frv_packet.dfa_state, insn) < 0; |
7455 | } | |
36a05131 | 7456 | |
36a05131 | 7457 | |
c557edf4 | 7458 | /* Add instruction INSN to the current packet. */ |
36a05131 | 7459 | |
c557edf4 RS |
7460 | static void |
7461 | frv_add_insn_to_packet (rtx insn) | |
7462 | { | |
7463 | struct frv_packet_group *packet_group; | |
7464 | ||
7465 | packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]]; | |
7466 | packet_group->insns[packet_group->num_insns++] = insn; | |
7467 | frv_packet.insns[frv_packet.num_insns++] = insn; | |
7468 | ||
7469 | frv_registers_update (PATTERN (insn)); | |
36a05131 BS |
7470 | } |
7471 | ||
c557edf4 RS |
7472 | |
7473 | /* Insert INSN (a member of frv_nops[]) into the current packet. If the | |
7474 | packet ends in a branch or call, insert the nop before it, otherwise | |
7475 | add to the end. */ | |
36a05131 BS |
7476 | |
7477 | static void | |
c557edf4 | 7478 | frv_insert_nop_in_packet (rtx insn) |
36a05131 | 7479 | { |
c557edf4 RS |
7480 | struct frv_packet_group *packet_group; |
7481 | rtx last; | |
7482 | ||
7483 | packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]]; | |
7484 | last = frv_packet.insns[frv_packet.num_insns - 1]; | |
7485 | if (GET_CODE (last) != INSN) | |
7486 | { | |
7487 | insn = emit_insn_before (PATTERN (insn), last); | |
7488 | frv_packet.insns[frv_packet.num_insns - 1] = insn; | |
7489 | frv_packet.insns[frv_packet.num_insns++] = last; | |
7490 | } | |
7491 | else | |
7492 | { | |
7493 | insn = emit_insn_after (PATTERN (insn), last); | |
7494 | frv_packet.insns[frv_packet.num_insns++] = insn; | |
7495 | } | |
7496 | packet_group->insns[packet_group->num_insns++] = insn; | |
7497 | } | |
7498 | ||
36a05131 | 7499 | |
c557edf4 RS |
7500 | /* If packing is enabled, divide the instructions into packets and |
7501 | return true. Call HANDLE_PACKET for each complete packet. */ | |
7502 | ||
7503 | static bool | |
7504 | frv_for_each_packet (void (*handle_packet) (void)) | |
7505 | { | |
7506 | rtx insn, next_insn; | |
7507 | ||
7508 | frv_packet.issue_rate = frv_issue_rate (); | |
7509 | ||
7510 | /* Early exit if we don't want to pack insns. */ | |
28a60850 RS |
7511 | if (!optimize |
7512 | || !flag_schedule_insns_after_reload | |
0b2c18fe | 7513 | || !TARGET_VLIW_BRANCH |
c557edf4 RS |
7514 | || frv_packet.issue_rate == 1) |
7515 | return false; | |
36a05131 | 7516 | |
c557edf4 | 7517 | /* Set up the initial packing state. */ |
36a05131 | 7518 | dfa_start (); |
c557edf4 | 7519 | frv_packet.dfa_state = alloca (state_size ()); |
36a05131 | 7520 | |
c557edf4 RS |
7521 | frv_start_packet_block (); |
7522 | for (insn = get_insns (); insn != 0; insn = next_insn) | |
36a05131 | 7523 | { |
c557edf4 RS |
7524 | enum rtx_code code; |
7525 | bool eh_insn_p; | |
36a05131 | 7526 | |
c557edf4 RS |
7527 | code = GET_CODE (insn); |
7528 | next_insn = NEXT_INSN (insn); | |
7529 | ||
7530 | if (code == CODE_LABEL) | |
36a05131 | 7531 | { |
c557edf4 RS |
7532 | frv_finish_packet (handle_packet); |
7533 | frv_start_packet_block (); | |
7534 | } | |
36a05131 | 7535 | |
c557edf4 RS |
7536 | if (INSN_P (insn)) |
7537 | switch (GET_CODE (PATTERN (insn))) | |
7538 | { | |
7539 | case USE: | |
7540 | case CLOBBER: | |
7541 | case ADDR_VEC: | |
7542 | case ADDR_DIFF_VEC: | |
7543 | break; | |
36a05131 | 7544 | |
c557edf4 RS |
7545 | default: |
7546 | /* Calls mustn't be packed on a TOMCAT. */ | |
7547 | if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT) | |
7548 | frv_finish_packet (handle_packet); | |
7549 | ||
7550 | /* Since the last instruction in a packet determines the EH | |
7551 | region, any exception-throwing instruction must come at | |
7552 | the end of reordered packet. Insns that issue to a | |
7553 | branch unit are bound to come last; for others it's | |
7554 | too hard to predict. */ | |
7555 | eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL); | |
7556 | if (eh_insn_p && !frv_issues_to_branch_unit_p (insn)) | |
7557 | frv_finish_packet (handle_packet); | |
7558 | ||
7559 | /* Finish the current packet if we can't add INSN to it. | |
7560 | Simulate cycles until INSN is ready to issue. */ | |
7561 | if (!frv_pack_insn_p (insn)) | |
7562 | { | |
7563 | frv_finish_packet (handle_packet); | |
7564 | while (!frv_pack_insn_p (insn)) | |
7565 | state_transition (frv_packet.dfa_state, 0); | |
7566 | } | |
36a05131 | 7567 | |
c557edf4 RS |
7568 | /* Add the instruction to the packet. */ |
7569 | frv_add_insn_to_packet (insn); | |
7570 | ||
7571 | /* Calls and jumps end a packet, as do insns that throw | |
7572 | an exception. */ | |
7573 | if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p) | |
7574 | frv_finish_packet (handle_packet); | |
7575 | break; | |
7576 | } | |
7577 | } | |
7578 | frv_finish_packet (handle_packet); | |
7579 | dfa_finish (); | |
7580 | return true; | |
7581 | } | |
7582 | \f | |
7583 | /* Subroutine of frv_sort_insn_group. We are trying to sort | |
7584 | frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly | |
7585 | language order. We have already picked a new position for | |
7586 | frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set. | |
7587 | These instructions will occupy elements [0, LOWER_SLOT) and | |
7588 | [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is | |
7589 | the DFA state after issuing these instructions. | |
7590 | ||
7591 | Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation | |
7592 | of the unused instructions. Return true if one such permutation gives | |
7593 | a valid ordering, leaving the successful permutation in sorted[]. | |
7594 | Do not modify sorted[] until a valid permutation is found. */ | |
7595 | ||
7596 | static bool | |
7597 | frv_sort_insn_group_1 (enum frv_insn_group group, | |
7598 | unsigned int lower_slot, unsigned int upper_slot, | |
7599 | unsigned int issued, unsigned int num_insns, | |
7600 | state_t state) | |
7601 | { | |
7602 | struct frv_packet_group *packet_group; | |
7603 | unsigned int i; | |
7604 | state_t test_state; | |
7605 | size_t dfa_size; | |
7606 | rtx insn; | |
7607 | ||
7608 | /* Early success if we've filled all the slots. */ | |
7609 | if (lower_slot == upper_slot) | |
7610 | return true; | |
7611 | ||
7612 | packet_group = &frv_packet.groups[group]; | |
7613 | dfa_size = state_size (); | |
7614 | test_state = alloca (dfa_size); | |
7615 | ||
7616 | /* Try issuing each unused instruction. */ | |
7617 | for (i = num_insns - 1; i + 1 != 0; i--) | |
7618 | if (~issued & (1 << i)) | |
7619 | { | |
7620 | insn = packet_group->sorted[i]; | |
7621 | memcpy (test_state, state, dfa_size); | |
7622 | if (state_transition (test_state, insn) < 0 | |
7623 | && cpu_unit_reservation_p (test_state, | |
7624 | NTH_UNIT (group, upper_slot - 1)) | |
7625 | && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1, | |
7626 | issued | (1 << i), num_insns, | |
7627 | test_state)) | |
7628 | { | |
7629 | packet_group->sorted[upper_slot - 1] = insn; | |
7630 | return true; | |
7631 | } | |
7632 | } | |
7633 | ||
7634 | return false; | |
7635 | } | |
7636 | ||
7637 | /* Compare two instructions by their frv_insn_unit. */ | |
7638 | ||
7639 | static int | |
7640 | frv_compare_insns (const void *first, const void *second) | |
7641 | { | |
5ead67f6 KG |
7642 | const rtx *const insn1 = (rtx const *) first, |
7643 | *const insn2 = (rtx const *) second; | |
c557edf4 RS |
7644 | return frv_insn_unit (*insn1) - frv_insn_unit (*insn2); |
7645 | } | |
7646 | ||
7647 | /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[] | |
7648 | and sort it into assembly language order. See frv.md for a description of | |
7649 | the algorithm. */ | |
7650 | ||
7651 | static void | |
7652 | frv_sort_insn_group (enum frv_insn_group group) | |
7653 | { | |
7654 | struct frv_packet_group *packet_group; | |
7655 | unsigned int first, i, nop, max_unit, num_slots; | |
7656 | state_t state, test_state; | |
7657 | size_t dfa_size; | |
7658 | ||
7659 | packet_group = &frv_packet.groups[group]; | |
75d0ac8d RS |
7660 | |
7661 | /* Assume no nop is needed. */ | |
7662 | packet_group->nop = 0; | |
7663 | ||
c557edf4 RS |
7664 | if (packet_group->num_insns == 0) |
7665 | return; | |
7666 | ||
7667 | /* Copy insns[] to sorted[]. */ | |
7668 | memcpy (packet_group->sorted, packet_group->insns, | |
7669 | sizeof (rtx) * packet_group->num_insns); | |
7670 | ||
7671 | /* Sort sorted[] by the unit that each insn tries to take first. */ | |
7672 | if (packet_group->num_insns > 1) | |
7673 | qsort (packet_group->sorted, packet_group->num_insns, | |
7674 | sizeof (rtx), frv_compare_insns); | |
7675 | ||
7676 | /* That's always enough for branch and control insns. */ | |
7677 | if (group == GROUP_B || group == GROUP_C) | |
7678 | return; | |
7679 | ||
7680 | dfa_size = state_size (); | |
7681 | state = alloca (dfa_size); | |
7682 | test_state = alloca (dfa_size); | |
7683 | ||
7684 | /* Find the highest FIRST such that sorted[0...FIRST-1] can issue | |
7685 | consecutively and such that the DFA takes unit X when sorted[X] | |
7686 | is added. Set STATE to the new DFA state. */ | |
7687 | state_reset (test_state); | |
7688 | for (first = 0; first < packet_group->num_insns; first++) | |
7689 | { | |
7690 | memcpy (state, test_state, dfa_size); | |
7691 | if (state_transition (test_state, packet_group->sorted[first]) >= 0 | |
7692 | || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first))) | |
7693 | break; | |
7694 | } | |
7695 | ||
7696 | /* If all the instructions issued in ascending order, we're done. */ | |
7697 | if (first == packet_group->num_insns) | |
7698 | return; | |
36a05131 | 7699 | |
c557edf4 RS |
7700 | /* Add nops to the end of sorted[] and try each permutation until |
7701 | we find one that works. */ | |
7702 | for (nop = 0; nop < frv_num_nops; nop++) | |
7703 | { | |
7704 | max_unit = frv_insn_unit (frv_nops[nop]); | |
7705 | if (frv_unit_groups[max_unit] == group) | |
36a05131 | 7706 | { |
c557edf4 RS |
7707 | packet_group->nop = frv_nops[nop]; |
7708 | num_slots = UNIT_NUMBER (max_unit) + 1; | |
7709 | for (i = packet_group->num_insns; i < num_slots; i++) | |
7710 | packet_group->sorted[i] = frv_nops[nop]; | |
7711 | if (frv_sort_insn_group_1 (group, first, num_slots, | |
7712 | (1 << first) - 1, num_slots, state)) | |
7713 | return; | |
36a05131 | 7714 | } |
c557edf4 | 7715 | } |
44e91694 | 7716 | gcc_unreachable (); |
c557edf4 RS |
7717 | } |
7718 | \f | |
7719 | /* Sort the current packet into assembly-language order. Set packing | |
7720 | flags as appropriate. */ | |
36a05131 | 7721 | |
c557edf4 RS |
7722 | static void |
7723 | frv_reorder_packet (void) | |
7724 | { | |
7725 | unsigned int cursor[NUM_GROUPS]; | |
7726 | rtx insns[ARRAY_SIZE (frv_unit_groups)]; | |
7727 | unsigned int unit, to, from; | |
7728 | enum frv_insn_group group; | |
7729 | struct frv_packet_group *packet_group; | |
7730 | ||
7731 | /* First sort each group individually. */ | |
7732 | for (group = 0; group < NUM_GROUPS; group++) | |
7733 | { | |
7734 | cursor[group] = 0; | |
7735 | frv_sort_insn_group (group); | |
7736 | } | |
7737 | ||
7738 | /* Go through the unit template and try add an instruction from | |
7739 | that unit's group. */ | |
7740 | to = 0; | |
7741 | for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++) | |
7742 | { | |
7743 | group = frv_unit_groups[unit]; | |
7744 | packet_group = &frv_packet.groups[group]; | |
7745 | if (cursor[group] < packet_group->num_insns) | |
36a05131 | 7746 | { |
c557edf4 | 7747 | /* frv_reorg should have added nops for us. */ |
44e91694 NS |
7748 | gcc_assert (packet_group->sorted[cursor[group]] |
7749 | != packet_group->nop); | |
c557edf4 | 7750 | insns[to++] = packet_group->sorted[cursor[group]++]; |
36a05131 | 7751 | } |
c557edf4 | 7752 | } |
36a05131 | 7753 | |
44e91694 | 7754 | gcc_assert (to == frv_packet.num_insns); |
36a05131 | 7755 | |
c557edf4 RS |
7756 | /* Clear the last instruction's packing flag, thus marking the end of |
7757 | a packet. Reorder the other instructions relative to it. */ | |
7758 | CLEAR_PACKING_FLAG (insns[to - 1]); | |
7759 | for (from = 0; from < to - 1; from++) | |
7760 | { | |
7761 | remove_insn (insns[from]); | |
6fb5fa3c | 7762 | add_insn_before (insns[from], insns[to - 1], NULL); |
c557edf4 RS |
7763 | SET_PACKING_FLAG (insns[from]); |
7764 | } | |
7765 | } | |
36a05131 | 7766 | |
36a05131 | 7767 | |
c557edf4 RS |
7768 | /* Divide instructions into packets. Reorder the contents of each |
7769 | packet so that they are in the correct assembly-language order. | |
7770 | ||
7771 | Since this pass can change the raw meaning of the rtl stream, it must | |
7772 | only be called at the last minute, just before the instructions are | |
7773 | written out. */ | |
7774 | ||
7775 | static void | |
7776 | frv_pack_insns (void) | |
7777 | { | |
7778 | if (frv_for_each_packet (frv_reorder_packet)) | |
7779 | frv_insn_packing_flag = 0; | |
7780 | else | |
7781 | frv_insn_packing_flag = -1; | |
7782 | } | |
7783 | \f | |
7784 | /* See whether we need to add nops to group GROUP in order to | |
7785 | make a valid packet. */ | |
7786 | ||
7787 | static void | |
7788 | frv_fill_unused_units (enum frv_insn_group group) | |
7789 | { | |
7790 | unsigned int non_nops, nops, i; | |
7791 | struct frv_packet_group *packet_group; | |
7792 | ||
7793 | packet_group = &frv_packet.groups[group]; | |
7794 | ||
7795 | /* Sort the instructions into assembly-language order. | |
7796 | Use nops to fill slots that are otherwise unused. */ | |
7797 | frv_sort_insn_group (group); | |
7798 | ||
7799 | /* See how many nops are needed before the final useful instruction. */ | |
7800 | i = nops = 0; | |
7801 | for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++) | |
7802 | while (packet_group->sorted[i++] == packet_group->nop) | |
7803 | nops++; | |
7804 | ||
7805 | /* Insert that many nops into the instruction stream. */ | |
7806 | while (nops-- > 0) | |
7807 | frv_insert_nop_in_packet (packet_group->nop); | |
7808 | } | |
7809 | ||
38c28a25 AH |
7810 | /* Return true if accesses IO1 and IO2 refer to the same doubleword. */ |
7811 | ||
7812 | static bool | |
7813 | frv_same_doubleword_p (const struct frv_io *io1, const struct frv_io *io2) | |
7814 | { | |
7815 | if (io1->const_address != 0 && io2->const_address != 0) | |
7816 | return io1->const_address == io2->const_address; | |
7817 | ||
7818 | if (io1->var_address != 0 && io2->var_address != 0) | |
7819 | return rtx_equal_p (io1->var_address, io2->var_address); | |
7820 | ||
7821 | return false; | |
7822 | } | |
7823 | ||
7824 | /* Return true if operations IO1 and IO2 are guaranteed to complete | |
7825 | in order. */ | |
7826 | ||
7827 | static bool | |
7828 | frv_io_fixed_order_p (const struct frv_io *io1, const struct frv_io *io2) | |
7829 | { | |
7830 | /* The order of writes is always preserved. */ | |
7831 | if (io1->type == FRV_IO_WRITE && io2->type == FRV_IO_WRITE) | |
7832 | return true; | |
7833 | ||
7834 | /* The order of reads isn't preserved. */ | |
7835 | if (io1->type != FRV_IO_WRITE && io2->type != FRV_IO_WRITE) | |
7836 | return false; | |
7837 | ||
7838 | /* One operation is a write and the other is (or could be) a read. | |
7839 | The order is only guaranteed if the accesses are to the same | |
7840 | doubleword. */ | |
7841 | return frv_same_doubleword_p (io1, io2); | |
7842 | } | |
7843 | ||
7844 | /* Generalize I/O operation X so that it covers both X and Y. */ | |
7845 | ||
7846 | static void | |
7847 | frv_io_union (struct frv_io *x, const struct frv_io *y) | |
7848 | { | |
7849 | if (x->type != y->type) | |
7850 | x->type = FRV_IO_UNKNOWN; | |
7851 | if (!frv_same_doubleword_p (x, y)) | |
7852 | { | |
7853 | x->const_address = 0; | |
7854 | x->var_address = 0; | |
7855 | } | |
7856 | } | |
7857 | ||
7858 | /* Fill IO with information about the load or store associated with | |
7859 | membar instruction INSN. */ | |
7860 | ||
7861 | static void | |
7862 | frv_extract_membar (struct frv_io *io, rtx insn) | |
7863 | { | |
7864 | extract_insn (insn); | |
7865 | io->type = INTVAL (recog_data.operand[2]); | |
7866 | io->const_address = INTVAL (recog_data.operand[1]); | |
7867 | io->var_address = XEXP (recog_data.operand[0], 0); | |
7868 | } | |
7869 | ||
7870 | /* A note_stores callback for which DATA points to an rtx. Nullify *DATA | |
7871 | if X is a register and *DATA depends on X. */ | |
7872 | ||
7873 | static void | |
7bc980e1 | 7874 | frv_io_check_address (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) |
38c28a25 | 7875 | { |
5ead67f6 | 7876 | rtx *other = (rtx *) data; |
38c28a25 AH |
7877 | |
7878 | if (REG_P (x) && *other != 0 && reg_overlap_mentioned_p (x, *other)) | |
7879 | *other = 0; | |
7880 | } | |
7881 | ||
7882 | /* A note_stores callback for which DATA points to a HARD_REG_SET. | |
7883 | Remove every modified register from the set. */ | |
7884 | ||
7885 | static void | |
7bc980e1 | 7886 | frv_io_handle_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) |
38c28a25 | 7887 | { |
5ead67f6 | 7888 | HARD_REG_SET *set = (HARD_REG_SET *) data; |
38c28a25 AH |
7889 | unsigned int regno; |
7890 | ||
7891 | if (REG_P (x)) | |
7892 | FOR_EACH_REGNO (regno, x) | |
7893 | CLEAR_HARD_REG_BIT (*set, regno); | |
7894 | } | |
7895 | ||
7896 | /* A for_each_rtx callback for which DATA points to a HARD_REG_SET. | |
7897 | Add every register in *X to the set. */ | |
7898 | ||
7899 | static int | |
7900 | frv_io_handle_use_1 (rtx *x, void *data) | |
7901 | { | |
5ead67f6 | 7902 | HARD_REG_SET *set = (HARD_REG_SET *) data; |
38c28a25 AH |
7903 | unsigned int regno; |
7904 | ||
7905 | if (REG_P (*x)) | |
7906 | FOR_EACH_REGNO (regno, *x) | |
7907 | SET_HARD_REG_BIT (*set, regno); | |
7908 | ||
7909 | return 0; | |
7910 | } | |
7911 | ||
7912 | /* A note_stores callback that applies frv_io_handle_use_1 to an | |
7913 | entire rhs value. */ | |
7914 | ||
7915 | static void | |
7916 | frv_io_handle_use (rtx *x, void *data) | |
7917 | { | |
7918 | for_each_rtx (x, frv_io_handle_use_1, data); | |
7919 | } | |
7920 | ||
7921 | /* Go through block BB looking for membars to remove. There are two | |
7922 | cases where intra-block analysis is enough: | |
7923 | ||
7924 | - a membar is redundant if it occurs between two consecutive I/O | |
7925 | operations and if those operations are guaranteed to complete | |
7926 | in order. | |
7927 | ||
7928 | - a membar for a __builtin_read is redundant if the result is | |
7929 | used before the next I/O operation is issued. | |
7930 | ||
7931 | If the last membar in the block could not be removed, and there | |
7932 | are guaranteed to be no I/O operations between that membar and | |
7933 | the end of the block, store the membar in *LAST_MEMBAR, otherwise | |
7934 | store null. | |
7935 | ||
7936 | Describe the block's first I/O operation in *NEXT_IO. Describe | |
7937 | an unknown operation if the block doesn't do any I/O. */ | |
7938 | ||
7939 | static void | |
7940 | frv_optimize_membar_local (basic_block bb, struct frv_io *next_io, | |
7941 | rtx *last_membar) | |
7942 | { | |
7943 | HARD_REG_SET used_regs; | |
7944 | rtx next_membar, set, insn; | |
7945 | bool next_is_end_p; | |
7946 | ||
7947 | /* NEXT_IO is the next I/O operation to be performed after the current | |
7948 | instruction. It starts off as being an unknown operation. */ | |
7949 | memset (next_io, 0, sizeof (*next_io)); | |
7950 | ||
7951 | /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */ | |
7952 | next_is_end_p = true; | |
7953 | ||
7954 | /* If the current instruction is a __builtin_read or __builtin_write, | |
7955 | NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR | |
7956 | is null if the membar has already been deleted. | |
7957 | ||
7958 | Note that the initialization here should only be needed to | |
536fa7b7 | 7959 | suppress warnings. */ |
38c28a25 AH |
7960 | next_membar = 0; |
7961 | ||
7962 | /* USED_REGS is the set of registers that are used before the | |
7963 | next I/O instruction. */ | |
7964 | CLEAR_HARD_REG_SET (used_regs); | |
7965 | ||
7966 | for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn)) | |
7967 | if (GET_CODE (insn) == CALL_INSN) | |
7968 | { | |
7969 | /* We can't predict what a call will do to volatile memory. */ | |
7970 | memset (next_io, 0, sizeof (struct frv_io)); | |
7971 | next_is_end_p = false; | |
7972 | CLEAR_HARD_REG_SET (used_regs); | |
7973 | } | |
7974 | else if (INSN_P (insn)) | |
7975 | switch (recog_memoized (insn)) | |
7976 | { | |
7977 | case CODE_FOR_optional_membar_qi: | |
7978 | case CODE_FOR_optional_membar_hi: | |
7979 | case CODE_FOR_optional_membar_si: | |
7980 | case CODE_FOR_optional_membar_di: | |
7981 | next_membar = insn; | |
7982 | if (next_is_end_p) | |
7983 | { | |
7984 | /* Local information isn't enough to decide whether this | |
7985 | membar is needed. Stash it away for later. */ | |
7986 | *last_membar = insn; | |
7987 | frv_extract_membar (next_io, insn); | |
7988 | next_is_end_p = false; | |
7989 | } | |
7990 | else | |
7991 | { | |
7992 | /* Check whether the I/O operation before INSN could be | |
7993 | reordered with one described by NEXT_IO. If it can't, | |
7994 | INSN will not be needed. */ | |
7995 | struct frv_io prev_io; | |
7996 | ||
7997 | frv_extract_membar (&prev_io, insn); | |
7998 | if (frv_io_fixed_order_p (&prev_io, next_io)) | |
7999 | { | |
8000 | if (dump_file) | |
8001 | fprintf (dump_file, | |
8002 | ";; [Local] Removing membar %d since order" | |
8003 | " of accesses is guaranteed\n", | |
8004 | INSN_UID (next_membar)); | |
8005 | ||
8006 | insn = NEXT_INSN (insn); | |
8007 | delete_insn (next_membar); | |
8008 | next_membar = 0; | |
8009 | } | |
8010 | *next_io = prev_io; | |
8011 | } | |
8012 | break; | |
8013 | ||
8014 | default: | |
8015 | /* Invalidate NEXT_IO's address if it depends on something that | |
8016 | is clobbered by INSN. */ | |
8017 | if (next_io->var_address) | |
8018 | note_stores (PATTERN (insn), frv_io_check_address, | |
8019 | &next_io->var_address); | |
8020 | ||
8021 | /* If the next membar is associated with a __builtin_read, | |
8022 | see if INSN reads from that address. If it does, and if | |
8023 | the destination register is used before the next I/O access, | |
8024 | there is no need for the membar. */ | |
8025 | set = PATTERN (insn); | |
8026 | if (next_io->type == FRV_IO_READ | |
8027 | && next_io->var_address != 0 | |
8028 | && next_membar != 0 | |
8029 | && GET_CODE (set) == SET | |
8030 | && GET_CODE (SET_DEST (set)) == REG | |
8031 | && TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set)))) | |
8032 | { | |
8033 | rtx src; | |
8034 | ||
8035 | src = SET_SRC (set); | |
8036 | if (GET_CODE (src) == ZERO_EXTEND) | |
8037 | src = XEXP (src, 0); | |
8038 | ||
8039 | if (GET_CODE (src) == MEM | |
8040 | && rtx_equal_p (XEXP (src, 0), next_io->var_address)) | |
8041 | { | |
8042 | if (dump_file) | |
8043 | fprintf (dump_file, | |
8044 | ";; [Local] Removing membar %d since the target" | |
8045 | " of %d is used before the I/O operation\n", | |
8046 | INSN_UID (next_membar), INSN_UID (insn)); | |
8047 | ||
8048 | if (next_membar == *last_membar) | |
8049 | *last_membar = 0; | |
8050 | ||
8051 | delete_insn (next_membar); | |
8052 | next_membar = 0; | |
8053 | } | |
8054 | } | |
8055 | ||
8056 | /* If INSN has volatile references, forget about any registers | |
8057 | that are used after it. Otherwise forget about uses that | |
8058 | are (or might be) defined by INSN. */ | |
8059 | if (volatile_refs_p (PATTERN (insn))) | |
8060 | CLEAR_HARD_REG_SET (used_regs); | |
8061 | else | |
8062 | note_stores (PATTERN (insn), frv_io_handle_set, &used_regs); | |
8063 | ||
8064 | note_uses (&PATTERN (insn), frv_io_handle_use, &used_regs); | |
8065 | break; | |
8066 | } | |
8067 | } | |
8068 | ||
8069 | /* See if MEMBAR, the last membar instruction in BB, can be removed. | |
8070 | FIRST_IO[X] describes the first operation performed by basic block X. */ | |
8071 | ||
8072 | static void | |
8073 | frv_optimize_membar_global (basic_block bb, struct frv_io *first_io, | |
8074 | rtx membar) | |
8075 | { | |
8076 | struct frv_io this_io, next_io; | |
8077 | edge succ; | |
8078 | edge_iterator ei; | |
8079 | ||
8080 | /* We need to keep the membar if there is an edge to the exit block. */ | |
8081 | FOR_EACH_EDGE (succ, ei, bb->succs) | |
8082 | /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */ | |
8083 | if (succ->dest == EXIT_BLOCK_PTR) | |
8084 | return; | |
8085 | ||
8086 | /* Work out the union of all successor blocks. */ | |
8087 | ei = ei_start (bb->succs); | |
8088 | ei_cond (ei, &succ); | |
8089 | /* next_io = first_io[bb->succ->dest->index]; */ | |
8090 | next_io = first_io[succ->dest->index]; | |
8091 | ei = ei_start (bb->succs); | |
8092 | if (ei_cond (ei, &succ)) | |
8093 | { | |
8094 | for (ei_next (&ei); ei_cond (ei, &succ); ei_next (&ei)) | |
8095 | /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/ | |
8096 | frv_io_union (&next_io, &first_io[succ->dest->index]); | |
8097 | } | |
8098 | else | |
8099 | gcc_unreachable (); | |
8100 | ||
8101 | frv_extract_membar (&this_io, membar); | |
8102 | if (frv_io_fixed_order_p (&this_io, &next_io)) | |
8103 | { | |
8104 | if (dump_file) | |
8105 | fprintf (dump_file, | |
8106 | ";; [Global] Removing membar %d since order of accesses" | |
8107 | " is guaranteed\n", INSN_UID (membar)); | |
8108 | ||
8109 | delete_insn (membar); | |
8110 | } | |
8111 | } | |
8112 | ||
8113 | /* Remove redundant membars from the current function. */ | |
8114 | ||
8115 | static void | |
8116 | frv_optimize_membar (void) | |
8117 | { | |
8118 | basic_block bb; | |
8119 | struct frv_io *first_io; | |
8120 | rtx *last_membar; | |
8121 | ||
8122 | compute_bb_for_insn (); | |
5ead67f6 KG |
8123 | first_io = XCNEWVEC (struct frv_io, last_basic_block); |
8124 | last_membar = XCNEWVEC (rtx, last_basic_block); | |
38c28a25 AH |
8125 | |
8126 | FOR_EACH_BB (bb) | |
8127 | frv_optimize_membar_local (bb, &first_io[bb->index], | |
8128 | &last_membar[bb->index]); | |
8129 | ||
8130 | FOR_EACH_BB (bb) | |
8131 | if (last_membar[bb->index] != 0) | |
8132 | frv_optimize_membar_global (bb, first_io, last_membar[bb->index]); | |
8133 | ||
8134 | free (first_io); | |
8135 | free (last_membar); | |
8136 | } | |
8137 | \f | |
c557edf4 RS |
8138 | /* Used by frv_reorg to keep track of the current packet's address. */ |
8139 | static unsigned int frv_packet_address; | |
36a05131 | 8140 | |
c557edf4 RS |
8141 | /* If the current packet falls through to a label, try to pad the packet |
8142 | with nops in order to fit the label's alignment requirements. */ | |
8143 | ||
8144 | static void | |
8145 | frv_align_label (void) | |
8146 | { | |
8147 | unsigned int alignment, target, nop; | |
8148 | rtx x, last, barrier, label; | |
8149 | ||
8150 | /* Walk forward to the start of the next packet. Set ALIGNMENT to the | |
8151 | maximum alignment of that packet, LABEL to the last label between | |
8152 | the packets, and BARRIER to the last barrier. */ | |
8153 | last = frv_packet.insns[frv_packet.num_insns - 1]; | |
8154 | label = barrier = 0; | |
8155 | alignment = 4; | |
8156 | for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x)) | |
8157 | { | |
8158 | if (LABEL_P (x)) | |
36a05131 | 8159 | { |
c557edf4 RS |
8160 | unsigned int subalign = 1 << label_to_alignment (x); |
8161 | alignment = MAX (alignment, subalign); | |
8162 | label = x; | |
36a05131 | 8163 | } |
c557edf4 RS |
8164 | if (BARRIER_P (x)) |
8165 | barrier = x; | |
8166 | } | |
36a05131 | 8167 | |
c557edf4 RS |
8168 | /* If -malign-labels, and the packet falls through to an unaligned |
8169 | label, try introducing a nop to align that label to 8 bytes. */ | |
8170 | if (TARGET_ALIGN_LABELS | |
8171 | && label != 0 | |
8172 | && barrier == 0 | |
8173 | && frv_packet.num_insns < frv_packet.issue_rate) | |
8174 | alignment = MAX (alignment, 8); | |
36a05131 | 8175 | |
c557edf4 RS |
8176 | /* Advance the address to the end of the current packet. */ |
8177 | frv_packet_address += frv_packet.num_insns * 4; | |
36a05131 | 8178 | |
c557edf4 RS |
8179 | /* Work out the target address, after alignment. */ |
8180 | target = (frv_packet_address + alignment - 1) & -alignment; | |
8181 | ||
8182 | /* If the packet falls through to the label, try to find an efficient | |
8183 | padding sequence. */ | |
8184 | if (barrier == 0) | |
8185 | { | |
8186 | /* First try adding nops to the current packet. */ | |
8187 | for (nop = 0; nop < frv_num_nops; nop++) | |
8188 | while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop])) | |
8189 | { | |
8190 | frv_insert_nop_in_packet (frv_nops[nop]); | |
8191 | frv_packet_address += 4; | |
8192 | } | |
8193 | ||
8194 | /* If we still haven't reached the target, add some new packets that | |
8195 | contain only nops. If there are two types of nop, insert an | |
8196 | alternating sequence of frv_nops[0] and frv_nops[1], which will | |
8197 | lead to packets like: | |
8198 | ||
8199 | nop.p | |
8200 | mnop.p/fnop.p | |
8201 | nop.p | |
8202 | mnop/fnop | |
8203 | ||
8204 | etc. Just emit frv_nops[0] if that's the only nop we have. */ | |
8205 | last = frv_packet.insns[frv_packet.num_insns - 1]; | |
8206 | nop = 0; | |
8207 | while (frv_packet_address < target) | |
8208 | { | |
8209 | last = emit_insn_after (PATTERN (frv_nops[nop]), last); | |
8210 | frv_packet_address += 4; | |
8211 | if (frv_num_nops > 1) | |
8212 | nop ^= 1; | |
36a05131 BS |
8213 | } |
8214 | } | |
8215 | ||
c557edf4 | 8216 | frv_packet_address = target; |
36a05131 BS |
8217 | } |
8218 | ||
c557edf4 RS |
8219 | /* Subroutine of frv_reorg, called after each packet has been constructed |
8220 | in frv_packet. */ | |
8221 | ||
8222 | static void | |
8223 | frv_reorg_packet (void) | |
8224 | { | |
8225 | frv_fill_unused_units (GROUP_I); | |
8226 | frv_fill_unused_units (GROUP_FM); | |
8227 | frv_align_label (); | |
8228 | } | |
8229 | ||
8230 | /* Add an instruction with pattern NOP to frv_nops[]. */ | |
8231 | ||
8232 | static void | |
8233 | frv_register_nop (rtx nop) | |
8234 | { | |
8235 | nop = make_insn_raw (nop); | |
8236 | NEXT_INSN (nop) = 0; | |
8237 | PREV_INSN (nop) = 0; | |
8238 | frv_nops[frv_num_nops++] = nop; | |
8239 | } | |
8240 | ||
8241 | /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions | |
8242 | into packets and check whether we need to insert nops in order to | |
8243 | fulfill the processor's issue requirements. Also, if the user has | |
8244 | requested a certain alignment for a label, try to meet that alignment | |
8245 | by inserting nops in the previous packet. */ | |
8246 | ||
8247 | static void | |
8248 | frv_reorg (void) | |
8249 | { | |
38c28a25 AH |
8250 | if (optimize > 0 && TARGET_OPTIMIZE_MEMBAR && cfun->machine->has_membar_p) |
8251 | frv_optimize_membar (); | |
8252 | ||
c557edf4 RS |
8253 | frv_num_nops = 0; |
8254 | frv_register_nop (gen_nop ()); | |
8255 | if (TARGET_MEDIA) | |
8256 | frv_register_nop (gen_mnop ()); | |
8257 | if (TARGET_HARD_FLOAT) | |
8258 | frv_register_nop (gen_fnop ()); | |
8259 | ||
8260 | /* Estimate the length of each branch. Although this may change after | |
8261 | we've inserted nops, it will only do so in big functions. */ | |
8262 | shorten_branches (get_insns ()); | |
8263 | ||
8264 | frv_packet_address = 0; | |
8265 | frv_for_each_packet (frv_reorg_packet); | |
8266 | } | |
36a05131 BS |
8267 | \f |
8268 | #define def_builtin(name, type, code) \ | |
c79efc4d | 8269 | add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL) |
36a05131 BS |
8270 | |
8271 | struct builtin_description | |
8272 | { | |
8273 | enum insn_code icode; | |
8274 | const char *name; | |
8275 | enum frv_builtins code; | |
8276 | enum rtx_code comparison; | |
8277 | unsigned int flag; | |
8278 | }; | |
8279 | ||
8280 | /* Media intrinsics that take a single, constant argument. */ | |
8281 | ||
8282 | static struct builtin_description bdesc_set[] = | |
8283 | { | |
8284 | { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 } | |
8285 | }; | |
8286 | ||
87b483a1 | 8287 | /* Media intrinsics that take just one argument. */ |
36a05131 BS |
8288 | |
8289 | static struct builtin_description bdesc_1arg[] = | |
8290 | { | |
8291 | { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 }, | |
8292 | { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 }, | |
8293 | { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 }, | |
8294 | { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 }, | |
c557edf4 RS |
8295 | { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 }, |
8296 | { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 } | |
36a05131 BS |
8297 | }; |
8298 | ||
87b483a1 | 8299 | /* Media intrinsics that take two arguments. */ |
36a05131 BS |
8300 | |
8301 | static struct builtin_description bdesc_2arg[] = | |
8302 | { | |
8303 | { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 }, | |
8304 | { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 }, | |
8305 | { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 }, | |
8306 | { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 }, | |
8307 | { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 }, | |
8308 | { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 }, | |
8309 | { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 }, | |
8310 | { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 }, | |
8311 | { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 }, | |
8312 | { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 }, | |
8313 | { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 }, | |
8314 | { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 }, | |
8315 | { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 }, | |
8316 | { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 }, | |
8317 | { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 }, | |
36a05131 BS |
8318 | { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 }, |
8319 | { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 }, | |
8320 | { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 }, | |
c557edf4 RS |
8321 | { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 }, |
8322 | { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 }, | |
8323 | { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 }, | |
8324 | { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 }, | |
8325 | { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 }, | |
8326 | { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 }, | |
8327 | { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 }, | |
8328 | { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 }, | |
8329 | { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 } | |
8330 | }; | |
8331 | ||
8332 | /* Integer intrinsics that take two arguments and have no return value. */ | |
8333 | ||
8334 | static struct builtin_description bdesc_int_void2arg[] = | |
8335 | { | |
8336 | { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 }, | |
8337 | { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 }, | |
8338 | { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 } | |
8339 | }; | |
8340 | ||
8341 | static struct builtin_description bdesc_prefetches[] = | |
8342 | { | |
8343 | { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 }, | |
8344 | { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 } | |
36a05131 BS |
8345 | }; |
8346 | ||
8347 | /* Media intrinsics that take two arguments, the first being an ACC number. */ | |
8348 | ||
8349 | static struct builtin_description bdesc_cut[] = | |
8350 | { | |
8351 | { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 }, | |
8352 | { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 }, | |
8353 | { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 } | |
8354 | }; | |
8355 | ||
87b483a1 | 8356 | /* Two-argument media intrinsics with an immediate second argument. */ |
36a05131 BS |
8357 | |
8358 | static struct builtin_description bdesc_2argimm[] = | |
8359 | { | |
8360 | { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 }, | |
8361 | { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 }, | |
8362 | { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 }, | |
8363 | { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 }, | |
8364 | { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 }, | |
8365 | { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 }, | |
8366 | { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 }, | |
8367 | { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 }, | |
8368 | { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 }, | |
8369 | { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 }, | |
8370 | { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 }, | |
8371 | { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 }, | |
8372 | { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 }, | |
8373 | { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 }, | |
c557edf4 RS |
8374 | { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 }, |
8375 | { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 }, | |
8376 | { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 } | |
36a05131 BS |
8377 | }; |
8378 | ||
8379 | /* Media intrinsics that take two arguments and return void, the first argument | |
87b483a1 | 8380 | being a pointer to 4 words in memory. */ |
36a05131 BS |
8381 | |
8382 | static struct builtin_description bdesc_void2arg[] = | |
8383 | { | |
8384 | { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 }, | |
8385 | { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 }, | |
8386 | }; | |
8387 | ||
8388 | /* Media intrinsics that take three arguments, the first being a const_int that | |
87b483a1 | 8389 | denotes an accumulator, and that return void. */ |
36a05131 BS |
8390 | |
8391 | static struct builtin_description bdesc_void3arg[] = | |
8392 | { | |
8393 | { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 }, | |
8394 | { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 }, | |
8395 | { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 }, | |
8396 | { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 }, | |
8397 | { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 }, | |
8398 | { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 }, | |
8399 | { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 }, | |
8400 | { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 }, | |
8401 | { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 }, | |
8402 | { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 }, | |
8403 | { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 }, | |
8404 | { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 }, | |
8405 | { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 }, | |
8406 | { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 }, | |
8407 | { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 }, | |
8408 | { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 }, | |
8409 | { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 }, | |
8410 | { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 }, | |
8411 | { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 }, | |
8412 | { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 }, | |
8413 | { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 }, | |
8414 | { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 }, | |
8415 | { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 }, | |
8416 | { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 }, | |
8417 | { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 } | |
8418 | }; | |
8419 | ||
8420 | /* Media intrinsics that take two accumulator numbers as argument and | |
8421 | return void. */ | |
8422 | ||
8423 | static struct builtin_description bdesc_voidacc[] = | |
8424 | { | |
8425 | { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 }, | |
8426 | { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 }, | |
8427 | { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 }, | |
8428 | { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 }, | |
8429 | { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 }, | |
8430 | { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 } | |
8431 | }; | |
8432 | ||
38c28a25 AH |
8433 | /* Intrinsics that load a value and then issue a MEMBAR. The load is |
8434 | a normal move and the ICODE is for the membar. */ | |
c14ff86e AH |
8435 | |
8436 | static struct builtin_description bdesc_loads[] = | |
8437 | { | |
38c28a25 AH |
8438 | { CODE_FOR_optional_membar_qi, "__builtin_read8", |
8439 | FRV_BUILTIN_READ8, 0, 0 }, | |
8440 | { CODE_FOR_optional_membar_hi, "__builtin_read16", | |
8441 | FRV_BUILTIN_READ16, 0, 0 }, | |
8442 | { CODE_FOR_optional_membar_si, "__builtin_read32", | |
8443 | FRV_BUILTIN_READ32, 0, 0 }, | |
8444 | { CODE_FOR_optional_membar_di, "__builtin_read64", | |
8445 | FRV_BUILTIN_READ64, 0, 0 } | |
c14ff86e AH |
8446 | }; |
8447 | ||
8448 | /* Likewise stores. */ | |
8449 | ||
8450 | static struct builtin_description bdesc_stores[] = | |
8451 | { | |
38c28a25 AH |
8452 | { CODE_FOR_optional_membar_qi, "__builtin_write8", |
8453 | FRV_BUILTIN_WRITE8, 0, 0 }, | |
8454 | { CODE_FOR_optional_membar_hi, "__builtin_write16", | |
8455 | FRV_BUILTIN_WRITE16, 0, 0 }, | |
8456 | { CODE_FOR_optional_membar_si, "__builtin_write32", | |
8457 | FRV_BUILTIN_WRITE32, 0, 0 }, | |
8458 | { CODE_FOR_optional_membar_di, "__builtin_write64", | |
8459 | FRV_BUILTIN_WRITE64, 0, 0 }, | |
c14ff86e AH |
8460 | }; |
8461 | ||
87b483a1 | 8462 | /* Initialize media builtins. */ |
36a05131 | 8463 | |
14966b94 | 8464 | static void |
f2206911 | 8465 | frv_init_builtins (void) |
36a05131 BS |
8466 | { |
8467 | tree endlink = void_list_node; | |
8468 | tree accumulator = integer_type_node; | |
8469 | tree integer = integer_type_node; | |
8470 | tree voidt = void_type_node; | |
8471 | tree uhalf = short_unsigned_type_node; | |
8472 | tree sword1 = long_integer_type_node; | |
8473 | tree uword1 = long_unsigned_type_node; | |
8474 | tree sword2 = long_long_integer_type_node; | |
8475 | tree uword2 = long_long_unsigned_type_node; | |
8476 | tree uword4 = build_pointer_type (uword1); | |
c14ff86e AH |
8477 | tree vptr = build_pointer_type (build_type_variant (void_type_node, 0, 1)); |
8478 | tree ubyte = unsigned_char_type_node; | |
c557edf4 | 8479 | tree iacc = integer_type_node; |
36a05131 BS |
8480 | |
8481 | #define UNARY(RET, T1) \ | |
8482 | build_function_type (RET, tree_cons (NULL_TREE, T1, endlink)) | |
8483 | ||
8484 | #define BINARY(RET, T1, T2) \ | |
8485 | build_function_type (RET, tree_cons (NULL_TREE, T1, \ | |
8486 | tree_cons (NULL_TREE, T2, endlink))) | |
8487 | ||
8488 | #define TRINARY(RET, T1, T2, T3) \ | |
8489 | build_function_type (RET, tree_cons (NULL_TREE, T1, \ | |
8490 | tree_cons (NULL_TREE, T2, \ | |
8491 | tree_cons (NULL_TREE, T3, endlink)))) | |
8492 | ||
a738d848 RS |
8493 | #define QUAD(RET, T1, T2, T3, T4) \ |
8494 | build_function_type (RET, tree_cons (NULL_TREE, T1, \ | |
8495 | tree_cons (NULL_TREE, T2, \ | |
8496 | tree_cons (NULL_TREE, T3, \ | |
8497 | tree_cons (NULL_TREE, T4, endlink))))) | |
8498 | ||
36a05131 BS |
8499 | tree void_ftype_void = build_function_type (voidt, endlink); |
8500 | ||
8501 | tree void_ftype_acc = UNARY (voidt, accumulator); | |
8502 | tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1); | |
8503 | tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2); | |
8504 | tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1); | |
8505 | tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator); | |
8506 | tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1); | |
8507 | tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1); | |
8508 | tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2); | |
8509 | tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2); | |
8510 | ||
8511 | tree uw1_ftype_uw1 = UNARY (uword1, uword1); | |
8512 | tree uw1_ftype_sw1 = UNARY (uword1, sword1); | |
8513 | tree uw1_ftype_uw2 = UNARY (uword1, uword2); | |
8514 | tree uw1_ftype_acc = UNARY (uword1, accumulator); | |
8515 | tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf); | |
8516 | tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1); | |
8517 | tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer); | |
8518 | tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1); | |
8519 | tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1); | |
8520 | tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1); | |
8521 | tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer); | |
8522 | ||
8523 | tree sw1_ftype_int = UNARY (sword1, integer); | |
8524 | tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1); | |
8525 | tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer); | |
8526 | ||
8527 | tree uw2_ftype_uw1 = UNARY (uword2, uword1); | |
8528 | tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer); | |
8529 | tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2); | |
8530 | tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer); | |
8531 | tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer); | |
a738d848 | 8532 | tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf); |
36a05131 BS |
8533 | |
8534 | tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2); | |
c557edf4 RS |
8535 | tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer); |
8536 | tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1); | |
8537 | tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1); | |
8538 | tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1); | |
8539 | tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2); | |
8540 | tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1); | |
8541 | tree sw1_ftype_sw1 = UNARY (sword1, sword1); | |
8542 | tree sw2_ftype_iacc = UNARY (sword2, iacc); | |
8543 | tree sw1_ftype_iacc = UNARY (sword1, iacc); | |
8544 | tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node); | |
c14ff86e AH |
8545 | tree uw1_ftype_vptr = UNARY (uword1, vptr); |
8546 | tree uw2_ftype_vptr = UNARY (uword2, vptr); | |
8547 | tree void_ftype_vptr_ub = BINARY (voidt, vptr, ubyte); | |
8548 | tree void_ftype_vptr_uh = BINARY (voidt, vptr, uhalf); | |
8549 | tree void_ftype_vptr_uw1 = BINARY (voidt, vptr, uword1); | |
8550 | tree void_ftype_vptr_uw2 = BINARY (voidt, vptr, uword2); | |
36a05131 BS |
8551 | |
8552 | def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND); | |
8553 | def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR); | |
8554 | def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR); | |
8555 | def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT); | |
8556 | def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI); | |
8557 | def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI); | |
8558 | def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT); | |
8559 | def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH); | |
8560 | def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI); | |
8561 | def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI); | |
8562 | def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI); | |
8563 | def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS); | |
8564 | def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU); | |
8565 | def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS); | |
8566 | def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS); | |
8567 | def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS); | |
8568 | def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS); | |
8569 | def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS); | |
8570 | def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU); | |
8571 | def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS); | |
8572 | def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU); | |
8573 | def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS); | |
8574 | def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU); | |
8575 | def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS); | |
8576 | def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU); | |
8577 | def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS); | |
8578 | def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS); | |
8579 | def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS); | |
8580 | def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS); | |
8581 | def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS); | |
8582 | def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU); | |
8583 | def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS); | |
8584 | def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU); | |
8585 | def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS); | |
8586 | def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU); | |
8587 | def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS); | |
8588 | def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU); | |
8589 | def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS); | |
8590 | def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU); | |
8591 | def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS); | |
8592 | def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU); | |
8593 | def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS); | |
8594 | def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU); | |
8595 | def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT); | |
8596 | def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS); | |
8597 | def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW); | |
8598 | def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD); | |
8599 | def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH); | |
8600 | def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH); | |
a738d848 | 8601 | def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH); |
b16c1435 | 8602 | def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH); |
36a05131 BS |
8603 | def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH); |
8604 | def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB); | |
8605 | def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE); | |
8606 | def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC); | |
8607 | def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA); | |
8608 | def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC); | |
8609 | def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG); | |
8610 | def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC); | |
8611 | def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG); | |
8612 | def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1); | |
8613 | def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2); | |
8614 | def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP); | |
8615 | def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS); | |
8616 | def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS); | |
8617 | def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS); | |
8618 | def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS); | |
8619 | def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS); | |
8620 | def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS); | |
8621 | def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS); | |
8622 | def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS); | |
8623 | def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS); | |
8624 | def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS); | |
8625 | def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI); | |
8626 | def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI); | |
8627 | def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI); | |
8628 | def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI); | |
8629 | def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS); | |
8630 | def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS); | |
8631 | def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS); | |
8632 | def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS); | |
8633 | def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH); | |
8634 | def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH); | |
8635 | def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH); | |
c557edf4 RS |
8636 | def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS); |
8637 | def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS); | |
8638 | def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI); | |
8639 | def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI); | |
8640 | def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL); | |
8641 | def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL); | |
8642 | def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS); | |
8643 | def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS); | |
8644 | def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU); | |
8645 | def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS); | |
8646 | def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS); | |
8647 | def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS); | |
8648 | def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN); | |
8649 | def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS); | |
8650 | def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll); | |
8651 | def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl); | |
8652 | def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll); | |
8653 | def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl); | |
8654 | def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0); | |
8655 | def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH); | |
c14ff86e AH |
8656 | def_builtin ("__builtin_read8", uw1_ftype_vptr, FRV_BUILTIN_READ8); |
8657 | def_builtin ("__builtin_read16", uw1_ftype_vptr, FRV_BUILTIN_READ16); | |
8658 | def_builtin ("__builtin_read32", uw1_ftype_vptr, FRV_BUILTIN_READ32); | |
8659 | def_builtin ("__builtin_read64", uw2_ftype_vptr, FRV_BUILTIN_READ64); | |
8660 | ||
8661 | def_builtin ("__builtin_write8", void_ftype_vptr_ub, FRV_BUILTIN_WRITE8); | |
8662 | def_builtin ("__builtin_write16", void_ftype_vptr_uh, FRV_BUILTIN_WRITE16); | |
8663 | def_builtin ("__builtin_write32", void_ftype_vptr_uw1, FRV_BUILTIN_WRITE32); | |
8664 | def_builtin ("__builtin_write64", void_ftype_vptr_uw2, FRV_BUILTIN_WRITE64); | |
36a05131 BS |
8665 | |
8666 | #undef UNARY | |
8667 | #undef BINARY | |
8668 | #undef TRINARY | |
a738d848 | 8669 | #undef QUAD |
36a05131 BS |
8670 | } |
8671 | ||
c15c90bb ZW |
8672 | /* Set the names for various arithmetic operations according to the |
8673 | FRV ABI. */ | |
8674 | static void | |
8675 | frv_init_libfuncs (void) | |
8676 | { | |
8677 | set_optab_libfunc (smod_optab, SImode, "__modi"); | |
8678 | set_optab_libfunc (umod_optab, SImode, "__umodi"); | |
8679 | ||
8680 | set_optab_libfunc (add_optab, DImode, "__addll"); | |
8681 | set_optab_libfunc (sub_optab, DImode, "__subll"); | |
8682 | set_optab_libfunc (smul_optab, DImode, "__mulll"); | |
8683 | set_optab_libfunc (sdiv_optab, DImode, "__divll"); | |
8684 | set_optab_libfunc (smod_optab, DImode, "__modll"); | |
8685 | set_optab_libfunc (umod_optab, DImode, "__umodll"); | |
8686 | set_optab_libfunc (and_optab, DImode, "__andll"); | |
8687 | set_optab_libfunc (ior_optab, DImode, "__orll"); | |
8688 | set_optab_libfunc (xor_optab, DImode, "__xorll"); | |
8689 | set_optab_libfunc (one_cmpl_optab, DImode, "__notll"); | |
8690 | ||
8691 | set_optab_libfunc (add_optab, SFmode, "__addf"); | |
8692 | set_optab_libfunc (sub_optab, SFmode, "__subf"); | |
8693 | set_optab_libfunc (smul_optab, SFmode, "__mulf"); | |
8694 | set_optab_libfunc (sdiv_optab, SFmode, "__divf"); | |
8695 | ||
8696 | set_optab_libfunc (add_optab, DFmode, "__addd"); | |
8697 | set_optab_libfunc (sub_optab, DFmode, "__subd"); | |
8698 | set_optab_libfunc (smul_optab, DFmode, "__muld"); | |
8699 | set_optab_libfunc (sdiv_optab, DFmode, "__divd"); | |
8700 | ||
85363ca0 ZW |
8701 | set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod"); |
8702 | set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof"); | |
8703 | ||
8704 | set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi"); | |
8705 | set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll"); | |
8706 | set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi"); | |
8707 | set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll"); | |
8708 | ||
8709 | set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui"); | |
09c55720 RS |
8710 | set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull"); |
8711 | set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui"); | |
8712 | set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull"); | |
85363ca0 ZW |
8713 | |
8714 | set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof"); | |
8715 | set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof"); | |
8716 | set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod"); | |
8717 | set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod"); | |
c15c90bb ZW |
8718 | } |
8719 | ||
36a05131 BS |
8720 | /* Convert an integer constant to an accumulator register. ICODE is the |
8721 | code of the target instruction, OPNUM is the number of the | |
8722 | accumulator operand and OPVAL is the constant integer. Try both | |
8723 | ACC and ACCG registers; only report an error if neither fit the | |
8724 | instruction. */ | |
8725 | ||
8726 | static rtx | |
f2206911 | 8727 | frv_int_to_acc (enum insn_code icode, int opnum, rtx opval) |
36a05131 BS |
8728 | { |
8729 | rtx reg; | |
c557edf4 RS |
8730 | int i; |
8731 | ||
0fa2e4df | 8732 | /* ACCs and ACCGs are implicit global registers if media intrinsics |
c557edf4 | 8733 | are being used. We set up this lazily to avoid creating lots of |
c112cf2b | 8734 | unnecessary call_insn rtl in non-media code. */ |
c557edf4 RS |
8735 | for (i = 0; i <= ACC_MASK; i++) |
8736 | if ((i & ACC_MASK) == i) | |
8737 | global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1; | |
36a05131 BS |
8738 | |
8739 | if (GET_CODE (opval) != CONST_INT) | |
8740 | { | |
8741 | error ("accumulator is not a constant integer"); | |
8742 | return NULL_RTX; | |
8743 | } | |
c557edf4 | 8744 | if ((INTVAL (opval) & ~ACC_MASK) != 0) |
36a05131 BS |
8745 | { |
8746 | error ("accumulator number is out of bounds"); | |
8747 | return NULL_RTX; | |
8748 | } | |
8749 | ||
8750 | reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode, | |
8751 | ACC_FIRST + INTVAL (opval)); | |
8752 | if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode)) | |
6fb5fa3c | 8753 | SET_REGNO (reg, ACCG_FIRST + INTVAL (opval)); |
36a05131 BS |
8754 | |
8755 | if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode)) | |
8756 | { | |
9e637a26 | 8757 | error ("inappropriate accumulator for %qs", insn_data[icode].name); |
36a05131 BS |
8758 | return NULL_RTX; |
8759 | } | |
8760 | return reg; | |
8761 | } | |
8762 | ||
8763 | /* If an ACC rtx has mode MODE, return the mode that the matching ACCG | |
8764 | should have. */ | |
8765 | ||
8766 | static enum machine_mode | |
f2206911 | 8767 | frv_matching_accg_mode (enum machine_mode mode) |
36a05131 BS |
8768 | { |
8769 | switch (mode) | |
8770 | { | |
8771 | case V4SImode: | |
8772 | return V4QImode; | |
8773 | ||
8774 | case DImode: | |
8775 | return HImode; | |
8776 | ||
8777 | case SImode: | |
8778 | return QImode; | |
8779 | ||
8780 | default: | |
44e91694 | 8781 | gcc_unreachable (); |
36a05131 BS |
8782 | } |
8783 | } | |
8784 | ||
38c28a25 AH |
8785 | /* Given that a __builtin_read or __builtin_write function is accessing |
8786 | address ADDRESS, return the value that should be used as operand 1 | |
8787 | of the membar. */ | |
8788 | ||
8789 | static rtx | |
8790 | frv_io_address_cookie (rtx address) | |
8791 | { | |
8792 | return (GET_CODE (address) == CONST_INT | |
8793 | ? GEN_INT (INTVAL (address) / 8 * 8) | |
8794 | : const0_rtx); | |
8795 | } | |
8796 | ||
36a05131 BS |
8797 | /* Return the accumulator guard that should be paired with accumulator |
8798 | register ACC. The mode of the returned register is in the same | |
8799 | class as ACC, but is four times smaller. */ | |
8800 | ||
8801 | rtx | |
f2206911 | 8802 | frv_matching_accg_for_acc (rtx acc) |
36a05131 BS |
8803 | { |
8804 | return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)), | |
8805 | REGNO (acc) - ACC_FIRST + ACCG_FIRST); | |
8806 | } | |
8807 | ||
2396bce1 EC |
8808 | /* Read the requested argument from the call EXP given by INDEX. |
8809 | Return the value as an rtx. */ | |
36a05131 BS |
8810 | |
8811 | static rtx | |
2396bce1 | 8812 | frv_read_argument (tree exp, unsigned int index) |
36a05131 | 8813 | { |
2396bce1 EC |
8814 | return expand_expr (CALL_EXPR_ARG (exp, index), |
8815 | NULL_RTX, VOIDmode, 0); | |
36a05131 BS |
8816 | } |
8817 | ||
c557edf4 RS |
8818 | /* Like frv_read_argument, but interpret the argument as the number |
8819 | of an IACC register and return a (reg:MODE ...) rtx for it. */ | |
8820 | ||
8821 | static rtx | |
2396bce1 EC |
8822 | frv_read_iacc_argument (enum machine_mode mode, tree call, |
8823 | unsigned int index) | |
c557edf4 RS |
8824 | { |
8825 | int i, regno; | |
8826 | rtx op; | |
8827 | ||
2396bce1 | 8828 | op = frv_read_argument (call, index); |
c557edf4 RS |
8829 | if (GET_CODE (op) != CONST_INT |
8830 | || INTVAL (op) < 0 | |
8831 | || INTVAL (op) > IACC_LAST - IACC_FIRST | |
8832 | || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0) | |
8833 | { | |
8834 | error ("invalid IACC argument"); | |
8835 | op = const0_rtx; | |
8836 | } | |
8837 | ||
0fa2e4df | 8838 | /* IACCs are implicit global registers. We set up this lazily to |
c112cf2b | 8839 | avoid creating lots of unnecessary call_insn rtl when IACCs aren't |
c557edf4 RS |
8840 | being used. */ |
8841 | regno = INTVAL (op) + IACC_FIRST; | |
8842 | for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++) | |
8843 | global_regs[regno + i] = 1; | |
8844 | ||
8845 | return gen_rtx_REG (mode, regno); | |
8846 | } | |
8847 | ||
36a05131 BS |
8848 | /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE. |
8849 | The instruction should require a constant operand of some sort. The | |
8850 | function prints an error if OPVAL is not valid. */ | |
8851 | ||
8852 | static int | |
f2206911 | 8853 | frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval) |
36a05131 BS |
8854 | { |
8855 | if (GET_CODE (opval) != CONST_INT) | |
8856 | { | |
9e637a26 | 8857 | error ("%qs expects a constant argument", insn_data[icode].name); |
36a05131 BS |
8858 | return FALSE; |
8859 | } | |
8860 | if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode)) | |
8861 | { | |
9e637a26 | 8862 | error ("constant argument out of range for %qs", insn_data[icode].name); |
36a05131 BS |
8863 | return FALSE; |
8864 | } | |
8865 | return TRUE; | |
8866 | } | |
8867 | ||
8868 | /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET | |
8869 | if it's not null, has the right mode, and satisfies operand 0's | |
8870 | predicate. */ | |
8871 | ||
8872 | static rtx | |
f2206911 | 8873 | frv_legitimize_target (enum insn_code icode, rtx target) |
36a05131 BS |
8874 | { |
8875 | enum machine_mode mode = insn_data[icode].operand[0].mode; | |
8876 | ||
8877 | if (! target | |
8878 | || GET_MODE (target) != mode | |
8879 | || ! (*insn_data[icode].operand[0].predicate) (target, mode)) | |
8880 | return gen_reg_rtx (mode); | |
8881 | else | |
8882 | return target; | |
8883 | } | |
8884 | ||
8885 | /* Given that ARG is being passed as operand OPNUM to instruction ICODE, | |
839a4992 | 8886 | check whether ARG satisfies the operand's constraints. If it doesn't, |
36a05131 BS |
8887 | copy ARG to a temporary register and return that. Otherwise return ARG |
8888 | itself. */ | |
8889 | ||
8890 | static rtx | |
f2206911 | 8891 | frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg) |
36a05131 BS |
8892 | { |
8893 | enum machine_mode mode = insn_data[icode].operand[opnum].mode; | |
8894 | ||
8895 | if ((*insn_data[icode].operand[opnum].predicate) (arg, mode)) | |
8896 | return arg; | |
8897 | else | |
8898 | return copy_to_mode_reg (mode, arg); | |
8899 | } | |
8900 | ||
c14ff86e AH |
8901 | /* Return a volatile memory reference of mode MODE whose address is ARG. */ |
8902 | ||
8903 | static rtx | |
8904 | frv_volatile_memref (enum machine_mode mode, rtx arg) | |
8905 | { | |
8906 | rtx mem; | |
8907 | ||
8908 | mem = gen_rtx_MEM (mode, memory_address (mode, arg)); | |
8909 | MEM_VOLATILE_P (mem) = 1; | |
8910 | return mem; | |
8911 | } | |
8912 | ||
36a05131 BS |
8913 | /* Expand builtins that take a single, constant argument. At the moment, |
8914 | only MHDSETS falls into this category. */ | |
8915 | ||
8916 | static rtx | |
2396bce1 | 8917 | frv_expand_set_builtin (enum insn_code icode, tree call, rtx target) |
36a05131 BS |
8918 | { |
8919 | rtx pat; | |
2396bce1 | 8920 | rtx op0 = frv_read_argument (call, 0); |
36a05131 BS |
8921 | |
8922 | if (! frv_check_constant_argument (icode, 1, op0)) | |
8923 | return NULL_RTX; | |
8924 | ||
8925 | target = frv_legitimize_target (icode, target); | |
8926 | pat = GEN_FCN (icode) (target, op0); | |
8927 | if (! pat) | |
8928 | return NULL_RTX; | |
8929 | ||
8930 | emit_insn (pat); | |
8931 | return target; | |
8932 | } | |
8933 | ||
87b483a1 | 8934 | /* Expand builtins that take one operand. */ |
36a05131 BS |
8935 | |
8936 | static rtx | |
2396bce1 | 8937 | frv_expand_unop_builtin (enum insn_code icode, tree call, rtx target) |
36a05131 BS |
8938 | { |
8939 | rtx pat; | |
2396bce1 | 8940 | rtx op0 = frv_read_argument (call, 0); |
36a05131 BS |
8941 | |
8942 | target = frv_legitimize_target (icode, target); | |
8943 | op0 = frv_legitimize_argument (icode, 1, op0); | |
8944 | pat = GEN_FCN (icode) (target, op0); | |
8945 | if (! pat) | |
8946 | return NULL_RTX; | |
8947 | ||
8948 | emit_insn (pat); | |
8949 | return target; | |
8950 | } | |
8951 | ||
87b483a1 | 8952 | /* Expand builtins that take two operands. */ |
36a05131 BS |
8953 | |
8954 | static rtx | |
2396bce1 | 8955 | frv_expand_binop_builtin (enum insn_code icode, tree call, rtx target) |
36a05131 BS |
8956 | { |
8957 | rtx pat; | |
2396bce1 EC |
8958 | rtx op0 = frv_read_argument (call, 0); |
8959 | rtx op1 = frv_read_argument (call, 1); | |
36a05131 BS |
8960 | |
8961 | target = frv_legitimize_target (icode, target); | |
8962 | op0 = frv_legitimize_argument (icode, 1, op0); | |
8963 | op1 = frv_legitimize_argument (icode, 2, op1); | |
8964 | pat = GEN_FCN (icode) (target, op0, op1); | |
8965 | if (! pat) | |
8966 | return NULL_RTX; | |
8967 | ||
8968 | emit_insn (pat); | |
8969 | return target; | |
8970 | } | |
8971 | ||
8972 | /* Expand cut-style builtins, which take two operands and an implicit ACCG | |
87b483a1 | 8973 | one. */ |
36a05131 BS |
8974 | |
8975 | static rtx | |
2396bce1 | 8976 | frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target) |
36a05131 BS |
8977 | { |
8978 | rtx pat; | |
2396bce1 EC |
8979 | rtx op0 = frv_read_argument (call, 0); |
8980 | rtx op1 = frv_read_argument (call, 1); | |
36a05131 BS |
8981 | rtx op2; |
8982 | ||
8983 | target = frv_legitimize_target (icode, target); | |
8984 | op0 = frv_int_to_acc (icode, 1, op0); | |
8985 | if (! op0) | |
8986 | return NULL_RTX; | |
8987 | ||
8988 | if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT) | |
8989 | { | |
8990 | if (! frv_check_constant_argument (icode, 2, op1)) | |
8991 | return NULL_RTX; | |
8992 | } | |
8993 | else | |
8994 | op1 = frv_legitimize_argument (icode, 2, op1); | |
8995 | ||
8996 | op2 = frv_matching_accg_for_acc (op0); | |
8997 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
8998 | if (! pat) | |
8999 | return NULL_RTX; | |
9000 | ||
9001 | emit_insn (pat); | |
9002 | return target; | |
9003 | } | |
9004 | ||
87b483a1 | 9005 | /* Expand builtins that take two operands and the second is immediate. */ |
36a05131 BS |
9006 | |
9007 | static rtx | |
2396bce1 | 9008 | frv_expand_binopimm_builtin (enum insn_code icode, tree call, rtx target) |
36a05131 BS |
9009 | { |
9010 | rtx pat; | |
2396bce1 EC |
9011 | rtx op0 = frv_read_argument (call, 0); |
9012 | rtx op1 = frv_read_argument (call, 1); | |
36a05131 BS |
9013 | |
9014 | if (! frv_check_constant_argument (icode, 2, op1)) | |
9015 | return NULL_RTX; | |
9016 | ||
9017 | target = frv_legitimize_target (icode, target); | |
9018 | op0 = frv_legitimize_argument (icode, 1, op0); | |
9019 | pat = GEN_FCN (icode) (target, op0, op1); | |
9020 | if (! pat) | |
9021 | return NULL_RTX; | |
9022 | ||
9023 | emit_insn (pat); | |
9024 | return target; | |
9025 | } | |
9026 | ||
9027 | /* Expand builtins that take two operands, the first operand being a pointer to | |
87b483a1 | 9028 | ints and return void. */ |
36a05131 BS |
9029 | |
9030 | static rtx | |
2396bce1 | 9031 | frv_expand_voidbinop_builtin (enum insn_code icode, tree call) |
36a05131 BS |
9032 | { |
9033 | rtx pat; | |
2396bce1 EC |
9034 | rtx op0 = frv_read_argument (call, 0); |
9035 | rtx op1 = frv_read_argument (call, 1); | |
36a05131 BS |
9036 | enum machine_mode mode0 = insn_data[icode].operand[0].mode; |
9037 | rtx addr; | |
9038 | ||
9039 | if (GET_CODE (op0) != MEM) | |
9040 | { | |
9041 | rtx reg = op0; | |
9042 | ||
9043 | if (! offsettable_address_p (0, mode0, op0)) | |
9044 | { | |
9045 | reg = gen_reg_rtx (Pmode); | |
9046 | emit_insn (gen_rtx_SET (VOIDmode, reg, op0)); | |
9047 | } | |
9048 | ||
9049 | op0 = gen_rtx_MEM (SImode, reg); | |
9050 | } | |
9051 | ||
9052 | addr = XEXP (op0, 0); | |
9053 | if (! offsettable_address_p (0, mode0, addr)) | |
9054 | addr = copy_to_mode_reg (Pmode, op0); | |
9055 | ||
9056 | op0 = change_address (op0, V4SImode, addr); | |
9057 | op1 = frv_legitimize_argument (icode, 1, op1); | |
9058 | pat = GEN_FCN (icode) (op0, op1); | |
9059 | if (! pat) | |
9060 | return 0; | |
9061 | ||
9062 | emit_insn (pat); | |
9063 | return 0; | |
9064 | } | |
9065 | ||
c557edf4 RS |
9066 | /* Expand builtins that take two long operands and return void. */ |
9067 | ||
9068 | static rtx | |
2396bce1 | 9069 | frv_expand_int_void2arg (enum insn_code icode, tree call) |
c557edf4 RS |
9070 | { |
9071 | rtx pat; | |
2396bce1 EC |
9072 | rtx op0 = frv_read_argument (call, 0); |
9073 | rtx op1 = frv_read_argument (call, 1); | |
c557edf4 RS |
9074 | |
9075 | op0 = frv_legitimize_argument (icode, 1, op0); | |
9076 | op1 = frv_legitimize_argument (icode, 1, op1); | |
9077 | pat = GEN_FCN (icode) (op0, op1); | |
9078 | if (! pat) | |
9079 | return NULL_RTX; | |
9080 | ||
9081 | emit_insn (pat); | |
9082 | return NULL_RTX; | |
9083 | } | |
9084 | ||
9085 | /* Expand prefetch builtins. These take a single address as argument. */ | |
9086 | ||
9087 | static rtx | |
2396bce1 | 9088 | frv_expand_prefetches (enum insn_code icode, tree call) |
c557edf4 RS |
9089 | { |
9090 | rtx pat; | |
2396bce1 | 9091 | rtx op0 = frv_read_argument (call, 0); |
c557edf4 RS |
9092 | |
9093 | pat = GEN_FCN (icode) (force_reg (Pmode, op0)); | |
9094 | if (! pat) | |
9095 | return 0; | |
9096 | ||
9097 | emit_insn (pat); | |
9098 | return 0; | |
9099 | } | |
9100 | ||
36a05131 BS |
9101 | /* Expand builtins that take three operands and return void. The first |
9102 | argument must be a constant that describes a pair or quad accumulators. A | |
9103 | fourth argument is created that is the accumulator guard register that | |
9104 | corresponds to the accumulator. */ | |
9105 | ||
9106 | static rtx | |
2396bce1 | 9107 | frv_expand_voidtriop_builtin (enum insn_code icode, tree call) |
36a05131 BS |
9108 | { |
9109 | rtx pat; | |
2396bce1 EC |
9110 | rtx op0 = frv_read_argument (call, 0); |
9111 | rtx op1 = frv_read_argument (call, 1); | |
9112 | rtx op2 = frv_read_argument (call, 2); | |
36a05131 BS |
9113 | rtx op3; |
9114 | ||
9115 | op0 = frv_int_to_acc (icode, 0, op0); | |
9116 | if (! op0) | |
9117 | return NULL_RTX; | |
9118 | ||
9119 | op1 = frv_legitimize_argument (icode, 1, op1); | |
9120 | op2 = frv_legitimize_argument (icode, 2, op2); | |
9121 | op3 = frv_matching_accg_for_acc (op0); | |
9122 | pat = GEN_FCN (icode) (op0, op1, op2, op3); | |
9123 | if (! pat) | |
9124 | return NULL_RTX; | |
9125 | ||
9126 | emit_insn (pat); | |
9127 | return NULL_RTX; | |
9128 | } | |
9129 | ||
9130 | /* Expand builtins that perform accumulator-to-accumulator operations. | |
9131 | These builtins take two accumulator numbers as argument and return | |
9132 | void. */ | |
9133 | ||
9134 | static rtx | |
2396bce1 | 9135 | frv_expand_voidaccop_builtin (enum insn_code icode, tree call) |
36a05131 BS |
9136 | { |
9137 | rtx pat; | |
2396bce1 EC |
9138 | rtx op0 = frv_read_argument (call, 0); |
9139 | rtx op1 = frv_read_argument (call, 1); | |
36a05131 BS |
9140 | rtx op2; |
9141 | rtx op3; | |
9142 | ||
9143 | op0 = frv_int_to_acc (icode, 0, op0); | |
9144 | if (! op0) | |
9145 | return NULL_RTX; | |
9146 | ||
9147 | op1 = frv_int_to_acc (icode, 1, op1); | |
9148 | if (! op1) | |
9149 | return NULL_RTX; | |
9150 | ||
9151 | op2 = frv_matching_accg_for_acc (op0); | |
9152 | op3 = frv_matching_accg_for_acc (op1); | |
9153 | pat = GEN_FCN (icode) (op0, op1, op2, op3); | |
9154 | if (! pat) | |
9155 | return NULL_RTX; | |
9156 | ||
9157 | emit_insn (pat); | |
9158 | return NULL_RTX; | |
9159 | } | |
9160 | ||
38c28a25 AH |
9161 | /* Expand a __builtin_read* function. ICODE is the instruction code for the |
9162 | membar and TARGET_MODE is the mode that the loaded value should have. */ | |
c14ff86e AH |
9163 | |
9164 | static rtx | |
38c28a25 | 9165 | frv_expand_load_builtin (enum insn_code icode, enum machine_mode target_mode, |
2396bce1 | 9166 | tree call, rtx target) |
c14ff86e | 9167 | { |
2396bce1 | 9168 | rtx op0 = frv_read_argument (call, 0); |
38c28a25 AH |
9169 | rtx cookie = frv_io_address_cookie (op0); |
9170 | ||
9171 | if (target == 0 || !REG_P (target)) | |
9172 | target = gen_reg_rtx (target_mode); | |
9173 | op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0); | |
9174 | convert_move (target, op0, 1); | |
9175 | emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ))); | |
9176 | cfun->machine->has_membar_p = 1; | |
c14ff86e AH |
9177 | return target; |
9178 | } | |
9179 | ||
38c28a25 | 9180 | /* Likewise __builtin_write* functions. */ |
c14ff86e AH |
9181 | |
9182 | static rtx | |
2396bce1 | 9183 | frv_expand_store_builtin (enum insn_code icode, tree call) |
c14ff86e | 9184 | { |
2396bce1 EC |
9185 | rtx op0 = frv_read_argument (call, 0); |
9186 | rtx op1 = frv_read_argument (call, 1); | |
38c28a25 | 9187 | rtx cookie = frv_io_address_cookie (op0); |
c14ff86e | 9188 | |
38c28a25 AH |
9189 | op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0); |
9190 | convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1); | |
9191 | emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE))); | |
9192 | cfun->machine->has_membar_p = 1; | |
c14ff86e AH |
9193 | return NULL_RTX; |
9194 | } | |
9195 | ||
a738d848 RS |
9196 | /* Expand the MDPACKH builtin. It takes four unsigned short arguments and |
9197 | each argument forms one word of the two double-word input registers. | |
2396bce1 EC |
9198 | CALL is the tree for the call and TARGET, if nonnull, suggests a good place |
9199 | to put the return value. */ | |
a738d848 RS |
9200 | |
9201 | static rtx | |
2396bce1 | 9202 | frv_expand_mdpackh_builtin (tree call, rtx target) |
a738d848 RS |
9203 | { |
9204 | enum insn_code icode = CODE_FOR_mdpackh; | |
9205 | rtx pat, op0, op1; | |
2396bce1 EC |
9206 | rtx arg1 = frv_read_argument (call, 0); |
9207 | rtx arg2 = frv_read_argument (call, 1); | |
9208 | rtx arg3 = frv_read_argument (call, 2); | |
9209 | rtx arg4 = frv_read_argument (call, 3); | |
a738d848 RS |
9210 | |
9211 | target = frv_legitimize_target (icode, target); | |
9212 | op0 = gen_reg_rtx (DImode); | |
9213 | op1 = gen_reg_rtx (DImode); | |
9214 | ||
0fa2e4df | 9215 | /* The high half of each word is not explicitly initialized, so indicate |
a738d848 | 9216 | that the input operands are not live before this point. */ |
c41c1387 RS |
9217 | emit_clobber (op0); |
9218 | emit_clobber (op1); | |
a738d848 RS |
9219 | |
9220 | /* Move each argument into the low half of its associated input word. */ | |
9221 | emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1); | |
9222 | emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2); | |
9223 | emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3); | |
9224 | emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4); | |
9225 | ||
9226 | pat = GEN_FCN (icode) (target, op0, op1); | |
9227 | if (! pat) | |
9228 | return NULL_RTX; | |
9229 | ||
9230 | emit_insn (pat); | |
9231 | return target; | |
9232 | } | |
9233 | ||
36a05131 BS |
9234 | /* Expand the MCLRACC builtin. This builtin takes a single accumulator |
9235 | number as argument. */ | |
9236 | ||
9237 | static rtx | |
2396bce1 | 9238 | frv_expand_mclracc_builtin (tree call) |
36a05131 BS |
9239 | { |
9240 | enum insn_code icode = CODE_FOR_mclracc; | |
9241 | rtx pat; | |
2396bce1 | 9242 | rtx op0 = frv_read_argument (call, 0); |
36a05131 BS |
9243 | |
9244 | op0 = frv_int_to_acc (icode, 0, op0); | |
9245 | if (! op0) | |
9246 | return NULL_RTX; | |
9247 | ||
9248 | pat = GEN_FCN (icode) (op0); | |
9249 | if (pat) | |
9250 | emit_insn (pat); | |
9251 | ||
9252 | return NULL_RTX; | |
9253 | } | |
9254 | ||
9255 | /* Expand builtins that take no arguments. */ | |
9256 | ||
9257 | static rtx | |
f2206911 | 9258 | frv_expand_noargs_builtin (enum insn_code icode) |
36a05131 | 9259 | { |
a556fd39 | 9260 | rtx pat = GEN_FCN (icode) (const0_rtx); |
36a05131 BS |
9261 | if (pat) |
9262 | emit_insn (pat); | |
9263 | ||
9264 | return NULL_RTX; | |
9265 | } | |
9266 | ||
9267 | /* Expand MRDACC and MRDACCG. These builtins take a single accumulator | |
9268 | number or accumulator guard number as argument and return an SI integer. */ | |
9269 | ||
9270 | static rtx | |
2396bce1 | 9271 | frv_expand_mrdacc_builtin (enum insn_code icode, tree call) |
36a05131 BS |
9272 | { |
9273 | rtx pat; | |
9274 | rtx target = gen_reg_rtx (SImode); | |
2396bce1 | 9275 | rtx op0 = frv_read_argument (call, 0); |
36a05131 BS |
9276 | |
9277 | op0 = frv_int_to_acc (icode, 1, op0); | |
9278 | if (! op0) | |
9279 | return NULL_RTX; | |
9280 | ||
9281 | pat = GEN_FCN (icode) (target, op0); | |
9282 | if (! pat) | |
9283 | return NULL_RTX; | |
9284 | ||
9285 | emit_insn (pat); | |
9286 | return target; | |
9287 | } | |
9288 | ||
9289 | /* Expand MWTACC and MWTACCG. These builtins take an accumulator or | |
9290 | accumulator guard as their first argument and an SImode value as their | |
9291 | second. */ | |
9292 | ||
9293 | static rtx | |
2396bce1 | 9294 | frv_expand_mwtacc_builtin (enum insn_code icode, tree call) |
36a05131 BS |
9295 | { |
9296 | rtx pat; | |
2396bce1 EC |
9297 | rtx op0 = frv_read_argument (call, 0); |
9298 | rtx op1 = frv_read_argument (call, 1); | |
36a05131 BS |
9299 | |
9300 | op0 = frv_int_to_acc (icode, 0, op0); | |
9301 | if (! op0) | |
9302 | return NULL_RTX; | |
9303 | ||
9304 | op1 = frv_legitimize_argument (icode, 1, op1); | |
9305 | pat = GEN_FCN (icode) (op0, op1); | |
9306 | if (pat) | |
9307 | emit_insn (pat); | |
9308 | ||
9309 | return NULL_RTX; | |
9310 | } | |
9311 | ||
c557edf4 RS |
9312 | /* Emit a move from SRC to DEST in SImode chunks. This can be used |
9313 | to move DImode values into and out of IACC0. */ | |
9314 | ||
9315 | static void | |
9316 | frv_split_iacc_move (rtx dest, rtx src) | |
9317 | { | |
9318 | enum machine_mode inner; | |
9319 | int i; | |
9320 | ||
9321 | inner = GET_MODE (dest); | |
9322 | for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode)) | |
9323 | emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i), | |
9324 | simplify_gen_subreg (SImode, src, inner, i)); | |
9325 | } | |
9326 | ||
87b483a1 | 9327 | /* Expand builtins. */ |
36a05131 | 9328 | |
14966b94 | 9329 | static rtx |
f2206911 KC |
9330 | frv_expand_builtin (tree exp, |
9331 | rtx target, | |
9332 | rtx subtarget ATTRIBUTE_UNUSED, | |
9333 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
9334 | int ignore ATTRIBUTE_UNUSED) | |
36a05131 | 9335 | { |
5039610b | 9336 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
36a05131 BS |
9337 | unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl); |
9338 | unsigned i; | |
9339 | struct builtin_description *d; | |
9340 | ||
c557edf4 | 9341 | if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA) |
36a05131 BS |
9342 | { |
9343 | error ("media functions are not available unless -mmedia is used"); | |
9344 | return NULL_RTX; | |
9345 | } | |
9346 | ||
9347 | switch (fcode) | |
9348 | { | |
9349 | case FRV_BUILTIN_MCOP1: | |
9350 | case FRV_BUILTIN_MCOP2: | |
9351 | case FRV_BUILTIN_MDUNPACKH: | |
9352 | case FRV_BUILTIN_MBTOHE: | |
9353 | if (! TARGET_MEDIA_REV1) | |
9354 | { | |
9355 | error ("this media function is only available on the fr500"); | |
9356 | return NULL_RTX; | |
9357 | } | |
9358 | break; | |
9359 | ||
9360 | case FRV_BUILTIN_MQXMACHS: | |
9361 | case FRV_BUILTIN_MQXMACXHS: | |
9362 | case FRV_BUILTIN_MQMACXHS: | |
9363 | case FRV_BUILTIN_MADDACCS: | |
9364 | case FRV_BUILTIN_MSUBACCS: | |
9365 | case FRV_BUILTIN_MASACCS: | |
9366 | case FRV_BUILTIN_MDADDACCS: | |
9367 | case FRV_BUILTIN_MDSUBACCS: | |
9368 | case FRV_BUILTIN_MDASACCS: | |
9369 | case FRV_BUILTIN_MABSHS: | |
9370 | case FRV_BUILTIN_MDROTLI: | |
9371 | case FRV_BUILTIN_MCPLHI: | |
9372 | case FRV_BUILTIN_MCPLI: | |
9373 | case FRV_BUILTIN_MDCUTSSI: | |
9374 | case FRV_BUILTIN_MQSATHS: | |
9375 | case FRV_BUILTIN_MHSETLOS: | |
9376 | case FRV_BUILTIN_MHSETLOH: | |
9377 | case FRV_BUILTIN_MHSETHIS: | |
9378 | case FRV_BUILTIN_MHSETHIH: | |
9379 | case FRV_BUILTIN_MHDSETS: | |
9380 | case FRV_BUILTIN_MHDSETH: | |
9381 | if (! TARGET_MEDIA_REV2) | |
9382 | { | |
c557edf4 RS |
9383 | error ("this media function is only available on the fr400" |
9384 | " and fr550"); | |
9385 | return NULL_RTX; | |
9386 | } | |
9387 | break; | |
9388 | ||
9389 | case FRV_BUILTIN_SMASS: | |
9390 | case FRV_BUILTIN_SMSSS: | |
9391 | case FRV_BUILTIN_SMU: | |
9392 | case FRV_BUILTIN_ADDSS: | |
9393 | case FRV_BUILTIN_SUBSS: | |
9394 | case FRV_BUILTIN_SLASS: | |
9395 | case FRV_BUILTIN_SCUTSS: | |
9396 | case FRV_BUILTIN_IACCreadll: | |
9397 | case FRV_BUILTIN_IACCreadl: | |
9398 | case FRV_BUILTIN_IACCsetll: | |
9399 | case FRV_BUILTIN_IACCsetl: | |
9400 | if (!TARGET_FR405_BUILTINS) | |
9401 | { | |
9402 | error ("this builtin function is only available" | |
9403 | " on the fr405 and fr450"); | |
9404 | return NULL_RTX; | |
9405 | } | |
9406 | break; | |
9407 | ||
9408 | case FRV_BUILTIN_PREFETCH: | |
9409 | if (!TARGET_FR500_FR550_BUILTINS) | |
9410 | { | |
9411 | error ("this builtin function is only available on the fr500" | |
9412 | " and fr550"); | |
9413 | return NULL_RTX; | |
9414 | } | |
9415 | break; | |
9416 | ||
9417 | case FRV_BUILTIN_MQLCLRHS: | |
9418 | case FRV_BUILTIN_MQLMTHS: | |
9419 | case FRV_BUILTIN_MQSLLHI: | |
9420 | case FRV_BUILTIN_MQSRAHI: | |
9421 | if (!TARGET_MEDIA_FR450) | |
9422 | { | |
9423 | error ("this builtin function is only available on the fr450"); | |
36a05131 BS |
9424 | return NULL_RTX; |
9425 | } | |
9426 | break; | |
9427 | ||
9428 | default: | |
9429 | break; | |
9430 | } | |
9431 | ||
87b483a1 | 9432 | /* Expand unique builtins. */ |
36a05131 BS |
9433 | |
9434 | switch (fcode) | |
9435 | { | |
9436 | case FRV_BUILTIN_MTRAP: | |
9437 | return frv_expand_noargs_builtin (CODE_FOR_mtrap); | |
9438 | ||
9439 | case FRV_BUILTIN_MCLRACC: | |
2396bce1 | 9440 | return frv_expand_mclracc_builtin (exp); |
36a05131 BS |
9441 | |
9442 | case FRV_BUILTIN_MCLRACCA: | |
9443 | if (TARGET_ACC_8) | |
9444 | return frv_expand_noargs_builtin (CODE_FOR_mclracca8); | |
9445 | else | |
9446 | return frv_expand_noargs_builtin (CODE_FOR_mclracca4); | |
9447 | ||
9448 | case FRV_BUILTIN_MRDACC: | |
2396bce1 | 9449 | return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, exp); |
36a05131 BS |
9450 | |
9451 | case FRV_BUILTIN_MRDACCG: | |
2396bce1 | 9452 | return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, exp); |
36a05131 BS |
9453 | |
9454 | case FRV_BUILTIN_MWTACC: | |
2396bce1 | 9455 | return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, exp); |
36a05131 BS |
9456 | |
9457 | case FRV_BUILTIN_MWTACCG: | |
2396bce1 | 9458 | return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, exp); |
36a05131 | 9459 | |
a738d848 | 9460 | case FRV_BUILTIN_MDPACKH: |
2396bce1 | 9461 | return frv_expand_mdpackh_builtin (exp, target); |
a738d848 | 9462 | |
c557edf4 RS |
9463 | case FRV_BUILTIN_IACCreadll: |
9464 | { | |
2396bce1 | 9465 | rtx src = frv_read_iacc_argument (DImode, exp, 0); |
c557edf4 RS |
9466 | if (target == 0 || !REG_P (target)) |
9467 | target = gen_reg_rtx (DImode); | |
9468 | frv_split_iacc_move (target, src); | |
9469 | return target; | |
9470 | } | |
9471 | ||
9472 | case FRV_BUILTIN_IACCreadl: | |
2396bce1 | 9473 | return frv_read_iacc_argument (SImode, exp, 0); |
c557edf4 RS |
9474 | |
9475 | case FRV_BUILTIN_IACCsetll: | |
9476 | { | |
2396bce1 EC |
9477 | rtx dest = frv_read_iacc_argument (DImode, exp, 0); |
9478 | rtx src = frv_read_argument (exp, 1); | |
c557edf4 RS |
9479 | frv_split_iacc_move (dest, force_reg (DImode, src)); |
9480 | return 0; | |
9481 | } | |
9482 | ||
9483 | case FRV_BUILTIN_IACCsetl: | |
9484 | { | |
2396bce1 EC |
9485 | rtx dest = frv_read_iacc_argument (SImode, exp, 0); |
9486 | rtx src = frv_read_argument (exp, 1); | |
c557edf4 RS |
9487 | emit_move_insn (dest, force_reg (SImode, src)); |
9488 | return 0; | |
9489 | } | |
9490 | ||
36a05131 BS |
9491 | default: |
9492 | break; | |
9493 | } | |
9494 | ||
87b483a1 | 9495 | /* Expand groups of builtins. */ |
36a05131 | 9496 | |
e97a46ce | 9497 | for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++) |
36a05131 | 9498 | if (d->code == fcode) |
2396bce1 | 9499 | return frv_expand_set_builtin (d->icode, exp, target); |
36a05131 | 9500 | |
e97a46ce | 9501 | for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
36a05131 | 9502 | if (d->code == fcode) |
2396bce1 | 9503 | return frv_expand_unop_builtin (d->icode, exp, target); |
36a05131 | 9504 | |
e97a46ce | 9505 | for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
36a05131 | 9506 | if (d->code == fcode) |
2396bce1 | 9507 | return frv_expand_binop_builtin (d->icode, exp, target); |
36a05131 | 9508 | |
e97a46ce | 9509 | for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++) |
36a05131 | 9510 | if (d->code == fcode) |
2396bce1 | 9511 | return frv_expand_cut_builtin (d->icode, exp, target); |
36a05131 | 9512 | |
e97a46ce KG |
9513 | for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++) |
9514 | if (d->code == fcode) | |
2396bce1 | 9515 | return frv_expand_binopimm_builtin (d->icode, exp, target); |
36a05131 | 9516 | |
e97a46ce KG |
9517 | for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++) |
9518 | if (d->code == fcode) | |
2396bce1 | 9519 | return frv_expand_voidbinop_builtin (d->icode, exp); |
36a05131 | 9520 | |
e97a46ce KG |
9521 | for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++) |
9522 | if (d->code == fcode) | |
2396bce1 | 9523 | return frv_expand_voidtriop_builtin (d->icode, exp); |
e97a46ce KG |
9524 | |
9525 | for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++) | |
9526 | if (d->code == fcode) | |
2396bce1 | 9527 | return frv_expand_voidaccop_builtin (d->icode, exp); |
36a05131 | 9528 | |
c557edf4 RS |
9529 | for (i = 0, d = bdesc_int_void2arg; |
9530 | i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++) | |
9531 | if (d->code == fcode) | |
2396bce1 | 9532 | return frv_expand_int_void2arg (d->icode, exp); |
c557edf4 RS |
9533 | |
9534 | for (i = 0, d = bdesc_prefetches; | |
9535 | i < ARRAY_SIZE (bdesc_prefetches); i++, d++) | |
9536 | if (d->code == fcode) | |
2396bce1 | 9537 | return frv_expand_prefetches (d->icode, exp); |
c557edf4 | 9538 | |
c14ff86e AH |
9539 | for (i = 0, d = bdesc_loads; i < ARRAY_SIZE (bdesc_loads); i++, d++) |
9540 | if (d->code == fcode) | |
38c28a25 | 9541 | return frv_expand_load_builtin (d->icode, TYPE_MODE (TREE_TYPE (exp)), |
2396bce1 | 9542 | exp, target); |
c14ff86e AH |
9543 | |
9544 | for (i = 0, d = bdesc_stores; i < ARRAY_SIZE (bdesc_stores); i++, d++) | |
9545 | if (d->code == fcode) | |
2396bce1 | 9546 | return frv_expand_store_builtin (d->icode, exp); |
c14ff86e | 9547 | |
36a05131 BS |
9548 | return 0; |
9549 | } | |
14966b94 | 9550 | |
b3fbfc07 | 9551 | static bool |
3101faab | 9552 | frv_in_small_data_p (const_tree decl) |
b3fbfc07 | 9553 | { |
0f6e5d45 | 9554 | HOST_WIDE_INT size; |
3101faab | 9555 | const_tree section_name; |
0f6e5d45 RH |
9556 | |
9557 | /* Don't apply the -G flag to internal compiler structures. We | |
9558 | should leave such structures in the main data section, partly | |
9559 | for efficiency and partly because the size of some of them | |
9560 | (such as C++ typeinfos) is not known until later. */ | |
9561 | if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl)) | |
9562 | return false; | |
9563 | ||
0f6e5d45 RH |
9564 | /* If we already know which section the decl should be in, see if |
9565 | it's a small data section. */ | |
9566 | section_name = DECL_SECTION_NAME (decl); | |
9567 | if (section_name) | |
9568 | { | |
44e91694 | 9569 | gcc_assert (TREE_CODE (section_name) == STRING_CST); |
0f6e5d45 RH |
9570 | if (frv_string_begins_with (section_name, ".sdata")) |
9571 | return true; | |
9572 | if (frv_string_begins_with (section_name, ".sbss")) | |
9573 | return true; | |
68c0ab4f | 9574 | return false; |
0f6e5d45 | 9575 | } |
b3fbfc07 | 9576 | |
68c0ab4f | 9577 | size = int_size_in_bytes (TREE_TYPE (decl)); |
fa37ed29 | 9578 | if (size > 0 && size <= g_switch_value) |
68c0ab4f RS |
9579 | return true; |
9580 | ||
0f6e5d45 | 9581 | return false; |
b3fbfc07 | 9582 | } |
3c50106f RH |
9583 | \f |
9584 | static bool | |
f2206911 KC |
9585 | frv_rtx_costs (rtx x, |
9586 | int code ATTRIBUTE_UNUSED, | |
9587 | int outer_code ATTRIBUTE_UNUSED, | |
f40751dd JH |
9588 | int *total, |
9589 | bool speed ATTRIBUTE_UNUSED) | |
3c50106f | 9590 | { |
34208acf AO |
9591 | if (outer_code == MEM) |
9592 | { | |
9593 | /* Don't differentiate between memory addresses. All the ones | |
9594 | we accept have equal cost. */ | |
9595 | *total = COSTS_N_INSNS (0); | |
9596 | return true; | |
9597 | } | |
9598 | ||
3c50106f RH |
9599 | switch (code) |
9600 | { | |
9601 | case CONST_INT: | |
2300b9dd | 9602 | /* Make 12-bit integers really cheap. */ |
3c50106f RH |
9603 | if (IN_RANGE_P (INTVAL (x), -2048, 2047)) |
9604 | { | |
9605 | *total = 0; | |
9606 | return true; | |
9607 | } | |
87b483a1 | 9608 | /* Fall through. */ |
3c50106f RH |
9609 | |
9610 | case CONST: | |
9611 | case LABEL_REF: | |
9612 | case SYMBOL_REF: | |
9613 | case CONST_DOUBLE: | |
9614 | *total = COSTS_N_INSNS (2); | |
9615 | return true; | |
9616 | ||
9617 | case PLUS: | |
9618 | case MINUS: | |
9619 | case AND: | |
9620 | case IOR: | |
9621 | case XOR: | |
9622 | case ASHIFT: | |
9623 | case ASHIFTRT: | |
9624 | case LSHIFTRT: | |
9625 | case NOT: | |
9626 | case NEG: | |
9627 | case COMPARE: | |
9628 | if (GET_MODE (x) == SImode) | |
9629 | *total = COSTS_N_INSNS (1); | |
9630 | else if (GET_MODE (x) == DImode) | |
9631 | *total = COSTS_N_INSNS (2); | |
9632 | else | |
9633 | *total = COSTS_N_INSNS (3); | |
9634 | return true; | |
9635 | ||
9636 | case MULT: | |
9637 | if (GET_MODE (x) == SImode) | |
9638 | *total = COSTS_N_INSNS (2); | |
9639 | else | |
9640 | *total = COSTS_N_INSNS (6); /* guess */ | |
9641 | return true; | |
9642 | ||
9643 | case DIV: | |
9644 | case UDIV: | |
9645 | case MOD: | |
9646 | case UMOD: | |
9647 | *total = COSTS_N_INSNS (18); | |
9648 | return true; | |
9649 | ||
34208acf AO |
9650 | case MEM: |
9651 | *total = COSTS_N_INSNS (3); | |
9652 | return true; | |
9653 | ||
3c50106f RH |
9654 | default: |
9655 | return false; | |
9656 | } | |
9657 | } | |
90a63880 RH |
9658 | \f |
9659 | static void | |
f2206911 | 9660 | frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED) |
90a63880 | 9661 | { |
d6b5193b | 9662 | switch_to_section (ctors_section); |
90a63880 | 9663 | assemble_align (POINTER_SIZE); |
34208acf AO |
9664 | if (TARGET_FDPIC) |
9665 | { | |
44e91694 NS |
9666 | int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1); |
9667 | ||
9668 | gcc_assert (ok); | |
34208acf AO |
9669 | return; |
9670 | } | |
90a63880 RH |
9671 | assemble_integer_with_op ("\t.picptr\t", symbol); |
9672 | } | |
9673 | ||
9674 | static void | |
f2206911 | 9675 | frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED) |
90a63880 | 9676 | { |
d6b5193b | 9677 | switch_to_section (dtors_section); |
90a63880 | 9678 | assemble_align (POINTER_SIZE); |
34208acf AO |
9679 | if (TARGET_FDPIC) |
9680 | { | |
44e91694 | 9681 | int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1); |
2396bce1 | 9682 | |
44e91694 | 9683 | gcc_assert (ok); |
34208acf AO |
9684 | return; |
9685 | } | |
90a63880 RH |
9686 | assemble_integer_with_op ("\t.picptr\t", symbol); |
9687 | } | |
8ac411c7 KH |
9688 | |
9689 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ | |
9690 | ||
9691 | static rtx | |
9692 | frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
9693 | int incoming ATTRIBUTE_UNUSED) | |
9694 | { | |
9695 | return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM); | |
9696 | } | |
c557edf4 | 9697 | |
bef8809e AH |
9698 | #define TLS_BIAS (2048 - 16) |
9699 | ||
fdbe66f2 | 9700 | /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. |
bef8809e AH |
9701 | We need to emit DTP-relative relocations. */ |
9702 | ||
fdbe66f2 | 9703 | static void |
bef8809e AH |
9704 | frv_output_dwarf_dtprel (FILE *file, int size, rtx x) |
9705 | { | |
44e91694 | 9706 | gcc_assert (size == 4); |
bef8809e AH |
9707 | fputs ("\t.picptr\ttlsmoff(", file); |
9708 | /* We want the unbiased TLS offset, so add the bias to the | |
9709 | expression, such that the implicit biasing cancels out. */ | |
9710 | output_addr_const (file, plus_constant (x, TLS_BIAS)); | |
9711 | fputs (")", file); | |
9712 | } | |
9713 | ||
c557edf4 | 9714 | #include "gt-frv.h" |