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36a05131 | 1 | /* Target macros for the FRV port of GCC. |
7adcbafe | 2 | Copyright (C) 1999-2022 Free Software Foundation, Inc. |
36a05131 BS |
3 | Contributed by Red Hat Inc. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it | |
8 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | by the Free Software Foundation; either version 3, or (at your |
36a05131 BS |
10 | option) any later version. |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
36a05131 BS |
20 | |
21 | #ifndef __FRV_H__ | |
22 | #define __FRV_H__ | |
23 | ||
36a05131 BS |
24 | /* Frv general purpose macros. */ |
25 | /* Align an address. */ | |
26 | #define ADDR_ALIGN(addr,align) (((addr) + (align) - 1) & ~((align) - 1)) | |
36a05131 BS |
27 | \f |
28 | /* Driver configuration. */ | |
29 | ||
34208acf AO |
30 | /* -fpic and -fPIC used to imply the -mlibrary-pic multilib, but with |
31 | FDPIC which multilib to use depends on whether FDPIC is in use or | |
32 | not. The trick we use is to introduce -multilib-library-pic as a | |
33 | pseudo-flag that selects the library-pic multilib, and map fpic | |
34 | and fPIC to it only if fdpic is not selected. Also, if fdpic is | |
35 | selected and no PIC/PIE options are present, we imply -fPIE. | |
36 | Otherwise, if -fpic or -fPIC are enabled and we're optimizing for | |
37 | speed, or if we have -On with n>=3, enable inlining of PLTs. As | |
38 | for -mgprel-ro, we want to enable it by default, but not for -fpic or | |
39 | -fpie. */ | |
40 | ||
41 | #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS \ | |
42 | "%{mno-pack:\ | |
43 | %{!mhard-float:-msoft-float}\ | |
44 | %{!mmedia:-mno-media}}\ | |
428b3812 | 45 | %{!mfdpic:%{" FPIC_SPEC ": -multilib-library-pic}}\ |
34208acf AO |
46 | %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\ |
47 | %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fPIE}}}}}}}} \ | |
428b3812 L |
48 | %{!mno-inline-plt:%{O*:%{!O0:%{!Os:%{" FPIC_SPEC ":-minline-plt} \ |
49 | %{" NO_FPIC_SPEC ":%{!O:%{!O1:%{!O2:-minline-plt}}}}}}}} \ | |
50 | %{!mno-gprel-ro:%{" NO_FPIE1_AND_FPIC1_SPEC ":-mgprel-ro}}} \ | |
34208acf AO |
51 | " |
52 | #ifndef SUBTARGET_DRIVER_SELF_SPECS | |
53 | # define SUBTARGET_DRIVER_SELF_SPECS | |
54 | #endif | |
55 | ||
36a05131 BS |
56 | #undef ASM_SPEC |
57 | #define ASM_SPEC "\ | |
d3153553 | 58 | %{G*} \ |
36a05131 BS |
59 | %{mtomcat-stats} \ |
60 | %{!mno-eflags: \ | |
61 | %{mcpu=*} \ | |
62 | %{mgpr-*} %{mfpr-*} \ | |
63 | %{msoft-float} %{mhard-float} \ | |
64 | %{mdword} %{mno-dword} \ | |
65 | %{mdouble} %{mno-double} \ | |
66 | %{mmedia} %{mno-media} \ | |
67 | %{mmuladd} %{mno-muladd} \ | |
68 | %{mpack} %{mno-pack} \ | |
afbe7e61 | 69 | %{mno-fdpic:-mnopic} %{mfdpic} \ |
428b3812 | 70 | %{" FPIE1_OR_FPIC1_SPEC ":-mpic} %{" FPIE2_OR_FPIC2_SPEC ":-mPIC} %{mlibrary-pic}}" |
36a05131 | 71 | |
36a05131 BS |
72 | #undef STARTFILE_SPEC |
73 | #define STARTFILE_SPEC "crt0%O%s frvbegin%O%s" | |
74 | ||
36a05131 BS |
75 | #undef ENDFILE_SPEC |
76 | #define ENDFILE_SPEC "frvend%O%s" | |
77 | ||
36a05131 BS |
78 | |
79 | #define MASK_DEFAULT_FRV \ | |
80 | (MASK_MEDIA \ | |
81 | | MASK_DOUBLE \ | |
82 | | MASK_MULADD \ | |
83 | | MASK_DWORD \ | |
84 | | MASK_PACK) | |
85 | ||
86 | #define MASK_DEFAULT_FR500 \ | |
87 | (MASK_MEDIA | MASK_DWORD | MASK_PACK) | |
88 | ||
c557edf4 RS |
89 | #define MASK_DEFAULT_FR550 \ |
90 | (MASK_MEDIA | MASK_DWORD | MASK_PACK) | |
91 | ||
92 | #define MASK_DEFAULT_FR450 \ | |
93 | (MASK_GPR_32 \ | |
94 | | MASK_FPR_32 \ | |
95 | | MASK_MEDIA \ | |
96 | | MASK_SOFT_FLOAT \ | |
97 | | MASK_DWORD \ | |
98 | | MASK_PACK) | |
99 | ||
36a05131 BS |
100 | #define MASK_DEFAULT_FR400 \ |
101 | (MASK_GPR_32 \ | |
102 | | MASK_FPR_32 \ | |
103 | | MASK_MEDIA \ | |
104 | | MASK_ACC_4 \ | |
105 | | MASK_SOFT_FLOAT \ | |
106 | | MASK_DWORD \ | |
107 | | MASK_PACK) | |
108 | ||
109 | #define MASK_DEFAULT_SIMPLE \ | |
110 | (MASK_GPR_32 | MASK_SOFT_FLOAT) | |
111 | ||
7ec022b2 KC |
112 | /* A C string constant that tells the GCC driver program options to pass to |
113 | `cc1'. It can also specify how to translate options you give to GCC into | |
114 | options for GCC to pass to the `cc1'. | |
36a05131 BS |
115 | |
116 | Do not define this macro if it does not need to do anything. */ | |
117 | /* For ABI compliance, we need to put bss data into the normal data section. */ | |
118 | #define CC1_SPEC "%{G*}" | |
119 | ||
36a05131 BS |
120 | #undef LINK_SPEC |
121 | #define LINK_SPEC "\ | |
122 | %{h*} %{v:-V} \ | |
34208acf | 123 | %{mfdpic:-melf32frvfd -z text} \ |
36a05131 BS |
124 | %{static:-dn -Bstatic} \ |
125 | %{shared:-Bdynamic} \ | |
126 | %{symbolic:-Bsymbolic} \ | |
c75d884b | 127 | %{G*}" |
36a05131 | 128 | |
36a05131 BS |
129 | #undef LIB_SPEC |
130 | #define LIB_SPEC "--start-group -lc -lsim --end-group" | |
131 | ||
c557edf4 | 132 | #ifndef CPU_TYPE |
36a05131 BS |
133 | #define CPU_TYPE FRV_CPU_FR500 |
134 | #endif | |
135 | ||
36a05131 BS |
136 | /* Run-time target specifications */ |
137 | ||
c557edf4 RS |
138 | #define TARGET_CPU_CPP_BUILTINS() \ |
139 | do \ | |
140 | { \ | |
141 | int issue_rate; \ | |
142 | \ | |
143 | builtin_define ("__frv__"); \ | |
144 | builtin_assert ("machine=frv"); \ | |
145 | \ | |
146 | issue_rate = frv_issue_rate (); \ | |
147 | if (issue_rate > 1) \ | |
148 | builtin_define_with_int_value ("__FRV_VLIW__", issue_rate); \ | |
149 | builtin_define_with_int_value ("__FRV_GPR__", NUM_GPRS); \ | |
150 | builtin_define_with_int_value ("__FRV_FPR__", NUM_FPRS); \ | |
151 | builtin_define_with_int_value ("__FRV_ACC__", NUM_ACCS); \ | |
152 | \ | |
153 | switch (frv_cpu_type) \ | |
154 | { \ | |
155 | case FRV_CPU_GENERIC: \ | |
156 | builtin_define ("__CPU_GENERIC__"); \ | |
157 | break; \ | |
158 | case FRV_CPU_FR550: \ | |
159 | builtin_define ("__CPU_FR550__"); \ | |
160 | break; \ | |
161 | case FRV_CPU_FR500: \ | |
162 | case FRV_CPU_TOMCAT: \ | |
163 | builtin_define ("__CPU_FR500__"); \ | |
164 | break; \ | |
165 | case FRV_CPU_FR450: \ | |
166 | builtin_define ("__CPU_FR450__"); \ | |
167 | break; \ | |
168 | case FRV_CPU_FR405: \ | |
169 | builtin_define ("__CPU_FR405__"); \ | |
170 | break; \ | |
171 | case FRV_CPU_FR400: \ | |
172 | builtin_define ("__CPU_FR400__"); \ | |
173 | break; \ | |
174 | case FRV_CPU_FR300: \ | |
175 | case FRV_CPU_SIMPLE: \ | |
176 | builtin_define ("__CPU_FR300__"); \ | |
177 | break; \ | |
178 | } \ | |
179 | \ | |
180 | if (TARGET_HARD_FLOAT) \ | |
181 | builtin_define ("__FRV_HARD_FLOAT__"); \ | |
182 | if (TARGET_DWORD) \ | |
183 | builtin_define ("__FRV_DWORD__"); \ | |
184 | if (TARGET_FDPIC) \ | |
185 | builtin_define ("__FRV_FDPIC__"); \ | |
186 | if (flag_leading_underscore > 0) \ | |
187 | builtin_define ("__FRV_UNDERSCORE__"); \ | |
188 | } \ | |
cc956ba2 | 189 | while (0) |
36a05131 BS |
190 | |
191 | \f | |
36a05131 BS |
192 | #define TARGET_HAS_FPRS (TARGET_HARD_FLOAT || TARGET_MEDIA) |
193 | ||
194 | #define NUM_GPRS (TARGET_GPR_32? 32 : 64) | |
195 | #define NUM_FPRS (!TARGET_HAS_FPRS? 0 : TARGET_FPR_32? 32 : 64) | |
196 | #define NUM_ACCS (!TARGET_MEDIA? 0 : TARGET_ACC_4? 4 : 8) | |
197 | ||
c557edf4 RS |
198 | /* X is a valid accumulator number if (X & ACC_MASK) == X. */ |
199 | #define ACC_MASK \ | |
200 | (!TARGET_MEDIA ? 0 \ | |
201 | : TARGET_ACC_4 ? 3 \ | |
202 | : frv_cpu_type == FRV_CPU_FR450 ? 11 \ | |
203 | : 7) | |
204 | ||
36a05131 BS |
205 | /* Macros to identify the blend of media instructions available. Revision 1 |
206 | is the one found on the FR500. Revision 2 includes the changes made for | |
207 | the FR400. | |
208 | ||
209 | Treat the generic processor as a revision 1 machine for now, for | |
210 | compatibility with earlier releases. */ | |
211 | ||
212 | #define TARGET_MEDIA_REV1 \ | |
213 | (TARGET_MEDIA \ | |
214 | && (frv_cpu_type == FRV_CPU_GENERIC \ | |
215 | || frv_cpu_type == FRV_CPU_FR500)) | |
216 | ||
217 | #define TARGET_MEDIA_REV2 \ | |
c557edf4 RS |
218 | (TARGET_MEDIA \ |
219 | && (frv_cpu_type == FRV_CPU_FR400 \ | |
220 | || frv_cpu_type == FRV_CPU_FR405 \ | |
221 | || frv_cpu_type == FRV_CPU_FR450 \ | |
222 | || frv_cpu_type == FRV_CPU_FR550)) | |
223 | ||
224 | #define TARGET_MEDIA_FR450 \ | |
225 | (frv_cpu_type == FRV_CPU_FR450) | |
226 | ||
227 | #define TARGET_FR500_FR550_BUILTINS \ | |
228 | (frv_cpu_type == FRV_CPU_FR500 \ | |
229 | || frv_cpu_type == FRV_CPU_FR550) | |
230 | ||
231 | #define TARGET_FR405_BUILTINS \ | |
232 | (frv_cpu_type == FRV_CPU_FR405 \ | |
233 | || frv_cpu_type == FRV_CPU_FR450) | |
36a05131 | 234 | |
bef8809e AH |
235 | #ifndef HAVE_AS_TLS |
236 | #define HAVE_AS_TLS 0 | |
237 | #endif | |
238 | ||
c557edf4 | 239 | #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (TARGET_ALIGN_LABELS ? 3 : 0) |
36a05131 BS |
240 | \f |
241 | /* Small Data Area Support. */ | |
242 | /* Maximum size of variables that go in .sdata/.sbss. | |
243 | The -msdata=foo switch also controls how small variables are handled. */ | |
244 | #ifndef SDATA_DEFAULT_SIZE | |
245 | #define SDATA_DEFAULT_SIZE 8 | |
246 | #endif | |
247 | ||
36a05131 BS |
248 | |
249 | /* Storage Layout */ | |
250 | ||
251 | /* Define this macro to have the value 1 if the most significant bit in a byte | |
252 | has the lowest number; otherwise define it to have the value zero. This | |
253 | means that bit-field instructions count from the most significant bit. If | |
254 | the machine has no bit-field instructions, then this must still be defined, | |
255 | but it doesn't matter which value it is defined to. This macro need not be | |
256 | a constant. | |
257 | ||
258 | This macro does not affect the way structure fields are packed into bytes or | |
259 | words; that is controlled by `BYTES_BIG_ENDIAN'. */ | |
260 | #define BITS_BIG_ENDIAN 1 | |
261 | ||
262 | /* Define this macro to have the value 1 if the most significant byte in a word | |
263 | has the lowest number. This macro need not be a constant. */ | |
264 | #define BYTES_BIG_ENDIAN 1 | |
265 | ||
266 | /* Define this macro to have the value 1 if, in a multiword object, the most | |
267 | significant word has the lowest number. This applies to both memory | |
7ec022b2 | 268 | locations and registers; GCC fundamentally assumes that the order of |
36a05131 BS |
269 | words in memory is the same as the order in registers. This macro need not |
270 | be a constant. */ | |
271 | #define WORDS_BIG_ENDIAN 1 | |
272 | ||
273 | /* Number of storage units in a word; normally 4. */ | |
274 | #define UNITS_PER_WORD 4 | |
275 | ||
276 | /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and | |
277 | which has the specified mode and signedness is to be stored in a register. | |
278 | This macro is only called when TYPE is a scalar type. | |
279 | ||
280 | On most RISC machines, which only have operations that operate on a full | |
281 | register, define this macro to set M to `word_mode' if M is an integer mode | |
282 | narrower than `BITS_PER_WORD'. In most cases, only integer modes should be | |
283 | widened because wider-precision floating-point operations are usually more | |
284 | expensive than their narrower counterparts. | |
285 | ||
286 | For most machines, the macro definition does not change UNSIGNEDP. However, | |
287 | some machines, have instructions that preferentially handle either signed or | |
288 | unsigned quantities of certain modes. For example, on the DEC Alpha, 32-bit | |
289 | loads from memory and 32-bit add instructions sign-extend the result to 64 | |
290 | bits. On such machines, set UNSIGNEDP according to which kind of extension | |
291 | is more efficient. | |
292 | ||
293 | Do not define this macro if it would never modify MODE. */ | |
294 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
295 | do \ | |
296 | { \ | |
297 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
298 | && GET_MODE_SIZE (MODE) < 4) \ | |
299 | (MODE) = SImode; \ | |
300 | } \ | |
301 | while (0) | |
302 | ||
303 | /* Normal alignment required for function parameters on the stack, in bits. | |
304 | All stack parameters receive at least this much alignment regardless of data | |
305 | type. On most machines, this is the same as the size of an integer. */ | |
306 | #define PARM_BOUNDARY 32 | |
307 | ||
308 | /* Define this macro if you wish to preserve a certain alignment for the stack | |
309 | pointer. The definition is a C expression for the desired alignment | |
310 | (measured in bits). | |
311 | ||
312 | If `PUSH_ROUNDING' is not defined, the stack will always be aligned to the | |
313 | specified boundary. If `PUSH_ROUNDING' is defined and specifies a less | |
314 | strict alignment than `STACK_BOUNDARY', the stack may be momentarily | |
315 | unaligned while pushing arguments. */ | |
316 | #define STACK_BOUNDARY 64 | |
317 | ||
318 | /* Alignment required for a function entry point, in bits. */ | |
319 | #define FUNCTION_BOUNDARY 128 | |
320 | ||
321 | /* Biggest alignment that any data type can require on this machine, | |
322 | in bits. */ | |
323 | #define BIGGEST_ALIGNMENT 64 | |
324 | ||
325 | /* @@@ A hack, needed because libobjc wants to use ADJUST_FIELD_ALIGN for | |
326 | some reason. */ | |
327 | #ifdef IN_TARGET_LIBS | |
328 | #define BIGGEST_FIELD_ALIGNMENT 64 | |
329 | #else | |
330 | /* An expression for the alignment of a structure field FIELD if the | |
7ec022b2 | 331 | alignment computed in the usual way is COMPUTED. GCC uses this |
36a05131 BS |
332 | value instead of the value in `BIGGEST_ALIGNMENT' or |
333 | `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */ | |
a4cf4b64 | 334 | #define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \ |
36a05131 BS |
335 | frv_adjust_field_align (FIELD, COMPUTED) |
336 | #endif | |
337 | ||
338 | /* If defined, a C expression to compute the alignment for a static variable. | |
339 | TYPE is the data type, and ALIGN is the alignment that the object | |
340 | would ordinarily have. The value of this macro is used instead of that | |
341 | alignment to align the object. | |
342 | ||
343 | If this macro is not defined, then ALIGN is used. | |
344 | ||
345 | One use of this macro is to increase alignment of medium-size data to make | |
346 | it all fit in fewer cache lines. Another is to cause character arrays to be | |
347 | word-aligned so that `strcpy' calls that copy constants to character arrays | |
348 | can be done inline. */ | |
349 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
350 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
351 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
352 | && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
353 | ||
36a05131 BS |
354 | /* Define this macro to be the value 1 if instructions will fail to work if |
355 | given data not on the nominal alignment. If instructions will merely go | |
356 | slower in that case, define this macro as 0. */ | |
357 | #define STRICT_ALIGNMENT 1 | |
358 | ||
36a05131 BS |
359 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
360 | ||
36a05131 BS |
361 | \f |
362 | /* Layout of Source Language Data Types. */ | |
363 | ||
364 | #define CHAR_TYPE_SIZE 8 | |
365 | #define SHORT_TYPE_SIZE 16 | |
366 | #define INT_TYPE_SIZE 32 | |
367 | #define LONG_TYPE_SIZE 32 | |
368 | #define LONG_LONG_TYPE_SIZE 64 | |
369 | #define FLOAT_TYPE_SIZE 32 | |
370 | #define DOUBLE_TYPE_SIZE 64 | |
371 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
372 | ||
373 | /* An expression whose value is 1 or 0, according to whether the type `char' | |
374 | should be signed or unsigned by default. The user can always override this | |
375 | default with the options `-fsigned-char' and `-funsigned-char'. */ | |
376 | #define DEFAULT_SIGNED_CHAR 1 | |
377 | ||
a3724010 JM |
378 | #undef SIZE_TYPE |
379 | #define SIZE_TYPE "unsigned int" | |
380 | ||
381 | #undef PTRDIFF_TYPE | |
382 | #define PTRDIFF_TYPE "int" | |
383 | ||
384 | #undef WCHAR_TYPE | |
385 | #define WCHAR_TYPE "long int" | |
386 | ||
387 | #undef WCHAR_TYPE_SIZE | |
388 | #define WCHAR_TYPE_SIZE BITS_PER_WORD | |
389 | ||
36a05131 BS |
390 | \f |
391 | /* General purpose registers. */ | |
392 | #define GPR_FIRST 0 /* First gpr */ | |
393 | #define GPR_LAST (GPR_FIRST + 63) /* Last gpr */ | |
394 | #define GPR_R0 GPR_FIRST /* R0, constant 0 */ | |
395 | #define GPR_FP (GPR_FIRST + 2) /* Frame pointer */ | |
396 | #define GPR_SP (GPR_FIRST + 1) /* Stack pointer */ | |
397 | /* small data register */ | |
34208acf AO |
398 | #define SDA_BASE_REG ((unsigned)(TARGET_FDPIC ? -1 : flag_pic ? PIC_REGNO : (GPR_FIRST + 16))) |
399 | #define PIC_REGNO (GPR_FIRST + (TARGET_FDPIC?15:17)) /* PIC register. */ | |
400 | #define FDPIC_FPTR_REGNO (GPR_FIRST + 14) /* uClinux PIC function pointer register. */ | |
401 | #define FDPIC_REGNO (GPR_FIRST + 15) /* uClinux PIC register. */ | |
402 | ||
b8a19ec4 NC |
403 | #define HARD_REGNO_RENAME_OK(from,to) (TARGET_FDPIC ? ((to) != FDPIC_REG) : 1) |
404 | ||
34208acf | 405 | #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO) |
36a05131 BS |
406 | |
407 | #define FPR_FIRST 64 /* First FP reg */ | |
408 | #define FPR_LAST 127 /* Last FP reg */ | |
409 | ||
36a05131 BS |
410 | #define GPR_TEMP_NUM frv_condexec_temps /* # gprs to reserve for temps */ |
411 | ||
412 | /* We reserve the last CR and CCR in each category to be used as a reload | |
413 | register to reload the CR/CCR registers. This is a kludge. */ | |
414 | #define CC_FIRST 128 /* First ICC/FCC reg */ | |
415 | #define CC_LAST 135 /* Last ICC/FCC reg */ | |
416 | #define ICC_FIRST (CC_FIRST + 4) /* First ICC reg */ | |
417 | #define ICC_LAST (CC_FIRST + 7) /* Last ICC reg */ | |
418 | #define ICC_TEMP (CC_FIRST + 7) /* Temporary ICC reg */ | |
419 | #define FCC_FIRST (CC_FIRST) /* First FCC reg */ | |
420 | #define FCC_LAST (CC_FIRST + 3) /* Last FCC reg */ | |
421 | ||
422 | /* Amount to shift a value to locate a ICC or FCC register in the CCR | |
423 | register and shift it to the bottom 4 bits. */ | |
424 | #define CC_SHIFT_RIGHT(REGNO) (((REGNO) - CC_FIRST) << 2) | |
425 | ||
426 | /* Mask to isolate a single ICC/FCC value. */ | |
427 | #define CC_MASK 0xf | |
428 | ||
429 | /* Masks to isolate the various bits in an ICC field. */ | |
430 | #define ICC_MASK_N 0x8 /* negative */ | |
431 | #define ICC_MASK_Z 0x4 /* zero */ | |
432 | #define ICC_MASK_V 0x2 /* overflow */ | |
433 | #define ICC_MASK_C 0x1 /* carry */ | |
434 | ||
435 | /* Mask to isolate the N/Z flags in an ICC. */ | |
436 | #define ICC_MASK_NZ (ICC_MASK_N | ICC_MASK_Z) | |
437 | ||
438 | /* Mask to isolate the Z/C flags in an ICC. */ | |
439 | #define ICC_MASK_ZC (ICC_MASK_Z | ICC_MASK_C) | |
440 | ||
441 | /* Masks to isolate the various bits in a FCC field. */ | |
442 | #define FCC_MASK_E 0x8 /* equal */ | |
443 | #define FCC_MASK_L 0x4 /* less than */ | |
444 | #define FCC_MASK_G 0x2 /* greater than */ | |
445 | #define FCC_MASK_U 0x1 /* unordered */ | |
446 | ||
447 | /* For CCR registers, the machine wants CR4..CR7 to be used for integer | |
448 | code and CR0..CR3 to be used for floating point. */ | |
449 | #define CR_FIRST 136 /* First CCR */ | |
450 | #define CR_LAST 143 /* Last CCR */ | |
451 | #define CR_NUM (CR_LAST-CR_FIRST+1) /* # of CCRs (8) */ | |
452 | #define ICR_FIRST (CR_FIRST + 4) /* First integer CCR */ | |
453 | #define ICR_LAST (CR_FIRST + 7) /* Last integer CCR */ | |
454 | #define ICR_TEMP ICR_LAST /* Temp integer CCR */ | |
455 | #define FCR_FIRST (CR_FIRST + 0) /* First float CCR */ | |
456 | #define FCR_LAST (CR_FIRST + 3) /* Last float CCR */ | |
457 | ||
458 | /* Amount to shift a value to locate a CR register in the CCCR special purpose | |
459 | register and shift it to the bottom 2 bits. */ | |
460 | #define CR_SHIFT_RIGHT(REGNO) (((REGNO) - CR_FIRST) << 1) | |
461 | ||
462 | /* Mask to isolate a single CR value. */ | |
463 | #define CR_MASK 0x3 | |
464 | ||
465 | #define ACC_FIRST 144 /* First acc register */ | |
c557edf4 | 466 | #define ACC_LAST 155 /* Last acc register */ |
36a05131 | 467 | |
c557edf4 RS |
468 | #define ACCG_FIRST 156 /* First accg register */ |
469 | #define ACCG_LAST 167 /* Last accg register */ | |
36a05131 | 470 | |
c557edf4 | 471 | #define AP_FIRST 168 /* fake argument pointer */ |
36a05131 | 472 | |
c557edf4 RS |
473 | #define SPR_FIRST 169 |
474 | #define SPR_LAST 172 | |
36a05131 BS |
475 | #define LR_REGNO (SPR_FIRST) |
476 | #define LCR_REGNO (SPR_FIRST + 1) | |
c557edf4 RS |
477 | #define IACC_FIRST (SPR_FIRST + 2) |
478 | #define IACC_LAST (SPR_FIRST + 3) | |
36a05131 | 479 | |
2f5b1308 | 480 | #define GPR_P(R) IN_RANGE (R, GPR_FIRST, GPR_LAST) |
36a05131 | 481 | #define GPR_OR_AP_P(R) (GPR_P (R) || (R) == ARG_POINTER_REGNUM) |
2f5b1308 JR |
482 | #define FPR_P(R) IN_RANGE (R, FPR_FIRST, FPR_LAST) |
483 | #define CC_P(R) IN_RANGE (R, CC_FIRST, CC_LAST) | |
484 | #define ICC_P(R) IN_RANGE (R, ICC_FIRST, ICC_LAST) | |
485 | #define FCC_P(R) IN_RANGE (R, FCC_FIRST, FCC_LAST) | |
486 | #define CR_P(R) IN_RANGE (R, CR_FIRST, CR_LAST) | |
487 | #define ICR_P(R) IN_RANGE (R, ICR_FIRST, ICR_LAST) | |
488 | #define FCR_P(R) IN_RANGE (R, FCR_FIRST, FCR_LAST) | |
489 | #define ACC_P(R) IN_RANGE (R, ACC_FIRST, ACC_LAST) | |
490 | #define ACCG_P(R) IN_RANGE (R, ACCG_FIRST, ACCG_LAST) | |
491 | #define SPR_P(R) IN_RANGE (R, SPR_FIRST, SPR_LAST) | |
36a05131 BS |
492 | |
493 | #define GPR_OR_PSEUDO_P(R) (GPR_P (R) || (R) >= FIRST_PSEUDO_REGISTER) | |
494 | #define FPR_OR_PSEUDO_P(R) (FPR_P (R) || (R) >= FIRST_PSEUDO_REGISTER) | |
495 | #define GPR_AP_OR_PSEUDO_P(R) (GPR_OR_AP_P (R) || (R) >= FIRST_PSEUDO_REGISTER) | |
496 | #define CC_OR_PSEUDO_P(R) (CC_P (R) || (R) >= FIRST_PSEUDO_REGISTER) | |
497 | #define ICC_OR_PSEUDO_P(R) (ICC_P (R) || (R) >= FIRST_PSEUDO_REGISTER) | |
498 | #define FCC_OR_PSEUDO_P(R) (FCC_P (R) || (R) >= FIRST_PSEUDO_REGISTER) | |
499 | #define CR_OR_PSEUDO_P(R) (CR_P (R) || (R) >= FIRST_PSEUDO_REGISTER) | |
500 | #define ICR_OR_PSEUDO_P(R) (ICR_P (R) || (R) >= FIRST_PSEUDO_REGISTER) | |
501 | #define FCR_OR_PSEUDO_P(R) (FCR_P (R) || (R) >= FIRST_PSEUDO_REGISTER) | |
502 | #define ACC_OR_PSEUDO_P(R) (ACC_P (R) || (R) >= FIRST_PSEUDO_REGISTER) | |
503 | #define ACCG_OR_PSEUDO_P(R) (ACCG_P (R) || (R) >= FIRST_PSEUDO_REGISTER) | |
504 | ||
505 | #define MAX_STACK_IMMEDIATE_OFFSET 2047 | |
506 | ||
507 | \f | |
508 | /* Register Basics. */ | |
509 | ||
510 | /* Number of hardware registers known to the compiler. They receive numbers 0 | |
511 | through `FIRST_PSEUDO_REGISTER-1'; thus, the first pseudo register's number | |
512 | really is assigned the number `FIRST_PSEUDO_REGISTER'. */ | |
513 | #define FIRST_PSEUDO_REGISTER (SPR_LAST + 1) | |
514 | ||
515 | /* The first/last register that can contain the arguments to a function. */ | |
516 | #define FIRST_ARG_REGNUM (GPR_FIRST + 8) | |
517 | #define LAST_ARG_REGNUM (FIRST_ARG_REGNUM + FRV_NUM_ARG_REGS - 1) | |
518 | ||
519 | /* Registers used by the exception handling functions. These should be | |
1ae58c30 | 520 | registers that are not otherwise used by the calling sequence. */ |
36a05131 BS |
521 | #define FIRST_EH_REGNUM 14 |
522 | #define LAST_EH_REGNUM 15 | |
523 | ||
524 | /* Scratch registers used in the prologue, epilogue and thunks. | |
525 | OFFSET_REGNO is for loading constant addends that are too big for a | |
526 | single instruction. TEMP_REGNO is used for transferring SPRs to and from | |
527 | the stack, and various other activities. */ | |
528 | #define OFFSET_REGNO 4 | |
529 | #define TEMP_REGNO 5 | |
530 | ||
531 | /* Registers used in the prologue. OLD_SP_REGNO is the old stack pointer, | |
532 | which is sometimes used to set up the frame pointer. */ | |
533 | #define OLD_SP_REGNO 6 | |
534 | ||
535 | /* Registers used in the epilogue. STACKADJ_REGNO stores the exception | |
536 | handler's stack adjustment. */ | |
537 | #define STACKADJ_REGNO 6 | |
538 | ||
539 | /* Registers used in thunks. JMP_REGNO is used for loading the target | |
540 | address. */ | |
541 | #define JUMP_REGNO 6 | |
542 | ||
543 | #define EH_RETURN_DATA_REGNO(N) ((N) <= (LAST_EH_REGNUM - FIRST_EH_REGNUM)? \ | |
544 | (N) + FIRST_EH_REGNUM : INVALID_REGNUM) | |
545 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, STACKADJ_REGNO) | |
546 | #define EH_RETURN_HANDLER_RTX RETURN_ADDR_RTX (0, frame_pointer_rtx) | |
547 | ||
e1175f68 RS |
548 | #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNO) |
549 | ||
36a05131 BS |
550 | /* An initializer that says which registers are used for fixed purposes all |
551 | throughout the compiled code and are therefore not available for general | |
552 | allocation. These would include the stack pointer, the frame pointer | |
553 | (except on machines where that can be used as a general register when no | |
554 | frame pointer is needed), the program counter on machines where that is | |
555 | considered one of the addressable registers, and any other numbered register | |
556 | with a standard use. | |
557 | ||
558 | This information is expressed as a sequence of numbers, separated by commas | |
559 | and surrounded by braces. The Nth number is 1 if register N is fixed, 0 | |
560 | otherwise. | |
561 | ||
562 | The table initialized from this macro, and the table initialized by the | |
563 | following one, may be overridden at run time either automatically, by the | |
564 | actions of the macro `CONDITIONAL_REGISTER_USAGE', or by the user with the | |
565 | command options `-ffixed-REG', `-fcall-used-REG' and `-fcall-saved-REG'. */ | |
566 | ||
567 | /* gr0 -- Hard Zero | |
568 | gr1 -- Stack Pointer | |
569 | gr2 -- Frame Pointer | |
570 | gr3 -- Hidden Parameter | |
571 | gr16 -- Small Data reserved | |
572 | gr17 -- Pic reserved | |
573 | gr28 -- OS reserved | |
574 | gr29 -- OS reserved | |
575 | gr30 -- OS reserved | |
576 | gr31 -- OS reserved | |
577 | cr3 -- reserved to reload FCC registers. | |
578 | cr7 -- reserved to reload ICC registers. */ | |
579 | #define FIXED_REGISTERS \ | |
580 | { /* Integer Registers */ \ | |
581 | 1, 1, 1, 1, 0, 0, 0, 0, /* 000-007, gr0 - gr7 */ \ | |
582 | 0, 0, 0, 0, 0, 0, 0, 0, /* 008-015, gr8 - gr15 */ \ | |
583 | 1, 1, 0, 0, 0, 0, 0, 0, /* 016-023, gr16 - gr23 */ \ | |
584 | 0, 0, 0, 0, 1, 1, 1, 1, /* 024-031, gr24 - gr31 */ \ | |
585 | 0, 0, 0, 0, 0, 0, 0, 0, /* 032-039, gr32 - gr39 */ \ | |
586 | 0, 0, 0, 0, 0, 0, 0, 0, /* 040-040, gr48 - gr47 */ \ | |
587 | 0, 0, 0, 0, 0, 0, 0, 0, /* 048-055, gr48 - gr55 */ \ | |
588 | 0, 0, 0, 0, 0, 0, 0, 0, /* 056-063, gr56 - gr63 */ \ | |
589 | /* Float Registers */ \ | |
590 | 0, 0, 0, 0, 0, 0, 0, 0, /* 064-071, fr0 - fr7 */ \ | |
591 | 0, 0, 0, 0, 0, 0, 0, 0, /* 072-079, fr8 - fr15 */ \ | |
592 | 0, 0, 0, 0, 0, 0, 0, 0, /* 080-087, fr16 - fr23 */ \ | |
593 | 0, 0, 0, 0, 0, 0, 0, 0, /* 088-095, fr24 - fr31 */ \ | |
594 | 0, 0, 0, 0, 0, 0, 0, 0, /* 096-103, fr32 - fr39 */ \ | |
595 | 0, 0, 0, 0, 0, 0, 0, 0, /* 104-111, fr48 - fr47 */ \ | |
596 | 0, 0, 0, 0, 0, 0, 0, 0, /* 112-119, fr48 - fr55 */ \ | |
597 | 0, 0, 0, 0, 0, 0, 0, 0, /* 120-127, fr56 - fr63 */ \ | |
598 | /* Condition Code Registers */ \ | |
599 | 0, 0, 0, 0, /* 128-131, fcc0 - fcc3 */ \ | |
600 | 0, 0, 0, 1, /* 132-135, icc0 - icc3 */ \ | |
601 | /* Conditional execution Registers (CCR) */ \ | |
602 | 0, 0, 0, 0, 0, 0, 0, 1, /* 136-143, cr0 - cr7 */ \ | |
603 | /* Accumulators */ \ | |
604 | 1, 1, 1, 1, 1, 1, 1, 1, /* 144-151, acc0 - acc7 */ \ | |
c557edf4 RS |
605 | 1, 1, 1, 1, /* 152-155, acc8 - acc11 */ \ |
606 | 1, 1, 1, 1, 1, 1, 1, 1, /* 156-163, accg0 - accg7 */ \ | |
607 | 1, 1, 1, 1, /* 164-167, accg8 - accg11 */ \ | |
36a05131 | 608 | /* Other registers */ \ |
c557edf4 | 609 | 1, /* 168, AP - fake arg ptr */ \ |
8d8256c1 | 610 | 1, /* 169, LR - Link register*/ \ |
c557edf4 RS |
611 | 0, /* 170, LCR - Loop count reg*/ \ |
612 | 1, 1 /* 171-172, iacc0 */ \ | |
36a05131 BS |
613 | } |
614 | ||
615 | /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered (in | |
616 | general) by function calls as well as for fixed registers. This macro | |
617 | therefore identifies the registers that are not available for general | |
618 | allocation of values that must live across function calls. | |
619 | ||
620 | If a register has 0 in `CALL_USED_REGISTERS', the compiler automatically | |
621 | saves it on function entry and restores it on function exit, if the register | |
622 | is used within the function. */ | |
623 | #define CALL_USED_REGISTERS \ | |
624 | { /* Integer Registers */ \ | |
625 | 1, 1, 1, 1, 1, 1, 1, 1, /* 000-007, gr0 - gr7 */ \ | |
626 | 1, 1, 1, 1, 1, 1, 1, 1, /* 008-015, gr8 - gr15 */ \ | |
627 | 1, 1, 0, 0, 0, 0, 0, 0, /* 016-023, gr16 - gr23 */ \ | |
628 | 0, 0, 0, 0, 1, 1, 1, 1, /* 024-031, gr24 - gr31 */ \ | |
629 | 1, 1, 1, 1, 1, 1, 1, 1, /* 032-039, gr32 - gr39 */ \ | |
630 | 1, 1, 1, 1, 1, 1, 1, 1, /* 040-040, gr48 - gr47 */ \ | |
631 | 0, 0, 0, 0, 0, 0, 0, 0, /* 048-055, gr48 - gr55 */ \ | |
632 | 0, 0, 0, 0, 0, 0, 0, 0, /* 056-063, gr56 - gr63 */ \ | |
633 | /* Float Registers */ \ | |
634 | 1, 1, 1, 1, 1, 1, 1, 1, /* 064-071, fr0 - fr7 */ \ | |
635 | 1, 1, 1, 1, 1, 1, 1, 1, /* 072-079, fr8 - fr15 */ \ | |
636 | 0, 0, 0, 0, 0, 0, 0, 0, /* 080-087, fr16 - fr23 */ \ | |
637 | 0, 0, 0, 0, 0, 0, 0, 0, /* 088-095, fr24 - fr31 */ \ | |
638 | 1, 1, 1, 1, 1, 1, 1, 1, /* 096-103, fr32 - fr39 */ \ | |
639 | 1, 1, 1, 1, 1, 1, 1, 1, /* 104-111, fr48 - fr47 */ \ | |
640 | 0, 0, 0, 0, 0, 0, 0, 0, /* 112-119, fr48 - fr55 */ \ | |
641 | 0, 0, 0, 0, 0, 0, 0, 0, /* 120-127, fr56 - fr63 */ \ | |
642 | /* Condition Code Registers */ \ | |
643 | 1, 1, 1, 1, /* 128-131, fcc0 - fcc3 */ \ | |
644 | 1, 1, 1, 1, /* 132-135, icc0 - icc3 */ \ | |
645 | /* Conditional execution Registers (CCR) */ \ | |
646 | 1, 1, 1, 1, 1, 1, 1, 1, /* 136-143, cr0 - cr7 */ \ | |
647 | /* Accumulators */ \ | |
648 | 1, 1, 1, 1, 1, 1, 1, 1, /* 144-151, acc0 - acc7 */ \ | |
c557edf4 RS |
649 | 1, 1, 1, 1, /* 152-155, acc8 - acc11 */ \ |
650 | 1, 1, 1, 1, 1, 1, 1, 1, /* 156-163, accg0 - accg7 */ \ | |
651 | 1, 1, 1, 1, /* 164-167, accg8 - accg11 */ \ | |
36a05131 | 652 | /* Other registers */ \ |
c557edf4 RS |
653 | 1, /* 168, AP - fake arg ptr */ \ |
654 | 1, /* 169, LR - Link register*/ \ | |
655 | 1, /* 170, LCR - Loop count reg */ \ | |
656 | 1, 1 /* 171-172, iacc0 */ \ | |
36a05131 BS |
657 | } |
658 | ||
36a05131 BS |
659 | \f |
660 | /* Order of allocation of registers. */ | |
661 | ||
662 | /* If defined, an initializer for a vector of integers, containing the numbers | |
7ec022b2 | 663 | of hard registers in the order in which GCC should prefer to use them |
36a05131 BS |
664 | (from most preferred to least). |
665 | ||
666 | If this macro is not defined, registers are used lowest numbered first (all | |
667 | else being equal). | |
668 | ||
669 | One use of this macro is on machines where the highest numbered registers | |
670 | must always be saved and the save-multiple-registers instruction supports | |
671 | only sequences of consecutive registers. On such machines, define | |
672 | `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered | |
673 | allocatable register first. */ | |
674 | ||
675 | /* On the FRV, allocate GR16 and GR17 after other saved registers so that we | |
676 | have a better chance of allocating 2 registers at a time and can use the | |
677 | double word load/store instructions in the prologue. */ | |
678 | #define REG_ALLOC_ORDER \ | |
679 | { \ | |
680 | /* volatile registers */ \ | |
681 | GPR_FIRST + 4, GPR_FIRST + 5, GPR_FIRST + 6, GPR_FIRST + 7, \ | |
682 | GPR_FIRST + 8, GPR_FIRST + 9, GPR_FIRST + 10, GPR_FIRST + 11, \ | |
683 | GPR_FIRST + 12, GPR_FIRST + 13, GPR_FIRST + 14, GPR_FIRST + 15, \ | |
684 | GPR_FIRST + 32, GPR_FIRST + 33, GPR_FIRST + 34, GPR_FIRST + 35, \ | |
685 | GPR_FIRST + 36, GPR_FIRST + 37, GPR_FIRST + 38, GPR_FIRST + 39, \ | |
686 | GPR_FIRST + 40, GPR_FIRST + 41, GPR_FIRST + 42, GPR_FIRST + 43, \ | |
687 | GPR_FIRST + 44, GPR_FIRST + 45, GPR_FIRST + 46, GPR_FIRST + 47, \ | |
688 | \ | |
689 | FPR_FIRST + 0, FPR_FIRST + 1, FPR_FIRST + 2, FPR_FIRST + 3, \ | |
690 | FPR_FIRST + 4, FPR_FIRST + 5, FPR_FIRST + 6, FPR_FIRST + 7, \ | |
691 | FPR_FIRST + 8, FPR_FIRST + 9, FPR_FIRST + 10, FPR_FIRST + 11, \ | |
692 | FPR_FIRST + 12, FPR_FIRST + 13, FPR_FIRST + 14, FPR_FIRST + 15, \ | |
693 | FPR_FIRST + 32, FPR_FIRST + 33, FPR_FIRST + 34, FPR_FIRST + 35, \ | |
694 | FPR_FIRST + 36, FPR_FIRST + 37, FPR_FIRST + 38, FPR_FIRST + 39, \ | |
695 | FPR_FIRST + 40, FPR_FIRST + 41, FPR_FIRST + 42, FPR_FIRST + 43, \ | |
696 | FPR_FIRST + 44, FPR_FIRST + 45, FPR_FIRST + 46, FPR_FIRST + 47, \ | |
697 | \ | |
698 | ICC_FIRST + 0, ICC_FIRST + 1, ICC_FIRST + 2, ICC_FIRST + 3, \ | |
699 | FCC_FIRST + 0, FCC_FIRST + 1, FCC_FIRST + 2, FCC_FIRST + 3, \ | |
700 | CR_FIRST + 0, CR_FIRST + 1, CR_FIRST + 2, CR_FIRST + 3, \ | |
701 | CR_FIRST + 4, CR_FIRST + 5, CR_FIRST + 6, CR_FIRST + 7, \ | |
702 | \ | |
703 | /* saved registers */ \ | |
704 | GPR_FIRST + 18, GPR_FIRST + 19, \ | |
705 | GPR_FIRST + 20, GPR_FIRST + 21, GPR_FIRST + 22, GPR_FIRST + 23, \ | |
706 | GPR_FIRST + 24, GPR_FIRST + 25, GPR_FIRST + 26, GPR_FIRST + 27, \ | |
707 | GPR_FIRST + 48, GPR_FIRST + 49, GPR_FIRST + 50, GPR_FIRST + 51, \ | |
708 | GPR_FIRST + 52, GPR_FIRST + 53, GPR_FIRST + 54, GPR_FIRST + 55, \ | |
709 | GPR_FIRST + 56, GPR_FIRST + 57, GPR_FIRST + 58, GPR_FIRST + 59, \ | |
710 | GPR_FIRST + 60, GPR_FIRST + 61, GPR_FIRST + 62, GPR_FIRST + 63, \ | |
711 | GPR_FIRST + 16, GPR_FIRST + 17, \ | |
712 | \ | |
713 | FPR_FIRST + 16, FPR_FIRST + 17, FPR_FIRST + 18, FPR_FIRST + 19, \ | |
714 | FPR_FIRST + 20, FPR_FIRST + 21, FPR_FIRST + 22, FPR_FIRST + 23, \ | |
715 | FPR_FIRST + 24, FPR_FIRST + 25, FPR_FIRST + 26, FPR_FIRST + 27, \ | |
716 | FPR_FIRST + 28, FPR_FIRST + 29, FPR_FIRST + 30, FPR_FIRST + 31, \ | |
717 | FPR_FIRST + 48, FPR_FIRST + 49, FPR_FIRST + 50, FPR_FIRST + 51, \ | |
718 | FPR_FIRST + 52, FPR_FIRST + 53, FPR_FIRST + 54, FPR_FIRST + 55, \ | |
719 | FPR_FIRST + 56, FPR_FIRST + 57, FPR_FIRST + 58, FPR_FIRST + 59, \ | |
720 | FPR_FIRST + 60, FPR_FIRST + 61, FPR_FIRST + 62, FPR_FIRST + 63, \ | |
721 | \ | |
722 | /* special or fixed registers */ \ | |
723 | GPR_FIRST + 0, GPR_FIRST + 1, GPR_FIRST + 2, GPR_FIRST + 3, \ | |
724 | GPR_FIRST + 28, GPR_FIRST + 29, GPR_FIRST + 30, GPR_FIRST + 31, \ | |
725 | ACC_FIRST + 0, ACC_FIRST + 1, ACC_FIRST + 2, ACC_FIRST + 3, \ | |
726 | ACC_FIRST + 4, ACC_FIRST + 5, ACC_FIRST + 6, ACC_FIRST + 7, \ | |
c557edf4 | 727 | ACC_FIRST + 8, ACC_FIRST + 9, ACC_FIRST + 10, ACC_FIRST + 11, \ |
36a05131 BS |
728 | ACCG_FIRST + 0, ACCG_FIRST + 1, ACCG_FIRST + 2, ACCG_FIRST + 3, \ |
729 | ACCG_FIRST + 4, ACCG_FIRST + 5, ACCG_FIRST + 6, ACCG_FIRST + 7, \ | |
c557edf4 RS |
730 | ACCG_FIRST + 8, ACCG_FIRST + 9, ACCG_FIRST + 10, ACCG_FIRST + 11, \ |
731 | AP_FIRST, LR_REGNO, LCR_REGNO, \ | |
732 | IACC_FIRST + 0, IACC_FIRST + 1 \ | |
36a05131 BS |
733 | } |
734 | ||
735 | \f | |
36a05131 BS |
736 | /* Define this macro if the compiler should avoid copies to/from CCmode |
737 | registers. You should only define this macro if support fo copying to/from | |
738 | CCmode is incomplete. */ | |
739 | #define AVOID_CCMODE_COPIES | |
740 | ||
741 | \f | |
742 | /* Register Classes. */ | |
743 | ||
744 | /* An enumeral type that must be defined with all the register class names as | |
745 | enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last | |
746 | register class, followed by one more enumeral value, `LIM_REG_CLASSES', | |
747 | which is not a register class but rather tells how many classes there are. | |
748 | ||
749 | Each register class has a number, which is the value of casting the class | |
750 | name to type `int'. The number serves as an index in many of the tables | |
751 | described below. */ | |
752 | enum reg_class | |
753 | { | |
754 | NO_REGS, | |
755 | ICC_REGS, | |
756 | FCC_REGS, | |
757 | CC_REGS, | |
758 | ICR_REGS, | |
759 | FCR_REGS, | |
760 | CR_REGS, | |
761 | LCR_REG, | |
762 | LR_REG, | |
bef8809e AH |
763 | GR8_REGS, |
764 | GR9_REGS, | |
765 | GR89_REGS, | |
34208acf AO |
766 | FDPIC_REGS, |
767 | FDPIC_FPTR_REGS, | |
768 | FDPIC_CALL_REGS, | |
36a05131 BS |
769 | SPR_REGS, |
770 | QUAD_ACC_REGS, | |
36a05131 BS |
771 | ACCG_REGS, |
772 | QUAD_FPR_REGS, | |
36a05131 | 773 | QUAD_REGS, |
36a05131 BS |
774 | GPR_REGS, |
775 | ALL_REGS, | |
776 | LIM_REG_CLASSES | |
777 | }; | |
778 | ||
779 | #define GENERAL_REGS GPR_REGS | |
780 | ||
781 | /* The number of distinct register classes, defined as follows: | |
782 | ||
783 | #define N_REG_CLASSES (int) LIM_REG_CLASSES */ | |
784 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) | |
785 | ||
786 | /* An initializer containing the names of the register classes as C string | |
787 | constants. These names are used in writing some of the debugging dumps. */ | |
788 | #define REG_CLASS_NAMES { \ | |
789 | "NO_REGS", \ | |
790 | "ICC_REGS", \ | |
791 | "FCC_REGS", \ | |
792 | "CC_REGS", \ | |
793 | "ICR_REGS", \ | |
794 | "FCR_REGS", \ | |
795 | "CR_REGS", \ | |
796 | "LCR_REG", \ | |
797 | "LR_REG", \ | |
bef8809e AH |
798 | "GR8_REGS", \ |
799 | "GR9_REGS", \ | |
800 | "GR89_REGS", \ | |
34208acf AO |
801 | "FDPIC_REGS", \ |
802 | "FDPIC_FPTR_REGS", \ | |
803 | "FDPIC_CALL_REGS", \ | |
36a05131 BS |
804 | "SPR_REGS", \ |
805 | "QUAD_ACC_REGS", \ | |
36a05131 BS |
806 | "ACCG_REGS", \ |
807 | "QUAD_FPR_REGS", \ | |
36a05131 | 808 | "QUAD_REGS", \ |
36a05131 BS |
809 | "GPR_REGS", \ |
810 | "ALL_REGS" \ | |
811 | } | |
812 | ||
813 | /* An initializer containing the contents of the register classes, as integers | |
814 | which are bit masks. The Nth integer specifies the contents of class N. | |
815 | The way the integer MASK is interpreted is that register R is in the class | |
816 | if `MASK & (1 << R)' is 1. | |
817 | ||
818 | When the machine has more than 32 registers, an integer does not suffice. | |
819 | Then the integers are replaced by sub-initializers, braced groupings | |
820 | containing several integers. Each sub-initializer must be suitable as an | |
821 | initializer for the type `HARD_REG_SET' which is defined in | |
822 | `hard-reg-set.h'. */ | |
823 | #define REG_CLASS_CONTENTS \ | |
824 | { /* gr0-gr31 gr32-gr63 fr0-fr31 fr32-fr-63 cc/ccr/acc ap/spr */ \ | |
825 | { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* NO_REGS */\ | |
826 | { 0x00000000,0x00000000,0x00000000,0x00000000,0x000000f0,0x0}, /* ICC_REGS */\ | |
827 | { 0x00000000,0x00000000,0x00000000,0x00000000,0x0000000f,0x0}, /* FCC_REGS */\ | |
828 | { 0x00000000,0x00000000,0x00000000,0x00000000,0x000000ff,0x0}, /* CC_REGS */\ | |
829 | { 0x00000000,0x00000000,0x00000000,0x00000000,0x0000f000,0x0}, /* ICR_REGS */\ | |
830 | { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000f00,0x0}, /* FCR_REGS */\ | |
831 | { 0x00000000,0x00000000,0x00000000,0x00000000,0x0000ff00,0x0}, /* CR_REGS */\ | |
c557edf4 RS |
832 | { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x400}, /* LCR_REGS */\ |
833 | { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x200}, /* LR_REGS */\ | |
bef8809e AH |
834 | { 0x00000100,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* GR8_REGS */\ |
835 | { 0x00000200,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* GR9_REGS */\ | |
836 | { 0x00000300,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* GR89_REGS */\ | |
34208acf AO |
837 | { 0x00008000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* FDPIC_REGS */\ |
838 | { 0x00004000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* FDPIC_FPTR_REGS */\ | |
839 | { 0x0000c000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* FDPIC_CALL_REGS */\ | |
c557edf4 RS |
840 | { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x1e00}, /* SPR_REGS */\ |
841 | { 0x00000000,0x00000000,0x00000000,0x00000000,0x0fff0000,0x0}, /* QUAD_ACC */\ | |
c557edf4 | 842 | { 0x00000000,0x00000000,0x00000000,0x00000000,0xf0000000,0xff}, /* ACCG_REGS*/\ |
36a05131 | 843 | { 0x00000000,0x00000000,0xffffffff,0xffffffff,0x00000000,0x0}, /* QUAD_FPR */\ |
36a05131 | 844 | { 0x0ffffffc,0xffffffff,0x00000000,0x00000000,0x00000000,0x0}, /* QUAD_REGS*/\ |
c557edf4 RS |
845 | { 0xffffffff,0xffffffff,0x00000000,0x00000000,0x00000000,0x100}, /* GPR_REGS */\ |
846 | { 0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0x1fff}, /* ALL_REGS */\ | |
36a05131 BS |
847 | } |
848 | ||
9b5db25d NC |
849 | #define EVEN_ACC_REGS QUAD_ACC_REGS |
850 | #define ACC_REGS QUAD_ACC_REGS | |
851 | #define FEVEN_REGS QUAD_FPR_REGS | |
852 | #define FPR_REGS QUAD_FPR_REGS | |
853 | #define EVEN_REGS QUAD_REGS | |
854 | ||
36a05131 BS |
855 | /* A C expression whose value is a register class containing hard register |
856 | REGNO. In general there is more than one such class; choose a class which | |
857 | is "minimal", meaning that no smaller class also contains the register. */ | |
858 | ||
859 | extern enum reg_class regno_reg_class[]; | |
860 | #define REGNO_REG_CLASS(REGNO) regno_reg_class [REGNO] | |
861 | ||
862 | /* A macro whose definition is the name of the class to which a valid base | |
863 | register must belong. A base register is one used in an address which is | |
864 | the register value plus a displacement. */ | |
865 | #define BASE_REG_CLASS GPR_REGS | |
866 | ||
867 | /* A macro whose definition is the name of the class to which a valid index | |
868 | register must belong. An index register is one used in an address where its | |
869 | value is either multiplied by a scale factor or added to another register | |
870 | (as well as added to a displacement). */ | |
871 | #define INDEX_REG_CLASS GPR_REGS | |
872 | ||
36a05131 BS |
873 | /* A C expression which is nonzero if register number NUM is suitable for use |
874 | as a base register in operand addresses. It may be either a suitable hard | |
875 | register or a pseudo register that has been allocated such a hard register. */ | |
876 | #define REGNO_OK_FOR_BASE_P(NUM) \ | |
877 | ((NUM) < FIRST_PSEUDO_REGISTER \ | |
878 | ? GPR_P (NUM) \ | |
879 | : (reg_renumber [NUM] >= 0 && GPR_P (reg_renumber [NUM]))) | |
880 | ||
881 | /* A C expression which is nonzero if register number NUM is suitable for use | |
882 | as an index register in operand addresses. It may be either a suitable hard | |
883 | register or a pseudo register that has been allocated such a hard register. | |
884 | ||
885 | The difference between an index register and a base register is that the | |
886 | index register may be scaled. If an address involves the sum of two | |
887 | registers, neither one of them scaled, then either one may be labeled the | |
888 | "base" and the other the "index"; but whichever labeling is used must fit | |
889 | the machine's constraints of which registers may serve in each capacity. | |
890 | The compiler will try both labelings, looking for one that is valid, and | |
891 | will reload one or both registers only if neither labeling works. */ | |
892 | #define REGNO_OK_FOR_INDEX_P(NUM) \ | |
893 | ((NUM) < FIRST_PSEUDO_REGISTER \ | |
894 | ? GPR_P (NUM) \ | |
895 | : (reg_renumber [NUM] >= 0 && GPR_P (reg_renumber [NUM]))) | |
896 | ||
36a05131 | 897 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
35f2d8ef | 898 | frv_secondary_reload_class (CLASS, MODE, X) |
36a05131 BS |
899 | |
900 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
35f2d8ef | 901 | frv_secondary_reload_class (CLASS, MODE, X) |
36a05131 | 902 | |
36a05131 BS |
903 | #define CLASS_MAX_NREGS(CLASS, MODE) frv_class_max_nregs (CLASS, MODE) |
904 | ||
905 | #define ZERO_P(x) (x == CONST0_RTX (GET_MODE (x))) | |
906 | ||
36a05131 BS |
907 | \f |
908 | /* Basic Stack Layout. */ | |
909 | ||
910 | /* Structure to describe information about a saved range of registers */ | |
911 | ||
912 | typedef struct frv_stack_regs { | |
913 | const char * name; /* name of the register ranges */ | |
914 | int first; /* first register in the range */ | |
915 | int last; /* last register in the range */ | |
916 | int size_1word; /* # of bytes to be stored via 1 word stores */ | |
917 | int size_2words; /* # of bytes to be stored via 2 word stores */ | |
918 | unsigned char field_p; /* true if the registers are a single SPR */ | |
919 | unsigned char dword_p; /* true if we can do dword stores */ | |
920 | unsigned char special_p; /* true if the regs have a fixed save loc. */ | |
921 | } frv_stack_regs_t; | |
922 | ||
923 | /* Register ranges to look into saving. */ | |
924 | #define STACK_REGS_GPR 0 /* Gprs (normally gr16..gr31, gr48..gr63) */ | |
925 | #define STACK_REGS_FPR 1 /* Fprs (normally fr16..fr31, fr48..fr63) */ | |
926 | #define STACK_REGS_LR 2 /* LR register */ | |
927 | #define STACK_REGS_CC 3 /* CCrs (normally not saved) */ | |
928 | #define STACK_REGS_LCR 5 /* lcr register */ | |
929 | #define STACK_REGS_STDARG 6 /* stdarg registers */ | |
930 | #define STACK_REGS_STRUCT 7 /* structure return (gr3) */ | |
931 | #define STACK_REGS_FP 8 /* FP register */ | |
932 | #define STACK_REGS_MAX 9 /* # of register ranges */ | |
933 | ||
934 | /* Values for save_p field. */ | |
935 | #define REG_SAVE_NO_SAVE 0 /* register not saved */ | |
936 | #define REG_SAVE_1WORD 1 /* save the register */ | |
937 | #define REG_SAVE_2WORDS 2 /* save register and register+1 */ | |
938 | ||
939 | /* Structure used to define the frv stack. */ | |
940 | ||
941 | typedef struct frv_stack { | |
942 | int total_size; /* total bytes allocated for stack */ | |
943 | int vars_size; /* variable save area size */ | |
944 | int parameter_size; /* outgoing parameter size */ | |
945 | int stdarg_size; /* size of regs needed to be saved for stdarg */ | |
946 | int regs_size; /* size of the saved registers */ | |
947 | int regs_size_1word; /* # of bytes to be stored via 1 word stores */ | |
948 | int regs_size_2words; /* # of bytes to be stored via 2 word stores */ | |
949 | int header_size; /* size of the old FP, struct ret., LR save */ | |
950 | int pretend_size; /* size of pretend args */ | |
951 | int vars_offset; /* offset to save local variables from new SP*/ | |
952 | int regs_offset; /* offset to save registers from new SP */ | |
953 | /* register range information */ | |
954 | frv_stack_regs_t regs[STACK_REGS_MAX]; | |
955 | /* offset to store each register */ | |
956 | int reg_offset[FIRST_PSEUDO_REGISTER]; | |
957 | /* whether to save register (& reg+1) */ | |
958 | unsigned char save_p[FIRST_PSEUDO_REGISTER]; | |
959 | } frv_stack_t; | |
960 | ||
961 | /* Define this macro if pushing a word onto the stack moves the stack pointer | |
962 | to a smaller address. */ | |
963 | #define STACK_GROWS_DOWNWARD 1 | |
964 | ||
a4d05547 | 965 | /* Define this macro to nonzero if the addresses of local variable slots |
f62c8a5c JJ |
966 | are at negative offsets from the frame pointer. */ |
967 | #define FRAME_GROWS_DOWNWARD 1 | |
36a05131 | 968 | |
36a05131 BS |
969 | /* Offset from the stack pointer register to the first location at which |
970 | outgoing arguments are placed. If not specified, the default value of zero | |
971 | is used. This is the proper value for most machines. | |
972 | ||
973 | If `ARGS_GROW_DOWNWARD', this is the offset to the location above the first | |
974 | location at which outgoing arguments are placed. */ | |
975 | #define STACK_POINTER_OFFSET 0 | |
976 | ||
977 | /* Offset from the argument pointer register to the first argument's address. | |
978 | On some machines it may depend on the data type of the function. | |
979 | ||
980 | If `ARGS_GROW_DOWNWARD', this is the offset to the location above the first | |
981 | argument's address. */ | |
982 | #define FIRST_PARM_OFFSET(FUNDECL) 0 | |
983 | ||
984 | /* A C expression whose value is RTL representing the address in a stack frame | |
985 | where the pointer to the caller's frame is stored. Assume that FRAMEADDR is | |
986 | an RTL expression for the address of the stack frame itself. | |
987 | ||
988 | If you don't define this macro, the default is to return the value of | |
989 | FRAMEADDR--that is, the stack frame address is also the address of the stack | |
990 | word that points to the previous frame. */ | |
991 | #define DYNAMIC_CHAIN_ADDRESS(FRAMEADDR) frv_dynamic_chain_address (FRAMEADDR) | |
992 | ||
993 | /* A C expression whose value is RTL representing the value of the return | |
994 | address for the frame COUNT steps up from the current frame, after the | |
995 | prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame | |
996 | pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is | |
997 | defined. | |
998 | ||
999 | The value of the expression must always be the correct address when COUNT is | |
1000 | zero, but may be `NULL_RTX' if there is not way to determine the return | |
1001 | address of other frames. */ | |
1002 | #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) frv_return_addr_rtx (COUNT, FRAMEADDR) | |
1003 | ||
36a05131 BS |
1004 | #define RETURN_POINTER_REGNUM LR_REGNO |
1005 | ||
1006 | /* A C expression whose value is RTL representing the location of the incoming | |
1007 | return address at the beginning of any function, before the prologue. This | |
1008 | RTL is either a `REG', indicating that the return value is saved in `REG', | |
1009 | or a `MEM' representing a location in the stack. | |
1010 | ||
1011 | You only need to define this macro if you want to support call frame | |
1012 | debugging information like that provided by DWARF 2. */ | |
1013 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (SImode, RETURN_POINTER_REGNUM) | |
1014 | ||
1015 | \f | |
1016 | /* Register That Address the Stack Frame. */ | |
1017 | ||
1018 | /* The register number of the stack pointer register, which must also be a | |
1019 | fixed register according to `FIXED_REGISTERS'. On most machines, the | |
1020 | hardware determines which register this is. */ | |
1021 | #define STACK_POINTER_REGNUM (GPR_FIRST + 1) | |
1022 | ||
1023 | /* The register number of the frame pointer register, which is used to access | |
1024 | automatic variables in the stack frame. On some machines, the hardware | |
1025 | determines which register this is. On other machines, you can choose any | |
1026 | register you wish for this purpose. */ | |
1027 | #define FRAME_POINTER_REGNUM (GPR_FIRST + 2) | |
1028 | ||
1029 | /* The register number of the arg pointer register, which is used to access the | |
1030 | function's argument list. On some machines, this is the same as the frame | |
1031 | pointer register. On some machines, the hardware determines which register | |
1032 | this is. On other machines, you can choose any register you wish for this | |
1033 | purpose. If this is not the same register as the frame pointer register, | |
1034 | then you must mark it as a fixed register according to `FIXED_REGISTERS', or | |
1035 | arrange to be able to eliminate it. */ | |
1036 | ||
1037 | /* On frv this is a fake register that is eliminated in | |
1038 | terms of either the frame pointer or stack pointer. */ | |
1039 | #define ARG_POINTER_REGNUM AP_FIRST | |
1040 | ||
1041 | /* Register numbers used for passing a function's static chain pointer. If | |
1042 | register windows are used, the register number as seen by the called | |
1043 | function is `STATIC_CHAIN_INCOMING_REGNUM', while the register number as | |
1044 | seen by the calling function is `STATIC_CHAIN_REGNUM'. If these registers | |
1045 | are the same, `STATIC_CHAIN_INCOMING_REGNUM' need not be defined. | |
1046 | ||
1047 | The static chain register need not be a fixed register. | |
1048 | ||
1049 | If the static chain is passed in memory, these macros should not be defined; | |
1050 | instead, the next two macros should be defined. */ | |
1051 | #define STATIC_CHAIN_REGNUM (GPR_FIRST + 7) | |
1052 | #define STATIC_CHAIN_INCOMING_REGNUM (GPR_FIRST + 7) | |
1053 | ||
1054 | \f | |
1055 | /* Eliminating the Frame Pointer and the Arg Pointer. */ | |
1056 | ||
36a05131 BS |
1057 | /* If defined, this macro specifies a table of register pairs used to eliminate |
1058 | unneeded registers that point into the stack frame. If it is not defined, | |
1059 | the only elimination attempted by the compiler is to replace references to | |
1060 | the frame pointer with references to the stack pointer. | |
1061 | ||
1062 | The definition of this macro is a list of structure initializations, each of | |
1063 | which specifies an original and replacement register. | |
1064 | ||
1065 | On some machines, the position of the argument pointer is not known until | |
1066 | the compilation is completed. In such a case, a separate hard register must | |
1067 | be used for the argument pointer. This register can be eliminated by | |
1068 | replacing it with either the frame pointer or the argument pointer, | |
1069 | depending on whether or not the frame pointer has been eliminated. | |
1070 | ||
1071 | In this case, you might specify: | |
1072 | #define ELIMINABLE_REGS \ | |
1073 | {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1074 | {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ | |
1075 | {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} | |
1076 | ||
1077 | Note that the elimination of the argument pointer with the stack pointer is | |
1078 | specified first since that is the preferred elimination. */ | |
1079 | ||
1080 | #define ELIMINABLE_REGS \ | |
1081 | { \ | |
1082 | {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1083 | {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ | |
1084 | {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \ | |
1085 | } | |
1086 | ||
53680238 BE |
1087 | /* This macro returns the initial difference between the specified pair |
1088 | of registers. */ | |
36a05131 BS |
1089 | |
1090 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
1091 | (OFFSET) = frv_initial_elimination_offset (FROM, TO) | |
1092 | ||
1093 | \f | |
1094 | /* Passing Function Arguments on the Stack. */ | |
1095 | ||
1096 | /* If defined, the maximum amount of space required for outgoing arguments will | |
1097 | be computed and placed into the variable | |
38173d38 | 1098 | `crtl->outgoing_args_size'. No space will be pushed onto the |
36a05131 BS |
1099 | stack for each call; instead, the function prologue should increase the |
1100 | stack frame size by this amount. | |
1101 | ||
1102 | Defining both `PUSH_ROUNDING' and `ACCUMULATE_OUTGOING_ARGS' is not | |
1103 | proper. */ | |
1104 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
1105 | ||
36a05131 | 1106 | \f |
36a05131 BS |
1107 | /* The number of register assigned to holding function arguments. */ |
1108 | ||
1109 | #define FRV_NUM_ARG_REGS 6 | |
1110 | ||
36a05131 BS |
1111 | /* A C type for declaring a variable that is used as the first argument of |
1112 | `FUNCTION_ARG' and other related values. For some target machines, the type | |
1113 | `int' suffices and can hold the number of bytes of argument so far. | |
1114 | ||
1115 | There is no need to record in `CUMULATIVE_ARGS' anything about the arguments | |
1116 | that have been passed on the stack. The compiler has other variables to | |
1117 | keep track of that. For target machines on which all arguments are passed | |
1118 | on the stack, there is no need to store anything in `CUMULATIVE_ARGS'; | |
1119 | however, the data structure must exist and should not be empty, so use | |
1120 | `int'. */ | |
1121 | #define CUMULATIVE_ARGS int | |
1122 | ||
1123 | /* A C statement (sans semicolon) for initializing the variable CUM for the | |
1124 | state at the beginning of the argument list. The variable has type | |
1125 | `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type | |
1126 | of the function which will receive the args, or 0 if the args are to a | |
1127 | compiler support library function. The value of INDIRECT is nonzero when | |
1128 | processing an indirect call, for example a call through a function pointer. | |
1129 | The value of INDIRECT is zero for a call to an explicitly named function, a | |
1130 | library function call, or when `INIT_CUMULATIVE_ARGS' is used to find | |
1131 | arguments for the function being compiled. | |
1132 | ||
1133 | When processing a call to a compiler support library function, LIBNAME | |
1134 | identifies which one. It is a `symbol_ref' rtx which contains the name of | |
1135 | the function, as a string. LIBNAME is 0 when an ordinary C function call is | |
1136 | being processed. Thus, each time this macro is called, either LIBNAME or | |
1137 | FNTYPE is nonzero, but never both of them at once. */ | |
1138 | ||
0f6937fe | 1139 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
563a317a | 1140 | frv_init_cumulative_args (&CUM, FNTYPE, LIBNAME, FNDECL, FALSE) |
36a05131 BS |
1141 | |
1142 | /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the | |
1143 | arguments for the function being compiled. If this macro is undefined, | |
1144 | `INIT_CUMULATIVE_ARGS' is used instead. | |
1145 | ||
1146 | The value passed for LIBNAME is always 0, since library routines with | |
7ec022b2 | 1147 | special calling conventions are never compiled with GCC. The argument |
36a05131 BS |
1148 | LIBNAME exists for symmetry with `INIT_CUMULATIVE_ARGS'. */ |
1149 | ||
1150 | #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ | |
563a317a | 1151 | frv_init_cumulative_args (&CUM, FNTYPE, LIBNAME, NULL, TRUE) |
36a05131 | 1152 | |
36a05131 BS |
1153 | /* A C expression that is nonzero if REGNO is the number of a hard register in |
1154 | which function arguments are sometimes passed. This does *not* include | |
1155 | implicit arguments such as the static chain and the structure-value address. | |
1156 | On many machines, no registers can be used for this purpose since all | |
1157 | function arguments are pushed on the stack. */ | |
1158 | #define FUNCTION_ARG_REGNO_P(REGNO) \ | |
1159 | ((REGNO) >= FIRST_ARG_REGNUM && ((REGNO) <= LAST_ARG_REGNUM)) | |
1160 | ||
1161 | \f | |
1162 | /* How Scalar Function Values are Returned. */ | |
1163 | ||
1164 | /* The number of the hard register that is used to return a scalar value from a | |
1165 | function call. */ | |
1166 | #define RETURN_VALUE_REGNUM (GPR_FIRST + 8) | |
1167 | ||
219d92a4 | 1168 | #define FUNCTION_VALUE_REGNO_P(REGNO) frv_function_value_regno_p (REGNO) |
36a05131 BS |
1169 | |
1170 | \f | |
1171 | /* How Large Values are Returned. */ | |
1172 | ||
56f42830 | 1173 | /* The number of the register that is used to pass the structure |
8ac411c7 KH |
1174 | value address. */ |
1175 | #define FRV_STRUCT_VALUE_REGNUM (GPR_FIRST + 3) | |
36a05131 BS |
1176 | |
1177 | \f | |
1178 | /* Function Entry and Exit. */ | |
1179 | ||
1180 | /* Define this macro as a C expression that is nonzero if the return | |
1181 | instruction or the function epilogue ignores the value of the stack pointer; | |
1182 | in other words, if it is safe to delete an instruction to adjust the stack | |
1183 | pointer before a return from the function. | |
1184 | ||
1185 | Note that this macro's value is relevant only for functions for which frame | |
1186 | pointers are maintained. It is never safe to delete a final stack | |
1187 | adjustment in a function that has no frame pointer, and the compiler knows | |
1188 | this regardless of `EXIT_IGNORE_STACK'. */ | |
1189 | #define EXIT_IGNORE_STACK 1 | |
36a05131 BS |
1190 | \f |
1191 | /* Generating Code for Profiling. */ | |
1192 | ||
1193 | /* A C statement or compound statement to output to FILE some assembler code to | |
1194 | call the profiling subroutine `mcount'. Before calling, the assembler code | |
1195 | must load the address of a counter variable into a register where `mcount' | |
1196 | expects to find the address. The name of this variable is `LP' followed by | |
1197 | the number LABELNO, so you would generate the name using `LP%d' in a | |
1198 | `fprintf'. | |
1199 | ||
1200 | The details of how the address should be passed to `mcount' are determined | |
7ec022b2 | 1201 | by your operating system environment, not by GCC. To figure them out, |
36a05131 BS |
1202 | compile a small program for profiling using the system's installed C |
1203 | compiler and look at the assembler code that results. | |
1204 | ||
1205 | This declaration must be present, but it can be an abort if profiling is | |
1206 | not implemented. */ | |
1207 | ||
b16c1435 | 1208 | #define FUNCTION_PROFILER(FILE, LABELNO) |
36a05131 | 1209 | |
36a05131 BS |
1210 | /* Trampolines for Nested Functions. */ |
1211 | ||
1212 | /* A C expression for the size in bytes of the trampoline, as an integer. */ | |
1213 | #define TRAMPOLINE_SIZE frv_trampoline_size () | |
1214 | ||
1215 | /* Alignment required for trampolines, in bits. | |
1216 | ||
1217 | If you don't define this macro, the value of `BIGGEST_ALIGNMENT' is used for | |
1218 | aligning trampolines. */ | |
34208acf | 1219 | #define TRAMPOLINE_ALIGNMENT (TARGET_FDPIC ? 64 : 32) |
36a05131 | 1220 | |
36a05131 BS |
1221 | /* Define this macro if trampolines need a special subroutine to do their work. |
1222 | The macro should expand to a series of `asm' statements which will be | |
7ec022b2 | 1223 | compiled with GCC. They go in a library function named |
36a05131 BS |
1224 | `__transfer_from_trampoline'. |
1225 | ||
1226 | If you need to avoid executing the ordinary prologue code of a compiled C | |
1227 | function when you jump to the subroutine, you can do so by placing a special | |
1228 | label of your own in the assembler code. Use one `asm' statement to | |
1229 | generate an assembler label, and another to make the label global. Then | |
1230 | trampolines can use that label to jump directly to your special assembler | |
1231 | code. */ | |
1232 | ||
1233 | #ifdef __FRV_UNDERSCORE__ | |
1234 | #define TRAMPOLINE_TEMPLATE_NAME "___trampoline_template" | |
1235 | #else | |
1236 | #define TRAMPOLINE_TEMPLATE_NAME "__trampoline_template" | |
1237 | #endif | |
1238 | ||
34208acf AO |
1239 | #define Twrite _write |
1240 | ||
1241 | #if ! __FRV_FDPIC__ | |
36a05131 | 1242 | #define TRANSFER_FROM_TRAMPOLINE \ |
34208acf | 1243 | extern int Twrite (int, const void *, unsigned); \ |
36a05131 BS |
1244 | \ |
1245 | void \ | |
f2206911 | 1246 | __trampoline_setup (short * addr, int size, int fnaddr, int sc) \ |
36a05131 BS |
1247 | { \ |
1248 | extern short __trampoline_template[]; \ | |
1249 | short * to = addr; \ | |
1250 | short * from = &__trampoline_template[0]; \ | |
1251 | int i; \ | |
1252 | \ | |
1253 | if (size < 20) \ | |
1254 | { \ | |
34208acf | 1255 | Twrite (2, "__trampoline_setup bad size\n", \ |
36a05131 BS |
1256 | sizeof ("__trampoline_setup bad size\n") - 1); \ |
1257 | exit (-1); \ | |
1258 | } \ | |
1259 | \ | |
1260 | to[0] = from[0]; \ | |
1261 | to[1] = (short)(fnaddr); \ | |
1262 | to[2] = from[2]; \ | |
1263 | to[3] = (short)(sc); \ | |
1264 | to[4] = from[4]; \ | |
1265 | to[5] = (short)(fnaddr >> 16); \ | |
1266 | to[6] = from[6]; \ | |
1267 | to[7] = (short)(sc >> 16); \ | |
1268 | to[8] = from[8]; \ | |
1269 | to[9] = from[9]; \ | |
1270 | \ | |
1271 | for (i = 0; i < 20; i++) \ | |
1272 | __asm__ volatile ("dcf @(%0,%1)\n\tici @(%0,%1)" :: "r" (to), "r" (i)); \ | |
1273 | } \ | |
1274 | \ | |
1275 | __asm__("\n" \ | |
1276 | "\t.globl " TRAMPOLINE_TEMPLATE_NAME "\n" \ | |
1277 | "\t.text\n" \ | |
1278 | TRAMPOLINE_TEMPLATE_NAME ":\n" \ | |
1279 | "\tsetlos #0, gr6\n" /* jump register */ \ | |
1280 | "\tsetlos #0, gr7\n" /* static chain */ \ | |
1281 | "\tsethi #0, gr6\n" \ | |
1282 | "\tsethi #0, gr7\n" \ | |
1283 | "\tjmpl @(gr0,gr6)\n"); | |
34208acf AO |
1284 | #else |
1285 | #define TRANSFER_FROM_TRAMPOLINE \ | |
1286 | extern int Twrite (int, const void *, unsigned); \ | |
1287 | \ | |
1288 | void \ | |
1289 | __trampoline_setup (addr, size, fnaddr, sc) \ | |
1290 | short * addr; \ | |
1291 | int size; \ | |
1292 | int fnaddr; \ | |
1293 | int sc; \ | |
1294 | { \ | |
1295 | extern short __trampoline_template[]; \ | |
1296 | short * from = &__trampoline_template[0]; \ | |
1297 | int i; \ | |
1298 | short **desc = (short **)addr; \ | |
1299 | short * to = addr + 4; \ | |
1300 | \ | |
1301 | if (size != 32) \ | |
1302 | { \ | |
1303 | Twrite (2, "__trampoline_setup bad size\n", \ | |
1304 | sizeof ("__trampoline_setup bad size\n") - 1); \ | |
1305 | exit (-1); \ | |
1306 | } \ | |
1307 | \ | |
6ef828bc MS |
1308 | /* Create a function descriptor with the address of the code below \ |
1309 | and NULL as the FDPIC value. We don't need the real GOT value \ | |
1310 | here, since we don't use it, so we use NULL, that is just as \ | |
34208acf AO |
1311 | good. */ \ |
1312 | desc[0] = to; \ | |
1313 | desc[1] = NULL; \ | |
1314 | size -= 8; \ | |
1315 | \ | |
1316 | to[0] = from[0]; \ | |
1317 | to[1] = (short)(fnaddr); \ | |
1318 | to[2] = from[2]; \ | |
1319 | to[3] = (short)(sc); \ | |
1320 | to[4] = from[4]; \ | |
1321 | to[5] = (short)(fnaddr >> 16); \ | |
1322 | to[6] = from[6]; \ | |
1323 | to[7] = (short)(sc >> 16); \ | |
1324 | to[8] = from[8]; \ | |
1325 | to[9] = from[9]; \ | |
1326 | to[10] = from[10]; \ | |
1327 | to[11] = from[11]; \ | |
1328 | \ | |
1329 | for (i = 0; i < size; i++) \ | |
1330 | __asm__ volatile ("dcf @(%0,%1)\n\tici @(%0,%1)" :: "r" (to), "r" (i)); \ | |
1331 | } \ | |
1332 | \ | |
1333 | __asm__("\n" \ | |
1334 | "\t.globl " TRAMPOLINE_TEMPLATE_NAME "\n" \ | |
1335 | "\t.text\n" \ | |
1336 | TRAMPOLINE_TEMPLATE_NAME ":\n" \ | |
1337 | "\tsetlos #0, gr6\n" /* Jump register. */ \ | |
1338 | "\tsetlos #0, gr7\n" /* Static chain. */ \ | |
1339 | "\tsethi #0, gr6\n" \ | |
1340 | "\tsethi #0, gr7\n" \ | |
1341 | "\tldd @(gr6,gr0),gr14\n" \ | |
1342 | "\tjmpl @(gr14,gr0)\n" \ | |
1343 | ); | |
1344 | #endif | |
36a05131 | 1345 | |
36a05131 BS |
1346 | \f |
1347 | /* Addressing Modes. */ | |
1348 | ||
36a05131 BS |
1349 | /* A number, the maximum number of registers that can appear in a valid memory |
1350 | address. Note that it is up to you to specify a value equal to the maximum | |
331d9186 | 1351 | number that `TARGET_LEGITIMATE_ADDRESS_P' would ever accept. */ |
36a05131 BS |
1352 | #define MAX_REGS_PER_ADDRESS 2 |
1353 | ||
36a05131 BS |
1354 | /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for |
1355 | use as a base register. For hard registers, it should always accept those | |
1356 | which the hardware permits and reject the others. Whether the macro accepts | |
1357 | or rejects pseudo registers must be controlled by `REG_OK_STRICT' as | |
1358 | described above. This usually requires two variant definitions, of which | |
1359 | `REG_OK_STRICT' controls the one actually used. */ | |
1360 | #ifdef REG_OK_STRICT | |
1361 | #define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X)) | |
1362 | #else | |
1363 | #define REG_OK_FOR_BASE_P(X) GPR_AP_OR_PSEUDO_P (REGNO (X)) | |
1364 | #endif | |
1365 | ||
1366 | /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for | |
1367 | use as an index register. | |
1368 | ||
1369 | The difference between an index register and a base register is that the | |
1370 | index register may be scaled. If an address involves the sum of two | |
1371 | registers, neither one of them scaled, then either one may be labeled the | |
1372 | "base" and the other the "index"; but whichever labeling is used must fit | |
1373 | the machine's constraints of which registers may serve in each capacity. | |
1374 | The compiler will try both labelings, looking for one that is valid, and | |
1375 | will reload one or both registers only if neither labeling works. */ | |
1376 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X) | |
1377 | ||
34208acf | 1378 | #define FIND_BASE_TERM frv_find_base_term |
36a05131 | 1379 | |
36a05131 BS |
1380 | /* The load-and-update commands allow pre-modification in addresses. |
1381 | The index has to be in a register. */ | |
1382 | #define HAVE_PRE_MODIFY_REG 1 | |
1383 | ||
1384 | \f | |
f1c9d07d EC |
1385 | /* We define extra CC modes in frv-modes.def so we need a selector. */ |
1386 | ||
036ff63f | 1387 | #define SELECT_CC_MODE frv_select_cc_mode |
36a05131 BS |
1388 | |
1389 | /* A C expression whose value is one if it is always safe to reverse a | |
1390 | comparison whose mode is MODE. If `SELECT_CC_MODE' can ever return MODE for | |
1391 | a floating-point inequality comparison, then `REVERSIBLE_CC_MODE (MODE)' | |
1392 | must be zero. | |
1393 | ||
1394 | You need not define this macro if it would always returns zero or if the | |
1395 | floating-point format is anything other than `IEEE_FLOAT_FORMAT'. For | |
981f6289 | 1396 | example, here is the definition used on the SPARC, where floating-point |
36a05131 BS |
1397 | inequality comparisons are always given `CCFPEmode': |
1398 | ||
1399 | #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) */ | |
1400 | ||
1401 | /* On frv, don't consider floating point comparisons to be reversible. In | |
87b483a1 | 1402 | theory, fp equality comparisons can be reversible. */ |
036ff63f RS |
1403 | #define REVERSIBLE_CC_MODE(MODE) \ |
1404 | ((MODE) == CCmode || (MODE) == CC_UNSmode || (MODE) == CC_NZmode) | |
36a05131 | 1405 | |
36a05131 BS |
1406 | \f |
1407 | /* Describing Relative Costs of Operations. */ | |
1408 | ||
36a05131 BS |
1409 | /* A C expression for the cost of a branch instruction. A value of 1 is the |
1410 | default; other values are interpreted relative to that. */ | |
3a4fd356 | 1411 | #define BRANCH_COST(speed_p, predictable_p) frv_branch_cost_int |
36a05131 BS |
1412 | |
1413 | /* Define this macro as a C expression which is nonzero if accessing less than | |
1414 | a word of memory (i.e. a `char' or a `short') is no faster than accessing a | |
1415 | word of memory, i.e., if such access require more than one instruction or if | |
1416 | there is no difference in cost between byte and (aligned) word loads. | |
1417 | ||
1418 | When this macro is not defined, the compiler will access a field by finding | |
1419 | the smallest containing object; when it is defined, a fullword load will be | |
1420 | used if alignment permits. Unless bytes accesses are faster than word | |
1421 | accesses, using word accesses is preferable since it may eliminate | |
1422 | subsequent memory access if subsequent accesses occur to other fields in the | |
1423 | same word of the structure, but to different bytes. */ | |
1424 | #define SLOW_BYTE_ACCESS 1 | |
1425 | ||
36a05131 BS |
1426 | /* Define this macro if it is as good or better to call a constant function |
1427 | address than to call an address kept in a register. */ | |
1e8552c2 | 1428 | #define NO_FUNCTION_CSE 1 |
36a05131 | 1429 | |
36a05131 BS |
1430 | \f |
1431 | /* Dividing the output into sections. */ | |
1432 | ||
1433 | /* A C expression whose value is a string containing the assembler operation | |
1434 | that should precede instructions and read-only data. Normally `".text"' is | |
1435 | right. */ | |
1436 | #define TEXT_SECTION_ASM_OP "\t.text" | |
1437 | ||
1438 | /* A C expression whose value is a string containing the assembler operation to | |
1439 | identify the following data as writable initialized data. Normally | |
1440 | `".data"' is right. */ | |
1441 | #define DATA_SECTION_ASM_OP "\t.data" | |
1442 | ||
36a05131 BS |
1443 | #define BSS_SECTION_ASM_OP "\t.section .bss,\"aw\"" |
1444 | ||
1445 | /* Short Data Support */ | |
1446 | #define SDATA_SECTION_ASM_OP "\t.section .sdata,\"aw\"" | |
36a05131 | 1447 | |
36a05131 BS |
1448 | #undef INIT_SECTION_ASM_OP |
1449 | #undef FINI_SECTION_ASM_OP | |
1450 | #define INIT_SECTION_ASM_OP "\t.section .init,\"ax\"" | |
1451 | #define FINI_SECTION_ASM_OP "\t.section .fini,\"ax\"" | |
1452 | ||
90a63880 RH |
1453 | #undef CTORS_SECTION_ASM_OP |
1454 | #undef DTORS_SECTION_ASM_OP | |
1455 | #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"a\"" | |
1456 | #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"a\"" | |
1457 | ||
36a05131 BS |
1458 | /* A C expression whose value is a string containing the assembler operation to |
1459 | switch to the fixup section that records all initialized pointers in a -fpic | |
1460 | program so they can be changed program startup time if the program is loaded | |
1461 | at a different address than linked for. */ | |
1462 | #define FIXUP_SECTION_ASM_OP "\t.section .rofixup,\"a\"" | |
36a05131 BS |
1463 | \f |
1464 | /* Position Independent Code. */ | |
1465 | ||
1466 | /* A C expression that is nonzero if X is a legitimate immediate operand on the | |
1467 | target machine when generating position independent code. You can assume | |
1468 | that X satisfies `CONSTANT_P', so you need not check this. You can also | |
1469 | assume FLAG_PIC is true, so you need not check it either. You need not | |
1470 | define this macro if all constants (including `SYMBOL_REF') can be immediate | |
1471 | operands when generating position independent code. */ | |
1472 | #define LEGITIMATE_PIC_OPERAND_P(X) \ | |
1473 | ( GET_CODE (X) == CONST_INT \ | |
1474 | || GET_CODE (X) == CONST_DOUBLE \ | |
1475 | || (GET_CODE (X) == HIGH && GET_CODE (XEXP (X, 0)) == CONST_INT) \ | |
6de9cd9a | 1476 | || got12_operand (X, VOIDmode)) \ |
36a05131 BS |
1477 | |
1478 | \f | |
1479 | /* The Overall Framework of an Assembler File. */ | |
1480 | ||
1481 | /* A C string constant describing how to begin a comment in the target | |
1482 | assembler language. The compiler assumes that the comment will end at the | |
1483 | end of the line. */ | |
1484 | #define ASM_COMMENT_START ";" | |
1485 | ||
1486 | /* A C string constant for text to be output before each `asm' statement or | |
1487 | group of consecutive ones. Normally this is `"#APP"', which is a comment | |
1488 | that has no effect on most assemblers but tells the GNU assembler that it | |
1489 | must check the lines that follow for all valid assembler constructs. */ | |
1490 | #define ASM_APP_ON "#APP\n" | |
1491 | ||
1492 | /* A C string constant for text to be output after each `asm' statement or | |
1493 | group of consecutive ones. Normally this is `"#NO_APP"', which tells the | |
1494 | GNU assembler to resume making the time-saving assumptions that are valid | |
1495 | for ordinary compiler output. */ | |
1496 | #define ASM_APP_OFF "#NO_APP\n" | |
1497 | ||
1498 | \f | |
1499 | /* Output of Data. */ | |
1500 | ||
1501 | /* This is how to output a label to dwarf/dwarf2. */ | |
1502 | #define ASM_OUTPUT_DWARF_ADDR(STREAM, LABEL) \ | |
1503 | do { \ | |
1504 | fprintf (STREAM, "\t.picptr\t"); \ | |
1505 | assemble_name (STREAM, LABEL); \ | |
1506 | } while (0) | |
1507 | ||
1508 | /* Whether to emit the gas specific dwarf2 line number support. */ | |
1509 | #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DEBUG_LOC) | |
1510 | \f | |
1511 | /* Output of Uninitialized Variables. */ | |
1512 | ||
1513 | /* A C statement (sans semicolon) to output to the stdio stream STREAM the | |
1514 | assembler definition of a local-common-label named NAME whose size is SIZE | |
1515 | bytes. The variable ROUNDED is the size rounded up to whatever alignment | |
1516 | the caller wants. | |
1517 | ||
1518 | Use the expression `assemble_name (STREAM, NAME)' to output the name itself; | |
1519 | before and after that, output the additional assembler syntax for defining | |
1520 | the name, and a newline. | |
1521 | ||
1522 | This macro controls how the assembler definitions of uninitialized static | |
1523 | variables are output. */ | |
1524 | #undef ASM_OUTPUT_LOCAL | |
1525 | ||
36a05131 BS |
1526 | #undef ASM_OUTPUT_ALIGNED_LOCAL |
1527 | ||
e53b6e56 | 1528 | /* This is for final.cc, because it is used by ASM_DECLARE_OBJECT_NAME. */ |
36a05131 BS |
1529 | extern int size_directive_output; |
1530 | ||
1531 | /* Like `ASM_OUTPUT_ALIGNED_LOCAL' except that it takes an additional | |
1532 | parameter - the DECL of variable to be output, if there is one. | |
1533 | This macro can be called with DECL == NULL_TREE. If you define | |
1534 | this macro, it is used in place of `ASM_OUTPUT_LOCAL' and | |
1535 | `ASM_OUTPUT_ALIGNED_LOCAL', and gives you more flexibility in | |
1536 | handling the destination of the variable. */ | |
1537 | #undef ASM_OUTPUT_ALIGNED_DECL_LOCAL | |
1538 | #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGN) \ | |
1539 | do { \ | |
fa37ed29 | 1540 | if ((SIZE) > 0 && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \ |
d6b5193b | 1541 | switch_to_section (get_named_section (NULL, ".sbss", 0)); \ |
36a05131 | 1542 | else \ |
d6b5193b | 1543 | switch_to_section (bss_section); \ |
36a05131 BS |
1544 | ASM_OUTPUT_ALIGN (STREAM, floor_log2 ((ALIGN) / BITS_PER_UNIT)); \ |
1545 | ASM_DECLARE_OBJECT_NAME (STREAM, NAME, DECL); \ | |
1546 | ASM_OUTPUT_SKIP (STREAM, (SIZE) ? (SIZE) : 1); \ | |
1547 | } while (0) | |
1548 | ||
1549 | \f | |
1550 | /* Output and Generation of Labels. */ | |
1551 | ||
1552 | /* A C statement (sans semicolon) to output to the stdio stream STREAM the | |
1553 | assembler definition of a label named NAME. Use the expression | |
1554 | `assemble_name (STREAM, NAME)' to output the name itself; before and after | |
1555 | that, output the additional assembler syntax for defining the name, and a | |
1556 | newline. */ | |
1557 | #define ASM_OUTPUT_LABEL(STREAM, NAME) \ | |
1558 | do { \ | |
1559 | assemble_name (STREAM, NAME); \ | |
1560 | fputs (":\n", STREAM); \ | |
1561 | } while (0) | |
1562 | ||
5eb99654 KG |
1563 | /* Globalizing directive for a label. */ |
1564 | #define GLOBAL_ASM_OP "\t.globl " | |
36a05131 | 1565 | |
36a05131 BS |
1566 | #undef ASM_GENERATE_INTERNAL_LABEL |
1567 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ | |
1568 | do { \ | |
1569 | sprintf (LABEL, "*.%s%ld", PREFIX, (long)NUM); \ | |
1570 | } while (0) | |
1571 | ||
36a05131 BS |
1572 | \f |
1573 | /* Macros Controlling Initialization Routines. */ | |
1574 | ||
36a05131 BS |
1575 | #undef INIT_SECTION_ASM_OP |
1576 | ||
1577 | /* If defined, `main' will call `__main' despite the presence of | |
1578 | `INIT_SECTION_ASM_OP'. This macro should be defined for systems where the | |
1579 | init section is not actually run automatically, but is still useful for | |
1580 | collecting the lists of constructors and destructors. */ | |
1581 | #define INVOKE__main | |
36a05131 BS |
1582 | \f |
1583 | /* Output of Assembler Instructions. */ | |
1584 | ||
1585 | /* A C initializer containing the assembler's names for the machine registers, | |
1586 | each one as a C string constant. This is what translates register numbers | |
1587 | in the compiler into assembler language. */ | |
1588 | #define REGISTER_NAMES \ | |
1589 | { \ | |
1590 | "gr0", "sp", "fp", "gr3", "gr4", "gr5", "gr6", "gr7", \ | |
1591 | "gr8", "gr9", "gr10", "gr11", "gr12", "gr13", "gr14", "gr15", \ | |
1592 | "gr16", "gr17", "gr18", "gr19", "gr20", "gr21", "gr22", "gr23", \ | |
1593 | "gr24", "gr25", "gr26", "gr27", "gr28", "gr29", "gr30", "gr31", \ | |
1594 | "gr32", "gr33", "gr34", "gr35", "gr36", "gr37", "gr38", "gr39", \ | |
1595 | "gr40", "gr41", "gr42", "gr43", "gr44", "gr45", "gr46", "gr47", \ | |
1596 | "gr48", "gr49", "gr50", "gr51", "gr52", "gr53", "gr54", "gr55", \ | |
1597 | "gr56", "gr57", "gr58", "gr59", "gr60", "gr61", "gr62", "gr63", \ | |
1598 | \ | |
1599 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \ | |
1600 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \ | |
1601 | "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \ | |
1602 | "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \ | |
1603 | "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \ | |
1604 | "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \ | |
1605 | "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \ | |
1606 | "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \ | |
1607 | \ | |
1608 | "fcc0", "fcc1", "fcc2", "fcc3", "icc0", "icc1", "icc2", "icc3", \ | |
1609 | "cc0", "cc1", "cc2", "cc3", "cc4", "cc5", "cc6", "cc7", \ | |
1610 | "acc0", "acc1", "acc2", "acc3", "acc4", "acc5", "acc6", "acc7", \ | |
c557edf4 | 1611 | "acc8", "acc9", "acc10", "acc11", \ |
36a05131 | 1612 | "accg0","accg1","accg2","accg3","accg4","accg5","accg6","accg7", \ |
c557edf4 RS |
1613 | "accg8", "accg9", "accg10", "accg11", \ |
1614 | "ap", "lr", "lcr", "iacc0h", "iacc0l" \ | |
36a05131 BS |
1615 | } |
1616 | ||
1617 | /* Define this macro if you are using an unusual assembler that | |
1618 | requires different names for the machine instructions. | |
1619 | ||
1620 | The definition is a C statement or statements which output an | |
1621 | assembler instruction opcode to the stdio stream STREAM. The | |
1622 | macro-operand PTR is a variable of type `char *' which points to | |
1623 | the opcode name in its "internal" form--the form that is written | |
1624 | in the machine description. The definition should output the | |
1625 | opcode name to STREAM, performing any translation you desire, and | |
1626 | increment the variable PTR to point at the end of the opcode so | |
1627 | that it will not be output twice. | |
1628 | ||
1629 | In fact, your macro definition may process less than the entire | |
1630 | opcode name, or more than the opcode name; but if you want to | |
1631 | process text that includes `%'-sequences to substitute operands, | |
1632 | you must take care of the substitution yourself. Just be sure to | |
1633 | increment PTR over whatever text should not be output normally. | |
1634 | ||
1635 | If you need to look at the operand values, they can be found as the | |
1636 | elements of `recog_operand'. | |
1637 | ||
1638 | If the macro definition does nothing, the instruction is output in | |
1639 | the usual way. */ | |
1640 | ||
1641 | #define ASM_OUTPUT_OPCODE(STREAM, PTR)\ | |
1642 | (PTR) = frv_asm_output_opcode (STREAM, PTR) | |
1643 | ||
1644 | /* If defined, a C statement to be executed just prior to the output | |
1645 | of assembler code for INSN, to modify the extracted operands so | |
1646 | they will be output differently. | |
1647 | ||
1648 | Here the argument OPVEC is the vector containing the operands | |
1649 | extracted from INSN, and NOPERANDS is the number of elements of | |
1650 | the vector which contain meaningful data for this insn. The | |
1651 | contents of this vector are what will be used to convert the insn | |
1652 | template into assembler code, so you can change the assembler | |
1653 | output by changing the contents of the vector. | |
1654 | ||
1655 | This macro is useful when various assembler syntaxes share a single | |
1656 | file of instruction patterns; by defining this macro differently, | |
1657 | you can cause a large class of instructions to be output | |
1658 | differently (such as with rearranged operands). Naturally, | |
1659 | variations in assembler syntax affecting individual insn patterns | |
1660 | ought to be handled by writing conditional output routines in | |
1661 | those patterns. | |
1662 | ||
1663 | If this macro is not defined, it is equivalent to a null statement. */ | |
1664 | ||
1665 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)\ | |
1666 | frv_final_prescan_insn (INSN, OPVEC, NOPERANDS) | |
1667 | ||
36a05131 BS |
1668 | #undef USER_LABEL_PREFIX |
1669 | #define USER_LABEL_PREFIX "" | |
1670 | #define REGISTER_PREFIX "" | |
1671 | #define LOCAL_LABEL_PREFIX "." | |
1672 | #define IMMEDIATE_PREFIX "#" | |
1673 | ||
1674 | \f | |
1675 | /* Output of dispatch tables. */ | |
1676 | ||
1677 | /* This macro should be provided on machines where the addresses in a dispatch | |
1678 | table are relative to the table's own address. | |
1679 | ||
1680 | The definition should be a C statement to output to the stdio stream STREAM | |
1681 | an assembler pseudo-instruction to generate a difference between two labels. | |
1682 | VALUE and REL are the numbers of two internal labels. The definitions of | |
4977bab6 | 1683 | these labels are output using `(*targetm.asm_out.internal_label)', and they must be |
36a05131 BS |
1684 | printed in the same way here. For example, |
1685 | ||
1686 | fprintf (STREAM, "\t.word L%d-L%d\n", VALUE, REL) */ | |
1687 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ | |
1688 | fprintf (STREAM, "\t.word .L%d-.L%d\n", VALUE, REL) | |
1689 | ||
1690 | /* This macro should be provided on machines where the addresses in a dispatch | |
1691 | table are absolute. | |
1692 | ||
1693 | The definition should be a C statement to output to the stdio stream STREAM | |
1694 | an assembler pseudo-instruction to generate a reference to a label. VALUE | |
1695 | is the number of an internal label whose definition is output using | |
4977bab6 | 1696 | `(*targetm.asm_out.internal_label)'. For example, |
36a05131 BS |
1697 | |
1698 | fprintf (STREAM, "\t.word L%d\n", VALUE) */ | |
1699 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ | |
1700 | fprintf (STREAM, "\t.word .L%d\n", VALUE) | |
1701 | ||
e133c867 | 1702 | #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic) |
36a05131 BS |
1703 | \f |
1704 | /* Assembler Commands for Exception Regions. */ | |
1705 | ||
1706 | /* Define this macro to 0 if your target supports DWARF 2 frame unwind | |
1707 | information, but it does not yet work with exception handling. Otherwise, | |
1708 | if your target supports this information (if it defines | |
01a07a64 SB |
1709 | `INCOMING_RETURN_ADDR_RTX' and `OBJECT_FORMAT_ELF'), GCC will provide |
1710 | a default definition of 1. | |
36a05131 BS |
1711 | |
1712 | If this macro is defined to 1, the DWARF 2 unwinder will be the default | |
1713 | exception handling mechanism; otherwise, setjmp/longjmp will be used by | |
1714 | default. | |
1715 | ||
1716 | If this macro is defined to anything, the DWARF 2 unwinder will be used | |
1717 | instead of inline unwinders and __unwind_function in the non-setjmp case. */ | |
1718 | #define DWARF2_UNWIND_INFO 1 | |
1719 | ||
1720 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO) | |
1721 | \f | |
1722 | /* Assembler Commands for Alignment. */ | |
1723 | ||
36a05131 BS |
1724 | #undef ASM_OUTPUT_SKIP |
1725 | #define ASM_OUTPUT_SKIP(STREAM, NBYTES) \ | |
58e15542 | 1726 | fprintf (STREAM, "\t.zero\t%u\n", (int)(NBYTES)) |
36a05131 BS |
1727 | |
1728 | /* A C statement to output to the stdio stream STREAM an assembler command to | |
1729 | advance the location counter to a multiple of 2 to the POWER bytes. POWER | |
1730 | will be a C expression of type `int'. */ | |
1731 | #define ASM_OUTPUT_ALIGN(STREAM, POWER) \ | |
1732 | fprintf ((STREAM), "\t.p2align %d\n", (POWER)) | |
1733 | ||
def49dc4 RS |
1734 | /* Inside the text section, align with unpacked nops rather than zeros. */ |
1735 | #define ASM_OUTPUT_ALIGN_WITH_NOP(STREAM, POWER) \ | |
1736 | fprintf ((STREAM), "\t.p2alignl %d,0x80880000\n", (POWER)) | |
36a05131 BS |
1737 | \f |
1738 | /* Macros Affecting all Debug Formats. */ | |
1739 | ||
1740 | /* A C expression that returns the DBX register number for the compiler | |
1741 | register number REGNO. In simple cases, the value of this expression may be | |
1742 | REGNO itself. But sometimes there are some registers that the compiler | |
1743 | knows about and DBX does not, or vice versa. In such cases, some register | |
1744 | may need to have one number in the compiler and another for DBX. | |
1745 | ||
7ec022b2 | 1746 | If two registers have consecutive numbers inside GCC, and they can be |
36a05131 BS |
1747 | used as a pair to hold a multiword value, then they *must* have consecutive |
1748 | numbers after renumbering with `DBX_REGISTER_NUMBER'. Otherwise, debuggers | |
1749 | will be unable to access such a pair, because they expect register pairs to | |
1750 | be consecutive in their own numbering scheme. | |
1751 | ||
1752 | If you find yourself defining `DBX_REGISTER_NUMBER' in way that does not | |
1753 | preserve register pairs, then what you must do instead is redefine the | |
1754 | actual register numbering scheme. | |
1755 | ||
1756 | This declaration is required. */ | |
1757 | #define DBX_REGISTER_NUMBER(REGNO) (REGNO) | |
1758 | ||
36a05131 BS |
1759 | #undef PREFERRED_DEBUGGING_TYPE |
1760 | #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG | |
36a05131 BS |
1761 | \f |
1762 | /* Miscellaneous Parameters. */ | |
1763 | ||
36a05131 BS |
1764 | /* An alias for a machine mode name. This is the machine mode that elements of |
1765 | a jump-table should have. */ | |
1766 | #define CASE_VECTOR_MODE SImode | |
1767 | ||
1768 | /* Define this macro if operations between registers with integral mode smaller | |
1769 | than a word are always performed on the entire register. Most RISC machines | |
1770 | have this property and most CISC machines do not. */ | |
9e11bfef | 1771 | #define WORD_REGISTER_OPERATIONS 1 |
36a05131 BS |
1772 | |
1773 | /* Define this macro to be a C expression indicating when insns that read | |
1774 | memory in MODE, an integral mode narrower than a word, set the bits outside | |
1775 | of MODE to be either the sign-extension or the zero-extension of the data | |
1776 | read. Return `SIGN_EXTEND' for values of MODE for which the insn | |
f822d252 | 1777 | sign-extends, `ZERO_EXTEND' for which it zero-extends, and `UNKNOWN' for other |
36a05131 BS |
1778 | modes. |
1779 | ||
1780 | This macro is not called with MODE non-integral or with a width greater than | |
1781 | or equal to `BITS_PER_WORD', so you may return any value in this case. Do | |
f822d252 | 1782 | not define this macro if it would always return `UNKNOWN'. On machines where |
36a05131 BS |
1783 | this macro is defined, you will normally define it as the constant |
1784 | `SIGN_EXTEND' or `ZERO_EXTEND'. */ | |
1785 | #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND | |
1786 | ||
1787 | /* Define if loading short immediate values into registers sign extends. */ | |
58f2ae18 | 1788 | #define SHORT_IMMEDIATES_SIGN_EXTEND 1 |
36a05131 | 1789 | |
36a05131 BS |
1790 | /* The maximum number of bytes that a single instruction can move quickly from |
1791 | memory to memory. */ | |
1792 | #define MOVE_MAX 8 | |
1793 | ||
36a05131 BS |
1794 | /* An alias for the machine mode for pointers. On most machines, define this |
1795 | to be the integer mode corresponding to the width of a hardware pointer; | |
1796 | `SImode' on 32-bit machine or `DImode' on 64-bit machines. On some machines | |
1797 | you must define this to be one of the partial integer modes, such as | |
1798 | `PSImode'. | |
1799 | ||
1800 | The width of `Pmode' must be at least as large as the value of | |
1801 | `POINTER_SIZE'. If it is not equal, you must define the macro | |
1802 | `POINTERS_EXTEND_UNSIGNED' to specify how pointers are extended to `Pmode'. */ | |
1803 | #define Pmode SImode | |
1804 | ||
1805 | /* An alias for the machine mode used for memory references to functions being | |
1806 | called, in `call' RTL expressions. On most machines this should be | |
1807 | `QImode'. */ | |
1808 | #define FUNCTION_MODE QImode | |
1809 | ||
36a05131 BS |
1810 | /* A C expression for the maximum number of instructions to execute via |
1811 | conditional execution instructions instead of a branch. A value of | |
1812 | BRANCH_COST+1 is the default if the machine does not use | |
1813 | cc0, and 1 if it does use cc0. */ | |
1814 | #define MAX_CONDITIONAL_EXECUTE frv_condexec_insns | |
1815 | ||
36a05131 BS |
1816 | /* A C expression to modify the code described by the conditional if |
1817 | information CE_INFO, possibly updating the tests in TRUE_EXPR, and | |
1818 | FALSE_EXPR for converting if-then and if-then-else code to conditional | |
1819 | instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the | |
1820 | tests cannot be converted. */ | |
1821 | #define IFCVT_MODIFY_TESTS(CE_INFO, TRUE_EXPR, FALSE_EXPR) \ | |
1822 | frv_ifcvt_modify_tests (CE_INFO, &TRUE_EXPR, &FALSE_EXPR) | |
1823 | ||
1824 | /* A C expression to modify the code described by the conditional if | |
1825 | information CE_INFO, for the basic block BB, possibly updating the tests in | |
1826 | TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or | |
1827 | if-then-else code to conditional instructions. OLD_TRUE and OLD_FALSE are | |
1828 | the previous tests. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if | |
1829 | the tests cannot be converted. */ | |
1830 | #define IFCVT_MODIFY_MULTIPLE_TESTS(CE_INFO, BB, TRUE_EXPR, FALSE_EXPR) \ | |
1831 | frv_ifcvt_modify_multiple_tests (CE_INFO, BB, &TRUE_EXPR, &FALSE_EXPR) | |
1832 | ||
1833 | /* A C expression to modify the code described by the conditional if | |
1834 | information CE_INFO with the new PATTERN in INSN. If PATTERN is a null | |
1835 | pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that | |
1836 | insn cannot be converted to be executed conditionally. */ | |
1837 | #define IFCVT_MODIFY_INSN(CE_INFO, PATTERN, INSN) \ | |
1838 | (PATTERN) = frv_ifcvt_modify_insn (CE_INFO, PATTERN, INSN) | |
1839 | ||
1840 | /* A C expression to perform any final machine dependent modifications in | |
1841 | converting code to conditional execution in the code described by the | |
1842 | conditional if information CE_INFO. */ | |
1843 | #define IFCVT_MODIFY_FINAL(CE_INFO) frv_ifcvt_modify_final (CE_INFO) | |
1844 | ||
1845 | /* A C expression to cancel any machine dependent modifications in converting | |
1846 | code to conditional execution in the code described by the conditional if | |
1847 | information CE_INFO. */ | |
1848 | #define IFCVT_MODIFY_CANCEL(CE_INFO) frv_ifcvt_modify_cancel (CE_INFO) | |
1849 | ||
67a0732f SB |
1850 | /* Initialize the machine-specific static data for if-conversion. */ |
1851 | #define IFCVT_MACHDEP_INIT(CE_INFO) frv_ifcvt_machdep_init (CE_INFO) | |
36a05131 | 1852 | |
36a05131 BS |
1853 | /* The definition of the following macro results in that the 2nd jump |
1854 | optimization (after the 2nd insn scheduling) is minimal. It is | |
1855 | necessary to define when start cycle marks of insns (TImode is used | |
1856 | for this) is used for VLIW insn packing. Some jump optimizations | |
1857 | make such marks invalid. These marks are corrected for some | |
1858 | (minimal) optimizations. ??? Probably the macro is temporary. | |
1859 | Final solution could making the 2nd jump optimizations before the | |
1860 | 2nd instruction scheduling or corrections of the marks for all jump | |
1861 | optimizations. Although some jump optimizations are actually | |
1862 | deoptimizations for VLIW (super-scalar) processors. */ | |
1863 | ||
1864 | #define MINIMAL_SECOND_JUMP_OPTIMIZATION | |
1865 | ||
36a05131 | 1866 | |
88cad84b | 1867 | /* If the following macro is defined and nonzero and deterministic |
36a05131 BS |
1868 | finite state automata are used for pipeline hazard recognition, we |
1869 | will try to exchange insns in queue ready to improve the schedule. | |
1870 | The more macro value, the more tries will be made. */ | |
1871 | #define FIRST_CYCLE_MULTIPASS_SCHEDULING 1 | |
1872 | ||
1873 | /* The following macro is used only when value of | |
1874 | FIRST_CYCLE_MULTIPASS_SCHEDULING is nonzero. The more macro value, | |
1875 | the more tries will be made to choose better schedule. If the | |
1876 | macro value is zero or negative there will be no multi-pass | |
1877 | scheduling. */ | |
1878 | #define FIRST_CYCLE_MULTIPASS_SCHEDULING_LOOKAHEAD frv_sched_lookahead | |
1879 | ||
36a05131 BS |
1880 | enum frv_builtins |
1881 | { | |
1882 | FRV_BUILTIN_MAND, | |
1883 | FRV_BUILTIN_MOR, | |
1884 | FRV_BUILTIN_MXOR, | |
1885 | FRV_BUILTIN_MNOT, | |
1886 | FRV_BUILTIN_MAVEH, | |
1887 | FRV_BUILTIN_MSATHS, | |
1888 | FRV_BUILTIN_MSATHU, | |
1889 | FRV_BUILTIN_MADDHSS, | |
1890 | FRV_BUILTIN_MADDHUS, | |
1891 | FRV_BUILTIN_MSUBHSS, | |
1892 | FRV_BUILTIN_MSUBHUS, | |
1893 | FRV_BUILTIN_MPACKH, | |
1894 | FRV_BUILTIN_MQADDHSS, | |
1895 | FRV_BUILTIN_MQADDHUS, | |
1896 | FRV_BUILTIN_MQSUBHSS, | |
1897 | FRV_BUILTIN_MQSUBHUS, | |
1898 | FRV_BUILTIN_MUNPACKH, | |
1899 | FRV_BUILTIN_MDPACKH, | |
1900 | FRV_BUILTIN_MBTOH, | |
1901 | FRV_BUILTIN_MHTOB, | |
1902 | FRV_BUILTIN_MCOP1, | |
1903 | FRV_BUILTIN_MCOP2, | |
1904 | FRV_BUILTIN_MROTLI, | |
1905 | FRV_BUILTIN_MROTRI, | |
1906 | FRV_BUILTIN_MWCUT, | |
1907 | FRV_BUILTIN_MSLLHI, | |
1908 | FRV_BUILTIN_MSRLHI, | |
1909 | FRV_BUILTIN_MSRAHI, | |
1910 | FRV_BUILTIN_MEXPDHW, | |
1911 | FRV_BUILTIN_MEXPDHD, | |
1912 | FRV_BUILTIN_MMULHS, | |
1913 | FRV_BUILTIN_MMULHU, | |
1914 | FRV_BUILTIN_MMULXHS, | |
1915 | FRV_BUILTIN_MMULXHU, | |
1916 | FRV_BUILTIN_MMACHS, | |
1917 | FRV_BUILTIN_MMACHU, | |
1918 | FRV_BUILTIN_MMRDHS, | |
1919 | FRV_BUILTIN_MMRDHU, | |
1920 | FRV_BUILTIN_MQMULHS, | |
1921 | FRV_BUILTIN_MQMULHU, | |
1922 | FRV_BUILTIN_MQMULXHU, | |
1923 | FRV_BUILTIN_MQMULXHS, | |
1924 | FRV_BUILTIN_MQMACHS, | |
1925 | FRV_BUILTIN_MQMACHU, | |
1926 | FRV_BUILTIN_MCPXRS, | |
1927 | FRV_BUILTIN_MCPXRU, | |
1928 | FRV_BUILTIN_MCPXIS, | |
1929 | FRV_BUILTIN_MCPXIU, | |
1930 | FRV_BUILTIN_MQCPXRS, | |
1931 | FRV_BUILTIN_MQCPXRU, | |
1932 | FRV_BUILTIN_MQCPXIS, | |
1933 | FRV_BUILTIN_MQCPXIU, | |
1934 | FRV_BUILTIN_MCUT, | |
1935 | FRV_BUILTIN_MCUTSS, | |
1936 | FRV_BUILTIN_MWTACC, | |
1937 | FRV_BUILTIN_MWTACCG, | |
1938 | FRV_BUILTIN_MRDACC, | |
1939 | FRV_BUILTIN_MRDACCG, | |
1940 | FRV_BUILTIN_MTRAP, | |
1941 | FRV_BUILTIN_MCLRACC, | |
1942 | FRV_BUILTIN_MCLRACCA, | |
1943 | FRV_BUILTIN_MDUNPACKH, | |
1944 | FRV_BUILTIN_MBTOHE, | |
1945 | FRV_BUILTIN_MQXMACHS, | |
1946 | FRV_BUILTIN_MQXMACXHS, | |
1947 | FRV_BUILTIN_MQMACXHS, | |
1948 | FRV_BUILTIN_MADDACCS, | |
1949 | FRV_BUILTIN_MSUBACCS, | |
1950 | FRV_BUILTIN_MASACCS, | |
1951 | FRV_BUILTIN_MDADDACCS, | |
1952 | FRV_BUILTIN_MDSUBACCS, | |
1953 | FRV_BUILTIN_MDASACCS, | |
1954 | FRV_BUILTIN_MABSHS, | |
1955 | FRV_BUILTIN_MDROTLI, | |
1956 | FRV_BUILTIN_MCPLHI, | |
1957 | FRV_BUILTIN_MCPLI, | |
1958 | FRV_BUILTIN_MDCUTSSI, | |
1959 | FRV_BUILTIN_MQSATHS, | |
c557edf4 RS |
1960 | FRV_BUILTIN_MQLCLRHS, |
1961 | FRV_BUILTIN_MQLMTHS, | |
1962 | FRV_BUILTIN_MQSLLHI, | |
1963 | FRV_BUILTIN_MQSRAHI, | |
36a05131 BS |
1964 | FRV_BUILTIN_MHSETLOS, |
1965 | FRV_BUILTIN_MHSETLOH, | |
1966 | FRV_BUILTIN_MHSETHIS, | |
1967 | FRV_BUILTIN_MHSETHIH, | |
1968 | FRV_BUILTIN_MHDSETS, | |
c557edf4 RS |
1969 | FRV_BUILTIN_MHDSETH, |
1970 | FRV_BUILTIN_SMUL, | |
1971 | FRV_BUILTIN_UMUL, | |
1972 | FRV_BUILTIN_PREFETCH0, | |
1973 | FRV_BUILTIN_PREFETCH, | |
1974 | FRV_BUILTIN_SMASS, | |
1975 | FRV_BUILTIN_SMSSS, | |
1976 | FRV_BUILTIN_SMU, | |
1977 | FRV_BUILTIN_SCUTSS, | |
1978 | FRV_BUILTIN_ADDSS, | |
1979 | FRV_BUILTIN_SUBSS, | |
1980 | FRV_BUILTIN_SLASS, | |
1981 | FRV_BUILTIN_IACCreadll, | |
1982 | FRV_BUILTIN_IACCreadl, | |
1983 | FRV_BUILTIN_IACCsetll, | |
1984 | FRV_BUILTIN_IACCsetl, | |
c14ff86e AH |
1985 | FRV_BUILTIN_SCAN, |
1986 | FRV_BUILTIN_READ8, | |
1987 | FRV_BUILTIN_READ16, | |
1988 | FRV_BUILTIN_READ32, | |
1989 | FRV_BUILTIN_READ64, | |
1990 | FRV_BUILTIN_WRITE8, | |
1991 | FRV_BUILTIN_WRITE16, | |
1992 | FRV_BUILTIN_WRITE32, | |
1993 | FRV_BUILTIN_WRITE64 | |
36a05131 | 1994 | }; |
c557edf4 | 1995 | #define FRV_BUILTIN_FIRST_NONMEDIA FRV_BUILTIN_SMUL |
36a05131 | 1996 | |
36a05131 BS |
1997 | /* Enable prototypes on the call rtl functions. */ |
1998 | #define MD_CALL_PROTOTYPES 1 | |
1999 | ||
c557edf4 RS |
2000 | #define CPU_UNITS_QUERY 1 |
2001 | ||
36a05131 | 2002 | #endif /* __FRV_H__ */ |