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7adcbafe | 1 | /* Copyright (C) 2016-2022 Free Software Foundation, Inc. |
5326695a AS |
2 | |
3 | This file is free software; you can redistribute it and/or modify it under | |
4 | the terms of the GNU General Public License as published by the Free | |
5 | Software Foundation; either version 3 of the License, or (at your option) | |
6 | any later version. | |
7 | ||
8 | This file is distributed in the hope that it will be useful, but WITHOUT | |
9 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
11 | for more details. | |
12 | ||
13 | You should have received a copy of the GNU General Public License | |
14 | along with GCC; see the file COPYING3. If not see | |
15 | <http://www.gnu.org/licenses/>. */ | |
16 | ||
17 | #ifndef _GCN_PROTOS_ | |
18 | #define _GCN_PROTOS_ | |
19 | ||
20 | extern void gcn_asm_output_symbol_ref (FILE *file, rtx x); | |
21 | extern tree gcn_builtin_decl (unsigned code, bool initialize_p); | |
22 | extern bool gcn_can_split_p (machine_mode, rtx); | |
23 | extern bool gcn_constant64_p (rtx); | |
24 | extern bool gcn_constant_p (rtx); | |
25 | extern rtx gcn_convert_mask_mode (rtx reg); | |
eff23b79 | 26 | extern unsigned int gcn_dwarf_register_number (unsigned int regno); |
5326695a AS |
27 | extern char * gcn_expand_dpp_shr_insn (machine_mode, const char *, int, int); |
28 | extern void gcn_expand_epilogue (); | |
29 | extern rtx gcn_expand_scaled_offsets (addr_space_t as, rtx base, rtx offsets, | |
30 | rtx scale, bool unsigned_p, rtx exec); | |
31 | extern void gcn_expand_prologue (); | |
32 | extern rtx gcn_expand_reduc_scalar (machine_mode, rtx, int); | |
33 | extern rtx gcn_expand_scalar_to_vector_address (machine_mode, rtx, rtx, rtx); | |
34 | extern void gcn_expand_vector_init (rtx, rtx); | |
35 | extern bool gcn_flat_address_p (rtx, machine_mode); | |
36 | extern bool gcn_fp_constant_p (rtx, bool); | |
37 | extern rtx gcn_full_exec (); | |
38 | extern rtx gcn_full_exec_reg (); | |
39 | extern rtx gcn_gen_undef (machine_mode); | |
40 | extern bool gcn_global_address_p (rtx); | |
11b8286a | 41 | extern tree gcn_goacc_adjust_private_decl (location_t, tree var, int level); |
e2a58ed6 JB |
42 | extern tree gcn_goacc_create_worker_broadcast_record (tree record_type, |
43 | bool sender, | |
2a3f9f65 JB |
44 | const char *name, |
45 | unsigned HOST_WIDE_INT offset); | |
5326695a AS |
46 | extern void gcn_goacc_reduction (gcall *call); |
47 | extern bool gcn_hard_regno_rename_ok (unsigned int from_reg, | |
48 | unsigned int to_reg); | |
49 | extern machine_mode gcn_hard_regno_caller_save_mode (unsigned int regno, | |
50 | unsigned int nregs, | |
51 | machine_mode regmode); | |
52 | extern bool gcn_hard_regno_mode_ok (int regno, machine_mode mode); | |
53 | extern int gcn_hard_regno_nregs (int regno, machine_mode mode); | |
54 | extern void gcn_hsa_declare_function_name (FILE *file, const char *name, | |
55 | tree decl); | |
56 | extern HOST_WIDE_INT gcn_initial_elimination_offset (int, int); | |
66b01cc3 | 57 | extern bool gcn_inline_constant64_p (rtx, bool); |
5326695a AS |
58 | extern bool gcn_inline_constant_p (rtx); |
59 | extern int gcn_inline_fp_constant_p (rtx, bool); | |
60 | extern reg_class gcn_mode_code_base_reg_class (machine_mode, addr_space_t, | |
61 | int, int); | |
62 | extern rtx gcn_oacc_dim_pos (int dim); | |
63 | extern rtx gcn_oacc_dim_size (int dim); | |
64 | extern rtx gcn_operand_doublepart (machine_mode, rtx, int); | |
65 | extern rtx gcn_operand_part (machine_mode, rtx, int); | |
66 | extern bool gcn_regno_mode_code_ok_for_base_p (int, machine_mode, | |
67 | addr_space_t, int, int); | |
68 | extern reg_class gcn_regno_reg_class (int regno); | |
69 | extern rtx gcn_scalar_exec (); | |
70 | extern rtx gcn_scalar_exec_reg (); | |
71 | extern bool gcn_scalar_flat_address_p (rtx); | |
72 | extern bool gcn_scalar_flat_mem_p (rtx); | |
73 | extern bool gcn_sgpr_move_p (rtx, rtx); | |
74 | extern bool gcn_valid_move_p (machine_mode, rtx, rtx); | |
75 | extern rtx gcn_vec_constant (machine_mode, int); | |
76 | extern rtx gcn_vec_constant (machine_mode, rtx); | |
77 | extern bool gcn_vgpr_move_p (rtx, rtx); | |
78 | extern void print_operand_address (FILE *file, register rtx addr); | |
79 | extern void print_operand (FILE *file, rtx x, int code); | |
80 | extern bool regno_ok_for_index_p (int); | |
81 | ||
82 | enum gcn_cvt_t | |
83 | { | |
84 | fix_trunc_cvt, | |
85 | fixuns_trunc_cvt, | |
86 | float_cvt, | |
87 | floatuns_cvt, | |
88 | extend_cvt, | |
89 | trunc_cvt | |
90 | }; | |
91 | ||
92 | extern bool gcn_valid_cvt_p (machine_mode from, machine_mode to, | |
93 | enum gcn_cvt_t op); | |
94 | ||
95 | #ifdef TREE_CODE | |
96 | extern void gcn_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, | |
97 | int); | |
98 | class gimple_opt_pass; | |
99 | extern gimple_opt_pass *make_pass_omp_gcn (gcc::context *ctxt); | |
100 | #endif | |
101 | ||
102 | /* Return true if MODE is valid for 1 VGPR register. */ | |
103 | ||
104 | inline bool | |
105 | vgpr_1reg_mode_p (machine_mode mode) | |
106 | { | |
107 | return (mode == SImode || mode == SFmode || mode == HImode || mode == QImode | |
108 | || mode == V64QImode || mode == V64HImode || mode == V64SImode | |
109 | || mode == V64HFmode || mode == V64SFmode || mode == BImode); | |
110 | } | |
111 | ||
112 | /* Return true if MODE is valid for 1 SGPR register. */ | |
113 | ||
114 | inline bool | |
115 | sgpr_1reg_mode_p (machine_mode mode) | |
116 | { | |
117 | return (mode == SImode || mode == SFmode || mode == HImode | |
118 | || mode == QImode || mode == BImode); | |
119 | } | |
120 | ||
121 | /* Return true if MODE is valid for pair of VGPR registers. */ | |
122 | ||
123 | inline bool | |
124 | vgpr_2reg_mode_p (machine_mode mode) | |
125 | { | |
126 | return (mode == DImode || mode == DFmode | |
127 | || mode == V64DImode || mode == V64DFmode); | |
128 | } | |
129 | ||
130 | /* Return true if MODE can be handled directly by VGPR operations. */ | |
131 | ||
132 | inline bool | |
133 | vgpr_vector_mode_p (machine_mode mode) | |
134 | { | |
135 | return (mode == V64QImode || mode == V64HImode | |
136 | || mode == V64SImode || mode == V64DImode | |
137 | || mode == V64HFmode || mode == V64SFmode || mode == V64DFmode); | |
138 | } | |
139 | ||
140 | ||
141 | /* Return true if MODE is valid for pair of SGPR registers. */ | |
142 | ||
143 | inline bool | |
144 | sgpr_2reg_mode_p (machine_mode mode) | |
145 | { | |
146 | return mode == DImode || mode == DFmode; | |
147 | } | |
148 | ||
149 | #endif |