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aarch64: adjust enum writeback after rename
[thirdparty/gcc.git] / gcc / config / gcn / gcn.h
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a945c346 1/* Copyright (C) 2016-2024 Free Software Foundation, Inc.
5326695a
AS		 2
3 This file is free software; you can redistribute it and/or modify it under
4 the terms of the GNU General Public License as published by the Free
5 Software Foundation; either version 3 of the License, or (at your option)
6 any later version.
7
8 This file is distributed in the hope that it will be useful, but WITHOUT
9 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 for more details.
12
13 You should have received a copy of the GNU General Public License
14 along with GCC; see the file COPYING3. If not see
15 <http://www.gnu.org/licenses/>. */
16
17#include "config/gcn/gcn-opts.h"
18
e41b2433
PAA		 19#define TARGET_CPU_CPP_BUILTINS() \
20 do \
21 { \
22 builtin_define ("__AMDGCN__"); \
23 if (TARGET_GCN3) \
24 builtin_define ("__GCN3__"); \
25 else if (TARGET_GCN5) \
26 builtin_define ("__GCN5__"); \
27 else if (TARGET_CDNA1) \
28 builtin_define ("__CDNA1__"); \
29 else if (TARGET_CDNA2) \
30 builtin_define ("__CDNA2__"); \
c7ec7bd1
AS		 31 else if (TARGET_RDNA2) \
32 builtin_define ("__RDNA2__"); \
52a2c659
TB		 33 else if (TARGET_RDNA3) \
34 builtin_define ("__RDNA3__"); \
159174f2
TS		 35 else \
36 gcc_unreachable (); \
e41b2433
PAA		 37 if (TARGET_FIJI) \
38 { \
39 builtin_define ("__fiji__"); \
40 builtin_define ("__gfx803__"); \
41 } \
42 else if (TARGET_VEGA10) \
43 builtin_define ("__gfx900__"); \
44 else if (TARGET_VEGA20) \
45 builtin_define ("__gfx906__"); \
46 else if (TARGET_GFX908) \
47 builtin_define ("__gfx908__"); \
159174f2
TS		 48 else if (TARGET_GFX90a) \
49 builtin_define ("__gfx90a__"); \
b8e9fd53
FH		 50 else if (TARGET_GFX90c) \
51 builtin_define ("__gfx90c__"); \
52a2c659 52 else if (TARGET_GFX1030) \
78b56a12
RB		 53 builtin_define ("__gfx1030__"); \
54 else if (TARGET_GFX1036) \
55 builtin_define ("__gfx1036__"); \
52a2c659
TB		 56 else if (TARGET_GFX1100) \
57 builtin_define ("__gfx1100__"); \
1bf18629
AS		 58 else if (TARGET_GFX1103) \
59 builtin_define ("__gfx1103__"); \
159174f2
TS		 60 else \
61 gcc_unreachable (); \
e41b2433 62 } while (0)
5326695a 63
52a2c659 64#define ASSEMBLER_DIALECT (TARGET_RDNA2_PLUS ? 1 : 0)
c7ec7bd1 65
5326695a
AS		 66/* Support for a compile-time default architecture and tuning.
67 The rules are:
68 --with-arch is ignored if -march is specified.
69 --with-tune is ignored if -mtune is specified. */
70#define OPTION_DEFAULT_SPECS \
71 {"arch", "%{!march=*:-march=%(VALUE)}" }, \
72 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }
73
74/* Default target_flags if no switches specified. */
75#ifndef TARGET_DEFAULT
76#define TARGET_DEFAULT 0
77#endif
78
79\f
80/* Storage Layout */
81#define BITS_BIG_ENDIAN 0
82#define BYTES_BIG_ENDIAN 0
83#define WORDS_BIG_ENDIAN 0
84
a8a730cd
JB		 85#ifdef IN_LIBGCC2
86/* We want DImode and TImode helpers. */
87#define UNITS_PER_WORD 8
88#else
89#define UNITS_PER_WORD 4
90#endif
5326695a
AS		 91
92#define POINTER_SIZE 64
93#define PARM_BOUNDARY 64
94#define STACK_BOUNDARY 64
95#define FUNCTION_BOUNDARY 32
96#define BIGGEST_ALIGNMENT 64
97#define EMPTY_FIELD_BOUNDARY 32
a8a730cd 98#define MAX_FIXED_MODE_SIZE 128
5326695a
AS		 99#define MAX_REGS_PER_ADDRESS 2
100#define STACK_SIZE_MODE DImode
101#define Pmode DImode
102#define CASE_VECTOR_MODE DImode
103#define FUNCTION_MODE QImode
104
105#define DATA_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 128 ? (ALIGN) : 128)
106#define LOCAL_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 64 ? (ALIGN) : 64)
107#define STACK_SLOT_ALIGNMENT(TYPE,MODE,ALIGN) ((ALIGN) > 64 ? (ALIGN) : 64)
108#define STRICT_ALIGNMENT 1
109
110/* Type Layout: match what x86_64 does. */
111#define INT_TYPE_SIZE 32
112#define LONG_TYPE_SIZE 64
113#define LONG_LONG_TYPE_SIZE 64
114#define FLOAT_TYPE_SIZE 32
115#define DOUBLE_TYPE_SIZE 64
116#define LONG_DOUBLE_TYPE_SIZE 64
117#define DEFAULT_SIGNED_CHAR 1
118#define PCC_BITFIELD_TYPE_MATTERS 1
119
120/* Frame Layout */
121#define FRAME_GROWS_DOWNWARD 0
122#define ARGS_GROW_DOWNWARD 1
123#define STACK_POINTER_OFFSET 0
124#define FIRST_PARM_OFFSET(FNDECL) 0
125#define DYNAMIC_CHAIN_ADDRESS(FP) plus_constant (Pmode, (FP), -16)
126#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGNUM)
251697a6 127#define DWARF_FRAME_RETURN_COLUMN 16
5326695a
AS		 128#define STACK_DYNAMIC_OFFSET(FNDECL) (-crtl->outgoing_args_size)
129#define ACCUMULATE_OUTGOING_ARGS 1
130#define RETURN_ADDR_RTX(COUNT,FRAMEADDR) \
131 ((COUNT) == 0 ? get_hard_reg_initial_val (Pmode, LINK_REGNUM) : NULL_RTX)
132\f
133/* Register Basics */
134#define FIRST_SGPR_REG 0
135#define SGPR_REGNO(N) ((N)+FIRST_SGPR_REG)
136#define LAST_SGPR_REG 101
137
138#define FLAT_SCRATCH_REG 102
139#define FLAT_SCRATCH_LO_REG 102
140#define FLAT_SCRATCH_HI_REG 103
141#define XNACK_MASK_REG 104
142#define XNACK_MASK_LO_REG 104
143#define XNACK_MASK_HI_REG 105
144#define VCC_LO_REG 106
145#define VCC_HI_REG 107
146#define VCCZ_REG 108
147#define TBA_REG 109
148#define TBA_LO_REG 109
149#define TBA_HI_REG 110
150#define TMA_REG 111
151#define TMA_LO_REG 111
152#define TMA_HI_REG 112
153#define TTMP0_REG 113
154#define TTMP11_REG 124
155#define M0_REG 125
156#define EXEC_REG 126
157#define EXEC_LO_REG 126
158#define EXEC_HI_REG 127
159#define EXECZ_REG 128
160#define SCC_REG 129
a5eb246e 161
5326695a 162/* 132-159 are reserved to simplify masks. */
a5eb246e 163
5326695a
AS		 164#define FIRST_VGPR_REG 160
165#define VGPR_REGNO(N) ((N)+FIRST_VGPR_REG)
166#define LAST_VGPR_REG 415
a5eb246e 167
ae0d2c24
AS		 168#define FIRST_AVGPR_REG 416
169#define AVGPR_REGNO(N) ((N)+FIRST_AVGPR_REG)
170#define LAST_AVGPR_REG 671
5326695a 171
a5eb246e
TS		 172#ifndef USED_FOR_TARGET
173STATIC_ASSERT (LAST_SGPR_REG + 1 - FIRST_SGPR_REG == 102);
174STATIC_ASSERT (LAST_VGPR_REG + 1 - FIRST_VGPR_REG == 256);
175STATIC_ASSERT (LAST_AVGPR_REG + 1 - FIRST_AVGPR_REG == 256);
176#endif /* USED_FOR_TARGET */
177
5326695a
AS		 178/* Frame Registers, and other registers */
179
180#define HARD_FRAME_POINTER_REGNUM 14
181#define STACK_POINTER_REGNUM 16
182#define LINK_REGNUM 18
183#define EXEC_SAVE_REG 20
184#define CC_SAVE_REG 22
4e191462 185#define RETURN_VALUE_REG 168 /* Must be divisible by 4. */
5326695a
AS		 186#define STATIC_CHAIN_REGNUM 30
187#define WORK_ITEM_ID_Z_REG 162
ae0d2c24
AS		 188#define SOFT_ARG_REG 672
189#define FRAME_POINTER_REGNUM 674
190#define DWARF_LINK_REGISTER 676
191#define FIRST_PSEUDO_REGISTER 677
5326695a 192
4e191462
AS		 193#define FIRST_PARM_REG (FIRST_SGPR_REG + 24)
194#define FIRST_VPARM_REG (FIRST_VGPR_REG + 8)
5326695a
AS		 195#define NUM_PARM_REGS 6
196
197/* There is no arg pointer. Just choose random fixed register that does
198 not intefere with anything. */
199#define ARG_POINTER_REGNUM SOFT_ARG_REG
200
201#define HARD_FRAME_POINTER_IS_ARG_POINTER 0
202#define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
203
a5eb246e
TS		 204#define SGPR_REGNO_P(N) ((N) >= FIRST_SGPR_REG && (N) <= LAST_SGPR_REG)
205#define VGPR_REGNO_P(N) ((N) >= FIRST_VGPR_REG && (N) <= LAST_VGPR_REG)
206#define AVGPR_REGNO_P(N) ((N) >= FIRST_AVGPR_REG && (N) <= LAST_AVGPR_REG)
5326695a
AS		 207#define SSRC_REGNO_P(N) ((N) <= SCC_REG && (N) != VCCZ_REG)
208#define SDST_REGNO_P(N) ((N) <= EXEC_HI_REG && (N) != VCCZ_REG)
209#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
210#define CC_REGNO_P(X) ((X) == SCC_REG || (X) == VCC_REG)
211#define FUNCTION_ARG_REGNO_P(N) \
4e191462
AS		 212 (((N) >= FIRST_PARM_REG && (N) < (FIRST_PARM_REG + NUM_PARM_REGS)) \
213 || ((N) >= FIRST_VPARM_REG && (N) < (FIRST_VPARM_REG + NUM_PARM_REGS)))
5326695a
AS		 214
215\f
216#define FIXED_REGISTERS { \
217 /* Scalars. */ \
f6fff8a6 218 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
5326695a 219/* fp sp lr. */ \
969089ff 220 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, \
5326695a
AS		 221/* exec_save, cc_save */ \
222 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
223 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
224 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
225 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
226 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
227 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
228 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
229 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
230 /* Special regs and padding. */ \
231/* flat xnack vcc tba tma ttmp */ \
232 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
233/* m0 exec scc */ \
234 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, \
235 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
236 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
ae0d2c24 237 /* VGPRs */ \
342f9464 238 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
5326695a
AS		 239 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
240 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
241 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
242 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
243 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
244 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
245 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
246 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
247 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
248 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
249 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
250 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
251 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
252 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
253 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
ae0d2c24
AS		 254 /* Accumulation VGPRs */ \
255 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
256 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
257 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
258 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
259 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
260 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
261 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
262 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
263 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
264 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
265 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
266 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
267 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
268 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
269 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
270 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
5326695a 271 /* Other registers. */ \
251697a6 272 1, 1, 1, 1, 1 \
5326695a
AS		 273}
274
275#define CALL_USED_REGISTERS { \
276 /* Scalars. */ \
277 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
969089ff 278 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, \
5326695a
AS		 279 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
280 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
281 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
282 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
283 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
284 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
285 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
286 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
287 /* Special regs and padding. */ \
288 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
289 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
290 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
291 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
ae0d2c24 292 /* VGPRs */ \
5326695a
AS		 293 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
294 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
295 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
296 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
297 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
298 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
299 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
300 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
301 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
302 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
303 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
304 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
305 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
306 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
307 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
308 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
ae0d2c24
AS		 309 /* Accumulation VGPRs */ \
310 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
311 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
312 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
313 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
314 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
315 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
316 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
317 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
318 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
319 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
320 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
321 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
322 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
323 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
324 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
325 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
5326695a 326 /* Other registers. */ \
251697a6 327 1, 1, 1, 1, 1 \
5326695a
AS		 328}
329
330\f
331#define HARD_REGNO_RENAME_OK(FROM, TO) \
332 gcn_hard_regno_rename_ok (FROM, TO)
333
334#define HARD_REGNO_CALLER_SAVE_MODE(HARDREG, NREGS, MODE) \
335 gcn_hard_regno_caller_save_mode ((HARDREG), (NREGS), (MODE))
336
337/* Register Classes */
338
339enum reg_class
340{
341 NO_REGS,
342
343 /* SCC */
344 SCC_CONDITIONAL_REG,
345
346 /* VCCZ */
347 VCCZ_CONDITIONAL_REG,
348
349 /* VCC */
350 VCC_CONDITIONAL_REG,
351
352 /* EXECZ */
353 EXECZ_CONDITIONAL_REG,
354
355 /* SCC VCCZ EXECZ */
356 ALL_CONDITIONAL_REGS,
357
358 /* EXEC */
359 EXEC_MASK_REG,
360
361 /* SGPR0-101 */
362 SGPR_REGS,
363
364 /* SGPR0-101 EXEC_LO/EXEC_HI */
365 SGPR_EXEC_REGS,
366
367 /* SGPR0-101, FLAT_SCRATCH_LO/HI, VCC LO/HI, TBA LO/HI, TMA LO/HI, TTMP0-11,
368 M0, VCCZ, SCC
369 (EXEC_LO/HI, EXECZ excluded to prevent compiler misuse.) */
370 SGPR_VOP_SRC_REGS,
371
372 /* SGPR0-101, FLAT_SCRATCH_LO/HI, XNACK_MASK_LO/HI, VCC LO/HI, TBA LO/HI
373 TMA LO/HI, TTMP0-11 */
374 SGPR_MEM_SRC_REGS,
375
376 /* SGPR0-101, FLAT_SCRATCH_LO/HI, XNACK_MASK_LO/HI, VCC LO/HI, TBA LO/HI
377 TMA LO/HI, TTMP0-11, M0, EXEC LO/HI */
378 SGPR_DST_REGS,
379
380 /* SGPR0-101, FLAT_SCRATCH_LO/HI, XNACK_MASK_LO/HI, VCC LO/HI, TBA LO/HI
381 TMA LO/HI, TTMP0-11 */
382 SGPR_SRC_REGS,
383 GENERAL_REGS,
384 VGPR_REGS,
ae0d2c24
AS		 385 AVGPR_REGS,
386 ALL_VGPR_REGS,
5326695a
AS		 387 ALL_GPR_REGS,
388 SRCDST_REGS,
389 AFP_REGS,
390 ALL_REGS,
391 LIM_REG_CLASSES
392};
393
394#define N_REG_CLASSES (int) LIM_REG_CLASSES
395
396#define REG_CLASS_NAMES \
397{ "NO_REGS", \
398 "SCC_CONDITIONAL_REG", \
399 "VCCZ_CONDITIONAL_REG", \
400 "VCC_CONDITIONAL_REG", \
401 "EXECZ_CONDITIONAL_REG", \
402 "ALL_CONDITIONAL_REGS", \
403 "EXEC_MASK_REG", \
404 "SGPR_REGS", \
405 "SGPR_EXEC_REGS", \
406 "SGPR_VOP3A_SRC_REGS", \
407 "SGPR_MEM_SRC_REGS", \
408 "SGPR_DST_REGS", \
409 "SGPR_SRC_REGS", \
410 "GENERAL_REGS", \
411 "VGPR_REGS", \
ae0d2c24
AS		 412 "AVGPR_REGS", \
413 "ALL_VGPR_REGS", \
5326695a
AS		 414 "ALL_GPR_REGS", \
415 "SRCDST_REGS", \
416 "AFP_REGS", \
417 "ALL_REGS" \
418}
419
420#define NAMED_REG_MASK(N) (1<<((N)-3*32))
421#define NAMED_REG_MASK2(N) (1<<((N)-4*32))
422
423#define REG_CLASS_CONTENTS { \
424 /* NO_REGS. */ \
425 {0, 0, 0, 0, \
ae0d2c24
AS		 426 0, 0, 0, 0, \
427 0, 0, 0, 0, \
5326695a
AS		 428 0, 0, 0, 0, \
429 0, 0, 0, 0, 0, 0}, \
430 /* SCC_CONDITIONAL_REG. */ \
431 {0, 0, 0, 0, \
432 NAMED_REG_MASK2 (SCC_REG), 0, 0, 0, \
ae0d2c24
AS		 433 0, 0, 0, 0, \
434 0, 0, 0, 0, \
435 0, 0, 0, 0, 0, 0}, \
5326695a
AS		 436 /* VCCZ_CONDITIONAL_REG. */ \
437 {0, 0, 0, NAMED_REG_MASK (VCCZ_REG), \
ae0d2c24
AS		 438 0, 0, 0, 0, \
439 0, 0, 0, 0, \
5326695a
AS		 440 0, 0, 0, 0, \
441 0, 0, 0, 0, 0, 0}, \
442 /* VCC_CONDITIONAL_REG. */ \
443 {0, 0, 0, NAMED_REG_MASK (VCC_LO_REG)|NAMED_REG_MASK (VCC_HI_REG), \
ae0d2c24
AS		 444 0, 0, 0, 0, \
445 0, 0, 0, 0, \
5326695a
AS		 446 0, 0, 0, 0, \
447 0, 0, 0, 0, 0, 0}, \
448 /* EXECZ_CONDITIONAL_REG. */ \
449 {0, 0, 0, 0, \
450 NAMED_REG_MASK2 (EXECZ_REG), 0, 0, 0, \
ae0d2c24
AS		 451 0, 0, 0, 0, \
452 0, 0, 0, 0, \
453 0, 0, 0, 0, 0, 0}, \
5326695a
AS		 454 /* ALL_CONDITIONAL_REGS. */ \
455 {0, 0, 0, NAMED_REG_MASK (VCCZ_REG), \
456 NAMED_REG_MASK2 (EXECZ_REG) | NAMED_REG_MASK2 (SCC_REG), 0, 0, 0, \
ae0d2c24
AS		 457 0, 0, 0, 0, \
458 0, 0, 0, 0, \
5326695a
AS		 459 0, 0, 0, 0, 0, 0}, \
460 /* EXEC_MASK_REG. */ \
461 {0, 0, 0, NAMED_REG_MASK (EXEC_LO_REG) | NAMED_REG_MASK (EXEC_HI_REG), \
ae0d2c24
AS		 462 0, 0, 0, 0, \
463 0, 0, 0, 0, \
5326695a
AS		 464 0, 0, 0, 0, \
465 0, 0, 0, 0, 0, 0}, \
466 /* SGPR_REGS. */ \
467 {0xffffffff, 0xffffffff, 0xffffffff, 0xf1, \
ae0d2c24
AS		 468 0, 0, 0, 0, \
469 0, 0, 0, 0, \
5326695a
AS		 470 0, 0, 0, 0, \
471 0, 0, 0, 0, 0, 0}, \
472 /* SGPR_EXEC_REGS. */ \
473 {0xffffffff, 0xffffffff, 0xffffffff, \
474 0xf1 | NAMED_REG_MASK (EXEC_LO_REG) | NAMED_REG_MASK (EXEC_HI_REG), \
475 0, 0, 0, 0, \
ae0d2c24
AS		 476 0, 0, 0, 0, \
477 0, 0, 0, 0, \
5326695a
AS		 478 0, 0, 0, 0, 0, 0}, \
479 /* SGPR_VOP_SRC_REGS. */ \
480 {0xffffffff, 0xffffffff, 0xffffffff, \
481 0xffffffff \
482 -NAMED_REG_MASK (EXEC_LO_REG) \
483 -NAMED_REG_MASK (EXEC_HI_REG), \
484 NAMED_REG_MASK2 (SCC_REG), 0, 0, 0, \
ae0d2c24
AS		 485 0, 0, 0, 0, \
486 0, 0, 0, 0, \
5326695a
AS		 487 0, 0, 0, 0, 0, 0}, \
488 /* SGPR_MEM_SRC_REGS. */ \
489 {0xffffffff, 0xffffffff, 0xffffffff, \
490 0xffffffff-NAMED_REG_MASK (VCCZ_REG)-NAMED_REG_MASK (M0_REG) \
491 -NAMED_REG_MASK (EXEC_LO_REG)-NAMED_REG_MASK (EXEC_HI_REG), \
492 0, 0, 0, 0, \
ae0d2c24
AS		 493 0, 0, 0, 0, \
494 0, 0, 0, 0, \
5326695a
AS		 495 0, 0, 0, 0, 0, 0}, \
496 /* SGPR_DST_REGS. */ \
497 {0xffffffff, 0xffffffff, 0xffffffff, \
498 0xffffffff-NAMED_REG_MASK (VCCZ_REG), \
499 0, 0, 0, 0, \
500 0, 0, 0, 0, 0, 0}, \
501 /* SGPR_SRC_REGS. */ \
502 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
503 NAMED_REG_MASK2 (EXECZ_REG) | NAMED_REG_MASK2 (SCC_REG), 0, 0, 0, \
ae0d2c24
AS		 504 0, 0, 0, 0, \
505 0, 0, 0, 0, \
5326695a
AS		 506 0, 0, 0, 0, 0, 0}, \
507 /* GENERAL_REGS. */ \
508 {0xffffffff, 0xffffffff, 0xffffffff, 0xf1, \
ae0d2c24
AS		 509 0, 0, 0, 0, \
510 0, 0, 0, 0, \
5326695a
AS		 511 0, 0, 0, 0, \
512 0, 0, 0, 0, 0, 0}, \
513 /* VGPR_REGS. */ \
514 {0, 0, 0, 0, \
515 0, 0xffffffff, 0xffffffff, 0xffffffff, \
ae0d2c24
AS		 516 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
517 0xffffffff, 0, 0, 0, \
518 0, 0, 0, 0, 0, 0}, \
519 /* AVGPR_REGS. */ \
520 {0, 0, 0, 0, \
521 0, 0, 0, 0, \
522 0, 0, 0, 0, \
523 0, 0xffffffff, 0xffffffff, 0xffffffff, \
524 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0}, \
525 /* ALL_VGPR_REGS. */ \
526 {0, 0, 0, 0, \
527 0, 0xffffffff, 0xffffffff, 0xffffffff, \
528 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
529 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
5326695a
AS		 530 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0}, \
531 /* ALL_GPR_REGS. */ \
532 {0xffffffff, 0xffffffff, 0xffffffff, 0xf1, \
533 0, 0xffffffff, 0xffffffff, 0xffffffff, \
ae0d2c24
AS		 534 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
535 0xffffffff, 0, 0, 0, \
536 0, 0, 0, 0, 0, 0}, \
5326695a
AS		 537 /* SRCDST_REGS. */ \
538 {0xffffffff, 0xffffffff, 0xffffffff, \
539 0xffffffff-NAMED_REG_MASK (VCCZ_REG), \
540 0, 0xffffffff, 0xffffffff, 0xffffffff, \
ae0d2c24
AS		 541 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
542 0xffffffff, 0, 0, 0, \
543 0, 0, 0, 0, 0, 0}, \
5326695a
AS		 544 /* AFP_REGS. */ \
545 {0, 0, 0, 0, \
ae0d2c24
AS		 546 0, 0, 0, 0, \
547 0, 0, 0, 0, \
5326695a
AS		 548 0, 0, 0, 0, \
549 0, 0, 0, 0, 0, 0xf}, \
550 /* ALL_REGS. */ \
551 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
ae0d2c24
AS		 552 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
553 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
5326695a
AS		 554 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
555 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0 }}
556
557#define REGNO_REG_CLASS(REGNO) gcn_regno_reg_class (REGNO)
558#define MODE_CODE_BASE_REG_CLASS(MODE, AS, OUTER, INDEX) \
559 gcn_mode_code_base_reg_class (MODE, AS, OUTER, INDEX)
560#define REGNO_MODE_CODE_OK_FOR_BASE_P(NUM, MODE, AS, OUTER, INDEX) \
561 gcn_regno_mode_code_ok_for_base_p (NUM, MODE, AS, OUTER, INDEX)
562#define INDEX_REG_CLASS VGPR_REGS
563#define REGNO_OK_FOR_INDEX_P(regno) regno_ok_for_index_p (regno)
564
565\f
566/* Address spaces. */
567enum gcn_address_spaces
568{
569 ADDR_SPACE_DEFAULT = 0,
570 ADDR_SPACE_FLAT,
571 ADDR_SPACE_SCALAR_FLAT,
572 ADDR_SPACE_FLAT_SCRATCH,
573 ADDR_SPACE_LDS,
574 ADDR_SPACE_GDS,
575 ADDR_SPACE_SCRATCH,
576 ADDR_SPACE_GLOBAL
577};
578#define REGISTER_TARGET_PRAGMAS() do { \
579 c_register_addr_space ("__flat", ADDR_SPACE_FLAT); \
580 c_register_addr_space ("__flat_scratch", ADDR_SPACE_FLAT_SCRATCH); \
581 c_register_addr_space ("__scalar_flat", ADDR_SPACE_SCALAR_FLAT); \
582 c_register_addr_space ("__lds", ADDR_SPACE_LDS); \
583 c_register_addr_space ("__gds", ADDR_SPACE_GDS); \
584 c_register_addr_space ("__global", ADDR_SPACE_GLOBAL); \
585} while (0);
586
587#define STACK_ADDR_SPACE \
588 (TARGET_GCN5_PLUS ? ADDR_SPACE_GLOBAL : ADDR_SPACE_FLAT)
589#define DEFAULT_ADDR_SPACE \
590 ((cfun && cfun->machine && !cfun->machine->use_flat_addressing) \
591 ? ADDR_SPACE_GLOBAL : ADDR_SPACE_FLAT)
592#define AS_SCALAR_FLAT_P(AS) ((AS) == ADDR_SPACE_SCALAR_FLAT)
593#define AS_FLAT_SCRATCH_P(AS) ((AS) == ADDR_SPACE_FLAT_SCRATCH)
594#define AS_FLAT_P(AS) ((AS) == ADDR_SPACE_FLAT \
595 || ((AS) == ADDR_SPACE_DEFAULT \
596 && DEFAULT_ADDR_SPACE == ADDR_SPACE_FLAT))
597#define AS_LDS_P(AS) ((AS) == ADDR_SPACE_LDS)
598#define AS_GDS_P(AS) ((AS) == ADDR_SPACE_GDS)
599#define AS_SCRATCH_P(AS) ((AS) == ADDR_SPACE_SCRATCH)
600#define AS_GLOBAL_P(AS) ((AS) == ADDR_SPACE_GLOBAL \
601 || ((AS) == ADDR_SPACE_DEFAULT \
602 && DEFAULT_ADDR_SPACE == ADDR_SPACE_GLOBAL))
603#define AS_ANY_FLAT_P(AS) (AS_FLAT_SCRATCH_P (AS) || AS_FLAT_P (AS))
604#define AS_ANY_DS_P(AS) (AS_LDS_P (AS) || AS_GDS_P (AS))
605
606\f
607/* Instruction Output */
608#define REGISTER_NAMES \
609 {"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", \
610 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", \
611 "s21", "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", \
612 "s31", "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", "s40", \
613 "s41", "s42", "s43", "s44", "s45", "s46", "s47", "s48", "s49", "s50", \
614 "s51", "s52", "s53", "s54", "s55", "s56", "s57", "s58", "s59", "s60", \
615 "s61", "s62", "s63", "s64", "s65", "s66", "s67", "s68", "s69", "s70", \
616 "s71", "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", "s80", \
617 "s81", "s82", "s83", "s84", "s85", "s86", "s87", "s88", "s89", "s90", \
618 "s91", "s92", "s93", "s94", "s95", "s96", "s97", "s98", "s99", \
619 "s100", "s101", \
620 "flat_scratch_lo", "flat_scratch_hi", "xnack_mask_lo", "xnack_mask_hi", \
621 "vcc_lo", "vcc_hi", "vccz", "tba_lo", "tba_hi", "tma_lo", "tma_hi", \
622 "ttmp0", "ttmp1", "ttmp2", "ttmp3", "ttmp4", "ttmp5", "ttmp6", "ttmp7", \
623 "ttmp8", "ttmp9", "ttmp10", "ttmp11", "m0", "exec_lo", "exec_hi", \
624 "execz", "scc", \
625 "res130", "res131", "res132", "res133", "res134", "res135", "res136", \
626 "res137", "res138", "res139", "res140", "res141", "res142", "res143", \
627 "res144", "res145", "res146", "res147", "res148", "res149", "res150", \
628 "res151", "res152", "res153", "res154", "res155", "res156", "res157", \
629 "res158", "res159", \
630 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", \
631 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", \
632 "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", \
633 "v31", "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", "v40", \
634 "v41", "v42", "v43", "v44", "v45", "v46", "v47", "v48", "v49", "v50", \
635 "v51", "v52", "v53", "v54", "v55", "v56", "v57", "v58", "v59", "v60", \
636 "v61", "v62", "v63", "v64", "v65", "v66", "v67", "v68", "v69", "v70", \
637 "v71", "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", "v80", \
638 "v81", "v82", "v83", "v84", "v85", "v86", "v87", "v88", "v89", "v90", \
639 "v91", "v92", "v93", "v94", "v95", "v96", "v97", "v98", "v99", "v100", \
640 "v101", "v102", "v103", "v104", "v105", "v106", "v107", "v108", "v109", \
641 "v110", "v111", "v112", "v113", "v114", "v115", "v116", "v117", "v118", \
642 "v119", "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", \
643 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", "v136", \
644 "v137", "v138", "v139", "v140", "v141", "v142", "v143", "v144", "v145", \
645 "v146", "v147", "v148", "v149", "v150", "v151", "v152", "v153", "v154", \
646 "v155", "v156", "v157", "v158", "v159", "v160", "v161", "v162", "v163", \
647 "v164", "v165", "v166", "v167", "v168", "v169", "v170", "v171", "v172", \
648 "v173", "v174", "v175", "v176", "v177", "v178", "v179", "v180", "v181", \
649 "v182", "v183", "v184", "v185", "v186", "v187", "v188", "v189", "v190", \
650 "v191", "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", \
651 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", "v208", \
652 "v209", "v210", "v211", "v212", "v213", "v214", "v215", "v216", "v217", \
653 "v218", "v219", "v220", "v221", "v222", "v223", "v224", "v225", "v226", \
654 "v227", "v228", "v229", "v230", "v231", "v232", "v233", "v234", "v235", \
655 "v236", "v237", "v238", "v239", "v240", "v241", "v242", "v243", "v244", \
656 "v245", "v246", "v247", "v248", "v249", "v250", "v251", "v252", "v253", \
657 "v254", "v255", \
ae0d2c24
AS		 658 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "a8", "a9", "a10", \
659 "a11", "a12", "a13", "a14", "a15", "a16", "a17", "a18", "a19", "a20", \
660 "a21", "a22", "a23", "a24", "a25", "a26", "a27", "a28", "a29", "a30", \
661 "a31", "a32", "a33", "a34", "a35", "a36", "a37", "a38", "a39", "a40", \
662 "a41", "a42", "a43", "a44", "a45", "a46", "a47", "a48", "a49", "a50", \
663 "a51", "a52", "a53", "a54", "a55", "a56", "a57", "a58", "a59", "a60", \
664 "a61", "a62", "a63", "a64", "a65", "a66", "a67", "a68", "a69", "a70", \
665 "a71", "a72", "a73", "a74", "a75", "a76", "a77", "a78", "a79", "a80", \
666 "a81", "a82", "a83", "a84", "a85", "a86", "a87", "a88", "a89", "a90", \
667 "a91", "a92", "a93", "a94", "a95", "a96", "a97", "a98", "a99", "a100", \
668 "a101", "a102", "a103", "a104", "a105", "a106", "a107", "a108", "a109", \
669 "a110", "a111", "a112", "a113", "a114", "a115", "a116", "a117", "a118", \
670 "a119", "a120", "a121", "a122", "a123", "a124", "a125", "a126", "a127", \
671 "a128", "a129", "a130", "a131", "a132", "a133", "a134", "a135", "a136", \
672 "a137", "a138", "a139", "a140", "a141", "a142", "a143", "a144", "a145", \
673 "a146", "a147", "a148", "a149", "a150", "a151", "a152", "a153", "a154", \
674 "a155", "a156", "a157", "a158", "a159", "a160", "a161", "a162", "a163", \
675 "a164", "a165", "a166", "a167", "a168", "a169", "a170", "a171", "a172", \
676 "a173", "a174", "a175", "a176", "a177", "a178", "a179", "a180", "a181", \
677 "a182", "a183", "a184", "a185", "a186", "a187", "a188", "a189", "a190", \
678 "a191", "a192", "a193", "a194", "a195", "a196", "a197", "a198", "a199", \
679 "a200", "a201", "a202", "a203", "a204", "a205", "a206", "a207", "a208", \
680 "a209", "a210", "a211", "a212", "a213", "a214", "a215", "a216", "a217", \
681 "a218", "a219", "a220", "a221", "a222", "a223", "a224", "a225", "a226", \
682 "a227", "a228", "a229", "a230", "a231", "a232", "a233", "a234", "a235", \
683 "a236", "a237", "a238", "a239", "a240", "a241", "a242", "a243", "a244", \
684 "a245", "a246", "a247", "a248", "a249", "a250", "a251", "a252", "a253", \
685 "a254", "a255", \
251697a6 686 "?ap0", "?ap1", "?fp0", "?fp1", "?dwlr" }
5326695a
AS		 687
688#define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE, X, CODE)
689#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
690#define PRINT_OPERAND_PUNCT_VALID_P(CODE) (CODE == '^')
691
692\f
693/* Register Arguments */
694
695#ifndef USED_FOR_TARGET
696
f062c3f1 697#define GCN_KERNEL_ARG_TYPES 16
5326695a
AS		 698struct GTY(()) gcn_kernel_args
699{
700 long requested;
701 int reg[GCN_KERNEL_ARG_TYPES];
702 int order[GCN_KERNEL_ARG_TYPES];
703 int nargs, nsgprs;
704};
705
706typedef struct gcn_args
707{
708 /* True if this isn't a kernel (HSA runtime entrypoint). */
709 bool normal_function;
710 tree fntype;
711 struct gcn_kernel_args args;
712 int num;
4e191462 713 int vnum;
5326695a
AS		 714 int offset;
715 int alignment;
716} CUMULATIVE_ARGS;
717#endif
718
719#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
720 gcn_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \
721 (N_NAMED_ARGS) != -1)
722
723\f
724#ifndef USED_FOR_TARGET
725
726#include "hash-table.h"
727#include "hash-map.h"
728#include "vec.h"
729
730struct GTY(()) machine_function
731{
732 struct gcn_kernel_args args;
733 int kernarg_segment_alignment;
734 int kernarg_segment_byte_size;
735 /* Frame layout info for normal functions. */
736 bool normal_function;
737 bool need_frame_pointer;
738 bool lr_needs_saving;
739 HOST_WIDE_INT outgoing_args_size;
740 HOST_WIDE_INT pretend_size;
741 HOST_WIDE_INT local_vars;
742 HOST_WIDE_INT callee_saves;
743
2a3f9f65
JB		 744 unsigned HOST_WIDE_INT reduction_base;
745 unsigned HOST_WIDE_INT reduction_limit;
5326695a
AS		 746
747 bool use_flat_addressing;
748};
749#endif
750
751\f
752/* Codes for all the GCN builtins. */
753
754enum gcn_builtin_codes
755{
756#define DEF_BUILTIN(fcode, icode, name, type, params, expander) \
757 GCN_BUILTIN_ ## fcode,
758#define DEF_BUILTIN_BINOP_INT_FP(fcode, ic, name) \
759 GCN_BUILTIN_ ## fcode ## _V64SI, \
760 GCN_BUILTIN_ ## fcode ## _V64SI_unspec,
761#include "gcn-builtins.def"
762#undef DEF_BUILTIN
763#undef DEF_BUILTIN_BINOP_INT_FP
764 GCN_BUILTIN_MAX
765};
766
767\f
768/* Misc */
769
770/* We can load/store 128-bit quantities, but having this larger than
771 MAX_FIXED_MODE_SIZE (which we want to be 64 bits) causes problems. */
772#define MOVE_MAX 8
773
774#define AVOID_CCMODE_COPIES 1
775#define SLOW_BYTE_ACCESS 0
776#define WORD_REGISTER_OPERATIONS 1
777
dbde9e2d
AS		 778/* Flag values are either BImode or DImode, but either way the compiler
779 should assume that all the bits are live. */
780#define STORE_FLAG_VALUE -1
781
5326695a
AS		 782/* Definitions for register eliminations.
783
784 This is an array of structures. Each structure initializes one pair
785 of eliminable registers. The "from" register number is given first,
786 followed by "to". Eliminations of the same "from" register are listed
787 in order of preference. */
788
789#define ELIMINABLE_REGS \
790{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
791 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
792 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
793 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }}
794
795/* Define the offset between two registers, one to be eliminated, and the
796 other its replacement, at the start of a routine. */
797
798#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
799 ((OFFSET) = gcn_initial_elimination_offset ((FROM), (TO)))
800
801
802/* Define this macro if it is advisable to hold scalars in registers
803 in a wider mode than that declared by the program. In such cases,
804 the value is constrained to be within the bounds of the declared
805 type, but kept valid in the wider mode. The signedness of the
806 extension may differ from that of the type. */
807
808#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
809 if (GET_MODE_CLASS (MODE) == MODE_INT \
810 && (TYPE == NULL || TREE_CODE (TYPE) != VECTOR_TYPE) \
811 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
812 { \
813 (MODE) = SImode; \
814 }
815
816/* This needs to match gcn_function_value. */
4e191462 817#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, RETURN_VALUE_REG)
5326695a 818
34bac264
AS		 819/* The s_ff0 and s_flbit instructions return -1 if no input bits are set. */
820#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 2)
821#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 2)
822
5326695a
AS		 823\f
824/* Costs. */
825
826/* Branches are to be dicouraged when theres an alternative.
827 FIXME: This number is plucked from the air. */
828#define BRANCH_COST(SPEED_P, PREDICABLE_P) 10
829
830\f
831/* Profiling */
832#define FUNCTION_PROFILER(FILE, LABELNO)
833#define NO_PROFILE_COUNTERS 1
834#define PROFILE_BEFORE_PROLOGUE 0
835
836/* Trampolines */
837#define TRAMPOLINE_SIZE 36
838#define TRAMPOLINE_ALIGNMENT 64
0d8753cf
AS		 839
840/* MD Optimization.
841 The following are intended to be obviously constant at compile time to
842 allow genconditions to eliminate bad patterns at compile time. */
843#define MODE_VF(M) \
844 ((M == V64QImode || M == V64HImode || M == V64HFmode || M == V64SImode \
845 || M == V64SFmode || M == V64DImode || M == V64DFmode) \
846 ? 64 \
847 : (M == V32QImode || M == V32HImode || M == V32HFmode || M == V32SImode \
848 || M == V32SFmode || M == V32DImode || M == V32DFmode) \
849 ? 32 \
850 : (M == V16QImode || M == V16HImode || M == V16HFmode || M == V16SImode \
851 || M == V16SFmode || M == V16DImode || M == V16DFmode) \
852 ? 16 \
853 : (M == V8QImode || M == V8HImode || M == V8HFmode || M == V8SImode \
854 || M == V8SFmode || M == V8DImode || M == V8DFmode) \
855 ? 8 \
856 : (M == V4QImode || M == V4HImode || M == V4HFmode || M == V4SImode \
857 || M == V4SFmode || M == V4DImode || M == V4DFmode) \
858 ? 4 \
859 : (M == V2QImode || M == V2HImode || M == V2HFmode || M == V2SImode \
860 || M == V2SFmode || M == V2DImode || M == V2DFmode) \
861 ? 2 \
862 : 1)
4d9d015c
TS		 863
864/* The C++ front end insists to link against libstdc++ -- which we don't build.
865 Tell it to instead link against the innocuous libgcc. */
866#define LIBSTDCXX "gcc"
Mirror of https://gcc.gnu.org/git/gcc.git