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340f6494 1/* Subroutines for insn-output.c for Renesas H8/300.
5624e564 2 Copyright (C) 1992-2015 Free Software Foundation, Inc.
48837e29
DE		 3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
07aae5c2 5
8aa063fb 6This file is part of GCC.
07aae5c2 7
8aa063fb 8GCC is free software; you can redistribute it and/or modify
07aae5c2 9it under the terms of the GNU General Public License as published by
2f83c7d6 10the Free Software Foundation; either version 3, or (at your option)
07aae5c2
SC		 11any later version.
12
8aa063fb 13GCC is distributed in the hope that it will be useful,
07aae5c2
SC		 14but WITHOUT ANY WARRANTY; without even the implied warranty of
15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
2f83c7d6
NC		 19along with GCC; see the file COPYING3. If not see
20<http://www.gnu.org/licenses/>. */
07aae5c2 21
07aae5c2 22#include "config.h"
c5c76735 23#include "system.h"
4977bab6
ZW		 24#include "coretypes.h"
25#include "tm.h"
07aae5c2 26#include "rtl.h"
40e23961
MC		 27#include "alias.h"
28#include "symtab.h"
bf6bb899 29#include "tree.h"
d8a2d370
DN		 30#include "stor-layout.h"
31#include "varasm.h"
32#include "calls.h"
33#include "stringpool.h"
07aae5c2
SC		 34#include "regs.h"
35#include "hard-reg-set.h"
07aae5c2
SC		 36#include "insn-config.h"
37#include "conditions.h"
07aae5c2
SC		 38#include "output.h"
39#include "insn-attr.h"
40#include "flags.h"
41#include "recog.h"
bf6bb899 42#include "function.h"
36566b39
PK		 43#include "expmed.h"
44#include "dojump.h"
45#include "explow.h"
46#include "emit-rtl.h"
47#include "stmt.h"
48#include "expr.h"
b0710fe1 49#include "insn-codes.h"
c15c90bb 50#include "optabs.h"
718f9c0f 51#include "diagnostic-core.h"
39dabefd 52#include "c-family/c-pragma.h" /* ??? */
441d04c6 53#include "tm_p.h"
ceaaaeab 54#include "tm-constrs.h"
672a6f42 55#include "target.h"
60393bbc
AM		 56#include "dominance.h"
57#include "cfg.h"
58#include "cfgrtl.h"
59#include "cfganal.h"
60#include "lcm.h"
61#include "cfgbuild.h"
62#include "cfgcleanup.h"
63#include "predict.h"
64#include "basic-block.h"
9690aa8e 65#include "df.h"
9b2b7279 66#include "builtins.h"
07aae5c2 67
994c5d85 68/* This file should be included last. */
d58627a0
RS		 69#include "target-def.h"
70
beed8fc0
AO		 71/* Classifies a h8300_src_operand or h8300_dst_operand.
72
73 H8OP_IMMEDIATE
74 A constant operand of some sort.
75
76 H8OP_REGISTER
77 An ordinary register.
78
79 H8OP_MEM_ABSOLUTE
80 A memory reference with a constant address.
81
82 H8OP_MEM_BASE
83 A memory reference with a register as its address.
84
85 H8OP_MEM_COMPLEX
86 Some other kind of memory reference. */
87enum h8300_operand_class
88{
89 H8OP_IMMEDIATE,
90 H8OP_REGISTER,
91 H8OP_MEM_ABSOLUTE,
92 H8OP_MEM_BASE,
93 H8OP_MEM_COMPLEX,
94 NUM_H8OPS
95};
96
beed8fc0
AO		 97/* For a general two-operand instruction, element [X][Y] gives
98 the length of the opcode fields when the first operand has class
99 (X + 1) and the second has class Y. */
100typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
101
07aae5c2 102/* Forward declarations. */
cb713a8d
KH		 103static const char *byte_reg (rtx, int);
104static int h8300_interrupt_function_p (tree);
3cfa3702 105static int h8300_saveall_function_p (tree);
cb713a8d
KH		 106static int h8300_monitor_function_p (tree);
107static int h8300_os_task_function_p (tree);
c72ea086 108static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool);
e68d4dd1 109static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
cb713a8d 110static unsigned int compute_saved_regs (void);
cb713a8d
KH		 111static const char *cond_string (enum rtx_code);
112static unsigned int h8300_asm_insn_count (const char *);
cb713a8d
KH		 113static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
114static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
115static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
88cb339e
N		 116static void h8300_print_operand_address (FILE *, rtx);
117static void h8300_print_operand (FILE *, rtx, int);
118static bool h8300_print_operand_punct_valid_p (unsigned char code);
ede75ee8 119#ifndef OBJECT_FORMAT_ELF
c18a5b6c 120static void h8300_asm_named_section (const char *, unsigned int, tree);
ede75ee8 121#endif
ef4bddc2 122static int h8300_register_move_cost (machine_mode, reg_class_t, reg_class_t);
cb713a8d
KH		 123static int h8300_and_costs (rtx);
124static int h8300_shift_costs (rtx);
ac447f25 125static void h8300_push_pop (int, int, bool, bool);
beed8fc0
AO		 126static int h8300_stack_offset_p (rtx, int);
127static int h8300_ldm_stm_regno (rtx, int, int, int);
beed8fc0
AO		 128static void h8300_reorg (void);
129static unsigned int h8300_constant_length (rtx);
130static unsigned int h8300_displacement_length (rtx, int);
131static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *);
132static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *);
133static unsigned int h8300_unary_length (rtx);
134static unsigned int h8300_short_immediate_length (rtx);
135static unsigned int h8300_bitfield_length (rtx, rtx);
e7041fcc 136static unsigned int h8300_binary_length (rtx_insn *, const h8300_length_table *);
beed8fc0
AO		 137static bool h8300_short_move_mem_p (rtx, enum rtx_code);
138static unsigned int h8300_move_length (rtx *, const h8300_length_table *);
2e762884 139static bool h8300_hard_regno_scratch_ok (unsigned int);
ef4bddc2 140static rtx h8300_get_index (rtx, machine_mode mode, int *);
f5b65a56 141
48837e29
DE		 142/* CPU_TYPE, says what cpu we're compiling for. */
143int cpu_type;
144
e392d367
KH		 145/* True if a #pragma interrupt has been seen for the current function. */
146static int pragma_interrupt;
07aae5c2
SC		 147
148/* True if a #pragma saveall has been seen for the current function. */
0869f126 149static int pragma_saveall;
07aae5c2 150
441d04c6 151static const char *const names_big[] =
07e4d94e 152{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
48837e29 153
441d04c6 154static const char *const names_extended[] =
07e4d94e 155{ "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
48837e29 156
441d04c6 157static const char *const names_upper_extended[] =
07e4d94e 158{ "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
48837e29
DE		 159
160/* Points to one of the above. */
161/* ??? The above could be put in an array indexed by CPU_TYPE. */
441d04c6 162const char * const *h8_reg_names;
48837e29
DE		 163
164/* Various operations needed by the following, indexed by CPU_TYPE. */
48837e29 165
441d04c6 166const char *h8_push_op, *h8_pop_op, *h8_mov_op;
dc66a1c4 167
beed8fc0
AO		 168/* Value of MOVE_RATIO. */
169int h8300_move_ratio;
672a6f42 170\f
c4dfc70c
DD		 171/* See below where shifts are handled for explanation of this enum. */
172
173enum shift_alg
174{
175 SHIFT_INLINE,
176 SHIFT_ROT_AND,
177 SHIFT_SPECIAL,
178 SHIFT_LOOP
179};
180
181/* Symbols of the various shifts which can be used as indices. */
182
183enum shift_type
184{
185 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
186};
187
188/* Macros to keep the shift algorithm tables small. */
189#define INL SHIFT_INLINE
190#define ROT SHIFT_ROT_AND
191#define LOP SHIFT_LOOP
192#define SPC SHIFT_SPECIAL
193
194/* The shift algorithms for each machine, mode, shift type, and shift
195 count are defined below. The three tables below correspond to
196 QImode, HImode, and SImode, respectively. Each table is organized
f411c849 197 by, in the order of indices, machine, shift type, and shift count. */
c4dfc70c
DD		 198
199static enum shift_alg shift_alg_qi[3][3][8] = {
200 {
201 /* TARGET_H8300 */
202 /* 0 1 2 3 4 5 6 7 */
203 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
204 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
205 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
206 },
207 {
208 /* TARGET_H8300H */
209 /* 0 1 2 3 4 5 6 7 */
210 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
211 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
212 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
213 },
214 {
215 /* TARGET_H8300S */
216 /* 0 1 2 3 4 5 6 7 */
217 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
218 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
219 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
220 }
221};
222
223static enum shift_alg shift_alg_hi[3][3][16] = {
224 {
225 /* TARGET_H8300 */
226 /* 0 1 2 3 4 5 6 7 */
227 /* 8 9 10 11 12 13 14 15 */
228 { INL, INL, INL, INL, INL, INL, INL, SPC,
229 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
230 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
231 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
232 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
233 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
234 },
235 {
236 /* TARGET_H8300H */
237 /* 0 1 2 3 4 5 6 7 */
238 /* 8 9 10 11 12 13 14 15 */
239 { INL, INL, INL, INL, INL, INL, INL, SPC,
240 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
241 { INL, INL, INL, INL, INL, INL, INL, SPC,
242 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
243 { INL, INL, INL, INL, INL, INL, INL, SPC,
244 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
245 },
246 {
247 /* TARGET_H8300S */
248 /* 0 1 2 3 4 5 6 7 */
249 /* 8 9 10 11 12 13 14 15 */
250 { INL, INL, INL, INL, INL, INL, INL, INL,
251 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
252 { INL, INL, INL, INL, INL, INL, INL, INL,
253 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
254 { INL, INL, INL, INL, INL, INL, INL, INL,
255 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
256 }
257};
258
259static enum shift_alg shift_alg_si[3][3][32] = {
260 {
261 /* TARGET_H8300 */
262 /* 0 1 2 3 4 5 6 7 */
263 /* 8 9 10 11 12 13 14 15 */
264 /* 16 17 18 19 20 21 22 23 */
265 /* 24 25 26 27 28 29 30 31 */
266 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
267 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
268 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
269 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
270 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
271 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
272 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
273 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
274 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
275 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
276 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
277 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
278 },
279 {
280 /* TARGET_H8300H */
281 /* 0 1 2 3 4 5 6 7 */
282 /* 8 9 10 11 12 13 14 15 */
283 /* 16 17 18 19 20 21 22 23 */
284 /* 24 25 26 27 28 29 30 31 */
285 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
286 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
287 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
1e5bdc40 288 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
c4dfc70c
DD		 289 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
290 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
291 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
1e5bdc40 292 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
c4dfc70c
DD		 293 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
294 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
295 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
296 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
297 },
298 {
299 /* TARGET_H8300S */
300 /* 0 1 2 3 4 5 6 7 */
301 /* 8 9 10 11 12 13 14 15 */
302 /* 16 17 18 19 20 21 22 23 */
303 /* 24 25 26 27 28 29 30 31 */
304 { INL, INL, INL, INL, INL, INL, INL, INL,
305 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
306 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
1e5bdc40 307 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
c4dfc70c
DD		 308 { INL, INL, INL, INL, INL, INL, INL, INL,
309 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
310 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
1e5bdc40 311 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
c4dfc70c
DD		 312 { INL, INL, INL, INL, INL, INL, INL, INL,
313 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
314 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
315 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
316 }
317};
318
319#undef INL
320#undef ROT
321#undef LOP
322#undef SPC
323
324enum h8_cpu
325{
326 H8_300,
327 H8_300H,
328 H8_S
329};
330
48837e29
DE		 331/* Initialize various cpu specific globals at start up. */
332
c5387660
JM		 333static void
334h8300_option_override (void)
48837e29 335{
cbf1b2da
KH		 336 static const char *const h8_push_ops[2] = { "push" , "push.l" };
337 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
338 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
339
f4ea8112
SKS		 340#ifndef OBJECT_FORMAT_ELF
341 if (TARGET_H8300SX)
342 {
343 error ("-msx is not supported in coff");
344 target_flags |= MASK_H8300S;
345 }
346#endif
347
48837e29
DE		 348 if (TARGET_H8300)
349 {
350 cpu_type = (int) CPU_H8300;
351 h8_reg_names = names_big;
352 }
353 else
354 {
3db11b5c 355 /* For this we treat the H8/300H and H8S the same. */
48837e29
DE		 356 cpu_type = (int) CPU_H8300H;
357 h8_reg_names = names_extended;
358 }
359 h8_push_op = h8_push_ops[cpu_type];
360 h8_pop_op = h8_pop_ops[cpu_type];
361 h8_mov_op = h8_mov_ops[cpu_type];
17f0f8fa
KH		 362
363 if (!TARGET_H8300S && TARGET_MAC)
400500c4 364 {
c725bd79 365 error ("-ms2600 is used without -ms");
5463c726 366 target_flags |= MASK_H8300S_1;
400500c4 367 }
920e86b8 368
39ba95b5
VK		 369 if (TARGET_H8300 && TARGET_NORMAL_MODE)
370 {
f4ea8112 371 error ("-mn is used without -mh or -ms or -msx");
39ba95b5
VK		 372 target_flags ^= MASK_NORMAL_MODE;
373 }
c4dfc70c 374
f4ea8112
SKS		 375 if (! TARGET_H8300S && TARGET_EXR)
376 {
377 error ("-mexr is used without -ms");
378 target_flags |= MASK_H8300S_1;
379 }
380
381 if (TARGET_H8300 && TARGET_INT32)
382 {
383 error ("-mint32 is not supported for H8300 and H8300L targets");
384 target_flags ^= MASK_INT32;
385 }
386
387 if ((!TARGET_H8300S && TARGET_EXR) && (!TARGET_H8300SX && TARGET_EXR))
388 {
389 error ("-mexr is used without -ms or -msx");
390 target_flags |= MASK_H8300S_1;
391 }
392
393 if ((!TARGET_H8300S && TARGET_NEXR) && (!TARGET_H8300SX && TARGET_NEXR))
394 {
395 warning (OPT_mno_exr, "-mno-exr valid only with -ms or -msx \
396 - Option ignored!");
397 }
398
2f6bd6eb
YS		 399#ifdef H8300_LINUX
400 if ((TARGET_NORMAL_MODE))
401 {
402 error ("-mn is not supported for linux targets");
403 target_flags ^= MASK_NORMAL_MODE;
404 }
405#endif
406
8bd06267 407 /* Some of the shifts are optimized for speed by default.
c4dfc70c 408 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
8bd06267 409 If optimizing for size, change shift_alg for those shift to
c4dfc70c 410 SHIFT_LOOP. */
b6894857 411 if (optimize_size)
c4dfc70c 412 {
b6894857
KH		 413 /* H8/300 */
414 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
415 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
416 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
417 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
c4dfc70c 418
b6894857
KH		 419 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
420 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
c4dfc70c 421
b6894857
KH		 422 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
423 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
c4dfc70c 424
b6894857
KH		 425 /* H8/300H */
426 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
427 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
c4dfc70c 428
b6894857
KH		 429 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
430 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
c4dfc70c 431
b6894857
KH		 432 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
433 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
434 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
435 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
c4dfc70c
DD		 436
437 /* H8S */
b6894857 438 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
c4dfc70c 439 }
beed8fc0
AO		 440
441 /* Work out a value for MOVE_RATIO. */
442 if (!TARGET_H8300SX)
443 {
444 /* Memory-memory moves are quite expensive without the
445 h8sx instructions. */
446 h8300_move_ratio = 3;
447 }
448 else if (flag_omit_frame_pointer)
449 {
450 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
451 sometimes be as short as two individual memory-to-memory moves,
452 but since they use all the call-saved registers, it seems better
453 to allow up to three moves here. */
454 h8300_move_ratio = 4;
455 }
456 else if (optimize_size)
457 {
458 /* In this case we don't use movmd sequences since they tend
459 to be longer than calls to memcpy(). Memory-to-memory
460 moves are cheaper than for !TARGET_H8300SX, so it makes
461 sense to have a slightly higher threshold. */
462 h8300_move_ratio = 4;
463 }
464 else
465 {
466 /* We use movmd sequences for some moves since it can be quicker
467 than calling memcpy(). The sequences will need to save and
468 restore er6 though, so bump up the cost. */
469 h8300_move_ratio = 6;
470 }
0685e770
DD		 471
472 /* This target defaults to strict volatile bitfields. */
36acc1a2 473 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
0685e770 474 flag_strict_volatile_bitfields = 1;
beed8fc0
AO		 475}
476
e9eba255
KH		 477/* Return the byte register name for a register rtx X. B should be 0
478 if you want a lower byte register. B should be 1 if you want an
479 upper byte register. */
480
9c188705 481static const char *
cb713a8d 482byte_reg (rtx x, int b)
07aae5c2 483{
9cbcd983
KH		 484 static const char *const names_small[] = {
485 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
486 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
487 };
07aae5c2 488
8c440872 489 gcc_assert (REG_P (x));
500fc80f 490
07aae5c2
SC		 491 return names_small[REGNO (x) * 2 + b];
492}
493
494/* REGNO must be saved/restored across calls if this macro is true. */
48837e29 495
9cbcd983 496#define WORD_REG_USED(regno) \
d60004ee 497 (regno < SP_REG \
9cbcd983
KH		 498 /* No need to save registers if this function will not return. */ \
499 && ! TREE_THIS_VOLATILE (current_function_decl) \
3cfa3702 500 && (h8300_saveall_function_p (current_function_decl) \
9cbcd983 501 /* Save any call saved register that was used. */ \
6fb5fa3c 502 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
9cbcd983 503 /* Save the frame pointer if it was used. */ \
6fb5fa3c 504 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
9cbcd983 505 /* Save any register used in an interrupt handler. */ \
e392d367 506 || (h8300_current_function_interrupt_function_p () \
6fb5fa3c 507 && df_regs_ever_live_p (regno)) \
9cbcd983
KH		 508 /* Save call clobbered registers in non-leaf interrupt \
509 handlers. */ \
e392d367 510 || (h8300_current_function_interrupt_function_p () \
9cbcd983 511 && call_used_regs[regno] \
416ff32e 512 && !crtl->is_leaf)))
07aae5c2 513
18674659 514/* We use this to wrap all emitted insns in the prologue. */
e7041fcc
DM		 515static rtx_insn *
516F (rtx_insn *x, bool set_it)
18674659 517{
c72ea086
DD		 518 if (set_it)
519 RTX_FRAME_RELATED_P (x) = 1;
18674659
DD		 520 return x;
521}
522
523/* Mark all the subexpressions of the PARALLEL rtx PAR as
524 frame-related. Return PAR.
525
526 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
527 PARALLEL rtx other than the first if they do not have the
528 FRAME_RELATED flag set on them. */
529static rtx
530Fpa (rtx par)
531{
532 int len = XVECLEN (par, 0);
533 int i;
534
535 for (i = 0; i < len; i++)
f698a4b1 536 RTX_FRAME_RELATED_P (XVECEXP (par, 0, i)) = 1;
18674659
DD		 537
538 return par;
539}
540
07aae5c2 541/* Output assembly language to FILE for the operation OP with operand size
48837e29 542 SIZE to adjust the stack pointer. */
48837e29 543
07aae5c2 544static void
c72ea086 545h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue)
07aae5c2 546{
72b1de44
KH		 547 /* If the frame size is 0, we don't have anything to do. */
548 if (size == 0)
f8b58e56 549 return;
72b1de44 550
68ee6df6
KH		 551 /* H8/300 cannot add/subtract a large constant with a single
552 instruction. If a temporary register is available, load the
553 constant to it and then do the addition. */
554 if (TARGET_H8300
555 && size > 4
556 && !h8300_current_function_interrupt_function_p ()
6de9cd9a 557 && !(cfun->static_chain_decl != NULL && sign < 0))
f8f26adc 558 {
68ee6df6 559 rtx r3 = gen_rtx_REG (Pmode, 3);
c72ea086 560 F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue);
18674659 561 F (emit_insn (gen_addhi3 (stack_pointer_rtx,
c72ea086 562 stack_pointer_rtx, r3)), in_prologue);
7b3d4613
KH		 563 }
564 else
565 {
68ee6df6
KH		 566 /* The stack adjustment made here is further optimized by the
567 splitter. In case of H8/300, the splitter always splits the
18674659
DD		 568 addition emitted here to make the adjustment interrupt-safe.
569 FIXME: We don't always tag those, because we don't know what
570 the splitter will do. */
72b1de44 571 if (Pmode == HImode)
18674659 572 {
e7041fcc
DM		 573 rtx_insn *x = emit_insn (gen_addhi3 (stack_pointer_rtx,
574 stack_pointer_rtx,
575 GEN_INT (sign * size)));
18674659 576 if (size < 4)
c72ea086 577 F (x, in_prologue);
18674659 578 }
72b1de44 579 else
18674659 580 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
c72ea086 581 stack_pointer_rtx, GEN_INT (sign * size))), in_prologue);
07aae5c2
SC		 582 }
583}
584
8682223f
KH		 585/* Round up frame size SIZE. */
586
e68d4dd1
UB		 587static HOST_WIDE_INT
588round_frame_size (HOST_WIDE_INT size)
8682223f 589{
489eda65
KH		 590 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
591 & -STACK_BOUNDARY / BITS_PER_UNIT);
8682223f
KH		 592}
593
594/* Compute which registers to push/pop.
595 Return a bit vector of registers. */
596
597static unsigned int
cb713a8d 598compute_saved_regs (void)
8682223f
KH		 599{
600 unsigned int saved_regs = 0;
601 int regno;
602
603 /* Construct a bit vector of registers to be pushed/popped. */
1807b726 604 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
8682223f
KH		 605 {
606 if (WORD_REG_USED (regno))
607 saved_regs |= 1 << regno;
608 }
609
610 /* Don't push/pop the frame pointer as it is treated separately. */
611 if (frame_pointer_needed)
1807b726 612 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
8682223f
KH		 613
614 return saved_regs;
615}
616
68ee6df6 617/* Emit an insn to push register RN. */
8682223f 618
8f1594b2 619static rtx
1901e8d6 620push (int rn, bool in_prologue)
8682223f 621{
68ee6df6
KH		 622 rtx reg = gen_rtx_REG (word_mode, rn);
623 rtx x;
624
513f31eb 625 if (TARGET_H8300)
68ee6df6 626 x = gen_push_h8300 (reg);
f24f0897 627 else if (!TARGET_NORMAL_MODE)
32da7865 628 x = gen_push_h8300hs_advanced (reg);
f24f0897
KH		 629 else
630 x = gen_push_h8300hs_normal (reg);
1901e8d6 631 x = F (emit_insn (x), in_prologue);
9690aa8e 632 add_reg_note (x, REG_INC, stack_pointer_rtx);
8f1594b2 633 return x;
8682223f
KH		 634}
635
68ee6df6 636/* Emit an insn to pop register RN. */
8682223f 637
8f1594b2 638static rtx
cb713a8d 639pop (int rn)
8682223f 640{
68ee6df6
KH		 641 rtx reg = gen_rtx_REG (word_mode, rn);
642 rtx x;
643
513f31eb 644 if (TARGET_H8300)
68ee6df6 645 x = gen_pop_h8300 (reg);
f24f0897 646 else if (!TARGET_NORMAL_MODE)
32da7865 647 x = gen_pop_h8300hs_advanced (reg);
f24f0897
KH		 648 else
649 x = gen_pop_h8300hs_normal (reg);
68ee6df6 650 x = emit_insn (x);
9690aa8e 651 add_reg_note (x, REG_INC, stack_pointer_rtx);
8f1594b2 652 return x;
8682223f 653}
07aae5c2 654
beed8fc0
AO		 655/* Emit an instruction to push or pop NREGS consecutive registers
656 starting at register REGNO. POP_P selects a pop rather than a
657 push and RETURN_P is true if the instruction should return.
658
659 It must be possible to do the requested operation in a single
660 instruction. If NREGS == 1 && !RETURN_P, use a normal push
661 or pop insn. Otherwise emit a parallel of the form:
662
663 (parallel
664 [(return) ;; if RETURN_P
665 (save or restore REGNO)
666 (save or restore REGNO + 1)
667 ...
668 (save or restore REGNO + NREGS - 1)
669 (set sp (plus sp (const_int adjust)))] */
670
671static void
ac447f25 672h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p)
beed8fc0
AO		 673{
674 int i, j;
675 rtvec vec;
18674659 676 rtx sp, offset, x;
beed8fc0
AO		 677
678 /* See whether we can use a simple push or pop. */
679 if (!return_p && nregs == 1)
680 {
681 if (pop_p)
682 pop (regno);
683 else
1901e8d6 684 push (regno, false);
beed8fc0
AO		 685 return;
686 }
687
688 /* We need one element for the return insn, if present, one for each
689 register, and one for stack adjustment. */
ac447f25 690 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1);
beed8fc0
AO		 691 sp = stack_pointer_rtx;
692 i = 0;
693
694 /* Add the return instruction. */
695 if (return_p)
696 {
3810076b 697 RTVEC_ELT (vec, i) = ret_rtx;
beed8fc0
AO		 698 i++;
699 }
700
701 /* Add the register moves. */
702 for (j = 0; j < nregs; j++)
703 {
704 rtx lhs, rhs;
705
706 if (pop_p)
707 {
708 /* Register REGNO + NREGS - 1 is popped first. Before the
709 stack adjustment, its slot is at address @sp. */
710 lhs = gen_rtx_REG (SImode, regno + j);
0a81f074
RS		 711 rhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp,
712 (nregs - j - 1) * 4));
beed8fc0
AO		 713 }
714 else
715 {
716 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
0a81f074 717 lhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, (j + 1) * -4));
beed8fc0
AO		 718 rhs = gen_rtx_REG (SImode, regno + j);
719 }
f7df4a84 720 RTVEC_ELT (vec, i + j) = gen_rtx_SET (lhs, rhs);
beed8fc0
AO		 721 }
722
723 /* Add the stack adjustment. */
724 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
f7df4a84 725 RTVEC_ELT (vec, i + j) = gen_rtx_SET (sp, gen_rtx_PLUS (Pmode, sp, offset));
beed8fc0 726
18674659
DD		 727 x = gen_rtx_PARALLEL (VOIDmode, vec);
728 if (!pop_p)
729 x = Fpa (x);
ac447f25
NC		 730
731 if (return_p)
732 emit_jump_insn (x);
733 else
734 emit_insn (x);
beed8fc0
AO		 735}
736
737/* Return true if X has the value sp + OFFSET. */
738
739static int
740h8300_stack_offset_p (rtx x, int offset)
741{
742 if (offset == 0)
743 return x == stack_pointer_rtx;
744
745 return (GET_CODE (x) == PLUS
746 && XEXP (x, 0) == stack_pointer_rtx
747 && GET_CODE (XEXP (x, 1)) == CONST_INT
748 && INTVAL (XEXP (x, 1)) == offset);
749}
750
751/* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
752 something that may be an ldm or stm instruction. If it fits
753 the required template, return the register it loads or stores,
754 otherwise return -1.
755
756 LOAD_P is true if X should be a load, false if it should be a store.
757 NREGS is the number of registers that the whole instruction is expected
758 to load or store. INDEX is the index of the register that X should
759 load or store, relative to the lowest-numbered register. */
760
761static int
762h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
763{
764 int regindex, memindex, offset;
765
766 if (load_p)
767 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
768 else
769 memindex = 0, regindex = 1, offset = (index + 1) * -4;
770
771 if (GET_CODE (x) == SET
772 && GET_CODE (XEXP (x, regindex)) == REG
773 && GET_CODE (XEXP (x, memindex)) == MEM
774 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
775 return REGNO (XEXP (x, regindex));
776
777 return -1;
778}
779
780/* Return true if the elements of VEC starting at FIRST describe an
781 ldm or stm instruction (LOAD_P says which). */
782
981c7dce 783int
beed8fc0
AO		 784h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
785{
786 rtx last;
787 int nregs, i, regno, adjust;
788
789 /* There must be a stack adjustment, a register move, and at least one
790 other operation (a return or another register move). */
791 if (GET_NUM_ELEM (vec) < 3)
792 return false;
793
794 /* Get the range of registers to be pushed or popped. */
795 nregs = GET_NUM_ELEM (vec) - first - 1;
796 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
797
798 /* Check that the call to h8300_ldm_stm_regno succeeded and
799 that we're only dealing with GPRs. */
800 if (regno < 0 || regno + nregs > 8)
801 return false;
802
803 /* 2-register h8s instructions must start with an even-numbered register.
804 3- and 4-register instructions must start with er0 or er4. */
805 if (!TARGET_H8300SX)
806 {
807 if ((regno & 1) != 0)
808 return false;
809 if (nregs > 2 && (regno & 3) != 0)
810 return false;
811 }
812
813 /* Check the other loads or stores. */
814 for (i = 1; i < nregs; i++)
815 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
816 != regno + i)
817 return false;
818
819 /* Check the stack adjustment. */
820 last = RTVEC_ELT (vec, first + nregs);
821 adjust = (load_p ? nregs : -nregs) * 4;
822 return (GET_CODE (last) == SET
823 && SET_DEST (last) == stack_pointer_rtx
824 && h8300_stack_offset_p (SET_SRC (last), adjust));
825}
826
f0b6f9a6 827/* This is what the stack looks like after the prolog of
07aae5c2
SC		 828 a function with a frame has been set up:
829
48837e29
DE		 830 <args>
831 PC
832 FP <- fp
833 <locals>
8bd06267 834 <saved registers> <- sp
07aae5c2
SC		 835
836 This is what the stack looks like after the prolog of
837 a function which doesn't have a frame:
838
48837e29
DE		 839 <args>
840 PC
841 <locals>
8bd06267 842 <saved registers> <- sp
07aae5c2
SC		 843*/
844
68ee6df6 845/* Generate RTL code for the function prologue. */
8682223f 846
68ee6df6 847void
cb713a8d 848h8300_expand_prologue (void)
07aae5c2 849{
e651d484 850 int regno;
8682223f 851 int saved_regs;
cda4bd43 852 int n_regs;
07aae5c2 853
fabe72bb
JL		 854 /* If the current function has the OS_Task attribute set, then
855 we have a naked prologue. */
856 if (h8300_os_task_function_p (current_function_decl))
68ee6df6 857 return;
fabe72bb
JL		 858
859 if (h8300_monitor_function_p (current_function_decl))
f4ea8112
SKS		 860 /* The monitor function act as normal functions, which means it
861 can accept parameters and return values. In addition to this,
862 interrupts are masked in prologue and return with "rte" in epilogue. */
68ee6df6 863 emit_insn (gen_monitor_prologue ());
fabe72bb 864
48837e29
DE		 865 if (frame_pointer_needed)
866 {
07e4d94e 867 /* Push fp. */
1901e8d6 868 push (HARD_FRAME_POINTER_REGNUM, true);
ac447f25 869 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true);
a1616dd9 870 }
48837e29 871
8682223f
KH		 872 /* Push the rest of the registers in ascending order. */
873 saved_regs = compute_saved_regs ();
e651d484 874 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
cda4bd43 875 {
cda4bd43 876 n_regs = 1;
8682223f 877 if (saved_regs & (1 << regno))
a1616dd9
JL		 878 {
879 if (TARGET_H8300S)
880 {
cda4bd43 881 /* See how many registers we can push at the same time. */
beed8fc0 882 if ((!TARGET_H8300SX || (regno & 3) == 0)
8682223f 883 && ((saved_regs >> regno) & 0x0f) == 0x0f)
cda4bd43
KH		 884 n_regs = 4;
885
beed8fc0 886 else if ((!TARGET_H8300SX || (regno & 3) == 0)
8682223f 887 && ((saved_regs >> regno) & 0x07) == 0x07)
cda4bd43
KH		 888 n_regs = 3;
889
beed8fc0 890 else if ((!TARGET_H8300SX || (regno & 1) == 0)
8682223f 891 && ((saved_regs >> regno) & 0x03) == 0x03)
cda4bd43 892 n_regs = 2;
a1616dd9 893 }
cda4bd43 894
ac447f25 895 h8300_push_pop (regno, n_regs, false, false);
07aae5c2
SC		 896 }
897 }
1807b726
KH		 898
899 /* Leave room for locals. */
c72ea086 900 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
ed1332ee
NC		 901
902 if (flag_stack_usage_info)
903 current_function_static_stack_size
904 = round_frame_size (get_frame_size ())
905 + (__builtin_popcount (saved_regs) * UNITS_PER_WORD)
906 + (frame_pointer_needed ? UNITS_PER_WORD : 0);
07aae5c2
SC		 907}
908
e9eba255
KH		 909/* Return nonzero if we can use "rts" for the function currently being
910 compiled. */
911
68ee6df6 912int
cb713a8d 913h8300_can_use_return_insn_p (void)
68ee6df6
KH		 914{
915 return (reload_completed
916 && !frame_pointer_needed
917 && get_frame_size () == 0
918 && compute_saved_regs () == 0);
919}
07aae5c2 920
68ee6df6
KH		 921/* Generate RTL code for the function epilogue. */
922
923void
cb713a8d 924h8300_expand_epilogue (void)
07aae5c2 925{
e651d484 926 int regno;
8682223f 927 int saved_regs;
cda4bd43 928 int n_regs;
beed8fc0
AO		 929 HOST_WIDE_INT frame_size;
930 bool returned_p;
07aae5c2 931
e392d367 932 if (h8300_os_task_function_p (current_function_decl))
68ee6df6
KH		 933 /* OS_Task epilogues are nearly naked -- they just have an
934 rts instruction. */
935 return;
07aae5c2 936
beed8fc0
AO		 937 frame_size = round_frame_size (get_frame_size ());
938 returned_p = false;
939
1807b726 940 /* Deallocate locals. */
c72ea086 941 h8300_emit_stack_adjustment (1, frame_size, false);
1807b726 942
8682223f
KH		 943 /* Pop the saved registers in descending order. */
944 saved_regs = compute_saved_regs ();
e651d484 945 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
cda4bd43 946 {
cda4bd43 947 n_regs = 1;
8682223f 948 if (saved_regs & (1 << regno))
07aae5c2 949 {
a1616dd9
JL		 950 if (TARGET_H8300S)
951 {
cda4bd43 952 /* See how many registers we can pop at the same time. */
beed8fc0
AO		 953 if ((TARGET_H8300SX || (regno & 3) == 3)
954 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
cda4bd43
KH		 955 n_regs = 4;
956
beed8fc0
AO		 957 else if ((TARGET_H8300SX || (regno & 3) == 2)
958 && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
cda4bd43
KH		 959 n_regs = 3;
960
beed8fc0
AO		 961 else if ((TARGET_H8300SX || (regno & 1) == 1)
962 && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
cda4bd43 963 n_regs = 2;
a1616dd9 964 }
cda4bd43 965
beed8fc0
AO		 966 /* See if this pop would be the last insn before the return.
967 If so, use rte/l or rts/l instead of pop or ldm.l. */
968 if (TARGET_H8300SX
969 && !frame_pointer_needed
970 && frame_size == 0
971 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
972 returned_p = true;
973
ac447f25 974 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p);
07aae5c2 975 }
07aae5c2 976 }
48837e29 977
07e4d94e 978 /* Pop frame pointer if we had one. */
a1616dd9 979 if (frame_pointer_needed)
beed8fc0
AO		 980 {
981 if (TARGET_H8300SX)
982 returned_p = true;
ac447f25 983 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p);
beed8fc0
AO		 984 }
985
986 if (!returned_p)
3810076b 987 emit_jump_insn (ret_rtx);
68ee6df6 988}
a1616dd9 989
e392d367
KH		 990/* Return nonzero if the current function is an interrupt
991 function. */
992
993int
cb713a8d 994h8300_current_function_interrupt_function_p (void)
e392d367 995{
f4ea8112
SKS		 996 return (h8300_interrupt_function_p (current_function_decl));
997}
998
999int
1000h8300_current_function_monitor_function_p ()
1001{
1002 return (h8300_monitor_function_p (current_function_decl));
e392d367
KH		 1003}
1004
48837e29
DE		 1005/* Output assembly code for the start of the file. */
1006
1bc7c5b6
ZW		 1007static void
1008h8300_file_start (void)
48837e29 1009{
1bc7c5b6 1010 default_file_start ();
8bd06267 1011
2f6bd6eb 1012 if (TARGET_H8300SX)
beed8fc0 1013 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
a1616dd9 1014 else if (TARGET_H8300S)
1bc7c5b6 1015 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
2f6bd6eb
YS		 1016 else if (TARGET_H8300H)
1017 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
48837e29
DE		 1018}
1019
1020/* Output assembly language code for the end of file. */
1021
a5fe455b 1022static void
cb713a8d 1023h8300_file_end (void)
48837e29 1024{
a5fe455b 1025 fputs ("\t.end\n", asm_out_file);
07aae5c2
SC		 1026}
1027\f
3cee1a78
KH		 1028/* Split an add of a small constant into two adds/subs insns.
1029
1030 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1031 instead of adds/subs. */
009ac3d3
RH		 1032
1033void
ef4bddc2 1034split_adds_subs (machine_mode mode, rtx *operands)
3b7d443c 1035{
009ac3d3
RH		 1036 HOST_WIDE_INT val = INTVAL (operands[1]);
1037 rtx reg = operands[0];
9492393e
KH		 1038 HOST_WIDE_INT sign = 1;
1039 HOST_WIDE_INT amount;
590734b6 1040 rtx (*gen_add) (rtx, rtx, rtx);
3b7d443c 1041
9492393e
KH		 1042 /* Force VAL to be positive so that we do not have to consider the
1043 sign. */
1044 if (val < 0)
3b7d443c 1045 {
9492393e
KH		 1046 val = -val;
1047 sign = -1;
1048 }
3b7d443c 1049
3cee1a78
KH		 1050 switch (mode)
1051 {
1052 case HImode:
590734b6 1053 gen_add = gen_addhi3;
3cee1a78
KH		 1054 break;
1055
1056 case SImode:
590734b6 1057 gen_add = gen_addsi3;
3cee1a78
KH		 1058 break;
1059
1060 default:
8c440872 1061 gcc_unreachable ();
3cee1a78
KH		 1062 }
1063
9492393e
KH		 1064 /* Try different amounts in descending order. */
1065 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
1066 amount > 0;
1067 amount /= 2)
1068 {
1a63219b 1069 for (; val >= amount; val -= amount)
590734b6 1070 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
3b7d443c
JL		 1071 }
1072
9492393e 1073 return;
3b7d443c
JL		 1074}
1075
07aae5c2 1076/* Handle machine specific pragmas for compatibility with existing
48837e29 1077 compilers for the H8/300.
07aae5c2 1078
f411c849 1079 pragma saveall generates prologue/epilogue code which saves and
07aae5c2 1080 restores all the registers on function entry.
48837e29 1081
07aae5c2
SC		 1082 pragma interrupt saves and restores all registers, and exits with
1083 an rte instruction rather than an rts. A pointer to a function
1084 with this attribute may be safely used in an interrupt vector. */
48837e29 1085
8b97c5f8 1086void
cb713a8d 1087h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
07aae5c2 1088{
e392d367 1089 pragma_interrupt = 1;
8b97c5f8 1090}
05a81fe5 1091
8b97c5f8 1092void
cb713a8d 1093h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
8b97c5f8
ZW		 1094{
1095 pragma_saveall = 1;
07aae5c2 1096}
8b97c5f8 1097
64bead4c
KH		 1098/* If the next function argument with MODE and TYPE is to be passed in
1099 a register, return a reg RTX for the hard register in which to pass
1100 the argument. CUM represents the state after the last argument.
56f9413b 1101 If the argument is to be pushed, NULL_RTX is returned.
48837e29 1102
56f9413b
NF		 1103 On the H8/300 all normal args are pushed, unless -mquickcall in which
1104 case the first 3 arguments are passed in registers. */
1105
1106static rtx
ef4bddc2 1107h8300_function_arg (cumulative_args_t cum_v, machine_mode mode,
56f9413b 1108 const_tree type, bool named)
07aae5c2 1109{
d5cc9181
JR		 1110 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1111
0ea6f6a0
KH		 1112 static const char *const hand_list[] = {
1113 "__main",
1114 "__cmpsi2",
1115 "__divhi3",
1116 "__modhi3",
1117 "__udivhi3",
1118 "__umodhi3",
1119 "__divsi3",
1120 "__modsi3",
1121 "__udivsi3",
1122 "__umodsi3",
1123 "__mulhi3",
1124 "__mulsi3",
1125 "__reg_memcpy",
1126 "__reg_memset",
1127 "__ucmpsi2",
1128 0,
1129 };
1130
7192cbf1 1131 rtx result = NULL_RTX;
441d04c6 1132 const char *fname;
48837e29
DE		 1133 int regpass = 0;
1134
dd07092e
JL		 1135 /* Never pass unnamed arguments in registers. */
1136 if (!named)
7192cbf1 1137 return NULL_RTX;
dd07092e 1138
48837e29
DE		 1139 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1140 if (TARGET_QUICKCALL)
1141 regpass = 3;
1142
1143 /* If calling hand written assembler, use 4 regs of args. */
48837e29
DE		 1144 if (cum->libcall)
1145 {
441d04c6 1146 const char * const *p;
48837e29
DE		 1147
1148 fname = XSTR (cum->libcall, 0);
1149
1150 /* See if this libcall is one of the hand coded ones. */
48837e29
DE		 1151 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1152 ;
07aae5c2 1153
48837e29
DE		 1154 if (*p)
1155 regpass = 4;
1156 }
1157
1158 if (regpass)
1159 {
1160 int size;
1161
1162 if (mode == BLKmode)
1163 size = int_size_in_bytes (type);
1164 else
1165 size = GET_MODE_SIZE (mode);
1166
15e0e275
KH		 1167 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1168 && cum->nbytes / UNITS_PER_WORD <= 3)
1169 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
48837e29 1170 }
07aae5c2 1171
48837e29
DE		 1172 return result;
1173}
56f9413b
NF		 1174
1175/* Update the data in CUM to advance over an argument
1176 of mode MODE and data type TYPE.
1177 (TYPE is null for libcalls where that information may not be available.) */
1178
1179static void
ef4bddc2 1180h8300_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
56f9413b
NF		 1181 const_tree type, bool named ATTRIBUTE_UNUSED)
1182{
d5cc9181
JR		 1183 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1184
56f9413b
NF		 1185 cum->nbytes += (mode != BLKmode
1186 ? (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD
1187 : (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD);
1188}
1189
48837e29 1190\f
88cb339e
N		 1191/* Implements TARGET_REGISTER_MOVE_COST.
1192
1193 Any SI register-to-register move may need to be reloaded,
1194 so inmplement h8300_register_move_cost to return > 2 so that reload never
1195 shortcuts. */
1196
1197static int
ef4bddc2 1198h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
88cb339e
N		 1199 reg_class_t from, reg_class_t to)
1200{
1201 if (from == MAC_REGS || to == MAC_REG)
1202 return 6;
1203 else
1204 return 3;
1205}
1206
e9eba255
KH		 1207/* Compute the cost of an and insn. */
1208
3c50106f 1209static int
cb713a8d 1210h8300_and_costs (rtx x)
73cc75e9
KH		 1211{
1212 rtx operands[4];
1213
1214 if (GET_MODE (x) == QImode)
1215 return 1;
1216
1217 if (GET_MODE (x) != HImode
1218 && GET_MODE (x) != SImode)
1219 return 100;
1220
1221 operands[0] = NULL;
beed8fc0 1222 operands[1] = XEXP (x, 0);
73cc75e9
KH		 1223 operands[2] = XEXP (x, 1);
1224 operands[3] = x;
4f4ebda3 1225 return compute_logical_op_length (GET_MODE (x), operands) / 2;
73cc75e9
KH		 1226}
1227
e9eba255
KH		 1228/* Compute the cost of a shift insn. */
1229
3c50106f 1230static int
cb713a8d 1231h8300_shift_costs (rtx x)
ae557002
KH		 1232{
1233 rtx operands[4];
1234
1235 if (GET_MODE (x) != QImode
1236 && GET_MODE (x) != HImode
1237 && GET_MODE (x) != SImode)
1238 return 100;
1239
1240 operands[0] = NULL;
1241 operands[1] = NULL;
1242 operands[2] = XEXP (x, 1);
1243 operands[3] = x;
4f4ebda3 1244 return compute_a_shift_length (NULL, operands) / 2;
ae557002 1245}
3c50106f 1246
e9eba255
KH		 1247/* Worker function for TARGET_RTX_COSTS. */
1248
3c50106f 1249static bool
68f932c4
RS		 1250h8300_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
1251 int *total, bool speed)
3c50106f 1252{
beed8fc0
AO		 1253 if (TARGET_H8300SX && outer_code == MEM)
1254 {
1255 /* Estimate the number of execution states needed to calculate
1256 the address. */
1257 if (register_operand (x, VOIDmode)
1258 || GET_CODE (x) == POST_INC
1259 || GET_CODE (x) == POST_DEC
1260 || CONSTANT_P (x))
1261 *total = 0;
1262 else
1263 *total = COSTS_N_INSNS (1);
1264 return true;
1265 }
1266
3c50106f
RH		 1267 switch (code)
1268 {
08dca707
KH		 1269 case CONST_INT:
1270 {
1271 HOST_WIDE_INT n = INTVAL (x);
1272
beed8fc0
AO		 1273 if (TARGET_H8300SX)
1274 {
1275 /* Constant operands need the same number of processor
1276 states as register operands. Although we could try to
f40751dd 1277 use a size-based cost for !speed, the lack of
beed8fc0
AO		 1278 of a mode makes the results very unpredictable. */
1279 *total = 0;
1280 return true;
1281 }
358a11bb 1282 if (-4 <= n && n <= 4)
08dca707
KH		 1283 {
1284 switch ((int) n)
1285 {
1286 case 0:
1287 *total = 0;
1288 return true;
1289 case 1:
1290 case 2:
1291 case -1:
1292 case -2:
1293 *total = 0 + (outer_code == SET);
1294 return true;
1295 case 4:
1296 case -4:
1297 if (TARGET_H8300H || TARGET_H8300S)
1298 *total = 0 + (outer_code == SET);
1299 else
1300 *total = 1;
1301 return true;
1302 }
1303 }
1304 *total = 1;
1305 return true;
1306 }
1307
1308 case CONST:
1309 case LABEL_REF:
1310 case SYMBOL_REF:
beed8fc0
AO		 1311 if (TARGET_H8300SX)
1312 {
1313 /* See comment for CONST_INT. */
1314 *total = 0;
1315 return true;
1316 }
08dca707
KH		 1317 *total = 3;
1318 return true;
1319
1320 case CONST_DOUBLE:
1321 *total = 20;
1322 return true;
1323
f90b7a5a
PB		 1324 case COMPARE:
1325 if (XEXP (x, 1) == const0_rtx)
1326 *total = 0;
1327 return false;
1328
3c50106f 1329 case AND:
beed8fc0
AO		 1330 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
1331 || !h8300_src_operand (XEXP (x, 1), VOIDmode))
1332 return false;
3c50106f
RH		 1333 *total = COSTS_N_INSNS (h8300_and_costs (x));
1334 return true;
1335
1336 /* We say that MOD and DIV are so expensive because otherwise we'll
1337 generate some really horrible code for division of a power of two. */
1338 case MOD:
1339 case DIV:
beed8fc0
AO		 1340 case UMOD:
1341 case UDIV:
1342 if (TARGET_H8300SX)
1343 switch (GET_MODE (x))
1344 {
1345 case QImode:
1346 case HImode:
f40751dd 1347 *total = COSTS_N_INSNS (!speed ? 4 : 10);
beed8fc0
AO		 1348 return false;
1349
1350 case SImode:
f40751dd 1351 *total = COSTS_N_INSNS (!speed ? 4 : 18);
beed8fc0
AO		 1352 return false;
1353
1354 default:
1355 break;
1356 }
1357 *total = COSTS_N_INSNS (12);
3c50106f
RH		 1358 return true;
1359
1360 case MULT:
beed8fc0
AO		 1361 if (TARGET_H8300SX)
1362 switch (GET_MODE (x))
1363 {
1364 case QImode:
1365 case HImode:
1366 *total = COSTS_N_INSNS (2);
1367 return false;
1368
1369 case SImode:
1370 *total = COSTS_N_INSNS (5);
1371 return false;
1372
1373 default:
1374 break;
1375 }
1376 *total = COSTS_N_INSNS (4);
3c50106f
RH		 1377 return true;
1378
1379 case ASHIFT:
1380 case ASHIFTRT:
1381 case LSHIFTRT:
beed8fc0
AO		 1382 if (h8sx_binary_shift_operator (x, VOIDmode))
1383 {
1384 *total = COSTS_N_INSNS (2);
1385 return false;
1386 }
1387 else if (h8sx_unary_shift_operator (x, VOIDmode))
1388 {
1389 *total = COSTS_N_INSNS (1);
1390 return false;
1391 }
3c50106f
RH		 1392 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1393 return true;
1394
1395 case ROTATE:
1396 case ROTATERT:
1397 if (GET_MODE (x) == HImode)
1398 *total = 2;
1399 else
1400 *total = 8;
1401 return true;
1402
1403 default:
beed8fc0
AO		 1404 *total = COSTS_N_INSNS (1);
1405 return false;
3c50106f
RH		 1406 }
1407}
48837e29 1408\f
07aae5c2
SC		 1409/* Documentation for the machine specific operand escapes:
1410
48837e29
DE		 1411 'E' like s but negative.
1412 'F' like t but negative.
1413 'G' constant just the negative
15dc331e
JL		 1414 'R' print operand as a byte:8 address if appropriate, else fall back to
1415 'X' handling.
48837e29 1416 'S' print operand as a long word
07aae5c2 1417 'T' print operand as a word
48837e29
DE		 1418 'V' find the set bit, and print its number.
1419 'W' find the clear bit, and print its number.
1420 'X' print operand as a byte
07aae5c2 1421 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
15dc331e 1422 If this operand isn't a register, fall back to 'R' handling.
48837e29 1423 'Z' print int & 7.
b059c02a 1424 'c' print the opcode corresponding to rtl
da55315a 1425 'e' first word of 32-bit value - if reg, then least reg. if mem
48837e29 1426 then least. if const then most sig word
da55315a 1427 'f' second word of 32-bit value - if reg, then biggest reg. if mem
48837e29 1428 then +2. if const then least sig word
07aae5c2
SC		 1429 'j' print operand as condition code.
1430 'k' print operand as reverse condition code.
beed8fc0
AO		 1431 'm' convert an integer operand to a size suffix (.b, .w or .l)
1432 'o' print an integer without a leading '#'
da55315a
KH		 1433 's' print as low byte of 16-bit value
1434 't' print as high byte of 16-bit value
1435 'w' print as low byte of 32-bit value
1436 'x' print as 2nd byte of 32-bit value
1437 'y' print as 3rd byte of 32-bit value
1438 'z' print as msb of 32-bit value
48837e29 1439*/
07aae5c2
SC		 1440
1441/* Return assembly language string which identifies a comparison type. */
1442
441d04c6 1443static const char *
cb713a8d 1444cond_string (enum rtx_code code)
07aae5c2
SC		 1445{
1446 switch (code)
1447 {
1448 case NE:
1449 return "ne";
1450 case EQ:
1451 return "eq";
1452 case GE:
1453 return "ge";
1454 case GT:
1455 return "gt";
1456 case LE:
1457 return "le";
1458 case LT:
1459 return "lt";
1460 case GEU:
1461 return "hs";
1462 case GTU:
1463 return "hi";
1464 case LEU:
1465 return "ls";
1466 case LTU:
1467 return "lo";
1468 default:
8c440872 1469 gcc_unreachable ();
07aae5c2
SC		 1470 }
1471}
1472
1473/* Print operand X using operand code CODE to assembly language output file
1474 FILE. */
1475
88cb339e
N		 1476static void
1477h8300_print_operand (FILE *file, rtx x, int code)
07aae5c2 1478{
269c14e1 1479 /* This is used for communication between codes V,W,Z and Y. */
07aae5c2
SC		 1480 static int bitint;
1481
1482 switch (code)
1483 {
f46b8378
SKS		 1484 case 'C':
1485 if (h8300_constant_length (x) == 2)
1486 fprintf (file, ":16");
1487 else
1488 fprintf (file, ":32");
1489 return;
48837e29
DE		 1490 case 'E':
1491 switch (GET_CODE (x))
1492 {
1493 case REG:
1494 fprintf (file, "%sl", names_big[REGNO (x)]);
1495 break;
1496 case CONST_INT:
b47900aa 1497 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
48837e29
DE		 1498 break;
1499 default:
8c440872 1500 gcc_unreachable ();
48837e29
DE		 1501 }
1502 break;
1503 case 'F':
1504 switch (GET_CODE (x))
1505 {
1506 case REG:
1507 fprintf (file, "%sh", names_big[REGNO (x)]);
1508 break;
1509 case CONST_INT:
b47900aa 1510 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
48837e29
DE		 1511 break;
1512 default:
8c440872 1513 gcc_unreachable ();
48837e29
DE		 1514 }
1515 break;
07aae5c2 1516 case 'G':
8c440872 1517 gcc_assert (GET_CODE (x) == CONST_INT);
b47900aa 1518 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
07aae5c2 1519 break;
48837e29
DE		 1520 case 'S':
1521 if (GET_CODE (x) == REG)
1522 fprintf (file, "%s", names_extended[REGNO (x)]);
07aae5c2 1523 else
48837e29 1524 goto def;
07aae5c2 1525 break;
48837e29
DE		 1526 case 'T':
1527 if (GET_CODE (x) == REG)
1528 fprintf (file, "%s", names_big[REGNO (x)]);
07aae5c2 1529 else
48837e29 1530 goto def;
07aae5c2 1531 break;
48837e29 1532 case 'V':
0f6b820c
KP		 1533 bitint = (INTVAL (x) & 0xffff);
1534 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1)
1535 bitint = exact_log2 (bitint & 0xff);
1536 else
1537 bitint = exact_log2 ((bitint >> 8) & 0xff);
8c440872 1538 gcc_assert (bitint >= 0);
4d4d89e2 1539 fprintf (file, "#%d", bitint);
07aae5c2 1540 break;
48837e29 1541 case 'W':
0f6b820c
KP		 1542 bitint = ((~INTVAL (x)) & 0xffff);
1543 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 )
1544 bitint = exact_log2 (bitint & 0xff);
1545 else
1546 bitint = (exact_log2 ((bitint >> 8) & 0xff));
8c440872 1547 gcc_assert (bitint >= 0);
4d4d89e2 1548 fprintf (file, "#%d", bitint);
07aae5c2 1549 break;
15dc331e 1550 case 'R':
48837e29
DE		 1551 case 'X':
1552 if (GET_CODE (x) == REG)
1553 fprintf (file, "%s", byte_reg (x, 0));
1554 else
1555 goto def;
1556 break;
1557 case 'Y':
8c440872 1558 gcc_assert (bitint >= 0);
48837e29
DE		 1559 if (GET_CODE (x) == REG)
1560 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1561 else
88cb339e 1562 h8300_print_operand (file, x, 'R');
48837e29
DE		 1563 bitint = -1;
1564 break;
1565 case 'Z':
1566 bitint = INTVAL (x);
07aae5c2
SC		 1567 fprintf (file, "#%d", bitint & 7);
1568 break;
b059c02a
KH		 1569 case 'c':
1570 switch (GET_CODE (x))
1571 {
1572 case IOR:
1573 fprintf (file, "or");
1574 break;
1575 case XOR:
1576 fprintf (file, "xor");
1577 break;
5abfd1af
KH		 1578 case AND:
1579 fprintf (file, "and");
1580 break;
b059c02a
KH		 1581 default:
1582 break;
1583 }
1584 break;
07aae5c2
SC		 1585 case 'e':
1586 switch (GET_CODE (x))
1587 {
1588 case REG:
48837e29
DE		 1589 if (TARGET_H8300)
1590 fprintf (file, "%s", names_big[REGNO (x)]);
1591 else
1592 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
07aae5c2
SC		 1593 break;
1594 case MEM:
88cb339e 1595 h8300_print_operand (file, x, 0);
07aae5c2
SC		 1596 break;
1597 case CONST_INT:
b47900aa 1598 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
07aae5c2 1599 break;
808fbfac
JL		 1600 case CONST_DOUBLE:
1601 {
1602 long val;
1603 REAL_VALUE_TYPE rv;
1604 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1605 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
441d04c6 1606 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
808fbfac
JL		 1607 break;
1608 }
07aae5c2 1609 default:
8c440872 1610 gcc_unreachable ();
07aae5c2
SC		 1611 break;
1612 }
1613 break;
07aae5c2
SC		 1614 case 'f':
1615 switch (GET_CODE (x))
1616 {
1617 case REG:
48837e29
DE		 1618 if (TARGET_H8300)
1619 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1620 else
1621 fprintf (file, "%s", names_big[REGNO (x)]);
07aae5c2 1622 break;
07aae5c2 1623 case MEM:
b72f00af 1624 x = adjust_address (x, HImode, 2);
88cb339e 1625 h8300_print_operand (file, x, 0);
07aae5c2 1626 break;
07aae5c2 1627 case CONST_INT:
b47900aa 1628 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
07aae5c2 1629 break;
808fbfac
JL		 1630 case CONST_DOUBLE:
1631 {
1632 long val;
1633 REAL_VALUE_TYPE rv;
1634 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1635 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
441d04c6 1636 fprintf (file, "#%ld", (val & 0xffff));
808fbfac
JL		 1637 break;
1638 }
07aae5c2 1639 default:
8c440872 1640 gcc_unreachable ();
07aae5c2
SC		 1641 }
1642 break;
07aae5c2 1643 case 'j':
761c70aa 1644 fputs (cond_string (GET_CODE (x)), file);
07aae5c2 1645 break;
07aae5c2 1646 case 'k':
761c70aa 1647 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
07aae5c2 1648 break;
beed8fc0 1649 case 'm':
8c440872
NS		 1650 gcc_assert (GET_CODE (x) == CONST_INT);
1651 switch (INTVAL (x))
1652 {
1653 case 1:
1654 fputs (".b", file);
1655 break;
1656
1657 case 2:
1658 fputs (".w", file);
1659 break;
1660
1661 case 4:
1662 fputs (".l", file);
1663 break;
1664
1665 default:
1666 gcc_unreachable ();
1667 }
beed8fc0
AO		 1668 break;
1669 case 'o':
88cb339e 1670 h8300_print_operand_address (file, x);
beed8fc0 1671 break;
48837e29
DE		 1672 case 's':
1673 if (GET_CODE (x) == CONST_INT)
b47900aa 1674 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
48837e29
DE		 1675 else
1676 fprintf (file, "%s", byte_reg (x, 0));
1677 break;
1678 case 't':
1679 if (GET_CODE (x) == CONST_INT)
b47900aa 1680 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
48837e29
DE		 1681 else
1682 fprintf (file, "%s", byte_reg (x, 1));
1683 break;
48837e29
DE		 1684 case 'w':
1685 if (GET_CODE (x) == CONST_INT)
b47900aa 1686 fprintf (file, "#%ld", INTVAL (x) & 0xff);
48837e29 1687 else
a1616dd9
JL		 1688 fprintf (file, "%s",
1689 byte_reg (x, TARGET_H8300 ? 2 : 0));
48837e29
DE		 1690 break;
1691 case 'x':
1692 if (GET_CODE (x) == CONST_INT)
b47900aa 1693 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
48837e29 1694 else
a1616dd9
JL		 1695 fprintf (file, "%s",
1696 byte_reg (x, TARGET_H8300 ? 3 : 1));
48837e29
DE		 1697 break;
1698 case 'y':
1699 if (GET_CODE (x) == CONST_INT)
b47900aa 1700 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
48837e29
DE		 1701 else
1702 fprintf (file, "%s", byte_reg (x, 0));
1703 break;
1704 case 'z':
1705 if (GET_CODE (x) == CONST_INT)
b47900aa 1706 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
48837e29
DE		 1707 else
1708 fprintf (file, "%s", byte_reg (x, 1));
1709 break;
1710
07aae5c2 1711 default:
48837e29 1712 def:
07aae5c2
SC		 1713 switch (GET_CODE (x))
1714 {
1715 case REG:
48837e29
DE		 1716 switch (GET_MODE (x))
1717 {
1718 case QImode:
269c14e1 1719#if 0 /* Is it asm ("mov.b %0,r2l", ...) */
48837e29
DE		 1720 fprintf (file, "%s", byte_reg (x, 0));
1721#else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1722 fprintf (file, "%s", names_big[REGNO (x)]);
1723#endif
1724 break;
1725 case HImode:
1726 fprintf (file, "%s", names_big[REGNO (x)]);
1727 break;
1728 case SImode:
8977e8a7 1729 case SFmode:
48837e29
DE		 1730 fprintf (file, "%s", names_extended[REGNO (x)]);
1731 break;
1732 default:
8c440872 1733 gcc_unreachable ();
48837e29 1734 }
07aae5c2
SC		 1735 break;
1736
1737 case MEM:
87e4ee91
KH		 1738 {
1739 rtx addr = XEXP (x, 0);
1740
1741 fprintf (file, "@");
1742 output_address (addr);
1743
beed8fc0
AO		 1744 /* Add a length suffix to constant addresses. Although this
1745 is often unnecessary, it helps to avoid ambiguity in the
1746 syntax of mova. If we wrote an insn like:
1747
1748 mova/w.l @(1,@foo.b),er0
1749
1750 then .b would be considered part of the symbol name.
1751 Adding a length after foo will avoid this. */
1752 if (CONSTANT_P (addr))
1753 switch (code)
1754 {
1755 case 'R':
1756 /* Used for mov.b and bit operations. */
1757 if (h8300_eightbit_constant_address_p (addr))
1758 {
1759 fprintf (file, ":8");
1760 break;
1761 }
1762
1763 /* Fall through. We should not get here if we are
1764 processing bit operations on H8/300 or H8/300H
1765 because 'U' constraint does not allow bit
1766 operations on the tiny area on these machines. */
1767
1768 case 'X':
1769 case 'T':
1770 case 'S':
1771 if (h8300_constant_length (addr) == 2)
1772 fprintf (file, ":16");
1773 else
1774 fprintf (file, ":32");
1775 break;
1776 default:
1777 break;
1778 }
87e4ee91 1779 }
07aae5c2
SC		 1780 break;
1781
1782 case CONST_INT:
1783 case SYMBOL_REF:
1784 case CONST:
1785 case LABEL_REF:
1786 fprintf (file, "#");
88cb339e 1787 h8300_print_operand_address (file, x);
07aae5c2 1788 break;
808fbfac
JL		 1789 case CONST_DOUBLE:
1790 {
1791 long val;
1792 REAL_VALUE_TYPE rv;
1793 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1794 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
441d04c6 1795 fprintf (file, "#%ld", val);
808fbfac
JL		 1796 break;
1797 }
441d04c6
KG		 1798 default:
1799 break;
07aae5c2
SC		 1800 }
1801 }
1802}
1803
88cb339e
N		 1804/* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1805
1806static bool
1807h8300_print_operand_punct_valid_p (unsigned char code)
1808{
1809 return (code == '#');
1810}
1811
07aae5c2
SC		 1812/* Output assembly language output for the address ADDR to FILE. */
1813
88cb339e
N		 1814static void
1815h8300_print_operand_address (FILE *file, rtx addr)
07aae5c2 1816{
beed8fc0
AO		 1817 rtx index;
1818 int size;
1819
07aae5c2
SC		 1820 switch (GET_CODE (addr))
1821 {
1822 case REG:
48837e29 1823 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
07aae5c2
SC		 1824 break;
1825
1826 case PRE_DEC:
48837e29 1827 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
07aae5c2
SC		 1828 break;
1829
1830 case POST_INC:
48837e29 1831 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
07aae5c2
SC		 1832 break;
1833
beed8fc0
AO		 1834 case PRE_INC:
1835 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1836 break;
1837
1838 case POST_DEC:
1839 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
1840 break;
1841
07aae5c2
SC		 1842 case PLUS:
1843 fprintf (file, "(");
beed8fc0
AO		 1844
1845 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
1846 if (GET_CODE (index) == REG)
07aae5c2
SC		 1847 {
1848 /* reg,foo */
88cb339e 1849 h8300_print_operand_address (file, XEXP (addr, 1));
07aae5c2 1850 fprintf (file, ",");
beed8fc0
AO		 1851 switch (size)
1852 {
1853 case 0:
88cb339e 1854 h8300_print_operand_address (file, index);
beed8fc0
AO		 1855 break;
1856
1857 case 1:
88cb339e 1858 h8300_print_operand (file, index, 'X');
beed8fc0
AO		 1859 fputs (".b", file);
1860 break;
1861
1862 case 2:
88cb339e 1863 h8300_print_operand (file, index, 'T');
beed8fc0
AO		 1864 fputs (".w", file);
1865 break;
1866
1867 case 4:
88cb339e 1868 h8300_print_operand (file, index, 'S');
beed8fc0
AO		 1869 fputs (".l", file);
1870 break;
1871 }
88cb339e 1872 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
07aae5c2
SC		 1873 }
1874 else
1875 {
1876 /* foo+k */
88cb339e 1877 h8300_print_operand_address (file, XEXP (addr, 0));
07aae5c2 1878 fprintf (file, "+");
88cb339e 1879 h8300_print_operand_address (file, XEXP (addr, 1));
07aae5c2
SC		 1880 }
1881 fprintf (file, ")");
1882 break;
1883
1884 case CONST_INT:
48837e29 1885 {
da55315a 1886 /* Since the H8/300 only has 16-bit pointers, negative values are also
48837e29
DE		 1887 those >= 32768. This happens for example with pointer minus a
1888 constant. We don't want to turn (char *p - 2) into
1889 (char *p + 65534) because loop unrolling can build upon this
1890 (IE: char *p + 131068). */
1891 int n = INTVAL (addr);
1892 if (TARGET_H8300)
1893 n = (int) (short) n;
7a770d8b 1894 fprintf (file, "%d", n);
48837e29
DE		 1895 break;
1896 }
07aae5c2
SC		 1897
1898 default:
1899 output_addr_const (file, addr);
1900 break;
1901 }
1902}
1903\f
07aae5c2
SC		 1904/* Output all insn addresses and their sizes into the assembly language
1905 output file. This is helpful for debugging whether the length attributes
1906 in the md file are correct. This is not meant to be a user selectable
1907 option. */
1908
1909void
e7041fcc 1910final_prescan_insn (rtx_insn *insn, rtx *operand ATTRIBUTE_UNUSED,
cb713a8d 1911 int num_operands ATTRIBUTE_UNUSED)
07aae5c2
SC		 1912{
1913 /* This holds the last insn address. */
1914 static int last_insn_address = 0;
1915
7798db98 1916 const int uid = INSN_UID (insn);
07aae5c2
SC		 1917
1918 if (TARGET_ADDRESSES)
1919 {
9d98a694
AO		 1920 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1921 INSN_ADDRESSES (uid) - last_insn_address);
1922 last_insn_address = INSN_ADDRESSES (uid);
07aae5c2
SC		 1923 }
1924}
1925
48837e29
DE		 1926/* Prepare for an SI sized move. */
1927
1928int
1a793acf 1929h8300_expand_movsi (rtx operands[])
07aae5c2 1930{
48837e29
DE		 1931 rtx src = operands[1];
1932 rtx dst = operands[0];
1933 if (!reload_in_progress && !reload_completed)
1934 {
1935 if (!register_operand (dst, GET_MODE (dst)))
1936 {
1937 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1938 emit_move_insn (tmp, src);
1939 operands[1] = tmp;
1940 }
1941 }
1942 return 0;
1943}
1944
7b5cbb57
AS		 1945/* Given FROM and TO register numbers, say whether this elimination is allowed.
1946 Frame pointer elimination is automatically handled.
1947
1948 For the h8300, if frame pointer elimination is being done, we would like to
1949 convert ap and rp into sp, not fp.
1950
1951 All other eliminations are valid. */
1952
1953static bool
1954h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
1955{
1956 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
1957}
1958
5efd84c5
NF		 1959/* Conditionally modify register usage based on target flags. */
1960
1961static void
1962h8300_conditional_register_usage (void)
1963{
1964 if (!TARGET_MAC)
1965 fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1;
1966}
1967
48837e29 1968/* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
07e4d94e
KH		 1969 Define the offset between two registers, one to be eliminated, and
1970 the other its replacement, at the start of a routine. */
07aae5c2 1971
48837e29 1972int
cb713a8d 1973h8300_initial_elimination_offset (int from, int to)
48837e29 1974{
d18ad191
KH		 1975 /* The number of bytes that the return address takes on the stack. */
1976 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
48837e29 1977
1807b726
KH		 1978 /* The number of bytes that the saved frame pointer takes on the stack. */
1979 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1980
1981 /* The number of bytes that the saved registers, excluding the frame
1982 pointer, take on the stack. */
1983 int saved_regs_size = 0;
48837e29 1984
1807b726
KH		 1985 /* The number of bytes that the locals takes on the stack. */
1986 int frame_size = round_frame_size (get_frame_size ());
48837e29 1987
1807b726 1988 int regno;
48837e29 1989
1807b726
KH		 1990 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1991 if (WORD_REG_USED (regno))
1992 saved_regs_size += UNITS_PER_WORD;
48837e29 1993
1807b726
KH		 1994 /* Adjust saved_regs_size because the above loop took the frame
1995 pointer int account. */
1996 saved_regs_size -= fp_size;
39ba95b5 1997
8c440872 1998 switch (to)
1807b726 1999 {
8c440872 2000 case HARD_FRAME_POINTER_REGNUM:
1807b726
KH		 2001 switch (from)
2002 {
2003 case ARG_POINTER_REGNUM:
2004 return pc_size + fp_size;
2005 case RETURN_ADDRESS_POINTER_REGNUM:
2006 return fp_size;
2007 case FRAME_POINTER_REGNUM:
2008 return -saved_regs_size;
2009 default:
8c440872 2010 gcc_unreachable ();
1807b726 2011 }
8c440872
NS		 2012 break;
2013 case STACK_POINTER_REGNUM:
1807b726
KH		 2014 switch (from)
2015 {
2016 case ARG_POINTER_REGNUM:
2017 return pc_size + saved_regs_size + frame_size;
2018 case RETURN_ADDRESS_POINTER_REGNUM:
2019 return saved_regs_size + frame_size;
2020 case FRAME_POINTER_REGNUM:
2021 return frame_size;
2022 default:
8c440872 2023 gcc_unreachable ();
1807b726 2024 }
8c440872
NS		 2025 break;
2026 default:
2027 gcc_unreachable ();
1807b726 2028 }
8c440872 2029 gcc_unreachable ();
48837e29
DE		 2030}
2031
e9eba255
KH		 2032/* Worker function for RETURN_ADDR_RTX. */
2033
1aae372e 2034rtx
cb713a8d 2035h8300_return_addr_rtx (int count, rtx frame)
1aae372e
JL		 2036{
2037 rtx ret;
2038
2039 if (count == 0)
2040 ret = gen_rtx_MEM (Pmode,
2041 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
2042 else if (flag_omit_frame_pointer)
2043 return (rtx) 0;
2044 else
2045 ret = gen_rtx_MEM (Pmode,
2046 memory_address (Pmode,
0a81f074
RS		 2047 plus_constant (Pmode, frame,
2048 UNITS_PER_WORD)));
1aae372e
JL		 2049 set_mem_alias_set (ret, get_frame_alias_set ());
2050 return ret;
2051}
2052
48837e29
DE		 2053/* Update the condition code from the insn. */
2054
441d04c6 2055void
e8a54173 2056notice_update_cc (rtx body, rtx_insn *insn)
48837e29 2057{
d99c740f
KH		 2058 rtx set;
2059
48837e29
DE		 2060 switch (get_attr_cc (insn))
2061 {
2062 case CC_NONE:
269c14e1 2063 /* Insn does not affect CC at all. */
48837e29
DE		 2064 break;
2065
2066 case CC_NONE_0HIT:
269c14e1 2067 /* Insn does not change CC, but the 0'th operand has been changed. */
48837e29 2068 if (cc_status.value1 != 0
1ccbefce 2069 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
48837e29 2070 cc_status.value1 = 0;
d4d6d0ce
KH		 2071 if (cc_status.value2 != 0
2072 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
2073 cc_status.value2 = 0;
48837e29
DE		 2074 break;
2075
065bbfe6 2076 case CC_SET_ZN:
1ccbefce 2077 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
269c14e1
DE		 2078 The V flag is unusable. The C flag may or may not be known but
2079 that's ok because alter_cond will change tests to use EQ/NE. */
48837e29 2080 CC_STATUS_INIT;
269c14e1 2081 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
d99c740f
KH		 2082 set = single_set (insn);
2083 cc_status.value1 = SET_SRC (set);
2084 if (SET_DEST (set) != cc0_rtx)
2085 cc_status.value2 = SET_DEST (set);
48837e29
DE		 2086 break;
2087
065bbfe6 2088 case CC_SET_ZNV:
1ccbefce 2089 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
065bbfe6
JL		 2090 The C flag may or may not be known but that's ok because
2091 alter_cond will change tests to use EQ/NE. */
2092 CC_STATUS_INIT;
2093 cc_status.flags |= CC_NO_CARRY;
d99c740f
KH		 2094 set = single_set (insn);
2095 cc_status.value1 = SET_SRC (set);
2096 if (SET_DEST (set) != cc0_rtx)
c8fcf20c
KH		 2097 {
2098 /* If the destination is STRICT_LOW_PART, strip off
2099 STRICT_LOW_PART. */
2100 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
2101 cc_status.value2 = XEXP (SET_DEST (set), 0);
2102 else
2103 cc_status.value2 = SET_DEST (set);
2104 }
065bbfe6
JL		 2105 break;
2106
beed8fc0
AO		 2107 case CC_COMPARE:
2108 /* The insn is a compare instruction. */
2109 CC_STATUS_INIT;
2110 cc_status.value1 = SET_SRC (body);
2111 break;
2112
2113 case CC_CLOBBER:
2114 /* Insn doesn't leave CC in a usable state. */
2115 CC_STATUS_INIT;
2116 break;
2117 }
2118}
beed8fc0
AO		 2119\f
2120/* Given that X occurs in an address of the form (plus X constant),
2121 return the part of X that is expected to be a register. There are
2122 four kinds of addressing mode to recognize:
2123
2124 @(dd,Rn)
2125 @(dd,RnL.b)
2126 @(dd,Rn.w)
2127 @(dd,ERn.l)
2128
2129 If SIZE is nonnull, and the address is one of the last three forms,
2130 set *SIZE to the index multiplication factor. Set it to 0 for
2131 plain @(dd,Rn) addresses.
2132
2133 MODE is the mode of the value being accessed. It can be VOIDmode
2134 if the address is known to be valid, but its mode is unknown. */
2135
f52d97da 2136static rtx
ef4bddc2 2137h8300_get_index (rtx x, machine_mode mode, int *size)
beed8fc0
AO		 2138{
2139 int dummy, factor;
2140
2141 if (size == 0)
2142 size = &dummy;
2143
2144 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
2145 if (TARGET_H8300SX
2146 && factor <= 4
2147 && (mode == VOIDmode
2148 || GET_MODE_CLASS (mode) == MODE_INT
2149 || GET_MODE_CLASS (mode) == MODE_FLOAT))
2150 {
2151 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
2152 {
2153 /* When accessing byte-sized values, the index can be
2154 a zero-extended QImode or HImode register. */
2155 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
2156 return XEXP (x, 0);
2157 }
2158 else
2159 {
2160 /* We're looking for addresses of the form:
2161
2162 (mult X I)
2163 or (mult (zero_extend X) I)
2164
2165 where I is the size of the operand being accessed.
2166 The canonical form of the second expression is:
2167
2168 (and (mult (subreg X) I) J)
2169
2170 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2171 rtx index;
2172
2173 if (GET_CODE (x) == AND
2174 && GET_CODE (XEXP (x, 1)) == CONST_INT
2175 && (factor == 0
2176 || INTVAL (XEXP (x, 1)) == 0xff * factor
2177 || INTVAL (XEXP (x, 1)) == 0xffff * factor))
2178 {
2179 index = XEXP (x, 0);
2180 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
2181 }
2182 else
2183 {
2184 index = x;
2185 *size = 4;
2186 }
2187
2188 if (GET_CODE (index) == MULT
2189 && GET_CODE (XEXP (index, 1)) == CONST_INT
2190 && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
2191 return XEXP (index, 0);
2192 }
2193 }
2194 *size = 0;
2195 return x;
2196}
2197\f
f52d97da
AS		 2198/* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2199
2200 On the H8/300, the predecrement and postincrement address depend thus
2201 (the amount of decrement or increment being the length of the operand). */
2202
2203static bool
5bfed9a9
GJL		 2204h8300_mode_dependent_address_p (const_rtx addr,
2205 addr_space_t as ATTRIBUTE_UNUSED)
f52d97da
AS		 2206{
2207 if (GET_CODE (addr) == PLUS
2208 && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0))
2209 return true;
2210
2211 return false;
2212}
2213\f
beed8fc0
AO		 2214static const h8300_length_table addb_length_table =
2215{
2216 /* #xx Rs @aa @Rs @xx */
2217 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2218 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2219 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2220 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2221};
2222
2223static const h8300_length_table addw_length_table =
2224{
2225 /* #xx Rs @aa @Rs @xx */
2226 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2227 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2228 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2229 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2230};
2231
2232static const h8300_length_table addl_length_table =
2233{
2234 /* #xx Rs @aa @Rs @xx */
2235 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2236 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2237 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2238 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2239};
2240
2241#define logicb_length_table addb_length_table
2242#define logicw_length_table addw_length_table
2243
2244static const h8300_length_table logicl_length_table =
2245{
2246 /* #xx Rs @aa @Rs @xx */
2247 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2248 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2249 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2250 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2251};
2252
2253static const h8300_length_table movb_length_table =
2254{
2255 /* #xx Rs @aa @Rs @xx */
2256 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2257 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2258 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2259 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2260};
2261
2262#define movw_length_table movb_length_table
2263
2264static const h8300_length_table movl_length_table =
2265{
2266 /* #xx Rs @aa @Rs @xx */
2267 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2268 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2269 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2270 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2271};
2272
2273/* Return the size of the given address or displacement constant. */
2274
2275static unsigned int
2276h8300_constant_length (rtx constant)
2277{
2278 /* Check for (@d:16,Reg). */
2279 if (GET_CODE (constant) == CONST_INT
2280 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
2281 return 2;
2282
2283 /* Check for (@d:16,Reg) in cases where the displacement is
2284 an absolute address. */
2285 if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
2286 return 2;
2287
2288 return 4;
2289}
2290
2291/* Return the size of a displacement field in address ADDR, which should
2292 have the form (plus X constant). SIZE is the number of bytes being
2293 accessed. */
2294
2295static unsigned int
2296h8300_displacement_length (rtx addr, int size)
2297{
2298 rtx offset;
2299
2300 offset = XEXP (addr, 1);
2301
2302 /* Check for @(d:2,Reg). */
2303 if (register_operand (XEXP (addr, 0), VOIDmode)
2304 && GET_CODE (offset) == CONST_INT
2305 && (INTVAL (offset) == size
2306 || INTVAL (offset) == size * 2
2307 || INTVAL (offset) == size * 3))
2308 return 0;
2309
2310 return h8300_constant_length (offset);
2311}
2312
0a2aaacc
KG		 2313/* Store the class of operand OP in *OPCLASS and return the length of any
2314 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
beed8fc0
AO		 2315 can be null if only the length is needed. */
2316
2317static unsigned int
0a2aaacc 2318h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
beed8fc0
AO		 2319{
2320 enum h8300_operand_class dummy;
2321
0a2aaacc
KG		 2322 if (opclass == 0)
2323 opclass = &dummy;
beed8fc0
AO		 2324
2325 if (CONSTANT_P (op))
2326 {
0a2aaacc 2327 *opclass = H8OP_IMMEDIATE;
beed8fc0
AO		 2328
2329 /* Byte-sized immediates are stored in the opcode fields. */
2330 if (size == 1)
2331 return 0;
2332
2333 /* If this is a 32-bit instruction, see whether the constant
2334 will fit into a 16-bit immediate field. */
2335 if (TARGET_H8300SX
2336 && size == 4
2337 && GET_CODE (op) == CONST_INT
2338 && IN_RANGE (INTVAL (op), 0, 0xffff))
2339 return 2;
2340
2341 return size;
2342 }
2343 else if (GET_CODE (op) == MEM)
2344 {
2345 op = XEXP (op, 0);
2346 if (CONSTANT_P (op))
2347 {
0a2aaacc 2348 *opclass = H8OP_MEM_ABSOLUTE;
beed8fc0
AO		 2349 return h8300_constant_length (op);
2350 }
2351 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
2352 {
0a2aaacc 2353 *opclass = H8OP_MEM_COMPLEX;
beed8fc0
AO		 2354 return h8300_displacement_length (op, size);
2355 }
2356 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
2357 {
0a2aaacc 2358 *opclass = H8OP_MEM_COMPLEX;
beed8fc0
AO		 2359 return 0;
2360 }
2361 else if (register_operand (op, VOIDmode))
2362 {
0a2aaacc 2363 *opclass = H8OP_MEM_BASE;
beed8fc0
AO		 2364 return 0;
2365 }
2366 }
8c440872 2367 gcc_assert (register_operand (op, VOIDmode));
0a2aaacc 2368 *opclass = H8OP_REGISTER;
8c440872 2369 return 0;
beed8fc0
AO		 2370}
2371
2372/* Return the length of the instruction described by TABLE given that
2373 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2374 and OP2 must be an h8300_src_operand. */
2375
2376static unsigned int
2377h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
2378{
2379 enum h8300_operand_class op1_class, op2_class;
2380 unsigned int size, immediate_length;
2381
2382 size = GET_MODE_SIZE (GET_MODE (op1));
2383 immediate_length = (h8300_classify_operand (op1, size, &op1_class)
2384 + h8300_classify_operand (op2, size, &op2_class));
2385 return immediate_length + (*table)[op1_class - 1][op2_class];
2386}
2387
2388/* Return the length of a unary instruction such as neg or not given that
2389 its operand is OP. */
2390
2391unsigned int
2392h8300_unary_length (rtx op)
2393{
0a2aaacc 2394 enum h8300_operand_class opclass;
beed8fc0
AO		 2395 unsigned int size, operand_length;
2396
2397 size = GET_MODE_SIZE (GET_MODE (op));
0a2aaacc
KG		 2398 operand_length = h8300_classify_operand (op, size, &opclass);
2399 switch (opclass)
beed8fc0
AO		 2400 {
2401 case H8OP_REGISTER:
2402 return 2;
2403
2404 case H8OP_MEM_BASE:
2405 return (size == 4 ? 6 : 4);
2406
2407 case H8OP_MEM_ABSOLUTE:
2408 return operand_length + (size == 4 ? 6 : 4);
2409
2410 case H8OP_MEM_COMPLEX:
2411 return operand_length + 6;
2412
2413 default:
8c440872 2414 gcc_unreachable ();
beed8fc0
AO		 2415 }
2416}
2417
2418/* Likewise short immediate instructions such as add.w #xx:3,OP. */
2419
2420static unsigned int
2421h8300_short_immediate_length (rtx op)
2422{
0a2aaacc 2423 enum h8300_operand_class opclass;
beed8fc0
AO		 2424 unsigned int size, operand_length;
2425
2426 size = GET_MODE_SIZE (GET_MODE (op));
0a2aaacc 2427 operand_length = h8300_classify_operand (op, size, &opclass);
beed8fc0 2428
0a2aaacc 2429 switch (opclass)
beed8fc0
AO		 2430 {
2431 case H8OP_REGISTER:
2432 return 2;
2433
2434 case H8OP_MEM_BASE:
2435 case H8OP_MEM_ABSOLUTE:
2436 case H8OP_MEM_COMPLEX:
2437 return 4 + operand_length;
2438
2439 default:
8c440872 2440 gcc_unreachable ();
beed8fc0
AO		 2441 }
2442}
2443
2444/* Likewise bitfield load and store instructions. */
48837e29 2445
beed8fc0
AO		 2446static unsigned int
2447h8300_bitfield_length (rtx op, rtx op2)
2448{
0a2aaacc 2449 enum h8300_operand_class opclass;
beed8fc0
AO		 2450 unsigned int size, operand_length;
2451
2452 if (GET_CODE (op) == REG)
2453 op = op2;
8c440872 2454 gcc_assert (GET_CODE (op) != REG);
beed8fc0
AO		 2455
2456 size = GET_MODE_SIZE (GET_MODE (op));
0a2aaacc 2457 operand_length = h8300_classify_operand (op, size, &opclass);
beed8fc0 2458
0a2aaacc 2459 switch (opclass)
beed8fc0
AO		 2460 {
2461 case H8OP_MEM_BASE:
2462 case H8OP_MEM_ABSOLUTE:
2463 case H8OP_MEM_COMPLEX:
2464 return 4 + operand_length;
2465
2466 default:
8c440872 2467 gcc_unreachable ();
07aae5c2 2468 }
48837e29
DE		 2469}
2470
beed8fc0 2471/* Calculate the length of general binary instruction INSN using TABLE. */
8ccf5d5f 2472
beed8fc0 2473static unsigned int
e7041fcc 2474h8300_binary_length (rtx_insn *insn, const h8300_length_table *table)
8ccf5d5f 2475{
beed8fc0
AO		 2476 rtx set;
2477
2478 set = single_set (insn);
8c440872 2479 gcc_assert (set);
beed8fc0
AO		 2480
2481 if (BINARY_P (SET_SRC (set)))
2482 return h8300_length_from_table (XEXP (SET_SRC (set), 0),
2483 XEXP (SET_SRC (set), 1), table);
beed8fc0 2484 else
8c440872
NS		 2485 {
2486 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
2487 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
2488 XEXP (XEXP (SET_SRC (set), 1), 1),
2489 table);
2490 }
8ccf5d5f
KH		 2491}
2492
beed8fc0
AO		 2493/* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2494 memory reference and either (1) it has the form @(d:16,Rn) or
2495 (2) its address has the code given by INC_CODE. */
8ccf5d5f 2496
beed8fc0
AO		 2497static bool
2498h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
8ccf5d5f 2499{
beed8fc0
AO		 2500 rtx addr;
2501 unsigned int size;
2502
2503 if (GET_CODE (op) != MEM)
2504 return false;
2505
2506 addr = XEXP (op, 0);
2507 size = GET_MODE_SIZE (GET_MODE (op));
2508 if (size != 1 && size != 2)
2509 return false;
2510
2511 return (GET_CODE (addr) == inc_code
2512 || (GET_CODE (addr) == PLUS
2513 && GET_CODE (XEXP (addr, 0)) == REG
2514 && h8300_displacement_length (addr, size) == 2));
8ccf5d5f
KH		 2515}
2516
beed8fc0
AO		 2517/* Calculate the length of move instruction INSN using the given length
2518 table. Although the tables are correct for most cases, there is some
2519 irregularity in the length of mov.b and mov.w. The following forms:
8ccf5d5f 2520
beed8fc0
AO		 2521 mov @ERs+, Rd
2522 mov @(d:16,ERs), Rd
2523 mov Rs, @-ERd
2524 mov Rs, @(d:16,ERd)
2525
2526 are two bytes shorter than most other "mov Rs, @complex" or
2527 "mov @complex,Rd" combinations. */
2528
2529static unsigned int
2530h8300_move_length (rtx *operands, const h8300_length_table *table)
8ccf5d5f 2531{
beed8fc0
AO		 2532 unsigned int size;
2533
2534 size = h8300_length_from_table (operands[0], operands[1], table);
2535 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
2536 size -= 2;
2537 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
2538 size -= 2;
2539 return size;
8ccf5d5f
KH		 2540}
2541
beed8fc0
AO		 2542/* Return the length of a mova instruction with the given operands.
2543 DEST is the register destination, SRC is the source address and
2544 OFFSET is the 16-bit or 32-bit displacement. */
2873836b 2545
beed8fc0
AO		 2546static unsigned int
2547h8300_mova_length (rtx dest, rtx src, rtx offset)
2873836b 2548{
beed8fc0
AO		 2549 unsigned int size;
2550
2551 size = (2
2552 + h8300_constant_length (offset)
2553 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
2554 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
2555 size += 2;
2556 return size;
2873836b
KH		 2557}
2558
beed8fc0
AO		 2559/* Compute the length of INSN based on its length_table attribute.
2560 OPERANDS is the array of its operands. */
2873836b 2561
beed8fc0 2562unsigned int
e7041fcc 2563h8300_insn_length_from_table (rtx_insn *insn, rtx * operands)
2873836b 2564{
beed8fc0
AO		 2565 switch (get_attr_length_table (insn))
2566 {
2567 case LENGTH_TABLE_NONE:
8c440872 2568 gcc_unreachable ();
beed8fc0
AO		 2569
2570 case LENGTH_TABLE_ADDB:
2571 return h8300_binary_length (insn, &addb_length_table);
2572
2573 case LENGTH_TABLE_ADDW:
2574 return h8300_binary_length (insn, &addw_length_table);
2575
2576 case LENGTH_TABLE_ADDL:
2577 return h8300_binary_length (insn, &addl_length_table);
2578
2579 case LENGTH_TABLE_LOGICB:
2580 return h8300_binary_length (insn, &logicb_length_table);
2581
2582 case LENGTH_TABLE_MOVB:
2583 return h8300_move_length (operands, &movb_length_table);
2584
2585 case LENGTH_TABLE_MOVW:
2586 return h8300_move_length (operands, &movw_length_table);
2587
2588 case LENGTH_TABLE_MOVL:
2589 return h8300_move_length (operands, &movl_length_table);
2590
2591 case LENGTH_TABLE_MOVA:
2592 return h8300_mova_length (operands[0], operands[1], operands[2]);
2593
2594 case LENGTH_TABLE_MOVA_ZERO:
2595 return h8300_mova_length (operands[0], operands[1], const0_rtx);
2596
2597 case LENGTH_TABLE_UNARY:
2598 return h8300_unary_length (operands[0]);
2599
2600 case LENGTH_TABLE_MOV_IMM4:
2601 return 2 + h8300_classify_operand (operands[0], 0, 0);
2602
2603 case LENGTH_TABLE_SHORT_IMMEDIATE:
2604 return h8300_short_immediate_length (operands[0]);
2605
2606 case LENGTH_TABLE_BITFIELD:
2607 return h8300_bitfield_length (operands[0], operands[1]);
2608
2609 case LENGTH_TABLE_BITBRANCH:
2610 return h8300_bitfield_length (operands[1], operands[2]) - 2;
8c440872
NS		 2611
2612 default:
2613 gcc_unreachable ();
beed8fc0 2614 }
2873836b
KH		 2615}
2616
beed8fc0
AO		 2617/* Return true if LHS and RHS are memory references that can be mapped
2618 to the same h8sx assembly operand. LHS appears as the destination of
2619 an instruction and RHS appears as a source.
f9d2de4d 2620
beed8fc0
AO		 2621 Three cases are allowed:
2622
2623 - RHS is @+Rn or @-Rn, LHS is @Rn
2624 - RHS is @Rn, LHS is @Rn+ or @Rn-
2625 - RHS and LHS have the same address and neither has side effects. */
2626
2627bool
2628h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
f9d2de4d 2629{
beed8fc0
AO		 2630 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
2631 {
2632 rhs = XEXP (rhs, 0);
2633 lhs = XEXP (lhs, 0);
2634
2635 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
2636 return rtx_equal_p (XEXP (rhs, 0), lhs);
2637
2638 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
2639 return rtx_equal_p (rhs, XEXP (lhs, 0));
2640
2641 if (rtx_equal_p (rhs, lhs))
2642 return true;
2643 }
2644 return false;
f9d2de4d
KH		 2645}
2646
beed8fc0
AO		 2647/* Return true if OPERANDS[1] can be mapped to the same assembly
2648 operand as OPERANDS[0]. */
f9d2de4d 2649
beed8fc0
AO		 2650bool
2651h8300_operands_match_p (rtx *operands)
f9d2de4d 2652{
beed8fc0
AO		 2653 if (register_operand (operands[0], VOIDmode)
2654 && register_operand (operands[1], VOIDmode))
2655 return true;
f9d2de4d 2656
beed8fc0
AO		 2657 if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
2658 return true;
2659
2660 return false;
f9d2de4d 2661}
beed8fc0
AO		 2662\f
2663/* Try using movmd to move LENGTH bytes from memory region SRC to memory
2664 region DEST. The two regions do not overlap and have the common
2665 alignment given by ALIGNMENT. Return true on success.
717d8b71 2666
beed8fc0
AO		 2667 Using movmd for variable-length moves seems to involve some
2668 complex trade-offs. For instance:
b059c02a 2669
beed8fc0
AO		 2670 - Preparing for a movmd instruction is similar to preparing
2671 for a memcpy. The main difference is that the arguments
2672 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2673
2674 - Since movmd clobbers the frame pointer, we need to save
2675 and restore it somehow when frame_pointer_needed. This can
2676 sometimes make movmd sequences longer than calls to memcpy().
2677
2678 - The counter register is 16 bits, so the instruction is only
2679 suitable for variable-length moves when sizeof (size_t) == 2.
2680 That's only true in normal mode.
2681
2682 - We will often lack static alignment information. Falling back
2683 on movmd.b would likely be slower than calling memcpy(), at least
2684 for big moves.
2685
2686 This function therefore only uses movmd when the length is a
2687 known constant, and only then if -fomit-frame-pointer is in
2688 effect or if we're not optimizing for size.
2689
2690 At the moment the function uses movmd for all in-range constants,
2691 but it might be better to fall back on memcpy() for large moves
2692 if ALIGNMENT == 1. */
2693
2694bool
2695h8sx_emit_movmd (rtx dest, rtx src, rtx length,
2696 HOST_WIDE_INT alignment)
b059c02a 2697{
beed8fc0
AO		 2698 if (!flag_omit_frame_pointer && optimize_size)
2699 return false;
b059c02a 2700
beed8fc0
AO		 2701 if (GET_CODE (length) == CONST_INT)
2702 {
2703 rtx dest_reg, src_reg, first_dest, first_src;
2704 HOST_WIDE_INT n;
2705 int factor;
2706
2707 /* Use movmd.l if the alignment allows it, otherwise fall back
2708 on movmd.b. */
2709 factor = (alignment >= 2 ? 4 : 1);
2710
2711 /* Make sure the length is within range. We can handle counter
2712 values up to 65536, although HImode truncation will make
2713 the count appear negative in rtl dumps. */
2714 n = INTVAL (length);
2715 if (n <= 0 || n / factor > 65536)
2716 return false;
2717
2718 /* Create temporary registers for the source and destination
2719 pointers. Initialize them to the start of each region. */
2720 dest_reg = copy_addr_to_reg (XEXP (dest, 0));
2721 src_reg = copy_addr_to_reg (XEXP (src, 0));
2722
2723 /* Create references to the movmd source and destination blocks. */
2724 first_dest = replace_equiv_address (dest, dest_reg);
2725 first_src = replace_equiv_address (src, src_reg);
2726
f5541398
RS		 2727 set_mem_size (first_dest, n & -factor);
2728 set_mem_size (first_src, n & -factor);
beed8fc0
AO		 2729
2730 length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode));
2731 emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor)));
2732
2733 if ((n & -factor) != n)
2734 {
2735 /* Move SRC and DEST past the region we just copied.
2736 This is done to update the memory attributes. */
2737 dest = adjust_address (dest, BLKmode, n & -factor);
2738 src = adjust_address (src, BLKmode, n & -factor);
2739
2740 /* Replace the addresses with the source and destination
2741 registers, which movmd has left with the right values. */
2742 dest = replace_equiv_address (dest, dest_reg);
2743 src = replace_equiv_address (src, src_reg);
2744
2745 /* Mop up the left-over bytes. */
2746 if (n & 2)
2747 emit_move_insn (adjust_address (dest, HImode, 0),
2748 adjust_address (src, HImode, 0));
2749 if (n & 1)
2750 emit_move_insn (adjust_address (dest, QImode, n & 2),
2751 adjust_address (src, QImode, n & 2));
2752 }
2753 return true;
2754 }
2755 return false;
b059c02a
KH		 2756}
2757
beed8fc0 2758/* Move ADDR into er6 after pushing its old value onto the stack. */
48837e29 2759
beed8fc0
AO		 2760void
2761h8300_swap_into_er6 (rtx addr)
48837e29 2762{
1901e8d6 2763 rtx insn = push (HARD_FRAME_POINTER_REGNUM, false);
8f1594b2
RH		 2764 if (frame_pointer_needed)
2765 add_reg_note (insn, REG_CFA_DEF_CFA,
0a81f074 2766 plus_constant (Pmode, gen_rtx_MEM (Pmode, stack_pointer_rtx),
8f1594b2
RH		 2767 2 * UNITS_PER_WORD));
2768 else
2769 add_reg_note (insn, REG_CFA_ADJUST_CFA,
f7df4a84 2770 gen_rtx_SET (stack_pointer_rtx,
0a81f074 2771 plus_constant (Pmode, stack_pointer_rtx, 4)));
8f1594b2 2772
beed8fc0
AO		 2773 emit_move_insn (hard_frame_pointer_rtx, addr);
2774 if (REGNO (addr) == SP_REG)
2775 emit_move_insn (hard_frame_pointer_rtx,
0a81f074 2776 plus_constant (Pmode, hard_frame_pointer_rtx,
beed8fc0
AO		 2777 GET_MODE_SIZE (word_mode)));
2778}
07aae5c2 2779
beed8fc0
AO		 2780/* Move the current value of er6 into ADDR and pop its old value
2781 from the stack. */
2782
2783void
2784h8300_swap_out_of_er6 (rtx addr)
2785{
8f1594b2
RH		 2786 rtx insn;
2787
beed8fc0
AO		 2788 if (REGNO (addr) != SP_REG)
2789 emit_move_insn (addr, hard_frame_pointer_rtx);
8f1594b2
RH		 2790
2791 insn = pop (HARD_FRAME_POINTER_REGNUM);
8f1594b2
RH		 2792 if (frame_pointer_needed)
2793 add_reg_note (insn, REG_CFA_DEF_CFA,
0a81f074
RS		 2794 plus_constant (Pmode, hard_frame_pointer_rtx,
2795 2 * UNITS_PER_WORD));
8f1594b2
RH		 2796 else
2797 add_reg_note (insn, REG_CFA_ADJUST_CFA,
f7df4a84 2798 gen_rtx_SET (stack_pointer_rtx,
0a81f074 2799 plus_constant (Pmode, stack_pointer_rtx, -4)));
07aae5c2 2800}
48837e29 2801\f
7948a9ea
KH		 2802/* Return the length of mov instruction. */
2803
2804unsigned int
2805compute_mov_length (rtx *operands)
2806{
2807 /* If the mov instruction involves a memory operand, we compute the
2808 length, assuming the largest addressing mode is used, and then
2809 adjust later in the function. Otherwise, we compute and return
2810 the exact length in one step. */
ef4bddc2 2811 machine_mode mode = GET_MODE (operands[0]);
7948a9ea
KH		 2812 rtx dest = operands[0];
2813 rtx src = operands[1];
2814 rtx addr;
2815
2816 if (GET_CODE (src) == MEM)
2817 addr = XEXP (src, 0);
2818 else if (GET_CODE (dest) == MEM)
2819 addr = XEXP (dest, 0);
2820 else
2821 addr = NULL_RTX;
2822
2823 if (TARGET_H8300)
2824 {
2825 unsigned int base_length;
2826
2827 switch (mode)
2828 {
2829 case QImode:
2830 if (addr == NULL_RTX)
2831 return 2;
2832
2833 /* The eightbit addressing is available only in QImode, so
2834 go ahead and take care of it. */
2835 if (h8300_eightbit_constant_address_p (addr))
2836 return 2;
2837
2838 base_length = 4;
2839 break;
2840
2841 case HImode:
2842 if (addr == NULL_RTX)
2843 {
2844 if (REG_P (src))
2845 return 2;
2846
2847 if (src == const0_rtx)
2848 return 2;
2849
2850 return 4;
2851 }
2852
2853 base_length = 4;
2854 break;
2855
2856 case SImode:
2857 if (addr == NULL_RTX)
2858 {
2859 if (REG_P (src))
2860 return 4;
2861
2862 if (GET_CODE (src) == CONST_INT)
2863 {
2864 if (src == const0_rtx)
2865 return 4;
2866
2867 if ((INTVAL (src) & 0xffff) == 0)
2868 return 6;
2869
2870 if ((INTVAL (src) & 0xffff) == 0)
2871 return 6;
f5139cc5
KH		 2872
2873 if ((INTVAL (src) & 0xffff)
2874 == ((INTVAL (src) >> 16) & 0xffff))
2875 return 6;
7948a9ea
KH		 2876 }
2877 return 8;
2878 }
2879
2880 base_length = 8;
2881 break;
2882
2883 case SFmode:
2884 if (addr == NULL_RTX)
2885 {
2886 if (REG_P (src))
2887 return 4;
2888
ceaaaeab 2889 if (satisfies_constraint_G (src))
2c4a71b3
KH		 2890 return 4;
2891
81983b04 2892 return 8;
7948a9ea
KH		 2893 }
2894
2895 base_length = 8;
2896 break;
2897
2898 default:
8c440872 2899 gcc_unreachable ();
7948a9ea
KH		 2900 }
2901
2902 /* Adjust the length based on the addressing mode used.
2903 Specifically, we subtract the difference between the actual
2904 length and the longest one, which is @(d:16,Rs). For SImode
2905 and SFmode, we double the adjustment because two mov.w are
2906 used to do the job. */
2907
2908 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2909 if (GET_CODE (addr) == PRE_DEC
2910 || GET_CODE (addr) == POST_INC)
2911 {
2912 if (mode == QImode || mode == HImode)
2913 return base_length - 2;
2914 else
2915 /* In SImode and SFmode, we use two mov.w instructions, so
2a43945f 2916 double the adjustment. */
7948a9ea
KH		 2917 return base_length - 4;
2918 }
2919
2920 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2921 in SImode and SFmode, the second mov.w involves an address
2922 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2923 only 2 bytes. */
2924 if (GET_CODE (addr) == REG)
2925 return base_length - 2;
2926
2927 return base_length;
2928 }
2929 else
2930 {
2931 unsigned int base_length;
2932
2933 switch (mode)
2934 {
2935 case QImode:
2936 if (addr == NULL_RTX)
2937 return 2;
2938
2939 /* The eightbit addressing is available only in QImode, so
2940 go ahead and take care of it. */
2941 if (h8300_eightbit_constant_address_p (addr))
2942 return 2;
2943
2944 base_length = 8;
2945 break;
2946
2947 case HImode:
2948 if (addr == NULL_RTX)
2949 {
2950 if (REG_P (src))
2951 return 2;
2952
2953 if (src == const0_rtx)
2954 return 2;
2955
2956 return 4;
2957 }
2958
2959 base_length = 8;
2960 break;
2961
2962 case SImode:
2963 if (addr == NULL_RTX)
2964 {
2965 if (REG_P (src))
2966 {
2967 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2968 return 4;
2969 else
2970 return 2;
2971 }
2972
2973 if (GET_CODE (src) == CONST_INT)
2974 {
2975 int val = INTVAL (src);
2976
2977 if (val == 0)
2978 return 2;
2979
2980 if (val == (val & 0x00ff) || val == (val & 0xff00))
2981 return 4;
80e58519 2982
7948a9ea
KH		 2983 switch (val & 0xffffffff)
2984 {
2985 case 0xffffffff:
2986 case 0xfffffffe:
2987 case 0xfffffffc:
2988 case 0x0000ffff:
2989 case 0x0000fffe:
2990 case 0xffff0000:
2991 case 0xfffe0000:
2992 case 0x00010000:
2993 case 0x00020000:
2994 return 4;
2995 }
2996 }
2997 return 6;
2998 }
2999
3000 base_length = 10;
3001 break;
3002
3003 case SFmode:
3004 if (addr == NULL_RTX)
3005 {
3006 if (REG_P (src))
3007 return 2;
3008
ceaaaeab 3009 if (satisfies_constraint_G (src))
7948a9ea 3010 return 2;
2c4a71b3 3011
7948a9ea
KH		 3012 return 6;
3013 }
3014
3015 base_length = 10;
3016 break;
3017
3018 default:
8c440872 3019 gcc_unreachable ();
7948a9ea
KH		 3020 }
3021
3022 /* Adjust the length based on the addressing mode used.
3023 Specifically, we subtract the difference between the actual
3024 length and the longest one, which is @(d:24,ERs). */
3025
3026 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
3027 if (GET_CODE (addr) == PRE_DEC
3028 || GET_CODE (addr) == POST_INC)
3029 return base_length - 6;
3030
3031 /* @ERs and @ERd are 6 bytes shorter than the longest. */
3032 if (GET_CODE (addr) == REG)
3033 return base_length - 6;
3034
3035 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
3036 longest. */
3037 if (GET_CODE (addr) == PLUS
3038 && GET_CODE (XEXP (addr, 0)) == REG
3039 && GET_CODE (XEXP (addr, 1)) == CONST_INT
3040 && INTVAL (XEXP (addr, 1)) > -32768
3041 && INTVAL (XEXP (addr, 1)) < 32767)
3042 return base_length - 4;
3043
3044 /* @aa:16 is 4 bytes shorter than the longest. */
3045 if (h8300_tiny_constant_address_p (addr))
3046 return base_length - 4;
3047
3048 /* @aa:24 is 2 bytes shorter than the longest. */
3049 if (CONSTANT_P (addr))
3050 return base_length - 2;
3051
3052 return base_length;
3053 }
3054}
3055\f
e9eba255
KH		 3056/* Output an addition insn. */
3057
366a7b27 3058const char *
cb713a8d 3059output_plussi (rtx *operands)
7d6ac401 3060{
ef4bddc2 3061 machine_mode mode = GET_MODE (operands[0]);
7d6ac401 3062
8c440872 3063 gcc_assert (mode == SImode);
7d6ac401
KH		 3064
3065 if (TARGET_H8300)
3066 {
cfedf91b
KH		 3067 if (GET_CODE (operands[2]) == REG)
3068 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3069
3070 if (GET_CODE (operands[2]) == CONST_INT)
3071 {
3072 HOST_WIDE_INT n = INTVAL (operands[2]);
3073
3074 if ((n & 0xffffff) == 0)
3075 return "add\t%z2,%z0";
3076 if ((n & 0xffff) == 0)
3077 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
3078 if ((n & 0xff) == 0)
3079 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3080 }
3081
3082 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
7d6ac401
KH		 3083 }
3084 else
3085 {
beed8fc0
AO		 3086 if (GET_CODE (operands[2]) == CONST_INT
3087 && register_operand (operands[1], VOIDmode))
7d6ac401
KH		 3088 {
3089 HOST_WIDE_INT intval = INTVAL (operands[2]);
3090
beed8fc0
AO		 3091 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3092 return "add.l\t%S2,%S0";
3093 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3094 return "sub.l\t%G2,%S0";
3095
7d6ac401
KH		 3096 /* See if we can finish with 2 bytes. */
3097
9ac7ebba 3098 switch ((unsigned int) intval & 0xffffffff)
7d6ac401
KH		 3099 {
3100 case 0x00000001:
3101 case 0x00000002:
3102 case 0x00000004:
3103 return "adds\t%2,%S0";
3104
3105 case 0xffffffff:
3106 case 0xfffffffe:
3107 case 0xfffffffc:
3108 return "subs\t%G2,%S0";
3109
3110 case 0x00010000:
3111 case 0x00020000:
3112 operands[2] = GEN_INT (intval >> 16);
3113 return "inc.w\t%2,%e0";
3114
3115 case 0xffff0000:
3116 case 0xfffe0000:
3117 operands[2] = GEN_INT (intval >> 16);
3118 return "dec.w\t%G2,%e0";
3119 }
3120
3121 /* See if we can finish with 4 bytes. */
3122 if ((intval & 0xffff) == 0)
3123 {
3124 operands[2] = GEN_INT (intval >> 16);
3125 return "add.w\t%2,%e0";
3126 }
3127 }
3128
beed8fc0
AO		 3129 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3130 {
3131 operands[2] = GEN_INT (-INTVAL (operands[2]));
3132 return "sub.l\t%S2,%S0";
3133 }
7d6ac401
KH		 3134 return "add.l\t%S2,%S0";
3135 }
3136}
3137
beed8fc0
AO		 3138/* ??? It would be much easier to add the h8sx stuff if a single function
3139 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
e9eba255
KH		 3140/* Compute the length of an addition insn. */
3141
7d6ac401 3142unsigned int
cb713a8d 3143compute_plussi_length (rtx *operands)
7d6ac401 3144{
ef4bddc2 3145 machine_mode mode = GET_MODE (operands[0]);
7d6ac401 3146
8c440872 3147 gcc_assert (mode == SImode);
7d6ac401
KH		 3148
3149 if (TARGET_H8300)
3150 {
cfedf91b
KH		 3151 if (GET_CODE (operands[2]) == REG)
3152 return 6;
3153
3154 if (GET_CODE (operands[2]) == CONST_INT)
3155 {
3156 HOST_WIDE_INT n = INTVAL (operands[2]);
3157
3158 if ((n & 0xffffff) == 0)
3159 return 2;
3160 if ((n & 0xffff) == 0)
3161 return 4;
3162 if ((n & 0xff) == 0)
3163 return 6;
3164 }
3165
3166 return 8;
7d6ac401
KH		 3167 }
3168 else
3169 {
beed8fc0
AO		 3170 if (GET_CODE (operands[2]) == CONST_INT
3171 && register_operand (operands[1], VOIDmode))
7d6ac401
KH		 3172 {
3173 HOST_WIDE_INT intval = INTVAL (operands[2]);
3174
beed8fc0
AO		 3175 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3176 return 2;
3177 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3178 return 2;
3179
7d6ac401
KH		 3180 /* See if we can finish with 2 bytes. */
3181
9ac7ebba 3182 switch ((unsigned int) intval & 0xffffffff)
7d6ac401
KH		 3183 {
3184 case 0x00000001:
3185 case 0x00000002:
3186 case 0x00000004:
3187 return 2;
3188
3189 case 0xffffffff:
3190 case 0xfffffffe:
3191 case 0xfffffffc:
3192 return 2;
3193
3194 case 0x00010000:
3195 case 0x00020000:
3196 return 2;
3197
3198 case 0xffff0000:
3199 case 0xfffe0000:
3200 return 2;
3201 }
3202
3203 /* See if we can finish with 4 bytes. */
3204 if ((intval & 0xffff) == 0)
3205 return 4;
3206 }
3207
beed8fc0
AO		 3208 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3209 return h8300_length_from_table (operands[0],
3210 GEN_INT (-INTVAL (operands[2])),
3211 &addl_length_table);
3212 else
3213 return h8300_length_from_table (operands[0], operands[2],
3214 &addl_length_table);
7d6ac401
KH		 3215 return 6;
3216 }
3217}
3218
e9eba255
KH		 3219/* Compute which flag bits are valid after an addition insn. */
3220
9690aa8e 3221enum attr_cc
cb713a8d 3222compute_plussi_cc (rtx *operands)
7d6ac401 3223{
ef4bddc2 3224 machine_mode mode = GET_MODE (operands[0]);
7d6ac401 3225
8c440872 3226 gcc_assert (mode == SImode);
7d6ac401
KH		 3227
3228 if (TARGET_H8300)
3229 {
cfedf91b 3230 return CC_CLOBBER;
7d6ac401
KH		 3231 }
3232 else
3233 {
beed8fc0
AO		 3234 if (GET_CODE (operands[2]) == CONST_INT
3235 && register_operand (operands[1], VOIDmode))
7d6ac401
KH		 3236 {
3237 HOST_WIDE_INT intval = INTVAL (operands[2]);
3238
beed8fc0
AO		 3239 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3240 return CC_SET_ZN;
3241 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3242 return CC_SET_ZN;
3243
7d6ac401
KH		 3244 /* See if we can finish with 2 bytes. */
3245
9ac7ebba 3246 switch ((unsigned int) intval & 0xffffffff)
7d6ac401
KH		 3247 {
3248 case 0x00000001:
3249 case 0x00000002:
3250 case 0x00000004:
3251 return CC_NONE_0HIT;
3252
3253 case 0xffffffff:
3254 case 0xfffffffe:
3255 case 0xfffffffc:
3256 return CC_NONE_0HIT;
3257
3258 case 0x00010000:
3259 case 0x00020000:
3260 return CC_CLOBBER;
3261
3262 case 0xffff0000:
3263 case 0xfffe0000:
3264 return CC_CLOBBER;
3265 }
3266
3267 /* See if we can finish with 4 bytes. */
3268 if ((intval & 0xffff) == 0)
3269 return CC_CLOBBER;
3270 }
3271
3272 return CC_SET_ZN;
3273 }
3274}
3275\f
e9eba255
KH		 3276/* Output a logical insn. */
3277
7d6ac401 3278const char *
ef4bddc2 3279output_logical_op (machine_mode mode, rtx *operands)
366a7b27 3280{
b42cff6b
KH		 3281 /* Figure out the logical op that we need to perform. */
3282 enum rtx_code code = GET_CODE (operands[3]);
366a7b27 3283 /* Pretend that every byte is affected if both operands are registers. */
7798db98 3284 const unsigned HOST_WIDE_INT intval =
366a7b27 3285 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
beed8fc0
AO		 3286 /* Always use the full instruction if the
3287 first operand is in memory. It is better
3288 to use define_splits to generate the shorter
3289 sequence where valid. */
3290 && register_operand (operands[1], VOIDmode)
366a7b27
KH		 3291 ? INTVAL (operands[2]) : 0x55555555);
3292 /* The determinant of the algorithm. If we perform an AND, 0
3293 affects a bit. Otherwise, 1 affects a bit. */
7798db98 3294 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
f9ac2f95
KH		 3295 /* Break up DET into pieces. */
3296 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3297 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
c5e7ce43
KH		 3298 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3299 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
f9ac2f95
KH		 3300 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3301 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3302 int lower_half_easy_p = 0;
3303 int upper_half_easy_p = 0;
366a7b27
KH		 3304 /* The name of an insn. */
3305 const char *opname;
3306 char insn_buf[100];
3307
3308 switch (code)
3309 {
3310 case AND:
3311 opname = "and";
3312 break;
3313 case IOR:
3314 opname = "or";
3315 break;
3316 case XOR:
3317 opname = "xor";
3318 break;
3319 default:
8c440872 3320 gcc_unreachable ();
366a7b27
KH		 3321 }
3322
3323 switch (mode)
3324 {
3325 case HImode:
3326 /* First, see if we can finish with one insn. */
3327 if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 3328 && b0 != 0
3329 && b1 != 0)
366a7b27
KH		 3330 {
3331 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
3332 output_asm_insn (insn_buf, operands);
3333 }
3334 else
3335 {
3336 /* Take care of the lower byte. */
c5e7ce43 3337 if (b0 != 0)
366a7b27
KH		 3338 {
3339 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
3340 output_asm_insn (insn_buf, operands);
3341 }
3342 /* Take care of the upper byte. */
c5e7ce43 3343 if (b1 != 0)
366a7b27
KH		 3344 {
3345 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
3346 output_asm_insn (insn_buf, operands);
3347 }
3348 }
3349 break;
3350 case SImode:
f9ac2f95
KH		 3351 if (TARGET_H8300H || TARGET_H8300S)
3352 {
3353 /* Determine if the lower half can be taken care of in no more
3354 than two bytes. */
3355 lower_half_easy_p = (b0 == 0
3356 || b1 == 0
3357 || (code != IOR && w0 == 0xffff));
3358
3359 /* Determine if the upper half can be taken care of in no more
3360 than two bytes. */
3361 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3362 || (code == AND && w1 == 0xff00));
3363 }
366a7b27 3364
f9ac2f95
KH		 3365 /* Check if doing everything with one insn is no worse than
3366 using multiple insns. */
366a7b27 3367 if ((TARGET_H8300H || TARGET_H8300S)
f9ac2f95 3368 && w0 != 0 && w1 != 0
472f2723
KH		 3369 && !(lower_half_easy_p && upper_half_easy_p)
3370 && !(code == IOR && w1 == 0xffff
3371 && (w0 & 0x8000) != 0 && lower_half_easy_p))
366a7b27
KH		 3372 {
3373 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
3374 output_asm_insn (insn_buf, operands);
3375 }
3376 else
3377 {
3378 /* Take care of the lower and upper words individually. For
3379 each word, we try different methods in the order of
3380
3381 1) the special insn (in case of AND or XOR),
3382 2) the word-wise insn, and
3383 3) The byte-wise insn. */
c5e7ce43 3384 if (w0 == 0xffff
6dfa4005 3385 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
366a7b27 3386 output_asm_insn ((code == AND)
187462ac 3387 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
366a7b27
KH		 3388 operands);
3389 else if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 3390 && (b0 != 0)
3391 && (b1 != 0))
366a7b27
KH		 3392 {
3393 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
3394 output_asm_insn (insn_buf, operands);
3395 }
3396 else
3397 {
c5e7ce43 3398 if (b0 != 0)
366a7b27
KH		 3399 {
3400 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
3401 output_asm_insn (insn_buf, operands);
3402 }
c5e7ce43 3403 if (b1 != 0)
366a7b27
KH		 3404 {
3405 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
3406 output_asm_insn (insn_buf, operands);
3407 }
3408 }
3409
c5e7ce43 3410 if ((w1 == 0xffff)
6dfa4005 3411 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
366a7b27 3412 output_asm_insn ((code == AND)
187462ac 3413 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
366a7b27 3414 operands);
472f2723
KH		 3415 else if ((TARGET_H8300H || TARGET_H8300S)
3416 && code == IOR
3417 && w1 == 0xffff
3418 && (w0 & 0x8000) != 0)
3419 {
3420 output_asm_insn ("exts.l\t%S0", operands);
3421 }
a6e8d113
KH		 3422 else if ((TARGET_H8300H || TARGET_H8300S)
3423 && code == AND
c5e7ce43 3424 && w1 == 0xff00)
a6e8d113 3425 {
dc5f17ec 3426 output_asm_insn ("extu.w\t%e0", operands);
a6e8d113 3427 }
366a7b27
KH		 3428 else if (TARGET_H8300H || TARGET_H8300S)
3429 {
c5e7ce43 3430 if (w1 != 0)
366a7b27
KH		 3431 {
3432 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
3433 output_asm_insn (insn_buf, operands);
3434 }
3435 }
3436 else
3437 {
c5e7ce43 3438 if (b2 != 0)
366a7b27
KH		 3439 {
3440 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
3441 output_asm_insn (insn_buf, operands);
3442 }
c5e7ce43 3443 if (b3 != 0)
366a7b27
KH		 3444 {
3445 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
3446 output_asm_insn (insn_buf, operands);
3447 }
3448 }
3449 }
3450 break;
3451 default:
8c440872 3452 gcc_unreachable ();
366a7b27
KH		 3453 }
3454 return "";
3455}
40367e2d 3456
e9eba255
KH		 3457/* Compute the length of a logical insn. */
3458
40367e2d 3459unsigned int
ef4bddc2 3460compute_logical_op_length (machine_mode mode, rtx *operands)
40367e2d 3461{
b42cff6b
KH		 3462 /* Figure out the logical op that we need to perform. */
3463 enum rtx_code code = GET_CODE (operands[3]);
40367e2d 3464 /* Pretend that every byte is affected if both operands are registers. */
7798db98 3465 const unsigned HOST_WIDE_INT intval =
40367e2d 3466 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
beed8fc0
AO		 3467 /* Always use the full instruction if the
3468 first operand is in memory. It is better
3469 to use define_splits to generate the shorter
3470 sequence where valid. */
3471 && register_operand (operands[1], VOIDmode)
40367e2d
KH		 3472 ? INTVAL (operands[2]) : 0x55555555);
3473 /* The determinant of the algorithm. If we perform an AND, 0
3474 affects a bit. Otherwise, 1 affects a bit. */
7798db98 3475 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
f9ac2f95
KH		 3476 /* Break up DET into pieces. */
3477 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3478 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
c5e7ce43
KH		 3479 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3480 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
f9ac2f95
KH		 3481 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3482 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3483 int lower_half_easy_p = 0;
3484 int upper_half_easy_p = 0;
40367e2d
KH		 3485 /* Insn length. */
3486 unsigned int length = 0;
3487
3488 switch (mode)
3489 {
3490 case HImode:
3491 /* First, see if we can finish with one insn. */
3492 if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 3493 && b0 != 0
3494 && b1 != 0)
40367e2d 3495 {
beed8fc0
AO		 3496 length = h8300_length_from_table (operands[1], operands[2],
3497 &logicw_length_table);
40367e2d
KH		 3498 }
3499 else
3500 {
3501 /* Take care of the lower byte. */
c5e7ce43 3502 if (b0 != 0)
40367e2d
KH		 3503 length += 2;
3504
3505 /* Take care of the upper byte. */
c5e7ce43 3506 if (b1 != 0)
40367e2d
KH		 3507 length += 2;
3508 }
3509 break;
3510 case SImode:
f9ac2f95
KH		 3511 if (TARGET_H8300H || TARGET_H8300S)
3512 {
3513 /* Determine if the lower half can be taken care of in no more
3514 than two bytes. */
3515 lower_half_easy_p = (b0 == 0
3516 || b1 == 0
3517 || (code != IOR && w0 == 0xffff));
3518
3519 /* Determine if the upper half can be taken care of in no more
3520 than two bytes. */
3521 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3522 || (code == AND && w1 == 0xff00));
3523 }
40367e2d 3524
f9ac2f95
KH		 3525 /* Check if doing everything with one insn is no worse than
3526 using multiple insns. */
40367e2d 3527 if ((TARGET_H8300H || TARGET_H8300S)
f9ac2f95 3528 && w0 != 0 && w1 != 0
472f2723
KH		 3529 && !(lower_half_easy_p && upper_half_easy_p)
3530 && !(code == IOR && w1 == 0xffff
3531 && (w0 & 0x8000) != 0 && lower_half_easy_p))
40367e2d 3532 {
beed8fc0
AO		 3533 length = h8300_length_from_table (operands[1], operands[2],
3534 &logicl_length_table);
40367e2d
KH		 3535 }
3536 else
3537 {
3538 /* Take care of the lower and upper words individually. For
3539 each word, we try different methods in the order of
3540
3541 1) the special insn (in case of AND or XOR),
3542 2) the word-wise insn, and
3543 3) The byte-wise insn. */
c5e7ce43 3544 if (w0 == 0xffff
40367e2d
KH		 3545 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3546 {
3547 length += 2;
3548 }
3549 else if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 3550 && (b0 != 0)
3551 && (b1 != 0))
40367e2d
KH		 3552 {
3553 length += 4;
3554 }
3555 else
3556 {
c5e7ce43 3557 if (b0 != 0)
40367e2d
KH		 3558 length += 2;
3559
c5e7ce43 3560 if (b1 != 0)
40367e2d
KH		 3561 length += 2;
3562 }
3563
c5e7ce43 3564 if (w1 == 0xffff
40367e2d
KH		 3565 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3566 {
3567 length += 2;
3568 }
472f2723
KH		 3569 else if ((TARGET_H8300H || TARGET_H8300S)
3570 && code == IOR
3571 && w1 == 0xffff
3572 && (w0 & 0x8000) != 0)
3573 {
3574 length += 2;
3575 }
a6e8d113
KH		 3576 else if ((TARGET_H8300H || TARGET_H8300S)
3577 && code == AND
c5e7ce43 3578 && w1 == 0xff00)
a6e8d113
KH		 3579 {
3580 length += 2;
3581 }
40367e2d
KH		 3582 else if (TARGET_H8300H || TARGET_H8300S)
3583 {
c5e7ce43 3584 if (w1 != 0)
40367e2d
KH		 3585 length += 4;
3586 }
3587 else
3588 {
c5e7ce43 3589 if (b2 != 0)
40367e2d
KH		 3590 length += 2;
3591
c5e7ce43 3592 if (b3 != 0)
40367e2d
KH		 3593 length += 2;
3594 }
3595 }
3596 break;
3597 default:
8c440872 3598 gcc_unreachable ();
40367e2d
KH		 3599 }
3600 return length;
3601}
b42cff6b 3602
e9eba255
KH		 3603/* Compute which flag bits are valid after a logical insn. */
3604
9690aa8e 3605enum attr_cc
ef4bddc2 3606compute_logical_op_cc (machine_mode mode, rtx *operands)
b42cff6b
KH		 3607{
3608 /* Figure out the logical op that we need to perform. */
3609 enum rtx_code code = GET_CODE (operands[3]);
3610 /* Pretend that every byte is affected if both operands are registers. */
7798db98 3611 const unsigned HOST_WIDE_INT intval =
b42cff6b 3612 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
beed8fc0
AO		 3613 /* Always use the full instruction if the
3614 first operand is in memory. It is better
3615 to use define_splits to generate the shorter
3616 sequence where valid. */
3617 && register_operand (operands[1], VOIDmode)
b42cff6b
KH		 3618 ? INTVAL (operands[2]) : 0x55555555);
3619 /* The determinant of the algorithm. If we perform an AND, 0
3620 affects a bit. Otherwise, 1 affects a bit. */
7798db98 3621 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
f9ac2f95
KH		 3622 /* Break up DET into pieces. */
3623 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3624 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3625 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3626 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3627 int lower_half_easy_p = 0;
3628 int upper_half_easy_p = 0;
b42cff6b
KH		 3629 /* Condition code. */
3630 enum attr_cc cc = CC_CLOBBER;
3631
3632 switch (mode)
3633 {
3634 case HImode:
3635 /* First, see if we can finish with one insn. */
3636 if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 3637 && b0 != 0
3638 && b1 != 0)
b42cff6b
KH		 3639 {
3640 cc = CC_SET_ZNV;
3641 }
3642 break;
3643 case SImode:
f9ac2f95
KH		 3644 if (TARGET_H8300H || TARGET_H8300S)
3645 {
3646 /* Determine if the lower half can be taken care of in no more
3647 than two bytes. */
3648 lower_half_easy_p = (b0 == 0
3649 || b1 == 0
3650 || (code != IOR && w0 == 0xffff));
3651
3652 /* Determine if the upper half can be taken care of in no more
3653 than two bytes. */
3654 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3655 || (code == AND && w1 == 0xff00));
3656 }
b42cff6b 3657
f9ac2f95
KH		 3658 /* Check if doing everything with one insn is no worse than
3659 using multiple insns. */
b42cff6b 3660 if ((TARGET_H8300H || TARGET_H8300S)
f9ac2f95 3661 && w0 != 0 && w1 != 0
472f2723
KH		 3662 && !(lower_half_easy_p && upper_half_easy_p)
3663 && !(code == IOR && w1 == 0xffff
3664 && (w0 & 0x8000) != 0 && lower_half_easy_p))
b42cff6b
KH		 3665 {
3666 cc = CC_SET_ZNV;
3667 }
472f2723
KH		 3668 else
3669 {
3670 if ((TARGET_H8300H || TARGET_H8300S)
3671 && code == IOR
3672 && w1 == 0xffff
3673 && (w0 & 0x8000) != 0)
3674 {
3675 cc = CC_SET_ZNV;
3676 }
3677 }
b42cff6b
KH		 3678 break;
3679 default:
8c440872 3680 gcc_unreachable ();
b42cff6b
KH		 3681 }
3682 return cc;
3683}
366a7b27 3684\f
8981ecd3
KH		 3685/* Expand a conditional branch. */
3686
3687void
f90b7a5a 3688h8300_expand_branch (rtx operands[])
8981ecd3 3689{
f90b7a5a
PB		 3690 enum rtx_code code = GET_CODE (operands[0]);
3691 rtx op0 = operands[1];
3692 rtx op1 = operands[2];
3693 rtx label = operands[3];
8981ecd3
KH		 3694 rtx tmp;
3695
f90b7a5a 3696 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
f7df4a84 3697 emit_insn (gen_rtx_SET (cc0_rtx, tmp));
f90b7a5a 3698
8981ecd3
KH		 3699 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
3700 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
3701 gen_rtx_LABEL_REF (VOIDmode, label),
3702 pc_rtx);
f7df4a84 3703 emit_jump_insn (gen_rtx_SET (pc_rtx, tmp));
8981ecd3 3704}
f90b7a5a
PB		 3705
3706
3707/* Expand a conditional store. */
3708
3709void
3710h8300_expand_store (rtx operands[])
3711{
3712 rtx dest = operands[0];
3713 enum rtx_code code = GET_CODE (operands[1]);
3714 rtx op0 = operands[2];
3715 rtx op1 = operands[3];
3716 rtx tmp;
3717
3718 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
f7df4a84 3719 emit_insn (gen_rtx_SET (cc0_rtx, tmp));
f90b7a5a
PB		 3720
3721 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx);
f7df4a84 3722 emit_insn (gen_rtx_SET (dest, tmp));
f90b7a5a 3723}
8981ecd3 3724\f
48837e29
DE		 3725/* Shifts.
3726
005e3e05
KH		 3727 We devote a fair bit of code to getting efficient shifts since we
3728 can only shift one bit at a time on the H8/300 and H8/300H and only
3db11b5c 3729 one or two bits at a time on the H8S.
005e3e05
KH		 3730
3731 All shift code falls into one of the following ways of
3732 implementation:
3733
3734 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3735 when a straight line shift is about the same size or smaller than
3736 a loop.
3737
3738 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3739 off the bits we don't need. This is used when only a few of the
3740 bits in the original value will survive in the shifted value.
3741
3742 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3743 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3744 shifts can be added if the shift count is slightly more than 8 or
3745 16. This case also includes other oddballs that are not worth
f411c849 3746 explaining here.
005e3e05 3747
3db11b5c 3748 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
005e3e05 3749
5ec0b66e
KH		 3750 For each shift count, we try to use code that has no trade-off
3751 between code size and speed whenever possible.
3752
3753 If the trade-off is unavoidable, we try to be reasonable.
3754 Specifically, the fastest version is one instruction longer than
3755 the shortest version, we take the fastest version. We also provide
3756 the use a way to switch back to the shortest version with -Os.
3757
3758 For the details of the shift algorithms for various shift counts,
3759 refer to shift_alg_[qhs]i. */
07aae5c2 3760
beed8fc0
AO		 3761/* Classify a shift with the given mode and code. OP is the shift amount. */
3762
3763enum h8sx_shift_type
ef4bddc2 3764h8sx_classify_shift (machine_mode mode, enum rtx_code code, rtx op)
beed8fc0
AO		 3765{
3766 if (!TARGET_H8300SX)
3767 return H8SX_SHIFT_NONE;
3768
3769 switch (code)
3770 {
3771 case ASHIFT:
3772 case LSHIFTRT:
3773 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3774 if (GET_CODE (op) != CONST_INT)
3775 return H8SX_SHIFT_BINARY;
3776
3777 /* Reject out-of-range shift amounts. */
3778 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
3779 return H8SX_SHIFT_NONE;
3780
3781 /* Power-of-2 shifts are effectively unary operations. */
3782 if (exact_log2 (INTVAL (op)) >= 0)
3783 return H8SX_SHIFT_UNARY;
3784
3785 return H8SX_SHIFT_BINARY;
3786
3787 case ASHIFTRT:
3788 if (op == const1_rtx || op == const2_rtx)
3789 return H8SX_SHIFT_UNARY;
3790 return H8SX_SHIFT_NONE;
3791
3792 case ROTATE:
3793 if (GET_CODE (op) == CONST_INT
3794 && (INTVAL (op) == 1
3795 || INTVAL (op) == 2
3796 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
3797 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
3798 return H8SX_SHIFT_UNARY;
3799 return H8SX_SHIFT_NONE;
3800
3801 default:
3802 return H8SX_SHIFT_NONE;
3803 }
3804}
3805
beed8fc0
AO		 3806/* Return the asm template for a single h8sx shift instruction.
3807 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3808 is the source and OPERANDS[3] is the shift. SUFFIX is the
88cb339e 3809 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
beed8fc0
AO		 3810 prefix for the destination operand. */
3811
3812const char *
3813output_h8sx_shift (rtx *operands, int suffix, int optype)
3814{
3815 static char buffer[16];
3816 const char *stem;
3817
3818 switch (GET_CODE (operands[3]))
3819 {
3820 case ASHIFT:
3821 stem = "shll";
3822 break;
3823
3824 case ASHIFTRT:
3825 stem = "shar";
3826 break;
3827
3828 case LSHIFTRT:
3829 stem = "shlr";
3830 break;
3831
3832 case ROTATE:
3833 stem = "rotl";
3834 if (INTVAL (operands[2]) > 2)
3835 {
3836 /* This is really a right rotate. */
3837 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
3838 - INTVAL (operands[2]));
3839 stem = "rotr";
3840 }
3841 break;
3842
3843 default:
8c440872 3844 gcc_unreachable ();
beed8fc0
AO		 3845 }
3846 if (operands[2] == const1_rtx)
3847 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
3848 else
3849 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
3850 return buffer;
3851}
48837e29 3852
317d21e9 3853/* Emit code to do shifts. */
48837e29 3854
beed8fc0 3855bool
ef4bddc2 3856expand_a_shift (machine_mode mode, enum rtx_code code, rtx operands[])
07aae5c2 3857{
beed8fc0
AO		 3858 switch (h8sx_classify_shift (mode, code, operands[2]))
3859 {
3860 case H8SX_SHIFT_BINARY:
3861 operands[1] = force_reg (mode, operands[1]);
3862 return false;
3863
3864 case H8SX_SHIFT_UNARY:
3865 return false;
3866
3867 case H8SX_SHIFT_NONE:
3868 break;
3869 }
3870
bc9b880c 3871 emit_move_insn (copy_rtx (operands[0]), operands[1]);
07aae5c2 3872
07e4d94e
KH		 3873 /* Need a loop to get all the bits we want - we generate the
3874 code at emit time, but need to allocate a scratch reg now. */
48837e29 3875
c5c76735
JL		 3876 emit_insn (gen_rtx_PARALLEL
3877 (VOIDmode,
48837e29 3878 gen_rtvec (2,
f7df4a84 3879 gen_rtx_SET (copy_rtx (operands[0]),
0f4c242b 3880 gen_rtx_fmt_ee (code, mode,
bc9b880c 3881 copy_rtx (operands[0]), operands[2])),
c5c76735
JL		 3882 gen_rtx_CLOBBER (VOIDmode,
3883 gen_rtx_SCRATCH (QImode)))));
beed8fc0 3884 return true;
48837e29
DE		 3885}
3886
48837e29
DE		 3887/* Symbols of the various modes which can be used as indices. */
3888
3889enum shift_mode
1a63219b
KH		 3890{
3891 QIshift, HIshift, SIshift
3892};
48837e29 3893
269c14e1
DE		 3894/* For single bit shift insns, record assembler and what bits of the
3895 condition code are valid afterwards (represented as various CC_FOO
3896 bits, 0 means CC isn't left in a usable state). */
48837e29
DE		 3897
3898struct shift_insn
3899{
8b60264b 3900 const char *const assembler;
9690aa8e 3901 const enum attr_cc cc_valid;
48837e29
DE		 3902};
3903
3904/* Assembler instruction shift table.
3905
3906 These tables are used to look up the basic shifts.
07e4d94e 3907 They are indexed by cpu, shift_type, and mode. */
07aae5c2 3908
48837e29
DE		 3909static const struct shift_insn shift_one[2][3][3] =
3910{
3911/* H8/300 */
3912 {
3913/* SHIFT_ASHIFT */
3914 {
45ca2106
KH		 3915 { "shll\t%X0", CC_SET_ZNV },
3916 { "add.w\t%T0,%T0", CC_SET_ZN },
3917 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
48837e29
DE		 3918 },
3919/* SHIFT_LSHIFTRT */
3920 {
45ca2106
KH		 3921 { "shlr\t%X0", CC_SET_ZNV },
3922 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3923 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
48837e29
DE		 3924 },
3925/* SHIFT_ASHIFTRT */
3926 {
45ca2106
KH		 3927 { "shar\t%X0", CC_SET_ZNV },
3928 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3929 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
48837e29
DE		 3930 }
3931 },
3932/* H8/300H */
3933 {
3934/* SHIFT_ASHIFT */
3935 {
45ca2106
KH		 3936 { "shll.b\t%X0", CC_SET_ZNV },
3937 { "shll.w\t%T0", CC_SET_ZNV },
3938 { "shll.l\t%S0", CC_SET_ZNV }
48837e29
DE		 3939 },
3940/* SHIFT_LSHIFTRT */
3941 {
45ca2106
KH		 3942 { "shlr.b\t%X0", CC_SET_ZNV },
3943 { "shlr.w\t%T0", CC_SET_ZNV },
3944 { "shlr.l\t%S0", CC_SET_ZNV }
48837e29
DE		 3945 },
3946/* SHIFT_ASHIFTRT */
3947 {
45ca2106
KH		 3948 { "shar.b\t%X0", CC_SET_ZNV },
3949 { "shar.w\t%T0", CC_SET_ZNV },
3950 { "shar.l\t%S0", CC_SET_ZNV }
48837e29
DE		 3951 }
3952 }
3953};
07aae5c2 3954
51c0c1d7
JL		 3955static const struct shift_insn shift_two[3][3] =
3956{
3957/* SHIFT_ASHIFT */
3958 {
45ca2106
KH		 3959 { "shll.b\t#2,%X0", CC_SET_ZNV },
3960 { "shll.w\t#2,%T0", CC_SET_ZNV },
3961 { "shll.l\t#2,%S0", CC_SET_ZNV }
51c0c1d7
JL		 3962 },
3963/* SHIFT_LSHIFTRT */
3964 {
45ca2106
KH		 3965 { "shlr.b\t#2,%X0", CC_SET_ZNV },
3966 { "shlr.w\t#2,%T0", CC_SET_ZNV },
3967 { "shlr.l\t#2,%S0", CC_SET_ZNV }
51c0c1d7
JL		 3968 },
3969/* SHIFT_ASHIFTRT */
3970 {
45ca2106
KH		 3971 { "shar.b\t#2,%X0", CC_SET_ZNV },
3972 { "shar.w\t#2,%T0", CC_SET_ZNV },
3973 { "shar.l\t#2,%S0", CC_SET_ZNV }
51c0c1d7
JL		 3974 }
3975};
3976
48837e29
DE		 3977/* Rotates are organized by which shift they'll be used in implementing.
3978 There's no need to record whether the cc is valid afterwards because
3979 it is the AND insn that will decide this. */
07aae5c2 3980
48837e29
DE		 3981static const char *const rotate_one[2][3][3] =
3982{
3983/* H8/300 */
3984 {
3985/* SHIFT_ASHIFT */
3986 {
51c0c1d7
JL		 3987 "rotr\t%X0",
3988 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
48837e29
DE		 3989 0
3990 },
3991/* SHIFT_LSHIFTRT */
3992 {
51c0c1d7
JL		 3993 "rotl\t%X0",
3994 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
48837e29
DE		 3995 0
3996 },
3997/* SHIFT_ASHIFTRT */
3998 {
51c0c1d7
JL		 3999 "rotl\t%X0",
4000 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
48837e29 4001 0
07aae5c2 4002 }
48837e29
DE		 4003 },
4004/* H8/300H */
4005 {
4006/* SHIFT_ASHIFT */
4007 {
51c0c1d7
JL		 4008 "rotr.b\t%X0",
4009 "rotr.w\t%T0",
4010 "rotr.l\t%S0"
48837e29
DE		 4011 },
4012/* SHIFT_LSHIFTRT */
07aae5c2 4013 {
51c0c1d7
JL		 4014 "rotl.b\t%X0",
4015 "rotl.w\t%T0",
4016 "rotl.l\t%S0"
48837e29
DE		 4017 },
4018/* SHIFT_ASHIFTRT */
4019 {
51c0c1d7
JL		 4020 "rotl.b\t%X0",
4021 "rotl.w\t%T0",
4022 "rotl.l\t%S0"
48837e29
DE		 4023 }
4024 }
4025};
4026
51c0c1d7
JL		 4027static const char *const rotate_two[3][3] =
4028{
4029/* SHIFT_ASHIFT */
4030 {
4031 "rotr.b\t#2,%X0",
4032 "rotr.w\t#2,%T0",
4033 "rotr.l\t#2,%S0"
4034 },
4035/* SHIFT_LSHIFTRT */
4036 {
4037 "rotl.b\t#2,%X0",
4038 "rotl.w\t#2,%T0",
4039 "rotl.l\t#2,%S0"
4040 },
4041/* SHIFT_ASHIFTRT */
4042 {
4043 "rotl.b\t#2,%X0",
4044 "rotl.w\t#2,%T0",
4045 "rotl.l\t#2,%S0"
4046 }
4047};
4048
35fb3d1f
KH		 4049struct shift_info {
4050 /* Shift algorithm. */
4051 enum shift_alg alg;
4052
4053 /* The number of bits to be shifted by shift1 and shift2. Valid
4054 when ALG is SHIFT_SPECIAL. */
4055 unsigned int remainder;
4056
4057 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
4058 const char *special;
4059
4060 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
9cd10576 4061 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
35fb3d1f
KH		 4062 const char *shift1;
4063
4064 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
9cd10576 4065 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
35fb3d1f
KH		 4066 const char *shift2;
4067
45ca2106 4068 /* CC status for SHIFT_INLINE. */
9690aa8e 4069 enum attr_cc cc_inline;
45ca2106
KH		 4070
4071 /* CC status for SHIFT_SPECIAL. */
9690aa8e 4072 enum attr_cc cc_special;
35fb3d1f
KH		 4073};
4074
cb713a8d
KH		 4075static void get_shift_alg (enum shift_type,
4076 enum shift_mode, unsigned int,
4077 struct shift_info *);
441d04c6 4078
c009a745
KH		 4079/* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
4080 best algorithm for doing the shift. The assembler code is stored
5ec0b66e
KH		 4081 in the pointers in INFO. We achieve the maximum efficiency in most
4082 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
4083 SImode in particular have a lot of room to optimize.
4084
4085 We first determine the strategy of the shift algorithm by a table
4086 lookup. If that tells us to use a hand crafted assembly code, we
4087 go into the big switch statement to find what that is. Otherwise,
4088 we resort to a generic way, such as inlining. In either case, the
4089 result is returned through INFO. */
48837e29 4090
cb33eb17 4091static void
cb713a8d
KH		 4092get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
4093 unsigned int count, struct shift_info *info)
48837e29 4094{
b9b575e6 4095 enum h8_cpu cpu;
769828ab
KH		 4096
4097 /* Find the target CPU. */
4098 if (TARGET_H8300)
b9b575e6 4099 cpu = H8_300;
2f6bd6eb 4100 else if (TARGET_H8300S)
b9b575e6 4101 cpu = H8_S;
2f6bd6eb
YS		 4102 else
4103 cpu = H8_300H;
769828ab 4104
96eaf358 4105 /* Find the shift algorithm. */
b9b575e6 4106 info->alg = SHIFT_LOOP;
48837e29
DE		 4107 switch (shift_mode)
4108 {
4109 case QIshift:
b9b575e6 4110 if (count < GET_MODE_BITSIZE (QImode))
96eaf358
KH		 4111 info->alg = shift_alg_qi[cpu][shift_type][count];
4112 break;
769828ab 4113
96eaf358 4114 case HIshift:
b9b575e6 4115 if (count < GET_MODE_BITSIZE (HImode))
96eaf358
KH		 4116 info->alg = shift_alg_hi[cpu][shift_type][count];
4117 break;
4118
4119 case SIshift:
b9b575e6 4120 if (count < GET_MODE_BITSIZE (SImode))
96eaf358
KH		 4121 info->alg = shift_alg_si[cpu][shift_type][count];
4122 break;
4123
4124 default:
8c440872 4125 gcc_unreachable ();
96eaf358
KH		 4126 }
4127
4128 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4129 switch (info->alg)
4130 {
4131 case SHIFT_INLINE:
4132 info->remainder = count;
4133 /* Fall through. */
4134
4135 case SHIFT_LOOP:
4136 /* It is up to the caller to know that looping clobbers cc. */
4137 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4138 info->shift2 = shift_two[shift_type][shift_mode].assembler;
45ca2106 4139 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
96eaf358
KH		 4140 goto end;
4141
4142 case SHIFT_ROT_AND:
4143 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
4144 info->shift2 = rotate_two[shift_type][shift_mode];
45ca2106 4145 info->cc_inline = CC_CLOBBER;
96eaf358
KH		 4146 goto end;
4147
4148 case SHIFT_SPECIAL:
4149 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4150 info->remainder = 0;
4151 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4152 info->shift2 = shift_two[shift_type][shift_mode].assembler;
45ca2106
KH		 4153 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4154 info->cc_special = CC_CLOBBER;
96eaf358
KH		 4155 break;
4156 }
51c0c1d7 4157
96eaf358
KH		 4158 /* Here we only deal with SHIFT_SPECIAL. */
4159 switch (shift_mode)
4160 {
4161 case QIshift:
769828ab
KH		 4162 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4163 through the entire value. */
8c440872
NS		 4164 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
4165 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
4166 goto end;
769828ab
KH		 4167
4168 case HIshift:
769828ab 4169 if (count == 7)
51c0c1d7 4170 {
a77b1dbc 4171 switch (shift_type)
51c0c1d7 4172 {
a77b1dbc
KH		 4173 case SHIFT_ASHIFT:
4174 if (TARGET_H8300)
4175 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4176 else
4177 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
692b7eb3 4178 goto end;
a77b1dbc
KH		 4179 case SHIFT_LSHIFTRT:
4180 if (TARGET_H8300)
4181 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4182 else
4183 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
692b7eb3 4184 goto end;
a77b1dbc 4185 case SHIFT_ASHIFTRT:
35fb3d1f 4186 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
692b7eb3 4187 goto end;
48837e29 4188 }
07aae5c2 4189 }
b30686ec 4190 else if ((8 <= count && count <= 13)
a38b3eea 4191 || (TARGET_H8300S && count == 14))
07aae5c2 4192 {
a7812c0b
KH		 4193 info->remainder = count - 8;
4194
51c0c1d7 4195 switch (shift_type)
48837e29 4196 {
51c0c1d7 4197 case SHIFT_ASHIFT:
35fb3d1f 4198 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
692b7eb3 4199 goto end;
51c0c1d7 4200 case SHIFT_LSHIFTRT:
a7612343
KH		 4201 if (TARGET_H8300)
4202 {
4203 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4204 info->shift1 = "shlr.b\t%s0";
45ca2106 4205 info->cc_inline = CC_SET_ZNV;
a7612343
KH		 4206 }
4207 else
4208 {
4209 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
45ca2106 4210 info->cc_special = CC_SET_ZNV;
a7612343 4211 }
692b7eb3 4212 goto end;
51c0c1d7
JL		 4213 case SHIFT_ASHIFTRT:
4214 if (TARGET_H8300)
a7612343
KH		 4215 {
4216 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4217 info->shift1 = "shar.b\t%s0";
a7612343 4218 }
51c0c1d7 4219 else
a7612343
KH		 4220 {
4221 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
45ca2106 4222 info->cc_special = CC_SET_ZNV;
a7612343 4223 }
692b7eb3 4224 goto end;
51c0c1d7
JL		 4225 }
4226 }
5e98fba2
DD		 4227 else if (count == 14)
4228 {
4229 switch (shift_type)
4230 {
4231 case SHIFT_ASHIFT:
4232 if (TARGET_H8300)
4233 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4234 goto end;
4235 case SHIFT_LSHIFTRT:
4236 if (TARGET_H8300)
4237 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4238 goto end;
4239 case SHIFT_ASHIFTRT:
4240 if (TARGET_H8300)
4241 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4242 else if (TARGET_H8300H)
45ca2106
KH		 4243 {
4244 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4245 info->cc_special = CC_SET_ZNV;
4246 }
5e98fba2 4247 else /* TARGET_H8300S */
8c440872 4248 gcc_unreachable ();
5e98fba2
DD		 4249 goto end;
4250 }
4251 }
1e41e866 4252 else if (count == 15)
51c0c1d7 4253 {
1e41e866
KH		 4254 switch (shift_type)
4255 {
4256 case SHIFT_ASHIFT:
4257 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4258 goto end;
4259 case SHIFT_LSHIFTRT:
4260 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4261 goto end;
4262 case SHIFT_ASHIFTRT:
4263 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4264 goto end;
4265 }
07aae5c2 4266 }
8c440872 4267 gcc_unreachable ();
51c0c1d7 4268
48837e29 4269 case SIshift:
1e41e866 4270 if (TARGET_H8300 && 8 <= count && count <= 9)
48837e29 4271 {
1e41e866
KH		 4272 info->remainder = count - 8;
4273
51c0c1d7 4274 switch (shift_type)
48837e29 4275 {
51c0c1d7 4276 case SHIFT_ASHIFT:
35fb3d1f 4277 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
692b7eb3 4278 goto end;
51c0c1d7 4279 case SHIFT_LSHIFTRT:
35fb3d1f 4280 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
1e41e866 4281 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
692b7eb3 4282 goto end;
51c0c1d7 4283 case SHIFT_ASHIFTRT:
35fb3d1f 4284 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
692b7eb3 4285 goto end;
48837e29 4286 }
48837e29 4287 }
e6bcfef9
JS		 4288 else if (count == 8 && !TARGET_H8300)
4289 {
4290 switch (shift_type)
4291 {
4292 case SHIFT_ASHIFT:
35fb3d1f 4293 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
692b7eb3 4294 goto end;
e6bcfef9 4295 case SHIFT_LSHIFTRT:
35fb3d1f 4296 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
692b7eb3 4297 goto end;
e6bcfef9 4298 case SHIFT_ASHIFTRT:
35fb3d1f 4299 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
692b7eb3 4300 goto end;
e6bcfef9
JS		 4301 }
4302 }
1e41e866
KH		 4303 else if (count == 15 && TARGET_H8300)
4304 {
4305 switch (shift_type)
4306 {
4307 case SHIFT_ASHIFT:
8c440872 4308 gcc_unreachable ();
1e41e866 4309 case SHIFT_LSHIFTRT:
a35abc3c 4310 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
1e41e866
KH		 4311 goto end;
4312 case SHIFT_ASHIFTRT:
a35abc3c 4313 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
1e41e866
KH		 4314 goto end;
4315 }
4316 }
dd69e230
KH		 4317 else if (count == 15 && !TARGET_H8300)
4318 {
4319 switch (shift_type)
4320 {
4321 case SHIFT_ASHIFT:
4322 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
45ca2106 4323 info->cc_special = CC_SET_ZNV;
dd69e230
KH		 4324 goto end;
4325 case SHIFT_LSHIFTRT:
18cf8dda 4326 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
45ca2106 4327 info->cc_special = CC_SET_ZNV;
dd69e230 4328 goto end;
aefc5826 4329 case SHIFT_ASHIFTRT:
8c440872 4330 gcc_unreachable ();
dd69e230
KH		 4331 }
4332 }
1e41e866 4333 else if ((TARGET_H8300 && 16 <= count && count <= 20)
a7812c0b 4334 || (TARGET_H8300H && 16 <= count && count <= 19)
e0f19bd0 4335 || (TARGET_H8300S && 16 <= count && count <= 21))
48837e29 4336 {
a7812c0b
KH		 4337 info->remainder = count - 16;
4338
48837e29
DE		 4339 switch (shift_type)
4340 {
4341 case SHIFT_ASHIFT:
35fb3d1f 4342 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
1e41e866 4343 if (TARGET_H8300)
b30686ec 4344 info->shift1 = "add.w\t%e0,%e0";
692b7eb3 4345 goto end;
51c0c1d7 4346 case SHIFT_LSHIFTRT:
1e41e866
KH		 4347 if (TARGET_H8300)
4348 {
a7612343
KH		 4349 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4350 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
1e41e866
KH		 4351 }
4352 else
4353 {
a7612343 4354 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
45ca2106 4355 info->cc_special = CC_SET_ZNV;
1e41e866 4356 }
692b7eb3 4357 goto end;
51c0c1d7
JL		 4358 case SHIFT_ASHIFTRT:
4359 if (TARGET_H8300)
1e41e866
KH		 4360 {
4361 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4362 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
4363 }
51c0c1d7 4364 else
1e41e866
KH		 4365 {
4366 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
45ca2106 4367 info->cc_special = CC_SET_ZNV;
1e41e866 4368 }
692b7eb3 4369 goto end;
51c0c1d7
JL		 4370 }
4371 }
1e41e866 4372 else if (TARGET_H8300 && 24 <= count && count <= 28)
f9477efd
KH		 4373 {
4374 info->remainder = count - 24;
f0b6f9a6 4375
f9477efd
KH		 4376 switch (shift_type)
4377 {
4378 case SHIFT_ASHIFT:
4379 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4380 info->shift1 = "shll.b\t%z0";
45ca2106 4381 info->cc_inline = CC_SET_ZNV;
f9477efd
KH		 4382 goto end;
4383 case SHIFT_LSHIFTRT:
4384 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4385 info->shift1 = "shlr.b\t%w0";
45ca2106 4386 info->cc_inline = CC_SET_ZNV;
f9477efd
KH		 4387 goto end;
4388 case SHIFT_ASHIFTRT:
d00f6ca6 4389 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
f9477efd 4390 info->shift1 = "shar.b\t%w0";
45ca2106 4391 info->cc_inline = CC_SET_ZNV;
7f473594
KH		 4392 goto end;
4393 }
4394 }
4a4ae922
KH		 4395 else if ((TARGET_H8300H && count == 24)
4396 || (TARGET_H8300S && 24 <= count && count <= 25))
e6bcfef9 4397 {
4a4ae922
KH		 4398 info->remainder = count - 24;
4399
e6bcfef9
JS		 4400 switch (shift_type)
4401 {
4402 case SHIFT_ASHIFT:
35fb3d1f 4403 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
692b7eb3 4404 goto end;
e6bcfef9 4405 case SHIFT_LSHIFTRT:
35fb3d1f 4406 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
45ca2106 4407 info->cc_special = CC_SET_ZNV;
692b7eb3 4408 goto end;
e6bcfef9 4409 case SHIFT_ASHIFTRT:
35fb3d1f 4410 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
45ca2106 4411 info->cc_special = CC_SET_ZNV;
692b7eb3 4412 goto end;
e6bcfef9
JS		 4413 }
4414 }
1e5bdc40
KH		 4415 else if (!TARGET_H8300 && count == 28)
4416 {
4417 switch (shift_type)
4418 {
4419 case SHIFT_ASHIFT:
4420 if (TARGET_H8300H)
4421 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4422 else
4423 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
1e5bdc40
KH		 4424 goto end;
4425 case SHIFT_LSHIFTRT:
4426 if (TARGET_H8300H)
45ca2106
KH		 4427 {
4428 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4429 info->cc_special = CC_SET_ZNV;
4430 }
1e5bdc40 4431 else
a7612343 4432 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
1e5bdc40
KH		 4433 goto end;
4434 case SHIFT_ASHIFTRT:
8c440872 4435 gcc_unreachable ();
1e5bdc40
KH		 4436 }
4437 }
4438 else if (!TARGET_H8300 && count == 29)
4439 {
4440 switch (shift_type)
4441 {
4442 case SHIFT_ASHIFT:
4443 if (TARGET_H8300H)
4444 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4445 else
4446 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
1e5bdc40
KH		 4447 goto end;
4448 case SHIFT_LSHIFTRT:
4449 if (TARGET_H8300H)
45ca2106
KH		 4450 {
4451 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4452 info->cc_special = CC_SET_ZNV;
4453 }
1e5bdc40 4454 else
45ca2106
KH		 4455 {
4456 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4457 info->cc_special = CC_SET_ZNV;
4458 }
1e5bdc40
KH		 4459 goto end;
4460 case SHIFT_ASHIFTRT:
8c440872 4461 gcc_unreachable ();
1e5bdc40
KH		 4462 }
4463 }
4464 else if (!TARGET_H8300 && count == 30)
4465 {
4466 switch (shift_type)
4467 {
4468 case SHIFT_ASHIFT:
4469 if (TARGET_H8300H)
4470 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4471 else
4472 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
1e5bdc40
KH		 4473 goto end;
4474 case SHIFT_LSHIFTRT:
4475 if (TARGET_H8300H)
a7612343 4476 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
1e5bdc40 4477 else
a7612343 4478 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
1e5bdc40
KH		 4479 goto end;
4480 case SHIFT_ASHIFTRT:
8c440872 4481 gcc_unreachable ();
1e5bdc40
KH		 4482 }
4483 }
48837e29
DE		 4484 else if (count == 31)
4485 {
dd69e230 4486 if (TARGET_H8300)
48837e29 4487 {
dd69e230
KH		 4488 switch (shift_type)
4489 {
4490 case SHIFT_ASHIFT:
4491 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4492 goto end;
4493 case SHIFT_LSHIFTRT:
4494 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4495 goto end;
4496 case SHIFT_ASHIFTRT:
4497 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4498 goto end;
4499 }
48837e29
DE		 4500 }
4501 else
4502 {
dd69e230 4503 switch (shift_type)
48837e29 4504 {
dd69e230
KH		 4505 case SHIFT_ASHIFT:
4506 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
45ca2106 4507 info->cc_special = CC_SET_ZNV;
dd69e230
KH		 4508 goto end;
4509 case SHIFT_LSHIFTRT:
4510 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
45ca2106 4511 info->cc_special = CC_SET_ZNV;
dd69e230
KH		 4512 goto end;
4513 case SHIFT_ASHIFTRT:
a7612343 4514 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
45ca2106 4515 info->cc_special = CC_SET_ZNV;
692b7eb3 4516 goto end;
48837e29 4517 }
48837e29
DE		 4518 }
4519 }
8c440872 4520 gcc_unreachable ();
51c0c1d7 4521
48837e29 4522 default:
8c440872 4523 gcc_unreachable ();
07aae5c2 4524 }
48837e29 4525
cb33eb17
KH		 4526 end:
4527 if (!TARGET_H8300S)
4528 info->shift2 = NULL;
07aae5c2
SC		 4529}
4530
be1e06df
KH		 4531/* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4532 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4533
4534int
ef4bddc2 4535h8300_shift_needs_scratch_p (int count, machine_mode mode)
be1e06df 4536{
b9b575e6 4537 enum h8_cpu cpu;
be1e06df
KH		 4538 int a, lr, ar;
4539
4540 if (GET_MODE_BITSIZE (mode) <= count)
4541 return 1;
4542
4543 /* Find out the target CPU. */
4544 if (TARGET_H8300)
b9b575e6 4545 cpu = H8_300;
2f6bd6eb 4546 else if (TARGET_H8300S)
b9b575e6 4547 cpu = H8_S;
2f6bd6eb
YS		 4548 else
4549 cpu = H8_300H;
be1e06df
KH		 4550
4551 /* Find the shift algorithm. */
4552 switch (mode)
4553 {
4554 case QImode:
4555 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
4556 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
4557 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
4558 break;
4559
4560 case HImode:
4561 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
4562 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
4563 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
4564 break;
4565
4566 case SImode:
4567 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
4568 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
4569 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
4570 break;
4571
4572 default:
8c440872 4573 gcc_unreachable ();
be1e06df
KH		 4574 }
4575
aa2fb4dd 4576 /* On H8/300H, count == 8 uses a scratch register. */
be1e06df 4577 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
75a3503b 4578 || (TARGET_H8300H && mode == SImode && count == 8));
be1e06df
KH		 4579}
4580
e9eba255 4581/* Output the assembler code for doing shifts. */
48837e29 4582
441d04c6 4583const char *
cb713a8d 4584output_a_shift (rtx *operands)
07aae5c2 4585{
48837e29 4586 static int loopend_lab;
48837e29 4587 rtx shift = operands[3];
ef4bddc2 4588 machine_mode mode = GET_MODE (shift);
48837e29
DE		 4589 enum rtx_code code = GET_CODE (shift);
4590 enum shift_type shift_type;
4591 enum shift_mode shift_mode;
35fb3d1f 4592 struct shift_info info;
8c440872 4593 int n;
48837e29
DE		 4594
4595 loopend_lab++;
4596
4597 switch (mode)
4598 {
4599 case QImode:
4600 shift_mode = QIshift;
4601 break;
4602 case HImode:
4603 shift_mode = HIshift;
4604 break;
4605 case SImode:
4606 shift_mode = SIshift;
4607 break;
4608 default:
8c440872 4609 gcc_unreachable ();
48837e29 4610 }
07aae5c2 4611
48837e29 4612 switch (code)
07aae5c2 4613 {
48837e29
DE		 4614 case ASHIFTRT:
4615 shift_type = SHIFT_ASHIFTRT;
4616 break;
4617 case LSHIFTRT:
4618 shift_type = SHIFT_LSHIFTRT;
4619 break;
4620 case ASHIFT:
4621 shift_type = SHIFT_ASHIFT;
4622 break;
4623 default:
8c440872 4624 gcc_unreachable ();
48837e29 4625 }
07aae5c2 4626
8c440872
NS		 4627 /* This case must be taken care of by one of the two splitters
4628 that convert a variable shift into a loop. */
4629 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4630
4631 n = INTVAL (operands[2]);
4632
4633 /* If the count is negative, make it 0. */
4634 if (n < 0)
4635 n = 0;
4636 /* If the count is too big, truncate it.
4637 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4638 do the intuitive thing. */
4639 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4640 n = GET_MODE_BITSIZE (mode);
4641
4642 get_shift_alg (shift_type, shift_mode, n, &info);
4643
4644 switch (info.alg)
48837e29 4645 {
8c440872
NS		 4646 case SHIFT_SPECIAL:
4647 output_asm_insn (info.special, operands);
4648 /* Fall through. */
48837e29 4649
8c440872
NS		 4650 case SHIFT_INLINE:
4651 n = info.remainder;
48837e29 4652
8c440872
NS		 4653 /* Emit two bit shifts first. */
4654 if (info.shift2 != NULL)
48837e29 4655 {
8c440872
NS		 4656 for (; n > 1; n -= 2)
4657 output_asm_insn (info.shift2, operands);
4658 }
51c0c1d7 4659
8c440872
NS		 4660 /* Now emit one bit shifts for any residual. */
4661 for (; n > 0; n--)
4662 output_asm_insn (info.shift1, operands);
4663 return "";
4664
4665 case SHIFT_ROT_AND:
4666 {
4667 int m = GET_MODE_BITSIZE (mode) - n;
4668 const int mask = (shift_type == SHIFT_ASHIFT
4669 ? ((1 << m) - 1) << n
4670 : (1 << m) - 1);
4671 char insn_buf[200];
4672
4673 /* Not all possibilities of rotate are supported. They shouldn't
4674 be generated, but let's watch for 'em. */
4675 gcc_assert (info.shift1);
4676
4677 /* Emit two bit rotates first. */
4678 if (info.shift2 != NULL)
48837e29 4679 {
8c440872
NS		 4680 for (; m > 1; m -= 2)
4681 output_asm_insn (info.shift2, operands);
4682 }
4683
4684 /* Now single bit rotates for any residual. */
4685 for (; m > 0; m--)
4686 output_asm_insn (info.shift1, operands);
4687
4688 /* Now mask off the high bits. */
4689 switch (mode)
4690 {
4691 case QImode:
4692 sprintf (insn_buf, "and\t#%d,%%X0", mask);
4693 break;
51c0c1d7 4694
8c440872
NS		 4695 case HImode:
4696 gcc_assert (TARGET_H8300H || TARGET_H8300S);
4697 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
4698 break;
51c0c1d7 4699
8c440872
NS		 4700 default:
4701 gcc_unreachable ();
48837e29 4702 }
b5eaf9ba 4703
8c440872
NS		 4704 output_asm_insn (insn_buf, operands);
4705 return "";
4706 }
b5eaf9ba 4707
8c440872
NS		 4708 case SHIFT_LOOP:
4709 /* A loop to shift by a "large" constant value.
4710 If we have shift-by-2 insns, use them. */
4711 if (info.shift2 != NULL)
4712 {
4713 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
4714 names_big[REGNO (operands[4])]);
4715 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4716 output_asm_insn (info.shift2, operands);
4717 output_asm_insn ("add #0xff,%X4", operands);
4718 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4719 if (n % 2)
4720 output_asm_insn (info.shift1, operands);
4721 }
4722 else
4723 {
4724 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
4725 names_big[REGNO (operands[4])]);
4726 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4727 output_asm_insn (info.shift1, operands);
4728 output_asm_insn ("add #0xff,%X4", operands);
4729 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
51c0c1d7 4730 }
8c440872
NS		 4731 return "";
4732
4733 default:
4734 gcc_unreachable ();
07aae5c2 4735 }
07aae5c2 4736}
86855e8c 4737
0a2aaacc 4738/* Count the number of assembly instructions in a string TEMPL. */
e9eba255 4739
86855e8c 4740static unsigned int
0a2aaacc 4741h8300_asm_insn_count (const char *templ)
86855e8c
KH		 4742{
4743 unsigned int count = 1;
4744
0a2aaacc
KG		 4745 for (; *templ; templ++)
4746 if (*templ == '\n')
86855e8c
KH		 4747 count++;
4748
4749 return count;
4750}
4751
e9eba255
KH		 4752/* Compute the length of a shift insn. */
4753
86855e8c 4754unsigned int
cb713a8d 4755compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
86855e8c
KH		 4756{
4757 rtx shift = operands[3];
ef4bddc2 4758 machine_mode mode = GET_MODE (shift);
86855e8c
KH		 4759 enum rtx_code code = GET_CODE (shift);
4760 enum shift_type shift_type;
4761 enum shift_mode shift_mode;
4762 struct shift_info info;
4763 unsigned int wlength = 0;
4764
4765 switch (mode)
4766 {
4767 case QImode:
4768 shift_mode = QIshift;
4769 break;
4770 case HImode:
4771 shift_mode = HIshift;
4772 break;
4773 case SImode:
4774 shift_mode = SIshift;
4775 break;
4776 default:
8c440872 4777 gcc_unreachable ();
86855e8c
KH		 4778 }
4779
4780 switch (code)
4781 {
4782 case ASHIFTRT:
4783 shift_type = SHIFT_ASHIFTRT;
4784 break;
4785 case LSHIFTRT:
4786 shift_type = SHIFT_LSHIFTRT;
4787 break;
4788 case ASHIFT:
4789 shift_type = SHIFT_ASHIFT;
4790 break;
4791 default:
8c440872 4792 gcc_unreachable ();
86855e8c
KH		 4793 }
4794
4795 if (GET_CODE (operands[2]) != CONST_INT)
4796 {
4797 /* Get the assembler code to do one shift. */
4798 get_shift_alg (shift_type, shift_mode, 1, &info);
4799
4800 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
4801 }
4802 else
4803 {
4804 int n = INTVAL (operands[2]);
4805
4806 /* If the count is negative, make it 0. */
4807 if (n < 0)
4808 n = 0;
4809 /* If the count is too big, truncate it.
4810 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4811 do the intuitive thing. */
4812 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4813 n = GET_MODE_BITSIZE (mode);
4814
4815 get_shift_alg (shift_type, shift_mode, n, &info);
4816
4817 switch (info.alg)
4818 {
4819 case SHIFT_SPECIAL:
4820 wlength += h8300_asm_insn_count (info.special);
41c3eb5d
KH		 4821
4822 /* Every assembly instruction used in SHIFT_SPECIAL case
4823 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4824 see xor.l, we just pretend that xor.l counts as two insns
4825 so that the insn length will be computed correctly. */
4826 if (strstr (info.special, "xor.l") != NULL)
4827 wlength++;
4828
86855e8c
KH		 4829 /* Fall through. */
4830
4831 case SHIFT_INLINE:
4832 n = info.remainder;
4833
4834 if (info.shift2 != NULL)
4835 {
4836 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
4837 n = n % 2;
4838 }
4839
4840 wlength += h8300_asm_insn_count (info.shift1) * n;
6b148bd9 4841
86855e8c
KH		 4842 return 2 * wlength;
4843
4844 case SHIFT_ROT_AND:
4845 {
4846 int m = GET_MODE_BITSIZE (mode) - n;
4847
4848 /* Not all possibilities of rotate are supported. They shouldn't
4849 be generated, but let's watch for 'em. */
8c440872 4850 gcc_assert (info.shift1);
86855e8c
KH		 4851
4852 if (info.shift2 != NULL)
4853 {
4854 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
4855 m = m % 2;
4856 }
4857
4858 wlength += h8300_asm_insn_count (info.shift1) * m;
6b148bd9 4859
86855e8c
KH		 4860 /* Now mask off the high bits. */
4861 switch (mode)
4862 {
4863 case QImode:
4864 wlength += 1;
4865 break;
4866 case HImode:
4867 wlength += 2;
4868 break;
4869 case SImode:
8c440872 4870 gcc_assert (!TARGET_H8300);
86855e8c
KH		 4871 wlength += 3;
4872 break;
4873 default:
8c440872 4874 gcc_unreachable ();
86855e8c
KH		 4875 }
4876 return 2 * wlength;
4877 }
4878
4879 case SHIFT_LOOP:
4880 /* A loop to shift by a "large" constant value.
4881 If we have shift-by-2 insns, use them. */
4882 if (info.shift2 != NULL)
4883 {
4884 wlength += 3 + h8300_asm_insn_count (info.shift2);
4885 if (n % 2)
4886 wlength += h8300_asm_insn_count (info.shift1);
4887 }
4888 else
4889 {
4890 wlength += 3 + h8300_asm_insn_count (info.shift1);
4891 }
4892 return 2 * wlength;
4893
4894 default:
8c440872 4895 gcc_unreachable ();
86855e8c
KH		 4896 }
4897 }
4898}
45ca2106 4899
e9eba255
KH		 4900/* Compute which flag bits are valid after a shift insn. */
4901
9690aa8e 4902enum attr_cc
cb713a8d 4903compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
45ca2106
KH		 4904{
4905 rtx shift = operands[3];
ef4bddc2 4906 machine_mode mode = GET_MODE (shift);
45ca2106
KH		 4907 enum rtx_code code = GET_CODE (shift);
4908 enum shift_type shift_type;
4909 enum shift_mode shift_mode;
4910 struct shift_info info;
8c440872
NS		 4911 int n;
4912
45ca2106
KH		 4913 switch (mode)
4914 {
4915 case QImode:
4916 shift_mode = QIshift;
4917 break;
4918 case HImode:
4919 shift_mode = HIshift;
4920 break;
4921 case SImode:
4922 shift_mode = SIshift;
4923 break;
4924 default:
8c440872 4925 gcc_unreachable ();
45ca2106
KH		 4926 }
4927
4928 switch (code)
4929 {
4930 case ASHIFTRT:
4931 shift_type = SHIFT_ASHIFTRT;
4932 break;
4933 case LSHIFTRT:
4934 shift_type = SHIFT_LSHIFTRT;
4935 break;
4936 case ASHIFT:
4937 shift_type = SHIFT_ASHIFT;
4938 break;
4939 default:
8c440872 4940 gcc_unreachable ();
45ca2106
KH		 4941 }
4942
8c440872
NS		 4943 /* This case must be taken care of by one of the two splitters
4944 that convert a variable shift into a loop. */
4945 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4946
4947 n = INTVAL (operands[2]);
4948
4949 /* If the count is negative, make it 0. */
4950 if (n < 0)
4951 n = 0;
4952 /* If the count is too big, truncate it.
4953 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4954 do the intuitive thing. */
4955 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4956 n = GET_MODE_BITSIZE (mode);
4957
4958 get_shift_alg (shift_type, shift_mode, n, &info);
4959
4960 switch (info.alg)
45ca2106 4961 {
8c440872
NS		 4962 case SHIFT_SPECIAL:
4963 if (info.remainder == 0)
4964 return info.cc_special;
45ca2106 4965
8c440872 4966 /* Fall through. */
45ca2106 4967
8c440872
NS		 4968 case SHIFT_INLINE:
4969 return info.cc_inline;
4970
4971 case SHIFT_ROT_AND:
4972 /* This case always ends with an and instruction. */
4973 return CC_SET_ZNV;
4974
4975 case SHIFT_LOOP:
4976 /* A loop to shift by a "large" constant value.
4977 If we have shift-by-2 insns, use them. */
4978 if (info.shift2 != NULL)
45ca2106 4979 {
8c440872
NS		 4980 if (n % 2)
4981 return info.cc_inline;
45ca2106 4982 }
8c440872
NS		 4983 return CC_CLOBBER;
4984
4985 default:
4986 gcc_unreachable ();
45ca2106
KH		 4987 }
4988}
48837e29 4989\f
edd71f0f
KH		 4990/* A rotation by a non-constant will cause a loop to be generated, in
4991 which a rotation by one bit is used. A rotation by a constant,
4992 including the one in the loop, will be taken care of by
caf7f21a 4993 output_a_rotate () at the insn emit time. */
edd71f0f
KH		 4994
4995int
3d2e90d6 4996expand_a_rotate (rtx operands[])
edd71f0f
KH		 4997{
4998 rtx dst = operands[0];
4999 rtx src = operands[1];
5000 rtx rotate_amount = operands[2];
ef4bddc2 5001 machine_mode mode = GET_MODE (dst);
edd71f0f 5002
beed8fc0
AO		 5003 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
5004 return false;
5005
edd71f0f
KH		 5006 /* We rotate in place. */
5007 emit_move_insn (dst, src);
5008
5009 if (GET_CODE (rotate_amount) != CONST_INT)
5010 {
5011 rtx counter = gen_reg_rtx (QImode);
19f8b229
TS		 5012 rtx_code_label *start_label = gen_label_rtx ();
5013 rtx_code_label *end_label = gen_label_rtx ();
edd71f0f
KH		 5014
5015 /* If the rotate amount is less than or equal to 0,
5016 we go out of the loop. */
a556fd39 5017 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
d43e0b7d 5018 QImode, 0, end_label);
edd71f0f
KH		 5019
5020 /* Initialize the loop counter. */
5021 emit_move_insn (counter, rotate_amount);
5022
5023 emit_label (start_label);
5024
5025 /* Rotate by one bit. */
01ab5574
KH		 5026 switch (mode)
5027 {
5028 case QImode:
5029 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
5030 break;
5031 case HImode:
5032 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
5033 break;
5034 case SImode:
5035 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
5036 break;
5037 default:
8c440872 5038 gcc_unreachable ();
01ab5574 5039 }
edd71f0f
KH		 5040
5041 /* Decrement the counter by 1. */
01ab5574 5042 emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
edd71f0f 5043
9cd10576 5044 /* If the loop counter is nonzero, we go back to the beginning
edd71f0f 5045 of the loop. */
a556fd39 5046 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
d43e0b7d 5047 start_label);
edd71f0f
KH		 5048
5049 emit_label (end_label);
5050 }
5051 else
5052 {
5053 /* Rotate by AMOUNT bits. */
01ab5574
KH		 5054 switch (mode)
5055 {
5056 case QImode:
5057 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
5058 break;
5059 case HImode:
5060 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
5061 break;
5062 case SImode:
5063 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
5064 break;
5065 default:
8c440872 5066 gcc_unreachable ();
01ab5574 5067 }
edd71f0f
KH		 5068 }
5069
5070 return 1;
5071}
5072
e9eba255 5073/* Output a rotate insn. */
edd71f0f
KH		 5074
5075const char *
caf7f21a 5076output_a_rotate (enum rtx_code code, rtx *operands)
edd71f0f
KH		 5077{
5078 rtx dst = operands[0];
5079 rtx rotate_amount = operands[2];
5080 enum shift_mode rotate_mode;
5081 enum shift_type rotate_type;
5082 const char *insn_buf;
5083 int bits;
5084 int amount;
ef4bddc2 5085 machine_mode mode = GET_MODE (dst);
edd71f0f 5086
8c440872 5087 gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
edd71f0f
KH		 5088
5089 switch (mode)
5090 {
5091 case QImode:
5092 rotate_mode = QIshift;
5093 break;
5094 case HImode:
5095 rotate_mode = HIshift;
5096 break;
5097 case SImode:
5098 rotate_mode = SIshift;
5099 break;
5100 default:
8c440872 5101 gcc_unreachable ();
edd71f0f
KH		 5102 }
5103
5104 switch (code)
5105 {
5106 case ROTATERT:
5107 rotate_type = SHIFT_ASHIFT;
5108 break;
5109 case ROTATE:
5110 rotate_type = SHIFT_LSHIFTRT;
5111 break;
5112 default:
8c440872 5113 gcc_unreachable ();
edd71f0f
KH		 5114 }
5115
5116 amount = INTVAL (rotate_amount);
5117
5118 /* Clean up AMOUNT. */
5119 if (amount < 0)
5120 amount = 0;
5121 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5122 amount = GET_MODE_BITSIZE (mode);
5123
5124 /* Determine the faster direction. After this phase, amount will be
5125 at most a half of GET_MODE_BITSIZE (mode). */
e0c32c62 5126 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
edd71f0f
KH		 5127 {
5128 /* Flip the direction. */
5129 amount = GET_MODE_BITSIZE (mode) - amount;
5130 rotate_type =
5131 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5132 }
5133
5134 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5135 boost up the rotation. */
5136 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5137 || (mode == HImode && TARGET_H8300H && amount >= 6)
5138 || (mode == HImode && TARGET_H8300S && amount == 8)
5139 || (mode == SImode && TARGET_H8300H && amount >= 10)
5140 || (mode == SImode && TARGET_H8300S && amount >= 13))
5141 {
5142 switch (mode)
5143 {
5144 case HImode:
5145 /* This code works on any family. */
5146 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5147 output_asm_insn (insn_buf, operands);
5148 break;
5149
5150 case SImode:
3db11b5c 5151 /* This code works on the H8/300H and H8S. */
edd71f0f
KH		 5152 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5153 output_asm_insn (insn_buf, operands);
5154 break;
5155
5156 default:
8c440872 5157 gcc_unreachable ();
edd71f0f
KH		 5158 }
5159
5160 /* Adjust AMOUNT and flip the direction. */
5161 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5162 rotate_type =
5163 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5164 }
5165
01ab5574 5166 /* Output rotate insns. */
edd71f0f
KH		 5167 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
5168 {
5169 if (bits == 2)
5170 insn_buf = rotate_two[rotate_type][rotate_mode];
5171 else
5172 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
2c54abce 5173
edd71f0f
KH		 5174 for (; amount >= bits; amount -= bits)
5175 output_asm_insn (insn_buf, operands);
5176 }
5177
5178 return "";
5179}
caf7f21a 5180
e9eba255
KH		 5181/* Compute the length of a rotate insn. */
5182
caf7f21a
KH		 5183unsigned int
5184compute_a_rotate_length (rtx *operands)
5185{
5186 rtx src = operands[1];
343fd2c7 5187 rtx amount_rtx = operands[2];
ef4bddc2 5188 machine_mode mode = GET_MODE (src);
caf7f21a
KH		 5189 int amount;
5190 unsigned int length = 0;
5191
8c440872 5192 gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
caf7f21a 5193
343fd2c7 5194 amount = INTVAL (amount_rtx);
caf7f21a
KH		 5195
5196 /* Clean up AMOUNT. */
5197 if (amount < 0)
5198 amount = 0;
5199 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5200 amount = GET_MODE_BITSIZE (mode);
5201
5202 /* Determine the faster direction. After this phase, amount
5203 will be at most a half of GET_MODE_BITSIZE (mode). */
5204 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5205 /* Flip the direction. */
5206 amount = GET_MODE_BITSIZE (mode) - amount;
5207
5208 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5209 boost up the rotation. */
5210 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5211 || (mode == HImode && TARGET_H8300H && amount >= 6)
5212 || (mode == HImode && TARGET_H8300S && amount == 8)
5213 || (mode == SImode && TARGET_H8300H && amount >= 10)
5214 || (mode == SImode && TARGET_H8300S && amount >= 13))
5215 {
5216 /* Adjust AMOUNT and flip the direction. */
5217 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5218 length += 6;
5219 }
5220
5221 /* We use 2-bit rotations on the H8S. */
5222 if (TARGET_H8300S)
5223 amount = amount / 2 + amount % 2;
5224
5225 /* The H8/300 uses three insns to rotate one bit, taking 6
5226 length. */
5227 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
5228
5229 return length;
5230}
edd71f0f 5231\f
48837e29 5232/* Fix the operands of a gen_xxx so that it could become a bit
2c54abce 5233 operating insn. */
07aae5c2
SC		 5234
5235int
4093985c 5236fix_bit_operand (rtx *operands, enum rtx_code code)
07aae5c2 5237{
abc95ed3 5238 /* The bit_operand predicate accepts any memory during RTL generation, but
48837e29
DE		 5239 only 'U' memory afterwards, so if this is a MEM operand, we must force
5240 it to be valid for 'U' by reloading the address. */
07aae5c2 5241
4093985c
KH		 5242 if (code == AND
5243 ? single_zero_operand (operands[2], QImode)
5244 : single_one_operand (operands[2], QImode))
07aae5c2 5245 {
2e760b15
KH		 5246 /* OK to have a memory dest. */
5247 if (GET_CODE (operands[0]) == MEM
ceaaaeab 5248 && !satisfies_constraint_U (operands[0]))
48837e29 5249 {
2e760b15
KH		 5250 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
5251 copy_to_mode_reg (Pmode,
5252 XEXP (operands[0], 0)));
5253 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5254 operands[0] = mem;
5255 }
48837e29 5256
2e760b15 5257 if (GET_CODE (operands[1]) == MEM
ceaaaeab 5258 && !satisfies_constraint_U (operands[1]))
2e760b15
KH		 5259 {
5260 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
5261 copy_to_mode_reg (Pmode,
5262 XEXP (operands[1], 0)));
5263 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5264 operands[1] = mem;
48837e29 5265 }
2e760b15 5266 return 0;
48837e29 5267 }
07aae5c2 5268
48837e29 5269 /* Dest and src op must be register. */
07aae5c2 5270
48837e29
DE		 5271 operands[1] = force_reg (QImode, operands[1]);
5272 {
5273 rtx res = gen_reg_rtx (QImode);
fd57a6e4 5274 switch (code)
a3579575
KH		 5275 {
5276 case AND:
5277 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
5278 break;
5279 case IOR:
5280 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
5281 break;
5282 case XOR:
5283 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
5284 break;
5285 default:
8c440872 5286 gcc_unreachable ();
a3579575
KH		 5287 }
5288 emit_insn (gen_movqi (operands[0], res));
48837e29
DE		 5289 }
5290 return 1;
07aae5c2 5291}
f5b65a56 5292
f5b65a56
JL		 5293/* Return nonzero if FUNC is an interrupt function as specified
5294 by the "interrupt" attribute. */
5295
5296static int
cb713a8d 5297h8300_interrupt_function_p (tree func)
f5b65a56
JL		 5298{
5299 tree a;
5300
5301 if (TREE_CODE (func) != FUNCTION_DECL)
5302 return 0;
5303
91d231cb 5304 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
f5b65a56
JL		 5305 return a != NULL_TREE;
5306}
5307
3cfa3702
KH		 5308/* Return nonzero if FUNC is a saveall function as specified by the
5309 "saveall" attribute. */
5310
5311static int
5312h8300_saveall_function_p (tree func)
5313{
5314 tree a;
5315
5316 if (TREE_CODE (func) != FUNCTION_DECL)
5317 return 0;
5318
5319 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
5320 return a != NULL_TREE;
5321}
5322
fabe72bb
JL		 5323/* Return nonzero if FUNC is an OS_Task function as specified
5324 by the "OS_Task" attribute. */
5325
5326static int
cb713a8d 5327h8300_os_task_function_p (tree func)
fabe72bb
JL		 5328{
5329 tree a;
5330
5331 if (TREE_CODE (func) != FUNCTION_DECL)
5332 return 0;
5333
91d231cb 5334 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
fabe72bb
JL		 5335 return a != NULL_TREE;
5336}
5337
5338/* Return nonzero if FUNC is a monitor function as specified
5339 by the "monitor" attribute. */
5340
5341static int
cb713a8d 5342h8300_monitor_function_p (tree func)
fabe72bb
JL		 5343{
5344 tree a;
5345
5346 if (TREE_CODE (func) != FUNCTION_DECL)
5347 return 0;
5348
91d231cb 5349 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
fabe72bb
JL		 5350 return a != NULL_TREE;
5351}
5352
f5b65a56
JL		 5353/* Return nonzero if FUNC is a function that should be called
5354 through the function vector. */
5355
5356int
cb713a8d 5357h8300_funcvec_function_p (tree func)
f5b65a56
JL		 5358{
5359 tree a;
5360
5361 if (TREE_CODE (func) != FUNCTION_DECL)
5362 return 0;
5363
91d231cb 5364 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
f5b65a56
JL		 5365 return a != NULL_TREE;
5366}
5367
887a8bd9 5368/* Return nonzero if DECL is a variable that's in the eight bit
15dc331e
JL		 5369 data area. */
5370
5371int
cb713a8d 5372h8300_eightbit_data_p (tree decl)
15dc331e
JL		 5373{
5374 tree a;
5375
5376 if (TREE_CODE (decl) != VAR_DECL)
5377 return 0;
5378
91d231cb 5379 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
15dc331e
JL		 5380 return a != NULL_TREE;
5381}
5382
887a8bd9
JL		 5383/* Return nonzero if DECL is a variable that's in the tiny
5384 data area. */
5385
5386int
cb713a8d 5387h8300_tiny_data_p (tree decl)
887a8bd9
JL		 5388{
5389 tree a;
5390
5391 if (TREE_CODE (decl) != VAR_DECL)
5392 return 0;
5393
91d231cb 5394 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
887a8bd9
JL		 5395 return a != NULL_TREE;
5396}
5397
3cfa3702
KH		 5398/* Generate an 'interrupt_handler' attribute for decls. We convert
5399 all the pragmas to corresponding attributes. */
2c1d2fcb
DD		 5400
5401static void
cb713a8d 5402h8300_insert_attributes (tree node, tree *attributes)
2c1d2fcb 5403{
3cfa3702
KH		 5404 if (TREE_CODE (node) == FUNCTION_DECL)
5405 {
5406 if (pragma_interrupt)
5407 {
5408 pragma_interrupt = 0;
2c1d2fcb 5409
3cfa3702
KH		 5410 /* Add an 'interrupt_handler' attribute. */
5411 *attributes = tree_cons (get_identifier ("interrupt_handler"),
5412 NULL, *attributes);
5413 }
e392d367 5414
3cfa3702
KH		 5415 if (pragma_saveall)
5416 {
5417 pragma_saveall = 0;
5418
5419 /* Add an 'saveall' attribute. */
5420 *attributes = tree_cons (get_identifier ("saveall"),
5421 NULL, *attributes);
5422 }
5423 }
2c1d2fcb
DD		 5424}
5425
91d231cb 5426/* Supported attributes:
f5b65a56 5427
97c5ec1d 5428 interrupt_handler: output a prologue and epilogue suitable for an
f5b65a56
JL		 5429 interrupt handler.
5430
3cfa3702
KH		 5431 saveall: output a prologue and epilogue that saves and restores
5432 all registers except the stack pointer.
5433
97c5ec1d 5434 function_vector: This function should be called through the
887a8bd9
JL		 5435 function vector.
5436
5437 eightbit_data: This variable lives in the 8-bit data area and can
5438 be referenced with 8-bit absolute memory addresses.
5439
5440 tiny_data: This variable lives in the tiny data area and can be
5441 referenced with 16-bit absolute memory references. */
f5b65a56 5442
6bc7bc14 5443static const struct attribute_spec h8300_attribute_table[] =
f5b65a56 5444{
62d784f7
KT		 5445 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
5446 affects_type_identity } */
5447 { "interrupt_handler", 0, 0, true, false, false,
5448 h8300_handle_fndecl_attribute, false },
5449 { "saveall", 0, 0, true, false, false,
5450 h8300_handle_fndecl_attribute, false },
5451 { "OS_Task", 0, 0, true, false, false,
5452 h8300_handle_fndecl_attribute, false },
5453 { "monitor", 0, 0, true, false, false,
5454 h8300_handle_fndecl_attribute, false },
5455 { "function_vector", 0, 0, true, false, false,
5456 h8300_handle_fndecl_attribute, false },
5457 { "eightbit_data", 0, 0, true, false, false,
5458 h8300_handle_eightbit_data_attribute, false },
5459 { "tiny_data", 0, 0, true, false, false,
5460 h8300_handle_tiny_data_attribute, false },
5461 { NULL, 0, 0, false, false, false, NULL, false }
91d231cb 5462};
f5b65a56 5463
15dc331e 5464
91d231cb
JM		 5465/* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5466 struct attribute_spec.handler. */
5467static tree
cb713a8d
KH		 5468h8300_handle_fndecl_attribute (tree *node, tree name,
5469 tree args ATTRIBUTE_UNUSED,
5470 int flags ATTRIBUTE_UNUSED,
5471 bool *no_add_attrs)
91d231cb
JM		 5472{
5473 if (TREE_CODE (*node) != FUNCTION_DECL)
5474 {
29d08eba
JM		 5475 warning (OPT_Wattributes, "%qE attribute only applies to functions",
5476 name);
91d231cb
JM		 5477 *no_add_attrs = true;
5478 }
5479
5480 return NULL_TREE;
5481}
5482
5483/* Handle an "eightbit_data" attribute; arguments as in
5484 struct attribute_spec.handler. */
5485static tree
cb713a8d
KH		 5486h8300_handle_eightbit_data_attribute (tree *node, tree name,
5487 tree args ATTRIBUTE_UNUSED,
5488 int flags ATTRIBUTE_UNUSED,
5489 bool *no_add_attrs)
91d231cb
JM		 5490{
5491 tree decl = *node;
5492
5493 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
15dc331e 5494 {
f961457f 5495 set_decl_section_name (decl, ".eight");
91d231cb
JM		 5496 }
5497 else
5498 {
29d08eba
JM		 5499 warning (OPT_Wattributes, "%qE attribute ignored",
5500 name);
91d231cb 5501 *no_add_attrs = true;
887a8bd9
JL		 5502 }
5503
91d231cb
JM		 5504 return NULL_TREE;
5505}
5506
5507/* Handle an "tiny_data" attribute; arguments as in
5508 struct attribute_spec.handler. */
5509static tree
cb713a8d
KH		 5510h8300_handle_tiny_data_attribute (tree *node, tree name,
5511 tree args ATTRIBUTE_UNUSED,
5512 int flags ATTRIBUTE_UNUSED,
5513 bool *no_add_attrs)
91d231cb
JM		 5514{
5515 tree decl = *node;
5516
5517 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
887a8bd9 5518 {
f961457f 5519 set_decl_section_name (decl, ".tiny");
91d231cb
JM		 5520 }
5521 else
5522 {
29d08eba
JM		 5523 warning (OPT_Wattributes, "%qE attribute ignored",
5524 name);
91d231cb 5525 *no_add_attrs = true;
15dc331e 5526 }
07e4d94e 5527
91d231cb 5528 return NULL_TREE;
f5b65a56
JL		 5529}
5530
dc66a1c4 5531/* Mark function vectors, and various small data objects. */
fb49053f
RH		 5532
5533static void
cb713a8d 5534h8300_encode_section_info (tree decl, rtx rtl, int first)
fb49053f 5535{
dc66a1c4
RH		 5536 int extra_flags = 0;
5537
c6a2438a 5538 default_encode_section_info (decl, rtl, first);
dc66a1c4 5539
fb49053f
RH		 5540 if (TREE_CODE (decl) == FUNCTION_DECL
5541 && h8300_funcvec_function_p (decl))
dc66a1c4 5542 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
fb49053f
RH		 5543 else if (TREE_CODE (decl) == VAR_DECL
5544 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
5545 {
5546 if (h8300_eightbit_data_p (decl))
dc66a1c4 5547 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
fb49053f 5548 else if (first && h8300_tiny_data_p (decl))
dc66a1c4 5549 extra_flags = SYMBOL_FLAG_TINY_DATA;
fb49053f 5550 }
772c5265 5551
dc66a1c4 5552 if (extra_flags)
c6a2438a 5553 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
772c5265
RH		 5554}
5555
e9eba255
KH		 5556/* Output a single-bit extraction. */
5557
441d04c6 5558const char *
cb713a8d 5559output_simode_bld (int bild, rtx operands[])
bd93f126 5560{
6be580c7
KH		 5561 if (TARGET_H8300)
5562 {
5563 /* Clear the destination register. */
5564 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
5565
5566 /* Now output the bit load or bit inverse load, and store it in
5567 the destination. */
5568 if (bild)
5569 output_asm_insn ("bild\t%Z2,%Y1", operands);
5570 else
5571 output_asm_insn ("bld\t%Z2,%Y1", operands);
bd93f126 5572
6be580c7
KH		 5573 output_asm_insn ("bst\t#0,%w0", operands);
5574 }
bd93f126 5575 else
6be580c7 5576 {
0eb933a0
KH		 5577 /* Determine if we can clear the destination first. */
5578 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
5579 && REGNO (operands[0]) != REGNO (operands[1]));
5580
5581 if (clear_first)
5582 output_asm_insn ("sub.l\t%S0,%S0", operands);
5583
6be580c7
KH		 5584 /* Output the bit load or bit inverse load. */
5585 if (bild)
5586 output_asm_insn ("bild\t%Z2,%Y1", operands);
5587 else
5588 output_asm_insn ("bld\t%Z2,%Y1", operands);
5589
0eb933a0
KH		 5590 if (!clear_first)
5591 output_asm_insn ("xor.l\t%S0,%S0", operands);
5592
5593 /* Perform the bit store. */
802a9907 5594 output_asm_insn ("rotxl.l\t%S0", operands);
6be580c7 5595 }
bd93f126
JL		 5596
5597 /* All done. */
5598 return "";
5599}
e6219736 5600
beed8fc0
AO		 5601/* Delayed-branch scheduling is more effective if we have some idea
5602 how long each instruction will be. Use a shorten_branches pass
5603 to get an initial estimate. */
5604
5605static void
5606h8300_reorg (void)
5607{
5608 if (flag_delayed_branch)
5609 shorten_branches (get_insns ());
5610}
5611
ede75ee8 5612#ifndef OBJECT_FORMAT_ELF
7c262518 5613static void
c18a5b6c
MM		 5614h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED,
5615 tree decl)
7c262518
RH		 5616{
5617 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5618 fprintf (asm_out_file, "\t.section %s\n", name);
5619}
ede75ee8 5620#endif /* ! OBJECT_FORMAT_ELF */
803d56f5 5621
7c143ed2
KH		 5622/* Nonzero if X is a constant address suitable as an 8-bit absolute,
5623 which is a special case of the 'R' operand. */
5624
803d56f5 5625int
cb713a8d 5626h8300_eightbit_constant_address_p (rtx x)
803d56f5 5627{
ff482c8d 5628 /* The ranges of the 8-bit area. */
d2d199a3
KH		 5629 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
5630 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
803d56f5
KH		 5631 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
5632 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
5633 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
5634 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
5635
5636 unsigned HOST_WIDE_INT addr;
5637
9675a91e 5638 /* We accept symbols declared with eightbit_data. */
dc66a1c4
RH		 5639 if (GET_CODE (x) == SYMBOL_REF)
5640 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
9675a91e 5641
9f9ab303
JL		 5642 if (GET_CODE (x) == CONST
5643 && GET_CODE (XEXP (x, 0)) == PLUS
5644 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
5645 && (SYMBOL_REF_FLAGS (XEXP (XEXP (x, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0)
5646 return 1;
5647
803d56f5
KH		 5648 if (GET_CODE (x) != CONST_INT)
5649 return 0;
5650
5651 addr = INTVAL (x);
5652
5653 return (0
39ba95b5 5654 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
803d56f5
KH		 5655 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
5656 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
5657}
5658
7c143ed2
KH		 5659/* Nonzero if X is a constant address suitable as an 16-bit absolute
5660 on H8/300H and H8S. */
5661
803d56f5 5662int
cb713a8d 5663h8300_tiny_constant_address_p (rtx x)
803d56f5 5664{
3f7211f1 5665 /* The ranges of the 16-bit area. */
803d56f5
KH		 5666 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
5667 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
5668 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
5669 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
5670 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
5671 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
5672 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
5673 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
5674
5675 unsigned HOST_WIDE_INT addr;
5676
d6456562
KH		 5677 switch (GET_CODE (x))
5678 {
5679 case SYMBOL_REF:
a4bb41cc
KH		 5680 /* In the normal mode, any symbol fits in the 16-bit absolute
5681 address range. We also accept symbols declared with
5682 tiny_data. */
5683 return (TARGET_NORMAL_MODE
5684 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
56b8e164 5685
d6456562
KH		 5686 case CONST_INT:
5687 addr = INTVAL (x);
5688 return (TARGET_NORMAL_MODE
5689 || (TARGET_H8300H
5690 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
5691 || (TARGET_H8300S
5692 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
803d56f5 5693
a4bb41cc
KH		 5694 case CONST:
5695 return TARGET_NORMAL_MODE;
5696
d6456562
KH		 5697 default:
5698 return 0;
5699 }
803d56f5 5700
803d56f5 5701}
9b98dc74 5702
e9eba255
KH		 5703/* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5704 locations that can be accessed as a 16-bit word. */
5705
9b98dc74 5706int
cb713a8d 5707byte_accesses_mergeable_p (rtx addr1, rtx addr2)
9b98dc74
KH		 5708{
5709 HOST_WIDE_INT offset1, offset2;
5710 rtx reg1, reg2;
5711
5712 if (REG_P (addr1))
5713 {
5714 reg1 = addr1;
5715 offset1 = 0;
5716 }
5717 else if (GET_CODE (addr1) == PLUS
5718 && REG_P (XEXP (addr1, 0))
5719 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
5720 {
5721 reg1 = XEXP (addr1, 0);
5722 offset1 = INTVAL (XEXP (addr1, 1));
5723 }
5724 else
5725 return 0;
5726
5727 if (REG_P (addr2))
5728 {
5729 reg2 = addr2;
5730 offset2 = 0;
5731 }
5732 else if (GET_CODE (addr2) == PLUS
5733 && REG_P (XEXP (addr2, 0))
5734 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
5735 {
5736 reg2 = XEXP (addr2, 0);
5737 offset2 = INTVAL (XEXP (addr2, 1));
5738 }
5739 else
5740 return 0;
5741
5742 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
5743 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
5744 && offset1 % 2 == 0
5745 && offset1 + 1 == offset2)
5746 return 1;
5747
5748 return 0;
5749}
02529902
KH		 5750
5751/* Return nonzero if we have the same comparison insn as I3 two insns
19cff4db 5752 before I3. I3 is assumed to be a comparison insn. */
02529902
KH		 5753
5754int
5755same_cmp_preceding_p (rtx i3)
5756{
68a1a6c0 5757 rtx_insn *i1, *i2;
02529902
KH		 5758
5759 /* Make sure we have a sequence of three insns. */
5760 i2 = prev_nonnote_insn (i3);
68a1a6c0 5761 if (i2 == NULL)
02529902
KH		 5762 return 0;
5763 i1 = prev_nonnote_insn (i2);
68a1a6c0 5764 if (i1 == NULL)
02529902
KH		 5765 return 0;
5766
5767 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5768 && any_condjump_p (i2) && onlyjump_p (i2));
5769}
c87ec0ba 5770
c06d5c85
KH		 5771/* Return nonzero if we have the same comparison insn as I1 two insns
5772 after I1. I1 is assumed to be a comparison insn. */
5773
5774int
5775same_cmp_following_p (rtx i1)
5776{
68a1a6c0 5777 rtx_insn *i2, *i3;
c06d5c85
KH		 5778
5779 /* Make sure we have a sequence of three insns. */
5780 i2 = next_nonnote_insn (i1);
68a1a6c0 5781 if (i2 == NULL)
c06d5c85
KH		 5782 return 0;
5783 i3 = next_nonnote_insn (i2);
68a1a6c0 5784 if (i3 == NULL)
c06d5c85
KH		 5785 return 0;
5786
5787 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5788 && any_condjump_p (i2) && onlyjump_p (i2));
5789}
5790
a466bea3 5791/* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
1ae58c30 5792 (or pops) N registers. OPERANDS are assumed to be an array of
a466bea3
KH		 5793 registers. */
5794
5795int
5796h8300_regs_ok_for_stm (int n, rtx operands[])
5797{
5798 switch (n)
5799 {
5800 case 2:
5801 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
5802 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
5803 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
5804 case 3:
5805 return ((REGNO (operands[0]) == 0
5806 && REGNO (operands[1]) == 1
5807 && REGNO (operands[2]) == 2)
5808 || (REGNO (operands[0]) == 4
5809 && REGNO (operands[1]) == 5
5810 && REGNO (operands[2]) == 6));
5811
5812 case 4:
5813 return (REGNO (operands[0]) == 0
5814 && REGNO (operands[1]) == 1
5815 && REGNO (operands[2]) == 2
5816 && REGNO (operands[3]) == 3);
8c440872
NS		 5817 default:
5818 gcc_unreachable ();
a466bea3 5819 }
a466bea3
KH		 5820}
5821
c87ec0ba
NY		 5822/* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5823
5824int
5825h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5826 unsigned int new_reg)
5827{
5828 /* Interrupt functions can only use registers that have already been
5829 saved by the prologue, even if they would normally be
5830 call-clobbered. */
5831
5832 if (h8300_current_function_interrupt_function_p ()
6fb5fa3c 5833 && !df_regs_ever_live_p (new_reg))
c87ec0ba
NY		 5834 return 0;
5835
80e58519 5836 return 1;
c87ec0ba 5837}
d0022200 5838
2e762884
DD		 5839/* Returns true if register REGNO is safe to be allocated as a scratch
5840 register in the current function. */
5841
5842static bool
5843h8300_hard_regno_scratch_ok (unsigned int regno)
5844{
5845 if (h8300_current_function_interrupt_function_p ()
5846 && ! WORD_REG_USED (regno))
5847 return false;
5848
5849 return true;
5850}
5851
5852
d0022200
KH		 5853/* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5854
5855static int
5856h8300_rtx_ok_for_base_p (rtx x, int strict)
5857{
5858 /* Strip off SUBREG if any. */
5859 if (GET_CODE (x) == SUBREG)
5860 x = SUBREG_REG (x);
5861
5862 return (REG_P (x)
5863 && (strict
5864 ? REG_OK_FOR_BASE_STRICT_P (x)
5865 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
5866}
5867
5868/* Return nozero if X is a legitimate address. On the H8/300, a
5869 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5870 CONSTANT_ADDRESS. */
5871
c6c3dba9 5872static bool
ef4bddc2 5873h8300_legitimate_address_p (machine_mode mode, rtx x, bool strict)
d0022200
KH		 5874{
5875 /* The register indirect addresses like @er0 is always valid. */
5876 if (h8300_rtx_ok_for_base_p (x, strict))
5877 return 1;
5878
5879 if (CONSTANT_ADDRESS_P (x))
5880 return 1;
5881
beed8fc0
AO		 5882 if (TARGET_H8300SX
5883 && ( GET_CODE (x) == PRE_INC
5884 || GET_CODE (x) == PRE_DEC
5885 || GET_CODE (x) == POST_INC
5886 || GET_CODE (x) == POST_DEC)
5887 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
5888 return 1;
5889
d0022200
KH		 5890 if (GET_CODE (x) == PLUS
5891 && CONSTANT_ADDRESS_P (XEXP (x, 1))
beed8fc0
AO		 5892 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
5893 mode, 0), strict))
d0022200
KH		 5894 return 1;
5895
5896 return 0;
5897}
07ee3b58
KH		 5898
5899/* Worker function for HARD_REGNO_NREGS.
5900
5901 We pretend the MAC register is 32bits -- we don't have any data
5902 types on the H8 series to handle more than 32bits. */
5903
5904int
ef4bddc2 5905h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, machine_mode mode)
07ee3b58
KH		 5906{
5907 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5908}
5909
5910/* Worker function for HARD_REGNO_MODE_OK. */
5911
5912int
ef4bddc2 5913h8300_hard_regno_mode_ok (int regno, machine_mode mode)
07ee3b58
KH		 5914{
5915 if (TARGET_H8300)
5916 /* If an even reg, then anything goes. Otherwise the mode must be
5917 QI or HI. */
5918 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
5919 else
5920 /* MAC register can only be of SImode. Otherwise, anything
5921 goes. */
5922 return regno == MAC_REG ? mode == SImode : 1;
5923}
f9b4f8c1
RH		 5924
5925/* Helper function for the move patterns. Make sure a move is legitimate. */
5926
5927bool
5928h8300_move_ok (rtx dest, rtx src)
5929{
5930 rtx addr, other;
5931
5932 /* Validate that at least one operand is a register. */
5933 if (MEM_P (dest))
5934 {
5935 if (MEM_P (src) || CONSTANT_P (src))
5936 return false;
5937 addr = XEXP (dest, 0);
5938 other = src;
5939 }
5940 else if (MEM_P (src))
5941 {
5942 addr = XEXP (src, 0);
5943 other = dest;
5944 }
5945 else
5946 return true;
5947
5948 /* Validate that auto-inc doesn't affect OTHER. */
5949 if (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC)
5950 return true;
5951 addr = XEXP (addr, 0);
5952
5953 if (addr == stack_pointer_rtx)
5954 return register_no_sp_elim_operand (other, VOIDmode);
5955 else
5956 return !reg_overlap_mentioned_p(other, addr);
5957}
6e014ef3 5958\f
c15c90bb
ZW		 5959/* Perform target dependent optabs initialization. */
5960static void
5961h8300_init_libfuncs (void)
5962{
5963 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
5964 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
5965 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
5966 set_optab_libfunc (smod_optab, HImode, "__modhi3");
5967 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
5968}
5969\f
9eaa7740
AS		 5970/* Worker function for TARGET_FUNCTION_VALUE.
5971
5972 On the H8 the return value is in R0/R1. */
5973
5974static rtx
5975h8300_function_value (const_tree ret_type,
5976 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
5977 bool outgoing ATTRIBUTE_UNUSED)
5978{
5979 return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG);
5980}
5981
5982/* Worker function for TARGET_LIBCALL_VALUE.
5983
5984 On the H8 the return value is in R0/R1. */
5985
5986static rtx
ef4bddc2 5987h8300_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
9eaa7740
AS		 5988{
5989 return gen_rtx_REG (mode, R0_REG);
5990}
5991
5992/* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5993
5994 On the H8, R0 is the only register thus used. */
5995
5996static bool
5997h8300_function_value_regno_p (const unsigned int regno)
5998{
5999 return (regno == R0_REG);
6000}
6001
e9eba255
KH		 6002/* Worker function for TARGET_RETURN_IN_MEMORY. */
6003
34bf1fe3 6004static bool
586de218 6005h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
34bf1fe3
KH		 6006{
6007 return (TYPE_MODE (type) == BLKmode
6008 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
6009}
6010\f
9f6ef043
RH		 6011/* We emit the entire trampoline here. Depending on the pointer size,
6012 we use a different trampoline.
6013
6014 Pmode == HImode
6015 vvvv context
6016 1 0000 7903xxxx mov.w #0x1234,r3
6017 2 0004 5A00xxxx jmp @0x1234
6018 ^^^^ function
6019
6020 Pmode == SImode
6021 vvvvvvvv context
6022 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
6023 3 0006 5Axxxxxx jmp @0x123456
6024 ^^^^^^ function
6025*/
6026
6027static void
6028h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
6029{
6030 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6031 rtx mem;
6032
6033 if (Pmode == HImode)
6034 {
6035 mem = adjust_address (m_tramp, HImode, 0);
6036 emit_move_insn (mem, GEN_INT (0x7903));
6037 mem = adjust_address (m_tramp, Pmode, 2);
6038 emit_move_insn (mem, cxt);
6039 mem = adjust_address (m_tramp, HImode, 4);
6040 emit_move_insn (mem, GEN_INT (0x5a00));
6041 mem = adjust_address (m_tramp, Pmode, 6);
6042 emit_move_insn (mem, fnaddr);
6043 }
6044 else
6045 {
6046 rtx tem;
6047
6048 mem = adjust_address (m_tramp, HImode, 0);
6049 emit_move_insn (mem, GEN_INT (0x7a03));
6050 mem = adjust_address (m_tramp, Pmode, 2);
6051 emit_move_insn (mem, cxt);
6052
6053 tem = copy_to_reg (fnaddr);
6054 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff)));
6055 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000)));
6056 mem = adjust_address (m_tramp, SImode, 6);
6057 emit_move_insn (mem, tem);
6058 }
6059}
6060\f
6e014ef3
KH		 6061/* Initialize the GCC target structure. */
6062#undef TARGET_ATTRIBUTE_TABLE
6063#define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
6064
6065#undef TARGET_ASM_ALIGNED_HI_OP
6066#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
6067
1bc7c5b6
ZW		 6068#undef TARGET_ASM_FILE_START
6069#define TARGET_ASM_FILE_START h8300_file_start
6070#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
6071#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
6072
6e014ef3
KH		 6073#undef TARGET_ASM_FILE_END
6074#define TARGET_ASM_FILE_END h8300_file_end
6075
88cb339e
N		 6076#undef TARGET_PRINT_OPERAND
6077#define TARGET_PRINT_OPERAND h8300_print_operand
6078#undef TARGET_PRINT_OPERAND_ADDRESS
6079#define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
6080#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
6081#define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
6082
6e014ef3
KH		 6083#undef TARGET_ENCODE_SECTION_INFO
6084#define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
6085
6086#undef TARGET_INSERT_ATTRIBUTES
6087#define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
6088
88cb339e
N		 6089#undef TARGET_REGISTER_MOVE_COST
6090#define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
6091
6e014ef3
KH		 6092#undef TARGET_RTX_COSTS
6093#define TARGET_RTX_COSTS h8300_rtx_costs
6094
c15c90bb
ZW		 6095#undef TARGET_INIT_LIBFUNCS
6096#define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
6097
9eaa7740
AS		 6098#undef TARGET_FUNCTION_VALUE
6099#define TARGET_FUNCTION_VALUE h8300_function_value
6100
6101#undef TARGET_LIBCALL_VALUE
6102#define TARGET_LIBCALL_VALUE h8300_libcall_value
6103
6104#undef TARGET_FUNCTION_VALUE_REGNO_P
6105#define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
6106
34bf1fe3
KH		 6107#undef TARGET_RETURN_IN_MEMORY
6108#define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
6109
56f9413b
NF		 6110#undef TARGET_FUNCTION_ARG
6111#define TARGET_FUNCTION_ARG h8300_function_arg
6112
6113#undef TARGET_FUNCTION_ARG_ADVANCE
6114#define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
6115
beed8fc0
AO		 6116#undef TARGET_MACHINE_DEPENDENT_REORG
6117#define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
6118
2e762884
DD		 6119#undef TARGET_HARD_REGNO_SCRATCH_OK
6120#define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
6121
c6c3dba9
PB		 6122#undef TARGET_LEGITIMATE_ADDRESS_P
6123#define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
6124
7b5cbb57
AS		 6125#undef TARGET_CAN_ELIMINATE
6126#define TARGET_CAN_ELIMINATE h8300_can_eliminate
6127
5efd84c5
NF		 6128#undef TARGET_CONDITIONAL_REGISTER_USAGE
6129#define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
6130
9f6ef043
RH		 6131#undef TARGET_TRAMPOLINE_INIT
6132#define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6133
c5387660
JM		 6134#undef TARGET_OPTION_OVERRIDE
6135#define TARGET_OPTION_OVERRIDE h8300_option_override
6136
f52d97da
AS		 6137#undef TARGET_MODE_DEPENDENT_ADDRESS_P
6138#define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6139
6e014ef3 6140struct gcc_target targetm = TARGET_INITIALIZER;
Mirror of https://gcc.gnu.org/git/gcc.git