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340f6494 | 1 | /* Subroutines for insn-output.c for Renesas H8/300. |
aefc5826 | 2 | Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
9eaa7740 | 3 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 |
66647d44 | 4 | Free Software Foundation, Inc. |
48837e29 DE |
5 | Contributed by Steve Chamberlain (sac@cygnus.com), |
6 | Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). | |
07aae5c2 | 7 | |
8aa063fb | 8 | This file is part of GCC. |
07aae5c2 | 9 | |
8aa063fb | 10 | GCC is free software; you can redistribute it and/or modify |
07aae5c2 | 11 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 12 | the Free Software Foundation; either version 3, or (at your option) |
07aae5c2 SC |
13 | any later version. |
14 | ||
8aa063fb | 15 | GCC is distributed in the hope that it will be useful, |
07aae5c2 SC |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
21 | along with GCC; see the file COPYING3. If not see |
22 | <http://www.gnu.org/licenses/>. */ | |
07aae5c2 | 23 | |
07aae5c2 | 24 | #include "config.h" |
c5c76735 | 25 | #include "system.h" |
4977bab6 ZW |
26 | #include "coretypes.h" |
27 | #include "tm.h" | |
07aae5c2 | 28 | #include "rtl.h" |
bf6bb899 | 29 | #include "tree.h" |
07aae5c2 SC |
30 | #include "regs.h" |
31 | #include "hard-reg-set.h" | |
07aae5c2 SC |
32 | #include "insn-config.h" |
33 | #include "conditions.h" | |
07aae5c2 SC |
34 | #include "output.h" |
35 | #include "insn-attr.h" | |
36 | #include "flags.h" | |
37 | #include "recog.h" | |
38 | #include "expr.h" | |
bf6bb899 | 39 | #include "function.h" |
c15c90bb | 40 | #include "optabs.h" |
718f9c0f | 41 | #include "diagnostic-core.h" |
39dabefd | 42 | #include "c-family/c-pragma.h" /* ??? */ |
441d04c6 | 43 | #include "tm_p.h" |
ceaaaeab | 44 | #include "tm-constrs.h" |
f2a9645f | 45 | #include "ggc.h" |
672a6f42 NB |
46 | #include "target.h" |
47 | #include "target-def.h" | |
9690aa8e | 48 | #include "df.h" |
07aae5c2 | 49 | |
beed8fc0 AO |
50 | /* Classifies a h8300_src_operand or h8300_dst_operand. |
51 | ||
52 | H8OP_IMMEDIATE | |
53 | A constant operand of some sort. | |
54 | ||
55 | H8OP_REGISTER | |
56 | An ordinary register. | |
57 | ||
58 | H8OP_MEM_ABSOLUTE | |
59 | A memory reference with a constant address. | |
60 | ||
61 | H8OP_MEM_BASE | |
62 | A memory reference with a register as its address. | |
63 | ||
64 | H8OP_MEM_COMPLEX | |
65 | Some other kind of memory reference. */ | |
66 | enum h8300_operand_class | |
67 | { | |
68 | H8OP_IMMEDIATE, | |
69 | H8OP_REGISTER, | |
70 | H8OP_MEM_ABSOLUTE, | |
71 | H8OP_MEM_BASE, | |
72 | H8OP_MEM_COMPLEX, | |
73 | NUM_H8OPS | |
74 | }; | |
75 | ||
beed8fc0 AO |
76 | /* For a general two-operand instruction, element [X][Y] gives |
77 | the length of the opcode fields when the first operand has class | |
78 | (X + 1) and the second has class Y. */ | |
79 | typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS]; | |
80 | ||
07aae5c2 | 81 | /* Forward declarations. */ |
cb713a8d KH |
82 | static const char *byte_reg (rtx, int); |
83 | static int h8300_interrupt_function_p (tree); | |
3cfa3702 | 84 | static int h8300_saveall_function_p (tree); |
cb713a8d KH |
85 | static int h8300_monitor_function_p (tree); |
86 | static int h8300_os_task_function_p (tree); | |
c72ea086 | 87 | static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool); |
e68d4dd1 | 88 | static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT); |
cb713a8d KH |
89 | static unsigned int compute_saved_regs (void); |
90 | static void push (int); | |
91 | static void pop (int); | |
92 | static const char *cond_string (enum rtx_code); | |
93 | static unsigned int h8300_asm_insn_count (const char *); | |
cb713a8d KH |
94 | static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *); |
95 | static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *); | |
96 | static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *); | |
ede75ee8 | 97 | #ifndef OBJECT_FORMAT_ELF |
c18a5b6c | 98 | static void h8300_asm_named_section (const char *, unsigned int, tree); |
ede75ee8 | 99 | #endif |
cb713a8d KH |
100 | static int h8300_and_costs (rtx); |
101 | static int h8300_shift_costs (rtx); | |
ac447f25 | 102 | static void h8300_push_pop (int, int, bool, bool); |
beed8fc0 AO |
103 | static int h8300_stack_offset_p (rtx, int); |
104 | static int h8300_ldm_stm_regno (rtx, int, int, int); | |
beed8fc0 AO |
105 | static void h8300_reorg (void); |
106 | static unsigned int h8300_constant_length (rtx); | |
107 | static unsigned int h8300_displacement_length (rtx, int); | |
108 | static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *); | |
109 | static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *); | |
110 | static unsigned int h8300_unary_length (rtx); | |
111 | static unsigned int h8300_short_immediate_length (rtx); | |
112 | static unsigned int h8300_bitfield_length (rtx, rtx); | |
113 | static unsigned int h8300_binary_length (rtx, const h8300_length_table *); | |
114 | static bool h8300_short_move_mem_p (rtx, enum rtx_code); | |
115 | static unsigned int h8300_move_length (rtx *, const h8300_length_table *); | |
2e762884 | 116 | static bool h8300_hard_regno_scratch_ok (unsigned int); |
f52d97da | 117 | static rtx h8300_get_index (rtx, enum machine_mode mode, int *); |
f5b65a56 | 118 | |
48837e29 DE |
119 | /* CPU_TYPE, says what cpu we're compiling for. */ |
120 | int cpu_type; | |
121 | ||
e392d367 KH |
122 | /* True if a #pragma interrupt has been seen for the current function. */ |
123 | static int pragma_interrupt; | |
07aae5c2 SC |
124 | |
125 | /* True if a #pragma saveall has been seen for the current function. */ | |
0869f126 | 126 | static int pragma_saveall; |
07aae5c2 | 127 | |
441d04c6 | 128 | static const char *const names_big[] = |
07e4d94e | 129 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" }; |
48837e29 | 130 | |
441d04c6 | 131 | static const char *const names_extended[] = |
07e4d94e | 132 | { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" }; |
48837e29 | 133 | |
441d04c6 | 134 | static const char *const names_upper_extended[] = |
07e4d94e | 135 | { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" }; |
48837e29 DE |
136 | |
137 | /* Points to one of the above. */ | |
138 | /* ??? The above could be put in an array indexed by CPU_TYPE. */ | |
441d04c6 | 139 | const char * const *h8_reg_names; |
48837e29 DE |
140 | |
141 | /* Various operations needed by the following, indexed by CPU_TYPE. */ | |
48837e29 | 142 | |
441d04c6 | 143 | const char *h8_push_op, *h8_pop_op, *h8_mov_op; |
dc66a1c4 | 144 | |
beed8fc0 AO |
145 | /* Value of MOVE_RATIO. */ |
146 | int h8300_move_ratio; | |
672a6f42 | 147 | \f |
c4dfc70c DD |
148 | /* See below where shifts are handled for explanation of this enum. */ |
149 | ||
150 | enum shift_alg | |
151 | { | |
152 | SHIFT_INLINE, | |
153 | SHIFT_ROT_AND, | |
154 | SHIFT_SPECIAL, | |
155 | SHIFT_LOOP | |
156 | }; | |
157 | ||
158 | /* Symbols of the various shifts which can be used as indices. */ | |
159 | ||
160 | enum shift_type | |
161 | { | |
162 | SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT | |
163 | }; | |
164 | ||
165 | /* Macros to keep the shift algorithm tables small. */ | |
166 | #define INL SHIFT_INLINE | |
167 | #define ROT SHIFT_ROT_AND | |
168 | #define LOP SHIFT_LOOP | |
169 | #define SPC SHIFT_SPECIAL | |
170 | ||
171 | /* The shift algorithms for each machine, mode, shift type, and shift | |
172 | count are defined below. The three tables below correspond to | |
173 | QImode, HImode, and SImode, respectively. Each table is organized | |
f411c849 | 174 | by, in the order of indices, machine, shift type, and shift count. */ |
c4dfc70c DD |
175 | |
176 | static enum shift_alg shift_alg_qi[3][3][8] = { | |
177 | { | |
178 | /* TARGET_H8300 */ | |
179 | /* 0 1 2 3 4 5 6 7 */ | |
180 | { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ | |
181 | { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ | |
182 | { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */ | |
183 | }, | |
184 | { | |
185 | /* TARGET_H8300H */ | |
186 | /* 0 1 2 3 4 5 6 7 */ | |
187 | { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ | |
188 | { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ | |
189 | { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */ | |
190 | }, | |
191 | { | |
192 | /* TARGET_H8300S */ | |
193 | /* 0 1 2 3 4 5 6 7 */ | |
194 | { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */ | |
195 | { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */ | |
196 | { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */ | |
197 | } | |
198 | }; | |
199 | ||
200 | static enum shift_alg shift_alg_hi[3][3][16] = { | |
201 | { | |
202 | /* TARGET_H8300 */ | |
203 | /* 0 1 2 3 4 5 6 7 */ | |
204 | /* 8 9 10 11 12 13 14 15 */ | |
205 | { INL, INL, INL, INL, INL, INL, INL, SPC, | |
206 | SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */ | |
207 | { INL, INL, INL, INL, INL, LOP, LOP, SPC, | |
208 | SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */ | |
209 | { INL, INL, INL, INL, INL, LOP, LOP, SPC, | |
210 | SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ | |
211 | }, | |
212 | { | |
213 | /* TARGET_H8300H */ | |
214 | /* 0 1 2 3 4 5 6 7 */ | |
215 | /* 8 9 10 11 12 13 14 15 */ | |
216 | { INL, INL, INL, INL, INL, INL, INL, SPC, | |
217 | SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ | |
218 | { INL, INL, INL, INL, INL, INL, INL, SPC, | |
219 | SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ | |
220 | { INL, INL, INL, INL, INL, INL, INL, SPC, | |
221 | SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ | |
222 | }, | |
223 | { | |
224 | /* TARGET_H8300S */ | |
225 | /* 0 1 2 3 4 5 6 7 */ | |
226 | /* 8 9 10 11 12 13 14 15 */ | |
227 | { INL, INL, INL, INL, INL, INL, INL, INL, | |
228 | SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ | |
229 | { INL, INL, INL, INL, INL, INL, INL, INL, | |
230 | SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ | |
231 | { INL, INL, INL, INL, INL, INL, INL, INL, | |
232 | SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ | |
233 | } | |
234 | }; | |
235 | ||
236 | static enum shift_alg shift_alg_si[3][3][32] = { | |
237 | { | |
238 | /* TARGET_H8300 */ | |
239 | /* 0 1 2 3 4 5 6 7 */ | |
240 | /* 8 9 10 11 12 13 14 15 */ | |
241 | /* 16 17 18 19 20 21 22 23 */ | |
242 | /* 24 25 26 27 28 29 30 31 */ | |
243 | { INL, INL, INL, LOP, LOP, LOP, LOP, LOP, | |
244 | SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP, | |
245 | SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP, | |
246 | SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */ | |
247 | { INL, INL, INL, LOP, LOP, LOP, LOP, LOP, | |
248 | SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC, | |
249 | SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP, | |
250 | SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */ | |
251 | { INL, INL, INL, LOP, LOP, LOP, LOP, LOP, | |
252 | SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, | |
253 | SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP, | |
254 | SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */ | |
255 | }, | |
256 | { | |
257 | /* TARGET_H8300H */ | |
258 | /* 0 1 2 3 4 5 6 7 */ | |
259 | /* 8 9 10 11 12 13 14 15 */ | |
260 | /* 16 17 18 19 20 21 22 23 */ | |
261 | /* 24 25 26 27 28 29 30 31 */ | |
262 | { INL, INL, INL, INL, INL, LOP, LOP, LOP, | |
263 | SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, | |
264 | SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP, | |
1e5bdc40 | 265 | SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */ |
c4dfc70c DD |
266 | { INL, INL, INL, INL, INL, LOP, LOP, LOP, |
267 | SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, | |
268 | SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP, | |
1e5bdc40 | 269 | SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */ |
c4dfc70c DD |
270 | { INL, INL, INL, INL, INL, LOP, LOP, LOP, |
271 | SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP, | |
272 | SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP, | |
273 | SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */ | |
274 | }, | |
275 | { | |
276 | /* TARGET_H8300S */ | |
277 | /* 0 1 2 3 4 5 6 7 */ | |
278 | /* 8 9 10 11 12 13 14 15 */ | |
279 | /* 16 17 18 19 20 21 22 23 */ | |
280 | /* 24 25 26 27 28 29 30 31 */ | |
281 | { INL, INL, INL, INL, INL, INL, INL, INL, | |
282 | INL, INL, INL, LOP, LOP, LOP, LOP, SPC, | |
283 | SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP, | |
1e5bdc40 | 284 | SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */ |
c4dfc70c DD |
285 | { INL, INL, INL, INL, INL, INL, INL, INL, |
286 | INL, INL, INL, LOP, LOP, LOP, LOP, SPC, | |
287 | SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP, | |
1e5bdc40 | 288 | SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */ |
c4dfc70c DD |
289 | { INL, INL, INL, INL, INL, INL, INL, INL, |
290 | INL, INL, INL, LOP, LOP, LOP, LOP, LOP, | |
291 | SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP, | |
292 | SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */ | |
293 | } | |
294 | }; | |
295 | ||
296 | #undef INL | |
297 | #undef ROT | |
298 | #undef LOP | |
299 | #undef SPC | |
300 | ||
301 | enum h8_cpu | |
302 | { | |
303 | H8_300, | |
304 | H8_300H, | |
305 | H8_S | |
306 | }; | |
307 | ||
3020190e | 308 | /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ |
fac0f722 | 309 | |
3020190e JM |
310 | static const struct default_options h8300_option_optimization_table[] = |
311 | { | |
312 | /* Basic block reordering is only beneficial on targets with cache | |
313 | and/or variable-cycle branches where (cycle count taken != | |
314 | cycle count not taken). */ | |
315 | { OPT_LEVELS_ALL, OPT_freorder_blocks, NULL, 0 }, | |
316 | { OPT_LEVELS_NONE, 0, NULL, 0 } | |
317 | }; | |
fac0f722 | 318 | |
48837e29 DE |
319 | /* Initialize various cpu specific globals at start up. */ |
320 | ||
c5387660 JM |
321 | static void |
322 | h8300_option_override (void) | |
48837e29 | 323 | { |
cbf1b2da KH |
324 | static const char *const h8_push_ops[2] = { "push" , "push.l" }; |
325 | static const char *const h8_pop_ops[2] = { "pop" , "pop.l" }; | |
326 | static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" }; | |
327 | ||
48837e29 DE |
328 | if (TARGET_H8300) |
329 | { | |
330 | cpu_type = (int) CPU_H8300; | |
331 | h8_reg_names = names_big; | |
332 | } | |
333 | else | |
334 | { | |
3db11b5c | 335 | /* For this we treat the H8/300H and H8S the same. */ |
48837e29 DE |
336 | cpu_type = (int) CPU_H8300H; |
337 | h8_reg_names = names_extended; | |
338 | } | |
339 | h8_push_op = h8_push_ops[cpu_type]; | |
340 | h8_pop_op = h8_pop_ops[cpu_type]; | |
341 | h8_mov_op = h8_mov_ops[cpu_type]; | |
17f0f8fa KH |
342 | |
343 | if (!TARGET_H8300S && TARGET_MAC) | |
400500c4 | 344 | { |
c725bd79 | 345 | error ("-ms2600 is used without -ms"); |
5463c726 | 346 | target_flags |= MASK_H8300S_1; |
400500c4 | 347 | } |
920e86b8 | 348 | |
39ba95b5 VK |
349 | if (TARGET_H8300 && TARGET_NORMAL_MODE) |
350 | { | |
92d4b8a0 | 351 | error ("-mn is used without -mh or -ms"); |
39ba95b5 VK |
352 | target_flags ^= MASK_NORMAL_MODE; |
353 | } | |
c4dfc70c | 354 | |
8bd06267 | 355 | /* Some of the shifts are optimized for speed by default. |
c4dfc70c | 356 | See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html |
8bd06267 | 357 | If optimizing for size, change shift_alg for those shift to |
c4dfc70c | 358 | SHIFT_LOOP. */ |
b6894857 | 359 | if (optimize_size) |
c4dfc70c | 360 | { |
b6894857 KH |
361 | /* H8/300 */ |
362 | shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP; | |
363 | shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP; | |
364 | shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP; | |
365 | shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP; | |
c4dfc70c | 366 | |
b6894857 KH |
367 | shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP; |
368 | shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP; | |
c4dfc70c | 369 | |
b6894857 KH |
370 | shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP; |
371 | shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; | |
c4dfc70c | 372 | |
b6894857 KH |
373 | /* H8/300H */ |
374 | shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP; | |
375 | shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP; | |
c4dfc70c | 376 | |
b6894857 KH |
377 | shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP; |
378 | shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP; | |
c4dfc70c | 379 | |
b6894857 KH |
380 | shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP; |
381 | shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP; | |
382 | shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP; | |
383 | shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; | |
c4dfc70c DD |
384 | |
385 | /* H8S */ | |
b6894857 | 386 | shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; |
c4dfc70c | 387 | } |
beed8fc0 AO |
388 | |
389 | /* Work out a value for MOVE_RATIO. */ | |
390 | if (!TARGET_H8300SX) | |
391 | { | |
392 | /* Memory-memory moves are quite expensive without the | |
393 | h8sx instructions. */ | |
394 | h8300_move_ratio = 3; | |
395 | } | |
396 | else if (flag_omit_frame_pointer) | |
397 | { | |
398 | /* movmd sequences are fairly cheap when er6 isn't fixed. They can | |
399 | sometimes be as short as two individual memory-to-memory moves, | |
400 | but since they use all the call-saved registers, it seems better | |
401 | to allow up to three moves here. */ | |
402 | h8300_move_ratio = 4; | |
403 | } | |
404 | else if (optimize_size) | |
405 | { | |
406 | /* In this case we don't use movmd sequences since they tend | |
407 | to be longer than calls to memcpy(). Memory-to-memory | |
408 | moves are cheaper than for !TARGET_H8300SX, so it makes | |
409 | sense to have a slightly higher threshold. */ | |
410 | h8300_move_ratio = 4; | |
411 | } | |
412 | else | |
413 | { | |
414 | /* We use movmd sequences for some moves since it can be quicker | |
415 | than calling memcpy(). The sequences will need to save and | |
416 | restore er6 though, so bump up the cost. */ | |
417 | h8300_move_ratio = 6; | |
418 | } | |
0685e770 DD |
419 | |
420 | /* This target defaults to strict volatile bitfields. */ | |
421 | if (flag_strict_volatile_bitfields < 0) | |
422 | flag_strict_volatile_bitfields = 1; | |
beed8fc0 AO |
423 | } |
424 | ||
e9eba255 KH |
425 | /* Return the byte register name for a register rtx X. B should be 0 |
426 | if you want a lower byte register. B should be 1 if you want an | |
427 | upper byte register. */ | |
428 | ||
9c188705 | 429 | static const char * |
cb713a8d | 430 | byte_reg (rtx x, int b) |
07aae5c2 | 431 | { |
9cbcd983 KH |
432 | static const char *const names_small[] = { |
433 | "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h", | |
434 | "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h" | |
435 | }; | |
07aae5c2 | 436 | |
8c440872 | 437 | gcc_assert (REG_P (x)); |
500fc80f | 438 | |
07aae5c2 SC |
439 | return names_small[REGNO (x) * 2 + b]; |
440 | } | |
441 | ||
442 | /* REGNO must be saved/restored across calls if this macro is true. */ | |
48837e29 | 443 | |
9cbcd983 | 444 | #define WORD_REG_USED(regno) \ |
d60004ee | 445 | (regno < SP_REG \ |
9cbcd983 KH |
446 | /* No need to save registers if this function will not return. */ \ |
447 | && ! TREE_THIS_VOLATILE (current_function_decl) \ | |
3cfa3702 | 448 | && (h8300_saveall_function_p (current_function_decl) \ |
9cbcd983 | 449 | /* Save any call saved register that was used. */ \ |
6fb5fa3c | 450 | || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \ |
9cbcd983 | 451 | /* Save the frame pointer if it was used. */ \ |
6fb5fa3c | 452 | || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \ |
9cbcd983 | 453 | /* Save any register used in an interrupt handler. */ \ |
e392d367 | 454 | || (h8300_current_function_interrupt_function_p () \ |
6fb5fa3c | 455 | && df_regs_ever_live_p (regno)) \ |
9cbcd983 KH |
456 | /* Save call clobbered registers in non-leaf interrupt \ |
457 | handlers. */ \ | |
e392d367 | 458 | || (h8300_current_function_interrupt_function_p () \ |
9cbcd983 | 459 | && call_used_regs[regno] \ |
fc80ea73 | 460 | && !current_function_is_leaf))) |
07aae5c2 | 461 | |
18674659 DD |
462 | /* We use this to wrap all emitted insns in the prologue. */ |
463 | static rtx | |
c72ea086 | 464 | F (rtx x, bool set_it) |
18674659 | 465 | { |
c72ea086 DD |
466 | if (set_it) |
467 | RTX_FRAME_RELATED_P (x) = 1; | |
18674659 DD |
468 | return x; |
469 | } | |
470 | ||
471 | /* Mark all the subexpressions of the PARALLEL rtx PAR as | |
472 | frame-related. Return PAR. | |
473 | ||
474 | dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a | |
475 | PARALLEL rtx other than the first if they do not have the | |
476 | FRAME_RELATED flag set on them. */ | |
477 | static rtx | |
478 | Fpa (rtx par) | |
479 | { | |
480 | int len = XVECLEN (par, 0); | |
481 | int i; | |
482 | ||
483 | for (i = 0; i < len; i++) | |
c72ea086 | 484 | F (XVECEXP (par, 0, i), true); |
18674659 DD |
485 | |
486 | return par; | |
487 | } | |
488 | ||
07aae5c2 | 489 | /* Output assembly language to FILE for the operation OP with operand size |
48837e29 | 490 | SIZE to adjust the stack pointer. */ |
48837e29 | 491 | |
07aae5c2 | 492 | static void |
c72ea086 | 493 | h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue) |
07aae5c2 | 494 | { |
72b1de44 KH |
495 | /* If the frame size is 0, we don't have anything to do. */ |
496 | if (size == 0) | |
f8b58e56 | 497 | return; |
72b1de44 | 498 | |
68ee6df6 KH |
499 | /* H8/300 cannot add/subtract a large constant with a single |
500 | instruction. If a temporary register is available, load the | |
501 | constant to it and then do the addition. */ | |
502 | if (TARGET_H8300 | |
503 | && size > 4 | |
504 | && !h8300_current_function_interrupt_function_p () | |
6de9cd9a | 505 | && !(cfun->static_chain_decl != NULL && sign < 0)) |
f8f26adc | 506 | { |
68ee6df6 | 507 | rtx r3 = gen_rtx_REG (Pmode, 3); |
c72ea086 | 508 | F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue); |
18674659 | 509 | F (emit_insn (gen_addhi3 (stack_pointer_rtx, |
c72ea086 | 510 | stack_pointer_rtx, r3)), in_prologue); |
7b3d4613 KH |
511 | } |
512 | else | |
513 | { | |
68ee6df6 KH |
514 | /* The stack adjustment made here is further optimized by the |
515 | splitter. In case of H8/300, the splitter always splits the | |
18674659 DD |
516 | addition emitted here to make the adjustment interrupt-safe. |
517 | FIXME: We don't always tag those, because we don't know what | |
518 | the splitter will do. */ | |
72b1de44 | 519 | if (Pmode == HImode) |
18674659 DD |
520 | { |
521 | rtx x = emit_insn (gen_addhi3 (stack_pointer_rtx, | |
522 | stack_pointer_rtx, GEN_INT (sign * size))); | |
523 | if (size < 4) | |
c72ea086 | 524 | F (x, in_prologue); |
18674659 | 525 | } |
72b1de44 | 526 | else |
18674659 | 527 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
c72ea086 | 528 | stack_pointer_rtx, GEN_INT (sign * size))), in_prologue); |
07aae5c2 SC |
529 | } |
530 | } | |
531 | ||
8682223f KH |
532 | /* Round up frame size SIZE. */ |
533 | ||
e68d4dd1 UB |
534 | static HOST_WIDE_INT |
535 | round_frame_size (HOST_WIDE_INT size) | |
8682223f | 536 | { |
489eda65 KH |
537 | return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1) |
538 | & -STACK_BOUNDARY / BITS_PER_UNIT); | |
8682223f KH |
539 | } |
540 | ||
541 | /* Compute which registers to push/pop. | |
542 | Return a bit vector of registers. */ | |
543 | ||
544 | static unsigned int | |
cb713a8d | 545 | compute_saved_regs (void) |
8682223f KH |
546 | { |
547 | unsigned int saved_regs = 0; | |
548 | int regno; | |
549 | ||
550 | /* Construct a bit vector of registers to be pushed/popped. */ | |
1807b726 | 551 | for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++) |
8682223f KH |
552 | { |
553 | if (WORD_REG_USED (regno)) | |
554 | saved_regs |= 1 << regno; | |
555 | } | |
556 | ||
557 | /* Don't push/pop the frame pointer as it is treated separately. */ | |
558 | if (frame_pointer_needed) | |
1807b726 | 559 | saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM); |
8682223f KH |
560 | |
561 | return saved_regs; | |
562 | } | |
563 | ||
68ee6df6 | 564 | /* Emit an insn to push register RN. */ |
8682223f KH |
565 | |
566 | static void | |
cb713a8d | 567 | push (int rn) |
8682223f | 568 | { |
68ee6df6 KH |
569 | rtx reg = gen_rtx_REG (word_mode, rn); |
570 | rtx x; | |
571 | ||
513f31eb | 572 | if (TARGET_H8300) |
68ee6df6 | 573 | x = gen_push_h8300 (reg); |
f24f0897 | 574 | else if (!TARGET_NORMAL_MODE) |
32da7865 | 575 | x = gen_push_h8300hs_advanced (reg); |
f24f0897 KH |
576 | else |
577 | x = gen_push_h8300hs_normal (reg); | |
ac447f25 | 578 | x = F (emit_insn (x), true); |
9690aa8e | 579 | add_reg_note (x, REG_INC, stack_pointer_rtx); |
8682223f KH |
580 | } |
581 | ||
68ee6df6 | 582 | /* Emit an insn to pop register RN. */ |
8682223f KH |
583 | |
584 | static void | |
cb713a8d | 585 | pop (int rn) |
8682223f | 586 | { |
68ee6df6 KH |
587 | rtx reg = gen_rtx_REG (word_mode, rn); |
588 | rtx x; | |
589 | ||
513f31eb | 590 | if (TARGET_H8300) |
68ee6df6 | 591 | x = gen_pop_h8300 (reg); |
f24f0897 | 592 | else if (!TARGET_NORMAL_MODE) |
32da7865 | 593 | x = gen_pop_h8300hs_advanced (reg); |
f24f0897 KH |
594 | else |
595 | x = gen_pop_h8300hs_normal (reg); | |
68ee6df6 | 596 | x = emit_insn (x); |
9690aa8e | 597 | add_reg_note (x, REG_INC, stack_pointer_rtx); |
8682223f | 598 | } |
07aae5c2 | 599 | |
beed8fc0 AO |
600 | /* Emit an instruction to push or pop NREGS consecutive registers |
601 | starting at register REGNO. POP_P selects a pop rather than a | |
602 | push and RETURN_P is true if the instruction should return. | |
603 | ||
604 | It must be possible to do the requested operation in a single | |
605 | instruction. If NREGS == 1 && !RETURN_P, use a normal push | |
606 | or pop insn. Otherwise emit a parallel of the form: | |
607 | ||
608 | (parallel | |
609 | [(return) ;; if RETURN_P | |
610 | (save or restore REGNO) | |
611 | (save or restore REGNO + 1) | |
612 | ... | |
613 | (save or restore REGNO + NREGS - 1) | |
614 | (set sp (plus sp (const_int adjust)))] */ | |
615 | ||
616 | static void | |
ac447f25 | 617 | h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p) |
beed8fc0 AO |
618 | { |
619 | int i, j; | |
620 | rtvec vec; | |
18674659 | 621 | rtx sp, offset, x; |
beed8fc0 AO |
622 | |
623 | /* See whether we can use a simple push or pop. */ | |
624 | if (!return_p && nregs == 1) | |
625 | { | |
626 | if (pop_p) | |
627 | pop (regno); | |
628 | else | |
629 | push (regno); | |
630 | return; | |
631 | } | |
632 | ||
633 | /* We need one element for the return insn, if present, one for each | |
634 | register, and one for stack adjustment. */ | |
ac447f25 | 635 | vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1); |
beed8fc0 AO |
636 | sp = stack_pointer_rtx; |
637 | i = 0; | |
638 | ||
639 | /* Add the return instruction. */ | |
640 | if (return_p) | |
641 | { | |
642 | RTVEC_ELT (vec, i) = gen_rtx_RETURN (VOIDmode); | |
643 | i++; | |
644 | } | |
645 | ||
646 | /* Add the register moves. */ | |
647 | for (j = 0; j < nregs; j++) | |
648 | { | |
649 | rtx lhs, rhs; | |
650 | ||
651 | if (pop_p) | |
652 | { | |
653 | /* Register REGNO + NREGS - 1 is popped first. Before the | |
654 | stack adjustment, its slot is at address @sp. */ | |
655 | lhs = gen_rtx_REG (SImode, regno + j); | |
656 | rhs = gen_rtx_MEM (SImode, plus_constant (sp, (nregs - j - 1) * 4)); | |
657 | } | |
658 | else | |
659 | { | |
660 | /* Register REGNO is pushed first and will be stored at @(-4,sp). */ | |
661 | lhs = gen_rtx_MEM (SImode, plus_constant (sp, (j + 1) * -4)); | |
662 | rhs = gen_rtx_REG (SImode, regno + j); | |
663 | } | |
664 | RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, lhs, rhs); | |
665 | } | |
666 | ||
667 | /* Add the stack adjustment. */ | |
668 | offset = GEN_INT ((pop_p ? nregs : -nregs) * 4); | |
669 | RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, sp, | |
670 | gen_rtx_PLUS (Pmode, sp, offset)); | |
671 | ||
18674659 DD |
672 | x = gen_rtx_PARALLEL (VOIDmode, vec); |
673 | if (!pop_p) | |
674 | x = Fpa (x); | |
ac447f25 NC |
675 | |
676 | if (return_p) | |
677 | emit_jump_insn (x); | |
678 | else | |
679 | emit_insn (x); | |
beed8fc0 AO |
680 | } |
681 | ||
682 | /* Return true if X has the value sp + OFFSET. */ | |
683 | ||
684 | static int | |
685 | h8300_stack_offset_p (rtx x, int offset) | |
686 | { | |
687 | if (offset == 0) | |
688 | return x == stack_pointer_rtx; | |
689 | ||
690 | return (GET_CODE (x) == PLUS | |
691 | && XEXP (x, 0) == stack_pointer_rtx | |
692 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
693 | && INTVAL (XEXP (x, 1)) == offset); | |
694 | } | |
695 | ||
696 | /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in | |
697 | something that may be an ldm or stm instruction. If it fits | |
698 | the required template, return the register it loads or stores, | |
699 | otherwise return -1. | |
700 | ||
701 | LOAD_P is true if X should be a load, false if it should be a store. | |
702 | NREGS is the number of registers that the whole instruction is expected | |
703 | to load or store. INDEX is the index of the register that X should | |
704 | load or store, relative to the lowest-numbered register. */ | |
705 | ||
706 | static int | |
707 | h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs) | |
708 | { | |
709 | int regindex, memindex, offset; | |
710 | ||
711 | if (load_p) | |
712 | regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4; | |
713 | else | |
714 | memindex = 0, regindex = 1, offset = (index + 1) * -4; | |
715 | ||
716 | if (GET_CODE (x) == SET | |
717 | && GET_CODE (XEXP (x, regindex)) == REG | |
718 | && GET_CODE (XEXP (x, memindex)) == MEM | |
719 | && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset)) | |
720 | return REGNO (XEXP (x, regindex)); | |
721 | ||
722 | return -1; | |
723 | } | |
724 | ||
725 | /* Return true if the elements of VEC starting at FIRST describe an | |
726 | ldm or stm instruction (LOAD_P says which). */ | |
727 | ||
981c7dce | 728 | int |
beed8fc0 AO |
729 | h8300_ldm_stm_parallel (rtvec vec, int load_p, int first) |
730 | { | |
731 | rtx last; | |
732 | int nregs, i, regno, adjust; | |
733 | ||
734 | /* There must be a stack adjustment, a register move, and at least one | |
735 | other operation (a return or another register move). */ | |
736 | if (GET_NUM_ELEM (vec) < 3) | |
737 | return false; | |
738 | ||
739 | /* Get the range of registers to be pushed or popped. */ | |
740 | nregs = GET_NUM_ELEM (vec) - first - 1; | |
741 | regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs); | |
742 | ||
743 | /* Check that the call to h8300_ldm_stm_regno succeeded and | |
744 | that we're only dealing with GPRs. */ | |
745 | if (regno < 0 || regno + nregs > 8) | |
746 | return false; | |
747 | ||
748 | /* 2-register h8s instructions must start with an even-numbered register. | |
749 | 3- and 4-register instructions must start with er0 or er4. */ | |
750 | if (!TARGET_H8300SX) | |
751 | { | |
752 | if ((regno & 1) != 0) | |
753 | return false; | |
754 | if (nregs > 2 && (regno & 3) != 0) | |
755 | return false; | |
756 | } | |
757 | ||
758 | /* Check the other loads or stores. */ | |
759 | for (i = 1; i < nregs; i++) | |
760 | if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs) | |
761 | != regno + i) | |
762 | return false; | |
763 | ||
764 | /* Check the stack adjustment. */ | |
765 | last = RTVEC_ELT (vec, first + nregs); | |
766 | adjust = (load_p ? nregs : -nregs) * 4; | |
767 | return (GET_CODE (last) == SET | |
768 | && SET_DEST (last) == stack_pointer_rtx | |
769 | && h8300_stack_offset_p (SET_SRC (last), adjust)); | |
770 | } | |
771 | ||
f0b6f9a6 | 772 | /* This is what the stack looks like after the prolog of |
07aae5c2 SC |
773 | a function with a frame has been set up: |
774 | ||
48837e29 DE |
775 | <args> |
776 | PC | |
777 | FP <- fp | |
778 | <locals> | |
8bd06267 | 779 | <saved registers> <- sp |
07aae5c2 SC |
780 | |
781 | This is what the stack looks like after the prolog of | |
782 | a function which doesn't have a frame: | |
783 | ||
48837e29 DE |
784 | <args> |
785 | PC | |
786 | <locals> | |
8bd06267 | 787 | <saved registers> <- sp |
07aae5c2 SC |
788 | */ |
789 | ||
68ee6df6 | 790 | /* Generate RTL code for the function prologue. */ |
8682223f | 791 | |
68ee6df6 | 792 | void |
cb713a8d | 793 | h8300_expand_prologue (void) |
07aae5c2 | 794 | { |
e651d484 | 795 | int regno; |
8682223f | 796 | int saved_regs; |
cda4bd43 | 797 | int n_regs; |
07aae5c2 | 798 | |
fabe72bb JL |
799 | /* If the current function has the OS_Task attribute set, then |
800 | we have a naked prologue. */ | |
801 | if (h8300_os_task_function_p (current_function_decl)) | |
68ee6df6 | 802 | return; |
fabe72bb JL |
803 | |
804 | if (h8300_monitor_function_p (current_function_decl)) | |
68ee6df6 KH |
805 | /* My understanding of monitor functions is they act just like |
806 | interrupt functions, except the prologue must mask | |
807 | interrupts. */ | |
808 | emit_insn (gen_monitor_prologue ()); | |
fabe72bb | 809 | |
48837e29 DE |
810 | if (frame_pointer_needed) |
811 | { | |
07e4d94e | 812 | /* Push fp. */ |
1807b726 | 813 | push (HARD_FRAME_POINTER_REGNUM); |
ac447f25 | 814 | F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true); |
a1616dd9 | 815 | } |
48837e29 | 816 | |
8682223f KH |
817 | /* Push the rest of the registers in ascending order. */ |
818 | saved_regs = compute_saved_regs (); | |
e651d484 | 819 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs) |
cda4bd43 | 820 | { |
cda4bd43 | 821 | n_regs = 1; |
8682223f | 822 | if (saved_regs & (1 << regno)) |
a1616dd9 JL |
823 | { |
824 | if (TARGET_H8300S) | |
825 | { | |
cda4bd43 | 826 | /* See how many registers we can push at the same time. */ |
beed8fc0 | 827 | if ((!TARGET_H8300SX || (regno & 3) == 0) |
8682223f | 828 | && ((saved_regs >> regno) & 0x0f) == 0x0f) |
cda4bd43 KH |
829 | n_regs = 4; |
830 | ||
beed8fc0 | 831 | else if ((!TARGET_H8300SX || (regno & 3) == 0) |
8682223f | 832 | && ((saved_regs >> regno) & 0x07) == 0x07) |
cda4bd43 KH |
833 | n_regs = 3; |
834 | ||
beed8fc0 | 835 | else if ((!TARGET_H8300SX || (regno & 1) == 0) |
8682223f | 836 | && ((saved_regs >> regno) & 0x03) == 0x03) |
cda4bd43 | 837 | n_regs = 2; |
a1616dd9 | 838 | } |
cda4bd43 | 839 | |
ac447f25 | 840 | h8300_push_pop (regno, n_regs, false, false); |
07aae5c2 SC |
841 | } |
842 | } | |
1807b726 KH |
843 | |
844 | /* Leave room for locals. */ | |
c72ea086 | 845 | h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true); |
07aae5c2 SC |
846 | } |
847 | ||
e9eba255 KH |
848 | /* Return nonzero if we can use "rts" for the function currently being |
849 | compiled. */ | |
850 | ||
68ee6df6 | 851 | int |
cb713a8d | 852 | h8300_can_use_return_insn_p (void) |
68ee6df6 KH |
853 | { |
854 | return (reload_completed | |
855 | && !frame_pointer_needed | |
856 | && get_frame_size () == 0 | |
857 | && compute_saved_regs () == 0); | |
858 | } | |
07aae5c2 | 859 | |
68ee6df6 KH |
860 | /* Generate RTL code for the function epilogue. */ |
861 | ||
862 | void | |
cb713a8d | 863 | h8300_expand_epilogue (void) |
07aae5c2 | 864 | { |
e651d484 | 865 | int regno; |
8682223f | 866 | int saved_regs; |
cda4bd43 | 867 | int n_regs; |
beed8fc0 AO |
868 | HOST_WIDE_INT frame_size; |
869 | bool returned_p; | |
07aae5c2 | 870 | |
e392d367 | 871 | if (h8300_os_task_function_p (current_function_decl)) |
68ee6df6 KH |
872 | /* OS_Task epilogues are nearly naked -- they just have an |
873 | rts instruction. */ | |
874 | return; | |
07aae5c2 | 875 | |
beed8fc0 AO |
876 | frame_size = round_frame_size (get_frame_size ()); |
877 | returned_p = false; | |
878 | ||
1807b726 | 879 | /* Deallocate locals. */ |
c72ea086 | 880 | h8300_emit_stack_adjustment (1, frame_size, false); |
1807b726 | 881 | |
8682223f KH |
882 | /* Pop the saved registers in descending order. */ |
883 | saved_regs = compute_saved_regs (); | |
e651d484 | 884 | for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs) |
cda4bd43 | 885 | { |
cda4bd43 | 886 | n_regs = 1; |
8682223f | 887 | if (saved_regs & (1 << regno)) |
07aae5c2 | 888 | { |
a1616dd9 JL |
889 | if (TARGET_H8300S) |
890 | { | |
cda4bd43 | 891 | /* See how many registers we can pop at the same time. */ |
beed8fc0 AO |
892 | if ((TARGET_H8300SX || (regno & 3) == 3) |
893 | && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f) | |
cda4bd43 KH |
894 | n_regs = 4; |
895 | ||
beed8fc0 AO |
896 | else if ((TARGET_H8300SX || (regno & 3) == 2) |
897 | && ((saved_regs << 2 >> regno) & 0x07) == 0x07) | |
cda4bd43 KH |
898 | n_regs = 3; |
899 | ||
beed8fc0 AO |
900 | else if ((TARGET_H8300SX || (regno & 1) == 1) |
901 | && ((saved_regs << 1 >> regno) & 0x03) == 0x03) | |
cda4bd43 | 902 | n_regs = 2; |
a1616dd9 | 903 | } |
cda4bd43 | 904 | |
beed8fc0 AO |
905 | /* See if this pop would be the last insn before the return. |
906 | If so, use rte/l or rts/l instead of pop or ldm.l. */ | |
907 | if (TARGET_H8300SX | |
908 | && !frame_pointer_needed | |
909 | && frame_size == 0 | |
910 | && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0) | |
911 | returned_p = true; | |
912 | ||
ac447f25 | 913 | h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p); |
07aae5c2 | 914 | } |
07aae5c2 | 915 | } |
48837e29 | 916 | |
07e4d94e | 917 | /* Pop frame pointer if we had one. */ |
a1616dd9 | 918 | if (frame_pointer_needed) |
beed8fc0 AO |
919 | { |
920 | if (TARGET_H8300SX) | |
921 | returned_p = true; | |
ac447f25 | 922 | h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p); |
beed8fc0 AO |
923 | } |
924 | ||
925 | if (!returned_p) | |
6d4a8967 | 926 | emit_jump_insn (gen_rtx_RETURN (VOIDmode)); |
68ee6df6 | 927 | } |
a1616dd9 | 928 | |
e392d367 KH |
929 | /* Return nonzero if the current function is an interrupt |
930 | function. */ | |
931 | ||
932 | int | |
cb713a8d | 933 | h8300_current_function_interrupt_function_p (void) |
e392d367 KH |
934 | { |
935 | return (h8300_interrupt_function_p (current_function_decl) | |
936 | || h8300_monitor_function_p (current_function_decl)); | |
937 | } | |
938 | ||
48837e29 DE |
939 | /* Output assembly code for the start of the file. */ |
940 | ||
1bc7c5b6 ZW |
941 | static void |
942 | h8300_file_start (void) | |
48837e29 | 943 | { |
1bc7c5b6 | 944 | default_file_start (); |
8bd06267 | 945 | |
48837e29 | 946 | if (TARGET_H8300H) |
1bc7c5b6 | 947 | fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file); |
beed8fc0 AO |
948 | else if (TARGET_H8300SX) |
949 | fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file); | |
a1616dd9 | 950 | else if (TARGET_H8300S) |
1bc7c5b6 | 951 | fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file); |
48837e29 DE |
952 | } |
953 | ||
954 | /* Output assembly language code for the end of file. */ | |
955 | ||
a5fe455b | 956 | static void |
cb713a8d | 957 | h8300_file_end (void) |
48837e29 | 958 | { |
a5fe455b | 959 | fputs ("\t.end\n", asm_out_file); |
07aae5c2 SC |
960 | } |
961 | \f | |
3cee1a78 KH |
962 | /* Split an add of a small constant into two adds/subs insns. |
963 | ||
964 | If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec | |
965 | instead of adds/subs. */ | |
009ac3d3 RH |
966 | |
967 | void | |
cb713a8d | 968 | split_adds_subs (enum machine_mode mode, rtx *operands) |
3b7d443c | 969 | { |
009ac3d3 RH |
970 | HOST_WIDE_INT val = INTVAL (operands[1]); |
971 | rtx reg = operands[0]; | |
9492393e KH |
972 | HOST_WIDE_INT sign = 1; |
973 | HOST_WIDE_INT amount; | |
590734b6 | 974 | rtx (*gen_add) (rtx, rtx, rtx); |
3b7d443c | 975 | |
9492393e KH |
976 | /* Force VAL to be positive so that we do not have to consider the |
977 | sign. */ | |
978 | if (val < 0) | |
3b7d443c | 979 | { |
9492393e KH |
980 | val = -val; |
981 | sign = -1; | |
982 | } | |
3b7d443c | 983 | |
3cee1a78 KH |
984 | switch (mode) |
985 | { | |
986 | case HImode: | |
590734b6 | 987 | gen_add = gen_addhi3; |
3cee1a78 KH |
988 | break; |
989 | ||
990 | case SImode: | |
590734b6 | 991 | gen_add = gen_addsi3; |
3cee1a78 KH |
992 | break; |
993 | ||
994 | default: | |
8c440872 | 995 | gcc_unreachable (); |
3cee1a78 KH |
996 | } |
997 | ||
9492393e KH |
998 | /* Try different amounts in descending order. */ |
999 | for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2; | |
1000 | amount > 0; | |
1001 | amount /= 2) | |
1002 | { | |
1a63219b | 1003 | for (; val >= amount; val -= amount) |
590734b6 | 1004 | emit_insn (gen_add (reg, reg, GEN_INT (sign * amount))); |
3b7d443c JL |
1005 | } |
1006 | ||
9492393e | 1007 | return; |
3b7d443c JL |
1008 | } |
1009 | ||
07aae5c2 | 1010 | /* Handle machine specific pragmas for compatibility with existing |
48837e29 | 1011 | compilers for the H8/300. |
07aae5c2 | 1012 | |
f411c849 | 1013 | pragma saveall generates prologue/epilogue code which saves and |
07aae5c2 | 1014 | restores all the registers on function entry. |
48837e29 | 1015 | |
07aae5c2 SC |
1016 | pragma interrupt saves and restores all registers, and exits with |
1017 | an rte instruction rather than an rts. A pointer to a function | |
1018 | with this attribute may be safely used in an interrupt vector. */ | |
48837e29 | 1019 | |
8b97c5f8 | 1020 | void |
cb713a8d | 1021 | h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED) |
07aae5c2 | 1022 | { |
e392d367 | 1023 | pragma_interrupt = 1; |
8b97c5f8 | 1024 | } |
05a81fe5 | 1025 | |
8b97c5f8 | 1026 | void |
cb713a8d | 1027 | h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED) |
8b97c5f8 ZW |
1028 | { |
1029 | pragma_saveall = 1; | |
07aae5c2 | 1030 | } |
8b97c5f8 | 1031 | |
64bead4c KH |
1032 | /* If the next function argument with MODE and TYPE is to be passed in |
1033 | a register, return a reg RTX for the hard register in which to pass | |
1034 | the argument. CUM represents the state after the last argument. | |
56f9413b | 1035 | If the argument is to be pushed, NULL_RTX is returned. |
48837e29 | 1036 | |
56f9413b NF |
1037 | On the H8/300 all normal args are pushed, unless -mquickcall in which |
1038 | case the first 3 arguments are passed in registers. */ | |
1039 | ||
1040 | static rtx | |
1041 | h8300_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
1042 | const_tree type, bool named) | |
07aae5c2 | 1043 | { |
0ea6f6a0 KH |
1044 | static const char *const hand_list[] = { |
1045 | "__main", | |
1046 | "__cmpsi2", | |
1047 | "__divhi3", | |
1048 | "__modhi3", | |
1049 | "__udivhi3", | |
1050 | "__umodhi3", | |
1051 | "__divsi3", | |
1052 | "__modsi3", | |
1053 | "__udivsi3", | |
1054 | "__umodsi3", | |
1055 | "__mulhi3", | |
1056 | "__mulsi3", | |
1057 | "__reg_memcpy", | |
1058 | "__reg_memset", | |
1059 | "__ucmpsi2", | |
1060 | 0, | |
1061 | }; | |
1062 | ||
7192cbf1 | 1063 | rtx result = NULL_RTX; |
441d04c6 | 1064 | const char *fname; |
48837e29 DE |
1065 | int regpass = 0; |
1066 | ||
dd07092e JL |
1067 | /* Never pass unnamed arguments in registers. */ |
1068 | if (!named) | |
7192cbf1 | 1069 | return NULL_RTX; |
dd07092e | 1070 | |
48837e29 DE |
1071 | /* Pass 3 regs worth of data in regs when user asked on the command line. */ |
1072 | if (TARGET_QUICKCALL) | |
1073 | regpass = 3; | |
1074 | ||
1075 | /* If calling hand written assembler, use 4 regs of args. */ | |
48837e29 DE |
1076 | if (cum->libcall) |
1077 | { | |
441d04c6 | 1078 | const char * const *p; |
48837e29 DE |
1079 | |
1080 | fname = XSTR (cum->libcall, 0); | |
1081 | ||
1082 | /* See if this libcall is one of the hand coded ones. */ | |
48837e29 DE |
1083 | for (p = hand_list; *p && strcmp (*p, fname) != 0; p++) |
1084 | ; | |
07aae5c2 | 1085 | |
48837e29 DE |
1086 | if (*p) |
1087 | regpass = 4; | |
1088 | } | |
1089 | ||
1090 | if (regpass) | |
1091 | { | |
1092 | int size; | |
1093 | ||
1094 | if (mode == BLKmode) | |
1095 | size = int_size_in_bytes (type); | |
1096 | else | |
1097 | size = GET_MODE_SIZE (mode); | |
1098 | ||
15e0e275 KH |
1099 | if (size + cum->nbytes <= regpass * UNITS_PER_WORD |
1100 | && cum->nbytes / UNITS_PER_WORD <= 3) | |
1101 | result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD); | |
48837e29 | 1102 | } |
07aae5c2 | 1103 | |
48837e29 DE |
1104 | return result; |
1105 | } | |
56f9413b NF |
1106 | |
1107 | /* Update the data in CUM to advance over an argument | |
1108 | of mode MODE and data type TYPE. | |
1109 | (TYPE is null for libcalls where that information may not be available.) */ | |
1110 | ||
1111 | static void | |
1112 | h8300_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
1113 | const_tree type, bool named ATTRIBUTE_UNUSED) | |
1114 | { | |
1115 | cum->nbytes += (mode != BLKmode | |
1116 | ? (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD | |
1117 | : (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD); | |
1118 | } | |
1119 | ||
48837e29 | 1120 | \f |
e9eba255 KH |
1121 | /* Compute the cost of an and insn. */ |
1122 | ||
3c50106f | 1123 | static int |
cb713a8d | 1124 | h8300_and_costs (rtx x) |
73cc75e9 KH |
1125 | { |
1126 | rtx operands[4]; | |
1127 | ||
1128 | if (GET_MODE (x) == QImode) | |
1129 | return 1; | |
1130 | ||
1131 | if (GET_MODE (x) != HImode | |
1132 | && GET_MODE (x) != SImode) | |
1133 | return 100; | |
1134 | ||
1135 | operands[0] = NULL; | |
beed8fc0 | 1136 | operands[1] = XEXP (x, 0); |
73cc75e9 KH |
1137 | operands[2] = XEXP (x, 1); |
1138 | operands[3] = x; | |
4f4ebda3 | 1139 | return compute_logical_op_length (GET_MODE (x), operands) / 2; |
73cc75e9 KH |
1140 | } |
1141 | ||
e9eba255 KH |
1142 | /* Compute the cost of a shift insn. */ |
1143 | ||
3c50106f | 1144 | static int |
cb713a8d | 1145 | h8300_shift_costs (rtx x) |
ae557002 KH |
1146 | { |
1147 | rtx operands[4]; | |
1148 | ||
1149 | if (GET_MODE (x) != QImode | |
1150 | && GET_MODE (x) != HImode | |
1151 | && GET_MODE (x) != SImode) | |
1152 | return 100; | |
1153 | ||
1154 | operands[0] = NULL; | |
1155 | operands[1] = NULL; | |
1156 | operands[2] = XEXP (x, 1); | |
1157 | operands[3] = x; | |
4f4ebda3 | 1158 | return compute_a_shift_length (NULL, operands) / 2; |
ae557002 | 1159 | } |
3c50106f | 1160 | |
e9eba255 KH |
1161 | /* Worker function for TARGET_RTX_COSTS. */ |
1162 | ||
3c50106f | 1163 | static bool |
f40751dd | 1164 | h8300_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed) |
3c50106f | 1165 | { |
beed8fc0 AO |
1166 | if (TARGET_H8300SX && outer_code == MEM) |
1167 | { | |
1168 | /* Estimate the number of execution states needed to calculate | |
1169 | the address. */ | |
1170 | if (register_operand (x, VOIDmode) | |
1171 | || GET_CODE (x) == POST_INC | |
1172 | || GET_CODE (x) == POST_DEC | |
1173 | || CONSTANT_P (x)) | |
1174 | *total = 0; | |
1175 | else | |
1176 | *total = COSTS_N_INSNS (1); | |
1177 | return true; | |
1178 | } | |
1179 | ||
3c50106f RH |
1180 | switch (code) |
1181 | { | |
08dca707 KH |
1182 | case CONST_INT: |
1183 | { | |
1184 | HOST_WIDE_INT n = INTVAL (x); | |
1185 | ||
beed8fc0 AO |
1186 | if (TARGET_H8300SX) |
1187 | { | |
1188 | /* Constant operands need the same number of processor | |
1189 | states as register operands. Although we could try to | |
f40751dd | 1190 | use a size-based cost for !speed, the lack of |
beed8fc0 AO |
1191 | of a mode makes the results very unpredictable. */ |
1192 | *total = 0; | |
1193 | return true; | |
1194 | } | |
08dca707 KH |
1195 | if (-4 <= n || n <= 4) |
1196 | { | |
1197 | switch ((int) n) | |
1198 | { | |
1199 | case 0: | |
1200 | *total = 0; | |
1201 | return true; | |
1202 | case 1: | |
1203 | case 2: | |
1204 | case -1: | |
1205 | case -2: | |
1206 | *total = 0 + (outer_code == SET); | |
1207 | return true; | |
1208 | case 4: | |
1209 | case -4: | |
1210 | if (TARGET_H8300H || TARGET_H8300S) | |
1211 | *total = 0 + (outer_code == SET); | |
1212 | else | |
1213 | *total = 1; | |
1214 | return true; | |
1215 | } | |
1216 | } | |
1217 | *total = 1; | |
1218 | return true; | |
1219 | } | |
1220 | ||
1221 | case CONST: | |
1222 | case LABEL_REF: | |
1223 | case SYMBOL_REF: | |
beed8fc0 AO |
1224 | if (TARGET_H8300SX) |
1225 | { | |
1226 | /* See comment for CONST_INT. */ | |
1227 | *total = 0; | |
1228 | return true; | |
1229 | } | |
08dca707 KH |
1230 | *total = 3; |
1231 | return true; | |
1232 | ||
1233 | case CONST_DOUBLE: | |
1234 | *total = 20; | |
1235 | return true; | |
1236 | ||
f90b7a5a PB |
1237 | case COMPARE: |
1238 | if (XEXP (x, 1) == const0_rtx) | |
1239 | *total = 0; | |
1240 | return false; | |
1241 | ||
3c50106f | 1242 | case AND: |
beed8fc0 AO |
1243 | if (!h8300_dst_operand (XEXP (x, 0), VOIDmode) |
1244 | || !h8300_src_operand (XEXP (x, 1), VOIDmode)) | |
1245 | return false; | |
3c50106f RH |
1246 | *total = COSTS_N_INSNS (h8300_and_costs (x)); |
1247 | return true; | |
1248 | ||
1249 | /* We say that MOD and DIV are so expensive because otherwise we'll | |
1250 | generate some really horrible code for division of a power of two. */ | |
1251 | case MOD: | |
1252 | case DIV: | |
beed8fc0 AO |
1253 | case UMOD: |
1254 | case UDIV: | |
1255 | if (TARGET_H8300SX) | |
1256 | switch (GET_MODE (x)) | |
1257 | { | |
1258 | case QImode: | |
1259 | case HImode: | |
f40751dd | 1260 | *total = COSTS_N_INSNS (!speed ? 4 : 10); |
beed8fc0 AO |
1261 | return false; |
1262 | ||
1263 | case SImode: | |
f40751dd | 1264 | *total = COSTS_N_INSNS (!speed ? 4 : 18); |
beed8fc0 AO |
1265 | return false; |
1266 | ||
1267 | default: | |
1268 | break; | |
1269 | } | |
1270 | *total = COSTS_N_INSNS (12); | |
3c50106f RH |
1271 | return true; |
1272 | ||
1273 | case MULT: | |
beed8fc0 AO |
1274 | if (TARGET_H8300SX) |
1275 | switch (GET_MODE (x)) | |
1276 | { | |
1277 | case QImode: | |
1278 | case HImode: | |
1279 | *total = COSTS_N_INSNS (2); | |
1280 | return false; | |
1281 | ||
1282 | case SImode: | |
1283 | *total = COSTS_N_INSNS (5); | |
1284 | return false; | |
1285 | ||
1286 | default: | |
1287 | break; | |
1288 | } | |
1289 | *total = COSTS_N_INSNS (4); | |
3c50106f RH |
1290 | return true; |
1291 | ||
1292 | case ASHIFT: | |
1293 | case ASHIFTRT: | |
1294 | case LSHIFTRT: | |
beed8fc0 AO |
1295 | if (h8sx_binary_shift_operator (x, VOIDmode)) |
1296 | { | |
1297 | *total = COSTS_N_INSNS (2); | |
1298 | return false; | |
1299 | } | |
1300 | else if (h8sx_unary_shift_operator (x, VOIDmode)) | |
1301 | { | |
1302 | *total = COSTS_N_INSNS (1); | |
1303 | return false; | |
1304 | } | |
3c50106f RH |
1305 | *total = COSTS_N_INSNS (h8300_shift_costs (x)); |
1306 | return true; | |
1307 | ||
1308 | case ROTATE: | |
1309 | case ROTATERT: | |
1310 | if (GET_MODE (x) == HImode) | |
1311 | *total = 2; | |
1312 | else | |
1313 | *total = 8; | |
1314 | return true; | |
1315 | ||
1316 | default: | |
beed8fc0 AO |
1317 | *total = COSTS_N_INSNS (1); |
1318 | return false; | |
3c50106f RH |
1319 | } |
1320 | } | |
48837e29 | 1321 | \f |
07aae5c2 SC |
1322 | /* Documentation for the machine specific operand escapes: |
1323 | ||
48837e29 DE |
1324 | 'E' like s but negative. |
1325 | 'F' like t but negative. | |
1326 | 'G' constant just the negative | |
15dc331e JL |
1327 | 'R' print operand as a byte:8 address if appropriate, else fall back to |
1328 | 'X' handling. | |
48837e29 | 1329 | 'S' print operand as a long word |
07aae5c2 | 1330 | 'T' print operand as a word |
48837e29 DE |
1331 | 'V' find the set bit, and print its number. |
1332 | 'W' find the clear bit, and print its number. | |
1333 | 'X' print operand as a byte | |
07aae5c2 | 1334 | 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8. |
15dc331e | 1335 | If this operand isn't a register, fall back to 'R' handling. |
48837e29 | 1336 | 'Z' print int & 7. |
b059c02a | 1337 | 'c' print the opcode corresponding to rtl |
da55315a | 1338 | 'e' first word of 32-bit value - if reg, then least reg. if mem |
48837e29 | 1339 | then least. if const then most sig word |
da55315a | 1340 | 'f' second word of 32-bit value - if reg, then biggest reg. if mem |
48837e29 | 1341 | then +2. if const then least sig word |
07aae5c2 SC |
1342 | 'j' print operand as condition code. |
1343 | 'k' print operand as reverse condition code. | |
beed8fc0 AO |
1344 | 'm' convert an integer operand to a size suffix (.b, .w or .l) |
1345 | 'o' print an integer without a leading '#' | |
da55315a KH |
1346 | 's' print as low byte of 16-bit value |
1347 | 't' print as high byte of 16-bit value | |
1348 | 'w' print as low byte of 32-bit value | |
1349 | 'x' print as 2nd byte of 32-bit value | |
1350 | 'y' print as 3rd byte of 32-bit value | |
1351 | 'z' print as msb of 32-bit value | |
48837e29 | 1352 | */ |
07aae5c2 SC |
1353 | |
1354 | /* Return assembly language string which identifies a comparison type. */ | |
1355 | ||
441d04c6 | 1356 | static const char * |
cb713a8d | 1357 | cond_string (enum rtx_code code) |
07aae5c2 SC |
1358 | { |
1359 | switch (code) | |
1360 | { | |
1361 | case NE: | |
1362 | return "ne"; | |
1363 | case EQ: | |
1364 | return "eq"; | |
1365 | case GE: | |
1366 | return "ge"; | |
1367 | case GT: | |
1368 | return "gt"; | |
1369 | case LE: | |
1370 | return "le"; | |
1371 | case LT: | |
1372 | return "lt"; | |
1373 | case GEU: | |
1374 | return "hs"; | |
1375 | case GTU: | |
1376 | return "hi"; | |
1377 | case LEU: | |
1378 | return "ls"; | |
1379 | case LTU: | |
1380 | return "lo"; | |
1381 | default: | |
8c440872 | 1382 | gcc_unreachable (); |
07aae5c2 SC |
1383 | } |
1384 | } | |
1385 | ||
1386 | /* Print operand X using operand code CODE to assembly language output file | |
1387 | FILE. */ | |
1388 | ||
1389 | void | |
cb713a8d | 1390 | print_operand (FILE *file, rtx x, int code) |
07aae5c2 | 1391 | { |
269c14e1 | 1392 | /* This is used for communication between codes V,W,Z and Y. */ |
07aae5c2 SC |
1393 | static int bitint; |
1394 | ||
1395 | switch (code) | |
1396 | { | |
48837e29 DE |
1397 | case 'E': |
1398 | switch (GET_CODE (x)) | |
1399 | { | |
1400 | case REG: | |
1401 | fprintf (file, "%sl", names_big[REGNO (x)]); | |
1402 | break; | |
1403 | case CONST_INT: | |
b47900aa | 1404 | fprintf (file, "#%ld", (-INTVAL (x)) & 0xff); |
48837e29 DE |
1405 | break; |
1406 | default: | |
8c440872 | 1407 | gcc_unreachable (); |
48837e29 DE |
1408 | } |
1409 | break; | |
1410 | case 'F': | |
1411 | switch (GET_CODE (x)) | |
1412 | { | |
1413 | case REG: | |
1414 | fprintf (file, "%sh", names_big[REGNO (x)]); | |
1415 | break; | |
1416 | case CONST_INT: | |
b47900aa | 1417 | fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8); |
48837e29 DE |
1418 | break; |
1419 | default: | |
8c440872 | 1420 | gcc_unreachable (); |
48837e29 DE |
1421 | } |
1422 | break; | |
07aae5c2 | 1423 | case 'G': |
8c440872 | 1424 | gcc_assert (GET_CODE (x) == CONST_INT); |
b47900aa | 1425 | fprintf (file, "#%ld", 0xff & (-INTVAL (x))); |
07aae5c2 | 1426 | break; |
48837e29 DE |
1427 | case 'S': |
1428 | if (GET_CODE (x) == REG) | |
1429 | fprintf (file, "%s", names_extended[REGNO (x)]); | |
07aae5c2 | 1430 | else |
48837e29 | 1431 | goto def; |
07aae5c2 | 1432 | break; |
48837e29 DE |
1433 | case 'T': |
1434 | if (GET_CODE (x) == REG) | |
1435 | fprintf (file, "%s", names_big[REGNO (x)]); | |
07aae5c2 | 1436 | else |
48837e29 | 1437 | goto def; |
07aae5c2 | 1438 | break; |
48837e29 | 1439 | case 'V': |
0f6b820c KP |
1440 | bitint = (INTVAL (x) & 0xffff); |
1441 | if ((exact_log2 ((bitint >> 8) & 0xff)) == -1) | |
1442 | bitint = exact_log2 (bitint & 0xff); | |
1443 | else | |
1444 | bitint = exact_log2 ((bitint >> 8) & 0xff); | |
8c440872 | 1445 | gcc_assert (bitint >= 0); |
4d4d89e2 | 1446 | fprintf (file, "#%d", bitint); |
07aae5c2 | 1447 | break; |
48837e29 | 1448 | case 'W': |
0f6b820c KP |
1449 | bitint = ((~INTVAL (x)) & 0xffff); |
1450 | if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 ) | |
1451 | bitint = exact_log2 (bitint & 0xff); | |
1452 | else | |
1453 | bitint = (exact_log2 ((bitint >> 8) & 0xff)); | |
8c440872 | 1454 | gcc_assert (bitint >= 0); |
4d4d89e2 | 1455 | fprintf (file, "#%d", bitint); |
07aae5c2 | 1456 | break; |
15dc331e | 1457 | case 'R': |
48837e29 DE |
1458 | case 'X': |
1459 | if (GET_CODE (x) == REG) | |
1460 | fprintf (file, "%s", byte_reg (x, 0)); | |
1461 | else | |
1462 | goto def; | |
1463 | break; | |
1464 | case 'Y': | |
8c440872 | 1465 | gcc_assert (bitint >= 0); |
48837e29 DE |
1466 | if (GET_CODE (x) == REG) |
1467 | fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l'); | |
1468 | else | |
15dc331e | 1469 | print_operand (file, x, 'R'); |
48837e29 DE |
1470 | bitint = -1; |
1471 | break; | |
1472 | case 'Z': | |
1473 | bitint = INTVAL (x); | |
07aae5c2 SC |
1474 | fprintf (file, "#%d", bitint & 7); |
1475 | break; | |
b059c02a KH |
1476 | case 'c': |
1477 | switch (GET_CODE (x)) | |
1478 | { | |
1479 | case IOR: | |
1480 | fprintf (file, "or"); | |
1481 | break; | |
1482 | case XOR: | |
1483 | fprintf (file, "xor"); | |
1484 | break; | |
5abfd1af KH |
1485 | case AND: |
1486 | fprintf (file, "and"); | |
1487 | break; | |
b059c02a KH |
1488 | default: |
1489 | break; | |
1490 | } | |
1491 | break; | |
07aae5c2 SC |
1492 | case 'e': |
1493 | switch (GET_CODE (x)) | |
1494 | { | |
1495 | case REG: | |
48837e29 DE |
1496 | if (TARGET_H8300) |
1497 | fprintf (file, "%s", names_big[REGNO (x)]); | |
1498 | else | |
1499 | fprintf (file, "%s", names_upper_extended[REGNO (x)]); | |
07aae5c2 SC |
1500 | break; |
1501 | case MEM: | |
07aae5c2 SC |
1502 | print_operand (file, x, 0); |
1503 | break; | |
1504 | case CONST_INT: | |
b47900aa | 1505 | fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff)); |
07aae5c2 | 1506 | break; |
808fbfac JL |
1507 | case CONST_DOUBLE: |
1508 | { | |
1509 | long val; | |
1510 | REAL_VALUE_TYPE rv; | |
1511 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
1512 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
441d04c6 | 1513 | fprintf (file, "#%ld", ((val >> 16) & 0xffff)); |
808fbfac JL |
1514 | break; |
1515 | } | |
07aae5c2 | 1516 | default: |
8c440872 | 1517 | gcc_unreachable (); |
07aae5c2 SC |
1518 | break; |
1519 | } | |
1520 | break; | |
07aae5c2 SC |
1521 | case 'f': |
1522 | switch (GET_CODE (x)) | |
1523 | { | |
1524 | case REG: | |
48837e29 DE |
1525 | if (TARGET_H8300) |
1526 | fprintf (file, "%s", names_big[REGNO (x) + 1]); | |
1527 | else | |
1528 | fprintf (file, "%s", names_big[REGNO (x)]); | |
07aae5c2 | 1529 | break; |
07aae5c2 | 1530 | case MEM: |
b72f00af | 1531 | x = adjust_address (x, HImode, 2); |
07aae5c2 SC |
1532 | print_operand (file, x, 0); |
1533 | break; | |
07aae5c2 | 1534 | case CONST_INT: |
b47900aa | 1535 | fprintf (file, "#%ld", INTVAL (x) & 0xffff); |
07aae5c2 | 1536 | break; |
808fbfac JL |
1537 | case CONST_DOUBLE: |
1538 | { | |
1539 | long val; | |
1540 | REAL_VALUE_TYPE rv; | |
1541 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
1542 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
441d04c6 | 1543 | fprintf (file, "#%ld", (val & 0xffff)); |
808fbfac JL |
1544 | break; |
1545 | } | |
07aae5c2 | 1546 | default: |
8c440872 | 1547 | gcc_unreachable (); |
07aae5c2 SC |
1548 | } |
1549 | break; | |
07aae5c2 | 1550 | case 'j': |
761c70aa | 1551 | fputs (cond_string (GET_CODE (x)), file); |
07aae5c2 | 1552 | break; |
07aae5c2 | 1553 | case 'k': |
761c70aa | 1554 | fputs (cond_string (reverse_condition (GET_CODE (x))), file); |
07aae5c2 | 1555 | break; |
beed8fc0 | 1556 | case 'm': |
8c440872 NS |
1557 | gcc_assert (GET_CODE (x) == CONST_INT); |
1558 | switch (INTVAL (x)) | |
1559 | { | |
1560 | case 1: | |
1561 | fputs (".b", file); | |
1562 | break; | |
1563 | ||
1564 | case 2: | |
1565 | fputs (".w", file); | |
1566 | break; | |
1567 | ||
1568 | case 4: | |
1569 | fputs (".l", file); | |
1570 | break; | |
1571 | ||
1572 | default: | |
1573 | gcc_unreachable (); | |
1574 | } | |
beed8fc0 AO |
1575 | break; |
1576 | case 'o': | |
1577 | print_operand_address (file, x); | |
1578 | break; | |
48837e29 DE |
1579 | case 's': |
1580 | if (GET_CODE (x) == CONST_INT) | |
b47900aa | 1581 | fprintf (file, "#%ld", (INTVAL (x)) & 0xff); |
48837e29 DE |
1582 | else |
1583 | fprintf (file, "%s", byte_reg (x, 0)); | |
1584 | break; | |
1585 | case 't': | |
1586 | if (GET_CODE (x) == CONST_INT) | |
b47900aa | 1587 | fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff); |
48837e29 DE |
1588 | else |
1589 | fprintf (file, "%s", byte_reg (x, 1)); | |
1590 | break; | |
48837e29 DE |
1591 | case 'w': |
1592 | if (GET_CODE (x) == CONST_INT) | |
b47900aa | 1593 | fprintf (file, "#%ld", INTVAL (x) & 0xff); |
48837e29 | 1594 | else |
a1616dd9 JL |
1595 | fprintf (file, "%s", |
1596 | byte_reg (x, TARGET_H8300 ? 2 : 0)); | |
48837e29 DE |
1597 | break; |
1598 | case 'x': | |
1599 | if (GET_CODE (x) == CONST_INT) | |
b47900aa | 1600 | fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff); |
48837e29 | 1601 | else |
a1616dd9 JL |
1602 | fprintf (file, "%s", |
1603 | byte_reg (x, TARGET_H8300 ? 3 : 1)); | |
48837e29 DE |
1604 | break; |
1605 | case 'y': | |
1606 | if (GET_CODE (x) == CONST_INT) | |
b47900aa | 1607 | fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff); |
48837e29 DE |
1608 | else |
1609 | fprintf (file, "%s", byte_reg (x, 0)); | |
1610 | break; | |
1611 | case 'z': | |
1612 | if (GET_CODE (x) == CONST_INT) | |
b47900aa | 1613 | fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff); |
48837e29 DE |
1614 | else |
1615 | fprintf (file, "%s", byte_reg (x, 1)); | |
1616 | break; | |
1617 | ||
07aae5c2 | 1618 | default: |
48837e29 | 1619 | def: |
07aae5c2 SC |
1620 | switch (GET_CODE (x)) |
1621 | { | |
1622 | case REG: | |
48837e29 DE |
1623 | switch (GET_MODE (x)) |
1624 | { | |
1625 | case QImode: | |
269c14e1 | 1626 | #if 0 /* Is it asm ("mov.b %0,r2l", ...) */ |
48837e29 DE |
1627 | fprintf (file, "%s", byte_reg (x, 0)); |
1628 | #else /* ... or is it asm ("mov.b %0l,r2l", ...) */ | |
1629 | fprintf (file, "%s", names_big[REGNO (x)]); | |
1630 | #endif | |
1631 | break; | |
1632 | case HImode: | |
1633 | fprintf (file, "%s", names_big[REGNO (x)]); | |
1634 | break; | |
1635 | case SImode: | |
8977e8a7 | 1636 | case SFmode: |
48837e29 DE |
1637 | fprintf (file, "%s", names_extended[REGNO (x)]); |
1638 | break; | |
1639 | default: | |
8c440872 | 1640 | gcc_unreachable (); |
48837e29 | 1641 | } |
07aae5c2 SC |
1642 | break; |
1643 | ||
1644 | case MEM: | |
87e4ee91 KH |
1645 | { |
1646 | rtx addr = XEXP (x, 0); | |
1647 | ||
1648 | fprintf (file, "@"); | |
1649 | output_address (addr); | |
1650 | ||
beed8fc0 AO |
1651 | /* Add a length suffix to constant addresses. Although this |
1652 | is often unnecessary, it helps to avoid ambiguity in the | |
1653 | syntax of mova. If we wrote an insn like: | |
1654 | ||
1655 | mova/w.l @(1,@foo.b),er0 | |
1656 | ||
1657 | then .b would be considered part of the symbol name. | |
1658 | Adding a length after foo will avoid this. */ | |
1659 | if (CONSTANT_P (addr)) | |
1660 | switch (code) | |
1661 | { | |
1662 | case 'R': | |
1663 | /* Used for mov.b and bit operations. */ | |
1664 | if (h8300_eightbit_constant_address_p (addr)) | |
1665 | { | |
1666 | fprintf (file, ":8"); | |
1667 | break; | |
1668 | } | |
1669 | ||
1670 | /* Fall through. We should not get here if we are | |
1671 | processing bit operations on H8/300 or H8/300H | |
1672 | because 'U' constraint does not allow bit | |
1673 | operations on the tiny area on these machines. */ | |
1674 | ||
1675 | case 'X': | |
1676 | case 'T': | |
1677 | case 'S': | |
1678 | if (h8300_constant_length (addr) == 2) | |
1679 | fprintf (file, ":16"); | |
1680 | else | |
1681 | fprintf (file, ":32"); | |
1682 | break; | |
1683 | default: | |
1684 | break; | |
1685 | } | |
87e4ee91 | 1686 | } |
07aae5c2 SC |
1687 | break; |
1688 | ||
1689 | case CONST_INT: | |
1690 | case SYMBOL_REF: | |
1691 | case CONST: | |
1692 | case LABEL_REF: | |
1693 | fprintf (file, "#"); | |
1694 | print_operand_address (file, x); | |
1695 | break; | |
808fbfac JL |
1696 | case CONST_DOUBLE: |
1697 | { | |
1698 | long val; | |
1699 | REAL_VALUE_TYPE rv; | |
1700 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
1701 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
441d04c6 | 1702 | fprintf (file, "#%ld", val); |
808fbfac JL |
1703 | break; |
1704 | } | |
441d04c6 KG |
1705 | default: |
1706 | break; | |
07aae5c2 SC |
1707 | } |
1708 | } | |
1709 | } | |
1710 | ||
1711 | /* Output assembly language output for the address ADDR to FILE. */ | |
1712 | ||
1713 | void | |
cb713a8d | 1714 | print_operand_address (FILE *file, rtx addr) |
07aae5c2 | 1715 | { |
beed8fc0 AO |
1716 | rtx index; |
1717 | int size; | |
1718 | ||
07aae5c2 SC |
1719 | switch (GET_CODE (addr)) |
1720 | { | |
1721 | case REG: | |
48837e29 | 1722 | fprintf (file, "%s", h8_reg_names[REGNO (addr)]); |
07aae5c2 SC |
1723 | break; |
1724 | ||
1725 | case PRE_DEC: | |
48837e29 | 1726 | fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]); |
07aae5c2 SC |
1727 | break; |
1728 | ||
1729 | case POST_INC: | |
48837e29 | 1730 | fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]); |
07aae5c2 SC |
1731 | break; |
1732 | ||
beed8fc0 AO |
1733 | case PRE_INC: |
1734 | fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]); | |
1735 | break; | |
1736 | ||
1737 | case POST_DEC: | |
1738 | fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]); | |
1739 | break; | |
1740 | ||
07aae5c2 SC |
1741 | case PLUS: |
1742 | fprintf (file, "("); | |
beed8fc0 AO |
1743 | |
1744 | index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size); | |
1745 | if (GET_CODE (index) == REG) | |
07aae5c2 SC |
1746 | { |
1747 | /* reg,foo */ | |
1748 | print_operand_address (file, XEXP (addr, 1)); | |
1749 | fprintf (file, ","); | |
beed8fc0 AO |
1750 | switch (size) |
1751 | { | |
1752 | case 0: | |
1753 | print_operand_address (file, index); | |
1754 | break; | |
1755 | ||
1756 | case 1: | |
1757 | print_operand (file, index, 'X'); | |
1758 | fputs (".b", file); | |
1759 | break; | |
1760 | ||
1761 | case 2: | |
1762 | print_operand (file, index, 'T'); | |
1763 | fputs (".w", file); | |
1764 | break; | |
1765 | ||
1766 | case 4: | |
1767 | print_operand (file, index, 'S'); | |
1768 | fputs (".l", file); | |
1769 | break; | |
1770 | } | |
1771 | /* print_operand_address (file, XEXP (addr, 0)); */ | |
07aae5c2 SC |
1772 | } |
1773 | else | |
1774 | { | |
1775 | /* foo+k */ | |
1776 | print_operand_address (file, XEXP (addr, 0)); | |
1777 | fprintf (file, "+"); | |
1778 | print_operand_address (file, XEXP (addr, 1)); | |
1779 | } | |
1780 | fprintf (file, ")"); | |
1781 | break; | |
1782 | ||
1783 | case CONST_INT: | |
48837e29 | 1784 | { |
da55315a | 1785 | /* Since the H8/300 only has 16-bit pointers, negative values are also |
48837e29 DE |
1786 | those >= 32768. This happens for example with pointer minus a |
1787 | constant. We don't want to turn (char *p - 2) into | |
1788 | (char *p + 65534) because loop unrolling can build upon this | |
1789 | (IE: char *p + 131068). */ | |
1790 | int n = INTVAL (addr); | |
1791 | if (TARGET_H8300) | |
1792 | n = (int) (short) n; | |
7a770d8b | 1793 | fprintf (file, "%d", n); |
48837e29 DE |
1794 | break; |
1795 | } | |
07aae5c2 SC |
1796 | |
1797 | default: | |
1798 | output_addr_const (file, addr); | |
1799 | break; | |
1800 | } | |
1801 | } | |
1802 | \f | |
07aae5c2 SC |
1803 | /* Output all insn addresses and their sizes into the assembly language |
1804 | output file. This is helpful for debugging whether the length attributes | |
1805 | in the md file are correct. This is not meant to be a user selectable | |
1806 | option. */ | |
1807 | ||
1808 | void | |
cb713a8d KH |
1809 | final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED, |
1810 | int num_operands ATTRIBUTE_UNUSED) | |
07aae5c2 SC |
1811 | { |
1812 | /* This holds the last insn address. */ | |
1813 | static int last_insn_address = 0; | |
1814 | ||
7798db98 | 1815 | const int uid = INSN_UID (insn); |
07aae5c2 SC |
1816 | |
1817 | if (TARGET_ADDRESSES) | |
1818 | { | |
9d98a694 AO |
1819 | fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid), |
1820 | INSN_ADDRESSES (uid) - last_insn_address); | |
1821 | last_insn_address = INSN_ADDRESSES (uid); | |
07aae5c2 SC |
1822 | } |
1823 | } | |
1824 | ||
48837e29 DE |
1825 | /* Prepare for an SI sized move. */ |
1826 | ||
1827 | int | |
1a793acf | 1828 | h8300_expand_movsi (rtx operands[]) |
07aae5c2 | 1829 | { |
48837e29 DE |
1830 | rtx src = operands[1]; |
1831 | rtx dst = operands[0]; | |
1832 | if (!reload_in_progress && !reload_completed) | |
1833 | { | |
1834 | if (!register_operand (dst, GET_MODE (dst))) | |
1835 | { | |
1836 | rtx tmp = gen_reg_rtx (GET_MODE (dst)); | |
1837 | emit_move_insn (tmp, src); | |
1838 | operands[1] = tmp; | |
1839 | } | |
1840 | } | |
1841 | return 0; | |
1842 | } | |
1843 | ||
7b5cbb57 AS |
1844 | /* Given FROM and TO register numbers, say whether this elimination is allowed. |
1845 | Frame pointer elimination is automatically handled. | |
1846 | ||
1847 | For the h8300, if frame pointer elimination is being done, we would like to | |
1848 | convert ap and rp into sp, not fp. | |
1849 | ||
1850 | All other eliminations are valid. */ | |
1851 | ||
1852 | static bool | |
1853 | h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) | |
1854 | { | |
1855 | return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true); | |
1856 | } | |
1857 | ||
5efd84c5 NF |
1858 | /* Conditionally modify register usage based on target flags. */ |
1859 | ||
1860 | static void | |
1861 | h8300_conditional_register_usage (void) | |
1862 | { | |
1863 | if (!TARGET_MAC) | |
1864 | fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1; | |
1865 | } | |
1866 | ||
48837e29 | 1867 | /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET). |
07e4d94e KH |
1868 | Define the offset between two registers, one to be eliminated, and |
1869 | the other its replacement, at the start of a routine. */ | |
07aae5c2 | 1870 | |
48837e29 | 1871 | int |
cb713a8d | 1872 | h8300_initial_elimination_offset (int from, int to) |
48837e29 | 1873 | { |
d18ad191 KH |
1874 | /* The number of bytes that the return address takes on the stack. */ |
1875 | int pc_size = POINTER_SIZE / BITS_PER_UNIT; | |
48837e29 | 1876 | |
1807b726 KH |
1877 | /* The number of bytes that the saved frame pointer takes on the stack. */ |
1878 | int fp_size = frame_pointer_needed * UNITS_PER_WORD; | |
1879 | ||
1880 | /* The number of bytes that the saved registers, excluding the frame | |
1881 | pointer, take on the stack. */ | |
1882 | int saved_regs_size = 0; | |
48837e29 | 1883 | |
1807b726 KH |
1884 | /* The number of bytes that the locals takes on the stack. */ |
1885 | int frame_size = round_frame_size (get_frame_size ()); | |
48837e29 | 1886 | |
1807b726 | 1887 | int regno; |
48837e29 | 1888 | |
1807b726 KH |
1889 | for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++) |
1890 | if (WORD_REG_USED (regno)) | |
1891 | saved_regs_size += UNITS_PER_WORD; | |
48837e29 | 1892 | |
1807b726 KH |
1893 | /* Adjust saved_regs_size because the above loop took the frame |
1894 | pointer int account. */ | |
1895 | saved_regs_size -= fp_size; | |
39ba95b5 | 1896 | |
8c440872 | 1897 | switch (to) |
1807b726 | 1898 | { |
8c440872 | 1899 | case HARD_FRAME_POINTER_REGNUM: |
1807b726 KH |
1900 | switch (from) |
1901 | { | |
1902 | case ARG_POINTER_REGNUM: | |
1903 | return pc_size + fp_size; | |
1904 | case RETURN_ADDRESS_POINTER_REGNUM: | |
1905 | return fp_size; | |
1906 | case FRAME_POINTER_REGNUM: | |
1907 | return -saved_regs_size; | |
1908 | default: | |
8c440872 | 1909 | gcc_unreachable (); |
1807b726 | 1910 | } |
8c440872 NS |
1911 | break; |
1912 | case STACK_POINTER_REGNUM: | |
1807b726 KH |
1913 | switch (from) |
1914 | { | |
1915 | case ARG_POINTER_REGNUM: | |
1916 | return pc_size + saved_regs_size + frame_size; | |
1917 | case RETURN_ADDRESS_POINTER_REGNUM: | |
1918 | return saved_regs_size + frame_size; | |
1919 | case FRAME_POINTER_REGNUM: | |
1920 | return frame_size; | |
1921 | default: | |
8c440872 | 1922 | gcc_unreachable (); |
1807b726 | 1923 | } |
8c440872 NS |
1924 | break; |
1925 | default: | |
1926 | gcc_unreachable (); | |
1807b726 | 1927 | } |
8c440872 | 1928 | gcc_unreachable (); |
48837e29 DE |
1929 | } |
1930 | ||
e9eba255 KH |
1931 | /* Worker function for RETURN_ADDR_RTX. */ |
1932 | ||
1aae372e | 1933 | rtx |
cb713a8d | 1934 | h8300_return_addr_rtx (int count, rtx frame) |
1aae372e JL |
1935 | { |
1936 | rtx ret; | |
1937 | ||
1938 | if (count == 0) | |
1939 | ret = gen_rtx_MEM (Pmode, | |
1940 | gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM)); | |
1941 | else if (flag_omit_frame_pointer) | |
1942 | return (rtx) 0; | |
1943 | else | |
1944 | ret = gen_rtx_MEM (Pmode, | |
1945 | memory_address (Pmode, | |
1946 | plus_constant (frame, UNITS_PER_WORD))); | |
1947 | set_mem_alias_set (ret, get_frame_alias_set ()); | |
1948 | return ret; | |
1949 | } | |
1950 | ||
48837e29 DE |
1951 | /* Update the condition code from the insn. */ |
1952 | ||
441d04c6 | 1953 | void |
cb713a8d | 1954 | notice_update_cc (rtx body, rtx insn) |
48837e29 | 1955 | { |
d99c740f KH |
1956 | rtx set; |
1957 | ||
48837e29 DE |
1958 | switch (get_attr_cc (insn)) |
1959 | { | |
1960 | case CC_NONE: | |
269c14e1 | 1961 | /* Insn does not affect CC at all. */ |
48837e29 DE |
1962 | break; |
1963 | ||
1964 | case CC_NONE_0HIT: | |
269c14e1 | 1965 | /* Insn does not change CC, but the 0'th operand has been changed. */ |
48837e29 | 1966 | if (cc_status.value1 != 0 |
1ccbefce | 1967 | && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1)) |
48837e29 | 1968 | cc_status.value1 = 0; |
d4d6d0ce KH |
1969 | if (cc_status.value2 != 0 |
1970 | && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2)) | |
1971 | cc_status.value2 = 0; | |
48837e29 DE |
1972 | break; |
1973 | ||
065bbfe6 | 1974 | case CC_SET_ZN: |
1ccbefce | 1975 | /* Insn sets the Z,N flags of CC to recog_data.operand[0]. |
269c14e1 DE |
1976 | The V flag is unusable. The C flag may or may not be known but |
1977 | that's ok because alter_cond will change tests to use EQ/NE. */ | |
48837e29 | 1978 | CC_STATUS_INIT; |
269c14e1 | 1979 | cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY; |
d99c740f KH |
1980 | set = single_set (insn); |
1981 | cc_status.value1 = SET_SRC (set); | |
1982 | if (SET_DEST (set) != cc0_rtx) | |
1983 | cc_status.value2 = SET_DEST (set); | |
48837e29 DE |
1984 | break; |
1985 | ||
065bbfe6 | 1986 | case CC_SET_ZNV: |
1ccbefce | 1987 | /* Insn sets the Z,N,V flags of CC to recog_data.operand[0]. |
065bbfe6 JL |
1988 | The C flag may or may not be known but that's ok because |
1989 | alter_cond will change tests to use EQ/NE. */ | |
1990 | CC_STATUS_INIT; | |
1991 | cc_status.flags |= CC_NO_CARRY; | |
d99c740f KH |
1992 | set = single_set (insn); |
1993 | cc_status.value1 = SET_SRC (set); | |
1994 | if (SET_DEST (set) != cc0_rtx) | |
c8fcf20c KH |
1995 | { |
1996 | /* If the destination is STRICT_LOW_PART, strip off | |
1997 | STRICT_LOW_PART. */ | |
1998 | if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) | |
1999 | cc_status.value2 = XEXP (SET_DEST (set), 0); | |
2000 | else | |
2001 | cc_status.value2 = SET_DEST (set); | |
2002 | } | |
065bbfe6 JL |
2003 | break; |
2004 | ||
beed8fc0 AO |
2005 | case CC_COMPARE: |
2006 | /* The insn is a compare instruction. */ | |
2007 | CC_STATUS_INIT; | |
2008 | cc_status.value1 = SET_SRC (body); | |
2009 | break; | |
2010 | ||
2011 | case CC_CLOBBER: | |
2012 | /* Insn doesn't leave CC in a usable state. */ | |
2013 | CC_STATUS_INIT; | |
2014 | break; | |
2015 | } | |
2016 | } | |
beed8fc0 AO |
2017 | \f |
2018 | /* Given that X occurs in an address of the form (plus X constant), | |
2019 | return the part of X that is expected to be a register. There are | |
2020 | four kinds of addressing mode to recognize: | |
2021 | ||
2022 | @(dd,Rn) | |
2023 | @(dd,RnL.b) | |
2024 | @(dd,Rn.w) | |
2025 | @(dd,ERn.l) | |
2026 | ||
2027 | If SIZE is nonnull, and the address is one of the last three forms, | |
2028 | set *SIZE to the index multiplication factor. Set it to 0 for | |
2029 | plain @(dd,Rn) addresses. | |
2030 | ||
2031 | MODE is the mode of the value being accessed. It can be VOIDmode | |
2032 | if the address is known to be valid, but its mode is unknown. */ | |
2033 | ||
f52d97da | 2034 | static rtx |
beed8fc0 AO |
2035 | h8300_get_index (rtx x, enum machine_mode mode, int *size) |
2036 | { | |
2037 | int dummy, factor; | |
2038 | ||
2039 | if (size == 0) | |
2040 | size = &dummy; | |
2041 | ||
2042 | factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode)); | |
2043 | if (TARGET_H8300SX | |
2044 | && factor <= 4 | |
2045 | && (mode == VOIDmode | |
2046 | || GET_MODE_CLASS (mode) == MODE_INT | |
2047 | || GET_MODE_CLASS (mode) == MODE_FLOAT)) | |
2048 | { | |
2049 | if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND) | |
2050 | { | |
2051 | /* When accessing byte-sized values, the index can be | |
2052 | a zero-extended QImode or HImode register. */ | |
2053 | *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0))); | |
2054 | return XEXP (x, 0); | |
2055 | } | |
2056 | else | |
2057 | { | |
2058 | /* We're looking for addresses of the form: | |
2059 | ||
2060 | (mult X I) | |
2061 | or (mult (zero_extend X) I) | |
2062 | ||
2063 | where I is the size of the operand being accessed. | |
2064 | The canonical form of the second expression is: | |
2065 | ||
2066 | (and (mult (subreg X) I) J) | |
2067 | ||
2068 | where J == GET_MODE_MASK (GET_MODE (X)) * I. */ | |
2069 | rtx index; | |
2070 | ||
2071 | if (GET_CODE (x) == AND | |
2072 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2073 | && (factor == 0 | |
2074 | || INTVAL (XEXP (x, 1)) == 0xff * factor | |
2075 | || INTVAL (XEXP (x, 1)) == 0xffff * factor)) | |
2076 | { | |
2077 | index = XEXP (x, 0); | |
2078 | *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1); | |
2079 | } | |
2080 | else | |
2081 | { | |
2082 | index = x; | |
2083 | *size = 4; | |
2084 | } | |
2085 | ||
2086 | if (GET_CODE (index) == MULT | |
2087 | && GET_CODE (XEXP (index, 1)) == CONST_INT | |
2088 | && (factor == 0 || factor == INTVAL (XEXP (index, 1)))) | |
2089 | return XEXP (index, 0); | |
2090 | } | |
2091 | } | |
2092 | *size = 0; | |
2093 | return x; | |
2094 | } | |
2095 | \f | |
f52d97da AS |
2096 | /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. |
2097 | ||
2098 | On the H8/300, the predecrement and postincrement address depend thus | |
2099 | (the amount of decrement or increment being the length of the operand). */ | |
2100 | ||
2101 | static bool | |
2102 | h8300_mode_dependent_address_p (const_rtx addr) | |
2103 | { | |
2104 | if (GET_CODE (addr) == PLUS | |
2105 | && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0)) | |
2106 | return true; | |
2107 | ||
2108 | return false; | |
2109 | } | |
2110 | \f | |
beed8fc0 AO |
2111 | static const h8300_length_table addb_length_table = |
2112 | { | |
2113 | /* #xx Rs @aa @Rs @xx */ | |
2114 | { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */ | |
2115 | { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */ | |
2116 | { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */ | |
2117 | { 6, 4, 4, 4, 6 } /* add.b xx,@xx */ | |
2118 | }; | |
2119 | ||
2120 | static const h8300_length_table addw_length_table = | |
2121 | { | |
2122 | /* #xx Rs @aa @Rs @xx */ | |
2123 | { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */ | |
2124 | { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */ | |
2125 | { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */ | |
2126 | { 4, 4, 4, 4, 6 } /* add.w xx,@xx */ | |
2127 | }; | |
2128 | ||
2129 | static const h8300_length_table addl_length_table = | |
2130 | { | |
2131 | /* #xx Rs @aa @Rs @xx */ | |
2132 | { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */ | |
2133 | { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */ | |
2134 | { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */ | |
2135 | { 4, 4, 6, 6, 6 } /* add.l xx,@xx */ | |
2136 | }; | |
2137 | ||
2138 | #define logicb_length_table addb_length_table | |
2139 | #define logicw_length_table addw_length_table | |
2140 | ||
2141 | static const h8300_length_table logicl_length_table = | |
2142 | { | |
2143 | /* #xx Rs @aa @Rs @xx */ | |
2144 | { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */ | |
2145 | { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */ | |
2146 | { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */ | |
2147 | { 4, 4, 6, 6, 6 } /* and.l xx,@xx */ | |
2148 | }; | |
2149 | ||
2150 | static const h8300_length_table movb_length_table = | |
2151 | { | |
2152 | /* #xx Rs @aa @Rs @xx */ | |
2153 | { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */ | |
2154 | { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */ | |
2155 | { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */ | |
2156 | { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */ | |
2157 | }; | |
2158 | ||
2159 | #define movw_length_table movb_length_table | |
2160 | ||
2161 | static const h8300_length_table movl_length_table = | |
2162 | { | |
2163 | /* #xx Rs @aa @Rs @xx */ | |
2164 | { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */ | |
2165 | { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */ | |
2166 | { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */ | |
2167 | { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */ | |
2168 | }; | |
2169 | ||
2170 | /* Return the size of the given address or displacement constant. */ | |
2171 | ||
2172 | static unsigned int | |
2173 | h8300_constant_length (rtx constant) | |
2174 | { | |
2175 | /* Check for (@d:16,Reg). */ | |
2176 | if (GET_CODE (constant) == CONST_INT | |
2177 | && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff)) | |
2178 | return 2; | |
2179 | ||
2180 | /* Check for (@d:16,Reg) in cases where the displacement is | |
2181 | an absolute address. */ | |
2182 | if (Pmode == HImode || h8300_tiny_constant_address_p (constant)) | |
2183 | return 2; | |
2184 | ||
2185 | return 4; | |
2186 | } | |
2187 | ||
2188 | /* Return the size of a displacement field in address ADDR, which should | |
2189 | have the form (plus X constant). SIZE is the number of bytes being | |
2190 | accessed. */ | |
2191 | ||
2192 | static unsigned int | |
2193 | h8300_displacement_length (rtx addr, int size) | |
2194 | { | |
2195 | rtx offset; | |
2196 | ||
2197 | offset = XEXP (addr, 1); | |
2198 | ||
2199 | /* Check for @(d:2,Reg). */ | |
2200 | if (register_operand (XEXP (addr, 0), VOIDmode) | |
2201 | && GET_CODE (offset) == CONST_INT | |
2202 | && (INTVAL (offset) == size | |
2203 | || INTVAL (offset) == size * 2 | |
2204 | || INTVAL (offset) == size * 3)) | |
2205 | return 0; | |
2206 | ||
2207 | return h8300_constant_length (offset); | |
2208 | } | |
2209 | ||
0a2aaacc KG |
2210 | /* Store the class of operand OP in *OPCLASS and return the length of any |
2211 | extra operand fields. SIZE is the number of bytes in OP. OPCLASS | |
beed8fc0 AO |
2212 | can be null if only the length is needed. */ |
2213 | ||
2214 | static unsigned int | |
0a2aaacc | 2215 | h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass) |
beed8fc0 AO |
2216 | { |
2217 | enum h8300_operand_class dummy; | |
2218 | ||
0a2aaacc KG |
2219 | if (opclass == 0) |
2220 | opclass = &dummy; | |
beed8fc0 AO |
2221 | |
2222 | if (CONSTANT_P (op)) | |
2223 | { | |
0a2aaacc | 2224 | *opclass = H8OP_IMMEDIATE; |
beed8fc0 AO |
2225 | |
2226 | /* Byte-sized immediates are stored in the opcode fields. */ | |
2227 | if (size == 1) | |
2228 | return 0; | |
2229 | ||
2230 | /* If this is a 32-bit instruction, see whether the constant | |
2231 | will fit into a 16-bit immediate field. */ | |
2232 | if (TARGET_H8300SX | |
2233 | && size == 4 | |
2234 | && GET_CODE (op) == CONST_INT | |
2235 | && IN_RANGE (INTVAL (op), 0, 0xffff)) | |
2236 | return 2; | |
2237 | ||
2238 | return size; | |
2239 | } | |
2240 | else if (GET_CODE (op) == MEM) | |
2241 | { | |
2242 | op = XEXP (op, 0); | |
2243 | if (CONSTANT_P (op)) | |
2244 | { | |
0a2aaacc | 2245 | *opclass = H8OP_MEM_ABSOLUTE; |
beed8fc0 AO |
2246 | return h8300_constant_length (op); |
2247 | } | |
2248 | else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1))) | |
2249 | { | |
0a2aaacc | 2250 | *opclass = H8OP_MEM_COMPLEX; |
beed8fc0 AO |
2251 | return h8300_displacement_length (op, size); |
2252 | } | |
2253 | else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC) | |
2254 | { | |
0a2aaacc | 2255 | *opclass = H8OP_MEM_COMPLEX; |
beed8fc0 AO |
2256 | return 0; |
2257 | } | |
2258 | else if (register_operand (op, VOIDmode)) | |
2259 | { | |
0a2aaacc | 2260 | *opclass = H8OP_MEM_BASE; |
beed8fc0 AO |
2261 | return 0; |
2262 | } | |
2263 | } | |
8c440872 | 2264 | gcc_assert (register_operand (op, VOIDmode)); |
0a2aaacc | 2265 | *opclass = H8OP_REGISTER; |
8c440872 | 2266 | return 0; |
beed8fc0 AO |
2267 | } |
2268 | ||
2269 | /* Return the length of the instruction described by TABLE given that | |
2270 | its operands are OP1 and OP2. OP1 must be an h8300_dst_operand | |
2271 | and OP2 must be an h8300_src_operand. */ | |
2272 | ||
2273 | static unsigned int | |
2274 | h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table) | |
2275 | { | |
2276 | enum h8300_operand_class op1_class, op2_class; | |
2277 | unsigned int size, immediate_length; | |
2278 | ||
2279 | size = GET_MODE_SIZE (GET_MODE (op1)); | |
2280 | immediate_length = (h8300_classify_operand (op1, size, &op1_class) | |
2281 | + h8300_classify_operand (op2, size, &op2_class)); | |
2282 | return immediate_length + (*table)[op1_class - 1][op2_class]; | |
2283 | } | |
2284 | ||
2285 | /* Return the length of a unary instruction such as neg or not given that | |
2286 | its operand is OP. */ | |
2287 | ||
2288 | unsigned int | |
2289 | h8300_unary_length (rtx op) | |
2290 | { | |
0a2aaacc | 2291 | enum h8300_operand_class opclass; |
beed8fc0 AO |
2292 | unsigned int size, operand_length; |
2293 | ||
2294 | size = GET_MODE_SIZE (GET_MODE (op)); | |
0a2aaacc KG |
2295 | operand_length = h8300_classify_operand (op, size, &opclass); |
2296 | switch (opclass) | |
beed8fc0 AO |
2297 | { |
2298 | case H8OP_REGISTER: | |
2299 | return 2; | |
2300 | ||
2301 | case H8OP_MEM_BASE: | |
2302 | return (size == 4 ? 6 : 4); | |
2303 | ||
2304 | case H8OP_MEM_ABSOLUTE: | |
2305 | return operand_length + (size == 4 ? 6 : 4); | |
2306 | ||
2307 | case H8OP_MEM_COMPLEX: | |
2308 | return operand_length + 6; | |
2309 | ||
2310 | default: | |
8c440872 | 2311 | gcc_unreachable (); |
beed8fc0 AO |
2312 | } |
2313 | } | |
2314 | ||
2315 | /* Likewise short immediate instructions such as add.w #xx:3,OP. */ | |
2316 | ||
2317 | static unsigned int | |
2318 | h8300_short_immediate_length (rtx op) | |
2319 | { | |
0a2aaacc | 2320 | enum h8300_operand_class opclass; |
beed8fc0 AO |
2321 | unsigned int size, operand_length; |
2322 | ||
2323 | size = GET_MODE_SIZE (GET_MODE (op)); | |
0a2aaacc | 2324 | operand_length = h8300_classify_operand (op, size, &opclass); |
beed8fc0 | 2325 | |
0a2aaacc | 2326 | switch (opclass) |
beed8fc0 AO |
2327 | { |
2328 | case H8OP_REGISTER: | |
2329 | return 2; | |
2330 | ||
2331 | case H8OP_MEM_BASE: | |
2332 | case H8OP_MEM_ABSOLUTE: | |
2333 | case H8OP_MEM_COMPLEX: | |
2334 | return 4 + operand_length; | |
2335 | ||
2336 | default: | |
8c440872 | 2337 | gcc_unreachable (); |
beed8fc0 AO |
2338 | } |
2339 | } | |
2340 | ||
2341 | /* Likewise bitfield load and store instructions. */ | |
48837e29 | 2342 | |
beed8fc0 AO |
2343 | static unsigned int |
2344 | h8300_bitfield_length (rtx op, rtx op2) | |
2345 | { | |
0a2aaacc | 2346 | enum h8300_operand_class opclass; |
beed8fc0 AO |
2347 | unsigned int size, operand_length; |
2348 | ||
2349 | if (GET_CODE (op) == REG) | |
2350 | op = op2; | |
8c440872 | 2351 | gcc_assert (GET_CODE (op) != REG); |
beed8fc0 AO |
2352 | |
2353 | size = GET_MODE_SIZE (GET_MODE (op)); | |
0a2aaacc | 2354 | operand_length = h8300_classify_operand (op, size, &opclass); |
beed8fc0 | 2355 | |
0a2aaacc | 2356 | switch (opclass) |
beed8fc0 AO |
2357 | { |
2358 | case H8OP_MEM_BASE: | |
2359 | case H8OP_MEM_ABSOLUTE: | |
2360 | case H8OP_MEM_COMPLEX: | |
2361 | return 4 + operand_length; | |
2362 | ||
2363 | default: | |
8c440872 | 2364 | gcc_unreachable (); |
07aae5c2 | 2365 | } |
48837e29 DE |
2366 | } |
2367 | ||
beed8fc0 | 2368 | /* Calculate the length of general binary instruction INSN using TABLE. */ |
8ccf5d5f | 2369 | |
beed8fc0 AO |
2370 | static unsigned int |
2371 | h8300_binary_length (rtx insn, const h8300_length_table *table) | |
8ccf5d5f | 2372 | { |
beed8fc0 AO |
2373 | rtx set; |
2374 | ||
2375 | set = single_set (insn); | |
8c440872 | 2376 | gcc_assert (set); |
beed8fc0 AO |
2377 | |
2378 | if (BINARY_P (SET_SRC (set))) | |
2379 | return h8300_length_from_table (XEXP (SET_SRC (set), 0), | |
2380 | XEXP (SET_SRC (set), 1), table); | |
beed8fc0 | 2381 | else |
8c440872 NS |
2382 | { |
2383 | gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY); | |
2384 | return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0), | |
2385 | XEXP (XEXP (SET_SRC (set), 1), 1), | |
2386 | table); | |
2387 | } | |
8ccf5d5f KH |
2388 | } |
2389 | ||
beed8fc0 AO |
2390 | /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte |
2391 | memory reference and either (1) it has the form @(d:16,Rn) or | |
2392 | (2) its address has the code given by INC_CODE. */ | |
8ccf5d5f | 2393 | |
beed8fc0 AO |
2394 | static bool |
2395 | h8300_short_move_mem_p (rtx op, enum rtx_code inc_code) | |
8ccf5d5f | 2396 | { |
beed8fc0 AO |
2397 | rtx addr; |
2398 | unsigned int size; | |
2399 | ||
2400 | if (GET_CODE (op) != MEM) | |
2401 | return false; | |
2402 | ||
2403 | addr = XEXP (op, 0); | |
2404 | size = GET_MODE_SIZE (GET_MODE (op)); | |
2405 | if (size != 1 && size != 2) | |
2406 | return false; | |
2407 | ||
2408 | return (GET_CODE (addr) == inc_code | |
2409 | || (GET_CODE (addr) == PLUS | |
2410 | && GET_CODE (XEXP (addr, 0)) == REG | |
2411 | && h8300_displacement_length (addr, size) == 2)); | |
8ccf5d5f KH |
2412 | } |
2413 | ||
beed8fc0 AO |
2414 | /* Calculate the length of move instruction INSN using the given length |
2415 | table. Although the tables are correct for most cases, there is some | |
2416 | irregularity in the length of mov.b and mov.w. The following forms: | |
8ccf5d5f | 2417 | |
beed8fc0 AO |
2418 | mov @ERs+, Rd |
2419 | mov @(d:16,ERs), Rd | |
2420 | mov Rs, @-ERd | |
2421 | mov Rs, @(d:16,ERd) | |
2422 | ||
2423 | are two bytes shorter than most other "mov Rs, @complex" or | |
2424 | "mov @complex,Rd" combinations. */ | |
2425 | ||
2426 | static unsigned int | |
2427 | h8300_move_length (rtx *operands, const h8300_length_table *table) | |
8ccf5d5f | 2428 | { |
beed8fc0 AO |
2429 | unsigned int size; |
2430 | ||
2431 | size = h8300_length_from_table (operands[0], operands[1], table); | |
2432 | if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC)) | |
2433 | size -= 2; | |
2434 | if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC)) | |
2435 | size -= 2; | |
2436 | return size; | |
8ccf5d5f KH |
2437 | } |
2438 | ||
beed8fc0 AO |
2439 | /* Return the length of a mova instruction with the given operands. |
2440 | DEST is the register destination, SRC is the source address and | |
2441 | OFFSET is the 16-bit or 32-bit displacement. */ | |
2873836b | 2442 | |
beed8fc0 AO |
2443 | static unsigned int |
2444 | h8300_mova_length (rtx dest, rtx src, rtx offset) | |
2873836b | 2445 | { |
beed8fc0 AO |
2446 | unsigned int size; |
2447 | ||
2448 | size = (2 | |
2449 | + h8300_constant_length (offset) | |
2450 | + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0)); | |
2451 | if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest)) | |
2452 | size += 2; | |
2453 | return size; | |
2873836b KH |
2454 | } |
2455 | ||
beed8fc0 AO |
2456 | /* Compute the length of INSN based on its length_table attribute. |
2457 | OPERANDS is the array of its operands. */ | |
2873836b | 2458 | |
beed8fc0 AO |
2459 | unsigned int |
2460 | h8300_insn_length_from_table (rtx insn, rtx * operands) | |
2873836b | 2461 | { |
beed8fc0 AO |
2462 | switch (get_attr_length_table (insn)) |
2463 | { | |
2464 | case LENGTH_TABLE_NONE: | |
8c440872 | 2465 | gcc_unreachable (); |
beed8fc0 AO |
2466 | |
2467 | case LENGTH_TABLE_ADDB: | |
2468 | return h8300_binary_length (insn, &addb_length_table); | |
2469 | ||
2470 | case LENGTH_TABLE_ADDW: | |
2471 | return h8300_binary_length (insn, &addw_length_table); | |
2472 | ||
2473 | case LENGTH_TABLE_ADDL: | |
2474 | return h8300_binary_length (insn, &addl_length_table); | |
2475 | ||
2476 | case LENGTH_TABLE_LOGICB: | |
2477 | return h8300_binary_length (insn, &logicb_length_table); | |
2478 | ||
2479 | case LENGTH_TABLE_MOVB: | |
2480 | return h8300_move_length (operands, &movb_length_table); | |
2481 | ||
2482 | case LENGTH_TABLE_MOVW: | |
2483 | return h8300_move_length (operands, &movw_length_table); | |
2484 | ||
2485 | case LENGTH_TABLE_MOVL: | |
2486 | return h8300_move_length (operands, &movl_length_table); | |
2487 | ||
2488 | case LENGTH_TABLE_MOVA: | |
2489 | return h8300_mova_length (operands[0], operands[1], operands[2]); | |
2490 | ||
2491 | case LENGTH_TABLE_MOVA_ZERO: | |
2492 | return h8300_mova_length (operands[0], operands[1], const0_rtx); | |
2493 | ||
2494 | case LENGTH_TABLE_UNARY: | |
2495 | return h8300_unary_length (operands[0]); | |
2496 | ||
2497 | case LENGTH_TABLE_MOV_IMM4: | |
2498 | return 2 + h8300_classify_operand (operands[0], 0, 0); | |
2499 | ||
2500 | case LENGTH_TABLE_SHORT_IMMEDIATE: | |
2501 | return h8300_short_immediate_length (operands[0]); | |
2502 | ||
2503 | case LENGTH_TABLE_BITFIELD: | |
2504 | return h8300_bitfield_length (operands[0], operands[1]); | |
2505 | ||
2506 | case LENGTH_TABLE_BITBRANCH: | |
2507 | return h8300_bitfield_length (operands[1], operands[2]) - 2; | |
8c440872 NS |
2508 | |
2509 | default: | |
2510 | gcc_unreachable (); | |
beed8fc0 | 2511 | } |
2873836b KH |
2512 | } |
2513 | ||
beed8fc0 AO |
2514 | /* Return true if LHS and RHS are memory references that can be mapped |
2515 | to the same h8sx assembly operand. LHS appears as the destination of | |
2516 | an instruction and RHS appears as a source. | |
f9d2de4d | 2517 | |
beed8fc0 AO |
2518 | Three cases are allowed: |
2519 | ||
2520 | - RHS is @+Rn or @-Rn, LHS is @Rn | |
2521 | - RHS is @Rn, LHS is @Rn+ or @Rn- | |
2522 | - RHS and LHS have the same address and neither has side effects. */ | |
2523 | ||
2524 | bool | |
2525 | h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs) | |
f9d2de4d | 2526 | { |
beed8fc0 AO |
2527 | if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM) |
2528 | { | |
2529 | rhs = XEXP (rhs, 0); | |
2530 | lhs = XEXP (lhs, 0); | |
2531 | ||
2532 | if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC) | |
2533 | return rtx_equal_p (XEXP (rhs, 0), lhs); | |
2534 | ||
2535 | if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC) | |
2536 | return rtx_equal_p (rhs, XEXP (lhs, 0)); | |
2537 | ||
2538 | if (rtx_equal_p (rhs, lhs)) | |
2539 | return true; | |
2540 | } | |
2541 | return false; | |
f9d2de4d KH |
2542 | } |
2543 | ||
beed8fc0 AO |
2544 | /* Return true if OPERANDS[1] can be mapped to the same assembly |
2545 | operand as OPERANDS[0]. */ | |
f9d2de4d | 2546 | |
beed8fc0 AO |
2547 | bool |
2548 | h8300_operands_match_p (rtx *operands) | |
f9d2de4d | 2549 | { |
beed8fc0 AO |
2550 | if (register_operand (operands[0], VOIDmode) |
2551 | && register_operand (operands[1], VOIDmode)) | |
2552 | return true; | |
f9d2de4d | 2553 | |
beed8fc0 AO |
2554 | if (h8sx_mergeable_memrefs_p (operands[0], operands[1])) |
2555 | return true; | |
2556 | ||
2557 | return false; | |
f9d2de4d | 2558 | } |
beed8fc0 AO |
2559 | \f |
2560 | /* Try using movmd to move LENGTH bytes from memory region SRC to memory | |
2561 | region DEST. The two regions do not overlap and have the common | |
2562 | alignment given by ALIGNMENT. Return true on success. | |
717d8b71 | 2563 | |
beed8fc0 AO |
2564 | Using movmd for variable-length moves seems to involve some |
2565 | complex trade-offs. For instance: | |
b059c02a | 2566 | |
beed8fc0 AO |
2567 | - Preparing for a movmd instruction is similar to preparing |
2568 | for a memcpy. The main difference is that the arguments | |
2569 | are moved into er4, er5 and er6 rather than er0, er1 and er2. | |
2570 | ||
2571 | - Since movmd clobbers the frame pointer, we need to save | |
2572 | and restore it somehow when frame_pointer_needed. This can | |
2573 | sometimes make movmd sequences longer than calls to memcpy(). | |
2574 | ||
2575 | - The counter register is 16 bits, so the instruction is only | |
2576 | suitable for variable-length moves when sizeof (size_t) == 2. | |
2577 | That's only true in normal mode. | |
2578 | ||
2579 | - We will often lack static alignment information. Falling back | |
2580 | on movmd.b would likely be slower than calling memcpy(), at least | |
2581 | for big moves. | |
2582 | ||
2583 | This function therefore only uses movmd when the length is a | |
2584 | known constant, and only then if -fomit-frame-pointer is in | |
2585 | effect or if we're not optimizing for size. | |
2586 | ||
2587 | At the moment the function uses movmd for all in-range constants, | |
2588 | but it might be better to fall back on memcpy() for large moves | |
2589 | if ALIGNMENT == 1. */ | |
2590 | ||
2591 | bool | |
2592 | h8sx_emit_movmd (rtx dest, rtx src, rtx length, | |
2593 | HOST_WIDE_INT alignment) | |
b059c02a | 2594 | { |
beed8fc0 AO |
2595 | if (!flag_omit_frame_pointer && optimize_size) |
2596 | return false; | |
b059c02a | 2597 | |
beed8fc0 AO |
2598 | if (GET_CODE (length) == CONST_INT) |
2599 | { | |
2600 | rtx dest_reg, src_reg, first_dest, first_src; | |
2601 | HOST_WIDE_INT n; | |
2602 | int factor; | |
2603 | ||
2604 | /* Use movmd.l if the alignment allows it, otherwise fall back | |
2605 | on movmd.b. */ | |
2606 | factor = (alignment >= 2 ? 4 : 1); | |
2607 | ||
2608 | /* Make sure the length is within range. We can handle counter | |
2609 | values up to 65536, although HImode truncation will make | |
2610 | the count appear negative in rtl dumps. */ | |
2611 | n = INTVAL (length); | |
2612 | if (n <= 0 || n / factor > 65536) | |
2613 | return false; | |
2614 | ||
2615 | /* Create temporary registers for the source and destination | |
2616 | pointers. Initialize them to the start of each region. */ | |
2617 | dest_reg = copy_addr_to_reg (XEXP (dest, 0)); | |
2618 | src_reg = copy_addr_to_reg (XEXP (src, 0)); | |
2619 | ||
2620 | /* Create references to the movmd source and destination blocks. */ | |
2621 | first_dest = replace_equiv_address (dest, dest_reg); | |
2622 | first_src = replace_equiv_address (src, src_reg); | |
2623 | ||
2624 | set_mem_size (first_dest, GEN_INT (n & -factor)); | |
2625 | set_mem_size (first_src, GEN_INT (n & -factor)); | |
2626 | ||
2627 | length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode)); | |
2628 | emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor))); | |
2629 | ||
2630 | if ((n & -factor) != n) | |
2631 | { | |
2632 | /* Move SRC and DEST past the region we just copied. | |
2633 | This is done to update the memory attributes. */ | |
2634 | dest = adjust_address (dest, BLKmode, n & -factor); | |
2635 | src = adjust_address (src, BLKmode, n & -factor); | |
2636 | ||
2637 | /* Replace the addresses with the source and destination | |
2638 | registers, which movmd has left with the right values. */ | |
2639 | dest = replace_equiv_address (dest, dest_reg); | |
2640 | src = replace_equiv_address (src, src_reg); | |
2641 | ||
2642 | /* Mop up the left-over bytes. */ | |
2643 | if (n & 2) | |
2644 | emit_move_insn (adjust_address (dest, HImode, 0), | |
2645 | adjust_address (src, HImode, 0)); | |
2646 | if (n & 1) | |
2647 | emit_move_insn (adjust_address (dest, QImode, n & 2), | |
2648 | adjust_address (src, QImode, n & 2)); | |
2649 | } | |
2650 | return true; | |
2651 | } | |
2652 | return false; | |
b059c02a KH |
2653 | } |
2654 | ||
beed8fc0 | 2655 | /* Move ADDR into er6 after pushing its old value onto the stack. */ |
48837e29 | 2656 | |
beed8fc0 AO |
2657 | void |
2658 | h8300_swap_into_er6 (rtx addr) | |
48837e29 | 2659 | { |
beed8fc0 AO |
2660 | push (HARD_FRAME_POINTER_REGNUM); |
2661 | emit_move_insn (hard_frame_pointer_rtx, addr); | |
2662 | if (REGNO (addr) == SP_REG) | |
2663 | emit_move_insn (hard_frame_pointer_rtx, | |
2664 | plus_constant (hard_frame_pointer_rtx, | |
2665 | GET_MODE_SIZE (word_mode))); | |
2666 | } | |
07aae5c2 | 2667 | |
beed8fc0 AO |
2668 | /* Move the current value of er6 into ADDR and pop its old value |
2669 | from the stack. */ | |
2670 | ||
2671 | void | |
2672 | h8300_swap_out_of_er6 (rtx addr) | |
2673 | { | |
2674 | if (REGNO (addr) != SP_REG) | |
2675 | emit_move_insn (addr, hard_frame_pointer_rtx); | |
2676 | pop (HARD_FRAME_POINTER_REGNUM); | |
07aae5c2 | 2677 | } |
48837e29 | 2678 | \f |
7948a9ea KH |
2679 | /* Return the length of mov instruction. */ |
2680 | ||
2681 | unsigned int | |
2682 | compute_mov_length (rtx *operands) | |
2683 | { | |
2684 | /* If the mov instruction involves a memory operand, we compute the | |
2685 | length, assuming the largest addressing mode is used, and then | |
2686 | adjust later in the function. Otherwise, we compute and return | |
2687 | the exact length in one step. */ | |
2688 | enum machine_mode mode = GET_MODE (operands[0]); | |
2689 | rtx dest = operands[0]; | |
2690 | rtx src = operands[1]; | |
2691 | rtx addr; | |
2692 | ||
2693 | if (GET_CODE (src) == MEM) | |
2694 | addr = XEXP (src, 0); | |
2695 | else if (GET_CODE (dest) == MEM) | |
2696 | addr = XEXP (dest, 0); | |
2697 | else | |
2698 | addr = NULL_RTX; | |
2699 | ||
2700 | if (TARGET_H8300) | |
2701 | { | |
2702 | unsigned int base_length; | |
2703 | ||
2704 | switch (mode) | |
2705 | { | |
2706 | case QImode: | |
2707 | if (addr == NULL_RTX) | |
2708 | return 2; | |
2709 | ||
2710 | /* The eightbit addressing is available only in QImode, so | |
2711 | go ahead and take care of it. */ | |
2712 | if (h8300_eightbit_constant_address_p (addr)) | |
2713 | return 2; | |
2714 | ||
2715 | base_length = 4; | |
2716 | break; | |
2717 | ||
2718 | case HImode: | |
2719 | if (addr == NULL_RTX) | |
2720 | { | |
2721 | if (REG_P (src)) | |
2722 | return 2; | |
2723 | ||
2724 | if (src == const0_rtx) | |
2725 | return 2; | |
2726 | ||
2727 | return 4; | |
2728 | } | |
2729 | ||
2730 | base_length = 4; | |
2731 | break; | |
2732 | ||
2733 | case SImode: | |
2734 | if (addr == NULL_RTX) | |
2735 | { | |
2736 | if (REG_P (src)) | |
2737 | return 4; | |
2738 | ||
2739 | if (GET_CODE (src) == CONST_INT) | |
2740 | { | |
2741 | if (src == const0_rtx) | |
2742 | return 4; | |
2743 | ||
2744 | if ((INTVAL (src) & 0xffff) == 0) | |
2745 | return 6; | |
2746 | ||
2747 | if ((INTVAL (src) & 0xffff) == 0) | |
2748 | return 6; | |
f5139cc5 KH |
2749 | |
2750 | if ((INTVAL (src) & 0xffff) | |
2751 | == ((INTVAL (src) >> 16) & 0xffff)) | |
2752 | return 6; | |
7948a9ea KH |
2753 | } |
2754 | return 8; | |
2755 | } | |
2756 | ||
2757 | base_length = 8; | |
2758 | break; | |
2759 | ||
2760 | case SFmode: | |
2761 | if (addr == NULL_RTX) | |
2762 | { | |
2763 | if (REG_P (src)) | |
2764 | return 4; | |
2765 | ||
ceaaaeab | 2766 | if (satisfies_constraint_G (src)) |
2c4a71b3 KH |
2767 | return 4; |
2768 | ||
81983b04 | 2769 | return 8; |
7948a9ea KH |
2770 | } |
2771 | ||
2772 | base_length = 8; | |
2773 | break; | |
2774 | ||
2775 | default: | |
8c440872 | 2776 | gcc_unreachable (); |
7948a9ea KH |
2777 | } |
2778 | ||
2779 | /* Adjust the length based on the addressing mode used. | |
2780 | Specifically, we subtract the difference between the actual | |
2781 | length and the longest one, which is @(d:16,Rs). For SImode | |
2782 | and SFmode, we double the adjustment because two mov.w are | |
2783 | used to do the job. */ | |
2784 | ||
2785 | /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */ | |
2786 | if (GET_CODE (addr) == PRE_DEC | |
2787 | || GET_CODE (addr) == POST_INC) | |
2788 | { | |
2789 | if (mode == QImode || mode == HImode) | |
2790 | return base_length - 2; | |
2791 | else | |
2792 | /* In SImode and SFmode, we use two mov.w instructions, so | |
2a43945f | 2793 | double the adjustment. */ |
7948a9ea KH |
2794 | return base_length - 4; |
2795 | } | |
2796 | ||
2797 | /* @Rs and @Rd are 2 bytes shorter than the longest. Note that | |
2798 | in SImode and SFmode, the second mov.w involves an address | |
2799 | with displacement, namely @(2,Rs) or @(2,Rd), so we subtract | |
2800 | only 2 bytes. */ | |
2801 | if (GET_CODE (addr) == REG) | |
2802 | return base_length - 2; | |
2803 | ||
2804 | return base_length; | |
2805 | } | |
2806 | else | |
2807 | { | |
2808 | unsigned int base_length; | |
2809 | ||
2810 | switch (mode) | |
2811 | { | |
2812 | case QImode: | |
2813 | if (addr == NULL_RTX) | |
2814 | return 2; | |
2815 | ||
2816 | /* The eightbit addressing is available only in QImode, so | |
2817 | go ahead and take care of it. */ | |
2818 | if (h8300_eightbit_constant_address_p (addr)) | |
2819 | return 2; | |
2820 | ||
2821 | base_length = 8; | |
2822 | break; | |
2823 | ||
2824 | case HImode: | |
2825 | if (addr == NULL_RTX) | |
2826 | { | |
2827 | if (REG_P (src)) | |
2828 | return 2; | |
2829 | ||
2830 | if (src == const0_rtx) | |
2831 | return 2; | |
2832 | ||
2833 | return 4; | |
2834 | } | |
2835 | ||
2836 | base_length = 8; | |
2837 | break; | |
2838 | ||
2839 | case SImode: | |
2840 | if (addr == NULL_RTX) | |
2841 | { | |
2842 | if (REG_P (src)) | |
2843 | { | |
2844 | if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG) | |
2845 | return 4; | |
2846 | else | |
2847 | return 2; | |
2848 | } | |
2849 | ||
2850 | if (GET_CODE (src) == CONST_INT) | |
2851 | { | |
2852 | int val = INTVAL (src); | |
2853 | ||
2854 | if (val == 0) | |
2855 | return 2; | |
2856 | ||
2857 | if (val == (val & 0x00ff) || val == (val & 0xff00)) | |
2858 | return 4; | |
80e58519 | 2859 | |
7948a9ea KH |
2860 | switch (val & 0xffffffff) |
2861 | { | |
2862 | case 0xffffffff: | |
2863 | case 0xfffffffe: | |
2864 | case 0xfffffffc: | |
2865 | case 0x0000ffff: | |
2866 | case 0x0000fffe: | |
2867 | case 0xffff0000: | |
2868 | case 0xfffe0000: | |
2869 | case 0x00010000: | |
2870 | case 0x00020000: | |
2871 | return 4; | |
2872 | } | |
2873 | } | |
2874 | return 6; | |
2875 | } | |
2876 | ||
2877 | base_length = 10; | |
2878 | break; | |
2879 | ||
2880 | case SFmode: | |
2881 | if (addr == NULL_RTX) | |
2882 | { | |
2883 | if (REG_P (src)) | |
2884 | return 2; | |
2885 | ||
ceaaaeab | 2886 | if (satisfies_constraint_G (src)) |
7948a9ea | 2887 | return 2; |
2c4a71b3 | 2888 | |
7948a9ea KH |
2889 | return 6; |
2890 | } | |
2891 | ||
2892 | base_length = 10; | |
2893 | break; | |
2894 | ||
2895 | default: | |
8c440872 | 2896 | gcc_unreachable (); |
7948a9ea KH |
2897 | } |
2898 | ||
2899 | /* Adjust the length based on the addressing mode used. | |
2900 | Specifically, we subtract the difference between the actual | |
2901 | length and the longest one, which is @(d:24,ERs). */ | |
2902 | ||
2903 | /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */ | |
2904 | if (GET_CODE (addr) == PRE_DEC | |
2905 | || GET_CODE (addr) == POST_INC) | |
2906 | return base_length - 6; | |
2907 | ||
2908 | /* @ERs and @ERd are 6 bytes shorter than the longest. */ | |
2909 | if (GET_CODE (addr) == REG) | |
2910 | return base_length - 6; | |
2911 | ||
2912 | /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the | |
2913 | longest. */ | |
2914 | if (GET_CODE (addr) == PLUS | |
2915 | && GET_CODE (XEXP (addr, 0)) == REG | |
2916 | && GET_CODE (XEXP (addr, 1)) == CONST_INT | |
2917 | && INTVAL (XEXP (addr, 1)) > -32768 | |
2918 | && INTVAL (XEXP (addr, 1)) < 32767) | |
2919 | return base_length - 4; | |
2920 | ||
2921 | /* @aa:16 is 4 bytes shorter than the longest. */ | |
2922 | if (h8300_tiny_constant_address_p (addr)) | |
2923 | return base_length - 4; | |
2924 | ||
2925 | /* @aa:24 is 2 bytes shorter than the longest. */ | |
2926 | if (CONSTANT_P (addr)) | |
2927 | return base_length - 2; | |
2928 | ||
2929 | return base_length; | |
2930 | } | |
2931 | } | |
2932 | \f | |
e9eba255 KH |
2933 | /* Output an addition insn. */ |
2934 | ||
366a7b27 | 2935 | const char * |
cb713a8d | 2936 | output_plussi (rtx *operands) |
7d6ac401 KH |
2937 | { |
2938 | enum machine_mode mode = GET_MODE (operands[0]); | |
2939 | ||
8c440872 | 2940 | gcc_assert (mode == SImode); |
7d6ac401 KH |
2941 | |
2942 | if (TARGET_H8300) | |
2943 | { | |
cfedf91b KH |
2944 | if (GET_CODE (operands[2]) == REG) |
2945 | return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0"; | |
2946 | ||
2947 | if (GET_CODE (operands[2]) == CONST_INT) | |
2948 | { | |
2949 | HOST_WIDE_INT n = INTVAL (operands[2]); | |
2950 | ||
2951 | if ((n & 0xffffff) == 0) | |
2952 | return "add\t%z2,%z0"; | |
2953 | if ((n & 0xffff) == 0) | |
2954 | return "add\t%y2,%y0\n\taddx\t%z2,%z0"; | |
2955 | if ((n & 0xff) == 0) | |
2956 | return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0"; | |
2957 | } | |
2958 | ||
2959 | return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0"; | |
7d6ac401 KH |
2960 | } |
2961 | else | |
2962 | { | |
beed8fc0 AO |
2963 | if (GET_CODE (operands[2]) == CONST_INT |
2964 | && register_operand (operands[1], VOIDmode)) | |
7d6ac401 KH |
2965 | { |
2966 | HOST_WIDE_INT intval = INTVAL (operands[2]); | |
2967 | ||
beed8fc0 AO |
2968 | if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) |
2969 | return "add.l\t%S2,%S0"; | |
2970 | if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) | |
2971 | return "sub.l\t%G2,%S0"; | |
2972 | ||
7d6ac401 KH |
2973 | /* See if we can finish with 2 bytes. */ |
2974 | ||
9ac7ebba | 2975 | switch ((unsigned int) intval & 0xffffffff) |
7d6ac401 KH |
2976 | { |
2977 | case 0x00000001: | |
2978 | case 0x00000002: | |
2979 | case 0x00000004: | |
2980 | return "adds\t%2,%S0"; | |
2981 | ||
2982 | case 0xffffffff: | |
2983 | case 0xfffffffe: | |
2984 | case 0xfffffffc: | |
2985 | return "subs\t%G2,%S0"; | |
2986 | ||
2987 | case 0x00010000: | |
2988 | case 0x00020000: | |
2989 | operands[2] = GEN_INT (intval >> 16); | |
2990 | return "inc.w\t%2,%e0"; | |
2991 | ||
2992 | case 0xffff0000: | |
2993 | case 0xfffe0000: | |
2994 | operands[2] = GEN_INT (intval >> 16); | |
2995 | return "dec.w\t%G2,%e0"; | |
2996 | } | |
2997 | ||
2998 | /* See if we can finish with 4 bytes. */ | |
2999 | if ((intval & 0xffff) == 0) | |
3000 | { | |
3001 | operands[2] = GEN_INT (intval >> 16); | |
3002 | return "add.w\t%2,%e0"; | |
3003 | } | |
3004 | } | |
3005 | ||
beed8fc0 AO |
3006 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) |
3007 | { | |
3008 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
3009 | return "sub.l\t%S2,%S0"; | |
3010 | } | |
7d6ac401 KH |
3011 | return "add.l\t%S2,%S0"; |
3012 | } | |
3013 | } | |
3014 | ||
beed8fc0 AO |
3015 | /* ??? It would be much easier to add the h8sx stuff if a single function |
3016 | classified the addition as either inc/dec, adds/subs, add.w or add.l. */ | |
e9eba255 KH |
3017 | /* Compute the length of an addition insn. */ |
3018 | ||
7d6ac401 | 3019 | unsigned int |
cb713a8d | 3020 | compute_plussi_length (rtx *operands) |
7d6ac401 KH |
3021 | { |
3022 | enum machine_mode mode = GET_MODE (operands[0]); | |
3023 | ||
8c440872 | 3024 | gcc_assert (mode == SImode); |
7d6ac401 KH |
3025 | |
3026 | if (TARGET_H8300) | |
3027 | { | |
cfedf91b KH |
3028 | if (GET_CODE (operands[2]) == REG) |
3029 | return 6; | |
3030 | ||
3031 | if (GET_CODE (operands[2]) == CONST_INT) | |
3032 | { | |
3033 | HOST_WIDE_INT n = INTVAL (operands[2]); | |
3034 | ||
3035 | if ((n & 0xffffff) == 0) | |
3036 | return 2; | |
3037 | if ((n & 0xffff) == 0) | |
3038 | return 4; | |
3039 | if ((n & 0xff) == 0) | |
3040 | return 6; | |
3041 | } | |
3042 | ||
3043 | return 8; | |
7d6ac401 KH |
3044 | } |
3045 | else | |
3046 | { | |
beed8fc0 AO |
3047 | if (GET_CODE (operands[2]) == CONST_INT |
3048 | && register_operand (operands[1], VOIDmode)) | |
7d6ac401 KH |
3049 | { |
3050 | HOST_WIDE_INT intval = INTVAL (operands[2]); | |
3051 | ||
beed8fc0 AO |
3052 | if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) |
3053 | return 2; | |
3054 | if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) | |
3055 | return 2; | |
3056 | ||
7d6ac401 KH |
3057 | /* See if we can finish with 2 bytes. */ |
3058 | ||
9ac7ebba | 3059 | switch ((unsigned int) intval & 0xffffffff) |
7d6ac401 KH |
3060 | { |
3061 | case 0x00000001: | |
3062 | case 0x00000002: | |
3063 | case 0x00000004: | |
3064 | return 2; | |
3065 | ||
3066 | case 0xffffffff: | |
3067 | case 0xfffffffe: | |
3068 | case 0xfffffffc: | |
3069 | return 2; | |
3070 | ||
3071 | case 0x00010000: | |
3072 | case 0x00020000: | |
3073 | return 2; | |
3074 | ||
3075 | case 0xffff0000: | |
3076 | case 0xfffe0000: | |
3077 | return 2; | |
3078 | } | |
3079 | ||
3080 | /* See if we can finish with 4 bytes. */ | |
3081 | if ((intval & 0xffff) == 0) | |
3082 | return 4; | |
3083 | } | |
3084 | ||
beed8fc0 AO |
3085 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) |
3086 | return h8300_length_from_table (operands[0], | |
3087 | GEN_INT (-INTVAL (operands[2])), | |
3088 | &addl_length_table); | |
3089 | else | |
3090 | return h8300_length_from_table (operands[0], operands[2], | |
3091 | &addl_length_table); | |
7d6ac401 KH |
3092 | return 6; |
3093 | } | |
3094 | } | |
3095 | ||
e9eba255 KH |
3096 | /* Compute which flag bits are valid after an addition insn. */ |
3097 | ||
9690aa8e | 3098 | enum attr_cc |
cb713a8d | 3099 | compute_plussi_cc (rtx *operands) |
7d6ac401 KH |
3100 | { |
3101 | enum machine_mode mode = GET_MODE (operands[0]); | |
3102 | ||
8c440872 | 3103 | gcc_assert (mode == SImode); |
7d6ac401 KH |
3104 | |
3105 | if (TARGET_H8300) | |
3106 | { | |
cfedf91b | 3107 | return CC_CLOBBER; |
7d6ac401 KH |
3108 | } |
3109 | else | |
3110 | { | |
beed8fc0 AO |
3111 | if (GET_CODE (operands[2]) == CONST_INT |
3112 | && register_operand (operands[1], VOIDmode)) | |
7d6ac401 KH |
3113 | { |
3114 | HOST_WIDE_INT intval = INTVAL (operands[2]); | |
3115 | ||
beed8fc0 AO |
3116 | if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) |
3117 | return CC_SET_ZN; | |
3118 | if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) | |
3119 | return CC_SET_ZN; | |
3120 | ||
7d6ac401 KH |
3121 | /* See if we can finish with 2 bytes. */ |
3122 | ||
9ac7ebba | 3123 | switch ((unsigned int) intval & 0xffffffff) |
7d6ac401 KH |
3124 | { |
3125 | case 0x00000001: | |
3126 | case 0x00000002: | |
3127 | case 0x00000004: | |
3128 | return CC_NONE_0HIT; | |
3129 | ||
3130 | case 0xffffffff: | |
3131 | case 0xfffffffe: | |
3132 | case 0xfffffffc: | |
3133 | return CC_NONE_0HIT; | |
3134 | ||
3135 | case 0x00010000: | |
3136 | case 0x00020000: | |
3137 | return CC_CLOBBER; | |
3138 | ||
3139 | case 0xffff0000: | |
3140 | case 0xfffe0000: | |
3141 | return CC_CLOBBER; | |
3142 | } | |
3143 | ||
3144 | /* See if we can finish with 4 bytes. */ | |
3145 | if ((intval & 0xffff) == 0) | |
3146 | return CC_CLOBBER; | |
3147 | } | |
3148 | ||
3149 | return CC_SET_ZN; | |
3150 | } | |
3151 | } | |
3152 | \f | |
e9eba255 KH |
3153 | /* Output a logical insn. */ |
3154 | ||
7d6ac401 | 3155 | const char * |
cb713a8d | 3156 | output_logical_op (enum machine_mode mode, rtx *operands) |
366a7b27 | 3157 | { |
b42cff6b KH |
3158 | /* Figure out the logical op that we need to perform. */ |
3159 | enum rtx_code code = GET_CODE (operands[3]); | |
366a7b27 | 3160 | /* Pretend that every byte is affected if both operands are registers. */ |
7798db98 | 3161 | const unsigned HOST_WIDE_INT intval = |
366a7b27 | 3162 | (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT) |
beed8fc0 AO |
3163 | /* Always use the full instruction if the |
3164 | first operand is in memory. It is better | |
3165 | to use define_splits to generate the shorter | |
3166 | sequence where valid. */ | |
3167 | && register_operand (operands[1], VOIDmode) | |
366a7b27 KH |
3168 | ? INTVAL (operands[2]) : 0x55555555); |
3169 | /* The determinant of the algorithm. If we perform an AND, 0 | |
3170 | affects a bit. Otherwise, 1 affects a bit. */ | |
7798db98 | 3171 | const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval; |
f9ac2f95 KH |
3172 | /* Break up DET into pieces. */ |
3173 | const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff; | |
3174 | const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff; | |
c5e7ce43 KH |
3175 | const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff; |
3176 | const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff; | |
f9ac2f95 KH |
3177 | const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff; |
3178 | const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff; | |
3179 | int lower_half_easy_p = 0; | |
3180 | int upper_half_easy_p = 0; | |
366a7b27 KH |
3181 | /* The name of an insn. */ |
3182 | const char *opname; | |
3183 | char insn_buf[100]; | |
3184 | ||
3185 | switch (code) | |
3186 | { | |
3187 | case AND: | |
3188 | opname = "and"; | |
3189 | break; | |
3190 | case IOR: | |
3191 | opname = "or"; | |
3192 | break; | |
3193 | case XOR: | |
3194 | opname = "xor"; | |
3195 | break; | |
3196 | default: | |
8c440872 | 3197 | gcc_unreachable (); |
366a7b27 KH |
3198 | } |
3199 | ||
3200 | switch (mode) | |
3201 | { | |
3202 | case HImode: | |
3203 | /* First, see if we can finish with one insn. */ | |
3204 | if ((TARGET_H8300H || TARGET_H8300S) | |
c5e7ce43 KH |
3205 | && b0 != 0 |
3206 | && b1 != 0) | |
366a7b27 KH |
3207 | { |
3208 | sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname); | |
3209 | output_asm_insn (insn_buf, operands); | |
3210 | } | |
3211 | else | |
3212 | { | |
3213 | /* Take care of the lower byte. */ | |
c5e7ce43 | 3214 | if (b0 != 0) |
366a7b27 KH |
3215 | { |
3216 | sprintf (insn_buf, "%s\t%%s2,%%s0", opname); | |
3217 | output_asm_insn (insn_buf, operands); | |
3218 | } | |
3219 | /* Take care of the upper byte. */ | |
c5e7ce43 | 3220 | if (b1 != 0) |
366a7b27 KH |
3221 | { |
3222 | sprintf (insn_buf, "%s\t%%t2,%%t0", opname); | |
3223 | output_asm_insn (insn_buf, operands); | |
3224 | } | |
3225 | } | |
3226 | break; | |
3227 | case SImode: | |
f9ac2f95 KH |
3228 | if (TARGET_H8300H || TARGET_H8300S) |
3229 | { | |
3230 | /* Determine if the lower half can be taken care of in no more | |
3231 | than two bytes. */ | |
3232 | lower_half_easy_p = (b0 == 0 | |
3233 | || b1 == 0 | |
3234 | || (code != IOR && w0 == 0xffff)); | |
3235 | ||
3236 | /* Determine if the upper half can be taken care of in no more | |
3237 | than two bytes. */ | |
3238 | upper_half_easy_p = ((code != IOR && w1 == 0xffff) | |
3239 | || (code == AND && w1 == 0xff00)); | |
3240 | } | |
366a7b27 | 3241 | |
f9ac2f95 KH |
3242 | /* Check if doing everything with one insn is no worse than |
3243 | using multiple insns. */ | |
366a7b27 | 3244 | if ((TARGET_H8300H || TARGET_H8300S) |
f9ac2f95 | 3245 | && w0 != 0 && w1 != 0 |
472f2723 KH |
3246 | && !(lower_half_easy_p && upper_half_easy_p) |
3247 | && !(code == IOR && w1 == 0xffff | |
3248 | && (w0 & 0x8000) != 0 && lower_half_easy_p)) | |
366a7b27 KH |
3249 | { |
3250 | sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname); | |
3251 | output_asm_insn (insn_buf, operands); | |
3252 | } | |
3253 | else | |
3254 | { | |
3255 | /* Take care of the lower and upper words individually. For | |
3256 | each word, we try different methods in the order of | |
3257 | ||
3258 | 1) the special insn (in case of AND or XOR), | |
3259 | 2) the word-wise insn, and | |
3260 | 3) The byte-wise insn. */ | |
c5e7ce43 | 3261 | if (w0 == 0xffff |
6dfa4005 | 3262 | && (TARGET_H8300 ? (code == AND) : (code != IOR))) |
366a7b27 | 3263 | output_asm_insn ((code == AND) |
187462ac | 3264 | ? "sub.w\t%f0,%f0" : "not.w\t%f0", |
366a7b27 KH |
3265 | operands); |
3266 | else if ((TARGET_H8300H || TARGET_H8300S) | |
c5e7ce43 KH |
3267 | && (b0 != 0) |
3268 | && (b1 != 0)) | |
366a7b27 KH |
3269 | { |
3270 | sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname); | |
3271 | output_asm_insn (insn_buf, operands); | |
3272 | } | |
3273 | else | |
3274 | { | |
c5e7ce43 | 3275 | if (b0 != 0) |
366a7b27 KH |
3276 | { |
3277 | sprintf (insn_buf, "%s\t%%w2,%%w0", opname); | |
3278 | output_asm_insn (insn_buf, operands); | |
3279 | } | |
c5e7ce43 | 3280 | if (b1 != 0) |
366a7b27 KH |
3281 | { |
3282 | sprintf (insn_buf, "%s\t%%x2,%%x0", opname); | |
3283 | output_asm_insn (insn_buf, operands); | |
3284 | } | |
3285 | } | |
3286 | ||
c5e7ce43 | 3287 | if ((w1 == 0xffff) |
6dfa4005 | 3288 | && (TARGET_H8300 ? (code == AND) : (code != IOR))) |
366a7b27 | 3289 | output_asm_insn ((code == AND) |
187462ac | 3290 | ? "sub.w\t%e0,%e0" : "not.w\t%e0", |
366a7b27 | 3291 | operands); |
472f2723 KH |
3292 | else if ((TARGET_H8300H || TARGET_H8300S) |
3293 | && code == IOR | |
3294 | && w1 == 0xffff | |
3295 | && (w0 & 0x8000) != 0) | |
3296 | { | |
3297 | output_asm_insn ("exts.l\t%S0", operands); | |
3298 | } | |
a6e8d113 KH |
3299 | else if ((TARGET_H8300H || TARGET_H8300S) |
3300 | && code == AND | |
c5e7ce43 | 3301 | && w1 == 0xff00) |
a6e8d113 | 3302 | { |
dc5f17ec | 3303 | output_asm_insn ("extu.w\t%e0", operands); |
a6e8d113 | 3304 | } |
366a7b27 KH |
3305 | else if (TARGET_H8300H || TARGET_H8300S) |
3306 | { | |
c5e7ce43 | 3307 | if (w1 != 0) |
366a7b27 KH |
3308 | { |
3309 | sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname); | |
3310 | output_asm_insn (insn_buf, operands); | |
3311 | } | |
3312 | } | |
3313 | else | |
3314 | { | |
c5e7ce43 | 3315 | if (b2 != 0) |
366a7b27 KH |
3316 | { |
3317 | sprintf (insn_buf, "%s\t%%y2,%%y0", opname); | |
3318 | output_asm_insn (insn_buf, operands); | |
3319 | } | |
c5e7ce43 | 3320 | if (b3 != 0) |
366a7b27 KH |
3321 | { |
3322 | sprintf (insn_buf, "%s\t%%z2,%%z0", opname); | |
3323 | output_asm_insn (insn_buf, operands); | |
3324 | } | |
3325 | } | |
3326 | } | |
3327 | break; | |
3328 | default: | |
8c440872 | 3329 | gcc_unreachable (); |
366a7b27 KH |
3330 | } |
3331 | return ""; | |
3332 | } | |
40367e2d | 3333 | |
e9eba255 KH |
3334 | /* Compute the length of a logical insn. */ |
3335 | ||
40367e2d | 3336 | unsigned int |
cb713a8d | 3337 | compute_logical_op_length (enum machine_mode mode, rtx *operands) |
40367e2d | 3338 | { |
b42cff6b KH |
3339 | /* Figure out the logical op that we need to perform. */ |
3340 | enum rtx_code code = GET_CODE (operands[3]); | |
40367e2d | 3341 | /* Pretend that every byte is affected if both operands are registers. */ |
7798db98 | 3342 | const unsigned HOST_WIDE_INT intval = |
40367e2d | 3343 | (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT) |
beed8fc0 AO |
3344 | /* Always use the full instruction if the |
3345 | first operand is in memory. It is better | |
3346 | to use define_splits to generate the shorter | |
3347 | sequence where valid. */ | |
3348 | && register_operand (operands[1], VOIDmode) | |
40367e2d KH |
3349 | ? INTVAL (operands[2]) : 0x55555555); |
3350 | /* The determinant of the algorithm. If we perform an AND, 0 | |
3351 | affects a bit. Otherwise, 1 affects a bit. */ | |
7798db98 | 3352 | const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval; |
f9ac2f95 KH |
3353 | /* Break up DET into pieces. */ |
3354 | const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff; | |
3355 | const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff; | |
c5e7ce43 KH |
3356 | const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff; |
3357 | const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff; | |
f9ac2f95 KH |
3358 | const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff; |
3359 | const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff; | |
3360 | int lower_half_easy_p = 0; | |
3361 | int upper_half_easy_p = 0; | |
40367e2d KH |
3362 | /* Insn length. */ |
3363 | unsigned int length = 0; | |
3364 | ||
3365 | switch (mode) | |
3366 | { | |
3367 | case HImode: | |
3368 | /* First, see if we can finish with one insn. */ | |
3369 | if ((TARGET_H8300H || TARGET_H8300S) | |
c5e7ce43 KH |
3370 | && b0 != 0 |
3371 | && b1 != 0) | |
40367e2d | 3372 | { |
beed8fc0 AO |
3373 | length = h8300_length_from_table (operands[1], operands[2], |
3374 | &logicw_length_table); | |
40367e2d KH |
3375 | } |
3376 | else | |
3377 | { | |
3378 | /* Take care of the lower byte. */ | |
c5e7ce43 | 3379 | if (b0 != 0) |
40367e2d KH |
3380 | length += 2; |
3381 | ||
3382 | /* Take care of the upper byte. */ | |
c5e7ce43 | 3383 | if (b1 != 0) |
40367e2d KH |
3384 | length += 2; |
3385 | } | |
3386 | break; | |
3387 | case SImode: | |
f9ac2f95 KH |
3388 | if (TARGET_H8300H || TARGET_H8300S) |
3389 | { | |
3390 | /* Determine if the lower half can be taken care of in no more | |
3391 | than two bytes. */ | |
3392 | lower_half_easy_p = (b0 == 0 | |
3393 | || b1 == 0 | |
3394 | || (code != IOR && w0 == 0xffff)); | |
3395 | ||
3396 | /* Determine if the upper half can be taken care of in no more | |
3397 | than two bytes. */ | |
3398 | upper_half_easy_p = ((code != IOR && w1 == 0xffff) | |
3399 | || (code == AND && w1 == 0xff00)); | |
3400 | } | |
40367e2d | 3401 | |
f9ac2f95 KH |
3402 | /* Check if doing everything with one insn is no worse than |
3403 | using multiple insns. */ | |
40367e2d | 3404 | if ((TARGET_H8300H || TARGET_H8300S) |
f9ac2f95 | 3405 | && w0 != 0 && w1 != 0 |
472f2723 KH |
3406 | && !(lower_half_easy_p && upper_half_easy_p) |
3407 | && !(code == IOR && w1 == 0xffff | |
3408 | && (w0 & 0x8000) != 0 && lower_half_easy_p)) | |
40367e2d | 3409 | { |
beed8fc0 AO |
3410 | length = h8300_length_from_table (operands[1], operands[2], |
3411 | &logicl_length_table); | |
40367e2d KH |
3412 | } |
3413 | else | |
3414 | { | |
3415 | /* Take care of the lower and upper words individually. For | |
3416 | each word, we try different methods in the order of | |
3417 | ||
3418 | 1) the special insn (in case of AND or XOR), | |
3419 | 2) the word-wise insn, and | |
3420 | 3) The byte-wise insn. */ | |
c5e7ce43 | 3421 | if (w0 == 0xffff |
40367e2d KH |
3422 | && (TARGET_H8300 ? (code == AND) : (code != IOR))) |
3423 | { | |
3424 | length += 2; | |
3425 | } | |
3426 | else if ((TARGET_H8300H || TARGET_H8300S) | |
c5e7ce43 KH |
3427 | && (b0 != 0) |
3428 | && (b1 != 0)) | |
40367e2d KH |
3429 | { |
3430 | length += 4; | |
3431 | } | |
3432 | else | |
3433 | { | |
c5e7ce43 | 3434 | if (b0 != 0) |
40367e2d KH |
3435 | length += 2; |
3436 | ||
c5e7ce43 | 3437 | if (b1 != 0) |
40367e2d KH |
3438 | length += 2; |
3439 | } | |
3440 | ||
c5e7ce43 | 3441 | if (w1 == 0xffff |
40367e2d KH |
3442 | && (TARGET_H8300 ? (code == AND) : (code != IOR))) |
3443 | { | |
3444 | length += 2; | |
3445 | } | |
472f2723 KH |
3446 | else if ((TARGET_H8300H || TARGET_H8300S) |
3447 | && code == IOR | |
3448 | && w1 == 0xffff | |
3449 | && (w0 & 0x8000) != 0) | |
3450 | { | |
3451 | length += 2; | |
3452 | } | |
a6e8d113 KH |
3453 | else if ((TARGET_H8300H || TARGET_H8300S) |
3454 | && code == AND | |
c5e7ce43 | 3455 | && w1 == 0xff00) |
a6e8d113 KH |
3456 | { |
3457 | length += 2; | |
3458 | } | |
40367e2d KH |
3459 | else if (TARGET_H8300H || TARGET_H8300S) |
3460 | { | |
c5e7ce43 | 3461 | if (w1 != 0) |
40367e2d KH |
3462 | length += 4; |
3463 | } | |
3464 | else | |
3465 | { | |
c5e7ce43 | 3466 | if (b2 != 0) |
40367e2d KH |
3467 | length += 2; |
3468 | ||
c5e7ce43 | 3469 | if (b3 != 0) |
40367e2d KH |
3470 | length += 2; |
3471 | } | |
3472 | } | |
3473 | break; | |
3474 | default: | |
8c440872 | 3475 | gcc_unreachable (); |
40367e2d KH |
3476 | } |
3477 | return length; | |
3478 | } | |
b42cff6b | 3479 | |
e9eba255 KH |
3480 | /* Compute which flag bits are valid after a logical insn. */ |
3481 | ||
9690aa8e | 3482 | enum attr_cc |
cb713a8d | 3483 | compute_logical_op_cc (enum machine_mode mode, rtx *operands) |
b42cff6b KH |
3484 | { |
3485 | /* Figure out the logical op that we need to perform. */ | |
3486 | enum rtx_code code = GET_CODE (operands[3]); | |
3487 | /* Pretend that every byte is affected if both operands are registers. */ | |
7798db98 | 3488 | const unsigned HOST_WIDE_INT intval = |
b42cff6b | 3489 | (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT) |
beed8fc0 AO |
3490 | /* Always use the full instruction if the |
3491 | first operand is in memory. It is better | |
3492 | to use define_splits to generate the shorter | |
3493 | sequence where valid. */ | |
3494 | && register_operand (operands[1], VOIDmode) | |
b42cff6b KH |
3495 | ? INTVAL (operands[2]) : 0x55555555); |
3496 | /* The determinant of the algorithm. If we perform an AND, 0 | |
3497 | affects a bit. Otherwise, 1 affects a bit. */ | |
7798db98 | 3498 | const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval; |
f9ac2f95 KH |
3499 | /* Break up DET into pieces. */ |
3500 | const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff; | |
3501 | const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff; | |
3502 | const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff; | |
3503 | const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff; | |
3504 | int lower_half_easy_p = 0; | |
3505 | int upper_half_easy_p = 0; | |
b42cff6b KH |
3506 | /* Condition code. */ |
3507 | enum attr_cc cc = CC_CLOBBER; | |
3508 | ||
3509 | switch (mode) | |
3510 | { | |
3511 | case HImode: | |
3512 | /* First, see if we can finish with one insn. */ | |
3513 | if ((TARGET_H8300H || TARGET_H8300S) | |
c5e7ce43 KH |
3514 | && b0 != 0 |
3515 | && b1 != 0) | |
b42cff6b KH |
3516 | { |
3517 | cc = CC_SET_ZNV; | |
3518 | } | |
3519 | break; | |
3520 | case SImode: | |
f9ac2f95 KH |
3521 | if (TARGET_H8300H || TARGET_H8300S) |
3522 | { | |
3523 | /* Determine if the lower half can be taken care of in no more | |
3524 | than two bytes. */ | |
3525 | lower_half_easy_p = (b0 == 0 | |
3526 | || b1 == 0 | |
3527 | || (code != IOR && w0 == 0xffff)); | |
3528 | ||
3529 | /* Determine if the upper half can be taken care of in no more | |
3530 | than two bytes. */ | |
3531 | upper_half_easy_p = ((code != IOR && w1 == 0xffff) | |
3532 | || (code == AND && w1 == 0xff00)); | |
3533 | } | |
b42cff6b | 3534 | |
f9ac2f95 KH |
3535 | /* Check if doing everything with one insn is no worse than |
3536 | using multiple insns. */ | |
b42cff6b | 3537 | if ((TARGET_H8300H || TARGET_H8300S) |
f9ac2f95 | 3538 | && w0 != 0 && w1 != 0 |
472f2723 KH |
3539 | && !(lower_half_easy_p && upper_half_easy_p) |
3540 | && !(code == IOR && w1 == 0xffff | |
3541 | && (w0 & 0x8000) != 0 && lower_half_easy_p)) | |
b42cff6b KH |
3542 | { |
3543 | cc = CC_SET_ZNV; | |
3544 | } | |
472f2723 KH |
3545 | else |
3546 | { | |
3547 | if ((TARGET_H8300H || TARGET_H8300S) | |
3548 | && code == IOR | |
3549 | && w1 == 0xffff | |
3550 | && (w0 & 0x8000) != 0) | |
3551 | { | |
3552 | cc = CC_SET_ZNV; | |
3553 | } | |
3554 | } | |
b42cff6b KH |
3555 | break; |
3556 | default: | |
8c440872 | 3557 | gcc_unreachable (); |
b42cff6b KH |
3558 | } |
3559 | return cc; | |
3560 | } | |
366a7b27 | 3561 | \f |
8981ecd3 KH |
3562 | /* Expand a conditional branch. */ |
3563 | ||
3564 | void | |
f90b7a5a | 3565 | h8300_expand_branch (rtx operands[]) |
8981ecd3 | 3566 | { |
f90b7a5a PB |
3567 | enum rtx_code code = GET_CODE (operands[0]); |
3568 | rtx op0 = operands[1]; | |
3569 | rtx op1 = operands[2]; | |
3570 | rtx label = operands[3]; | |
8981ecd3 KH |
3571 | rtx tmp; |
3572 | ||
f90b7a5a PB |
3573 | tmp = gen_rtx_COMPARE (VOIDmode, op0, op1); |
3574 | emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp)); | |
3575 | ||
8981ecd3 KH |
3576 | tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx); |
3577 | tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, | |
3578 | gen_rtx_LABEL_REF (VOIDmode, label), | |
3579 | pc_rtx); | |
3580 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp)); | |
3581 | } | |
f90b7a5a PB |
3582 | |
3583 | ||
3584 | /* Expand a conditional store. */ | |
3585 | ||
3586 | void | |
3587 | h8300_expand_store (rtx operands[]) | |
3588 | { | |
3589 | rtx dest = operands[0]; | |
3590 | enum rtx_code code = GET_CODE (operands[1]); | |
3591 | rtx op0 = operands[2]; | |
3592 | rtx op1 = operands[3]; | |
3593 | rtx tmp; | |
3594 | ||
3595 | tmp = gen_rtx_COMPARE (VOIDmode, op0, op1); | |
3596 | emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp)); | |
3597 | ||
3598 | tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx); | |
3599 | emit_insn (gen_rtx_SET (VOIDmode, dest, tmp)); | |
3600 | } | |
8981ecd3 | 3601 | \f |
48837e29 DE |
3602 | /* Shifts. |
3603 | ||
005e3e05 KH |
3604 | We devote a fair bit of code to getting efficient shifts since we |
3605 | can only shift one bit at a time on the H8/300 and H8/300H and only | |
3db11b5c | 3606 | one or two bits at a time on the H8S. |
005e3e05 KH |
3607 | |
3608 | All shift code falls into one of the following ways of | |
3609 | implementation: | |
3610 | ||
3611 | o SHIFT_INLINE: Emit straight line code for the shift; this is used | |
3612 | when a straight line shift is about the same size or smaller than | |
3613 | a loop. | |
3614 | ||
3615 | o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask | |
3616 | off the bits we don't need. This is used when only a few of the | |
3617 | bits in the original value will survive in the shifted value. | |
3618 | ||
3619 | o SHIFT_SPECIAL: Often it's possible to move a byte or a word to | |
3620 | simulate a shift by 8, 16, or 24 bits. Once moved, a few inline | |
3621 | shifts can be added if the shift count is slightly more than 8 or | |
3622 | 16. This case also includes other oddballs that are not worth | |
f411c849 | 3623 | explaining here. |
005e3e05 | 3624 | |
3db11b5c | 3625 | o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts. |
005e3e05 | 3626 | |
5ec0b66e KH |
3627 | For each shift count, we try to use code that has no trade-off |
3628 | between code size and speed whenever possible. | |
3629 | ||
3630 | If the trade-off is unavoidable, we try to be reasonable. | |
3631 | Specifically, the fastest version is one instruction longer than | |
3632 | the shortest version, we take the fastest version. We also provide | |
3633 | the use a way to switch back to the shortest version with -Os. | |
3634 | ||
3635 | For the details of the shift algorithms for various shift counts, | |
3636 | refer to shift_alg_[qhs]i. */ | |
07aae5c2 | 3637 | |
beed8fc0 AO |
3638 | /* Classify a shift with the given mode and code. OP is the shift amount. */ |
3639 | ||
3640 | enum h8sx_shift_type | |
3641 | h8sx_classify_shift (enum machine_mode mode, enum rtx_code code, rtx op) | |
3642 | { | |
3643 | if (!TARGET_H8300SX) | |
3644 | return H8SX_SHIFT_NONE; | |
3645 | ||
3646 | switch (code) | |
3647 | { | |
3648 | case ASHIFT: | |
3649 | case LSHIFTRT: | |
3650 | /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */ | |
3651 | if (GET_CODE (op) != CONST_INT) | |
3652 | return H8SX_SHIFT_BINARY; | |
3653 | ||
3654 | /* Reject out-of-range shift amounts. */ | |
3655 | if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode)) | |
3656 | return H8SX_SHIFT_NONE; | |
3657 | ||
3658 | /* Power-of-2 shifts are effectively unary operations. */ | |
3659 | if (exact_log2 (INTVAL (op)) >= 0) | |
3660 | return H8SX_SHIFT_UNARY; | |
3661 | ||
3662 | return H8SX_SHIFT_BINARY; | |
3663 | ||
3664 | case ASHIFTRT: | |
3665 | if (op == const1_rtx || op == const2_rtx) | |
3666 | return H8SX_SHIFT_UNARY; | |
3667 | return H8SX_SHIFT_NONE; | |
3668 | ||
3669 | case ROTATE: | |
3670 | if (GET_CODE (op) == CONST_INT | |
3671 | && (INTVAL (op) == 1 | |
3672 | || INTVAL (op) == 2 | |
3673 | || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2 | |
3674 | || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1)) | |
3675 | return H8SX_SHIFT_UNARY; | |
3676 | return H8SX_SHIFT_NONE; | |
3677 | ||
3678 | default: | |
3679 | return H8SX_SHIFT_NONE; | |
3680 | } | |
3681 | } | |
3682 | ||
beed8fc0 AO |
3683 | /* Return the asm template for a single h8sx shift instruction. |
3684 | OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2] | |
3685 | is the source and OPERANDS[3] is the shift. SUFFIX is the | |
3686 | size suffix ('b', 'w' or 'l') and OPTYPE is the print_operand | |
3687 | prefix for the destination operand. */ | |
3688 | ||
3689 | const char * | |
3690 | output_h8sx_shift (rtx *operands, int suffix, int optype) | |
3691 | { | |
3692 | static char buffer[16]; | |
3693 | const char *stem; | |
3694 | ||
3695 | switch (GET_CODE (operands[3])) | |
3696 | { | |
3697 | case ASHIFT: | |
3698 | stem = "shll"; | |
3699 | break; | |
3700 | ||
3701 | case ASHIFTRT: | |
3702 | stem = "shar"; | |
3703 | break; | |
3704 | ||
3705 | case LSHIFTRT: | |
3706 | stem = "shlr"; | |
3707 | break; | |
3708 | ||
3709 | case ROTATE: | |
3710 | stem = "rotl"; | |
3711 | if (INTVAL (operands[2]) > 2) | |
3712 | { | |
3713 | /* This is really a right rotate. */ | |
3714 | operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0])) | |
3715 | - INTVAL (operands[2])); | |
3716 | stem = "rotr"; | |
3717 | } | |
3718 | break; | |
3719 | ||
3720 | default: | |
8c440872 | 3721 | gcc_unreachable (); |
beed8fc0 AO |
3722 | } |
3723 | if (operands[2] == const1_rtx) | |
3724 | sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype); | |
3725 | else | |
3726 | sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype); | |
3727 | return buffer; | |
3728 | } | |
48837e29 | 3729 | |
317d21e9 | 3730 | /* Emit code to do shifts. */ |
48837e29 | 3731 | |
beed8fc0 | 3732 | bool |
9690aa8e | 3733 | expand_a_shift (enum machine_mode mode, enum rtx_code code, rtx operands[]) |
07aae5c2 | 3734 | { |
beed8fc0 AO |
3735 | switch (h8sx_classify_shift (mode, code, operands[2])) |
3736 | { | |
3737 | case H8SX_SHIFT_BINARY: | |
3738 | operands[1] = force_reg (mode, operands[1]); | |
3739 | return false; | |
3740 | ||
3741 | case H8SX_SHIFT_UNARY: | |
3742 | return false; | |
3743 | ||
3744 | case H8SX_SHIFT_NONE: | |
3745 | break; | |
3746 | } | |
3747 | ||
bc9b880c | 3748 | emit_move_insn (copy_rtx (operands[0]), operands[1]); |
07aae5c2 | 3749 | |
07e4d94e KH |
3750 | /* Need a loop to get all the bits we want - we generate the |
3751 | code at emit time, but need to allocate a scratch reg now. */ | |
48837e29 | 3752 | |
c5c76735 JL |
3753 | emit_insn (gen_rtx_PARALLEL |
3754 | (VOIDmode, | |
48837e29 | 3755 | gen_rtvec (2, |
bc9b880c | 3756 | gen_rtx_SET (VOIDmode, copy_rtx (operands[0]), |
0f4c242b | 3757 | gen_rtx_fmt_ee (code, mode, |
bc9b880c | 3758 | copy_rtx (operands[0]), operands[2])), |
c5c76735 JL |
3759 | gen_rtx_CLOBBER (VOIDmode, |
3760 | gen_rtx_SCRATCH (QImode))))); | |
beed8fc0 | 3761 | return true; |
48837e29 DE |
3762 | } |
3763 | ||
48837e29 DE |
3764 | /* Symbols of the various modes which can be used as indices. */ |
3765 | ||
3766 | enum shift_mode | |
1a63219b KH |
3767 | { |
3768 | QIshift, HIshift, SIshift | |
3769 | }; | |
48837e29 | 3770 | |
269c14e1 DE |
3771 | /* For single bit shift insns, record assembler and what bits of the |
3772 | condition code are valid afterwards (represented as various CC_FOO | |
3773 | bits, 0 means CC isn't left in a usable state). */ | |
48837e29 DE |
3774 | |
3775 | struct shift_insn | |
3776 | { | |
8b60264b | 3777 | const char *const assembler; |
9690aa8e | 3778 | const enum attr_cc cc_valid; |
48837e29 DE |
3779 | }; |
3780 | ||
3781 | /* Assembler instruction shift table. | |
3782 | ||
3783 | These tables are used to look up the basic shifts. | |
07e4d94e | 3784 | They are indexed by cpu, shift_type, and mode. */ |
07aae5c2 | 3785 | |
48837e29 DE |
3786 | static const struct shift_insn shift_one[2][3][3] = |
3787 | { | |
3788 | /* H8/300 */ | |
3789 | { | |
3790 | /* SHIFT_ASHIFT */ | |
3791 | { | |
45ca2106 KH |
3792 | { "shll\t%X0", CC_SET_ZNV }, |
3793 | { "add.w\t%T0,%T0", CC_SET_ZN }, | |
3794 | { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER } | |
48837e29 DE |
3795 | }, |
3796 | /* SHIFT_LSHIFTRT */ | |
3797 | { | |
45ca2106 KH |
3798 | { "shlr\t%X0", CC_SET_ZNV }, |
3799 | { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER }, | |
3800 | { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER } | |
48837e29 DE |
3801 | }, |
3802 | /* SHIFT_ASHIFTRT */ | |
3803 | { | |
45ca2106 KH |
3804 | { "shar\t%X0", CC_SET_ZNV }, |
3805 | { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER }, | |
3806 | { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER } | |
48837e29 DE |
3807 | } |
3808 | }, | |
3809 | /* H8/300H */ | |
3810 | { | |
3811 | /* SHIFT_ASHIFT */ | |
3812 | { | |
45ca2106 KH |
3813 | { "shll.b\t%X0", CC_SET_ZNV }, |
3814 | { "shll.w\t%T0", CC_SET_ZNV }, | |
3815 | { "shll.l\t%S0", CC_SET_ZNV } | |
48837e29 DE |
3816 | }, |
3817 | /* SHIFT_LSHIFTRT */ | |
3818 | { | |
45ca2106 KH |
3819 | { "shlr.b\t%X0", CC_SET_ZNV }, |
3820 | { "shlr.w\t%T0", CC_SET_ZNV }, | |
3821 | { "shlr.l\t%S0", CC_SET_ZNV } | |
48837e29 DE |
3822 | }, |
3823 | /* SHIFT_ASHIFTRT */ | |
3824 | { | |
45ca2106 KH |
3825 | { "shar.b\t%X0", CC_SET_ZNV }, |
3826 | { "shar.w\t%T0", CC_SET_ZNV }, | |
3827 | { "shar.l\t%S0", CC_SET_ZNV } | |
48837e29 DE |
3828 | } |
3829 | } | |
3830 | }; | |
07aae5c2 | 3831 | |
51c0c1d7 JL |
3832 | static const struct shift_insn shift_two[3][3] = |
3833 | { | |
3834 | /* SHIFT_ASHIFT */ | |
3835 | { | |
45ca2106 KH |
3836 | { "shll.b\t#2,%X0", CC_SET_ZNV }, |
3837 | { "shll.w\t#2,%T0", CC_SET_ZNV }, | |
3838 | { "shll.l\t#2,%S0", CC_SET_ZNV } | |
51c0c1d7 JL |
3839 | }, |
3840 | /* SHIFT_LSHIFTRT */ | |
3841 | { | |
45ca2106 KH |
3842 | { "shlr.b\t#2,%X0", CC_SET_ZNV }, |
3843 | { "shlr.w\t#2,%T0", CC_SET_ZNV }, | |
3844 | { "shlr.l\t#2,%S0", CC_SET_ZNV } | |
51c0c1d7 JL |
3845 | }, |
3846 | /* SHIFT_ASHIFTRT */ | |
3847 | { | |
45ca2106 KH |
3848 | { "shar.b\t#2,%X0", CC_SET_ZNV }, |
3849 | { "shar.w\t#2,%T0", CC_SET_ZNV }, | |
3850 | { "shar.l\t#2,%S0", CC_SET_ZNV } | |
51c0c1d7 JL |
3851 | } |
3852 | }; | |
3853 | ||
48837e29 DE |
3854 | /* Rotates are organized by which shift they'll be used in implementing. |
3855 | There's no need to record whether the cc is valid afterwards because | |
3856 | it is the AND insn that will decide this. */ | |
07aae5c2 | 3857 | |
48837e29 DE |
3858 | static const char *const rotate_one[2][3][3] = |
3859 | { | |
3860 | /* H8/300 */ | |
3861 | { | |
3862 | /* SHIFT_ASHIFT */ | |
3863 | { | |
51c0c1d7 JL |
3864 | "rotr\t%X0", |
3865 | "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0", | |
48837e29 DE |
3866 | 0 |
3867 | }, | |
3868 | /* SHIFT_LSHIFTRT */ | |
3869 | { | |
51c0c1d7 JL |
3870 | "rotl\t%X0", |
3871 | "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0", | |
48837e29 DE |
3872 | 0 |
3873 | }, | |
3874 | /* SHIFT_ASHIFTRT */ | |
3875 | { | |
51c0c1d7 JL |
3876 | "rotl\t%X0", |
3877 | "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0", | |
48837e29 | 3878 | 0 |
07aae5c2 | 3879 | } |
48837e29 DE |
3880 | }, |
3881 | /* H8/300H */ | |
3882 | { | |
3883 | /* SHIFT_ASHIFT */ | |
3884 | { | |
51c0c1d7 JL |
3885 | "rotr.b\t%X0", |
3886 | "rotr.w\t%T0", | |
3887 | "rotr.l\t%S0" | |
48837e29 DE |
3888 | }, |
3889 | /* SHIFT_LSHIFTRT */ | |
07aae5c2 | 3890 | { |
51c0c1d7 JL |
3891 | "rotl.b\t%X0", |
3892 | "rotl.w\t%T0", | |
3893 | "rotl.l\t%S0" | |
48837e29 DE |
3894 | }, |
3895 | /* SHIFT_ASHIFTRT */ | |
3896 | { | |
51c0c1d7 JL |
3897 | "rotl.b\t%X0", |
3898 | "rotl.w\t%T0", | |
3899 | "rotl.l\t%S0" | |
48837e29 DE |
3900 | } |
3901 | } | |
3902 | }; | |
3903 | ||
51c0c1d7 JL |
3904 | static const char *const rotate_two[3][3] = |
3905 | { | |
3906 | /* SHIFT_ASHIFT */ | |
3907 | { | |
3908 | "rotr.b\t#2,%X0", | |
3909 | "rotr.w\t#2,%T0", | |
3910 | "rotr.l\t#2,%S0" | |
3911 | }, | |
3912 | /* SHIFT_LSHIFTRT */ | |
3913 | { | |
3914 | "rotl.b\t#2,%X0", | |
3915 | "rotl.w\t#2,%T0", | |
3916 | "rotl.l\t#2,%S0" | |
3917 | }, | |
3918 | /* SHIFT_ASHIFTRT */ | |
3919 | { | |
3920 | "rotl.b\t#2,%X0", | |
3921 | "rotl.w\t#2,%T0", | |
3922 | "rotl.l\t#2,%S0" | |
3923 | } | |
3924 | }; | |
3925 | ||
35fb3d1f KH |
3926 | struct shift_info { |
3927 | /* Shift algorithm. */ | |
3928 | enum shift_alg alg; | |
3929 | ||
3930 | /* The number of bits to be shifted by shift1 and shift2. Valid | |
3931 | when ALG is SHIFT_SPECIAL. */ | |
3932 | unsigned int remainder; | |
3933 | ||
3934 | /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */ | |
3935 | const char *special; | |
3936 | ||
3937 | /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE | |
9cd10576 | 3938 | or SHIFT_SPECIAL, and REMAINDER is nonzero. */ |
35fb3d1f KH |
3939 | const char *shift1; |
3940 | ||
3941 | /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE | |
9cd10576 | 3942 | or SHIFT_SPECIAL, and REMAINDER is nonzero. */ |
35fb3d1f KH |
3943 | const char *shift2; |
3944 | ||
45ca2106 | 3945 | /* CC status for SHIFT_INLINE. */ |
9690aa8e | 3946 | enum attr_cc cc_inline; |
45ca2106 KH |
3947 | |
3948 | /* CC status for SHIFT_SPECIAL. */ | |
9690aa8e | 3949 | enum attr_cc cc_special; |
35fb3d1f KH |
3950 | }; |
3951 | ||
cb713a8d KH |
3952 | static void get_shift_alg (enum shift_type, |
3953 | enum shift_mode, unsigned int, | |
3954 | struct shift_info *); | |
441d04c6 | 3955 | |
c009a745 KH |
3956 | /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the |
3957 | best algorithm for doing the shift. The assembler code is stored | |
5ec0b66e KH |
3958 | in the pointers in INFO. We achieve the maximum efficiency in most |
3959 | cases when !TARGET_H8300. In case of TARGET_H8300, shifts in | |
3960 | SImode in particular have a lot of room to optimize. | |
3961 | ||
3962 | We first determine the strategy of the shift algorithm by a table | |
3963 | lookup. If that tells us to use a hand crafted assembly code, we | |
3964 | go into the big switch statement to find what that is. Otherwise, | |
3965 | we resort to a generic way, such as inlining. In either case, the | |
3966 | result is returned through INFO. */ | |
48837e29 | 3967 | |
cb33eb17 | 3968 | static void |
cb713a8d KH |
3969 | get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode, |
3970 | unsigned int count, struct shift_info *info) | |
48837e29 | 3971 | { |
b9b575e6 | 3972 | enum h8_cpu cpu; |
769828ab KH |
3973 | |
3974 | /* Find the target CPU. */ | |
3975 | if (TARGET_H8300) | |
b9b575e6 | 3976 | cpu = H8_300; |
769828ab | 3977 | else if (TARGET_H8300H) |
b9b575e6 | 3978 | cpu = H8_300H; |
769828ab | 3979 | else |
b9b575e6 | 3980 | cpu = H8_S; |
769828ab | 3981 | |
96eaf358 | 3982 | /* Find the shift algorithm. */ |
b9b575e6 | 3983 | info->alg = SHIFT_LOOP; |
48837e29 DE |
3984 | switch (shift_mode) |
3985 | { | |
3986 | case QIshift: | |
b9b575e6 | 3987 | if (count < GET_MODE_BITSIZE (QImode)) |
96eaf358 KH |
3988 | info->alg = shift_alg_qi[cpu][shift_type][count]; |
3989 | break; | |
769828ab | 3990 | |
96eaf358 | 3991 | case HIshift: |
b9b575e6 | 3992 | if (count < GET_MODE_BITSIZE (HImode)) |
96eaf358 KH |
3993 | info->alg = shift_alg_hi[cpu][shift_type][count]; |
3994 | break; | |
3995 | ||
3996 | case SIshift: | |
b9b575e6 | 3997 | if (count < GET_MODE_BITSIZE (SImode)) |
96eaf358 KH |
3998 | info->alg = shift_alg_si[cpu][shift_type][count]; |
3999 | break; | |
4000 | ||
4001 | default: | |
8c440872 | 4002 | gcc_unreachable (); |
96eaf358 KH |
4003 | } |
4004 | ||
4005 | /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */ | |
4006 | switch (info->alg) | |
4007 | { | |
4008 | case SHIFT_INLINE: | |
4009 | info->remainder = count; | |
4010 | /* Fall through. */ | |
4011 | ||
4012 | case SHIFT_LOOP: | |
4013 | /* It is up to the caller to know that looping clobbers cc. */ | |
4014 | info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler; | |
4015 | info->shift2 = shift_two[shift_type][shift_mode].assembler; | |
45ca2106 | 4016 | info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid; |
96eaf358 KH |
4017 | goto end; |
4018 | ||
4019 | case SHIFT_ROT_AND: | |
4020 | info->shift1 = rotate_one[cpu_type][shift_type][shift_mode]; | |
4021 | info->shift2 = rotate_two[shift_type][shift_mode]; | |
45ca2106 | 4022 | info->cc_inline = CC_CLOBBER; |
96eaf358 KH |
4023 | goto end; |
4024 | ||
4025 | case SHIFT_SPECIAL: | |
4026 | /* REMAINDER is 0 for most cases, so initialize it to 0. */ | |
4027 | info->remainder = 0; | |
4028 | info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler; | |
4029 | info->shift2 = shift_two[shift_type][shift_mode].assembler; | |
45ca2106 KH |
4030 | info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid; |
4031 | info->cc_special = CC_CLOBBER; | |
96eaf358 KH |
4032 | break; |
4033 | } | |
51c0c1d7 | 4034 | |
96eaf358 KH |
4035 | /* Here we only deal with SHIFT_SPECIAL. */ |
4036 | switch (shift_mode) | |
4037 | { | |
4038 | case QIshift: | |
769828ab KH |
4039 | /* For ASHIFTRT by 7 bits, the sign bit is simply replicated |
4040 | through the entire value. */ | |
8c440872 NS |
4041 | gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7); |
4042 | info->special = "shll\t%X0\n\tsubx\t%X0,%X0"; | |
4043 | goto end; | |
769828ab KH |
4044 | |
4045 | case HIshift: | |
769828ab | 4046 | if (count == 7) |
51c0c1d7 | 4047 | { |
a77b1dbc | 4048 | switch (shift_type) |
51c0c1d7 | 4049 | { |
a77b1dbc KH |
4050 | case SHIFT_ASHIFT: |
4051 | if (TARGET_H8300) | |
4052 | info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0"; | |
4053 | else | |
4054 | info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0"; | |
692b7eb3 | 4055 | goto end; |
a77b1dbc KH |
4056 | case SHIFT_LSHIFTRT: |
4057 | if (TARGET_H8300) | |
4058 | info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0"; | |
4059 | else | |
4060 | info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0"; | |
692b7eb3 | 4061 | goto end; |
a77b1dbc | 4062 | case SHIFT_ASHIFTRT: |
35fb3d1f | 4063 | info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0"; |
692b7eb3 | 4064 | goto end; |
48837e29 | 4065 | } |
07aae5c2 | 4066 | } |
b30686ec | 4067 | else if ((8 <= count && count <= 13) |
a38b3eea | 4068 | || (TARGET_H8300S && count == 14)) |
07aae5c2 | 4069 | { |
a7812c0b KH |
4070 | info->remainder = count - 8; |
4071 | ||
51c0c1d7 | 4072 | switch (shift_type) |
48837e29 | 4073 | { |
51c0c1d7 | 4074 | case SHIFT_ASHIFT: |
35fb3d1f | 4075 | info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0"; |
692b7eb3 | 4076 | goto end; |
51c0c1d7 | 4077 | case SHIFT_LSHIFTRT: |
a7612343 KH |
4078 | if (TARGET_H8300) |
4079 | { | |
4080 | info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0"; | |
4081 | info->shift1 = "shlr.b\t%s0"; | |
45ca2106 | 4082 | info->cc_inline = CC_SET_ZNV; |
a7612343 KH |
4083 | } |
4084 | else | |
4085 | { | |
4086 | info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0"; | |
45ca2106 | 4087 | info->cc_special = CC_SET_ZNV; |
a7612343 | 4088 | } |
692b7eb3 | 4089 | goto end; |
51c0c1d7 JL |
4090 | case SHIFT_ASHIFTRT: |
4091 | if (TARGET_H8300) | |
a7612343 KH |
4092 | { |
4093 | info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0"; | |
4094 | info->shift1 = "shar.b\t%s0"; | |
a7612343 | 4095 | } |
51c0c1d7 | 4096 | else |
a7612343 KH |
4097 | { |
4098 | info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0"; | |
45ca2106 | 4099 | info->cc_special = CC_SET_ZNV; |
a7612343 | 4100 | } |
692b7eb3 | 4101 | goto end; |
51c0c1d7 JL |
4102 | } |
4103 | } | |
5e98fba2 DD |
4104 | else if (count == 14) |
4105 | { | |
4106 | switch (shift_type) | |
4107 | { | |
4108 | case SHIFT_ASHIFT: | |
4109 | if (TARGET_H8300) | |
4110 | info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0"; | |
4111 | goto end; | |
4112 | case SHIFT_LSHIFTRT: | |
4113 | if (TARGET_H8300) | |
4114 | info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0"; | |
4115 | goto end; | |
4116 | case SHIFT_ASHIFTRT: | |
4117 | if (TARGET_H8300) | |
4118 | info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0"; | |
4119 | else if (TARGET_H8300H) | |
45ca2106 KH |
4120 | { |
4121 | info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0"; | |
4122 | info->cc_special = CC_SET_ZNV; | |
4123 | } | |
5e98fba2 | 4124 | else /* TARGET_H8300S */ |
8c440872 | 4125 | gcc_unreachable (); |
5e98fba2 DD |
4126 | goto end; |
4127 | } | |
4128 | } | |
1e41e866 | 4129 | else if (count == 15) |
51c0c1d7 | 4130 | { |
1e41e866 KH |
4131 | switch (shift_type) |
4132 | { | |
4133 | case SHIFT_ASHIFT: | |
4134 | info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0"; | |
4135 | goto end; | |
4136 | case SHIFT_LSHIFTRT: | |
4137 | info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0"; | |
4138 | goto end; | |
4139 | case SHIFT_ASHIFTRT: | |
4140 | info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0"; | |
4141 | goto end; | |
4142 | } | |
07aae5c2 | 4143 | } |
8c440872 | 4144 | gcc_unreachable (); |
51c0c1d7 | 4145 | |
48837e29 | 4146 | case SIshift: |
1e41e866 | 4147 | if (TARGET_H8300 && 8 <= count && count <= 9) |
48837e29 | 4148 | { |
1e41e866 KH |
4149 | info->remainder = count - 8; |
4150 | ||
51c0c1d7 | 4151 | switch (shift_type) |
48837e29 | 4152 | { |
51c0c1d7 | 4153 | case SHIFT_ASHIFT: |
35fb3d1f | 4154 | info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0"; |
692b7eb3 | 4155 | goto end; |
51c0c1d7 | 4156 | case SHIFT_LSHIFTRT: |
35fb3d1f | 4157 | info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0"; |
1e41e866 | 4158 | info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0"; |
692b7eb3 | 4159 | goto end; |
51c0c1d7 | 4160 | case SHIFT_ASHIFTRT: |
35fb3d1f | 4161 | info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0"; |
692b7eb3 | 4162 | goto end; |
48837e29 | 4163 | } |
48837e29 | 4164 | } |
e6bcfef9 JS |
4165 | else if (count == 8 && !TARGET_H8300) |
4166 | { | |
4167 | switch (shift_type) | |
4168 | { | |
4169 | case SHIFT_ASHIFT: | |
35fb3d1f | 4170 | info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0"; |
692b7eb3 | 4171 | goto end; |
e6bcfef9 | 4172 | case SHIFT_LSHIFTRT: |
35fb3d1f | 4173 | info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0"; |
692b7eb3 | 4174 | goto end; |
e6bcfef9 | 4175 | case SHIFT_ASHIFTRT: |
35fb3d1f | 4176 | info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0"; |
692b7eb3 | 4177 | goto end; |
e6bcfef9 JS |
4178 | } |
4179 | } | |
1e41e866 KH |
4180 | else if (count == 15 && TARGET_H8300) |
4181 | { | |
4182 | switch (shift_type) | |
4183 | { | |
4184 | case SHIFT_ASHIFT: | |
8c440872 | 4185 | gcc_unreachable (); |
1e41e866 | 4186 | case SHIFT_LSHIFTRT: |
a35abc3c | 4187 | info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0"; |
1e41e866 KH |
4188 | goto end; |
4189 | case SHIFT_ASHIFTRT: | |
a35abc3c | 4190 | info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0"; |
1e41e866 KH |
4191 | goto end; |
4192 | } | |
4193 | } | |
dd69e230 KH |
4194 | else if (count == 15 && !TARGET_H8300) |
4195 | { | |
4196 | switch (shift_type) | |
4197 | { | |
4198 | case SHIFT_ASHIFT: | |
4199 | info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0"; | |
45ca2106 | 4200 | info->cc_special = CC_SET_ZNV; |
dd69e230 KH |
4201 | goto end; |
4202 | case SHIFT_LSHIFTRT: | |
18cf8dda | 4203 | info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0"; |
45ca2106 | 4204 | info->cc_special = CC_SET_ZNV; |
dd69e230 | 4205 | goto end; |
aefc5826 | 4206 | case SHIFT_ASHIFTRT: |
8c440872 | 4207 | gcc_unreachable (); |
dd69e230 KH |
4208 | } |
4209 | } | |
1e41e866 | 4210 | else if ((TARGET_H8300 && 16 <= count && count <= 20) |
a7812c0b | 4211 | || (TARGET_H8300H && 16 <= count && count <= 19) |
e0f19bd0 | 4212 | || (TARGET_H8300S && 16 <= count && count <= 21)) |
48837e29 | 4213 | { |
a7812c0b KH |
4214 | info->remainder = count - 16; |
4215 | ||
48837e29 DE |
4216 | switch (shift_type) |
4217 | { | |
4218 | case SHIFT_ASHIFT: | |
35fb3d1f | 4219 | info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0"; |
1e41e866 | 4220 | if (TARGET_H8300) |
b30686ec | 4221 | info->shift1 = "add.w\t%e0,%e0"; |
692b7eb3 | 4222 | goto end; |
51c0c1d7 | 4223 | case SHIFT_LSHIFTRT: |
1e41e866 KH |
4224 | if (TARGET_H8300) |
4225 | { | |
a7612343 KH |
4226 | info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0"; |
4227 | info->shift1 = "shlr\t%x0\n\trotxr\t%w0"; | |
1e41e866 KH |
4228 | } |
4229 | else | |
4230 | { | |
a7612343 | 4231 | info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0"; |
45ca2106 | 4232 | info->cc_special = CC_SET_ZNV; |
1e41e866 | 4233 | } |
692b7eb3 | 4234 | goto end; |
51c0c1d7 JL |
4235 | case SHIFT_ASHIFTRT: |
4236 | if (TARGET_H8300) | |
1e41e866 KH |
4237 | { |
4238 | info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0"; | |
4239 | info->shift1 = "shar\t%x0\n\trotxr\t%w0"; | |
4240 | } | |
51c0c1d7 | 4241 | else |
1e41e866 KH |
4242 | { |
4243 | info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0"; | |
45ca2106 | 4244 | info->cc_special = CC_SET_ZNV; |
1e41e866 | 4245 | } |
692b7eb3 | 4246 | goto end; |
51c0c1d7 JL |
4247 | } |
4248 | } | |
1e41e866 | 4249 | else if (TARGET_H8300 && 24 <= count && count <= 28) |
f9477efd KH |
4250 | { |
4251 | info->remainder = count - 24; | |
f0b6f9a6 | 4252 | |
f9477efd KH |
4253 | switch (shift_type) |
4254 | { | |
4255 | case SHIFT_ASHIFT: | |
4256 | info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0"; | |
4257 | info->shift1 = "shll.b\t%z0"; | |
45ca2106 | 4258 | info->cc_inline = CC_SET_ZNV; |
f9477efd KH |
4259 | goto end; |
4260 | case SHIFT_LSHIFTRT: | |
4261 | info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0"; | |
4262 | info->shift1 = "shlr.b\t%w0"; | |
45ca2106 | 4263 | info->cc_inline = CC_SET_ZNV; |
f9477efd KH |
4264 | goto end; |
4265 | case SHIFT_ASHIFTRT: | |
4266 | info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0"; | |
4267 | info->shift1 = "shar.b\t%w0"; | |
45ca2106 | 4268 | info->cc_inline = CC_SET_ZNV; |
7f473594 KH |
4269 | goto end; |
4270 | } | |
4271 | } | |
4a4ae922 KH |
4272 | else if ((TARGET_H8300H && count == 24) |
4273 | || (TARGET_H8300S && 24 <= count && count <= 25)) | |
e6bcfef9 | 4274 | { |
4a4ae922 KH |
4275 | info->remainder = count - 24; |
4276 | ||
e6bcfef9 JS |
4277 | switch (shift_type) |
4278 | { | |
4279 | case SHIFT_ASHIFT: | |
35fb3d1f | 4280 | info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0"; |
692b7eb3 | 4281 | goto end; |
e6bcfef9 | 4282 | case SHIFT_LSHIFTRT: |
35fb3d1f | 4283 | info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0"; |
45ca2106 | 4284 | info->cc_special = CC_SET_ZNV; |
692b7eb3 | 4285 | goto end; |
e6bcfef9 | 4286 | case SHIFT_ASHIFTRT: |
35fb3d1f | 4287 | info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0"; |
45ca2106 | 4288 | info->cc_special = CC_SET_ZNV; |
692b7eb3 | 4289 | goto end; |
e6bcfef9 JS |
4290 | } |
4291 | } | |
1e5bdc40 KH |
4292 | else if (!TARGET_H8300 && count == 28) |
4293 | { | |
4294 | switch (shift_type) | |
4295 | { | |
4296 | case SHIFT_ASHIFT: | |
4297 | if (TARGET_H8300H) | |
4298 | info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; | |
4299 | else | |
4300 | info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0"; | |
1e5bdc40 KH |
4301 | goto end; |
4302 | case SHIFT_LSHIFTRT: | |
4303 | if (TARGET_H8300H) | |
45ca2106 KH |
4304 | { |
4305 | info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; | |
4306 | info->cc_special = CC_SET_ZNV; | |
4307 | } | |
1e5bdc40 | 4308 | else |
a7612343 | 4309 | info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0"; |
1e5bdc40 KH |
4310 | goto end; |
4311 | case SHIFT_ASHIFTRT: | |
8c440872 | 4312 | gcc_unreachable (); |
1e5bdc40 KH |
4313 | } |
4314 | } | |
4315 | else if (!TARGET_H8300 && count == 29) | |
4316 | { | |
4317 | switch (shift_type) | |
4318 | { | |
4319 | case SHIFT_ASHIFT: | |
4320 | if (TARGET_H8300H) | |
4321 | info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; | |
4322 | else | |
4323 | info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; | |
1e5bdc40 KH |
4324 | goto end; |
4325 | case SHIFT_LSHIFTRT: | |
4326 | if (TARGET_H8300H) | |
45ca2106 KH |
4327 | { |
4328 | info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; | |
4329 | info->cc_special = CC_SET_ZNV; | |
4330 | } | |
1e5bdc40 | 4331 | else |
45ca2106 KH |
4332 | { |
4333 | info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; | |
4334 | info->cc_special = CC_SET_ZNV; | |
4335 | } | |
1e5bdc40 KH |
4336 | goto end; |
4337 | case SHIFT_ASHIFTRT: | |
8c440872 | 4338 | gcc_unreachable (); |
1e5bdc40 KH |
4339 | } |
4340 | } | |
4341 | else if (!TARGET_H8300 && count == 30) | |
4342 | { | |
4343 | switch (shift_type) | |
4344 | { | |
4345 | case SHIFT_ASHIFT: | |
4346 | if (TARGET_H8300H) | |
4347 | info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; | |
4348 | else | |
4349 | info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0"; | |
1e5bdc40 KH |
4350 | goto end; |
4351 | case SHIFT_LSHIFTRT: | |
4352 | if (TARGET_H8300H) | |
a7612343 | 4353 | info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; |
1e5bdc40 | 4354 | else |
a7612343 | 4355 | info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0"; |
1e5bdc40 KH |
4356 | goto end; |
4357 | case SHIFT_ASHIFTRT: | |
8c440872 | 4358 | gcc_unreachable (); |
1e5bdc40 KH |
4359 | } |
4360 | } | |
48837e29 DE |
4361 | else if (count == 31) |
4362 | { | |
dd69e230 | 4363 | if (TARGET_H8300) |
48837e29 | 4364 | { |
dd69e230 KH |
4365 | switch (shift_type) |
4366 | { | |
4367 | case SHIFT_ASHIFT: | |
4368 | info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0"; | |
4369 | goto end; | |
4370 | case SHIFT_LSHIFTRT: | |
4371 | info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0"; | |
4372 | goto end; | |
4373 | case SHIFT_ASHIFTRT: | |
4374 | info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0"; | |
4375 | goto end; | |
4376 | } | |
48837e29 DE |
4377 | } |
4378 | else | |
4379 | { | |
dd69e230 | 4380 | switch (shift_type) |
48837e29 | 4381 | { |
dd69e230 KH |
4382 | case SHIFT_ASHIFT: |
4383 | info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0"; | |
45ca2106 | 4384 | info->cc_special = CC_SET_ZNV; |
dd69e230 KH |
4385 | goto end; |
4386 | case SHIFT_LSHIFTRT: | |
4387 | info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0"; | |
45ca2106 | 4388 | info->cc_special = CC_SET_ZNV; |
dd69e230 KH |
4389 | goto end; |
4390 | case SHIFT_ASHIFTRT: | |
a7612343 | 4391 | info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0"; |
45ca2106 | 4392 | info->cc_special = CC_SET_ZNV; |
692b7eb3 | 4393 | goto end; |
48837e29 | 4394 | } |
48837e29 DE |
4395 | } |
4396 | } | |
8c440872 | 4397 | gcc_unreachable (); |
51c0c1d7 | 4398 | |
48837e29 | 4399 | default: |
8c440872 | 4400 | gcc_unreachable (); |
07aae5c2 | 4401 | } |
48837e29 | 4402 | |
cb33eb17 KH |
4403 | end: |
4404 | if (!TARGET_H8300S) | |
4405 | info->shift2 = NULL; | |
07aae5c2 SC |
4406 | } |
4407 | ||
be1e06df KH |
4408 | /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be |
4409 | needed for some shift with COUNT and MODE. Return 0 otherwise. */ | |
4410 | ||
4411 | int | |
cb713a8d | 4412 | h8300_shift_needs_scratch_p (int count, enum machine_mode mode) |
be1e06df | 4413 | { |
b9b575e6 | 4414 | enum h8_cpu cpu; |
be1e06df KH |
4415 | int a, lr, ar; |
4416 | ||
4417 | if (GET_MODE_BITSIZE (mode) <= count) | |
4418 | return 1; | |
4419 | ||
4420 | /* Find out the target CPU. */ | |
4421 | if (TARGET_H8300) | |
b9b575e6 | 4422 | cpu = H8_300; |
be1e06df | 4423 | else if (TARGET_H8300H) |
b9b575e6 | 4424 | cpu = H8_300H; |
be1e06df | 4425 | else |
b9b575e6 | 4426 | cpu = H8_S; |
be1e06df KH |
4427 | |
4428 | /* Find the shift algorithm. */ | |
4429 | switch (mode) | |
4430 | { | |
4431 | case QImode: | |
4432 | a = shift_alg_qi[cpu][SHIFT_ASHIFT][count]; | |
4433 | lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count]; | |
4434 | ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count]; | |
4435 | break; | |
4436 | ||
4437 | case HImode: | |
4438 | a = shift_alg_hi[cpu][SHIFT_ASHIFT][count]; | |
4439 | lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count]; | |
4440 | ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count]; | |
4441 | break; | |
4442 | ||
4443 | case SImode: | |
4444 | a = shift_alg_si[cpu][SHIFT_ASHIFT][count]; | |
4445 | lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count]; | |
4446 | ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count]; | |
4447 | break; | |
4448 | ||
4449 | default: | |
8c440872 | 4450 | gcc_unreachable (); |
be1e06df KH |
4451 | } |
4452 | ||
aa2fb4dd | 4453 | /* On H8/300H, count == 8 uses a scratch register. */ |
be1e06df | 4454 | return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP |
75a3503b | 4455 | || (TARGET_H8300H && mode == SImode && count == 8)); |
be1e06df KH |
4456 | } |
4457 | ||
e9eba255 | 4458 | /* Output the assembler code for doing shifts. */ |
48837e29 | 4459 | |
441d04c6 | 4460 | const char * |
cb713a8d | 4461 | output_a_shift (rtx *operands) |
07aae5c2 | 4462 | { |
48837e29 | 4463 | static int loopend_lab; |
48837e29 DE |
4464 | rtx shift = operands[3]; |
4465 | enum machine_mode mode = GET_MODE (shift); | |
4466 | enum rtx_code code = GET_CODE (shift); | |
4467 | enum shift_type shift_type; | |
4468 | enum shift_mode shift_mode; | |
35fb3d1f | 4469 | struct shift_info info; |
8c440872 | 4470 | int n; |
48837e29 DE |
4471 | |
4472 | loopend_lab++; | |
4473 | ||
4474 | switch (mode) | |
4475 | { | |
4476 | case QImode: | |
4477 | shift_mode = QIshift; | |
4478 | break; | |
4479 | case HImode: | |
4480 | shift_mode = HIshift; | |
4481 | break; | |
4482 | case SImode: | |
4483 | shift_mode = SIshift; | |
4484 | break; | |
4485 | default: | |
8c440872 | 4486 | gcc_unreachable (); |
48837e29 | 4487 | } |
07aae5c2 | 4488 | |
48837e29 | 4489 | switch (code) |
07aae5c2 | 4490 | { |
48837e29 DE |
4491 | case ASHIFTRT: |
4492 | shift_type = SHIFT_ASHIFTRT; | |
4493 | break; | |
4494 | case LSHIFTRT: | |
4495 | shift_type = SHIFT_LSHIFTRT; | |
4496 | break; | |
4497 | case ASHIFT: | |
4498 | shift_type = SHIFT_ASHIFT; | |
4499 | break; | |
4500 | default: | |
8c440872 | 4501 | gcc_unreachable (); |
48837e29 | 4502 | } |
07aae5c2 | 4503 | |
8c440872 NS |
4504 | /* This case must be taken care of by one of the two splitters |
4505 | that convert a variable shift into a loop. */ | |
4506 | gcc_assert (GET_CODE (operands[2]) == CONST_INT); | |
4507 | ||
4508 | n = INTVAL (operands[2]); | |
4509 | ||
4510 | /* If the count is negative, make it 0. */ | |
4511 | if (n < 0) | |
4512 | n = 0; | |
4513 | /* If the count is too big, truncate it. | |
4514 | ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to | |
4515 | do the intuitive thing. */ | |
4516 | else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) | |
4517 | n = GET_MODE_BITSIZE (mode); | |
4518 | ||
4519 | get_shift_alg (shift_type, shift_mode, n, &info); | |
4520 | ||
4521 | switch (info.alg) | |
48837e29 | 4522 | { |
8c440872 NS |
4523 | case SHIFT_SPECIAL: |
4524 | output_asm_insn (info.special, operands); | |
4525 | /* Fall through. */ | |
48837e29 | 4526 | |
8c440872 NS |
4527 | case SHIFT_INLINE: |
4528 | n = info.remainder; | |
48837e29 | 4529 | |
8c440872 NS |
4530 | /* Emit two bit shifts first. */ |
4531 | if (info.shift2 != NULL) | |
48837e29 | 4532 | { |
8c440872 NS |
4533 | for (; n > 1; n -= 2) |
4534 | output_asm_insn (info.shift2, operands); | |
4535 | } | |
51c0c1d7 | 4536 | |
8c440872 NS |
4537 | /* Now emit one bit shifts for any residual. */ |
4538 | for (; n > 0; n--) | |
4539 | output_asm_insn (info.shift1, operands); | |
4540 | return ""; | |
4541 | ||
4542 | case SHIFT_ROT_AND: | |
4543 | { | |
4544 | int m = GET_MODE_BITSIZE (mode) - n; | |
4545 | const int mask = (shift_type == SHIFT_ASHIFT | |
4546 | ? ((1 << m) - 1) << n | |
4547 | : (1 << m) - 1); | |
4548 | char insn_buf[200]; | |
4549 | ||
4550 | /* Not all possibilities of rotate are supported. They shouldn't | |
4551 | be generated, but let's watch for 'em. */ | |
4552 | gcc_assert (info.shift1); | |
4553 | ||
4554 | /* Emit two bit rotates first. */ | |
4555 | if (info.shift2 != NULL) | |
48837e29 | 4556 | { |
8c440872 NS |
4557 | for (; m > 1; m -= 2) |
4558 | output_asm_insn (info.shift2, operands); | |
4559 | } | |
4560 | ||
4561 | /* Now single bit rotates for any residual. */ | |
4562 | for (; m > 0; m--) | |
4563 | output_asm_insn (info.shift1, operands); | |
4564 | ||
4565 | /* Now mask off the high bits. */ | |
4566 | switch (mode) | |
4567 | { | |
4568 | case QImode: | |
4569 | sprintf (insn_buf, "and\t#%d,%%X0", mask); | |
4570 | break; | |
51c0c1d7 | 4571 | |
8c440872 NS |
4572 | case HImode: |
4573 | gcc_assert (TARGET_H8300H || TARGET_H8300S); | |
4574 | sprintf (insn_buf, "and.w\t#%d,%%T0", mask); | |
4575 | break; | |
51c0c1d7 | 4576 | |
8c440872 NS |
4577 | default: |
4578 | gcc_unreachable (); | |
48837e29 | 4579 | } |
b5eaf9ba | 4580 | |
8c440872 NS |
4581 | output_asm_insn (insn_buf, operands); |
4582 | return ""; | |
4583 | } | |
b5eaf9ba | 4584 | |
8c440872 NS |
4585 | case SHIFT_LOOP: |
4586 | /* A loop to shift by a "large" constant value. | |
4587 | If we have shift-by-2 insns, use them. */ | |
4588 | if (info.shift2 != NULL) | |
4589 | { | |
4590 | fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2, | |
4591 | names_big[REGNO (operands[4])]); | |
4592 | fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); | |
4593 | output_asm_insn (info.shift2, operands); | |
4594 | output_asm_insn ("add #0xff,%X4", operands); | |
4595 | fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); | |
4596 | if (n % 2) | |
4597 | output_asm_insn (info.shift1, operands); | |
4598 | } | |
4599 | else | |
4600 | { | |
4601 | fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n, | |
4602 | names_big[REGNO (operands[4])]); | |
4603 | fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); | |
4604 | output_asm_insn (info.shift1, operands); | |
4605 | output_asm_insn ("add #0xff,%X4", operands); | |
4606 | fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); | |
51c0c1d7 | 4607 | } |
8c440872 NS |
4608 | return ""; |
4609 | ||
4610 | default: | |
4611 | gcc_unreachable (); | |
07aae5c2 | 4612 | } |
07aae5c2 | 4613 | } |
86855e8c | 4614 | |
0a2aaacc | 4615 | /* Count the number of assembly instructions in a string TEMPL. */ |
e9eba255 | 4616 | |
86855e8c | 4617 | static unsigned int |
0a2aaacc | 4618 | h8300_asm_insn_count (const char *templ) |
86855e8c KH |
4619 | { |
4620 | unsigned int count = 1; | |
4621 | ||
0a2aaacc KG |
4622 | for (; *templ; templ++) |
4623 | if (*templ == '\n') | |
86855e8c KH |
4624 | count++; |
4625 | ||
4626 | return count; | |
4627 | } | |
4628 | ||
e9eba255 KH |
4629 | /* Compute the length of a shift insn. */ |
4630 | ||
86855e8c | 4631 | unsigned int |
cb713a8d | 4632 | compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands) |
86855e8c KH |
4633 | { |
4634 | rtx shift = operands[3]; | |
4635 | enum machine_mode mode = GET_MODE (shift); | |
4636 | enum rtx_code code = GET_CODE (shift); | |
4637 | enum shift_type shift_type; | |
4638 | enum shift_mode shift_mode; | |
4639 | struct shift_info info; | |
4640 | unsigned int wlength = 0; | |
4641 | ||
4642 | switch (mode) | |
4643 | { | |
4644 | case QImode: | |
4645 | shift_mode = QIshift; | |
4646 | break; | |
4647 | case HImode: | |
4648 | shift_mode = HIshift; | |
4649 | break; | |
4650 | case SImode: | |
4651 | shift_mode = SIshift; | |
4652 | break; | |
4653 | default: | |
8c440872 | 4654 | gcc_unreachable (); |
86855e8c KH |
4655 | } |
4656 | ||
4657 | switch (code) | |
4658 | { | |
4659 | case ASHIFTRT: | |
4660 | shift_type = SHIFT_ASHIFTRT; | |
4661 | break; | |
4662 | case LSHIFTRT: | |
4663 | shift_type = SHIFT_LSHIFTRT; | |
4664 | break; | |
4665 | case ASHIFT: | |
4666 | shift_type = SHIFT_ASHIFT; | |
4667 | break; | |
4668 | default: | |
8c440872 | 4669 | gcc_unreachable (); |
86855e8c KH |
4670 | } |
4671 | ||
4672 | if (GET_CODE (operands[2]) != CONST_INT) | |
4673 | { | |
4674 | /* Get the assembler code to do one shift. */ | |
4675 | get_shift_alg (shift_type, shift_mode, 1, &info); | |
4676 | ||
4677 | return (4 + h8300_asm_insn_count (info.shift1)) * 2; | |
4678 | } | |
4679 | else | |
4680 | { | |
4681 | int n = INTVAL (operands[2]); | |
4682 | ||
4683 | /* If the count is negative, make it 0. */ | |
4684 | if (n < 0) | |
4685 | n = 0; | |
4686 | /* If the count is too big, truncate it. | |
4687 | ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to | |
4688 | do the intuitive thing. */ | |
4689 | else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) | |
4690 | n = GET_MODE_BITSIZE (mode); | |
4691 | ||
4692 | get_shift_alg (shift_type, shift_mode, n, &info); | |
4693 | ||
4694 | switch (info.alg) | |
4695 | { | |
4696 | case SHIFT_SPECIAL: | |
4697 | wlength += h8300_asm_insn_count (info.special); | |
41c3eb5d KH |
4698 | |
4699 | /* Every assembly instruction used in SHIFT_SPECIAL case | |
4700 | takes 2 bytes except xor.l, which takes 4 bytes, so if we | |
4701 | see xor.l, we just pretend that xor.l counts as two insns | |
4702 | so that the insn length will be computed correctly. */ | |
4703 | if (strstr (info.special, "xor.l") != NULL) | |
4704 | wlength++; | |
4705 | ||
86855e8c KH |
4706 | /* Fall through. */ |
4707 | ||
4708 | case SHIFT_INLINE: | |
4709 | n = info.remainder; | |
4710 | ||
4711 | if (info.shift2 != NULL) | |
4712 | { | |
4713 | wlength += h8300_asm_insn_count (info.shift2) * (n / 2); | |
4714 | n = n % 2; | |
4715 | } | |
4716 | ||
4717 | wlength += h8300_asm_insn_count (info.shift1) * n; | |
6b148bd9 | 4718 | |
86855e8c KH |
4719 | return 2 * wlength; |
4720 | ||
4721 | case SHIFT_ROT_AND: | |
4722 | { | |
4723 | int m = GET_MODE_BITSIZE (mode) - n; | |
4724 | ||
4725 | /* Not all possibilities of rotate are supported. They shouldn't | |
4726 | be generated, but let's watch for 'em. */ | |
8c440872 | 4727 | gcc_assert (info.shift1); |
86855e8c KH |
4728 | |
4729 | if (info.shift2 != NULL) | |
4730 | { | |
4731 | wlength += h8300_asm_insn_count (info.shift2) * (m / 2); | |
4732 | m = m % 2; | |
4733 | } | |
4734 | ||
4735 | wlength += h8300_asm_insn_count (info.shift1) * m; | |
6b148bd9 | 4736 | |
86855e8c KH |
4737 | /* Now mask off the high bits. */ |
4738 | switch (mode) | |
4739 | { | |
4740 | case QImode: | |
4741 | wlength += 1; | |
4742 | break; | |
4743 | case HImode: | |
4744 | wlength += 2; | |
4745 | break; | |
4746 | case SImode: | |
8c440872 | 4747 | gcc_assert (!TARGET_H8300); |
86855e8c KH |
4748 | wlength += 3; |
4749 | break; | |
4750 | default: | |
8c440872 | 4751 | gcc_unreachable (); |
86855e8c KH |
4752 | } |
4753 | return 2 * wlength; | |
4754 | } | |
4755 | ||
4756 | case SHIFT_LOOP: | |
4757 | /* A loop to shift by a "large" constant value. | |
4758 | If we have shift-by-2 insns, use them. */ | |
4759 | if (info.shift2 != NULL) | |
4760 | { | |
4761 | wlength += 3 + h8300_asm_insn_count (info.shift2); | |
4762 | if (n % 2) | |
4763 | wlength += h8300_asm_insn_count (info.shift1); | |
4764 | } | |
4765 | else | |
4766 | { | |
4767 | wlength += 3 + h8300_asm_insn_count (info.shift1); | |
4768 | } | |
4769 | return 2 * wlength; | |
4770 | ||
4771 | default: | |
8c440872 | 4772 | gcc_unreachable (); |
86855e8c KH |
4773 | } |
4774 | } | |
4775 | } | |
45ca2106 | 4776 | |
e9eba255 KH |
4777 | /* Compute which flag bits are valid after a shift insn. */ |
4778 | ||
9690aa8e | 4779 | enum attr_cc |
cb713a8d | 4780 | compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands) |
45ca2106 KH |
4781 | { |
4782 | rtx shift = operands[3]; | |
4783 | enum machine_mode mode = GET_MODE (shift); | |
4784 | enum rtx_code code = GET_CODE (shift); | |
4785 | enum shift_type shift_type; | |
4786 | enum shift_mode shift_mode; | |
4787 | struct shift_info info; | |
8c440872 NS |
4788 | int n; |
4789 | ||
45ca2106 KH |
4790 | switch (mode) |
4791 | { | |
4792 | case QImode: | |
4793 | shift_mode = QIshift; | |
4794 | break; | |
4795 | case HImode: | |
4796 | shift_mode = HIshift; | |
4797 | break; | |
4798 | case SImode: | |
4799 | shift_mode = SIshift; | |
4800 | break; | |
4801 | default: | |
8c440872 | 4802 | gcc_unreachable (); |
45ca2106 KH |
4803 | } |
4804 | ||
4805 | switch (code) | |
4806 | { | |
4807 | case ASHIFTRT: | |
4808 | shift_type = SHIFT_ASHIFTRT; | |
4809 | break; | |
4810 | case LSHIFTRT: | |
4811 | shift_type = SHIFT_LSHIFTRT; | |
4812 | break; | |
4813 | case ASHIFT: | |
4814 | shift_type = SHIFT_ASHIFT; | |
4815 | break; | |
4816 | default: | |
8c440872 | 4817 | gcc_unreachable (); |
45ca2106 KH |
4818 | } |
4819 | ||
8c440872 NS |
4820 | /* This case must be taken care of by one of the two splitters |
4821 | that convert a variable shift into a loop. */ | |
4822 | gcc_assert (GET_CODE (operands[2]) == CONST_INT); | |
4823 | ||
4824 | n = INTVAL (operands[2]); | |
4825 | ||
4826 | /* If the count is negative, make it 0. */ | |
4827 | if (n < 0) | |
4828 | n = 0; | |
4829 | /* If the count is too big, truncate it. | |
4830 | ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to | |
4831 | do the intuitive thing. */ | |
4832 | else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) | |
4833 | n = GET_MODE_BITSIZE (mode); | |
4834 | ||
4835 | get_shift_alg (shift_type, shift_mode, n, &info); | |
4836 | ||
4837 | switch (info.alg) | |
45ca2106 | 4838 | { |
8c440872 NS |
4839 | case SHIFT_SPECIAL: |
4840 | if (info.remainder == 0) | |
4841 | return info.cc_special; | |
45ca2106 | 4842 | |
8c440872 | 4843 | /* Fall through. */ |
45ca2106 | 4844 | |
8c440872 NS |
4845 | case SHIFT_INLINE: |
4846 | return info.cc_inline; | |
4847 | ||
4848 | case SHIFT_ROT_AND: | |
4849 | /* This case always ends with an and instruction. */ | |
4850 | return CC_SET_ZNV; | |
4851 | ||
4852 | case SHIFT_LOOP: | |
4853 | /* A loop to shift by a "large" constant value. | |
4854 | If we have shift-by-2 insns, use them. */ | |
4855 | if (info.shift2 != NULL) | |
45ca2106 | 4856 | { |
8c440872 NS |
4857 | if (n % 2) |
4858 | return info.cc_inline; | |
45ca2106 | 4859 | } |
8c440872 NS |
4860 | return CC_CLOBBER; |
4861 | ||
4862 | default: | |
4863 | gcc_unreachable (); | |
45ca2106 KH |
4864 | } |
4865 | } | |
48837e29 | 4866 | \f |
edd71f0f KH |
4867 | /* A rotation by a non-constant will cause a loop to be generated, in |
4868 | which a rotation by one bit is used. A rotation by a constant, | |
4869 | including the one in the loop, will be taken care of by | |
caf7f21a | 4870 | output_a_rotate () at the insn emit time. */ |
edd71f0f KH |
4871 | |
4872 | int | |
3d2e90d6 | 4873 | expand_a_rotate (rtx operands[]) |
edd71f0f KH |
4874 | { |
4875 | rtx dst = operands[0]; | |
4876 | rtx src = operands[1]; | |
4877 | rtx rotate_amount = operands[2]; | |
4878 | enum machine_mode mode = GET_MODE (dst); | |
edd71f0f | 4879 | |
beed8fc0 AO |
4880 | if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY) |
4881 | return false; | |
4882 | ||
edd71f0f KH |
4883 | /* We rotate in place. */ |
4884 | emit_move_insn (dst, src); | |
4885 | ||
4886 | if (GET_CODE (rotate_amount) != CONST_INT) | |
4887 | { | |
4888 | rtx counter = gen_reg_rtx (QImode); | |
4889 | rtx start_label = gen_label_rtx (); | |
4890 | rtx end_label = gen_label_rtx (); | |
4891 | ||
4892 | /* If the rotate amount is less than or equal to 0, | |
4893 | we go out of the loop. */ | |
a556fd39 | 4894 | emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX, |
d43e0b7d | 4895 | QImode, 0, end_label); |
edd71f0f KH |
4896 | |
4897 | /* Initialize the loop counter. */ | |
4898 | emit_move_insn (counter, rotate_amount); | |
4899 | ||
4900 | emit_label (start_label); | |
4901 | ||
4902 | /* Rotate by one bit. */ | |
01ab5574 KH |
4903 | switch (mode) |
4904 | { | |
4905 | case QImode: | |
4906 | emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx)); | |
4907 | break; | |
4908 | case HImode: | |
4909 | emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx)); | |
4910 | break; | |
4911 | case SImode: | |
4912 | emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx)); | |
4913 | break; | |
4914 | default: | |
8c440872 | 4915 | gcc_unreachable (); |
01ab5574 | 4916 | } |
edd71f0f KH |
4917 | |
4918 | /* Decrement the counter by 1. */ | |
01ab5574 | 4919 | emit_insn (gen_addqi3 (counter, counter, constm1_rtx)); |
edd71f0f | 4920 | |
9cd10576 | 4921 | /* If the loop counter is nonzero, we go back to the beginning |
edd71f0f | 4922 | of the loop. */ |
a556fd39 | 4923 | emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1, |
d43e0b7d | 4924 | start_label); |
edd71f0f KH |
4925 | |
4926 | emit_label (end_label); | |
4927 | } | |
4928 | else | |
4929 | { | |
4930 | /* Rotate by AMOUNT bits. */ | |
01ab5574 KH |
4931 | switch (mode) |
4932 | { | |
4933 | case QImode: | |
4934 | emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount)); | |
4935 | break; | |
4936 | case HImode: | |
4937 | emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount)); | |
4938 | break; | |
4939 | case SImode: | |
4940 | emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount)); | |
4941 | break; | |
4942 | default: | |
8c440872 | 4943 | gcc_unreachable (); |
01ab5574 | 4944 | } |
edd71f0f KH |
4945 | } |
4946 | ||
4947 | return 1; | |
4948 | } | |
4949 | ||
e9eba255 | 4950 | /* Output a rotate insn. */ |
edd71f0f KH |
4951 | |
4952 | const char * | |
caf7f21a | 4953 | output_a_rotate (enum rtx_code code, rtx *operands) |
edd71f0f KH |
4954 | { |
4955 | rtx dst = operands[0]; | |
4956 | rtx rotate_amount = operands[2]; | |
4957 | enum shift_mode rotate_mode; | |
4958 | enum shift_type rotate_type; | |
4959 | const char *insn_buf; | |
4960 | int bits; | |
4961 | int amount; | |
4962 | enum machine_mode mode = GET_MODE (dst); | |
4963 | ||
8c440872 | 4964 | gcc_assert (GET_CODE (rotate_amount) == CONST_INT); |
edd71f0f KH |
4965 | |
4966 | switch (mode) | |
4967 | { | |
4968 | case QImode: | |
4969 | rotate_mode = QIshift; | |
4970 | break; | |
4971 | case HImode: | |
4972 | rotate_mode = HIshift; | |
4973 | break; | |
4974 | case SImode: | |
4975 | rotate_mode = SIshift; | |
4976 | break; | |
4977 | default: | |
8c440872 | 4978 | gcc_unreachable (); |
edd71f0f KH |
4979 | } |
4980 | ||
4981 | switch (code) | |
4982 | { | |
4983 | case ROTATERT: | |
4984 | rotate_type = SHIFT_ASHIFT; | |
4985 | break; | |
4986 | case ROTATE: | |
4987 | rotate_type = SHIFT_LSHIFTRT; | |
4988 | break; | |
4989 | default: | |
8c440872 | 4990 | gcc_unreachable (); |
edd71f0f KH |
4991 | } |
4992 | ||
4993 | amount = INTVAL (rotate_amount); | |
4994 | ||
4995 | /* Clean up AMOUNT. */ | |
4996 | if (amount < 0) | |
4997 | amount = 0; | |
4998 | if ((unsigned int) amount > GET_MODE_BITSIZE (mode)) | |
4999 | amount = GET_MODE_BITSIZE (mode); | |
5000 | ||
5001 | /* Determine the faster direction. After this phase, amount will be | |
5002 | at most a half of GET_MODE_BITSIZE (mode). */ | |
e0c32c62 | 5003 | if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2) |
edd71f0f KH |
5004 | { |
5005 | /* Flip the direction. */ | |
5006 | amount = GET_MODE_BITSIZE (mode) - amount; | |
5007 | rotate_type = | |
5008 | (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT; | |
5009 | } | |
5010 | ||
5011 | /* See if a byte swap (in HImode) or a word swap (in SImode) can | |
5012 | boost up the rotation. */ | |
5013 | if ((mode == HImode && TARGET_H8300 && amount >= 5) | |
5014 | || (mode == HImode && TARGET_H8300H && amount >= 6) | |
5015 | || (mode == HImode && TARGET_H8300S && amount == 8) | |
5016 | || (mode == SImode && TARGET_H8300H && amount >= 10) | |
5017 | || (mode == SImode && TARGET_H8300S && amount >= 13)) | |
5018 | { | |
5019 | switch (mode) | |
5020 | { | |
5021 | case HImode: | |
5022 | /* This code works on any family. */ | |
5023 | insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0"; | |
5024 | output_asm_insn (insn_buf, operands); | |
5025 | break; | |
5026 | ||
5027 | case SImode: | |
3db11b5c | 5028 | /* This code works on the H8/300H and H8S. */ |
edd71f0f KH |
5029 | insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0"; |
5030 | output_asm_insn (insn_buf, operands); | |
5031 | break; | |
5032 | ||
5033 | default: | |
8c440872 | 5034 | gcc_unreachable (); |
edd71f0f KH |
5035 | } |
5036 | ||
5037 | /* Adjust AMOUNT and flip the direction. */ | |
5038 | amount = GET_MODE_BITSIZE (mode) / 2 - amount; | |
5039 | rotate_type = | |
5040 | (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT; | |
5041 | } | |
5042 | ||
01ab5574 | 5043 | /* Output rotate insns. */ |
edd71f0f KH |
5044 | for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2) |
5045 | { | |
5046 | if (bits == 2) | |
5047 | insn_buf = rotate_two[rotate_type][rotate_mode]; | |
5048 | else | |
5049 | insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode]; | |
2c54abce | 5050 | |
edd71f0f KH |
5051 | for (; amount >= bits; amount -= bits) |
5052 | output_asm_insn (insn_buf, operands); | |
5053 | } | |
5054 | ||
5055 | return ""; | |
5056 | } | |
caf7f21a | 5057 | |
e9eba255 KH |
5058 | /* Compute the length of a rotate insn. */ |
5059 | ||
caf7f21a KH |
5060 | unsigned int |
5061 | compute_a_rotate_length (rtx *operands) | |
5062 | { | |
5063 | rtx src = operands[1]; | |
343fd2c7 | 5064 | rtx amount_rtx = operands[2]; |
caf7f21a KH |
5065 | enum machine_mode mode = GET_MODE (src); |
5066 | int amount; | |
5067 | unsigned int length = 0; | |
5068 | ||
8c440872 | 5069 | gcc_assert (GET_CODE (amount_rtx) == CONST_INT); |
caf7f21a | 5070 | |
343fd2c7 | 5071 | amount = INTVAL (amount_rtx); |
caf7f21a KH |
5072 | |
5073 | /* Clean up AMOUNT. */ | |
5074 | if (amount < 0) | |
5075 | amount = 0; | |
5076 | if ((unsigned int) amount > GET_MODE_BITSIZE (mode)) | |
5077 | amount = GET_MODE_BITSIZE (mode); | |
5078 | ||
5079 | /* Determine the faster direction. After this phase, amount | |
5080 | will be at most a half of GET_MODE_BITSIZE (mode). */ | |
5081 | if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2) | |
5082 | /* Flip the direction. */ | |
5083 | amount = GET_MODE_BITSIZE (mode) - amount; | |
5084 | ||
5085 | /* See if a byte swap (in HImode) or a word swap (in SImode) can | |
5086 | boost up the rotation. */ | |
5087 | if ((mode == HImode && TARGET_H8300 && amount >= 5) | |
5088 | || (mode == HImode && TARGET_H8300H && amount >= 6) | |
5089 | || (mode == HImode && TARGET_H8300S && amount == 8) | |
5090 | || (mode == SImode && TARGET_H8300H && amount >= 10) | |
5091 | || (mode == SImode && TARGET_H8300S && amount >= 13)) | |
5092 | { | |
5093 | /* Adjust AMOUNT and flip the direction. */ | |
5094 | amount = GET_MODE_BITSIZE (mode) / 2 - amount; | |
5095 | length += 6; | |
5096 | } | |
5097 | ||
5098 | /* We use 2-bit rotations on the H8S. */ | |
5099 | if (TARGET_H8300S) | |
5100 | amount = amount / 2 + amount % 2; | |
5101 | ||
5102 | /* The H8/300 uses three insns to rotate one bit, taking 6 | |
5103 | length. */ | |
5104 | length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2); | |
5105 | ||
5106 | return length; | |
5107 | } | |
edd71f0f | 5108 | \f |
48837e29 | 5109 | /* Fix the operands of a gen_xxx so that it could become a bit |
2c54abce | 5110 | operating insn. */ |
07aae5c2 SC |
5111 | |
5112 | int | |
4093985c | 5113 | fix_bit_operand (rtx *operands, enum rtx_code code) |
07aae5c2 | 5114 | { |
abc95ed3 | 5115 | /* The bit_operand predicate accepts any memory during RTL generation, but |
48837e29 DE |
5116 | only 'U' memory afterwards, so if this is a MEM operand, we must force |
5117 | it to be valid for 'U' by reloading the address. */ | |
07aae5c2 | 5118 | |
4093985c KH |
5119 | if (code == AND |
5120 | ? single_zero_operand (operands[2], QImode) | |
5121 | : single_one_operand (operands[2], QImode)) | |
07aae5c2 | 5122 | { |
2e760b15 KH |
5123 | /* OK to have a memory dest. */ |
5124 | if (GET_CODE (operands[0]) == MEM | |
ceaaaeab | 5125 | && !satisfies_constraint_U (operands[0])) |
48837e29 | 5126 | { |
2e760b15 KH |
5127 | rtx mem = gen_rtx_MEM (GET_MODE (operands[0]), |
5128 | copy_to_mode_reg (Pmode, | |
5129 | XEXP (operands[0], 0))); | |
5130 | MEM_COPY_ATTRIBUTES (mem, operands[0]); | |
5131 | operands[0] = mem; | |
5132 | } | |
48837e29 | 5133 | |
2e760b15 | 5134 | if (GET_CODE (operands[1]) == MEM |
ceaaaeab | 5135 | && !satisfies_constraint_U (operands[1])) |
2e760b15 KH |
5136 | { |
5137 | rtx mem = gen_rtx_MEM (GET_MODE (operands[1]), | |
5138 | copy_to_mode_reg (Pmode, | |
5139 | XEXP (operands[1], 0))); | |
5140 | MEM_COPY_ATTRIBUTES (mem, operands[0]); | |
5141 | operands[1] = mem; | |
48837e29 | 5142 | } |
2e760b15 | 5143 | return 0; |
48837e29 | 5144 | } |
07aae5c2 | 5145 | |
48837e29 | 5146 | /* Dest and src op must be register. */ |
07aae5c2 | 5147 | |
48837e29 DE |
5148 | operands[1] = force_reg (QImode, operands[1]); |
5149 | { | |
5150 | rtx res = gen_reg_rtx (QImode); | |
fd57a6e4 | 5151 | switch (code) |
a3579575 KH |
5152 | { |
5153 | case AND: | |
5154 | emit_insn (gen_andqi3_1 (res, operands[1], operands[2])); | |
5155 | break; | |
5156 | case IOR: | |
5157 | emit_insn (gen_iorqi3_1 (res, operands[1], operands[2])); | |
5158 | break; | |
5159 | case XOR: | |
5160 | emit_insn (gen_xorqi3_1 (res, operands[1], operands[2])); | |
5161 | break; | |
5162 | default: | |
8c440872 | 5163 | gcc_unreachable (); |
a3579575 KH |
5164 | } |
5165 | emit_insn (gen_movqi (operands[0], res)); | |
48837e29 DE |
5166 | } |
5167 | return 1; | |
07aae5c2 | 5168 | } |
f5b65a56 | 5169 | |
f5b65a56 JL |
5170 | /* Return nonzero if FUNC is an interrupt function as specified |
5171 | by the "interrupt" attribute. */ | |
5172 | ||
5173 | static int | |
cb713a8d | 5174 | h8300_interrupt_function_p (tree func) |
f5b65a56 JL |
5175 | { |
5176 | tree a; | |
5177 | ||
5178 | if (TREE_CODE (func) != FUNCTION_DECL) | |
5179 | return 0; | |
5180 | ||
91d231cb | 5181 | a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func)); |
f5b65a56 JL |
5182 | return a != NULL_TREE; |
5183 | } | |
5184 | ||
3cfa3702 KH |
5185 | /* Return nonzero if FUNC is a saveall function as specified by the |
5186 | "saveall" attribute. */ | |
5187 | ||
5188 | static int | |
5189 | h8300_saveall_function_p (tree func) | |
5190 | { | |
5191 | tree a; | |
5192 | ||
5193 | if (TREE_CODE (func) != FUNCTION_DECL) | |
5194 | return 0; | |
5195 | ||
5196 | a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func)); | |
5197 | return a != NULL_TREE; | |
5198 | } | |
5199 | ||
fabe72bb JL |
5200 | /* Return nonzero if FUNC is an OS_Task function as specified |
5201 | by the "OS_Task" attribute. */ | |
5202 | ||
5203 | static int | |
cb713a8d | 5204 | h8300_os_task_function_p (tree func) |
fabe72bb JL |
5205 | { |
5206 | tree a; | |
5207 | ||
5208 | if (TREE_CODE (func) != FUNCTION_DECL) | |
5209 | return 0; | |
5210 | ||
91d231cb | 5211 | a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func)); |
fabe72bb JL |
5212 | return a != NULL_TREE; |
5213 | } | |
5214 | ||
5215 | /* Return nonzero if FUNC is a monitor function as specified | |
5216 | by the "monitor" attribute. */ | |
5217 | ||
5218 | static int | |
cb713a8d | 5219 | h8300_monitor_function_p (tree func) |
fabe72bb JL |
5220 | { |
5221 | tree a; | |
5222 | ||
5223 | if (TREE_CODE (func) != FUNCTION_DECL) | |
5224 | return 0; | |
5225 | ||
91d231cb | 5226 | a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func)); |
fabe72bb JL |
5227 | return a != NULL_TREE; |
5228 | } | |
5229 | ||
f5b65a56 JL |
5230 | /* Return nonzero if FUNC is a function that should be called |
5231 | through the function vector. */ | |
5232 | ||
5233 | int | |
cb713a8d | 5234 | h8300_funcvec_function_p (tree func) |
f5b65a56 JL |
5235 | { |
5236 | tree a; | |
5237 | ||
5238 | if (TREE_CODE (func) != FUNCTION_DECL) | |
5239 | return 0; | |
5240 | ||
91d231cb | 5241 | a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func)); |
f5b65a56 JL |
5242 | return a != NULL_TREE; |
5243 | } | |
5244 | ||
887a8bd9 | 5245 | /* Return nonzero if DECL is a variable that's in the eight bit |
15dc331e JL |
5246 | data area. */ |
5247 | ||
5248 | int | |
cb713a8d | 5249 | h8300_eightbit_data_p (tree decl) |
15dc331e JL |
5250 | { |
5251 | tree a; | |
5252 | ||
5253 | if (TREE_CODE (decl) != VAR_DECL) | |
5254 | return 0; | |
5255 | ||
91d231cb | 5256 | a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl)); |
15dc331e JL |
5257 | return a != NULL_TREE; |
5258 | } | |
5259 | ||
887a8bd9 JL |
5260 | /* Return nonzero if DECL is a variable that's in the tiny |
5261 | data area. */ | |
5262 | ||
5263 | int | |
cb713a8d | 5264 | h8300_tiny_data_p (tree decl) |
887a8bd9 JL |
5265 | { |
5266 | tree a; | |
5267 | ||
5268 | if (TREE_CODE (decl) != VAR_DECL) | |
5269 | return 0; | |
5270 | ||
91d231cb | 5271 | a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl)); |
887a8bd9 JL |
5272 | return a != NULL_TREE; |
5273 | } | |
5274 | ||
3cfa3702 KH |
5275 | /* Generate an 'interrupt_handler' attribute for decls. We convert |
5276 | all the pragmas to corresponding attributes. */ | |
2c1d2fcb DD |
5277 | |
5278 | static void | |
cb713a8d | 5279 | h8300_insert_attributes (tree node, tree *attributes) |
2c1d2fcb | 5280 | { |
3cfa3702 KH |
5281 | if (TREE_CODE (node) == FUNCTION_DECL) |
5282 | { | |
5283 | if (pragma_interrupt) | |
5284 | { | |
5285 | pragma_interrupt = 0; | |
2c1d2fcb | 5286 | |
3cfa3702 KH |
5287 | /* Add an 'interrupt_handler' attribute. */ |
5288 | *attributes = tree_cons (get_identifier ("interrupt_handler"), | |
5289 | NULL, *attributes); | |
5290 | } | |
e392d367 | 5291 | |
3cfa3702 KH |
5292 | if (pragma_saveall) |
5293 | { | |
5294 | pragma_saveall = 0; | |
5295 | ||
5296 | /* Add an 'saveall' attribute. */ | |
5297 | *attributes = tree_cons (get_identifier ("saveall"), | |
5298 | NULL, *attributes); | |
5299 | } | |
5300 | } | |
2c1d2fcb DD |
5301 | } |
5302 | ||
91d231cb | 5303 | /* Supported attributes: |
f5b65a56 | 5304 | |
97c5ec1d | 5305 | interrupt_handler: output a prologue and epilogue suitable for an |
f5b65a56 JL |
5306 | interrupt handler. |
5307 | ||
3cfa3702 KH |
5308 | saveall: output a prologue and epilogue that saves and restores |
5309 | all registers except the stack pointer. | |
5310 | ||
97c5ec1d | 5311 | function_vector: This function should be called through the |
887a8bd9 JL |
5312 | function vector. |
5313 | ||
5314 | eightbit_data: This variable lives in the 8-bit data area and can | |
5315 | be referenced with 8-bit absolute memory addresses. | |
5316 | ||
5317 | tiny_data: This variable lives in the tiny data area and can be | |
5318 | referenced with 16-bit absolute memory references. */ | |
f5b65a56 | 5319 | |
6bc7bc14 | 5320 | static const struct attribute_spec h8300_attribute_table[] = |
f5b65a56 | 5321 | { |
62d784f7 KT |
5322 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler, |
5323 | affects_type_identity } */ | |
5324 | { "interrupt_handler", 0, 0, true, false, false, | |
5325 | h8300_handle_fndecl_attribute, false }, | |
5326 | { "saveall", 0, 0, true, false, false, | |
5327 | h8300_handle_fndecl_attribute, false }, | |
5328 | { "OS_Task", 0, 0, true, false, false, | |
5329 | h8300_handle_fndecl_attribute, false }, | |
5330 | { "monitor", 0, 0, true, false, false, | |
5331 | h8300_handle_fndecl_attribute, false }, | |
5332 | { "function_vector", 0, 0, true, false, false, | |
5333 | h8300_handle_fndecl_attribute, false }, | |
5334 | { "eightbit_data", 0, 0, true, false, false, | |
5335 | h8300_handle_eightbit_data_attribute, false }, | |
5336 | { "tiny_data", 0, 0, true, false, false, | |
5337 | h8300_handle_tiny_data_attribute, false }, | |
5338 | { NULL, 0, 0, false, false, false, NULL, false } | |
91d231cb | 5339 | }; |
f5b65a56 | 5340 | |
15dc331e | 5341 | |
91d231cb JM |
5342 | /* Handle an attribute requiring a FUNCTION_DECL; arguments as in |
5343 | struct attribute_spec.handler. */ | |
5344 | static tree | |
cb713a8d KH |
5345 | h8300_handle_fndecl_attribute (tree *node, tree name, |
5346 | tree args ATTRIBUTE_UNUSED, | |
5347 | int flags ATTRIBUTE_UNUSED, | |
5348 | bool *no_add_attrs) | |
91d231cb JM |
5349 | { |
5350 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
5351 | { | |
29d08eba JM |
5352 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
5353 | name); | |
91d231cb JM |
5354 | *no_add_attrs = true; |
5355 | } | |
5356 | ||
5357 | return NULL_TREE; | |
5358 | } | |
5359 | ||
5360 | /* Handle an "eightbit_data" attribute; arguments as in | |
5361 | struct attribute_spec.handler. */ | |
5362 | static tree | |
cb713a8d KH |
5363 | h8300_handle_eightbit_data_attribute (tree *node, tree name, |
5364 | tree args ATTRIBUTE_UNUSED, | |
5365 | int flags ATTRIBUTE_UNUSED, | |
5366 | bool *no_add_attrs) | |
91d231cb JM |
5367 | { |
5368 | tree decl = *node; | |
5369 | ||
5370 | if (TREE_STATIC (decl) || DECL_EXTERNAL (decl)) | |
15dc331e | 5371 | { |
64378c91 | 5372 | DECL_SECTION_NAME (decl) = build_string (7, ".eight"); |
91d231cb JM |
5373 | } |
5374 | else | |
5375 | { | |
29d08eba JM |
5376 | warning (OPT_Wattributes, "%qE attribute ignored", |
5377 | name); | |
91d231cb | 5378 | *no_add_attrs = true; |
887a8bd9 JL |
5379 | } |
5380 | ||
91d231cb JM |
5381 | return NULL_TREE; |
5382 | } | |
5383 | ||
5384 | /* Handle an "tiny_data" attribute; arguments as in | |
5385 | struct attribute_spec.handler. */ | |
5386 | static tree | |
cb713a8d KH |
5387 | h8300_handle_tiny_data_attribute (tree *node, tree name, |
5388 | tree args ATTRIBUTE_UNUSED, | |
5389 | int flags ATTRIBUTE_UNUSED, | |
5390 | bool *no_add_attrs) | |
91d231cb JM |
5391 | { |
5392 | tree decl = *node; | |
5393 | ||
5394 | if (TREE_STATIC (decl) || DECL_EXTERNAL (decl)) | |
887a8bd9 | 5395 | { |
64378c91 | 5396 | DECL_SECTION_NAME (decl) = build_string (6, ".tiny"); |
91d231cb JM |
5397 | } |
5398 | else | |
5399 | { | |
29d08eba JM |
5400 | warning (OPT_Wattributes, "%qE attribute ignored", |
5401 | name); | |
91d231cb | 5402 | *no_add_attrs = true; |
15dc331e | 5403 | } |
07e4d94e | 5404 | |
91d231cb | 5405 | return NULL_TREE; |
f5b65a56 JL |
5406 | } |
5407 | ||
dc66a1c4 | 5408 | /* Mark function vectors, and various small data objects. */ |
fb49053f RH |
5409 | |
5410 | static void | |
cb713a8d | 5411 | h8300_encode_section_info (tree decl, rtx rtl, int first) |
fb49053f | 5412 | { |
dc66a1c4 RH |
5413 | int extra_flags = 0; |
5414 | ||
c6a2438a | 5415 | default_encode_section_info (decl, rtl, first); |
dc66a1c4 | 5416 | |
fb49053f RH |
5417 | if (TREE_CODE (decl) == FUNCTION_DECL |
5418 | && h8300_funcvec_function_p (decl)) | |
dc66a1c4 | 5419 | extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION; |
fb49053f RH |
5420 | else if (TREE_CODE (decl) == VAR_DECL |
5421 | && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))) | |
5422 | { | |
5423 | if (h8300_eightbit_data_p (decl)) | |
dc66a1c4 | 5424 | extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA; |
fb49053f | 5425 | else if (first && h8300_tiny_data_p (decl)) |
dc66a1c4 | 5426 | extra_flags = SYMBOL_FLAG_TINY_DATA; |
fb49053f | 5427 | } |
772c5265 | 5428 | |
dc66a1c4 | 5429 | if (extra_flags) |
c6a2438a | 5430 | SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags; |
772c5265 RH |
5431 | } |
5432 | ||
e9eba255 KH |
5433 | /* Output a single-bit extraction. */ |
5434 | ||
441d04c6 | 5435 | const char * |
cb713a8d | 5436 | output_simode_bld (int bild, rtx operands[]) |
bd93f126 | 5437 | { |
6be580c7 KH |
5438 | if (TARGET_H8300) |
5439 | { | |
5440 | /* Clear the destination register. */ | |
5441 | output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands); | |
5442 | ||
5443 | /* Now output the bit load or bit inverse load, and store it in | |
5444 | the destination. */ | |
5445 | if (bild) | |
5446 | output_asm_insn ("bild\t%Z2,%Y1", operands); | |
5447 | else | |
5448 | output_asm_insn ("bld\t%Z2,%Y1", operands); | |
bd93f126 | 5449 | |
6be580c7 KH |
5450 | output_asm_insn ("bst\t#0,%w0", operands); |
5451 | } | |
bd93f126 | 5452 | else |
6be580c7 | 5453 | { |
0eb933a0 KH |
5454 | /* Determine if we can clear the destination first. */ |
5455 | int clear_first = (REG_P (operands[0]) && REG_P (operands[1]) | |
5456 | && REGNO (operands[0]) != REGNO (operands[1])); | |
5457 | ||
5458 | if (clear_first) | |
5459 | output_asm_insn ("sub.l\t%S0,%S0", operands); | |
5460 | ||
6be580c7 KH |
5461 | /* Output the bit load or bit inverse load. */ |
5462 | if (bild) | |
5463 | output_asm_insn ("bild\t%Z2,%Y1", operands); | |
5464 | else | |
5465 | output_asm_insn ("bld\t%Z2,%Y1", operands); | |
5466 | ||
0eb933a0 KH |
5467 | if (!clear_first) |
5468 | output_asm_insn ("xor.l\t%S0,%S0", operands); | |
5469 | ||
5470 | /* Perform the bit store. */ | |
802a9907 | 5471 | output_asm_insn ("rotxl.l\t%S0", operands); |
6be580c7 | 5472 | } |
bd93f126 JL |
5473 | |
5474 | /* All done. */ | |
5475 | return ""; | |
5476 | } | |
e6219736 | 5477 | |
beed8fc0 AO |
5478 | /* Delayed-branch scheduling is more effective if we have some idea |
5479 | how long each instruction will be. Use a shorten_branches pass | |
5480 | to get an initial estimate. */ | |
5481 | ||
5482 | static void | |
5483 | h8300_reorg (void) | |
5484 | { | |
5485 | if (flag_delayed_branch) | |
5486 | shorten_branches (get_insns ()); | |
5487 | } | |
5488 | ||
ede75ee8 | 5489 | #ifndef OBJECT_FORMAT_ELF |
7c262518 | 5490 | static void |
c18a5b6c MM |
5491 | h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED, |
5492 | tree decl) | |
7c262518 RH |
5493 | { |
5494 | /* ??? Perhaps we should be using default_coff_asm_named_section. */ | |
5495 | fprintf (asm_out_file, "\t.section %s\n", name); | |
5496 | } | |
ede75ee8 | 5497 | #endif /* ! OBJECT_FORMAT_ELF */ |
803d56f5 | 5498 | |
7c143ed2 KH |
5499 | /* Nonzero if X is a constant address suitable as an 8-bit absolute, |
5500 | which is a special case of the 'R' operand. */ | |
5501 | ||
803d56f5 | 5502 | int |
cb713a8d | 5503 | h8300_eightbit_constant_address_p (rtx x) |
803d56f5 | 5504 | { |
ff482c8d | 5505 | /* The ranges of the 8-bit area. */ |
d2d199a3 KH |
5506 | const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode); |
5507 | const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode); | |
803d56f5 KH |
5508 | const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode); |
5509 | const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode); | |
5510 | const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode); | |
5511 | const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode); | |
5512 | ||
5513 | unsigned HOST_WIDE_INT addr; | |
5514 | ||
9675a91e | 5515 | /* We accept symbols declared with eightbit_data. */ |
dc66a1c4 RH |
5516 | if (GET_CODE (x) == SYMBOL_REF) |
5517 | return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0; | |
9675a91e | 5518 | |
803d56f5 KH |
5519 | if (GET_CODE (x) != CONST_INT) |
5520 | return 0; | |
5521 | ||
5522 | addr = INTVAL (x); | |
5523 | ||
5524 | return (0 | |
39ba95b5 | 5525 | || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2)) |
803d56f5 KH |
5526 | || (TARGET_H8300H && IN_RANGE (addr, h1, h2)) |
5527 | || (TARGET_H8300S && IN_RANGE (addr, s1, s2))); | |
5528 | } | |
5529 | ||
7c143ed2 KH |
5530 | /* Nonzero if X is a constant address suitable as an 16-bit absolute |
5531 | on H8/300H and H8S. */ | |
5532 | ||
803d56f5 | 5533 | int |
cb713a8d | 5534 | h8300_tiny_constant_address_p (rtx x) |
803d56f5 | 5535 | { |
3f7211f1 | 5536 | /* The ranges of the 16-bit area. */ |
803d56f5 KH |
5537 | const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode); |
5538 | const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode); | |
5539 | const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode); | |
5540 | const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode); | |
5541 | const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode); | |
5542 | const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode); | |
5543 | const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode); | |
5544 | const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode); | |
5545 | ||
5546 | unsigned HOST_WIDE_INT addr; | |
5547 | ||
d6456562 KH |
5548 | switch (GET_CODE (x)) |
5549 | { | |
5550 | case SYMBOL_REF: | |
a4bb41cc KH |
5551 | /* In the normal mode, any symbol fits in the 16-bit absolute |
5552 | address range. We also accept symbols declared with | |
5553 | tiny_data. */ | |
5554 | return (TARGET_NORMAL_MODE | |
5555 | || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0); | |
56b8e164 | 5556 | |
d6456562 KH |
5557 | case CONST_INT: |
5558 | addr = INTVAL (x); | |
5559 | return (TARGET_NORMAL_MODE | |
5560 | || (TARGET_H8300H | |
5561 | && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4))) | |
5562 | || (TARGET_H8300S | |
5563 | && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4)))); | |
803d56f5 | 5564 | |
a4bb41cc KH |
5565 | case CONST: |
5566 | return TARGET_NORMAL_MODE; | |
5567 | ||
d6456562 KH |
5568 | default: |
5569 | return 0; | |
5570 | } | |
803d56f5 | 5571 | |
803d56f5 | 5572 | } |
9b98dc74 | 5573 | |
e9eba255 KH |
5574 | /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory |
5575 | locations that can be accessed as a 16-bit word. */ | |
5576 | ||
9b98dc74 | 5577 | int |
cb713a8d | 5578 | byte_accesses_mergeable_p (rtx addr1, rtx addr2) |
9b98dc74 KH |
5579 | { |
5580 | HOST_WIDE_INT offset1, offset2; | |
5581 | rtx reg1, reg2; | |
5582 | ||
5583 | if (REG_P (addr1)) | |
5584 | { | |
5585 | reg1 = addr1; | |
5586 | offset1 = 0; | |
5587 | } | |
5588 | else if (GET_CODE (addr1) == PLUS | |
5589 | && REG_P (XEXP (addr1, 0)) | |
5590 | && GET_CODE (XEXP (addr1, 1)) == CONST_INT) | |
5591 | { | |
5592 | reg1 = XEXP (addr1, 0); | |
5593 | offset1 = INTVAL (XEXP (addr1, 1)); | |
5594 | } | |
5595 | else | |
5596 | return 0; | |
5597 | ||
5598 | if (REG_P (addr2)) | |
5599 | { | |
5600 | reg2 = addr2; | |
5601 | offset2 = 0; | |
5602 | } | |
5603 | else if (GET_CODE (addr2) == PLUS | |
5604 | && REG_P (XEXP (addr2, 0)) | |
5605 | && GET_CODE (XEXP (addr2, 1)) == CONST_INT) | |
5606 | { | |
5607 | reg2 = XEXP (addr2, 0); | |
5608 | offset2 = INTVAL (XEXP (addr2, 1)); | |
5609 | } | |
5610 | else | |
5611 | return 0; | |
5612 | ||
5613 | if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx) | |
5614 | || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx)) | |
5615 | && offset1 % 2 == 0 | |
5616 | && offset1 + 1 == offset2) | |
5617 | return 1; | |
5618 | ||
5619 | return 0; | |
5620 | } | |
02529902 KH |
5621 | |
5622 | /* Return nonzero if we have the same comparison insn as I3 two insns | |
19cff4db | 5623 | before I3. I3 is assumed to be a comparison insn. */ |
02529902 KH |
5624 | |
5625 | int | |
5626 | same_cmp_preceding_p (rtx i3) | |
5627 | { | |
5628 | rtx i1, i2; | |
5629 | ||
5630 | /* Make sure we have a sequence of three insns. */ | |
5631 | i2 = prev_nonnote_insn (i3); | |
5632 | if (i2 == NULL_RTX) | |
5633 | return 0; | |
5634 | i1 = prev_nonnote_insn (i2); | |
5635 | if (i1 == NULL_RTX) | |
5636 | return 0; | |
5637 | ||
5638 | return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3)) | |
5639 | && any_condjump_p (i2) && onlyjump_p (i2)); | |
5640 | } | |
c87ec0ba | 5641 | |
c06d5c85 KH |
5642 | /* Return nonzero if we have the same comparison insn as I1 two insns |
5643 | after I1. I1 is assumed to be a comparison insn. */ | |
5644 | ||
5645 | int | |
5646 | same_cmp_following_p (rtx i1) | |
5647 | { | |
5648 | rtx i2, i3; | |
5649 | ||
5650 | /* Make sure we have a sequence of three insns. */ | |
5651 | i2 = next_nonnote_insn (i1); | |
5652 | if (i2 == NULL_RTX) | |
5653 | return 0; | |
5654 | i3 = next_nonnote_insn (i2); | |
5655 | if (i3 == NULL_RTX) | |
5656 | return 0; | |
5657 | ||
5658 | return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3)) | |
5659 | && any_condjump_p (i2) && onlyjump_p (i2)); | |
5660 | } | |
5661 | ||
a466bea3 | 5662 | /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes |
1ae58c30 | 5663 | (or pops) N registers. OPERANDS are assumed to be an array of |
a466bea3 KH |
5664 | registers. */ |
5665 | ||
5666 | int | |
5667 | h8300_regs_ok_for_stm (int n, rtx operands[]) | |
5668 | { | |
5669 | switch (n) | |
5670 | { | |
5671 | case 2: | |
5672 | return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1) | |
5673 | || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3) | |
5674 | || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5)); | |
5675 | case 3: | |
5676 | return ((REGNO (operands[0]) == 0 | |
5677 | && REGNO (operands[1]) == 1 | |
5678 | && REGNO (operands[2]) == 2) | |
5679 | || (REGNO (operands[0]) == 4 | |
5680 | && REGNO (operands[1]) == 5 | |
5681 | && REGNO (operands[2]) == 6)); | |
5682 | ||
5683 | case 4: | |
5684 | return (REGNO (operands[0]) == 0 | |
5685 | && REGNO (operands[1]) == 1 | |
5686 | && REGNO (operands[2]) == 2 | |
5687 | && REGNO (operands[3]) == 3); | |
8c440872 NS |
5688 | default: |
5689 | gcc_unreachable (); | |
a466bea3 | 5690 | } |
a466bea3 KH |
5691 | } |
5692 | ||
c87ec0ba NY |
5693 | /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */ |
5694 | ||
5695 | int | |
5696 | h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, | |
5697 | unsigned int new_reg) | |
5698 | { | |
5699 | /* Interrupt functions can only use registers that have already been | |
5700 | saved by the prologue, even if they would normally be | |
5701 | call-clobbered. */ | |
5702 | ||
5703 | if (h8300_current_function_interrupt_function_p () | |
6fb5fa3c | 5704 | && !df_regs_ever_live_p (new_reg)) |
c87ec0ba NY |
5705 | return 0; |
5706 | ||
80e58519 | 5707 | return 1; |
c87ec0ba | 5708 | } |
d0022200 | 5709 | |
2e762884 DD |
5710 | /* Returns true if register REGNO is safe to be allocated as a scratch |
5711 | register in the current function. */ | |
5712 | ||
5713 | static bool | |
5714 | h8300_hard_regno_scratch_ok (unsigned int regno) | |
5715 | { | |
5716 | if (h8300_current_function_interrupt_function_p () | |
5717 | && ! WORD_REG_USED (regno)) | |
5718 | return false; | |
5719 | ||
5720 | return true; | |
5721 | } | |
5722 | ||
5723 | ||
d0022200 KH |
5724 | /* Return nonzero if X is a legitimate constant. */ |
5725 | ||
5726 | int | |
5727 | h8300_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED) | |
5728 | { | |
5729 | return 1; | |
5730 | } | |
5731 | ||
5732 | /* Return nonzero if X is a REG or SUBREG suitable as a base register. */ | |
5733 | ||
5734 | static int | |
5735 | h8300_rtx_ok_for_base_p (rtx x, int strict) | |
5736 | { | |
5737 | /* Strip off SUBREG if any. */ | |
5738 | if (GET_CODE (x) == SUBREG) | |
5739 | x = SUBREG_REG (x); | |
5740 | ||
5741 | return (REG_P (x) | |
5742 | && (strict | |
5743 | ? REG_OK_FOR_BASE_STRICT_P (x) | |
5744 | : REG_OK_FOR_BASE_NONSTRICT_P (x))); | |
5745 | } | |
5746 | ||
5747 | /* Return nozero if X is a legitimate address. On the H8/300, a | |
5748 | legitimate address has the form REG, REG+CONSTANT_ADDRESS or | |
5749 | CONSTANT_ADDRESS. */ | |
5750 | ||
c6c3dba9 PB |
5751 | static bool |
5752 | h8300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) | |
d0022200 KH |
5753 | { |
5754 | /* The register indirect addresses like @er0 is always valid. */ | |
5755 | if (h8300_rtx_ok_for_base_p (x, strict)) | |
5756 | return 1; | |
5757 | ||
5758 | if (CONSTANT_ADDRESS_P (x)) | |
5759 | return 1; | |
5760 | ||
beed8fc0 AO |
5761 | if (TARGET_H8300SX |
5762 | && ( GET_CODE (x) == PRE_INC | |
5763 | || GET_CODE (x) == PRE_DEC | |
5764 | || GET_CODE (x) == POST_INC | |
5765 | || GET_CODE (x) == POST_DEC) | |
5766 | && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict)) | |
5767 | return 1; | |
5768 | ||
d0022200 KH |
5769 | if (GET_CODE (x) == PLUS |
5770 | && CONSTANT_ADDRESS_P (XEXP (x, 1)) | |
beed8fc0 AO |
5771 | && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0), |
5772 | mode, 0), strict)) | |
d0022200 KH |
5773 | return 1; |
5774 | ||
5775 | return 0; | |
5776 | } | |
07ee3b58 KH |
5777 | |
5778 | /* Worker function for HARD_REGNO_NREGS. | |
5779 | ||
5780 | We pretend the MAC register is 32bits -- we don't have any data | |
5781 | types on the H8 series to handle more than 32bits. */ | |
5782 | ||
5783 | int | |
5784 | h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, enum machine_mode mode) | |
5785 | { | |
5786 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
5787 | } | |
5788 | ||
5789 | /* Worker function for HARD_REGNO_MODE_OK. */ | |
5790 | ||
5791 | int | |
5792 | h8300_hard_regno_mode_ok (int regno, enum machine_mode mode) | |
5793 | { | |
5794 | if (TARGET_H8300) | |
5795 | /* If an even reg, then anything goes. Otherwise the mode must be | |
5796 | QI or HI. */ | |
5797 | return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode); | |
5798 | else | |
5799 | /* MAC register can only be of SImode. Otherwise, anything | |
5800 | goes. */ | |
5801 | return regno == MAC_REG ? mode == SImode : 1; | |
5802 | } | |
6e014ef3 | 5803 | \f |
c15c90bb ZW |
5804 | /* Perform target dependent optabs initialization. */ |
5805 | static void | |
5806 | h8300_init_libfuncs (void) | |
5807 | { | |
5808 | set_optab_libfunc (smul_optab, HImode, "__mulhi3"); | |
5809 | set_optab_libfunc (sdiv_optab, HImode, "__divhi3"); | |
5810 | set_optab_libfunc (udiv_optab, HImode, "__udivhi3"); | |
5811 | set_optab_libfunc (smod_optab, HImode, "__modhi3"); | |
5812 | set_optab_libfunc (umod_optab, HImode, "__umodhi3"); | |
5813 | } | |
5814 | \f | |
9eaa7740 AS |
5815 | /* Worker function for TARGET_FUNCTION_VALUE. |
5816 | ||
5817 | On the H8 the return value is in R0/R1. */ | |
5818 | ||
5819 | static rtx | |
5820 | h8300_function_value (const_tree ret_type, | |
5821 | const_tree fn_decl_or_type ATTRIBUTE_UNUSED, | |
5822 | bool outgoing ATTRIBUTE_UNUSED) | |
5823 | { | |
5824 | return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG); | |
5825 | } | |
5826 | ||
5827 | /* Worker function for TARGET_LIBCALL_VALUE. | |
5828 | ||
5829 | On the H8 the return value is in R0/R1. */ | |
5830 | ||
5831 | static rtx | |
5832 | h8300_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) | |
5833 | { | |
5834 | return gen_rtx_REG (mode, R0_REG); | |
5835 | } | |
5836 | ||
5837 | /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P. | |
5838 | ||
5839 | On the H8, R0 is the only register thus used. */ | |
5840 | ||
5841 | static bool | |
5842 | h8300_function_value_regno_p (const unsigned int regno) | |
5843 | { | |
5844 | return (regno == R0_REG); | |
5845 | } | |
5846 | ||
e9eba255 KH |
5847 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
5848 | ||
34bf1fe3 | 5849 | static bool |
586de218 | 5850 | h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
34bf1fe3 KH |
5851 | { |
5852 | return (TYPE_MODE (type) == BLKmode | |
5853 | || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8)); | |
5854 | } | |
5855 | \f | |
9f6ef043 RH |
5856 | /* We emit the entire trampoline here. Depending on the pointer size, |
5857 | we use a different trampoline. | |
5858 | ||
5859 | Pmode == HImode | |
5860 | vvvv context | |
5861 | 1 0000 7903xxxx mov.w #0x1234,r3 | |
5862 | 2 0004 5A00xxxx jmp @0x1234 | |
5863 | ^^^^ function | |
5864 | ||
5865 | Pmode == SImode | |
5866 | vvvvvvvv context | |
5867 | 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3 | |
5868 | 3 0006 5Axxxxxx jmp @0x123456 | |
5869 | ^^^^^^ function | |
5870 | */ | |
5871 | ||
5872 | static void | |
5873 | h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt) | |
5874 | { | |
5875 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
5876 | rtx mem; | |
5877 | ||
5878 | if (Pmode == HImode) | |
5879 | { | |
5880 | mem = adjust_address (m_tramp, HImode, 0); | |
5881 | emit_move_insn (mem, GEN_INT (0x7903)); | |
5882 | mem = adjust_address (m_tramp, Pmode, 2); | |
5883 | emit_move_insn (mem, cxt); | |
5884 | mem = adjust_address (m_tramp, HImode, 4); | |
5885 | emit_move_insn (mem, GEN_INT (0x5a00)); | |
5886 | mem = adjust_address (m_tramp, Pmode, 6); | |
5887 | emit_move_insn (mem, fnaddr); | |
5888 | } | |
5889 | else | |
5890 | { | |
5891 | rtx tem; | |
5892 | ||
5893 | mem = adjust_address (m_tramp, HImode, 0); | |
5894 | emit_move_insn (mem, GEN_INT (0x7a03)); | |
5895 | mem = adjust_address (m_tramp, Pmode, 2); | |
5896 | emit_move_insn (mem, cxt); | |
5897 | ||
5898 | tem = copy_to_reg (fnaddr); | |
5899 | emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff))); | |
5900 | emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000))); | |
5901 | mem = adjust_address (m_tramp, SImode, 6); | |
5902 | emit_move_insn (mem, tem); | |
5903 | } | |
5904 | } | |
5905 | \f | |
6e014ef3 KH |
5906 | /* Initialize the GCC target structure. */ |
5907 | #undef TARGET_ATTRIBUTE_TABLE | |
5908 | #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table | |
5909 | ||
5910 | #undef TARGET_ASM_ALIGNED_HI_OP | |
5911 | #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
5912 | ||
1bc7c5b6 ZW |
5913 | #undef TARGET_ASM_FILE_START |
5914 | #define TARGET_ASM_FILE_START h8300_file_start | |
5915 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
5916 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
5917 | ||
6e014ef3 KH |
5918 | #undef TARGET_ASM_FILE_END |
5919 | #define TARGET_ASM_FILE_END h8300_file_end | |
5920 | ||
5921 | #undef TARGET_ENCODE_SECTION_INFO | |
5922 | #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info | |
5923 | ||
5924 | #undef TARGET_INSERT_ATTRIBUTES | |
5925 | #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes | |
5926 | ||
5927 | #undef TARGET_RTX_COSTS | |
5928 | #define TARGET_RTX_COSTS h8300_rtx_costs | |
5929 | ||
c15c90bb ZW |
5930 | #undef TARGET_INIT_LIBFUNCS |
5931 | #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs | |
5932 | ||
9eaa7740 AS |
5933 | #undef TARGET_FUNCTION_VALUE |
5934 | #define TARGET_FUNCTION_VALUE h8300_function_value | |
5935 | ||
5936 | #undef TARGET_LIBCALL_VALUE | |
5937 | #define TARGET_LIBCALL_VALUE h8300_libcall_value | |
5938 | ||
5939 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
5940 | #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p | |
5941 | ||
34bf1fe3 KH |
5942 | #undef TARGET_RETURN_IN_MEMORY |
5943 | #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory | |
5944 | ||
56f9413b NF |
5945 | #undef TARGET_FUNCTION_ARG |
5946 | #define TARGET_FUNCTION_ARG h8300_function_arg | |
5947 | ||
5948 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
5949 | #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance | |
5950 | ||
beed8fc0 AO |
5951 | #undef TARGET_MACHINE_DEPENDENT_REORG |
5952 | #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg | |
5953 | ||
2e762884 DD |
5954 | #undef TARGET_HARD_REGNO_SCRATCH_OK |
5955 | #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok | |
5956 | ||
c6c3dba9 PB |
5957 | #undef TARGET_LEGITIMATE_ADDRESS_P |
5958 | #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p | |
5959 | ||
1aeceea4 PT |
5960 | #undef TARGET_DEFAULT_TARGET_FLAGS |
5961 | #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT | |
5962 | ||
7b5cbb57 AS |
5963 | #undef TARGET_CAN_ELIMINATE |
5964 | #define TARGET_CAN_ELIMINATE h8300_can_eliminate | |
5965 | ||
5efd84c5 NF |
5966 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
5967 | #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage | |
5968 | ||
9f6ef043 RH |
5969 | #undef TARGET_TRAMPOLINE_INIT |
5970 | #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init | |
5971 | ||
c5387660 JM |
5972 | #undef TARGET_OPTION_OVERRIDE |
5973 | #define TARGET_OPTION_OVERRIDE h8300_option_override | |
5974 | ||
3020190e JM |
5975 | #undef TARGET_OPTION_OPTIMIZATION_TABLE |
5976 | #define TARGET_OPTION_OPTIMIZATION_TABLE h8300_option_optimization_table | |
fac0f722 | 5977 | |
19779181 NF |
5978 | #undef TARGET_EXCEPT_UNWIND_INFO |
5979 | #define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info | |
5980 | ||
f52d97da AS |
5981 | #undef TARGET_MODE_DEPENDENT_ADDRESS_P |
5982 | #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p | |
5983 | ||
6e014ef3 | 5984 | struct gcc_target targetm = TARGET_INITIALIZER; |