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07aae5c2 | 1 | /* Subroutines for insn-output.c for Hitachi H8/300. |
3c71736a | 2 | Copyright (C) 1992, 1993, 1994, 1995, 1996 Free Software Foundation, Inc. |
48837e29 DE |
3 | Contributed by Steve Chamberlain (sac@cygnus.com), |
4 | Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). | |
07aae5c2 SC |
5 | |
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
97aadbb9 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
07aae5c2 SC |
22 | |
23 | #include <stdio.h> | |
24 | #include "config.h" | |
25 | #include "rtl.h" | |
26 | #include "regs.h" | |
27 | #include "hard-reg-set.h" | |
28 | #include "real.h" | |
29 | #include "insn-config.h" | |
30 | #include "conditions.h" | |
31 | #include "insn-flags.h" | |
32 | #include "output.h" | |
33 | #include "insn-attr.h" | |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
36 | #include "expr.h" | |
37 | #include "tree.h" | |
887a8bd9 | 38 | #include "obstack.h" |
07aae5c2 SC |
39 | |
40 | /* Forward declarations. */ | |
41 | void print_operand_address (); | |
42 | char *index (); | |
43 | ||
f5b65a56 | 44 | static int h8300_interrupt_function_p PROTO ((tree)); |
fabe72bb JL |
45 | static int h8300_monitor_function_p PROTO ((tree)); |
46 | static int h8300_os_task_function_p PROTO ((tree)); | |
f5b65a56 | 47 | |
48837e29 DE |
48 | /* CPU_TYPE, says what cpu we're compiling for. */ |
49 | int cpu_type; | |
50 | ||
f5b65a56 JL |
51 | /* True if the current function is an interrupt handler |
52 | (either via #pragma or an attribute specification). */ | |
53 | int interrupt_handler; | |
54 | ||
fabe72bb JL |
55 | /* True if the current fucntion is an OS Task |
56 | (via an attribute specification). */ | |
57 | int os_task; | |
58 | ||
59 | /* True if the current function is a monitor | |
60 | (via an attribute specification). */ | |
61 | int monitor; | |
07aae5c2 SC |
62 | |
63 | /* True if a #pragma saveall has been seen for the current function. */ | |
64 | int pragma_saveall; | |
65 | ||
48837e29 DE |
66 | static char *names_big[] = |
67 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7"}; | |
68 | ||
69 | static char *names_extended[] = | |
70 | {"er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7"}; | |
71 | ||
72 | static char *names_upper_extended[] = | |
73 | {"e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7"}; | |
74 | ||
75 | /* Points to one of the above. */ | |
76 | /* ??? The above could be put in an array indexed by CPU_TYPE. */ | |
77 | char **h8_reg_names; | |
78 | ||
79 | /* Various operations needed by the following, indexed by CPU_TYPE. */ | |
48837e29 DE |
80 | |
81 | static char *h8_push_ops[2] = | |
82 | {"push", "push.l"}; | |
83 | static char *h8_pop_ops[2] = | |
84 | {"pop", "pop.l"}; | |
85 | static char *h8_mov_ops[2] = | |
86 | {"mov.w", "mov.l"}; | |
87 | ||
88 | char *h8_push_op, *h8_pop_op, *h8_mov_op; | |
89 | ||
90 | /* Initialize various cpu specific globals at start up. */ | |
91 | ||
92 | void | |
93 | h8300_init_once () | |
94 | { | |
95 | if (TARGET_H8300) | |
96 | { | |
97 | cpu_type = (int) CPU_H8300; | |
98 | h8_reg_names = names_big; | |
99 | } | |
100 | else | |
101 | { | |
102 | cpu_type = (int) CPU_H8300H; | |
103 | h8_reg_names = names_extended; | |
104 | } | |
105 | h8_push_op = h8_push_ops[cpu_type]; | |
106 | h8_pop_op = h8_pop_ops[cpu_type]; | |
107 | h8_mov_op = h8_mov_ops[cpu_type]; | |
108 | } | |
07aae5c2 SC |
109 | |
110 | char * | |
111 | byte_reg (x, b) | |
112 | rtx x; | |
113 | int b; | |
114 | { | |
48837e29 DE |
115 | static char *names_small[] = |
116 | {"r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h", | |
bd93f126 | 117 | "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"}; |
07aae5c2 SC |
118 | |
119 | return names_small[REGNO (x) * 2 + b]; | |
120 | } | |
121 | ||
122 | /* REGNO must be saved/restored across calls if this macro is true. */ | |
48837e29 DE |
123 | |
124 | #define WORD_REG_USED(regno) \ | |
125 | (regno < 7 && \ | |
f5b65a56 | 126 | (interrupt_handler \ |
48837e29 DE |
127 | || pragma_saveall \ |
128 | || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno]) \ | |
129 | || (regs_ever_live[regno] & !call_used_regs[regno]))) | |
07aae5c2 SC |
130 | |
131 | /* Output assembly language to FILE for the operation OP with operand size | |
48837e29 | 132 | SIZE to adjust the stack pointer. */ |
48837e29 | 133 | |
07aae5c2 | 134 | static void |
f8f26adc | 135 | dosize (file, op, size) |
07aae5c2 SC |
136 | FILE *file; |
137 | char *op; | |
138 | unsigned int size; | |
07aae5c2 | 139 | { |
f8f26adc JL |
140 | /* On the h8300h, for sizes <= 8 bytes it is as good or |
141 | better to use adds/subs insns rather than add.l/sub.l | |
142 | with an immediate value. */ | |
143 | if (size > 4 && size <= 8 && TARGET_H8300H) | |
144 | { | |
145 | /* Crank the size down to <= 4 */ | |
146 | fprintf (file, "\t%ss\t#%d,sp\n", op, 4); | |
147 | size -= 4; | |
148 | } | |
149 | ||
07aae5c2 SC |
150 | switch (size) |
151 | { | |
152 | case 4: | |
82fa9209 JL |
153 | if (TARGET_H8300H) |
154 | { | |
155 | fprintf (file, "\t%ss\t#%d,sp\n", op, 4); | |
156 | size = 0; | |
157 | break; | |
158 | } | |
07aae5c2 SC |
159 | case 3: |
160 | fprintf (file, "\t%ss\t#%d,sp\n", op, 2); | |
161 | size -= 2; | |
162 | /* Fall through... */ | |
163 | case 2: | |
164 | case 1: | |
165 | fprintf (file, "\t%ss\t#%d,sp\n", op, size); | |
166 | size = 0; | |
167 | break; | |
168 | case 0: | |
169 | break; | |
170 | default: | |
48837e29 DE |
171 | if (TARGET_H8300) |
172 | fprintf (file, "\tmov.w\t#%d,r3\n\t%s.w\tr3,sp\n", size, op); | |
173 | else | |
174 | fprintf (file, "\t%s\t#%d,sp\n", op, size); | |
07aae5c2 SC |
175 | size = 0; |
176 | break; | |
177 | } | |
178 | } | |
179 | ||
180 | /* Output assembly language code for the function prologue. */ | |
48837e29 DE |
181 | static int push_order[FIRST_PSEUDO_REGISTER] = |
182 | {6, 5, 4, 3, 2, 1, 0, -1, -1}; | |
183 | static int pop_order[FIRST_PSEUDO_REGISTER] = | |
184 | {0, 1, 2, 3, 4, 5, 6, -1, -1}; | |
07aae5c2 SC |
185 | |
186 | /* This is what the stack looks like after the prolog of | |
187 | a function with a frame has been set up: | |
188 | ||
48837e29 DE |
189 | <args> |
190 | PC | |
191 | FP <- fp | |
192 | <locals> | |
193 | <saved registers> <- sp | |
07aae5c2 SC |
194 | |
195 | This is what the stack looks like after the prolog of | |
196 | a function which doesn't have a frame: | |
197 | ||
48837e29 DE |
198 | <args> |
199 | PC | |
200 | <locals> | |
201 | <saved registers> <- sp | |
07aae5c2 SC |
202 | */ |
203 | ||
204 | void | |
205 | function_prologue (file, size) | |
206 | FILE *file; | |
207 | int size; | |
208 | { | |
209 | register int mask = 0; | |
48837e29 | 210 | int fsize = (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8; |
07aae5c2 SC |
211 | int idx; |
212 | ||
dd07092e JL |
213 | /* Note a function with the interrupt attribute and set interrupt_handler |
214 | accordingly. */ | |
f5b65a56 JL |
215 | if (h8300_interrupt_function_p (current_function_decl)) |
216 | interrupt_handler = 1; | |
217 | ||
fabe72bb JL |
218 | /* If the current function has the OS_Task attribute set, then |
219 | we have a naked prologue. */ | |
220 | if (h8300_os_task_function_p (current_function_decl)) | |
221 | { | |
222 | fprintf (file, ";OS_Task prologue\n"); | |
223 | os_task = 1; | |
224 | return; | |
225 | } | |
226 | ||
227 | if (h8300_monitor_function_p (current_function_decl)) | |
228 | { | |
229 | /* My understanding of monitor functions is they act just | |
230 | like interrupt functions, except the prologue must | |
231 | mask interrupts. */ | |
232 | fprintf (file, ";monitor prologue\n"); | |
233 | interrupt_handler = 1; | |
234 | monitor = 1; | |
ea3a7ffa JL |
235 | if (TARGET_H8300) |
236 | { | |
237 | fprintf (file, "\tsubs\t#2,sp\n"); | |
238 | fprintf (file, "\tpush\tr0\n"); | |
239 | fprintf (file, "\tstc\tccr,r0l\n"); | |
240 | fprintf (file, "\torc\t#128,ccr\n"); | |
241 | fprintf (file, "\tmov.b\tr0l,@(4,sp)\n"); | |
242 | } | |
243 | else if (TARGET_H8300H) | |
244 | { | |
245 | fprintf (file, "\tpush\ter0\n"); | |
246 | fprintf (file, "\tstc\tccr,r0l\n"); | |
247 | fprintf (file, "\torc\t#128,ccr\n"); | |
248 | fprintf (file, "\tmov.b\tr0l,@(4,sp)\n"); | |
249 | } | |
fabe72bb JL |
250 | } |
251 | ||
48837e29 DE |
252 | if (frame_pointer_needed) |
253 | { | |
254 | /* Push fp */ | |
255 | fprintf (file, "\t%s\t%s\n", h8_push_op, | |
256 | h8_reg_names[FRAME_POINTER_REGNUM]); | |
257 | fprintf (file, "\t%s\t%s,%s\n", h8_mov_op, | |
258 | h8_reg_names[STACK_POINTER_REGNUM], | |
259 | h8_reg_names[FRAME_POINTER_REGNUM]); | |
260 | ||
261 | /* leave room for locals */ | |
f8f26adc | 262 | dosize (file, "sub", fsize); |
07aae5c2 | 263 | |
48837e29 DE |
264 | /* Push the rest of the registers */ |
265 | for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++) | |
07aae5c2 SC |
266 | { |
267 | int regno = push_order[idx]; | |
268 | ||
48837e29 DE |
269 | if (regno >= 0 && WORD_REG_USED (regno) && regno != FRAME_POINTER_REGNUM) |
270 | fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[regno]); | |
07aae5c2 SC |
271 | } |
272 | } | |
273 | else | |
274 | { | |
f8f26adc | 275 | dosize (file, "sub", fsize); |
07aae5c2 SC |
276 | for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++) |
277 | { | |
278 | int regno = push_order[idx]; | |
279 | ||
48837e29 DE |
280 | if (regno >= 0 && WORD_REG_USED (regno)) |
281 | fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[regno]); | |
07aae5c2 SC |
282 | } |
283 | } | |
284 | } | |
285 | ||
286 | /* Output assembly language code for the function epilogue. */ | |
287 | ||
288 | void | |
289 | function_epilogue (file, size) | |
290 | FILE *file; | |
291 | int size; | |
292 | { | |
293 | register int regno; | |
294 | register int mask = 0; | |
48837e29 | 295 | int fsize = (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8; |
07aae5c2 SC |
296 | int nregs; |
297 | int offset; | |
298 | int idx; | |
299 | rtx insn = get_last_insn (); | |
300 | ||
fabe72bb JL |
301 | if (os_task) |
302 | { | |
303 | /* OS_Task epilogues are nearly naked -- they just have an | |
304 | rts instruction. */ | |
305 | fprintf (file, ";OS_task epilogue\n"); | |
306 | fprintf (file, "\trts\n"); | |
307 | goto out; | |
308 | } | |
309 | ||
310 | /* monitor epilogues are the same as interrupt function epilogues. | |
311 | Just make a note that we're in an monitor epilogue. */ | |
312 | if (monitor) | |
313 | fprintf(file, ";monitor epilogue\n"); | |
314 | ||
07aae5c2 SC |
315 | /* If the last insn was a BARRIER, we don't have to write any code. */ |
316 | if (GET_CODE (insn) == NOTE) | |
317 | insn = prev_nonnote_insn (insn); | |
318 | if (insn && GET_CODE (insn) == BARRIER) | |
319 | return; | |
320 | ||
321 | nregs = 0; | |
322 | ||
323 | if (frame_pointer_needed) | |
324 | { | |
48837e29 | 325 | /* Pop saved registers */ |
07aae5c2 SC |
326 | for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++) |
327 | { | |
328 | regno = pop_order[idx]; | |
48837e29 DE |
329 | if (regno >= 0 && regno != FRAME_POINTER_REGNUM && WORD_REG_USED (regno)) |
330 | fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[regno]); | |
07aae5c2 | 331 | } |
48837e29 | 332 | /* deallocate locals */ |
f8f26adc | 333 | dosize (file, "add", fsize); |
48837e29 DE |
334 | /* pop frame pointer */ |
335 | fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[FRAME_POINTER_REGNUM]); | |
07aae5c2 SC |
336 | } |
337 | else | |
338 | { | |
48837e29 | 339 | /* pop saved registers */ |
07aae5c2 SC |
340 | for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++) |
341 | { | |
342 | regno = pop_order[idx]; | |
48837e29 DE |
343 | if (regno >= 0 && WORD_REG_USED (regno)) |
344 | fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[regno]); | |
07aae5c2 | 345 | } |
48837e29 | 346 | /* deallocate locals */ |
b74f9efe | 347 | dosize (file, "add", fsize); |
07aae5c2 | 348 | } |
48837e29 | 349 | |
ea3a7ffa JL |
350 | /* If this is a monitor function, there is one register still left on |
351 | the stack. */ | |
352 | if (monitor) | |
353 | fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[0]); | |
354 | ||
dd07092e JL |
355 | if (interrupt_handler) |
356 | fprintf (file, "\trte\n"); | |
07aae5c2 | 357 | else |
dd07092e | 358 | fprintf (file, "\trts\n"); |
07aae5c2 | 359 | |
fabe72bb | 360 | out: |
f5b65a56 | 361 | interrupt_handler = 0; |
fabe72bb JL |
362 | os_task = 0; |
363 | monitor = 0; | |
07aae5c2 | 364 | pragma_saveall = 0; |
48837e29 DE |
365 | } |
366 | ||
367 | /* Output assembly code for the start of the file. */ | |
368 | ||
369 | asm_file_start (file) | |
370 | FILE *file; | |
371 | { | |
372 | fprintf (file, ";\tGCC For the Hitachi H8/300\n"); | |
373 | fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n"); | |
374 | fprintf (file, ";\trelease F-1\n"); | |
375 | if (optimize) | |
376 | fprintf (file, "; -O%d\n", optimize); | |
377 | if (TARGET_H8300H) | |
378 | fprintf (file, "\n\t.h8300h\n"); | |
379 | else | |
380 | fprintf (file, "\n\n"); | |
381 | output_file_directive (file, main_input_filename); | |
382 | } | |
383 | ||
384 | /* Output assembly language code for the end of file. */ | |
385 | ||
386 | void | |
387 | asm_file_end (file) | |
388 | FILE *file; | |
389 | { | |
390 | fprintf (file, "\t.end\n"); | |
07aae5c2 SC |
391 | } |
392 | \f | |
48837e29 DE |
393 | /* Return true if VALUE is a valid constant for constraint 'P'. |
394 | IE: VALUE is a power of two <= 2**15. */ | |
07aae5c2 SC |
395 | |
396 | int | |
48837e29 DE |
397 | small_power_of_two (value) |
398 | int value; | |
07aae5c2 SC |
399 | { |
400 | switch (value) | |
401 | { | |
402 | case 1: | |
403 | case 2: | |
404 | case 4: | |
405 | case 8: | |
406 | case 16: | |
407 | case 32: | |
408 | case 64: | |
409 | case 128: | |
07aae5c2 SC |
410 | case 256: |
411 | case 512: | |
412 | case 1024: | |
413 | case 2048: | |
414 | case 4096: | |
415 | case 8192: | |
416 | case 16384: | |
417 | case 32768: | |
418 | return 1; | |
419 | } | |
420 | return 0; | |
421 | } | |
422 | ||
48837e29 DE |
423 | /* Return true if VALUE is a valid constant for constraint 'O', which |
424 | means that the constant would be ok to use as a bit for a bclr | |
425 | instruction. */ | |
426 | ||
427 | int | |
428 | ok_for_bclr (value) | |
429 | int value; | |
430 | { | |
431 | return small_power_of_two ((~value) & 0xff); | |
432 | } | |
433 | ||
07aae5c2 SC |
434 | /* Return true is OP is a valid source operand for an integer move |
435 | instruction. */ | |
48837e29 | 436 | |
07aae5c2 SC |
437 | int |
438 | general_operand_src (op, mode) | |
439 | rtx op; | |
440 | enum machine_mode mode; | |
441 | { | |
48837e29 DE |
442 | if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC) |
443 | return 1; | |
07aae5c2 SC |
444 | return general_operand (op, mode); |
445 | } | |
446 | ||
447 | /* Return true if OP is a valid destination operand for an integer move | |
448 | instruction. */ | |
48837e29 | 449 | |
07aae5c2 SC |
450 | int |
451 | general_operand_dst (op, mode) | |
452 | rtx op; | |
453 | enum machine_mode mode; | |
454 | { | |
48837e29 DE |
455 | if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == PRE_DEC) |
456 | return 1; | |
07aae5c2 SC |
457 | return general_operand (op, mode); |
458 | } | |
48837e29 DE |
459 | |
460 | /* Return true if OP is a const valid for a bit clear instruction. */ | |
461 | ||
462 | int | |
463 | o_operand (operand, mode) | |
464 | rtx operand; | |
465 | enum machine_mode mode; | |
466 | { | |
467 | return (GET_CODE (operand) == CONST_INT | |
468 | && CONST_OK_FOR_O (INTVAL (operand))); | |
469 | } | |
470 | ||
471 | /* Return true if OP is a const valid for a bit set or bit xor instruction. */ | |
472 | ||
473 | int | |
474 | p_operand (operand, mode) | |
475 | rtx operand; | |
476 | enum machine_mode mode; | |
477 | { | |
478 | return (GET_CODE (operand) == CONST_INT | |
479 | && CONST_OK_FOR_P (INTVAL (operand))); | |
480 | } | |
481 | ||
482 | /* Return true if OP is a valid call operand. */ | |
483 | ||
484 | int | |
485 | call_insn_operand (op, mode) | |
486 | rtx op; | |
487 | enum machine_mode mode; | |
488 | { | |
489 | if (GET_CODE (op) == MEM) | |
490 | { | |
491 | rtx inside = XEXP (op, 0); | |
492 | if (register_operand (inside, Pmode)) | |
493 | return 1; | |
494 | if (CONSTANT_ADDRESS_P (inside)) | |
495 | return 1; | |
496 | } | |
497 | return 0; | |
498 | } | |
499 | ||
3b7d443c JL |
500 | int |
501 | adds_subs_operand (op, mode) | |
502 | rtx op; | |
503 | enum machine_mode mode; | |
504 | { | |
505 | if (GET_CODE (op) == CONST_INT) | |
506 | { | |
507 | if (INTVAL (op) <= 4 && INTVAL (op) >= 0) | |
508 | return 1; | |
509 | if (INTVAL (op) >= -4 && INTVAL (op) <= 0) | |
510 | return 1; | |
511 | if (TARGET_H8300H | |
512 | && INTVAL (op) != 7 | |
17b706a6 | 513 | && (INTVAL (op) <= 8 && INTVAL (op) >= 0)) |
3b7d443c JL |
514 | return 1; |
515 | if (TARGET_H8300H | |
516 | && INTVAL (op) != -7 | |
17b706a6 | 517 | && (INTVAL (op) >= -8 && INTVAL (op) <= 0)) |
3b7d443c JL |
518 | return 1; |
519 | } | |
520 | return 0; | |
521 | } | |
522 | ||
e6219736 JL |
523 | /* Return nonzero if op is an adds/subs operand which only requires |
524 | one insn to implement. It is assumed that OP is already an adds/subs | |
525 | operand. */ | |
526 | int | |
527 | one_insn_adds_subs_operand (op, mode) | |
528 | rtx op; | |
529 | enum machine_mode mode; | |
530 | { | |
531 | int val = INTVAL (op); | |
532 | ||
533 | if (val == 1 || val == -1 | |
534 | || val == 2 || val == -2 | |
535 | || (TARGET_H8300H | |
536 | && (val == 4 || val == -4))) | |
537 | return 1; | |
538 | return 0; | |
539 | } | |
540 | ||
3b7d443c JL |
541 | char * |
542 | output_adds_subs (operands) | |
543 | rtx *operands; | |
544 | { | |
545 | int val = INTVAL (operands[2]); | |
546 | ||
547 | /* First get the value into the range -4..4 inclusive. | |
548 | ||
549 | The only way it can be out of this range is when TARGET_H8300H | |
550 | is true, thus it is safe to use adds #4 and subs #4. */ | |
551 | if (val > 4) | |
552 | { | |
553 | output_asm_insn ("adds #4,%A0", operands); | |
554 | val -= 4; | |
555 | } | |
556 | ||
557 | if (val < -4) | |
558 | { | |
559 | output_asm_insn ("subs #4,%A0", operands); | |
560 | val += 4; | |
561 | } | |
562 | ||
563 | /* Handle case were val == 4 or val == -4 and we're compiling | |
564 | for TARGET_H8300H. */ | |
565 | if (TARGET_H8300H && val == 4) | |
566 | return "adds #4,%A0"; | |
567 | ||
568 | if (TARGET_H8300H && val == -4) | |
569 | return "subs #4,%A0"; | |
570 | ||
571 | if (val > 2) | |
572 | { | |
573 | output_asm_insn ("adds #2,%A0", operands); | |
574 | val -= 2; | |
575 | } | |
576 | ||
577 | if (val < -2) | |
578 | { | |
579 | output_asm_insn ("subs #2,%A0", operands); | |
580 | val += 2; | |
581 | } | |
582 | ||
583 | /* val should be one or two now. */ | |
584 | if (val == 2) | |
585 | return "adds #2,%A0"; | |
586 | ||
587 | if (val == -2) | |
588 | return "subs #2,%A0"; | |
589 | ||
590 | /* val should be one now. */ | |
591 | if (val == 1) | |
592 | return "adds #1,%A0"; | |
593 | ||
594 | if (val == -1) | |
595 | return "subs #1,%A0"; | |
596 | ||
597 | /* In theory, this can't happen. */ | |
598 | abort (); | |
599 | } | |
600 | ||
f5b65a56 JL |
601 | /* Return true if OP is a valid call operand, and OP represents |
602 | an operand for a small call (4 bytes instead of 6 bytes). */ | |
603 | ||
604 | int | |
605 | small_call_insn_operand (op, mode) | |
606 | rtx op; | |
607 | enum machine_mode mode; | |
608 | { | |
609 | if (GET_CODE (op) == MEM) | |
610 | { | |
611 | rtx inside = XEXP (op, 0); | |
612 | ||
613 | /* Register indirect is a small call. */ | |
614 | if (register_operand (inside, Pmode)) | |
615 | return 1; | |
616 | ||
617 | /* A call through the function vector is a small | |
618 | call too. */ | |
619 | if (GET_CODE (inside) == SYMBOL_REF | |
620 | && SYMBOL_REF_FLAG (inside)) | |
621 | return 1; | |
622 | } | |
623 | /* Otherwise it's a large call. */ | |
624 | return 0; | |
625 | } | |
626 | ||
48837e29 DE |
627 | /* Return true if OP is a valid jump operand. */ |
628 | ||
629 | int | |
630 | jump_address_operand (op, mode) | |
631 | rtx op; | |
632 | enum machine_mode mode; | |
633 | { | |
634 | if (GET_CODE (op) == REG) | |
635 | return mode == Pmode; | |
636 | ||
637 | if (GET_CODE (op) == MEM) | |
638 | { | |
639 | rtx inside = XEXP (op, 0); | |
640 | if (register_operand (inside, Pmode)) | |
641 | return 1; | |
642 | if (CONSTANT_ADDRESS_P (inside)) | |
643 | return 1; | |
644 | } | |
645 | return 0; | |
646 | } | |
647 | ||
648 | /* Recognize valid operands for bitfield instructions. */ | |
649 | ||
650 | extern int rtx_equal_function_value_matters; | |
651 | ||
652 | int | |
653 | bit_operand (op, mode) | |
654 | rtx op; | |
655 | enum machine_mode mode; | |
656 | { | |
657 | /* We can except any general operand, expept that MEM operands must | |
658 | be limited to those that use addresses valid for the 'U' constraint. */ | |
659 | if (!general_operand (op, mode)) | |
660 | return 0; | |
661 | ||
662 | /* Accept any mem during RTL generation. Otherwise, the code that does | |
663 | insv and extzv will think that we can not handle memory. However, | |
664 | to avoid reload problems, we only accept 'U' MEM operands after RTL | |
665 | generation. This means that any named pattern which uses this predicate | |
666 | must force its operands to match 'U' before emitting RTL. */ | |
667 | ||
668 | if (GET_CODE (op) == REG) | |
669 | return 1; | |
670 | if (GET_CODE (op) == SUBREG) | |
671 | return 1; | |
672 | if (!rtx_equal_function_value_matters) | |
673 | { | |
674 | /* We're building rtl */ | |
675 | return GET_CODE (op) == MEM; | |
676 | } | |
677 | else | |
678 | { | |
679 | return (GET_CODE (op) == MEM | |
680 | && EXTRA_CONSTRAINT (op, 'U')); | |
681 | } | |
682 | } | |
683 | ||
887a8bd9 JL |
684 | int |
685 | bit_memory_operand (op, mode) | |
686 | rtx op; | |
687 | enum machine_mode mode; | |
688 | { | |
689 | return (GET_CODE (op) == MEM | |
690 | && EXTRA_CONSTRAINT (op, 'U')); | |
691 | } | |
692 | ||
48837e29 DE |
693 | /* Recognize valid operators for bit test. */ |
694 | ||
695 | int | |
696 | eq_operator (x, mode) | |
697 | rtx x; | |
698 | enum machine_mode mode; | |
699 | { | |
700 | return (GET_CODE (x) == EQ || GET_CODE (x) == NE); | |
701 | } | |
702 | ||
07aae5c2 | 703 | /* Handle machine specific pragmas for compatibility with existing |
48837e29 | 704 | compilers for the H8/300. |
07aae5c2 SC |
705 | |
706 | pragma saveall generates prolog/epilog code which saves and | |
707 | restores all the registers on function entry. | |
48837e29 | 708 | |
07aae5c2 SC |
709 | pragma interrupt saves and restores all registers, and exits with |
710 | an rte instruction rather than an rts. A pointer to a function | |
711 | with this attribute may be safely used in an interrupt vector. */ | |
48837e29 | 712 | |
07aae5c2 | 713 | int |
5bb43f8f | 714 | handle_pragma (file, t) |
07aae5c2 | 715 | FILE *file; |
5bb43f8f | 716 | tree t; |
07aae5c2 | 717 | { |
5bb43f8f JW |
718 | int retval = 0; |
719 | register char *pname; | |
07aae5c2 | 720 | |
5bb43f8f JW |
721 | if (TREE_CODE (t) != IDENTIFIER_NODE) |
722 | return 0; | |
05a81fe5 | 723 | |
5bb43f8f JW |
724 | pname = IDENTIFIER_POINTER (t); |
725 | if (strcmp (pname, "interrupt") == 0) | |
726 | interrupt_handler = retval = 1; | |
727 | else if (strcmp (pname, "saveall") == 0) | |
728 | pragma_saveall = retval = 1; | |
05a81fe5 | 729 | |
5bb43f8f | 730 | return retval; |
07aae5c2 SC |
731 | } |
732 | \f | |
733 | /* If the next arg with MODE and TYPE is to be passed in a register, return | |
734 | the rtx to represent where it is passed. CUM represents the state after | |
735 | the last argument. NAMED is not used. */ | |
736 | ||
48837e29 DE |
737 | static char *hand_list[] = |
738 | { | |
739 | "__main", | |
740 | "__cmpsi2", | |
741 | "__divhi3", | |
742 | "__modhi3", | |
743 | "__udivhi3", | |
744 | "__umodhi3", | |
745 | "__divsi3", | |
746 | "__modsi3", | |
747 | "__udivsi3", | |
748 | "__umodsi3", | |
749 | "__mulhi3", | |
750 | "__mulsi3", | |
751 | "__reg_memcpy", | |
752 | "__reg_memset", | |
753 | "__ucmpsi2", | |
754 | 0, | |
755 | }; | |
756 | ||
757 | /* Return an RTX to represent where a value with mode MODE will be returned | |
758 | from a function. If the result is 0, the argument is pushed. */ | |
759 | ||
07aae5c2 SC |
760 | rtx |
761 | function_arg (cum, mode, type, named) | |
762 | CUMULATIVE_ARGS *cum; | |
763 | enum machine_mode mode; | |
764 | tree type; | |
765 | int named; | |
766 | { | |
767 | rtx result = 0; | |
48837e29 DE |
768 | char *fname; |
769 | int regpass = 0; | |
770 | ||
dd07092e JL |
771 | /* Never pass unnamed arguments in registers. */ |
772 | if (!named) | |
773 | return 0; | |
774 | ||
48837e29 DE |
775 | /* Pass 3 regs worth of data in regs when user asked on the command line. */ |
776 | if (TARGET_QUICKCALL) | |
777 | regpass = 3; | |
778 | ||
779 | /* If calling hand written assembler, use 4 regs of args. */ | |
780 | ||
781 | if (cum->libcall) | |
782 | { | |
783 | char **p; | |
784 | ||
785 | fname = XSTR (cum->libcall, 0); | |
786 | ||
787 | /* See if this libcall is one of the hand coded ones. */ | |
07aae5c2 | 788 | |
48837e29 DE |
789 | for (p = hand_list; *p && strcmp (*p, fname) != 0; p++) |
790 | ; | |
07aae5c2 | 791 | |
48837e29 DE |
792 | if (*p) |
793 | regpass = 4; | |
794 | } | |
795 | ||
796 | if (regpass) | |
797 | { | |
798 | int size; | |
799 | ||
800 | if (mode == BLKmode) | |
801 | size = int_size_in_bytes (type); | |
802 | else | |
803 | size = GET_MODE_SIZE (mode); | |
804 | ||
805 | if (size + cum->nbytes > regpass * UNITS_PER_WORD) | |
806 | { | |
807 | result = 0; | |
808 | } | |
809 | else | |
810 | { | |
811 | switch (cum->nbytes / UNITS_PER_WORD) | |
812 | { | |
813 | case 0: | |
814 | result = gen_rtx (REG, mode, 0); | |
815 | break; | |
816 | case 1: | |
817 | result = gen_rtx (REG, mode, 1); | |
818 | break; | |
819 | case 2: | |
820 | result = gen_rtx (REG, mode, 2); | |
821 | break; | |
822 | case 3: | |
823 | result = gen_rtx (REG, mode, 3); | |
824 | break; | |
825 | default: | |
826 | result = 0; | |
827 | } | |
828 | } | |
829 | } | |
07aae5c2 | 830 | |
48837e29 DE |
831 | return result; |
832 | } | |
833 | \f | |
834 | /* Return the cost of the rtx R with code CODE. */ | |
07aae5c2 | 835 | |
48837e29 DE |
836 | int |
837 | const_costs (r, c) | |
838 | rtx r; | |
839 | enum rtx_code c; | |
840 | { | |
841 | switch (c) | |
07aae5c2 | 842 | { |
48837e29 DE |
843 | case CONST_INT: |
844 | switch (INTVAL (r)) | |
07aae5c2 SC |
845 | { |
846 | case 0: | |
48837e29 | 847 | case 1: |
07aae5c2 | 848 | case 2: |
48837e29 DE |
849 | case -1: |
850 | case -2: | |
07aae5c2 | 851 | return 0; |
5ae5999c JL |
852 | case 4: |
853 | case -4: | |
854 | if (TARGET_H8300H) | |
855 | return 0; | |
856 | else | |
857 | return 1; | |
48837e29 DE |
858 | default: |
859 | return 1; | |
07aae5c2 | 860 | } |
48837e29 DE |
861 | |
862 | case CONST: | |
863 | case LABEL_REF: | |
864 | case SYMBOL_REF: | |
865 | return 3; | |
866 | ||
867 | case CONST_DOUBLE: | |
868 | return 20; | |
869 | ||
870 | default: | |
871 | return 4; | |
07aae5c2 | 872 | } |
07aae5c2 | 873 | } |
48837e29 | 874 | \f |
07aae5c2 SC |
875 | /* Documentation for the machine specific operand escapes: |
876 | ||
48837e29 | 877 | 'A' print rn in h8/300 mode, erN in H8/300H mode |
07aae5c2 | 878 | 'C' print (operand - 2). |
48837e29 DE |
879 | 'E' like s but negative. |
880 | 'F' like t but negative. | |
881 | 'G' constant just the negative | |
07aae5c2 SC |
882 | 'L' fake label, changed after used twice. |
883 | 'M' turn a 'M' constant into its negative mod 2. | |
48837e29 | 884 | 'P' if operand is incing/decing sp, print .w, otherwise .b. |
15dc331e JL |
885 | 'R' print operand as a byte:8 address if appropriate, else fall back to |
886 | 'X' handling. | |
48837e29 | 887 | 'S' print operand as a long word |
07aae5c2 | 888 | 'T' print operand as a word |
48837e29 DE |
889 | 'U' if operand is incing/decing sp, print l, otherwise nothing. |
890 | 'V' find the set bit, and print its number. | |
891 | 'W' find the clear bit, and print its number. | |
892 | 'X' print operand as a byte | |
07aae5c2 | 893 | 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8. |
15dc331e | 894 | If this operand isn't a register, fall back to 'R' handling. |
48837e29 DE |
895 | 'Z' print int & 7. |
896 | 'b' print the bit opcode | |
897 | 'c' print the ibit opcode | |
898 | 'd' bcc if EQ, bcs if NE | |
899 | 'e' first word of 32 bit value - if reg, then least reg. if mem | |
900 | then least. if const then most sig word | |
901 | 'f' second word of 32 bit value - if reg, then biggest reg. if mem | |
902 | then +2. if const then least sig word | |
903 | 'g' bcs if EQ, bcc if NE | |
07aae5c2 SC |
904 | 'j' print operand as condition code. |
905 | 'k' print operand as reverse condition code. | |
48837e29 DE |
906 | 's' print as low byte of 16 bit value |
907 | 't' print as high byte of 16 bit value | |
908 | 'w' print as low byte of 32 bit value | |
909 | 'x' print as 2nd byte of 32 bit value | |
910 | 'y' print as 3rd byte of 32 bit value | |
911 | 'z' print as msb of 32 bit value | |
912 | */ | |
07aae5c2 SC |
913 | |
914 | /* Return assembly language string which identifies a comparison type. */ | |
915 | ||
48837e29 | 916 | static char * |
07aae5c2 SC |
917 | cond_string (code) |
918 | enum rtx_code code; | |
919 | { | |
920 | switch (code) | |
921 | { | |
922 | case NE: | |
923 | return "ne"; | |
924 | case EQ: | |
925 | return "eq"; | |
926 | case GE: | |
927 | return "ge"; | |
928 | case GT: | |
929 | return "gt"; | |
930 | case LE: | |
931 | return "le"; | |
932 | case LT: | |
933 | return "lt"; | |
934 | case GEU: | |
935 | return "hs"; | |
936 | case GTU: | |
937 | return "hi"; | |
938 | case LEU: | |
939 | return "ls"; | |
940 | case LTU: | |
941 | return "lo"; | |
942 | default: | |
943 | abort (); | |
944 | } | |
945 | } | |
946 | ||
947 | /* Print operand X using operand code CODE to assembly language output file | |
948 | FILE. */ | |
949 | ||
950 | void | |
951 | print_operand (file, x, code) | |
952 | FILE *file; | |
953 | rtx x; | |
954 | int code; | |
955 | { | |
956 | /* This is used to general unique labels for the 'L' code. */ | |
957 | static int lab = 1000; | |
958 | ||
959 | /* This is used for communication between the 'P' and 'U' codes. */ | |
960 | static char *last_p; | |
961 | ||
269c14e1 | 962 | /* This is used for communication between codes V,W,Z and Y. */ |
07aae5c2 SC |
963 | static int bitint; |
964 | ||
965 | switch (code) | |
966 | { | |
48837e29 | 967 | case 'A': |
07aae5c2 | 968 | if (GET_CODE (x) == REG) |
48837e29 | 969 | fprintf (file, "%s", h8_reg_names[REGNO (x)]); |
07aae5c2 SC |
970 | else |
971 | goto def; | |
972 | break; | |
48837e29 DE |
973 | case 'C': |
974 | fprintf (file, "#%d", INTVAL (x) - 2); | |
975 | break; | |
976 | case 'E': | |
977 | switch (GET_CODE (x)) | |
978 | { | |
979 | case REG: | |
980 | fprintf (file, "%sl", names_big[REGNO (x)]); | |
981 | break; | |
982 | case CONST_INT: | |
983 | fprintf (file, "#%d", (-INTVAL (x)) & 0xff); | |
984 | break; | |
985 | default: | |
986 | abort (); | |
987 | } | |
988 | break; | |
989 | case 'F': | |
990 | switch (GET_CODE (x)) | |
991 | { | |
992 | case REG: | |
993 | fprintf (file, "%sh", names_big[REGNO (x)]); | |
994 | break; | |
995 | case CONST_INT: | |
996 | fprintf (file, "#%d", ((-INTVAL (x)) & 0xff00) >> 8); | |
997 | break; | |
998 | default: | |
999 | abort (); | |
1000 | } | |
1001 | break; | |
07aae5c2 SC |
1002 | case 'G': |
1003 | if (GET_CODE (x) != CONST_INT) | |
1004 | abort (); | |
1005 | fprintf (file, "#%d", 0xff & (-INTVAL (x))); | |
1006 | break; | |
48837e29 DE |
1007 | case 'L': |
1008 | /* 'L' must always be used twice in a single pattern. It generates | |
ddd5a7c1 | 1009 | the same label twice, and then will generate a unique label the |
48837e29 DE |
1010 | next time it is used. */ |
1011 | asm_fprintf (file, "tl%d", (lab++) / 2); | |
07aae5c2 | 1012 | break; |
48837e29 DE |
1013 | case 'M': |
1014 | /* For 3/-3 and 4/-4, the other 2 is handled separately. */ | |
1015 | switch (INTVAL (x)) | |
1016 | { | |
1017 | case 2: | |
1018 | case 4: | |
1019 | case -2: | |
1020 | case -4: | |
1021 | fprintf (file, "#2"); | |
1022 | break; | |
1023 | case 1: | |
1024 | case 3: | |
1025 | case -1: | |
1026 | case -3: | |
1027 | fprintf (file, "#1"); | |
1028 | break; | |
1029 | default: | |
1030 | abort (); | |
1031 | } | |
07aae5c2 | 1032 | break; |
48837e29 DE |
1033 | case 'P': |
1034 | if (REGNO (XEXP (XEXP (x, 0), 0)) == STACK_POINTER_REGNUM) | |
1035 | { | |
1036 | last_p = ""; | |
1037 | fprintf (file, ".w"); | |
1038 | } | |
07aae5c2 | 1039 | else |
48837e29 DE |
1040 | { |
1041 | last_p = "l"; | |
1042 | fprintf (file, ".b"); | |
1043 | } | |
07aae5c2 | 1044 | break; |
48837e29 DE |
1045 | case 'S': |
1046 | if (GET_CODE (x) == REG) | |
1047 | fprintf (file, "%s", names_extended[REGNO (x)]); | |
07aae5c2 | 1048 | else |
48837e29 | 1049 | goto def; |
07aae5c2 | 1050 | break; |
48837e29 DE |
1051 | case 'T': |
1052 | if (GET_CODE (x) == REG) | |
1053 | fprintf (file, "%s", names_big[REGNO (x)]); | |
07aae5c2 | 1054 | else |
48837e29 | 1055 | goto def; |
07aae5c2 | 1056 | break; |
48837e29 DE |
1057 | case 'U': |
1058 | fprintf (file, "%s%s", names_big[REGNO (x)], last_p); | |
07aae5c2 | 1059 | break; |
48837e29 DE |
1060 | case 'V': |
1061 | bitint = exact_log2 (INTVAL (x)); | |
1062 | if (bitint == -1) | |
07aae5c2 | 1063 | abort (); |
07aae5c2 SC |
1064 | fprintf (file, "#%d", bitint & 7); |
1065 | break; | |
48837e29 | 1066 | case 'W': |
07aae5c2 SC |
1067 | bitint = exact_log2 ((~INTVAL (x)) & 0xff); |
1068 | if (bitint == -1) | |
1069 | abort (); | |
1070 | fprintf (file, "#%d", bitint & 7); | |
1071 | break; | |
15dc331e | 1072 | case 'R': |
48837e29 DE |
1073 | case 'X': |
1074 | if (GET_CODE (x) == REG) | |
1075 | fprintf (file, "%s", byte_reg (x, 0)); | |
1076 | else | |
1077 | goto def; | |
1078 | break; | |
1079 | case 'Y': | |
07aae5c2 SC |
1080 | if (bitint == -1) |
1081 | abort (); | |
48837e29 DE |
1082 | if (GET_CODE (x) == REG) |
1083 | fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l'); | |
1084 | else | |
15dc331e | 1085 | print_operand (file, x, 'R'); |
48837e29 DE |
1086 | bitint = -1; |
1087 | break; | |
1088 | case 'Z': | |
1089 | bitint = INTVAL (x); | |
07aae5c2 SC |
1090 | fprintf (file, "#%d", bitint & 7); |
1091 | break; | |
48837e29 DE |
1092 | case 'b': |
1093 | switch (GET_CODE (x)) | |
07aae5c2 | 1094 | { |
48837e29 DE |
1095 | case IOR: |
1096 | fprintf (file, "bor"); | |
1097 | break; | |
1098 | case XOR: | |
1099 | fprintf (file, "bxor"); | |
1100 | break; | |
1101 | case AND: | |
1102 | fprintf (file, "band"); | |
1103 | break; | |
07aae5c2 | 1104 | } |
48837e29 DE |
1105 | break; |
1106 | case 'c': | |
1107 | switch (GET_CODE (x)) | |
07aae5c2 | 1108 | { |
48837e29 DE |
1109 | case IOR: |
1110 | fprintf (file, "bior"); | |
1111 | break; | |
1112 | case XOR: | |
1113 | fprintf (file, "bixor"); | |
1114 | break; | |
1115 | case AND: | |
1116 | fprintf (file, "biand"); | |
1117 | break; | |
07aae5c2 SC |
1118 | } |
1119 | break; | |
48837e29 DE |
1120 | case 'd': |
1121 | switch (GET_CODE (x)) | |
07aae5c2 | 1122 | { |
48837e29 DE |
1123 | case EQ: |
1124 | fprintf (file, "bcc"); | |
07aae5c2 | 1125 | break; |
48837e29 DE |
1126 | case NE: |
1127 | fprintf (file, "bcs"); | |
07aae5c2 | 1128 | break; |
07aae5c2 SC |
1129 | default: |
1130 | abort (); | |
1131 | } | |
1132 | break; | |
07aae5c2 SC |
1133 | case 'e': |
1134 | switch (GET_CODE (x)) | |
1135 | { | |
1136 | case REG: | |
48837e29 DE |
1137 | if (TARGET_H8300) |
1138 | fprintf (file, "%s", names_big[REGNO (x)]); | |
1139 | else | |
1140 | fprintf (file, "%s", names_upper_extended[REGNO (x)]); | |
07aae5c2 SC |
1141 | break; |
1142 | case MEM: | |
1143 | x = adj_offsettable_operand (x, 0); | |
1144 | print_operand (file, x, 0); | |
1145 | break; | |
1146 | case CONST_INT: | |
1147 | fprintf (file, "#%d", ((INTVAL (x) >> 16) & 0xffff)); | |
1148 | break; | |
1149 | default: | |
1150 | abort (); | |
1151 | break; | |
1152 | } | |
1153 | break; | |
07aae5c2 SC |
1154 | case 'f': |
1155 | switch (GET_CODE (x)) | |
1156 | { | |
1157 | case REG: | |
48837e29 DE |
1158 | if (TARGET_H8300) |
1159 | fprintf (file, "%s", names_big[REGNO (x) + 1]); | |
1160 | else | |
1161 | fprintf (file, "%s", names_big[REGNO (x)]); | |
07aae5c2 | 1162 | break; |
07aae5c2 SC |
1163 | case MEM: |
1164 | x = adj_offsettable_operand (x, 2); | |
1165 | print_operand (file, x, 0); | |
1166 | break; | |
07aae5c2 SC |
1167 | case CONST_INT: |
1168 | fprintf (file, "#%d", INTVAL (x) & 0xffff); | |
1169 | break; | |
07aae5c2 SC |
1170 | default: |
1171 | abort (); | |
1172 | } | |
1173 | break; | |
48837e29 | 1174 | case 'g': |
07aae5c2 SC |
1175 | switch (GET_CODE (x)) |
1176 | { | |
48837e29 DE |
1177 | case NE: |
1178 | fprintf (file, "bcc"); | |
07aae5c2 | 1179 | break; |
48837e29 DE |
1180 | case EQ: |
1181 | fprintf (file, "bcs"); | |
07aae5c2 | 1182 | break; |
07aae5c2 SC |
1183 | default: |
1184 | abort (); | |
1185 | } | |
1186 | break; | |
07aae5c2 SC |
1187 | case 'j': |
1188 | asm_fprintf (file, cond_string (GET_CODE (x))); | |
1189 | break; | |
07aae5c2 SC |
1190 | case 'k': |
1191 | asm_fprintf (file, cond_string (reverse_condition (GET_CODE (x)))); | |
1192 | break; | |
48837e29 DE |
1193 | case 's': |
1194 | if (GET_CODE (x) == CONST_INT) | |
1195 | fprintf (file, "#%d", (INTVAL (x)) & 0xff); | |
1196 | else | |
1197 | fprintf (file, "%s", byte_reg (x, 0)); | |
1198 | break; | |
1199 | case 't': | |
1200 | if (GET_CODE (x) == CONST_INT) | |
1201 | fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff); | |
1202 | else | |
1203 | fprintf (file, "%s", byte_reg (x, 1)); | |
1204 | break; | |
1205 | case 'u': | |
1206 | if (GET_CODE (x) != CONST_INT) | |
1207 | abort (); | |
1208 | fprintf (file, "%d", INTVAL (x)); | |
1209 | break; | |
1210 | case 'w': | |
1211 | if (GET_CODE (x) == CONST_INT) | |
1212 | fprintf (file, "#%d", INTVAL (x) & 0xff); | |
1213 | else | |
1214 | fprintf (file, "%s", byte_reg (x, TARGET_H8300 ? 2 : 0)); | |
1215 | break; | |
1216 | case 'x': | |
1217 | if (GET_CODE (x) == CONST_INT) | |
1218 | fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff); | |
1219 | else | |
1220 | fprintf (file, "%s", byte_reg (x, TARGET_H8300 ? 3 : 1)); | |
1221 | break; | |
1222 | case 'y': | |
1223 | if (GET_CODE (x) == CONST_INT) | |
1224 | fprintf (file, "#%d", (INTVAL (x) >> 16) & 0xff); | |
1225 | else | |
1226 | fprintf (file, "%s", byte_reg (x, 0)); | |
1227 | break; | |
1228 | case 'z': | |
1229 | if (GET_CODE (x) == CONST_INT) | |
1230 | fprintf (file, "#%d", (INTVAL (x) >> 24) & 0xff); | |
1231 | else | |
1232 | fprintf (file, "%s", byte_reg (x, 1)); | |
1233 | break; | |
1234 | ||
07aae5c2 | 1235 | default: |
48837e29 | 1236 | def: |
07aae5c2 SC |
1237 | switch (GET_CODE (x)) |
1238 | { | |
1239 | case REG: | |
48837e29 DE |
1240 | switch (GET_MODE (x)) |
1241 | { | |
1242 | case QImode: | |
269c14e1 | 1243 | #if 0 /* Is it asm ("mov.b %0,r2l", ...) */ |
48837e29 DE |
1244 | fprintf (file, "%s", byte_reg (x, 0)); |
1245 | #else /* ... or is it asm ("mov.b %0l,r2l", ...) */ | |
1246 | fprintf (file, "%s", names_big[REGNO (x)]); | |
1247 | #endif | |
1248 | break; | |
1249 | case HImode: | |
1250 | fprintf (file, "%s", names_big[REGNO (x)]); | |
1251 | break; | |
1252 | case SImode: | |
8977e8a7 | 1253 | case SFmode: |
48837e29 DE |
1254 | fprintf (file, "%s", names_extended[REGNO (x)]); |
1255 | break; | |
1256 | default: | |
1257 | abort (); | |
1258 | } | |
07aae5c2 SC |
1259 | break; |
1260 | ||
1261 | case MEM: | |
1262 | fprintf (file, "@"); | |
1263 | output_address (XEXP (x, 0)); | |
15dc331e JL |
1264 | |
1265 | /* If this is an 'R' operand (reference into the 8-bit area), | |
1266 | then specify a symbolic address as "foo:8". */ | |
1267 | if (code == 'R' | |
1268 | && GET_CODE (XEXP (x, 0)) == SYMBOL_REF | |
1269 | && SYMBOL_REF_FLAG (XEXP (x, 0))) | |
1270 | fprintf (file, ":8"); | |
887a8bd9 JL |
1271 | if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF |
1272 | && TINY_DATA_NAME_P (XSTR (XEXP (x, 0), 0))) | |
1273 | fprintf (file, ":16"); | |
07aae5c2 SC |
1274 | break; |
1275 | ||
1276 | case CONST_INT: | |
1277 | case SYMBOL_REF: | |
1278 | case CONST: | |
1279 | case LABEL_REF: | |
1280 | fprintf (file, "#"); | |
1281 | print_operand_address (file, x); | |
1282 | break; | |
1283 | } | |
1284 | } | |
1285 | } | |
1286 | ||
1287 | /* Output assembly language output for the address ADDR to FILE. */ | |
1288 | ||
1289 | void | |
1290 | print_operand_address (file, addr) | |
1291 | FILE *file; | |
1292 | rtx addr; | |
1293 | { | |
1294 | switch (GET_CODE (addr)) | |
1295 | { | |
1296 | case REG: | |
48837e29 | 1297 | fprintf (file, "%s", h8_reg_names[REGNO (addr)]); |
07aae5c2 SC |
1298 | break; |
1299 | ||
1300 | case PRE_DEC: | |
48837e29 | 1301 | fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]); |
07aae5c2 SC |
1302 | break; |
1303 | ||
1304 | case POST_INC: | |
48837e29 | 1305 | fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]); |
07aae5c2 SC |
1306 | break; |
1307 | ||
1308 | case PLUS: | |
1309 | fprintf (file, "("); | |
1310 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
1311 | { | |
1312 | /* reg,foo */ | |
1313 | print_operand_address (file, XEXP (addr, 1)); | |
1314 | fprintf (file, ","); | |
1315 | print_operand_address (file, XEXP (addr, 0)); | |
1316 | } | |
1317 | else | |
1318 | { | |
1319 | /* foo+k */ | |
1320 | print_operand_address (file, XEXP (addr, 0)); | |
1321 | fprintf (file, "+"); | |
1322 | print_operand_address (file, XEXP (addr, 1)); | |
1323 | } | |
1324 | fprintf (file, ")"); | |
1325 | break; | |
1326 | ||
1327 | case CONST_INT: | |
48837e29 DE |
1328 | { |
1329 | /* Since the h8/300 only has 16 bit pointers, negative values are also | |
1330 | those >= 32768. This happens for example with pointer minus a | |
1331 | constant. We don't want to turn (char *p - 2) into | |
1332 | (char *p + 65534) because loop unrolling can build upon this | |
1333 | (IE: char *p + 131068). */ | |
1334 | int n = INTVAL (addr); | |
1335 | if (TARGET_H8300) | |
1336 | n = (int) (short) n; | |
1337 | if (n < 0) | |
1338 | /* ??? Why the special case for -ve values? */ | |
1339 | fprintf (file, "-%d", -n); | |
1340 | else | |
1341 | fprintf (file, "%d", n); | |
1342 | break; | |
1343 | } | |
07aae5c2 SC |
1344 | |
1345 | default: | |
1346 | output_addr_const (file, addr); | |
1347 | break; | |
1348 | } | |
1349 | } | |
1350 | \f | |
07aae5c2 SC |
1351 | /* Output all insn addresses and their sizes into the assembly language |
1352 | output file. This is helpful for debugging whether the length attributes | |
1353 | in the md file are correct. This is not meant to be a user selectable | |
1354 | option. */ | |
1355 | ||
1356 | void | |
1357 | final_prescan_insn (insn, operand, num_operands) | |
1358 | rtx insn, *operand; | |
1359 | int num_operands; | |
1360 | { | |
1361 | /* This holds the last insn address. */ | |
1362 | static int last_insn_address = 0; | |
1363 | ||
1364 | int uid = INSN_UID (insn); | |
1365 | ||
48837e29 DE |
1366 | if (TARGET_RTL_DUMP) |
1367 | { | |
1368 | fprintf (asm_out_file, "\n****************"); | |
1369 | print_rtl (asm_out_file, PATTERN (insn)); | |
1370 | fprintf (asm_out_file, "\n"); | |
1371 | } | |
1372 | ||
07aae5c2 SC |
1373 | if (TARGET_ADDRESSES) |
1374 | { | |
48837e29 | 1375 | fprintf (asm_out_file, "; 0x%x %d\n", insn_addresses[uid], |
07aae5c2 SC |
1376 | insn_addresses[uid] - last_insn_address); |
1377 | last_insn_address = insn_addresses[uid]; | |
1378 | } | |
1379 | } | |
1380 | ||
48837e29 DE |
1381 | /* Prepare for an SI sized move. */ |
1382 | ||
1383 | int | |
1384 | do_movsi (operands) | |
1385 | rtx operands[]; | |
07aae5c2 | 1386 | { |
48837e29 DE |
1387 | rtx src = operands[1]; |
1388 | rtx dst = operands[0]; | |
1389 | if (!reload_in_progress && !reload_completed) | |
1390 | { | |
1391 | if (!register_operand (dst, GET_MODE (dst))) | |
1392 | { | |
1393 | rtx tmp = gen_reg_rtx (GET_MODE (dst)); | |
1394 | emit_move_insn (tmp, src); | |
1395 | operands[1] = tmp; | |
1396 | } | |
1397 | } | |
1398 | return 0; | |
1399 | } | |
1400 | ||
1401 | /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET). | |
1402 | Define the offset between two registers, one to be eliminated, and the other | |
1403 | its replacement, at the start of a routine. */ | |
07aae5c2 | 1404 | |
48837e29 DE |
1405 | int |
1406 | initial_offset (from, to) | |
1407 | { | |
1408 | int offset = 0; | |
1409 | ||
1410 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) | |
1411 | offset = UNITS_PER_WORD + frame_pointer_needed * UNITS_PER_WORD; | |
1412 | else | |
07aae5c2 | 1413 | { |
48837e29 DE |
1414 | int regno; |
1415 | ||
1416 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
1417 | if ((regs_ever_live[regno] | |
1418 | && (!call_used_regs[regno] || regno == FRAME_POINTER_REGNUM))) | |
1419 | offset += UNITS_PER_WORD; | |
1420 | ||
1421 | /* See the comments for get_frame_size. We need to round it up to | |
1422 | STACK_BOUNDARY. */ | |
1423 | ||
1424 | offset += ((get_frame_size () + STACK_BOUNDARY / BITS_PER_UNIT - 1) | |
1425 | & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1)); | |
1426 | ||
1427 | if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
1428 | offset += UNITS_PER_WORD; /* Skip saved PC */ | |
1429 | } | |
1430 | return offset; | |
1431 | } | |
1432 | ||
1433 | /* Update the condition code from the insn. */ | |
1434 | ||
1435 | int | |
1436 | notice_update_cc (body, insn) | |
1437 | rtx body; | |
1438 | rtx insn; | |
1439 | { | |
1440 | switch (get_attr_cc (insn)) | |
1441 | { | |
1442 | case CC_NONE: | |
269c14e1 | 1443 | /* Insn does not affect CC at all. */ |
48837e29 DE |
1444 | break; |
1445 | ||
1446 | case CC_NONE_0HIT: | |
269c14e1 | 1447 | /* Insn does not change CC, but the 0'th operand has been changed. */ |
48837e29 DE |
1448 | if (cc_status.value1 != 0 |
1449 | && reg_overlap_mentioned_p (recog_operand[0], cc_status.value1)) | |
1450 | cc_status.value1 = 0; | |
48837e29 DE |
1451 | break; |
1452 | ||
1453 | case CC_SET: | |
269c14e1 DE |
1454 | /* Insn sets the Z,N flags of CC to recog_operand[0]. |
1455 | V is always set to 0. C may or may not be set to 0 but that's ok | |
1456 | because alter_cond will change tests to use EQ/NE. */ | |
48837e29 | 1457 | CC_STATUS_INIT; |
269c14e1 | 1458 | cc_status.flags |= CC_OVERFLOW_0 | CC_NO_CARRY; |
48837e29 DE |
1459 | cc_status.value1 = recog_operand[0]; |
1460 | break; | |
1461 | ||
269c14e1 DE |
1462 | case CC_SET_ZN_C0: |
1463 | /* Insn sets the Z,N flags of CC to recog_operand[0]. | |
1464 | The V flag is unusable. The C flag may or may not be known but | |
1465 | that's ok because alter_cond will change tests to use EQ/NE. */ | |
48837e29 | 1466 | CC_STATUS_INIT; |
269c14e1 DE |
1467 | cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY; |
1468 | cc_status.value1 = recog_operand[0]; | |
48837e29 DE |
1469 | break; |
1470 | ||
269c14e1 DE |
1471 | case CC_COMPARE: |
1472 | /* The insn is a compare instruction. */ | |
48837e29 | 1473 | CC_STATUS_INIT; |
269c14e1 | 1474 | cc_status.value1 = SET_SRC (body); |
48837e29 DE |
1475 | break; |
1476 | ||
48837e29 | 1477 | case CC_CLOBBER: |
269c14e1 | 1478 | /* Insn doesn't leave CC in a usable state. */ |
48837e29 DE |
1479 | CC_STATUS_INIT; |
1480 | break; | |
07aae5c2 | 1481 | } |
48837e29 DE |
1482 | } |
1483 | ||
269c14e1 DE |
1484 | /* Return 1 if a previous compare needs to be re-issued. This will happen |
1485 | if the compare was deleted because the previous insn set it, but the | |
1486 | branch needs CC flags not set. | |
1487 | ||
1488 | OP is the comparison being performed. */ | |
1489 | ||
1490 | int | |
1491 | restore_compare_p (op) | |
1492 | rtx op; | |
1493 | { | |
1494 | switch (GET_CODE (op)) | |
1495 | { | |
1496 | case EQ: | |
1497 | case NE: | |
1498 | break; | |
1499 | case LT: | |
1500 | case LE: | |
1501 | case GT: | |
1502 | case GE: | |
1503 | if (cc_status.flags & CC_OVERFLOW_UNUSABLE) | |
1504 | return 1; | |
1505 | break; | |
1506 | case LTU: | |
1507 | case LEU: | |
1508 | case GTU: | |
1509 | case GEU: | |
1510 | /* If the carry flag isn't usable, the test should have been changed | |
1511 | by alter_cond. */ | |
1512 | if (cc_status.flags & CC_NO_CARRY) | |
1513 | abort (); | |
1514 | break; | |
1515 | default: | |
1516 | abort (); | |
1517 | } | |
1518 | ||
1519 | return 0; | |
1520 | } | |
1521 | ||
48837e29 DE |
1522 | /* Recognize valid operators for bit instructions */ |
1523 | ||
1524 | int | |
1525 | bit_operator (x, mode) | |
1526 | rtx x; | |
1527 | enum machine_mode mode; | |
1528 | { | |
1529 | enum rtx_code code = GET_CODE (x); | |
07aae5c2 | 1530 | |
48837e29 DE |
1531 | return (code == XOR |
1532 | || code == AND | |
1533 | || code == IOR); | |
07aae5c2 | 1534 | } |
48837e29 DE |
1535 | \f |
1536 | /* Shifts. | |
1537 | ||
1538 | We devote a fair bit of code to getting efficient shifts since we can only | |
1539 | shift one bit at a time. See the .md file for more comments. | |
1540 | ||
1541 | Here are some thoughts on what the absolutely positively best code is. | |
1542 | "Best" here means some rational trade-off between code size and speed, | |
1543 | where speed is more preferred but not at the expense of generating 20 insns. | |
1544 | ||
1545 | H8/300 QImode shifts | |
1546 | 1-4 - do them inline | |
1547 | 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits | |
1548 | ASHIFTRT: loop | |
1549 | 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits | |
1550 | ASHIFTRT: shll, subx (propagate carry bit to all bits) | |
1551 | ||
1552 | H8/300 HImode shifts | |
1553 | 1-4 - do them inline | |
1554 | 5-6 - loop | |
1555 | 7 - shift other way once, move byte into place, move carry bit into place | |
1556 | 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT) | |
1557 | 9 - inline shift 1-4, move byte, set other byte | |
1558 | 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0 | |
1559 | - ASHIFTRT: loop | |
1560 | 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0 | |
1561 | - ASHIFTRT: shll, subx, set other byte | |
1562 | ||
1563 | H8/300 SImode shifts | |
1564 | 1-2 - do them inline | |
1565 | 3-6 - loop | |
1566 | 7 - shift other way once, move bytes into place, | |
1567 | move carry into place (possibly with sign extension) | |
1568 | 8 - move bytes into place, zero or sign extend other | |
1569 | 9-14 - loop | |
1570 | 15 - shift other way once, move word into place, move carry into place | |
1571 | 16 - move word, zero or sign extend other | |
1572 | 17-23 - loop | |
1573 | 24 - move bytes into place, zero or sign extend other | |
1574 | 25-27 - loop | |
1575 | 28-30 - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place, | |
1576 | zero others | |
1577 | ASHIFTRT: loop | |
1578 | 31 - ASHIFT | LSHIFTRT: rotate top byte, mask, byte byte into place, | |
1579 | zero others | |
1580 | ASHIFTRT: shll top byte, subx, copy to other bytes | |
1581 | ||
1582 | H8/300H QImode shifts | |
1583 | - same as H8/300 | |
1584 | ||
1585 | H8/300H HImode shifts | |
1586 | - same as H8/300 | |
1587 | ||
1588 | H8/300H SImode shifts | |
1589 | (These are complicated by the fact that we don't have byte level access to | |
1590 | the top word.) | |
1591 | A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw) | |
1592 | 1-4 - do them inline | |
1593 | 5-14 - loop | |
1594 | 15 - shift other way once, move word into place, move carry into place | |
1595 | (with sign extension for ASHIFTRT) | |
1596 | 16 - move word into place, zero or sign extend other | |
1597 | 17-23 - loop | |
1598 | 24 - ASHIFT: move byte 0(msb) to byte 1, zero byte 0, | |
1599 | move word 0 to word 1, zero word 0 | |
1600 | LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0, | |
1601 | zero word 1, zero byte 1 | |
1602 | ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0, | |
1603 | sign extend byte 0, sign extend word 0 | |
1604 | 25-27 - either loop, or | |
1605 | do 24 bit shift, inline rest | |
1606 | 28-30 - ASHIFT: rotate 4/3/2, mask | |
1607 | LSHIFTRT: rotate 4/3/2, mask | |
1608 | ASHIFTRT: loop | |
1609 | 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0 | |
1610 | ||
1611 | Don't Panic!!! | |
1612 | ||
1613 | All of these haven't been implemented. I've just documented them and | |
1614 | provided hooks so they can be. | |
1615 | */ | |
07aae5c2 SC |
1616 | |
1617 | int | |
48837e29 DE |
1618 | nshift_operator (x, mode) |
1619 | rtx x; | |
1620 | enum machine_mode mode; | |
1621 | { | |
1622 | switch (GET_CODE (x)) | |
1623 | { | |
1624 | case ASHIFTRT: | |
1625 | case LSHIFTRT: | |
1626 | case ASHIFT: | |
1627 | return 1; | |
1628 | ||
1629 | default: | |
1630 | return 0; | |
1631 | } | |
1632 | } | |
1633 | ||
1634 | /* Called from the .md file to emit code to do shifts. | |
1635 | Returns a boolean indicating success | |
1636 | (currently this is always TRUE). */ | |
1637 | ||
1638 | int | |
1639 | expand_a_shift (mode, code, operands) | |
1640 | enum machine_mode mode; | |
07aae5c2 SC |
1641 | int code; |
1642 | rtx operands[]; | |
07aae5c2 | 1643 | { |
07aae5c2 SC |
1644 | emit_move_insn (operands[0], operands[1]); |
1645 | ||
48837e29 DE |
1646 | /* need a loop to get all the bits we want - we generate the |
1647 | code at emit time, but need to allocate a scratch reg now */ | |
1648 | ||
1649 | emit_insn (gen_rtx | |
1650 | (PARALLEL, VOIDmode, | |
1651 | gen_rtvec (2, | |
1652 | gen_rtx (SET, VOIDmode, operands[0], | |
1653 | gen_rtx (code, mode, operands[0], operands[2])), | |
1654 | gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, QImode, 0))))); | |
1655 | ||
1656 | return 1; | |
1657 | } | |
1658 | ||
1659 | /* Shift algorithm determination. | |
1660 | ||
1661 | There are various ways of doing a shift: | |
1662 | SHIFT_INLINE: If the amount is small enough, just generate as many one-bit | |
1663 | shifts as we need. | |
1664 | SHIFT_ROT_AND: If the amount is large but close to either end, rotate the | |
1665 | necessary bits into position and then set the rest to zero. | |
1666 | SHIFT_SPECIAL: Hand crafted assembler. | |
1667 | SHIFT_LOOP: If the above methods fail, just loop. */ | |
1668 | ||
1669 | enum shift_alg | |
1670 | { | |
1671 | SHIFT_INLINE, | |
1672 | SHIFT_ROT_AND, | |
1673 | SHIFT_SPECIAL, | |
1674 | SHIFT_LOOP, | |
1675 | SHIFT_MAX | |
1676 | }; | |
1677 | ||
1678 | /* Symbols of the various shifts which can be used as indices. */ | |
1679 | ||
1680 | enum shift_type | |
1681 | { | |
1682 | SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT | |
1683 | }; | |
1684 | ||
1685 | /* Symbols of the various modes which can be used as indices. */ | |
1686 | ||
1687 | enum shift_mode | |
1688 | { | |
1689 | QIshift, HIshift, SIshift | |
1690 | }; | |
1691 | ||
269c14e1 DE |
1692 | /* For single bit shift insns, record assembler and what bits of the |
1693 | condition code are valid afterwards (represented as various CC_FOO | |
1694 | bits, 0 means CC isn't left in a usable state). */ | |
48837e29 DE |
1695 | |
1696 | struct shift_insn | |
1697 | { | |
1698 | char *assembler; | |
1699 | int cc_valid; | |
1700 | }; | |
1701 | ||
1702 | /* Assembler instruction shift table. | |
1703 | ||
1704 | These tables are used to look up the basic shifts. | |
1705 | They are indexed by cpu, shift_type, and mode. | |
1706 | */ | |
07aae5c2 | 1707 | |
48837e29 DE |
1708 | static const struct shift_insn shift_one[2][3][3] = |
1709 | { | |
1710 | /* H8/300 */ | |
1711 | { | |
1712 | /* SHIFT_ASHIFT */ | |
1713 | { | |
269c14e1 DE |
1714 | { "shll %X0", CC_OVERFLOW_0 | CC_NO_CARRY }, |
1715 | { "add.w %T0,%T0\t; shal.w", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }, | |
48837e29 DE |
1716 | { "add.w %f0,%f0\t; shal.l\n\taddx %y0,%y0\n\taddx %z0,%z0\t; end shal.l", 0 } |
1717 | }, | |
1718 | /* SHIFT_LSHIFTRT */ | |
1719 | { | |
269c14e1 | 1720 | { "shlr %X0", CC_OVERFLOW_0 | CC_NO_CARRY }, |
48837e29 DE |
1721 | { "shlr %t0\t; shlr.w\n\trotxr %s0\t; end shlr.w", 0 }, |
1722 | { "shlr %z0\t; shlr.l\n\trotxr %y0\n\trotxr %x0\n\trotxr %w0\t; end shlr.l", 0 } | |
1723 | }, | |
1724 | /* SHIFT_ASHIFTRT */ | |
1725 | { | |
269c14e1 | 1726 | { "shar %X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }, |
48837e29 DE |
1727 | { "shar %t0\t; shar.w\n\trotxr %s0\t; end shar.w", 0 }, |
1728 | { "shar %z0\t; shar.l\n\trotxr %y0\n\trotxr %x0\n\trotxr %w0\t; end shar.l", 0 } | |
1729 | } | |
1730 | }, | |
1731 | /* H8/300H */ | |
1732 | { | |
1733 | /* SHIFT_ASHIFT */ | |
1734 | { | |
269c14e1 DE |
1735 | { "shll.b %X0", CC_OVERFLOW_0 | CC_NO_CARRY }, |
1736 | { "shll.w %T0", CC_OVERFLOW_0 | CC_NO_CARRY }, | |
1737 | { "shll.l %S0", CC_OVERFLOW_0 | CC_NO_CARRY } | |
48837e29 DE |
1738 | }, |
1739 | /* SHIFT_LSHIFTRT */ | |
1740 | { | |
269c14e1 DE |
1741 | { "shlr.b %X0", CC_OVERFLOW_0 | CC_NO_CARRY }, |
1742 | { "shlr.w %T0", CC_OVERFLOW_0 | CC_NO_CARRY }, | |
1743 | { "shlr.l %S0", CC_OVERFLOW_0 | CC_NO_CARRY } | |
48837e29 DE |
1744 | }, |
1745 | /* SHIFT_ASHIFTRT */ | |
1746 | { | |
269c14e1 DE |
1747 | { "shar.b %X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }, |
1748 | { "shar.w %T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }, | |
1749 | { "shar.l %S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY } | |
48837e29 DE |
1750 | } |
1751 | } | |
1752 | }; | |
07aae5c2 | 1753 | |
48837e29 DE |
1754 | /* Rotates are organized by which shift they'll be used in implementing. |
1755 | There's no need to record whether the cc is valid afterwards because | |
1756 | it is the AND insn that will decide this. */ | |
07aae5c2 | 1757 | |
48837e29 DE |
1758 | static const char *const rotate_one[2][3][3] = |
1759 | { | |
1760 | /* H8/300 */ | |
1761 | { | |
1762 | /* SHIFT_ASHIFT */ | |
1763 | { | |
1764 | "rotr %X0", | |
1765 | "shlr %t0\t; rotr.w\n\trotxr %s0\n\tbst #7,%t0\t; end rotr.w", | |
1766 | 0 | |
1767 | }, | |
1768 | /* SHIFT_LSHIFTRT */ | |
1769 | { | |
1770 | "rotl %X0", | |
1771 | "shll %s0\t; rotl.w\n\trotxl %t0\n\tbst #0,%s0\t; end rotl.w", | |
1772 | 0 | |
1773 | }, | |
1774 | /* SHIFT_ASHIFTRT */ | |
1775 | { | |
1776 | "rotl %X0", | |
1777 | "shll %s0\t; rotl.w\n\trotxl %t0\n\tbst #0,%s0\t; end rotl.w", | |
1778 | 0 | |
07aae5c2 | 1779 | } |
48837e29 DE |
1780 | }, |
1781 | /* H8/300H */ | |
1782 | { | |
1783 | /* SHIFT_ASHIFT */ | |
1784 | { | |
1785 | "rotr.b %X0", | |
1786 | "rotr.w %T0", | |
1787 | "rotr.l %S0" | |
1788 | }, | |
1789 | /* SHIFT_LSHIFTRT */ | |
07aae5c2 | 1790 | { |
48837e29 DE |
1791 | "rotl.b %X0", |
1792 | "rotl.w %T0", | |
1793 | "rotl.l %S0" | |
1794 | }, | |
1795 | /* SHIFT_ASHIFTRT */ | |
1796 | { | |
1797 | "rotl.b %X0", | |
1798 | "rotl.w %T0", | |
1799 | "rotl.l %S0" | |
1800 | } | |
1801 | } | |
1802 | }; | |
1803 | ||
1804 | /* Given CPU, MODE, SHIFT_TYPE, and shift count COUNT, determine the best | |
1805 | algorithm for doing the shift. The assembler code is stored in ASSEMBLER. | |
1806 | We don't achieve maximum efficiency in all cases, but the hooks are here | |
1807 | to do so. | |
1808 | ||
1809 | For now we just use lots of switch statements. Since we don't even come | |
1810 | close to supporting all the cases, this is simplest. If this function ever | |
1811 | gets too big, perhaps resort to a more table based lookup. Of course, | |
1812 | at this point you may just wish to do it all in rtl. | |
1813 | ||
1814 | WARNING: The constraints on insns shiftbyn_QI/HI/SI assume shifts of | |
1815 | 1,2,3,4 will be inlined (1,2 for SI). */ | |
1816 | ||
1817 | static enum shift_alg | |
1818 | get_shift_alg (cpu, shift_type, mode, count, assembler_p, cc_valid_p) | |
1819 | enum attr_cpu cpu; | |
1820 | enum shift_type shift_type; | |
1821 | enum machine_mode mode; | |
1822 | int count; | |
1823 | const char **assembler_p; | |
1824 | int *cc_valid_p; | |
1825 | { | |
1826 | /* The default is to loop. */ | |
1827 | enum shift_alg alg = SHIFT_LOOP; | |
1828 | enum shift_mode shift_mode; | |
1829 | ||
1830 | /* We don't handle negative shifts or shifts greater than the word size, | |
1831 | they should have been handled already. */ | |
07aae5c2 | 1832 | |
48837e29 DE |
1833 | if (count < 0 || count > GET_MODE_BITSIZE (mode)) |
1834 | abort (); | |
1835 | ||
1836 | switch (mode) | |
1837 | { | |
1838 | case QImode: | |
1839 | shift_mode = QIshift; | |
1840 | break; | |
1841 | case HImode: | |
1842 | shift_mode = HIshift; | |
1843 | break; | |
1844 | case SImode: | |
1845 | shift_mode = SIshift; | |
1846 | break; | |
1847 | default: | |
1848 | abort (); | |
1849 | } | |
1850 | ||
1851 | /* Assume either SHIFT_LOOP or SHIFT_INLINE. | |
1852 | It is up to the caller to know that looping clobbers cc. */ | |
1853 | *assembler_p = shift_one[cpu][shift_type][shift_mode].assembler; | |
1854 | *cc_valid_p = shift_one[cpu][shift_type][shift_mode].cc_valid; | |
1855 | ||
1856 | /* Now look for cases we want to optimize. */ | |
1857 | ||
1858 | switch (shift_mode) | |
1859 | { | |
1860 | case QIshift: | |
1861 | if (count <= 4) | |
1862 | return SHIFT_INLINE; | |
1863 | else if (count <= 6) | |
07aae5c2 | 1864 | { |
48837e29 DE |
1865 | if (shift_type == SHIFT_ASHIFTRT) |
1866 | { | |
1867 | return SHIFT_LOOP; | |
1868 | } | |
1869 | else | |
1870 | { | |
1871 | *assembler_p = rotate_one[cpu][shift_type][shift_mode]; | |
1872 | *cc_valid_p = 0; | |
1873 | return SHIFT_ROT_AND; | |
1874 | } | |
07aae5c2 | 1875 | } |
48837e29 | 1876 | else if (count == 7) |
07aae5c2 | 1877 | { |
48837e29 DE |
1878 | if (shift_type == SHIFT_ASHIFTRT) |
1879 | { | |
1880 | *assembler_p = "shll %X0\t; shar.b(7)\n\tsubx %X0,%X0\t; end shar.b(7)"; | |
1881 | *cc_valid_p = 0; | |
1882 | return SHIFT_SPECIAL; | |
1883 | } | |
1884 | else | |
1885 | { | |
1886 | *assembler_p = rotate_one[cpu][shift_type][shift_mode]; | |
1887 | *cc_valid_p = 0; | |
1888 | return SHIFT_ROT_AND; | |
1889 | } | |
07aae5c2 | 1890 | } |
48837e29 DE |
1891 | break; |
1892 | case HIshift: | |
1893 | if (count <= 4) | |
1894 | return SHIFT_INLINE; | |
1895 | else if (count == 8) | |
1896 | { | |
1897 | switch (shift_type) | |
1898 | { | |
1899 | case SHIFT_ASHIFT: | |
1900 | *assembler_p = "mov.b %s0,%t0\t; shal.w(8)\n\tsub.b %s0,%s0\t; end shal.w(8)"; | |
1901 | *cc_valid_p = 0; | |
1902 | return SHIFT_SPECIAL; | |
1903 | case SHIFT_LSHIFTRT: | |
1904 | *assembler_p = "mov.b %t0,%s0\t; shlr.w(8)\n\tsub.b %t0,%t0\t; end shlr.w(8)"; | |
1905 | *cc_valid_p = 0; | |
1906 | return SHIFT_SPECIAL; | |
1907 | case SHIFT_ASHIFTRT: | |
1908 | if (cpu == CPU_H8300) | |
1909 | *assembler_p = "mov.b %t0,%s0\t; shar.w(8)\n\tshll %t0\n\tsubx %t0,%t0\t; end shar.w(8)"; | |
1910 | else | |
1911 | *assembler_p = "mov.b %t0,%s0\t; shar.w(8)\n\texts.w %T0\t; end shar.w(8)"; | |
1912 | *cc_valid_p = 0; | |
1913 | return SHIFT_SPECIAL; | |
1914 | } | |
1915 | abort (); | |
1916 | } | |
1917 | else if (count == 15) | |
07aae5c2 | 1918 | { |
48837e29 DE |
1919 | if (shift_type == SHIFT_ASHIFTRT) |
1920 | { | |
1921 | *assembler_p = "shll %t0,%t0\t; shar.w(15)\n\tsubx %t0,%t0\n\tmov.b %t0,%s0\t; end shar.w(15)"; | |
1922 | *cc_valid_p = 0; | |
1923 | return SHIFT_SPECIAL; | |
1924 | } | |
1925 | else | |
1926 | { | |
1927 | *assembler_p = rotate_one[cpu][shift_type][shift_mode]; | |
1928 | *cc_valid_p = 0; | |
1929 | return SHIFT_ROT_AND; | |
1930 | } | |
07aae5c2 | 1931 | } |
48837e29 DE |
1932 | break; |
1933 | case SIshift: | |
1934 | if (count <= (cpu == CPU_H8300 ? 2 : 4)) | |
1935 | return SHIFT_INLINE; | |
1936 | else if (count == 8) | |
1937 | { | |
1938 | if (cpu == CPU_H8300) | |
1939 | { | |
1940 | switch (shift_type) | |
1941 | { | |
1942 | case SHIFT_ASHIFT: | |
1943 | *assembler_p = "mov.b %y0,%z0\t; shal.l(8)\n\tmov.b %x0,%y0\n\tmov.b %w0,%x0\n\tsub.b %w0,%w0\t; end shal.l(8)"; | |
1944 | *cc_valid_p = 0; | |
1945 | return SHIFT_SPECIAL; | |
1946 | case SHIFT_LSHIFTRT: | |
1947 | *assembler_p = "mov.b %x0,%w0\t; shlr.l(8)\n\tmov.b %y0,%x0\n\tmov.b %z0,%y0\n\tsub.b %z0,%z0\t; end shlr.l(8)"; | |
1948 | *cc_valid_p = 0; | |
1949 | return SHIFT_SPECIAL; | |
1950 | case SHIFT_ASHIFTRT: | |
1951 | *assembler_p = "mov.b %x0,%w0\t; shar.l(8)\n\tmov.b %y0,%x0\n\tmov.b %z0,%y0\n\tshll %z0\n\tsubx %z0,%z0; end shar.l(8)"; | |
1952 | *cc_valid_p = 0; | |
1953 | return SHIFT_SPECIAL; | |
1954 | } | |
1955 | } | |
1956 | else /* CPU_H8300H */ | |
1957 | /* We don't have byte level access to the high word so this isn't | |
1958 | easy to do. For now, just loop. */ | |
1959 | ; | |
1960 | } | |
1961 | else if (count == 16) | |
1962 | { | |
1963 | switch (shift_type) | |
1964 | { | |
1965 | case SHIFT_ASHIFT: | |
1966 | *assembler_p = "mov.w %f0,%e0\t; shal.l(16)\n\tsub.w %f0,%f0\t; end shal.l(16)"; | |
1967 | *cc_valid_p = 0; | |
1968 | return SHIFT_SPECIAL; | |
1969 | case SHIFT_LSHIFTRT: | |
1970 | *assembler_p = "mov.w %e0,%f0\t; shlr.l(16)\n\tsub.w %e0,%e0\t; end shlr.l(16)"; | |
1971 | *cc_valid_p = 0; | |
1972 | return SHIFT_SPECIAL; | |
1973 | case SHIFT_ASHIFTRT: | |
1974 | if (cpu == CPU_H8300) | |
1975 | *assembler_p = "mov.w %e0,%f0\t; shar.l(16)\n\tshll %z0\n\tsubx %z0,%z0\n\tmov.b %z0,%y0\t; end shar.l(16)"; | |
1976 | else | |
1977 | *assembler_p = "mov.w %e0,%f0\t; shar.l(16)\n\texts.l %S0\t; end shar.l(16)"; | |
1978 | *cc_valid_p = 0; | |
1979 | return SHIFT_SPECIAL; | |
1980 | } | |
1981 | } | |
1982 | else if (count >= 28 && count <= 30) | |
1983 | { | |
1984 | if (shift_type == SHIFT_ASHIFTRT) | |
1985 | { | |
1986 | return SHIFT_LOOP; | |
1987 | } | |
1988 | else | |
1989 | { | |
1990 | if (cpu == CPU_H8300) | |
1991 | return SHIFT_LOOP; | |
1992 | else | |
1993 | { | |
1994 | *assembler_p = rotate_one[cpu][shift_type][shift_mode]; | |
1995 | *cc_valid_p = 0; | |
1996 | return SHIFT_ROT_AND; | |
1997 | } | |
1998 | } | |
1999 | } | |
2000 | else if (count == 31) | |
2001 | { | |
2002 | if (shift_type == SHIFT_ASHIFTRT) | |
2003 | { | |
2004 | if (cpu == CPU_H8300) | |
2005 | *assembler_p = "shll %z0\t; shar.l(31)\n\tsubx %w0,%w0\n\tmov.b %w0,%x0\n\tmov.w %f0,%e0\t; end shar.l(31)"; | |
2006 | else | |
2007 | *assembler_p = "shll %e0\t; shar.l(31)\n\tsubx %w0,%w0\n\tmov.b %w0,%x0\n\tmov.w %f0,%e0\t; end shar.l(31)"; | |
2008 | *cc_valid_p = 0; | |
2009 | return SHIFT_SPECIAL; | |
2010 | } | |
2011 | else | |
2012 | { | |
2013 | if (cpu == CPU_H8300) | |
2014 | { | |
2015 | if (shift_type == SHIFT_ASHIFT) | |
2016 | *assembler_p = "sub.w %e0,%e0\t; shal.l(31)\n\tshlr %w0\n\tmov.w %e0,%f0\n\trotxr %z0\t; end shal.l(31)"; | |
2017 | else | |
2018 | *assembler_p = "sub.w %f0,%f0\t; shlr.l(31)\n\tshll %z0\n\tmov.w %f0,%e0\n\trotxl %w0\t; end shlr.l(31)"; | |
2019 | *cc_valid_p = 0; | |
2020 | return SHIFT_SPECIAL; | |
2021 | } | |
2022 | else | |
2023 | { | |
2024 | *assembler_p = rotate_one[cpu][shift_type][shift_mode]; | |
2025 | *cc_valid_p = 0; | |
2026 | return SHIFT_ROT_AND; | |
2027 | } | |
2028 | } | |
2029 | } | |
2030 | break; | |
2031 | default: | |
2032 | abort (); | |
07aae5c2 | 2033 | } |
48837e29 DE |
2034 | |
2035 | return alg; | |
07aae5c2 SC |
2036 | } |
2037 | ||
48837e29 DE |
2038 | /* Emit the assembler code for doing shifts. */ |
2039 | ||
2040 | char * | |
2041 | emit_a_shift (insn, operands) | |
2042 | rtx insn; | |
2043 | rtx *operands; | |
07aae5c2 | 2044 | { |
48837e29 DE |
2045 | static int loopend_lab; |
2046 | char *assembler; | |
2047 | int cc_valid; | |
2048 | rtx inside = PATTERN (insn); | |
2049 | rtx shift = operands[3]; | |
2050 | enum machine_mode mode = GET_MODE (shift); | |
2051 | enum rtx_code code = GET_CODE (shift); | |
2052 | enum shift_type shift_type; | |
2053 | enum shift_mode shift_mode; | |
2054 | ||
2055 | loopend_lab++; | |
2056 | ||
2057 | switch (mode) | |
2058 | { | |
2059 | case QImode: | |
2060 | shift_mode = QIshift; | |
2061 | break; | |
2062 | case HImode: | |
2063 | shift_mode = HIshift; | |
2064 | break; | |
2065 | case SImode: | |
2066 | shift_mode = SIshift; | |
2067 | break; | |
2068 | default: | |
2069 | abort (); | |
2070 | } | |
07aae5c2 | 2071 | |
48837e29 | 2072 | switch (code) |
07aae5c2 | 2073 | { |
48837e29 DE |
2074 | case ASHIFTRT: |
2075 | shift_type = SHIFT_ASHIFTRT; | |
2076 | break; | |
2077 | case LSHIFTRT: | |
2078 | shift_type = SHIFT_LSHIFTRT; | |
2079 | break; | |
2080 | case ASHIFT: | |
2081 | shift_type = SHIFT_ASHIFT; | |
2082 | break; | |
2083 | default: | |
2084 | abort (); | |
2085 | } | |
07aae5c2 | 2086 | |
48837e29 DE |
2087 | if (GET_CODE (operands[2]) != CONST_INT) |
2088 | { | |
2089 | /* Indexing by reg, so have to loop and test at top */ | |
2090 | output_asm_insn ("mov.b %X2,%X4", operands); | |
2091 | fprintf (asm_out_file, "\tble .Lle%d\n", loopend_lab); | |
2092 | ||
2093 | /* Get the assembler code to do one shift. */ | |
2094 | get_shift_alg (cpu_type, shift_type, mode, 1, &assembler, &cc_valid); | |
2095 | } | |
2096 | else | |
2097 | { | |
2098 | int n = INTVAL (operands[2]); | |
2099 | enum shift_alg alg; | |
2100 | ||
2101 | /* If the count is negative, make it 0. */ | |
2102 | if (n < 0) | |
2103 | n = 0; | |
2104 | /* If the count is too big, truncate it. | |
2105 | ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to | |
2106 | do the intuitive thing. */ | |
2107 | else if (n > GET_MODE_BITSIZE (mode)) | |
2108 | n = GET_MODE_BITSIZE (mode); | |
2109 | ||
2110 | alg = get_shift_alg (cpu_type, shift_type, mode, n, &assembler, &cc_valid); | |
2111 | ||
2112 | switch (alg) | |
2113 | { | |
2114 | case SHIFT_INLINE: | |
2115 | while (--n >= 0) | |
2116 | output_asm_insn (assembler, operands); | |
2117 | if (cc_valid) | |
269c14e1 DE |
2118 | { |
2119 | cc_status.value1 = operands[0]; | |
2120 | cc_status.flags |= cc_valid; | |
2121 | } | |
48837e29 DE |
2122 | return ""; |
2123 | case SHIFT_ROT_AND: | |
2124 | { | |
2125 | int m = GET_MODE_BITSIZE (mode) - n; | |
2126 | int mask = (shift_type == SHIFT_ASHIFT | |
2127 | ? ((1 << GET_MODE_BITSIZE (mode) - n) - 1) << n | |
2128 | : (1 << GET_MODE_BITSIZE (mode) - n) - 1); | |
2129 | char insn_buf[200]; | |
2130 | /* Not all possibilities of rotate are supported. They shouldn't | |
2131 | be generated, but let's watch for 'em. */ | |
2132 | if (assembler == 0) | |
2133 | abort (); | |
2134 | while (--m >= 0) | |
2135 | output_asm_insn (assembler, operands); | |
2136 | if (TARGET_H8300) | |
2137 | { | |
2138 | switch (mode) | |
2139 | { | |
2140 | case QImode: | |
2141 | sprintf (insn_buf, "and #%d,%%X0\t; end shift %d via rotate+and", | |
2142 | mask, n); | |
2143 | cc_status.value1 = operands[0]; | |
269c14e1 | 2144 | cc_status.flags |= CC_OVERFLOW_0 | CC_NO_CARRY; |
48837e29 DE |
2145 | break; |
2146 | case HImode: | |
2147 | sprintf (insn_buf, "and #%d,%%s0\n\tand #%d,%%t0\t; end shift %d via rotate+and", | |
2148 | mask & 255, mask >> 8, n); | |
2149 | break; | |
2150 | case SImode: | |
2151 | abort (); | |
2152 | } | |
2153 | } | |
2154 | else | |
2155 | { | |
2156 | sprintf (insn_buf, "and.%c #%d,%%%c0", | |
2157 | "bwl"[shift_mode], mask, | |
2158 | mode == QImode ? 'X' : mode == HImode ? 'T' : 'S'); | |
2159 | cc_status.value1 = operands[0]; | |
269c14e1 | 2160 | cc_status.flags |= CC_OVERFLOW_0 | CC_NO_CARRY; |
48837e29 DE |
2161 | } |
2162 | output_asm_insn (insn_buf, operands); | |
2163 | return ""; | |
2164 | } | |
2165 | case SHIFT_SPECIAL: | |
2166 | output_asm_insn (assembler, operands); | |
2167 | return ""; | |
07aae5c2 | 2168 | } |
48837e29 DE |
2169 | |
2170 | /* Need a loop, move limit to tmp reg */ | |
2171 | fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n, names_big[REGNO (operands[4])]); | |
07aae5c2 | 2172 | } |
48837e29 DE |
2173 | |
2174 | fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); | |
2175 | output_asm_insn (assembler, operands); | |
2176 | output_asm_insn ("add #0xff,%X4", operands); | |
2177 | fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); | |
2178 | fprintf (asm_out_file, ".Lle%d:\n", loopend_lab); | |
2179 | ||
2180 | return ""; | |
07aae5c2 | 2181 | } |
48837e29 DE |
2182 | \f |
2183 | /* Fix the operands of a gen_xxx so that it could become a bit | |
2184 | operating insn. */ | |
07aae5c2 SC |
2185 | |
2186 | int | |
48837e29 DE |
2187 | fix_bit_operand (operands, what, type) |
2188 | rtx *operands; | |
2189 | char what; | |
2190 | enum rtx_code type; | |
07aae5c2 | 2191 | { |
abc95ed3 | 2192 | /* The bit_operand predicate accepts any memory during RTL generation, but |
48837e29 DE |
2193 | only 'U' memory afterwards, so if this is a MEM operand, we must force |
2194 | it to be valid for 'U' by reloading the address. */ | |
07aae5c2 | 2195 | |
48837e29 | 2196 | if (GET_CODE (operands[2]) == CONST_INT) |
07aae5c2 | 2197 | { |
48837e29 DE |
2198 | if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), what)) |
2199 | { | |
2200 | /* Ok to have a memory dest. */ | |
2201 | if (GET_CODE (operands[0]) == MEM && !EXTRA_CONSTRAINT (operands[0], 'U')) | |
2202 | { | |
2203 | rtx mem; | |
2204 | mem = gen_rtx (MEM, GET_MODE (operands[0]), | |
2205 | copy_to_mode_reg (Pmode, XEXP (operands[0], 0))); | |
2206 | RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (operands[0]); | |
2207 | MEM_IN_STRUCT_P (mem) = MEM_IN_STRUCT_P (operands[0]); | |
2208 | MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (operands[0]); | |
2209 | operands[0] = mem; | |
2210 | } | |
2211 | ||
2212 | if (GET_CODE (operands[1]) == MEM && !EXTRA_CONSTRAINT (operands[1], 'U')) | |
2213 | { | |
2214 | rtx mem; | |
2215 | mem = gen_rtx (MEM, GET_MODE (operands[1]), | |
2216 | copy_to_mode_reg (Pmode, XEXP (operands[1], 0))); | |
2217 | RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (operands[1]); | |
2218 | MEM_IN_STRUCT_P (mem) = MEM_IN_STRUCT_P (operands[1]); | |
2219 | MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (operands[1]); | |
2220 | operands[1] = mem; | |
2221 | } | |
2222 | return 0; | |
2223 | } | |
2224 | } | |
07aae5c2 | 2225 | |
48837e29 | 2226 | /* Dest and src op must be register. */ |
07aae5c2 | 2227 | |
48837e29 DE |
2228 | operands[1] = force_reg (QImode, operands[1]); |
2229 | { | |
2230 | rtx res = gen_reg_rtx (QImode); | |
2231 | emit_insn (gen_rtx (SET, VOIDmode, res, gen_rtx (type, QImode, operands[1], operands[2]))); | |
2232 | emit_insn (gen_rtx (SET, VOIDmode, operands[0], res)); | |
2233 | } | |
2234 | return 1; | |
07aae5c2 | 2235 | } |
f5b65a56 | 2236 | |
f5b65a56 JL |
2237 | /* Return nonzero if FUNC is an interrupt function as specified |
2238 | by the "interrupt" attribute. */ | |
2239 | ||
2240 | static int | |
2241 | h8300_interrupt_function_p (func) | |
2242 | tree func; | |
2243 | { | |
2244 | tree a; | |
2245 | ||
2246 | if (TREE_CODE (func) != FUNCTION_DECL) | |
2247 | return 0; | |
2248 | ||
97c5ec1d | 2249 | a = lookup_attribute ("interrupt_handler", DECL_MACHINE_ATTRIBUTES (func)); |
f5b65a56 JL |
2250 | return a != NULL_TREE; |
2251 | } | |
2252 | ||
fabe72bb JL |
2253 | /* Return nonzero if FUNC is an OS_Task function as specified |
2254 | by the "OS_Task" attribute. */ | |
2255 | ||
2256 | static int | |
2257 | h8300_os_task_function_p (func) | |
2258 | tree func; | |
2259 | { | |
2260 | tree a; | |
2261 | ||
2262 | if (TREE_CODE (func) != FUNCTION_DECL) | |
2263 | return 0; | |
2264 | ||
2265 | a = lookup_attribute ("OS_Task", DECL_MACHINE_ATTRIBUTES (func)); | |
2266 | return a != NULL_TREE; | |
2267 | } | |
2268 | ||
2269 | /* Return nonzero if FUNC is a monitor function as specified | |
2270 | by the "monitor" attribute. */ | |
2271 | ||
2272 | static int | |
2273 | h8300_monitor_function_p (func) | |
2274 | tree func; | |
2275 | { | |
2276 | tree a; | |
2277 | ||
2278 | if (TREE_CODE (func) != FUNCTION_DECL) | |
2279 | return 0; | |
2280 | ||
2281 | a = lookup_attribute ("monitor", DECL_MACHINE_ATTRIBUTES (func)); | |
2282 | return a != NULL_TREE; | |
2283 | } | |
2284 | ||
f5b65a56 JL |
2285 | /* Return nonzero if FUNC is a function that should be called |
2286 | through the function vector. */ | |
2287 | ||
2288 | int | |
2289 | h8300_funcvec_function_p (func) | |
2290 | tree func; | |
2291 | { | |
2292 | tree a; | |
2293 | ||
2294 | if (TREE_CODE (func) != FUNCTION_DECL) | |
2295 | return 0; | |
2296 | ||
97c5ec1d | 2297 | a = lookup_attribute ("function_vector", DECL_MACHINE_ATTRIBUTES (func)); |
f5b65a56 JL |
2298 | return a != NULL_TREE; |
2299 | } | |
2300 | ||
887a8bd9 | 2301 | /* Return nonzero if DECL is a variable that's in the eight bit |
15dc331e JL |
2302 | data area. */ |
2303 | ||
2304 | int | |
fabdc32d | 2305 | h8300_eightbit_data_p (decl) |
15dc331e JL |
2306 | tree decl; |
2307 | { | |
2308 | tree a; | |
2309 | ||
2310 | if (TREE_CODE (decl) != VAR_DECL) | |
2311 | return 0; | |
2312 | ||
fabdc32d | 2313 | a = lookup_attribute ("eightbit_data", DECL_MACHINE_ATTRIBUTES (decl)); |
15dc331e JL |
2314 | return a != NULL_TREE; |
2315 | } | |
2316 | ||
887a8bd9 JL |
2317 | /* Return nonzero if DECL is a variable that's in the tiny |
2318 | data area. */ | |
2319 | ||
2320 | int | |
2321 | h8300_tiny_data_p (decl) | |
2322 | tree decl; | |
2323 | { | |
2324 | tree a; | |
2325 | ||
2326 | if (TREE_CODE (decl) != VAR_DECL) | |
2327 | return 0; | |
2328 | ||
2329 | a = lookup_attribute ("tiny_data", DECL_MACHINE_ATTRIBUTES (decl)); | |
2330 | return a != NULL_TREE; | |
2331 | } | |
2332 | ||
f5b65a56 JL |
2333 | /* Return nonzero if ATTR is a valid attribute for DECL. |
2334 | ATTRIBUTES are any existing attributes and ARGS are the arguments | |
2335 | supplied with ATTR. | |
2336 | ||
2337 | Supported attributes: | |
2338 | ||
97c5ec1d | 2339 | interrupt_handler: output a prologue and epilogue suitable for an |
f5b65a56 JL |
2340 | interrupt handler. |
2341 | ||
97c5ec1d | 2342 | function_vector: This function should be called through the |
887a8bd9 JL |
2343 | function vector. |
2344 | ||
2345 | eightbit_data: This variable lives in the 8-bit data area and can | |
2346 | be referenced with 8-bit absolute memory addresses. | |
2347 | ||
2348 | tiny_data: This variable lives in the tiny data area and can be | |
2349 | referenced with 16-bit absolute memory references. */ | |
f5b65a56 JL |
2350 | |
2351 | int | |
2352 | h8300_valid_machine_decl_attribute (decl, attributes, attr, args) | |
2353 | tree decl; | |
2354 | tree attributes; | |
2355 | tree attr; | |
2356 | tree args; | |
2357 | { | |
2358 | if (args != NULL_TREE) | |
2359 | return 0; | |
2360 | ||
97c5ec1d | 2361 | if (is_attribute_p ("interrupt_handler", attr) |
fabe72bb JL |
2362 | || is_attribute_p ("OS_Task", attr) |
2363 | || is_attribute_p ("monitor", attr) | |
97c5ec1d | 2364 | || is_attribute_p ("function_vector", attr)) |
f5b65a56 | 2365 | return TREE_CODE (decl) == FUNCTION_DECL; |
15dc331e | 2366 | |
fabdc32d | 2367 | if (is_attribute_p ("eightbit_data", attr) |
15dc331e JL |
2368 | && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))) |
2369 | { | |
2370 | if (DECL_INITIAL (decl) == NULL_TREE) | |
2371 | { | |
2372 | warning ("Only initialized variables can be placed into the 8-bit area."); | |
2373 | return 0; | |
2374 | } | |
887a8bd9 JL |
2375 | DECL_SECTION_NAME (decl) = build_string (7, ".eight"); |
2376 | return 1; | |
2377 | } | |
2378 | ||
2379 | if (is_attribute_p ("tiny_data", attr) | |
2380 | && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))) | |
2381 | { | |
2382 | if (DECL_INITIAL (decl) == NULL_TREE) | |
2383 | { | |
2384 | warning ("Only initialized variables can be placed into the 8-bit area."); | |
2385 | return 0; | |
2386 | } | |
2387 | DECL_SECTION_NAME (decl) = build_string (6, ".tiny"); | |
15dc331e JL |
2388 | return 1; |
2389 | } | |
2390 | ||
f5b65a56 JL |
2391 | return 0; |
2392 | } | |
2393 | ||
887a8bd9 JL |
2394 | extern struct obstack *saveable_obstack; |
2395 | ||
2396 | h8300_encode_label (decl) | |
2397 | tree decl; | |
2398 | { | |
2399 | char *str = XSTR (XEXP (DECL_RTL (decl), 0), 0); | |
2400 | int len = strlen (str); | |
2401 | char *newstr; | |
2402 | ||
2403 | newstr = obstack_alloc (saveable_obstack, len + 2); | |
2404 | ||
2405 | strcpy (newstr + 1, str); | |
2406 | *newstr = '*'; | |
2407 | XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr; | |
2408 | } | |
2409 | ||
bd93f126 JL |
2410 | char * |
2411 | output_simode_bld (bild, log2, operands) | |
2412 | int bild; | |
2413 | int log2; | |
2414 | rtx operands[]; | |
2415 | { | |
2416 | /* Clear the destination register. */ | |
2417 | if (TARGET_H8300H) | |
2418 | output_asm_insn ("sub.l\t%S0,%S0", operands); | |
2419 | else | |
2420 | output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands); | |
2421 | ||
2422 | /* Get the bit number we want to load. */ | |
2423 | if (log2) | |
2424 | operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2]))); | |
2425 | ||
2426 | /* Now output the bit load or bit inverse load, and store it in | |
2427 | the destination. */ | |
2428 | if (bild) | |
2429 | output_asm_insn ("bild\t%Z2,%Y1\n\tbst\t#0,%w0", operands); | |
2430 | else | |
2431 | output_asm_insn ("bld\t%Z2,%Y1\n\tbst\t#0,%w0", operands); | |
2432 | ||
2433 | /* All done. */ | |
2434 | return ""; | |
2435 | } | |
e6219736 JL |
2436 | |
2437 | /* Given INSN and it's current length LENGTH, return the adjustment | |
2438 | (in bytes) to correctly compute INSN's length. | |
2439 | ||
2440 | We use this to get the lengths of various memory references correct. */ | |
2441 | ||
2442 | h8300_adjust_insn_length (insn, length) | |
2443 | rtx insn; | |
2444 | int length; | |
2445 | { | |
2446 | rtx pat = PATTERN (insn); | |
2447 | ||
2448 | /* Adjust length for reg->mem and mem->reg copies. */ | |
2449 | if (GET_CODE (pat) == SET | |
2450 | && (GET_CODE (SET_SRC (pat)) == MEM | |
2451 | || GET_CODE (SET_DEST (pat)) == MEM)) | |
2452 | { | |
2453 | /* This insn might need a length adjustment. */ | |
2454 | rtx addr; | |
2455 | ||
2456 | if (GET_CODE (SET_SRC (pat)) == MEM) | |
2457 | addr = XEXP (SET_SRC (pat), 0); | |
2458 | else | |
2459 | addr = XEXP (SET_DEST (pat), 0); | |
2460 | ||
2461 | /* On the H8/300, only one adjustment is necessary; if the | |
2462 | address mode is register indirect, then this insn is two | |
2463 | bytes shorter than indicated in the machine description. */ | |
2464 | if (TARGET_H8300 && GET_CODE (addr) == REG) | |
2465 | return -2; | |
2466 | ||
2467 | /* On the H8/300H, register indirect is 6 bytes shorter than | |
2468 | indicated in the machine description. */ | |
2469 | if (TARGET_H8300H && GET_CODE (addr) == REG) | |
2470 | return -6; | |
2471 | ||
2472 | /* On the H8/300H, reg + d, for small displacements is 4 bytes | |
2473 | shorter than indicated in the machine description. */ | |
2474 | if (TARGET_H8300H | |
2475 | && GET_CODE (addr) == PLUS | |
2476 | && GET_CODE (XEXP (addr, 0)) == REG | |
2477 | && GET_CODE (XEXP (addr, 1)) == CONST_INT | |
2478 | && INTVAL (XEXP (addr, 1)) > -32768 | |
2479 | && INTVAL (XEXP (addr, 1)) < 32767) | |
2480 | return -4; | |
887a8bd9 JL |
2481 | |
2482 | /* On the H8/300H, abs:16 is two bytes shorter than the | |
2483 | more general abs:24. */ | |
2484 | if (TARGET_H8300H | |
2485 | && GET_CODE (addr) == SYMBOL_REF | |
2486 | && TINY_DATA_NAME_P (XSTR (addr, 0))) | |
2487 | return -2; | |
e6219736 JL |
2488 | } |
2489 | ||
2490 | /* Loading some constants needs adjustment. */ | |
2491 | if (GET_CODE (pat) == SET | |
2492 | && GET_CODE (SET_SRC (pat)) == CONST_INT | |
2493 | && GET_MODE (SET_DEST (pat)) == SImode | |
2494 | && INTVAL (SET_SRC (pat)) != 0) | |
2495 | { | |
2496 | if (TARGET_H8300 | |
2497 | && ((INTVAL (SET_SRC (pat)) & 0xffff) == 0 | |
2498 | || ((INTVAL (SET_SRC (pat)) >> 16) & 0xffff) == 0)) | |
2499 | return -2; | |
2500 | ||
2501 | if (TARGET_H8300H) | |
2502 | { | |
2503 | int val = INTVAL (SET_SRC (pat)); | |
2504 | ||
2505 | if (val == (val & 0xff) | |
2506 | || val == (val & 0xff00)) | |
2507 | return -6; | |
2508 | ||
2509 | if (val == -4 || val == -2 || val == -1) | |
2510 | return -6; | |
2511 | } | |
2512 | } | |
2513 | ||
dd4fd0a0 JL |
2514 | /* Shifts need various adjustments. */ |
2515 | if (GET_CODE (pat) == PARALLEL | |
2516 | && GET_CODE (XVECEXP (pat, 0, 0)) == SET | |
2517 | && (GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFTRT | |
2518 | || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == LSHIFTRT | |
2519 | || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFT)) | |
2520 | { | |
2521 | rtx src = SET_SRC (XVECEXP (pat, 0, 0)); | |
2522 | enum machine_mode mode = GET_MODE (src); | |
2523 | ||
2524 | if (GET_CODE (XEXP (src, 1)) != CONST_INT) | |
2525 | return 0; | |
2526 | ||
2527 | /* QImode shifts by small constants take one insn | |
2528 | per shift. So the adjustment is 20 (md length) - | |
2529 | # shifts * 2. */ | |
2530 | if (mode == QImode && INTVAL (XEXP (src, 1)) <= 4) | |
2531 | return -(20 - INTVAL (XEXP (src, 1)) * 2); | |
2532 | ||
2533 | /* Similarly for HImode and SImode shifts by | |
2534 | small constants on the H8/300H. */ | |
2535 | if (TARGET_H8300H | |
2536 | && (mode == HImode || mode == SImode) | |
2537 | && INTVAL (XEXP (src, 1)) <= 4) | |
2538 | return -(20 - INTVAL (XEXP (src, 1)) * 2); | |
2539 | ||
2540 | /* HImode shifts by small constants for the H8/300. */ | |
2541 | if (mode == HImode | |
2542 | && INTVAL (XEXP (src, 1)) <= 4) | |
2543 | return -(20 - (INTVAL (XEXP (src, 1)) | |
2544 | * (GET_CODE (src) == ASHIFT ? 2 : 4))); | |
2545 | ||
2546 | /* SImode shifts by small constants for the H8/300. */ | |
2547 | if (mode == SImode | |
2548 | && INTVAL (XEXP (src, 1)) <= 2) | |
2549 | return -(20 - (INTVAL (XEXP (src, 1)) | |
2550 | * (GET_CODE (src) == ASHIFT ? 6 : 8))); | |
2551 | ||
2552 | /* XXX ??? Could check for more shift/rotate cases here. */ | |
2553 | } | |
2554 | ||
e6219736 JL |
2555 | return 0; |
2556 | } |