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[Committed] Restore build on !TARGET_TRULY_NOOP_TRUNCATION targets
[thirdparty/gcc.git] / gcc / config / h8300 / h8300.c
CommitLineData
340f6494 1/* Subroutines for insn-output.c for Renesas H8/300.
99dee823 2 Copyright (C) 1992-2021 Free Software Foundation, Inc.
48837e29
DE		 3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
07aae5c2 5
8aa063fb 6This file is part of GCC.
07aae5c2 7
8aa063fb 8GCC is free software; you can redistribute it and/or modify
07aae5c2 9it under the terms of the GNU General Public License as published by
2f83c7d6 10the Free Software Foundation; either version 3, or (at your option)
07aae5c2
SC		 11any later version.
12
8aa063fb 13GCC is distributed in the hope that it will be useful,
07aae5c2
SC		 14but WITHOUT ANY WARRANTY; without even the implied warranty of
15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
2f83c7d6
NC		 19along with GCC; see the file COPYING3. If not see
20<http://www.gnu.org/licenses/>. */
07aae5c2 21
8fcc61f8
RS		 22#define IN_TARGET_CODE 1
23
07aae5c2 24#include "config.h"
c5c76735 25#include "system.h"
4977bab6 26#include "coretypes.h"
c7131fb2 27#include "backend.h"
e11c4407 28#include "target.h"
07aae5c2 29#include "rtl.h"
e11c4407 30#include "tree.h"
c7131fb2 31#include "df.h"
4d0cdd0c 32#include "memmodel.h"
e11c4407
AM		 33#include "tm_p.h"
34#include "stringpool.h"
314e6352 35#include "attribs.h"
e11c4407
AM		 36#include "optabs.h"
37#include "regs.h"
38#include "emit-rtl.h"
39#include "recog.h"
40#include "diagnostic-core.h"
40e23961 41#include "alias.h"
d8a2d370
DN		 42#include "stor-layout.h"
43#include "varasm.h"
44#include "calls.h"
07aae5c2 45#include "conditions.h"
07aae5c2
SC		 46#include "output.h"
47#include "insn-attr.h"
48#include "flags.h"
36566b39 49#include "explow.h"
36566b39 50#include "expr.h"
ceaaaeab 51#include "tm-constrs.h"
9b2b7279 52#include "builtins.h"
07aae5c2 53
994c5d85 54/* This file should be included last. */
d58627a0
RS		 55#include "target-def.h"
56
beed8fc0
AO		 57/* Classifies a h8300_src_operand or h8300_dst_operand.
58
59 H8OP_IMMEDIATE
60 A constant operand of some sort.
61
62 H8OP_REGISTER
63 An ordinary register.
64
65 H8OP_MEM_ABSOLUTE
66 A memory reference with a constant address.
67
68 H8OP_MEM_BASE
69 A memory reference with a register as its address.
70
71 H8OP_MEM_COMPLEX
72 Some other kind of memory reference. */
73enum h8300_operand_class
74{
75 H8OP_IMMEDIATE,
76 H8OP_REGISTER,
77 H8OP_MEM_ABSOLUTE,
78 H8OP_MEM_BASE,
79 H8OP_MEM_COMPLEX,
80 NUM_H8OPS
81};
82
beed8fc0
AO		 83/* For a general two-operand instruction, element [X][Y] gives
84 the length of the opcode fields when the first operand has class
85 (X + 1) and the second has class Y. */
86typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
87
07aae5c2 88/* Forward declarations. */
cb713a8d
KH		 89static const char *byte_reg (rtx, int);
90static int h8300_interrupt_function_p (tree);
3cfa3702 91static int h8300_saveall_function_p (tree);
cb713a8d
KH		 92static int h8300_monitor_function_p (tree);
93static int h8300_os_task_function_p (tree);
12bb62fb 94static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT);
e68d4dd1 95static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
cb713a8d 96static unsigned int compute_saved_regs (void);
cb713a8d
KH		 97static const char *cond_string (enum rtx_code);
98static unsigned int h8300_asm_insn_count (const char *);
cb713a8d
KH		 99static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
100static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
101static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
cc8ca59e 102static void h8300_print_operand_address (FILE *, machine_mode, rtx);
88cb339e
N		 103static void h8300_print_operand (FILE *, rtx, int);
104static bool h8300_print_operand_punct_valid_p (unsigned char code);
ef4bddc2 105static int h8300_register_move_cost (machine_mode, reg_class_t, reg_class_t);
cb713a8d
KH		 106static int h8300_and_costs (rtx);
107static int h8300_shift_costs (rtx);
ac447f25 108static void h8300_push_pop (int, int, bool, bool);
beed8fc0
AO		 109static int h8300_stack_offset_p (rtx, int);
110static int h8300_ldm_stm_regno (rtx, int, int, int);
beed8fc0
AO		 111static void h8300_reorg (void);
112static unsigned int h8300_constant_length (rtx);
113static unsigned int h8300_displacement_length (rtx, int);
114static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *);
115static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *);
116static unsigned int h8300_unary_length (rtx);
117static unsigned int h8300_short_immediate_length (rtx);
118static unsigned int h8300_bitfield_length (rtx, rtx);
e7041fcc 119static unsigned int h8300_binary_length (rtx_insn *, const h8300_length_table *);
beed8fc0
AO		 120static bool h8300_short_move_mem_p (rtx, enum rtx_code);
121static unsigned int h8300_move_length (rtx *, const h8300_length_table *);
2e762884 122static bool h8300_hard_regno_scratch_ok (unsigned int);
ef4bddc2 123static rtx h8300_get_index (rtx, machine_mode mode, int *);
f5b65a56 124
48837e29
DE		 125/* CPU_TYPE, says what cpu we're compiling for. */
126int cpu_type;
127
e392d367
KH		 128/* True if a #pragma interrupt has been seen for the current function. */
129static int pragma_interrupt;
07aae5c2
SC		 130
131/* True if a #pragma saveall has been seen for the current function. */
0869f126 132static int pragma_saveall;
07aae5c2 133
441d04c6 134static const char *const names_big[] =
f16897cb 135{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc" };
48837e29 136
441d04c6 137static const char *const names_extended[] =
f16897cb 138{ "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7", "cc" };
48837e29 139
441d04c6 140static const char *const names_upper_extended[] =
f16897cb 141{ "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7", "cc" };
48837e29
DE		 142
143/* Points to one of the above. */
144/* ??? The above could be put in an array indexed by CPU_TYPE. */
441d04c6 145const char * const *h8_reg_names;
48837e29
DE		 146
147/* Various operations needed by the following, indexed by CPU_TYPE. */
48837e29 148
441d04c6 149const char *h8_push_op, *h8_pop_op, *h8_mov_op;
dc66a1c4 150
beed8fc0
AO		 151/* Value of MOVE_RATIO. */
152int h8300_move_ratio;
672a6f42 153\f
c4dfc70c
DD		 154/* See below where shifts are handled for explanation of this enum. */
155
156enum shift_alg
157{
158 SHIFT_INLINE,
159 SHIFT_ROT_AND,
160 SHIFT_SPECIAL,
161 SHIFT_LOOP
162};
163
164/* Symbols of the various shifts which can be used as indices. */
165
166enum shift_type
167{
168 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
169};
170
171/* Macros to keep the shift algorithm tables small. */
172#define INL SHIFT_INLINE
173#define ROT SHIFT_ROT_AND
174#define LOP SHIFT_LOOP
175#define SPC SHIFT_SPECIAL
176
177/* The shift algorithms for each machine, mode, shift type, and shift
178 count are defined below. The three tables below correspond to
179 QImode, HImode, and SImode, respectively. Each table is organized
f411c849 180 by, in the order of indices, machine, shift type, and shift count. */
c4dfc70c 181
27c1afd5 182static enum shift_alg shift_alg_qi[2][3][8] = {
c4dfc70c
DD		 183 {
184 /* TARGET_H8300H */
185 /* 0 1 2 3 4 5 6 7 */
186 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
187 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
188 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
189 },
190 {
191 /* TARGET_H8300S */
192 /* 0 1 2 3 4 5 6 7 */
193 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
194 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
195 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
196 }
197};
198
27c1afd5 199static enum shift_alg shift_alg_hi[2][3][16] = {
c4dfc70c
DD		 200 {
201 /* TARGET_H8300H */
202 /* 0 1 2 3 4 5 6 7 */
203 /* 8 9 10 11 12 13 14 15 */
204 { INL, INL, INL, INL, INL, INL, INL, SPC,
205 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
206 { INL, INL, INL, INL, INL, INL, INL, SPC,
207 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
208 { INL, INL, INL, INL, INL, INL, INL, SPC,
209 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
210 },
211 {
212 /* TARGET_H8300S */
213 /* 0 1 2 3 4 5 6 7 */
214 /* 8 9 10 11 12 13 14 15 */
215 { INL, INL, INL, INL, INL, INL, INL, INL,
5f80c627 216 SPC, SPC, SPC, SPC, ROT, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
c4dfc70c 217 { INL, INL, INL, INL, INL, INL, INL, INL,
5f80c627 218 SPC, SPC, SPC, SPC, ROT, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
c4dfc70c
DD		 219 { INL, INL, INL, INL, INL, INL, INL, INL,
220 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
221 }
222};
223
27c1afd5 224static enum shift_alg shift_alg_si[2][3][32] = {
c4dfc70c
DD		 225 {
226 /* TARGET_H8300H */
227 /* 0 1 2 3 4 5 6 7 */
228 /* 8 9 10 11 12 13 14 15 */
229 /* 16 17 18 19 20 21 22 23 */
230 /* 24 25 26 27 28 29 30 31 */
882f1d58 231 { INL, INL, INL, INL, INL, INL, INL, LOP,
c4dfc70c 232 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
882f1d58
JL		 233 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC,
234 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
235 { INL, INL, INL, INL, INL, INL, INL, LOP,
c4dfc70c 236 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
882f1d58
JL		 237 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC,
238 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
239 { INL, INL, INL, INL, INL, INL, INL, LOP,
5f80c627 240 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
882f1d58 241 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC,
5f80c627 242 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
c4dfc70c
DD		 243 },
244 {
245 /* TARGET_H8300S */
246 /* 0 1 2 3 4 5 6 7 */
247 /* 8 9 10 11 12 13 14 15 */
248 /* 16 17 18 19 20 21 22 23 */
249 /* 24 25 26 27 28 29 30 31 */
250 { INL, INL, INL, INL, INL, INL, INL, INL,
75a71765
JL		 251 INL, INL, INL, INL, INL, INL, INL, SPC,
252 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC,
253 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
c4dfc70c 254 { INL, INL, INL, INL, INL, INL, INL, INL,
75a71765
JL		 255 INL, INL, INL, INL, INL, INL, INL, SPC,
256 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC,
257 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
c4dfc70c 258 { INL, INL, INL, INL, INL, INL, INL, INL,
5f80c627 259 INL, INL, INL, INL, INL, INL, INL, SPC,
75a71765
JL		 260 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC,
261 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
c4dfc70c
DD		 262 }
263};
264
265#undef INL
266#undef ROT
267#undef LOP
268#undef SPC
269
270enum h8_cpu
271{
c4dfc70c
DD		 272 H8_300H,
273 H8_S
274};
275
48837e29
DE		 276/* Initialize various cpu specific globals at start up. */
277
c5387660
JM		 278static void
279h8300_option_override (void)
48837e29 280{
cbf1b2da
KH		 281 static const char *const h8_push_ops[2] = { "push" , "push.l" };
282 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
283 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
284
27c1afd5
JL		 285 /* For this we treat the H8/300H and H8S the same. */
286 cpu_type = (int) CPU_H8300H;
287 h8_reg_names = names_extended;
48837e29
DE		 288 h8_push_op = h8_push_ops[cpu_type];
289 h8_pop_op = h8_pop_ops[cpu_type];
290 h8_mov_op = h8_mov_ops[cpu_type];
17f0f8fa 291
27c1afd5
JL		 292 /* If we're compiling for the H8/S, then turn off H8/300H. */
293 if (TARGET_H8300S)
294 target_flags &= ~MASK_H8300H;
295
17f0f8fa 296 if (!TARGET_H8300S && TARGET_MAC)
400500c4 297 {
a3f9f006 298 error ("%<-ms2600%> is used without %<-ms%>");
5463c726 299 target_flags |= MASK_H8300S_1;
400500c4 300 }
920e86b8 301
f4ea8112
SKS		 302 if (! TARGET_H8300S && TARGET_EXR)
303 {
a3f9f006 304 error ("%<-mexr%> is used without %<-ms%>");
f4ea8112
SKS		 305 target_flags |= MASK_H8300S_1;
306 }
307
f4ea8112
SKS		 308 if ((!TARGET_H8300S && TARGET_EXR) && (!TARGET_H8300SX && TARGET_EXR))
309 {
a3f9f006 310 error ("%<-mexr%> is used without %<-ms%> or %<-msx%>");
f4ea8112
SKS		 311 target_flags |= MASK_H8300S_1;
312 }
313
314 if ((!TARGET_H8300S && TARGET_NEXR) && (!TARGET_H8300SX && TARGET_NEXR))
315 {
dfa075d0
JL		 316 warning (OPT_mno_exr, "%<-mno-exr%> is valid only with %<-ms%> or "
317 "%<-msx%> - option ignored");
f4ea8112
SKS		 318 }
319
2f6bd6eb
YS		 320#ifdef H8300_LINUX
321 if ((TARGET_NORMAL_MODE))
322 {
a3f9f006 323 error ("%<-mn%> is not supported for linux targets");
2f6bd6eb
YS		 324 target_flags ^= MASK_NORMAL_MODE;
325 }
326#endif
327
8bd06267 328 /* Some of the shifts are optimized for speed by default.
c4dfc70c 329 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
8bd06267 330 If optimizing for size, change shift_alg for those shift to
c4dfc70c 331 SHIFT_LOOP. */
b6894857 332 if (optimize_size)
c4dfc70c 333 {
b6894857
KH		 334 /* H8/300H */
335 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
336 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
c4dfc70c 337
b6894857
KH		 338 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
339 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
c4dfc70c 340
b6894857
KH		 341 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
342 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
343 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
344 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
c4dfc70c 345
882f1d58
JL		 346 shift_alg_si[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
347 shift_alg_si[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
348 shift_alg_si[H8_300H][SHIFT_ASHIFT][20] = SHIFT_LOOP;
349 shift_alg_si[H8_300H][SHIFT_ASHIFT][21] = SHIFT_LOOP;
350 shift_alg_si[H8_300H][SHIFT_ASHIFT][22] = SHIFT_LOOP;
351 shift_alg_si[H8_300H][SHIFT_ASHIFT][23] = SHIFT_LOOP;
352 shift_alg_si[H8_300H][SHIFT_ASHIFT][25] = SHIFT_LOOP;
353 shift_alg_si[H8_300H][SHIFT_ASHIFT][26] = SHIFT_LOOP;
354 shift_alg_si[H8_300H][SHIFT_ASHIFT][27] = SHIFT_LOOP;
355
356 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
357 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
358 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][20] = SHIFT_LOOP;
359 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][21] = SHIFT_LOOP;
360 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][22] = SHIFT_LOOP;
361 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][23] = SHIFT_LOOP;
362 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][25] = SHIFT_LOOP;
363 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][26] = SHIFT_LOOP;
364 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][27] = SHIFT_LOOP;
365
366 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
367 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
368 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][20] = SHIFT_LOOP;
369 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][21] = SHIFT_LOOP;
370 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][22] = SHIFT_LOOP;
371 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][23] = SHIFT_LOOP;
372 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][25] = SHIFT_LOOP;
373 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][26] = SHIFT_LOOP;
374 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][27] = SHIFT_LOOP;
5f80c627
JL		 375 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][28] = SHIFT_LOOP;
376 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][29] = SHIFT_LOOP;
377 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][30] = SHIFT_LOOP;
882f1d58 378
c4dfc70c 379 /* H8S */
b6894857 380 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
75a71765
JL		 381
382 shift_alg_si[H8_S][SHIFT_ASHIFT][11] = SHIFT_LOOP;
383 shift_alg_si[H8_S][SHIFT_ASHIFT][12] = SHIFT_LOOP;
384 shift_alg_si[H8_S][SHIFT_ASHIFT][13] = SHIFT_LOOP;
385 shift_alg_si[H8_S][SHIFT_ASHIFT][14] = SHIFT_LOOP;
386 shift_alg_si[H8_S][SHIFT_ASHIFT][22] = SHIFT_LOOP;
387 shift_alg_si[H8_S][SHIFT_ASHIFT][23] = SHIFT_LOOP;
388 shift_alg_si[H8_S][SHIFT_ASHIFT][26] = SHIFT_LOOP;
389 shift_alg_si[H8_S][SHIFT_ASHIFT][27] = SHIFT_LOOP;
390
391 shift_alg_si[H8_S][SHIFT_LSHIFTRT][11] = SHIFT_LOOP;
392 shift_alg_si[H8_S][SHIFT_LSHIFTRT][12] = SHIFT_LOOP;
393 shift_alg_si[H8_S][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
394 shift_alg_si[H8_S][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
395 shift_alg_si[H8_S][SHIFT_LSHIFTRT][22] = SHIFT_LOOP;
396 shift_alg_si[H8_S][SHIFT_LSHIFTRT][23] = SHIFT_LOOP;
397 shift_alg_si[H8_S][SHIFT_LSHIFTRT][26] = SHIFT_LOOP;
398 shift_alg_si[H8_S][SHIFT_LSHIFTRT][27] = SHIFT_LOOP;
399
400 shift_alg_si[H8_S][SHIFT_ASHIFTRT][11] = SHIFT_LOOP;
401 shift_alg_si[H8_S][SHIFT_ASHIFTRT][12] = SHIFT_LOOP;
402 shift_alg_si[H8_S][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
403 shift_alg_si[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
404 shift_alg_si[H8_S][SHIFT_ASHIFTRT][22] = SHIFT_LOOP;
405 shift_alg_si[H8_S][SHIFT_ASHIFTRT][23] = SHIFT_LOOP;
406 shift_alg_si[H8_S][SHIFT_ASHIFTRT][26] = SHIFT_LOOP;
407 shift_alg_si[H8_S][SHIFT_ASHIFTRT][27] = SHIFT_LOOP;
408 shift_alg_si[H8_S][SHIFT_ASHIFTRT][28] = SHIFT_LOOP;
409 shift_alg_si[H8_S][SHIFT_ASHIFTRT][29] = SHIFT_LOOP;
410 shift_alg_si[H8_S][SHIFT_ASHIFTRT][30] = SHIFT_LOOP;
c4dfc70c 411 }
beed8fc0
AO		 412
413 /* Work out a value for MOVE_RATIO. */
414 if (!TARGET_H8300SX)
415 {
416 /* Memory-memory moves are quite expensive without the
417 h8sx instructions. */
418 h8300_move_ratio = 3;
419 }
420 else if (flag_omit_frame_pointer)
421 {
422 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
423 sometimes be as short as two individual memory-to-memory moves,
424 but since they use all the call-saved registers, it seems better
425 to allow up to three moves here. */
426 h8300_move_ratio = 4;
427 }
428 else if (optimize_size)
429 {
430 /* In this case we don't use movmd sequences since they tend
431 to be longer than calls to memcpy(). Memory-to-memory
432 moves are cheaper than for !TARGET_H8300SX, so it makes
433 sense to have a slightly higher threshold. */
434 h8300_move_ratio = 4;
435 }
436 else
437 {
438 /* We use movmd sequences for some moves since it can be quicker
439 than calling memcpy(). The sequences will need to save and
440 restore er6 though, so bump up the cost. */
441 h8300_move_ratio = 6;
442 }
0685e770
DD		 443
444 /* This target defaults to strict volatile bitfields. */
36acc1a2 445 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
0685e770 446 flag_strict_volatile_bitfields = 1;
beed8fc0
AO		 447}
448
e9eba255
KH		 449/* Return the byte register name for a register rtx X. B should be 0
450 if you want a lower byte register. B should be 1 if you want an
451 upper byte register. */
452
9c188705 453static const char *
cb713a8d 454byte_reg (rtx x, int b)
07aae5c2 455{
9cbcd983
KH		 456 static const char *const names_small[] = {
457 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
458 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
459 };
07aae5c2 460
8c440872 461 gcc_assert (REG_P (x));
500fc80f 462
07aae5c2
SC		 463 return names_small[REGNO (x) * 2 + b];
464}
465
466/* REGNO must be saved/restored across calls if this macro is true. */
48837e29 467
9cbcd983 468#define WORD_REG_USED(regno) \
d60004ee 469 (regno < SP_REG \
9cbcd983
KH		 470 /* No need to save registers if this function will not return. */ \
471 && ! TREE_THIS_VOLATILE (current_function_decl) \
3cfa3702 472 && (h8300_saveall_function_p (current_function_decl) \
9cbcd983 473 /* Save any call saved register that was used. */ \
a365fa06
RS		 474 || (df_regs_ever_live_p (regno) \
475 && !call_used_or_fixed_reg_p (regno)) \
9cbcd983 476 /* Save the frame pointer if it was used. */ \
6fb5fa3c 477 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
9cbcd983 478 /* Save any register used in an interrupt handler. */ \
e392d367 479 || (h8300_current_function_interrupt_function_p () \
6fb5fa3c 480 && df_regs_ever_live_p (regno)) \
9cbcd983
KH		 481 /* Save call clobbered registers in non-leaf interrupt \
482 handlers. */ \
e392d367 483 || (h8300_current_function_interrupt_function_p () \
a365fa06 484 && call_used_or_fixed_reg_p (regno) \
416ff32e 485 && !crtl->is_leaf)))
07aae5c2 486
18674659 487/* We use this to wrap all emitted insns in the prologue. */
e7041fcc
DM		 488static rtx_insn *
489F (rtx_insn *x, bool set_it)
18674659 490{
c72ea086
DD		 491 if (set_it)
492 RTX_FRAME_RELATED_P (x) = 1;
18674659
DD		 493 return x;
494}
495
496/* Mark all the subexpressions of the PARALLEL rtx PAR as
497 frame-related. Return PAR.
498
499 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
500 PARALLEL rtx other than the first if they do not have the
501 FRAME_RELATED flag set on them. */
502static rtx
503Fpa (rtx par)
504{
505 int len = XVECLEN (par, 0);
506 int i;
507
508 for (i = 0; i < len; i++)
f698a4b1 509 RTX_FRAME_RELATED_P (XVECEXP (par, 0, i)) = 1;
18674659
DD		 510
511 return par;
512}
513
07aae5c2 514/* Output assembly language to FILE for the operation OP with operand size
48837e29 515 SIZE to adjust the stack pointer. */
48837e29 516
07aae5c2 517static void
12bb62fb 518h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size)
07aae5c2 519{
72b1de44
KH		 520 /* If the frame size is 0, we don't have anything to do. */
521 if (size == 0)
f8b58e56 522 return;
72b1de44 523
27c1afd5
JL		 524 /* The stack adjustment made here is further optimized by the
525 splitter. In case of H8/300, the splitter always splits the
526 addition emitted here to make the adjustment interrupt-safe.
527 FIXME: We don't always tag those, because we don't know what
528 the splitter will do. */
529 if (Pmode == HImode)
f8f26adc 530 {
27c1afd5
JL		 531 rtx_insn *x = emit_insn (gen_addhi3 (stack_pointer_rtx,
532 stack_pointer_rtx,
533 GEN_INT (sign * size)));
534 if (size < 4)
f16897cb 535 F (x, 0);
7b3d4613
KH		 536 }
537 else
27c1afd5 538 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
f16897cb 539 stack_pointer_rtx, GEN_INT (sign * size))), 0);
07aae5c2
SC		 540}
541
8682223f
KH		 542/* Round up frame size SIZE. */
543
e68d4dd1
UB		 544static HOST_WIDE_INT
545round_frame_size (HOST_WIDE_INT size)
8682223f 546{
489eda65
KH		 547 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
548 & -STACK_BOUNDARY / BITS_PER_UNIT);
8682223f
KH		 549}
550
551/* Compute which registers to push/pop.
552 Return a bit vector of registers. */
553
554static unsigned int
cb713a8d 555compute_saved_regs (void)
8682223f
KH		 556{
557 unsigned int saved_regs = 0;
558 int regno;
559
560 /* Construct a bit vector of registers to be pushed/popped. */
1807b726 561 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
8682223f
KH		 562 {
563 if (WORD_REG_USED (regno))
564 saved_regs |= 1 << regno;
565 }
566
567 /* Don't push/pop the frame pointer as it is treated separately. */
568 if (frame_pointer_needed)
1807b726 569 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
8682223f
KH		 570
571 return saved_regs;
572}
573
68ee6df6 574/* Emit an insn to push register RN. */
8682223f 575
8f1594b2 576static rtx
12bb62fb 577push (int rn)
8682223f 578{
68ee6df6
KH		 579 rtx reg = gen_rtx_REG (word_mode, rn);
580 rtx x;
581
27c1afd5 582 if (!TARGET_NORMAL_MODE)
32da7865 583 x = gen_push_h8300hs_advanced (reg);
f24f0897
KH		 584 else
585 x = gen_push_h8300hs_normal (reg);
f16897cb 586 x = F (emit_insn (x), 0);
9690aa8e 587 add_reg_note (x, REG_INC, stack_pointer_rtx);
8f1594b2 588 return x;
8682223f
KH		 589}
590
68ee6df6 591/* Emit an insn to pop register RN. */
8682223f 592
8f1594b2 593static rtx
cb713a8d 594pop (int rn)
8682223f 595{
68ee6df6
KH		 596 rtx reg = gen_rtx_REG (word_mode, rn);
597 rtx x;
598
27c1afd5 599 if (!TARGET_NORMAL_MODE)
32da7865 600 x = gen_pop_h8300hs_advanced (reg);
f24f0897
KH		 601 else
602 x = gen_pop_h8300hs_normal (reg);
68ee6df6 603 x = emit_insn (x);
9690aa8e 604 add_reg_note (x, REG_INC, stack_pointer_rtx);
8f1594b2 605 return x;
8682223f 606}
07aae5c2 607
beed8fc0
AO		 608/* Emit an instruction to push or pop NREGS consecutive registers
609 starting at register REGNO. POP_P selects a pop rather than a
610 push and RETURN_P is true if the instruction should return.
611
612 It must be possible to do the requested operation in a single
613 instruction. If NREGS == 1 && !RETURN_P, use a normal push
614 or pop insn. Otherwise emit a parallel of the form:
615
616 (parallel
617 [(return) ;; if RETURN_P
618 (save or restore REGNO)
619 (save or restore REGNO + 1)
620 ...
621 (save or restore REGNO + NREGS - 1)
622 (set sp (plus sp (const_int adjust)))] */
623
624static void
ac447f25 625h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p)
beed8fc0
AO		 626{
627 int i, j;
628 rtvec vec;
18674659 629 rtx sp, offset, x;
beed8fc0
AO		 630
631 /* See whether we can use a simple push or pop. */
632 if (!return_p && nregs == 1)
633 {
634 if (pop_p)
635 pop (regno);
636 else
12bb62fb 637 push (regno);
beed8fc0
AO		 638 return;
639 }
640
641 /* We need one element for the return insn, if present, one for each
642 register, and one for stack adjustment. */
ac447f25 643 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1);
beed8fc0
AO		 644 sp = stack_pointer_rtx;
645 i = 0;
646
647 /* Add the return instruction. */
648 if (return_p)
649 {
3810076b 650 RTVEC_ELT (vec, i) = ret_rtx;
beed8fc0
AO		 651 i++;
652 }
653
654 /* Add the register moves. */
655 for (j = 0; j < nregs; j++)
656 {
657 rtx lhs, rhs;
658
659 if (pop_p)
660 {
661 /* Register REGNO + NREGS - 1 is popped first. Before the
662 stack adjustment, its slot is at address @sp. */
663 lhs = gen_rtx_REG (SImode, regno + j);
0a81f074
RS		 664 rhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp,
665 (nregs - j - 1) * 4));
beed8fc0
AO		 666 }
667 else
668 {
669 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
0a81f074 670 lhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, (j + 1) * -4));
beed8fc0
AO		 671 rhs = gen_rtx_REG (SImode, regno + j);
672 }
f7df4a84 673 RTVEC_ELT (vec, i + j) = gen_rtx_SET (lhs, rhs);
beed8fc0
AO		 674 }
675
676 /* Add the stack adjustment. */
677 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
f7df4a84 678 RTVEC_ELT (vec, i + j) = gen_rtx_SET (sp, gen_rtx_PLUS (Pmode, sp, offset));
beed8fc0 679
18674659
DD		 680 x = gen_rtx_PARALLEL (VOIDmode, vec);
681 if (!pop_p)
682 x = Fpa (x);
ac447f25
NC		 683
684 if (return_p)
685 emit_jump_insn (x);
686 else
687 emit_insn (x);
beed8fc0
AO		 688}
689
690/* Return true if X has the value sp + OFFSET. */
691
692static int
693h8300_stack_offset_p (rtx x, int offset)
694{
695 if (offset == 0)
696 return x == stack_pointer_rtx;
697
698 return (GET_CODE (x) == PLUS
699 && XEXP (x, 0) == stack_pointer_rtx
700 && GET_CODE (XEXP (x, 1)) == CONST_INT
701 && INTVAL (XEXP (x, 1)) == offset);
702}
703
704/* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
705 something that may be an ldm or stm instruction. If it fits
706 the required template, return the register it loads or stores,
707 otherwise return -1.
708
709 LOAD_P is true if X should be a load, false if it should be a store.
710 NREGS is the number of registers that the whole instruction is expected
711 to load or store. INDEX is the index of the register that X should
712 load or store, relative to the lowest-numbered register. */
713
714static int
715h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
716{
717 int regindex, memindex, offset;
718
719 if (load_p)
720 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
721 else
722 memindex = 0, regindex = 1, offset = (index + 1) * -4;
723
724 if (GET_CODE (x) == SET
725 && GET_CODE (XEXP (x, regindex)) == REG
726 && GET_CODE (XEXP (x, memindex)) == MEM
727 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
728 return REGNO (XEXP (x, regindex));
729
730 return -1;
731}
732
733/* Return true if the elements of VEC starting at FIRST describe an
734 ldm or stm instruction (LOAD_P says which). */
735
981c7dce 736int
beed8fc0
AO		 737h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
738{
739 rtx last;
740 int nregs, i, regno, adjust;
741
742 /* There must be a stack adjustment, a register move, and at least one
743 other operation (a return or another register move). */
744 if (GET_NUM_ELEM (vec) < 3)
745 return false;
746
747 /* Get the range of registers to be pushed or popped. */
748 nregs = GET_NUM_ELEM (vec) - first - 1;
749 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
750
751 /* Check that the call to h8300_ldm_stm_regno succeeded and
752 that we're only dealing with GPRs. */
753 if (regno < 0 || regno + nregs > 8)
754 return false;
755
756 /* 2-register h8s instructions must start with an even-numbered register.
757 3- and 4-register instructions must start with er0 or er4. */
758 if (!TARGET_H8300SX)
759 {
760 if ((regno & 1) != 0)
761 return false;
762 if (nregs > 2 && (regno & 3) != 0)
763 return false;
764 }
765
766 /* Check the other loads or stores. */
767 for (i = 1; i < nregs; i++)
768 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
769 != regno + i)
770 return false;
771
772 /* Check the stack adjustment. */
773 last = RTVEC_ELT (vec, first + nregs);
774 adjust = (load_p ? nregs : -nregs) * 4;
775 return (GET_CODE (last) == SET
776 && SET_DEST (last) == stack_pointer_rtx
777 && h8300_stack_offset_p (SET_SRC (last), adjust));
778}
779
f0b6f9a6 780/* This is what the stack looks like after the prolog of
07aae5c2
SC		 781 a function with a frame has been set up:
782
48837e29
DE		 783 <args>
784 PC
785 FP <- fp
786 <locals>
8bd06267 787 <saved registers> <- sp
07aae5c2
SC		 788
789 This is what the stack looks like after the prolog of
790 a function which doesn't have a frame:
791
48837e29
DE		 792 <args>
793 PC
794 <locals>
8bd06267 795 <saved registers> <- sp
07aae5c2
SC		 796*/
797
68ee6df6 798/* Generate RTL code for the function prologue. */
8682223f 799
68ee6df6 800void
cb713a8d 801h8300_expand_prologue (void)
07aae5c2 802{
e651d484 803 int regno;
8682223f 804 int saved_regs;
cda4bd43 805 int n_regs;
07aae5c2 806
fabe72bb
JL		 807 /* If the current function has the OS_Task attribute set, then
808 we have a naked prologue. */
809 if (h8300_os_task_function_p (current_function_decl))
68ee6df6 810 return;
fabe72bb
JL		 811
812 if (h8300_monitor_function_p (current_function_decl))
f4ea8112
SKS		 813 /* The monitor function act as normal functions, which means it
814 can accept parameters and return values. In addition to this,
815 interrupts are masked in prologue and return with "rte" in epilogue. */
68ee6df6 816 emit_insn (gen_monitor_prologue ());
fabe72bb 817
48837e29
DE		 818 if (frame_pointer_needed)
819 {
07e4d94e 820 /* Push fp. */
12bb62fb 821 push (HARD_FRAME_POINTER_REGNUM);
f16897cb 822 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), 0);
a1616dd9 823 }
48837e29 824
8682223f
KH		 825 /* Push the rest of the registers in ascending order. */
826 saved_regs = compute_saved_regs ();
e651d484 827 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
cda4bd43 828 {
cda4bd43 829 n_regs = 1;
8682223f 830 if (saved_regs & (1 << regno))
a1616dd9
JL		 831 {
832 if (TARGET_H8300S)
833 {
cda4bd43 834 /* See how many registers we can push at the same time. */
040e0e44 835 if ((TARGET_H8300SX || (regno & 3) == 0)
8682223f 836 && ((saved_regs >> regno) & 0x0f) == 0x0f)
cda4bd43
KH		 837 n_regs = 4;
838
040e0e44 839 else if ((TARGET_H8300SX || (regno & 3) == 0)
8682223f 840 && ((saved_regs >> regno) & 0x07) == 0x07)
cda4bd43
KH		 841 n_regs = 3;
842
040e0e44 843 else if ((TARGET_H8300SX || (regno & 1) == 0)
8682223f 844 && ((saved_regs >> regno) & 0x03) == 0x03)
cda4bd43 845 n_regs = 2;
a1616dd9 846 }
cda4bd43 847
ac447f25 848 h8300_push_pop (regno, n_regs, false, false);
07aae5c2
SC		 849 }
850 }
1807b726
KH		 851
852 /* Leave room for locals. */
12bb62fb 853 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()));
ed1332ee
NC		 854
855 if (flag_stack_usage_info)
856 current_function_static_stack_size
857 = round_frame_size (get_frame_size ())
858 + (__builtin_popcount (saved_regs) * UNITS_PER_WORD)
859 + (frame_pointer_needed ? UNITS_PER_WORD : 0);
07aae5c2
SC		 860}
861
e9eba255
KH		 862/* Return nonzero if we can use "rts" for the function currently being
863 compiled. */
864
68ee6df6 865int
cb713a8d 866h8300_can_use_return_insn_p (void)
68ee6df6
KH		 867{
868 return (reload_completed
869 && !frame_pointer_needed
870 && get_frame_size () == 0
871 && compute_saved_regs () == 0);
872}
07aae5c2 873
68ee6df6
KH		 874/* Generate RTL code for the function epilogue. */
875
876void
cb713a8d 877h8300_expand_epilogue (void)
07aae5c2 878{
e651d484 879 int regno;
8682223f 880 int saved_regs;
cda4bd43 881 int n_regs;
beed8fc0
AO		 882 HOST_WIDE_INT frame_size;
883 bool returned_p;
07aae5c2 884
e392d367 885 if (h8300_os_task_function_p (current_function_decl))
68ee6df6
KH		 886 /* OS_Task epilogues are nearly naked -- they just have an
887 rts instruction. */
888 return;
07aae5c2 889
beed8fc0
AO		 890 frame_size = round_frame_size (get_frame_size ());
891 returned_p = false;
892
1807b726 893 /* Deallocate locals. */
12bb62fb 894 h8300_emit_stack_adjustment (1, frame_size);
1807b726 895
8682223f
KH		 896 /* Pop the saved registers in descending order. */
897 saved_regs = compute_saved_regs ();
e651d484 898 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
cda4bd43 899 {
cda4bd43 900 n_regs = 1;
8682223f 901 if (saved_regs & (1 << regno))
07aae5c2 902 {
a1616dd9
JL		 903 if (TARGET_H8300S)
904 {
cda4bd43 905 /* See how many registers we can pop at the same time. */
beed8fc0
AO		 906 if ((TARGET_H8300SX || (regno & 3) == 3)
907 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
cda4bd43
KH		 908 n_regs = 4;
909
beed8fc0
AO		 910 else if ((TARGET_H8300SX || (regno & 3) == 2)
911 && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
cda4bd43
KH		 912 n_regs = 3;
913
beed8fc0
AO		 914 else if ((TARGET_H8300SX || (regno & 1) == 1)
915 && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
cda4bd43 916 n_regs = 2;
a1616dd9 917 }
cda4bd43 918
beed8fc0
AO		 919 /* See if this pop would be the last insn before the return.
920 If so, use rte/l or rts/l instead of pop or ldm.l. */
921 if (TARGET_H8300SX
922 && !frame_pointer_needed
923 && frame_size == 0
924 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
925 returned_p = true;
926
ac447f25 927 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p);
07aae5c2 928 }
07aae5c2 929 }
48837e29 930
07e4d94e 931 /* Pop frame pointer if we had one. */
a1616dd9 932 if (frame_pointer_needed)
beed8fc0
AO		 933 {
934 if (TARGET_H8300SX)
935 returned_p = true;
ac447f25 936 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p);
beed8fc0
AO		 937 }
938
939 if (!returned_p)
3810076b 940 emit_jump_insn (ret_rtx);
68ee6df6 941}
a1616dd9 942
e392d367
KH		 943/* Return nonzero if the current function is an interrupt
944 function. */
945
946int
cb713a8d 947h8300_current_function_interrupt_function_p (void)
e392d367 948{
f4ea8112
SKS		 949 return (h8300_interrupt_function_p (current_function_decl));
950}
951
952int
953h8300_current_function_monitor_function_p ()
954{
955 return (h8300_monitor_function_p (current_function_decl));
e392d367
KH		 956}
957
48837e29
DE		 958/* Output assembly code for the start of the file. */
959
1bc7c5b6
ZW		 960static void
961h8300_file_start (void)
48837e29 962{
1bc7c5b6 963 default_file_start ();
8bd06267 964
2f6bd6eb 965 if (TARGET_H8300SX)
beed8fc0 966 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
a1616dd9 967 else if (TARGET_H8300S)
1bc7c5b6 968 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
2f6bd6eb
YS		 969 else if (TARGET_H8300H)
970 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
48837e29
DE		 971}
972
973/* Output assembly language code for the end of file. */
974
a5fe455b 975static void
cb713a8d 976h8300_file_end (void)
48837e29 977{
a5fe455b 978 fputs ("\t.end\n", asm_out_file);
07aae5c2
SC		 979}
980\f
3cee1a78
KH		 981/* Split an add of a small constant into two adds/subs insns.
982
983 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
984 instead of adds/subs. */
009ac3d3
RH		 985
986void
ef4bddc2 987split_adds_subs (machine_mode mode, rtx *operands)
3b7d443c 988{
009ac3d3
RH		 989 HOST_WIDE_INT val = INTVAL (operands[1]);
990 rtx reg = operands[0];
9492393e
KH		 991 HOST_WIDE_INT sign = 1;
992 HOST_WIDE_INT amount;
590734b6 993 rtx (*gen_add) (rtx, rtx, rtx);
3b7d443c 994
9492393e
KH		 995 /* Force VAL to be positive so that we do not have to consider the
996 sign. */
997 if (val < 0)
3b7d443c 998 {
9492393e
KH		 999 val = -val;
1000 sign = -1;
1001 }
3b7d443c 1002
3cee1a78
KH		 1003 switch (mode)
1004 {
4e10a5a7 1005 case E_HImode:
590734b6 1006 gen_add = gen_addhi3;
3cee1a78
KH		 1007 break;
1008
4e10a5a7 1009 case E_SImode:
590734b6 1010 gen_add = gen_addsi3;
3cee1a78
KH		 1011 break;
1012
1013 default:
8c440872 1014 gcc_unreachable ();
3cee1a78
KH		 1015 }
1016
9492393e 1017 /* Try different amounts in descending order. */
27c1afd5 1018 for (amount = 4; amount > 0; amount /= 2)
9492393e 1019 {
1a63219b 1020 for (; val >= amount; val -= amount)
590734b6 1021 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
3b7d443c
JL		 1022 }
1023
9492393e 1024 return;
3b7d443c
JL		 1025}
1026
07aae5c2 1027/* Handle machine specific pragmas for compatibility with existing
48837e29 1028 compilers for the H8/300.
07aae5c2 1029
f411c849 1030 pragma saveall generates prologue/epilogue code which saves and
07aae5c2 1031 restores all the registers on function entry.
48837e29 1032
07aae5c2
SC		 1033 pragma interrupt saves and restores all registers, and exits with
1034 an rte instruction rather than an rts. A pointer to a function
1035 with this attribute may be safely used in an interrupt vector. */
48837e29 1036
8b97c5f8 1037void
cb713a8d 1038h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
07aae5c2 1039{
e392d367 1040 pragma_interrupt = 1;
8b97c5f8 1041}
05a81fe5 1042
8b97c5f8 1043void
cb713a8d 1044h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
8b97c5f8
ZW		 1045{
1046 pragma_saveall = 1;
07aae5c2 1047}
8b97c5f8 1048
6783fdb7
RS		 1049/* If the next function argument ARG is to be passed in a register, return
1050 a reg RTX for the hard register in which to pass the argument. CUM
1051 represents the state after the last argument. If the argument is to
1052 be pushed, NULL_RTX is returned.
48837e29 1053
56f9413b
NF		 1054 On the H8/300 all normal args are pushed, unless -mquickcall in which
1055 case the first 3 arguments are passed in registers. */
1056
1057static rtx
6783fdb7 1058h8300_function_arg (cumulative_args_t cum_v, const function_arg_info &arg)
07aae5c2 1059{
d5cc9181
JR		 1060 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1061
0ea6f6a0
KH		 1062 static const char *const hand_list[] = {
1063 "__main",
1064 "__cmpsi2",
1065 "__divhi3",
1066 "__modhi3",
1067 "__udivhi3",
1068 "__umodhi3",
1069 "__divsi3",
1070 "__modsi3",
1071 "__udivsi3",
1072 "__umodsi3",
1073 "__mulhi3",
1074 "__mulsi3",
1075 "__reg_memcpy",
1076 "__reg_memset",
1077 "__ucmpsi2",
1078 0,
1079 };
1080
7192cbf1 1081 rtx result = NULL_RTX;
441d04c6 1082 const char *fname;
48837e29
DE		 1083 int regpass = 0;
1084
dd07092e 1085 /* Never pass unnamed arguments in registers. */
6783fdb7 1086 if (!arg.named)
7192cbf1 1087 return NULL_RTX;
dd07092e 1088
48837e29
DE		 1089 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1090 if (TARGET_QUICKCALL)
1091 regpass = 3;
1092
1093 /* If calling hand written assembler, use 4 regs of args. */
48837e29
DE		 1094 if (cum->libcall)
1095 {
441d04c6 1096 const char * const *p;
48837e29
DE		 1097
1098 fname = XSTR (cum->libcall, 0);
1099
1100 /* See if this libcall is one of the hand coded ones. */
48837e29
DE		 1101 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1102 ;
07aae5c2 1103
48837e29
DE		 1104 if (*p)
1105 regpass = 4;
1106 }
1107
1108 if (regpass)
1109 {
6783fdb7 1110 int size = arg.promoted_size_in_bytes ();
15e0e275
KH		 1111 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1112 && cum->nbytes / UNITS_PER_WORD <= 3)
6783fdb7 1113 result = gen_rtx_REG (arg.mode, cum->nbytes / UNITS_PER_WORD);
48837e29 1114 }
07aae5c2 1115
48837e29
DE		 1116 return result;
1117}
56f9413b 1118
6930c98c 1119/* Update the data in CUM to advance over argument ARG. */
56f9413b
NF		 1120
1121static void
6930c98c
RS		 1122h8300_function_arg_advance (cumulative_args_t cum_v,
1123 const function_arg_info &arg)
56f9413b 1124{
d5cc9181
JR		 1125 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1126
6930c98c
RS		 1127 cum->nbytes += ((arg.promoted_size_in_bytes () + UNITS_PER_WORD - 1)
1128 & -UNITS_PER_WORD);
56f9413b
NF		 1129}
1130
48837e29 1131\f
88cb339e
N		 1132/* Implements TARGET_REGISTER_MOVE_COST.
1133
1134 Any SI register-to-register move may need to be reloaded,
1135 so inmplement h8300_register_move_cost to return > 2 so that reload never
1136 shortcuts. */
1137
1138static int
ef4bddc2 1139h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
88cb339e
N		 1140 reg_class_t from, reg_class_t to)
1141{
1142 if (from == MAC_REGS || to == MAC_REG)
1143 return 6;
1144 else
1145 return 3;
1146}
1147
e9eba255
KH		 1148/* Compute the cost of an and insn. */
1149
3c50106f 1150static int
cb713a8d 1151h8300_and_costs (rtx x)
73cc75e9
KH		 1152{
1153 rtx operands[4];
1154
1155 if (GET_MODE (x) == QImode)
1156 return 1;
1157
1158 if (GET_MODE (x) != HImode
1159 && GET_MODE (x) != SImode)
1160 return 100;
1161
1162 operands[0] = NULL;
beed8fc0 1163 operands[1] = XEXP (x, 0);
73cc75e9
KH		 1164 operands[2] = XEXP (x, 1);
1165 operands[3] = x;
402c818a 1166 return compute_logical_op_length (GET_MODE (x), AND, operands, NULL) / 2;
73cc75e9
KH		 1167}
1168
e9eba255
KH		 1169/* Compute the cost of a shift insn. */
1170
3c50106f 1171static int
cb713a8d 1172h8300_shift_costs (rtx x)
ae557002 1173{
b60761ba 1174 rtx operands[3];
ae557002
KH		 1175
1176 if (GET_MODE (x) != QImode
1177 && GET_MODE (x) != HImode
1178 && GET_MODE (x) != SImode)
1179 return 100;
1180
b60761ba 1181 operands[0] = gen_rtx_REG (GET_MODE (x), 0);
ae557002
KH		 1182 operands[1] = NULL;
1183 operands[2] = XEXP (x, 1);
b60761ba 1184 return compute_a_shift_length (operands, GET_CODE (x)) / 2;
ae557002 1185}
3c50106f 1186
e9eba255
KH		 1187/* Worker function for TARGET_RTX_COSTS. */
1188
3c50106f 1189static bool
e548c9df
AM		 1190h8300_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code,
1191 int opno ATTRIBUTE_UNUSED, int *total, bool speed)
3c50106f 1192{
e548c9df
AM		 1193 int code = GET_CODE (x);
1194
beed8fc0
AO		 1195 if (TARGET_H8300SX && outer_code == MEM)
1196 {
1197 /* Estimate the number of execution states needed to calculate
1198 the address. */
1199 if (register_operand (x, VOIDmode)
1200 || GET_CODE (x) == POST_INC
1201 || GET_CODE (x) == POST_DEC
1202 || CONSTANT_P (x))
1203 *total = 0;
1204 else
1205 *total = COSTS_N_INSNS (1);
1206 return true;
1207 }
1208
3c50106f
RH		 1209 switch (code)
1210 {
08dca707
KH		 1211 case CONST_INT:
1212 {
1213 HOST_WIDE_INT n = INTVAL (x);
1214
beed8fc0
AO		 1215 if (TARGET_H8300SX)
1216 {
1217 /* Constant operands need the same number of processor
1218 states as register operands. Although we could try to
f40751dd 1219 use a size-based cost for !speed, the lack of
beed8fc0
AO		 1220 of a mode makes the results very unpredictable. */
1221 *total = 0;
1222 return true;
1223 }
01512446 1224 if (n >= -4 && n <= 4)
08dca707
KH		 1225 {
1226 switch ((int) n)
1227 {
1228 case 0:
1229 *total = 0;
1230 return true;
1231 case 1:
1232 case 2:
1233 case -1:
1234 case -2:
1235 *total = 0 + (outer_code == SET);
1236 return true;
1237 case 4:
1238 case -4:
27c1afd5 1239 *total = 0 + (outer_code == SET);
08dca707
KH		 1240 return true;
1241 }
1242 }
1243 *total = 1;
1244 return true;
1245 }
1246
1247 case CONST:
1248 case LABEL_REF:
1249 case SYMBOL_REF:
beed8fc0
AO		 1250 if (TARGET_H8300SX)
1251 {
1252 /* See comment for CONST_INT. */
1253 *total = 0;
1254 return true;
1255 }
08dca707
KH		 1256 *total = 3;
1257 return true;
1258
1259 case CONST_DOUBLE:
1260 *total = 20;
1261 return true;
1262
f90b7a5a 1263 case COMPARE:
f80565da
JL		 1264 case NE:
1265 case EQ:
1266 case GE:
1267 case GT:
1268 case LE:
1269 case LT:
1270 case GEU:
1271 case GTU:
1272 case LEU:
1273 case LTU:
f90b7a5a
PB		 1274 if (XEXP (x, 1) == const0_rtx)
1275 *total = 0;
1276 return false;
1277
3c50106f 1278 case AND:
beed8fc0
AO		 1279 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
1280 || !h8300_src_operand (XEXP (x, 1), VOIDmode))
1281 return false;
3c50106f
RH		 1282 *total = COSTS_N_INSNS (h8300_and_costs (x));
1283 return true;
1284
1285 /* We say that MOD and DIV are so expensive because otherwise we'll
1286 generate some really horrible code for division of a power of two. */
1287 case MOD:
1288 case DIV:
beed8fc0
AO		 1289 case UMOD:
1290 case UDIV:
1291 if (TARGET_H8300SX)
1292 switch (GET_MODE (x))
1293 {
4e10a5a7
RS		 1294 case E_QImode:
1295 case E_HImode:
f40751dd 1296 *total = COSTS_N_INSNS (!speed ? 4 : 10);
beed8fc0
AO		 1297 return false;
1298
4e10a5a7 1299 case E_SImode:
f40751dd 1300 *total = COSTS_N_INSNS (!speed ? 4 : 18);
beed8fc0
AO		 1301 return false;
1302
1303 default:
1304 break;
1305 }
1306 *total = COSTS_N_INSNS (12);
3c50106f
RH		 1307 return true;
1308
1309 case MULT:
beed8fc0
AO		 1310 if (TARGET_H8300SX)
1311 switch (GET_MODE (x))
1312 {
4e10a5a7
RS		 1313 case E_QImode:
1314 case E_HImode:
beed8fc0
AO		 1315 *total = COSTS_N_INSNS (2);
1316 return false;
1317
4e10a5a7 1318 case E_SImode:
beed8fc0
AO		 1319 *total = COSTS_N_INSNS (5);
1320 return false;
1321
1322 default:
1323 break;
1324 }
1325 *total = COSTS_N_INSNS (4);
3c50106f
RH		 1326 return true;
1327
1328 case ASHIFT:
1329 case ASHIFTRT:
1330 case LSHIFTRT:
beed8fc0
AO		 1331 if (h8sx_binary_shift_operator (x, VOIDmode))
1332 {
1333 *total = COSTS_N_INSNS (2);
1334 return false;
1335 }
1336 else if (h8sx_unary_shift_operator (x, VOIDmode))
1337 {
1338 *total = COSTS_N_INSNS (1);
1339 return false;
1340 }
3c50106f
RH		 1341 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1342 return true;
1343
1344 case ROTATE:
1345 case ROTATERT:
1346 if (GET_MODE (x) == HImode)
1347 *total = 2;
1348 else
1349 *total = 8;
1350 return true;
1351
1352 default:
beed8fc0
AO		 1353 *total = COSTS_N_INSNS (1);
1354 return false;
3c50106f
RH		 1355 }
1356}
48837e29 1357\f
07aae5c2
SC		 1358/* Documentation for the machine specific operand escapes:
1359
48837e29
DE		 1360 'E' like s but negative.
1361 'F' like t but negative.
1362 'G' constant just the negative
15dc331e
JL		 1363 'R' print operand as a byte:8 address if appropriate, else fall back to
1364 'X' handling.
48837e29 1365 'S' print operand as a long word
07aae5c2 1366 'T' print operand as a word
48837e29
DE		 1367 'V' find the set bit, and print its number.
1368 'W' find the clear bit, and print its number.
1369 'X' print operand as a byte
07aae5c2 1370 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
15dc331e 1371 If this operand isn't a register, fall back to 'R' handling.
48837e29 1372 'Z' print int & 7.
b059c02a 1373 'c' print the opcode corresponding to rtl
da55315a 1374 'e' first word of 32-bit value - if reg, then least reg. if mem
48837e29 1375 then least. if const then most sig word
da55315a 1376 'f' second word of 32-bit value - if reg, then biggest reg. if mem
48837e29 1377 then +2. if const then least sig word
07aae5c2
SC		 1378 'j' print operand as condition code.
1379 'k' print operand as reverse condition code.
beed8fc0
AO		 1380 'm' convert an integer operand to a size suffix (.b, .w or .l)
1381 'o' print an integer without a leading '#'
da55315a
KH		 1382 's' print as low byte of 16-bit value
1383 't' print as high byte of 16-bit value
1384 'w' print as low byte of 32-bit value
1385 'x' print as 2nd byte of 32-bit value
1386 'y' print as 3rd byte of 32-bit value
1387 'z' print as msb of 32-bit value
48837e29 1388*/
07aae5c2
SC		 1389
1390/* Return assembly language string which identifies a comparison type. */
1391
441d04c6 1392static const char *
cb713a8d 1393cond_string (enum rtx_code code)
07aae5c2
SC		 1394{
1395 switch (code)
1396 {
1397 case NE:
1398 return "ne";
1399 case EQ:
1400 return "eq";
1401 case GE:
1402 return "ge";
1403 case GT:
1404 return "gt";
1405 case LE:
1406 return "le";
1407 case LT:
1408 return "lt";
1409 case GEU:
1410 return "hs";
1411 case GTU:
1412 return "hi";
1413 case LEU:
1414 return "ls";
1415 case LTU:
1416 return "lo";
1417 default:
8c440872 1418 gcc_unreachable ();
07aae5c2
SC		 1419 }
1420}
1421
1422/* Print operand X using operand code CODE to assembly language output file
1423 FILE. */
1424
88cb339e
N		 1425static void
1426h8300_print_operand (FILE *file, rtx x, int code)
07aae5c2 1427{
269c14e1 1428 /* This is used for communication between codes V,W,Z and Y. */
07aae5c2
SC		 1429 static int bitint;
1430
1431 switch (code)
1432 {
f46b8378
SKS		 1433 case 'C':
1434 if (h8300_constant_length (x) == 2)
1435 fprintf (file, ":16");
1436 else
1437 fprintf (file, ":32");
1438 return;
48837e29
DE		 1439 case 'E':
1440 switch (GET_CODE (x))
1441 {
1442 case REG:
1443 fprintf (file, "%sl", names_big[REGNO (x)]);
1444 break;
1445 case CONST_INT:
b47900aa 1446 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
48837e29
DE		 1447 break;
1448 default:
8c440872 1449 gcc_unreachable ();
48837e29
DE		 1450 }
1451 break;
1452 case 'F':
1453 switch (GET_CODE (x))
1454 {
1455 case REG:
1456 fprintf (file, "%sh", names_big[REGNO (x)]);
1457 break;
1458 case CONST_INT:
b47900aa 1459 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
48837e29
DE		 1460 break;
1461 default:
8c440872 1462 gcc_unreachable ();
48837e29
DE		 1463 }
1464 break;
07aae5c2 1465 case 'G':
8c440872 1466 gcc_assert (GET_CODE (x) == CONST_INT);
b47900aa 1467 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
07aae5c2 1468 break;
48837e29
DE		 1469 case 'S':
1470 if (GET_CODE (x) == REG)
1471 fprintf (file, "%s", names_extended[REGNO (x)]);
07aae5c2 1472 else
48837e29 1473 goto def;
07aae5c2 1474 break;
48837e29
DE		 1475 case 'T':
1476 if (GET_CODE (x) == REG)
1477 fprintf (file, "%s", names_big[REGNO (x)]);
07aae5c2 1478 else
48837e29 1479 goto def;
07aae5c2 1480 break;
48837e29 1481 case 'V':
0f6b820c
KP		 1482 bitint = (INTVAL (x) & 0xffff);
1483 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1)
1484 bitint = exact_log2 (bitint & 0xff);
1485 else
1486 bitint = exact_log2 ((bitint >> 8) & 0xff);
8c440872 1487 gcc_assert (bitint >= 0);
4d4d89e2 1488 fprintf (file, "#%d", bitint);
07aae5c2 1489 break;
48837e29 1490 case 'W':
0f6b820c
KP		 1491 bitint = ((~INTVAL (x)) & 0xffff);
1492 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 )
1493 bitint = exact_log2 (bitint & 0xff);
1494 else
1495 bitint = (exact_log2 ((bitint >> 8) & 0xff));
8c440872 1496 gcc_assert (bitint >= 0);
4d4d89e2 1497 fprintf (file, "#%d", bitint);
07aae5c2 1498 break;
15dc331e 1499 case 'R':
48837e29
DE		 1500 case 'X':
1501 if (GET_CODE (x) == REG)
1502 fprintf (file, "%s", byte_reg (x, 0));
1503 else
1504 goto def;
1505 break;
1506 case 'Y':
8c440872 1507 gcc_assert (bitint >= 0);
48837e29
DE		 1508 if (GET_CODE (x) == REG)
1509 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1510 else
88cb339e 1511 h8300_print_operand (file, x, 'R');
48837e29
DE		 1512 bitint = -1;
1513 break;
1514 case 'Z':
1515 bitint = INTVAL (x);
07aae5c2
SC		 1516 fprintf (file, "#%d", bitint & 7);
1517 break;
b059c02a
KH		 1518 case 'c':
1519 switch (GET_CODE (x))
1520 {
1521 case IOR:
1522 fprintf (file, "or");
1523 break;
1524 case XOR:
1525 fprintf (file, "xor");
1526 break;
5abfd1af
KH		 1527 case AND:
1528 fprintf (file, "and");
1529 break;
b059c02a
KH		 1530 default:
1531 break;
1532 }
1533 break;
07aae5c2
SC		 1534 case 'e':
1535 switch (GET_CODE (x))
1536 {
1537 case REG:
27c1afd5 1538 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
07aae5c2
SC		 1539 break;
1540 case MEM:
88cb339e 1541 h8300_print_operand (file, x, 0);
07aae5c2
SC		 1542 break;
1543 case CONST_INT:
b47900aa 1544 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
07aae5c2 1545 break;
808fbfac
JL		 1546 case CONST_DOUBLE:
1547 {
1548 long val;
34a72c33 1549 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val);
441d04c6 1550 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
808fbfac
JL		 1551 break;
1552 }
07aae5c2 1553 default:
8c440872 1554 gcc_unreachable ();
07aae5c2
SC		 1555 break;
1556 }
1557 break;
07aae5c2
SC		 1558 case 'f':
1559 switch (GET_CODE (x))
1560 {
1561 case REG:
27c1afd5 1562 fprintf (file, "%s", names_big[REGNO (x)]);
07aae5c2 1563 break;
07aae5c2 1564 case MEM:
b72f00af 1565 x = adjust_address (x, HImode, 2);
88cb339e 1566 h8300_print_operand (file, x, 0);
07aae5c2 1567 break;
07aae5c2 1568 case CONST_INT:
b47900aa 1569 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
07aae5c2 1570 break;
808fbfac
JL		 1571 case CONST_DOUBLE:
1572 {
1573 long val;
34a72c33 1574 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val);
441d04c6 1575 fprintf (file, "#%ld", (val & 0xffff));
808fbfac
JL		 1576 break;
1577 }
07aae5c2 1578 default:
8c440872 1579 gcc_unreachable ();
07aae5c2
SC		 1580 }
1581 break;
07aae5c2 1582 case 'j':
f16897cb
AL		 1583 if (GET_CODE (x) == LT && GET_MODE (XEXP (x, 0)) == E_CCZNmode)
1584 fputs ("mi", file);
1585 else if (GET_CODE (x) == GE && GET_MODE (XEXP (x, 0)) == E_CCZNmode)
1586 fputs ("pl", file);
1587 else
1588 fputs (cond_string (GET_CODE (x)), file);
07aae5c2 1589 break;
07aae5c2 1590 case 'k':
f16897cb
AL		 1591 if (GET_CODE (x) == LT && GET_MODE (XEXP (x, 0)) == E_CCZNmode)
1592 fputs ("pl", file);
1593 else if (GET_CODE (x) == GE && GET_MODE (XEXP (x, 0)) == E_CCZNmode)
1594 fputs ("mi", file);
1595 else
1596 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
07aae5c2 1597 break;
beed8fc0 1598 case 'm':
8c440872
NS		 1599 gcc_assert (GET_CODE (x) == CONST_INT);
1600 switch (INTVAL (x))
1601 {
1602 case 1:
1603 fputs (".b", file);
1604 break;
1605
1606 case 2:
1607 fputs (".w", file);
1608 break;
1609
1610 case 4:
1611 fputs (".l", file);
1612 break;
1613
1614 default:
1615 gcc_unreachable ();
1616 }
beed8fc0
AO		 1617 break;
1618 case 'o':
cc8ca59e 1619 h8300_print_operand_address (file, VOIDmode, x);
beed8fc0 1620 break;
48837e29
DE		 1621 case 's':
1622 if (GET_CODE (x) == CONST_INT)
b47900aa 1623 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
64c9f2d9 1624 else if (GET_CODE (x) == REG)
48837e29 1625 fprintf (file, "%s", byte_reg (x, 0));
64c9f2d9
JL		 1626 else
1627 output_operand_lossage ("Expected register or constant integer.");
48837e29
DE		 1628 break;
1629 case 't':
1630 if (GET_CODE (x) == CONST_INT)
b47900aa 1631 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
64c9f2d9 1632 else if (GET_CODE (x) == REG)
48837e29 1633 fprintf (file, "%s", byte_reg (x, 1));
64c9f2d9
JL		 1634 else
1635 output_operand_lossage ("Expected register or constant integer.");
48837e29 1636 break;
48837e29
DE		 1637 case 'w':
1638 if (GET_CODE (x) == CONST_INT)
b47900aa 1639 fprintf (file, "#%ld", INTVAL (x) & 0xff);
64c9f2d9 1640 else if (GET_CODE (x) == REG)
27c1afd5 1641 fprintf (file, "%s", byte_reg (x, 0));
64c9f2d9
JL		 1642 else
1643 output_operand_lossage ("Expected register or constant integer.");
48837e29
DE		 1644 break;
1645 case 'x':
1646 if (GET_CODE (x) == CONST_INT)
b47900aa 1647 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
64c9f2d9 1648 else if (GET_CODE (x) == REG)
27c1afd5 1649 fprintf (file, "%s", byte_reg (x, 1));
64c9f2d9
JL		 1650 else
1651 output_operand_lossage ("Expected register or constant integer.");
48837e29
DE		 1652 break;
1653 case 'y':
1654 if (GET_CODE (x) == CONST_INT)
b47900aa 1655 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
64c9f2d9 1656 else if (GET_CODE (x) == REG)
48837e29 1657 fprintf (file, "%s", byte_reg (x, 0));
64c9f2d9
JL		 1658 else
1659 output_operand_lossage ("Expected register or constant integer.");
48837e29
DE		 1660 break;
1661 case 'z':
1662 if (GET_CODE (x) == CONST_INT)
b47900aa 1663 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
64c9f2d9 1664 else if (GET_CODE (x) == REG)
48837e29 1665 fprintf (file, "%s", byte_reg (x, 1));
64c9f2d9
JL		 1666 else
1667 output_operand_lossage ("Expected register or constant integer.");
48837e29
DE		 1668 break;
1669
07aae5c2 1670 default:
48837e29 1671 def:
07aae5c2
SC		 1672 switch (GET_CODE (x))
1673 {
1674 case REG:
48837e29
DE		 1675 switch (GET_MODE (x))
1676 {
4e10a5a7 1677 case E_QImode:
269c14e1 1678#if 0 /* Is it asm ("mov.b %0,r2l", ...) */
48837e29
DE		 1679 fprintf (file, "%s", byte_reg (x, 0));
1680#else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1681 fprintf (file, "%s", names_big[REGNO (x)]);
1682#endif
1683 break;
4e10a5a7 1684 case E_HImode:
48837e29
DE		 1685 fprintf (file, "%s", names_big[REGNO (x)]);
1686 break;
4e10a5a7
RS		 1687 case E_SImode:
1688 case E_SFmode:
48837e29
DE		 1689 fprintf (file, "%s", names_extended[REGNO (x)]);
1690 break;
1691 default:
8c440872 1692 gcc_unreachable ();
48837e29 1693 }
07aae5c2
SC		 1694 break;
1695
1696 case MEM:
87e4ee91
KH		 1697 {
1698 rtx addr = XEXP (x, 0);
1699
1700 fprintf (file, "@");
cc8ca59e 1701 output_address (GET_MODE (x), addr);
87e4ee91 1702
beed8fc0
AO		 1703 /* Add a length suffix to constant addresses. Although this
1704 is often unnecessary, it helps to avoid ambiguity in the
1705 syntax of mova. If we wrote an insn like:
1706
1707 mova/w.l @(1,@foo.b),er0
1708
1709 then .b would be considered part of the symbol name.
1710 Adding a length after foo will avoid this. */
1711 if (CONSTANT_P (addr))
1712 switch (code)
1713 {
1714 case 'R':
1715 /* Used for mov.b and bit operations. */
1716 if (h8300_eightbit_constant_address_p (addr))
1717 {
1718 fprintf (file, ":8");
1719 break;
1720 }
1721
451c15c2
JL		 1722 /* FALLTHRU */
1723
1724 /* We should not get here if we are processing bit
1725 operations on H8/300 or H8/300H because 'U'
1726 constraint does not allow bit operations on the
1727 tiny area on these machines. */
beed8fc0
AO		 1728
1729 case 'X':
1730 case 'T':
1731 case 'S':
1732 if (h8300_constant_length (addr) == 2)
1733 fprintf (file, ":16");
1734 else
1735 fprintf (file, ":32");
1736 break;
1737 default:
1738 break;
1739 }
87e4ee91 1740 }
07aae5c2
SC		 1741 break;
1742
1743 case CONST_INT:
1744 case SYMBOL_REF:
1745 case CONST:
1746 case LABEL_REF:
1747 fprintf (file, "#");
cc8ca59e 1748 h8300_print_operand_address (file, VOIDmode, x);
07aae5c2 1749 break;
808fbfac
JL		 1750 case CONST_DOUBLE:
1751 {
1752 long val;
34a72c33 1753 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val);
441d04c6 1754 fprintf (file, "#%ld", val);
808fbfac
JL		 1755 break;
1756 }
441d04c6
KG		 1757 default:
1758 break;
07aae5c2
SC		 1759 }
1760 }
1761}
1762
88cb339e
N		 1763/* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1764
1765static bool
1766h8300_print_operand_punct_valid_p (unsigned char code)
1767{
1768 return (code == '#');
1769}
1770
07aae5c2
SC		 1771/* Output assembly language output for the address ADDR to FILE. */
1772
88cb339e 1773static void
cc8ca59e 1774h8300_print_operand_address (FILE *file, machine_mode mode, rtx addr)
07aae5c2 1775{
beed8fc0
AO		 1776 rtx index;
1777 int size;
1778
07aae5c2
SC		 1779 switch (GET_CODE (addr))
1780 {
1781 case REG:
48837e29 1782 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
07aae5c2
SC		 1783 break;
1784
1785 case PRE_DEC:
48837e29 1786 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
07aae5c2
SC		 1787 break;
1788
1789 case POST_INC:
48837e29 1790 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
07aae5c2
SC		 1791 break;
1792
beed8fc0
AO		 1793 case PRE_INC:
1794 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1795 break;
1796
1797 case POST_DEC:
1798 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
1799 break;
1800
07aae5c2
SC		 1801 case PLUS:
1802 fprintf (file, "(");
beed8fc0
AO		 1803
1804 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
1805 if (GET_CODE (index) == REG)
07aae5c2
SC		 1806 {
1807 /* reg,foo */
cc8ca59e 1808 h8300_print_operand_address (file, mode, XEXP (addr, 1));
07aae5c2 1809 fprintf (file, ",");
beed8fc0
AO		 1810 switch (size)
1811 {
1812 case 0:
cc8ca59e 1813 h8300_print_operand_address (file, mode, index);
beed8fc0
AO		 1814 break;
1815
1816 case 1:
88cb339e 1817 h8300_print_operand (file, index, 'X');
beed8fc0
AO		 1818 fputs (".b", file);
1819 break;
1820
1821 case 2:
88cb339e 1822 h8300_print_operand (file, index, 'T');
beed8fc0
AO		 1823 fputs (".w", file);
1824 break;
1825
1826 case 4:
88cb339e 1827 h8300_print_operand (file, index, 'S');
beed8fc0
AO		 1828 fputs (".l", file);
1829 break;
1830 }
88cb339e 1831 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
07aae5c2
SC		 1832 }
1833 else
1834 {
1835 /* foo+k */
cc8ca59e 1836 h8300_print_operand_address (file, mode, XEXP (addr, 0));
07aae5c2 1837 fprintf (file, "+");
cc8ca59e 1838 h8300_print_operand_address (file, mode, XEXP (addr, 1));
07aae5c2
SC		 1839 }
1840 fprintf (file, ")");
1841 break;
1842
1843 case CONST_INT:
48837e29 1844 {
48837e29 1845 int n = INTVAL (addr);
7a770d8b 1846 fprintf (file, "%d", n);
48837e29
DE		 1847 break;
1848 }
07aae5c2
SC		 1849
1850 default:
1851 output_addr_const (file, addr);
1852 break;
1853 }
1854}
1855\f
07aae5c2
SC		 1856/* Output all insn addresses and their sizes into the assembly language
1857 output file. This is helpful for debugging whether the length attributes
1858 in the md file are correct. This is not meant to be a user selectable
1859 option. */
1860
1861void
e7041fcc 1862final_prescan_insn (rtx_insn *insn, rtx *operand ATTRIBUTE_UNUSED,
cb713a8d 1863 int num_operands ATTRIBUTE_UNUSED)
07aae5c2
SC		 1864{
1865 /* This holds the last insn address. */
1866 static int last_insn_address = 0;
1867
7798db98 1868 const int uid = INSN_UID (insn);
07aae5c2
SC		 1869
1870 if (TARGET_ADDRESSES)
1871 {
9d98a694
AO		 1872 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1873 INSN_ADDRESSES (uid) - last_insn_address);
1874 last_insn_address = INSN_ADDRESSES (uid);
07aae5c2
SC		 1875 }
1876}
1877
48837e29
DE		 1878/* Prepare for an SI sized move. */
1879
1880int
1a793acf 1881h8300_expand_movsi (rtx operands[])
07aae5c2 1882{
48837e29
DE		 1883 rtx src = operands[1];
1884 rtx dst = operands[0];
1885 if (!reload_in_progress && !reload_completed)
1886 {
1887 if (!register_operand (dst, GET_MODE (dst)))
1888 {
1889 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1890 emit_move_insn (tmp, src);
1891 operands[1] = tmp;
1892 }
1893 }
1894 return 0;
1895}
1896
7b5cbb57
AS		 1897/* Given FROM and TO register numbers, say whether this elimination is allowed.
1898 Frame pointer elimination is automatically handled.
1899
1900 For the h8300, if frame pointer elimination is being done, we would like to
1901 convert ap and rp into sp, not fp.
1902
1903 All other eliminations are valid. */
1904
1905static bool
1906h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
1907{
1908 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
1909}
1910
5efd84c5
NF		 1911/* Conditionally modify register usage based on target flags. */
1912
1913static void
1914h8300_conditional_register_usage (void)
1915{
1916 if (!TARGET_MAC)
1917 fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1;
1918}
1919
48837e29 1920/* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
07e4d94e
KH		 1921 Define the offset between two registers, one to be eliminated, and
1922 the other its replacement, at the start of a routine. */
07aae5c2 1923
48837e29 1924int
cb713a8d 1925h8300_initial_elimination_offset (int from, int to)
48837e29 1926{
d18ad191
KH		 1927 /* The number of bytes that the return address takes on the stack. */
1928 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
48837e29 1929
1807b726
KH		 1930 /* The number of bytes that the saved frame pointer takes on the stack. */
1931 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1932
1933 /* The number of bytes that the saved registers, excluding the frame
1934 pointer, take on the stack. */
1935 int saved_regs_size = 0;
48837e29 1936
1807b726
KH		 1937 /* The number of bytes that the locals takes on the stack. */
1938 int frame_size = round_frame_size (get_frame_size ());
48837e29 1939
1807b726 1940 int regno;
48837e29 1941
1807b726
KH		 1942 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1943 if (WORD_REG_USED (regno))
1944 saved_regs_size += UNITS_PER_WORD;
48837e29 1945
1807b726
KH		 1946 /* Adjust saved_regs_size because the above loop took the frame
1947 pointer int account. */
1948 saved_regs_size -= fp_size;
39ba95b5 1949
8c440872 1950 switch (to)
1807b726 1951 {
8c440872 1952 case HARD_FRAME_POINTER_REGNUM:
1807b726
KH		 1953 switch (from)
1954 {
1955 case ARG_POINTER_REGNUM:
1956 return pc_size + fp_size;
1957 case RETURN_ADDRESS_POINTER_REGNUM:
1958 return fp_size;
1959 case FRAME_POINTER_REGNUM:
1960 return -saved_regs_size;
1961 default:
8c440872 1962 gcc_unreachable ();
1807b726 1963 }
8c440872
NS		 1964 break;
1965 case STACK_POINTER_REGNUM:
1807b726
KH		 1966 switch (from)
1967 {
1968 case ARG_POINTER_REGNUM:
1969 return pc_size + saved_regs_size + frame_size;
1970 case RETURN_ADDRESS_POINTER_REGNUM:
1971 return saved_regs_size + frame_size;
1972 case FRAME_POINTER_REGNUM:
1973 return frame_size;
1974 default:
8c440872 1975 gcc_unreachable ();
1807b726 1976 }
8c440872
NS		 1977 break;
1978 default:
1979 gcc_unreachable ();
1807b726 1980 }
8c440872 1981 gcc_unreachable ();
48837e29
DE		 1982}
1983
e9eba255
KH		 1984/* Worker function for RETURN_ADDR_RTX. */
1985
1aae372e 1986rtx
cb713a8d 1987h8300_return_addr_rtx (int count, rtx frame)
1aae372e
JL		 1988{
1989 rtx ret;
1990
1991 if (count == 0)
1992 ret = gen_rtx_MEM (Pmode,
1993 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1994 else if (flag_omit_frame_pointer)
1995 return (rtx) 0;
1996 else
1997 ret = gen_rtx_MEM (Pmode,
1998 memory_address (Pmode,
0a81f074
RS		 1999 plus_constant (Pmode, frame,
2000 UNITS_PER_WORD)));
1aae372e
JL		 2001 set_mem_alias_set (ret, get_frame_alias_set ());
2002 return ret;
2003}
2004
f16897cb
AL		 2005
2006machine_mode
2007h8300_select_cc_mode (enum rtx_code cond, rtx op0, rtx op1)
2008{
2009 if (op1 == const0_rtx
2010 && (cond == EQ || cond == NE || cond == LT || cond == GE)
2011 && (GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
3a50aed0
JL		 2012 || GET_CODE (op0) == NEG || GET_CODE (op0) == AND
2013 || GET_CODE (op0) == IOR || GET_CODE (op0) == XOR
2014 || GET_CODE (op0) == NOT || GET_CODE (op0) == ASHIFT
2015 || GET_CODE (op0) == ASHIFTRT || GET_CODE (op0) == LSHIFTRT
629cbc68 2016 || GET_CODE (op0) == MULT || GET_CODE (op0) == SYMBOL_REF
6fcba9ef
JL		 2017 || GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND
2018 || REG_P (op0) || MEM_P (op0)))
f16897cb
AL		 2019 return CCZNmode;
2020
2021 return CCmode;
2022}
2023
beed8fc0
AO		 2024\f
2025/* Given that X occurs in an address of the form (plus X constant),
2026 return the part of X that is expected to be a register. There are
2027 four kinds of addressing mode to recognize:
2028
2029 @(dd,Rn)
2030 @(dd,RnL.b)
2031 @(dd,Rn.w)
2032 @(dd,ERn.l)
2033
2034 If SIZE is nonnull, and the address is one of the last three forms,
2035 set *SIZE to the index multiplication factor. Set it to 0 for
2036 plain @(dd,Rn) addresses.
2037
2038 MODE is the mode of the value being accessed. It can be VOIDmode
2039 if the address is known to be valid, but its mode is unknown. */
2040
f52d97da 2041static rtx
ef4bddc2 2042h8300_get_index (rtx x, machine_mode mode, int *size)
beed8fc0
AO		 2043{
2044 int dummy, factor;
2045
2046 if (size == 0)
2047 size = &dummy;
2048
2049 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
2050 if (TARGET_H8300SX
2051 && factor <= 4
2052 && (mode == VOIDmode
2053 || GET_MODE_CLASS (mode) == MODE_INT
2054 || GET_MODE_CLASS (mode) == MODE_FLOAT))
2055 {
2056 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
2057 {
2058 /* When accessing byte-sized values, the index can be
2059 a zero-extended QImode or HImode register. */
2060 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
2061 return XEXP (x, 0);
2062 }
2063 else
2064 {
2065 /* We're looking for addresses of the form:
2066
2067 (mult X I)
2068 or (mult (zero_extend X) I)
2069
2070 where I is the size of the operand being accessed.
2071 The canonical form of the second expression is:
2072
2073 (and (mult (subreg X) I) J)
2074
2075 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2076 rtx index;
2077
2078 if (GET_CODE (x) == AND
2079 && GET_CODE (XEXP (x, 1)) == CONST_INT
2080 && (factor == 0
2081 || INTVAL (XEXP (x, 1)) == 0xff * factor
2082 || INTVAL (XEXP (x, 1)) == 0xffff * factor))
2083 {
2084 index = XEXP (x, 0);
2085 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
2086 }
2087 else
2088 {
2089 index = x;
2090 *size = 4;
2091 }
2092
2093 if (GET_CODE (index) == MULT
2094 && GET_CODE (XEXP (index, 1)) == CONST_INT
2095 && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
2096 return XEXP (index, 0);
2097 }
2098 }
2099 *size = 0;
2100 return x;
2101}
2102\f
f52d97da
AS		 2103/* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2104
2105 On the H8/300, the predecrement and postincrement address depend thus
2106 (the amount of decrement or increment being the length of the operand). */
2107
2108static bool
5bfed9a9
GJL		 2109h8300_mode_dependent_address_p (const_rtx addr,
2110 addr_space_t as ATTRIBUTE_UNUSED)
f52d97da
AS		 2111{
2112 if (GET_CODE (addr) == PLUS
2113 && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0))
2114 return true;
2115
2116 return false;
2117}
2118\f
beed8fc0
AO		 2119static const h8300_length_table addb_length_table =
2120{
2121 /* #xx Rs @aa @Rs @xx */
2122 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2123 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2124 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2125 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2126};
2127
2128static const h8300_length_table addw_length_table =
2129{
2130 /* #xx Rs @aa @Rs @xx */
2131 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2132 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2133 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2134 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2135};
2136
2137static const h8300_length_table addl_length_table =
2138{
2139 /* #xx Rs @aa @Rs @xx */
2140 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2141 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2142 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2143 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2144};
2145
2146#define logicb_length_table addb_length_table
2147#define logicw_length_table addw_length_table
2148
2149static const h8300_length_table logicl_length_table =
2150{
2151 /* #xx Rs @aa @Rs @xx */
2152 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2153 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2154 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2155 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2156};
2157
2158static const h8300_length_table movb_length_table =
2159{
2160 /* #xx Rs @aa @Rs @xx */
2161 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2162 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2163 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2164 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2165};
2166
2167#define movw_length_table movb_length_table
2168
2169static const h8300_length_table movl_length_table =
2170{
2171 /* #xx Rs @aa @Rs @xx */
2172 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2173 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2174 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2175 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2176};
2177
2178/* Return the size of the given address or displacement constant. */
2179
2180static unsigned int
2181h8300_constant_length (rtx constant)
2182{
2183 /* Check for (@d:16,Reg). */
2184 if (GET_CODE (constant) == CONST_INT
2185 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
2186 return 2;
2187
2188 /* Check for (@d:16,Reg) in cases where the displacement is
2189 an absolute address. */
2190 if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
2191 return 2;
2192
2193 return 4;
2194}
2195
2196/* Return the size of a displacement field in address ADDR, which should
2197 have the form (plus X constant). SIZE is the number of bytes being
2198 accessed. */
2199
2200static unsigned int
2201h8300_displacement_length (rtx addr, int size)
2202{
2203 rtx offset;
2204
2205 offset = XEXP (addr, 1);
2206
2207 /* Check for @(d:2,Reg). */
2208 if (register_operand (XEXP (addr, 0), VOIDmode)
2209 && GET_CODE (offset) == CONST_INT
2210 && (INTVAL (offset) == size
2211 || INTVAL (offset) == size * 2
2212 || INTVAL (offset) == size * 3))
2213 return 0;
2214
2215 return h8300_constant_length (offset);
2216}
2217
0a2aaacc
KG		 2218/* Store the class of operand OP in *OPCLASS and return the length of any
2219 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
beed8fc0
AO		 2220 can be null if only the length is needed. */
2221
2222static unsigned int
0a2aaacc 2223h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
beed8fc0
AO		 2224{
2225 enum h8300_operand_class dummy;
2226
0a2aaacc
KG		 2227 if (opclass == 0)
2228 opclass = &dummy;
beed8fc0
AO		 2229
2230 if (CONSTANT_P (op))
2231 {
0a2aaacc 2232 *opclass = H8OP_IMMEDIATE;
beed8fc0
AO		 2233
2234 /* Byte-sized immediates are stored in the opcode fields. */
2235 if (size == 1)
2236 return 0;
2237
2238 /* If this is a 32-bit instruction, see whether the constant
2239 will fit into a 16-bit immediate field. */
2240 if (TARGET_H8300SX
2241 && size == 4
2242 && GET_CODE (op) == CONST_INT
2243 && IN_RANGE (INTVAL (op), 0, 0xffff))
2244 return 2;
2245
2246 return size;
2247 }
2248 else if (GET_CODE (op) == MEM)
2249 {
2250 op = XEXP (op, 0);
2251 if (CONSTANT_P (op))
2252 {
0a2aaacc 2253 *opclass = H8OP_MEM_ABSOLUTE;
beed8fc0
AO		 2254 return h8300_constant_length (op);
2255 }
2256 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
2257 {
0a2aaacc 2258 *opclass = H8OP_MEM_COMPLEX;
beed8fc0
AO		 2259 return h8300_displacement_length (op, size);
2260 }
2261 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
2262 {
0a2aaacc 2263 *opclass = H8OP_MEM_COMPLEX;
beed8fc0
AO		 2264 return 0;
2265 }
2266 else if (register_operand (op, VOIDmode))
2267 {
0a2aaacc 2268 *opclass = H8OP_MEM_BASE;
beed8fc0
AO		 2269 return 0;
2270 }
2271 }
8c440872 2272 gcc_assert (register_operand (op, VOIDmode));
0a2aaacc 2273 *opclass = H8OP_REGISTER;
8c440872 2274 return 0;
beed8fc0
AO		 2275}
2276
2277/* Return the length of the instruction described by TABLE given that
2278 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2279 and OP2 must be an h8300_src_operand. */
2280
2281static unsigned int
2282h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
2283{
2284 enum h8300_operand_class op1_class, op2_class;
2285 unsigned int size, immediate_length;
2286
2287 size = GET_MODE_SIZE (GET_MODE (op1));
2288 immediate_length = (h8300_classify_operand (op1, size, &op1_class)
2289 + h8300_classify_operand (op2, size, &op2_class));
2290 return immediate_length + (*table)[op1_class - 1][op2_class];
2291}
2292
2293/* Return the length of a unary instruction such as neg or not given that
2294 its operand is OP. */
2295
2296unsigned int
2297h8300_unary_length (rtx op)
2298{
0a2aaacc 2299 enum h8300_operand_class opclass;
beed8fc0
AO		 2300 unsigned int size, operand_length;
2301
2302 size = GET_MODE_SIZE (GET_MODE (op));
0a2aaacc
KG		 2303 operand_length = h8300_classify_operand (op, size, &opclass);
2304 switch (opclass)
beed8fc0
AO		 2305 {
2306 case H8OP_REGISTER:
2307 return 2;
2308
2309 case H8OP_MEM_BASE:
2310 return (size == 4 ? 6 : 4);
2311
2312 case H8OP_MEM_ABSOLUTE:
2313 return operand_length + (size == 4 ? 6 : 4);
2314
2315 case H8OP_MEM_COMPLEX:
2316 return operand_length + 6;
2317
2318 default:
8c440872 2319 gcc_unreachable ();
beed8fc0
AO		 2320 }
2321}
2322
2323/* Likewise short immediate instructions such as add.w #xx:3,OP. */
2324
2325static unsigned int
2326h8300_short_immediate_length (rtx op)
2327{
0a2aaacc 2328 enum h8300_operand_class opclass;
beed8fc0
AO		 2329 unsigned int size, operand_length;
2330
2331 size = GET_MODE_SIZE (GET_MODE (op));
0a2aaacc 2332 operand_length = h8300_classify_operand (op, size, &opclass);
beed8fc0 2333
0a2aaacc 2334 switch (opclass)
beed8fc0
AO		 2335 {
2336 case H8OP_REGISTER:
2337 return 2;
2338
2339 case H8OP_MEM_BASE:
2340 case H8OP_MEM_ABSOLUTE:
2341 case H8OP_MEM_COMPLEX:
2342 return 4 + operand_length;
2343
2344 default:
8c440872 2345 gcc_unreachable ();
beed8fc0
AO		 2346 }
2347}
2348
2349/* Likewise bitfield load and store instructions. */
48837e29 2350
beed8fc0
AO		 2351static unsigned int
2352h8300_bitfield_length (rtx op, rtx op2)
2353{
0a2aaacc 2354 enum h8300_operand_class opclass;
beed8fc0
AO		 2355 unsigned int size, operand_length;
2356
2357 if (GET_CODE (op) == REG)
2358 op = op2;
8c440872 2359 gcc_assert (GET_CODE (op) != REG);
beed8fc0
AO		 2360
2361 size = GET_MODE_SIZE (GET_MODE (op));
0a2aaacc 2362 operand_length = h8300_classify_operand (op, size, &opclass);
beed8fc0 2363
0a2aaacc 2364 switch (opclass)
beed8fc0
AO		 2365 {
2366 case H8OP_MEM_BASE:
2367 case H8OP_MEM_ABSOLUTE:
2368 case H8OP_MEM_COMPLEX:
2369 return 4 + operand_length;
2370
2371 default:
8c440872 2372 gcc_unreachable ();
07aae5c2 2373 }
48837e29
DE		 2374}
2375
beed8fc0 2376/* Calculate the length of general binary instruction INSN using TABLE. */
8ccf5d5f 2377
beed8fc0 2378static unsigned int
e7041fcc 2379h8300_binary_length (rtx_insn *insn, const h8300_length_table *table)
8ccf5d5f 2380{
beed8fc0 2381 rtx set;
f16897cb
AL		 2382 rtx pattern;
2383
2384 if (GET_CODE (insn) != INSN)
2385 gcc_unreachable ();
beed8fc0 2386
f16897cb
AL		 2387 pattern = PATTERN (insn);
2388 if (GET_CODE (pattern) == PARALLEL
2389 && GET_CODE (XVECEXP (pattern, 0, 0)) == SET
2390 && GET_CODE (SET_SRC (XVECEXP (pattern, 0, 0))) == COMPARE)
2391 set = XVECEXP (pattern, 0, 1);
2392 else
2393 set = single_set (insn);
8c440872 2394 gcc_assert (set);
beed8fc0
AO		 2395
2396 if (BINARY_P (SET_SRC (set)))
2397 return h8300_length_from_table (XEXP (SET_SRC (set), 0),
2398 XEXP (SET_SRC (set), 1), table);
beed8fc0 2399 else
8c440872
NS		 2400 {
2401 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
2402 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
2403 XEXP (XEXP (SET_SRC (set), 1), 1),
2404 table);
2405 }
8ccf5d5f
KH		 2406}
2407
beed8fc0
AO		 2408/* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2409 memory reference and either (1) it has the form @(d:16,Rn) or
2410 (2) its address has the code given by INC_CODE. */
8ccf5d5f 2411
beed8fc0
AO		 2412static bool
2413h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
8ccf5d5f 2414{
beed8fc0
AO		 2415 rtx addr;
2416 unsigned int size;
2417
2418 if (GET_CODE (op) != MEM)
2419 return false;
2420
2421 addr = XEXP (op, 0);
2422 size = GET_MODE_SIZE (GET_MODE (op));
2423 if (size != 1 && size != 2)
2424 return false;
2425
2426 return (GET_CODE (addr) == inc_code
2427 || (GET_CODE (addr) == PLUS
2428 && GET_CODE (XEXP (addr, 0)) == REG
2429 && h8300_displacement_length (addr, size) == 2));
8ccf5d5f
KH		 2430}
2431
beed8fc0
AO		 2432/* Calculate the length of move instruction INSN using the given length
2433 table. Although the tables are correct for most cases, there is some
2434 irregularity in the length of mov.b and mov.w. The following forms:
8ccf5d5f 2435
beed8fc0
AO		 2436 mov @ERs+, Rd
2437 mov @(d:16,ERs), Rd
2438 mov Rs, @-ERd
2439 mov Rs, @(d:16,ERd)
2440
2441 are two bytes shorter than most other "mov Rs, @complex" or
2442 "mov @complex,Rd" combinations. */
2443
2444static unsigned int
2445h8300_move_length (rtx *operands, const h8300_length_table *table)
8ccf5d5f 2446{
beed8fc0
AO		 2447 unsigned int size;
2448
2449 size = h8300_length_from_table (operands[0], operands[1], table);
2450 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
2451 size -= 2;
2452 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
2453 size -= 2;
2454 return size;
8ccf5d5f
KH		 2455}
2456
beed8fc0
AO		 2457/* Return the length of a mova instruction with the given operands.
2458 DEST is the register destination, SRC is the source address and
2459 OFFSET is the 16-bit or 32-bit displacement. */
2873836b 2460
beed8fc0
AO		 2461static unsigned int
2462h8300_mova_length (rtx dest, rtx src, rtx offset)
2873836b 2463{
beed8fc0
AO		 2464 unsigned int size;
2465
2466 size = (2
2467 + h8300_constant_length (offset)
2468 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
2469 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
2470 size += 2;
2471 return size;
2873836b
KH		 2472}
2473
beed8fc0
AO		 2474/* Compute the length of INSN based on its length_table attribute.
2475 OPERANDS is the array of its operands. */
2873836b 2476
beed8fc0 2477unsigned int
e7041fcc 2478h8300_insn_length_from_table (rtx_insn *insn, rtx * operands)
2873836b 2479{
beed8fc0
AO		 2480 switch (get_attr_length_table (insn))
2481 {
2482 case LENGTH_TABLE_NONE:
8c440872 2483 gcc_unreachable ();
beed8fc0 2484
c3c3ddbb
JL		 2485 case LENGTH_TABLE_ADD:
2486 if (GET_MODE (operands[0]) == QImode)
2487 return h8300_binary_length (insn, &addb_length_table);
2488 else if (GET_MODE (operands[0]) == HImode)
2489 return h8300_binary_length (insn, &addw_length_table);
2490 else if (GET_MODE (operands[0]) == SImode)
2491 return h8300_binary_length (insn, &addl_length_table);
2492 gcc_unreachable ();
beed8fc0
AO		 2493
2494 case LENGTH_TABLE_LOGICB:
2495 return h8300_binary_length (insn, &logicb_length_table);
2496
2497 case LENGTH_TABLE_MOVB:
2498 return h8300_move_length (operands, &movb_length_table);
2499
2500 case LENGTH_TABLE_MOVW:
2501 return h8300_move_length (operands, &movw_length_table);
2502
2503 case LENGTH_TABLE_MOVL:
2504 return h8300_move_length (operands, &movl_length_table);
2505
2506 case LENGTH_TABLE_MOVA:
2507 return h8300_mova_length (operands[0], operands[1], operands[2]);
2508
2509 case LENGTH_TABLE_MOVA_ZERO:
2510 return h8300_mova_length (operands[0], operands[1], const0_rtx);
2511
2512 case LENGTH_TABLE_UNARY:
2513 return h8300_unary_length (operands[0]);
2514
2515 case LENGTH_TABLE_MOV_IMM4:
2516 return 2 + h8300_classify_operand (operands[0], 0, 0);
2517
2518 case LENGTH_TABLE_SHORT_IMMEDIATE:
2519 return h8300_short_immediate_length (operands[0]);
2520
2521 case LENGTH_TABLE_BITFIELD:
2522 return h8300_bitfield_length (operands[0], operands[1]);
2523
2524 case LENGTH_TABLE_BITBRANCH:
2525 return h8300_bitfield_length (operands[1], operands[2]) - 2;
8c440872
NS		 2526
2527 default:
2528 gcc_unreachable ();
beed8fc0 2529 }
2873836b
KH		 2530}
2531
beed8fc0
AO		 2532/* Return true if LHS and RHS are memory references that can be mapped
2533 to the same h8sx assembly operand. LHS appears as the destination of
2534 an instruction and RHS appears as a source.
f9d2de4d 2535
beed8fc0
AO		 2536 Three cases are allowed:
2537
2538 - RHS is @+Rn or @-Rn, LHS is @Rn
2539 - RHS is @Rn, LHS is @Rn+ or @Rn-
2540 - RHS and LHS have the same address and neither has side effects. */
2541
2542bool
2543h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
f9d2de4d 2544{
beed8fc0
AO		 2545 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
2546 {
2547 rhs = XEXP (rhs, 0);
2548 lhs = XEXP (lhs, 0);
2549
2550 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
2551 return rtx_equal_p (XEXP (rhs, 0), lhs);
2552
2553 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
2554 return rtx_equal_p (rhs, XEXP (lhs, 0));
2555
2556 if (rtx_equal_p (rhs, lhs))
2557 return true;
2558 }
2559 return false;
f9d2de4d
KH		 2560}
2561
beed8fc0
AO		 2562/* Return true if OPERANDS[1] can be mapped to the same assembly
2563 operand as OPERANDS[0]. */
f9d2de4d 2564
beed8fc0
AO		 2565bool
2566h8300_operands_match_p (rtx *operands)
f9d2de4d 2567{
beed8fc0
AO		 2568 if (register_operand (operands[0], VOIDmode)
2569 && register_operand (operands[1], VOIDmode))
2570 return true;
f9d2de4d 2571
beed8fc0
AO		 2572 if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
2573 return true;
2574
2575 return false;
f9d2de4d 2576}
beed8fc0 2577\f
7948a9ea
KH		 2578/* Return the length of mov instruction. */
2579
2580unsigned int
2581compute_mov_length (rtx *operands)
2582{
2583 /* If the mov instruction involves a memory operand, we compute the
2584 length, assuming the largest addressing mode is used, and then
2585 adjust later in the function. Otherwise, we compute and return
2586 the exact length in one step. */
ef4bddc2 2587 machine_mode mode = GET_MODE (operands[0]);
7948a9ea
KH		 2588 rtx dest = operands[0];
2589 rtx src = operands[1];
2590 rtx addr;
2591
2592 if (GET_CODE (src) == MEM)
2593 addr = XEXP (src, 0);
2594 else if (GET_CODE (dest) == MEM)
2595 addr = XEXP (dest, 0);
2596 else
2597 addr = NULL_RTX;
2598
27c1afd5 2599 unsigned int base_length;
7948a9ea 2600
27c1afd5
JL		 2601 switch (mode)
2602 {
2603 case E_QImode:
2604 if (addr == NULL_RTX)
2605 return 2;
7948a9ea 2606
27c1afd5
JL		 2607 /* The eightbit addressing is available only in QImode, so
2608 go ahead and take care of it. */
2609 if (h8300_eightbit_constant_address_p (addr))
2610 return 2;
7948a9ea 2611
27c1afd5 2612 base_length = 8;
7948a9ea
KH		 2613 break;
2614
27c1afd5
JL		 2615 case E_HImode:
2616 if (addr == NULL_RTX)
2617 {
2618 if (REG_P (src))
2619 return 2;
7948a9ea 2620
27c1afd5
JL		 2621 if (src == const0_rtx)
2622 return 2;
7948a9ea 2623
27c1afd5
JL		 2624 return 4;
2625 }
7948a9ea 2626
27c1afd5
JL		 2627 base_length = 8;
2628 break;
7948a9ea 2629
27c1afd5
JL		 2630 case E_SImode:
2631 if (addr == NULL_RTX)
2632 {
2633 if (REG_P (src))
7948a9ea 2634 {
27c1afd5 2635 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
7948a9ea 2636 return 4;
27c1afd5
JL		 2637 else
2638 return 2;
7948a9ea
KH		 2639 }
2640
27c1afd5 2641 if (GET_CODE (src) == CONST_INT)
7948a9ea 2642 {
27c1afd5
JL		 2643 int val = INTVAL (src);
2644
2645 if (val == 0)
2646 return 2;
7948a9ea 2647
27c1afd5 2648 if (val == (val & 0x00ff) || val == (val & 0xff00))
2c4a71b3
KH		 2649 return 4;
2650
27c1afd5
JL		 2651 switch (val & 0xffffffff)
2652 {
2653 case 0xffffffff:
2654 case 0xfffffffe:
2655 case 0xfffffffc:
2656 case 0x0000ffff:
2657 case 0x0000fffe:
2658 case 0xffff0000:
2659 case 0xfffe0000:
2660 case 0x00010000:
2661 case 0x00020000:
2662 return 4;
2663 }
7948a9ea 2664 }
27c1afd5 2665 return 6;
7948a9ea
KH		 2666 }
2667
27c1afd5
JL		 2668 base_length = 10;
2669 break;
7948a9ea 2670
27c1afd5
JL		 2671 case E_SFmode:
2672 if (addr == NULL_RTX)
7948a9ea 2673 {
27c1afd5
JL		 2674 if (REG_P (src))
2675 return 2;
7948a9ea 2676
27c1afd5 2677 if (satisfies_constraint_G (src))
7948a9ea
KH		 2678 return 2;
2679
27c1afd5
JL		 2680 return 6;
2681 }
7948a9ea 2682
27c1afd5
JL		 2683 base_length = 10;
2684 break;
80e58519 2685
27c1afd5
JL		 2686 default:
2687 gcc_unreachable ();
2688 }
7948a9ea 2689
27c1afd5
JL		 2690 /* Adjust the length based on the addressing mode used.
2691 Specifically, we subtract the difference between the actual
2692 length and the longest one, which is @(d:24,ERs). */
7948a9ea 2693
27c1afd5
JL		 2694 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2695 if (GET_CODE (addr) == PRE_DEC
2696 || GET_CODE (addr) == POST_INC)
2697 return base_length - 6;
7948a9ea 2698
27c1afd5
JL		 2699 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2700 if (GET_CODE (addr) == REG)
2701 return base_length - 6;
2c4a71b3 2702
27c1afd5
JL		 2703 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2704 longest. */
2705 if (GET_CODE (addr) == PLUS
2706 && GET_CODE (XEXP (addr, 0)) == REG
2707 && GET_CODE (XEXP (addr, 1)) == CONST_INT
2708 && INTVAL (XEXP (addr, 1)) > -32768
2709 && INTVAL (XEXP (addr, 1)) < 32767)
2710 return base_length - 4;
7948a9ea 2711
27c1afd5
JL		 2712 /* @aa:16 is 4 bytes shorter than the longest. */
2713 if (h8300_tiny_constant_address_p (addr))
2714 return base_length - 4;
7948a9ea 2715
27c1afd5
JL		 2716 /* @aa:24 is 2 bytes shorter than the longest. */
2717 if (CONSTANT_P (addr))
2718 return base_length - 2;
7948a9ea 2719
27c1afd5 2720 return base_length;
7948a9ea
KH		 2721}
2722\f
e9eba255
KH		 2723/* Output an addition insn. */
2724
366a7b27 2725const char *
f16897cb 2726output_plussi (rtx *operands, bool need_flags)
7d6ac401 2727{
ef4bddc2 2728 machine_mode mode = GET_MODE (operands[0]);
7d6ac401 2729
8c440872 2730 gcc_assert (mode == SImode);
7d6ac401 2731
27c1afd5
JL		 2732 if (GET_CODE (operands[2]) == CONST_INT
2733 && register_operand (operands[1], VOIDmode))
7d6ac401 2734 {
27c1afd5 2735 HOST_WIDE_INT intval = INTVAL (operands[2]);
7d6ac401 2736
27c1afd5
JL		 2737 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
2738 return "add.l\t%S2,%S0";
2739 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
2740 return "sub.l\t%G2,%S0";
beed8fc0 2741
27c1afd5 2742 /* See if we can finish with 2 bytes. */
7d6ac401 2743
27c1afd5
JL		 2744 switch ((unsigned int) intval & 0xffffffff)
2745 {
f16897cb
AL		 2746 /* INC/DEC set the flags, but adds/subs do not. So if we
2747 need flags, use the former and not the latter. */
27c1afd5 2748 case 0x00000001:
f16897cb
AL		 2749 if (need_flags)
2750 return "inc.l\t#1,%S0";
2751 else
2752 return "adds\t%2,%S0";
27c1afd5 2753 case 0x00000002:
f16897cb
AL		 2754 if (need_flags)
2755 return "inc.l\t#2,%S0";
2756 else
2757 return "adds\t%2,%S0";
27c1afd5 2758 case 0xffffffff:
f16897cb
AL		 2759 if (need_flags)
2760 return "dec.l\t#1,%S0";
2761 else
2762 return "subs\t%G2,%S0";
27c1afd5 2763 case 0xfffffffe:
f16897cb
AL		 2764 if (need_flags)
2765 return "dec.l\t#2,%S0";
2766 else
2767 return "subs\t%G2,%S0";
2768
2769 /* These six cases have optimized paths when we do not
2770 need flags. Otherwise we let them fallthru. */
2771 case 0x00000004:
2772 if (!need_flags)
2773 return "adds\t%2,%S0";
2774
12bb62fb
JL		 2775 /* FALLTHRU */
2776
27c1afd5 2777 case 0xfffffffc:
f16897cb
AL		 2778 if (!need_flags)
2779 return "subs\t%G2,%S0";
27c1afd5 2780
12bb62fb
JL		 2781 /* FALLTHRU */
2782
27c1afd5
JL		 2783 case 0x00010000:
2784 case 0x00020000:
f16897cb
AL		 2785 if (!need_flags)
2786 {
2787 operands[2] = GEN_INT (intval >> 16);
2788 return "inc.w\t%2,%e0";
2789 }
27c1afd5 2790
12bb62fb
JL		 2791 /* FALLTHRU */
2792
27c1afd5
JL		 2793 case 0xffff0000:
2794 case 0xfffe0000:
f16897cb
AL		 2795 if (!need_flags)
2796 {
2797 operands[2] = GEN_INT (intval >> 16);
2798 return "dec.w\t%G2,%e0";
2799 }
12bb62fb
JL		 2800
2801 /* FALLTHRU */
2802
7d6ac401
KH		 2803 }
2804
27c1afd5
JL		 2805 /* See if we can finish with 4 bytes. */
2806 if ((intval & 0xffff) == 0)
beed8fc0 2807 {
27c1afd5
JL		 2808 operands[2] = GEN_INT (intval >> 16);
2809 return "add.w\t%2,%e0";
beed8fc0 2810 }
7d6ac401 2811 }
27c1afd5
JL		 2812
2813 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
2814 {
2815 operands[2] = GEN_INT (-INTVAL (operands[2]));
2816 return "sub.l\t%S2,%S0";
2817 }
2818 return "add.l\t%S2,%S0";
7d6ac401
KH		 2819}
2820
beed8fc0
AO		 2821/* ??? It would be much easier to add the h8sx stuff if a single function
2822 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
e9eba255
KH		 2823/* Compute the length of an addition insn. */
2824
7d6ac401 2825unsigned int
f16897cb 2826compute_plussi_length (rtx *operands, bool need_flags)
7d6ac401 2827{
ef4bddc2 2828 machine_mode mode = GET_MODE (operands[0]);
7d6ac401 2829
8c440872 2830 gcc_assert (mode == SImode);
7d6ac401 2831
27c1afd5
JL		 2832 if (GET_CODE (operands[2]) == CONST_INT
2833 && register_operand (operands[1], VOIDmode))
7d6ac401 2834 {
27c1afd5 2835 HOST_WIDE_INT intval = INTVAL (operands[2]);
cfedf91b 2836
27c1afd5
JL		 2837 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
2838 return 2;
2839 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
2840 return 2;
cfedf91b 2841
27c1afd5 2842 /* See if we can finish with 2 bytes. */
cfedf91b 2843
27c1afd5 2844 switch ((unsigned int) intval & 0xffffffff)
7d6ac401 2845 {
27c1afd5
JL		 2846 case 0x00000001:
2847 case 0x00000002:
27c1afd5 2848 return 2;
f16897cb
AL		 2849 case 0x00000004:
2850 if (need_flags)
2851 return 6;
2852 else
2853 return 2;
27c1afd5
JL		 2854
2855 case 0xffffffff:
2856 case 0xfffffffe:
27c1afd5 2857 return 2;
f16897cb
AL		 2858 case 0xfffffffc:
2859 if (need_flags)
2860 return 6;
2861 else
2862 return 2;
27c1afd5
JL		 2863
2864 case 0x00010000:
2865 case 0x00020000:
f16897cb
AL		 2866 if (!need_flags)
2867 return 2;
27c1afd5 2868
12bb62fb
JL		 2869 /* FALLTHRU */
2870
27c1afd5
JL		 2871 case 0xffff0000:
2872 case 0xfffe0000:
f16897cb
AL		 2873 if (!need_flags)
2874 return 2;
12bb62fb
JL		 2875
2876 /* FALLTHRU */
2877
7d6ac401
KH		 2878 }
2879
27c1afd5
JL		 2880 /* See if we can finish with 4 bytes. */
2881 if ((intval & 0xffff) == 0)
2882 return 4;
7d6ac401 2883 }
27c1afd5
JL		 2884
2885 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
2886 return h8300_length_from_table (operands[0],
2887 GEN_INT (-INTVAL (operands[2])),
2888 &addl_length_table);
2889 else
2890 return h8300_length_from_table (operands[0], operands[2],
2891 &addl_length_table);
7d6ac401
KH		 2892}
2893
e9eba255
KH		 2894/* Compute which flag bits are valid after an addition insn. */
2895
5ddb6eca 2896enum attr_old_cc
cb713a8d 2897compute_plussi_cc (rtx *operands)
7d6ac401 2898{
ef4bddc2 2899 machine_mode mode = GET_MODE (operands[0]);
7d6ac401 2900
8c440872 2901 gcc_assert (mode == SImode);
7d6ac401 2902
27c1afd5
JL		 2903 if (GET_CODE (operands[2]) == CONST_INT
2904 && register_operand (operands[1], VOIDmode))
7d6ac401 2905 {
27c1afd5 2906 HOST_WIDE_INT intval = INTVAL (operands[2]);
7d6ac401 2907
27c1afd5 2908 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
5ddb6eca 2909 return OLD_CC_SET_ZN;
27c1afd5 2910 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
5ddb6eca 2911 return OLD_CC_SET_ZN;
beed8fc0 2912
27c1afd5 2913 /* See if we can finish with 2 bytes. */
7d6ac401 2914
27c1afd5
JL		 2915 switch ((unsigned int) intval & 0xffffffff)
2916 {
2917 case 0x00000001:
2918 case 0x00000002:
2919 case 0x00000004:
5ddb6eca 2920 return OLD_CC_NONE_0HIT;
27c1afd5
JL		 2921
2922 case 0xffffffff:
2923 case 0xfffffffe:
2924 case 0xfffffffc:
5ddb6eca 2925 return OLD_CC_NONE_0HIT;
27c1afd5
JL		 2926
2927 case 0x00010000:
2928 case 0x00020000:
5ddb6eca 2929 return OLD_CC_CLOBBER;
27c1afd5
JL		 2930
2931 case 0xffff0000:
2932 case 0xfffe0000:
5ddb6eca 2933 return OLD_CC_CLOBBER;
7d6ac401
KH		 2934 }
2935
27c1afd5
JL		 2936 /* See if we can finish with 4 bytes. */
2937 if ((intval & 0xffff) == 0)
5ddb6eca 2938 return OLD_CC_CLOBBER;
7d6ac401 2939 }
27c1afd5 2940
5ddb6eca 2941 return OLD_CC_SET_ZN;
7d6ac401
KH		 2942}
2943\f
e9eba255
KH		 2944/* Output a logical insn. */
2945
7d6ac401 2946const char *
402c818a 2947output_logical_op (machine_mode mode, rtx_code code, rtx *operands, rtx_insn *insn)
366a7b27
KH		 2948{
2949 /* Pretend that every byte is affected if both operands are registers. */
7798db98 2950 const unsigned HOST_WIDE_INT intval =
366a7b27 2951 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
beed8fc0
AO		 2952 /* Always use the full instruction if the
2953 first operand is in memory. It is better
2954 to use define_splits to generate the shorter
2955 sequence where valid. */
2956 && register_operand (operands[1], VOIDmode)
366a7b27
KH		 2957 ? INTVAL (operands[2]) : 0x55555555);
2958 /* The determinant of the algorithm. If we perform an AND, 0
2959 affects a bit. Otherwise, 1 affects a bit. */
7798db98 2960 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
f9ac2f95
KH		 2961 /* Break up DET into pieces. */
2962 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2963 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2964 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2965 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2966 int lower_half_easy_p = 0;
2967 int upper_half_easy_p = 0;
366a7b27
KH		 2968 /* The name of an insn. */
2969 const char *opname;
2970 char insn_buf[100];
2971
402c818a
JL		 2972 /* INSN is the current insn, we examine its overall form to see if we're
2973 supposed to set or clobber the condition codes.
2974
2975 This is important to know. If we are setting condition codes, then we
2976 must do the operation in MODE and not in some smaller size.
2977
2978 The key is to look at the second object in the PARALLEL. If it is not
2979 a CLOBBER, then we care about the condition codes. */
2980 rtx pattern = PATTERN (insn);
2981 gcc_assert (GET_CODE (pattern) == PARALLEL);
2982 rtx second_op = XVECEXP (pattern, 0, 1);
2983 bool cc_meaningful = (GET_CODE (second_op) != CLOBBER);
2984
366a7b27
KH		 2985 switch (code)
2986 {
2987 case AND:
2988 opname = "and";
2989 break;
2990 case IOR:
2991 opname = "or";
2992 break;
2993 case XOR:
2994 opname = "xor";
2995 break;
2996 default:
8c440872 2997 gcc_unreachable ();
366a7b27
KH		 2998 }
2999
3000 switch (mode)
3001 {
4ea5fe8b
JL		 3002 case E_QImode:
3003 sprintf (insn_buf, "%s.b\t%%X2,%%X0", opname);
3004 output_asm_insn (insn_buf, operands);
3005 break;
4e10a5a7 3006 case E_HImode:
402c818a
JL		 3007 /* First, see if we can (or must) finish with one insn. */
3008 if (cc_meaningful
3009 || (b0 != 0 && b1 != 0))
366a7b27
KH		 3010 {
3011 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
3012 output_asm_insn (insn_buf, operands);
3013 }
3014 else
3015 {
3016 /* Take care of the lower byte. */
c5e7ce43 3017 if (b0 != 0)
366a7b27
KH		 3018 {
3019 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
3020 output_asm_insn (insn_buf, operands);
3021 }
3022 /* Take care of the upper byte. */
c5e7ce43 3023 if (b1 != 0)
366a7b27
KH		 3024 {
3025 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
3026 output_asm_insn (insn_buf, operands);
3027 }
3028 }
3029 break;
4e10a5a7 3030 case E_SImode:
27c1afd5
JL		 3031 /* Determine if the lower half can be taken care of in no more
3032 than two bytes. */
3033 lower_half_easy_p = (b0 == 0
3034 || b1 == 0
3035 || (code != IOR && w0 == 0xffff));
3036
3037 /* Determine if the upper half can be taken care of in no more
3038 than two bytes. */
3039 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3040 || (code == AND && w1 == 0xff00));
366a7b27 3041
f9ac2f95
KH		 3042 /* Check if doing everything with one insn is no worse than
3043 using multiple insns. */
402c818a
JL		 3044 if (cc_meaningful
3045 || (w0 != 0 && w1 != 0
3046 && !(lower_half_easy_p && upper_half_easy_p)
3047 && !(code == IOR && w1 == 0xffff
3048 && (w0 & 0x8000) != 0 && lower_half_easy_p)))
366a7b27
KH		 3049 {
3050 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
3051 output_asm_insn (insn_buf, operands);
3052 }
3053 else
3054 {
3055 /* Take care of the lower and upper words individually. For
3056 each word, we try different methods in the order of
3057
3058 1) the special insn (in case of AND or XOR),
3059 2) the word-wise insn, and
3060 3) The byte-wise insn. */
27c1afd5 3061 if (w0 == 0xffff && (code != IOR))
366a7b27 3062 output_asm_insn ((code == AND)
187462ac 3063 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
366a7b27 3064 operands);
27c1afd5 3065 else if ((b0 != 0) && (b1 != 0))
366a7b27
KH		 3066 {
3067 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
3068 output_asm_insn (insn_buf, operands);
3069 }
3070 else
3071 {
c5e7ce43 3072 if (b0 != 0)
366a7b27
KH		 3073 {
3074 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
3075 output_asm_insn (insn_buf, operands);
3076 }
c5e7ce43 3077 if (b1 != 0)
366a7b27
KH		 3078 {
3079 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
3080 output_asm_insn (insn_buf, operands);
3081 }
3082 }
3083
27c1afd5 3084 if ((w1 == 0xffff) && (code != IOR))
366a7b27 3085 output_asm_insn ((code == AND)
187462ac 3086 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
366a7b27 3087 operands);
27c1afd5 3088 else if (code == IOR
472f2723
KH		 3089 && w1 == 0xffff
3090 && (w0 & 0x8000) != 0)
3091 {
3092 output_asm_insn ("exts.l\t%S0", operands);
3093 }
27c1afd5 3094 else if (code == AND
c5e7ce43 3095 && w1 == 0xff00)
a6e8d113 3096 {
dc5f17ec 3097 output_asm_insn ("extu.w\t%e0", operands);
a6e8d113 3098 }
27c1afd5 3099 else
366a7b27 3100 {
c5e7ce43 3101 if (w1 != 0)
366a7b27
KH		 3102 {
3103 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
3104 output_asm_insn (insn_buf, operands);
3105 }
3106 }
366a7b27
KH		 3107 }
3108 break;
3109 default:
8c440872 3110 gcc_unreachable ();
366a7b27
KH		 3111 }
3112 return "";
3113}
40367e2d 3114
e9eba255
KH		 3115/* Compute the length of a logical insn. */
3116
40367e2d 3117unsigned int
402c818a 3118compute_logical_op_length (machine_mode mode, rtx_code code, rtx *operands, rtx_insn *insn)
40367e2d
KH		 3119{
3120 /* Pretend that every byte is affected if both operands are registers. */
7798db98 3121 const unsigned HOST_WIDE_INT intval =
40367e2d 3122 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
beed8fc0
AO		 3123 /* Always use the full instruction if the
3124 first operand is in memory. It is better
3125 to use define_splits to generate the shorter
3126 sequence where valid. */
3127 && register_operand (operands[1], VOIDmode)
40367e2d
KH		 3128 ? INTVAL (operands[2]) : 0x55555555);
3129 /* The determinant of the algorithm. If we perform an AND, 0
3130 affects a bit. Otherwise, 1 affects a bit. */
7798db98 3131 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
f9ac2f95
KH		 3132 /* Break up DET into pieces. */
3133 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3134 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3135 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3136 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3137 int lower_half_easy_p = 0;
3138 int upper_half_easy_p = 0;
40367e2d
KH		 3139 /* Insn length. */
3140 unsigned int length = 0;
3141
402c818a
JL		 3142 /* INSN is the current insn, we examine its overall form to see if we're
3143 supposed to set or clobber the condition codes.
3144
3145 This is important to know. If we are setting condition codes, then we
3146 must do the operation in MODE and not in some smaller size.
3147
3148 The key is to look at the second object in the PARALLEL. If it is not
3149 a CLOBBER, then we care about the condition codes. */
3150 bool cc_meaningful = false;
3151 if (insn)
3152 {
3153 rtx pattern = PATTERN (insn);
3154 gcc_assert (GET_CODE (pattern) == PARALLEL);
3155 rtx second_op = XVECEXP (pattern, 0, 1);
3156 cc_meaningful = (GET_CODE (second_op) != CLOBBER);
3157 }
3158
40367e2d
KH		 3159 switch (mode)
3160 {
4ea5fe8b
JL		 3161 case E_QImode:
3162 return 2;
3163
4e10a5a7 3164 case E_HImode:
40367e2d 3165 /* First, see if we can finish with one insn. */
402c818a
JL		 3166 if (cc_meaningful
3167 || (b0 != 0 && b1 != 0))
40367e2d 3168 {
beed8fc0
AO		 3169 length = h8300_length_from_table (operands[1], operands[2],
3170 &logicw_length_table);
40367e2d
KH		 3171 }
3172 else
3173 {
3174 /* Take care of the lower byte. */
c5e7ce43 3175 if (b0 != 0)
40367e2d
KH		 3176 length += 2;
3177
3178 /* Take care of the upper byte. */
c5e7ce43 3179 if (b1 != 0)
40367e2d
KH		 3180 length += 2;
3181 }
3182 break;
4e10a5a7 3183 case E_SImode:
27c1afd5
JL		 3184 /* Determine if the lower half can be taken care of in no more
3185 than two bytes. */
3186 lower_half_easy_p = (b0 == 0
3187 || b1 == 0
3188 || (code != IOR && w0 == 0xffff));
3189
3190 /* Determine if the upper half can be taken care of in no more
3191 than two bytes. */
3192 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3193 || (code == AND && w1 == 0xff00));
40367e2d 3194
f9ac2f95
KH		 3195 /* Check if doing everything with one insn is no worse than
3196 using multiple insns. */
402c818a
JL		 3197 if (cc_meaningful
3198 || (w0 != 0 && w1 != 0
3199 && !(lower_half_easy_p && upper_half_easy_p)
3200 && !(code == IOR && w1 == 0xffff
3201 && (w0 & 0x8000) != 0 && lower_half_easy_p)))
40367e2d 3202 {
beed8fc0
AO		 3203 length = h8300_length_from_table (operands[1], operands[2],
3204 &logicl_length_table);
40367e2d
KH		 3205 }
3206 else
3207 {
3208 /* Take care of the lower and upper words individually. For
3209 each word, we try different methods in the order of
3210
3211 1) the special insn (in case of AND or XOR),
3212 2) the word-wise insn, and
3213 3) The byte-wise insn. */
27c1afd5 3214 if (w0 == 0xffff && (code != IOR))
40367e2d
KH		 3215 {
3216 length += 2;
3217 }
27c1afd5 3218 else if ((b0 != 0) && (b1 != 0))
40367e2d
KH		 3219 {
3220 length += 4;
3221 }
3222 else
3223 {
c5e7ce43 3224 if (b0 != 0)
40367e2d
KH		 3225 length += 2;
3226
c5e7ce43 3227 if (b1 != 0)
40367e2d
KH		 3228 length += 2;
3229 }
3230
27c1afd5 3231 if (w1 == 0xffff && (code != IOR))
40367e2d
KH		 3232 {
3233 length += 2;
3234 }
27c1afd5 3235 else if (code == IOR
472f2723
KH		 3236 && w1 == 0xffff
3237 && (w0 & 0x8000) != 0)
3238 {
3239 length += 2;
3240 }
27c1afd5 3241 else if (code == AND && w1 == 0xff00)
a6e8d113
KH		 3242 {
3243 length += 2;
3244 }
27c1afd5 3245 else
40367e2d 3246 {
c5e7ce43 3247 if (w1 != 0)
40367e2d
KH		 3248 length += 4;
3249 }
40367e2d
KH		 3250 }
3251 break;
3252 default:
8c440872 3253 gcc_unreachable ();
40367e2d
KH		 3254 }
3255 return length;
3256}
b42cff6b 3257
366a7b27 3258\f
f16897cb 3259#if 0
8981ecd3
KH		 3260/* Expand a conditional branch. */
3261
3262void
f90b7a5a 3263h8300_expand_branch (rtx operands[])
8981ecd3 3264{
f90b7a5a
PB		 3265 enum rtx_code code = GET_CODE (operands[0]);
3266 rtx op0 = operands[1];
3267 rtx op1 = operands[2];
3268 rtx label = operands[3];
8981ecd3
KH		 3269 rtx tmp;
3270
f90b7a5a 3271 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
f7df4a84 3272 emit_insn (gen_rtx_SET (cc0_rtx, tmp));
f90b7a5a 3273
8981ecd3
KH		 3274 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
3275 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
3276 gen_rtx_LABEL_REF (VOIDmode, label),
3277 pc_rtx);
f7df4a84 3278 emit_jump_insn (gen_rtx_SET (pc_rtx, tmp));
8981ecd3 3279}
f90b7a5a
PB		 3280
3281
3282/* Expand a conditional store. */
3283
3284void
3285h8300_expand_store (rtx operands[])
3286{
3287 rtx dest = operands[0];
3288 enum rtx_code code = GET_CODE (operands[1]);
3289 rtx op0 = operands[2];
3290 rtx op1 = operands[3];
3291 rtx tmp;
3292
3293 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
f7df4a84 3294 emit_insn (gen_rtx_SET (cc0_rtx, tmp));
f90b7a5a
PB		 3295
3296 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx);
f7df4a84 3297 emit_insn (gen_rtx_SET (dest, tmp));
f90b7a5a 3298}
f16897cb 3299#endif
8981ecd3 3300\f
48837e29
DE		 3301/* Shifts.
3302
005e3e05
KH		 3303 We devote a fair bit of code to getting efficient shifts since we
3304 can only shift one bit at a time on the H8/300 and H8/300H and only
3db11b5c 3305 one or two bits at a time on the H8S.
005e3e05
KH		 3306
3307 All shift code falls into one of the following ways of
3308 implementation:
3309
3310 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3311 when a straight line shift is about the same size or smaller than
3312 a loop.
3313
3314 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3315 off the bits we don't need. This is used when only a few of the
3316 bits in the original value will survive in the shifted value.
3317
3318 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3319 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3320 shifts can be added if the shift count is slightly more than 8 or
3321 16. This case also includes other oddballs that are not worth
f411c849 3322 explaining here.
005e3e05 3323
3db11b5c 3324 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
005e3e05 3325
5ec0b66e
KH		 3326 For each shift count, we try to use code that has no trade-off
3327 between code size and speed whenever possible.
3328
3329 If the trade-off is unavoidable, we try to be reasonable.
3330 Specifically, the fastest version is one instruction longer than
3331 the shortest version, we take the fastest version. We also provide
3332 the use a way to switch back to the shortest version with -Os.
3333
3334 For the details of the shift algorithms for various shift counts,
3335 refer to shift_alg_[qhs]i. */
07aae5c2 3336
beed8fc0
AO		 3337/* Classify a shift with the given mode and code. OP is the shift amount. */
3338
3339enum h8sx_shift_type
ef4bddc2 3340h8sx_classify_shift (machine_mode mode, enum rtx_code code, rtx op)
beed8fc0
AO		 3341{
3342 if (!TARGET_H8300SX)
3343 return H8SX_SHIFT_NONE;
3344
3345 switch (code)
3346 {
3347 case ASHIFT:
3348 case LSHIFTRT:
3349 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3350 if (GET_CODE (op) != CONST_INT)
3351 return H8SX_SHIFT_BINARY;
3352
3353 /* Reject out-of-range shift amounts. */
3354 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
3355 return H8SX_SHIFT_NONE;
3356
3357 /* Power-of-2 shifts are effectively unary operations. */
3358 if (exact_log2 (INTVAL (op)) >= 0)
3359 return H8SX_SHIFT_UNARY;
3360
3361 return H8SX_SHIFT_BINARY;
3362
3363 case ASHIFTRT:
3364 if (op == const1_rtx || op == const2_rtx)
3365 return H8SX_SHIFT_UNARY;
3366 return H8SX_SHIFT_NONE;
3367
3368 case ROTATE:
3369 if (GET_CODE (op) == CONST_INT
3370 && (INTVAL (op) == 1
3371 || INTVAL (op) == 2
3372 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
3373 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
3374 return H8SX_SHIFT_UNARY;
3375 return H8SX_SHIFT_NONE;
3376
3377 default:
3378 return H8SX_SHIFT_NONE;
3379 }
3380}
3381
beed8fc0
AO		 3382/* Return the asm template for a single h8sx shift instruction.
3383 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3384 is the source and OPERANDS[3] is the shift. SUFFIX is the
88cb339e 3385 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
beed8fc0
AO		 3386 prefix for the destination operand. */
3387
3388const char *
3389output_h8sx_shift (rtx *operands, int suffix, int optype)
3390{
3391 static char buffer[16];
3392 const char *stem;
3393
3394 switch (GET_CODE (operands[3]))
3395 {
3396 case ASHIFT:
3397 stem = "shll";
3398 break;
3399
3400 case ASHIFTRT:
3401 stem = "shar";
3402 break;
3403
3404 case LSHIFTRT:
3405 stem = "shlr";
3406 break;
3407
3408 case ROTATE:
3409 stem = "rotl";
3410 if (INTVAL (operands[2]) > 2)
3411 {
3412 /* This is really a right rotate. */
3413 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
3414 - INTVAL (operands[2]));
3415 stem = "rotr";
3416 }
3417 break;
3418
3419 default:
8c440872 3420 gcc_unreachable ();
beed8fc0
AO		 3421 }
3422 if (operands[2] == const1_rtx)
3423 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
3424 else
3425 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
3426 return buffer;
3427}
48837e29 3428
317d21e9 3429/* Emit code to do shifts. */
48837e29 3430
beed8fc0 3431bool
ef4bddc2 3432expand_a_shift (machine_mode mode, enum rtx_code code, rtx operands[])
07aae5c2 3433{
beed8fc0
AO		 3434 switch (h8sx_classify_shift (mode, code, operands[2]))
3435 {
3436 case H8SX_SHIFT_BINARY:
3437 operands[1] = force_reg (mode, operands[1]);
3438 return false;
3439
3440 case H8SX_SHIFT_UNARY:
3441 return false;
3442
3443 case H8SX_SHIFT_NONE:
3444 break;
3445 }
3446
07e4d94e
KH		 3447 /* Need a loop to get all the bits we want - we generate the
3448 code at emit time, but need to allocate a scratch reg now. */
70033749
JL		 3449 emit_move_insn (copy_rtx (operands[0]), operands[1]);
3450 if (operands[2] == CONST0_RTX (QImode))
3451 ;
3452 else if (GET_CODE (operands[2]) == CONST_INT
3453 && !h8300_shift_needs_scratch_p (INTVAL (operands[2]), mode, code))
3454 emit_insn (gen_rtx_SET (copy_rtx (operands[0]),
3455 gen_rtx_fmt_ee (code, mode,
3456 copy_rtx (operands[1]), operands[2])));
3457 else
3458 emit_insn (gen_rtx_PARALLEL
3459 (VOIDmode,
3460 gen_rtvec (2,
3461 gen_rtx_SET (copy_rtx (operands[0]),
3462 gen_rtx_fmt_ee (code, mode,
3463 copy_rtx (operands[0]), operands[2])),
3464 gen_rtx_CLOBBER (VOIDmode,
3465 gen_rtx_SCRATCH (QImode)))));
beed8fc0 3466 return true;
48837e29
DE		 3467}
3468
48837e29
DE		 3469/* Symbols of the various modes which can be used as indices. */
3470
3471enum shift_mode
1a63219b
KH		 3472{
3473 QIshift, HIshift, SIshift
3474};
48837e29 3475
269c14e1 3476/* For single bit shift insns, record assembler and what bits of the
5ddb6eca 3477 condition code are valid afterwards (represented as various OLD_CC_FOO
269c14e1 3478 bits, 0 means CC isn't left in a usable state). */
48837e29
DE		 3479
3480struct shift_insn
3481{
8b60264b 3482 const char *const assembler;
5ddb6eca 3483 const enum attr_old_cc cc_valid;
48837e29
DE		 3484};
3485
3486/* Assembler instruction shift table.
3487
3488 These tables are used to look up the basic shifts.
07e4d94e 3489 They are indexed by cpu, shift_type, and mode. */
07aae5c2 3490
48837e29
DE		 3491static const struct shift_insn shift_one[2][3][3] =
3492{
3493/* H8/300 */
3494 {
3495/* SHIFT_ASHIFT */
3496 {
5ddb6eca
JL		 3497 { "shll\t%X0", OLD_CC_SET_ZNV },
3498 { "add.w\t%T0,%T0", OLD_CC_SET_ZN },
3499 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", OLD_CC_CLOBBER }
48837e29
DE		 3500 },
3501/* SHIFT_LSHIFTRT */
3502 {
5ddb6eca
JL		 3503 { "shlr\t%X0", OLD_CC_SET_ZNV },
3504 { "shlr\t%t0\n\trotxr\t%s0", OLD_CC_CLOBBER },
3505 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", OLD_CC_CLOBBER }
48837e29
DE		 3506 },
3507/* SHIFT_ASHIFTRT */
3508 {
5ddb6eca
JL		 3509 { "shar\t%X0", OLD_CC_SET_ZNV },
3510 { "shar\t%t0\n\trotxr\t%s0", OLD_CC_CLOBBER },
3511 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", OLD_CC_CLOBBER }
48837e29
DE		 3512 }
3513 },
3514/* H8/300H */
3515 {
3516/* SHIFT_ASHIFT */
3517 {
5ddb6eca
JL		 3518 { "shll.b\t%X0", OLD_CC_SET_ZNV },
3519 { "shll.w\t%T0", OLD_CC_SET_ZNV },
3520 { "shll.l\t%S0", OLD_CC_SET_ZNV }
48837e29
DE		 3521 },
3522/* SHIFT_LSHIFTRT */
3523 {
5ddb6eca
JL		 3524 { "shlr.b\t%X0", OLD_CC_SET_ZNV },
3525 { "shlr.w\t%T0", OLD_CC_SET_ZNV },
3526 { "shlr.l\t%S0", OLD_CC_SET_ZNV }
48837e29
DE		 3527 },
3528/* SHIFT_ASHIFTRT */
3529 {
5ddb6eca
JL		 3530 { "shar.b\t%X0", OLD_CC_SET_ZNV },
3531 { "shar.w\t%T0", OLD_CC_SET_ZNV },
3532 { "shar.l\t%S0", OLD_CC_SET_ZNV }
48837e29
DE		 3533 }
3534 }
3535};
07aae5c2 3536
51c0c1d7
JL		 3537static const struct shift_insn shift_two[3][3] =
3538{
3539/* SHIFT_ASHIFT */
3540 {
5ddb6eca
JL		 3541 { "shll.b\t#2,%X0", OLD_CC_SET_ZNV },
3542 { "shll.w\t#2,%T0", OLD_CC_SET_ZNV },
3543 { "shll.l\t#2,%S0", OLD_CC_SET_ZNV }
51c0c1d7
JL		 3544 },
3545/* SHIFT_LSHIFTRT */
3546 {
5ddb6eca
JL		 3547 { "shlr.b\t#2,%X0", OLD_CC_SET_ZNV },
3548 { "shlr.w\t#2,%T0", OLD_CC_SET_ZNV },
3549 { "shlr.l\t#2,%S0", OLD_CC_SET_ZNV }
51c0c1d7
JL		 3550 },
3551/* SHIFT_ASHIFTRT */
3552 {
5ddb6eca
JL		 3553 { "shar.b\t#2,%X0", OLD_CC_SET_ZNV },
3554 { "shar.w\t#2,%T0", OLD_CC_SET_ZNV },
3555 { "shar.l\t#2,%S0", OLD_CC_SET_ZNV }
51c0c1d7
JL		 3556 }
3557};
3558
48837e29
DE		 3559/* Rotates are organized by which shift they'll be used in implementing.
3560 There's no need to record whether the cc is valid afterwards because
3561 it is the AND insn that will decide this. */
07aae5c2 3562
48837e29
DE		 3563static const char *const rotate_one[2][3][3] =
3564{
3565/* H8/300 */
3566 {
3567/* SHIFT_ASHIFT */
3568 {
51c0c1d7
JL		 3569 "rotr\t%X0",
3570 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
48837e29
DE		 3571 0
3572 },
3573/* SHIFT_LSHIFTRT */
3574 {
51c0c1d7
JL		 3575 "rotl\t%X0",
3576 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
48837e29
DE		 3577 0
3578 },
3579/* SHIFT_ASHIFTRT */
3580 {
51c0c1d7
JL		 3581 "rotl\t%X0",
3582 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
48837e29 3583 0
07aae5c2 3584 }
48837e29
DE		 3585 },
3586/* H8/300H */
3587 {
3588/* SHIFT_ASHIFT */
3589 {
51c0c1d7
JL		 3590 "rotr.b\t%X0",
3591 "rotr.w\t%T0",
3592 "rotr.l\t%S0"
48837e29
DE		 3593 },
3594/* SHIFT_LSHIFTRT */
07aae5c2 3595 {
51c0c1d7
JL		 3596 "rotl.b\t%X0",
3597 "rotl.w\t%T0",
3598 "rotl.l\t%S0"
48837e29
DE		 3599 },
3600/* SHIFT_ASHIFTRT */
3601 {
51c0c1d7
JL		 3602 "rotl.b\t%X0",
3603 "rotl.w\t%T0",
3604 "rotl.l\t%S0"
48837e29
DE		 3605 }
3606 }
3607};
3608
51c0c1d7
JL		 3609static const char *const rotate_two[3][3] =
3610{
3611/* SHIFT_ASHIFT */
3612 {
3613 "rotr.b\t#2,%X0",
3614 "rotr.w\t#2,%T0",
3615 "rotr.l\t#2,%S0"
3616 },
3617/* SHIFT_LSHIFTRT */
3618 {
3619 "rotl.b\t#2,%X0",
3620 "rotl.w\t#2,%T0",
3621 "rotl.l\t#2,%S0"
3622 },
3623/* SHIFT_ASHIFTRT */
3624 {
3625 "rotl.b\t#2,%X0",
3626 "rotl.w\t#2,%T0",
3627 "rotl.l\t#2,%S0"
3628 }
3629};
3630
35fb3d1f
KH		 3631struct shift_info {
3632 /* Shift algorithm. */
3633 enum shift_alg alg;
3634
3635 /* The number of bits to be shifted by shift1 and shift2. Valid
3636 when ALG is SHIFT_SPECIAL. */
3637 unsigned int remainder;
3638
3639 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
3640 const char *special;
3641
3642 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
9cd10576 3643 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
35fb3d1f
KH		 3644 const char *shift1;
3645
3646 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
9cd10576 3647 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
35fb3d1f
KH		 3648 const char *shift2;
3649
45ca2106 3650 /* CC status for SHIFT_INLINE. */
5ddb6eca 3651 enum attr_old_cc cc_inline;
45ca2106
KH		 3652
3653 /* CC status for SHIFT_SPECIAL. */
5ddb6eca 3654 enum attr_old_cc cc_special;
35fb3d1f
KH		 3655};
3656
cb713a8d
KH		 3657static void get_shift_alg (enum shift_type,
3658 enum shift_mode, unsigned int,
3659 struct shift_info *);
441d04c6 3660
c009a745
KH		 3661/* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
3662 best algorithm for doing the shift. The assembler code is stored
5ec0b66e 3663 in the pointers in INFO. We achieve the maximum efficiency in most
27c1afd5 3664 cases.
5ec0b66e
KH		 3665
3666 We first determine the strategy of the shift algorithm by a table
3667 lookup. If that tells us to use a hand crafted assembly code, we
3668 go into the big switch statement to find what that is. Otherwise,
3669 we resort to a generic way, such as inlining. In either case, the
3670 result is returned through INFO. */
48837e29 3671
cb33eb17 3672static void
cb713a8d
KH		 3673get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
3674 unsigned int count, struct shift_info *info)
48837e29 3675{
b9b575e6 3676 enum h8_cpu cpu;
769828ab 3677
27c1afd5 3678 if (TARGET_H8300S)
b9b575e6 3679 cpu = H8_S;
2f6bd6eb
YS		 3680 else
3681 cpu = H8_300H;
769828ab 3682
96eaf358 3683 /* Find the shift algorithm. */
b9b575e6 3684 info->alg = SHIFT_LOOP;
48837e29
DE		 3685 switch (shift_mode)
3686 {
3687 case QIshift:
b9b575e6 3688 if (count < GET_MODE_BITSIZE (QImode))
96eaf358
KH		 3689 info->alg = shift_alg_qi[cpu][shift_type][count];
3690 break;
769828ab 3691
96eaf358 3692 case HIshift:
b9b575e6 3693 if (count < GET_MODE_BITSIZE (HImode))
96eaf358
KH		 3694 info->alg = shift_alg_hi[cpu][shift_type][count];
3695 break;
3696
3697 case SIshift:
b9b575e6 3698 if (count < GET_MODE_BITSIZE (SImode))
96eaf358
KH		 3699 info->alg = shift_alg_si[cpu][shift_type][count];
3700 break;
3701
3702 default:
8c440872 3703 gcc_unreachable ();
96eaf358
KH		 3704 }
3705
3706 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
3707 switch (info->alg)
3708 {
3709 case SHIFT_INLINE:
3710 info->remainder = count;
3711 /* Fall through. */
3712
3713 case SHIFT_LOOP:
3714 /* It is up to the caller to know that looping clobbers cc. */
3715 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
3716 info->shift2 = shift_two[shift_type][shift_mode].assembler;
45ca2106 3717 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
96eaf358
KH		 3718 goto end;
3719
3720 case SHIFT_ROT_AND:
3721 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
3722 info->shift2 = rotate_two[shift_type][shift_mode];
5ddb6eca 3723 info->cc_inline = OLD_CC_CLOBBER;
96eaf358
KH		 3724 goto end;
3725
3726 case SHIFT_SPECIAL:
3727 /* REMAINDER is 0 for most cases, so initialize it to 0. */
3728 info->remainder = 0;
3729 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
3730 info->shift2 = shift_two[shift_type][shift_mode].assembler;
45ca2106 3731 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
5ddb6eca 3732 info->cc_special = OLD_CC_CLOBBER;
96eaf358
KH		 3733 break;
3734 }
51c0c1d7 3735
96eaf358
KH		 3736 /* Here we only deal with SHIFT_SPECIAL. */
3737 switch (shift_mode)
3738 {
3739 case QIshift:
769828ab
KH		 3740 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
3741 through the entire value. */
8c440872
NS		 3742 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
3743 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
3744 goto end;
769828ab
KH		 3745
3746 case HIshift:
769828ab 3747 if (count == 7)
51c0c1d7 3748 {
a77b1dbc 3749 switch (shift_type)
51c0c1d7 3750 {
a77b1dbc 3751 case SHIFT_ASHIFT:
27c1afd5 3752 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
692b7eb3 3753 goto end;
a77b1dbc 3754 case SHIFT_LSHIFTRT:
27c1afd5 3755 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
692b7eb3 3756 goto end;
a77b1dbc 3757 case SHIFT_ASHIFTRT:
35fb3d1f 3758 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
692b7eb3 3759 goto end;
48837e29 3760 }
07aae5c2 3761 }
01512446 3762 else if ((count >= 8 && count <= 13)
a38b3eea 3763 || (TARGET_H8300S && count == 14))
07aae5c2 3764 {
a7812c0b
KH		 3765 info->remainder = count - 8;
3766
51c0c1d7 3767 switch (shift_type)
48837e29 3768 {
51c0c1d7 3769 case SHIFT_ASHIFT:
35fb3d1f 3770 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
692b7eb3 3771 goto end;
51c0c1d7 3772 case SHIFT_LSHIFTRT:
27c1afd5 3773 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
5ddb6eca 3774 info->cc_special = OLD_CC_SET_ZNV;
692b7eb3 3775 goto end;
51c0c1d7 3776 case SHIFT_ASHIFTRT:
27c1afd5 3777 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
5ddb6eca 3778 info->cc_special = OLD_CC_SET_ZNV;
692b7eb3 3779 goto end;
51c0c1d7
JL		 3780 }
3781 }
5e98fba2
DD		 3782 else if (count == 14)
3783 {
3784 switch (shift_type)
3785 {
3786 case SHIFT_ASHIFT:
5e98fba2 3787 case SHIFT_LSHIFTRT:
27c1afd5 3788 goto end;
5e98fba2
DD		 3789 goto end;
3790 case SHIFT_ASHIFTRT:
27c1afd5 3791 if (TARGET_H8300H)
45ca2106
KH		 3792 {
3793 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
5ddb6eca 3794 info->cc_special = OLD_CC_SET_ZNV;
45ca2106 3795 }
5e98fba2 3796 else /* TARGET_H8300S */
8c440872 3797 gcc_unreachable ();
5e98fba2
DD		 3798 goto end;
3799 }
3800 }
1e41e866 3801 else if (count == 15)
51c0c1d7 3802 {
1e41e866
KH		 3803 switch (shift_type)
3804 {
3805 case SHIFT_ASHIFT:
3806 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
3807 goto end;
3808 case SHIFT_LSHIFTRT:
3809 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
3810 goto end;
3811 case SHIFT_ASHIFTRT:
3812 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
3813 goto end;
3814 }
07aae5c2 3815 }
8c440872 3816 gcc_unreachable ();
51c0c1d7 3817
48837e29 3818 case SIshift:
27c1afd5 3819 if (count == 8)
e6bcfef9
JS		 3820 {
3821 switch (shift_type)
3822 {
3823 case SHIFT_ASHIFT:
b60761ba 3824 info->special = "mov.w\t%e0,%f3\n\tmov.b\t%s3,%t3\n\tmov.b\t%t0,%s3\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f3,%e0";
692b7eb3 3825 goto end;
e6bcfef9 3826 case SHIFT_LSHIFTRT:
b60761ba 3827 info->special = "mov.w\t%e0,%f3\n\tmov.b\t%t0,%s0\n\tmov.b\t%s3,%t0\n\tmov.b\t%t3,%s3\n\textu.w\t%f3\n\tmov.w\t%f3,%e0";
692b7eb3 3828 goto end;
e6bcfef9 3829 case SHIFT_ASHIFTRT:
b60761ba 3830 info->special = "mov.w\t%e0,%f3\n\tmov.b\t%t0,%s0\n\tmov.b\t%s3,%t0\n\tmov.b\t%t3,%s3\n\texts.w\t%f3\n\tmov.w\t%f3,%e0";
692b7eb3 3831 goto end;
e6bcfef9
JS		 3832 }
3833 }
27c1afd5 3834 else if (count == 15)
dd69e230 3835 {
5f80c627
JL		 3836 /* The basic idea here is to use the shift-by-16 idiom to make things
3837 small and efficient. Of course, that loses one bit that we need,
3838 so we stuff the bit into C, shift by 16, then rotate the bit
3839 back in. */
dd69e230
KH		 3840 switch (shift_type)
3841 {
3842 case SHIFT_ASHIFT:
3843 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
5ddb6eca 3844 info->cc_special = OLD_CC_SET_ZNV;
dd69e230
KH		 3845 goto end;
3846 case SHIFT_LSHIFTRT:
18cf8dda 3847 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
5ddb6eca 3848 info->cc_special = OLD_CC_SET_ZNV;
dd69e230 3849 goto end;
aefc5826 3850 case SHIFT_ASHIFTRT:
5f80c627
JL		 3851 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\texts.l\t%S0\n\trotxl.l\t%S0";
3852 info->cc_special = OLD_CC_SET_ZNV;
3853 goto end;
dd69e230
KH		 3854 }
3855 }
75a71765 3856 else if (count >= 16 && count <= 23)
48837e29 3857 {
a7812c0b
KH		 3858 info->remainder = count - 16;
3859
48837e29
DE		 3860 switch (shift_type)
3861 {
3862 case SHIFT_ASHIFT:
35fb3d1f 3863 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
692b7eb3 3864 goto end;
51c0c1d7 3865 case SHIFT_LSHIFTRT:
27c1afd5 3866 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
5ddb6eca 3867 info->cc_special = OLD_CC_SET_ZNV;
f9477efd
KH		 3868 goto end;
3869 case SHIFT_ASHIFTRT:
27c1afd5 3870 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
5ddb6eca 3871 info->cc_special = OLD_CC_SET_ZNV;
5f80c627
JL		 3872 goto end;
3873 }
3874 }
3875 else if (TARGET_H8300S && count == 27)
3876 {
3877 switch (shift_type)
3878 {
3879 case SHIFT_ASHIFT:
3880 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3881 goto end;
3882 case SHIFT_LSHIFTRT:
3883 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3884 goto end;
3885 case SHIFT_ASHIFTRT:
3886 info->remainder = count - 24;
3887 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
3888 info->cc_special = OLD_CC_SET_ZNV;
7f473594
KH		 3889 goto end;
3890 }
3891 }
75a71765 3892 else if (count >= 24 && count <= 27)
e6bcfef9 3893 {
4a4ae922
KH		 3894 info->remainder = count - 24;
3895
e6bcfef9
JS		 3896 switch (shift_type)
3897 {
3898 case SHIFT_ASHIFT:
35fb3d1f 3899 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
692b7eb3 3900 goto end;
e6bcfef9 3901 case SHIFT_LSHIFTRT:
35fb3d1f 3902 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
5ddb6eca 3903 info->cc_special = OLD_CC_SET_ZNV;
692b7eb3 3904 goto end;
e6bcfef9 3905 case SHIFT_ASHIFTRT:
35fb3d1f 3906 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
5ddb6eca 3907 info->cc_special = OLD_CC_SET_ZNV;
692b7eb3 3908 goto end;
e6bcfef9
JS		 3909 }
3910 }
27c1afd5 3911 else if (count == 28)
1e5bdc40
KH		 3912 {
3913 switch (shift_type)
3914 {
3915 case SHIFT_ASHIFT:
3916 if (TARGET_H8300H)
3917 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3918 else
3919 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
1e5bdc40
KH		 3920 goto end;
3921 case SHIFT_LSHIFTRT:
3922 if (TARGET_H8300H)
45ca2106
KH		 3923 {
3924 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
5ddb6eca 3925 info->cc_special = OLD_CC_SET_ZNV;
45ca2106 3926 }
1e5bdc40 3927 else
a7612343 3928 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
1e5bdc40
KH		 3929 goto end;
3930 case SHIFT_ASHIFTRT:
75a71765
JL		 3931 info->remainder = count - 24;
3932 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
3933 info->cc_special = OLD_CC_SET_ZNV;
3934 goto end;
1e5bdc40
KH		 3935 }
3936 }
27c1afd5 3937 else if (count == 29)
1e5bdc40
KH		 3938 {
3939 switch (shift_type)
3940 {
3941 case SHIFT_ASHIFT:
3942 if (TARGET_H8300H)
3943 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3944 else
3945 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
1e5bdc40
KH		 3946 goto end;
3947 case SHIFT_LSHIFTRT:
3948 if (TARGET_H8300H)
45ca2106
KH		 3949 {
3950 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
5ddb6eca 3951 info->cc_special = OLD_CC_SET_ZNV;
45ca2106 3952 }
1e5bdc40 3953 else
45ca2106
KH		 3954 {
3955 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
5ddb6eca 3956 info->cc_special = OLD_CC_SET_ZNV;
45ca2106 3957 }
1e5bdc40
KH		 3958 goto end;
3959 case SHIFT_ASHIFTRT:
75a71765
JL		 3960 info->remainder = count - 24;
3961 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
3962 info->cc_special = OLD_CC_SET_ZNV;
3963 goto end;
1e5bdc40
KH		 3964 }
3965 }
27c1afd5 3966 else if (count == 30)
1e5bdc40
KH		 3967 {
3968 switch (shift_type)
3969 {
3970 case SHIFT_ASHIFT:
3971 if (TARGET_H8300H)
3972 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3973 else
3974 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
1e5bdc40
KH		 3975 goto end;
3976 case SHIFT_LSHIFTRT:
3977 if (TARGET_H8300H)
a7612343 3978 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
1e5bdc40 3979 else
a7612343 3980 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
1e5bdc40
KH		 3981 goto end;
3982 case SHIFT_ASHIFTRT:
75a71765
JL		 3983 info->remainder = count - 24;
3984 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
3985 info->cc_special = OLD_CC_SET_ZNV;
3986 goto end;
1e5bdc40
KH		 3987 }
3988 }
48837e29
DE		 3989 else if (count == 31)
3990 {
27c1afd5 3991 switch (shift_type)
48837e29 3992 {
27c1afd5
JL		 3993 case SHIFT_ASHIFT:
3994 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
5ddb6eca 3995 info->cc_special = OLD_CC_SET_ZNV;
27c1afd5
JL		 3996 goto end;
3997 case SHIFT_LSHIFTRT:
3998 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
5ddb6eca 3999 info->cc_special = OLD_CC_SET_ZNV;
27c1afd5
JL		 4000 goto end;
4001 case SHIFT_ASHIFTRT:
4002 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
5ddb6eca 4003 info->cc_special = OLD_CC_SET_ZNV;
27c1afd5 4004 goto end;
48837e29
DE		 4005 }
4006 }
8c440872 4007 gcc_unreachable ();
51c0c1d7 4008
48837e29 4009 default:
8c440872 4010 gcc_unreachable ();
07aae5c2 4011 }
48837e29 4012
cb33eb17
KH		 4013 end:
4014 if (!TARGET_H8300S)
4015 info->shift2 = NULL;
07aae5c2
SC		 4016}
4017
be1e06df
KH		 4018/* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4019 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4020
4021int
70033749 4022h8300_shift_needs_scratch_p (int count, machine_mode mode, enum rtx_code type)
be1e06df 4023{
b9b575e6 4024 enum h8_cpu cpu;
be1e06df
KH		 4025 int a, lr, ar;
4026
4027 if (GET_MODE_BITSIZE (mode) <= count)
4028 return 1;
4029
4030 /* Find out the target CPU. */
27c1afd5 4031 if (TARGET_H8300S)
b9b575e6 4032 cpu = H8_S;
2f6bd6eb
YS		 4033 else
4034 cpu = H8_300H;
be1e06df
KH		 4035
4036 /* Find the shift algorithm. */
4037 switch (mode)
4038 {
4e10a5a7 4039 case E_QImode:
be1e06df
KH		 4040 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
4041 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
4042 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
4043 break;
4044
4e10a5a7 4045 case E_HImode:
be1e06df
KH		 4046 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
4047 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
4048 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
4049 break;
4050
4e10a5a7 4051 case E_SImode:
be1e06df
KH		 4052 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
4053 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
4054 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
4055 break;
4056
4057 default:
8c440872 4058 gcc_unreachable ();
be1e06df
KH		 4059 }
4060
aa2fb4dd 4061 /* On H8/300H, count == 8 uses a scratch register. */
70033749
JL		 4062 if (type == CLOBBER)
4063 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
4064 || (TARGET_H8300H && mode == SImode && count == 8));
4065 else if (type == ASHIFT)
4066 return (a == SHIFT_LOOP
4067 || (TARGET_H8300H && mode == SImode && count == 8));
4068 else if (type == LSHIFTRT)
4069 return (lr == SHIFT_LOOP
4070 || (TARGET_H8300H && mode == SImode && count == 8));
4071 else if (type == ASHIFTRT)
4072 return (ar == SHIFT_LOOP
4073 || (TARGET_H8300H && mode == SImode && count == 8));
12bb62fb 4074 gcc_unreachable ();
be1e06df
KH		 4075}
4076
e9eba255 4077/* Output the assembler code for doing shifts. */
48837e29 4078
441d04c6 4079const char *
b60761ba 4080output_a_shift (rtx operands[4], rtx_code code)
07aae5c2 4081{
48837e29 4082 static int loopend_lab;
b60761ba 4083 machine_mode mode = GET_MODE (operands[0]);
48837e29
DE		 4084 enum shift_type shift_type;
4085 enum shift_mode shift_mode;
35fb3d1f 4086 struct shift_info info;
8c440872 4087 int n;
48837e29
DE		 4088
4089 loopend_lab++;
4090
4091 switch (mode)
4092 {
4e10a5a7 4093 case E_QImode:
48837e29
DE		 4094 shift_mode = QIshift;
4095 break;
4e10a5a7 4096 case E_HImode:
48837e29
DE		 4097 shift_mode = HIshift;
4098 break;
4e10a5a7 4099 case E_SImode:
48837e29
DE		 4100 shift_mode = SIshift;
4101 break;
4102 default:
8c440872 4103 gcc_unreachable ();
48837e29 4104 }
07aae5c2 4105
48837e29 4106 switch (code)
07aae5c2 4107 {
48837e29
DE		 4108 case ASHIFTRT:
4109 shift_type = SHIFT_ASHIFTRT;
4110 break;
4111 case LSHIFTRT:
4112 shift_type = SHIFT_LSHIFTRT;
4113 break;
4114 case ASHIFT:
4115 shift_type = SHIFT_ASHIFT;
4116 break;
4117 default:
8c440872 4118 gcc_unreachable ();
48837e29 4119 }
07aae5c2 4120
8c440872
NS		 4121 /* This case must be taken care of by one of the two splitters
4122 that convert a variable shift into a loop. */
4123 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4124
4125 n = INTVAL (operands[2]);
4126
4127 /* If the count is negative, make it 0. */
4128 if (n < 0)
4129 n = 0;
4130 /* If the count is too big, truncate it.
4131 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4132 do the intuitive thing. */
4133 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4134 n = GET_MODE_BITSIZE (mode);
4135
4136 get_shift_alg (shift_type, shift_mode, n, &info);
4137
4138 switch (info.alg)
48837e29 4139 {
8c440872
NS		 4140 case SHIFT_SPECIAL:
4141 output_asm_insn (info.special, operands);
4142 /* Fall through. */
48837e29 4143
8c440872
NS		 4144 case SHIFT_INLINE:
4145 n = info.remainder;
48837e29 4146
8c440872
NS		 4147 /* Emit two bit shifts first. */
4148 if (info.shift2 != NULL)
48837e29 4149 {
8c440872
NS		 4150 for (; n > 1; n -= 2)
4151 output_asm_insn (info.shift2, operands);
4152 }
51c0c1d7 4153
8c440872
NS		 4154 /* Now emit one bit shifts for any residual. */
4155 for (; n > 0; n--)
4156 output_asm_insn (info.shift1, operands);
4157 return "";
4158
4159 case SHIFT_ROT_AND:
4160 {
4161 int m = GET_MODE_BITSIZE (mode) - n;
4162 const int mask = (shift_type == SHIFT_ASHIFT
4163 ? ((1 << m) - 1) << n
4164 : (1 << m) - 1);
4165 char insn_buf[200];
4166
4167 /* Not all possibilities of rotate are supported. They shouldn't
4168 be generated, but let's watch for 'em. */
4169 gcc_assert (info.shift1);
4170
4171 /* Emit two bit rotates first. */
4172 if (info.shift2 != NULL)
48837e29 4173 {
8c440872
NS		 4174 for (; m > 1; m -= 2)
4175 output_asm_insn (info.shift2, operands);
4176 }
4177
4178 /* Now single bit rotates for any residual. */
4179 for (; m > 0; m--)
4180 output_asm_insn (info.shift1, operands);
4181
4182 /* Now mask off the high bits. */
4183 switch (mode)
4184 {
4e10a5a7 4185 case E_QImode:
8c440872
NS		 4186 sprintf (insn_buf, "and\t#%d,%%X0", mask);
4187 break;
51c0c1d7 4188
4e10a5a7 4189 case E_HImode:
8c440872
NS		 4190 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
4191 break;
51c0c1d7 4192
8c440872
NS		 4193 default:
4194 gcc_unreachable ();
48837e29 4195 }
b5eaf9ba 4196
8c440872
NS		 4197 output_asm_insn (insn_buf, operands);
4198 return "";
4199 }
b5eaf9ba 4200
8c440872
NS		 4201 case SHIFT_LOOP:
4202 /* A loop to shift by a "large" constant value.
4203 If we have shift-by-2 insns, use them. */
4204 if (info.shift2 != NULL)
4205 {
4206 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
b60761ba 4207 names_big[REGNO (operands[3])]);
8c440872
NS		 4208 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4209 output_asm_insn (info.shift2, operands);
b60761ba 4210 output_asm_insn ("add #0xff,%X3", operands);
8c440872
NS		 4211 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4212 if (n % 2)
4213 output_asm_insn (info.shift1, operands);
4214 }
4215 else
4216 {
4217 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
b60761ba 4218 names_big[REGNO (operands[3])]);
8c440872
NS		 4219 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4220 output_asm_insn (info.shift1, operands);
b60761ba 4221 output_asm_insn ("add #0xff,%X3", operands);
8c440872 4222 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
51c0c1d7 4223 }
8c440872
NS		 4224 return "";
4225
4226 default:
4227 gcc_unreachable ();
07aae5c2 4228 }
07aae5c2 4229}
86855e8c 4230
0a2aaacc 4231/* Count the number of assembly instructions in a string TEMPL. */
e9eba255 4232
86855e8c 4233static unsigned int
0a2aaacc 4234h8300_asm_insn_count (const char *templ)
86855e8c
KH		 4235{
4236 unsigned int count = 1;
4237
0a2aaacc
KG		 4238 for (; *templ; templ++)
4239 if (*templ == '\n')
86855e8c
KH		 4240 count++;
4241
4242 return count;
4243}
4244
e9eba255
KH		 4245/* Compute the length of a shift insn. */
4246
86855e8c 4247unsigned int
b60761ba 4248compute_a_shift_length (rtx operands[3], rtx_code code)
86855e8c 4249{
b60761ba 4250 enum machine_mode mode = GET_MODE (operands[0]);
86855e8c
KH		 4251 enum shift_type shift_type;
4252 enum shift_mode shift_mode;
4253 struct shift_info info;
4254 unsigned int wlength = 0;
4255
4256 switch (mode)
4257 {
4e10a5a7 4258 case E_QImode:
86855e8c
KH		 4259 shift_mode = QIshift;
4260 break;
4e10a5a7 4261 case E_HImode:
86855e8c
KH		 4262 shift_mode = HIshift;
4263 break;
4e10a5a7 4264 case E_SImode:
86855e8c
KH		 4265 shift_mode = SIshift;
4266 break;
4267 default:
8c440872 4268 gcc_unreachable ();
86855e8c
KH		 4269 }
4270
4271 switch (code)
4272 {
4273 case ASHIFTRT:
4274 shift_type = SHIFT_ASHIFTRT;
4275 break;
4276 case LSHIFTRT:
4277 shift_type = SHIFT_LSHIFTRT;
4278 break;
4279 case ASHIFT:
4280 shift_type = SHIFT_ASHIFT;
4281 break;
4282 default:
8c440872 4283 gcc_unreachable ();
86855e8c
KH		 4284 }
4285
4286 if (GET_CODE (operands[2]) != CONST_INT)
4287 {
4288 /* Get the assembler code to do one shift. */
4289 get_shift_alg (shift_type, shift_mode, 1, &info);
4290
4291 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
4292 }
4293 else
4294 {
4295 int n = INTVAL (operands[2]);
4296
4297 /* If the count is negative, make it 0. */
4298 if (n < 0)
4299 n = 0;
4300 /* If the count is too big, truncate it.
4301 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4302 do the intuitive thing. */
4303 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4304 n = GET_MODE_BITSIZE (mode);
4305
4306 get_shift_alg (shift_type, shift_mode, n, &info);
4307
4308 switch (info.alg)
4309 {
4310 case SHIFT_SPECIAL:
4311 wlength += h8300_asm_insn_count (info.special);
41c3eb5d
KH		 4312
4313 /* Every assembly instruction used in SHIFT_SPECIAL case
4314 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4315 see xor.l, we just pretend that xor.l counts as two insns
4316 so that the insn length will be computed correctly. */
4317 if (strstr (info.special, "xor.l") != NULL)
4318 wlength++;
4319
86855e8c
KH		 4320 /* Fall through. */
4321
4322 case SHIFT_INLINE:
4323 n = info.remainder;
4324
4325 if (info.shift2 != NULL)
4326 {
4327 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
4328 n = n % 2;
4329 }
4330
4331 wlength += h8300_asm_insn_count (info.shift1) * n;
6b148bd9 4332
86855e8c
KH		 4333 return 2 * wlength;
4334
4335 case SHIFT_ROT_AND:
4336 {
4337 int m = GET_MODE_BITSIZE (mode) - n;
4338
4339 /* Not all possibilities of rotate are supported. They shouldn't
4340 be generated, but let's watch for 'em. */
8c440872 4341 gcc_assert (info.shift1);
86855e8c
KH		 4342
4343 if (info.shift2 != NULL)
4344 {
4345 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
4346 m = m % 2;
4347 }
4348
4349 wlength += h8300_asm_insn_count (info.shift1) * m;
6b148bd9 4350
86855e8c
KH		 4351 /* Now mask off the high bits. */
4352 switch (mode)
4353 {
4e10a5a7 4354 case E_QImode:
86855e8c
KH		 4355 wlength += 1;
4356 break;
4e10a5a7 4357 case E_HImode:
86855e8c
KH		 4358 wlength += 2;
4359 break;
4e10a5a7 4360 case E_SImode:
86855e8c
KH		 4361 wlength += 3;
4362 break;
4363 default:
8c440872 4364 gcc_unreachable ();
86855e8c
KH		 4365 }
4366 return 2 * wlength;
4367 }
4368
4369 case SHIFT_LOOP:
4370 /* A loop to shift by a "large" constant value.
4371 If we have shift-by-2 insns, use them. */
4372 if (info.shift2 != NULL)
4373 {
4374 wlength += 3 + h8300_asm_insn_count (info.shift2);
4375 if (n % 2)
4376 wlength += h8300_asm_insn_count (info.shift1);
4377 }
4378 else
4379 {
4380 wlength += 3 + h8300_asm_insn_count (info.shift1);
4381 }
4382 return 2 * wlength;
4383
4384 default:
8c440872 4385 gcc_unreachable ();
86855e8c
KH		 4386 }
4387 }
4388}
45ca2106 4389
e9eba255
KH		 4390/* Compute which flag bits are valid after a shift insn. */
4391
f16897cb 4392int
7aa5fb17 4393compute_a_shift_cc (rtx operands[3], rtx_code code)
45ca2106 4394{
7aa5fb17 4395 machine_mode mode = GET_MODE (operands[0]);
45ca2106
KH		 4396 enum shift_type shift_type;
4397 enum shift_mode shift_mode;
4398 struct shift_info info;
8c440872
NS		 4399 int n;
4400
45ca2106
KH		 4401 switch (mode)
4402 {
4e10a5a7 4403 case E_QImode:
45ca2106
KH		 4404 shift_mode = QIshift;
4405 break;
4e10a5a7 4406 case E_HImode:
45ca2106
KH		 4407 shift_mode = HIshift;
4408 break;
4e10a5a7 4409 case E_SImode:
45ca2106
KH		 4410 shift_mode = SIshift;
4411 break;
4412 default:
8c440872 4413 gcc_unreachable ();
45ca2106
KH		 4414 }
4415
4416 switch (code)
4417 {
4418 case ASHIFTRT:
4419 shift_type = SHIFT_ASHIFTRT;
4420 break;
4421 case LSHIFTRT:
4422 shift_type = SHIFT_LSHIFTRT;
4423 break;
4424 case ASHIFT:
4425 shift_type = SHIFT_ASHIFT;
4426 break;
4427 default:
8c440872 4428 gcc_unreachable ();
45ca2106
KH		 4429 }
4430
8c440872
NS		 4431 /* This case must be taken care of by one of the two splitters
4432 that convert a variable shift into a loop. */
4433 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4434
4435 n = INTVAL (operands[2]);
4436
4437 /* If the count is negative, make it 0. */
4438 if (n < 0)
4439 n = 0;
4440 /* If the count is too big, truncate it.
4441 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4442 do the intuitive thing. */
4443 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4444 n = GET_MODE_BITSIZE (mode);
4445
4446 get_shift_alg (shift_type, shift_mode, n, &info);
4447
4448 switch (info.alg)
45ca2106 4449 {
8c440872
NS		 4450 case SHIFT_SPECIAL:
4451 if (info.remainder == 0)
7aa5fb17
JL		 4452 return (info.cc_special == OLD_CC_SET_ZN
4453 || info.cc_special == OLD_CC_SET_ZNV);
45ca2106 4454
8c440872 4455 /* Fall through. */
45ca2106 4456
8c440872 4457 case SHIFT_INLINE:
7aa5fb17
JL		 4458 return (info.cc_inline == OLD_CC_SET_ZN
4459 || info.cc_inline == OLD_CC_SET_ZNV);
8c440872
NS		 4460
4461 case SHIFT_ROT_AND:
4462 /* This case always ends with an and instruction. */
7aa5fb17 4463 return true;
8c440872
NS		 4464
4465 case SHIFT_LOOP:
4466 /* A loop to shift by a "large" constant value.
4467 If we have shift-by-2 insns, use them. */
4468 if (info.shift2 != NULL)
45ca2106 4469 {
8c440872 4470 if (n % 2)
7aa5fb17
JL		 4471 return (info.cc_inline == OLD_CC_SET_ZN
4472 || info.cc_inline == OLD_CC_SET_ZNV);
4473
45ca2106 4474 }
7aa5fb17 4475 return false;
8c440872
NS		 4476
4477 default:
4478 gcc_unreachable ();
45ca2106
KH		 4479 }
4480}
48837e29 4481\f
edd71f0f
KH		 4482/* A rotation by a non-constant will cause a loop to be generated, in
4483 which a rotation by one bit is used. A rotation by a constant,
4484 including the one in the loop, will be taken care of by
caf7f21a 4485 output_a_rotate () at the insn emit time. */
edd71f0f
KH		 4486
4487int
3d2e90d6 4488expand_a_rotate (rtx operands[])
edd71f0f
KH		 4489{
4490 rtx dst = operands[0];
4491 rtx src = operands[1];
4492 rtx rotate_amount = operands[2];
ef4bddc2 4493 machine_mode mode = GET_MODE (dst);
edd71f0f 4494
beed8fc0
AO		 4495 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
4496 return false;
4497
edd71f0f
KH		 4498 /* We rotate in place. */
4499 emit_move_insn (dst, src);
4500
4501 if (GET_CODE (rotate_amount) != CONST_INT)
4502 {
4503 rtx counter = gen_reg_rtx (QImode);
19f8b229
TS		 4504 rtx_code_label *start_label = gen_label_rtx ();
4505 rtx_code_label *end_label = gen_label_rtx ();
edd71f0f
KH		 4506
4507 /* If the rotate amount is less than or equal to 0,
4508 we go out of the loop. */
a556fd39 4509 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
d43e0b7d 4510 QImode, 0, end_label);
edd71f0f
KH		 4511
4512 /* Initialize the loop counter. */
4513 emit_move_insn (counter, rotate_amount);
4514
4515 emit_label (start_label);
4516
4517 /* Rotate by one bit. */
01ab5574
KH		 4518 switch (mode)
4519 {
4e10a5a7 4520 case E_QImode:
01ab5574
KH		 4521 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
4522 break;
4e10a5a7 4523 case E_HImode:
01ab5574
KH		 4524 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
4525 break;
4e10a5a7 4526 case E_SImode:
01ab5574
KH		 4527 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
4528 break;
4529 default:
8c440872 4530 gcc_unreachable ();
01ab5574 4531 }
edd71f0f
KH		 4532
4533 /* Decrement the counter by 1. */
01ab5574 4534 emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
edd71f0f 4535
9cd10576 4536 /* If the loop counter is nonzero, we go back to the beginning
edd71f0f 4537 of the loop. */
a556fd39 4538 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
d43e0b7d 4539 start_label);
edd71f0f
KH		 4540
4541 emit_label (end_label);
4542 }
4543 else
4544 {
4545 /* Rotate by AMOUNT bits. */
01ab5574
KH		 4546 switch (mode)
4547 {
4e10a5a7 4548 case E_QImode:
01ab5574
KH		 4549 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
4550 break;
4e10a5a7 4551 case E_HImode:
01ab5574
KH		 4552 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
4553 break;
4e10a5a7 4554 case E_SImode:
01ab5574
KH		 4555 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
4556 break;
4557 default:
8c440872 4558 gcc_unreachable ();
01ab5574 4559 }
edd71f0f
KH		 4560 }
4561
4562 return 1;
4563}
4564
e9eba255 4565/* Output a rotate insn. */
edd71f0f
KH		 4566
4567const char *
caf7f21a 4568output_a_rotate (enum rtx_code code, rtx *operands)
edd71f0f
KH		 4569{
4570 rtx dst = operands[0];
4571 rtx rotate_amount = operands[2];
4572 enum shift_mode rotate_mode;
4573 enum shift_type rotate_type;
4574 const char *insn_buf;
4575 int bits;
4576 int amount;
ef4bddc2 4577 machine_mode mode = GET_MODE (dst);
edd71f0f 4578
8c440872 4579 gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
edd71f0f
KH		 4580
4581 switch (mode)
4582 {
4e10a5a7 4583 case E_QImode:
edd71f0f
KH		 4584 rotate_mode = QIshift;
4585 break;
4e10a5a7 4586 case E_HImode:
edd71f0f
KH		 4587 rotate_mode = HIshift;
4588 break;
4e10a5a7 4589 case E_SImode:
edd71f0f
KH		 4590 rotate_mode = SIshift;
4591 break;
4592 default:
8c440872 4593 gcc_unreachable ();
edd71f0f
KH		 4594 }
4595
4596 switch (code)
4597 {
4598 case ROTATERT:
4599 rotate_type = SHIFT_ASHIFT;
4600 break;
4601 case ROTATE:
4602 rotate_type = SHIFT_LSHIFTRT;
4603 break;
4604 default:
8c440872 4605 gcc_unreachable ();
edd71f0f
KH		 4606 }
4607
4608 amount = INTVAL (rotate_amount);
4609
4610 /* Clean up AMOUNT. */
4611 if (amount < 0)
4612 amount = 0;
4613 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4614 amount = GET_MODE_BITSIZE (mode);
4615
4616 /* Determine the faster direction. After this phase, amount will be
4617 at most a half of GET_MODE_BITSIZE (mode). */
e0c32c62 4618 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
edd71f0f
KH		 4619 {
4620 /* Flip the direction. */
4621 amount = GET_MODE_BITSIZE (mode) - amount;
4622 rotate_type =
4623 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
4624 }
4625
4626 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4627 boost up the rotation. */
27c1afd5 4628 if ((mode == HImode && TARGET_H8300H && amount >= 6)
edd71f0f
KH		 4629 || (mode == HImode && TARGET_H8300S && amount == 8)
4630 || (mode == SImode && TARGET_H8300H && amount >= 10)
4631 || (mode == SImode && TARGET_H8300S && amount >= 13))
4632 {
4633 switch (mode)
4634 {
4e10a5a7 4635 case E_HImode:
edd71f0f
KH		 4636 /* This code works on any family. */
4637 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
4638 output_asm_insn (insn_buf, operands);
4639 break;
4640
4e10a5a7 4641 case E_SImode:
3db11b5c 4642 /* This code works on the H8/300H and H8S. */
edd71f0f
KH		 4643 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
4644 output_asm_insn (insn_buf, operands);
4645 break;
4646
4647 default:
8c440872 4648 gcc_unreachable ();
edd71f0f
KH		 4649 }
4650
4651 /* Adjust AMOUNT and flip the direction. */
4652 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4653 rotate_type =
4654 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
4655 }
4656
01ab5574 4657 /* Output rotate insns. */
edd71f0f
KH		 4658 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
4659 {
4660 if (bits == 2)
4661 insn_buf = rotate_two[rotate_type][rotate_mode];
4662 else
4663 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
2c54abce 4664
edd71f0f
KH		 4665 for (; amount >= bits; amount -= bits)
4666 output_asm_insn (insn_buf, operands);
4667 }
4668
4669 return "";
4670}
caf7f21a 4671
e9eba255
KH		 4672/* Compute the length of a rotate insn. */
4673
caf7f21a
KH		 4674unsigned int
4675compute_a_rotate_length (rtx *operands)
4676{
4677 rtx src = operands[1];
343fd2c7 4678 rtx amount_rtx = operands[2];
ef4bddc2 4679 machine_mode mode = GET_MODE (src);
caf7f21a
KH		 4680 int amount;
4681 unsigned int length = 0;
4682
8c440872 4683 gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
caf7f21a 4684
343fd2c7 4685 amount = INTVAL (amount_rtx);
caf7f21a
KH		 4686
4687 /* Clean up AMOUNT. */
4688 if (amount < 0)
4689 amount = 0;
4690 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4691 amount = GET_MODE_BITSIZE (mode);
4692
4693 /* Determine the faster direction. After this phase, amount
4694 will be at most a half of GET_MODE_BITSIZE (mode). */
4695 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4696 /* Flip the direction. */
4697 amount = GET_MODE_BITSIZE (mode) - amount;
4698
4699 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4700 boost up the rotation. */
27c1afd5 4701 if ((mode == HImode && TARGET_H8300H && amount >= 6)
caf7f21a
KH		 4702 || (mode == HImode && TARGET_H8300S && amount == 8)
4703 || (mode == SImode && TARGET_H8300H && amount >= 10)
4704 || (mode == SImode && TARGET_H8300S && amount >= 13))
4705 {
4706 /* Adjust AMOUNT and flip the direction. */
4707 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4708 length += 6;
4709 }
4710
4711 /* We use 2-bit rotations on the H8S. */
4712 if (TARGET_H8300S)
4713 amount = amount / 2 + amount % 2;
4714
4715 /* The H8/300 uses three insns to rotate one bit, taking 6
4716 length. */
27c1afd5 4717 length += amount * 2;
caf7f21a
KH		 4718
4719 return length;
4720}
edd71f0f 4721\f
48837e29 4722/* Fix the operands of a gen_xxx so that it could become a bit
2c54abce 4723 operating insn. */
07aae5c2
SC		 4724
4725int
4093985c 4726fix_bit_operand (rtx *operands, enum rtx_code code)
07aae5c2 4727{
abc95ed3 4728 /* The bit_operand predicate accepts any memory during RTL generation, but
48837e29
DE		 4729 only 'U' memory afterwards, so if this is a MEM operand, we must force
4730 it to be valid for 'U' by reloading the address. */
07aae5c2 4731
4093985c
KH		 4732 if (code == AND
4733 ? single_zero_operand (operands[2], QImode)
4734 : single_one_operand (operands[2], QImode))
07aae5c2 4735 {
2e760b15
KH		 4736 /* OK to have a memory dest. */
4737 if (GET_CODE (operands[0]) == MEM
ceaaaeab 4738 && !satisfies_constraint_U (operands[0]))
48837e29 4739 {
2e760b15
KH		 4740 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
4741 copy_to_mode_reg (Pmode,
4742 XEXP (operands[0], 0)));
4743 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4744 operands[0] = mem;
4745 }
48837e29 4746
2e760b15 4747 if (GET_CODE (operands[1]) == MEM
ceaaaeab 4748 && !satisfies_constraint_U (operands[1]))
2e760b15
KH		 4749 {
4750 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
4751 copy_to_mode_reg (Pmode,
4752 XEXP (operands[1], 0)));
4753 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4754 operands[1] = mem;
48837e29 4755 }
2e760b15 4756 return 0;
48837e29 4757 }
07aae5c2 4758
48837e29 4759 /* Dest and src op must be register. */
07aae5c2 4760
48837e29
DE		 4761 operands[1] = force_reg (QImode, operands[1]);
4762 {
4763 rtx res = gen_reg_rtx (QImode);
fd57a6e4 4764 switch (code)
a3579575
KH		 4765 {
4766 case AND:
4767 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
4768 break;
4769 case IOR:
4770 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
4771 break;
4772 case XOR:
4773 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
4774 break;
4775 default:
8c440872 4776 gcc_unreachable ();
a3579575
KH		 4777 }
4778 emit_insn (gen_movqi (operands[0], res));
48837e29
DE		 4779 }
4780 return 1;
07aae5c2 4781}
f5b65a56 4782
f5b65a56
JL		 4783/* Return nonzero if FUNC is an interrupt function as specified
4784 by the "interrupt" attribute. */
4785
4786static int
cb713a8d 4787h8300_interrupt_function_p (tree func)
f5b65a56
JL		 4788{
4789 tree a;
4790
4791 if (TREE_CODE (func) != FUNCTION_DECL)
4792 return 0;
4793
91d231cb 4794 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
f5b65a56
JL		 4795 return a != NULL_TREE;
4796}
4797
3cfa3702
KH		 4798/* Return nonzero if FUNC is a saveall function as specified by the
4799 "saveall" attribute. */
4800
4801static int
4802h8300_saveall_function_p (tree func)
4803{
4804 tree a;
4805
4806 if (TREE_CODE (func) != FUNCTION_DECL)
4807 return 0;
4808
4809 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
4810 return a != NULL_TREE;
4811}
4812
fabe72bb
JL		 4813/* Return nonzero if FUNC is an OS_Task function as specified
4814 by the "OS_Task" attribute. */
4815
4816static int
cb713a8d 4817h8300_os_task_function_p (tree func)
fabe72bb
JL		 4818{
4819 tree a;
4820
4821 if (TREE_CODE (func) != FUNCTION_DECL)
4822 return 0;
4823
91d231cb 4824 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
fabe72bb
JL		 4825 return a != NULL_TREE;
4826}
4827
4828/* Return nonzero if FUNC is a monitor function as specified
4829 by the "monitor" attribute. */
4830
4831static int
cb713a8d 4832h8300_monitor_function_p (tree func)
fabe72bb
JL		 4833{
4834 tree a;
4835
4836 if (TREE_CODE (func) != FUNCTION_DECL)
4837 return 0;
4838
91d231cb 4839 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
fabe72bb
JL		 4840 return a != NULL_TREE;
4841}
4842
f5b65a56
JL		 4843/* Return nonzero if FUNC is a function that should be called
4844 through the function vector. */
4845
4846int
cb713a8d 4847h8300_funcvec_function_p (tree func)
f5b65a56
JL		 4848{
4849 tree a;
4850
4851 if (TREE_CODE (func) != FUNCTION_DECL)
4852 return 0;
4853
91d231cb 4854 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
f5b65a56
JL		 4855 return a != NULL_TREE;
4856}
4857
887a8bd9 4858/* Return nonzero if DECL is a variable that's in the eight bit
15dc331e
JL		 4859 data area. */
4860
4861int
cb713a8d 4862h8300_eightbit_data_p (tree decl)
15dc331e
JL		 4863{
4864 tree a;
4865
4866 if (TREE_CODE (decl) != VAR_DECL)
4867 return 0;
4868
91d231cb 4869 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
15dc331e
JL		 4870 return a != NULL_TREE;
4871}
4872
887a8bd9
JL		 4873/* Return nonzero if DECL is a variable that's in the tiny
4874 data area. */
4875
4876int
cb713a8d 4877h8300_tiny_data_p (tree decl)
887a8bd9
JL		 4878{
4879 tree a;
4880
4881 if (TREE_CODE (decl) != VAR_DECL)
4882 return 0;
4883
91d231cb 4884 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
887a8bd9
JL		 4885 return a != NULL_TREE;
4886}
4887
3cfa3702
KH		 4888/* Generate an 'interrupt_handler' attribute for decls. We convert
4889 all the pragmas to corresponding attributes. */
2c1d2fcb
DD		 4890
4891static void
cb713a8d 4892h8300_insert_attributes (tree node, tree *attributes)
2c1d2fcb 4893{
3cfa3702
KH		 4894 if (TREE_CODE (node) == FUNCTION_DECL)
4895 {
4896 if (pragma_interrupt)
4897 {
4898 pragma_interrupt = 0;
2c1d2fcb 4899
3cfa3702
KH		 4900 /* Add an 'interrupt_handler' attribute. */
4901 *attributes = tree_cons (get_identifier ("interrupt_handler"),
4902 NULL, *attributes);
4903 }
e392d367 4904
3cfa3702
KH		 4905 if (pragma_saveall)
4906 {
4907 pragma_saveall = 0;
4908
4909 /* Add an 'saveall' attribute. */
4910 *attributes = tree_cons (get_identifier ("saveall"),
4911 NULL, *attributes);
4912 }
4913 }
2c1d2fcb
DD		 4914}
4915
91d231cb 4916/* Supported attributes:
f5b65a56 4917
97c5ec1d 4918 interrupt_handler: output a prologue and epilogue suitable for an
f5b65a56
JL		 4919 interrupt handler.
4920
3cfa3702
KH		 4921 saveall: output a prologue and epilogue that saves and restores
4922 all registers except the stack pointer.
4923
97c5ec1d 4924 function_vector: This function should be called through the
887a8bd9
JL		 4925 function vector.
4926
4927 eightbit_data: This variable lives in the 8-bit data area and can
4928 be referenced with 8-bit absolute memory addresses.
4929
4930 tiny_data: This variable lives in the tiny data area and can be
4931 referenced with 16-bit absolute memory references. */
f5b65a56 4932
6bc7bc14 4933static const struct attribute_spec h8300_attribute_table[] =
f5b65a56 4934{
4849deb1
JJ		 4935 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
4936 affects_type_identity, handler, exclude } */
4937 { "interrupt_handler", 0, 0, true, false, false, false,
4938 h8300_handle_fndecl_attribute, NULL },
4939 { "saveall", 0, 0, true, false, false, false,
4940 h8300_handle_fndecl_attribute, NULL },
4941 { "OS_Task", 0, 0, true, false, false, false,
4942 h8300_handle_fndecl_attribute, NULL },
4943 { "monitor", 0, 0, true, false, false, false,
4944 h8300_handle_fndecl_attribute, NULL },
4945 { "function_vector", 0, 0, true, false, false, false,
4946 h8300_handle_fndecl_attribute, NULL },
4947 { "eightbit_data", 0, 0, true, false, false, false,
4948 h8300_handle_eightbit_data_attribute, NULL },
4949 { "tiny_data", 0, 0, true, false, false, false,
4950 h8300_handle_tiny_data_attribute, NULL },
4951 { NULL, 0, 0, false, false, false, false, NULL, NULL }
91d231cb 4952};
f5b65a56 4953
15dc331e 4954
91d231cb
JM		 4955/* Handle an attribute requiring a FUNCTION_DECL; arguments as in
4956 struct attribute_spec.handler. */
4957static tree
cb713a8d
KH		 4958h8300_handle_fndecl_attribute (tree *node, tree name,
4959 tree args ATTRIBUTE_UNUSED,
4960 int flags ATTRIBUTE_UNUSED,
4961 bool *no_add_attrs)
91d231cb
JM		 4962{
4963 if (TREE_CODE (*node) != FUNCTION_DECL)
4964 {
29d08eba
JM		 4965 warning (OPT_Wattributes, "%qE attribute only applies to functions",
4966 name);
91d231cb
JM		 4967 *no_add_attrs = true;
4968 }
4969
4970 return NULL_TREE;
4971}
4972
4973/* Handle an "eightbit_data" attribute; arguments as in
4974 struct attribute_spec.handler. */
4975static tree
cb713a8d
KH		 4976h8300_handle_eightbit_data_attribute (tree *node, tree name,
4977 tree args ATTRIBUTE_UNUSED,
4978 int flags ATTRIBUTE_UNUSED,
4979 bool *no_add_attrs)
91d231cb
JM		 4980{
4981 tree decl = *node;
4982
4983 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
15dc331e 4984 {
f961457f 4985 set_decl_section_name (decl, ".eight");
91d231cb
JM		 4986 }
4987 else
4988 {
29d08eba
JM		 4989 warning (OPT_Wattributes, "%qE attribute ignored",
4990 name);
91d231cb 4991 *no_add_attrs = true;
887a8bd9
JL		 4992 }
4993
91d231cb
JM		 4994 return NULL_TREE;
4995}
4996
4997/* Handle an "tiny_data" attribute; arguments as in
4998 struct attribute_spec.handler. */
4999static tree
cb713a8d
KH		 5000h8300_handle_tiny_data_attribute (tree *node, tree name,
5001 tree args ATTRIBUTE_UNUSED,
5002 int flags ATTRIBUTE_UNUSED,
5003 bool *no_add_attrs)
91d231cb
JM		 5004{
5005 tree decl = *node;
5006
5007 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
887a8bd9 5008 {
f961457f 5009 set_decl_section_name (decl, ".tiny");
91d231cb
JM		 5010 }
5011 else
5012 {
29d08eba
JM		 5013 warning (OPT_Wattributes, "%qE attribute ignored",
5014 name);
91d231cb 5015 *no_add_attrs = true;
15dc331e 5016 }
07e4d94e 5017
91d231cb 5018 return NULL_TREE;
f5b65a56
JL		 5019}
5020
dc66a1c4 5021/* Mark function vectors, and various small data objects. */
fb49053f
RH		 5022
5023static void
cb713a8d 5024h8300_encode_section_info (tree decl, rtx rtl, int first)
fb49053f 5025{
dc66a1c4
RH		 5026 int extra_flags = 0;
5027
c6a2438a 5028 default_encode_section_info (decl, rtl, first);
dc66a1c4 5029
fb49053f
RH		 5030 if (TREE_CODE (decl) == FUNCTION_DECL
5031 && h8300_funcvec_function_p (decl))
dc66a1c4 5032 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
fb49053f
RH		 5033 else if (TREE_CODE (decl) == VAR_DECL
5034 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
5035 {
5036 if (h8300_eightbit_data_p (decl))
dc66a1c4 5037 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
fb49053f 5038 else if (first && h8300_tiny_data_p (decl))
dc66a1c4 5039 extra_flags = SYMBOL_FLAG_TINY_DATA;
fb49053f 5040 }
772c5265 5041
dc66a1c4 5042 if (extra_flags)
c6a2438a 5043 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
772c5265
RH		 5044}
5045
e9eba255
KH		 5046/* Output a single-bit extraction. */
5047
441d04c6 5048const char *
cb713a8d 5049output_simode_bld (int bild, rtx operands[])
bd93f126 5050{
27c1afd5
JL		 5051 /* Determine if we can clear the destination first. */
5052 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
5053 && REGNO (operands[0]) != REGNO (operands[1]));
6be580c7 5054
27c1afd5
JL		 5055 if (clear_first)
5056 output_asm_insn ("sub.l\t%S0,%S0", operands);
bd93f126 5057
27c1afd5
JL		 5058 /* Output the bit load or bit inverse load. */
5059 if (bild)
5060 output_asm_insn ("bild\t%Z2,%Y1", operands);
bd93f126 5061 else
27c1afd5 5062 output_asm_insn ("bld\t%Z2,%Y1", operands);
0eb933a0 5063
27c1afd5
JL		 5064 if (!clear_first)
5065 output_asm_insn ("xor.l\t%S0,%S0", operands);
0eb933a0 5066
27c1afd5
JL		 5067 /* Perform the bit store. */
5068 output_asm_insn ("rotxl.l\t%S0", operands);
bd93f126
JL		 5069
5070 /* All done. */
5071 return "";
5072}
e6219736 5073
beed8fc0
AO		 5074/* Delayed-branch scheduling is more effective if we have some idea
5075 how long each instruction will be. Use a shorten_branches pass
5076 to get an initial estimate. */
5077
5078static void
5079h8300_reorg (void)
5080{
5081 if (flag_delayed_branch)
5082 shorten_branches (get_insns ());
5083}
5084
7c143ed2
KH		 5085/* Nonzero if X is a constant address suitable as an 8-bit absolute,
5086 which is a special case of the 'R' operand. */
5087
803d56f5 5088int
cb713a8d 5089h8300_eightbit_constant_address_p (rtx x)
803d56f5 5090{
ff482c8d 5091 /* The ranges of the 8-bit area. */
d2d199a3
KH		 5092 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
5093 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
803d56f5
KH		 5094 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
5095 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
5096 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
5097 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
5098
5099 unsigned HOST_WIDE_INT addr;
5100
9675a91e 5101 /* We accept symbols declared with eightbit_data. */
dc66a1c4
RH		 5102 if (GET_CODE (x) == SYMBOL_REF)
5103 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
9675a91e 5104
9f9ab303
JL		 5105 if (GET_CODE (x) == CONST
5106 && GET_CODE (XEXP (x, 0)) == PLUS
5107 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
5108 && (SYMBOL_REF_FLAGS (XEXP (XEXP (x, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0)
5109 return 1;
5110
803d56f5
KH		 5111 if (GET_CODE (x) != CONST_INT)
5112 return 0;
5113
5114 addr = INTVAL (x);
5115
5116 return (0
27c1afd5 5117 || (TARGET_NORMAL_MODE && IN_RANGE (addr, n1, n2))
803d56f5
KH		 5118 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
5119 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
5120}
5121
7c143ed2
KH		 5122/* Nonzero if X is a constant address suitable as an 16-bit absolute
5123 on H8/300H and H8S. */
5124
803d56f5 5125int
cb713a8d 5126h8300_tiny_constant_address_p (rtx x)
803d56f5 5127{
3f7211f1 5128 /* The ranges of the 16-bit area. */
803d56f5
KH		 5129 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
5130 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
5131 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
5132 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
5133 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
5134 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
5135 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
5136 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
5137
5138 unsigned HOST_WIDE_INT addr;
5139
d6456562
KH		 5140 switch (GET_CODE (x))
5141 {
5142 case SYMBOL_REF:
a4bb41cc
KH		 5143 /* In the normal mode, any symbol fits in the 16-bit absolute
5144 address range. We also accept symbols declared with
5145 tiny_data. */
5146 return (TARGET_NORMAL_MODE
5147 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
56b8e164 5148
d6456562
KH		 5149 case CONST_INT:
5150 addr = INTVAL (x);
5151 return (TARGET_NORMAL_MODE
5152 || (TARGET_H8300H
5153 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
5154 || (TARGET_H8300S
5155 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
803d56f5 5156
a4bb41cc
KH		 5157 case CONST:
5158 return TARGET_NORMAL_MODE;
5159
d6456562
KH		 5160 default:
5161 return 0;
5162 }
803d56f5 5163
803d56f5 5164}
9b98dc74 5165
e9eba255
KH		 5166/* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5167 locations that can be accessed as a 16-bit word. */
5168
9b98dc74 5169int
cb713a8d 5170byte_accesses_mergeable_p (rtx addr1, rtx addr2)
9b98dc74
KH		 5171{
5172 HOST_WIDE_INT offset1, offset2;
5173 rtx reg1, reg2;
5174
5175 if (REG_P (addr1))
5176 {
5177 reg1 = addr1;
5178 offset1 = 0;
5179 }
5180 else if (GET_CODE (addr1) == PLUS
5181 && REG_P (XEXP (addr1, 0))
5182 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
5183 {
5184 reg1 = XEXP (addr1, 0);
5185 offset1 = INTVAL (XEXP (addr1, 1));
5186 }
5187 else
5188 return 0;
5189
5190 if (REG_P (addr2))
5191 {
5192 reg2 = addr2;
5193 offset2 = 0;
5194 }
5195 else if (GET_CODE (addr2) == PLUS
5196 && REG_P (XEXP (addr2, 0))
5197 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
5198 {
5199 reg2 = XEXP (addr2, 0);
5200 offset2 = INTVAL (XEXP (addr2, 1));
5201 }
5202 else
5203 return 0;
5204
5205 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
5206 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
5207 && offset1 % 2 == 0
5208 && offset1 + 1 == offset2)
5209 return 1;
5210
5211 return 0;
5212}
02529902
KH		 5213
5214/* Return nonzero if we have the same comparison insn as I3 two insns
19cff4db 5215 before I3. I3 is assumed to be a comparison insn. */
02529902
KH		 5216
5217int
82082f65 5218same_cmp_preceding_p (rtx_insn *i3)
02529902 5219{
68a1a6c0 5220 rtx_insn *i1, *i2;
02529902
KH		 5221
5222 /* Make sure we have a sequence of three insns. */
5223 i2 = prev_nonnote_insn (i3);
68a1a6c0 5224 if (i2 == NULL)
02529902
KH		 5225 return 0;
5226 i1 = prev_nonnote_insn (i2);
68a1a6c0 5227 if (i1 == NULL)
02529902
KH		 5228 return 0;
5229
5230 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5231 && any_condjump_p (i2) && onlyjump_p (i2));
5232}
c87ec0ba 5233
c06d5c85
KH		 5234/* Return nonzero if we have the same comparison insn as I1 two insns
5235 after I1. I1 is assumed to be a comparison insn. */
5236
5237int
82082f65 5238same_cmp_following_p (rtx_insn *i1)
c06d5c85 5239{
68a1a6c0 5240 rtx_insn *i2, *i3;
c06d5c85
KH		 5241
5242 /* Make sure we have a sequence of three insns. */
5243 i2 = next_nonnote_insn (i1);
68a1a6c0 5244 if (i2 == NULL)
c06d5c85
KH		 5245 return 0;
5246 i3 = next_nonnote_insn (i2);
68a1a6c0 5247 if (i3 == NULL)
c06d5c85
KH		 5248 return 0;
5249
5250 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5251 && any_condjump_p (i2) && onlyjump_p (i2));
5252}
5253
a466bea3 5254/* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
1ae58c30 5255 (or pops) N registers. OPERANDS are assumed to be an array of
a466bea3
KH		 5256 registers. */
5257
5258int
5259h8300_regs_ok_for_stm (int n, rtx operands[])
5260{
5261 switch (n)
5262 {
5263 case 2:
5264 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
5265 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
5266 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
5267 case 3:
5268 return ((REGNO (operands[0]) == 0
5269 && REGNO (operands[1]) == 1
5270 && REGNO (operands[2]) == 2)
5271 || (REGNO (operands[0]) == 4
5272 && REGNO (operands[1]) == 5
5273 && REGNO (operands[2]) == 6));
5274
5275 case 4:
5276 return (REGNO (operands[0]) == 0
5277 && REGNO (operands[1]) == 1
5278 && REGNO (operands[2]) == 2
5279 && REGNO (operands[3]) == 3);
8c440872
NS		 5280 default:
5281 gcc_unreachable ();
a466bea3 5282 }
a466bea3
KH		 5283}
5284
c87ec0ba
NY		 5285/* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5286
5287int
5288h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5289 unsigned int new_reg)
5290{
5291 /* Interrupt functions can only use registers that have already been
5292 saved by the prologue, even if they would normally be
5293 call-clobbered. */
5294
5295 if (h8300_current_function_interrupt_function_p ()
6fb5fa3c 5296 && !df_regs_ever_live_p (new_reg))
c87ec0ba
NY		 5297 return 0;
5298
80e58519 5299 return 1;
c87ec0ba 5300}
d0022200 5301
2e762884
DD		 5302/* Returns true if register REGNO is safe to be allocated as a scratch
5303 register in the current function. */
5304
5305static bool
5306h8300_hard_regno_scratch_ok (unsigned int regno)
5307{
5308 if (h8300_current_function_interrupt_function_p ()
5309 && ! WORD_REG_USED (regno))
5310 return false;
5311
5312 return true;
5313}
5314
5315
d0022200
KH		 5316/* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5317
5318static int
5319h8300_rtx_ok_for_base_p (rtx x, int strict)
5320{
5321 /* Strip off SUBREG if any. */
5322 if (GET_CODE (x) == SUBREG)
5323 x = SUBREG_REG (x);
5324
5325 return (REG_P (x)
5326 && (strict
5327 ? REG_OK_FOR_BASE_STRICT_P (x)
5328 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
5329}
5330
5331/* Return nozero if X is a legitimate address. On the H8/300, a
5332 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5333 CONSTANT_ADDRESS. */
5334
c6c3dba9 5335static bool
ef4bddc2 5336h8300_legitimate_address_p (machine_mode mode, rtx x, bool strict)
d0022200
KH		 5337{
5338 /* The register indirect addresses like @er0 is always valid. */
5339 if (h8300_rtx_ok_for_base_p (x, strict))
5340 return 1;
5341
5342 if (CONSTANT_ADDRESS_P (x))
5343 return 1;
5344
beed8fc0
AO		 5345 if (TARGET_H8300SX
5346 && ( GET_CODE (x) == PRE_INC
5347 || GET_CODE (x) == PRE_DEC
5348 || GET_CODE (x) == POST_INC
5349 || GET_CODE (x) == POST_DEC)
5350 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
5351 return 1;
5352
d0022200
KH		 5353 if (GET_CODE (x) == PLUS
5354 && CONSTANT_ADDRESS_P (XEXP (x, 1))
beed8fc0
AO		 5355 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
5356 mode, 0), strict))
d0022200
KH		 5357 return 1;
5358
5359 return 0;
5360}
07ee3b58 5361
f939c3e6 5362/* Implement TARGET_HARD_REGNO_MODE_OK. */
07ee3b58 5363
f939c3e6
RS		 5364static bool
5365h8300_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
07ee3b58 5366{
27c1afd5
JL		 5367 /* MAC register can only be of SImode. Otherwise, anything
5368 goes. */
5369 return regno == MAC_REG ? mode == SImode : 1;
07ee3b58 5370}
f9b4f8c1 5371
99e1629f
RS		 5372/* Implement TARGET_MODES_TIEABLE_P. */
5373
5374static bool
5375h8300_modes_tieable_p (machine_mode mode1, machine_mode mode2)
5376{
5377 return (mode1 == mode2
5378 || ((mode1 == QImode
5379 || mode1 == HImode
27c1afd5 5380 || mode1 == SImode)
99e1629f
RS		 5381 && (mode2 == QImode
5382 || mode2 == HImode
27c1afd5 5383 || mode2 == SImode)));
99e1629f
RS		 5384}
5385
f9b4f8c1
RH		 5386/* Helper function for the move patterns. Make sure a move is legitimate. */
5387
5388bool
5389h8300_move_ok (rtx dest, rtx src)
5390{
5391 rtx addr, other;
5392
5393 /* Validate that at least one operand is a register. */
5394 if (MEM_P (dest))
5395 {
5396 if (MEM_P (src) || CONSTANT_P (src))
5397 return false;
5398 addr = XEXP (dest, 0);
5399 other = src;
5400 }
5401 else if (MEM_P (src))
5402 {
5403 addr = XEXP (src, 0);
5404 other = dest;
5405 }
5406 else
5407 return true;
5408
5409 /* Validate that auto-inc doesn't affect OTHER. */
5410 if (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC)
5411 return true;
5412 addr = XEXP (addr, 0);
5413
5414 if (addr == stack_pointer_rtx)
5415 return register_no_sp_elim_operand (other, VOIDmode);
5416 else
5417 return !reg_overlap_mentioned_p(other, addr);
5418}
6e014ef3 5419\f
c15c90bb
ZW		 5420/* Perform target dependent optabs initialization. */
5421static void
5422h8300_init_libfuncs (void)
5423{
5424 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
5425 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
5426 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
5427 set_optab_libfunc (smod_optab, HImode, "__modhi3");
5428 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
5429}
5430\f
9eaa7740
AS		 5431/* Worker function for TARGET_FUNCTION_VALUE.
5432
5433 On the H8 the return value is in R0/R1. */
5434
5435static rtx
5436h8300_function_value (const_tree ret_type,
5437 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
5438 bool outgoing ATTRIBUTE_UNUSED)
5439{
5440 return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG);
5441}
5442
5443/* Worker function for TARGET_LIBCALL_VALUE.
5444
5445 On the H8 the return value is in R0/R1. */
5446
5447static rtx
ef4bddc2 5448h8300_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
9eaa7740
AS		 5449{
5450 return gen_rtx_REG (mode, R0_REG);
5451}
5452
5453/* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5454
5455 On the H8, R0 is the only register thus used. */
5456
5457static bool
5458h8300_function_value_regno_p (const unsigned int regno)
5459{
5460 return (regno == R0_REG);
5461}
5462
e9eba255
KH		 5463/* Worker function for TARGET_RETURN_IN_MEMORY. */
5464
34bf1fe3 5465static bool
586de218 5466h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
34bf1fe3
KH		 5467{
5468 return (TYPE_MODE (type) == BLKmode
27c1afd5 5469 || GET_MODE_SIZE (TYPE_MODE (type)) > 8);
34bf1fe3
KH		 5470}
5471\f
9f6ef043
RH		 5472/* We emit the entire trampoline here. Depending on the pointer size,
5473 we use a different trampoline.
5474
5475 Pmode == HImode
5476 vvvv context
5477 1 0000 7903xxxx mov.w #0x1234,r3
5478 2 0004 5A00xxxx jmp @0x1234
5479 ^^^^ function
5480
5481 Pmode == SImode
5482 vvvvvvvv context
5483 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
5484 3 0006 5Axxxxxx jmp @0x123456
5485 ^^^^^^ function
5486*/
5487
5488static void
5489h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
5490{
5491 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
5492 rtx mem;
5493
5494 if (Pmode == HImode)
5495 {
5496 mem = adjust_address (m_tramp, HImode, 0);
5497 emit_move_insn (mem, GEN_INT (0x7903));
5498 mem = adjust_address (m_tramp, Pmode, 2);
5499 emit_move_insn (mem, cxt);
5500 mem = adjust_address (m_tramp, HImode, 4);
5501 emit_move_insn (mem, GEN_INT (0x5a00));
5502 mem = adjust_address (m_tramp, Pmode, 6);
5503 emit_move_insn (mem, fnaddr);
5504 }
5505 else
5506 {
5507 rtx tem;
5508
5509 mem = adjust_address (m_tramp, HImode, 0);
5510 emit_move_insn (mem, GEN_INT (0x7a03));
5511 mem = adjust_address (m_tramp, Pmode, 2);
5512 emit_move_insn (mem, cxt);
5513
5514 tem = copy_to_reg (fnaddr);
5515 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff)));
5516 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000)));
5517 mem = adjust_address (m_tramp, SImode, 6);
5518 emit_move_insn (mem, tem);
5519 }
5520}
7b4df2bf
RS		 5521
5522/* Implement PUSH_ROUNDING.
5523
5524 On the H8/300, @-sp really pushes a byte if you ask it to - but that's
5525 dangerous, so we claim that it always pushes a word, then we catch
5526 the mov.b rx,@-sp and turn it into a mov.w rx,@-sp on output.
5527
5528 On the H8/300H, we simplify TARGET_QUICKCALL by setting this to 4
5529 and doing a similar thing. */
5530
5531poly_int64
5532h8300_push_rounding (poly_int64 bytes)
5533{
5534 return ((bytes + PARM_BOUNDARY / 8 - 1) & (-PARM_BOUNDARY / 8));
5535}
9f6ef043 5536\f
6e014ef3
KH		 5537/* Initialize the GCC target structure. */
5538#undef TARGET_ATTRIBUTE_TABLE
5539#define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
5540
5541#undef TARGET_ASM_ALIGNED_HI_OP
5542#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
5543
1bc7c5b6
ZW		 5544#undef TARGET_ASM_FILE_START
5545#define TARGET_ASM_FILE_START h8300_file_start
5546#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5547#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5548
6e014ef3
KH		 5549#undef TARGET_ASM_FILE_END
5550#define TARGET_ASM_FILE_END h8300_file_end
5551
88cb339e
N		 5552#undef TARGET_PRINT_OPERAND
5553#define TARGET_PRINT_OPERAND h8300_print_operand
5554#undef TARGET_PRINT_OPERAND_ADDRESS
5555#define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
5556#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
5557#define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
5558
6e014ef3
KH		 5559#undef TARGET_ENCODE_SECTION_INFO
5560#define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
5561
5562#undef TARGET_INSERT_ATTRIBUTES
5563#define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
5564
88cb339e
N		 5565#undef TARGET_REGISTER_MOVE_COST
5566#define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
5567
6e014ef3
KH		 5568#undef TARGET_RTX_COSTS
5569#define TARGET_RTX_COSTS h8300_rtx_costs
5570
c15c90bb
ZW		 5571#undef TARGET_INIT_LIBFUNCS
5572#define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
5573
9eaa7740
AS		 5574#undef TARGET_FUNCTION_VALUE
5575#define TARGET_FUNCTION_VALUE h8300_function_value
5576
5577#undef TARGET_LIBCALL_VALUE
5578#define TARGET_LIBCALL_VALUE h8300_libcall_value
5579
5580#undef TARGET_FUNCTION_VALUE_REGNO_P
5581#define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
5582
34bf1fe3
KH		 5583#undef TARGET_RETURN_IN_MEMORY
5584#define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
5585
56f9413b
NF		 5586#undef TARGET_FUNCTION_ARG
5587#define TARGET_FUNCTION_ARG h8300_function_arg
5588
5589#undef TARGET_FUNCTION_ARG_ADVANCE
5590#define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
5591
beed8fc0
AO		 5592#undef TARGET_MACHINE_DEPENDENT_REORG
5593#define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
5594
2e762884
DD		 5595#undef TARGET_HARD_REGNO_SCRATCH_OK
5596#define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
5597
f939c3e6
RS		 5598#undef TARGET_HARD_REGNO_MODE_OK
5599#define TARGET_HARD_REGNO_MODE_OK h8300_hard_regno_mode_ok
5600
99e1629f
RS		 5601#undef TARGET_MODES_TIEABLE_P
5602#define TARGET_MODES_TIEABLE_P h8300_modes_tieable_p
5603
d81db636
SB		 5604#undef TARGET_LRA_P
5605#define TARGET_LRA_P hook_bool_void_false
5606
c6c3dba9
PB		 5607#undef TARGET_LEGITIMATE_ADDRESS_P
5608#define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
5609
7b5cbb57
AS		 5610#undef TARGET_CAN_ELIMINATE
5611#define TARGET_CAN_ELIMINATE h8300_can_eliminate
5612
5efd84c5
NF		 5613#undef TARGET_CONDITIONAL_REGISTER_USAGE
5614#define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
5615
9f6ef043
RH		 5616#undef TARGET_TRAMPOLINE_INIT
5617#define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
5618
c5387660
JM		 5619#undef TARGET_OPTION_OVERRIDE
5620#define TARGET_OPTION_OVERRIDE h8300_option_override
5621
f52d97da
AS		 5622#undef TARGET_MODE_DEPENDENT_ADDRESS_P
5623#define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
5624
efbf3c34
JL		 5625#undef TARGET_HAVE_SPECULATION_SAFE_VALUE
5626#define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
5627
f16897cb
AL		 5628#undef TARGET_FLAGS_REGNUM
5629#define TARGET_FLAGS_REGNUM 12
5630
6e014ef3 5631struct gcc_target targetm = TARGET_INITIALIZER;
Mirror of https://gcc.gnu.org/git/gcc.git