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340f6494 | 1 | /* Subroutines for insn-output.c for Renesas H8/300. |
99dee823 | 2 | Copyright (C) 1992-2021 Free Software Foundation, Inc. |
48837e29 DE |
3 | Contributed by Steve Chamberlain (sac@cygnus.com), |
4 | Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). | |
07aae5c2 | 5 | |
8aa063fb | 6 | This file is part of GCC. |
07aae5c2 | 7 | |
8aa063fb | 8 | GCC is free software; you can redistribute it and/or modify |
07aae5c2 | 9 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
07aae5c2 SC |
11 | any later version. |
12 | ||
8aa063fb | 13 | GCC is distributed in the hope that it will be useful, |
07aae5c2 SC |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
07aae5c2 | 21 | |
8fcc61f8 RS |
22 | #define IN_TARGET_CODE 1 |
23 | ||
07aae5c2 | 24 | #include "config.h" |
c5c76735 | 25 | #include "system.h" |
4977bab6 | 26 | #include "coretypes.h" |
c7131fb2 | 27 | #include "backend.h" |
e11c4407 | 28 | #include "target.h" |
07aae5c2 | 29 | #include "rtl.h" |
e11c4407 | 30 | #include "tree.h" |
c7131fb2 | 31 | #include "df.h" |
4d0cdd0c | 32 | #include "memmodel.h" |
e11c4407 AM |
33 | #include "tm_p.h" |
34 | #include "stringpool.h" | |
314e6352 | 35 | #include "attribs.h" |
e11c4407 AM |
36 | #include "optabs.h" |
37 | #include "regs.h" | |
38 | #include "emit-rtl.h" | |
39 | #include "recog.h" | |
40 | #include "diagnostic-core.h" | |
40e23961 | 41 | #include "alias.h" |
d8a2d370 DN |
42 | #include "stor-layout.h" |
43 | #include "varasm.h" | |
44 | #include "calls.h" | |
07aae5c2 | 45 | #include "conditions.h" |
07aae5c2 SC |
46 | #include "output.h" |
47 | #include "insn-attr.h" | |
48 | #include "flags.h" | |
36566b39 | 49 | #include "explow.h" |
36566b39 | 50 | #include "expr.h" |
ceaaaeab | 51 | #include "tm-constrs.h" |
9b2b7279 | 52 | #include "builtins.h" |
07aae5c2 | 53 | |
994c5d85 | 54 | /* This file should be included last. */ |
d58627a0 RS |
55 | #include "target-def.h" |
56 | ||
beed8fc0 AO |
57 | /* Classifies a h8300_src_operand or h8300_dst_operand. |
58 | ||
59 | H8OP_IMMEDIATE | |
60 | A constant operand of some sort. | |
61 | ||
62 | H8OP_REGISTER | |
63 | An ordinary register. | |
64 | ||
65 | H8OP_MEM_ABSOLUTE | |
66 | A memory reference with a constant address. | |
67 | ||
68 | H8OP_MEM_BASE | |
69 | A memory reference with a register as its address. | |
70 | ||
71 | H8OP_MEM_COMPLEX | |
72 | Some other kind of memory reference. */ | |
73 | enum h8300_operand_class | |
74 | { | |
75 | H8OP_IMMEDIATE, | |
76 | H8OP_REGISTER, | |
77 | H8OP_MEM_ABSOLUTE, | |
78 | H8OP_MEM_BASE, | |
79 | H8OP_MEM_COMPLEX, | |
80 | NUM_H8OPS | |
81 | }; | |
82 | ||
beed8fc0 AO |
83 | /* For a general two-operand instruction, element [X][Y] gives |
84 | the length of the opcode fields when the first operand has class | |
85 | (X + 1) and the second has class Y. */ | |
86 | typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS]; | |
87 | ||
07aae5c2 | 88 | /* Forward declarations. */ |
cb713a8d KH |
89 | static const char *byte_reg (rtx, int); |
90 | static int h8300_interrupt_function_p (tree); | |
3cfa3702 | 91 | static int h8300_saveall_function_p (tree); |
cb713a8d KH |
92 | static int h8300_monitor_function_p (tree); |
93 | static int h8300_os_task_function_p (tree); | |
c72ea086 | 94 | static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool); |
e68d4dd1 | 95 | static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT); |
cb713a8d | 96 | static unsigned int compute_saved_regs (void); |
cb713a8d KH |
97 | static const char *cond_string (enum rtx_code); |
98 | static unsigned int h8300_asm_insn_count (const char *); | |
cb713a8d KH |
99 | static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *); |
100 | static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *); | |
101 | static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *); | |
cc8ca59e | 102 | static void h8300_print_operand_address (FILE *, machine_mode, rtx); |
88cb339e N |
103 | static void h8300_print_operand (FILE *, rtx, int); |
104 | static bool h8300_print_operand_punct_valid_p (unsigned char code); | |
ef4bddc2 | 105 | static int h8300_register_move_cost (machine_mode, reg_class_t, reg_class_t); |
cb713a8d KH |
106 | static int h8300_and_costs (rtx); |
107 | static int h8300_shift_costs (rtx); | |
ac447f25 | 108 | static void h8300_push_pop (int, int, bool, bool); |
beed8fc0 AO |
109 | static int h8300_stack_offset_p (rtx, int); |
110 | static int h8300_ldm_stm_regno (rtx, int, int, int); | |
beed8fc0 AO |
111 | static void h8300_reorg (void); |
112 | static unsigned int h8300_constant_length (rtx); | |
113 | static unsigned int h8300_displacement_length (rtx, int); | |
114 | static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *); | |
115 | static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *); | |
116 | static unsigned int h8300_unary_length (rtx); | |
117 | static unsigned int h8300_short_immediate_length (rtx); | |
118 | static unsigned int h8300_bitfield_length (rtx, rtx); | |
e7041fcc | 119 | static unsigned int h8300_binary_length (rtx_insn *, const h8300_length_table *); |
beed8fc0 AO |
120 | static bool h8300_short_move_mem_p (rtx, enum rtx_code); |
121 | static unsigned int h8300_move_length (rtx *, const h8300_length_table *); | |
2e762884 | 122 | static bool h8300_hard_regno_scratch_ok (unsigned int); |
ef4bddc2 | 123 | static rtx h8300_get_index (rtx, machine_mode mode, int *); |
f5b65a56 | 124 | |
48837e29 DE |
125 | /* CPU_TYPE, says what cpu we're compiling for. */ |
126 | int cpu_type; | |
127 | ||
e392d367 KH |
128 | /* True if a #pragma interrupt has been seen for the current function. */ |
129 | static int pragma_interrupt; | |
07aae5c2 SC |
130 | |
131 | /* True if a #pragma saveall has been seen for the current function. */ | |
0869f126 | 132 | static int pragma_saveall; |
07aae5c2 | 133 | |
441d04c6 | 134 | static const char *const names_big[] = |
f16897cb | 135 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc" }; |
48837e29 | 136 | |
441d04c6 | 137 | static const char *const names_extended[] = |
f16897cb | 138 | { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7", "cc" }; |
48837e29 | 139 | |
441d04c6 | 140 | static const char *const names_upper_extended[] = |
f16897cb | 141 | { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7", "cc" }; |
48837e29 DE |
142 | |
143 | /* Points to one of the above. */ | |
144 | /* ??? The above could be put in an array indexed by CPU_TYPE. */ | |
441d04c6 | 145 | const char * const *h8_reg_names; |
48837e29 DE |
146 | |
147 | /* Various operations needed by the following, indexed by CPU_TYPE. */ | |
48837e29 | 148 | |
441d04c6 | 149 | const char *h8_push_op, *h8_pop_op, *h8_mov_op; |
dc66a1c4 | 150 | |
beed8fc0 AO |
151 | /* Value of MOVE_RATIO. */ |
152 | int h8300_move_ratio; | |
672a6f42 | 153 | \f |
c4dfc70c DD |
154 | /* See below where shifts are handled for explanation of this enum. */ |
155 | ||
156 | enum shift_alg | |
157 | { | |
158 | SHIFT_INLINE, | |
159 | SHIFT_ROT_AND, | |
160 | SHIFT_SPECIAL, | |
161 | SHIFT_LOOP | |
162 | }; | |
163 | ||
164 | /* Symbols of the various shifts which can be used as indices. */ | |
165 | ||
166 | enum shift_type | |
167 | { | |
168 | SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT | |
169 | }; | |
170 | ||
171 | /* Macros to keep the shift algorithm tables small. */ | |
172 | #define INL SHIFT_INLINE | |
173 | #define ROT SHIFT_ROT_AND | |
174 | #define LOP SHIFT_LOOP | |
175 | #define SPC SHIFT_SPECIAL | |
176 | ||
177 | /* The shift algorithms for each machine, mode, shift type, and shift | |
178 | count are defined below. The three tables below correspond to | |
179 | QImode, HImode, and SImode, respectively. Each table is organized | |
f411c849 | 180 | by, in the order of indices, machine, shift type, and shift count. */ |
c4dfc70c | 181 | |
27c1afd5 | 182 | static enum shift_alg shift_alg_qi[2][3][8] = { |
c4dfc70c DD |
183 | { |
184 | /* TARGET_H8300H */ | |
185 | /* 0 1 2 3 4 5 6 7 */ | |
186 | { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ | |
187 | { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ | |
188 | { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */ | |
189 | }, | |
190 | { | |
191 | /* TARGET_H8300S */ | |
192 | /* 0 1 2 3 4 5 6 7 */ | |
193 | { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */ | |
194 | { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */ | |
195 | { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */ | |
196 | } | |
197 | }; | |
198 | ||
27c1afd5 | 199 | static enum shift_alg shift_alg_hi[2][3][16] = { |
c4dfc70c DD |
200 | { |
201 | /* TARGET_H8300H */ | |
202 | /* 0 1 2 3 4 5 6 7 */ | |
203 | /* 8 9 10 11 12 13 14 15 */ | |
204 | { INL, INL, INL, INL, INL, INL, INL, SPC, | |
205 | SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ | |
206 | { INL, INL, INL, INL, INL, INL, INL, SPC, | |
207 | SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ | |
208 | { INL, INL, INL, INL, INL, INL, INL, SPC, | |
209 | SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ | |
210 | }, | |
211 | { | |
212 | /* TARGET_H8300S */ | |
213 | /* 0 1 2 3 4 5 6 7 */ | |
214 | /* 8 9 10 11 12 13 14 15 */ | |
215 | { INL, INL, INL, INL, INL, INL, INL, INL, | |
216 | SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ | |
217 | { INL, INL, INL, INL, INL, INL, INL, INL, | |
218 | SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ | |
219 | { INL, INL, INL, INL, INL, INL, INL, INL, | |
220 | SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ | |
221 | } | |
222 | }; | |
223 | ||
27c1afd5 | 224 | static enum shift_alg shift_alg_si[2][3][32] = { |
c4dfc70c DD |
225 | { |
226 | /* TARGET_H8300H */ | |
227 | /* 0 1 2 3 4 5 6 7 */ | |
228 | /* 8 9 10 11 12 13 14 15 */ | |
229 | /* 16 17 18 19 20 21 22 23 */ | |
230 | /* 24 25 26 27 28 29 30 31 */ | |
231 | { INL, INL, INL, INL, INL, LOP, LOP, LOP, | |
232 | SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, | |
233 | SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP, | |
1e5bdc40 | 234 | SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */ |
c4dfc70c DD |
235 | { INL, INL, INL, INL, INL, LOP, LOP, LOP, |
236 | SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, | |
237 | SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP, | |
1e5bdc40 | 238 | SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */ |
c4dfc70c DD |
239 | { INL, INL, INL, INL, INL, LOP, LOP, LOP, |
240 | SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP, | |
241 | SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP, | |
242 | SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */ | |
243 | }, | |
244 | { | |
245 | /* TARGET_H8300S */ | |
246 | /* 0 1 2 3 4 5 6 7 */ | |
247 | /* 8 9 10 11 12 13 14 15 */ | |
248 | /* 16 17 18 19 20 21 22 23 */ | |
249 | /* 24 25 26 27 28 29 30 31 */ | |
250 | { INL, INL, INL, INL, INL, INL, INL, INL, | |
251 | INL, INL, INL, LOP, LOP, LOP, LOP, SPC, | |
252 | SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP, | |
1e5bdc40 | 253 | SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */ |
c4dfc70c DD |
254 | { INL, INL, INL, INL, INL, INL, INL, INL, |
255 | INL, INL, INL, LOP, LOP, LOP, LOP, SPC, | |
256 | SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP, | |
1e5bdc40 | 257 | SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */ |
c4dfc70c DD |
258 | { INL, INL, INL, INL, INL, INL, INL, INL, |
259 | INL, INL, INL, LOP, LOP, LOP, LOP, LOP, | |
260 | SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP, | |
261 | SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */ | |
262 | } | |
263 | }; | |
264 | ||
265 | #undef INL | |
266 | #undef ROT | |
267 | #undef LOP | |
268 | #undef SPC | |
269 | ||
270 | enum h8_cpu | |
271 | { | |
c4dfc70c DD |
272 | H8_300H, |
273 | H8_S | |
274 | }; | |
275 | ||
48837e29 DE |
276 | /* Initialize various cpu specific globals at start up. */ |
277 | ||
c5387660 JM |
278 | static void |
279 | h8300_option_override (void) | |
48837e29 | 280 | { |
cbf1b2da KH |
281 | static const char *const h8_push_ops[2] = { "push" , "push.l" }; |
282 | static const char *const h8_pop_ops[2] = { "pop" , "pop.l" }; | |
283 | static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" }; | |
284 | ||
27c1afd5 JL |
285 | /* For this we treat the H8/300H and H8S the same. */ |
286 | cpu_type = (int) CPU_H8300H; | |
287 | h8_reg_names = names_extended; | |
48837e29 DE |
288 | h8_push_op = h8_push_ops[cpu_type]; |
289 | h8_pop_op = h8_pop_ops[cpu_type]; | |
290 | h8_mov_op = h8_mov_ops[cpu_type]; | |
17f0f8fa | 291 | |
27c1afd5 JL |
292 | /* If we're compiling for the H8/S, then turn off H8/300H. */ |
293 | if (TARGET_H8300S) | |
294 | target_flags &= ~MASK_H8300H; | |
295 | ||
17f0f8fa | 296 | if (!TARGET_H8300S && TARGET_MAC) |
400500c4 | 297 | { |
a3f9f006 | 298 | error ("%<-ms2600%> is used without %<-ms%>"); |
5463c726 | 299 | target_flags |= MASK_H8300S_1; |
400500c4 | 300 | } |
920e86b8 | 301 | |
f4ea8112 SKS |
302 | if (! TARGET_H8300S && TARGET_EXR) |
303 | { | |
a3f9f006 | 304 | error ("%<-mexr%> is used without %<-ms%>"); |
f4ea8112 SKS |
305 | target_flags |= MASK_H8300S_1; |
306 | } | |
307 | ||
f4ea8112 SKS |
308 | if ((!TARGET_H8300S && TARGET_EXR) && (!TARGET_H8300SX && TARGET_EXR)) |
309 | { | |
a3f9f006 | 310 | error ("%<-mexr%> is used without %<-ms%> or %<-msx%>"); |
f4ea8112 SKS |
311 | target_flags |= MASK_H8300S_1; |
312 | } | |
313 | ||
314 | if ((!TARGET_H8300S && TARGET_NEXR) && (!TARGET_H8300SX && TARGET_NEXR)) | |
315 | { | |
dfa075d0 JL |
316 | warning (OPT_mno_exr, "%<-mno-exr%> is valid only with %<-ms%> or " |
317 | "%<-msx%> - option ignored"); | |
f4ea8112 SKS |
318 | } |
319 | ||
2f6bd6eb YS |
320 | #ifdef H8300_LINUX |
321 | if ((TARGET_NORMAL_MODE)) | |
322 | { | |
a3f9f006 | 323 | error ("%<-mn%> is not supported for linux targets"); |
2f6bd6eb YS |
324 | target_flags ^= MASK_NORMAL_MODE; |
325 | } | |
326 | #endif | |
327 | ||
8bd06267 | 328 | /* Some of the shifts are optimized for speed by default. |
c4dfc70c | 329 | See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html |
8bd06267 | 330 | If optimizing for size, change shift_alg for those shift to |
c4dfc70c | 331 | SHIFT_LOOP. */ |
b6894857 | 332 | if (optimize_size) |
c4dfc70c | 333 | { |
b6894857 KH |
334 | /* H8/300H */ |
335 | shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP; | |
336 | shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP; | |
c4dfc70c | 337 | |
b6894857 KH |
338 | shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP; |
339 | shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP; | |
c4dfc70c | 340 | |
b6894857 KH |
341 | shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP; |
342 | shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP; | |
343 | shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP; | |
344 | shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; | |
c4dfc70c DD |
345 | |
346 | /* H8S */ | |
b6894857 | 347 | shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; |
c4dfc70c | 348 | } |
beed8fc0 AO |
349 | |
350 | /* Work out a value for MOVE_RATIO. */ | |
351 | if (!TARGET_H8300SX) | |
352 | { | |
353 | /* Memory-memory moves are quite expensive without the | |
354 | h8sx instructions. */ | |
355 | h8300_move_ratio = 3; | |
356 | } | |
357 | else if (flag_omit_frame_pointer) | |
358 | { | |
359 | /* movmd sequences are fairly cheap when er6 isn't fixed. They can | |
360 | sometimes be as short as two individual memory-to-memory moves, | |
361 | but since they use all the call-saved registers, it seems better | |
362 | to allow up to three moves here. */ | |
363 | h8300_move_ratio = 4; | |
364 | } | |
365 | else if (optimize_size) | |
366 | { | |
367 | /* In this case we don't use movmd sequences since they tend | |
368 | to be longer than calls to memcpy(). Memory-to-memory | |
369 | moves are cheaper than for !TARGET_H8300SX, so it makes | |
370 | sense to have a slightly higher threshold. */ | |
371 | h8300_move_ratio = 4; | |
372 | } | |
373 | else | |
374 | { | |
375 | /* We use movmd sequences for some moves since it can be quicker | |
376 | than calling memcpy(). The sequences will need to save and | |
377 | restore er6 though, so bump up the cost. */ | |
378 | h8300_move_ratio = 6; | |
379 | } | |
0685e770 DD |
380 | |
381 | /* This target defaults to strict volatile bitfields. */ | |
36acc1a2 | 382 | if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2)) |
0685e770 | 383 | flag_strict_volatile_bitfields = 1; |
beed8fc0 AO |
384 | } |
385 | ||
e9eba255 KH |
386 | /* Return the byte register name for a register rtx X. B should be 0 |
387 | if you want a lower byte register. B should be 1 if you want an | |
388 | upper byte register. */ | |
389 | ||
9c188705 | 390 | static const char * |
cb713a8d | 391 | byte_reg (rtx x, int b) |
07aae5c2 | 392 | { |
9cbcd983 KH |
393 | static const char *const names_small[] = { |
394 | "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h", | |
395 | "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h" | |
396 | }; | |
07aae5c2 | 397 | |
8c440872 | 398 | gcc_assert (REG_P (x)); |
500fc80f | 399 | |
07aae5c2 SC |
400 | return names_small[REGNO (x) * 2 + b]; |
401 | } | |
402 | ||
403 | /* REGNO must be saved/restored across calls if this macro is true. */ | |
48837e29 | 404 | |
9cbcd983 | 405 | #define WORD_REG_USED(regno) \ |
d60004ee | 406 | (regno < SP_REG \ |
9cbcd983 KH |
407 | /* No need to save registers if this function will not return. */ \ |
408 | && ! TREE_THIS_VOLATILE (current_function_decl) \ | |
3cfa3702 | 409 | && (h8300_saveall_function_p (current_function_decl) \ |
9cbcd983 | 410 | /* Save any call saved register that was used. */ \ |
a365fa06 RS |
411 | || (df_regs_ever_live_p (regno) \ |
412 | && !call_used_or_fixed_reg_p (regno)) \ | |
9cbcd983 | 413 | /* Save the frame pointer if it was used. */ \ |
6fb5fa3c | 414 | || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \ |
9cbcd983 | 415 | /* Save any register used in an interrupt handler. */ \ |
e392d367 | 416 | || (h8300_current_function_interrupt_function_p () \ |
6fb5fa3c | 417 | && df_regs_ever_live_p (regno)) \ |
9cbcd983 KH |
418 | /* Save call clobbered registers in non-leaf interrupt \ |
419 | handlers. */ \ | |
e392d367 | 420 | || (h8300_current_function_interrupt_function_p () \ |
a365fa06 | 421 | && call_used_or_fixed_reg_p (regno) \ |
416ff32e | 422 | && !crtl->is_leaf))) |
07aae5c2 | 423 | |
18674659 | 424 | /* We use this to wrap all emitted insns in the prologue. */ |
e7041fcc DM |
425 | static rtx_insn * |
426 | F (rtx_insn *x, bool set_it) | |
18674659 | 427 | { |
c72ea086 DD |
428 | if (set_it) |
429 | RTX_FRAME_RELATED_P (x) = 1; | |
18674659 DD |
430 | return x; |
431 | } | |
432 | ||
433 | /* Mark all the subexpressions of the PARALLEL rtx PAR as | |
434 | frame-related. Return PAR. | |
435 | ||
436 | dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a | |
437 | PARALLEL rtx other than the first if they do not have the | |
438 | FRAME_RELATED flag set on them. */ | |
439 | static rtx | |
440 | Fpa (rtx par) | |
441 | { | |
442 | int len = XVECLEN (par, 0); | |
443 | int i; | |
444 | ||
445 | for (i = 0; i < len; i++) | |
f698a4b1 | 446 | RTX_FRAME_RELATED_P (XVECEXP (par, 0, i)) = 1; |
18674659 DD |
447 | |
448 | return par; | |
449 | } | |
450 | ||
07aae5c2 | 451 | /* Output assembly language to FILE for the operation OP with operand size |
48837e29 | 452 | SIZE to adjust the stack pointer. */ |
48837e29 | 453 | |
07aae5c2 | 454 | static void |
c72ea086 | 455 | h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue) |
07aae5c2 | 456 | { |
72b1de44 KH |
457 | /* If the frame size is 0, we don't have anything to do. */ |
458 | if (size == 0) | |
f8b58e56 | 459 | return; |
72b1de44 | 460 | |
27c1afd5 JL |
461 | /* The stack adjustment made here is further optimized by the |
462 | splitter. In case of H8/300, the splitter always splits the | |
463 | addition emitted here to make the adjustment interrupt-safe. | |
464 | FIXME: We don't always tag those, because we don't know what | |
465 | the splitter will do. */ | |
466 | if (Pmode == HImode) | |
f8f26adc | 467 | { |
27c1afd5 JL |
468 | rtx_insn *x = emit_insn (gen_addhi3 (stack_pointer_rtx, |
469 | stack_pointer_rtx, | |
470 | GEN_INT (sign * size))); | |
471 | if (size < 4) | |
f16897cb | 472 | F (x, 0); |
7b3d4613 KH |
473 | } |
474 | else | |
27c1afd5 | 475 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
f16897cb | 476 | stack_pointer_rtx, GEN_INT (sign * size))), 0); |
07aae5c2 SC |
477 | } |
478 | ||
8682223f KH |
479 | /* Round up frame size SIZE. */ |
480 | ||
e68d4dd1 UB |
481 | static HOST_WIDE_INT |
482 | round_frame_size (HOST_WIDE_INT size) | |
8682223f | 483 | { |
489eda65 KH |
484 | return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1) |
485 | & -STACK_BOUNDARY / BITS_PER_UNIT); | |
8682223f KH |
486 | } |
487 | ||
488 | /* Compute which registers to push/pop. | |
489 | Return a bit vector of registers. */ | |
490 | ||
491 | static unsigned int | |
cb713a8d | 492 | compute_saved_regs (void) |
8682223f KH |
493 | { |
494 | unsigned int saved_regs = 0; | |
495 | int regno; | |
496 | ||
497 | /* Construct a bit vector of registers to be pushed/popped. */ | |
1807b726 | 498 | for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++) |
8682223f KH |
499 | { |
500 | if (WORD_REG_USED (regno)) | |
501 | saved_regs |= 1 << regno; | |
502 | } | |
503 | ||
504 | /* Don't push/pop the frame pointer as it is treated separately. */ | |
505 | if (frame_pointer_needed) | |
1807b726 | 506 | saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM); |
8682223f KH |
507 | |
508 | return saved_regs; | |
509 | } | |
510 | ||
68ee6df6 | 511 | /* Emit an insn to push register RN. */ |
8682223f | 512 | |
8f1594b2 | 513 | static rtx |
1901e8d6 | 514 | push (int rn, bool in_prologue) |
8682223f | 515 | { |
68ee6df6 KH |
516 | rtx reg = gen_rtx_REG (word_mode, rn); |
517 | rtx x; | |
518 | ||
27c1afd5 | 519 | if (!TARGET_NORMAL_MODE) |
32da7865 | 520 | x = gen_push_h8300hs_advanced (reg); |
f24f0897 KH |
521 | else |
522 | x = gen_push_h8300hs_normal (reg); | |
f16897cb | 523 | x = F (emit_insn (x), 0); |
9690aa8e | 524 | add_reg_note (x, REG_INC, stack_pointer_rtx); |
8f1594b2 | 525 | return x; |
8682223f KH |
526 | } |
527 | ||
68ee6df6 | 528 | /* Emit an insn to pop register RN. */ |
8682223f | 529 | |
8f1594b2 | 530 | static rtx |
cb713a8d | 531 | pop (int rn) |
8682223f | 532 | { |
68ee6df6 KH |
533 | rtx reg = gen_rtx_REG (word_mode, rn); |
534 | rtx x; | |
535 | ||
27c1afd5 | 536 | if (!TARGET_NORMAL_MODE) |
32da7865 | 537 | x = gen_pop_h8300hs_advanced (reg); |
f24f0897 KH |
538 | else |
539 | x = gen_pop_h8300hs_normal (reg); | |
68ee6df6 | 540 | x = emit_insn (x); |
9690aa8e | 541 | add_reg_note (x, REG_INC, stack_pointer_rtx); |
8f1594b2 | 542 | return x; |
8682223f | 543 | } |
07aae5c2 | 544 | |
beed8fc0 AO |
545 | /* Emit an instruction to push or pop NREGS consecutive registers |
546 | starting at register REGNO. POP_P selects a pop rather than a | |
547 | push and RETURN_P is true if the instruction should return. | |
548 | ||
549 | It must be possible to do the requested operation in a single | |
550 | instruction. If NREGS == 1 && !RETURN_P, use a normal push | |
551 | or pop insn. Otherwise emit a parallel of the form: | |
552 | ||
553 | (parallel | |
554 | [(return) ;; if RETURN_P | |
555 | (save or restore REGNO) | |
556 | (save or restore REGNO + 1) | |
557 | ... | |
558 | (save or restore REGNO + NREGS - 1) | |
559 | (set sp (plus sp (const_int adjust)))] */ | |
560 | ||
561 | static void | |
ac447f25 | 562 | h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p) |
beed8fc0 AO |
563 | { |
564 | int i, j; | |
565 | rtvec vec; | |
18674659 | 566 | rtx sp, offset, x; |
beed8fc0 AO |
567 | |
568 | /* See whether we can use a simple push or pop. */ | |
569 | if (!return_p && nregs == 1) | |
570 | { | |
571 | if (pop_p) | |
572 | pop (regno); | |
573 | else | |
1901e8d6 | 574 | push (regno, false); |
beed8fc0 AO |
575 | return; |
576 | } | |
577 | ||
578 | /* We need one element for the return insn, if present, one for each | |
579 | register, and one for stack adjustment. */ | |
ac447f25 | 580 | vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1); |
beed8fc0 AO |
581 | sp = stack_pointer_rtx; |
582 | i = 0; | |
583 | ||
584 | /* Add the return instruction. */ | |
585 | if (return_p) | |
586 | { | |
3810076b | 587 | RTVEC_ELT (vec, i) = ret_rtx; |
beed8fc0 AO |
588 | i++; |
589 | } | |
590 | ||
591 | /* Add the register moves. */ | |
592 | for (j = 0; j < nregs; j++) | |
593 | { | |
594 | rtx lhs, rhs; | |
595 | ||
596 | if (pop_p) | |
597 | { | |
598 | /* Register REGNO + NREGS - 1 is popped first. Before the | |
599 | stack adjustment, its slot is at address @sp. */ | |
600 | lhs = gen_rtx_REG (SImode, regno + j); | |
0a81f074 RS |
601 | rhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, |
602 | (nregs - j - 1) * 4)); | |
beed8fc0 AO |
603 | } |
604 | else | |
605 | { | |
606 | /* Register REGNO is pushed first and will be stored at @(-4,sp). */ | |
0a81f074 | 607 | lhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, (j + 1) * -4)); |
beed8fc0 AO |
608 | rhs = gen_rtx_REG (SImode, regno + j); |
609 | } | |
f7df4a84 | 610 | RTVEC_ELT (vec, i + j) = gen_rtx_SET (lhs, rhs); |
beed8fc0 AO |
611 | } |
612 | ||
613 | /* Add the stack adjustment. */ | |
614 | offset = GEN_INT ((pop_p ? nregs : -nregs) * 4); | |
f7df4a84 | 615 | RTVEC_ELT (vec, i + j) = gen_rtx_SET (sp, gen_rtx_PLUS (Pmode, sp, offset)); |
beed8fc0 | 616 | |
18674659 DD |
617 | x = gen_rtx_PARALLEL (VOIDmode, vec); |
618 | if (!pop_p) | |
619 | x = Fpa (x); | |
ac447f25 NC |
620 | |
621 | if (return_p) | |
622 | emit_jump_insn (x); | |
623 | else | |
624 | emit_insn (x); | |
beed8fc0 AO |
625 | } |
626 | ||
627 | /* Return true if X has the value sp + OFFSET. */ | |
628 | ||
629 | static int | |
630 | h8300_stack_offset_p (rtx x, int offset) | |
631 | { | |
632 | if (offset == 0) | |
633 | return x == stack_pointer_rtx; | |
634 | ||
635 | return (GET_CODE (x) == PLUS | |
636 | && XEXP (x, 0) == stack_pointer_rtx | |
637 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
638 | && INTVAL (XEXP (x, 1)) == offset); | |
639 | } | |
640 | ||
641 | /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in | |
642 | something that may be an ldm or stm instruction. If it fits | |
643 | the required template, return the register it loads or stores, | |
644 | otherwise return -1. | |
645 | ||
646 | LOAD_P is true if X should be a load, false if it should be a store. | |
647 | NREGS is the number of registers that the whole instruction is expected | |
648 | to load or store. INDEX is the index of the register that X should | |
649 | load or store, relative to the lowest-numbered register. */ | |
650 | ||
651 | static int | |
652 | h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs) | |
653 | { | |
654 | int regindex, memindex, offset; | |
655 | ||
656 | if (load_p) | |
657 | regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4; | |
658 | else | |
659 | memindex = 0, regindex = 1, offset = (index + 1) * -4; | |
660 | ||
661 | if (GET_CODE (x) == SET | |
662 | && GET_CODE (XEXP (x, regindex)) == REG | |
663 | && GET_CODE (XEXP (x, memindex)) == MEM | |
664 | && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset)) | |
665 | return REGNO (XEXP (x, regindex)); | |
666 | ||
667 | return -1; | |
668 | } | |
669 | ||
670 | /* Return true if the elements of VEC starting at FIRST describe an | |
671 | ldm or stm instruction (LOAD_P says which). */ | |
672 | ||
981c7dce | 673 | int |
beed8fc0 AO |
674 | h8300_ldm_stm_parallel (rtvec vec, int load_p, int first) |
675 | { | |
676 | rtx last; | |
677 | int nregs, i, regno, adjust; | |
678 | ||
679 | /* There must be a stack adjustment, a register move, and at least one | |
680 | other operation (a return or another register move). */ | |
681 | if (GET_NUM_ELEM (vec) < 3) | |
682 | return false; | |
683 | ||
684 | /* Get the range of registers to be pushed or popped. */ | |
685 | nregs = GET_NUM_ELEM (vec) - first - 1; | |
686 | regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs); | |
687 | ||
688 | /* Check that the call to h8300_ldm_stm_regno succeeded and | |
689 | that we're only dealing with GPRs. */ | |
690 | if (regno < 0 || regno + nregs > 8) | |
691 | return false; | |
692 | ||
693 | /* 2-register h8s instructions must start with an even-numbered register. | |
694 | 3- and 4-register instructions must start with er0 or er4. */ | |
695 | if (!TARGET_H8300SX) | |
696 | { | |
697 | if ((regno & 1) != 0) | |
698 | return false; | |
699 | if (nregs > 2 && (regno & 3) != 0) | |
700 | return false; | |
701 | } | |
702 | ||
703 | /* Check the other loads or stores. */ | |
704 | for (i = 1; i < nregs; i++) | |
705 | if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs) | |
706 | != regno + i) | |
707 | return false; | |
708 | ||
709 | /* Check the stack adjustment. */ | |
710 | last = RTVEC_ELT (vec, first + nregs); | |
711 | adjust = (load_p ? nregs : -nregs) * 4; | |
712 | return (GET_CODE (last) == SET | |
713 | && SET_DEST (last) == stack_pointer_rtx | |
714 | && h8300_stack_offset_p (SET_SRC (last), adjust)); | |
715 | } | |
716 | ||
f0b6f9a6 | 717 | /* This is what the stack looks like after the prolog of |
07aae5c2 SC |
718 | a function with a frame has been set up: |
719 | ||
48837e29 DE |
720 | <args> |
721 | PC | |
722 | FP <- fp | |
723 | <locals> | |
8bd06267 | 724 | <saved registers> <- sp |
07aae5c2 SC |
725 | |
726 | This is what the stack looks like after the prolog of | |
727 | a function which doesn't have a frame: | |
728 | ||
48837e29 DE |
729 | <args> |
730 | PC | |
731 | <locals> | |
8bd06267 | 732 | <saved registers> <- sp |
07aae5c2 SC |
733 | */ |
734 | ||
68ee6df6 | 735 | /* Generate RTL code for the function prologue. */ |
8682223f | 736 | |
68ee6df6 | 737 | void |
cb713a8d | 738 | h8300_expand_prologue (void) |
07aae5c2 | 739 | { |
e651d484 | 740 | int regno; |
8682223f | 741 | int saved_regs; |
cda4bd43 | 742 | int n_regs; |
07aae5c2 | 743 | |
fabe72bb JL |
744 | /* If the current function has the OS_Task attribute set, then |
745 | we have a naked prologue. */ | |
746 | if (h8300_os_task_function_p (current_function_decl)) | |
68ee6df6 | 747 | return; |
fabe72bb JL |
748 | |
749 | if (h8300_monitor_function_p (current_function_decl)) | |
f4ea8112 SKS |
750 | /* The monitor function act as normal functions, which means it |
751 | can accept parameters and return values. In addition to this, | |
752 | interrupts are masked in prologue and return with "rte" in epilogue. */ | |
68ee6df6 | 753 | emit_insn (gen_monitor_prologue ()); |
fabe72bb | 754 | |
48837e29 DE |
755 | if (frame_pointer_needed) |
756 | { | |
07e4d94e | 757 | /* Push fp. */ |
1901e8d6 | 758 | push (HARD_FRAME_POINTER_REGNUM, true); |
f16897cb | 759 | F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), 0); |
a1616dd9 | 760 | } |
48837e29 | 761 | |
8682223f KH |
762 | /* Push the rest of the registers in ascending order. */ |
763 | saved_regs = compute_saved_regs (); | |
e651d484 | 764 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs) |
cda4bd43 | 765 | { |
cda4bd43 | 766 | n_regs = 1; |
8682223f | 767 | if (saved_regs & (1 << regno)) |
a1616dd9 JL |
768 | { |
769 | if (TARGET_H8300S) | |
770 | { | |
cda4bd43 | 771 | /* See how many registers we can push at the same time. */ |
040e0e44 | 772 | if ((TARGET_H8300SX || (regno & 3) == 0) |
8682223f | 773 | && ((saved_regs >> regno) & 0x0f) == 0x0f) |
cda4bd43 KH |
774 | n_regs = 4; |
775 | ||
040e0e44 | 776 | else if ((TARGET_H8300SX || (regno & 3) == 0) |
8682223f | 777 | && ((saved_regs >> regno) & 0x07) == 0x07) |
cda4bd43 KH |
778 | n_regs = 3; |
779 | ||
040e0e44 | 780 | else if ((TARGET_H8300SX || (regno & 1) == 0) |
8682223f | 781 | && ((saved_regs >> regno) & 0x03) == 0x03) |
cda4bd43 | 782 | n_regs = 2; |
a1616dd9 | 783 | } |
cda4bd43 | 784 | |
ac447f25 | 785 | h8300_push_pop (regno, n_regs, false, false); |
07aae5c2 SC |
786 | } |
787 | } | |
1807b726 KH |
788 | |
789 | /* Leave room for locals. */ | |
c72ea086 | 790 | h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true); |
ed1332ee NC |
791 | |
792 | if (flag_stack_usage_info) | |
793 | current_function_static_stack_size | |
794 | = round_frame_size (get_frame_size ()) | |
795 | + (__builtin_popcount (saved_regs) * UNITS_PER_WORD) | |
796 | + (frame_pointer_needed ? UNITS_PER_WORD : 0); | |
07aae5c2 SC |
797 | } |
798 | ||
e9eba255 KH |
799 | /* Return nonzero if we can use "rts" for the function currently being |
800 | compiled. */ | |
801 | ||
68ee6df6 | 802 | int |
cb713a8d | 803 | h8300_can_use_return_insn_p (void) |
68ee6df6 KH |
804 | { |
805 | return (reload_completed | |
806 | && !frame_pointer_needed | |
807 | && get_frame_size () == 0 | |
808 | && compute_saved_regs () == 0); | |
809 | } | |
07aae5c2 | 810 | |
68ee6df6 KH |
811 | /* Generate RTL code for the function epilogue. */ |
812 | ||
813 | void | |
cb713a8d | 814 | h8300_expand_epilogue (void) |
07aae5c2 | 815 | { |
e651d484 | 816 | int regno; |
8682223f | 817 | int saved_regs; |
cda4bd43 | 818 | int n_regs; |
beed8fc0 AO |
819 | HOST_WIDE_INT frame_size; |
820 | bool returned_p; | |
07aae5c2 | 821 | |
e392d367 | 822 | if (h8300_os_task_function_p (current_function_decl)) |
68ee6df6 KH |
823 | /* OS_Task epilogues are nearly naked -- they just have an |
824 | rts instruction. */ | |
825 | return; | |
07aae5c2 | 826 | |
beed8fc0 AO |
827 | frame_size = round_frame_size (get_frame_size ()); |
828 | returned_p = false; | |
829 | ||
1807b726 | 830 | /* Deallocate locals. */ |
c72ea086 | 831 | h8300_emit_stack_adjustment (1, frame_size, false); |
1807b726 | 832 | |
8682223f KH |
833 | /* Pop the saved registers in descending order. */ |
834 | saved_regs = compute_saved_regs (); | |
e651d484 | 835 | for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs) |
cda4bd43 | 836 | { |
cda4bd43 | 837 | n_regs = 1; |
8682223f | 838 | if (saved_regs & (1 << regno)) |
07aae5c2 | 839 | { |
a1616dd9 JL |
840 | if (TARGET_H8300S) |
841 | { | |
cda4bd43 | 842 | /* See how many registers we can pop at the same time. */ |
beed8fc0 AO |
843 | if ((TARGET_H8300SX || (regno & 3) == 3) |
844 | && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f) | |
cda4bd43 KH |
845 | n_regs = 4; |
846 | ||
beed8fc0 AO |
847 | else if ((TARGET_H8300SX || (regno & 3) == 2) |
848 | && ((saved_regs << 2 >> regno) & 0x07) == 0x07) | |
cda4bd43 KH |
849 | n_regs = 3; |
850 | ||
beed8fc0 AO |
851 | else if ((TARGET_H8300SX || (regno & 1) == 1) |
852 | && ((saved_regs << 1 >> regno) & 0x03) == 0x03) | |
cda4bd43 | 853 | n_regs = 2; |
a1616dd9 | 854 | } |
cda4bd43 | 855 | |
beed8fc0 AO |
856 | /* See if this pop would be the last insn before the return. |
857 | If so, use rte/l or rts/l instead of pop or ldm.l. */ | |
858 | if (TARGET_H8300SX | |
859 | && !frame_pointer_needed | |
860 | && frame_size == 0 | |
861 | && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0) | |
862 | returned_p = true; | |
863 | ||
ac447f25 | 864 | h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p); |
07aae5c2 | 865 | } |
07aae5c2 | 866 | } |
48837e29 | 867 | |
07e4d94e | 868 | /* Pop frame pointer if we had one. */ |
a1616dd9 | 869 | if (frame_pointer_needed) |
beed8fc0 AO |
870 | { |
871 | if (TARGET_H8300SX) | |
872 | returned_p = true; | |
ac447f25 | 873 | h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p); |
beed8fc0 AO |
874 | } |
875 | ||
876 | if (!returned_p) | |
3810076b | 877 | emit_jump_insn (ret_rtx); |
68ee6df6 | 878 | } |
a1616dd9 | 879 | |
e392d367 KH |
880 | /* Return nonzero if the current function is an interrupt |
881 | function. */ | |
882 | ||
883 | int | |
cb713a8d | 884 | h8300_current_function_interrupt_function_p (void) |
e392d367 | 885 | { |
f4ea8112 SKS |
886 | return (h8300_interrupt_function_p (current_function_decl)); |
887 | } | |
888 | ||
889 | int | |
890 | h8300_current_function_monitor_function_p () | |
891 | { | |
892 | return (h8300_monitor_function_p (current_function_decl)); | |
e392d367 KH |
893 | } |
894 | ||
48837e29 DE |
895 | /* Output assembly code for the start of the file. */ |
896 | ||
1bc7c5b6 ZW |
897 | static void |
898 | h8300_file_start (void) | |
48837e29 | 899 | { |
1bc7c5b6 | 900 | default_file_start (); |
8bd06267 | 901 | |
2f6bd6eb | 902 | if (TARGET_H8300SX) |
beed8fc0 | 903 | fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file); |
a1616dd9 | 904 | else if (TARGET_H8300S) |
1bc7c5b6 | 905 | fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file); |
2f6bd6eb YS |
906 | else if (TARGET_H8300H) |
907 | fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file); | |
48837e29 DE |
908 | } |
909 | ||
910 | /* Output assembly language code for the end of file. */ | |
911 | ||
a5fe455b | 912 | static void |
cb713a8d | 913 | h8300_file_end (void) |
48837e29 | 914 | { |
a5fe455b | 915 | fputs ("\t.end\n", asm_out_file); |
07aae5c2 SC |
916 | } |
917 | \f | |
3cee1a78 KH |
918 | /* Split an add of a small constant into two adds/subs insns. |
919 | ||
920 | If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec | |
921 | instead of adds/subs. */ | |
009ac3d3 RH |
922 | |
923 | void | |
ef4bddc2 | 924 | split_adds_subs (machine_mode mode, rtx *operands) |
3b7d443c | 925 | { |
009ac3d3 RH |
926 | HOST_WIDE_INT val = INTVAL (operands[1]); |
927 | rtx reg = operands[0]; | |
9492393e KH |
928 | HOST_WIDE_INT sign = 1; |
929 | HOST_WIDE_INT amount; | |
590734b6 | 930 | rtx (*gen_add) (rtx, rtx, rtx); |
3b7d443c | 931 | |
9492393e KH |
932 | /* Force VAL to be positive so that we do not have to consider the |
933 | sign. */ | |
934 | if (val < 0) | |
3b7d443c | 935 | { |
9492393e KH |
936 | val = -val; |
937 | sign = -1; | |
938 | } | |
3b7d443c | 939 | |
3cee1a78 KH |
940 | switch (mode) |
941 | { | |
4e10a5a7 | 942 | case E_HImode: |
590734b6 | 943 | gen_add = gen_addhi3; |
3cee1a78 KH |
944 | break; |
945 | ||
4e10a5a7 | 946 | case E_SImode: |
590734b6 | 947 | gen_add = gen_addsi3; |
3cee1a78 KH |
948 | break; |
949 | ||
950 | default: | |
8c440872 | 951 | gcc_unreachable (); |
3cee1a78 KH |
952 | } |
953 | ||
9492393e | 954 | /* Try different amounts in descending order. */ |
27c1afd5 | 955 | for (amount = 4; amount > 0; amount /= 2) |
9492393e | 956 | { |
1a63219b | 957 | for (; val >= amount; val -= amount) |
590734b6 | 958 | emit_insn (gen_add (reg, reg, GEN_INT (sign * amount))); |
3b7d443c JL |
959 | } |
960 | ||
9492393e | 961 | return; |
3b7d443c JL |
962 | } |
963 | ||
07aae5c2 | 964 | /* Handle machine specific pragmas for compatibility with existing |
48837e29 | 965 | compilers for the H8/300. |
07aae5c2 | 966 | |
f411c849 | 967 | pragma saveall generates prologue/epilogue code which saves and |
07aae5c2 | 968 | restores all the registers on function entry. |
48837e29 | 969 | |
07aae5c2 SC |
970 | pragma interrupt saves and restores all registers, and exits with |
971 | an rte instruction rather than an rts. A pointer to a function | |
972 | with this attribute may be safely used in an interrupt vector. */ | |
48837e29 | 973 | |
8b97c5f8 | 974 | void |
cb713a8d | 975 | h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED) |
07aae5c2 | 976 | { |
e392d367 | 977 | pragma_interrupt = 1; |
8b97c5f8 | 978 | } |
05a81fe5 | 979 | |
8b97c5f8 | 980 | void |
cb713a8d | 981 | h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED) |
8b97c5f8 ZW |
982 | { |
983 | pragma_saveall = 1; | |
07aae5c2 | 984 | } |
8b97c5f8 | 985 | |
6783fdb7 RS |
986 | /* If the next function argument ARG is to be passed in a register, return |
987 | a reg RTX for the hard register in which to pass the argument. CUM | |
988 | represents the state after the last argument. If the argument is to | |
989 | be pushed, NULL_RTX is returned. | |
48837e29 | 990 | |
56f9413b NF |
991 | On the H8/300 all normal args are pushed, unless -mquickcall in which |
992 | case the first 3 arguments are passed in registers. */ | |
993 | ||
994 | static rtx | |
6783fdb7 | 995 | h8300_function_arg (cumulative_args_t cum_v, const function_arg_info &arg) |
07aae5c2 | 996 | { |
d5cc9181 JR |
997 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
998 | ||
0ea6f6a0 KH |
999 | static const char *const hand_list[] = { |
1000 | "__main", | |
1001 | "__cmpsi2", | |
1002 | "__divhi3", | |
1003 | "__modhi3", | |
1004 | "__udivhi3", | |
1005 | "__umodhi3", | |
1006 | "__divsi3", | |
1007 | "__modsi3", | |
1008 | "__udivsi3", | |
1009 | "__umodsi3", | |
1010 | "__mulhi3", | |
1011 | "__mulsi3", | |
1012 | "__reg_memcpy", | |
1013 | "__reg_memset", | |
1014 | "__ucmpsi2", | |
1015 | 0, | |
1016 | }; | |
1017 | ||
7192cbf1 | 1018 | rtx result = NULL_RTX; |
441d04c6 | 1019 | const char *fname; |
48837e29 DE |
1020 | int regpass = 0; |
1021 | ||
dd07092e | 1022 | /* Never pass unnamed arguments in registers. */ |
6783fdb7 | 1023 | if (!arg.named) |
7192cbf1 | 1024 | return NULL_RTX; |
dd07092e | 1025 | |
48837e29 DE |
1026 | /* Pass 3 regs worth of data in regs when user asked on the command line. */ |
1027 | if (TARGET_QUICKCALL) | |
1028 | regpass = 3; | |
1029 | ||
1030 | /* If calling hand written assembler, use 4 regs of args. */ | |
48837e29 DE |
1031 | if (cum->libcall) |
1032 | { | |
441d04c6 | 1033 | const char * const *p; |
48837e29 DE |
1034 | |
1035 | fname = XSTR (cum->libcall, 0); | |
1036 | ||
1037 | /* See if this libcall is one of the hand coded ones. */ | |
48837e29 DE |
1038 | for (p = hand_list; *p && strcmp (*p, fname) != 0; p++) |
1039 | ; | |
07aae5c2 | 1040 | |
48837e29 DE |
1041 | if (*p) |
1042 | regpass = 4; | |
1043 | } | |
1044 | ||
1045 | if (regpass) | |
1046 | { | |
6783fdb7 | 1047 | int size = arg.promoted_size_in_bytes (); |
15e0e275 KH |
1048 | if (size + cum->nbytes <= regpass * UNITS_PER_WORD |
1049 | && cum->nbytes / UNITS_PER_WORD <= 3) | |
6783fdb7 | 1050 | result = gen_rtx_REG (arg.mode, cum->nbytes / UNITS_PER_WORD); |
48837e29 | 1051 | } |
07aae5c2 | 1052 | |
48837e29 DE |
1053 | return result; |
1054 | } | |
56f9413b | 1055 | |
6930c98c | 1056 | /* Update the data in CUM to advance over argument ARG. */ |
56f9413b NF |
1057 | |
1058 | static void | |
6930c98c RS |
1059 | h8300_function_arg_advance (cumulative_args_t cum_v, |
1060 | const function_arg_info &arg) | |
56f9413b | 1061 | { |
d5cc9181 JR |
1062 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
1063 | ||
6930c98c RS |
1064 | cum->nbytes += ((arg.promoted_size_in_bytes () + UNITS_PER_WORD - 1) |
1065 | & -UNITS_PER_WORD); | |
56f9413b NF |
1066 | } |
1067 | ||
48837e29 | 1068 | \f |
88cb339e N |
1069 | /* Implements TARGET_REGISTER_MOVE_COST. |
1070 | ||
1071 | Any SI register-to-register move may need to be reloaded, | |
1072 | so inmplement h8300_register_move_cost to return > 2 so that reload never | |
1073 | shortcuts. */ | |
1074 | ||
1075 | static int | |
ef4bddc2 | 1076 | h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, |
88cb339e N |
1077 | reg_class_t from, reg_class_t to) |
1078 | { | |
1079 | if (from == MAC_REGS || to == MAC_REG) | |
1080 | return 6; | |
1081 | else | |
1082 | return 3; | |
1083 | } | |
1084 | ||
e9eba255 KH |
1085 | /* Compute the cost of an and insn. */ |
1086 | ||
3c50106f | 1087 | static int |
cb713a8d | 1088 | h8300_and_costs (rtx x) |
73cc75e9 KH |
1089 | { |
1090 | rtx operands[4]; | |
1091 | ||
1092 | if (GET_MODE (x) == QImode) | |
1093 | return 1; | |
1094 | ||
1095 | if (GET_MODE (x) != HImode | |
1096 | && GET_MODE (x) != SImode) | |
1097 | return 100; | |
1098 | ||
1099 | operands[0] = NULL; | |
beed8fc0 | 1100 | operands[1] = XEXP (x, 0); |
73cc75e9 KH |
1101 | operands[2] = XEXP (x, 1); |
1102 | operands[3] = x; | |
4f4ebda3 | 1103 | return compute_logical_op_length (GET_MODE (x), operands) / 2; |
73cc75e9 KH |
1104 | } |
1105 | ||
e9eba255 KH |
1106 | /* Compute the cost of a shift insn. */ |
1107 | ||
3c50106f | 1108 | static int |
cb713a8d | 1109 | h8300_shift_costs (rtx x) |
ae557002 KH |
1110 | { |
1111 | rtx operands[4]; | |
1112 | ||
1113 | if (GET_MODE (x) != QImode | |
1114 | && GET_MODE (x) != HImode | |
1115 | && GET_MODE (x) != SImode) | |
1116 | return 100; | |
1117 | ||
1118 | operands[0] = NULL; | |
1119 | operands[1] = NULL; | |
1120 | operands[2] = XEXP (x, 1); | |
1121 | operands[3] = x; | |
4f4ebda3 | 1122 | return compute_a_shift_length (NULL, operands) / 2; |
ae557002 | 1123 | } |
3c50106f | 1124 | |
e9eba255 KH |
1125 | /* Worker function for TARGET_RTX_COSTS. */ |
1126 | ||
3c50106f | 1127 | static bool |
e548c9df AM |
1128 | h8300_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code, |
1129 | int opno ATTRIBUTE_UNUSED, int *total, bool speed) | |
3c50106f | 1130 | { |
e548c9df AM |
1131 | int code = GET_CODE (x); |
1132 | ||
beed8fc0 AO |
1133 | if (TARGET_H8300SX && outer_code == MEM) |
1134 | { | |
1135 | /* Estimate the number of execution states needed to calculate | |
1136 | the address. */ | |
1137 | if (register_operand (x, VOIDmode) | |
1138 | || GET_CODE (x) == POST_INC | |
1139 | || GET_CODE (x) == POST_DEC | |
1140 | || CONSTANT_P (x)) | |
1141 | *total = 0; | |
1142 | else | |
1143 | *total = COSTS_N_INSNS (1); | |
1144 | return true; | |
1145 | } | |
1146 | ||
3c50106f RH |
1147 | switch (code) |
1148 | { | |
08dca707 KH |
1149 | case CONST_INT: |
1150 | { | |
1151 | HOST_WIDE_INT n = INTVAL (x); | |
1152 | ||
beed8fc0 AO |
1153 | if (TARGET_H8300SX) |
1154 | { | |
1155 | /* Constant operands need the same number of processor | |
1156 | states as register operands. Although we could try to | |
f40751dd | 1157 | use a size-based cost for !speed, the lack of |
beed8fc0 AO |
1158 | of a mode makes the results very unpredictable. */ |
1159 | *total = 0; | |
1160 | return true; | |
1161 | } | |
01512446 | 1162 | if (n >= -4 && n <= 4) |
08dca707 KH |
1163 | { |
1164 | switch ((int) n) | |
1165 | { | |
1166 | case 0: | |
1167 | *total = 0; | |
1168 | return true; | |
1169 | case 1: | |
1170 | case 2: | |
1171 | case -1: | |
1172 | case -2: | |
1173 | *total = 0 + (outer_code == SET); | |
1174 | return true; | |
1175 | case 4: | |
1176 | case -4: | |
27c1afd5 | 1177 | *total = 0 + (outer_code == SET); |
08dca707 KH |
1178 | return true; |
1179 | } | |
1180 | } | |
1181 | *total = 1; | |
1182 | return true; | |
1183 | } | |
1184 | ||
1185 | case CONST: | |
1186 | case LABEL_REF: | |
1187 | case SYMBOL_REF: | |
beed8fc0 AO |
1188 | if (TARGET_H8300SX) |
1189 | { | |
1190 | /* See comment for CONST_INT. */ | |
1191 | *total = 0; | |
1192 | return true; | |
1193 | } | |
08dca707 KH |
1194 | *total = 3; |
1195 | return true; | |
1196 | ||
1197 | case CONST_DOUBLE: | |
1198 | *total = 20; | |
1199 | return true; | |
1200 | ||
f90b7a5a | 1201 | case COMPARE: |
f80565da JL |
1202 | case NE: |
1203 | case EQ: | |
1204 | case GE: | |
1205 | case GT: | |
1206 | case LE: | |
1207 | case LT: | |
1208 | case GEU: | |
1209 | case GTU: | |
1210 | case LEU: | |
1211 | case LTU: | |
f90b7a5a PB |
1212 | if (XEXP (x, 1) == const0_rtx) |
1213 | *total = 0; | |
1214 | return false; | |
1215 | ||
3c50106f | 1216 | case AND: |
beed8fc0 AO |
1217 | if (!h8300_dst_operand (XEXP (x, 0), VOIDmode) |
1218 | || !h8300_src_operand (XEXP (x, 1), VOIDmode)) | |
1219 | return false; | |
3c50106f RH |
1220 | *total = COSTS_N_INSNS (h8300_and_costs (x)); |
1221 | return true; | |
1222 | ||
1223 | /* We say that MOD and DIV are so expensive because otherwise we'll | |
1224 | generate some really horrible code for division of a power of two. */ | |
1225 | case MOD: | |
1226 | case DIV: | |
beed8fc0 AO |
1227 | case UMOD: |
1228 | case UDIV: | |
1229 | if (TARGET_H8300SX) | |
1230 | switch (GET_MODE (x)) | |
1231 | { | |
4e10a5a7 RS |
1232 | case E_QImode: |
1233 | case E_HImode: | |
f40751dd | 1234 | *total = COSTS_N_INSNS (!speed ? 4 : 10); |
beed8fc0 AO |
1235 | return false; |
1236 | ||
4e10a5a7 | 1237 | case E_SImode: |
f40751dd | 1238 | *total = COSTS_N_INSNS (!speed ? 4 : 18); |
beed8fc0 AO |
1239 | return false; |
1240 | ||
1241 | default: | |
1242 | break; | |
1243 | } | |
1244 | *total = COSTS_N_INSNS (12); | |
3c50106f RH |
1245 | return true; |
1246 | ||
1247 | case MULT: | |
beed8fc0 AO |
1248 | if (TARGET_H8300SX) |
1249 | switch (GET_MODE (x)) | |
1250 | { | |
4e10a5a7 RS |
1251 | case E_QImode: |
1252 | case E_HImode: | |
beed8fc0 AO |
1253 | *total = COSTS_N_INSNS (2); |
1254 | return false; | |
1255 | ||
4e10a5a7 | 1256 | case E_SImode: |
beed8fc0 AO |
1257 | *total = COSTS_N_INSNS (5); |
1258 | return false; | |
1259 | ||
1260 | default: | |
1261 | break; | |
1262 | } | |
1263 | *total = COSTS_N_INSNS (4); | |
3c50106f RH |
1264 | return true; |
1265 | ||
1266 | case ASHIFT: | |
1267 | case ASHIFTRT: | |
1268 | case LSHIFTRT: | |
beed8fc0 AO |
1269 | if (h8sx_binary_shift_operator (x, VOIDmode)) |
1270 | { | |
1271 | *total = COSTS_N_INSNS (2); | |
1272 | return false; | |
1273 | } | |
1274 | else if (h8sx_unary_shift_operator (x, VOIDmode)) | |
1275 | { | |
1276 | *total = COSTS_N_INSNS (1); | |
1277 | return false; | |
1278 | } | |
3c50106f RH |
1279 | *total = COSTS_N_INSNS (h8300_shift_costs (x)); |
1280 | return true; | |
1281 | ||
1282 | case ROTATE: | |
1283 | case ROTATERT: | |
1284 | if (GET_MODE (x) == HImode) | |
1285 | *total = 2; | |
1286 | else | |
1287 | *total = 8; | |
1288 | return true; | |
1289 | ||
1290 | default: | |
beed8fc0 AO |
1291 | *total = COSTS_N_INSNS (1); |
1292 | return false; | |
3c50106f RH |
1293 | } |
1294 | } | |
48837e29 | 1295 | \f |
07aae5c2 SC |
1296 | /* Documentation for the machine specific operand escapes: |
1297 | ||
48837e29 DE |
1298 | 'E' like s but negative. |
1299 | 'F' like t but negative. | |
1300 | 'G' constant just the negative | |
15dc331e JL |
1301 | 'R' print operand as a byte:8 address if appropriate, else fall back to |
1302 | 'X' handling. | |
48837e29 | 1303 | 'S' print operand as a long word |
07aae5c2 | 1304 | 'T' print operand as a word |
48837e29 DE |
1305 | 'V' find the set bit, and print its number. |
1306 | 'W' find the clear bit, and print its number. | |
1307 | 'X' print operand as a byte | |
07aae5c2 | 1308 | 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8. |
15dc331e | 1309 | If this operand isn't a register, fall back to 'R' handling. |
48837e29 | 1310 | 'Z' print int & 7. |
b059c02a | 1311 | 'c' print the opcode corresponding to rtl |
da55315a | 1312 | 'e' first word of 32-bit value - if reg, then least reg. if mem |
48837e29 | 1313 | then least. if const then most sig word |
da55315a | 1314 | 'f' second word of 32-bit value - if reg, then biggest reg. if mem |
48837e29 | 1315 | then +2. if const then least sig word |
07aae5c2 SC |
1316 | 'j' print operand as condition code. |
1317 | 'k' print operand as reverse condition code. | |
beed8fc0 AO |
1318 | 'm' convert an integer operand to a size suffix (.b, .w or .l) |
1319 | 'o' print an integer without a leading '#' | |
da55315a KH |
1320 | 's' print as low byte of 16-bit value |
1321 | 't' print as high byte of 16-bit value | |
1322 | 'w' print as low byte of 32-bit value | |
1323 | 'x' print as 2nd byte of 32-bit value | |
1324 | 'y' print as 3rd byte of 32-bit value | |
1325 | 'z' print as msb of 32-bit value | |
48837e29 | 1326 | */ |
07aae5c2 SC |
1327 | |
1328 | /* Return assembly language string which identifies a comparison type. */ | |
1329 | ||
441d04c6 | 1330 | static const char * |
cb713a8d | 1331 | cond_string (enum rtx_code code) |
07aae5c2 SC |
1332 | { |
1333 | switch (code) | |
1334 | { | |
1335 | case NE: | |
1336 | return "ne"; | |
1337 | case EQ: | |
1338 | return "eq"; | |
1339 | case GE: | |
1340 | return "ge"; | |
1341 | case GT: | |
1342 | return "gt"; | |
1343 | case LE: | |
1344 | return "le"; | |
1345 | case LT: | |
1346 | return "lt"; | |
1347 | case GEU: | |
1348 | return "hs"; | |
1349 | case GTU: | |
1350 | return "hi"; | |
1351 | case LEU: | |
1352 | return "ls"; | |
1353 | case LTU: | |
1354 | return "lo"; | |
1355 | default: | |
8c440872 | 1356 | gcc_unreachable (); |
07aae5c2 SC |
1357 | } |
1358 | } | |
1359 | ||
1360 | /* Print operand X using operand code CODE to assembly language output file | |
1361 | FILE. */ | |
1362 | ||
88cb339e N |
1363 | static void |
1364 | h8300_print_operand (FILE *file, rtx x, int code) | |
07aae5c2 | 1365 | { |
269c14e1 | 1366 | /* This is used for communication between codes V,W,Z and Y. */ |
07aae5c2 SC |
1367 | static int bitint; |
1368 | ||
1369 | switch (code) | |
1370 | { | |
f46b8378 SKS |
1371 | case 'C': |
1372 | if (h8300_constant_length (x) == 2) | |
1373 | fprintf (file, ":16"); | |
1374 | else | |
1375 | fprintf (file, ":32"); | |
1376 | return; | |
48837e29 DE |
1377 | case 'E': |
1378 | switch (GET_CODE (x)) | |
1379 | { | |
1380 | case REG: | |
1381 | fprintf (file, "%sl", names_big[REGNO (x)]); | |
1382 | break; | |
1383 | case CONST_INT: | |
b47900aa | 1384 | fprintf (file, "#%ld", (-INTVAL (x)) & 0xff); |
48837e29 DE |
1385 | break; |
1386 | default: | |
8c440872 | 1387 | gcc_unreachable (); |
48837e29 DE |
1388 | } |
1389 | break; | |
1390 | case 'F': | |
1391 | switch (GET_CODE (x)) | |
1392 | { | |
1393 | case REG: | |
1394 | fprintf (file, "%sh", names_big[REGNO (x)]); | |
1395 | break; | |
1396 | case CONST_INT: | |
b47900aa | 1397 | fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8); |
48837e29 DE |
1398 | break; |
1399 | default: | |
8c440872 | 1400 | gcc_unreachable (); |
48837e29 DE |
1401 | } |
1402 | break; | |
07aae5c2 | 1403 | case 'G': |
8c440872 | 1404 | gcc_assert (GET_CODE (x) == CONST_INT); |
b47900aa | 1405 | fprintf (file, "#%ld", 0xff & (-INTVAL (x))); |
07aae5c2 | 1406 | break; |
48837e29 DE |
1407 | case 'S': |
1408 | if (GET_CODE (x) == REG) | |
1409 | fprintf (file, "%s", names_extended[REGNO (x)]); | |
07aae5c2 | 1410 | else |
48837e29 | 1411 | goto def; |
07aae5c2 | 1412 | break; |
48837e29 DE |
1413 | case 'T': |
1414 | if (GET_CODE (x) == REG) | |
1415 | fprintf (file, "%s", names_big[REGNO (x)]); | |
07aae5c2 | 1416 | else |
48837e29 | 1417 | goto def; |
07aae5c2 | 1418 | break; |
48837e29 | 1419 | case 'V': |
0f6b820c KP |
1420 | bitint = (INTVAL (x) & 0xffff); |
1421 | if ((exact_log2 ((bitint >> 8) & 0xff)) == -1) | |
1422 | bitint = exact_log2 (bitint & 0xff); | |
1423 | else | |
1424 | bitint = exact_log2 ((bitint >> 8) & 0xff); | |
8c440872 | 1425 | gcc_assert (bitint >= 0); |
4d4d89e2 | 1426 | fprintf (file, "#%d", bitint); |
07aae5c2 | 1427 | break; |
48837e29 | 1428 | case 'W': |
0f6b820c KP |
1429 | bitint = ((~INTVAL (x)) & 0xffff); |
1430 | if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 ) | |
1431 | bitint = exact_log2 (bitint & 0xff); | |
1432 | else | |
1433 | bitint = (exact_log2 ((bitint >> 8) & 0xff)); | |
8c440872 | 1434 | gcc_assert (bitint >= 0); |
4d4d89e2 | 1435 | fprintf (file, "#%d", bitint); |
07aae5c2 | 1436 | break; |
15dc331e | 1437 | case 'R': |
48837e29 DE |
1438 | case 'X': |
1439 | if (GET_CODE (x) == REG) | |
1440 | fprintf (file, "%s", byte_reg (x, 0)); | |
1441 | else | |
1442 | goto def; | |
1443 | break; | |
1444 | case 'Y': | |
8c440872 | 1445 | gcc_assert (bitint >= 0); |
48837e29 DE |
1446 | if (GET_CODE (x) == REG) |
1447 | fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l'); | |
1448 | else | |
88cb339e | 1449 | h8300_print_operand (file, x, 'R'); |
48837e29 DE |
1450 | bitint = -1; |
1451 | break; | |
1452 | case 'Z': | |
1453 | bitint = INTVAL (x); | |
07aae5c2 SC |
1454 | fprintf (file, "#%d", bitint & 7); |
1455 | break; | |
b059c02a KH |
1456 | case 'c': |
1457 | switch (GET_CODE (x)) | |
1458 | { | |
1459 | case IOR: | |
1460 | fprintf (file, "or"); | |
1461 | break; | |
1462 | case XOR: | |
1463 | fprintf (file, "xor"); | |
1464 | break; | |
5abfd1af KH |
1465 | case AND: |
1466 | fprintf (file, "and"); | |
1467 | break; | |
b059c02a KH |
1468 | default: |
1469 | break; | |
1470 | } | |
1471 | break; | |
07aae5c2 SC |
1472 | case 'e': |
1473 | switch (GET_CODE (x)) | |
1474 | { | |
1475 | case REG: | |
27c1afd5 | 1476 | fprintf (file, "%s", names_upper_extended[REGNO (x)]); |
07aae5c2 SC |
1477 | break; |
1478 | case MEM: | |
88cb339e | 1479 | h8300_print_operand (file, x, 0); |
07aae5c2 SC |
1480 | break; |
1481 | case CONST_INT: | |
b47900aa | 1482 | fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff)); |
07aae5c2 | 1483 | break; |
808fbfac JL |
1484 | case CONST_DOUBLE: |
1485 | { | |
1486 | long val; | |
34a72c33 | 1487 | REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val); |
441d04c6 | 1488 | fprintf (file, "#%ld", ((val >> 16) & 0xffff)); |
808fbfac JL |
1489 | break; |
1490 | } | |
07aae5c2 | 1491 | default: |
8c440872 | 1492 | gcc_unreachable (); |
07aae5c2 SC |
1493 | break; |
1494 | } | |
1495 | break; | |
07aae5c2 SC |
1496 | case 'f': |
1497 | switch (GET_CODE (x)) | |
1498 | { | |
1499 | case REG: | |
27c1afd5 | 1500 | fprintf (file, "%s", names_big[REGNO (x)]); |
07aae5c2 | 1501 | break; |
07aae5c2 | 1502 | case MEM: |
b72f00af | 1503 | x = adjust_address (x, HImode, 2); |
88cb339e | 1504 | h8300_print_operand (file, x, 0); |
07aae5c2 | 1505 | break; |
07aae5c2 | 1506 | case CONST_INT: |
b47900aa | 1507 | fprintf (file, "#%ld", INTVAL (x) & 0xffff); |
07aae5c2 | 1508 | break; |
808fbfac JL |
1509 | case CONST_DOUBLE: |
1510 | { | |
1511 | long val; | |
34a72c33 | 1512 | REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val); |
441d04c6 | 1513 | fprintf (file, "#%ld", (val & 0xffff)); |
808fbfac JL |
1514 | break; |
1515 | } | |
07aae5c2 | 1516 | default: |
8c440872 | 1517 | gcc_unreachable (); |
07aae5c2 SC |
1518 | } |
1519 | break; | |
07aae5c2 | 1520 | case 'j': |
f16897cb AL |
1521 | if (GET_CODE (x) == LT && GET_MODE (XEXP (x, 0)) == E_CCZNmode) |
1522 | fputs ("mi", file); | |
1523 | else if (GET_CODE (x) == GE && GET_MODE (XEXP (x, 0)) == E_CCZNmode) | |
1524 | fputs ("pl", file); | |
1525 | else | |
1526 | fputs (cond_string (GET_CODE (x)), file); | |
07aae5c2 | 1527 | break; |
07aae5c2 | 1528 | case 'k': |
f16897cb AL |
1529 | if (GET_CODE (x) == LT && GET_MODE (XEXP (x, 0)) == E_CCZNmode) |
1530 | fputs ("pl", file); | |
1531 | else if (GET_CODE (x) == GE && GET_MODE (XEXP (x, 0)) == E_CCZNmode) | |
1532 | fputs ("mi", file); | |
1533 | else | |
1534 | fputs (cond_string (reverse_condition (GET_CODE (x))), file); | |
07aae5c2 | 1535 | break; |
beed8fc0 | 1536 | case 'm': |
8c440872 NS |
1537 | gcc_assert (GET_CODE (x) == CONST_INT); |
1538 | switch (INTVAL (x)) | |
1539 | { | |
1540 | case 1: | |
1541 | fputs (".b", file); | |
1542 | break; | |
1543 | ||
1544 | case 2: | |
1545 | fputs (".w", file); | |
1546 | break; | |
1547 | ||
1548 | case 4: | |
1549 | fputs (".l", file); | |
1550 | break; | |
1551 | ||
1552 | default: | |
1553 | gcc_unreachable (); | |
1554 | } | |
beed8fc0 AO |
1555 | break; |
1556 | case 'o': | |
cc8ca59e | 1557 | h8300_print_operand_address (file, VOIDmode, x); |
beed8fc0 | 1558 | break; |
48837e29 DE |
1559 | case 's': |
1560 | if (GET_CODE (x) == CONST_INT) | |
b47900aa | 1561 | fprintf (file, "#%ld", (INTVAL (x)) & 0xff); |
64c9f2d9 | 1562 | else if (GET_CODE (x) == REG) |
48837e29 | 1563 | fprintf (file, "%s", byte_reg (x, 0)); |
64c9f2d9 JL |
1564 | else |
1565 | output_operand_lossage ("Expected register or constant integer."); | |
48837e29 DE |
1566 | break; |
1567 | case 't': | |
1568 | if (GET_CODE (x) == CONST_INT) | |
b47900aa | 1569 | fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff); |
64c9f2d9 | 1570 | else if (GET_CODE (x) == REG) |
48837e29 | 1571 | fprintf (file, "%s", byte_reg (x, 1)); |
64c9f2d9 JL |
1572 | else |
1573 | output_operand_lossage ("Expected register or constant integer."); | |
48837e29 | 1574 | break; |
48837e29 DE |
1575 | case 'w': |
1576 | if (GET_CODE (x) == CONST_INT) | |
b47900aa | 1577 | fprintf (file, "#%ld", INTVAL (x) & 0xff); |
64c9f2d9 | 1578 | else if (GET_CODE (x) == REG) |
27c1afd5 | 1579 | fprintf (file, "%s", byte_reg (x, 0)); |
64c9f2d9 JL |
1580 | else |
1581 | output_operand_lossage ("Expected register or constant integer."); | |
48837e29 DE |
1582 | break; |
1583 | case 'x': | |
1584 | if (GET_CODE (x) == CONST_INT) | |
b47900aa | 1585 | fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff); |
64c9f2d9 | 1586 | else if (GET_CODE (x) == REG) |
27c1afd5 | 1587 | fprintf (file, "%s", byte_reg (x, 1)); |
64c9f2d9 JL |
1588 | else |
1589 | output_operand_lossage ("Expected register or constant integer."); | |
48837e29 DE |
1590 | break; |
1591 | case 'y': | |
1592 | if (GET_CODE (x) == CONST_INT) | |
b47900aa | 1593 | fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff); |
64c9f2d9 | 1594 | else if (GET_CODE (x) == REG) |
48837e29 | 1595 | fprintf (file, "%s", byte_reg (x, 0)); |
64c9f2d9 JL |
1596 | else |
1597 | output_operand_lossage ("Expected register or constant integer."); | |
48837e29 DE |
1598 | break; |
1599 | case 'z': | |
1600 | if (GET_CODE (x) == CONST_INT) | |
b47900aa | 1601 | fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff); |
64c9f2d9 | 1602 | else if (GET_CODE (x) == REG) |
48837e29 | 1603 | fprintf (file, "%s", byte_reg (x, 1)); |
64c9f2d9 JL |
1604 | else |
1605 | output_operand_lossage ("Expected register or constant integer."); | |
48837e29 DE |
1606 | break; |
1607 | ||
07aae5c2 | 1608 | default: |
48837e29 | 1609 | def: |
07aae5c2 SC |
1610 | switch (GET_CODE (x)) |
1611 | { | |
1612 | case REG: | |
48837e29 DE |
1613 | switch (GET_MODE (x)) |
1614 | { | |
4e10a5a7 | 1615 | case E_QImode: |
269c14e1 | 1616 | #if 0 /* Is it asm ("mov.b %0,r2l", ...) */ |
48837e29 DE |
1617 | fprintf (file, "%s", byte_reg (x, 0)); |
1618 | #else /* ... or is it asm ("mov.b %0l,r2l", ...) */ | |
1619 | fprintf (file, "%s", names_big[REGNO (x)]); | |
1620 | #endif | |
1621 | break; | |
4e10a5a7 | 1622 | case E_HImode: |
48837e29 DE |
1623 | fprintf (file, "%s", names_big[REGNO (x)]); |
1624 | break; | |
4e10a5a7 RS |
1625 | case E_SImode: |
1626 | case E_SFmode: | |
48837e29 DE |
1627 | fprintf (file, "%s", names_extended[REGNO (x)]); |
1628 | break; | |
1629 | default: | |
8c440872 | 1630 | gcc_unreachable (); |
48837e29 | 1631 | } |
07aae5c2 SC |
1632 | break; |
1633 | ||
1634 | case MEM: | |
87e4ee91 KH |
1635 | { |
1636 | rtx addr = XEXP (x, 0); | |
1637 | ||
1638 | fprintf (file, "@"); | |
cc8ca59e | 1639 | output_address (GET_MODE (x), addr); |
87e4ee91 | 1640 | |
beed8fc0 AO |
1641 | /* Add a length suffix to constant addresses. Although this |
1642 | is often unnecessary, it helps to avoid ambiguity in the | |
1643 | syntax of mova. If we wrote an insn like: | |
1644 | ||
1645 | mova/w.l @(1,@foo.b),er0 | |
1646 | ||
1647 | then .b would be considered part of the symbol name. | |
1648 | Adding a length after foo will avoid this. */ | |
1649 | if (CONSTANT_P (addr)) | |
1650 | switch (code) | |
1651 | { | |
1652 | case 'R': | |
1653 | /* Used for mov.b and bit operations. */ | |
1654 | if (h8300_eightbit_constant_address_p (addr)) | |
1655 | { | |
1656 | fprintf (file, ":8"); | |
1657 | break; | |
1658 | } | |
1659 | ||
451c15c2 JL |
1660 | /* FALLTHRU */ |
1661 | ||
1662 | /* We should not get here if we are processing bit | |
1663 | operations on H8/300 or H8/300H because 'U' | |
1664 | constraint does not allow bit operations on the | |
1665 | tiny area on these machines. */ | |
beed8fc0 AO |
1666 | |
1667 | case 'X': | |
1668 | case 'T': | |
1669 | case 'S': | |
1670 | if (h8300_constant_length (addr) == 2) | |
1671 | fprintf (file, ":16"); | |
1672 | else | |
1673 | fprintf (file, ":32"); | |
1674 | break; | |
1675 | default: | |
1676 | break; | |
1677 | } | |
87e4ee91 | 1678 | } |
07aae5c2 SC |
1679 | break; |
1680 | ||
1681 | case CONST_INT: | |
1682 | case SYMBOL_REF: | |
1683 | case CONST: | |
1684 | case LABEL_REF: | |
1685 | fprintf (file, "#"); | |
cc8ca59e | 1686 | h8300_print_operand_address (file, VOIDmode, x); |
07aae5c2 | 1687 | break; |
808fbfac JL |
1688 | case CONST_DOUBLE: |
1689 | { | |
1690 | long val; | |
34a72c33 | 1691 | REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val); |
441d04c6 | 1692 | fprintf (file, "#%ld", val); |
808fbfac JL |
1693 | break; |
1694 | } | |
441d04c6 KG |
1695 | default: |
1696 | break; | |
07aae5c2 SC |
1697 | } |
1698 | } | |
1699 | } | |
1700 | ||
88cb339e N |
1701 | /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */ |
1702 | ||
1703 | static bool | |
1704 | h8300_print_operand_punct_valid_p (unsigned char code) | |
1705 | { | |
1706 | return (code == '#'); | |
1707 | } | |
1708 | ||
07aae5c2 SC |
1709 | /* Output assembly language output for the address ADDR to FILE. */ |
1710 | ||
88cb339e | 1711 | static void |
cc8ca59e | 1712 | h8300_print_operand_address (FILE *file, machine_mode mode, rtx addr) |
07aae5c2 | 1713 | { |
beed8fc0 AO |
1714 | rtx index; |
1715 | int size; | |
1716 | ||
07aae5c2 SC |
1717 | switch (GET_CODE (addr)) |
1718 | { | |
1719 | case REG: | |
48837e29 | 1720 | fprintf (file, "%s", h8_reg_names[REGNO (addr)]); |
07aae5c2 SC |
1721 | break; |
1722 | ||
1723 | case PRE_DEC: | |
48837e29 | 1724 | fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]); |
07aae5c2 SC |
1725 | break; |
1726 | ||
1727 | case POST_INC: | |
48837e29 | 1728 | fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]); |
07aae5c2 SC |
1729 | break; |
1730 | ||
beed8fc0 AO |
1731 | case PRE_INC: |
1732 | fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]); | |
1733 | break; | |
1734 | ||
1735 | case POST_DEC: | |
1736 | fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]); | |
1737 | break; | |
1738 | ||
07aae5c2 SC |
1739 | case PLUS: |
1740 | fprintf (file, "("); | |
beed8fc0 AO |
1741 | |
1742 | index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size); | |
1743 | if (GET_CODE (index) == REG) | |
07aae5c2 SC |
1744 | { |
1745 | /* reg,foo */ | |
cc8ca59e | 1746 | h8300_print_operand_address (file, mode, XEXP (addr, 1)); |
07aae5c2 | 1747 | fprintf (file, ","); |
beed8fc0 AO |
1748 | switch (size) |
1749 | { | |
1750 | case 0: | |
cc8ca59e | 1751 | h8300_print_operand_address (file, mode, index); |
beed8fc0 AO |
1752 | break; |
1753 | ||
1754 | case 1: | |
88cb339e | 1755 | h8300_print_operand (file, index, 'X'); |
beed8fc0 AO |
1756 | fputs (".b", file); |
1757 | break; | |
1758 | ||
1759 | case 2: | |
88cb339e | 1760 | h8300_print_operand (file, index, 'T'); |
beed8fc0 AO |
1761 | fputs (".w", file); |
1762 | break; | |
1763 | ||
1764 | case 4: | |
88cb339e | 1765 | h8300_print_operand (file, index, 'S'); |
beed8fc0 AO |
1766 | fputs (".l", file); |
1767 | break; | |
1768 | } | |
88cb339e | 1769 | /* h8300_print_operand_address (file, XEXP (addr, 0)); */ |
07aae5c2 SC |
1770 | } |
1771 | else | |
1772 | { | |
1773 | /* foo+k */ | |
cc8ca59e | 1774 | h8300_print_operand_address (file, mode, XEXP (addr, 0)); |
07aae5c2 | 1775 | fprintf (file, "+"); |
cc8ca59e | 1776 | h8300_print_operand_address (file, mode, XEXP (addr, 1)); |
07aae5c2 SC |
1777 | } |
1778 | fprintf (file, ")"); | |
1779 | break; | |
1780 | ||
1781 | case CONST_INT: | |
48837e29 | 1782 | { |
48837e29 | 1783 | int n = INTVAL (addr); |
7a770d8b | 1784 | fprintf (file, "%d", n); |
48837e29 DE |
1785 | break; |
1786 | } | |
07aae5c2 SC |
1787 | |
1788 | default: | |
1789 | output_addr_const (file, addr); | |
1790 | break; | |
1791 | } | |
1792 | } | |
1793 | \f | |
07aae5c2 SC |
1794 | /* Output all insn addresses and their sizes into the assembly language |
1795 | output file. This is helpful for debugging whether the length attributes | |
1796 | in the md file are correct. This is not meant to be a user selectable | |
1797 | option. */ | |
1798 | ||
1799 | void | |
e7041fcc | 1800 | final_prescan_insn (rtx_insn *insn, rtx *operand ATTRIBUTE_UNUSED, |
cb713a8d | 1801 | int num_operands ATTRIBUTE_UNUSED) |
07aae5c2 SC |
1802 | { |
1803 | /* This holds the last insn address. */ | |
1804 | static int last_insn_address = 0; | |
1805 | ||
7798db98 | 1806 | const int uid = INSN_UID (insn); |
07aae5c2 SC |
1807 | |
1808 | if (TARGET_ADDRESSES) | |
1809 | { | |
9d98a694 AO |
1810 | fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid), |
1811 | INSN_ADDRESSES (uid) - last_insn_address); | |
1812 | last_insn_address = INSN_ADDRESSES (uid); | |
07aae5c2 SC |
1813 | } |
1814 | } | |
1815 | ||
48837e29 DE |
1816 | /* Prepare for an SI sized move. */ |
1817 | ||
1818 | int | |
1a793acf | 1819 | h8300_expand_movsi (rtx operands[]) |
07aae5c2 | 1820 | { |
48837e29 DE |
1821 | rtx src = operands[1]; |
1822 | rtx dst = operands[0]; | |
1823 | if (!reload_in_progress && !reload_completed) | |
1824 | { | |
1825 | if (!register_operand (dst, GET_MODE (dst))) | |
1826 | { | |
1827 | rtx tmp = gen_reg_rtx (GET_MODE (dst)); | |
1828 | emit_move_insn (tmp, src); | |
1829 | operands[1] = tmp; | |
1830 | } | |
1831 | } | |
1832 | return 0; | |
1833 | } | |
1834 | ||
7b5cbb57 AS |
1835 | /* Given FROM and TO register numbers, say whether this elimination is allowed. |
1836 | Frame pointer elimination is automatically handled. | |
1837 | ||
1838 | For the h8300, if frame pointer elimination is being done, we would like to | |
1839 | convert ap and rp into sp, not fp. | |
1840 | ||
1841 | All other eliminations are valid. */ | |
1842 | ||
1843 | static bool | |
1844 | h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) | |
1845 | { | |
1846 | return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true); | |
1847 | } | |
1848 | ||
5efd84c5 NF |
1849 | /* Conditionally modify register usage based on target flags. */ |
1850 | ||
1851 | static void | |
1852 | h8300_conditional_register_usage (void) | |
1853 | { | |
1854 | if (!TARGET_MAC) | |
1855 | fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1; | |
1856 | } | |
1857 | ||
48837e29 | 1858 | /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET). |
07e4d94e KH |
1859 | Define the offset between two registers, one to be eliminated, and |
1860 | the other its replacement, at the start of a routine. */ | |
07aae5c2 | 1861 | |
48837e29 | 1862 | int |
cb713a8d | 1863 | h8300_initial_elimination_offset (int from, int to) |
48837e29 | 1864 | { |
d18ad191 KH |
1865 | /* The number of bytes that the return address takes on the stack. */ |
1866 | int pc_size = POINTER_SIZE / BITS_PER_UNIT; | |
48837e29 | 1867 | |
1807b726 KH |
1868 | /* The number of bytes that the saved frame pointer takes on the stack. */ |
1869 | int fp_size = frame_pointer_needed * UNITS_PER_WORD; | |
1870 | ||
1871 | /* The number of bytes that the saved registers, excluding the frame | |
1872 | pointer, take on the stack. */ | |
1873 | int saved_regs_size = 0; | |
48837e29 | 1874 | |
1807b726 KH |
1875 | /* The number of bytes that the locals takes on the stack. */ |
1876 | int frame_size = round_frame_size (get_frame_size ()); | |
48837e29 | 1877 | |
1807b726 | 1878 | int regno; |
48837e29 | 1879 | |
1807b726 KH |
1880 | for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++) |
1881 | if (WORD_REG_USED (regno)) | |
1882 | saved_regs_size += UNITS_PER_WORD; | |
48837e29 | 1883 | |
1807b726 KH |
1884 | /* Adjust saved_regs_size because the above loop took the frame |
1885 | pointer int account. */ | |
1886 | saved_regs_size -= fp_size; | |
39ba95b5 | 1887 | |
8c440872 | 1888 | switch (to) |
1807b726 | 1889 | { |
8c440872 | 1890 | case HARD_FRAME_POINTER_REGNUM: |
1807b726 KH |
1891 | switch (from) |
1892 | { | |
1893 | case ARG_POINTER_REGNUM: | |
1894 | return pc_size + fp_size; | |
1895 | case RETURN_ADDRESS_POINTER_REGNUM: | |
1896 | return fp_size; | |
1897 | case FRAME_POINTER_REGNUM: | |
1898 | return -saved_regs_size; | |
1899 | default: | |
8c440872 | 1900 | gcc_unreachable (); |
1807b726 | 1901 | } |
8c440872 NS |
1902 | break; |
1903 | case STACK_POINTER_REGNUM: | |
1807b726 KH |
1904 | switch (from) |
1905 | { | |
1906 | case ARG_POINTER_REGNUM: | |
1907 | return pc_size + saved_regs_size + frame_size; | |
1908 | case RETURN_ADDRESS_POINTER_REGNUM: | |
1909 | return saved_regs_size + frame_size; | |
1910 | case FRAME_POINTER_REGNUM: | |
1911 | return frame_size; | |
1912 | default: | |
8c440872 | 1913 | gcc_unreachable (); |
1807b726 | 1914 | } |
8c440872 NS |
1915 | break; |
1916 | default: | |
1917 | gcc_unreachable (); | |
1807b726 | 1918 | } |
8c440872 | 1919 | gcc_unreachable (); |
48837e29 DE |
1920 | } |
1921 | ||
e9eba255 KH |
1922 | /* Worker function for RETURN_ADDR_RTX. */ |
1923 | ||
1aae372e | 1924 | rtx |
cb713a8d | 1925 | h8300_return_addr_rtx (int count, rtx frame) |
1aae372e JL |
1926 | { |
1927 | rtx ret; | |
1928 | ||
1929 | if (count == 0) | |
1930 | ret = gen_rtx_MEM (Pmode, | |
1931 | gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM)); | |
1932 | else if (flag_omit_frame_pointer) | |
1933 | return (rtx) 0; | |
1934 | else | |
1935 | ret = gen_rtx_MEM (Pmode, | |
1936 | memory_address (Pmode, | |
0a81f074 RS |
1937 | plus_constant (Pmode, frame, |
1938 | UNITS_PER_WORD))); | |
1aae372e JL |
1939 | set_mem_alias_set (ret, get_frame_alias_set ()); |
1940 | return ret; | |
1941 | } | |
1942 | ||
f16897cb AL |
1943 | |
1944 | machine_mode | |
1945 | h8300_select_cc_mode (enum rtx_code cond, rtx op0, rtx op1) | |
1946 | { | |
1947 | if (op1 == const0_rtx | |
1948 | && (cond == EQ || cond == NE || cond == LT || cond == GE) | |
1949 | && (GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS | |
1950 | || GET_CODE (op0) == NEG || GET_CODE (op0) == AND | |
1951 | || GET_CODE (op0) == IOR || GET_CODE (op0) == XOR | |
1952 | || GET_CODE (op0) == NOT || GET_CODE (op0) == ASHIFT | |
1953 | || GET_CODE (op0) == REG || GET_CODE (op0) == MULT)) | |
1954 | return CCZNmode; | |
1955 | ||
1956 | return CCmode; | |
1957 | } | |
1958 | ||
beed8fc0 AO |
1959 | \f |
1960 | /* Given that X occurs in an address of the form (plus X constant), | |
1961 | return the part of X that is expected to be a register. There are | |
1962 | four kinds of addressing mode to recognize: | |
1963 | ||
1964 | @(dd,Rn) | |
1965 | @(dd,RnL.b) | |
1966 | @(dd,Rn.w) | |
1967 | @(dd,ERn.l) | |
1968 | ||
1969 | If SIZE is nonnull, and the address is one of the last three forms, | |
1970 | set *SIZE to the index multiplication factor. Set it to 0 for | |
1971 | plain @(dd,Rn) addresses. | |
1972 | ||
1973 | MODE is the mode of the value being accessed. It can be VOIDmode | |
1974 | if the address is known to be valid, but its mode is unknown. */ | |
1975 | ||
f52d97da | 1976 | static rtx |
ef4bddc2 | 1977 | h8300_get_index (rtx x, machine_mode mode, int *size) |
beed8fc0 AO |
1978 | { |
1979 | int dummy, factor; | |
1980 | ||
1981 | if (size == 0) | |
1982 | size = &dummy; | |
1983 | ||
1984 | factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode)); | |
1985 | if (TARGET_H8300SX | |
1986 | && factor <= 4 | |
1987 | && (mode == VOIDmode | |
1988 | || GET_MODE_CLASS (mode) == MODE_INT | |
1989 | || GET_MODE_CLASS (mode) == MODE_FLOAT)) | |
1990 | { | |
1991 | if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND) | |
1992 | { | |
1993 | /* When accessing byte-sized values, the index can be | |
1994 | a zero-extended QImode or HImode register. */ | |
1995 | *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0))); | |
1996 | return XEXP (x, 0); | |
1997 | } | |
1998 | else | |
1999 | { | |
2000 | /* We're looking for addresses of the form: | |
2001 | ||
2002 | (mult X I) | |
2003 | or (mult (zero_extend X) I) | |
2004 | ||
2005 | where I is the size of the operand being accessed. | |
2006 | The canonical form of the second expression is: | |
2007 | ||
2008 | (and (mult (subreg X) I) J) | |
2009 | ||
2010 | where J == GET_MODE_MASK (GET_MODE (X)) * I. */ | |
2011 | rtx index; | |
2012 | ||
2013 | if (GET_CODE (x) == AND | |
2014 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2015 | && (factor == 0 | |
2016 | || INTVAL (XEXP (x, 1)) == 0xff * factor | |
2017 | || INTVAL (XEXP (x, 1)) == 0xffff * factor)) | |
2018 | { | |
2019 | index = XEXP (x, 0); | |
2020 | *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1); | |
2021 | } | |
2022 | else | |
2023 | { | |
2024 | index = x; | |
2025 | *size = 4; | |
2026 | } | |
2027 | ||
2028 | if (GET_CODE (index) == MULT | |
2029 | && GET_CODE (XEXP (index, 1)) == CONST_INT | |
2030 | && (factor == 0 || factor == INTVAL (XEXP (index, 1)))) | |
2031 | return XEXP (index, 0); | |
2032 | } | |
2033 | } | |
2034 | *size = 0; | |
2035 | return x; | |
2036 | } | |
2037 | \f | |
f52d97da AS |
2038 | /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. |
2039 | ||
2040 | On the H8/300, the predecrement and postincrement address depend thus | |
2041 | (the amount of decrement or increment being the length of the operand). */ | |
2042 | ||
2043 | static bool | |
5bfed9a9 GJL |
2044 | h8300_mode_dependent_address_p (const_rtx addr, |
2045 | addr_space_t as ATTRIBUTE_UNUSED) | |
f52d97da AS |
2046 | { |
2047 | if (GET_CODE (addr) == PLUS | |
2048 | && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0)) | |
2049 | return true; | |
2050 | ||
2051 | return false; | |
2052 | } | |
2053 | \f | |
beed8fc0 AO |
2054 | static const h8300_length_table addb_length_table = |
2055 | { | |
2056 | /* #xx Rs @aa @Rs @xx */ | |
2057 | { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */ | |
2058 | { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */ | |
2059 | { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */ | |
2060 | { 6, 4, 4, 4, 6 } /* add.b xx,@xx */ | |
2061 | }; | |
2062 | ||
2063 | static const h8300_length_table addw_length_table = | |
2064 | { | |
2065 | /* #xx Rs @aa @Rs @xx */ | |
2066 | { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */ | |
2067 | { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */ | |
2068 | { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */ | |
2069 | { 4, 4, 4, 4, 6 } /* add.w xx,@xx */ | |
2070 | }; | |
2071 | ||
2072 | static const h8300_length_table addl_length_table = | |
2073 | { | |
2074 | /* #xx Rs @aa @Rs @xx */ | |
2075 | { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */ | |
2076 | { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */ | |
2077 | { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */ | |
2078 | { 4, 4, 6, 6, 6 } /* add.l xx,@xx */ | |
2079 | }; | |
2080 | ||
2081 | #define logicb_length_table addb_length_table | |
2082 | #define logicw_length_table addw_length_table | |
2083 | ||
2084 | static const h8300_length_table logicl_length_table = | |
2085 | { | |
2086 | /* #xx Rs @aa @Rs @xx */ | |
2087 | { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */ | |
2088 | { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */ | |
2089 | { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */ | |
2090 | { 4, 4, 6, 6, 6 } /* and.l xx,@xx */ | |
2091 | }; | |
2092 | ||
2093 | static const h8300_length_table movb_length_table = | |
2094 | { | |
2095 | /* #xx Rs @aa @Rs @xx */ | |
2096 | { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */ | |
2097 | { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */ | |
2098 | { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */ | |
2099 | { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */ | |
2100 | }; | |
2101 | ||
2102 | #define movw_length_table movb_length_table | |
2103 | ||
2104 | static const h8300_length_table movl_length_table = | |
2105 | { | |
2106 | /* #xx Rs @aa @Rs @xx */ | |
2107 | { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */ | |
2108 | { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */ | |
2109 | { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */ | |
2110 | { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */ | |
2111 | }; | |
2112 | ||
2113 | /* Return the size of the given address or displacement constant. */ | |
2114 | ||
2115 | static unsigned int | |
2116 | h8300_constant_length (rtx constant) | |
2117 | { | |
2118 | /* Check for (@d:16,Reg). */ | |
2119 | if (GET_CODE (constant) == CONST_INT | |
2120 | && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff)) | |
2121 | return 2; | |
2122 | ||
2123 | /* Check for (@d:16,Reg) in cases where the displacement is | |
2124 | an absolute address. */ | |
2125 | if (Pmode == HImode || h8300_tiny_constant_address_p (constant)) | |
2126 | return 2; | |
2127 | ||
2128 | return 4; | |
2129 | } | |
2130 | ||
2131 | /* Return the size of a displacement field in address ADDR, which should | |
2132 | have the form (plus X constant). SIZE is the number of bytes being | |
2133 | accessed. */ | |
2134 | ||
2135 | static unsigned int | |
2136 | h8300_displacement_length (rtx addr, int size) | |
2137 | { | |
2138 | rtx offset; | |
2139 | ||
2140 | offset = XEXP (addr, 1); | |
2141 | ||
2142 | /* Check for @(d:2,Reg). */ | |
2143 | if (register_operand (XEXP (addr, 0), VOIDmode) | |
2144 | && GET_CODE (offset) == CONST_INT | |
2145 | && (INTVAL (offset) == size | |
2146 | || INTVAL (offset) == size * 2 | |
2147 | || INTVAL (offset) == size * 3)) | |
2148 | return 0; | |
2149 | ||
2150 | return h8300_constant_length (offset); | |
2151 | } | |
2152 | ||
0a2aaacc KG |
2153 | /* Store the class of operand OP in *OPCLASS and return the length of any |
2154 | extra operand fields. SIZE is the number of bytes in OP. OPCLASS | |
beed8fc0 AO |
2155 | can be null if only the length is needed. */ |
2156 | ||
2157 | static unsigned int | |
0a2aaacc | 2158 | h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass) |
beed8fc0 AO |
2159 | { |
2160 | enum h8300_operand_class dummy; | |
2161 | ||
0a2aaacc KG |
2162 | if (opclass == 0) |
2163 | opclass = &dummy; | |
beed8fc0 AO |
2164 | |
2165 | if (CONSTANT_P (op)) | |
2166 | { | |
0a2aaacc | 2167 | *opclass = H8OP_IMMEDIATE; |
beed8fc0 AO |
2168 | |
2169 | /* Byte-sized immediates are stored in the opcode fields. */ | |
2170 | if (size == 1) | |
2171 | return 0; | |
2172 | ||
2173 | /* If this is a 32-bit instruction, see whether the constant | |
2174 | will fit into a 16-bit immediate field. */ | |
2175 | if (TARGET_H8300SX | |
2176 | && size == 4 | |
2177 | && GET_CODE (op) == CONST_INT | |
2178 | && IN_RANGE (INTVAL (op), 0, 0xffff)) | |
2179 | return 2; | |
2180 | ||
2181 | return size; | |
2182 | } | |
2183 | else if (GET_CODE (op) == MEM) | |
2184 | { | |
2185 | op = XEXP (op, 0); | |
2186 | if (CONSTANT_P (op)) | |
2187 | { | |
0a2aaacc | 2188 | *opclass = H8OP_MEM_ABSOLUTE; |
beed8fc0 AO |
2189 | return h8300_constant_length (op); |
2190 | } | |
2191 | else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1))) | |
2192 | { | |
0a2aaacc | 2193 | *opclass = H8OP_MEM_COMPLEX; |
beed8fc0 AO |
2194 | return h8300_displacement_length (op, size); |
2195 | } | |
2196 | else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC) | |
2197 | { | |
0a2aaacc | 2198 | *opclass = H8OP_MEM_COMPLEX; |
beed8fc0 AO |
2199 | return 0; |
2200 | } | |
2201 | else if (register_operand (op, VOIDmode)) | |
2202 | { | |
0a2aaacc | 2203 | *opclass = H8OP_MEM_BASE; |
beed8fc0 AO |
2204 | return 0; |
2205 | } | |
2206 | } | |
8c440872 | 2207 | gcc_assert (register_operand (op, VOIDmode)); |
0a2aaacc | 2208 | *opclass = H8OP_REGISTER; |
8c440872 | 2209 | return 0; |
beed8fc0 AO |
2210 | } |
2211 | ||
2212 | /* Return the length of the instruction described by TABLE given that | |
2213 | its operands are OP1 and OP2. OP1 must be an h8300_dst_operand | |
2214 | and OP2 must be an h8300_src_operand. */ | |
2215 | ||
2216 | static unsigned int | |
2217 | h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table) | |
2218 | { | |
2219 | enum h8300_operand_class op1_class, op2_class; | |
2220 | unsigned int size, immediate_length; | |
2221 | ||
2222 | size = GET_MODE_SIZE (GET_MODE (op1)); | |
2223 | immediate_length = (h8300_classify_operand (op1, size, &op1_class) | |
2224 | + h8300_classify_operand (op2, size, &op2_class)); | |
2225 | return immediate_length + (*table)[op1_class - 1][op2_class]; | |
2226 | } | |
2227 | ||
2228 | /* Return the length of a unary instruction such as neg or not given that | |
2229 | its operand is OP. */ | |
2230 | ||
2231 | unsigned int | |
2232 | h8300_unary_length (rtx op) | |
2233 | { | |
0a2aaacc | 2234 | enum h8300_operand_class opclass; |
beed8fc0 AO |
2235 | unsigned int size, operand_length; |
2236 | ||
2237 | size = GET_MODE_SIZE (GET_MODE (op)); | |
0a2aaacc KG |
2238 | operand_length = h8300_classify_operand (op, size, &opclass); |
2239 | switch (opclass) | |
beed8fc0 AO |
2240 | { |
2241 | case H8OP_REGISTER: | |
2242 | return 2; | |
2243 | ||
2244 | case H8OP_MEM_BASE: | |
2245 | return (size == 4 ? 6 : 4); | |
2246 | ||
2247 | case H8OP_MEM_ABSOLUTE: | |
2248 | return operand_length + (size == 4 ? 6 : 4); | |
2249 | ||
2250 | case H8OP_MEM_COMPLEX: | |
2251 | return operand_length + 6; | |
2252 | ||
2253 | default: | |
8c440872 | 2254 | gcc_unreachable (); |
beed8fc0 AO |
2255 | } |
2256 | } | |
2257 | ||
2258 | /* Likewise short immediate instructions such as add.w #xx:3,OP. */ | |
2259 | ||
2260 | static unsigned int | |
2261 | h8300_short_immediate_length (rtx op) | |
2262 | { | |
0a2aaacc | 2263 | enum h8300_operand_class opclass; |
beed8fc0 AO |
2264 | unsigned int size, operand_length; |
2265 | ||
2266 | size = GET_MODE_SIZE (GET_MODE (op)); | |
0a2aaacc | 2267 | operand_length = h8300_classify_operand (op, size, &opclass); |
beed8fc0 | 2268 | |
0a2aaacc | 2269 | switch (opclass) |
beed8fc0 AO |
2270 | { |
2271 | case H8OP_REGISTER: | |
2272 | return 2; | |
2273 | ||
2274 | case H8OP_MEM_BASE: | |
2275 | case H8OP_MEM_ABSOLUTE: | |
2276 | case H8OP_MEM_COMPLEX: | |
2277 | return 4 + operand_length; | |
2278 | ||
2279 | default: | |
8c440872 | 2280 | gcc_unreachable (); |
beed8fc0 AO |
2281 | } |
2282 | } | |
2283 | ||
2284 | /* Likewise bitfield load and store instructions. */ | |
48837e29 | 2285 | |
beed8fc0 AO |
2286 | static unsigned int |
2287 | h8300_bitfield_length (rtx op, rtx op2) | |
2288 | { | |
0a2aaacc | 2289 | enum h8300_operand_class opclass; |
beed8fc0 AO |
2290 | unsigned int size, operand_length; |
2291 | ||
2292 | if (GET_CODE (op) == REG) | |
2293 | op = op2; | |
8c440872 | 2294 | gcc_assert (GET_CODE (op) != REG); |
beed8fc0 AO |
2295 | |
2296 | size = GET_MODE_SIZE (GET_MODE (op)); | |
0a2aaacc | 2297 | operand_length = h8300_classify_operand (op, size, &opclass); |
beed8fc0 | 2298 | |
0a2aaacc | 2299 | switch (opclass) |
beed8fc0 AO |
2300 | { |
2301 | case H8OP_MEM_BASE: | |
2302 | case H8OP_MEM_ABSOLUTE: | |
2303 | case H8OP_MEM_COMPLEX: | |
2304 | return 4 + operand_length; | |
2305 | ||
2306 | default: | |
8c440872 | 2307 | gcc_unreachable (); |
07aae5c2 | 2308 | } |
48837e29 DE |
2309 | } |
2310 | ||
beed8fc0 | 2311 | /* Calculate the length of general binary instruction INSN using TABLE. */ |
8ccf5d5f | 2312 | |
beed8fc0 | 2313 | static unsigned int |
e7041fcc | 2314 | h8300_binary_length (rtx_insn *insn, const h8300_length_table *table) |
8ccf5d5f | 2315 | { |
beed8fc0 | 2316 | rtx set; |
f16897cb AL |
2317 | rtx pattern; |
2318 | ||
2319 | if (GET_CODE (insn) != INSN) | |
2320 | gcc_unreachable (); | |
beed8fc0 | 2321 | |
f16897cb AL |
2322 | pattern = PATTERN (insn); |
2323 | if (GET_CODE (pattern) == PARALLEL | |
2324 | && GET_CODE (XVECEXP (pattern, 0, 0)) == SET | |
2325 | && GET_CODE (SET_SRC (XVECEXP (pattern, 0, 0))) == COMPARE) | |
2326 | set = XVECEXP (pattern, 0, 1); | |
2327 | else | |
2328 | set = single_set (insn); | |
8c440872 | 2329 | gcc_assert (set); |
beed8fc0 AO |
2330 | |
2331 | if (BINARY_P (SET_SRC (set))) | |
2332 | return h8300_length_from_table (XEXP (SET_SRC (set), 0), | |
2333 | XEXP (SET_SRC (set), 1), table); | |
beed8fc0 | 2334 | else |
8c440872 NS |
2335 | { |
2336 | gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY); | |
2337 | return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0), | |
2338 | XEXP (XEXP (SET_SRC (set), 1), 1), | |
2339 | table); | |
2340 | } | |
8ccf5d5f KH |
2341 | } |
2342 | ||
beed8fc0 AO |
2343 | /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte |
2344 | memory reference and either (1) it has the form @(d:16,Rn) or | |
2345 | (2) its address has the code given by INC_CODE. */ | |
8ccf5d5f | 2346 | |
beed8fc0 AO |
2347 | static bool |
2348 | h8300_short_move_mem_p (rtx op, enum rtx_code inc_code) | |
8ccf5d5f | 2349 | { |
beed8fc0 AO |
2350 | rtx addr; |
2351 | unsigned int size; | |
2352 | ||
2353 | if (GET_CODE (op) != MEM) | |
2354 | return false; | |
2355 | ||
2356 | addr = XEXP (op, 0); | |
2357 | size = GET_MODE_SIZE (GET_MODE (op)); | |
2358 | if (size != 1 && size != 2) | |
2359 | return false; | |
2360 | ||
2361 | return (GET_CODE (addr) == inc_code | |
2362 | || (GET_CODE (addr) == PLUS | |
2363 | && GET_CODE (XEXP (addr, 0)) == REG | |
2364 | && h8300_displacement_length (addr, size) == 2)); | |
8ccf5d5f KH |
2365 | } |
2366 | ||
beed8fc0 AO |
2367 | /* Calculate the length of move instruction INSN using the given length |
2368 | table. Although the tables are correct for most cases, there is some | |
2369 | irregularity in the length of mov.b and mov.w. The following forms: | |
8ccf5d5f | 2370 | |
beed8fc0 AO |
2371 | mov @ERs+, Rd |
2372 | mov @(d:16,ERs), Rd | |
2373 | mov Rs, @-ERd | |
2374 | mov Rs, @(d:16,ERd) | |
2375 | ||
2376 | are two bytes shorter than most other "mov Rs, @complex" or | |
2377 | "mov @complex,Rd" combinations. */ | |
2378 | ||
2379 | static unsigned int | |
2380 | h8300_move_length (rtx *operands, const h8300_length_table *table) | |
8ccf5d5f | 2381 | { |
beed8fc0 AO |
2382 | unsigned int size; |
2383 | ||
2384 | size = h8300_length_from_table (operands[0], operands[1], table); | |
2385 | if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC)) | |
2386 | size -= 2; | |
2387 | if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC)) | |
2388 | size -= 2; | |
2389 | return size; | |
8ccf5d5f KH |
2390 | } |
2391 | ||
beed8fc0 AO |
2392 | /* Return the length of a mova instruction with the given operands. |
2393 | DEST is the register destination, SRC is the source address and | |
2394 | OFFSET is the 16-bit or 32-bit displacement. */ | |
2873836b | 2395 | |
beed8fc0 AO |
2396 | static unsigned int |
2397 | h8300_mova_length (rtx dest, rtx src, rtx offset) | |
2873836b | 2398 | { |
beed8fc0 AO |
2399 | unsigned int size; |
2400 | ||
2401 | size = (2 | |
2402 | + h8300_constant_length (offset) | |
2403 | + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0)); | |
2404 | if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest)) | |
2405 | size += 2; | |
2406 | return size; | |
2873836b KH |
2407 | } |
2408 | ||
beed8fc0 AO |
2409 | /* Compute the length of INSN based on its length_table attribute. |
2410 | OPERANDS is the array of its operands. */ | |
2873836b | 2411 | |
beed8fc0 | 2412 | unsigned int |
e7041fcc | 2413 | h8300_insn_length_from_table (rtx_insn *insn, rtx * operands) |
2873836b | 2414 | { |
beed8fc0 AO |
2415 | switch (get_attr_length_table (insn)) |
2416 | { | |
2417 | case LENGTH_TABLE_NONE: | |
8c440872 | 2418 | gcc_unreachable (); |
beed8fc0 | 2419 | |
c3c3ddbb JL |
2420 | case LENGTH_TABLE_ADD: |
2421 | if (GET_MODE (operands[0]) == QImode) | |
2422 | return h8300_binary_length (insn, &addb_length_table); | |
2423 | else if (GET_MODE (operands[0]) == HImode) | |
2424 | return h8300_binary_length (insn, &addw_length_table); | |
2425 | else if (GET_MODE (operands[0]) == SImode) | |
2426 | return h8300_binary_length (insn, &addl_length_table); | |
2427 | gcc_unreachable (); | |
beed8fc0 AO |
2428 | |
2429 | case LENGTH_TABLE_LOGICB: | |
2430 | return h8300_binary_length (insn, &logicb_length_table); | |
2431 | ||
2432 | case LENGTH_TABLE_MOVB: | |
2433 | return h8300_move_length (operands, &movb_length_table); | |
2434 | ||
2435 | case LENGTH_TABLE_MOVW: | |
2436 | return h8300_move_length (operands, &movw_length_table); | |
2437 | ||
2438 | case LENGTH_TABLE_MOVL: | |
2439 | return h8300_move_length (operands, &movl_length_table); | |
2440 | ||
2441 | case LENGTH_TABLE_MOVA: | |
2442 | return h8300_mova_length (operands[0], operands[1], operands[2]); | |
2443 | ||
2444 | case LENGTH_TABLE_MOVA_ZERO: | |
2445 | return h8300_mova_length (operands[0], operands[1], const0_rtx); | |
2446 | ||
2447 | case LENGTH_TABLE_UNARY: | |
2448 | return h8300_unary_length (operands[0]); | |
2449 | ||
2450 | case LENGTH_TABLE_MOV_IMM4: | |
2451 | return 2 + h8300_classify_operand (operands[0], 0, 0); | |
2452 | ||
2453 | case LENGTH_TABLE_SHORT_IMMEDIATE: | |
2454 | return h8300_short_immediate_length (operands[0]); | |
2455 | ||
2456 | case LENGTH_TABLE_BITFIELD: | |
2457 | return h8300_bitfield_length (operands[0], operands[1]); | |
2458 | ||
2459 | case LENGTH_TABLE_BITBRANCH: | |
2460 | return h8300_bitfield_length (operands[1], operands[2]) - 2; | |
8c440872 NS |
2461 | |
2462 | default: | |
2463 | gcc_unreachable (); | |
beed8fc0 | 2464 | } |
2873836b KH |
2465 | } |
2466 | ||
beed8fc0 AO |
2467 | /* Return true if LHS and RHS are memory references that can be mapped |
2468 | to the same h8sx assembly operand. LHS appears as the destination of | |
2469 | an instruction and RHS appears as a source. | |
f9d2de4d | 2470 | |
beed8fc0 AO |
2471 | Three cases are allowed: |
2472 | ||
2473 | - RHS is @+Rn or @-Rn, LHS is @Rn | |
2474 | - RHS is @Rn, LHS is @Rn+ or @Rn- | |
2475 | - RHS and LHS have the same address and neither has side effects. */ | |
2476 | ||
2477 | bool | |
2478 | h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs) | |
f9d2de4d | 2479 | { |
beed8fc0 AO |
2480 | if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM) |
2481 | { | |
2482 | rhs = XEXP (rhs, 0); | |
2483 | lhs = XEXP (lhs, 0); | |
2484 | ||
2485 | if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC) | |
2486 | return rtx_equal_p (XEXP (rhs, 0), lhs); | |
2487 | ||
2488 | if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC) | |
2489 | return rtx_equal_p (rhs, XEXP (lhs, 0)); | |
2490 | ||
2491 | if (rtx_equal_p (rhs, lhs)) | |
2492 | return true; | |
2493 | } | |
2494 | return false; | |
f9d2de4d KH |
2495 | } |
2496 | ||
beed8fc0 AO |
2497 | /* Return true if OPERANDS[1] can be mapped to the same assembly |
2498 | operand as OPERANDS[0]. */ | |
f9d2de4d | 2499 | |
beed8fc0 AO |
2500 | bool |
2501 | h8300_operands_match_p (rtx *operands) | |
f9d2de4d | 2502 | { |
beed8fc0 AO |
2503 | if (register_operand (operands[0], VOIDmode) |
2504 | && register_operand (operands[1], VOIDmode)) | |
2505 | return true; | |
f9d2de4d | 2506 | |
beed8fc0 AO |
2507 | if (h8sx_mergeable_memrefs_p (operands[0], operands[1])) |
2508 | return true; | |
2509 | ||
2510 | return false; | |
f9d2de4d | 2511 | } |
beed8fc0 | 2512 | \f |
7948a9ea KH |
2513 | /* Return the length of mov instruction. */ |
2514 | ||
2515 | unsigned int | |
2516 | compute_mov_length (rtx *operands) | |
2517 | { | |
2518 | /* If the mov instruction involves a memory operand, we compute the | |
2519 | length, assuming the largest addressing mode is used, and then | |
2520 | adjust later in the function. Otherwise, we compute and return | |
2521 | the exact length in one step. */ | |
ef4bddc2 | 2522 | machine_mode mode = GET_MODE (operands[0]); |
7948a9ea KH |
2523 | rtx dest = operands[0]; |
2524 | rtx src = operands[1]; | |
2525 | rtx addr; | |
2526 | ||
2527 | if (GET_CODE (src) == MEM) | |
2528 | addr = XEXP (src, 0); | |
2529 | else if (GET_CODE (dest) == MEM) | |
2530 | addr = XEXP (dest, 0); | |
2531 | else | |
2532 | addr = NULL_RTX; | |
2533 | ||
27c1afd5 | 2534 | unsigned int base_length; |
7948a9ea | 2535 | |
27c1afd5 JL |
2536 | switch (mode) |
2537 | { | |
2538 | case E_QImode: | |
2539 | if (addr == NULL_RTX) | |
2540 | return 2; | |
7948a9ea | 2541 | |
27c1afd5 JL |
2542 | /* The eightbit addressing is available only in QImode, so |
2543 | go ahead and take care of it. */ | |
2544 | if (h8300_eightbit_constant_address_p (addr)) | |
2545 | return 2; | |
7948a9ea | 2546 | |
27c1afd5 | 2547 | base_length = 8; |
7948a9ea KH |
2548 | break; |
2549 | ||
27c1afd5 JL |
2550 | case E_HImode: |
2551 | if (addr == NULL_RTX) | |
2552 | { | |
2553 | if (REG_P (src)) | |
2554 | return 2; | |
7948a9ea | 2555 | |
27c1afd5 JL |
2556 | if (src == const0_rtx) |
2557 | return 2; | |
7948a9ea | 2558 | |
27c1afd5 JL |
2559 | return 4; |
2560 | } | |
7948a9ea | 2561 | |
27c1afd5 JL |
2562 | base_length = 8; |
2563 | break; | |
7948a9ea | 2564 | |
27c1afd5 JL |
2565 | case E_SImode: |
2566 | if (addr == NULL_RTX) | |
2567 | { | |
2568 | if (REG_P (src)) | |
7948a9ea | 2569 | { |
27c1afd5 | 2570 | if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG) |
7948a9ea | 2571 | return 4; |
27c1afd5 JL |
2572 | else |
2573 | return 2; | |
7948a9ea KH |
2574 | } |
2575 | ||
27c1afd5 | 2576 | if (GET_CODE (src) == CONST_INT) |
7948a9ea | 2577 | { |
27c1afd5 JL |
2578 | int val = INTVAL (src); |
2579 | ||
2580 | if (val == 0) | |
2581 | return 2; | |
7948a9ea | 2582 | |
27c1afd5 | 2583 | if (val == (val & 0x00ff) || val == (val & 0xff00)) |
2c4a71b3 KH |
2584 | return 4; |
2585 | ||
27c1afd5 JL |
2586 | switch (val & 0xffffffff) |
2587 | { | |
2588 | case 0xffffffff: | |
2589 | case 0xfffffffe: | |
2590 | case 0xfffffffc: | |
2591 | case 0x0000ffff: | |
2592 | case 0x0000fffe: | |
2593 | case 0xffff0000: | |
2594 | case 0xfffe0000: | |
2595 | case 0x00010000: | |
2596 | case 0x00020000: | |
2597 | return 4; | |
2598 | } | |
7948a9ea | 2599 | } |
27c1afd5 | 2600 | return 6; |
7948a9ea KH |
2601 | } |
2602 | ||
27c1afd5 JL |
2603 | base_length = 10; |
2604 | break; | |
7948a9ea | 2605 | |
27c1afd5 JL |
2606 | case E_SFmode: |
2607 | if (addr == NULL_RTX) | |
7948a9ea | 2608 | { |
27c1afd5 JL |
2609 | if (REG_P (src)) |
2610 | return 2; | |
7948a9ea | 2611 | |
27c1afd5 | 2612 | if (satisfies_constraint_G (src)) |
7948a9ea KH |
2613 | return 2; |
2614 | ||
27c1afd5 JL |
2615 | return 6; |
2616 | } | |
7948a9ea | 2617 | |
27c1afd5 JL |
2618 | base_length = 10; |
2619 | break; | |
80e58519 | 2620 | |
27c1afd5 JL |
2621 | default: |
2622 | gcc_unreachable (); | |
2623 | } | |
7948a9ea | 2624 | |
27c1afd5 JL |
2625 | /* Adjust the length based on the addressing mode used. |
2626 | Specifically, we subtract the difference between the actual | |
2627 | length and the longest one, which is @(d:24,ERs). */ | |
7948a9ea | 2628 | |
27c1afd5 JL |
2629 | /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */ |
2630 | if (GET_CODE (addr) == PRE_DEC | |
2631 | || GET_CODE (addr) == POST_INC) | |
2632 | return base_length - 6; | |
7948a9ea | 2633 | |
27c1afd5 JL |
2634 | /* @ERs and @ERd are 6 bytes shorter than the longest. */ |
2635 | if (GET_CODE (addr) == REG) | |
2636 | return base_length - 6; | |
2c4a71b3 | 2637 | |
27c1afd5 JL |
2638 | /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the |
2639 | longest. */ | |
2640 | if (GET_CODE (addr) == PLUS | |
2641 | && GET_CODE (XEXP (addr, 0)) == REG | |
2642 | && GET_CODE (XEXP (addr, 1)) == CONST_INT | |
2643 | && INTVAL (XEXP (addr, 1)) > -32768 | |
2644 | && INTVAL (XEXP (addr, 1)) < 32767) | |
2645 | return base_length - 4; | |
7948a9ea | 2646 | |
27c1afd5 JL |
2647 | /* @aa:16 is 4 bytes shorter than the longest. */ |
2648 | if (h8300_tiny_constant_address_p (addr)) | |
2649 | return base_length - 4; | |
7948a9ea | 2650 | |
27c1afd5 JL |
2651 | /* @aa:24 is 2 bytes shorter than the longest. */ |
2652 | if (CONSTANT_P (addr)) | |
2653 | return base_length - 2; | |
7948a9ea | 2654 | |
27c1afd5 | 2655 | return base_length; |
7948a9ea KH |
2656 | } |
2657 | \f | |
e9eba255 KH |
2658 | /* Output an addition insn. */ |
2659 | ||
366a7b27 | 2660 | const char * |
f16897cb | 2661 | output_plussi (rtx *operands, bool need_flags) |
7d6ac401 | 2662 | { |
ef4bddc2 | 2663 | machine_mode mode = GET_MODE (operands[0]); |
7d6ac401 | 2664 | |
8c440872 | 2665 | gcc_assert (mode == SImode); |
7d6ac401 | 2666 | |
27c1afd5 JL |
2667 | if (GET_CODE (operands[2]) == CONST_INT |
2668 | && register_operand (operands[1], VOIDmode)) | |
7d6ac401 | 2669 | { |
27c1afd5 | 2670 | HOST_WIDE_INT intval = INTVAL (operands[2]); |
7d6ac401 | 2671 | |
27c1afd5 JL |
2672 | if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) |
2673 | return "add.l\t%S2,%S0"; | |
2674 | if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) | |
2675 | return "sub.l\t%G2,%S0"; | |
beed8fc0 | 2676 | |
27c1afd5 | 2677 | /* See if we can finish with 2 bytes. */ |
7d6ac401 | 2678 | |
27c1afd5 JL |
2679 | switch ((unsigned int) intval & 0xffffffff) |
2680 | { | |
f16897cb AL |
2681 | /* INC/DEC set the flags, but adds/subs do not. So if we |
2682 | need flags, use the former and not the latter. */ | |
27c1afd5 | 2683 | case 0x00000001: |
f16897cb AL |
2684 | if (need_flags) |
2685 | return "inc.l\t#1,%S0"; | |
2686 | else | |
2687 | return "adds\t%2,%S0"; | |
27c1afd5 | 2688 | case 0x00000002: |
f16897cb AL |
2689 | if (need_flags) |
2690 | return "inc.l\t#2,%S0"; | |
2691 | else | |
2692 | return "adds\t%2,%S0"; | |
27c1afd5 | 2693 | case 0xffffffff: |
f16897cb AL |
2694 | if (need_flags) |
2695 | return "dec.l\t#1,%S0"; | |
2696 | else | |
2697 | return "subs\t%G2,%S0"; | |
27c1afd5 | 2698 | case 0xfffffffe: |
f16897cb AL |
2699 | if (need_flags) |
2700 | return "dec.l\t#2,%S0"; | |
2701 | else | |
2702 | return "subs\t%G2,%S0"; | |
2703 | ||
2704 | /* These six cases have optimized paths when we do not | |
2705 | need flags. Otherwise we let them fallthru. */ | |
2706 | case 0x00000004: | |
2707 | if (!need_flags) | |
2708 | return "adds\t%2,%S0"; | |
2709 | ||
27c1afd5 | 2710 | case 0xfffffffc: |
f16897cb AL |
2711 | if (!need_flags) |
2712 | return "subs\t%G2,%S0"; | |
27c1afd5 JL |
2713 | |
2714 | case 0x00010000: | |
2715 | case 0x00020000: | |
f16897cb AL |
2716 | if (!need_flags) |
2717 | { | |
2718 | operands[2] = GEN_INT (intval >> 16); | |
2719 | return "inc.w\t%2,%e0"; | |
2720 | } | |
27c1afd5 JL |
2721 | |
2722 | case 0xffff0000: | |
2723 | case 0xfffe0000: | |
f16897cb AL |
2724 | if (!need_flags) |
2725 | { | |
2726 | operands[2] = GEN_INT (intval >> 16); | |
2727 | return "dec.w\t%G2,%e0"; | |
2728 | } | |
7d6ac401 KH |
2729 | } |
2730 | ||
27c1afd5 JL |
2731 | /* See if we can finish with 4 bytes. */ |
2732 | if ((intval & 0xffff) == 0) | |
beed8fc0 | 2733 | { |
27c1afd5 JL |
2734 | operands[2] = GEN_INT (intval >> 16); |
2735 | return "add.w\t%2,%e0"; | |
beed8fc0 | 2736 | } |
7d6ac401 | 2737 | } |
27c1afd5 JL |
2738 | |
2739 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
2740 | { | |
2741 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
2742 | return "sub.l\t%S2,%S0"; | |
2743 | } | |
2744 | return "add.l\t%S2,%S0"; | |
7d6ac401 KH |
2745 | } |
2746 | ||
beed8fc0 AO |
2747 | /* ??? It would be much easier to add the h8sx stuff if a single function |
2748 | classified the addition as either inc/dec, adds/subs, add.w or add.l. */ | |
e9eba255 KH |
2749 | /* Compute the length of an addition insn. */ |
2750 | ||
7d6ac401 | 2751 | unsigned int |
f16897cb | 2752 | compute_plussi_length (rtx *operands, bool need_flags) |
7d6ac401 | 2753 | { |
ef4bddc2 | 2754 | machine_mode mode = GET_MODE (operands[0]); |
7d6ac401 | 2755 | |
8c440872 | 2756 | gcc_assert (mode == SImode); |
7d6ac401 | 2757 | |
27c1afd5 JL |
2758 | if (GET_CODE (operands[2]) == CONST_INT |
2759 | && register_operand (operands[1], VOIDmode)) | |
7d6ac401 | 2760 | { |
27c1afd5 | 2761 | HOST_WIDE_INT intval = INTVAL (operands[2]); |
cfedf91b | 2762 | |
27c1afd5 JL |
2763 | if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) |
2764 | return 2; | |
2765 | if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) | |
2766 | return 2; | |
cfedf91b | 2767 | |
27c1afd5 | 2768 | /* See if we can finish with 2 bytes. */ |
cfedf91b | 2769 | |
27c1afd5 | 2770 | switch ((unsigned int) intval & 0xffffffff) |
7d6ac401 | 2771 | { |
27c1afd5 JL |
2772 | case 0x00000001: |
2773 | case 0x00000002: | |
27c1afd5 | 2774 | return 2; |
f16897cb AL |
2775 | case 0x00000004: |
2776 | if (need_flags) | |
2777 | return 6; | |
2778 | else | |
2779 | return 2; | |
27c1afd5 JL |
2780 | |
2781 | case 0xffffffff: | |
2782 | case 0xfffffffe: | |
27c1afd5 | 2783 | return 2; |
f16897cb AL |
2784 | case 0xfffffffc: |
2785 | if (need_flags) | |
2786 | return 6; | |
2787 | else | |
2788 | return 2; | |
27c1afd5 JL |
2789 | |
2790 | case 0x00010000: | |
2791 | case 0x00020000: | |
f16897cb AL |
2792 | if (!need_flags) |
2793 | return 2; | |
27c1afd5 JL |
2794 | |
2795 | case 0xffff0000: | |
2796 | case 0xfffe0000: | |
f16897cb AL |
2797 | if (!need_flags) |
2798 | return 2; | |
7d6ac401 KH |
2799 | } |
2800 | ||
27c1afd5 JL |
2801 | /* See if we can finish with 4 bytes. */ |
2802 | if ((intval & 0xffff) == 0) | |
2803 | return 4; | |
7d6ac401 | 2804 | } |
27c1afd5 JL |
2805 | |
2806 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
2807 | return h8300_length_from_table (operands[0], | |
2808 | GEN_INT (-INTVAL (operands[2])), | |
2809 | &addl_length_table); | |
2810 | else | |
2811 | return h8300_length_from_table (operands[0], operands[2], | |
2812 | &addl_length_table); | |
7d6ac401 KH |
2813 | } |
2814 | ||
e9eba255 KH |
2815 | /* Compute which flag bits are valid after an addition insn. */ |
2816 | ||
5ddb6eca | 2817 | enum attr_old_cc |
cb713a8d | 2818 | compute_plussi_cc (rtx *operands) |
7d6ac401 | 2819 | { |
ef4bddc2 | 2820 | machine_mode mode = GET_MODE (operands[0]); |
7d6ac401 | 2821 | |
8c440872 | 2822 | gcc_assert (mode == SImode); |
7d6ac401 | 2823 | |
27c1afd5 JL |
2824 | if (GET_CODE (operands[2]) == CONST_INT |
2825 | && register_operand (operands[1], VOIDmode)) | |
7d6ac401 | 2826 | { |
27c1afd5 | 2827 | HOST_WIDE_INT intval = INTVAL (operands[2]); |
7d6ac401 | 2828 | |
27c1afd5 | 2829 | if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) |
5ddb6eca | 2830 | return OLD_CC_SET_ZN; |
27c1afd5 | 2831 | if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) |
5ddb6eca | 2832 | return OLD_CC_SET_ZN; |
beed8fc0 | 2833 | |
27c1afd5 | 2834 | /* See if we can finish with 2 bytes. */ |
7d6ac401 | 2835 | |
27c1afd5 JL |
2836 | switch ((unsigned int) intval & 0xffffffff) |
2837 | { | |
2838 | case 0x00000001: | |
2839 | case 0x00000002: | |
2840 | case 0x00000004: | |
5ddb6eca | 2841 | return OLD_CC_NONE_0HIT; |
27c1afd5 JL |
2842 | |
2843 | case 0xffffffff: | |
2844 | case 0xfffffffe: | |
2845 | case 0xfffffffc: | |
5ddb6eca | 2846 | return OLD_CC_NONE_0HIT; |
27c1afd5 JL |
2847 | |
2848 | case 0x00010000: | |
2849 | case 0x00020000: | |
5ddb6eca | 2850 | return OLD_CC_CLOBBER; |
27c1afd5 JL |
2851 | |
2852 | case 0xffff0000: | |
2853 | case 0xfffe0000: | |
5ddb6eca | 2854 | return OLD_CC_CLOBBER; |
7d6ac401 KH |
2855 | } |
2856 | ||
27c1afd5 JL |
2857 | /* See if we can finish with 4 bytes. */ |
2858 | if ((intval & 0xffff) == 0) | |
5ddb6eca | 2859 | return OLD_CC_CLOBBER; |
7d6ac401 | 2860 | } |
27c1afd5 | 2861 | |
5ddb6eca | 2862 | return OLD_CC_SET_ZN; |
7d6ac401 KH |
2863 | } |
2864 | \f | |
e9eba255 KH |
2865 | /* Output a logical insn. */ |
2866 | ||
7d6ac401 | 2867 | const char * |
ef4bddc2 | 2868 | output_logical_op (machine_mode mode, rtx *operands) |
366a7b27 | 2869 | { |
b42cff6b KH |
2870 | /* Figure out the logical op that we need to perform. */ |
2871 | enum rtx_code code = GET_CODE (operands[3]); | |
366a7b27 | 2872 | /* Pretend that every byte is affected if both operands are registers. */ |
7798db98 | 2873 | const unsigned HOST_WIDE_INT intval = |
366a7b27 | 2874 | (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT) |
beed8fc0 AO |
2875 | /* Always use the full instruction if the |
2876 | first operand is in memory. It is better | |
2877 | to use define_splits to generate the shorter | |
2878 | sequence where valid. */ | |
2879 | && register_operand (operands[1], VOIDmode) | |
366a7b27 KH |
2880 | ? INTVAL (operands[2]) : 0x55555555); |
2881 | /* The determinant of the algorithm. If we perform an AND, 0 | |
2882 | affects a bit. Otherwise, 1 affects a bit. */ | |
7798db98 | 2883 | const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval; |
f9ac2f95 KH |
2884 | /* Break up DET into pieces. */ |
2885 | const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff; | |
2886 | const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff; | |
2887 | const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff; | |
2888 | const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff; | |
2889 | int lower_half_easy_p = 0; | |
2890 | int upper_half_easy_p = 0; | |
366a7b27 KH |
2891 | /* The name of an insn. */ |
2892 | const char *opname; | |
2893 | char insn_buf[100]; | |
2894 | ||
2895 | switch (code) | |
2896 | { | |
2897 | case AND: | |
2898 | opname = "and"; | |
2899 | break; | |
2900 | case IOR: | |
2901 | opname = "or"; | |
2902 | break; | |
2903 | case XOR: | |
2904 | opname = "xor"; | |
2905 | break; | |
2906 | default: | |
8c440872 | 2907 | gcc_unreachable (); |
366a7b27 KH |
2908 | } |
2909 | ||
2910 | switch (mode) | |
2911 | { | |
4e10a5a7 | 2912 | case E_HImode: |
366a7b27 | 2913 | /* First, see if we can finish with one insn. */ |
27c1afd5 | 2914 | if (b0 != 0 && b1 != 0) |
366a7b27 KH |
2915 | { |
2916 | sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname); | |
2917 | output_asm_insn (insn_buf, operands); | |
2918 | } | |
2919 | else | |
2920 | { | |
2921 | /* Take care of the lower byte. */ | |
c5e7ce43 | 2922 | if (b0 != 0) |
366a7b27 KH |
2923 | { |
2924 | sprintf (insn_buf, "%s\t%%s2,%%s0", opname); | |
2925 | output_asm_insn (insn_buf, operands); | |
2926 | } | |
2927 | /* Take care of the upper byte. */ | |
c5e7ce43 | 2928 | if (b1 != 0) |
366a7b27 KH |
2929 | { |
2930 | sprintf (insn_buf, "%s\t%%t2,%%t0", opname); | |
2931 | output_asm_insn (insn_buf, operands); | |
2932 | } | |
2933 | } | |
2934 | break; | |
4e10a5a7 | 2935 | case E_SImode: |
27c1afd5 JL |
2936 | /* Determine if the lower half can be taken care of in no more |
2937 | than two bytes. */ | |
2938 | lower_half_easy_p = (b0 == 0 | |
2939 | || b1 == 0 | |
2940 | || (code != IOR && w0 == 0xffff)); | |
2941 | ||
2942 | /* Determine if the upper half can be taken care of in no more | |
2943 | than two bytes. */ | |
2944 | upper_half_easy_p = ((code != IOR && w1 == 0xffff) | |
2945 | || (code == AND && w1 == 0xff00)); | |
366a7b27 | 2946 | |
f9ac2f95 KH |
2947 | /* Check if doing everything with one insn is no worse than |
2948 | using multiple insns. */ | |
27c1afd5 | 2949 | if (w0 != 0 && w1 != 0 |
472f2723 KH |
2950 | && !(lower_half_easy_p && upper_half_easy_p) |
2951 | && !(code == IOR && w1 == 0xffff | |
2952 | && (w0 & 0x8000) != 0 && lower_half_easy_p)) | |
366a7b27 KH |
2953 | { |
2954 | sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname); | |
2955 | output_asm_insn (insn_buf, operands); | |
2956 | } | |
2957 | else | |
2958 | { | |
2959 | /* Take care of the lower and upper words individually. For | |
2960 | each word, we try different methods in the order of | |
2961 | ||
2962 | 1) the special insn (in case of AND or XOR), | |
2963 | 2) the word-wise insn, and | |
2964 | 3) The byte-wise insn. */ | |
27c1afd5 | 2965 | if (w0 == 0xffff && (code != IOR)) |
366a7b27 | 2966 | output_asm_insn ((code == AND) |
187462ac | 2967 | ? "sub.w\t%f0,%f0" : "not.w\t%f0", |
366a7b27 | 2968 | operands); |
27c1afd5 | 2969 | else if ((b0 != 0) && (b1 != 0)) |
366a7b27 KH |
2970 | { |
2971 | sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname); | |
2972 | output_asm_insn (insn_buf, operands); | |
2973 | } | |
2974 | else | |
2975 | { | |
c5e7ce43 | 2976 | if (b0 != 0) |
366a7b27 KH |
2977 | { |
2978 | sprintf (insn_buf, "%s\t%%w2,%%w0", opname); | |
2979 | output_asm_insn (insn_buf, operands); | |
2980 | } | |
c5e7ce43 | 2981 | if (b1 != 0) |
366a7b27 KH |
2982 | { |
2983 | sprintf (insn_buf, "%s\t%%x2,%%x0", opname); | |
2984 | output_asm_insn (insn_buf, operands); | |
2985 | } | |
2986 | } | |
2987 | ||
27c1afd5 | 2988 | if ((w1 == 0xffff) && (code != IOR)) |
366a7b27 | 2989 | output_asm_insn ((code == AND) |
187462ac | 2990 | ? "sub.w\t%e0,%e0" : "not.w\t%e0", |
366a7b27 | 2991 | operands); |
27c1afd5 | 2992 | else if (code == IOR |
472f2723 KH |
2993 | && w1 == 0xffff |
2994 | && (w0 & 0x8000) != 0) | |
2995 | { | |
2996 | output_asm_insn ("exts.l\t%S0", operands); | |
2997 | } | |
27c1afd5 | 2998 | else if (code == AND |
c5e7ce43 | 2999 | && w1 == 0xff00) |
a6e8d113 | 3000 | { |
dc5f17ec | 3001 | output_asm_insn ("extu.w\t%e0", operands); |
a6e8d113 | 3002 | } |
27c1afd5 | 3003 | else |
366a7b27 | 3004 | { |
c5e7ce43 | 3005 | if (w1 != 0) |
366a7b27 KH |
3006 | { |
3007 | sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname); | |
3008 | output_asm_insn (insn_buf, operands); | |
3009 | } | |
3010 | } | |
366a7b27 KH |
3011 | } |
3012 | break; | |
3013 | default: | |
8c440872 | 3014 | gcc_unreachable (); |
366a7b27 KH |
3015 | } |
3016 | return ""; | |
3017 | } | |
40367e2d | 3018 | |
e9eba255 KH |
3019 | /* Compute the length of a logical insn. */ |
3020 | ||
40367e2d | 3021 | unsigned int |
ef4bddc2 | 3022 | compute_logical_op_length (machine_mode mode, rtx *operands) |
40367e2d | 3023 | { |
b42cff6b KH |
3024 | /* Figure out the logical op that we need to perform. */ |
3025 | enum rtx_code code = GET_CODE (operands[3]); | |
40367e2d | 3026 | /* Pretend that every byte is affected if both operands are registers. */ |
7798db98 | 3027 | const unsigned HOST_WIDE_INT intval = |
40367e2d | 3028 | (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT) |
beed8fc0 AO |
3029 | /* Always use the full instruction if the |
3030 | first operand is in memory. It is better | |
3031 | to use define_splits to generate the shorter | |
3032 | sequence where valid. */ | |
3033 | && register_operand (operands[1], VOIDmode) | |
40367e2d KH |
3034 | ? INTVAL (operands[2]) : 0x55555555); |
3035 | /* The determinant of the algorithm. If we perform an AND, 0 | |
3036 | affects a bit. Otherwise, 1 affects a bit. */ | |
7798db98 | 3037 | const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval; |
f9ac2f95 KH |
3038 | /* Break up DET into pieces. */ |
3039 | const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff; | |
3040 | const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff; | |
3041 | const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff; | |
3042 | const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff; | |
3043 | int lower_half_easy_p = 0; | |
3044 | int upper_half_easy_p = 0; | |
40367e2d KH |
3045 | /* Insn length. */ |
3046 | unsigned int length = 0; | |
3047 | ||
3048 | switch (mode) | |
3049 | { | |
4e10a5a7 | 3050 | case E_HImode: |
40367e2d | 3051 | /* First, see if we can finish with one insn. */ |
27c1afd5 | 3052 | if (b0 != 0 && b1 != 0) |
40367e2d | 3053 | { |
beed8fc0 AO |
3054 | length = h8300_length_from_table (operands[1], operands[2], |
3055 | &logicw_length_table); | |
40367e2d KH |
3056 | } |
3057 | else | |
3058 | { | |
3059 | /* Take care of the lower byte. */ | |
c5e7ce43 | 3060 | if (b0 != 0) |
40367e2d KH |
3061 | length += 2; |
3062 | ||
3063 | /* Take care of the upper byte. */ | |
c5e7ce43 | 3064 | if (b1 != 0) |
40367e2d KH |
3065 | length += 2; |
3066 | } | |
3067 | break; | |
4e10a5a7 | 3068 | case E_SImode: |
27c1afd5 JL |
3069 | /* Determine if the lower half can be taken care of in no more |
3070 | than two bytes. */ | |
3071 | lower_half_easy_p = (b0 == 0 | |
3072 | || b1 == 0 | |
3073 | || (code != IOR && w0 == 0xffff)); | |
3074 | ||
3075 | /* Determine if the upper half can be taken care of in no more | |
3076 | than two bytes. */ | |
3077 | upper_half_easy_p = ((code != IOR && w1 == 0xffff) | |
3078 | || (code == AND && w1 == 0xff00)); | |
40367e2d | 3079 | |
f9ac2f95 KH |
3080 | /* Check if doing everything with one insn is no worse than |
3081 | using multiple insns. */ | |
27c1afd5 | 3082 | if (w0 != 0 && w1 != 0 |
472f2723 KH |
3083 | && !(lower_half_easy_p && upper_half_easy_p) |
3084 | && !(code == IOR && w1 == 0xffff | |
3085 | && (w0 & 0x8000) != 0 && lower_half_easy_p)) | |
40367e2d | 3086 | { |
beed8fc0 AO |
3087 | length = h8300_length_from_table (operands[1], operands[2], |
3088 | &logicl_length_table); | |
40367e2d KH |
3089 | } |
3090 | else | |
3091 | { | |
3092 | /* Take care of the lower and upper words individually. For | |
3093 | each word, we try different methods in the order of | |
3094 | ||
3095 | 1) the special insn (in case of AND or XOR), | |
3096 | 2) the word-wise insn, and | |
3097 | 3) The byte-wise insn. */ | |
27c1afd5 | 3098 | if (w0 == 0xffff && (code != IOR)) |
40367e2d KH |
3099 | { |
3100 | length += 2; | |
3101 | } | |
27c1afd5 | 3102 | else if ((b0 != 0) && (b1 != 0)) |
40367e2d KH |
3103 | { |
3104 | length += 4; | |
3105 | } | |
3106 | else | |
3107 | { | |
c5e7ce43 | 3108 | if (b0 != 0) |
40367e2d KH |
3109 | length += 2; |
3110 | ||
c5e7ce43 | 3111 | if (b1 != 0) |
40367e2d KH |
3112 | length += 2; |
3113 | } | |
3114 | ||
27c1afd5 | 3115 | if (w1 == 0xffff && (code != IOR)) |
40367e2d KH |
3116 | { |
3117 | length += 2; | |
3118 | } | |
27c1afd5 | 3119 | else if (code == IOR |
472f2723 KH |
3120 | && w1 == 0xffff |
3121 | && (w0 & 0x8000) != 0) | |
3122 | { | |
3123 | length += 2; | |
3124 | } | |
27c1afd5 | 3125 | else if (code == AND && w1 == 0xff00) |
a6e8d113 KH |
3126 | { |
3127 | length += 2; | |
3128 | } | |
27c1afd5 | 3129 | else |
40367e2d | 3130 | { |
c5e7ce43 | 3131 | if (w1 != 0) |
40367e2d KH |
3132 | length += 4; |
3133 | } | |
40367e2d KH |
3134 | } |
3135 | break; | |
3136 | default: | |
8c440872 | 3137 | gcc_unreachable (); |
40367e2d KH |
3138 | } |
3139 | return length; | |
3140 | } | |
b42cff6b | 3141 | |
e9eba255 KH |
3142 | /* Compute which flag bits are valid after a logical insn. */ |
3143 | ||
f16897cb | 3144 | int |
ef4bddc2 | 3145 | compute_logical_op_cc (machine_mode mode, rtx *operands) |
b42cff6b KH |
3146 | { |
3147 | /* Figure out the logical op that we need to perform. */ | |
3148 | enum rtx_code code = GET_CODE (operands[3]); | |
3149 | /* Pretend that every byte is affected if both operands are registers. */ | |
7798db98 | 3150 | const unsigned HOST_WIDE_INT intval = |
b42cff6b | 3151 | (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT) |
beed8fc0 AO |
3152 | /* Always use the full instruction if the |
3153 | first operand is in memory. It is better | |
3154 | to use define_splits to generate the shorter | |
3155 | sequence where valid. */ | |
3156 | && register_operand (operands[1], VOIDmode) | |
b42cff6b KH |
3157 | ? INTVAL (operands[2]) : 0x55555555); |
3158 | /* The determinant of the algorithm. If we perform an AND, 0 | |
3159 | affects a bit. Otherwise, 1 affects a bit. */ | |
7798db98 | 3160 | const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval; |
f9ac2f95 KH |
3161 | /* Break up DET into pieces. */ |
3162 | const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff; | |
3163 | const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff; | |
3164 | const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff; | |
3165 | const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff; | |
3166 | int lower_half_easy_p = 0; | |
3167 | int upper_half_easy_p = 0; | |
b42cff6b | 3168 | /* Condition code. */ |
5ddb6eca | 3169 | enum attr_old_cc cc = OLD_CC_CLOBBER; |
b42cff6b KH |
3170 | |
3171 | switch (mode) | |
3172 | { | |
4e10a5a7 | 3173 | case E_HImode: |
b42cff6b | 3174 | /* First, see if we can finish with one insn. */ |
27c1afd5 | 3175 | if (b0 != 0 && b1 != 0) |
b42cff6b | 3176 | { |
5ddb6eca | 3177 | cc = OLD_CC_SET_ZNV; |
b42cff6b KH |
3178 | } |
3179 | break; | |
4e10a5a7 | 3180 | case E_SImode: |
27c1afd5 JL |
3181 | /* Determine if the lower half can be taken care of in no more |
3182 | than two bytes. */ | |
3183 | lower_half_easy_p = (b0 == 0 | |
3184 | || b1 == 0 | |
3185 | || (code != IOR && w0 == 0xffff)); | |
3186 | ||
3187 | /* Determine if the upper half can be taken care of in no more | |
3188 | than two bytes. */ | |
3189 | upper_half_easy_p = ((code != IOR && w1 == 0xffff) | |
3190 | || (code == AND && w1 == 0xff00)); | |
b42cff6b | 3191 | |
f9ac2f95 KH |
3192 | /* Check if doing everything with one insn is no worse than |
3193 | using multiple insns. */ | |
27c1afd5 | 3194 | if (w0 != 0 && w1 != 0 |
472f2723 KH |
3195 | && !(lower_half_easy_p && upper_half_easy_p) |
3196 | && !(code == IOR && w1 == 0xffff | |
3197 | && (w0 & 0x8000) != 0 && lower_half_easy_p)) | |
b42cff6b | 3198 | { |
5ddb6eca | 3199 | cc = OLD_CC_SET_ZNV; |
b42cff6b | 3200 | } |
472f2723 KH |
3201 | else |
3202 | { | |
27c1afd5 | 3203 | if (code == IOR |
472f2723 KH |
3204 | && w1 == 0xffff |
3205 | && (w0 & 0x8000) != 0) | |
3206 | { | |
5ddb6eca | 3207 | cc = OLD_CC_SET_ZNV; |
472f2723 KH |
3208 | } |
3209 | } | |
b42cff6b KH |
3210 | break; |
3211 | default: | |
8c440872 | 3212 | gcc_unreachable (); |
b42cff6b KH |
3213 | } |
3214 | return cc; | |
3215 | } | |
366a7b27 | 3216 | \f |
f16897cb | 3217 | #if 0 |
8981ecd3 KH |
3218 | /* Expand a conditional branch. */ |
3219 | ||
3220 | void | |
f90b7a5a | 3221 | h8300_expand_branch (rtx operands[]) |
8981ecd3 | 3222 | { |
f90b7a5a PB |
3223 | enum rtx_code code = GET_CODE (operands[0]); |
3224 | rtx op0 = operands[1]; | |
3225 | rtx op1 = operands[2]; | |
3226 | rtx label = operands[3]; | |
8981ecd3 KH |
3227 | rtx tmp; |
3228 | ||
f90b7a5a | 3229 | tmp = gen_rtx_COMPARE (VOIDmode, op0, op1); |
f7df4a84 | 3230 | emit_insn (gen_rtx_SET (cc0_rtx, tmp)); |
f90b7a5a | 3231 | |
8981ecd3 KH |
3232 | tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx); |
3233 | tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, | |
3234 | gen_rtx_LABEL_REF (VOIDmode, label), | |
3235 | pc_rtx); | |
f7df4a84 | 3236 | emit_jump_insn (gen_rtx_SET (pc_rtx, tmp)); |
8981ecd3 | 3237 | } |
f90b7a5a PB |
3238 | |
3239 | ||
3240 | /* Expand a conditional store. */ | |
3241 | ||
3242 | void | |
3243 | h8300_expand_store (rtx operands[]) | |
3244 | { | |
3245 | rtx dest = operands[0]; | |
3246 | enum rtx_code code = GET_CODE (operands[1]); | |
3247 | rtx op0 = operands[2]; | |
3248 | rtx op1 = operands[3]; | |
3249 | rtx tmp; | |
3250 | ||
3251 | tmp = gen_rtx_COMPARE (VOIDmode, op0, op1); | |
f7df4a84 | 3252 | emit_insn (gen_rtx_SET (cc0_rtx, tmp)); |
f90b7a5a PB |
3253 | |
3254 | tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx); | |
f7df4a84 | 3255 | emit_insn (gen_rtx_SET (dest, tmp)); |
f90b7a5a | 3256 | } |
f16897cb | 3257 | #endif |
8981ecd3 | 3258 | \f |
48837e29 DE |
3259 | /* Shifts. |
3260 | ||
005e3e05 KH |
3261 | We devote a fair bit of code to getting efficient shifts since we |
3262 | can only shift one bit at a time on the H8/300 and H8/300H and only | |
3db11b5c | 3263 | one or two bits at a time on the H8S. |
005e3e05 KH |
3264 | |
3265 | All shift code falls into one of the following ways of | |
3266 | implementation: | |
3267 | ||
3268 | o SHIFT_INLINE: Emit straight line code for the shift; this is used | |
3269 | when a straight line shift is about the same size or smaller than | |
3270 | a loop. | |
3271 | ||
3272 | o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask | |
3273 | off the bits we don't need. This is used when only a few of the | |
3274 | bits in the original value will survive in the shifted value. | |
3275 | ||
3276 | o SHIFT_SPECIAL: Often it's possible to move a byte or a word to | |
3277 | simulate a shift by 8, 16, or 24 bits. Once moved, a few inline | |
3278 | shifts can be added if the shift count is slightly more than 8 or | |
3279 | 16. This case also includes other oddballs that are not worth | |
f411c849 | 3280 | explaining here. |
005e3e05 | 3281 | |
3db11b5c | 3282 | o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts. |
005e3e05 | 3283 | |
5ec0b66e KH |
3284 | For each shift count, we try to use code that has no trade-off |
3285 | between code size and speed whenever possible. | |
3286 | ||
3287 | If the trade-off is unavoidable, we try to be reasonable. | |
3288 | Specifically, the fastest version is one instruction longer than | |
3289 | the shortest version, we take the fastest version. We also provide | |
3290 | the use a way to switch back to the shortest version with -Os. | |
3291 | ||
3292 | For the details of the shift algorithms for various shift counts, | |
3293 | refer to shift_alg_[qhs]i. */ | |
07aae5c2 | 3294 | |
beed8fc0 AO |
3295 | /* Classify a shift with the given mode and code. OP is the shift amount. */ |
3296 | ||
3297 | enum h8sx_shift_type | |
ef4bddc2 | 3298 | h8sx_classify_shift (machine_mode mode, enum rtx_code code, rtx op) |
beed8fc0 AO |
3299 | { |
3300 | if (!TARGET_H8300SX) | |
3301 | return H8SX_SHIFT_NONE; | |
3302 | ||
3303 | switch (code) | |
3304 | { | |
3305 | case ASHIFT: | |
3306 | case LSHIFTRT: | |
3307 | /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */ | |
3308 | if (GET_CODE (op) != CONST_INT) | |
3309 | return H8SX_SHIFT_BINARY; | |
3310 | ||
3311 | /* Reject out-of-range shift amounts. */ | |
3312 | if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode)) | |
3313 | return H8SX_SHIFT_NONE; | |
3314 | ||
3315 | /* Power-of-2 shifts are effectively unary operations. */ | |
3316 | if (exact_log2 (INTVAL (op)) >= 0) | |
3317 | return H8SX_SHIFT_UNARY; | |
3318 | ||
3319 | return H8SX_SHIFT_BINARY; | |
3320 | ||
3321 | case ASHIFTRT: | |
3322 | if (op == const1_rtx || op == const2_rtx) | |
3323 | return H8SX_SHIFT_UNARY; | |
3324 | return H8SX_SHIFT_NONE; | |
3325 | ||
3326 | case ROTATE: | |
3327 | if (GET_CODE (op) == CONST_INT | |
3328 | && (INTVAL (op) == 1 | |
3329 | || INTVAL (op) == 2 | |
3330 | || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2 | |
3331 | || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1)) | |
3332 | return H8SX_SHIFT_UNARY; | |
3333 | return H8SX_SHIFT_NONE; | |
3334 | ||
3335 | default: | |
3336 | return H8SX_SHIFT_NONE; | |
3337 | } | |
3338 | } | |
3339 | ||
beed8fc0 AO |
3340 | /* Return the asm template for a single h8sx shift instruction. |
3341 | OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2] | |
3342 | is the source and OPERANDS[3] is the shift. SUFFIX is the | |
88cb339e | 3343 | size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand |
beed8fc0 AO |
3344 | prefix for the destination operand. */ |
3345 | ||
3346 | const char * | |
3347 | output_h8sx_shift (rtx *operands, int suffix, int optype) | |
3348 | { | |
3349 | static char buffer[16]; | |
3350 | const char *stem; | |
3351 | ||
3352 | switch (GET_CODE (operands[3])) | |
3353 | { | |
3354 | case ASHIFT: | |
3355 | stem = "shll"; | |
3356 | break; | |
3357 | ||
3358 | case ASHIFTRT: | |
3359 | stem = "shar"; | |
3360 | break; | |
3361 | ||
3362 | case LSHIFTRT: | |
3363 | stem = "shlr"; | |
3364 | break; | |
3365 | ||
3366 | case ROTATE: | |
3367 | stem = "rotl"; | |
3368 | if (INTVAL (operands[2]) > 2) | |
3369 | { | |
3370 | /* This is really a right rotate. */ | |
3371 | operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0])) | |
3372 | - INTVAL (operands[2])); | |
3373 | stem = "rotr"; | |
3374 | } | |
3375 | break; | |
3376 | ||
3377 | default: | |
8c440872 | 3378 | gcc_unreachable (); |
beed8fc0 AO |
3379 | } |
3380 | if (operands[2] == const1_rtx) | |
3381 | sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype); | |
3382 | else | |
3383 | sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype); | |
3384 | return buffer; | |
3385 | } | |
48837e29 | 3386 | |
317d21e9 | 3387 | /* Emit code to do shifts. */ |
48837e29 | 3388 | |
beed8fc0 | 3389 | bool |
ef4bddc2 | 3390 | expand_a_shift (machine_mode mode, enum rtx_code code, rtx operands[]) |
07aae5c2 | 3391 | { |
beed8fc0 AO |
3392 | switch (h8sx_classify_shift (mode, code, operands[2])) |
3393 | { | |
3394 | case H8SX_SHIFT_BINARY: | |
3395 | operands[1] = force_reg (mode, operands[1]); | |
3396 | return false; | |
3397 | ||
3398 | case H8SX_SHIFT_UNARY: | |
3399 | return false; | |
3400 | ||
3401 | case H8SX_SHIFT_NONE: | |
3402 | break; | |
3403 | } | |
3404 | ||
07e4d94e KH |
3405 | /* Need a loop to get all the bits we want - we generate the |
3406 | code at emit time, but need to allocate a scratch reg now. */ | |
70033749 JL |
3407 | emit_move_insn (copy_rtx (operands[0]), operands[1]); |
3408 | if (operands[2] == CONST0_RTX (QImode)) | |
3409 | ; | |
3410 | else if (GET_CODE (operands[2]) == CONST_INT | |
3411 | && !h8300_shift_needs_scratch_p (INTVAL (operands[2]), mode, code)) | |
3412 | emit_insn (gen_rtx_SET (copy_rtx (operands[0]), | |
3413 | gen_rtx_fmt_ee (code, mode, | |
3414 | copy_rtx (operands[1]), operands[2]))); | |
3415 | else | |
3416 | emit_insn (gen_rtx_PARALLEL | |
3417 | (VOIDmode, | |
3418 | gen_rtvec (2, | |
3419 | gen_rtx_SET (copy_rtx (operands[0]), | |
3420 | gen_rtx_fmt_ee (code, mode, | |
3421 | copy_rtx (operands[0]), operands[2])), | |
3422 | gen_rtx_CLOBBER (VOIDmode, | |
3423 | gen_rtx_SCRATCH (QImode))))); | |
beed8fc0 | 3424 | return true; |
48837e29 DE |
3425 | } |
3426 | ||
48837e29 DE |
3427 | /* Symbols of the various modes which can be used as indices. */ |
3428 | ||
3429 | enum shift_mode | |
1a63219b KH |
3430 | { |
3431 | QIshift, HIshift, SIshift | |
3432 | }; | |
48837e29 | 3433 | |
269c14e1 | 3434 | /* For single bit shift insns, record assembler and what bits of the |
5ddb6eca | 3435 | condition code are valid afterwards (represented as various OLD_CC_FOO |
269c14e1 | 3436 | bits, 0 means CC isn't left in a usable state). */ |
48837e29 DE |
3437 | |
3438 | struct shift_insn | |
3439 | { | |
8b60264b | 3440 | const char *const assembler; |
5ddb6eca | 3441 | const enum attr_old_cc cc_valid; |
48837e29 DE |
3442 | }; |
3443 | ||
3444 | /* Assembler instruction shift table. | |
3445 | ||
3446 | These tables are used to look up the basic shifts. | |
07e4d94e | 3447 | They are indexed by cpu, shift_type, and mode. */ |
07aae5c2 | 3448 | |
48837e29 DE |
3449 | static const struct shift_insn shift_one[2][3][3] = |
3450 | { | |
3451 | /* H8/300 */ | |
3452 | { | |
3453 | /* SHIFT_ASHIFT */ | |
3454 | { | |
5ddb6eca JL |
3455 | { "shll\t%X0", OLD_CC_SET_ZNV }, |
3456 | { "add.w\t%T0,%T0", OLD_CC_SET_ZN }, | |
3457 | { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", OLD_CC_CLOBBER } | |
48837e29 DE |
3458 | }, |
3459 | /* SHIFT_LSHIFTRT */ | |
3460 | { | |
5ddb6eca JL |
3461 | { "shlr\t%X0", OLD_CC_SET_ZNV }, |
3462 | { "shlr\t%t0\n\trotxr\t%s0", OLD_CC_CLOBBER }, | |
3463 | { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", OLD_CC_CLOBBER } | |
48837e29 DE |
3464 | }, |
3465 | /* SHIFT_ASHIFTRT */ | |
3466 | { | |
5ddb6eca JL |
3467 | { "shar\t%X0", OLD_CC_SET_ZNV }, |
3468 | { "shar\t%t0\n\trotxr\t%s0", OLD_CC_CLOBBER }, | |
3469 | { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", OLD_CC_CLOBBER } | |
48837e29 DE |
3470 | } |
3471 | }, | |
3472 | /* H8/300H */ | |
3473 | { | |
3474 | /* SHIFT_ASHIFT */ | |
3475 | { | |
5ddb6eca JL |
3476 | { "shll.b\t%X0", OLD_CC_SET_ZNV }, |
3477 | { "shll.w\t%T0", OLD_CC_SET_ZNV }, | |
3478 | { "shll.l\t%S0", OLD_CC_SET_ZNV } | |
48837e29 DE |
3479 | }, |
3480 | /* SHIFT_LSHIFTRT */ | |
3481 | { | |
5ddb6eca JL |
3482 | { "shlr.b\t%X0", OLD_CC_SET_ZNV }, |
3483 | { "shlr.w\t%T0", OLD_CC_SET_ZNV }, | |
3484 | { "shlr.l\t%S0", OLD_CC_SET_ZNV } | |
48837e29 DE |
3485 | }, |
3486 | /* SHIFT_ASHIFTRT */ | |
3487 | { | |
5ddb6eca JL |
3488 | { "shar.b\t%X0", OLD_CC_SET_ZNV }, |
3489 | { "shar.w\t%T0", OLD_CC_SET_ZNV }, | |
3490 | { "shar.l\t%S0", OLD_CC_SET_ZNV } | |
48837e29 DE |
3491 | } |
3492 | } | |
3493 | }; | |
07aae5c2 | 3494 | |
51c0c1d7 JL |
3495 | static const struct shift_insn shift_two[3][3] = |
3496 | { | |
3497 | /* SHIFT_ASHIFT */ | |
3498 | { | |
5ddb6eca JL |
3499 | { "shll.b\t#2,%X0", OLD_CC_SET_ZNV }, |
3500 | { "shll.w\t#2,%T0", OLD_CC_SET_ZNV }, | |
3501 | { "shll.l\t#2,%S0", OLD_CC_SET_ZNV } | |
51c0c1d7 JL |
3502 | }, |
3503 | /* SHIFT_LSHIFTRT */ | |
3504 | { | |
5ddb6eca JL |
3505 | { "shlr.b\t#2,%X0", OLD_CC_SET_ZNV }, |
3506 | { "shlr.w\t#2,%T0", OLD_CC_SET_ZNV }, | |
3507 | { "shlr.l\t#2,%S0", OLD_CC_SET_ZNV } | |
51c0c1d7 JL |
3508 | }, |
3509 | /* SHIFT_ASHIFTRT */ | |
3510 | { | |
5ddb6eca JL |
3511 | { "shar.b\t#2,%X0", OLD_CC_SET_ZNV }, |
3512 | { "shar.w\t#2,%T0", OLD_CC_SET_ZNV }, | |
3513 | { "shar.l\t#2,%S0", OLD_CC_SET_ZNV } | |
51c0c1d7 JL |
3514 | } |
3515 | }; | |
3516 | ||
48837e29 DE |
3517 | /* Rotates are organized by which shift they'll be used in implementing. |
3518 | There's no need to record whether the cc is valid afterwards because | |
3519 | it is the AND insn that will decide this. */ | |
07aae5c2 | 3520 | |
48837e29 DE |
3521 | static const char *const rotate_one[2][3][3] = |
3522 | { | |
3523 | /* H8/300 */ | |
3524 | { | |
3525 | /* SHIFT_ASHIFT */ | |
3526 | { | |
51c0c1d7 JL |
3527 | "rotr\t%X0", |
3528 | "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0", | |
48837e29 DE |
3529 | 0 |
3530 | }, | |
3531 | /* SHIFT_LSHIFTRT */ | |
3532 | { | |
51c0c1d7 JL |
3533 | "rotl\t%X0", |
3534 | "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0", | |
48837e29 DE |
3535 | 0 |
3536 | }, | |
3537 | /* SHIFT_ASHIFTRT */ | |
3538 | { | |
51c0c1d7 JL |
3539 | "rotl\t%X0", |
3540 | "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0", | |
48837e29 | 3541 | 0 |
07aae5c2 | 3542 | } |
48837e29 DE |
3543 | }, |
3544 | /* H8/300H */ | |
3545 | { | |
3546 | /* SHIFT_ASHIFT */ | |
3547 | { | |
51c0c1d7 JL |
3548 | "rotr.b\t%X0", |
3549 | "rotr.w\t%T0", | |
3550 | "rotr.l\t%S0" | |
48837e29 DE |
3551 | }, |
3552 | /* SHIFT_LSHIFTRT */ | |
07aae5c2 | 3553 | { |
51c0c1d7 JL |
3554 | "rotl.b\t%X0", |
3555 | "rotl.w\t%T0", | |
3556 | "rotl.l\t%S0" | |
48837e29 DE |
3557 | }, |
3558 | /* SHIFT_ASHIFTRT */ | |
3559 | { | |
51c0c1d7 JL |
3560 | "rotl.b\t%X0", |
3561 | "rotl.w\t%T0", | |
3562 | "rotl.l\t%S0" | |
48837e29 DE |
3563 | } |
3564 | } | |
3565 | }; | |
3566 | ||
51c0c1d7 JL |
3567 | static const char *const rotate_two[3][3] = |
3568 | { | |
3569 | /* SHIFT_ASHIFT */ | |
3570 | { | |
3571 | "rotr.b\t#2,%X0", | |
3572 | "rotr.w\t#2,%T0", | |
3573 | "rotr.l\t#2,%S0" | |
3574 | }, | |
3575 | /* SHIFT_LSHIFTRT */ | |
3576 | { | |
3577 | "rotl.b\t#2,%X0", | |
3578 | "rotl.w\t#2,%T0", | |
3579 | "rotl.l\t#2,%S0" | |
3580 | }, | |
3581 | /* SHIFT_ASHIFTRT */ | |
3582 | { | |
3583 | "rotl.b\t#2,%X0", | |
3584 | "rotl.w\t#2,%T0", | |
3585 | "rotl.l\t#2,%S0" | |
3586 | } | |
3587 | }; | |
3588 | ||
35fb3d1f KH |
3589 | struct shift_info { |
3590 | /* Shift algorithm. */ | |
3591 | enum shift_alg alg; | |
3592 | ||
3593 | /* The number of bits to be shifted by shift1 and shift2. Valid | |
3594 | when ALG is SHIFT_SPECIAL. */ | |
3595 | unsigned int remainder; | |
3596 | ||
3597 | /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */ | |
3598 | const char *special; | |
3599 | ||
3600 | /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE | |
9cd10576 | 3601 | or SHIFT_SPECIAL, and REMAINDER is nonzero. */ |
35fb3d1f KH |
3602 | const char *shift1; |
3603 | ||
3604 | /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE | |
9cd10576 | 3605 | or SHIFT_SPECIAL, and REMAINDER is nonzero. */ |
35fb3d1f KH |
3606 | const char *shift2; |
3607 | ||
45ca2106 | 3608 | /* CC status for SHIFT_INLINE. */ |
5ddb6eca | 3609 | enum attr_old_cc cc_inline; |
45ca2106 KH |
3610 | |
3611 | /* CC status for SHIFT_SPECIAL. */ | |
5ddb6eca | 3612 | enum attr_old_cc cc_special; |
35fb3d1f KH |
3613 | }; |
3614 | ||
cb713a8d KH |
3615 | static void get_shift_alg (enum shift_type, |
3616 | enum shift_mode, unsigned int, | |
3617 | struct shift_info *); | |
441d04c6 | 3618 | |
c009a745 KH |
3619 | /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the |
3620 | best algorithm for doing the shift. The assembler code is stored | |
5ec0b66e | 3621 | in the pointers in INFO. We achieve the maximum efficiency in most |
27c1afd5 | 3622 | cases. |
5ec0b66e KH |
3623 | |
3624 | We first determine the strategy of the shift algorithm by a table | |
3625 | lookup. If that tells us to use a hand crafted assembly code, we | |
3626 | go into the big switch statement to find what that is. Otherwise, | |
3627 | we resort to a generic way, such as inlining. In either case, the | |
3628 | result is returned through INFO. */ | |
48837e29 | 3629 | |
cb33eb17 | 3630 | static void |
cb713a8d KH |
3631 | get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode, |
3632 | unsigned int count, struct shift_info *info) | |
48837e29 | 3633 | { |
b9b575e6 | 3634 | enum h8_cpu cpu; |
769828ab | 3635 | |
27c1afd5 | 3636 | if (TARGET_H8300S) |
b9b575e6 | 3637 | cpu = H8_S; |
2f6bd6eb YS |
3638 | else |
3639 | cpu = H8_300H; | |
769828ab | 3640 | |
96eaf358 | 3641 | /* Find the shift algorithm. */ |
b9b575e6 | 3642 | info->alg = SHIFT_LOOP; |
48837e29 DE |
3643 | switch (shift_mode) |
3644 | { | |
3645 | case QIshift: | |
b9b575e6 | 3646 | if (count < GET_MODE_BITSIZE (QImode)) |
96eaf358 KH |
3647 | info->alg = shift_alg_qi[cpu][shift_type][count]; |
3648 | break; | |
769828ab | 3649 | |
96eaf358 | 3650 | case HIshift: |
b9b575e6 | 3651 | if (count < GET_MODE_BITSIZE (HImode)) |
96eaf358 KH |
3652 | info->alg = shift_alg_hi[cpu][shift_type][count]; |
3653 | break; | |
3654 | ||
3655 | case SIshift: | |
b9b575e6 | 3656 | if (count < GET_MODE_BITSIZE (SImode)) |
96eaf358 KH |
3657 | info->alg = shift_alg_si[cpu][shift_type][count]; |
3658 | break; | |
3659 | ||
3660 | default: | |
8c440872 | 3661 | gcc_unreachable (); |
96eaf358 KH |
3662 | } |
3663 | ||
3664 | /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */ | |
3665 | switch (info->alg) | |
3666 | { | |
3667 | case SHIFT_INLINE: | |
3668 | info->remainder = count; | |
3669 | /* Fall through. */ | |
3670 | ||
3671 | case SHIFT_LOOP: | |
3672 | /* It is up to the caller to know that looping clobbers cc. */ | |
3673 | info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler; | |
3674 | info->shift2 = shift_two[shift_type][shift_mode].assembler; | |
45ca2106 | 3675 | info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid; |
96eaf358 KH |
3676 | goto end; |
3677 | ||
3678 | case SHIFT_ROT_AND: | |
3679 | info->shift1 = rotate_one[cpu_type][shift_type][shift_mode]; | |
3680 | info->shift2 = rotate_two[shift_type][shift_mode]; | |
5ddb6eca | 3681 | info->cc_inline = OLD_CC_CLOBBER; |
96eaf358 KH |
3682 | goto end; |
3683 | ||
3684 | case SHIFT_SPECIAL: | |
3685 | /* REMAINDER is 0 for most cases, so initialize it to 0. */ | |
3686 | info->remainder = 0; | |
3687 | info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler; | |
3688 | info->shift2 = shift_two[shift_type][shift_mode].assembler; | |
45ca2106 | 3689 | info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid; |
5ddb6eca | 3690 | info->cc_special = OLD_CC_CLOBBER; |
96eaf358 KH |
3691 | break; |
3692 | } | |
51c0c1d7 | 3693 | |
96eaf358 KH |
3694 | /* Here we only deal with SHIFT_SPECIAL. */ |
3695 | switch (shift_mode) | |
3696 | { | |
3697 | case QIshift: | |
769828ab KH |
3698 | /* For ASHIFTRT by 7 bits, the sign bit is simply replicated |
3699 | through the entire value. */ | |
8c440872 NS |
3700 | gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7); |
3701 | info->special = "shll\t%X0\n\tsubx\t%X0,%X0"; | |
3702 | goto end; | |
769828ab KH |
3703 | |
3704 | case HIshift: | |
769828ab | 3705 | if (count == 7) |
51c0c1d7 | 3706 | { |
a77b1dbc | 3707 | switch (shift_type) |
51c0c1d7 | 3708 | { |
a77b1dbc | 3709 | case SHIFT_ASHIFT: |
27c1afd5 | 3710 | info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0"; |
692b7eb3 | 3711 | goto end; |
a77b1dbc | 3712 | case SHIFT_LSHIFTRT: |
27c1afd5 | 3713 | info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0"; |
692b7eb3 | 3714 | goto end; |
a77b1dbc | 3715 | case SHIFT_ASHIFTRT: |
35fb3d1f | 3716 | info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0"; |
692b7eb3 | 3717 | goto end; |
48837e29 | 3718 | } |
07aae5c2 | 3719 | } |
01512446 | 3720 | else if ((count >= 8 && count <= 13) |
a38b3eea | 3721 | || (TARGET_H8300S && count == 14)) |
07aae5c2 | 3722 | { |
a7812c0b KH |
3723 | info->remainder = count - 8; |
3724 | ||
51c0c1d7 | 3725 | switch (shift_type) |
48837e29 | 3726 | { |
51c0c1d7 | 3727 | case SHIFT_ASHIFT: |
35fb3d1f | 3728 | info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0"; |
692b7eb3 | 3729 | goto end; |
51c0c1d7 | 3730 | case SHIFT_LSHIFTRT: |
27c1afd5 | 3731 | info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0"; |
5ddb6eca | 3732 | info->cc_special = OLD_CC_SET_ZNV; |
692b7eb3 | 3733 | goto end; |
51c0c1d7 | 3734 | case SHIFT_ASHIFTRT: |
27c1afd5 | 3735 | info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0"; |
5ddb6eca | 3736 | info->cc_special = OLD_CC_SET_ZNV; |
692b7eb3 | 3737 | goto end; |
51c0c1d7 JL |
3738 | } |
3739 | } | |
5e98fba2 DD |
3740 | else if (count == 14) |
3741 | { | |
3742 | switch (shift_type) | |
3743 | { | |
3744 | case SHIFT_ASHIFT: | |
5e98fba2 | 3745 | case SHIFT_LSHIFTRT: |
27c1afd5 | 3746 | goto end; |
5e98fba2 DD |
3747 | goto end; |
3748 | case SHIFT_ASHIFTRT: | |
27c1afd5 | 3749 | if (TARGET_H8300H) |
45ca2106 KH |
3750 | { |
3751 | info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0"; | |
5ddb6eca | 3752 | info->cc_special = OLD_CC_SET_ZNV; |
45ca2106 | 3753 | } |
5e98fba2 | 3754 | else /* TARGET_H8300S */ |
8c440872 | 3755 | gcc_unreachable (); |
5e98fba2 DD |
3756 | goto end; |
3757 | } | |
3758 | } | |
1e41e866 | 3759 | else if (count == 15) |
51c0c1d7 | 3760 | { |
1e41e866 KH |
3761 | switch (shift_type) |
3762 | { | |
3763 | case SHIFT_ASHIFT: | |
3764 | info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0"; | |
3765 | goto end; | |
3766 | case SHIFT_LSHIFTRT: | |
3767 | info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0"; | |
3768 | goto end; | |
3769 | case SHIFT_ASHIFTRT: | |
3770 | info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0"; | |
3771 | goto end; | |
3772 | } | |
07aae5c2 | 3773 | } |
8c440872 | 3774 | gcc_unreachable (); |
51c0c1d7 | 3775 | |
48837e29 | 3776 | case SIshift: |
27c1afd5 | 3777 | if (count == 8) |
e6bcfef9 JS |
3778 | { |
3779 | switch (shift_type) | |
3780 | { | |
3781 | case SHIFT_ASHIFT: | |
35fb3d1f | 3782 | info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0"; |
692b7eb3 | 3783 | goto end; |
e6bcfef9 | 3784 | case SHIFT_LSHIFTRT: |
35fb3d1f | 3785 | info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0"; |
692b7eb3 | 3786 | goto end; |
e6bcfef9 | 3787 | case SHIFT_ASHIFTRT: |
35fb3d1f | 3788 | info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0"; |
692b7eb3 | 3789 | goto end; |
e6bcfef9 JS |
3790 | } |
3791 | } | |
27c1afd5 | 3792 | else if (count == 15) |
dd69e230 KH |
3793 | { |
3794 | switch (shift_type) | |
3795 | { | |
3796 | case SHIFT_ASHIFT: | |
3797 | info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0"; | |
5ddb6eca | 3798 | info->cc_special = OLD_CC_SET_ZNV; |
dd69e230 KH |
3799 | goto end; |
3800 | case SHIFT_LSHIFTRT: | |
18cf8dda | 3801 | info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0"; |
5ddb6eca | 3802 | info->cc_special = OLD_CC_SET_ZNV; |
dd69e230 | 3803 | goto end; |
aefc5826 | 3804 | case SHIFT_ASHIFTRT: |
8c440872 | 3805 | gcc_unreachable (); |
dd69e230 KH |
3806 | } |
3807 | } | |
27c1afd5 | 3808 | else if ((TARGET_H8300H && count >= 16 && count <= 19) |
01512446 | 3809 | || (TARGET_H8300S && count >= 16 && count <= 21)) |
48837e29 | 3810 | { |
a7812c0b KH |
3811 | info->remainder = count - 16; |
3812 | ||
48837e29 DE |
3813 | switch (shift_type) |
3814 | { | |
3815 | case SHIFT_ASHIFT: | |
35fb3d1f | 3816 | info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0"; |
692b7eb3 | 3817 | goto end; |
51c0c1d7 | 3818 | case SHIFT_LSHIFTRT: |
27c1afd5 | 3819 | info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0"; |
5ddb6eca | 3820 | info->cc_special = OLD_CC_SET_ZNV; |
f9477efd KH |
3821 | goto end; |
3822 | case SHIFT_ASHIFTRT: | |
27c1afd5 | 3823 | info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0"; |
5ddb6eca | 3824 | info->cc_special = OLD_CC_SET_ZNV; |
7f473594 KH |
3825 | goto end; |
3826 | } | |
3827 | } | |
4a4ae922 | 3828 | else if ((TARGET_H8300H && count == 24) |
01512446 | 3829 | || (TARGET_H8300S && count >= 24 && count <= 25)) |
e6bcfef9 | 3830 | { |
4a4ae922 KH |
3831 | info->remainder = count - 24; |
3832 | ||
e6bcfef9 JS |
3833 | switch (shift_type) |
3834 | { | |
3835 | case SHIFT_ASHIFT: | |
35fb3d1f | 3836 | info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0"; |
692b7eb3 | 3837 | goto end; |
e6bcfef9 | 3838 | case SHIFT_LSHIFTRT: |
35fb3d1f | 3839 | info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0"; |
5ddb6eca | 3840 | info->cc_special = OLD_CC_SET_ZNV; |
692b7eb3 | 3841 | goto end; |
e6bcfef9 | 3842 | case SHIFT_ASHIFTRT: |
35fb3d1f | 3843 | info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0"; |
5ddb6eca | 3844 | info->cc_special = OLD_CC_SET_ZNV; |
692b7eb3 | 3845 | goto end; |
e6bcfef9 JS |
3846 | } |
3847 | } | |
27c1afd5 | 3848 | else if (count == 28) |
1e5bdc40 KH |
3849 | { |
3850 | switch (shift_type) | |
3851 | { | |
3852 | case SHIFT_ASHIFT: | |
3853 | if (TARGET_H8300H) | |
3854 | info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; | |
3855 | else | |
3856 | info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0"; | |
1e5bdc40 KH |
3857 | goto end; |
3858 | case SHIFT_LSHIFTRT: | |
3859 | if (TARGET_H8300H) | |
45ca2106 KH |
3860 | { |
3861 | info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; | |
5ddb6eca | 3862 | info->cc_special = OLD_CC_SET_ZNV; |
45ca2106 | 3863 | } |
1e5bdc40 | 3864 | else |
a7612343 | 3865 | info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0"; |
1e5bdc40 KH |
3866 | goto end; |
3867 | case SHIFT_ASHIFTRT: | |
8c440872 | 3868 | gcc_unreachable (); |
1e5bdc40 KH |
3869 | } |
3870 | } | |
27c1afd5 | 3871 | else if (count == 29) |
1e5bdc40 KH |
3872 | { |
3873 | switch (shift_type) | |
3874 | { | |
3875 | case SHIFT_ASHIFT: | |
3876 | if (TARGET_H8300H) | |
3877 | info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; | |
3878 | else | |
3879 | info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; | |
1e5bdc40 KH |
3880 | goto end; |
3881 | case SHIFT_LSHIFTRT: | |
3882 | if (TARGET_H8300H) | |
45ca2106 KH |
3883 | { |
3884 | info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; | |
5ddb6eca | 3885 | info->cc_special = OLD_CC_SET_ZNV; |
45ca2106 | 3886 | } |
1e5bdc40 | 3887 | else |
45ca2106 KH |
3888 | { |
3889 | info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; | |
5ddb6eca | 3890 | info->cc_special = OLD_CC_SET_ZNV; |
45ca2106 | 3891 | } |
1e5bdc40 KH |
3892 | goto end; |
3893 | case SHIFT_ASHIFTRT: | |
8c440872 | 3894 | gcc_unreachable (); |
1e5bdc40 KH |
3895 | } |
3896 | } | |
27c1afd5 | 3897 | else if (count == 30) |
1e5bdc40 KH |
3898 | { |
3899 | switch (shift_type) | |
3900 | { | |
3901 | case SHIFT_ASHIFT: | |
3902 | if (TARGET_H8300H) | |
3903 | info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; | |
3904 | else | |
3905 | info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0"; | |
1e5bdc40 KH |
3906 | goto end; |
3907 | case SHIFT_LSHIFTRT: | |
3908 | if (TARGET_H8300H) | |
a7612343 | 3909 | info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; |
1e5bdc40 | 3910 | else |
a7612343 | 3911 | info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0"; |
1e5bdc40 KH |
3912 | goto end; |
3913 | case SHIFT_ASHIFTRT: | |
8c440872 | 3914 | gcc_unreachable (); |
1e5bdc40 KH |
3915 | } |
3916 | } | |
48837e29 DE |
3917 | else if (count == 31) |
3918 | { | |
27c1afd5 | 3919 | switch (shift_type) |
48837e29 | 3920 | { |
27c1afd5 JL |
3921 | case SHIFT_ASHIFT: |
3922 | info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0"; | |
5ddb6eca | 3923 | info->cc_special = OLD_CC_SET_ZNV; |
27c1afd5 JL |
3924 | goto end; |
3925 | case SHIFT_LSHIFTRT: | |
3926 | info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0"; | |
5ddb6eca | 3927 | info->cc_special = OLD_CC_SET_ZNV; |
27c1afd5 JL |
3928 | goto end; |
3929 | case SHIFT_ASHIFTRT: | |
3930 | info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0"; | |
5ddb6eca | 3931 | info->cc_special = OLD_CC_SET_ZNV; |
27c1afd5 | 3932 | goto end; |
48837e29 DE |
3933 | } |
3934 | } | |
8c440872 | 3935 | gcc_unreachable (); |
51c0c1d7 | 3936 | |
48837e29 | 3937 | default: |
8c440872 | 3938 | gcc_unreachable (); |
07aae5c2 | 3939 | } |
48837e29 | 3940 | |
cb33eb17 KH |
3941 | end: |
3942 | if (!TARGET_H8300S) | |
3943 | info->shift2 = NULL; | |
07aae5c2 SC |
3944 | } |
3945 | ||
be1e06df KH |
3946 | /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be |
3947 | needed for some shift with COUNT and MODE. Return 0 otherwise. */ | |
3948 | ||
3949 | int | |
70033749 | 3950 | h8300_shift_needs_scratch_p (int count, machine_mode mode, enum rtx_code type) |
be1e06df | 3951 | { |
b9b575e6 | 3952 | enum h8_cpu cpu; |
be1e06df KH |
3953 | int a, lr, ar; |
3954 | ||
3955 | if (GET_MODE_BITSIZE (mode) <= count) | |
3956 | return 1; | |
3957 | ||
3958 | /* Find out the target CPU. */ | |
27c1afd5 | 3959 | if (TARGET_H8300S) |
b9b575e6 | 3960 | cpu = H8_S; |
2f6bd6eb YS |
3961 | else |
3962 | cpu = H8_300H; | |
be1e06df KH |
3963 | |
3964 | /* Find the shift algorithm. */ | |
3965 | switch (mode) | |
3966 | { | |
4e10a5a7 | 3967 | case E_QImode: |
be1e06df KH |
3968 | a = shift_alg_qi[cpu][SHIFT_ASHIFT][count]; |
3969 | lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count]; | |
3970 | ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count]; | |
3971 | break; | |
3972 | ||
4e10a5a7 | 3973 | case E_HImode: |
be1e06df KH |
3974 | a = shift_alg_hi[cpu][SHIFT_ASHIFT][count]; |
3975 | lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count]; | |
3976 | ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count]; | |
3977 | break; | |
3978 | ||
4e10a5a7 | 3979 | case E_SImode: |
be1e06df KH |
3980 | a = shift_alg_si[cpu][SHIFT_ASHIFT][count]; |
3981 | lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count]; | |
3982 | ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count]; | |
3983 | break; | |
3984 | ||
3985 | default: | |
8c440872 | 3986 | gcc_unreachable (); |
be1e06df KH |
3987 | } |
3988 | ||
aa2fb4dd | 3989 | /* On H8/300H, count == 8 uses a scratch register. */ |
70033749 JL |
3990 | if (type == CLOBBER) |
3991 | return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP | |
3992 | || (TARGET_H8300H && mode == SImode && count == 8)); | |
3993 | else if (type == ASHIFT) | |
3994 | return (a == SHIFT_LOOP | |
3995 | || (TARGET_H8300H && mode == SImode && count == 8)); | |
3996 | else if (type == LSHIFTRT) | |
3997 | return (lr == SHIFT_LOOP | |
3998 | || (TARGET_H8300H && mode == SImode && count == 8)); | |
3999 | else if (type == ASHIFTRT) | |
4000 | return (ar == SHIFT_LOOP | |
4001 | || (TARGET_H8300H && mode == SImode && count == 8)); | |
be1e06df KH |
4002 | } |
4003 | ||
e9eba255 | 4004 | /* Output the assembler code for doing shifts. */ |
48837e29 | 4005 | |
441d04c6 | 4006 | const char * |
cb713a8d | 4007 | output_a_shift (rtx *operands) |
07aae5c2 | 4008 | { |
48837e29 | 4009 | static int loopend_lab; |
48837e29 | 4010 | rtx shift = operands[3]; |
ef4bddc2 | 4011 | machine_mode mode = GET_MODE (shift); |
48837e29 DE |
4012 | enum rtx_code code = GET_CODE (shift); |
4013 | enum shift_type shift_type; | |
4014 | enum shift_mode shift_mode; | |
35fb3d1f | 4015 | struct shift_info info; |
8c440872 | 4016 | int n; |
48837e29 DE |
4017 | |
4018 | loopend_lab++; | |
4019 | ||
4020 | switch (mode) | |
4021 | { | |
4e10a5a7 | 4022 | case E_QImode: |
48837e29 DE |
4023 | shift_mode = QIshift; |
4024 | break; | |
4e10a5a7 | 4025 | case E_HImode: |
48837e29 DE |
4026 | shift_mode = HIshift; |
4027 | break; | |
4e10a5a7 | 4028 | case E_SImode: |
48837e29 DE |
4029 | shift_mode = SIshift; |
4030 | break; | |
4031 | default: | |
8c440872 | 4032 | gcc_unreachable (); |
48837e29 | 4033 | } |
07aae5c2 | 4034 | |
48837e29 | 4035 | switch (code) |
07aae5c2 | 4036 | { |
48837e29 DE |
4037 | case ASHIFTRT: |
4038 | shift_type = SHIFT_ASHIFTRT; | |
4039 | break; | |
4040 | case LSHIFTRT: | |
4041 | shift_type = SHIFT_LSHIFTRT; | |
4042 | break; | |
4043 | case ASHIFT: | |
4044 | shift_type = SHIFT_ASHIFT; | |
4045 | break; | |
4046 | default: | |
8c440872 | 4047 | gcc_unreachable (); |
48837e29 | 4048 | } |
07aae5c2 | 4049 | |
8c440872 NS |
4050 | /* This case must be taken care of by one of the two splitters |
4051 | that convert a variable shift into a loop. */ | |
4052 | gcc_assert (GET_CODE (operands[2]) == CONST_INT); | |
4053 | ||
4054 | n = INTVAL (operands[2]); | |
4055 | ||
4056 | /* If the count is negative, make it 0. */ | |
4057 | if (n < 0) | |
4058 | n = 0; | |
4059 | /* If the count is too big, truncate it. | |
4060 | ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to | |
4061 | do the intuitive thing. */ | |
4062 | else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) | |
4063 | n = GET_MODE_BITSIZE (mode); | |
4064 | ||
4065 | get_shift_alg (shift_type, shift_mode, n, &info); | |
4066 | ||
4067 | switch (info.alg) | |
48837e29 | 4068 | { |
8c440872 NS |
4069 | case SHIFT_SPECIAL: |
4070 | output_asm_insn (info.special, operands); | |
4071 | /* Fall through. */ | |
48837e29 | 4072 | |
8c440872 NS |
4073 | case SHIFT_INLINE: |
4074 | n = info.remainder; | |
48837e29 | 4075 | |
8c440872 NS |
4076 | /* Emit two bit shifts first. */ |
4077 | if (info.shift2 != NULL) | |
48837e29 | 4078 | { |
8c440872 NS |
4079 | for (; n > 1; n -= 2) |
4080 | output_asm_insn (info.shift2, operands); | |
4081 | } | |
51c0c1d7 | 4082 | |
8c440872 NS |
4083 | /* Now emit one bit shifts for any residual. */ |
4084 | for (; n > 0; n--) | |
4085 | output_asm_insn (info.shift1, operands); | |
4086 | return ""; | |
4087 | ||
4088 | case SHIFT_ROT_AND: | |
4089 | { | |
4090 | int m = GET_MODE_BITSIZE (mode) - n; | |
4091 | const int mask = (shift_type == SHIFT_ASHIFT | |
4092 | ? ((1 << m) - 1) << n | |
4093 | : (1 << m) - 1); | |
4094 | char insn_buf[200]; | |
4095 | ||
4096 | /* Not all possibilities of rotate are supported. They shouldn't | |
4097 | be generated, but let's watch for 'em. */ | |
4098 | gcc_assert (info.shift1); | |
4099 | ||
4100 | /* Emit two bit rotates first. */ | |
4101 | if (info.shift2 != NULL) | |
48837e29 | 4102 | { |
8c440872 NS |
4103 | for (; m > 1; m -= 2) |
4104 | output_asm_insn (info.shift2, operands); | |
4105 | } | |
4106 | ||
4107 | /* Now single bit rotates for any residual. */ | |
4108 | for (; m > 0; m--) | |
4109 | output_asm_insn (info.shift1, operands); | |
4110 | ||
4111 | /* Now mask off the high bits. */ | |
4112 | switch (mode) | |
4113 | { | |
4e10a5a7 | 4114 | case E_QImode: |
8c440872 NS |
4115 | sprintf (insn_buf, "and\t#%d,%%X0", mask); |
4116 | break; | |
51c0c1d7 | 4117 | |
4e10a5a7 | 4118 | case E_HImode: |
8c440872 NS |
4119 | sprintf (insn_buf, "and.w\t#%d,%%T0", mask); |
4120 | break; | |
51c0c1d7 | 4121 | |
8c440872 NS |
4122 | default: |
4123 | gcc_unreachable (); | |
48837e29 | 4124 | } |
b5eaf9ba | 4125 | |
8c440872 NS |
4126 | output_asm_insn (insn_buf, operands); |
4127 | return ""; | |
4128 | } | |
b5eaf9ba | 4129 | |
8c440872 NS |
4130 | case SHIFT_LOOP: |
4131 | /* A loop to shift by a "large" constant value. | |
4132 | If we have shift-by-2 insns, use them. */ | |
4133 | if (info.shift2 != NULL) | |
4134 | { | |
4135 | fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2, | |
4136 | names_big[REGNO (operands[4])]); | |
4137 | fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); | |
4138 | output_asm_insn (info.shift2, operands); | |
4139 | output_asm_insn ("add #0xff,%X4", operands); | |
4140 | fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); | |
4141 | if (n % 2) | |
4142 | output_asm_insn (info.shift1, operands); | |
4143 | } | |
4144 | else | |
4145 | { | |
4146 | fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n, | |
4147 | names_big[REGNO (operands[4])]); | |
4148 | fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); | |
4149 | output_asm_insn (info.shift1, operands); | |
4150 | output_asm_insn ("add #0xff,%X4", operands); | |
4151 | fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); | |
51c0c1d7 | 4152 | } |
8c440872 NS |
4153 | return ""; |
4154 | ||
4155 | default: | |
4156 | gcc_unreachable (); | |
07aae5c2 | 4157 | } |
07aae5c2 | 4158 | } |
86855e8c | 4159 | |
0a2aaacc | 4160 | /* Count the number of assembly instructions in a string TEMPL. */ |
e9eba255 | 4161 | |
86855e8c | 4162 | static unsigned int |
0a2aaacc | 4163 | h8300_asm_insn_count (const char *templ) |
86855e8c KH |
4164 | { |
4165 | unsigned int count = 1; | |
4166 | ||
0a2aaacc KG |
4167 | for (; *templ; templ++) |
4168 | if (*templ == '\n') | |
86855e8c KH |
4169 | count++; |
4170 | ||
4171 | return count; | |
4172 | } | |
4173 | ||
e9eba255 KH |
4174 | /* Compute the length of a shift insn. */ |
4175 | ||
86855e8c | 4176 | unsigned int |
cb713a8d | 4177 | compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands) |
86855e8c KH |
4178 | { |
4179 | rtx shift = operands[3]; | |
ef4bddc2 | 4180 | machine_mode mode = GET_MODE (shift); |
86855e8c KH |
4181 | enum rtx_code code = GET_CODE (shift); |
4182 | enum shift_type shift_type; | |
4183 | enum shift_mode shift_mode; | |
4184 | struct shift_info info; | |
4185 | unsigned int wlength = 0; | |
4186 | ||
4187 | switch (mode) | |
4188 | { | |
4e10a5a7 | 4189 | case E_QImode: |
86855e8c KH |
4190 | shift_mode = QIshift; |
4191 | break; | |
4e10a5a7 | 4192 | case E_HImode: |
86855e8c KH |
4193 | shift_mode = HIshift; |
4194 | break; | |
4e10a5a7 | 4195 | case E_SImode: |
86855e8c KH |
4196 | shift_mode = SIshift; |
4197 | break; | |
4198 | default: | |
8c440872 | 4199 | gcc_unreachable (); |
86855e8c KH |
4200 | } |
4201 | ||
4202 | switch (code) | |
4203 | { | |
4204 | case ASHIFTRT: | |
4205 | shift_type = SHIFT_ASHIFTRT; | |
4206 | break; | |
4207 | case LSHIFTRT: | |
4208 | shift_type = SHIFT_LSHIFTRT; | |
4209 | break; | |
4210 | case ASHIFT: | |
4211 | shift_type = SHIFT_ASHIFT; | |
4212 | break; | |
4213 | default: | |
8c440872 | 4214 | gcc_unreachable (); |
86855e8c KH |
4215 | } |
4216 | ||
4217 | if (GET_CODE (operands[2]) != CONST_INT) | |
4218 | { | |
4219 | /* Get the assembler code to do one shift. */ | |
4220 | get_shift_alg (shift_type, shift_mode, 1, &info); | |
4221 | ||
4222 | return (4 + h8300_asm_insn_count (info.shift1)) * 2; | |
4223 | } | |
4224 | else | |
4225 | { | |
4226 | int n = INTVAL (operands[2]); | |
4227 | ||
4228 | /* If the count is negative, make it 0. */ | |
4229 | if (n < 0) | |
4230 | n = 0; | |
4231 | /* If the count is too big, truncate it. | |
4232 | ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to | |
4233 | do the intuitive thing. */ | |
4234 | else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) | |
4235 | n = GET_MODE_BITSIZE (mode); | |
4236 | ||
4237 | get_shift_alg (shift_type, shift_mode, n, &info); | |
4238 | ||
4239 | switch (info.alg) | |
4240 | { | |
4241 | case SHIFT_SPECIAL: | |
4242 | wlength += h8300_asm_insn_count (info.special); | |
41c3eb5d KH |
4243 | |
4244 | /* Every assembly instruction used in SHIFT_SPECIAL case | |
4245 | takes 2 bytes except xor.l, which takes 4 bytes, so if we | |
4246 | see xor.l, we just pretend that xor.l counts as two insns | |
4247 | so that the insn length will be computed correctly. */ | |
4248 | if (strstr (info.special, "xor.l") != NULL) | |
4249 | wlength++; | |
4250 | ||
86855e8c KH |
4251 | /* Fall through. */ |
4252 | ||
4253 | case SHIFT_INLINE: | |
4254 | n = info.remainder; | |
4255 | ||
4256 | if (info.shift2 != NULL) | |
4257 | { | |
4258 | wlength += h8300_asm_insn_count (info.shift2) * (n / 2); | |
4259 | n = n % 2; | |
4260 | } | |
4261 | ||
4262 | wlength += h8300_asm_insn_count (info.shift1) * n; | |
6b148bd9 | 4263 | |
86855e8c KH |
4264 | return 2 * wlength; |
4265 | ||
4266 | case SHIFT_ROT_AND: | |
4267 | { | |
4268 | int m = GET_MODE_BITSIZE (mode) - n; | |
4269 | ||
4270 | /* Not all possibilities of rotate are supported. They shouldn't | |
4271 | be generated, but let's watch for 'em. */ | |
8c440872 | 4272 | gcc_assert (info.shift1); |
86855e8c KH |
4273 | |
4274 | if (info.shift2 != NULL) | |
4275 | { | |
4276 | wlength += h8300_asm_insn_count (info.shift2) * (m / 2); | |
4277 | m = m % 2; | |
4278 | } | |
4279 | ||
4280 | wlength += h8300_asm_insn_count (info.shift1) * m; | |
6b148bd9 | 4281 | |
86855e8c KH |
4282 | /* Now mask off the high bits. */ |
4283 | switch (mode) | |
4284 | { | |
4e10a5a7 | 4285 | case E_QImode: |
86855e8c KH |
4286 | wlength += 1; |
4287 | break; | |
4e10a5a7 | 4288 | case E_HImode: |
86855e8c KH |
4289 | wlength += 2; |
4290 | break; | |
4e10a5a7 | 4291 | case E_SImode: |
86855e8c KH |
4292 | wlength += 3; |
4293 | break; | |
4294 | default: | |
8c440872 | 4295 | gcc_unreachable (); |
86855e8c KH |
4296 | } |
4297 | return 2 * wlength; | |
4298 | } | |
4299 | ||
4300 | case SHIFT_LOOP: | |
4301 | /* A loop to shift by a "large" constant value. | |
4302 | If we have shift-by-2 insns, use them. */ | |
4303 | if (info.shift2 != NULL) | |
4304 | { | |
4305 | wlength += 3 + h8300_asm_insn_count (info.shift2); | |
4306 | if (n % 2) | |
4307 | wlength += h8300_asm_insn_count (info.shift1); | |
4308 | } | |
4309 | else | |
4310 | { | |
4311 | wlength += 3 + h8300_asm_insn_count (info.shift1); | |
4312 | } | |
4313 | return 2 * wlength; | |
4314 | ||
4315 | default: | |
8c440872 | 4316 | gcc_unreachable (); |
86855e8c KH |
4317 | } |
4318 | } | |
4319 | } | |
45ca2106 | 4320 | |
e9eba255 KH |
4321 | /* Compute which flag bits are valid after a shift insn. */ |
4322 | ||
f16897cb | 4323 | int |
cb713a8d | 4324 | compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands) |
45ca2106 KH |
4325 | { |
4326 | rtx shift = operands[3]; | |
ef4bddc2 | 4327 | machine_mode mode = GET_MODE (shift); |
45ca2106 KH |
4328 | enum rtx_code code = GET_CODE (shift); |
4329 | enum shift_type shift_type; | |
4330 | enum shift_mode shift_mode; | |
4331 | struct shift_info info; | |
8c440872 NS |
4332 | int n; |
4333 | ||
45ca2106 KH |
4334 | switch (mode) |
4335 | { | |
4e10a5a7 | 4336 | case E_QImode: |
45ca2106 KH |
4337 | shift_mode = QIshift; |
4338 | break; | |
4e10a5a7 | 4339 | case E_HImode: |
45ca2106 KH |
4340 | shift_mode = HIshift; |
4341 | break; | |
4e10a5a7 | 4342 | case E_SImode: |
45ca2106 KH |
4343 | shift_mode = SIshift; |
4344 | break; | |
4345 | default: | |
8c440872 | 4346 | gcc_unreachable (); |
45ca2106 KH |
4347 | } |
4348 | ||
4349 | switch (code) | |
4350 | { | |
4351 | case ASHIFTRT: | |
4352 | shift_type = SHIFT_ASHIFTRT; | |
4353 | break; | |
4354 | case LSHIFTRT: | |
4355 | shift_type = SHIFT_LSHIFTRT; | |
4356 | break; | |
4357 | case ASHIFT: | |
4358 | shift_type = SHIFT_ASHIFT; | |
4359 | break; | |
4360 | default: | |
8c440872 | 4361 | gcc_unreachable (); |
45ca2106 KH |
4362 | } |
4363 | ||
8c440872 NS |
4364 | /* This case must be taken care of by one of the two splitters |
4365 | that convert a variable shift into a loop. */ | |
4366 | gcc_assert (GET_CODE (operands[2]) == CONST_INT); | |
4367 | ||
4368 | n = INTVAL (operands[2]); | |
4369 | ||
4370 | /* If the count is negative, make it 0. */ | |
4371 | if (n < 0) | |
4372 | n = 0; | |
4373 | /* If the count is too big, truncate it. | |
4374 | ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to | |
4375 | do the intuitive thing. */ | |
4376 | else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) | |
4377 | n = GET_MODE_BITSIZE (mode); | |
4378 | ||
4379 | get_shift_alg (shift_type, shift_mode, n, &info); | |
4380 | ||
4381 | switch (info.alg) | |
45ca2106 | 4382 | { |
8c440872 NS |
4383 | case SHIFT_SPECIAL: |
4384 | if (info.remainder == 0) | |
4385 | return info.cc_special; | |
45ca2106 | 4386 | |
8c440872 | 4387 | /* Fall through. */ |
45ca2106 | 4388 | |
8c440872 NS |
4389 | case SHIFT_INLINE: |
4390 | return info.cc_inline; | |
4391 | ||
4392 | case SHIFT_ROT_AND: | |
4393 | /* This case always ends with an and instruction. */ | |
5ddb6eca | 4394 | return OLD_CC_SET_ZNV; |
8c440872 NS |
4395 | |
4396 | case SHIFT_LOOP: | |
4397 | /* A loop to shift by a "large" constant value. | |
4398 | If we have shift-by-2 insns, use them. */ | |
4399 | if (info.shift2 != NULL) | |
45ca2106 | 4400 | { |
8c440872 NS |
4401 | if (n % 2) |
4402 | return info.cc_inline; | |
45ca2106 | 4403 | } |
5ddb6eca | 4404 | return OLD_CC_CLOBBER; |
8c440872 NS |
4405 | |
4406 | default: | |
4407 | gcc_unreachable (); | |
45ca2106 KH |
4408 | } |
4409 | } | |
48837e29 | 4410 | \f |
edd71f0f KH |
4411 | /* A rotation by a non-constant will cause a loop to be generated, in |
4412 | which a rotation by one bit is used. A rotation by a constant, | |
4413 | including the one in the loop, will be taken care of by | |
caf7f21a | 4414 | output_a_rotate () at the insn emit time. */ |
edd71f0f KH |
4415 | |
4416 | int | |
3d2e90d6 | 4417 | expand_a_rotate (rtx operands[]) |
edd71f0f KH |
4418 | { |
4419 | rtx dst = operands[0]; | |
4420 | rtx src = operands[1]; | |
4421 | rtx rotate_amount = operands[2]; | |
ef4bddc2 | 4422 | machine_mode mode = GET_MODE (dst); |
edd71f0f | 4423 | |
beed8fc0 AO |
4424 | if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY) |
4425 | return false; | |
4426 | ||
edd71f0f KH |
4427 | /* We rotate in place. */ |
4428 | emit_move_insn (dst, src); | |
4429 | ||
4430 | if (GET_CODE (rotate_amount) != CONST_INT) | |
4431 | { | |
4432 | rtx counter = gen_reg_rtx (QImode); | |
19f8b229 TS |
4433 | rtx_code_label *start_label = gen_label_rtx (); |
4434 | rtx_code_label *end_label = gen_label_rtx (); | |
edd71f0f KH |
4435 | |
4436 | /* If the rotate amount is less than or equal to 0, | |
4437 | we go out of the loop. */ | |
a556fd39 | 4438 | emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX, |
d43e0b7d | 4439 | QImode, 0, end_label); |
edd71f0f KH |
4440 | |
4441 | /* Initialize the loop counter. */ | |
4442 | emit_move_insn (counter, rotate_amount); | |
4443 | ||
4444 | emit_label (start_label); | |
4445 | ||
4446 | /* Rotate by one bit. */ | |
01ab5574 KH |
4447 | switch (mode) |
4448 | { | |
4e10a5a7 | 4449 | case E_QImode: |
01ab5574 KH |
4450 | emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx)); |
4451 | break; | |
4e10a5a7 | 4452 | case E_HImode: |
01ab5574 KH |
4453 | emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx)); |
4454 | break; | |
4e10a5a7 | 4455 | case E_SImode: |
01ab5574 KH |
4456 | emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx)); |
4457 | break; | |
4458 | default: | |
8c440872 | 4459 | gcc_unreachable (); |
01ab5574 | 4460 | } |
edd71f0f KH |
4461 | |
4462 | /* Decrement the counter by 1. */ | |
01ab5574 | 4463 | emit_insn (gen_addqi3 (counter, counter, constm1_rtx)); |
edd71f0f | 4464 | |
9cd10576 | 4465 | /* If the loop counter is nonzero, we go back to the beginning |
edd71f0f | 4466 | of the loop. */ |
a556fd39 | 4467 | emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1, |
d43e0b7d | 4468 | start_label); |
edd71f0f KH |
4469 | |
4470 | emit_label (end_label); | |
4471 | } | |
4472 | else | |
4473 | { | |
4474 | /* Rotate by AMOUNT bits. */ | |
01ab5574 KH |
4475 | switch (mode) |
4476 | { | |
4e10a5a7 | 4477 | case E_QImode: |
01ab5574 KH |
4478 | emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount)); |
4479 | break; | |
4e10a5a7 | 4480 | case E_HImode: |
01ab5574 KH |
4481 | emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount)); |
4482 | break; | |
4e10a5a7 | 4483 | case E_SImode: |
01ab5574 KH |
4484 | emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount)); |
4485 | break; | |
4486 | default: | |
8c440872 | 4487 | gcc_unreachable (); |
01ab5574 | 4488 | } |
edd71f0f KH |
4489 | } |
4490 | ||
4491 | return 1; | |
4492 | } | |
4493 | ||
e9eba255 | 4494 | /* Output a rotate insn. */ |
edd71f0f KH |
4495 | |
4496 | const char * | |
caf7f21a | 4497 | output_a_rotate (enum rtx_code code, rtx *operands) |
edd71f0f KH |
4498 | { |
4499 | rtx dst = operands[0]; | |
4500 | rtx rotate_amount = operands[2]; | |
4501 | enum shift_mode rotate_mode; | |
4502 | enum shift_type rotate_type; | |
4503 | const char *insn_buf; | |
4504 | int bits; | |
4505 | int amount; | |
ef4bddc2 | 4506 | machine_mode mode = GET_MODE (dst); |
edd71f0f | 4507 | |
8c440872 | 4508 | gcc_assert (GET_CODE (rotate_amount) == CONST_INT); |
edd71f0f KH |
4509 | |
4510 | switch (mode) | |
4511 | { | |
4e10a5a7 | 4512 | case E_QImode: |
edd71f0f KH |
4513 | rotate_mode = QIshift; |
4514 | break; | |
4e10a5a7 | 4515 | case E_HImode: |
edd71f0f KH |
4516 | rotate_mode = HIshift; |
4517 | break; | |
4e10a5a7 | 4518 | case E_SImode: |
edd71f0f KH |
4519 | rotate_mode = SIshift; |
4520 | break; | |
4521 | default: | |
8c440872 | 4522 | gcc_unreachable (); |
edd71f0f KH |
4523 | } |
4524 | ||
4525 | switch (code) | |
4526 | { | |
4527 | case ROTATERT: | |
4528 | rotate_type = SHIFT_ASHIFT; | |
4529 | break; | |
4530 | case ROTATE: | |
4531 | rotate_type = SHIFT_LSHIFTRT; | |
4532 | break; | |
4533 | default: | |
8c440872 | 4534 | gcc_unreachable (); |
edd71f0f KH |
4535 | } |
4536 | ||
4537 | amount = INTVAL (rotate_amount); | |
4538 | ||
4539 | /* Clean up AMOUNT. */ | |
4540 | if (amount < 0) | |
4541 | amount = 0; | |
4542 | if ((unsigned int) amount > GET_MODE_BITSIZE (mode)) | |
4543 | amount = GET_MODE_BITSIZE (mode); | |
4544 | ||
4545 | /* Determine the faster direction. After this phase, amount will be | |
4546 | at most a half of GET_MODE_BITSIZE (mode). */ | |
e0c32c62 | 4547 | if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2) |
edd71f0f KH |
4548 | { |
4549 | /* Flip the direction. */ | |
4550 | amount = GET_MODE_BITSIZE (mode) - amount; | |
4551 | rotate_type = | |
4552 | (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT; | |
4553 | } | |
4554 | ||
4555 | /* See if a byte swap (in HImode) or a word swap (in SImode) can | |
4556 | boost up the rotation. */ | |
27c1afd5 | 4557 | if ((mode == HImode && TARGET_H8300H && amount >= 6) |
edd71f0f KH |
4558 | || (mode == HImode && TARGET_H8300S && amount == 8) |
4559 | || (mode == SImode && TARGET_H8300H && amount >= 10) | |
4560 | || (mode == SImode && TARGET_H8300S && amount >= 13)) | |
4561 | { | |
4562 | switch (mode) | |
4563 | { | |
4e10a5a7 | 4564 | case E_HImode: |
edd71f0f KH |
4565 | /* This code works on any family. */ |
4566 | insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0"; | |
4567 | output_asm_insn (insn_buf, operands); | |
4568 | break; | |
4569 | ||
4e10a5a7 | 4570 | case E_SImode: |
3db11b5c | 4571 | /* This code works on the H8/300H and H8S. */ |
edd71f0f KH |
4572 | insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0"; |
4573 | output_asm_insn (insn_buf, operands); | |
4574 | break; | |
4575 | ||
4576 | default: | |
8c440872 | 4577 | gcc_unreachable (); |
edd71f0f KH |
4578 | } |
4579 | ||
4580 | /* Adjust AMOUNT and flip the direction. */ | |
4581 | amount = GET_MODE_BITSIZE (mode) / 2 - amount; | |
4582 | rotate_type = | |
4583 | (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT; | |
4584 | } | |
4585 | ||
01ab5574 | 4586 | /* Output rotate insns. */ |
edd71f0f KH |
4587 | for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2) |
4588 | { | |
4589 | if (bits == 2) | |
4590 | insn_buf = rotate_two[rotate_type][rotate_mode]; | |
4591 | else | |
4592 | insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode]; | |
2c54abce | 4593 | |
edd71f0f KH |
4594 | for (; amount >= bits; amount -= bits) |
4595 | output_asm_insn (insn_buf, operands); | |
4596 | } | |
4597 | ||
4598 | return ""; | |
4599 | } | |
caf7f21a | 4600 | |
e9eba255 KH |
4601 | /* Compute the length of a rotate insn. */ |
4602 | ||
caf7f21a KH |
4603 | unsigned int |
4604 | compute_a_rotate_length (rtx *operands) | |
4605 | { | |
4606 | rtx src = operands[1]; | |
343fd2c7 | 4607 | rtx amount_rtx = operands[2]; |
ef4bddc2 | 4608 | machine_mode mode = GET_MODE (src); |
caf7f21a KH |
4609 | int amount; |
4610 | unsigned int length = 0; | |
4611 | ||
8c440872 | 4612 | gcc_assert (GET_CODE (amount_rtx) == CONST_INT); |
caf7f21a | 4613 | |
343fd2c7 | 4614 | amount = INTVAL (amount_rtx); |
caf7f21a KH |
4615 | |
4616 | /* Clean up AMOUNT. */ | |
4617 | if (amount < 0) | |
4618 | amount = 0; | |
4619 | if ((unsigned int) amount > GET_MODE_BITSIZE (mode)) | |
4620 | amount = GET_MODE_BITSIZE (mode); | |
4621 | ||
4622 | /* Determine the faster direction. After this phase, amount | |
4623 | will be at most a half of GET_MODE_BITSIZE (mode). */ | |
4624 | if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2) | |
4625 | /* Flip the direction. */ | |
4626 | amount = GET_MODE_BITSIZE (mode) - amount; | |
4627 | ||
4628 | /* See if a byte swap (in HImode) or a word swap (in SImode) can | |
4629 | boost up the rotation. */ | |
27c1afd5 | 4630 | if ((mode == HImode && TARGET_H8300H && amount >= 6) |
caf7f21a KH |
4631 | || (mode == HImode && TARGET_H8300S && amount == 8) |
4632 | || (mode == SImode && TARGET_H8300H && amount >= 10) | |
4633 | || (mode == SImode && TARGET_H8300S && amount >= 13)) | |
4634 | { | |
4635 | /* Adjust AMOUNT and flip the direction. */ | |
4636 | amount = GET_MODE_BITSIZE (mode) / 2 - amount; | |
4637 | length += 6; | |
4638 | } | |
4639 | ||
4640 | /* We use 2-bit rotations on the H8S. */ | |
4641 | if (TARGET_H8300S) | |
4642 | amount = amount / 2 + amount % 2; | |
4643 | ||
4644 | /* The H8/300 uses three insns to rotate one bit, taking 6 | |
4645 | length. */ | |
27c1afd5 | 4646 | length += amount * 2; |
caf7f21a KH |
4647 | |
4648 | return length; | |
4649 | } | |
edd71f0f | 4650 | \f |
48837e29 | 4651 | /* Fix the operands of a gen_xxx so that it could become a bit |
2c54abce | 4652 | operating insn. */ |
07aae5c2 SC |
4653 | |
4654 | int | |
4093985c | 4655 | fix_bit_operand (rtx *operands, enum rtx_code code) |
07aae5c2 | 4656 | { |
abc95ed3 | 4657 | /* The bit_operand predicate accepts any memory during RTL generation, but |
48837e29 DE |
4658 | only 'U' memory afterwards, so if this is a MEM operand, we must force |
4659 | it to be valid for 'U' by reloading the address. */ | |
07aae5c2 | 4660 | |
4093985c KH |
4661 | if (code == AND |
4662 | ? single_zero_operand (operands[2], QImode) | |
4663 | : single_one_operand (operands[2], QImode)) | |
07aae5c2 | 4664 | { |
2e760b15 KH |
4665 | /* OK to have a memory dest. */ |
4666 | if (GET_CODE (operands[0]) == MEM | |
ceaaaeab | 4667 | && !satisfies_constraint_U (operands[0])) |
48837e29 | 4668 | { |
2e760b15 KH |
4669 | rtx mem = gen_rtx_MEM (GET_MODE (operands[0]), |
4670 | copy_to_mode_reg (Pmode, | |
4671 | XEXP (operands[0], 0))); | |
4672 | MEM_COPY_ATTRIBUTES (mem, operands[0]); | |
4673 | operands[0] = mem; | |
4674 | } | |
48837e29 | 4675 | |
2e760b15 | 4676 | if (GET_CODE (operands[1]) == MEM |
ceaaaeab | 4677 | && !satisfies_constraint_U (operands[1])) |
2e760b15 KH |
4678 | { |
4679 | rtx mem = gen_rtx_MEM (GET_MODE (operands[1]), | |
4680 | copy_to_mode_reg (Pmode, | |
4681 | XEXP (operands[1], 0))); | |
4682 | MEM_COPY_ATTRIBUTES (mem, operands[0]); | |
4683 | operands[1] = mem; | |
48837e29 | 4684 | } |
2e760b15 | 4685 | return 0; |
48837e29 | 4686 | } |
07aae5c2 | 4687 | |
48837e29 | 4688 | /* Dest and src op must be register. */ |
07aae5c2 | 4689 | |
48837e29 DE |
4690 | operands[1] = force_reg (QImode, operands[1]); |
4691 | { | |
4692 | rtx res = gen_reg_rtx (QImode); | |
fd57a6e4 | 4693 | switch (code) |
a3579575 KH |
4694 | { |
4695 | case AND: | |
4696 | emit_insn (gen_andqi3_1 (res, operands[1], operands[2])); | |
4697 | break; | |
4698 | case IOR: | |
4699 | emit_insn (gen_iorqi3_1 (res, operands[1], operands[2])); | |
4700 | break; | |
4701 | case XOR: | |
4702 | emit_insn (gen_xorqi3_1 (res, operands[1], operands[2])); | |
4703 | break; | |
4704 | default: | |
8c440872 | 4705 | gcc_unreachable (); |
a3579575 KH |
4706 | } |
4707 | emit_insn (gen_movqi (operands[0], res)); | |
48837e29 DE |
4708 | } |
4709 | return 1; | |
07aae5c2 | 4710 | } |
f5b65a56 | 4711 | |
f5b65a56 JL |
4712 | /* Return nonzero if FUNC is an interrupt function as specified |
4713 | by the "interrupt" attribute. */ | |
4714 | ||
4715 | static int | |
cb713a8d | 4716 | h8300_interrupt_function_p (tree func) |
f5b65a56 JL |
4717 | { |
4718 | tree a; | |
4719 | ||
4720 | if (TREE_CODE (func) != FUNCTION_DECL) | |
4721 | return 0; | |
4722 | ||
91d231cb | 4723 | a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func)); |
f5b65a56 JL |
4724 | return a != NULL_TREE; |
4725 | } | |
4726 | ||
3cfa3702 KH |
4727 | /* Return nonzero if FUNC is a saveall function as specified by the |
4728 | "saveall" attribute. */ | |
4729 | ||
4730 | static int | |
4731 | h8300_saveall_function_p (tree func) | |
4732 | { | |
4733 | tree a; | |
4734 | ||
4735 | if (TREE_CODE (func) != FUNCTION_DECL) | |
4736 | return 0; | |
4737 | ||
4738 | a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func)); | |
4739 | return a != NULL_TREE; | |
4740 | } | |
4741 | ||
fabe72bb JL |
4742 | /* Return nonzero if FUNC is an OS_Task function as specified |
4743 | by the "OS_Task" attribute. */ | |
4744 | ||
4745 | static int | |
cb713a8d | 4746 | h8300_os_task_function_p (tree func) |
fabe72bb JL |
4747 | { |
4748 | tree a; | |
4749 | ||
4750 | if (TREE_CODE (func) != FUNCTION_DECL) | |
4751 | return 0; | |
4752 | ||
91d231cb | 4753 | a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func)); |
fabe72bb JL |
4754 | return a != NULL_TREE; |
4755 | } | |
4756 | ||
4757 | /* Return nonzero if FUNC is a monitor function as specified | |
4758 | by the "monitor" attribute. */ | |
4759 | ||
4760 | static int | |
cb713a8d | 4761 | h8300_monitor_function_p (tree func) |
fabe72bb JL |
4762 | { |
4763 | tree a; | |
4764 | ||
4765 | if (TREE_CODE (func) != FUNCTION_DECL) | |
4766 | return 0; | |
4767 | ||
91d231cb | 4768 | a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func)); |
fabe72bb JL |
4769 | return a != NULL_TREE; |
4770 | } | |
4771 | ||
f5b65a56 JL |
4772 | /* Return nonzero if FUNC is a function that should be called |
4773 | through the function vector. */ | |
4774 | ||
4775 | int | |
cb713a8d | 4776 | h8300_funcvec_function_p (tree func) |
f5b65a56 JL |
4777 | { |
4778 | tree a; | |
4779 | ||
4780 | if (TREE_CODE (func) != FUNCTION_DECL) | |
4781 | return 0; | |
4782 | ||
91d231cb | 4783 | a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func)); |
f5b65a56 JL |
4784 | return a != NULL_TREE; |
4785 | } | |
4786 | ||
887a8bd9 | 4787 | /* Return nonzero if DECL is a variable that's in the eight bit |
15dc331e JL |
4788 | data area. */ |
4789 | ||
4790 | int | |
cb713a8d | 4791 | h8300_eightbit_data_p (tree decl) |
15dc331e JL |
4792 | { |
4793 | tree a; | |
4794 | ||
4795 | if (TREE_CODE (decl) != VAR_DECL) | |
4796 | return 0; | |
4797 | ||
91d231cb | 4798 | a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl)); |
15dc331e JL |
4799 | return a != NULL_TREE; |
4800 | } | |
4801 | ||
887a8bd9 JL |
4802 | /* Return nonzero if DECL is a variable that's in the tiny |
4803 | data area. */ | |
4804 | ||
4805 | int | |
cb713a8d | 4806 | h8300_tiny_data_p (tree decl) |
887a8bd9 JL |
4807 | { |
4808 | tree a; | |
4809 | ||
4810 | if (TREE_CODE (decl) != VAR_DECL) | |
4811 | return 0; | |
4812 | ||
91d231cb | 4813 | a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl)); |
887a8bd9 JL |
4814 | return a != NULL_TREE; |
4815 | } | |
4816 | ||
3cfa3702 KH |
4817 | /* Generate an 'interrupt_handler' attribute for decls. We convert |
4818 | all the pragmas to corresponding attributes. */ | |
2c1d2fcb DD |
4819 | |
4820 | static void | |
cb713a8d | 4821 | h8300_insert_attributes (tree node, tree *attributes) |
2c1d2fcb | 4822 | { |
3cfa3702 KH |
4823 | if (TREE_CODE (node) == FUNCTION_DECL) |
4824 | { | |
4825 | if (pragma_interrupt) | |
4826 | { | |
4827 | pragma_interrupt = 0; | |
2c1d2fcb | 4828 | |
3cfa3702 KH |
4829 | /* Add an 'interrupt_handler' attribute. */ |
4830 | *attributes = tree_cons (get_identifier ("interrupt_handler"), | |
4831 | NULL, *attributes); | |
4832 | } | |
e392d367 | 4833 | |
3cfa3702 KH |
4834 | if (pragma_saveall) |
4835 | { | |
4836 | pragma_saveall = 0; | |
4837 | ||
4838 | /* Add an 'saveall' attribute. */ | |
4839 | *attributes = tree_cons (get_identifier ("saveall"), | |
4840 | NULL, *attributes); | |
4841 | } | |
4842 | } | |
2c1d2fcb DD |
4843 | } |
4844 | ||
91d231cb | 4845 | /* Supported attributes: |
f5b65a56 | 4846 | |
97c5ec1d | 4847 | interrupt_handler: output a prologue and epilogue suitable for an |
f5b65a56 JL |
4848 | interrupt handler. |
4849 | ||
3cfa3702 KH |
4850 | saveall: output a prologue and epilogue that saves and restores |
4851 | all registers except the stack pointer. | |
4852 | ||
97c5ec1d | 4853 | function_vector: This function should be called through the |
887a8bd9 JL |
4854 | function vector. |
4855 | ||
4856 | eightbit_data: This variable lives in the 8-bit data area and can | |
4857 | be referenced with 8-bit absolute memory addresses. | |
4858 | ||
4859 | tiny_data: This variable lives in the tiny data area and can be | |
4860 | referenced with 16-bit absolute memory references. */ | |
f5b65a56 | 4861 | |
6bc7bc14 | 4862 | static const struct attribute_spec h8300_attribute_table[] = |
f5b65a56 | 4863 | { |
4849deb1 JJ |
4864 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, |
4865 | affects_type_identity, handler, exclude } */ | |
4866 | { "interrupt_handler", 0, 0, true, false, false, false, | |
4867 | h8300_handle_fndecl_attribute, NULL }, | |
4868 | { "saveall", 0, 0, true, false, false, false, | |
4869 | h8300_handle_fndecl_attribute, NULL }, | |
4870 | { "OS_Task", 0, 0, true, false, false, false, | |
4871 | h8300_handle_fndecl_attribute, NULL }, | |
4872 | { "monitor", 0, 0, true, false, false, false, | |
4873 | h8300_handle_fndecl_attribute, NULL }, | |
4874 | { "function_vector", 0, 0, true, false, false, false, | |
4875 | h8300_handle_fndecl_attribute, NULL }, | |
4876 | { "eightbit_data", 0, 0, true, false, false, false, | |
4877 | h8300_handle_eightbit_data_attribute, NULL }, | |
4878 | { "tiny_data", 0, 0, true, false, false, false, | |
4879 | h8300_handle_tiny_data_attribute, NULL }, | |
4880 | { NULL, 0, 0, false, false, false, false, NULL, NULL } | |
91d231cb | 4881 | }; |
f5b65a56 | 4882 | |
15dc331e | 4883 | |
91d231cb JM |
4884 | /* Handle an attribute requiring a FUNCTION_DECL; arguments as in |
4885 | struct attribute_spec.handler. */ | |
4886 | static tree | |
cb713a8d KH |
4887 | h8300_handle_fndecl_attribute (tree *node, tree name, |
4888 | tree args ATTRIBUTE_UNUSED, | |
4889 | int flags ATTRIBUTE_UNUSED, | |
4890 | bool *no_add_attrs) | |
91d231cb JM |
4891 | { |
4892 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
4893 | { | |
29d08eba JM |
4894 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
4895 | name); | |
91d231cb JM |
4896 | *no_add_attrs = true; |
4897 | } | |
4898 | ||
4899 | return NULL_TREE; | |
4900 | } | |
4901 | ||
4902 | /* Handle an "eightbit_data" attribute; arguments as in | |
4903 | struct attribute_spec.handler. */ | |
4904 | static tree | |
cb713a8d KH |
4905 | h8300_handle_eightbit_data_attribute (tree *node, tree name, |
4906 | tree args ATTRIBUTE_UNUSED, | |
4907 | int flags ATTRIBUTE_UNUSED, | |
4908 | bool *no_add_attrs) | |
91d231cb JM |
4909 | { |
4910 | tree decl = *node; | |
4911 | ||
4912 | if (TREE_STATIC (decl) || DECL_EXTERNAL (decl)) | |
15dc331e | 4913 | { |
f961457f | 4914 | set_decl_section_name (decl, ".eight"); |
91d231cb JM |
4915 | } |
4916 | else | |
4917 | { | |
29d08eba JM |
4918 | warning (OPT_Wattributes, "%qE attribute ignored", |
4919 | name); | |
91d231cb | 4920 | *no_add_attrs = true; |
887a8bd9 JL |
4921 | } |
4922 | ||
91d231cb JM |
4923 | return NULL_TREE; |
4924 | } | |
4925 | ||
4926 | /* Handle an "tiny_data" attribute; arguments as in | |
4927 | struct attribute_spec.handler. */ | |
4928 | static tree | |
cb713a8d KH |
4929 | h8300_handle_tiny_data_attribute (tree *node, tree name, |
4930 | tree args ATTRIBUTE_UNUSED, | |
4931 | int flags ATTRIBUTE_UNUSED, | |
4932 | bool *no_add_attrs) | |
91d231cb JM |
4933 | { |
4934 | tree decl = *node; | |
4935 | ||
4936 | if (TREE_STATIC (decl) || DECL_EXTERNAL (decl)) | |
887a8bd9 | 4937 | { |
f961457f | 4938 | set_decl_section_name (decl, ".tiny"); |
91d231cb JM |
4939 | } |
4940 | else | |
4941 | { | |
29d08eba JM |
4942 | warning (OPT_Wattributes, "%qE attribute ignored", |
4943 | name); | |
91d231cb | 4944 | *no_add_attrs = true; |
15dc331e | 4945 | } |
07e4d94e | 4946 | |
91d231cb | 4947 | return NULL_TREE; |
f5b65a56 JL |
4948 | } |
4949 | ||
dc66a1c4 | 4950 | /* Mark function vectors, and various small data objects. */ |
fb49053f RH |
4951 | |
4952 | static void | |
cb713a8d | 4953 | h8300_encode_section_info (tree decl, rtx rtl, int first) |
fb49053f | 4954 | { |
dc66a1c4 RH |
4955 | int extra_flags = 0; |
4956 | ||
c6a2438a | 4957 | default_encode_section_info (decl, rtl, first); |
dc66a1c4 | 4958 | |
fb49053f RH |
4959 | if (TREE_CODE (decl) == FUNCTION_DECL |
4960 | && h8300_funcvec_function_p (decl)) | |
dc66a1c4 | 4961 | extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION; |
fb49053f RH |
4962 | else if (TREE_CODE (decl) == VAR_DECL |
4963 | && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))) | |
4964 | { | |
4965 | if (h8300_eightbit_data_p (decl)) | |
dc66a1c4 | 4966 | extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA; |
fb49053f | 4967 | else if (first && h8300_tiny_data_p (decl)) |
dc66a1c4 | 4968 | extra_flags = SYMBOL_FLAG_TINY_DATA; |
fb49053f | 4969 | } |
772c5265 | 4970 | |
dc66a1c4 | 4971 | if (extra_flags) |
c6a2438a | 4972 | SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags; |
772c5265 RH |
4973 | } |
4974 | ||
e9eba255 KH |
4975 | /* Output a single-bit extraction. */ |
4976 | ||
441d04c6 | 4977 | const char * |
cb713a8d | 4978 | output_simode_bld (int bild, rtx operands[]) |
bd93f126 | 4979 | { |
27c1afd5 JL |
4980 | /* Determine if we can clear the destination first. */ |
4981 | int clear_first = (REG_P (operands[0]) && REG_P (operands[1]) | |
4982 | && REGNO (operands[0]) != REGNO (operands[1])); | |
6be580c7 | 4983 | |
27c1afd5 JL |
4984 | if (clear_first) |
4985 | output_asm_insn ("sub.l\t%S0,%S0", operands); | |
bd93f126 | 4986 | |
27c1afd5 JL |
4987 | /* Output the bit load or bit inverse load. */ |
4988 | if (bild) | |
4989 | output_asm_insn ("bild\t%Z2,%Y1", operands); | |
bd93f126 | 4990 | else |
27c1afd5 | 4991 | output_asm_insn ("bld\t%Z2,%Y1", operands); |
0eb933a0 | 4992 | |
27c1afd5 JL |
4993 | if (!clear_first) |
4994 | output_asm_insn ("xor.l\t%S0,%S0", operands); | |
0eb933a0 | 4995 | |
27c1afd5 JL |
4996 | /* Perform the bit store. */ |
4997 | output_asm_insn ("rotxl.l\t%S0", operands); | |
bd93f126 JL |
4998 | |
4999 | /* All done. */ | |
5000 | return ""; | |
5001 | } | |
e6219736 | 5002 | |
beed8fc0 AO |
5003 | /* Delayed-branch scheduling is more effective if we have some idea |
5004 | how long each instruction will be. Use a shorten_branches pass | |
5005 | to get an initial estimate. */ | |
5006 | ||
5007 | static void | |
5008 | h8300_reorg (void) | |
5009 | { | |
5010 | if (flag_delayed_branch) | |
5011 | shorten_branches (get_insns ()); | |
5012 | } | |
5013 | ||
7c143ed2 KH |
5014 | /* Nonzero if X is a constant address suitable as an 8-bit absolute, |
5015 | which is a special case of the 'R' operand. */ | |
5016 | ||
803d56f5 | 5017 | int |
cb713a8d | 5018 | h8300_eightbit_constant_address_p (rtx x) |
803d56f5 | 5019 | { |
ff482c8d | 5020 | /* The ranges of the 8-bit area. */ |
d2d199a3 KH |
5021 | const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode); |
5022 | const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode); | |
803d56f5 KH |
5023 | const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode); |
5024 | const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode); | |
5025 | const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode); | |
5026 | const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode); | |
5027 | ||
5028 | unsigned HOST_WIDE_INT addr; | |
5029 | ||
9675a91e | 5030 | /* We accept symbols declared with eightbit_data. */ |
dc66a1c4 RH |
5031 | if (GET_CODE (x) == SYMBOL_REF) |
5032 | return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0; | |
9675a91e | 5033 | |
9f9ab303 JL |
5034 | if (GET_CODE (x) == CONST |
5035 | && GET_CODE (XEXP (x, 0)) == PLUS | |
5036 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
5037 | && (SYMBOL_REF_FLAGS (XEXP (XEXP (x, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0) | |
5038 | return 1; | |
5039 | ||
803d56f5 KH |
5040 | if (GET_CODE (x) != CONST_INT) |
5041 | return 0; | |
5042 | ||
5043 | addr = INTVAL (x); | |
5044 | ||
5045 | return (0 | |
27c1afd5 | 5046 | || (TARGET_NORMAL_MODE && IN_RANGE (addr, n1, n2)) |
803d56f5 KH |
5047 | || (TARGET_H8300H && IN_RANGE (addr, h1, h2)) |
5048 | || (TARGET_H8300S && IN_RANGE (addr, s1, s2))); | |
5049 | } | |
5050 | ||
7c143ed2 KH |
5051 | /* Nonzero if X is a constant address suitable as an 16-bit absolute |
5052 | on H8/300H and H8S. */ | |
5053 | ||
803d56f5 | 5054 | int |
cb713a8d | 5055 | h8300_tiny_constant_address_p (rtx x) |
803d56f5 | 5056 | { |
3f7211f1 | 5057 | /* The ranges of the 16-bit area. */ |
803d56f5 KH |
5058 | const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode); |
5059 | const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode); | |
5060 | const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode); | |
5061 | const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode); | |
5062 | const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode); | |
5063 | const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode); | |
5064 | const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode); | |
5065 | const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode); | |
5066 | ||
5067 | unsigned HOST_WIDE_INT addr; | |
5068 | ||
d6456562 KH |
5069 | switch (GET_CODE (x)) |
5070 | { | |
5071 | case SYMBOL_REF: | |
a4bb41cc KH |
5072 | /* In the normal mode, any symbol fits in the 16-bit absolute |
5073 | address range. We also accept symbols declared with | |
5074 | tiny_data. */ | |
5075 | return (TARGET_NORMAL_MODE | |
5076 | || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0); | |
56b8e164 | 5077 | |
d6456562 KH |
5078 | case CONST_INT: |
5079 | addr = INTVAL (x); | |
5080 | return (TARGET_NORMAL_MODE | |
5081 | || (TARGET_H8300H | |
5082 | && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4))) | |
5083 | || (TARGET_H8300S | |
5084 | && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4)))); | |
803d56f5 | 5085 | |
a4bb41cc KH |
5086 | case CONST: |
5087 | return TARGET_NORMAL_MODE; | |
5088 | ||
d6456562 KH |
5089 | default: |
5090 | return 0; | |
5091 | } | |
803d56f5 | 5092 | |
803d56f5 | 5093 | } |
9b98dc74 | 5094 | |
e9eba255 KH |
5095 | /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory |
5096 | locations that can be accessed as a 16-bit word. */ | |
5097 | ||
9b98dc74 | 5098 | int |
cb713a8d | 5099 | byte_accesses_mergeable_p (rtx addr1, rtx addr2) |
9b98dc74 KH |
5100 | { |
5101 | HOST_WIDE_INT offset1, offset2; | |
5102 | rtx reg1, reg2; | |
5103 | ||
5104 | if (REG_P (addr1)) | |
5105 | { | |
5106 | reg1 = addr1; | |
5107 | offset1 = 0; | |
5108 | } | |
5109 | else if (GET_CODE (addr1) == PLUS | |
5110 | && REG_P (XEXP (addr1, 0)) | |
5111 | && GET_CODE (XEXP (addr1, 1)) == CONST_INT) | |
5112 | { | |
5113 | reg1 = XEXP (addr1, 0); | |
5114 | offset1 = INTVAL (XEXP (addr1, 1)); | |
5115 | } | |
5116 | else | |
5117 | return 0; | |
5118 | ||
5119 | if (REG_P (addr2)) | |
5120 | { | |
5121 | reg2 = addr2; | |
5122 | offset2 = 0; | |
5123 | } | |
5124 | else if (GET_CODE (addr2) == PLUS | |
5125 | && REG_P (XEXP (addr2, 0)) | |
5126 | && GET_CODE (XEXP (addr2, 1)) == CONST_INT) | |
5127 | { | |
5128 | reg2 = XEXP (addr2, 0); | |
5129 | offset2 = INTVAL (XEXP (addr2, 1)); | |
5130 | } | |
5131 | else | |
5132 | return 0; | |
5133 | ||
5134 | if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx) | |
5135 | || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx)) | |
5136 | && offset1 % 2 == 0 | |
5137 | && offset1 + 1 == offset2) | |
5138 | return 1; | |
5139 | ||
5140 | return 0; | |
5141 | } | |
02529902 KH |
5142 | |
5143 | /* Return nonzero if we have the same comparison insn as I3 two insns | |
19cff4db | 5144 | before I3. I3 is assumed to be a comparison insn. */ |
02529902 KH |
5145 | |
5146 | int | |
82082f65 | 5147 | same_cmp_preceding_p (rtx_insn *i3) |
02529902 | 5148 | { |
68a1a6c0 | 5149 | rtx_insn *i1, *i2; |
02529902 KH |
5150 | |
5151 | /* Make sure we have a sequence of three insns. */ | |
5152 | i2 = prev_nonnote_insn (i3); | |
68a1a6c0 | 5153 | if (i2 == NULL) |
02529902 KH |
5154 | return 0; |
5155 | i1 = prev_nonnote_insn (i2); | |
68a1a6c0 | 5156 | if (i1 == NULL) |
02529902 KH |
5157 | return 0; |
5158 | ||
5159 | return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3)) | |
5160 | && any_condjump_p (i2) && onlyjump_p (i2)); | |
5161 | } | |
c87ec0ba | 5162 | |
c06d5c85 KH |
5163 | /* Return nonzero if we have the same comparison insn as I1 two insns |
5164 | after I1. I1 is assumed to be a comparison insn. */ | |
5165 | ||
5166 | int | |
82082f65 | 5167 | same_cmp_following_p (rtx_insn *i1) |
c06d5c85 | 5168 | { |
68a1a6c0 | 5169 | rtx_insn *i2, *i3; |
c06d5c85 KH |
5170 | |
5171 | /* Make sure we have a sequence of three insns. */ | |
5172 | i2 = next_nonnote_insn (i1); | |
68a1a6c0 | 5173 | if (i2 == NULL) |
c06d5c85 KH |
5174 | return 0; |
5175 | i3 = next_nonnote_insn (i2); | |
68a1a6c0 | 5176 | if (i3 == NULL) |
c06d5c85 KH |
5177 | return 0; |
5178 | ||
5179 | return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3)) | |
5180 | && any_condjump_p (i2) && onlyjump_p (i2)); | |
5181 | } | |
5182 | ||
a466bea3 | 5183 | /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes |
1ae58c30 | 5184 | (or pops) N registers. OPERANDS are assumed to be an array of |
a466bea3 KH |
5185 | registers. */ |
5186 | ||
5187 | int | |
5188 | h8300_regs_ok_for_stm (int n, rtx operands[]) | |
5189 | { | |
5190 | switch (n) | |
5191 | { | |
5192 | case 2: | |
5193 | return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1) | |
5194 | || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3) | |
5195 | || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5)); | |
5196 | case 3: | |
5197 | return ((REGNO (operands[0]) == 0 | |
5198 | && REGNO (operands[1]) == 1 | |
5199 | && REGNO (operands[2]) == 2) | |
5200 | || (REGNO (operands[0]) == 4 | |
5201 | && REGNO (operands[1]) == 5 | |
5202 | && REGNO (operands[2]) == 6)); | |
5203 | ||
5204 | case 4: | |
5205 | return (REGNO (operands[0]) == 0 | |
5206 | && REGNO (operands[1]) == 1 | |
5207 | && REGNO (operands[2]) == 2 | |
5208 | && REGNO (operands[3]) == 3); | |
8c440872 NS |
5209 | default: |
5210 | gcc_unreachable (); | |
a466bea3 | 5211 | } |
a466bea3 KH |
5212 | } |
5213 | ||
c87ec0ba NY |
5214 | /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */ |
5215 | ||
5216 | int | |
5217 | h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, | |
5218 | unsigned int new_reg) | |
5219 | { | |
5220 | /* Interrupt functions can only use registers that have already been | |
5221 | saved by the prologue, even if they would normally be | |
5222 | call-clobbered. */ | |
5223 | ||
5224 | if (h8300_current_function_interrupt_function_p () | |
6fb5fa3c | 5225 | && !df_regs_ever_live_p (new_reg)) |
c87ec0ba NY |
5226 | return 0; |
5227 | ||
80e58519 | 5228 | return 1; |
c87ec0ba | 5229 | } |
d0022200 | 5230 | |
2e762884 DD |
5231 | /* Returns true if register REGNO is safe to be allocated as a scratch |
5232 | register in the current function. */ | |
5233 | ||
5234 | static bool | |
5235 | h8300_hard_regno_scratch_ok (unsigned int regno) | |
5236 | { | |
5237 | if (h8300_current_function_interrupt_function_p () | |
5238 | && ! WORD_REG_USED (regno)) | |
5239 | return false; | |
5240 | ||
5241 | return true; | |
5242 | } | |
5243 | ||
5244 | ||
d0022200 KH |
5245 | /* Return nonzero if X is a REG or SUBREG suitable as a base register. */ |
5246 | ||
5247 | static int | |
5248 | h8300_rtx_ok_for_base_p (rtx x, int strict) | |
5249 | { | |
5250 | /* Strip off SUBREG if any. */ | |
5251 | if (GET_CODE (x) == SUBREG) | |
5252 | x = SUBREG_REG (x); | |
5253 | ||
5254 | return (REG_P (x) | |
5255 | && (strict | |
5256 | ? REG_OK_FOR_BASE_STRICT_P (x) | |
5257 | : REG_OK_FOR_BASE_NONSTRICT_P (x))); | |
5258 | } | |
5259 | ||
5260 | /* Return nozero if X is a legitimate address. On the H8/300, a | |
5261 | legitimate address has the form REG, REG+CONSTANT_ADDRESS or | |
5262 | CONSTANT_ADDRESS. */ | |
5263 | ||
c6c3dba9 | 5264 | static bool |
ef4bddc2 | 5265 | h8300_legitimate_address_p (machine_mode mode, rtx x, bool strict) |
d0022200 KH |
5266 | { |
5267 | /* The register indirect addresses like @er0 is always valid. */ | |
5268 | if (h8300_rtx_ok_for_base_p (x, strict)) | |
5269 | return 1; | |
5270 | ||
5271 | if (CONSTANT_ADDRESS_P (x)) | |
5272 | return 1; | |
5273 | ||
beed8fc0 AO |
5274 | if (TARGET_H8300SX |
5275 | && ( GET_CODE (x) == PRE_INC | |
5276 | || GET_CODE (x) == PRE_DEC | |
5277 | || GET_CODE (x) == POST_INC | |
5278 | || GET_CODE (x) == POST_DEC) | |
5279 | && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict)) | |
5280 | return 1; | |
5281 | ||
d0022200 KH |
5282 | if (GET_CODE (x) == PLUS |
5283 | && CONSTANT_ADDRESS_P (XEXP (x, 1)) | |
beed8fc0 AO |
5284 | && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0), |
5285 | mode, 0), strict)) | |
d0022200 KH |
5286 | return 1; |
5287 | ||
5288 | return 0; | |
5289 | } | |
07ee3b58 | 5290 | |
f939c3e6 | 5291 | /* Implement TARGET_HARD_REGNO_MODE_OK. */ |
07ee3b58 | 5292 | |
f939c3e6 RS |
5293 | static bool |
5294 | h8300_hard_regno_mode_ok (unsigned int regno, machine_mode mode) | |
07ee3b58 | 5295 | { |
27c1afd5 JL |
5296 | /* MAC register can only be of SImode. Otherwise, anything |
5297 | goes. */ | |
5298 | return regno == MAC_REG ? mode == SImode : 1; | |
07ee3b58 | 5299 | } |
f9b4f8c1 | 5300 | |
99e1629f RS |
5301 | /* Implement TARGET_MODES_TIEABLE_P. */ |
5302 | ||
5303 | static bool | |
5304 | h8300_modes_tieable_p (machine_mode mode1, machine_mode mode2) | |
5305 | { | |
5306 | return (mode1 == mode2 | |
5307 | || ((mode1 == QImode | |
5308 | || mode1 == HImode | |
27c1afd5 | 5309 | || mode1 == SImode) |
99e1629f RS |
5310 | && (mode2 == QImode |
5311 | || mode2 == HImode | |
27c1afd5 | 5312 | || mode2 == SImode))); |
99e1629f RS |
5313 | } |
5314 | ||
f9b4f8c1 RH |
5315 | /* Helper function for the move patterns. Make sure a move is legitimate. */ |
5316 | ||
5317 | bool | |
5318 | h8300_move_ok (rtx dest, rtx src) | |
5319 | { | |
5320 | rtx addr, other; | |
5321 | ||
5322 | /* Validate that at least one operand is a register. */ | |
5323 | if (MEM_P (dest)) | |
5324 | { | |
5325 | if (MEM_P (src) || CONSTANT_P (src)) | |
5326 | return false; | |
5327 | addr = XEXP (dest, 0); | |
5328 | other = src; | |
5329 | } | |
5330 | else if (MEM_P (src)) | |
5331 | { | |
5332 | addr = XEXP (src, 0); | |
5333 | other = dest; | |
5334 | } | |
5335 | else | |
5336 | return true; | |
5337 | ||
5338 | /* Validate that auto-inc doesn't affect OTHER. */ | |
5339 | if (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC) | |
5340 | return true; | |
5341 | addr = XEXP (addr, 0); | |
5342 | ||
5343 | if (addr == stack_pointer_rtx) | |
5344 | return register_no_sp_elim_operand (other, VOIDmode); | |
5345 | else | |
5346 | return !reg_overlap_mentioned_p(other, addr); | |
5347 | } | |
6e014ef3 | 5348 | \f |
c15c90bb ZW |
5349 | /* Perform target dependent optabs initialization. */ |
5350 | static void | |
5351 | h8300_init_libfuncs (void) | |
5352 | { | |
5353 | set_optab_libfunc (smul_optab, HImode, "__mulhi3"); | |
5354 | set_optab_libfunc (sdiv_optab, HImode, "__divhi3"); | |
5355 | set_optab_libfunc (udiv_optab, HImode, "__udivhi3"); | |
5356 | set_optab_libfunc (smod_optab, HImode, "__modhi3"); | |
5357 | set_optab_libfunc (umod_optab, HImode, "__umodhi3"); | |
5358 | } | |
5359 | \f | |
9eaa7740 AS |
5360 | /* Worker function for TARGET_FUNCTION_VALUE. |
5361 | ||
5362 | On the H8 the return value is in R0/R1. */ | |
5363 | ||
5364 | static rtx | |
5365 | h8300_function_value (const_tree ret_type, | |
5366 | const_tree fn_decl_or_type ATTRIBUTE_UNUSED, | |
5367 | bool outgoing ATTRIBUTE_UNUSED) | |
5368 | { | |
5369 | return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG); | |
5370 | } | |
5371 | ||
5372 | /* Worker function for TARGET_LIBCALL_VALUE. | |
5373 | ||
5374 | On the H8 the return value is in R0/R1. */ | |
5375 | ||
5376 | static rtx | |
ef4bddc2 | 5377 | h8300_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) |
9eaa7740 AS |
5378 | { |
5379 | return gen_rtx_REG (mode, R0_REG); | |
5380 | } | |
5381 | ||
5382 | /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P. | |
5383 | ||
5384 | On the H8, R0 is the only register thus used. */ | |
5385 | ||
5386 | static bool | |
5387 | h8300_function_value_regno_p (const unsigned int regno) | |
5388 | { | |
5389 | return (regno == R0_REG); | |
5390 | } | |
5391 | ||
e9eba255 KH |
5392 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
5393 | ||
34bf1fe3 | 5394 | static bool |
586de218 | 5395 | h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
34bf1fe3 KH |
5396 | { |
5397 | return (TYPE_MODE (type) == BLKmode | |
27c1afd5 | 5398 | || GET_MODE_SIZE (TYPE_MODE (type)) > 8); |
34bf1fe3 KH |
5399 | } |
5400 | \f | |
9f6ef043 RH |
5401 | /* We emit the entire trampoline here. Depending on the pointer size, |
5402 | we use a different trampoline. | |
5403 | ||
5404 | Pmode == HImode | |
5405 | vvvv context | |
5406 | 1 0000 7903xxxx mov.w #0x1234,r3 | |
5407 | 2 0004 5A00xxxx jmp @0x1234 | |
5408 | ^^^^ function | |
5409 | ||
5410 | Pmode == SImode | |
5411 | vvvvvvvv context | |
5412 | 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3 | |
5413 | 3 0006 5Axxxxxx jmp @0x123456 | |
5414 | ^^^^^^ function | |
5415 | */ | |
5416 | ||
5417 | static void | |
5418 | h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt) | |
5419 | { | |
5420 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
5421 | rtx mem; | |
5422 | ||
5423 | if (Pmode == HImode) | |
5424 | { | |
5425 | mem = adjust_address (m_tramp, HImode, 0); | |
5426 | emit_move_insn (mem, GEN_INT (0x7903)); | |
5427 | mem = adjust_address (m_tramp, Pmode, 2); | |
5428 | emit_move_insn (mem, cxt); | |
5429 | mem = adjust_address (m_tramp, HImode, 4); | |
5430 | emit_move_insn (mem, GEN_INT (0x5a00)); | |
5431 | mem = adjust_address (m_tramp, Pmode, 6); | |
5432 | emit_move_insn (mem, fnaddr); | |
5433 | } | |
5434 | else | |
5435 | { | |
5436 | rtx tem; | |
5437 | ||
5438 | mem = adjust_address (m_tramp, HImode, 0); | |
5439 | emit_move_insn (mem, GEN_INT (0x7a03)); | |
5440 | mem = adjust_address (m_tramp, Pmode, 2); | |
5441 | emit_move_insn (mem, cxt); | |
5442 | ||
5443 | tem = copy_to_reg (fnaddr); | |
5444 | emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff))); | |
5445 | emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000))); | |
5446 | mem = adjust_address (m_tramp, SImode, 6); | |
5447 | emit_move_insn (mem, tem); | |
5448 | } | |
5449 | } | |
7b4df2bf RS |
5450 | |
5451 | /* Implement PUSH_ROUNDING. | |
5452 | ||
5453 | On the H8/300, @-sp really pushes a byte if you ask it to - but that's | |
5454 | dangerous, so we claim that it always pushes a word, then we catch | |
5455 | the mov.b rx,@-sp and turn it into a mov.w rx,@-sp on output. | |
5456 | ||
5457 | On the H8/300H, we simplify TARGET_QUICKCALL by setting this to 4 | |
5458 | and doing a similar thing. */ | |
5459 | ||
5460 | poly_int64 | |
5461 | h8300_push_rounding (poly_int64 bytes) | |
5462 | { | |
5463 | return ((bytes + PARM_BOUNDARY / 8 - 1) & (-PARM_BOUNDARY / 8)); | |
5464 | } | |
9f6ef043 | 5465 | \f |
6e014ef3 KH |
5466 | /* Initialize the GCC target structure. */ |
5467 | #undef TARGET_ATTRIBUTE_TABLE | |
5468 | #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table | |
5469 | ||
5470 | #undef TARGET_ASM_ALIGNED_HI_OP | |
5471 | #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
5472 | ||
1bc7c5b6 ZW |
5473 | #undef TARGET_ASM_FILE_START |
5474 | #define TARGET_ASM_FILE_START h8300_file_start | |
5475 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
5476 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
5477 | ||
6e014ef3 KH |
5478 | #undef TARGET_ASM_FILE_END |
5479 | #define TARGET_ASM_FILE_END h8300_file_end | |
5480 | ||
88cb339e N |
5481 | #undef TARGET_PRINT_OPERAND |
5482 | #define TARGET_PRINT_OPERAND h8300_print_operand | |
5483 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
5484 | #define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address | |
5485 | #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P | |
5486 | #define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p | |
5487 | ||
6e014ef3 KH |
5488 | #undef TARGET_ENCODE_SECTION_INFO |
5489 | #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info | |
5490 | ||
5491 | #undef TARGET_INSERT_ATTRIBUTES | |
5492 | #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes | |
5493 | ||
88cb339e N |
5494 | #undef TARGET_REGISTER_MOVE_COST |
5495 | #define TARGET_REGISTER_MOVE_COST h8300_register_move_cost | |
5496 | ||
6e014ef3 KH |
5497 | #undef TARGET_RTX_COSTS |
5498 | #define TARGET_RTX_COSTS h8300_rtx_costs | |
5499 | ||
c15c90bb ZW |
5500 | #undef TARGET_INIT_LIBFUNCS |
5501 | #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs | |
5502 | ||
9eaa7740 AS |
5503 | #undef TARGET_FUNCTION_VALUE |
5504 | #define TARGET_FUNCTION_VALUE h8300_function_value | |
5505 | ||
5506 | #undef TARGET_LIBCALL_VALUE | |
5507 | #define TARGET_LIBCALL_VALUE h8300_libcall_value | |
5508 | ||
5509 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
5510 | #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p | |
5511 | ||
34bf1fe3 KH |
5512 | #undef TARGET_RETURN_IN_MEMORY |
5513 | #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory | |
5514 | ||
56f9413b NF |
5515 | #undef TARGET_FUNCTION_ARG |
5516 | #define TARGET_FUNCTION_ARG h8300_function_arg | |
5517 | ||
5518 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
5519 | #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance | |
5520 | ||
beed8fc0 AO |
5521 | #undef TARGET_MACHINE_DEPENDENT_REORG |
5522 | #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg | |
5523 | ||
2e762884 DD |
5524 | #undef TARGET_HARD_REGNO_SCRATCH_OK |
5525 | #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok | |
5526 | ||
f939c3e6 RS |
5527 | #undef TARGET_HARD_REGNO_MODE_OK |
5528 | #define TARGET_HARD_REGNO_MODE_OK h8300_hard_regno_mode_ok | |
5529 | ||
99e1629f RS |
5530 | #undef TARGET_MODES_TIEABLE_P |
5531 | #define TARGET_MODES_TIEABLE_P h8300_modes_tieable_p | |
5532 | ||
d81db636 SB |
5533 | #undef TARGET_LRA_P |
5534 | #define TARGET_LRA_P hook_bool_void_false | |
5535 | ||
c6c3dba9 PB |
5536 | #undef TARGET_LEGITIMATE_ADDRESS_P |
5537 | #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p | |
5538 | ||
7b5cbb57 AS |
5539 | #undef TARGET_CAN_ELIMINATE |
5540 | #define TARGET_CAN_ELIMINATE h8300_can_eliminate | |
5541 | ||
5efd84c5 NF |
5542 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
5543 | #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage | |
5544 | ||
9f6ef043 RH |
5545 | #undef TARGET_TRAMPOLINE_INIT |
5546 | #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init | |
5547 | ||
c5387660 JM |
5548 | #undef TARGET_OPTION_OVERRIDE |
5549 | #define TARGET_OPTION_OVERRIDE h8300_option_override | |
5550 | ||
f52d97da AS |
5551 | #undef TARGET_MODE_DEPENDENT_ADDRESS_P |
5552 | #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p | |
5553 | ||
efbf3c34 JL |
5554 | #undef TARGET_HAVE_SPECULATION_SAFE_VALUE |
5555 | #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed | |
5556 | ||
f16897cb AL |
5557 | #undef TARGET_FLAGS_REGNUM |
5558 | #define TARGET_FLAGS_REGNUM 12 | |
5559 | ||
6e014ef3 | 5560 | struct gcc_target targetm = TARGET_INITIALIZER; |