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2014-10-16 Andrew MacLeod <amacleod@redhat.com>
[thirdparty/gcc.git] / gcc / config / h8300 / h8300.c
CommitLineData
716085c2 1/* Subroutines for insn-output.c for Renesas H8/300.
3aea1f79 2 Copyright (C) 1992-2014 Free Software Foundation, Inc.
b839e0b4 3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
e1629549 5
dbbae424 6This file is part of GCC.
e1629549 7
dbbae424 8GCC is free software; you can redistribute it and/or modify
e1629549 9it under the terms of the GNU General Public License as published by
038d1e19 10the Free Software Foundation; either version 3, or (at your option)
e1629549 11any later version.
12
dbbae424 13GCC is distributed in the hope that it will be useful,
e1629549 14but WITHOUT ANY WARRANTY; without even the implied warranty of
15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
038d1e19 19along with GCC; see the file COPYING3. If not see
20<http://www.gnu.org/licenses/>. */
e1629549 21
e1629549 22#include "config.h"
7014838c 23#include "system.h"
805e22b2 24#include "coretypes.h"
25#include "tm.h"
e1629549 26#include "rtl.h"
4faf81b8 27#include "tree.h"
9ed99284 28#include "stor-layout.h"
29#include "varasm.h"
30#include "calls.h"
31#include "stringpool.h"
e1629549 32#include "regs.h"
33#include "hard-reg-set.h"
e1629549 34#include "insn-config.h"
35#include "conditions.h"
e1629549 36#include "output.h"
37#include "insn-attr.h"
38#include "flags.h"
39#include "recog.h"
40#include "expr.h"
a3020f2f 41#include "hashtab.h"
42#include "hash-set.h"
43#include "vec.h"
44#include "machmode.h"
45#include "input.h"
4faf81b8 46#include "function.h"
f2f543a3 47#include "optabs.h"
0b205f4c 48#include "diagnostic-core.h"
7bedc3a0 49#include "c-family/c-pragma.h" /* ??? */
9305fe33 50#include "tm_p.h"
424f5954 51#include "tm-constrs.h"
f8870f17 52#include "ggc.h"
a767736d 53#include "target.h"
54#include "target-def.h"
539b539f 55#include "df.h"
f7715905 56#include "builtins.h"
e1629549 57
727c62dd 58/* Classifies a h8300_src_operand or h8300_dst_operand.
59
60 H8OP_IMMEDIATE
61 A constant operand of some sort.
62
63 H8OP_REGISTER
64 An ordinary register.
65
66 H8OP_MEM_ABSOLUTE
67 A memory reference with a constant address.
68
69 H8OP_MEM_BASE
70 A memory reference with a register as its address.
71
72 H8OP_MEM_COMPLEX
73 Some other kind of memory reference. */
74enum h8300_operand_class
75{
76 H8OP_IMMEDIATE,
77 H8OP_REGISTER,
78 H8OP_MEM_ABSOLUTE,
79 H8OP_MEM_BASE,
80 H8OP_MEM_COMPLEX,
81 NUM_H8OPS
82};
83
727c62dd 84/* For a general two-operand instruction, element [X][Y] gives
85 the length of the opcode fields when the first operand has class
86 (X + 1) and the second has class Y. */
87typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
88
e1629549 89/* Forward declarations. */
230002f2 90static const char *byte_reg (rtx, int);
91static int h8300_interrupt_function_p (tree);
5344805f 92static int h8300_saveall_function_p (tree);
230002f2 93static int h8300_monitor_function_p (tree);
94static int h8300_os_task_function_p (tree);
5da0dad2 95static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool);
959e2f12 96static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
230002f2 97static unsigned int compute_saved_regs (void);
230002f2 98static const char *cond_string (enum rtx_code);
99static unsigned int h8300_asm_insn_count (const char *);
230002f2 100static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
101static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
102static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
87ad9aff 103static void h8300_print_operand_address (FILE *, rtx);
104static void h8300_print_operand (FILE *, rtx, int);
105static bool h8300_print_operand_punct_valid_p (unsigned char code);
6e4758ce 106#ifndef OBJECT_FORMAT_ELF
537cd941 107static void h8300_asm_named_section (const char *, unsigned int, tree);
6e4758ce 108#endif
87ad9aff 109static int h8300_register_move_cost (enum machine_mode, reg_class_t, reg_class_t);
230002f2 110static int h8300_and_costs (rtx);
111static int h8300_shift_costs (rtx);
5a23ee68 112static void h8300_push_pop (int, int, bool, bool);
727c62dd 113static int h8300_stack_offset_p (rtx, int);
114static int h8300_ldm_stm_regno (rtx, int, int, int);
727c62dd 115static void h8300_reorg (void);
116static unsigned int h8300_constant_length (rtx);
117static unsigned int h8300_displacement_length (rtx, int);
118static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *);
119static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *);
120static unsigned int h8300_unary_length (rtx);
121static unsigned int h8300_short_immediate_length (rtx);
122static unsigned int h8300_bitfield_length (rtx, rtx);
1a1ed145 123static unsigned int h8300_binary_length (rtx_insn *, const h8300_length_table *);
727c62dd 124static bool h8300_short_move_mem_p (rtx, enum rtx_code);
125static unsigned int h8300_move_length (rtx *, const h8300_length_table *);
cf695b54 126static bool h8300_hard_regno_scratch_ok (unsigned int);
958f5301 127static rtx h8300_get_index (rtx, enum machine_mode mode, int *);
b11bfc61 128
b839e0b4 129/* CPU_TYPE, says what cpu we're compiling for. */
130int cpu_type;
131
41ed3bcd 132/* True if a #pragma interrupt has been seen for the current function. */
133static int pragma_interrupt;
e1629549 134
135/* True if a #pragma saveall has been seen for the current function. */
8ba450ad 136static int pragma_saveall;
e1629549 137
9305fe33 138static const char *const names_big[] =
eb2aa24e 139{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
b839e0b4 140
9305fe33 141static const char *const names_extended[] =
eb2aa24e 142{ "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
b839e0b4 143
9305fe33 144static const char *const names_upper_extended[] =
eb2aa24e 145{ "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
b839e0b4 146
147/* Points to one of the above. */
148/* ??? The above could be put in an array indexed by CPU_TYPE. */
9305fe33 149const char * const *h8_reg_names;
b839e0b4 150
151/* Various operations needed by the following, indexed by CPU_TYPE. */
b839e0b4 152
9305fe33 153const char *h8_push_op, *h8_pop_op, *h8_mov_op;
d37aaac2 154
727c62dd 155/* Value of MOVE_RATIO. */
156int h8300_move_ratio;
a767736d 157\f
0650a2e5 158/* See below where shifts are handled for explanation of this enum. */
159
160enum shift_alg
161{
162 SHIFT_INLINE,
163 SHIFT_ROT_AND,
164 SHIFT_SPECIAL,
165 SHIFT_LOOP
166};
167
168/* Symbols of the various shifts which can be used as indices. */
169
170enum shift_type
171{
172 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
173};
174
175/* Macros to keep the shift algorithm tables small. */
176#define INL SHIFT_INLINE
177#define ROT SHIFT_ROT_AND
178#define LOP SHIFT_LOOP
179#define SPC SHIFT_SPECIAL
180
181/* The shift algorithms for each machine, mode, shift type, and shift
182 count are defined below. The three tables below correspond to
183 QImode, HImode, and SImode, respectively. Each table is organized
cc72e60a 184 by, in the order of indices, machine, shift type, and shift count. */
0650a2e5 185
186static enum shift_alg shift_alg_qi[3][3][8] = {
187 {
188 /* TARGET_H8300 */
189 /* 0 1 2 3 4 5 6 7 */
190 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
191 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
192 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
193 },
194 {
195 /* TARGET_H8300H */
196 /* 0 1 2 3 4 5 6 7 */
197 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
198 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
199 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
200 },
201 {
202 /* TARGET_H8300S */
203 /* 0 1 2 3 4 5 6 7 */
204 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
205 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
206 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
207 }
208};
209
210static enum shift_alg shift_alg_hi[3][3][16] = {
211 {
212 /* TARGET_H8300 */
213 /* 0 1 2 3 4 5 6 7 */
214 /* 8 9 10 11 12 13 14 15 */
215 { INL, INL, INL, INL, INL, INL, INL, SPC,
216 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
217 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
218 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
219 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
220 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
221 },
222 {
223 /* TARGET_H8300H */
224 /* 0 1 2 3 4 5 6 7 */
225 /* 8 9 10 11 12 13 14 15 */
226 { INL, INL, INL, INL, INL, INL, INL, SPC,
227 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
228 { INL, INL, INL, INL, INL, INL, INL, SPC,
229 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
230 { INL, INL, INL, INL, INL, INL, INL, SPC,
231 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
232 },
233 {
234 /* TARGET_H8300S */
235 /* 0 1 2 3 4 5 6 7 */
236 /* 8 9 10 11 12 13 14 15 */
237 { INL, INL, INL, INL, INL, INL, INL, INL,
238 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
239 { INL, INL, INL, INL, INL, INL, INL, INL,
240 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
241 { INL, INL, INL, INL, INL, INL, INL, INL,
242 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
243 }
244};
245
246static enum shift_alg shift_alg_si[3][3][32] = {
247 {
248 /* TARGET_H8300 */
249 /* 0 1 2 3 4 5 6 7 */
250 /* 8 9 10 11 12 13 14 15 */
251 /* 16 17 18 19 20 21 22 23 */
252 /* 24 25 26 27 28 29 30 31 */
253 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
254 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
255 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
256 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
257 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
258 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
259 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
260 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
261 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
262 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
263 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
264 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
265 },
266 {
267 /* TARGET_H8300H */
268 /* 0 1 2 3 4 5 6 7 */
269 /* 8 9 10 11 12 13 14 15 */
270 /* 16 17 18 19 20 21 22 23 */
271 /* 24 25 26 27 28 29 30 31 */
272 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
273 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
274 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
567c4b66 275 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
0650a2e5 276 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
277 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
278 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
567c4b66 279 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
0650a2e5 280 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
281 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
282 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
283 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
284 },
285 {
286 /* TARGET_H8300S */
287 /* 0 1 2 3 4 5 6 7 */
288 /* 8 9 10 11 12 13 14 15 */
289 /* 16 17 18 19 20 21 22 23 */
290 /* 24 25 26 27 28 29 30 31 */
291 { INL, INL, INL, INL, INL, INL, INL, INL,
292 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
293 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
567c4b66 294 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
0650a2e5 295 { INL, INL, INL, INL, INL, INL, INL, INL,
296 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
297 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
567c4b66 298 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
0650a2e5 299 { INL, INL, INL, INL, INL, INL, INL, INL,
300 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
301 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
302 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
303 }
304};
305
306#undef INL
307#undef ROT
308#undef LOP
309#undef SPC
310
311enum h8_cpu
312{
313 H8_300,
314 H8_300H,
315 H8_S
316};
317
b839e0b4 318/* Initialize various cpu specific globals at start up. */
319
4c834714 320static void
321h8300_option_override (void)
b839e0b4 322{
1592a00c 323 static const char *const h8_push_ops[2] = { "push" , "push.l" };
324 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
325 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
326
d3677aa8 327#ifndef OBJECT_FORMAT_ELF
328 if (TARGET_H8300SX)
329 {
330 error ("-msx is not supported in coff");
331 target_flags |= MASK_H8300S;
332 }
333#endif
334
b839e0b4 335 if (TARGET_H8300)
336 {
337 cpu_type = (int) CPU_H8300;
338 h8_reg_names = names_big;
339 }
340 else
341 {
11f95d7c 342 /* For this we treat the H8/300H and H8S the same. */
b839e0b4 343 cpu_type = (int) CPU_H8300H;
344 h8_reg_names = names_extended;
345 }
346 h8_push_op = h8_push_ops[cpu_type];
347 h8_pop_op = h8_pop_ops[cpu_type];
348 h8_mov_op = h8_mov_ops[cpu_type];
92d7ef92 349
350 if (!TARGET_H8300S && TARGET_MAC)
f060a027 351 {
68435912 352 error ("-ms2600 is used without -ms");
3f21adc8 353 target_flags |= MASK_H8300S_1;
f060a027 354 }
16b503e9 355
35a462ce 356 if (TARGET_H8300 && TARGET_NORMAL_MODE)
357 {
d3677aa8 358 error ("-mn is used without -mh or -ms or -msx");
35a462ce 359 target_flags ^= MASK_NORMAL_MODE;
360 }
0650a2e5 361
d3677aa8 362 if (! TARGET_H8300S && TARGET_EXR)
363 {
364 error ("-mexr is used without -ms");
365 target_flags |= MASK_H8300S_1;
366 }
367
368 if (TARGET_H8300 && TARGET_INT32)
369 {
370 error ("-mint32 is not supported for H8300 and H8300L targets");
371 target_flags ^= MASK_INT32;
372 }
373
374 if ((!TARGET_H8300S && TARGET_EXR) && (!TARGET_H8300SX && TARGET_EXR))
375 {
376 error ("-mexr is used without -ms or -msx");
377 target_flags |= MASK_H8300S_1;
378 }
379
380 if ((!TARGET_H8300S && TARGET_NEXR) && (!TARGET_H8300SX && TARGET_NEXR))
381 {
382 warning (OPT_mno_exr, "-mno-exr valid only with -ms or -msx \
383 - Option ignored!");
384 }
385
9f56f86b 386 /* Some of the shifts are optimized for speed by default.
0650a2e5 387 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
9f56f86b 388 If optimizing for size, change shift_alg for those shift to
0650a2e5 389 SHIFT_LOOP. */
3a599070 390 if (optimize_size)
0650a2e5 391 {
3a599070 392 /* H8/300 */
393 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
394 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
395 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
396 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
0650a2e5 397
3a599070 398 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
399 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
0650a2e5 400
3a599070 401 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
402 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
0650a2e5 403
3a599070 404 /* H8/300H */
405 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
406 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
0650a2e5 407
3a599070 408 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
409 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
0650a2e5 410
3a599070 411 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
412 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
413 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
414 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
0650a2e5 415
416 /* H8S */
3a599070 417 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
0650a2e5 418 }
727c62dd 419
420 /* Work out a value for MOVE_RATIO. */
421 if (!TARGET_H8300SX)
422 {
423 /* Memory-memory moves are quite expensive without the
424 h8sx instructions. */
425 h8300_move_ratio = 3;
426 }
427 else if (flag_omit_frame_pointer)
428 {
429 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
430 sometimes be as short as two individual memory-to-memory moves,
431 but since they use all the call-saved registers, it seems better
432 to allow up to three moves here. */
433 h8300_move_ratio = 4;
434 }
435 else if (optimize_size)
436 {
437 /* In this case we don't use movmd sequences since they tend
438 to be longer than calls to memcpy(). Memory-to-memory
439 moves are cheaper than for !TARGET_H8300SX, so it makes
440 sense to have a slightly higher threshold. */
441 h8300_move_ratio = 4;
442 }
443 else
444 {
445 /* We use movmd sequences for some moves since it can be quicker
446 than calling memcpy(). The sequences will need to save and
447 restore er6 though, so bump up the cost. */
448 h8300_move_ratio = 6;
449 }
1af17d44 450
451 /* This target defaults to strict volatile bitfields. */
941a2396 452 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
1af17d44 453 flag_strict_volatile_bitfields = 1;
727c62dd 454}
455
cdfb02e8 456/* Return the byte register name for a register rtx X. B should be 0
457 if you want a lower byte register. B should be 1 if you want an
458 upper byte register. */
459
7198848c 460static const char *
230002f2 461byte_reg (rtx x, int b)
e1629549 462{
ded3e58c 463 static const char *const names_small[] = {
464 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
465 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
466 };
e1629549 467
3afe906b 468 gcc_assert (REG_P (x));
589b6991 469
e1629549 470 return names_small[REGNO (x) * 2 + b];
471}
472
473/* REGNO must be saved/restored across calls if this macro is true. */
b839e0b4 474
ded3e58c 475#define WORD_REG_USED(regno) \
b91522ff 476 (regno < SP_REG \
ded3e58c 477 /* No need to save registers if this function will not return. */ \
478 && ! TREE_THIS_VOLATILE (current_function_decl) \
5344805f 479 && (h8300_saveall_function_p (current_function_decl) \
ded3e58c 480 /* Save any call saved register that was used. */ \
3072d30e 481 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
ded3e58c 482 /* Save the frame pointer if it was used. */ \
3072d30e 483 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
ded3e58c 484 /* Save any register used in an interrupt handler. */ \
41ed3bcd 485 || (h8300_current_function_interrupt_function_p () \
3072d30e 486 && df_regs_ever_live_p (regno)) \
ded3e58c 487 /* Save call clobbered registers in non-leaf interrupt \
488 handlers. */ \
41ed3bcd 489 || (h8300_current_function_interrupt_function_p () \
ded3e58c 490 && call_used_regs[regno] \
d5bf7b64 491 && !crtl->is_leaf)))
e1629549 492
80c13943 493/* We use this to wrap all emitted insns in the prologue. */
1a1ed145 494static rtx_insn *
495F (rtx_insn *x, bool set_it)
80c13943 496{
5da0dad2 497 if (set_it)
498 RTX_FRAME_RELATED_P (x) = 1;
80c13943 499 return x;
500}
501
502/* Mark all the subexpressions of the PARALLEL rtx PAR as
503 frame-related. Return PAR.
504
505 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
506 PARALLEL rtx other than the first if they do not have the
507 FRAME_RELATED flag set on them. */
508static rtx
509Fpa (rtx par)
510{
511 int len = XVECLEN (par, 0);
512 int i;
513
514 for (i = 0; i < len; i++)
1a1ed145 515 F (as_a <rtx_insn *> (XVECEXP (par, 0, i)), true);
80c13943 516
517 return par;
518}
519
e1629549 520/* Output assembly language to FILE for the operation OP with operand size
b839e0b4 521 SIZE to adjust the stack pointer. */
b839e0b4 522
e1629549 523static void
5da0dad2 524h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue)
e1629549 525{
921a6571 526 /* If the frame size is 0, we don't have anything to do. */
527 if (size == 0)
a3dedda8 528 return;
921a6571 529
8f260b97 530 /* H8/300 cannot add/subtract a large constant with a single
531 instruction. If a temporary register is available, load the
532 constant to it and then do the addition. */
533 if (TARGET_H8300
534 && size > 4
535 && !h8300_current_function_interrupt_function_p ()
4ee9c684 536 && !(cfun->static_chain_decl != NULL && sign < 0))
b9393aaf 537 {
8f260b97 538 rtx r3 = gen_rtx_REG (Pmode, 3);
5da0dad2 539 F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue);
80c13943 540 F (emit_insn (gen_addhi3 (stack_pointer_rtx,
5da0dad2 541 stack_pointer_rtx, r3)), in_prologue);
bfc1492f 542 }
543 else
544 {
8f260b97 545 /* The stack adjustment made here is further optimized by the
546 splitter. In case of H8/300, the splitter always splits the
80c13943 547 addition emitted here to make the adjustment interrupt-safe.
548 FIXME: We don't always tag those, because we don't know what
549 the splitter will do. */
921a6571 550 if (Pmode == HImode)
80c13943 551 {
1a1ed145 552 rtx_insn *x = emit_insn (gen_addhi3 (stack_pointer_rtx,
553 stack_pointer_rtx,
554 GEN_INT (sign * size)));
80c13943 555 if (size < 4)
5da0dad2 556 F (x, in_prologue);
80c13943 557 }
921a6571 558 else
80c13943 559 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
5da0dad2 560 stack_pointer_rtx, GEN_INT (sign * size))), in_prologue);
e1629549 561 }
562}
563
b1292c73 564/* Round up frame size SIZE. */
565
959e2f12 566static HOST_WIDE_INT
567round_frame_size (HOST_WIDE_INT size)
b1292c73 568{
b25ffd74 569 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
570 & -STACK_BOUNDARY / BITS_PER_UNIT);
b1292c73 571}
572
573/* Compute which registers to push/pop.
574 Return a bit vector of registers. */
575
576static unsigned int
230002f2 577compute_saved_regs (void)
b1292c73 578{
579 unsigned int saved_regs = 0;
580 int regno;
581
582 /* Construct a bit vector of registers to be pushed/popped. */
f4ac50fb 583 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
b1292c73 584 {
585 if (WORD_REG_USED (regno))
586 saved_regs |= 1 << regno;
587 }
588
589 /* Don't push/pop the frame pointer as it is treated separately. */
590 if (frame_pointer_needed)
f4ac50fb 591 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
b1292c73 592
593 return saved_regs;
594}
595
8f260b97 596/* Emit an insn to push register RN. */
b1292c73 597
a5c6cfdd 598static rtx
230002f2 599push (int rn)
b1292c73 600{
8f260b97 601 rtx reg = gen_rtx_REG (word_mode, rn);
602 rtx x;
603
4081a531 604 if (TARGET_H8300)
8f260b97 605 x = gen_push_h8300 (reg);
c99597ba 606 else if (!TARGET_NORMAL_MODE)
34712114 607 x = gen_push_h8300hs_advanced (reg);
c99597ba 608 else
609 x = gen_push_h8300hs_normal (reg);
5a23ee68 610 x = F (emit_insn (x), true);
539b539f 611 add_reg_note (x, REG_INC, stack_pointer_rtx);
a5c6cfdd 612 return x;
b1292c73 613}
614
8f260b97 615/* Emit an insn to pop register RN. */
b1292c73 616
a5c6cfdd 617static rtx
230002f2 618pop (int rn)
b1292c73 619{
8f260b97 620 rtx reg = gen_rtx_REG (word_mode, rn);
621 rtx x;
622
4081a531 623 if (TARGET_H8300)
8f260b97 624 x = gen_pop_h8300 (reg);
c99597ba 625 else if (!TARGET_NORMAL_MODE)
34712114 626 x = gen_pop_h8300hs_advanced (reg);
c99597ba 627 else
628 x = gen_pop_h8300hs_normal (reg);
8f260b97 629 x = emit_insn (x);
539b539f 630 add_reg_note (x, REG_INC, stack_pointer_rtx);
a5c6cfdd 631 return x;
b1292c73 632}
e1629549 633
727c62dd 634/* Emit an instruction to push or pop NREGS consecutive registers
635 starting at register REGNO. POP_P selects a pop rather than a
636 push and RETURN_P is true if the instruction should return.
637
638 It must be possible to do the requested operation in a single
639 instruction. If NREGS == 1 && !RETURN_P, use a normal push
640 or pop insn. Otherwise emit a parallel of the form:
641
642 (parallel
643 [(return) ;; if RETURN_P
644 (save or restore REGNO)
645 (save or restore REGNO + 1)
646 ...
647 (save or restore REGNO + NREGS - 1)
648 (set sp (plus sp (const_int adjust)))] */
649
650static void
5a23ee68 651h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p)
727c62dd 652{
653 int i, j;
654 rtvec vec;
80c13943 655 rtx sp, offset, x;
727c62dd 656
657 /* See whether we can use a simple push or pop. */
658 if (!return_p && nregs == 1)
659 {
660 if (pop_p)
661 pop (regno);
662 else
663 push (regno);
664 return;
665 }
666
667 /* We need one element for the return insn, if present, one for each
668 register, and one for stack adjustment. */
5a23ee68 669 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1);
727c62dd 670 sp = stack_pointer_rtx;
671 i = 0;
672
673 /* Add the return instruction. */
674 if (return_p)
675 {
1a860023 676 RTVEC_ELT (vec, i) = ret_rtx;
727c62dd 677 i++;
678 }
679
680 /* Add the register moves. */
681 for (j = 0; j < nregs; j++)
682 {
683 rtx lhs, rhs;
684
685 if (pop_p)
686 {
687 /* Register REGNO + NREGS - 1 is popped first. Before the
688 stack adjustment, its slot is at address @sp. */
689 lhs = gen_rtx_REG (SImode, regno + j);
29c05e22 690 rhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp,
691 (nregs - j - 1) * 4));
727c62dd 692 }
693 else
694 {
695 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
29c05e22 696 lhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, (j + 1) * -4));
727c62dd 697 rhs = gen_rtx_REG (SImode, regno + j);
698 }
699 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, lhs, rhs);
700 }
701
702 /* Add the stack adjustment. */
703 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
704 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, sp,
705 gen_rtx_PLUS (Pmode, sp, offset));
706
80c13943 707 x = gen_rtx_PARALLEL (VOIDmode, vec);
708 if (!pop_p)
709 x = Fpa (x);
5a23ee68 710
711 if (return_p)
712 emit_jump_insn (x);
713 else
714 emit_insn (x);
727c62dd 715}
716
717/* Return true if X has the value sp + OFFSET. */
718
719static int
720h8300_stack_offset_p (rtx x, int offset)
721{
722 if (offset == 0)
723 return x == stack_pointer_rtx;
724
725 return (GET_CODE (x) == PLUS
726 && XEXP (x, 0) == stack_pointer_rtx
727 && GET_CODE (XEXP (x, 1)) == CONST_INT
728 && INTVAL (XEXP (x, 1)) == offset);
729}
730
731/* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
732 something that may be an ldm or stm instruction. If it fits
733 the required template, return the register it loads or stores,
734 otherwise return -1.
735
736 LOAD_P is true if X should be a load, false if it should be a store.
737 NREGS is the number of registers that the whole instruction is expected
738 to load or store. INDEX is the index of the register that X should
739 load or store, relative to the lowest-numbered register. */
740
741static int
742h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
743{
744 int regindex, memindex, offset;
745
746 if (load_p)
747 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
748 else
749 memindex = 0, regindex = 1, offset = (index + 1) * -4;
750
751 if (GET_CODE (x) == SET
752 && GET_CODE (XEXP (x, regindex)) == REG
753 && GET_CODE (XEXP (x, memindex)) == MEM
754 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
755 return REGNO (XEXP (x, regindex));
756
757 return -1;
758}
759
760/* Return true if the elements of VEC starting at FIRST describe an
761 ldm or stm instruction (LOAD_P says which). */
762
d255713c 763int
727c62dd 764h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
765{
766 rtx last;
767 int nregs, i, regno, adjust;
768
769 /* There must be a stack adjustment, a register move, and at least one
770 other operation (a return or another register move). */
771 if (GET_NUM_ELEM (vec) < 3)
772 return false;
773
774 /* Get the range of registers to be pushed or popped. */
775 nregs = GET_NUM_ELEM (vec) - first - 1;
776 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
777
778 /* Check that the call to h8300_ldm_stm_regno succeeded and
779 that we're only dealing with GPRs. */
780 if (regno < 0 || regno + nregs > 8)
781 return false;
782
783 /* 2-register h8s instructions must start with an even-numbered register.
784 3- and 4-register instructions must start with er0 or er4. */
785 if (!TARGET_H8300SX)
786 {
787 if ((regno & 1) != 0)
788 return false;
789 if (nregs > 2 && (regno & 3) != 0)
790 return false;
791 }
792
793 /* Check the other loads or stores. */
794 for (i = 1; i < nregs; i++)
795 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
796 != regno + i)
797 return false;
798
799 /* Check the stack adjustment. */
800 last = RTVEC_ELT (vec, first + nregs);
801 adjust = (load_p ? nregs : -nregs) * 4;
802 return (GET_CODE (last) == SET
803 && SET_DEST (last) == stack_pointer_rtx
804 && h8300_stack_offset_p (SET_SRC (last), adjust));
805}
806
f2702e8a 807/* This is what the stack looks like after the prolog of
e1629549 808 a function with a frame has been set up:
809
b839e0b4 810 <args>
811 PC
812 FP <- fp
813 <locals>
9f56f86b 814 <saved registers> <- sp
e1629549 815
816 This is what the stack looks like after the prolog of
817 a function which doesn't have a frame:
818
b839e0b4 819 <args>
820 PC
821 <locals>
9f56f86b 822 <saved registers> <- sp
e1629549 823*/
824
8f260b97 825/* Generate RTL code for the function prologue. */
b1292c73 826
8f260b97 827void
230002f2 828h8300_expand_prologue (void)
e1629549 829{
b2adb3e0 830 int regno;
b1292c73 831 int saved_regs;
97709d8d 832 int n_regs;
e1629549 833
09c48b9c 834 /* If the current function has the OS_Task attribute set, then
835 we have a naked prologue. */
836 if (h8300_os_task_function_p (current_function_decl))
8f260b97 837 return;
09c48b9c 838
839 if (h8300_monitor_function_p (current_function_decl))
d3677aa8 840 /* The monitor function act as normal functions, which means it
841 can accept parameters and return values. In addition to this,
842 interrupts are masked in prologue and return with "rte" in epilogue. */
8f260b97 843 emit_insn (gen_monitor_prologue ());
09c48b9c 844
b839e0b4 845 if (frame_pointer_needed)
846 {
eb2aa24e 847 /* Push fp. */
f4ac50fb 848 push (HARD_FRAME_POINTER_REGNUM);
5a23ee68 849 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true);
69b4e418 850 }
b839e0b4 851
b1292c73 852 /* Push the rest of the registers in ascending order. */
853 saved_regs = compute_saved_regs ();
b2adb3e0 854 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
97709d8d 855 {
97709d8d 856 n_regs = 1;
b1292c73 857 if (saved_regs & (1 << regno))
69b4e418 858 {
859 if (TARGET_H8300S)
860 {
97709d8d 861 /* See how many registers we can push at the same time. */
727c62dd 862 if ((!TARGET_H8300SX || (regno & 3) == 0)
b1292c73 863 && ((saved_regs >> regno) & 0x0f) == 0x0f)
97709d8d 864 n_regs = 4;
865
727c62dd 866 else if ((!TARGET_H8300SX || (regno & 3) == 0)
b1292c73 867 && ((saved_regs >> regno) & 0x07) == 0x07)
97709d8d 868 n_regs = 3;
869
727c62dd 870 else if ((!TARGET_H8300SX || (regno & 1) == 0)
b1292c73 871 && ((saved_regs >> regno) & 0x03) == 0x03)
97709d8d 872 n_regs = 2;
69b4e418 873 }
97709d8d 874
5a23ee68 875 h8300_push_pop (regno, n_regs, false, false);
e1629549 876 }
877 }
f4ac50fb 878
879 /* Leave room for locals. */
5da0dad2 880 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
e1629549 881}
882
cdfb02e8 883/* Return nonzero if we can use "rts" for the function currently being
884 compiled. */
885
8f260b97 886int
230002f2 887h8300_can_use_return_insn_p (void)
8f260b97 888{
889 return (reload_completed
890 && !frame_pointer_needed
891 && get_frame_size () == 0
892 && compute_saved_regs () == 0);
893}
e1629549 894
8f260b97 895/* Generate RTL code for the function epilogue. */
896
897void
230002f2 898h8300_expand_epilogue (void)
e1629549 899{
b2adb3e0 900 int regno;
b1292c73 901 int saved_regs;
97709d8d 902 int n_regs;
727c62dd 903 HOST_WIDE_INT frame_size;
904 bool returned_p;
e1629549 905
41ed3bcd 906 if (h8300_os_task_function_p (current_function_decl))
8f260b97 907 /* OS_Task epilogues are nearly naked -- they just have an
908 rts instruction. */
909 return;
e1629549 910
727c62dd 911 frame_size = round_frame_size (get_frame_size ());
912 returned_p = false;
913
f4ac50fb 914 /* Deallocate locals. */
5da0dad2 915 h8300_emit_stack_adjustment (1, frame_size, false);
f4ac50fb 916
b1292c73 917 /* Pop the saved registers in descending order. */
918 saved_regs = compute_saved_regs ();
b2adb3e0 919 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
97709d8d 920 {
97709d8d 921 n_regs = 1;
b1292c73 922 if (saved_regs & (1 << regno))
e1629549 923 {
69b4e418 924 if (TARGET_H8300S)
925 {
97709d8d 926 /* See how many registers we can pop at the same time. */
727c62dd 927 if ((TARGET_H8300SX || (regno & 3) == 3)
928 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
97709d8d 929 n_regs = 4;
930
727c62dd 931 else if ((TARGET_H8300SX || (regno & 3) == 2)
932 && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
97709d8d 933 n_regs = 3;
934
727c62dd 935 else if ((TARGET_H8300SX || (regno & 1) == 1)
936 && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
97709d8d 937 n_regs = 2;
69b4e418 938 }
97709d8d 939
727c62dd 940 /* See if this pop would be the last insn before the return.
941 If so, use rte/l or rts/l instead of pop or ldm.l. */
942 if (TARGET_H8300SX
943 && !frame_pointer_needed
944 && frame_size == 0
945 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
946 returned_p = true;
947
5a23ee68 948 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p);
e1629549 949 }
e1629549 950 }
b839e0b4 951
eb2aa24e 952 /* Pop frame pointer if we had one. */
69b4e418 953 if (frame_pointer_needed)
727c62dd 954 {
955 if (TARGET_H8300SX)
956 returned_p = true;
5a23ee68 957 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p);
727c62dd 958 }
959
960 if (!returned_p)
1a860023 961 emit_jump_insn (ret_rtx);
8f260b97 962}
69b4e418 963
41ed3bcd 964/* Return nonzero if the current function is an interrupt
965 function. */
966
967int
230002f2 968h8300_current_function_interrupt_function_p (void)
41ed3bcd 969{
d3677aa8 970 return (h8300_interrupt_function_p (current_function_decl));
971}
972
973int
974h8300_current_function_monitor_function_p ()
975{
976 return (h8300_monitor_function_p (current_function_decl));
41ed3bcd 977}
978
b839e0b4 979/* Output assembly code for the start of the file. */
980
92c473b8 981static void
982h8300_file_start (void)
b839e0b4 983{
92c473b8 984 default_file_start ();
9f56f86b 985
b839e0b4 986 if (TARGET_H8300H)
92c473b8 987 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
727c62dd 988 else if (TARGET_H8300SX)
989 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
69b4e418 990 else if (TARGET_H8300S)
92c473b8 991 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
b839e0b4 992}
993
994/* Output assembly language code for the end of file. */
995
f6940372 996static void
230002f2 997h8300_file_end (void)
b839e0b4 998{
f6940372 999 fputs ("\t.end\n", asm_out_file);
e1629549 1000}
1001\f
c5673261 1002/* Split an add of a small constant into two adds/subs insns.
1003
1004 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1005 instead of adds/subs. */
8e7d5182 1006
1007void
230002f2 1008split_adds_subs (enum machine_mode mode, rtx *operands)
0a56558f 1009{
8e7d5182 1010 HOST_WIDE_INT val = INTVAL (operands[1]);
1011 rtx reg = operands[0];
d8afbfc6 1012 HOST_WIDE_INT sign = 1;
1013 HOST_WIDE_INT amount;
90b024e5 1014 rtx (*gen_add) (rtx, rtx, rtx);
0a56558f 1015
d8afbfc6 1016 /* Force VAL to be positive so that we do not have to consider the
1017 sign. */
1018 if (val < 0)
0a56558f 1019 {
d8afbfc6 1020 val = -val;
1021 sign = -1;
1022 }
0a56558f 1023
c5673261 1024 switch (mode)
1025 {
1026 case HImode:
90b024e5 1027 gen_add = gen_addhi3;
c5673261 1028 break;
1029
1030 case SImode:
90b024e5 1031 gen_add = gen_addsi3;
c5673261 1032 break;
1033
1034 default:
3afe906b 1035 gcc_unreachable ();
c5673261 1036 }
1037
d8afbfc6 1038 /* Try different amounts in descending order. */
1039 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
1040 amount > 0;
1041 amount /= 2)
1042 {
27276a3b 1043 for (; val >= amount; val -= amount)
90b024e5 1044 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
0a56558f 1045 }
1046
d8afbfc6 1047 return;
0a56558f 1048}
1049
e1629549 1050/* Handle machine specific pragmas for compatibility with existing
b839e0b4 1051 compilers for the H8/300.
e1629549 1052
cc72e60a 1053 pragma saveall generates prologue/epilogue code which saves and
e1629549 1054 restores all the registers on function entry.
b839e0b4 1055
e1629549 1056 pragma interrupt saves and restores all registers, and exits with
1057 an rte instruction rather than an rts. A pointer to a function
1058 with this attribute may be safely used in an interrupt vector. */
b839e0b4 1059
1fcd08b1 1060void
230002f2 1061h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
e1629549 1062{
41ed3bcd 1063 pragma_interrupt = 1;
1fcd08b1 1064}
b97b38c0 1065
1fcd08b1 1066void
230002f2 1067h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1fcd08b1 1068{
1069 pragma_saveall = 1;
e1629549 1070}
1fcd08b1 1071
c738c371 1072/* If the next function argument with MODE and TYPE is to be passed in
1073 a register, return a reg RTX for the hard register in which to pass
1074 the argument. CUM represents the state after the last argument.
e7489b8b 1075 If the argument is to be pushed, NULL_RTX is returned.
b839e0b4 1076
e7489b8b 1077 On the H8/300 all normal args are pushed, unless -mquickcall in which
1078 case the first 3 arguments are passed in registers. */
1079
1080static rtx
39cba157 1081h8300_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
e7489b8b 1082 const_tree type, bool named)
e1629549 1083{
39cba157 1084 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1085
70a21926 1086 static const char *const hand_list[] = {
1087 "__main",
1088 "__cmpsi2",
1089 "__divhi3",
1090 "__modhi3",
1091 "__udivhi3",
1092 "__umodhi3",
1093 "__divsi3",
1094 "__modsi3",
1095 "__udivsi3",
1096 "__umodsi3",
1097 "__mulhi3",
1098 "__mulsi3",
1099 "__reg_memcpy",
1100 "__reg_memset",
1101 "__ucmpsi2",
1102 0,
1103 };
1104
6996dd46 1105 rtx result = NULL_RTX;
9305fe33 1106 const char *fname;
b839e0b4 1107 int regpass = 0;
1108
0d37f3a1 1109 /* Never pass unnamed arguments in registers. */
1110 if (!named)
6996dd46 1111 return NULL_RTX;
0d37f3a1 1112
b839e0b4 1113 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1114 if (TARGET_QUICKCALL)
1115 regpass = 3;
1116
1117 /* If calling hand written assembler, use 4 regs of args. */
b839e0b4 1118 if (cum->libcall)
1119 {
9305fe33 1120 const char * const *p;
b839e0b4 1121
1122 fname = XSTR (cum->libcall, 0);
1123
1124 /* See if this libcall is one of the hand coded ones. */
b839e0b4 1125 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1126 ;
e1629549 1127
b839e0b4 1128 if (*p)
1129 regpass = 4;
1130 }
1131
1132 if (regpass)
1133 {
1134 int size;
1135
1136 if (mode == BLKmode)
1137 size = int_size_in_bytes (type);
1138 else
1139 size = GET_MODE_SIZE (mode);
1140
60ff2ea8 1141 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1142 && cum->nbytes / UNITS_PER_WORD <= 3)
1143 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
b839e0b4 1144 }
e1629549 1145
b839e0b4 1146 return result;
1147}
e7489b8b 1148
1149/* Update the data in CUM to advance over an argument
1150 of mode MODE and data type TYPE.
1151 (TYPE is null for libcalls where that information may not be available.) */
1152
1153static void
39cba157 1154h8300_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
e7489b8b 1155 const_tree type, bool named ATTRIBUTE_UNUSED)
1156{
39cba157 1157 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1158
e7489b8b 1159 cum->nbytes += (mode != BLKmode
1160 ? (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD
1161 : (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD);
1162}
1163
b839e0b4 1164\f
87ad9aff 1165/* Implements TARGET_REGISTER_MOVE_COST.
1166
1167 Any SI register-to-register move may need to be reloaded,
1168 so inmplement h8300_register_move_cost to return > 2 so that reload never
1169 shortcuts. */
1170
1171static int
1172h8300_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1173 reg_class_t from, reg_class_t to)
1174{
1175 if (from == MAC_REGS || to == MAC_REG)
1176 return 6;
1177 else
1178 return 3;
1179}
1180
cdfb02e8 1181/* Compute the cost of an and insn. */
1182
fab7adbf 1183static int
230002f2 1184h8300_and_costs (rtx x)
b785ceb4 1185{
1186 rtx operands[4];
1187
1188 if (GET_MODE (x) == QImode)
1189 return 1;
1190
1191 if (GET_MODE (x) != HImode
1192 && GET_MODE (x) != SImode)
1193 return 100;
1194
1195 operands[0] = NULL;
727c62dd 1196 operands[1] = XEXP (x, 0);
b785ceb4 1197 operands[2] = XEXP (x, 1);
1198 operands[3] = x;
5a622ac3 1199 return compute_logical_op_length (GET_MODE (x), operands) / 2;
b785ceb4 1200}
1201
cdfb02e8 1202/* Compute the cost of a shift insn. */
1203
fab7adbf 1204static int
230002f2 1205h8300_shift_costs (rtx x)
c033ada4 1206{
1207 rtx operands[4];
1208
1209 if (GET_MODE (x) != QImode
1210 && GET_MODE (x) != HImode
1211 && GET_MODE (x) != SImode)
1212 return 100;
1213
1214 operands[0] = NULL;
1215 operands[1] = NULL;
1216 operands[2] = XEXP (x, 1);
1217 operands[3] = x;
5a622ac3 1218 return compute_a_shift_length (NULL, operands) / 2;
c033ada4 1219}
fab7adbf 1220
cdfb02e8 1221/* Worker function for TARGET_RTX_COSTS. */
1222
fab7adbf 1223static bool
20d892d1 1224h8300_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
1225 int *total, bool speed)
fab7adbf 1226{
727c62dd 1227 if (TARGET_H8300SX && outer_code == MEM)
1228 {
1229 /* Estimate the number of execution states needed to calculate
1230 the address. */
1231 if (register_operand (x, VOIDmode)
1232 || GET_CODE (x) == POST_INC
1233 || GET_CODE (x) == POST_DEC
1234 || CONSTANT_P (x))
1235 *total = 0;
1236 else
1237 *total = COSTS_N_INSNS (1);
1238 return true;
1239 }
1240
fab7adbf 1241 switch (code)
1242 {
1d6dae88 1243 case CONST_INT:
1244 {
1245 HOST_WIDE_INT n = INTVAL (x);
1246
727c62dd 1247 if (TARGET_H8300SX)
1248 {
1249 /* Constant operands need the same number of processor
1250 states as register operands. Although we could try to
f529eb25 1251 use a size-based cost for !speed, the lack of
727c62dd 1252 of a mode makes the results very unpredictable. */
1253 *total = 0;
1254 return true;
1255 }
6b5c1012 1256 if (-4 <= n && n <= 4)
1d6dae88 1257 {
1258 switch ((int) n)
1259 {
1260 case 0:
1261 *total = 0;
1262 return true;
1263 case 1:
1264 case 2:
1265 case -1:
1266 case -2:
1267 *total = 0 + (outer_code == SET);
1268 return true;
1269 case 4:
1270 case -4:
1271 if (TARGET_H8300H || TARGET_H8300S)
1272 *total = 0 + (outer_code == SET);
1273 else
1274 *total = 1;
1275 return true;
1276 }
1277 }
1278 *total = 1;
1279 return true;
1280 }
1281
1282 case CONST:
1283 case LABEL_REF:
1284 case SYMBOL_REF:
727c62dd 1285 if (TARGET_H8300SX)
1286 {
1287 /* See comment for CONST_INT. */
1288 *total = 0;
1289 return true;
1290 }
1d6dae88 1291 *total = 3;
1292 return true;
1293
1294 case CONST_DOUBLE:
1295 *total = 20;
1296 return true;
1297
74f4459c 1298 case COMPARE:
1299 if (XEXP (x, 1) == const0_rtx)
1300 *total = 0;
1301 return false;
1302
fab7adbf 1303 case AND:
727c62dd 1304 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
1305 || !h8300_src_operand (XEXP (x, 1), VOIDmode))
1306 return false;
fab7adbf 1307 *total = COSTS_N_INSNS (h8300_and_costs (x));
1308 return true;
1309
1310 /* We say that MOD and DIV are so expensive because otherwise we'll
1311 generate some really horrible code for division of a power of two. */
1312 case MOD:
1313 case DIV:
727c62dd 1314 case UMOD:
1315 case UDIV:
1316 if (TARGET_H8300SX)
1317 switch (GET_MODE (x))
1318 {
1319 case QImode:
1320 case HImode:
f529eb25 1321 *total = COSTS_N_INSNS (!speed ? 4 : 10);
727c62dd 1322 return false;
1323
1324 case SImode:
f529eb25 1325 *total = COSTS_N_INSNS (!speed ? 4 : 18);
727c62dd 1326 return false;
1327
1328 default:
1329 break;
1330 }
1331 *total = COSTS_N_INSNS (12);
fab7adbf 1332 return true;
1333
1334 case MULT:
727c62dd 1335 if (TARGET_H8300SX)
1336 switch (GET_MODE (x))
1337 {
1338 case QImode:
1339 case HImode:
1340 *total = COSTS_N_INSNS (2);
1341 return false;
1342
1343 case SImode:
1344 *total = COSTS_N_INSNS (5);
1345 return false;
1346
1347 default:
1348 break;
1349 }
1350 *total = COSTS_N_INSNS (4);
fab7adbf 1351 return true;
1352
1353 case ASHIFT:
1354 case ASHIFTRT:
1355 case LSHIFTRT:
727c62dd 1356 if (h8sx_binary_shift_operator (x, VOIDmode))
1357 {
1358 *total = COSTS_N_INSNS (2);
1359 return false;
1360 }
1361 else if (h8sx_unary_shift_operator (x, VOIDmode))
1362 {
1363 *total = COSTS_N_INSNS (1);
1364 return false;
1365 }
fab7adbf 1366 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1367 return true;
1368
1369 case ROTATE:
1370 case ROTATERT:
1371 if (GET_MODE (x) == HImode)
1372 *total = 2;
1373 else
1374 *total = 8;
1375 return true;
1376
1377 default:
727c62dd 1378 *total = COSTS_N_INSNS (1);
1379 return false;
fab7adbf 1380 }
1381}
b839e0b4 1382\f
e1629549 1383/* Documentation for the machine specific operand escapes:
1384
b839e0b4 1385 'E' like s but negative.
1386 'F' like t but negative.
1387 'G' constant just the negative
2c7be643 1388 'R' print operand as a byte:8 address if appropriate, else fall back to
1389 'X' handling.
b839e0b4 1390 'S' print operand as a long word
e1629549 1391 'T' print operand as a word
b839e0b4 1392 'V' find the set bit, and print its number.
1393 'W' find the clear bit, and print its number.
1394 'X' print operand as a byte
e1629549 1395 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
2c7be643 1396 If this operand isn't a register, fall back to 'R' handling.
b839e0b4 1397 'Z' print int & 7.
4c924258 1398 'c' print the opcode corresponding to rtl
03fb0c81 1399 'e' first word of 32-bit value - if reg, then least reg. if mem
b839e0b4 1400 then least. if const then most sig word
03fb0c81 1401 'f' second word of 32-bit value - if reg, then biggest reg. if mem
b839e0b4 1402 then +2. if const then least sig word
e1629549 1403 'j' print operand as condition code.
1404 'k' print operand as reverse condition code.
727c62dd 1405 'm' convert an integer operand to a size suffix (.b, .w or .l)
1406 'o' print an integer without a leading '#'
03fb0c81 1407 's' print as low byte of 16-bit value
1408 't' print as high byte of 16-bit value
1409 'w' print as low byte of 32-bit value
1410 'x' print as 2nd byte of 32-bit value
1411 'y' print as 3rd byte of 32-bit value
1412 'z' print as msb of 32-bit value
b839e0b4 1413*/
e1629549 1414
1415/* Return assembly language string which identifies a comparison type. */
1416
9305fe33 1417static const char *
230002f2 1418cond_string (enum rtx_code code)
e1629549 1419{
1420 switch (code)
1421 {
1422 case NE:
1423 return "ne";
1424 case EQ:
1425 return "eq";
1426 case GE:
1427 return "ge";
1428 case GT:
1429 return "gt";
1430 case LE:
1431 return "le";
1432 case LT:
1433 return "lt";
1434 case GEU:
1435 return "hs";
1436 case GTU:
1437 return "hi";
1438 case LEU:
1439 return "ls";
1440 case LTU:
1441 return "lo";
1442 default:
3afe906b 1443 gcc_unreachable ();
e1629549 1444 }
1445}
1446
1447/* Print operand X using operand code CODE to assembly language output file
1448 FILE. */
1449
87ad9aff 1450static void
1451h8300_print_operand (FILE *file, rtx x, int code)
e1629549 1452{
30c992ef 1453 /* This is used for communication between codes V,W,Z and Y. */
e1629549 1454 static int bitint;
1455
1456 switch (code)
1457 {
3d835ed7 1458 case 'C':
1459 if (h8300_constant_length (x) == 2)
1460 fprintf (file, ":16");
1461 else
1462 fprintf (file, ":32");
1463 return;
b839e0b4 1464 case 'E':
1465 switch (GET_CODE (x))
1466 {
1467 case REG:
1468 fprintf (file, "%sl", names_big[REGNO (x)]);
1469 break;
1470 case CONST_INT:
21650cc9 1471 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
b839e0b4 1472 break;
1473 default:
3afe906b 1474 gcc_unreachable ();
b839e0b4 1475 }
1476 break;
1477 case 'F':
1478 switch (GET_CODE (x))
1479 {
1480 case REG:
1481 fprintf (file, "%sh", names_big[REGNO (x)]);
1482 break;
1483 case CONST_INT:
21650cc9 1484 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
b839e0b4 1485 break;
1486 default:
3afe906b 1487 gcc_unreachable ();
b839e0b4 1488 }
1489 break;
e1629549 1490 case 'G':
3afe906b 1491 gcc_assert (GET_CODE (x) == CONST_INT);
21650cc9 1492 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
e1629549 1493 break;
b839e0b4 1494 case 'S':
1495 if (GET_CODE (x) == REG)
1496 fprintf (file, "%s", names_extended[REGNO (x)]);
e1629549 1497 else
b839e0b4 1498 goto def;
e1629549 1499 break;
b839e0b4 1500 case 'T':
1501 if (GET_CODE (x) == REG)
1502 fprintf (file, "%s", names_big[REGNO (x)]);
e1629549 1503 else
b839e0b4 1504 goto def;
e1629549 1505 break;
b839e0b4 1506 case 'V':
cfdcbbf4 1507 bitint = (INTVAL (x) & 0xffff);
1508 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1)
1509 bitint = exact_log2 (bitint & 0xff);
1510 else
1511 bitint = exact_log2 ((bitint >> 8) & 0xff);
3afe906b 1512 gcc_assert (bitint >= 0);
3a59a065 1513 fprintf (file, "#%d", bitint);
e1629549 1514 break;
b839e0b4 1515 case 'W':
cfdcbbf4 1516 bitint = ((~INTVAL (x)) & 0xffff);
1517 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 )
1518 bitint = exact_log2 (bitint & 0xff);
1519 else
1520 bitint = (exact_log2 ((bitint >> 8) & 0xff));
3afe906b 1521 gcc_assert (bitint >= 0);
3a59a065 1522 fprintf (file, "#%d", bitint);
e1629549 1523 break;
2c7be643 1524 case 'R':
b839e0b4 1525 case 'X':
1526 if (GET_CODE (x) == REG)
1527 fprintf (file, "%s", byte_reg (x, 0));
1528 else
1529 goto def;
1530 break;
1531 case 'Y':
3afe906b 1532 gcc_assert (bitint >= 0);
b839e0b4 1533 if (GET_CODE (x) == REG)
1534 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1535 else
87ad9aff 1536 h8300_print_operand (file, x, 'R');
b839e0b4 1537 bitint = -1;
1538 break;
1539 case 'Z':
1540 bitint = INTVAL (x);
e1629549 1541 fprintf (file, "#%d", bitint & 7);
1542 break;
4c924258 1543 case 'c':
1544 switch (GET_CODE (x))
1545 {
1546 case IOR:
1547 fprintf (file, "or");
1548 break;
1549 case XOR:
1550 fprintf (file, "xor");
1551 break;
77016b8f 1552 case AND:
1553 fprintf (file, "and");
1554 break;
4c924258 1555 default:
1556 break;
1557 }
1558 break;
e1629549 1559 case 'e':
1560 switch (GET_CODE (x))
1561 {
1562 case REG:
b839e0b4 1563 if (TARGET_H8300)
1564 fprintf (file, "%s", names_big[REGNO (x)]);
1565 else
1566 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
e1629549 1567 break;
1568 case MEM:
87ad9aff 1569 h8300_print_operand (file, x, 0);
e1629549 1570 break;
1571 case CONST_INT:
21650cc9 1572 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
e1629549 1573 break;
737a5d5b 1574 case CONST_DOUBLE:
1575 {
1576 long val;
1577 REAL_VALUE_TYPE rv;
1578 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1579 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
9305fe33 1580 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
737a5d5b 1581 break;
1582 }
e1629549 1583 default:
3afe906b 1584 gcc_unreachable ();
e1629549 1585 break;
1586 }
1587 break;
e1629549 1588 case 'f':
1589 switch (GET_CODE (x))
1590 {
1591 case REG:
b839e0b4 1592 if (TARGET_H8300)
1593 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1594 else
1595 fprintf (file, "%s", names_big[REGNO (x)]);
e1629549 1596 break;
e1629549 1597 case MEM:
eafc6604 1598 x = adjust_address (x, HImode, 2);
87ad9aff 1599 h8300_print_operand (file, x, 0);
e1629549 1600 break;
e1629549 1601 case CONST_INT:
21650cc9 1602 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
e1629549 1603 break;
737a5d5b 1604 case CONST_DOUBLE:
1605 {
1606 long val;
1607 REAL_VALUE_TYPE rv;
1608 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1609 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
9305fe33 1610 fprintf (file, "#%ld", (val & 0xffff));
737a5d5b 1611 break;
1612 }
e1629549 1613 default:
3afe906b 1614 gcc_unreachable ();
e1629549 1615 }
1616 break;
e1629549 1617 case 'j':
7fe1d31c 1618 fputs (cond_string (GET_CODE (x)), file);
e1629549 1619 break;
e1629549 1620 case 'k':
7fe1d31c 1621 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
e1629549 1622 break;
727c62dd 1623 case 'm':
3afe906b 1624 gcc_assert (GET_CODE (x) == CONST_INT);
1625 switch (INTVAL (x))
1626 {
1627 case 1:
1628 fputs (".b", file);
1629 break;
1630
1631 case 2:
1632 fputs (".w", file);
1633 break;
1634
1635 case 4:
1636 fputs (".l", file);
1637 break;
1638
1639 default:
1640 gcc_unreachable ();
1641 }
727c62dd 1642 break;
1643 case 'o':
87ad9aff 1644 h8300_print_operand_address (file, x);
727c62dd 1645 break;
b839e0b4 1646 case 's':
1647 if (GET_CODE (x) == CONST_INT)
21650cc9 1648 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
b839e0b4 1649 else
1650 fprintf (file, "%s", byte_reg (x, 0));
1651 break;
1652 case 't':
1653 if (GET_CODE (x) == CONST_INT)
21650cc9 1654 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
b839e0b4 1655 else
1656 fprintf (file, "%s", byte_reg (x, 1));
1657 break;
b839e0b4 1658 case 'w':
1659 if (GET_CODE (x) == CONST_INT)
21650cc9 1660 fprintf (file, "#%ld", INTVAL (x) & 0xff);
b839e0b4 1661 else
69b4e418 1662 fprintf (file, "%s",
1663 byte_reg (x, TARGET_H8300 ? 2 : 0));
b839e0b4 1664 break;
1665 case 'x':
1666 if (GET_CODE (x) == CONST_INT)
21650cc9 1667 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
b839e0b4 1668 else
69b4e418 1669 fprintf (file, "%s",
1670 byte_reg (x, TARGET_H8300 ? 3 : 1));
b839e0b4 1671 break;
1672 case 'y':
1673 if (GET_CODE (x) == CONST_INT)
21650cc9 1674 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
b839e0b4 1675 else
1676 fprintf (file, "%s", byte_reg (x, 0));
1677 break;
1678 case 'z':
1679 if (GET_CODE (x) == CONST_INT)
21650cc9 1680 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
b839e0b4 1681 else
1682 fprintf (file, "%s", byte_reg (x, 1));
1683 break;
1684
e1629549 1685 default:
b839e0b4 1686 def:
e1629549 1687 switch (GET_CODE (x))
1688 {
1689 case REG:
b839e0b4 1690 switch (GET_MODE (x))
1691 {
1692 case QImode:
30c992ef 1693#if 0 /* Is it asm ("mov.b %0,r2l", ...) */
b839e0b4 1694 fprintf (file, "%s", byte_reg (x, 0));
1695#else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1696 fprintf (file, "%s", names_big[REGNO (x)]);
1697#endif
1698 break;
1699 case HImode:
1700 fprintf (file, "%s", names_big[REGNO (x)]);
1701 break;
1702 case SImode:
5d369cd7 1703 case SFmode:
b839e0b4 1704 fprintf (file, "%s", names_extended[REGNO (x)]);
1705 break;
1706 default:
3afe906b 1707 gcc_unreachable ();
b839e0b4 1708 }
e1629549 1709 break;
1710
1711 case MEM:
b99f3ebb 1712 {
1713 rtx addr = XEXP (x, 0);
1714
1715 fprintf (file, "@");
1716 output_address (addr);
1717
727c62dd 1718 /* Add a length suffix to constant addresses. Although this
1719 is often unnecessary, it helps to avoid ambiguity in the
1720 syntax of mova. If we wrote an insn like:
1721
1722 mova/w.l @(1,@foo.b),er0
1723
1724 then .b would be considered part of the symbol name.
1725 Adding a length after foo will avoid this. */
1726 if (CONSTANT_P (addr))
1727 switch (code)
1728 {
1729 case 'R':
1730 /* Used for mov.b and bit operations. */
1731 if (h8300_eightbit_constant_address_p (addr))
1732 {
1733 fprintf (file, ":8");
1734 break;
1735 }
1736
1737 /* Fall through. We should not get here if we are
1738 processing bit operations on H8/300 or H8/300H
1739 because 'U' constraint does not allow bit
1740 operations on the tiny area on these machines. */
1741
1742 case 'X':
1743 case 'T':
1744 case 'S':
1745 if (h8300_constant_length (addr) == 2)
1746 fprintf (file, ":16");
1747 else
1748 fprintf (file, ":32");
1749 break;
1750 default:
1751 break;
1752 }
b99f3ebb 1753 }
e1629549 1754 break;
1755
1756 case CONST_INT:
1757 case SYMBOL_REF:
1758 case CONST:
1759 case LABEL_REF:
1760 fprintf (file, "#");
87ad9aff 1761 h8300_print_operand_address (file, x);
e1629549 1762 break;
737a5d5b 1763 case CONST_DOUBLE:
1764 {
1765 long val;
1766 REAL_VALUE_TYPE rv;
1767 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1768 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
9305fe33 1769 fprintf (file, "#%ld", val);
737a5d5b 1770 break;
1771 }
9305fe33 1772 default:
1773 break;
e1629549 1774 }
1775 }
1776}
1777
87ad9aff 1778/* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1779
1780static bool
1781h8300_print_operand_punct_valid_p (unsigned char code)
1782{
1783 return (code == '#');
1784}
1785
e1629549 1786/* Output assembly language output for the address ADDR to FILE. */
1787
87ad9aff 1788static void
1789h8300_print_operand_address (FILE *file, rtx addr)
e1629549 1790{
727c62dd 1791 rtx index;
1792 int size;
1793
e1629549 1794 switch (GET_CODE (addr))
1795 {
1796 case REG:
b839e0b4 1797 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
e1629549 1798 break;
1799
1800 case PRE_DEC:
b839e0b4 1801 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
e1629549 1802 break;
1803
1804 case POST_INC:
b839e0b4 1805 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
e1629549 1806 break;
1807
727c62dd 1808 case PRE_INC:
1809 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1810 break;
1811
1812 case POST_DEC:
1813 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
1814 break;
1815
e1629549 1816 case PLUS:
1817 fprintf (file, "(");
727c62dd 1818
1819 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
1820 if (GET_CODE (index) == REG)
e1629549 1821 {
1822 /* reg,foo */
87ad9aff 1823 h8300_print_operand_address (file, XEXP (addr, 1));
e1629549 1824 fprintf (file, ",");
727c62dd 1825 switch (size)
1826 {
1827 case 0:
87ad9aff 1828 h8300_print_operand_address (file, index);
727c62dd 1829 break;
1830
1831 case 1:
87ad9aff 1832 h8300_print_operand (file, index, 'X');
727c62dd 1833 fputs (".b", file);
1834 break;
1835
1836 case 2:
87ad9aff 1837 h8300_print_operand (file, index, 'T');
727c62dd 1838 fputs (".w", file);
1839 break;
1840
1841 case 4:
87ad9aff 1842 h8300_print_operand (file, index, 'S');
727c62dd 1843 fputs (".l", file);
1844 break;
1845 }
87ad9aff 1846 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
e1629549 1847 }
1848 else
1849 {
1850 /* foo+k */
87ad9aff 1851 h8300_print_operand_address (file, XEXP (addr, 0));
e1629549 1852 fprintf (file, "+");
87ad9aff 1853 h8300_print_operand_address (file, XEXP (addr, 1));
e1629549 1854 }
1855 fprintf (file, ")");
1856 break;
1857
1858 case CONST_INT:
b839e0b4 1859 {
03fb0c81 1860 /* Since the H8/300 only has 16-bit pointers, negative values are also
b839e0b4 1861 those >= 32768. This happens for example with pointer minus a
1862 constant. We don't want to turn (char *p - 2) into
1863 (char *p + 65534) because loop unrolling can build upon this
1864 (IE: char *p + 131068). */
1865 int n = INTVAL (addr);
1866 if (TARGET_H8300)
1867 n = (int) (short) n;
90a38175 1868 fprintf (file, "%d", n);
b839e0b4 1869 break;
1870 }
e1629549 1871
1872 default:
1873 output_addr_const (file, addr);
1874 break;
1875 }
1876}
1877\f
e1629549 1878/* Output all insn addresses and their sizes into the assembly language
1879 output file. This is helpful for debugging whether the length attributes
1880 in the md file are correct. This is not meant to be a user selectable
1881 option. */
1882
1883void
1a1ed145 1884final_prescan_insn (rtx_insn *insn, rtx *operand ATTRIBUTE_UNUSED,
230002f2 1885 int num_operands ATTRIBUTE_UNUSED)
e1629549 1886{
1887 /* This holds the last insn address. */
1888 static int last_insn_address = 0;
1889
407921a5 1890 const int uid = INSN_UID (insn);
e1629549 1891
1892 if (TARGET_ADDRESSES)
1893 {
47fc0706 1894 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1895 INSN_ADDRESSES (uid) - last_insn_address);
1896 last_insn_address = INSN_ADDRESSES (uid);
e1629549 1897 }
1898}
1899
b839e0b4 1900/* Prepare for an SI sized move. */
1901
1902int
1564ec41 1903h8300_expand_movsi (rtx operands[])
e1629549 1904{
b839e0b4 1905 rtx src = operands[1];
1906 rtx dst = operands[0];
1907 if (!reload_in_progress && !reload_completed)
1908 {
1909 if (!register_operand (dst, GET_MODE (dst)))
1910 {
1911 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1912 emit_move_insn (tmp, src);
1913 operands[1] = tmp;
1914 }
1915 }
1916 return 0;
1917}
1918
cd90919d 1919/* Given FROM and TO register numbers, say whether this elimination is allowed.
1920 Frame pointer elimination is automatically handled.
1921
1922 For the h8300, if frame pointer elimination is being done, we would like to
1923 convert ap and rp into sp, not fp.
1924
1925 All other eliminations are valid. */
1926
1927static bool
1928h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
1929{
1930 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
1931}
1932
b2d7ede1 1933/* Conditionally modify register usage based on target flags. */
1934
1935static void
1936h8300_conditional_register_usage (void)
1937{
1938 if (!TARGET_MAC)
1939 fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1;
1940}
1941
b839e0b4 1942/* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
eb2aa24e 1943 Define the offset between two registers, one to be eliminated, and
1944 the other its replacement, at the start of a routine. */
e1629549 1945
b839e0b4 1946int
230002f2 1947h8300_initial_elimination_offset (int from, int to)
b839e0b4 1948{
32351c92 1949 /* The number of bytes that the return address takes on the stack. */
1950 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
b839e0b4 1951
f4ac50fb 1952 /* The number of bytes that the saved frame pointer takes on the stack. */
1953 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1954
1955 /* The number of bytes that the saved registers, excluding the frame
1956 pointer, take on the stack. */
1957 int saved_regs_size = 0;
b839e0b4 1958
f4ac50fb 1959 /* The number of bytes that the locals takes on the stack. */
1960 int frame_size = round_frame_size (get_frame_size ());
b839e0b4 1961
f4ac50fb 1962 int regno;
b839e0b4 1963
f4ac50fb 1964 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1965 if (WORD_REG_USED (regno))
1966 saved_regs_size += UNITS_PER_WORD;
b839e0b4 1967
f4ac50fb 1968 /* Adjust saved_regs_size because the above loop took the frame
1969 pointer int account. */
1970 saved_regs_size -= fp_size;
35a462ce 1971
3afe906b 1972 switch (to)
f4ac50fb 1973 {
3afe906b 1974 case HARD_FRAME_POINTER_REGNUM:
f4ac50fb 1975 switch (from)
1976 {
1977 case ARG_POINTER_REGNUM:
1978 return pc_size + fp_size;
1979 case RETURN_ADDRESS_POINTER_REGNUM:
1980 return fp_size;
1981 case FRAME_POINTER_REGNUM:
1982 return -saved_regs_size;
1983 default:
3afe906b 1984 gcc_unreachable ();
f4ac50fb 1985 }
3afe906b 1986 break;
1987 case STACK_POINTER_REGNUM:
f4ac50fb 1988 switch (from)
1989 {
1990 case ARG_POINTER_REGNUM:
1991 return pc_size + saved_regs_size + frame_size;
1992 case RETURN_ADDRESS_POINTER_REGNUM:
1993 return saved_regs_size + frame_size;
1994 case FRAME_POINTER_REGNUM:
1995 return frame_size;
1996 default:
3afe906b 1997 gcc_unreachable ();
f4ac50fb 1998 }
3afe906b 1999 break;
2000 default:
2001 gcc_unreachable ();
f4ac50fb 2002 }
3afe906b 2003 gcc_unreachable ();
b839e0b4 2004}
2005
cdfb02e8 2006/* Worker function for RETURN_ADDR_RTX. */
2007
f643a7d5 2008rtx
230002f2 2009h8300_return_addr_rtx (int count, rtx frame)
f643a7d5 2010{
2011 rtx ret;
2012
2013 if (count == 0)
2014 ret = gen_rtx_MEM (Pmode,
2015 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
2016 else if (flag_omit_frame_pointer)
2017 return (rtx) 0;
2018 else
2019 ret = gen_rtx_MEM (Pmode,
2020 memory_address (Pmode,
29c05e22 2021 plus_constant (Pmode, frame,
2022 UNITS_PER_WORD)));
f643a7d5 2023 set_mem_alias_set (ret, get_frame_alias_set ());
2024 return ret;
2025}
2026
b839e0b4 2027/* Update the condition code from the insn. */
2028
9305fe33 2029void
50fc2d35 2030notice_update_cc (rtx body, rtx_insn *insn)
b839e0b4 2031{
1617b5d2 2032 rtx set;
2033
b839e0b4 2034 switch (get_attr_cc (insn))
2035 {
2036 case CC_NONE:
30c992ef 2037 /* Insn does not affect CC at all. */
b839e0b4 2038 break;
2039
2040 case CC_NONE_0HIT:
30c992ef 2041 /* Insn does not change CC, but the 0'th operand has been changed. */
b839e0b4 2042 if (cc_status.value1 != 0
ed420a25 2043 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
b839e0b4 2044 cc_status.value1 = 0;
ad992f91 2045 if (cc_status.value2 != 0
2046 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
2047 cc_status.value2 = 0;
b839e0b4 2048 break;
2049
a618bce0 2050 case CC_SET_ZN:
ed420a25 2051 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
30c992ef 2052 The V flag is unusable. The C flag may or may not be known but
2053 that's ok because alter_cond will change tests to use EQ/NE. */
b839e0b4 2054 CC_STATUS_INIT;
30c992ef 2055 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1617b5d2 2056 set = single_set (insn);
2057 cc_status.value1 = SET_SRC (set);
2058 if (SET_DEST (set) != cc0_rtx)
2059 cc_status.value2 = SET_DEST (set);
b839e0b4 2060 break;
2061
a618bce0 2062 case CC_SET_ZNV:
ed420a25 2063 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
a618bce0 2064 The C flag may or may not be known but that's ok because
2065 alter_cond will change tests to use EQ/NE. */
2066 CC_STATUS_INIT;
2067 cc_status.flags |= CC_NO_CARRY;
1617b5d2 2068 set = single_set (insn);
2069 cc_status.value1 = SET_SRC (set);
2070 if (SET_DEST (set) != cc0_rtx)
83e2d3b1 2071 {
2072 /* If the destination is STRICT_LOW_PART, strip off
2073 STRICT_LOW_PART. */
2074 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
2075 cc_status.value2 = XEXP (SET_DEST (set), 0);
2076 else
2077 cc_status.value2 = SET_DEST (set);
2078 }
a618bce0 2079 break;
2080
727c62dd 2081 case CC_COMPARE:
2082 /* The insn is a compare instruction. */
2083 CC_STATUS_INIT;
2084 cc_status.value1 = SET_SRC (body);
2085 break;
2086
2087 case CC_CLOBBER:
2088 /* Insn doesn't leave CC in a usable state. */
2089 CC_STATUS_INIT;
2090 break;
2091 }
2092}
727c62dd 2093\f
2094/* Given that X occurs in an address of the form (plus X constant),
2095 return the part of X that is expected to be a register. There are
2096 four kinds of addressing mode to recognize:
2097
2098 @(dd,Rn)
2099 @(dd,RnL.b)
2100 @(dd,Rn.w)
2101 @(dd,ERn.l)
2102
2103 If SIZE is nonnull, and the address is one of the last three forms,
2104 set *SIZE to the index multiplication factor. Set it to 0 for
2105 plain @(dd,Rn) addresses.
2106
2107 MODE is the mode of the value being accessed. It can be VOIDmode
2108 if the address is known to be valid, but its mode is unknown. */
2109
958f5301 2110static rtx
727c62dd 2111h8300_get_index (rtx x, enum machine_mode mode, int *size)
2112{
2113 int dummy, factor;
2114
2115 if (size == 0)
2116 size = &dummy;
2117
2118 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
2119 if (TARGET_H8300SX
2120 && factor <= 4
2121 && (mode == VOIDmode
2122 || GET_MODE_CLASS (mode) == MODE_INT
2123 || GET_MODE_CLASS (mode) == MODE_FLOAT))
2124 {
2125 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
2126 {
2127 /* When accessing byte-sized values, the index can be
2128 a zero-extended QImode or HImode register. */
2129 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
2130 return XEXP (x, 0);
2131 }
2132 else
2133 {
2134 /* We're looking for addresses of the form:
2135
2136 (mult X I)
2137 or (mult (zero_extend X) I)
2138
2139 where I is the size of the operand being accessed.
2140 The canonical form of the second expression is:
2141
2142 (and (mult (subreg X) I) J)
2143
2144 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2145 rtx index;
2146
2147 if (GET_CODE (x) == AND
2148 && GET_CODE (XEXP (x, 1)) == CONST_INT
2149 && (factor == 0
2150 || INTVAL (XEXP (x, 1)) == 0xff * factor
2151 || INTVAL (XEXP (x, 1)) == 0xffff * factor))
2152 {
2153 index = XEXP (x, 0);
2154 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
2155 }
2156 else
2157 {
2158 index = x;
2159 *size = 4;
2160 }
2161
2162 if (GET_CODE (index) == MULT
2163 && GET_CODE (XEXP (index, 1)) == CONST_INT
2164 && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
2165 return XEXP (index, 0);
2166 }
2167 }
2168 *size = 0;
2169 return x;
2170}
2171\f
958f5301 2172/* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2173
2174 On the H8/300, the predecrement and postincrement address depend thus
2175 (the amount of decrement or increment being the length of the operand). */
2176
2177static bool
4e27ffd0 2178h8300_mode_dependent_address_p (const_rtx addr,
2179 addr_space_t as ATTRIBUTE_UNUSED)
958f5301 2180{
2181 if (GET_CODE (addr) == PLUS
2182 && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0))
2183 return true;
2184
2185 return false;
2186}
2187\f
727c62dd 2188static const h8300_length_table addb_length_table =
2189{
2190 /* #xx Rs @aa @Rs @xx */
2191 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2192 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2193 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2194 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2195};
2196
2197static const h8300_length_table addw_length_table =
2198{
2199 /* #xx Rs @aa @Rs @xx */
2200 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2201 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2202 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2203 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2204};
2205
2206static const h8300_length_table addl_length_table =
2207{
2208 /* #xx Rs @aa @Rs @xx */
2209 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2210 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2211 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2212 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2213};
2214
2215#define logicb_length_table addb_length_table
2216#define logicw_length_table addw_length_table
2217
2218static const h8300_length_table logicl_length_table =
2219{
2220 /* #xx Rs @aa @Rs @xx */
2221 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2222 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2223 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2224 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2225};
2226
2227static const h8300_length_table movb_length_table =
2228{
2229 /* #xx Rs @aa @Rs @xx */
2230 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2231 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2232 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2233 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2234};
2235
2236#define movw_length_table movb_length_table
2237
2238static const h8300_length_table movl_length_table =
2239{
2240 /* #xx Rs @aa @Rs @xx */
2241 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2242 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2243 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2244 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2245};
2246
2247/* Return the size of the given address or displacement constant. */
2248
2249static unsigned int
2250h8300_constant_length (rtx constant)
2251{
2252 /* Check for (@d:16,Reg). */
2253 if (GET_CODE (constant) == CONST_INT
2254 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
2255 return 2;
2256
2257 /* Check for (@d:16,Reg) in cases where the displacement is
2258 an absolute address. */
2259 if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
2260 return 2;
2261
2262 return 4;
2263}
2264
2265/* Return the size of a displacement field in address ADDR, which should
2266 have the form (plus X constant). SIZE is the number of bytes being
2267 accessed. */
2268
2269static unsigned int
2270h8300_displacement_length (rtx addr, int size)
2271{
2272 rtx offset;
2273
2274 offset = XEXP (addr, 1);
2275
2276 /* Check for @(d:2,Reg). */
2277 if (register_operand (XEXP (addr, 0), VOIDmode)
2278 && GET_CODE (offset) == CONST_INT
2279 && (INTVAL (offset) == size
2280 || INTVAL (offset) == size * 2
2281 || INTVAL (offset) == size * 3))
2282 return 0;
2283
2284 return h8300_constant_length (offset);
2285}
2286
8deb3959 2287/* Store the class of operand OP in *OPCLASS and return the length of any
2288 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
727c62dd 2289 can be null if only the length is needed. */
2290
2291static unsigned int
8deb3959 2292h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
727c62dd 2293{
2294 enum h8300_operand_class dummy;
2295
8deb3959 2296 if (opclass == 0)
2297 opclass = &dummy;
727c62dd 2298
2299 if (CONSTANT_P (op))
2300 {
8deb3959 2301 *opclass = H8OP_IMMEDIATE;
727c62dd 2302
2303 /* Byte-sized immediates are stored in the opcode fields. */
2304 if (size == 1)
2305 return 0;
2306
2307 /* If this is a 32-bit instruction, see whether the constant
2308 will fit into a 16-bit immediate field. */
2309 if (TARGET_H8300SX
2310 && size == 4
2311 && GET_CODE (op) == CONST_INT
2312 && IN_RANGE (INTVAL (op), 0, 0xffff))
2313 return 2;
2314
2315 return size;
2316 }
2317 else if (GET_CODE (op) == MEM)
2318 {
2319 op = XEXP (op, 0);
2320 if (CONSTANT_P (op))
2321 {
8deb3959 2322 *opclass = H8OP_MEM_ABSOLUTE;
727c62dd 2323 return h8300_constant_length (op);
2324 }
2325 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
2326 {
8deb3959 2327 *opclass = H8OP_MEM_COMPLEX;
727c62dd 2328 return h8300_displacement_length (op, size);
2329 }
2330 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
2331 {
8deb3959 2332 *opclass = H8OP_MEM_COMPLEX;
727c62dd 2333 return 0;
2334 }
2335 else if (register_operand (op, VOIDmode))
2336 {
8deb3959 2337 *opclass = H8OP_MEM_BASE;
727c62dd 2338 return 0;
2339 }
2340 }
3afe906b 2341 gcc_assert (register_operand (op, VOIDmode));
8deb3959 2342 *opclass = H8OP_REGISTER;
3afe906b 2343 return 0;
727c62dd 2344}
2345
2346/* Return the length of the instruction described by TABLE given that
2347 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2348 and OP2 must be an h8300_src_operand. */
2349
2350static unsigned int
2351h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
2352{
2353 enum h8300_operand_class op1_class, op2_class;
2354 unsigned int size, immediate_length;
2355
2356 size = GET_MODE_SIZE (GET_MODE (op1));
2357 immediate_length = (h8300_classify_operand (op1, size, &op1_class)
2358 + h8300_classify_operand (op2, size, &op2_class));
2359 return immediate_length + (*table)[op1_class - 1][op2_class];
2360}
2361
2362/* Return the length of a unary instruction such as neg or not given that
2363 its operand is OP. */
2364
2365unsigned int
2366h8300_unary_length (rtx op)
2367{
8deb3959 2368 enum h8300_operand_class opclass;
727c62dd 2369 unsigned int size, operand_length;
2370
2371 size = GET_MODE_SIZE (GET_MODE (op));
8deb3959 2372 operand_length = h8300_classify_operand (op, size, &opclass);
2373 switch (opclass)
727c62dd 2374 {
2375 case H8OP_REGISTER:
2376 return 2;
2377
2378 case H8OP_MEM_BASE:
2379 return (size == 4 ? 6 : 4);
2380
2381 case H8OP_MEM_ABSOLUTE:
2382 return operand_length + (size == 4 ? 6 : 4);
2383
2384 case H8OP_MEM_COMPLEX:
2385 return operand_length + 6;
2386
2387 default:
3afe906b 2388 gcc_unreachable ();
727c62dd 2389 }
2390}
2391
2392/* Likewise short immediate instructions such as add.w #xx:3,OP. */
2393
2394static unsigned int
2395h8300_short_immediate_length (rtx op)
2396{
8deb3959 2397 enum h8300_operand_class opclass;
727c62dd 2398 unsigned int size, operand_length;
2399
2400 size = GET_MODE_SIZE (GET_MODE (op));
8deb3959 2401 operand_length = h8300_classify_operand (op, size, &opclass);
727c62dd 2402
8deb3959 2403 switch (opclass)
727c62dd 2404 {
2405 case H8OP_REGISTER:
2406 return 2;
2407
2408 case H8OP_MEM_BASE:
2409 case H8OP_MEM_ABSOLUTE:
2410 case H8OP_MEM_COMPLEX:
2411 return 4 + operand_length;
2412
2413 default:
3afe906b 2414 gcc_unreachable ();
727c62dd 2415 }
2416}
2417
2418/* Likewise bitfield load and store instructions. */
b839e0b4 2419
727c62dd 2420static unsigned int
2421h8300_bitfield_length (rtx op, rtx op2)
2422{
8deb3959 2423 enum h8300_operand_class opclass;
727c62dd 2424 unsigned int size, operand_length;
2425
2426 if (GET_CODE (op) == REG)
2427 op = op2;
3afe906b 2428 gcc_assert (GET_CODE (op) != REG);
727c62dd 2429
2430 size = GET_MODE_SIZE (GET_MODE (op));
8deb3959 2431 operand_length = h8300_classify_operand (op, size, &opclass);
727c62dd 2432
8deb3959 2433 switch (opclass)
727c62dd 2434 {
2435 case H8OP_MEM_BASE:
2436 case H8OP_MEM_ABSOLUTE:
2437 case H8OP_MEM_COMPLEX:
2438 return 4 + operand_length;
2439
2440 default:
3afe906b 2441 gcc_unreachable ();
e1629549 2442 }
b839e0b4 2443}
2444
727c62dd 2445/* Calculate the length of general binary instruction INSN using TABLE. */
90e56b83 2446
727c62dd 2447static unsigned int
1a1ed145 2448h8300_binary_length (rtx_insn *insn, const h8300_length_table *table)
90e56b83 2449{
727c62dd 2450 rtx set;
2451
2452 set = single_set (insn);
3afe906b 2453 gcc_assert (set);
727c62dd 2454
2455 if (BINARY_P (SET_SRC (set)))
2456 return h8300_length_from_table (XEXP (SET_SRC (set), 0),
2457 XEXP (SET_SRC (set), 1), table);
727c62dd 2458 else
3afe906b 2459 {
2460 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
2461 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
2462 XEXP (XEXP (SET_SRC (set), 1), 1),
2463 table);
2464 }
90e56b83 2465}
2466
727c62dd 2467/* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2468 memory reference and either (1) it has the form @(d:16,Rn) or
2469 (2) its address has the code given by INC_CODE. */
90e56b83 2470
727c62dd 2471static bool
2472h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
90e56b83 2473{
727c62dd 2474 rtx addr;
2475 unsigned int size;
2476
2477 if (GET_CODE (op) != MEM)
2478 return false;
2479
2480 addr = XEXP (op, 0);
2481 size = GET_MODE_SIZE (GET_MODE (op));
2482 if (size != 1 && size != 2)
2483 return false;
2484
2485 return (GET_CODE (addr) == inc_code
2486 || (GET_CODE (addr) == PLUS
2487 && GET_CODE (XEXP (addr, 0)) == REG
2488 && h8300_displacement_length (addr, size) == 2));
90e56b83 2489}
2490
727c62dd 2491/* Calculate the length of move instruction INSN using the given length
2492 table. Although the tables are correct for most cases, there is some
2493 irregularity in the length of mov.b and mov.w. The following forms:
90e56b83 2494
727c62dd 2495 mov @ERs+, Rd
2496 mov @(d:16,ERs), Rd
2497 mov Rs, @-ERd
2498 mov Rs, @(d:16,ERd)
2499
2500 are two bytes shorter than most other "mov Rs, @complex" or
2501 "mov @complex,Rd" combinations. */
2502
2503static unsigned int
2504h8300_move_length (rtx *operands, const h8300_length_table *table)
90e56b83 2505{
727c62dd 2506 unsigned int size;
2507
2508 size = h8300_length_from_table (operands[0], operands[1], table);
2509 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
2510 size -= 2;
2511 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
2512 size -= 2;
2513 return size;
90e56b83 2514}
2515
727c62dd 2516/* Return the length of a mova instruction with the given operands.
2517 DEST is the register destination, SRC is the source address and
2518 OFFSET is the 16-bit or 32-bit displacement. */
0d565792 2519
727c62dd 2520static unsigned int
2521h8300_mova_length (rtx dest, rtx src, rtx offset)
0d565792 2522{
727c62dd 2523 unsigned int size;
2524
2525 size = (2
2526 + h8300_constant_length (offset)
2527 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
2528 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
2529 size += 2;
2530 return size;
0d565792 2531}
2532
727c62dd 2533/* Compute the length of INSN based on its length_table attribute.
2534 OPERANDS is the array of its operands. */
0d565792 2535
727c62dd 2536unsigned int
1a1ed145 2537h8300_insn_length_from_table (rtx_insn *insn, rtx * operands)
0d565792 2538{
727c62dd 2539 switch (get_attr_length_table (insn))
2540 {
2541 case LENGTH_TABLE_NONE:
3afe906b 2542 gcc_unreachable ();
727c62dd 2543
2544 case LENGTH_TABLE_ADDB:
2545 return h8300_binary_length (insn, &addb_length_table);
2546
2547 case LENGTH_TABLE_ADDW:
2548 return h8300_binary_length (insn, &addw_length_table);
2549
2550 case LENGTH_TABLE_ADDL:
2551 return h8300_binary_length (insn, &addl_length_table);
2552
2553 case LENGTH_TABLE_LOGICB:
2554 return h8300_binary_length (insn, &logicb_length_table);
2555
2556 case LENGTH_TABLE_MOVB:
2557 return h8300_move_length (operands, &movb_length_table);
2558
2559 case LENGTH_TABLE_MOVW:
2560 return h8300_move_length (operands, &movw_length_table);
2561
2562 case LENGTH_TABLE_MOVL:
2563 return h8300_move_length (operands, &movl_length_table);
2564
2565 case LENGTH_TABLE_MOVA:
2566 return h8300_mova_length (operands[0], operands[1], operands[2]);
2567
2568 case LENGTH_TABLE_MOVA_ZERO:
2569 return h8300_mova_length (operands[0], operands[1], const0_rtx);
2570
2571 case LENGTH_TABLE_UNARY:
2572 return h8300_unary_length (operands[0]);
2573
2574 case LENGTH_TABLE_MOV_IMM4:
2575 return 2 + h8300_classify_operand (operands[0], 0, 0);
2576
2577 case LENGTH_TABLE_SHORT_IMMEDIATE:
2578 return h8300_short_immediate_length (operands[0]);
2579
2580 case LENGTH_TABLE_BITFIELD:
2581 return h8300_bitfield_length (operands[0], operands[1]);
2582
2583 case LENGTH_TABLE_BITBRANCH:
2584 return h8300_bitfield_length (operands[1], operands[2]) - 2;
3afe906b 2585
2586 default:
2587 gcc_unreachable ();
727c62dd 2588 }
0d565792 2589}
2590
727c62dd 2591/* Return true if LHS and RHS are memory references that can be mapped
2592 to the same h8sx assembly operand. LHS appears as the destination of
2593 an instruction and RHS appears as a source.
079b5951 2594
727c62dd 2595 Three cases are allowed:
2596
2597 - RHS is @+Rn or @-Rn, LHS is @Rn
2598 - RHS is @Rn, LHS is @Rn+ or @Rn-
2599 - RHS and LHS have the same address and neither has side effects. */
2600
2601bool
2602h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
079b5951 2603{
727c62dd 2604 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
2605 {
2606 rhs = XEXP (rhs, 0);
2607 lhs = XEXP (lhs, 0);
2608
2609 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
2610 return rtx_equal_p (XEXP (rhs, 0), lhs);
2611
2612 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
2613 return rtx_equal_p (rhs, XEXP (lhs, 0));
2614
2615 if (rtx_equal_p (rhs, lhs))
2616 return true;
2617 }
2618 return false;
079b5951 2619}
2620
727c62dd 2621/* Return true if OPERANDS[1] can be mapped to the same assembly
2622 operand as OPERANDS[0]. */
079b5951 2623
727c62dd 2624bool
2625h8300_operands_match_p (rtx *operands)
079b5951 2626{
727c62dd 2627 if (register_operand (operands[0], VOIDmode)
2628 && register_operand (operands[1], VOIDmode))
2629 return true;
079b5951 2630
727c62dd 2631 if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
2632 return true;
2633
2634 return false;
079b5951 2635}
727c62dd 2636\f
2637/* Try using movmd to move LENGTH bytes from memory region SRC to memory
2638 region DEST. The two regions do not overlap and have the common
2639 alignment given by ALIGNMENT. Return true on success.
c6720edd 2640
727c62dd 2641 Using movmd for variable-length moves seems to involve some
2642 complex trade-offs. For instance:
4c924258 2643
727c62dd 2644 - Preparing for a movmd instruction is similar to preparing
2645 for a memcpy. The main difference is that the arguments
2646 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2647
2648 - Since movmd clobbers the frame pointer, we need to save
2649 and restore it somehow when frame_pointer_needed. This can
2650 sometimes make movmd sequences longer than calls to memcpy().
2651
2652 - The counter register is 16 bits, so the instruction is only
2653 suitable for variable-length moves when sizeof (size_t) == 2.
2654 That's only true in normal mode.
2655
2656 - We will often lack static alignment information. Falling back
2657 on movmd.b would likely be slower than calling memcpy(), at least
2658 for big moves.
2659
2660 This function therefore only uses movmd when the length is a
2661 known constant, and only then if -fomit-frame-pointer is in
2662 effect or if we're not optimizing for size.
2663
2664 At the moment the function uses movmd for all in-range constants,
2665 but it might be better to fall back on memcpy() for large moves
2666 if ALIGNMENT == 1. */
2667
2668bool
2669h8sx_emit_movmd (rtx dest, rtx src, rtx length,
2670 HOST_WIDE_INT alignment)
4c924258 2671{
727c62dd 2672 if (!flag_omit_frame_pointer && optimize_size)
2673 return false;
4c924258 2674
727c62dd 2675 if (GET_CODE (length) == CONST_INT)
2676 {
2677 rtx dest_reg, src_reg, first_dest, first_src;
2678 HOST_WIDE_INT n;
2679 int factor;
2680
2681 /* Use movmd.l if the alignment allows it, otherwise fall back
2682 on movmd.b. */
2683 factor = (alignment >= 2 ? 4 : 1);
2684
2685 /* Make sure the length is within range. We can handle counter
2686 values up to 65536, although HImode truncation will make
2687 the count appear negative in rtl dumps. */
2688 n = INTVAL (length);
2689 if (n <= 0 || n / factor > 65536)
2690 return false;
2691
2692 /* Create temporary registers for the source and destination
2693 pointers. Initialize them to the start of each region. */
2694 dest_reg = copy_addr_to_reg (XEXP (dest, 0));
2695 src_reg = copy_addr_to_reg (XEXP (src, 0));
2696
2697 /* Create references to the movmd source and destination blocks. */
2698 first_dest = replace_equiv_address (dest, dest_reg);
2699 first_src = replace_equiv_address (src, src_reg);
2700
5b2a69fa 2701 set_mem_size (first_dest, n & -factor);
2702 set_mem_size (first_src, n & -factor);
727c62dd 2703
2704 length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode));
2705 emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor)));
2706
2707 if ((n & -factor) != n)
2708 {
2709 /* Move SRC and DEST past the region we just copied.
2710 This is done to update the memory attributes. */
2711 dest = adjust_address (dest, BLKmode, n & -factor);
2712 src = adjust_address (src, BLKmode, n & -factor);
2713
2714 /* Replace the addresses with the source and destination
2715 registers, which movmd has left with the right values. */
2716 dest = replace_equiv_address (dest, dest_reg);
2717 src = replace_equiv_address (src, src_reg);
2718
2719 /* Mop up the left-over bytes. */
2720 if (n & 2)
2721 emit_move_insn (adjust_address (dest, HImode, 0),
2722 adjust_address (src, HImode, 0));
2723 if (n & 1)
2724 emit_move_insn (adjust_address (dest, QImode, n & 2),
2725 adjust_address (src, QImode, n & 2));
2726 }
2727 return true;
2728 }
2729 return false;
4c924258 2730}
2731
727c62dd 2732/* Move ADDR into er6 after pushing its old value onto the stack. */
b839e0b4 2733
727c62dd 2734void
2735h8300_swap_into_er6 (rtx addr)
b839e0b4 2736{
a5c6cfdd 2737 rtx insn = push (HARD_FRAME_POINTER_REGNUM);
2738 if (frame_pointer_needed)
2739 add_reg_note (insn, REG_CFA_DEF_CFA,
29c05e22 2740 plus_constant (Pmode, gen_rtx_MEM (Pmode, stack_pointer_rtx),
a5c6cfdd 2741 2 * UNITS_PER_WORD));
2742 else
2743 add_reg_note (insn, REG_CFA_ADJUST_CFA,
2744 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
29c05e22 2745 plus_constant (Pmode, stack_pointer_rtx, 4)));
a5c6cfdd 2746
727c62dd 2747 emit_move_insn (hard_frame_pointer_rtx, addr);
2748 if (REGNO (addr) == SP_REG)
2749 emit_move_insn (hard_frame_pointer_rtx,
29c05e22 2750 plus_constant (Pmode, hard_frame_pointer_rtx,
727c62dd 2751 GET_MODE_SIZE (word_mode)));
2752}
e1629549 2753
727c62dd 2754/* Move the current value of er6 into ADDR and pop its old value
2755 from the stack. */
2756
2757void
2758h8300_swap_out_of_er6 (rtx addr)
2759{
a5c6cfdd 2760 rtx insn;
2761
727c62dd 2762 if (REGNO (addr) != SP_REG)
2763 emit_move_insn (addr, hard_frame_pointer_rtx);
a5c6cfdd 2764
2765 insn = pop (HARD_FRAME_POINTER_REGNUM);
2766 RTX_FRAME_RELATED_P (insn) = 1;
2767 if (frame_pointer_needed)
2768 add_reg_note (insn, REG_CFA_DEF_CFA,
29c05e22 2769 plus_constant (Pmode, hard_frame_pointer_rtx,
2770 2 * UNITS_PER_WORD));
a5c6cfdd 2771 else
2772 add_reg_note (insn, REG_CFA_ADJUST_CFA,
2773 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
29c05e22 2774 plus_constant (Pmode, stack_pointer_rtx, -4)));
e1629549 2775}
b839e0b4 2776\f
2e295ea4 2777/* Return the length of mov instruction. */
2778
2779unsigned int
2780compute_mov_length (rtx *operands)
2781{
2782 /* If the mov instruction involves a memory operand, we compute the
2783 length, assuming the largest addressing mode is used, and then
2784 adjust later in the function. Otherwise, we compute and return
2785 the exact length in one step. */
2786 enum machine_mode mode = GET_MODE (operands[0]);
2787 rtx dest = operands[0];
2788 rtx src = operands[1];
2789 rtx addr;
2790
2791 if (GET_CODE (src) == MEM)
2792 addr = XEXP (src, 0);
2793 else if (GET_CODE (dest) == MEM)
2794 addr = XEXP (dest, 0);
2795 else
2796 addr = NULL_RTX;
2797
2798 if (TARGET_H8300)
2799 {
2800 unsigned int base_length;
2801
2802 switch (mode)
2803 {
2804 case QImode:
2805 if (addr == NULL_RTX)
2806 return 2;
2807
2808 /* The eightbit addressing is available only in QImode, so
2809 go ahead and take care of it. */
2810 if (h8300_eightbit_constant_address_p (addr))
2811 return 2;
2812
2813 base_length = 4;
2814 break;
2815
2816 case HImode:
2817 if (addr == NULL_RTX)
2818 {
2819 if (REG_P (src))
2820 return 2;
2821
2822 if (src == const0_rtx)
2823 return 2;
2824
2825 return 4;
2826 }
2827
2828 base_length = 4;
2829 break;
2830
2831 case SImode:
2832 if (addr == NULL_RTX)
2833 {
2834 if (REG_P (src))
2835 return 4;
2836
2837 if (GET_CODE (src) == CONST_INT)
2838 {
2839 if (src == const0_rtx)
2840 return 4;
2841
2842 if ((INTVAL (src) & 0xffff) == 0)
2843 return 6;
2844
2845 if ((INTVAL (src) & 0xffff) == 0)
2846 return 6;
786637e0 2847
2848 if ((INTVAL (src) & 0xffff)
2849 == ((INTVAL (src) >> 16) & 0xffff))
2850 return 6;
2e295ea4 2851 }
2852 return 8;
2853 }
2854
2855 base_length = 8;
2856 break;
2857
2858 case SFmode:
2859 if (addr == NULL_RTX)
2860 {
2861 if (REG_P (src))
2862 return 4;
2863
424f5954 2864 if (satisfies_constraint_G (src))
f62378f4 2865 return 4;
2866
ead5f19f 2867 return 8;
2e295ea4 2868 }
2869
2870 base_length = 8;
2871 break;
2872
2873 default:
3afe906b 2874 gcc_unreachable ();
2e295ea4 2875 }
2876
2877 /* Adjust the length based on the addressing mode used.
2878 Specifically, we subtract the difference between the actual
2879 length and the longest one, which is @(d:16,Rs). For SImode
2880 and SFmode, we double the adjustment because two mov.w are
2881 used to do the job. */
2882
2883 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2884 if (GET_CODE (addr) == PRE_DEC
2885 || GET_CODE (addr) == POST_INC)
2886 {
2887 if (mode == QImode || mode == HImode)
2888 return base_length - 2;
2889 else
2890 /* In SImode and SFmode, we use two mov.w instructions, so
3c364971 2891 double the adjustment. */
2e295ea4 2892 return base_length - 4;
2893 }
2894
2895 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2896 in SImode and SFmode, the second mov.w involves an address
2897 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2898 only 2 bytes. */
2899 if (GET_CODE (addr) == REG)
2900 return base_length - 2;
2901
2902 return base_length;
2903 }
2904 else
2905 {
2906 unsigned int base_length;
2907
2908 switch (mode)
2909 {
2910 case QImode:
2911 if (addr == NULL_RTX)
2912 return 2;
2913
2914 /* The eightbit addressing is available only in QImode, so
2915 go ahead and take care of it. */
2916 if (h8300_eightbit_constant_address_p (addr))
2917 return 2;
2918
2919 base_length = 8;
2920 break;
2921
2922 case HImode:
2923 if (addr == NULL_RTX)
2924 {
2925 if (REG_P (src))
2926 return 2;
2927
2928 if (src == const0_rtx)
2929 return 2;
2930
2931 return 4;
2932 }
2933
2934 base_length = 8;
2935 break;
2936
2937 case SImode:
2938 if (addr == NULL_RTX)
2939 {
2940 if (REG_P (src))
2941 {
2942 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2943 return 4;
2944 else
2945 return 2;
2946 }
2947
2948 if (GET_CODE (src) == CONST_INT)
2949 {
2950 int val = INTVAL (src);
2951
2952 if (val == 0)
2953 return 2;
2954
2955 if (val == (val & 0x00ff) || val == (val & 0xff00))
2956 return 4;
6fe6e17a 2957
2e295ea4 2958 switch (val & 0xffffffff)
2959 {
2960 case 0xffffffff:
2961 case 0xfffffffe:
2962 case 0xfffffffc:
2963 case 0x0000ffff:
2964 case 0x0000fffe:
2965 case 0xffff0000:
2966 case 0xfffe0000:
2967 case 0x00010000:
2968 case 0x00020000:
2969 return 4;
2970 }
2971 }
2972 return 6;
2973 }
2974
2975 base_length = 10;
2976 break;
2977
2978 case SFmode:
2979 if (addr == NULL_RTX)
2980 {
2981 if (REG_P (src))
2982 return 2;
2983
424f5954 2984 if (satisfies_constraint_G (src))
2e295ea4 2985 return 2;
f62378f4 2986
2e295ea4 2987 return 6;
2988 }
2989
2990 base_length = 10;
2991 break;
2992
2993 default:
3afe906b 2994 gcc_unreachable ();
2e295ea4 2995 }
2996
2997 /* Adjust the length based on the addressing mode used.
2998 Specifically, we subtract the difference between the actual
2999 length and the longest one, which is @(d:24,ERs). */
3000
3001 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
3002 if (GET_CODE (addr) == PRE_DEC
3003 || GET_CODE (addr) == POST_INC)
3004 return base_length - 6;
3005
3006 /* @ERs and @ERd are 6 bytes shorter than the longest. */
3007 if (GET_CODE (addr) == REG)
3008 return base_length - 6;
3009
3010 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
3011 longest. */
3012 if (GET_CODE (addr) == PLUS
3013 && GET_CODE (XEXP (addr, 0)) == REG
3014 && GET_CODE (XEXP (addr, 1)) == CONST_INT
3015 && INTVAL (XEXP (addr, 1)) > -32768
3016 && INTVAL (XEXP (addr, 1)) < 32767)
3017 return base_length - 4;
3018
3019 /* @aa:16 is 4 bytes shorter than the longest. */
3020 if (h8300_tiny_constant_address_p (addr))
3021 return base_length - 4;
3022
3023 /* @aa:24 is 2 bytes shorter than the longest. */
3024 if (CONSTANT_P (addr))
3025 return base_length - 2;
3026
3027 return base_length;
3028 }
3029}
3030\f
cdfb02e8 3031/* Output an addition insn. */
3032
6a8a3fa3 3033const char *
230002f2 3034output_plussi (rtx *operands)
aa3382b1 3035{
3036 enum machine_mode mode = GET_MODE (operands[0]);
3037
3afe906b 3038 gcc_assert (mode == SImode);
aa3382b1 3039
3040 if (TARGET_H8300)
3041 {
469dc9d2 3042 if (GET_CODE (operands[2]) == REG)
3043 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3044
3045 if (GET_CODE (operands[2]) == CONST_INT)
3046 {
3047 HOST_WIDE_INT n = INTVAL (operands[2]);
3048
3049 if ((n & 0xffffff) == 0)
3050 return "add\t%z2,%z0";
3051 if ((n & 0xffff) == 0)
3052 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
3053 if ((n & 0xff) == 0)
3054 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3055 }
3056
3057 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
aa3382b1 3058 }
3059 else
3060 {
727c62dd 3061 if (GET_CODE (operands[2]) == CONST_INT
3062 && register_operand (operands[1], VOIDmode))
aa3382b1 3063 {
3064 HOST_WIDE_INT intval = INTVAL (operands[2]);
3065
727c62dd 3066 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3067 return "add.l\t%S2,%S0";
3068 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3069 return "sub.l\t%G2,%S0";
3070
aa3382b1 3071 /* See if we can finish with 2 bytes. */
3072
11233c59 3073 switch ((unsigned int) intval & 0xffffffff)
aa3382b1 3074 {
3075 case 0x00000001:
3076 case 0x00000002:
3077 case 0x00000004:
3078 return "adds\t%2,%S0";
3079
3080 case 0xffffffff:
3081 case 0xfffffffe:
3082 case 0xfffffffc:
3083 return "subs\t%G2,%S0";
3084
3085 case 0x00010000:
3086 case 0x00020000:
3087 operands[2] = GEN_INT (intval >> 16);
3088 return "inc.w\t%2,%e0";
3089
3090 case 0xffff0000:
3091 case 0xfffe0000:
3092 operands[2] = GEN_INT (intval >> 16);
3093 return "dec.w\t%G2,%e0";
3094 }
3095
3096 /* See if we can finish with 4 bytes. */
3097 if ((intval & 0xffff) == 0)
3098 {
3099 operands[2] = GEN_INT (intval >> 16);
3100 return "add.w\t%2,%e0";
3101 }
3102 }
3103
727c62dd 3104 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3105 {
3106 operands[2] = GEN_INT (-INTVAL (operands[2]));
3107 return "sub.l\t%S2,%S0";
3108 }
aa3382b1 3109 return "add.l\t%S2,%S0";
3110 }
3111}
3112
727c62dd 3113/* ??? It would be much easier to add the h8sx stuff if a single function
3114 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
cdfb02e8 3115/* Compute the length of an addition insn. */
3116
aa3382b1 3117unsigned int
230002f2 3118compute_plussi_length (rtx *operands)
aa3382b1 3119{
3120 enum machine_mode mode = GET_MODE (operands[0]);
3121
3afe906b 3122 gcc_assert (mode == SImode);
aa3382b1 3123
3124 if (TARGET_H8300)
3125 {
469dc9d2 3126 if (GET_CODE (operands[2]) == REG)
3127 return 6;
3128
3129 if (GET_CODE (operands[2]) == CONST_INT)
3130 {
3131 HOST_WIDE_INT n = INTVAL (operands[2]);
3132
3133 if ((n & 0xffffff) == 0)
3134 return 2;
3135 if ((n & 0xffff) == 0)
3136 return 4;
3137 if ((n & 0xff) == 0)
3138 return 6;
3139 }
3140
3141 return 8;
aa3382b1 3142 }
3143 else
3144 {
727c62dd 3145 if (GET_CODE (operands[2]) == CONST_INT
3146 && register_operand (operands[1], VOIDmode))
aa3382b1 3147 {
3148 HOST_WIDE_INT intval = INTVAL (operands[2]);
3149
727c62dd 3150 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3151 return 2;
3152 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3153 return 2;
3154
aa3382b1 3155 /* See if we can finish with 2 bytes. */
3156
11233c59 3157 switch ((unsigned int) intval & 0xffffffff)
aa3382b1 3158 {
3159 case 0x00000001:
3160 case 0x00000002:
3161 case 0x00000004:
3162 return 2;
3163
3164 case 0xffffffff:
3165 case 0xfffffffe:
3166 case 0xfffffffc:
3167 return 2;
3168
3169 case 0x00010000:
3170 case 0x00020000:
3171 return 2;
3172
3173 case 0xffff0000:
3174 case 0xfffe0000:
3175 return 2;
3176 }
3177
3178 /* See if we can finish with 4 bytes. */
3179 if ((intval & 0xffff) == 0)
3180 return 4;
3181 }
3182
727c62dd 3183 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3184 return h8300_length_from_table (operands[0],
3185 GEN_INT (-INTVAL (operands[2])),
3186 &addl_length_table);
3187 else
3188 return h8300_length_from_table (operands[0], operands[2],
3189 &addl_length_table);
aa3382b1 3190 return 6;
3191 }
3192}
3193
cdfb02e8 3194/* Compute which flag bits are valid after an addition insn. */
3195
539b539f 3196enum attr_cc
230002f2 3197compute_plussi_cc (rtx *operands)
aa3382b1 3198{
3199 enum machine_mode mode = GET_MODE (operands[0]);
3200
3afe906b 3201 gcc_assert (mode == SImode);
aa3382b1 3202
3203 if (TARGET_H8300)
3204 {
469dc9d2 3205 return CC_CLOBBER;
aa3382b1 3206 }
3207 else
3208 {
727c62dd 3209 if (GET_CODE (operands[2]) == CONST_INT
3210 && register_operand (operands[1], VOIDmode))
aa3382b1 3211 {
3212 HOST_WIDE_INT intval = INTVAL (operands[2]);
3213
727c62dd 3214 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3215 return CC_SET_ZN;
3216 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3217 return CC_SET_ZN;
3218
aa3382b1 3219 /* See if we can finish with 2 bytes. */
3220
11233c59 3221 switch ((unsigned int) intval & 0xffffffff)
aa3382b1 3222 {
3223 case 0x00000001:
3224 case 0x00000002:
3225 case 0x00000004:
3226 return CC_NONE_0HIT;
3227
3228 case 0xffffffff:
3229 case 0xfffffffe:
3230 case 0xfffffffc:
3231 return CC_NONE_0HIT;
3232
3233 case 0x00010000:
3234 case 0x00020000:
3235 return CC_CLOBBER;
3236
3237 case 0xffff0000:
3238 case 0xfffe0000:
3239 return CC_CLOBBER;
3240 }
3241
3242 /* See if we can finish with 4 bytes. */
3243 if ((intval & 0xffff) == 0)
3244 return CC_CLOBBER;
3245 }
3246
3247 return CC_SET_ZN;
3248 }
3249}
3250\f
cdfb02e8 3251/* Output a logical insn. */
3252
aa3382b1 3253const char *
230002f2 3254output_logical_op (enum machine_mode mode, rtx *operands)
6a8a3fa3 3255{
6ad7df02 3256 /* Figure out the logical op that we need to perform. */
3257 enum rtx_code code = GET_CODE (operands[3]);
6a8a3fa3 3258 /* Pretend that every byte is affected if both operands are registers. */
407921a5 3259 const unsigned HOST_WIDE_INT intval =
6a8a3fa3 3260 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
727c62dd 3261 /* Always use the full instruction if the
3262 first operand is in memory. It is better
3263 to use define_splits to generate the shorter
3264 sequence where valid. */
3265 && register_operand (operands[1], VOIDmode)
6a8a3fa3 3266 ? INTVAL (operands[2]) : 0x55555555);
3267 /* The determinant of the algorithm. If we perform an AND, 0
3268 affects a bit. Otherwise, 1 affects a bit. */
407921a5 3269 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
e6cf6c71 3270 /* Break up DET into pieces. */
3271 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3272 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
cdcf26ff 3273 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3274 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
e6cf6c71 3275 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3276 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3277 int lower_half_easy_p = 0;
3278 int upper_half_easy_p = 0;
6a8a3fa3 3279 /* The name of an insn. */
3280 const char *opname;
3281 char insn_buf[100];
3282
3283 switch (code)
3284 {
3285 case AND:
3286 opname = "and";
3287 break;
3288 case IOR:
3289 opname = "or";
3290 break;
3291 case XOR:
3292 opname = "xor";
3293 break;
3294 default:
3afe906b 3295 gcc_unreachable ();
6a8a3fa3 3296 }
3297
3298 switch (mode)
3299 {
3300 case HImode:
3301 /* First, see if we can finish with one insn. */
3302 if ((TARGET_H8300H || TARGET_H8300S)
cdcf26ff 3303 && b0 != 0
3304 && b1 != 0)
6a8a3fa3 3305 {
3306 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
3307 output_asm_insn (insn_buf, operands);
3308 }
3309 else
3310 {
3311 /* Take care of the lower byte. */
cdcf26ff 3312 if (b0 != 0)
6a8a3fa3 3313 {
3314 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
3315 output_asm_insn (insn_buf, operands);
3316 }
3317 /* Take care of the upper byte. */
cdcf26ff 3318 if (b1 != 0)
6a8a3fa3 3319 {
3320 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
3321 output_asm_insn (insn_buf, operands);
3322 }
3323 }
3324 break;
3325 case SImode:
e6cf6c71 3326 if (TARGET_H8300H || TARGET_H8300S)
3327 {
3328 /* Determine if the lower half can be taken care of in no more
3329 than two bytes. */
3330 lower_half_easy_p = (b0 == 0
3331 || b1 == 0
3332 || (code != IOR && w0 == 0xffff));
3333
3334 /* Determine if the upper half can be taken care of in no more
3335 than two bytes. */
3336 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3337 || (code == AND && w1 == 0xff00));
3338 }
6a8a3fa3 3339
e6cf6c71 3340 /* Check if doing everything with one insn is no worse than
3341 using multiple insns. */
6a8a3fa3 3342 if ((TARGET_H8300H || TARGET_H8300S)
e6cf6c71 3343 && w0 != 0 && w1 != 0
0372ccb5 3344 && !(lower_half_easy_p && upper_half_easy_p)
3345 && !(code == IOR && w1 == 0xffff
3346 && (w0 & 0x8000) != 0 && lower_half_easy_p))
6a8a3fa3 3347 {
3348 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
3349 output_asm_insn (insn_buf, operands);
3350 }
3351 else
3352 {
3353 /* Take care of the lower and upper words individually. For
3354 each word, we try different methods in the order of
3355
3356 1) the special insn (in case of AND or XOR),
3357 2) the word-wise insn, and
3358 3) The byte-wise insn. */
cdcf26ff 3359 if (w0 == 0xffff
a9d986d9 3360 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
6a8a3fa3 3361 output_asm_insn ((code == AND)
b0422000 3362 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
6a8a3fa3 3363 operands);
3364 else if ((TARGET_H8300H || TARGET_H8300S)
cdcf26ff 3365 && (b0 != 0)
3366 && (b1 != 0))
6a8a3fa3 3367 {
3368 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
3369 output_asm_insn (insn_buf, operands);
3370 }
3371 else
3372 {
cdcf26ff 3373 if (b0 != 0)
6a8a3fa3 3374 {
3375 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
3376 output_asm_insn (insn_buf, operands);
3377 }
cdcf26ff 3378 if (b1 != 0)
6a8a3fa3 3379 {
3380 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
3381 output_asm_insn (insn_buf, operands);
3382 }
3383 }
3384
cdcf26ff 3385 if ((w1 == 0xffff)
a9d986d9 3386 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
6a8a3fa3 3387 output_asm_insn ((code == AND)
b0422000 3388 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
6a8a3fa3 3389 operands);
0372ccb5 3390 else if ((TARGET_H8300H || TARGET_H8300S)
3391 && code == IOR
3392 && w1 == 0xffff
3393 && (w0 & 0x8000) != 0)
3394 {
3395 output_asm_insn ("exts.l\t%S0", operands);
3396 }
f4bdef90 3397 else if ((TARGET_H8300H || TARGET_H8300S)
3398 && code == AND
cdcf26ff 3399 && w1 == 0xff00)
f4bdef90 3400 {
1c75fadf 3401 output_asm_insn ("extu.w\t%e0", operands);
f4bdef90 3402 }
6a8a3fa3 3403 else if (TARGET_H8300H || TARGET_H8300S)
3404 {
cdcf26ff 3405 if (w1 != 0)
6a8a3fa3 3406 {
3407 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
3408 output_asm_insn (insn_buf, operands);
3409 }
3410 }
3411 else
3412 {
cdcf26ff 3413 if (b2 != 0)
6a8a3fa3 3414 {
3415 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
3416 output_asm_insn (insn_buf, operands);
3417 }
cdcf26ff 3418 if (b3 != 0)
6a8a3fa3 3419 {
3420 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
3421 output_asm_insn (insn_buf, operands);
3422 }
3423 }
3424 }
3425 break;
3426 default:
3afe906b 3427 gcc_unreachable ();
6a8a3fa3 3428 }
3429 return "";
3430}
359e4f59 3431
cdfb02e8 3432/* Compute the length of a logical insn. */
3433
359e4f59 3434unsigned int
230002f2 3435compute_logical_op_length (enum machine_mode mode, rtx *operands)
359e4f59 3436{
6ad7df02 3437 /* Figure out the logical op that we need to perform. */
3438 enum rtx_code code = GET_CODE (operands[3]);
359e4f59 3439 /* Pretend that every byte is affected if both operands are registers. */
407921a5 3440 const unsigned HOST_WIDE_INT intval =
359e4f59 3441 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
727c62dd 3442 /* Always use the full instruction if the
3443 first operand is in memory. It is better
3444 to use define_splits to generate the shorter
3445 sequence where valid. */
3446 && register_operand (operands[1], VOIDmode)
359e4f59 3447 ? INTVAL (operands[2]) : 0x55555555);
3448 /* The determinant of the algorithm. If we perform an AND, 0
3449 affects a bit. Otherwise, 1 affects a bit. */
407921a5 3450 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
e6cf6c71 3451 /* Break up DET into pieces. */
3452 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3453 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
cdcf26ff 3454 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3455 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
e6cf6c71 3456 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3457 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3458 int lower_half_easy_p = 0;
3459 int upper_half_easy_p = 0;
359e4f59 3460 /* Insn length. */
3461 unsigned int length = 0;
3462
3463 switch (mode)
3464 {
3465 case HImode:
3466 /* First, see if we can finish with one insn. */
3467 if ((TARGET_H8300H || TARGET_H8300S)
cdcf26ff 3468 && b0 != 0
3469 && b1 != 0)
359e4f59 3470 {
727c62dd 3471 length = h8300_length_from_table (operands[1], operands[2],
3472 &logicw_length_table);
359e4f59 3473 }
3474 else
3475 {
3476 /* Take care of the lower byte. */
cdcf26ff 3477 if (b0 != 0)
359e4f59 3478 length += 2;
3479
3480 /* Take care of the upper byte. */
cdcf26ff 3481 if (b1 != 0)
359e4f59 3482 length += 2;
3483 }
3484 break;
3485 case SImode:
e6cf6c71 3486 if (TARGET_H8300H || TARGET_H8300S)
3487 {
3488 /* Determine if the lower half can be taken care of in no more
3489 than two bytes. */
3490 lower_half_easy_p = (b0 == 0
3491 || b1 == 0
3492 || (code != IOR && w0 == 0xffff));
3493
3494 /* Determine if the upper half can be taken care of in no more
3495 than two bytes. */
3496 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3497 || (code == AND && w1 == 0xff00));
3498 }
359e4f59 3499
e6cf6c71 3500 /* Check if doing everything with one insn is no worse than
3501 using multiple insns. */
359e4f59 3502 if ((TARGET_H8300H || TARGET_H8300S)
e6cf6c71 3503 && w0 != 0 && w1 != 0
0372ccb5 3504 && !(lower_half_easy_p && upper_half_easy_p)
3505 && !(code == IOR && w1 == 0xffff
3506 && (w0 & 0x8000) != 0 && lower_half_easy_p))
359e4f59 3507 {
727c62dd 3508 length = h8300_length_from_table (operands[1], operands[2],
3509 &logicl_length_table);
359e4f59 3510 }
3511 else
3512 {
3513 /* Take care of the lower and upper words individually. For
3514 each word, we try different methods in the order of
3515
3516 1) the special insn (in case of AND or XOR),
3517 2) the word-wise insn, and
3518 3) The byte-wise insn. */
cdcf26ff 3519 if (w0 == 0xffff
359e4f59 3520 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3521 {
3522 length += 2;
3523 }
3524 else if ((TARGET_H8300H || TARGET_H8300S)
cdcf26ff 3525 && (b0 != 0)
3526 && (b1 != 0))
359e4f59 3527 {
3528 length += 4;
3529 }
3530 else
3531 {
cdcf26ff 3532 if (b0 != 0)
359e4f59 3533 length += 2;
3534
cdcf26ff 3535 if (b1 != 0)
359e4f59 3536 length += 2;
3537 }
3538
cdcf26ff 3539 if (w1 == 0xffff
359e4f59 3540 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3541 {
3542 length += 2;
3543 }
0372ccb5 3544 else if ((TARGET_H8300H || TARGET_H8300S)
3545 && code == IOR
3546 && w1 == 0xffff
3547 && (w0 & 0x8000) != 0)
3548 {
3549 length += 2;
3550 }
f4bdef90 3551 else if ((TARGET_H8300H || TARGET_H8300S)
3552 && code == AND
cdcf26ff 3553 && w1 == 0xff00)
f4bdef90 3554 {
3555 length += 2;
3556 }
359e4f59 3557 else if (TARGET_H8300H || TARGET_H8300S)
3558 {
cdcf26ff 3559 if (w1 != 0)
359e4f59 3560 length += 4;
3561 }
3562 else
3563 {
cdcf26ff 3564 if (b2 != 0)
359e4f59 3565 length += 2;
3566
cdcf26ff 3567 if (b3 != 0)
359e4f59 3568 length += 2;
3569 }
3570 }
3571 break;
3572 default:
3afe906b 3573 gcc_unreachable ();
359e4f59 3574 }
3575 return length;
3576}
6ad7df02 3577
cdfb02e8 3578/* Compute which flag bits are valid after a logical insn. */
3579
539b539f 3580enum attr_cc
230002f2 3581compute_logical_op_cc (enum machine_mode mode, rtx *operands)
6ad7df02 3582{
3583 /* Figure out the logical op that we need to perform. */
3584 enum rtx_code code = GET_CODE (operands[3]);
3585 /* Pretend that every byte is affected if both operands are registers. */
407921a5 3586 const unsigned HOST_WIDE_INT intval =
6ad7df02 3587 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
727c62dd 3588 /* Always use the full instruction if the
3589 first operand is in memory. It is better
3590 to use define_splits to generate the shorter
3591 sequence where valid. */
3592 && register_operand (operands[1], VOIDmode)
6ad7df02 3593 ? INTVAL (operands[2]) : 0x55555555);
3594 /* The determinant of the algorithm. If we perform an AND, 0
3595 affects a bit. Otherwise, 1 affects a bit. */
407921a5 3596 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
e6cf6c71 3597 /* Break up DET into pieces. */
3598 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3599 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3600 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3601 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3602 int lower_half_easy_p = 0;
3603 int upper_half_easy_p = 0;
6ad7df02 3604 /* Condition code. */
3605 enum attr_cc cc = CC_CLOBBER;
3606
3607 switch (mode)
3608 {
3609 case HImode:
3610 /* First, see if we can finish with one insn. */
3611 if ((TARGET_H8300H || TARGET_H8300S)
cdcf26ff 3612 && b0 != 0
3613 && b1 != 0)
6ad7df02 3614 {
3615 cc = CC_SET_ZNV;
3616 }
3617 break;
3618 case SImode:
e6cf6c71 3619 if (TARGET_H8300H || TARGET_H8300S)
3620 {
3621 /* Determine if the lower half can be taken care of in no more
3622 than two bytes. */
3623 lower_half_easy_p = (b0 == 0
3624 || b1 == 0
3625 || (code != IOR && w0 == 0xffff));
3626
3627 /* Determine if the upper half can be taken care of in no more
3628 than two bytes. */
3629 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3630 || (code == AND && w1 == 0xff00));
3631 }
6ad7df02 3632
e6cf6c71 3633 /* Check if doing everything with one insn is no worse than
3634 using multiple insns. */
6ad7df02 3635 if ((TARGET_H8300H || TARGET_H8300S)
e6cf6c71 3636 && w0 != 0 && w1 != 0
0372ccb5 3637 && !(lower_half_easy_p && upper_half_easy_p)
3638 && !(code == IOR && w1 == 0xffff
3639 && (w0 & 0x8000) != 0 && lower_half_easy_p))
6ad7df02 3640 {
3641 cc = CC_SET_ZNV;
3642 }
0372ccb5 3643 else
3644 {
3645 if ((TARGET_H8300H || TARGET_H8300S)
3646 && code == IOR
3647 && w1 == 0xffff
3648 && (w0 & 0x8000) != 0)
3649 {
3650 cc = CC_SET_ZNV;
3651 }
3652 }
6ad7df02 3653 break;
3654 default:
3afe906b 3655 gcc_unreachable ();
6ad7df02 3656 }
3657 return cc;
3658}
6a8a3fa3 3659\f
ab5a13fd 3660/* Expand a conditional branch. */
3661
3662void
74f4459c 3663h8300_expand_branch (rtx operands[])
ab5a13fd 3664{
74f4459c 3665 enum rtx_code code = GET_CODE (operands[0]);
3666 rtx op0 = operands[1];
3667 rtx op1 = operands[2];
3668 rtx label = operands[3];
ab5a13fd 3669 rtx tmp;
3670
74f4459c 3671 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3672 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3673
ab5a13fd 3674 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
3675 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
3676 gen_rtx_LABEL_REF (VOIDmode, label),
3677 pc_rtx);
3678 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
3679}
74f4459c 3680
3681
3682/* Expand a conditional store. */
3683
3684void
3685h8300_expand_store (rtx operands[])
3686{
3687 rtx dest = operands[0];
3688 enum rtx_code code = GET_CODE (operands[1]);
3689 rtx op0 = operands[2];
3690 rtx op1 = operands[3];
3691 rtx tmp;
3692
3693 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3694 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3695
3696 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx);
3697 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
3698}
ab5a13fd 3699\f
b839e0b4 3700/* Shifts.
3701
f465f633 3702 We devote a fair bit of code to getting efficient shifts since we
3703 can only shift one bit at a time on the H8/300 and H8/300H and only
11f95d7c 3704 one or two bits at a time on the H8S.
f465f633 3705
3706 All shift code falls into one of the following ways of
3707 implementation:
3708
3709 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3710 when a straight line shift is about the same size or smaller than
3711 a loop.
3712
3713 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3714 off the bits we don't need. This is used when only a few of the
3715 bits in the original value will survive in the shifted value.
3716
3717 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3718 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3719 shifts can be added if the shift count is slightly more than 8 or
3720 16. This case also includes other oddballs that are not worth
cc72e60a 3721 explaining here.
f465f633 3722
11f95d7c 3723 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
f465f633 3724
140ee624 3725 For each shift count, we try to use code that has no trade-off
3726 between code size and speed whenever possible.
3727
3728 If the trade-off is unavoidable, we try to be reasonable.
3729 Specifically, the fastest version is one instruction longer than
3730 the shortest version, we take the fastest version. We also provide
3731 the use a way to switch back to the shortest version with -Os.
3732
3733 For the details of the shift algorithms for various shift counts,
3734 refer to shift_alg_[qhs]i. */
e1629549 3735
727c62dd 3736/* Classify a shift with the given mode and code. OP is the shift amount. */
3737
3738enum h8sx_shift_type
3739h8sx_classify_shift (enum machine_mode mode, enum rtx_code code, rtx op)
3740{
3741 if (!TARGET_H8300SX)
3742 return H8SX_SHIFT_NONE;
3743
3744 switch (code)
3745 {
3746 case ASHIFT:
3747 case LSHIFTRT:
3748 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3749 if (GET_CODE (op) != CONST_INT)
3750 return H8SX_SHIFT_BINARY;
3751
3752 /* Reject out-of-range shift amounts. */
3753 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
3754 return H8SX_SHIFT_NONE;
3755
3756 /* Power-of-2 shifts are effectively unary operations. */
3757 if (exact_log2 (INTVAL (op)) >= 0)
3758 return H8SX_SHIFT_UNARY;
3759
3760 return H8SX_SHIFT_BINARY;
3761
3762 case ASHIFTRT:
3763 if (op == const1_rtx || op == const2_rtx)
3764 return H8SX_SHIFT_UNARY;
3765 return H8SX_SHIFT_NONE;
3766
3767 case ROTATE:
3768 if (GET_CODE (op) == CONST_INT
3769 && (INTVAL (op) == 1
3770 || INTVAL (op) == 2
3771 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
3772 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
3773 return H8SX_SHIFT_UNARY;
3774 return H8SX_SHIFT_NONE;
3775
3776 default:
3777 return H8SX_SHIFT_NONE;
3778 }
3779}
3780
727c62dd 3781/* Return the asm template for a single h8sx shift instruction.
3782 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3783 is the source and OPERANDS[3] is the shift. SUFFIX is the
87ad9aff 3784 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
727c62dd 3785 prefix for the destination operand. */
3786
3787const char *
3788output_h8sx_shift (rtx *operands, int suffix, int optype)
3789{
3790 static char buffer[16];
3791 const char *stem;
3792
3793 switch (GET_CODE (operands[3]))
3794 {
3795 case ASHIFT:
3796 stem = "shll";
3797 break;
3798
3799 case ASHIFTRT:
3800 stem = "shar";
3801 break;
3802
3803 case LSHIFTRT:
3804 stem = "shlr";
3805 break;
3806
3807 case ROTATE:
3808 stem = "rotl";
3809 if (INTVAL (operands[2]) > 2)
3810 {
3811 /* This is really a right rotate. */
3812 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
3813 - INTVAL (operands[2]));
3814 stem = "rotr";
3815 }
3816 break;
3817
3818 default:
3afe906b 3819 gcc_unreachable ();
727c62dd 3820 }
3821 if (operands[2] == const1_rtx)
3822 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
3823 else
3824 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
3825 return buffer;
3826}
b839e0b4 3827
6b07073d 3828/* Emit code to do shifts. */
b839e0b4 3829
727c62dd 3830bool
539b539f 3831expand_a_shift (enum machine_mode mode, enum rtx_code code, rtx operands[])
e1629549 3832{
727c62dd 3833 switch (h8sx_classify_shift (mode, code, operands[2]))
3834 {
3835 case H8SX_SHIFT_BINARY:
3836 operands[1] = force_reg (mode, operands[1]);
3837 return false;
3838
3839 case H8SX_SHIFT_UNARY:
3840 return false;
3841
3842 case H8SX_SHIFT_NONE:
3843 break;
3844 }
3845
d3652418 3846 emit_move_insn (copy_rtx (operands[0]), operands[1]);
e1629549 3847
eb2aa24e 3848 /* Need a loop to get all the bits we want - we generate the
3849 code at emit time, but need to allocate a scratch reg now. */
b839e0b4 3850
7014838c 3851 emit_insn (gen_rtx_PARALLEL
3852 (VOIDmode,
b839e0b4 3853 gen_rtvec (2,
d3652418 3854 gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
dc55b8a9 3855 gen_rtx_fmt_ee (code, mode,
d3652418 3856 copy_rtx (operands[0]), operands[2])),
7014838c 3857 gen_rtx_CLOBBER (VOIDmode,
3858 gen_rtx_SCRATCH (QImode)))));
727c62dd 3859 return true;
b839e0b4 3860}
3861
b839e0b4 3862/* Symbols of the various modes which can be used as indices. */
3863
3864enum shift_mode
27276a3b 3865{
3866 QIshift, HIshift, SIshift
3867};
b839e0b4 3868
30c992ef 3869/* For single bit shift insns, record assembler and what bits of the
3870 condition code are valid afterwards (represented as various CC_FOO
3871 bits, 0 means CC isn't left in a usable state). */
b839e0b4 3872
3873struct shift_insn
3874{
e99c3a1d 3875 const char *const assembler;
539b539f 3876 const enum attr_cc cc_valid;
b839e0b4 3877};
3878
3879/* Assembler instruction shift table.
3880
3881 These tables are used to look up the basic shifts.
eb2aa24e 3882 They are indexed by cpu, shift_type, and mode. */
e1629549 3883
b839e0b4 3884static const struct shift_insn shift_one[2][3][3] =
3885{
3886/* H8/300 */
3887 {
3888/* SHIFT_ASHIFT */
3889 {
fd7729c5 3890 { "shll\t%X0", CC_SET_ZNV },
3891 { "add.w\t%T0,%T0", CC_SET_ZN },
3892 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
b839e0b4 3893 },
3894/* SHIFT_LSHIFTRT */
3895 {
fd7729c5 3896 { "shlr\t%X0", CC_SET_ZNV },
3897 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3898 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
b839e0b4 3899 },
3900/* SHIFT_ASHIFTRT */
3901 {
fd7729c5 3902 { "shar\t%X0", CC_SET_ZNV },
3903 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3904 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
b839e0b4 3905 }
3906 },
3907/* H8/300H */
3908 {
3909/* SHIFT_ASHIFT */
3910 {
fd7729c5 3911 { "shll.b\t%X0", CC_SET_ZNV },
3912 { "shll.w\t%T0", CC_SET_ZNV },
3913 { "shll.l\t%S0", CC_SET_ZNV }
b839e0b4 3914 },
3915/* SHIFT_LSHIFTRT */
3916 {
fd7729c5 3917 { "shlr.b\t%X0", CC_SET_ZNV },
3918 { "shlr.w\t%T0", CC_SET_ZNV },
3919 { "shlr.l\t%S0", CC_SET_ZNV }
b839e0b4 3920 },
3921/* SHIFT_ASHIFTRT */
3922 {
fd7729c5 3923 { "shar.b\t%X0", CC_SET_ZNV },
3924 { "shar.w\t%T0", CC_SET_ZNV },
3925 { "shar.l\t%S0", CC_SET_ZNV }
b839e0b4 3926 }
3927 }
3928};
e1629549 3929
52abe980 3930static const struct shift_insn shift_two[3][3] =
3931{
3932/* SHIFT_ASHIFT */
3933 {
fd7729c5 3934 { "shll.b\t#2,%X0", CC_SET_ZNV },
3935 { "shll.w\t#2,%T0", CC_SET_ZNV },
3936 { "shll.l\t#2,%S0", CC_SET_ZNV }
52abe980 3937 },
3938/* SHIFT_LSHIFTRT */
3939 {
fd7729c5 3940 { "shlr.b\t#2,%X0", CC_SET_ZNV },
3941 { "shlr.w\t#2,%T0", CC_SET_ZNV },
3942 { "shlr.l\t#2,%S0", CC_SET_ZNV }
52abe980 3943 },
3944/* SHIFT_ASHIFTRT */
3945 {
fd7729c5 3946 { "shar.b\t#2,%X0", CC_SET_ZNV },
3947 { "shar.w\t#2,%T0", CC_SET_ZNV },
3948 { "shar.l\t#2,%S0", CC_SET_ZNV }
52abe980 3949 }
3950};
3951
b839e0b4 3952/* Rotates are organized by which shift they'll be used in implementing.
3953 There's no need to record whether the cc is valid afterwards because
3954 it is the AND insn that will decide this. */
e1629549 3955
b839e0b4 3956static const char *const rotate_one[2][3][3] =
3957{
3958/* H8/300 */
3959 {
3960/* SHIFT_ASHIFT */
3961 {
52abe980 3962 "rotr\t%X0",
3963 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
b839e0b4 3964 0
3965 },
3966/* SHIFT_LSHIFTRT */
3967 {
52abe980 3968 "rotl\t%X0",
3969 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
b839e0b4 3970 0
3971 },
3972/* SHIFT_ASHIFTRT */
3973 {
52abe980 3974 "rotl\t%X0",
3975 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
b839e0b4 3976 0
e1629549 3977 }
b839e0b4 3978 },
3979/* H8/300H */
3980 {
3981/* SHIFT_ASHIFT */
3982 {
52abe980 3983 "rotr.b\t%X0",
3984 "rotr.w\t%T0",
3985 "rotr.l\t%S0"
b839e0b4 3986 },
3987/* SHIFT_LSHIFTRT */
e1629549 3988 {
52abe980 3989 "rotl.b\t%X0",
3990 "rotl.w\t%T0",
3991 "rotl.l\t%S0"
b839e0b4 3992 },
3993/* SHIFT_ASHIFTRT */
3994 {
52abe980 3995 "rotl.b\t%X0",
3996 "rotl.w\t%T0",
3997 "rotl.l\t%S0"
b839e0b4 3998 }
3999 }
4000};
4001
52abe980 4002static const char *const rotate_two[3][3] =
4003{
4004/* SHIFT_ASHIFT */
4005 {
4006 "rotr.b\t#2,%X0",
4007 "rotr.w\t#2,%T0",
4008 "rotr.l\t#2,%S0"
4009 },
4010/* SHIFT_LSHIFTRT */
4011 {
4012 "rotl.b\t#2,%X0",
4013 "rotl.w\t#2,%T0",
4014 "rotl.l\t#2,%S0"
4015 },
4016/* SHIFT_ASHIFTRT */
4017 {
4018 "rotl.b\t#2,%X0",
4019 "rotl.w\t#2,%T0",
4020 "rotl.l\t#2,%S0"
4021 }
4022};
4023
4765dbab 4024struct shift_info {
4025 /* Shift algorithm. */
4026 enum shift_alg alg;
4027
4028 /* The number of bits to be shifted by shift1 and shift2. Valid
4029 when ALG is SHIFT_SPECIAL. */
4030 unsigned int remainder;
4031
4032 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
4033 const char *special;
4034
4035 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
c46dc351 4036 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4765dbab 4037 const char *shift1;
4038
4039 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
c46dc351 4040 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4765dbab 4041 const char *shift2;
4042
fd7729c5 4043 /* CC status for SHIFT_INLINE. */
539b539f 4044 enum attr_cc cc_inline;
fd7729c5 4045
4046 /* CC status for SHIFT_SPECIAL. */
539b539f 4047 enum attr_cc cc_special;
4765dbab 4048};
4049
230002f2 4050static void get_shift_alg (enum shift_type,
4051 enum shift_mode, unsigned int,
4052 struct shift_info *);
9305fe33 4053
ec0b80c6 4054/* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
4055 best algorithm for doing the shift. The assembler code is stored
140ee624 4056 in the pointers in INFO. We achieve the maximum efficiency in most
4057 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
4058 SImode in particular have a lot of room to optimize.
4059
4060 We first determine the strategy of the shift algorithm by a table
4061 lookup. If that tells us to use a hand crafted assembly code, we
4062 go into the big switch statement to find what that is. Otherwise,
4063 we resort to a generic way, such as inlining. In either case, the
4064 result is returned through INFO. */
b839e0b4 4065
5a40b38e 4066static void
230002f2 4067get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
4068 unsigned int count, struct shift_info *info)
b839e0b4 4069{
5d822c00 4070 enum h8_cpu cpu;
58285553 4071
4072 /* Find the target CPU. */
4073 if (TARGET_H8300)
5d822c00 4074 cpu = H8_300;
58285553 4075 else if (TARGET_H8300H)
5d822c00 4076 cpu = H8_300H;
58285553 4077 else
5d822c00 4078 cpu = H8_S;
58285553 4079
ce8940f6 4080 /* Find the shift algorithm. */
5d822c00 4081 info->alg = SHIFT_LOOP;
b839e0b4 4082 switch (shift_mode)
4083 {
4084 case QIshift:
5d822c00 4085 if (count < GET_MODE_BITSIZE (QImode))
ce8940f6 4086 info->alg = shift_alg_qi[cpu][shift_type][count];
4087 break;
58285553 4088
ce8940f6 4089 case HIshift:
5d822c00 4090 if (count < GET_MODE_BITSIZE (HImode))
ce8940f6 4091 info->alg = shift_alg_hi[cpu][shift_type][count];
4092 break;
4093
4094 case SIshift:
5d822c00 4095 if (count < GET_MODE_BITSIZE (SImode))
ce8940f6 4096 info->alg = shift_alg_si[cpu][shift_type][count];
4097 break;
4098
4099 default:
3afe906b 4100 gcc_unreachable ();
ce8940f6 4101 }
4102
4103 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4104 switch (info->alg)
4105 {
4106 case SHIFT_INLINE:
4107 info->remainder = count;
4108 /* Fall through. */
4109
4110 case SHIFT_LOOP:
4111 /* It is up to the caller to know that looping clobbers cc. */
4112 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4113 info->shift2 = shift_two[shift_type][shift_mode].assembler;
fd7729c5 4114 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
ce8940f6 4115 goto end;
4116
4117 case SHIFT_ROT_AND:
4118 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
4119 info->shift2 = rotate_two[shift_type][shift_mode];
fd7729c5 4120 info->cc_inline = CC_CLOBBER;
ce8940f6 4121 goto end;
4122
4123 case SHIFT_SPECIAL:
4124 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4125 info->remainder = 0;
4126 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4127 info->shift2 = shift_two[shift_type][shift_mode].assembler;
fd7729c5 4128 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4129 info->cc_special = CC_CLOBBER;
ce8940f6 4130 break;
4131 }
52abe980 4132
ce8940f6 4133 /* Here we only deal with SHIFT_SPECIAL. */
4134 switch (shift_mode)
4135 {
4136 case QIshift:
58285553 4137 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4138 through the entire value. */
3afe906b 4139 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
4140 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
4141 goto end;
58285553 4142
4143 case HIshift:
58285553 4144 if (count == 7)
52abe980 4145 {
79b29436 4146 switch (shift_type)
52abe980 4147 {
79b29436 4148 case SHIFT_ASHIFT:
4149 if (TARGET_H8300)
4150 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4151 else
4152 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
606a6902 4153 goto end;
79b29436 4154 case SHIFT_LSHIFTRT:
4155 if (TARGET_H8300)
4156 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4157 else
4158 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
606a6902 4159 goto end;
79b29436 4160 case SHIFT_ASHIFTRT:
4765dbab 4161 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
606a6902 4162 goto end;
b839e0b4 4163 }
e1629549 4164 }
a033fe93 4165 else if ((8 <= count && count <= 13)
8796f52f 4166 || (TARGET_H8300S && count == 14))
e1629549 4167 {
8db8f925 4168 info->remainder = count - 8;
4169
52abe980 4170 switch (shift_type)
b839e0b4 4171 {
52abe980 4172 case SHIFT_ASHIFT:
4765dbab 4173 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
606a6902 4174 goto end;
52abe980 4175 case SHIFT_LSHIFTRT:
903ae79d 4176 if (TARGET_H8300)
4177 {
4178 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4179 info->shift1 = "shlr.b\t%s0";
fd7729c5 4180 info->cc_inline = CC_SET_ZNV;
903ae79d 4181 }
4182 else
4183 {
4184 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
fd7729c5 4185 info->cc_special = CC_SET_ZNV;
903ae79d 4186 }
606a6902 4187 goto end;
52abe980 4188 case SHIFT_ASHIFTRT:
4189 if (TARGET_H8300)
903ae79d 4190 {
4191 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4192 info->shift1 = "shar.b\t%s0";
903ae79d 4193 }
52abe980 4194 else
903ae79d 4195 {
4196 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
fd7729c5 4197 info->cc_special = CC_SET_ZNV;
903ae79d 4198 }
606a6902 4199 goto end;
52abe980 4200 }
4201 }
a0bbe9df 4202 else if (count == 14)
4203 {
4204 switch (shift_type)
4205 {
4206 case SHIFT_ASHIFT:
4207 if (TARGET_H8300)
4208 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4209 goto end;
4210 case SHIFT_LSHIFTRT:
4211 if (TARGET_H8300)
4212 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4213 goto end;
4214 case SHIFT_ASHIFTRT:
4215 if (TARGET_H8300)
4216 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4217 else if (TARGET_H8300H)
fd7729c5 4218 {
4219 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4220 info->cc_special = CC_SET_ZNV;
4221 }
a0bbe9df 4222 else /* TARGET_H8300S */
3afe906b 4223 gcc_unreachable ();
a0bbe9df 4224 goto end;
4225 }
4226 }
f76e2664 4227 else if (count == 15)
52abe980 4228 {
f76e2664 4229 switch (shift_type)
4230 {
4231 case SHIFT_ASHIFT:
4232 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4233 goto end;
4234 case SHIFT_LSHIFTRT:
4235 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4236 goto end;
4237 case SHIFT_ASHIFTRT:
4238 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4239 goto end;
4240 }
e1629549 4241 }
3afe906b 4242 gcc_unreachable ();
52abe980 4243
b839e0b4 4244 case SIshift:
f76e2664 4245 if (TARGET_H8300 && 8 <= count && count <= 9)
b839e0b4 4246 {
f76e2664 4247 info->remainder = count - 8;
4248
52abe980 4249 switch (shift_type)
b839e0b4 4250 {
52abe980 4251 case SHIFT_ASHIFT:
4765dbab 4252 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
606a6902 4253 goto end;
52abe980 4254 case SHIFT_LSHIFTRT:
4765dbab 4255 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
f76e2664 4256 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
606a6902 4257 goto end;
52abe980 4258 case SHIFT_ASHIFTRT:
4765dbab 4259 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
606a6902 4260 goto end;
b839e0b4 4261 }
b839e0b4 4262 }
9bbc06f2 4263 else if (count == 8 && !TARGET_H8300)
4264 {
4265 switch (shift_type)
4266 {
4267 case SHIFT_ASHIFT:
4765dbab 4268 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
606a6902 4269 goto end;
9bbc06f2 4270 case SHIFT_LSHIFTRT:
4765dbab 4271 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
606a6902 4272 goto end;
9bbc06f2 4273 case SHIFT_ASHIFTRT:
4765dbab 4274 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
606a6902 4275 goto end;
9bbc06f2 4276 }
4277 }
f76e2664 4278 else if (count == 15 && TARGET_H8300)
4279 {
4280 switch (shift_type)
4281 {
4282 case SHIFT_ASHIFT:
3afe906b 4283 gcc_unreachable ();
f76e2664 4284 case SHIFT_LSHIFTRT:
a6f6d86d 4285 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
f76e2664 4286 goto end;
4287 case SHIFT_ASHIFTRT:
a6f6d86d 4288 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
f76e2664 4289 goto end;
4290 }
4291 }
37e1f65a 4292 else if (count == 15 && !TARGET_H8300)
4293 {
4294 switch (shift_type)
4295 {
4296 case SHIFT_ASHIFT:
4297 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
fd7729c5 4298 info->cc_special = CC_SET_ZNV;
37e1f65a 4299 goto end;
4300 case SHIFT_LSHIFTRT:
d2079f6d 4301 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
fd7729c5 4302 info->cc_special = CC_SET_ZNV;
37e1f65a 4303 goto end;
7913b5f4 4304 case SHIFT_ASHIFTRT:
3afe906b 4305 gcc_unreachable ();
37e1f65a 4306 }
4307 }
f76e2664 4308 else if ((TARGET_H8300 && 16 <= count && count <= 20)
8db8f925 4309 || (TARGET_H8300H && 16 <= count && count <= 19)
776e0da8 4310 || (TARGET_H8300S && 16 <= count && count <= 21))
b839e0b4 4311 {
8db8f925 4312 info->remainder = count - 16;
4313
b839e0b4 4314 switch (shift_type)
4315 {
4316 case SHIFT_ASHIFT:
4765dbab 4317 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
f76e2664 4318 if (TARGET_H8300)
a033fe93 4319 info->shift1 = "add.w\t%e0,%e0";
606a6902 4320 goto end;
52abe980 4321 case SHIFT_LSHIFTRT:
f76e2664 4322 if (TARGET_H8300)
4323 {
903ae79d 4324 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4325 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
f76e2664 4326 }
4327 else
4328 {
903ae79d 4329 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
fd7729c5 4330 info->cc_special = CC_SET_ZNV;
f76e2664 4331 }
606a6902 4332 goto end;
52abe980 4333 case SHIFT_ASHIFTRT:
4334 if (TARGET_H8300)
f76e2664 4335 {
4336 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4337 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
4338 }
52abe980 4339 else
f76e2664 4340 {
4341 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
fd7729c5 4342 info->cc_special = CC_SET_ZNV;
f76e2664 4343 }
606a6902 4344 goto end;
52abe980 4345 }
4346 }
f76e2664 4347 else if (TARGET_H8300 && 24 <= count && count <= 28)
81c3eb11 4348 {
4349 info->remainder = count - 24;
f2702e8a 4350
81c3eb11 4351 switch (shift_type)
4352 {
4353 case SHIFT_ASHIFT:
4354 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4355 info->shift1 = "shll.b\t%z0";
fd7729c5 4356 info->cc_inline = CC_SET_ZNV;
81c3eb11 4357 goto end;
4358 case SHIFT_LSHIFTRT:
4359 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4360 info->shift1 = "shlr.b\t%w0";
fd7729c5 4361 info->cc_inline = CC_SET_ZNV;
81c3eb11 4362 goto end;
4363 case SHIFT_ASHIFTRT:
4364 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
4365 info->shift1 = "shar.b\t%w0";
fd7729c5 4366 info->cc_inline = CC_SET_ZNV;
b44470aa 4367 goto end;
4368 }
4369 }
0d219270 4370 else if ((TARGET_H8300H && count == 24)
4371 || (TARGET_H8300S && 24 <= count && count <= 25))
9bbc06f2 4372 {
0d219270 4373 info->remainder = count - 24;
4374
9bbc06f2 4375 switch (shift_type)
4376 {
4377 case SHIFT_ASHIFT:
4765dbab 4378 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
606a6902 4379 goto end;
9bbc06f2 4380 case SHIFT_LSHIFTRT:
4765dbab 4381 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
fd7729c5 4382 info->cc_special = CC_SET_ZNV;
606a6902 4383 goto end;
9bbc06f2 4384 case SHIFT_ASHIFTRT:
4765dbab 4385 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
fd7729c5 4386 info->cc_special = CC_SET_ZNV;
606a6902 4387 goto end;
9bbc06f2 4388 }
4389 }
567c4b66 4390 else if (!TARGET_H8300 && count == 28)
4391 {
4392 switch (shift_type)
4393 {
4394 case SHIFT_ASHIFT:
4395 if (TARGET_H8300H)
4396 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4397 else
4398 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
567c4b66 4399 goto end;
4400 case SHIFT_LSHIFTRT:
4401 if (TARGET_H8300H)
fd7729c5 4402 {
4403 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4404 info->cc_special = CC_SET_ZNV;
4405 }
567c4b66 4406 else
903ae79d 4407 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
567c4b66 4408 goto end;
4409 case SHIFT_ASHIFTRT:
3afe906b 4410 gcc_unreachable ();
567c4b66 4411 }
4412 }
4413 else if (!TARGET_H8300 && count == 29)
4414 {
4415 switch (shift_type)
4416 {
4417 case SHIFT_ASHIFT:
4418 if (TARGET_H8300H)
4419 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4420 else
4421 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
567c4b66 4422 goto end;
4423 case SHIFT_LSHIFTRT:
4424 if (TARGET_H8300H)
fd7729c5 4425 {
4426 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4427 info->cc_special = CC_SET_ZNV;
4428 }
567c4b66 4429 else
fd7729c5 4430 {
4431 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4432 info->cc_special = CC_SET_ZNV;
4433 }
567c4b66 4434 goto end;
4435 case SHIFT_ASHIFTRT:
3afe906b 4436 gcc_unreachable ();
567c4b66 4437 }
4438 }
4439 else if (!TARGET_H8300 && count == 30)
4440 {
4441 switch (shift_type)
4442 {
4443 case SHIFT_ASHIFT:
4444 if (TARGET_H8300H)
4445 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4446 else
4447 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
567c4b66 4448 goto end;
4449 case SHIFT_LSHIFTRT:
4450 if (TARGET_H8300H)
903ae79d 4451 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
567c4b66 4452 else
903ae79d 4453 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
567c4b66 4454 goto end;
4455 case SHIFT_ASHIFTRT:
3afe906b 4456 gcc_unreachable ();
567c4b66 4457 }
4458 }
b839e0b4 4459 else if (count == 31)
4460 {
37e1f65a 4461 if (TARGET_H8300)
b839e0b4 4462 {
37e1f65a 4463 switch (shift_type)
4464 {
4465 case SHIFT_ASHIFT:
4466 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4467 goto end;
4468 case SHIFT_LSHIFTRT:
4469 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4470 goto end;
4471 case SHIFT_ASHIFTRT:
4472 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4473 goto end;
4474 }
b839e0b4 4475 }
4476 else
4477 {
37e1f65a 4478 switch (shift_type)
b839e0b4 4479 {
37e1f65a 4480 case SHIFT_ASHIFT:
4481 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
fd7729c5 4482 info->cc_special = CC_SET_ZNV;
37e1f65a 4483 goto end;
4484 case SHIFT_LSHIFTRT:
4485 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
fd7729c5 4486 info->cc_special = CC_SET_ZNV;
37e1f65a 4487 goto end;
4488 case SHIFT_ASHIFTRT:
903ae79d 4489 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
fd7729c5 4490 info->cc_special = CC_SET_ZNV;
606a6902 4491 goto end;
b839e0b4 4492 }
b839e0b4 4493 }
4494 }
3afe906b 4495 gcc_unreachable ();
52abe980 4496
b839e0b4 4497 default:
3afe906b 4498 gcc_unreachable ();
e1629549 4499 }
b839e0b4 4500
5a40b38e 4501 end:
4502 if (!TARGET_H8300S)
4503 info->shift2 = NULL;
e1629549 4504}
4505
6b30b2e6 4506/* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4507 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4508
4509int
230002f2 4510h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
6b30b2e6 4511{
5d822c00 4512 enum h8_cpu cpu;
6b30b2e6 4513 int a, lr, ar;
4514
4515 if (GET_MODE_BITSIZE (mode) <= count)
4516 return 1;
4517
4518 /* Find out the target CPU. */
4519 if (TARGET_H8300)
5d822c00 4520 cpu = H8_300;
6b30b2e6 4521 else if (TARGET_H8300H)
5d822c00 4522 cpu = H8_300H;
6b30b2e6 4523 else
5d822c00 4524 cpu = H8_S;
6b30b2e6 4525
4526 /* Find the shift algorithm. */
4527 switch (mode)
4528 {
4529 case QImode:
4530 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
4531 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
4532 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
4533 break;
4534
4535 case HImode:
4536 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
4537 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
4538 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
4539 break;
4540
4541 case SImode:
4542 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
4543 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
4544 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
4545 break;
4546
4547 default:
3afe906b 4548 gcc_unreachable ();
6b30b2e6 4549 }
4550
33a9c2d6 4551 /* On H8/300H, count == 8 uses a scratch register. */
6b30b2e6 4552 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
c6ff55c2 4553 || (TARGET_H8300H && mode == SImode && count == 8));
6b30b2e6 4554}
4555
cdfb02e8 4556/* Output the assembler code for doing shifts. */
b839e0b4 4557
9305fe33 4558const char *
230002f2 4559output_a_shift (rtx *operands)
e1629549 4560{
b839e0b4 4561 static int loopend_lab;
b839e0b4 4562 rtx shift = operands[3];
4563 enum machine_mode mode = GET_MODE (shift);
4564 enum rtx_code code = GET_CODE (shift);
4565 enum shift_type shift_type;
4566 enum shift_mode shift_mode;
4765dbab 4567 struct shift_info info;
3afe906b 4568 int n;
b839e0b4 4569
4570 loopend_lab++;
4571
4572 switch (mode)
4573 {
4574 case QImode:
4575 shift_mode = QIshift;
4576 break;
4577 case HImode:
4578 shift_mode = HIshift;
4579 break;
4580 case SImode:
4581 shift_mode = SIshift;
4582 break;
4583 default:
3afe906b 4584 gcc_unreachable ();
b839e0b4 4585 }
e1629549 4586
b839e0b4 4587 switch (code)
e1629549 4588 {
b839e0b4 4589 case ASHIFTRT:
4590 shift_type = SHIFT_ASHIFTRT;
4591 break;
4592 case LSHIFTRT:
4593 shift_type = SHIFT_LSHIFTRT;
4594 break;
4595 case ASHIFT:
4596 shift_type = SHIFT_ASHIFT;
4597 break;
4598 default:
3afe906b 4599 gcc_unreachable ();
b839e0b4 4600 }
e1629549 4601
3afe906b 4602 /* This case must be taken care of by one of the two splitters
4603 that convert a variable shift into a loop. */
4604 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4605
4606 n = INTVAL (operands[2]);
4607
4608 /* If the count is negative, make it 0. */
4609 if (n < 0)
4610 n = 0;
4611 /* If the count is too big, truncate it.
4612 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4613 do the intuitive thing. */
4614 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4615 n = GET_MODE_BITSIZE (mode);
4616
4617 get_shift_alg (shift_type, shift_mode, n, &info);
4618
4619 switch (info.alg)
b839e0b4 4620 {
3afe906b 4621 case SHIFT_SPECIAL:
4622 output_asm_insn (info.special, operands);
4623 /* Fall through. */
b839e0b4 4624
3afe906b 4625 case SHIFT_INLINE:
4626 n = info.remainder;
b839e0b4 4627
3afe906b 4628 /* Emit two bit shifts first. */
4629 if (info.shift2 != NULL)
b839e0b4 4630 {
3afe906b 4631 for (; n > 1; n -= 2)
4632 output_asm_insn (info.shift2, operands);
4633 }
52abe980 4634
3afe906b 4635 /* Now emit one bit shifts for any residual. */
4636 for (; n > 0; n--)
4637 output_asm_insn (info.shift1, operands);
4638 return "";
4639
4640 case SHIFT_ROT_AND:
4641 {
4642 int m = GET_MODE_BITSIZE (mode) - n;
4643 const int mask = (shift_type == SHIFT_ASHIFT
4644 ? ((1 << m) - 1) << n
4645 : (1 << m) - 1);
4646 char insn_buf[200];
4647
4648 /* Not all possibilities of rotate are supported. They shouldn't
4649 be generated, but let's watch for 'em. */
4650 gcc_assert (info.shift1);
4651
4652 /* Emit two bit rotates first. */
4653 if (info.shift2 != NULL)
b839e0b4 4654 {
3afe906b 4655 for (; m > 1; m -= 2)
4656 output_asm_insn (info.shift2, operands);
4657 }
4658
4659 /* Now single bit rotates for any residual. */
4660 for (; m > 0; m--)
4661 output_asm_insn (info.shift1, operands);
4662
4663 /* Now mask off the high bits. */
4664 switch (mode)
4665 {
4666 case QImode:
4667 sprintf (insn_buf, "and\t#%d,%%X0", mask);
4668 break;
52abe980 4669
3afe906b 4670 case HImode:
4671 gcc_assert (TARGET_H8300H || TARGET_H8300S);
4672 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
4673 break;
52abe980 4674
3afe906b 4675 default:
4676 gcc_unreachable ();
b839e0b4 4677 }
cb95c693 4678
3afe906b 4679 output_asm_insn (insn_buf, operands);
4680 return "";
4681 }
cb95c693 4682
3afe906b 4683 case SHIFT_LOOP:
4684 /* A loop to shift by a "large" constant value.
4685 If we have shift-by-2 insns, use them. */
4686 if (info.shift2 != NULL)
4687 {
4688 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
4689 names_big[REGNO (operands[4])]);
4690 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4691 output_asm_insn (info.shift2, operands);
4692 output_asm_insn ("add #0xff,%X4", operands);
4693 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4694 if (n % 2)
4695 output_asm_insn (info.shift1, operands);
4696 }
4697 else
4698 {
4699 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
4700 names_big[REGNO (operands[4])]);
4701 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4702 output_asm_insn (info.shift1, operands);
4703 output_asm_insn ("add #0xff,%X4", operands);
4704 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
52abe980 4705 }
3afe906b 4706 return "";
4707
4708 default:
4709 gcc_unreachable ();
e1629549 4710 }
e1629549 4711}
484c1e8d 4712
8deb3959 4713/* Count the number of assembly instructions in a string TEMPL. */
cdfb02e8 4714
484c1e8d 4715static unsigned int
8deb3959 4716h8300_asm_insn_count (const char *templ)
484c1e8d 4717{
4718 unsigned int count = 1;
4719
8deb3959 4720 for (; *templ; templ++)
4721 if (*templ == '\n')
484c1e8d 4722 count++;
4723
4724 return count;
4725}
4726
cdfb02e8 4727/* Compute the length of a shift insn. */
4728
484c1e8d 4729unsigned int
230002f2 4730compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
484c1e8d 4731{
4732 rtx shift = operands[3];
4733 enum machine_mode mode = GET_MODE (shift);
4734 enum rtx_code code = GET_CODE (shift);
4735 enum shift_type shift_type;
4736 enum shift_mode shift_mode;
4737 struct shift_info info;
4738 unsigned int wlength = 0;
4739
4740 switch (mode)
4741 {
4742 case QImode:
4743 shift_mode = QIshift;
4744 break;
4745 case HImode:
4746 shift_mode = HIshift;
4747 break;
4748 case SImode:
4749 shift_mode = SIshift;
4750 break;
4751 default:
3afe906b 4752 gcc_unreachable ();
484c1e8d 4753 }
4754
4755 switch (code)
4756 {
4757 case ASHIFTRT:
4758 shift_type = SHIFT_ASHIFTRT;
4759 break;
4760 case LSHIFTRT:
4761 shift_type = SHIFT_LSHIFTRT;
4762 break;
4763 case ASHIFT:
4764 shift_type = SHIFT_ASHIFT;
4765 break;
4766 default:
3afe906b 4767 gcc_unreachable ();
484c1e8d 4768 }
4769
4770 if (GET_CODE (operands[2]) != CONST_INT)
4771 {
4772 /* Get the assembler code to do one shift. */
4773 get_shift_alg (shift_type, shift_mode, 1, &info);
4774
4775 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
4776 }
4777 else
4778 {
4779 int n = INTVAL (operands[2]);
4780
4781 /* If the count is negative, make it 0. */
4782 if (n < 0)
4783 n = 0;
4784 /* If the count is too big, truncate it.
4785 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4786 do the intuitive thing. */
4787 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4788 n = GET_MODE_BITSIZE (mode);
4789
4790 get_shift_alg (shift_type, shift_mode, n, &info);
4791
4792 switch (info.alg)
4793 {
4794 case SHIFT_SPECIAL:
4795 wlength += h8300_asm_insn_count (info.special);
f56f0ed0 4796
4797 /* Every assembly instruction used in SHIFT_SPECIAL case
4798 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4799 see xor.l, we just pretend that xor.l counts as two insns
4800 so that the insn length will be computed correctly. */
4801 if (strstr (info.special, "xor.l") != NULL)
4802 wlength++;
4803
484c1e8d 4804 /* Fall through. */
4805
4806 case SHIFT_INLINE:
4807 n = info.remainder;
4808
4809 if (info.shift2 != NULL)
4810 {
4811 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
4812 n = n % 2;
4813 }
4814
4815 wlength += h8300_asm_insn_count (info.shift1) * n;
66b41076 4816
484c1e8d 4817 return 2 * wlength;
4818
4819 case SHIFT_ROT_AND:
4820 {
4821 int m = GET_MODE_BITSIZE (mode) - n;
4822
4823 /* Not all possibilities of rotate are supported. They shouldn't
4824 be generated, but let's watch for 'em. */
3afe906b 4825 gcc_assert (info.shift1);
484c1e8d 4826
4827 if (info.shift2 != NULL)
4828 {
4829 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
4830 m = m % 2;
4831 }
4832
4833 wlength += h8300_asm_insn_count (info.shift1) * m;
66b41076 4834
484c1e8d 4835 /* Now mask off the high bits. */
4836 switch (mode)
4837 {
4838 case QImode:
4839 wlength += 1;
4840 break;
4841 case HImode:
4842 wlength += 2;
4843 break;
4844 case SImode:
3afe906b 4845 gcc_assert (!TARGET_H8300);
484c1e8d 4846 wlength += 3;
4847 break;
4848 default:
3afe906b 4849 gcc_unreachable ();
484c1e8d 4850 }
4851 return 2 * wlength;
4852 }
4853
4854 case SHIFT_LOOP:
4855 /* A loop to shift by a "large" constant value.
4856 If we have shift-by-2 insns, use them. */
4857 if (info.shift2 != NULL)
4858 {
4859 wlength += 3 + h8300_asm_insn_count (info.shift2);
4860 if (n % 2)
4861 wlength += h8300_asm_insn_count (info.shift1);
4862 }
4863 else
4864 {
4865 wlength += 3 + h8300_asm_insn_count (info.shift1);
4866 }
4867 return 2 * wlength;
4868
4869 default:
3afe906b 4870 gcc_unreachable ();
484c1e8d 4871 }
4872 }
4873}
fd7729c5 4874
cdfb02e8 4875/* Compute which flag bits are valid after a shift insn. */
4876
539b539f 4877enum attr_cc
230002f2 4878compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
fd7729c5 4879{
4880 rtx shift = operands[3];
4881 enum machine_mode mode = GET_MODE (shift);
4882 enum rtx_code code = GET_CODE (shift);
4883 enum shift_type shift_type;
4884 enum shift_mode shift_mode;
4885 struct shift_info info;
3afe906b 4886 int n;
4887
fd7729c5 4888 switch (mode)
4889 {
4890 case QImode:
4891 shift_mode = QIshift;
4892 break;
4893 case HImode:
4894 shift_mode = HIshift;
4895 break;
4896 case SImode:
4897 shift_mode = SIshift;
4898 break;
4899 default:
3afe906b 4900 gcc_unreachable ();
fd7729c5 4901 }
4902
4903 switch (code)
4904 {
4905 case ASHIFTRT:
4906 shift_type = SHIFT_ASHIFTRT;
4907 break;
4908 case LSHIFTRT:
4909 shift_type = SHIFT_LSHIFTRT;
4910 break;
4911 case ASHIFT:
4912 shift_type = SHIFT_ASHIFT;
4913 break;
4914 default:
3afe906b 4915 gcc_unreachable ();
fd7729c5 4916 }
4917
3afe906b 4918 /* This case must be taken care of by one of the two splitters
4919 that convert a variable shift into a loop. */
4920 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4921
4922 n = INTVAL (operands[2]);
4923
4924 /* If the count is negative, make it 0. */
4925 if (n < 0)
4926 n = 0;
4927 /* If the count is too big, truncate it.
4928 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4929 do the intuitive thing. */
4930 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4931 n = GET_MODE_BITSIZE (mode);
4932
4933 get_shift_alg (shift_type, shift_mode, n, &info);
4934
4935 switch (info.alg)
fd7729c5 4936 {
3afe906b 4937 case SHIFT_SPECIAL:
4938 if (info.remainder == 0)
4939 return info.cc_special;
fd7729c5 4940
3afe906b 4941 /* Fall through. */
fd7729c5 4942
3afe906b 4943 case SHIFT_INLINE:
4944 return info.cc_inline;
4945
4946 case SHIFT_ROT_AND:
4947 /* This case always ends with an and instruction. */
4948 return CC_SET_ZNV;
4949
4950 case SHIFT_LOOP:
4951 /* A loop to shift by a "large" constant value.
4952 If we have shift-by-2 insns, use them. */
4953 if (info.shift2 != NULL)
fd7729c5 4954 {
3afe906b 4955 if (n % 2)
4956 return info.cc_inline;
fd7729c5 4957 }
3afe906b 4958 return CC_CLOBBER;
4959
4960 default:
4961 gcc_unreachable ();
fd7729c5 4962 }
4963}
b839e0b4 4964\f
b4fa7cf2 4965/* A rotation by a non-constant will cause a loop to be generated, in
4966 which a rotation by one bit is used. A rotation by a constant,
4967 including the one in the loop, will be taken care of by
af63c5ce 4968 output_a_rotate () at the insn emit time. */
b4fa7cf2 4969
4970int
a620f9df 4971expand_a_rotate (rtx operands[])
b4fa7cf2 4972{
4973 rtx dst = operands[0];
4974 rtx src = operands[1];
4975 rtx rotate_amount = operands[2];
4976 enum machine_mode mode = GET_MODE (dst);
b4fa7cf2 4977
727c62dd 4978 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
4979 return false;
4980
b4fa7cf2 4981 /* We rotate in place. */
4982 emit_move_insn (dst, src);
4983
4984 if (GET_CODE (rotate_amount) != CONST_INT)
4985 {
4986 rtx counter = gen_reg_rtx (QImode);
79f6a8ed 4987 rtx_code_label *start_label = gen_label_rtx ();
4988 rtx_code_label *end_label = gen_label_rtx ();
b4fa7cf2 4989
4990 /* If the rotate amount is less than or equal to 0,
4991 we go out of the loop. */
bcd9bd66 4992 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
7e69f45b 4993 QImode, 0, end_label);
b4fa7cf2 4994
4995 /* Initialize the loop counter. */
4996 emit_move_insn (counter, rotate_amount);
4997
4998 emit_label (start_label);
4999
5000 /* Rotate by one bit. */
18618acc 5001 switch (mode)
5002 {
5003 case QImode:
5004 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
5005 break;
5006 case HImode:
5007 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
5008 break;
5009 case SImode:
5010 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
5011 break;
5012 default:
3afe906b 5013 gcc_unreachable ();
18618acc 5014 }
b4fa7cf2 5015
5016 /* Decrement the counter by 1. */
18618acc 5017 emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
b4fa7cf2 5018
c46dc351 5019 /* If the loop counter is nonzero, we go back to the beginning
b4fa7cf2 5020 of the loop. */
bcd9bd66 5021 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
7e69f45b 5022 start_label);
b4fa7cf2 5023
5024 emit_label (end_label);
5025 }
5026 else
5027 {
5028 /* Rotate by AMOUNT bits. */
18618acc 5029 switch (mode)
5030 {
5031 case QImode:
5032 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
5033 break;
5034 case HImode:
5035 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
5036 break;
5037 case SImode:
5038 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
5039 break;
5040 default:
3afe906b 5041 gcc_unreachable ();
18618acc 5042 }
b4fa7cf2 5043 }
5044
5045 return 1;
5046}
5047
cdfb02e8 5048/* Output a rotate insn. */
b4fa7cf2 5049
5050const char *
af63c5ce 5051output_a_rotate (enum rtx_code code, rtx *operands)
b4fa7cf2 5052{
5053 rtx dst = operands[0];
5054 rtx rotate_amount = operands[2];
5055 enum shift_mode rotate_mode;
5056 enum shift_type rotate_type;
5057 const char *insn_buf;
5058 int bits;
5059 int amount;
5060 enum machine_mode mode = GET_MODE (dst);
5061
3afe906b 5062 gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
b4fa7cf2 5063
5064 switch (mode)
5065 {
5066 case QImode:
5067 rotate_mode = QIshift;
5068 break;
5069 case HImode:
5070 rotate_mode = HIshift;
5071 break;
5072 case SImode:
5073 rotate_mode = SIshift;
5074 break;
5075 default:
3afe906b 5076 gcc_unreachable ();
b4fa7cf2 5077 }
5078
5079 switch (code)
5080 {
5081 case ROTATERT:
5082 rotate_type = SHIFT_ASHIFT;
5083 break;
5084 case ROTATE:
5085 rotate_type = SHIFT_LSHIFTRT;
5086 break;
5087 default:
3afe906b 5088 gcc_unreachable ();
b4fa7cf2 5089 }
5090
5091 amount = INTVAL (rotate_amount);
5092
5093 /* Clean up AMOUNT. */
5094 if (amount < 0)
5095 amount = 0;
5096 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5097 amount = GET_MODE_BITSIZE (mode);
5098
5099 /* Determine the faster direction. After this phase, amount will be
5100 at most a half of GET_MODE_BITSIZE (mode). */
de8409f8 5101 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
b4fa7cf2 5102 {
5103 /* Flip the direction. */
5104 amount = GET_MODE_BITSIZE (mode) - amount;
5105 rotate_type =
5106 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5107 }
5108
5109 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5110 boost up the rotation. */
5111 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5112 || (mode == HImode && TARGET_H8300H && amount >= 6)
5113 || (mode == HImode && TARGET_H8300S && amount == 8)
5114 || (mode == SImode && TARGET_H8300H && amount >= 10)
5115 || (mode == SImode && TARGET_H8300S && amount >= 13))
5116 {
5117 switch (mode)
5118 {
5119 case HImode:
5120 /* This code works on any family. */
5121 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5122 output_asm_insn (insn_buf, operands);
5123 break;
5124
5125 case SImode:
11f95d7c 5126 /* This code works on the H8/300H and H8S. */
b4fa7cf2 5127 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5128 output_asm_insn (insn_buf, operands);
5129 break;
5130
5131 default:
3afe906b 5132 gcc_unreachable ();
b4fa7cf2 5133 }
5134
5135 /* Adjust AMOUNT and flip the direction. */
5136 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5137 rotate_type =
5138 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5139 }
5140
18618acc 5141 /* Output rotate insns. */
b4fa7cf2 5142 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
5143 {
5144 if (bits == 2)
5145 insn_buf = rotate_two[rotate_type][rotate_mode];
5146 else
5147 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
a86fab2e 5148
b4fa7cf2 5149 for (; amount >= bits; amount -= bits)
5150 output_asm_insn (insn_buf, operands);
5151 }
5152
5153 return "";
5154}
af63c5ce 5155
cdfb02e8 5156/* Compute the length of a rotate insn. */
5157
af63c5ce 5158unsigned int
5159compute_a_rotate_length (rtx *operands)
5160{
5161 rtx src = operands[1];
3ab64e09 5162 rtx amount_rtx = operands[2];
af63c5ce 5163 enum machine_mode mode = GET_MODE (src);
5164 int amount;
5165 unsigned int length = 0;
5166
3afe906b 5167 gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
af63c5ce 5168
3ab64e09 5169 amount = INTVAL (amount_rtx);
af63c5ce 5170
5171 /* Clean up AMOUNT. */
5172 if (amount < 0)
5173 amount = 0;
5174 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5175 amount = GET_MODE_BITSIZE (mode);
5176
5177 /* Determine the faster direction. After this phase, amount
5178 will be at most a half of GET_MODE_BITSIZE (mode). */
5179 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5180 /* Flip the direction. */
5181 amount = GET_MODE_BITSIZE (mode) - amount;
5182
5183 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5184 boost up the rotation. */
5185 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5186 || (mode == HImode && TARGET_H8300H && amount >= 6)
5187 || (mode == HImode && TARGET_H8300S && amount == 8)
5188 || (mode == SImode && TARGET_H8300H && amount >= 10)
5189 || (mode == SImode && TARGET_H8300S && amount >= 13))
5190 {
5191 /* Adjust AMOUNT and flip the direction. */
5192 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5193 length += 6;
5194 }
5195
5196 /* We use 2-bit rotations on the H8S. */
5197 if (TARGET_H8300S)
5198 amount = amount / 2 + amount % 2;
5199
5200 /* The H8/300 uses three insns to rotate one bit, taking 6
5201 length. */
5202 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
5203
5204 return length;
5205}
b4fa7cf2 5206\f
b839e0b4 5207/* Fix the operands of a gen_xxx so that it could become a bit
a86fab2e 5208 operating insn. */
e1629549 5209
5210int
eb53e102 5211fix_bit_operand (rtx *operands, enum rtx_code code)
e1629549 5212{
b090827b 5213 /* The bit_operand predicate accepts any memory during RTL generation, but
b839e0b4 5214 only 'U' memory afterwards, so if this is a MEM operand, we must force
5215 it to be valid for 'U' by reloading the address. */
e1629549 5216
eb53e102 5217 if (code == AND
5218 ? single_zero_operand (operands[2], QImode)
5219 : single_one_operand (operands[2], QImode))
e1629549 5220 {
c7619744 5221 /* OK to have a memory dest. */
5222 if (GET_CODE (operands[0]) == MEM
424f5954 5223 && !satisfies_constraint_U (operands[0]))
b839e0b4 5224 {
c7619744 5225 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
5226 copy_to_mode_reg (Pmode,
5227 XEXP (operands[0], 0)));
5228 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5229 operands[0] = mem;
5230 }
b839e0b4 5231
c7619744 5232 if (GET_CODE (operands[1]) == MEM
424f5954 5233 && !satisfies_constraint_U (operands[1]))
c7619744 5234 {
5235 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
5236 copy_to_mode_reg (Pmode,
5237 XEXP (operands[1], 0)));
5238 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5239 operands[1] = mem;
b839e0b4 5240 }
c7619744 5241 return 0;
b839e0b4 5242 }
e1629549 5243
b839e0b4 5244 /* Dest and src op must be register. */
e1629549 5245
b839e0b4 5246 operands[1] = force_reg (QImode, operands[1]);
5247 {
5248 rtx res = gen_reg_rtx (QImode);
bd80419e 5249 switch (code)
4b042441 5250 {
5251 case AND:
5252 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
5253 break;
5254 case IOR:
5255 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
5256 break;
5257 case XOR:
5258 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
5259 break;
5260 default:
3afe906b 5261 gcc_unreachable ();
4b042441 5262 }
5263 emit_insn (gen_movqi (operands[0], res));
b839e0b4 5264 }
5265 return 1;
e1629549 5266}
b11bfc61 5267
b11bfc61 5268/* Return nonzero if FUNC is an interrupt function as specified
5269 by the "interrupt" attribute. */
5270
5271static int
230002f2 5272h8300_interrupt_function_p (tree func)
b11bfc61 5273{
5274 tree a;
5275
5276 if (TREE_CODE (func) != FUNCTION_DECL)
5277 return 0;
5278
e3c541f0 5279 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
b11bfc61 5280 return a != NULL_TREE;
5281}
5282
5344805f 5283/* Return nonzero if FUNC is a saveall function as specified by the
5284 "saveall" attribute. */
5285
5286static int
5287h8300_saveall_function_p (tree func)
5288{
5289 tree a;
5290
5291 if (TREE_CODE (func) != FUNCTION_DECL)
5292 return 0;
5293
5294 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
5295 return a != NULL_TREE;
5296}
5297
09c48b9c 5298/* Return nonzero if FUNC is an OS_Task function as specified
5299 by the "OS_Task" attribute. */
5300
5301static int
230002f2 5302h8300_os_task_function_p (tree func)
09c48b9c 5303{
5304 tree a;
5305
5306 if (TREE_CODE (func) != FUNCTION_DECL)
5307 return 0;
5308
e3c541f0 5309 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
09c48b9c 5310 return a != NULL_TREE;
5311}
5312
5313/* Return nonzero if FUNC is a monitor function as specified
5314 by the "monitor" attribute. */
5315
5316static int
230002f2 5317h8300_monitor_function_p (tree func)
09c48b9c 5318{
5319 tree a;
5320
5321 if (TREE_CODE (func) != FUNCTION_DECL)
5322 return 0;
5323
e3c541f0 5324 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
09c48b9c 5325 return a != NULL_TREE;
5326}
5327
b11bfc61 5328/* Return nonzero if FUNC is a function that should be called
5329 through the function vector. */
5330
5331int
230002f2 5332h8300_funcvec_function_p (tree func)
b11bfc61 5333{
5334 tree a;
5335
5336 if (TREE_CODE (func) != FUNCTION_DECL)
5337 return 0;
5338
e3c541f0 5339 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
b11bfc61 5340 return a != NULL_TREE;
5341}
5342
27a0be8f 5343/* Return nonzero if DECL is a variable that's in the eight bit
2c7be643 5344 data area. */
5345
5346int
230002f2 5347h8300_eightbit_data_p (tree decl)
2c7be643 5348{
5349 tree a;
5350
5351 if (TREE_CODE (decl) != VAR_DECL)
5352 return 0;
5353
e3c541f0 5354 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
2c7be643 5355 return a != NULL_TREE;
5356}
5357
27a0be8f 5358/* Return nonzero if DECL is a variable that's in the tiny
5359 data area. */
5360
5361int
230002f2 5362h8300_tiny_data_p (tree decl)
27a0be8f 5363{
5364 tree a;
5365
5366 if (TREE_CODE (decl) != VAR_DECL)
5367 return 0;
5368
e3c541f0 5369 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
27a0be8f 5370 return a != NULL_TREE;
5371}
5372
5344805f 5373/* Generate an 'interrupt_handler' attribute for decls. We convert
5374 all the pragmas to corresponding attributes. */
ad7d09f6 5375
5376static void
230002f2 5377h8300_insert_attributes (tree node, tree *attributes)
ad7d09f6 5378{
5344805f 5379 if (TREE_CODE (node) == FUNCTION_DECL)
5380 {
5381 if (pragma_interrupt)
5382 {
5383 pragma_interrupt = 0;
ad7d09f6 5384
5344805f 5385 /* Add an 'interrupt_handler' attribute. */
5386 *attributes = tree_cons (get_identifier ("interrupt_handler"),
5387 NULL, *attributes);
5388 }
41ed3bcd 5389
5344805f 5390 if (pragma_saveall)
5391 {
5392 pragma_saveall = 0;
5393
5394 /* Add an 'saveall' attribute. */
5395 *attributes = tree_cons (get_identifier ("saveall"),
5396 NULL, *attributes);
5397 }
5398 }
ad7d09f6 5399}
5400
e3c541f0 5401/* Supported attributes:
b11bfc61 5402
bd297402 5403 interrupt_handler: output a prologue and epilogue suitable for an
b11bfc61 5404 interrupt handler.
5405
5344805f 5406 saveall: output a prologue and epilogue that saves and restores
5407 all registers except the stack pointer.
5408
bd297402 5409 function_vector: This function should be called through the
27a0be8f 5410 function vector.
5411
5412 eightbit_data: This variable lives in the 8-bit data area and can
5413 be referenced with 8-bit absolute memory addresses.
5414
5415 tiny_data: This variable lives in the tiny data area and can be
5416 referenced with 16-bit absolute memory references. */
b11bfc61 5417
cd819d2f 5418static const struct attribute_spec h8300_attribute_table[] =
b11bfc61 5419{
ac86af5d 5420 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
5421 affects_type_identity } */
5422 { "interrupt_handler", 0, 0, true, false, false,
5423 h8300_handle_fndecl_attribute, false },
5424 { "saveall", 0, 0, true, false, false,
5425 h8300_handle_fndecl_attribute, false },
5426 { "OS_Task", 0, 0, true, false, false,
5427 h8300_handle_fndecl_attribute, false },
5428 { "monitor", 0, 0, true, false, false,
5429 h8300_handle_fndecl_attribute, false },
5430 { "function_vector", 0, 0, true, false, false,
5431 h8300_handle_fndecl_attribute, false },
5432 { "eightbit_data", 0, 0, true, false, false,
5433 h8300_handle_eightbit_data_attribute, false },
5434 { "tiny_data", 0, 0, true, false, false,
5435 h8300_handle_tiny_data_attribute, false },
5436 { NULL, 0, 0, false, false, false, NULL, false }
e3c541f0 5437};
b11bfc61 5438
2c7be643 5439
e3c541f0 5440/* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5441 struct attribute_spec.handler. */
5442static tree
230002f2 5443h8300_handle_fndecl_attribute (tree *node, tree name,
5444 tree args ATTRIBUTE_UNUSED,
5445 int flags ATTRIBUTE_UNUSED,
5446 bool *no_add_attrs)
e3c541f0 5447{
5448 if (TREE_CODE (*node) != FUNCTION_DECL)
5449 {
67a779df 5450 warning (OPT_Wattributes, "%qE attribute only applies to functions",
5451 name);
e3c541f0 5452 *no_add_attrs = true;
5453 }
5454
5455 return NULL_TREE;
5456}
5457
5458/* Handle an "eightbit_data" attribute; arguments as in
5459 struct attribute_spec.handler. */
5460static tree
230002f2 5461h8300_handle_eightbit_data_attribute (tree *node, tree name,
5462 tree args ATTRIBUTE_UNUSED,
5463 int flags ATTRIBUTE_UNUSED,
5464 bool *no_add_attrs)
e3c541f0 5465{
5466 tree decl = *node;
5467
5468 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
2c7be643 5469 {
738a6bda 5470 set_decl_section_name (decl, ".eight");
e3c541f0 5471 }
5472 else
5473 {
67a779df 5474 warning (OPT_Wattributes, "%qE attribute ignored",
5475 name);
e3c541f0 5476 *no_add_attrs = true;
27a0be8f 5477 }
5478
e3c541f0 5479 return NULL_TREE;
5480}
5481
5482/* Handle an "tiny_data" attribute; arguments as in
5483 struct attribute_spec.handler. */
5484static tree
230002f2 5485h8300_handle_tiny_data_attribute (tree *node, tree name,
5486 tree args ATTRIBUTE_UNUSED,
5487 int flags ATTRIBUTE_UNUSED,
5488 bool *no_add_attrs)
e3c541f0 5489{
5490 tree decl = *node;
5491
5492 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
27a0be8f 5493 {
738a6bda 5494 set_decl_section_name (decl, ".tiny");
e3c541f0 5495 }
5496 else
5497 {
67a779df 5498 warning (OPT_Wattributes, "%qE attribute ignored",
5499 name);
e3c541f0 5500 *no_add_attrs = true;
2c7be643 5501 }
eb2aa24e 5502
e3c541f0 5503 return NULL_TREE;
b11bfc61 5504}
5505
d37aaac2 5506/* Mark function vectors, and various small data objects. */
7811991d 5507
5508static void
230002f2 5509h8300_encode_section_info (tree decl, rtx rtl, int first)
7811991d 5510{
d37aaac2 5511 int extra_flags = 0;
5512
2c129d70 5513 default_encode_section_info (decl, rtl, first);
d37aaac2 5514
7811991d 5515 if (TREE_CODE (decl) == FUNCTION_DECL
5516 && h8300_funcvec_function_p (decl))
d37aaac2 5517 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
7811991d 5518 else if (TREE_CODE (decl) == VAR_DECL
5519 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
5520 {
5521 if (h8300_eightbit_data_p (decl))
d37aaac2 5522 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
7811991d 5523 else if (first && h8300_tiny_data_p (decl))
d37aaac2 5524 extra_flags = SYMBOL_FLAG_TINY_DATA;
7811991d 5525 }
7b4a38a6 5526
d37aaac2 5527 if (extra_flags)
2c129d70 5528 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
7b4a38a6 5529}
5530
cdfb02e8 5531/* Output a single-bit extraction. */
5532
9305fe33 5533const char *
230002f2 5534output_simode_bld (int bild, rtx operands[])
92eae32b 5535{
7ef78393 5536 if (TARGET_H8300)
5537 {
5538 /* Clear the destination register. */
5539 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
5540
5541 /* Now output the bit load or bit inverse load, and store it in
5542 the destination. */
5543 if (bild)
5544 output_asm_insn ("bild\t%Z2,%Y1", operands);
5545 else
5546 output_asm_insn ("bld\t%Z2,%Y1", operands);
92eae32b 5547
7ef78393 5548 output_asm_insn ("bst\t#0,%w0", operands);
5549 }
92eae32b 5550 else
7ef78393 5551 {
7d3e46b8 5552 /* Determine if we can clear the destination first. */
5553 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
5554 && REGNO (operands[0]) != REGNO (operands[1]));
5555
5556 if (clear_first)
5557 output_asm_insn ("sub.l\t%S0,%S0", operands);
5558
7ef78393 5559 /* Output the bit load or bit inverse load. */
5560 if (bild)
5561 output_asm_insn ("bild\t%Z2,%Y1", operands);
5562 else
5563 output_asm_insn ("bld\t%Z2,%Y1", operands);
5564
7d3e46b8 5565 if (!clear_first)
5566 output_asm_insn ("xor.l\t%S0,%S0", operands);
5567
5568 /* Perform the bit store. */
04b5bef5 5569 output_asm_insn ("rotxl.l\t%S0", operands);
7ef78393 5570 }
92eae32b 5571
5572 /* All done. */
5573 return "";
5574}
fe19f1e0 5575
727c62dd 5576/* Delayed-branch scheduling is more effective if we have some idea
5577 how long each instruction will be. Use a shorten_branches pass
5578 to get an initial estimate. */
5579
5580static void
5581h8300_reorg (void)
5582{
5583 if (flag_delayed_branch)
5584 shorten_branches (get_insns ());
5585}
5586
6e4758ce 5587#ifndef OBJECT_FORMAT_ELF
2cb4ac60 5588static void
537cd941 5589h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED,
5590 tree decl)
2cb4ac60 5591{
5592 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5593 fprintf (asm_out_file, "\t.section %s\n", name);
5594}
6e4758ce 5595#endif /* ! OBJECT_FORMAT_ELF */
6c48c1e4 5596
e566129f 5597/* Nonzero if X is a constant address suitable as an 8-bit absolute,
5598 which is a special case of the 'R' operand. */
5599
6c48c1e4 5600int
230002f2 5601h8300_eightbit_constant_address_p (rtx x)
6c48c1e4 5602{
1d60d981 5603 /* The ranges of the 8-bit area. */
424064e7 5604 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
5605 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
6c48c1e4 5606 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
5607 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
5608 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
5609 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
5610
5611 unsigned HOST_WIDE_INT addr;
5612
e55c1a72 5613 /* We accept symbols declared with eightbit_data. */
d37aaac2 5614 if (GET_CODE (x) == SYMBOL_REF)
5615 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
e55c1a72 5616
6c48c1e4 5617 if (GET_CODE (x) != CONST_INT)
5618 return 0;
5619
5620 addr = INTVAL (x);
5621
5622 return (0
35a462ce 5623 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
6c48c1e4 5624 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
5625 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
5626}
5627
e566129f 5628/* Nonzero if X is a constant address suitable as an 16-bit absolute
5629 on H8/300H and H8S. */
5630
6c48c1e4 5631int
230002f2 5632h8300_tiny_constant_address_p (rtx x)
6c48c1e4 5633{
462c2024 5634 /* The ranges of the 16-bit area. */
6c48c1e4 5635 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
5636 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
5637 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
5638 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
5639 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
5640 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
5641 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
5642 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
5643
5644 unsigned HOST_WIDE_INT addr;
5645
52d2fba2 5646 switch (GET_CODE (x))
5647 {
5648 case SYMBOL_REF:
abe5efd4 5649 /* In the normal mode, any symbol fits in the 16-bit absolute
5650 address range. We also accept symbols declared with
5651 tiny_data. */
5652 return (TARGET_NORMAL_MODE
5653 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
3696208f 5654
52d2fba2 5655 case CONST_INT:
5656 addr = INTVAL (x);
5657 return (TARGET_NORMAL_MODE
5658 || (TARGET_H8300H
5659 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
5660 || (TARGET_H8300S
5661 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
6c48c1e4 5662
abe5efd4 5663 case CONST:
5664 return TARGET_NORMAL_MODE;
5665
52d2fba2 5666 default:
5667 return 0;
5668 }
6c48c1e4 5669
6c48c1e4 5670}
e33ecec3 5671
cdfb02e8 5672/* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5673 locations that can be accessed as a 16-bit word. */
5674
e33ecec3 5675int
230002f2 5676byte_accesses_mergeable_p (rtx addr1, rtx addr2)
e33ecec3 5677{
5678 HOST_WIDE_INT offset1, offset2;
5679 rtx reg1, reg2;
5680
5681 if (REG_P (addr1))
5682 {
5683 reg1 = addr1;
5684 offset1 = 0;
5685 }
5686 else if (GET_CODE (addr1) == PLUS
5687 && REG_P (XEXP (addr1, 0))
5688 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
5689 {
5690 reg1 = XEXP (addr1, 0);
5691 offset1 = INTVAL (XEXP (addr1, 1));
5692 }
5693 else
5694 return 0;
5695
5696 if (REG_P (addr2))
5697 {
5698 reg2 = addr2;
5699 offset2 = 0;
5700 }
5701 else if (GET_CODE (addr2) == PLUS
5702 && REG_P (XEXP (addr2, 0))
5703 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
5704 {
5705 reg2 = XEXP (addr2, 0);
5706 offset2 = INTVAL (XEXP (addr2, 1));
5707 }
5708 else
5709 return 0;
5710
5711 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
5712 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
5713 && offset1 % 2 == 0
5714 && offset1 + 1 == offset2)
5715 return 1;
5716
5717 return 0;
5718}
8c71b4e9 5719
5720/* Return nonzero if we have the same comparison insn as I3 two insns
be002911 5721 before I3. I3 is assumed to be a comparison insn. */
8c71b4e9 5722
5723int
5724same_cmp_preceding_p (rtx i3)
5725{
93ee8dfb 5726 rtx_insn *i1, *i2;
8c71b4e9 5727
5728 /* Make sure we have a sequence of three insns. */
5729 i2 = prev_nonnote_insn (i3);
93ee8dfb 5730 if (i2 == NULL)
8c71b4e9 5731 return 0;
5732 i1 = prev_nonnote_insn (i2);
93ee8dfb 5733 if (i1 == NULL)
8c71b4e9 5734 return 0;
5735
5736 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5737 && any_condjump_p (i2) && onlyjump_p (i2));
5738}
01272fdf 5739
5b9da921 5740/* Return nonzero if we have the same comparison insn as I1 two insns
5741 after I1. I1 is assumed to be a comparison insn. */
5742
5743int
5744same_cmp_following_p (rtx i1)
5745{
93ee8dfb 5746 rtx_insn *i2, *i3;
5b9da921 5747
5748 /* Make sure we have a sequence of three insns. */
5749 i2 = next_nonnote_insn (i1);
93ee8dfb 5750 if (i2 == NULL)
5b9da921 5751 return 0;
5752 i3 = next_nonnote_insn (i2);
93ee8dfb 5753 if (i3 == NULL)
5b9da921 5754 return 0;
5755
5756 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5757 && any_condjump_p (i2) && onlyjump_p (i2));
5758}
5759
f41916c8 5760/* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
7bd28bba 5761 (or pops) N registers. OPERANDS are assumed to be an array of
f41916c8 5762 registers. */
5763
5764int
5765h8300_regs_ok_for_stm (int n, rtx operands[])
5766{
5767 switch (n)
5768 {
5769 case 2:
5770 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
5771 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
5772 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
5773 case 3:
5774 return ((REGNO (operands[0]) == 0
5775 && REGNO (operands[1]) == 1
5776 && REGNO (operands[2]) == 2)
5777 || (REGNO (operands[0]) == 4
5778 && REGNO (operands[1]) == 5
5779 && REGNO (operands[2]) == 6));
5780
5781 case 4:
5782 return (REGNO (operands[0]) == 0
5783 && REGNO (operands[1]) == 1
5784 && REGNO (operands[2]) == 2
5785 && REGNO (operands[3]) == 3);
3afe906b 5786 default:
5787 gcc_unreachable ();
f41916c8 5788 }
f41916c8 5789}
5790
01272fdf 5791/* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5792
5793int
5794h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5795 unsigned int new_reg)
5796{
5797 /* Interrupt functions can only use registers that have already been
5798 saved by the prologue, even if they would normally be
5799 call-clobbered. */
5800
5801 if (h8300_current_function_interrupt_function_p ()
3072d30e 5802 && !df_regs_ever_live_p (new_reg))
01272fdf 5803 return 0;
5804
6fe6e17a 5805 return 1;
01272fdf 5806}
9a5775fe 5807
cf695b54 5808/* Returns true if register REGNO is safe to be allocated as a scratch
5809 register in the current function. */
5810
5811static bool
5812h8300_hard_regno_scratch_ok (unsigned int regno)
5813{
5814 if (h8300_current_function_interrupt_function_p ()
5815 && ! WORD_REG_USED (regno))
5816 return false;
5817
5818 return true;
5819}
5820
5821
9a5775fe 5822/* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5823
5824static int
5825h8300_rtx_ok_for_base_p (rtx x, int strict)
5826{
5827 /* Strip off SUBREG if any. */
5828 if (GET_CODE (x) == SUBREG)
5829 x = SUBREG_REG (x);
5830
5831 return (REG_P (x)
5832 && (strict
5833 ? REG_OK_FOR_BASE_STRICT_P (x)
5834 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
5835}
5836
5837/* Return nozero if X is a legitimate address. On the H8/300, a
5838 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5839 CONSTANT_ADDRESS. */
5840
fd50b071 5841static bool
5842h8300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
9a5775fe 5843{
5844 /* The register indirect addresses like @er0 is always valid. */
5845 if (h8300_rtx_ok_for_base_p (x, strict))
5846 return 1;
5847
5848 if (CONSTANT_ADDRESS_P (x))
5849 return 1;
5850
727c62dd 5851 if (TARGET_H8300SX
5852 && ( GET_CODE (x) == PRE_INC
5853 || GET_CODE (x) == PRE_DEC
5854 || GET_CODE (x) == POST_INC
5855 || GET_CODE (x) == POST_DEC)
5856 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
5857 return 1;
5858
9a5775fe 5859 if (GET_CODE (x) == PLUS
5860 && CONSTANT_ADDRESS_P (XEXP (x, 1))
727c62dd 5861 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
5862 mode, 0), strict))
9a5775fe 5863 return 1;
5864
5865 return 0;
5866}
a578a1cc 5867
5868/* Worker function for HARD_REGNO_NREGS.
5869
5870 We pretend the MAC register is 32bits -- we don't have any data
5871 types on the H8 series to handle more than 32bits. */
5872
5873int
5874h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, enum machine_mode mode)
5875{
5876 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5877}
5878
5879/* Worker function for HARD_REGNO_MODE_OK. */
5880
5881int
5882h8300_hard_regno_mode_ok (int regno, enum machine_mode mode)
5883{
5884 if (TARGET_H8300)
5885 /* If an even reg, then anything goes. Otherwise the mode must be
5886 QI or HI. */
5887 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
5888 else
5889 /* MAC register can only be of SImode. Otherwise, anything
5890 goes. */
5891 return regno == MAC_REG ? mode == SImode : 1;
5892}
e8bd1224 5893
5894/* Helper function for the move patterns. Make sure a move is legitimate. */
5895
5896bool
5897h8300_move_ok (rtx dest, rtx src)
5898{
5899 rtx addr, other;
5900
5901 /* Validate that at least one operand is a register. */
5902 if (MEM_P (dest))
5903 {
5904 if (MEM_P (src) || CONSTANT_P (src))
5905 return false;
5906 addr = XEXP (dest, 0);
5907 other = src;
5908 }
5909 else if (MEM_P (src))
5910 {
5911 addr = XEXP (src, 0);
5912 other = dest;
5913 }
5914 else
5915 return true;
5916
5917 /* Validate that auto-inc doesn't affect OTHER. */
5918 if (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC)
5919 return true;
5920 addr = XEXP (addr, 0);
5921
5922 if (addr == stack_pointer_rtx)
5923 return register_no_sp_elim_operand (other, VOIDmode);
5924 else
5925 return !reg_overlap_mentioned_p(other, addr);
5926}
9fb90c4e 5927\f
f2f543a3 5928/* Perform target dependent optabs initialization. */
5929static void
5930h8300_init_libfuncs (void)
5931{
5932 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
5933 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
5934 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
5935 set_optab_libfunc (smod_optab, HImode, "__modhi3");
5936 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
5937}
5938\f
9f4cd859 5939/* Worker function for TARGET_FUNCTION_VALUE.
5940
5941 On the H8 the return value is in R0/R1. */
5942
5943static rtx
5944h8300_function_value (const_tree ret_type,
5945 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
5946 bool outgoing ATTRIBUTE_UNUSED)
5947{
5948 return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG);
5949}
5950
5951/* Worker function for TARGET_LIBCALL_VALUE.
5952
5953 On the H8 the return value is in R0/R1. */
5954
5955static rtx
5956h8300_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5957{
5958 return gen_rtx_REG (mode, R0_REG);
5959}
5960
5961/* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5962
5963 On the H8, R0 is the only register thus used. */
5964
5965static bool
5966h8300_function_value_regno_p (const unsigned int regno)
5967{
5968 return (regno == R0_REG);
5969}
5970
cdfb02e8 5971/* Worker function for TARGET_RETURN_IN_MEMORY. */
5972
5c6c612a 5973static bool
fb80456a 5974h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5c6c612a 5975{
5976 return (TYPE_MODE (type) == BLKmode
5977 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
5978}
5979\f
70fe8eb7 5980/* We emit the entire trampoline here. Depending on the pointer size,
5981 we use a different trampoline.
5982
5983 Pmode == HImode
5984 vvvv context
5985 1 0000 7903xxxx mov.w #0x1234,r3
5986 2 0004 5A00xxxx jmp @0x1234
5987 ^^^^ function
5988
5989 Pmode == SImode
5990 vvvvvvvv context
5991 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
5992 3 0006 5Axxxxxx jmp @0x123456
5993 ^^^^^^ function
5994*/
5995
5996static void
5997h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
5998{
5999 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6000 rtx mem;
6001
6002 if (Pmode == HImode)
6003 {
6004 mem = adjust_address (m_tramp, HImode, 0);
6005 emit_move_insn (mem, GEN_INT (0x7903));
6006 mem = adjust_address (m_tramp, Pmode, 2);
6007 emit_move_insn (mem, cxt);
6008 mem = adjust_address (m_tramp, HImode, 4);
6009 emit_move_insn (mem, GEN_INT (0x5a00));
6010 mem = adjust_address (m_tramp, Pmode, 6);
6011 emit_move_insn (mem, fnaddr);
6012 }
6013 else
6014 {
6015 rtx tem;
6016
6017 mem = adjust_address (m_tramp, HImode, 0);
6018 emit_move_insn (mem, GEN_INT (0x7a03));
6019 mem = adjust_address (m_tramp, Pmode, 2);
6020 emit_move_insn (mem, cxt);
6021
6022 tem = copy_to_reg (fnaddr);
6023 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff)));
6024 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000)));
6025 mem = adjust_address (m_tramp, SImode, 6);
6026 emit_move_insn (mem, tem);
6027 }
6028}
6029\f
9fb90c4e 6030/* Initialize the GCC target structure. */
6031#undef TARGET_ATTRIBUTE_TABLE
6032#define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
6033
6034#undef TARGET_ASM_ALIGNED_HI_OP
6035#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
6036
92c473b8 6037#undef TARGET_ASM_FILE_START
6038#define TARGET_ASM_FILE_START h8300_file_start
6039#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
6040#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
6041
9fb90c4e 6042#undef TARGET_ASM_FILE_END
6043#define TARGET_ASM_FILE_END h8300_file_end
6044
87ad9aff 6045#undef TARGET_PRINT_OPERAND
6046#define TARGET_PRINT_OPERAND h8300_print_operand
6047#undef TARGET_PRINT_OPERAND_ADDRESS
6048#define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
6049#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
6050#define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
6051
9fb90c4e 6052#undef TARGET_ENCODE_SECTION_INFO
6053#define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
6054
6055#undef TARGET_INSERT_ATTRIBUTES
6056#define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
6057
87ad9aff 6058#undef TARGET_REGISTER_MOVE_COST
6059#define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
6060
9fb90c4e 6061#undef TARGET_RTX_COSTS
6062#define TARGET_RTX_COSTS h8300_rtx_costs
6063
f2f543a3 6064#undef TARGET_INIT_LIBFUNCS
6065#define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
6066
9f4cd859 6067#undef TARGET_FUNCTION_VALUE
6068#define TARGET_FUNCTION_VALUE h8300_function_value
6069
6070#undef TARGET_LIBCALL_VALUE
6071#define TARGET_LIBCALL_VALUE h8300_libcall_value
6072
6073#undef TARGET_FUNCTION_VALUE_REGNO_P
6074#define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
6075
5c6c612a 6076#undef TARGET_RETURN_IN_MEMORY
6077#define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
6078
e7489b8b 6079#undef TARGET_FUNCTION_ARG
6080#define TARGET_FUNCTION_ARG h8300_function_arg
6081
6082#undef TARGET_FUNCTION_ARG_ADVANCE
6083#define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
6084
727c62dd 6085#undef TARGET_MACHINE_DEPENDENT_REORG
6086#define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
6087
cf695b54 6088#undef TARGET_HARD_REGNO_SCRATCH_OK
6089#define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
6090
fd50b071 6091#undef TARGET_LEGITIMATE_ADDRESS_P
6092#define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
6093
cd90919d 6094#undef TARGET_CAN_ELIMINATE
6095#define TARGET_CAN_ELIMINATE h8300_can_eliminate
6096
b2d7ede1 6097#undef TARGET_CONDITIONAL_REGISTER_USAGE
6098#define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
6099
70fe8eb7 6100#undef TARGET_TRAMPOLINE_INIT
6101#define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6102
4c834714 6103#undef TARGET_OPTION_OVERRIDE
6104#define TARGET_OPTION_OVERRIDE h8300_option_override
6105
958f5301 6106#undef TARGET_MODE_DEPENDENT_ADDRESS_P
6107#define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6108
9fb90c4e 6109struct gcc_target targetm = TARGET_INITIALIZER;
Mirror of https://gcc.gnu.org/git/gcc.git