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Turn HARD_REGNO_MODE_OK into a target hook
[thirdparty/gcc.git] / gcc / config / h8300 / h8300.c
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716085c2 1/* Subroutines for insn-output.c for Renesas H8/300.
aad93da1 2 Copyright (C) 1992-2017 Free Software Foundation, Inc.
b839e0b4 3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
e1629549 5
dbbae424 6This file is part of GCC.
e1629549 7
dbbae424 8GCC is free software; you can redistribute it and/or modify
e1629549 9it under the terms of the GNU General Public License as published by
038d1e19 10the Free Software Foundation; either version 3, or (at your option)
e1629549 11any later version.
12
dbbae424 13GCC is distributed in the hope that it will be useful,
e1629549 14but WITHOUT ANY WARRANTY; without even the implied warranty of
15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
038d1e19 19along with GCC; see the file COPYING3. If not see
20<http://www.gnu.org/licenses/>. */
e1629549 21
e1629549 22#include "config.h"
7014838c 23#include "system.h"
805e22b2 24#include "coretypes.h"
9ef16211 25#include "backend.h"
c1eb80de 26#include "target.h"
e1629549 27#include "rtl.h"
c1eb80de 28#include "tree.h"
9ef16211 29#include "df.h"
ad7b10a2 30#include "memmodel.h"
c1eb80de 31#include "tm_p.h"
32#include "stringpool.h"
30a86690 33#include "attribs.h"
c1eb80de 34#include "optabs.h"
35#include "regs.h"
36#include "emit-rtl.h"
37#include "recog.h"
38#include "diagnostic-core.h"
b20a8bb4 39#include "alias.h"
9ed99284 40#include "stor-layout.h"
41#include "varasm.h"
42#include "calls.h"
e1629549 43#include "conditions.h"
e1629549 44#include "output.h"
45#include "insn-attr.h"
46#include "flags.h"
d53441c8 47#include "explow.h"
d53441c8 48#include "expr.h"
424f5954 49#include "tm-constrs.h"
f7715905 50#include "builtins.h"
e1629549 51
0c71fb4f 52/* This file should be included last. */
4b498588 53#include "target-def.h"
54
727c62dd 55/* Classifies a h8300_src_operand or h8300_dst_operand.
56
57 H8OP_IMMEDIATE
58 A constant operand of some sort.
59
60 H8OP_REGISTER
61 An ordinary register.
62
63 H8OP_MEM_ABSOLUTE
64 A memory reference with a constant address.
65
66 H8OP_MEM_BASE
67 A memory reference with a register as its address.
68
69 H8OP_MEM_COMPLEX
70 Some other kind of memory reference. */
71enum h8300_operand_class
72{
73 H8OP_IMMEDIATE,
74 H8OP_REGISTER,
75 H8OP_MEM_ABSOLUTE,
76 H8OP_MEM_BASE,
77 H8OP_MEM_COMPLEX,
78 NUM_H8OPS
79};
80
727c62dd 81/* For a general two-operand instruction, element [X][Y] gives
82 the length of the opcode fields when the first operand has class
83 (X + 1) and the second has class Y. */
84typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
85
e1629549 86/* Forward declarations. */
230002f2 87static const char *byte_reg (rtx, int);
88static int h8300_interrupt_function_p (tree);
5344805f 89static int h8300_saveall_function_p (tree);
230002f2 90static int h8300_monitor_function_p (tree);
91static int h8300_os_task_function_p (tree);
5da0dad2 92static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool);
959e2f12 93static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
230002f2 94static unsigned int compute_saved_regs (void);
230002f2 95static const char *cond_string (enum rtx_code);
96static unsigned int h8300_asm_insn_count (const char *);
230002f2 97static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
98static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
99static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
3c047fe9 100static void h8300_print_operand_address (FILE *, machine_mode, rtx);
87ad9aff 101static void h8300_print_operand (FILE *, rtx, int);
102static bool h8300_print_operand_punct_valid_p (unsigned char code);
6e4758ce 103#ifndef OBJECT_FORMAT_ELF
537cd941 104static void h8300_asm_named_section (const char *, unsigned int, tree);
6e4758ce 105#endif
3754d046 106static int h8300_register_move_cost (machine_mode, reg_class_t, reg_class_t);
230002f2 107static int h8300_and_costs (rtx);
108static int h8300_shift_costs (rtx);
5a23ee68 109static void h8300_push_pop (int, int, bool, bool);
727c62dd 110static int h8300_stack_offset_p (rtx, int);
111static int h8300_ldm_stm_regno (rtx, int, int, int);
727c62dd 112static void h8300_reorg (void);
113static unsigned int h8300_constant_length (rtx);
114static unsigned int h8300_displacement_length (rtx, int);
115static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *);
116static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *);
117static unsigned int h8300_unary_length (rtx);
118static unsigned int h8300_short_immediate_length (rtx);
119static unsigned int h8300_bitfield_length (rtx, rtx);
1a1ed145 120static unsigned int h8300_binary_length (rtx_insn *, const h8300_length_table *);
727c62dd 121static bool h8300_short_move_mem_p (rtx, enum rtx_code);
122static unsigned int h8300_move_length (rtx *, const h8300_length_table *);
cf695b54 123static bool h8300_hard_regno_scratch_ok (unsigned int);
3754d046 124static rtx h8300_get_index (rtx, machine_mode mode, int *);
b11bfc61 125
b839e0b4 126/* CPU_TYPE, says what cpu we're compiling for. */
127int cpu_type;
128
41ed3bcd 129/* True if a #pragma interrupt has been seen for the current function. */
130static int pragma_interrupt;
e1629549 131
132/* True if a #pragma saveall has been seen for the current function. */
8ba450ad 133static int pragma_saveall;
e1629549 134
9305fe33 135static const char *const names_big[] =
eb2aa24e 136{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
b839e0b4 137
9305fe33 138static const char *const names_extended[] =
eb2aa24e 139{ "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
b839e0b4 140
9305fe33 141static const char *const names_upper_extended[] =
eb2aa24e 142{ "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
b839e0b4 143
144/* Points to one of the above. */
145/* ??? The above could be put in an array indexed by CPU_TYPE. */
9305fe33 146const char * const *h8_reg_names;
b839e0b4 147
148/* Various operations needed by the following, indexed by CPU_TYPE. */
b839e0b4 149
9305fe33 150const char *h8_push_op, *h8_pop_op, *h8_mov_op;
d37aaac2 151
727c62dd 152/* Value of MOVE_RATIO. */
153int h8300_move_ratio;
a767736d 154\f
0650a2e5 155/* See below where shifts are handled for explanation of this enum. */
156
157enum shift_alg
158{
159 SHIFT_INLINE,
160 SHIFT_ROT_AND,
161 SHIFT_SPECIAL,
162 SHIFT_LOOP
163};
164
165/* Symbols of the various shifts which can be used as indices. */
166
167enum shift_type
168{
169 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
170};
171
172/* Macros to keep the shift algorithm tables small. */
173#define INL SHIFT_INLINE
174#define ROT SHIFT_ROT_AND
175#define LOP SHIFT_LOOP
176#define SPC SHIFT_SPECIAL
177
178/* The shift algorithms for each machine, mode, shift type, and shift
179 count are defined below. The three tables below correspond to
180 QImode, HImode, and SImode, respectively. Each table is organized
cc72e60a 181 by, in the order of indices, machine, shift type, and shift count. */
0650a2e5 182
183static enum shift_alg shift_alg_qi[3][3][8] = {
184 {
185 /* TARGET_H8300 */
186 /* 0 1 2 3 4 5 6 7 */
187 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
188 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
189 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
190 },
191 {
192 /* TARGET_H8300H */
193 /* 0 1 2 3 4 5 6 7 */
194 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
195 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
196 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
197 },
198 {
199 /* TARGET_H8300S */
200 /* 0 1 2 3 4 5 6 7 */
201 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
202 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
203 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
204 }
205};
206
207static enum shift_alg shift_alg_hi[3][3][16] = {
208 {
209 /* TARGET_H8300 */
210 /* 0 1 2 3 4 5 6 7 */
211 /* 8 9 10 11 12 13 14 15 */
212 { INL, INL, INL, INL, INL, INL, INL, SPC,
213 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
214 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
215 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
216 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
217 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
218 },
219 {
220 /* TARGET_H8300H */
221 /* 0 1 2 3 4 5 6 7 */
222 /* 8 9 10 11 12 13 14 15 */
223 { INL, INL, INL, INL, INL, INL, INL, SPC,
224 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
225 { INL, INL, INL, INL, INL, INL, INL, SPC,
226 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
227 { INL, INL, INL, INL, INL, INL, INL, SPC,
228 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
229 },
230 {
231 /* TARGET_H8300S */
232 /* 0 1 2 3 4 5 6 7 */
233 /* 8 9 10 11 12 13 14 15 */
234 { INL, INL, INL, INL, INL, INL, INL, INL,
235 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
236 { INL, INL, INL, INL, INL, INL, INL, INL,
237 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
238 { INL, INL, INL, INL, INL, INL, INL, INL,
239 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
240 }
241};
242
243static enum shift_alg shift_alg_si[3][3][32] = {
244 {
245 /* TARGET_H8300 */
246 /* 0 1 2 3 4 5 6 7 */
247 /* 8 9 10 11 12 13 14 15 */
248 /* 16 17 18 19 20 21 22 23 */
249 /* 24 25 26 27 28 29 30 31 */
250 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
251 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
252 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
253 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
254 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
255 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
256 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
257 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
258 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
259 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
260 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
261 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
262 },
263 {
264 /* TARGET_H8300H */
265 /* 0 1 2 3 4 5 6 7 */
266 /* 8 9 10 11 12 13 14 15 */
267 /* 16 17 18 19 20 21 22 23 */
268 /* 24 25 26 27 28 29 30 31 */
269 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
270 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
271 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
567c4b66 272 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
0650a2e5 273 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
274 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
275 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
567c4b66 276 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
0650a2e5 277 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
278 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
279 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
280 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
281 },
282 {
283 /* TARGET_H8300S */
284 /* 0 1 2 3 4 5 6 7 */
285 /* 8 9 10 11 12 13 14 15 */
286 /* 16 17 18 19 20 21 22 23 */
287 /* 24 25 26 27 28 29 30 31 */
288 { INL, INL, INL, INL, INL, INL, INL, INL,
289 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
290 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
567c4b66 291 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
0650a2e5 292 { INL, INL, INL, INL, INL, INL, INL, INL,
293 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
294 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
567c4b66 295 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
0650a2e5 296 { INL, INL, INL, INL, INL, INL, INL, INL,
297 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
298 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
299 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
300 }
301};
302
303#undef INL
304#undef ROT
305#undef LOP
306#undef SPC
307
308enum h8_cpu
309{
310 H8_300,
311 H8_300H,
312 H8_S
313};
314
b839e0b4 315/* Initialize various cpu specific globals at start up. */
316
4c834714 317static void
318h8300_option_override (void)
b839e0b4 319{
1592a00c 320 static const char *const h8_push_ops[2] = { "push" , "push.l" };
321 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
322 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
323
d3677aa8 324#ifndef OBJECT_FORMAT_ELF
325 if (TARGET_H8300SX)
326 {
327 error ("-msx is not supported in coff");
328 target_flags |= MASK_H8300S;
329 }
330#endif
331
b839e0b4 332 if (TARGET_H8300)
333 {
334 cpu_type = (int) CPU_H8300;
335 h8_reg_names = names_big;
336 }
337 else
338 {
11f95d7c 339 /* For this we treat the H8/300H and H8S the same. */
b839e0b4 340 cpu_type = (int) CPU_H8300H;
341 h8_reg_names = names_extended;
342 }
343 h8_push_op = h8_push_ops[cpu_type];
344 h8_pop_op = h8_pop_ops[cpu_type];
345 h8_mov_op = h8_mov_ops[cpu_type];
92d7ef92 346
347 if (!TARGET_H8300S && TARGET_MAC)
f060a027 348 {
68435912 349 error ("-ms2600 is used without -ms");
3f21adc8 350 target_flags |= MASK_H8300S_1;
f060a027 351 }
16b503e9 352
35a462ce 353 if (TARGET_H8300 && TARGET_NORMAL_MODE)
354 {
d3677aa8 355 error ("-mn is used without -mh or -ms or -msx");
35a462ce 356 target_flags ^= MASK_NORMAL_MODE;
357 }
0650a2e5 358
d3677aa8 359 if (! TARGET_H8300S && TARGET_EXR)
360 {
361 error ("-mexr is used without -ms");
362 target_flags |= MASK_H8300S_1;
363 }
364
365 if (TARGET_H8300 && TARGET_INT32)
366 {
367 error ("-mint32 is not supported for H8300 and H8300L targets");
368 target_flags ^= MASK_INT32;
369 }
370
371 if ((!TARGET_H8300S && TARGET_EXR) && (!TARGET_H8300SX && TARGET_EXR))
372 {
373 error ("-mexr is used without -ms or -msx");
374 target_flags |= MASK_H8300S_1;
375 }
376
377 if ((!TARGET_H8300S && TARGET_NEXR) && (!TARGET_H8300SX && TARGET_NEXR))
378 {
379 warning (OPT_mno_exr, "-mno-exr valid only with -ms or -msx \
380 - Option ignored!");
381 }
382
acff2768 383#ifdef H8300_LINUX
384 if ((TARGET_NORMAL_MODE))
385 {
386 error ("-mn is not supported for linux targets");
387 target_flags ^= MASK_NORMAL_MODE;
388 }
389#endif
390
9f56f86b 391 /* Some of the shifts are optimized for speed by default.
0650a2e5 392 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
9f56f86b 393 If optimizing for size, change shift_alg for those shift to
0650a2e5 394 SHIFT_LOOP. */
3a599070 395 if (optimize_size)
0650a2e5 396 {
3a599070 397 /* H8/300 */
398 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
399 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
400 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
401 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
0650a2e5 402
3a599070 403 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
404 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
0650a2e5 405
3a599070 406 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
407 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
0650a2e5 408
3a599070 409 /* H8/300H */
410 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
411 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
0650a2e5 412
3a599070 413 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
414 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
0650a2e5 415
3a599070 416 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
417 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
418 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
419 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
0650a2e5 420
421 /* H8S */
3a599070 422 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
0650a2e5 423 }
727c62dd 424
425 /* Work out a value for MOVE_RATIO. */
426 if (!TARGET_H8300SX)
427 {
428 /* Memory-memory moves are quite expensive without the
429 h8sx instructions. */
430 h8300_move_ratio = 3;
431 }
432 else if (flag_omit_frame_pointer)
433 {
434 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
435 sometimes be as short as two individual memory-to-memory moves,
436 but since they use all the call-saved registers, it seems better
437 to allow up to three moves here. */
438 h8300_move_ratio = 4;
439 }
440 else if (optimize_size)
441 {
442 /* In this case we don't use movmd sequences since they tend
443 to be longer than calls to memcpy(). Memory-to-memory
444 moves are cheaper than for !TARGET_H8300SX, so it makes
445 sense to have a slightly higher threshold. */
446 h8300_move_ratio = 4;
447 }
448 else
449 {
450 /* We use movmd sequences for some moves since it can be quicker
451 than calling memcpy(). The sequences will need to save and
452 restore er6 though, so bump up the cost. */
453 h8300_move_ratio = 6;
454 }
1af17d44 455
456 /* This target defaults to strict volatile bitfields. */
941a2396 457 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
1af17d44 458 flag_strict_volatile_bitfields = 1;
727c62dd 459}
460
cdfb02e8 461/* Return the byte register name for a register rtx X. B should be 0
462 if you want a lower byte register. B should be 1 if you want an
463 upper byte register. */
464
7198848c 465static const char *
230002f2 466byte_reg (rtx x, int b)
e1629549 467{
ded3e58c 468 static const char *const names_small[] = {
469 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
470 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
471 };
e1629549 472
3afe906b 473 gcc_assert (REG_P (x));
589b6991 474
e1629549 475 return names_small[REGNO (x) * 2 + b];
476}
477
478/* REGNO must be saved/restored across calls if this macro is true. */
b839e0b4 479
ded3e58c 480#define WORD_REG_USED(regno) \
b91522ff 481 (regno < SP_REG \
ded3e58c 482 /* No need to save registers if this function will not return. */ \
483 && ! TREE_THIS_VOLATILE (current_function_decl) \
5344805f 484 && (h8300_saveall_function_p (current_function_decl) \
ded3e58c 485 /* Save any call saved register that was used. */ \
3072d30e 486 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
ded3e58c 487 /* Save the frame pointer if it was used. */ \
3072d30e 488 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
ded3e58c 489 /* Save any register used in an interrupt handler. */ \
41ed3bcd 490 || (h8300_current_function_interrupt_function_p () \
3072d30e 491 && df_regs_ever_live_p (regno)) \
ded3e58c 492 /* Save call clobbered registers in non-leaf interrupt \
493 handlers. */ \
41ed3bcd 494 || (h8300_current_function_interrupt_function_p () \
ded3e58c 495 && call_used_regs[regno] \
d5bf7b64 496 && !crtl->is_leaf)))
e1629549 497
80c13943 498/* We use this to wrap all emitted insns in the prologue. */
1a1ed145 499static rtx_insn *
500F (rtx_insn *x, bool set_it)
80c13943 501{
5da0dad2 502 if (set_it)
503 RTX_FRAME_RELATED_P (x) = 1;
80c13943 504 return x;
505}
506
507/* Mark all the subexpressions of the PARALLEL rtx PAR as
508 frame-related. Return PAR.
509
510 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
511 PARALLEL rtx other than the first if they do not have the
512 FRAME_RELATED flag set on them. */
513static rtx
514Fpa (rtx par)
515{
516 int len = XVECLEN (par, 0);
517 int i;
518
519 for (i = 0; i < len; i++)
7a5fbc9c 520 RTX_FRAME_RELATED_P (XVECEXP (par, 0, i)) = 1;
80c13943 521
522 return par;
523}
524
e1629549 525/* Output assembly language to FILE for the operation OP with operand size
b839e0b4 526 SIZE to adjust the stack pointer. */
b839e0b4 527
e1629549 528static void
5da0dad2 529h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue)
e1629549 530{
921a6571 531 /* If the frame size is 0, we don't have anything to do. */
532 if (size == 0)
a3dedda8 533 return;
921a6571 534
8f260b97 535 /* H8/300 cannot add/subtract a large constant with a single
536 instruction. If a temporary register is available, load the
537 constant to it and then do the addition. */
538 if (TARGET_H8300
539 && size > 4
540 && !h8300_current_function_interrupt_function_p ()
4ee9c684 541 && !(cfun->static_chain_decl != NULL && sign < 0))
b9393aaf 542 {
8f260b97 543 rtx r3 = gen_rtx_REG (Pmode, 3);
5da0dad2 544 F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue);
80c13943 545 F (emit_insn (gen_addhi3 (stack_pointer_rtx,
5da0dad2 546 stack_pointer_rtx, r3)), in_prologue);
bfc1492f 547 }
548 else
549 {
8f260b97 550 /* The stack adjustment made here is further optimized by the
551 splitter. In case of H8/300, the splitter always splits the
80c13943 552 addition emitted here to make the adjustment interrupt-safe.
553 FIXME: We don't always tag those, because we don't know what
554 the splitter will do. */
921a6571 555 if (Pmode == HImode)
80c13943 556 {
1a1ed145 557 rtx_insn *x = emit_insn (gen_addhi3 (stack_pointer_rtx,
558 stack_pointer_rtx,
559 GEN_INT (sign * size)));
80c13943 560 if (size < 4)
5da0dad2 561 F (x, in_prologue);
80c13943 562 }
921a6571 563 else
80c13943 564 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
5da0dad2 565 stack_pointer_rtx, GEN_INT (sign * size))), in_prologue);
e1629549 566 }
567}
568
b1292c73 569/* Round up frame size SIZE. */
570
959e2f12 571static HOST_WIDE_INT
572round_frame_size (HOST_WIDE_INT size)
b1292c73 573{
b25ffd74 574 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
575 & -STACK_BOUNDARY / BITS_PER_UNIT);
b1292c73 576}
577
578/* Compute which registers to push/pop.
579 Return a bit vector of registers. */
580
581static unsigned int
230002f2 582compute_saved_regs (void)
b1292c73 583{
584 unsigned int saved_regs = 0;
585 int regno;
586
587 /* Construct a bit vector of registers to be pushed/popped. */
f4ac50fb 588 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
b1292c73 589 {
590 if (WORD_REG_USED (regno))
591 saved_regs |= 1 << regno;
592 }
593
594 /* Don't push/pop the frame pointer as it is treated separately. */
595 if (frame_pointer_needed)
f4ac50fb 596 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
b1292c73 597
598 return saved_regs;
599}
600
8f260b97 601/* Emit an insn to push register RN. */
b1292c73 602
a5c6cfdd 603static rtx
42231db5 604push (int rn, bool in_prologue)
b1292c73 605{
8f260b97 606 rtx reg = gen_rtx_REG (word_mode, rn);
607 rtx x;
608
4081a531 609 if (TARGET_H8300)
8f260b97 610 x = gen_push_h8300 (reg);
c99597ba 611 else if (!TARGET_NORMAL_MODE)
34712114 612 x = gen_push_h8300hs_advanced (reg);
c99597ba 613 else
614 x = gen_push_h8300hs_normal (reg);
42231db5 615 x = F (emit_insn (x), in_prologue);
539b539f 616 add_reg_note (x, REG_INC, stack_pointer_rtx);
a5c6cfdd 617 return x;
b1292c73 618}
619
8f260b97 620/* Emit an insn to pop register RN. */
b1292c73 621
a5c6cfdd 622static rtx
230002f2 623pop (int rn)
b1292c73 624{
8f260b97 625 rtx reg = gen_rtx_REG (word_mode, rn);
626 rtx x;
627
4081a531 628 if (TARGET_H8300)
8f260b97 629 x = gen_pop_h8300 (reg);
c99597ba 630 else if (!TARGET_NORMAL_MODE)
34712114 631 x = gen_pop_h8300hs_advanced (reg);
c99597ba 632 else
633 x = gen_pop_h8300hs_normal (reg);
8f260b97 634 x = emit_insn (x);
539b539f 635 add_reg_note (x, REG_INC, stack_pointer_rtx);
a5c6cfdd 636 return x;
b1292c73 637}
e1629549 638
727c62dd 639/* Emit an instruction to push or pop NREGS consecutive registers
640 starting at register REGNO. POP_P selects a pop rather than a
641 push and RETURN_P is true if the instruction should return.
642
643 It must be possible to do the requested operation in a single
644 instruction. If NREGS == 1 && !RETURN_P, use a normal push
645 or pop insn. Otherwise emit a parallel of the form:
646
647 (parallel
648 [(return) ;; if RETURN_P
649 (save or restore REGNO)
650 (save or restore REGNO + 1)
651 ...
652 (save or restore REGNO + NREGS - 1)
653 (set sp (plus sp (const_int adjust)))] */
654
655static void
5a23ee68 656h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p)
727c62dd 657{
658 int i, j;
659 rtvec vec;
80c13943 660 rtx sp, offset, x;
727c62dd 661
662 /* See whether we can use a simple push or pop. */
663 if (!return_p && nregs == 1)
664 {
665 if (pop_p)
666 pop (regno);
667 else
42231db5 668 push (regno, false);
727c62dd 669 return;
670 }
671
672 /* We need one element for the return insn, if present, one for each
673 register, and one for stack adjustment. */
5a23ee68 674 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1);
727c62dd 675 sp = stack_pointer_rtx;
676 i = 0;
677
678 /* Add the return instruction. */
679 if (return_p)
680 {
1a860023 681 RTVEC_ELT (vec, i) = ret_rtx;
727c62dd 682 i++;
683 }
684
685 /* Add the register moves. */
686 for (j = 0; j < nregs; j++)
687 {
688 rtx lhs, rhs;
689
690 if (pop_p)
691 {
692 /* Register REGNO + NREGS - 1 is popped first. Before the
693 stack adjustment, its slot is at address @sp. */
694 lhs = gen_rtx_REG (SImode, regno + j);
29c05e22 695 rhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp,
696 (nregs - j - 1) * 4));
727c62dd 697 }
698 else
699 {
700 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
29c05e22 701 lhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, (j + 1) * -4));
727c62dd 702 rhs = gen_rtx_REG (SImode, regno + j);
703 }
d1f9b275 704 RTVEC_ELT (vec, i + j) = gen_rtx_SET (lhs, rhs);
727c62dd 705 }
706
707 /* Add the stack adjustment. */
708 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
d1f9b275 709 RTVEC_ELT (vec, i + j) = gen_rtx_SET (sp, gen_rtx_PLUS (Pmode, sp, offset));
727c62dd 710
80c13943 711 x = gen_rtx_PARALLEL (VOIDmode, vec);
712 if (!pop_p)
713 x = Fpa (x);
5a23ee68 714
715 if (return_p)
716 emit_jump_insn (x);
717 else
718 emit_insn (x);
727c62dd 719}
720
721/* Return true if X has the value sp + OFFSET. */
722
723static int
724h8300_stack_offset_p (rtx x, int offset)
725{
726 if (offset == 0)
727 return x == stack_pointer_rtx;
728
729 return (GET_CODE (x) == PLUS
730 && XEXP (x, 0) == stack_pointer_rtx
731 && GET_CODE (XEXP (x, 1)) == CONST_INT
732 && INTVAL (XEXP (x, 1)) == offset);
733}
734
735/* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
736 something that may be an ldm or stm instruction. If it fits
737 the required template, return the register it loads or stores,
738 otherwise return -1.
739
740 LOAD_P is true if X should be a load, false if it should be a store.
741 NREGS is the number of registers that the whole instruction is expected
742 to load or store. INDEX is the index of the register that X should
743 load or store, relative to the lowest-numbered register. */
744
745static int
746h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
747{
748 int regindex, memindex, offset;
749
750 if (load_p)
751 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
752 else
753 memindex = 0, regindex = 1, offset = (index + 1) * -4;
754
755 if (GET_CODE (x) == SET
756 && GET_CODE (XEXP (x, regindex)) == REG
757 && GET_CODE (XEXP (x, memindex)) == MEM
758 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
759 return REGNO (XEXP (x, regindex));
760
761 return -1;
762}
763
764/* Return true if the elements of VEC starting at FIRST describe an
765 ldm or stm instruction (LOAD_P says which). */
766
d255713c 767int
727c62dd 768h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
769{
770 rtx last;
771 int nregs, i, regno, adjust;
772
773 /* There must be a stack adjustment, a register move, and at least one
774 other operation (a return or another register move). */
775 if (GET_NUM_ELEM (vec) < 3)
776 return false;
777
778 /* Get the range of registers to be pushed or popped. */
779 nregs = GET_NUM_ELEM (vec) - first - 1;
780 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
781
782 /* Check that the call to h8300_ldm_stm_regno succeeded and
783 that we're only dealing with GPRs. */
784 if (regno < 0 || regno + nregs > 8)
785 return false;
786
787 /* 2-register h8s instructions must start with an even-numbered register.
788 3- and 4-register instructions must start with er0 or er4. */
789 if (!TARGET_H8300SX)
790 {
791 if ((regno & 1) != 0)
792 return false;
793 if (nregs > 2 && (regno & 3) != 0)
794 return false;
795 }
796
797 /* Check the other loads or stores. */
798 for (i = 1; i < nregs; i++)
799 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
800 != regno + i)
801 return false;
802
803 /* Check the stack adjustment. */
804 last = RTVEC_ELT (vec, first + nregs);
805 adjust = (load_p ? nregs : -nregs) * 4;
806 return (GET_CODE (last) == SET
807 && SET_DEST (last) == stack_pointer_rtx
808 && h8300_stack_offset_p (SET_SRC (last), adjust));
809}
810
f2702e8a 811/* This is what the stack looks like after the prolog of
e1629549 812 a function with a frame has been set up:
813
b839e0b4 814 <args>
815 PC
816 FP <- fp
817 <locals>
9f56f86b 818 <saved registers> <- sp
e1629549 819
820 This is what the stack looks like after the prolog of
821 a function which doesn't have a frame:
822
b839e0b4 823 <args>
824 PC
825 <locals>
9f56f86b 826 <saved registers> <- sp
e1629549 827*/
828
8f260b97 829/* Generate RTL code for the function prologue. */
b1292c73 830
8f260b97 831void
230002f2 832h8300_expand_prologue (void)
e1629549 833{
b2adb3e0 834 int regno;
b1292c73 835 int saved_regs;
97709d8d 836 int n_regs;
e1629549 837
09c48b9c 838 /* If the current function has the OS_Task attribute set, then
839 we have a naked prologue. */
840 if (h8300_os_task_function_p (current_function_decl))
8f260b97 841 return;
09c48b9c 842
843 if (h8300_monitor_function_p (current_function_decl))
d3677aa8 844 /* The monitor function act as normal functions, which means it
845 can accept parameters and return values. In addition to this,
846 interrupts are masked in prologue and return with "rte" in epilogue. */
8f260b97 847 emit_insn (gen_monitor_prologue ());
09c48b9c 848
b839e0b4 849 if (frame_pointer_needed)
850 {
eb2aa24e 851 /* Push fp. */
42231db5 852 push (HARD_FRAME_POINTER_REGNUM, true);
5a23ee68 853 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true);
69b4e418 854 }
b839e0b4 855
b1292c73 856 /* Push the rest of the registers in ascending order. */
857 saved_regs = compute_saved_regs ();
b2adb3e0 858 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
97709d8d 859 {
97709d8d 860 n_regs = 1;
b1292c73 861 if (saved_regs & (1 << regno))
69b4e418 862 {
863 if (TARGET_H8300S)
864 {
97709d8d 865 /* See how many registers we can push at the same time. */
727c62dd 866 if ((!TARGET_H8300SX || (regno & 3) == 0)
b1292c73 867 && ((saved_regs >> regno) & 0x0f) == 0x0f)
97709d8d 868 n_regs = 4;
869
727c62dd 870 else if ((!TARGET_H8300SX || (regno & 3) == 0)
b1292c73 871 && ((saved_regs >> regno) & 0x07) == 0x07)
97709d8d 872 n_regs = 3;
873
727c62dd 874 else if ((!TARGET_H8300SX || (regno & 1) == 0)
b1292c73 875 && ((saved_regs >> regno) & 0x03) == 0x03)
97709d8d 876 n_regs = 2;
69b4e418 877 }
97709d8d 878
5a23ee68 879 h8300_push_pop (regno, n_regs, false, false);
e1629549 880 }
881 }
f4ac50fb 882
883 /* Leave room for locals. */
5da0dad2 884 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
cc16f5e2 885
886 if (flag_stack_usage_info)
887 current_function_static_stack_size
888 = round_frame_size (get_frame_size ())
889 + (__builtin_popcount (saved_regs) * UNITS_PER_WORD)
890 + (frame_pointer_needed ? UNITS_PER_WORD : 0);
e1629549 891}
892
cdfb02e8 893/* Return nonzero if we can use "rts" for the function currently being
894 compiled. */
895
8f260b97 896int
230002f2 897h8300_can_use_return_insn_p (void)
8f260b97 898{
899 return (reload_completed
900 && !frame_pointer_needed
901 && get_frame_size () == 0
902 && compute_saved_regs () == 0);
903}
e1629549 904
8f260b97 905/* Generate RTL code for the function epilogue. */
906
907void
230002f2 908h8300_expand_epilogue (void)
e1629549 909{
b2adb3e0 910 int regno;
b1292c73 911 int saved_regs;
97709d8d 912 int n_regs;
727c62dd 913 HOST_WIDE_INT frame_size;
914 bool returned_p;
e1629549 915
41ed3bcd 916 if (h8300_os_task_function_p (current_function_decl))
8f260b97 917 /* OS_Task epilogues are nearly naked -- they just have an
918 rts instruction. */
919 return;
e1629549 920
727c62dd 921 frame_size = round_frame_size (get_frame_size ());
922 returned_p = false;
923
f4ac50fb 924 /* Deallocate locals. */
5da0dad2 925 h8300_emit_stack_adjustment (1, frame_size, false);
f4ac50fb 926
b1292c73 927 /* Pop the saved registers in descending order. */
928 saved_regs = compute_saved_regs ();
b2adb3e0 929 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
97709d8d 930 {
97709d8d 931 n_regs = 1;
b1292c73 932 if (saved_regs & (1 << regno))
e1629549 933 {
69b4e418 934 if (TARGET_H8300S)
935 {
97709d8d 936 /* See how many registers we can pop at the same time. */
727c62dd 937 if ((TARGET_H8300SX || (regno & 3) == 3)
938 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
97709d8d 939 n_regs = 4;
940
727c62dd 941 else if ((TARGET_H8300SX || (regno & 3) == 2)
942 && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
97709d8d 943 n_regs = 3;
944
727c62dd 945 else if ((TARGET_H8300SX || (regno & 1) == 1)
946 && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
97709d8d 947 n_regs = 2;
69b4e418 948 }
97709d8d 949
727c62dd 950 /* See if this pop would be the last insn before the return.
951 If so, use rte/l or rts/l instead of pop or ldm.l. */
952 if (TARGET_H8300SX
953 && !frame_pointer_needed
954 && frame_size == 0
955 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
956 returned_p = true;
957
5a23ee68 958 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p);
e1629549 959 }
e1629549 960 }
b839e0b4 961
eb2aa24e 962 /* Pop frame pointer if we had one. */
69b4e418 963 if (frame_pointer_needed)
727c62dd 964 {
965 if (TARGET_H8300SX)
966 returned_p = true;
5a23ee68 967 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p);
727c62dd 968 }
969
970 if (!returned_p)
1a860023 971 emit_jump_insn (ret_rtx);
8f260b97 972}
69b4e418 973
41ed3bcd 974/* Return nonzero if the current function is an interrupt
975 function. */
976
977int
230002f2 978h8300_current_function_interrupt_function_p (void)
41ed3bcd 979{
d3677aa8 980 return (h8300_interrupt_function_p (current_function_decl));
981}
982
983int
984h8300_current_function_monitor_function_p ()
985{
986 return (h8300_monitor_function_p (current_function_decl));
41ed3bcd 987}
988
b839e0b4 989/* Output assembly code for the start of the file. */
990
92c473b8 991static void
992h8300_file_start (void)
b839e0b4 993{
92c473b8 994 default_file_start ();
9f56f86b 995
acff2768 996 if (TARGET_H8300SX)
727c62dd 997 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
69b4e418 998 else if (TARGET_H8300S)
92c473b8 999 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
acff2768 1000 else if (TARGET_H8300H)
1001 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
b839e0b4 1002}
1003
1004/* Output assembly language code for the end of file. */
1005
f6940372 1006static void
230002f2 1007h8300_file_end (void)
b839e0b4 1008{
f6940372 1009 fputs ("\t.end\n", asm_out_file);
e1629549 1010}
1011\f
c5673261 1012/* Split an add of a small constant into two adds/subs insns.
1013
1014 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1015 instead of adds/subs. */
8e7d5182 1016
1017void
3754d046 1018split_adds_subs (machine_mode mode, rtx *operands)
0a56558f 1019{
8e7d5182 1020 HOST_WIDE_INT val = INTVAL (operands[1]);
1021 rtx reg = operands[0];
d8afbfc6 1022 HOST_WIDE_INT sign = 1;
1023 HOST_WIDE_INT amount;
90b024e5 1024 rtx (*gen_add) (rtx, rtx, rtx);
0a56558f 1025
d8afbfc6 1026 /* Force VAL to be positive so that we do not have to consider the
1027 sign. */
1028 if (val < 0)
0a56558f 1029 {
d8afbfc6 1030 val = -val;
1031 sign = -1;
1032 }
0a56558f 1033
c5673261 1034 switch (mode)
1035 {
916ace94 1036 case E_HImode:
90b024e5 1037 gen_add = gen_addhi3;
c5673261 1038 break;
1039
916ace94 1040 case E_SImode:
90b024e5 1041 gen_add = gen_addsi3;
c5673261 1042 break;
1043
1044 default:
3afe906b 1045 gcc_unreachable ();
c5673261 1046 }
1047
d8afbfc6 1048 /* Try different amounts in descending order. */
1049 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
1050 amount > 0;
1051 amount /= 2)
1052 {
27276a3b 1053 for (; val >= amount; val -= amount)
90b024e5 1054 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
0a56558f 1055 }
1056
d8afbfc6 1057 return;
0a56558f 1058}
1059
e1629549 1060/* Handle machine specific pragmas for compatibility with existing
b839e0b4 1061 compilers for the H8/300.
e1629549 1062
cc72e60a 1063 pragma saveall generates prologue/epilogue code which saves and
e1629549 1064 restores all the registers on function entry.
b839e0b4 1065
e1629549 1066 pragma interrupt saves and restores all registers, and exits with
1067 an rte instruction rather than an rts. A pointer to a function
1068 with this attribute may be safely used in an interrupt vector. */
b839e0b4 1069
1fcd08b1 1070void
230002f2 1071h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
e1629549 1072{
41ed3bcd 1073 pragma_interrupt = 1;
1fcd08b1 1074}
b97b38c0 1075
1fcd08b1 1076void
230002f2 1077h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1fcd08b1 1078{
1079 pragma_saveall = 1;
e1629549 1080}
1fcd08b1 1081
c738c371 1082/* If the next function argument with MODE and TYPE is to be passed in
1083 a register, return a reg RTX for the hard register in which to pass
1084 the argument. CUM represents the state after the last argument.
e7489b8b 1085 If the argument is to be pushed, NULL_RTX is returned.
b839e0b4 1086
e7489b8b 1087 On the H8/300 all normal args are pushed, unless -mquickcall in which
1088 case the first 3 arguments are passed in registers. */
1089
1090static rtx
3754d046 1091h8300_function_arg (cumulative_args_t cum_v, machine_mode mode,
e7489b8b 1092 const_tree type, bool named)
e1629549 1093{
39cba157 1094 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1095
70a21926 1096 static const char *const hand_list[] = {
1097 "__main",
1098 "__cmpsi2",
1099 "__divhi3",
1100 "__modhi3",
1101 "__udivhi3",
1102 "__umodhi3",
1103 "__divsi3",
1104 "__modsi3",
1105 "__udivsi3",
1106 "__umodsi3",
1107 "__mulhi3",
1108 "__mulsi3",
1109 "__reg_memcpy",
1110 "__reg_memset",
1111 "__ucmpsi2",
1112 0,
1113 };
1114
6996dd46 1115 rtx result = NULL_RTX;
9305fe33 1116 const char *fname;
b839e0b4 1117 int regpass = 0;
1118
0d37f3a1 1119 /* Never pass unnamed arguments in registers. */
1120 if (!named)
6996dd46 1121 return NULL_RTX;
0d37f3a1 1122
b839e0b4 1123 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1124 if (TARGET_QUICKCALL)
1125 regpass = 3;
1126
1127 /* If calling hand written assembler, use 4 regs of args. */
b839e0b4 1128 if (cum->libcall)
1129 {
9305fe33 1130 const char * const *p;
b839e0b4 1131
1132 fname = XSTR (cum->libcall, 0);
1133
1134 /* See if this libcall is one of the hand coded ones. */
b839e0b4 1135 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1136 ;
e1629549 1137
b839e0b4 1138 if (*p)
1139 regpass = 4;
1140 }
1141
1142 if (regpass)
1143 {
1144 int size;
1145
1146 if (mode == BLKmode)
1147 size = int_size_in_bytes (type);
1148 else
1149 size = GET_MODE_SIZE (mode);
1150
60ff2ea8 1151 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1152 && cum->nbytes / UNITS_PER_WORD <= 3)
1153 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
b839e0b4 1154 }
e1629549 1155
b839e0b4 1156 return result;
1157}
e7489b8b 1158
1159/* Update the data in CUM to advance over an argument
1160 of mode MODE and data type TYPE.
1161 (TYPE is null for libcalls where that information may not be available.) */
1162
1163static void
3754d046 1164h8300_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
e7489b8b 1165 const_tree type, bool named ATTRIBUTE_UNUSED)
1166{
39cba157 1167 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1168
e7489b8b 1169 cum->nbytes += (mode != BLKmode
1170 ? (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD
1171 : (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD);
1172}
1173
b839e0b4 1174\f
87ad9aff 1175/* Implements TARGET_REGISTER_MOVE_COST.
1176
1177 Any SI register-to-register move may need to be reloaded,
1178 so inmplement h8300_register_move_cost to return > 2 so that reload never
1179 shortcuts. */
1180
1181static int
3754d046 1182h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
87ad9aff 1183 reg_class_t from, reg_class_t to)
1184{
1185 if (from == MAC_REGS || to == MAC_REG)
1186 return 6;
1187 else
1188 return 3;
1189}
1190
cdfb02e8 1191/* Compute the cost of an and insn. */
1192
fab7adbf 1193static int
230002f2 1194h8300_and_costs (rtx x)
b785ceb4 1195{
1196 rtx operands[4];
1197
1198 if (GET_MODE (x) == QImode)
1199 return 1;
1200
1201 if (GET_MODE (x) != HImode
1202 && GET_MODE (x) != SImode)
1203 return 100;
1204
1205 operands[0] = NULL;
727c62dd 1206 operands[1] = XEXP (x, 0);
b785ceb4 1207 operands[2] = XEXP (x, 1);
1208 operands[3] = x;
5a622ac3 1209 return compute_logical_op_length (GET_MODE (x), operands) / 2;
b785ceb4 1210}
1211
cdfb02e8 1212/* Compute the cost of a shift insn. */
1213
fab7adbf 1214static int
230002f2 1215h8300_shift_costs (rtx x)
c033ada4 1216{
1217 rtx operands[4];
1218
1219 if (GET_MODE (x) != QImode
1220 && GET_MODE (x) != HImode
1221 && GET_MODE (x) != SImode)
1222 return 100;
1223
1224 operands[0] = NULL;
1225 operands[1] = NULL;
1226 operands[2] = XEXP (x, 1);
1227 operands[3] = x;
5a622ac3 1228 return compute_a_shift_length (NULL, operands) / 2;
c033ada4 1229}
fab7adbf 1230
cdfb02e8 1231/* Worker function for TARGET_RTX_COSTS. */
1232
fab7adbf 1233static bool
5ae4887d 1234h8300_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code,
1235 int opno ATTRIBUTE_UNUSED, int *total, bool speed)
fab7adbf 1236{
5ae4887d 1237 int code = GET_CODE (x);
1238
727c62dd 1239 if (TARGET_H8300SX && outer_code == MEM)
1240 {
1241 /* Estimate the number of execution states needed to calculate
1242 the address. */
1243 if (register_operand (x, VOIDmode)
1244 || GET_CODE (x) == POST_INC
1245 || GET_CODE (x) == POST_DEC
1246 || CONSTANT_P (x))
1247 *total = 0;
1248 else
1249 *total = COSTS_N_INSNS (1);
1250 return true;
1251 }
1252
fab7adbf 1253 switch (code)
1254 {
1d6dae88 1255 case CONST_INT:
1256 {
1257 HOST_WIDE_INT n = INTVAL (x);
1258
727c62dd 1259 if (TARGET_H8300SX)
1260 {
1261 /* Constant operands need the same number of processor
1262 states as register operands. Although we could try to
f529eb25 1263 use a size-based cost for !speed, the lack of
727c62dd 1264 of a mode makes the results very unpredictable. */
1265 *total = 0;
1266 return true;
1267 }
6b5c1012 1268 if (-4 <= n && n <= 4)
1d6dae88 1269 {
1270 switch ((int) n)
1271 {
1272 case 0:
1273 *total = 0;
1274 return true;
1275 case 1:
1276 case 2:
1277 case -1:
1278 case -2:
1279 *total = 0 + (outer_code == SET);
1280 return true;
1281 case 4:
1282 case -4:
1283 if (TARGET_H8300H || TARGET_H8300S)
1284 *total = 0 + (outer_code == SET);
1285 else
1286 *total = 1;
1287 return true;
1288 }
1289 }
1290 *total = 1;
1291 return true;
1292 }
1293
1294 case CONST:
1295 case LABEL_REF:
1296 case SYMBOL_REF:
727c62dd 1297 if (TARGET_H8300SX)
1298 {
1299 /* See comment for CONST_INT. */
1300 *total = 0;
1301 return true;
1302 }
1d6dae88 1303 *total = 3;
1304 return true;
1305
1306 case CONST_DOUBLE:
1307 *total = 20;
1308 return true;
1309
74f4459c 1310 case COMPARE:
1311 if (XEXP (x, 1) == const0_rtx)
1312 *total = 0;
1313 return false;
1314
fab7adbf 1315 case AND:
727c62dd 1316 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
1317 || !h8300_src_operand (XEXP (x, 1), VOIDmode))
1318 return false;
fab7adbf 1319 *total = COSTS_N_INSNS (h8300_and_costs (x));
1320 return true;
1321
1322 /* We say that MOD and DIV are so expensive because otherwise we'll
1323 generate some really horrible code for division of a power of two. */
1324 case MOD:
1325 case DIV:
727c62dd 1326 case UMOD:
1327 case UDIV:
1328 if (TARGET_H8300SX)
1329 switch (GET_MODE (x))
1330 {
916ace94 1331 case E_QImode:
1332 case E_HImode:
f529eb25 1333 *total = COSTS_N_INSNS (!speed ? 4 : 10);
727c62dd 1334 return false;
1335
916ace94 1336 case E_SImode:
f529eb25 1337 *total = COSTS_N_INSNS (!speed ? 4 : 18);
727c62dd 1338 return false;
1339
1340 default:
1341 break;
1342 }
1343 *total = COSTS_N_INSNS (12);
fab7adbf 1344 return true;
1345
1346 case MULT:
727c62dd 1347 if (TARGET_H8300SX)
1348 switch (GET_MODE (x))
1349 {
916ace94 1350 case E_QImode:
1351 case E_HImode:
727c62dd 1352 *total = COSTS_N_INSNS (2);
1353 return false;
1354
916ace94 1355 case E_SImode:
727c62dd 1356 *total = COSTS_N_INSNS (5);
1357 return false;
1358
1359 default:
1360 break;
1361 }
1362 *total = COSTS_N_INSNS (4);
fab7adbf 1363 return true;
1364
1365 case ASHIFT:
1366 case ASHIFTRT:
1367 case LSHIFTRT:
727c62dd 1368 if (h8sx_binary_shift_operator (x, VOIDmode))
1369 {
1370 *total = COSTS_N_INSNS (2);
1371 return false;
1372 }
1373 else if (h8sx_unary_shift_operator (x, VOIDmode))
1374 {
1375 *total = COSTS_N_INSNS (1);
1376 return false;
1377 }
fab7adbf 1378 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1379 return true;
1380
1381 case ROTATE:
1382 case ROTATERT:
1383 if (GET_MODE (x) == HImode)
1384 *total = 2;
1385 else
1386 *total = 8;
1387 return true;
1388
1389 default:
727c62dd 1390 *total = COSTS_N_INSNS (1);
1391 return false;
fab7adbf 1392 }
1393}
b839e0b4 1394\f
e1629549 1395/* Documentation for the machine specific operand escapes:
1396
b839e0b4 1397 'E' like s but negative.
1398 'F' like t but negative.
1399 'G' constant just the negative
2c7be643 1400 'R' print operand as a byte:8 address if appropriate, else fall back to
1401 'X' handling.
b839e0b4 1402 'S' print operand as a long word
e1629549 1403 'T' print operand as a word
b839e0b4 1404 'V' find the set bit, and print its number.
1405 'W' find the clear bit, and print its number.
1406 'X' print operand as a byte
e1629549 1407 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
2c7be643 1408 If this operand isn't a register, fall back to 'R' handling.
b839e0b4 1409 'Z' print int & 7.
4c924258 1410 'c' print the opcode corresponding to rtl
03fb0c81 1411 'e' first word of 32-bit value - if reg, then least reg. if mem
b839e0b4 1412 then least. if const then most sig word
03fb0c81 1413 'f' second word of 32-bit value - if reg, then biggest reg. if mem
b839e0b4 1414 then +2. if const then least sig word
e1629549 1415 'j' print operand as condition code.
1416 'k' print operand as reverse condition code.
727c62dd 1417 'm' convert an integer operand to a size suffix (.b, .w or .l)
1418 'o' print an integer without a leading '#'
03fb0c81 1419 's' print as low byte of 16-bit value
1420 't' print as high byte of 16-bit value
1421 'w' print as low byte of 32-bit value
1422 'x' print as 2nd byte of 32-bit value
1423 'y' print as 3rd byte of 32-bit value
1424 'z' print as msb of 32-bit value
b839e0b4 1425*/
e1629549 1426
1427/* Return assembly language string which identifies a comparison type. */
1428
9305fe33 1429static const char *
230002f2 1430cond_string (enum rtx_code code)
e1629549 1431{
1432 switch (code)
1433 {
1434 case NE:
1435 return "ne";
1436 case EQ:
1437 return "eq";
1438 case GE:
1439 return "ge";
1440 case GT:
1441 return "gt";
1442 case LE:
1443 return "le";
1444 case LT:
1445 return "lt";
1446 case GEU:
1447 return "hs";
1448 case GTU:
1449 return "hi";
1450 case LEU:
1451 return "ls";
1452 case LTU:
1453 return "lo";
1454 default:
3afe906b 1455 gcc_unreachable ();
e1629549 1456 }
1457}
1458
1459/* Print operand X using operand code CODE to assembly language output file
1460 FILE. */
1461
87ad9aff 1462static void
1463h8300_print_operand (FILE *file, rtx x, int code)
e1629549 1464{
30c992ef 1465 /* This is used for communication between codes V,W,Z and Y. */
e1629549 1466 static int bitint;
1467
1468 switch (code)
1469 {
3d835ed7 1470 case 'C':
1471 if (h8300_constant_length (x) == 2)
1472 fprintf (file, ":16");
1473 else
1474 fprintf (file, ":32");
1475 return;
b839e0b4 1476 case 'E':
1477 switch (GET_CODE (x))
1478 {
1479 case REG:
1480 fprintf (file, "%sl", names_big[REGNO (x)]);
1481 break;
1482 case CONST_INT:
21650cc9 1483 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
b839e0b4 1484 break;
1485 default:
3afe906b 1486 gcc_unreachable ();
b839e0b4 1487 }
1488 break;
1489 case 'F':
1490 switch (GET_CODE (x))
1491 {
1492 case REG:
1493 fprintf (file, "%sh", names_big[REGNO (x)]);
1494 break;
1495 case CONST_INT:
21650cc9 1496 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
b839e0b4 1497 break;
1498 default:
3afe906b 1499 gcc_unreachable ();
b839e0b4 1500 }
1501 break;
e1629549 1502 case 'G':
3afe906b 1503 gcc_assert (GET_CODE (x) == CONST_INT);
21650cc9 1504 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
e1629549 1505 break;
b839e0b4 1506 case 'S':
1507 if (GET_CODE (x) == REG)
1508 fprintf (file, "%s", names_extended[REGNO (x)]);
e1629549 1509 else
b839e0b4 1510 goto def;
e1629549 1511 break;
b839e0b4 1512 case 'T':
1513 if (GET_CODE (x) == REG)
1514 fprintf (file, "%s", names_big[REGNO (x)]);
e1629549 1515 else
b839e0b4 1516 goto def;
e1629549 1517 break;
b839e0b4 1518 case 'V':
cfdcbbf4 1519 bitint = (INTVAL (x) & 0xffff);
1520 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1)
1521 bitint = exact_log2 (bitint & 0xff);
1522 else
1523 bitint = exact_log2 ((bitint >> 8) & 0xff);
3afe906b 1524 gcc_assert (bitint >= 0);
3a59a065 1525 fprintf (file, "#%d", bitint);
e1629549 1526 break;
b839e0b4 1527 case 'W':
cfdcbbf4 1528 bitint = ((~INTVAL (x)) & 0xffff);
1529 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 )
1530 bitint = exact_log2 (bitint & 0xff);
1531 else
1532 bitint = (exact_log2 ((bitint >> 8) & 0xff));
3afe906b 1533 gcc_assert (bitint >= 0);
3a59a065 1534 fprintf (file, "#%d", bitint);
e1629549 1535 break;
2c7be643 1536 case 'R':
b839e0b4 1537 case 'X':
1538 if (GET_CODE (x) == REG)
1539 fprintf (file, "%s", byte_reg (x, 0));
1540 else
1541 goto def;
1542 break;
1543 case 'Y':
3afe906b 1544 gcc_assert (bitint >= 0);
b839e0b4 1545 if (GET_CODE (x) == REG)
1546 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1547 else
87ad9aff 1548 h8300_print_operand (file, x, 'R');
b839e0b4 1549 bitint = -1;
1550 break;
1551 case 'Z':
1552 bitint = INTVAL (x);
e1629549 1553 fprintf (file, "#%d", bitint & 7);
1554 break;
4c924258 1555 case 'c':
1556 switch (GET_CODE (x))
1557 {
1558 case IOR:
1559 fprintf (file, "or");
1560 break;
1561 case XOR:
1562 fprintf (file, "xor");
1563 break;
77016b8f 1564 case AND:
1565 fprintf (file, "and");
1566 break;
4c924258 1567 default:
1568 break;
1569 }
1570 break;
e1629549 1571 case 'e':
1572 switch (GET_CODE (x))
1573 {
1574 case REG:
b839e0b4 1575 if (TARGET_H8300)
1576 fprintf (file, "%s", names_big[REGNO (x)]);
1577 else
1578 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
e1629549 1579 break;
1580 case MEM:
87ad9aff 1581 h8300_print_operand (file, x, 0);
e1629549 1582 break;
1583 case CONST_INT:
21650cc9 1584 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
e1629549 1585 break;
737a5d5b 1586 case CONST_DOUBLE:
1587 {
1588 long val;
945f7b03 1589 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val);
9305fe33 1590 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
737a5d5b 1591 break;
1592 }
e1629549 1593 default:
3afe906b 1594 gcc_unreachable ();
e1629549 1595 break;
1596 }
1597 break;
e1629549 1598 case 'f':
1599 switch (GET_CODE (x))
1600 {
1601 case REG:
b839e0b4 1602 if (TARGET_H8300)
1603 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1604 else
1605 fprintf (file, "%s", names_big[REGNO (x)]);
e1629549 1606 break;
e1629549 1607 case MEM:
eafc6604 1608 x = adjust_address (x, HImode, 2);
87ad9aff 1609 h8300_print_operand (file, x, 0);
e1629549 1610 break;
e1629549 1611 case CONST_INT:
21650cc9 1612 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
e1629549 1613 break;
737a5d5b 1614 case CONST_DOUBLE:
1615 {
1616 long val;
945f7b03 1617 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val);
9305fe33 1618 fprintf (file, "#%ld", (val & 0xffff));
737a5d5b 1619 break;
1620 }
e1629549 1621 default:
3afe906b 1622 gcc_unreachable ();
e1629549 1623 }
1624 break;
e1629549 1625 case 'j':
7fe1d31c 1626 fputs (cond_string (GET_CODE (x)), file);
e1629549 1627 break;
e1629549 1628 case 'k':
7fe1d31c 1629 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
e1629549 1630 break;
727c62dd 1631 case 'm':
3afe906b 1632 gcc_assert (GET_CODE (x) == CONST_INT);
1633 switch (INTVAL (x))
1634 {
1635 case 1:
1636 fputs (".b", file);
1637 break;
1638
1639 case 2:
1640 fputs (".w", file);
1641 break;
1642
1643 case 4:
1644 fputs (".l", file);
1645 break;
1646
1647 default:
1648 gcc_unreachable ();
1649 }
727c62dd 1650 break;
1651 case 'o':
3c047fe9 1652 h8300_print_operand_address (file, VOIDmode, x);
727c62dd 1653 break;
b839e0b4 1654 case 's':
1655 if (GET_CODE (x) == CONST_INT)
21650cc9 1656 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
b839e0b4 1657 else
1658 fprintf (file, "%s", byte_reg (x, 0));
1659 break;
1660 case 't':
1661 if (GET_CODE (x) == CONST_INT)
21650cc9 1662 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
b839e0b4 1663 else
1664 fprintf (file, "%s", byte_reg (x, 1));
1665 break;
b839e0b4 1666 case 'w':
1667 if (GET_CODE (x) == CONST_INT)
21650cc9 1668 fprintf (file, "#%ld", INTVAL (x) & 0xff);
b839e0b4 1669 else
69b4e418 1670 fprintf (file, "%s",
1671 byte_reg (x, TARGET_H8300 ? 2 : 0));
b839e0b4 1672 break;
1673 case 'x':
1674 if (GET_CODE (x) == CONST_INT)
21650cc9 1675 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
b839e0b4 1676 else
69b4e418 1677 fprintf (file, "%s",
1678 byte_reg (x, TARGET_H8300 ? 3 : 1));
b839e0b4 1679 break;
1680 case 'y':
1681 if (GET_CODE (x) == CONST_INT)
21650cc9 1682 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
b839e0b4 1683 else
1684 fprintf (file, "%s", byte_reg (x, 0));
1685 break;
1686 case 'z':
1687 if (GET_CODE (x) == CONST_INT)
21650cc9 1688 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
b839e0b4 1689 else
1690 fprintf (file, "%s", byte_reg (x, 1));
1691 break;
1692
e1629549 1693 default:
b839e0b4 1694 def:
e1629549 1695 switch (GET_CODE (x))
1696 {
1697 case REG:
b839e0b4 1698 switch (GET_MODE (x))
1699 {
916ace94 1700 case E_QImode:
30c992ef 1701#if 0 /* Is it asm ("mov.b %0,r2l", ...) */
b839e0b4 1702 fprintf (file, "%s", byte_reg (x, 0));
1703#else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1704 fprintf (file, "%s", names_big[REGNO (x)]);
1705#endif
1706 break;
916ace94 1707 case E_HImode:
b839e0b4 1708 fprintf (file, "%s", names_big[REGNO (x)]);
1709 break;
916ace94 1710 case E_SImode:
1711 case E_SFmode:
b839e0b4 1712 fprintf (file, "%s", names_extended[REGNO (x)]);
1713 break;
1714 default:
3afe906b 1715 gcc_unreachable ();
b839e0b4 1716 }
e1629549 1717 break;
1718
1719 case MEM:
b99f3ebb 1720 {
1721 rtx addr = XEXP (x, 0);
1722
1723 fprintf (file, "@");
3c047fe9 1724 output_address (GET_MODE (x), addr);
b99f3ebb 1725
727c62dd 1726 /* Add a length suffix to constant addresses. Although this
1727 is often unnecessary, it helps to avoid ambiguity in the
1728 syntax of mova. If we wrote an insn like:
1729
1730 mova/w.l @(1,@foo.b),er0
1731
1732 then .b would be considered part of the symbol name.
1733 Adding a length after foo will avoid this. */
1734 if (CONSTANT_P (addr))
1735 switch (code)
1736 {
1737 case 'R':
1738 /* Used for mov.b and bit operations. */
1739 if (h8300_eightbit_constant_address_p (addr))
1740 {
1741 fprintf (file, ":8");
1742 break;
1743 }
1744
64884a1b 1745 /* FALLTHRU */
1746
1747 /* We should not get here if we are processing bit
1748 operations on H8/300 or H8/300H because 'U'
1749 constraint does not allow bit operations on the
1750 tiny area on these machines. */
727c62dd 1751
1752 case 'X':
1753 case 'T':
1754 case 'S':
1755 if (h8300_constant_length (addr) == 2)
1756 fprintf (file, ":16");
1757 else
1758 fprintf (file, ":32");
1759 break;
1760 default:
1761 break;
1762 }
b99f3ebb 1763 }
e1629549 1764 break;
1765
1766 case CONST_INT:
1767 case SYMBOL_REF:
1768 case CONST:
1769 case LABEL_REF:
1770 fprintf (file, "#");
3c047fe9 1771 h8300_print_operand_address (file, VOIDmode, x);
e1629549 1772 break;
737a5d5b 1773 case CONST_DOUBLE:
1774 {
1775 long val;
945f7b03 1776 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val);
9305fe33 1777 fprintf (file, "#%ld", val);
737a5d5b 1778 break;
1779 }
9305fe33 1780 default:
1781 break;
e1629549 1782 }
1783 }
1784}
1785
87ad9aff 1786/* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1787
1788static bool
1789h8300_print_operand_punct_valid_p (unsigned char code)
1790{
1791 return (code == '#');
1792}
1793
e1629549 1794/* Output assembly language output for the address ADDR to FILE. */
1795
87ad9aff 1796static void
3c047fe9 1797h8300_print_operand_address (FILE *file, machine_mode mode, rtx addr)
e1629549 1798{
727c62dd 1799 rtx index;
1800 int size;
1801
e1629549 1802 switch (GET_CODE (addr))
1803 {
1804 case REG:
b839e0b4 1805 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
e1629549 1806 break;
1807
1808 case PRE_DEC:
b839e0b4 1809 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
e1629549 1810 break;
1811
1812 case POST_INC:
b839e0b4 1813 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
e1629549 1814 break;
1815
727c62dd 1816 case PRE_INC:
1817 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1818 break;
1819
1820 case POST_DEC:
1821 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
1822 break;
1823
e1629549 1824 case PLUS:
1825 fprintf (file, "(");
727c62dd 1826
1827 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
1828 if (GET_CODE (index) == REG)
e1629549 1829 {
1830 /* reg,foo */
3c047fe9 1831 h8300_print_operand_address (file, mode, XEXP (addr, 1));
e1629549 1832 fprintf (file, ",");
727c62dd 1833 switch (size)
1834 {
1835 case 0:
3c047fe9 1836 h8300_print_operand_address (file, mode, index);
727c62dd 1837 break;
1838
1839 case 1:
87ad9aff 1840 h8300_print_operand (file, index, 'X');
727c62dd 1841 fputs (".b", file);
1842 break;
1843
1844 case 2:
87ad9aff 1845 h8300_print_operand (file, index, 'T');
727c62dd 1846 fputs (".w", file);
1847 break;
1848
1849 case 4:
87ad9aff 1850 h8300_print_operand (file, index, 'S');
727c62dd 1851 fputs (".l", file);
1852 break;
1853 }
87ad9aff 1854 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
e1629549 1855 }
1856 else
1857 {
1858 /* foo+k */
3c047fe9 1859 h8300_print_operand_address (file, mode, XEXP (addr, 0));
e1629549 1860 fprintf (file, "+");
3c047fe9 1861 h8300_print_operand_address (file, mode, XEXP (addr, 1));
e1629549 1862 }
1863 fprintf (file, ")");
1864 break;
1865
1866 case CONST_INT:
b839e0b4 1867 {
03fb0c81 1868 /* Since the H8/300 only has 16-bit pointers, negative values are also
b839e0b4 1869 those >= 32768. This happens for example with pointer minus a
1870 constant. We don't want to turn (char *p - 2) into
1871 (char *p + 65534) because loop unrolling can build upon this
1872 (IE: char *p + 131068). */
1873 int n = INTVAL (addr);
1874 if (TARGET_H8300)
1875 n = (int) (short) n;
90a38175 1876 fprintf (file, "%d", n);
b839e0b4 1877 break;
1878 }
e1629549 1879
1880 default:
1881 output_addr_const (file, addr);
1882 break;
1883 }
1884}
1885\f
e1629549 1886/* Output all insn addresses and their sizes into the assembly language
1887 output file. This is helpful for debugging whether the length attributes
1888 in the md file are correct. This is not meant to be a user selectable
1889 option. */
1890
1891void
1a1ed145 1892final_prescan_insn (rtx_insn *insn, rtx *operand ATTRIBUTE_UNUSED,
230002f2 1893 int num_operands ATTRIBUTE_UNUSED)
e1629549 1894{
1895 /* This holds the last insn address. */
1896 static int last_insn_address = 0;
1897
407921a5 1898 const int uid = INSN_UID (insn);
e1629549 1899
1900 if (TARGET_ADDRESSES)
1901 {
47fc0706 1902 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1903 INSN_ADDRESSES (uid) - last_insn_address);
1904 last_insn_address = INSN_ADDRESSES (uid);
e1629549 1905 }
1906}
1907
b839e0b4 1908/* Prepare for an SI sized move. */
1909
1910int
1564ec41 1911h8300_expand_movsi (rtx operands[])
e1629549 1912{
b839e0b4 1913 rtx src = operands[1];
1914 rtx dst = operands[0];
1915 if (!reload_in_progress && !reload_completed)
1916 {
1917 if (!register_operand (dst, GET_MODE (dst)))
1918 {
1919 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1920 emit_move_insn (tmp, src);
1921 operands[1] = tmp;
1922 }
1923 }
1924 return 0;
1925}
1926
cd90919d 1927/* Given FROM and TO register numbers, say whether this elimination is allowed.
1928 Frame pointer elimination is automatically handled.
1929
1930 For the h8300, if frame pointer elimination is being done, we would like to
1931 convert ap and rp into sp, not fp.
1932
1933 All other eliminations are valid. */
1934
1935static bool
1936h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
1937{
1938 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
1939}
1940
b2d7ede1 1941/* Conditionally modify register usage based on target flags. */
1942
1943static void
1944h8300_conditional_register_usage (void)
1945{
1946 if (!TARGET_MAC)
1947 fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1;
1948}
1949
b839e0b4 1950/* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
eb2aa24e 1951 Define the offset between two registers, one to be eliminated, and
1952 the other its replacement, at the start of a routine. */
e1629549 1953
b839e0b4 1954int
230002f2 1955h8300_initial_elimination_offset (int from, int to)
b839e0b4 1956{
32351c92 1957 /* The number of bytes that the return address takes on the stack. */
1958 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
b839e0b4 1959
f4ac50fb 1960 /* The number of bytes that the saved frame pointer takes on the stack. */
1961 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1962
1963 /* The number of bytes that the saved registers, excluding the frame
1964 pointer, take on the stack. */
1965 int saved_regs_size = 0;
b839e0b4 1966
f4ac50fb 1967 /* The number of bytes that the locals takes on the stack. */
1968 int frame_size = round_frame_size (get_frame_size ());
b839e0b4 1969
f4ac50fb 1970 int regno;
b839e0b4 1971
f4ac50fb 1972 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1973 if (WORD_REG_USED (regno))
1974 saved_regs_size += UNITS_PER_WORD;
b839e0b4 1975
f4ac50fb 1976 /* Adjust saved_regs_size because the above loop took the frame
1977 pointer int account. */
1978 saved_regs_size -= fp_size;
35a462ce 1979
3afe906b 1980 switch (to)
f4ac50fb 1981 {
3afe906b 1982 case HARD_FRAME_POINTER_REGNUM:
f4ac50fb 1983 switch (from)
1984 {
1985 case ARG_POINTER_REGNUM:
1986 return pc_size + fp_size;
1987 case RETURN_ADDRESS_POINTER_REGNUM:
1988 return fp_size;
1989 case FRAME_POINTER_REGNUM:
1990 return -saved_regs_size;
1991 default:
3afe906b 1992 gcc_unreachable ();
f4ac50fb 1993 }
3afe906b 1994 break;
1995 case STACK_POINTER_REGNUM:
f4ac50fb 1996 switch (from)
1997 {
1998 case ARG_POINTER_REGNUM:
1999 return pc_size + saved_regs_size + frame_size;
2000 case RETURN_ADDRESS_POINTER_REGNUM:
2001 return saved_regs_size + frame_size;
2002 case FRAME_POINTER_REGNUM:
2003 return frame_size;
2004 default:
3afe906b 2005 gcc_unreachable ();
f4ac50fb 2006 }
3afe906b 2007 break;
2008 default:
2009 gcc_unreachable ();
f4ac50fb 2010 }
3afe906b 2011 gcc_unreachable ();
b839e0b4 2012}
2013
cdfb02e8 2014/* Worker function for RETURN_ADDR_RTX. */
2015
f643a7d5 2016rtx
230002f2 2017h8300_return_addr_rtx (int count, rtx frame)
f643a7d5 2018{
2019 rtx ret;
2020
2021 if (count == 0)
2022 ret = gen_rtx_MEM (Pmode,
2023 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
2024 else if (flag_omit_frame_pointer)
2025 return (rtx) 0;
2026 else
2027 ret = gen_rtx_MEM (Pmode,
2028 memory_address (Pmode,
29c05e22 2029 plus_constant (Pmode, frame,
2030 UNITS_PER_WORD)));
f643a7d5 2031 set_mem_alias_set (ret, get_frame_alias_set ());
2032 return ret;
2033}
2034
b839e0b4 2035/* Update the condition code from the insn. */
2036
9305fe33 2037void
50fc2d35 2038notice_update_cc (rtx body, rtx_insn *insn)
b839e0b4 2039{
1617b5d2 2040 rtx set;
2041
b839e0b4 2042 switch (get_attr_cc (insn))
2043 {
2044 case CC_NONE:
30c992ef 2045 /* Insn does not affect CC at all. */
b839e0b4 2046 break;
2047
2048 case CC_NONE_0HIT:
30c992ef 2049 /* Insn does not change CC, but the 0'th operand has been changed. */
b839e0b4 2050 if (cc_status.value1 != 0
ed420a25 2051 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
b839e0b4 2052 cc_status.value1 = 0;
ad992f91 2053 if (cc_status.value2 != 0
2054 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
2055 cc_status.value2 = 0;
b839e0b4 2056 break;
2057
a618bce0 2058 case CC_SET_ZN:
ed420a25 2059 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
30c992ef 2060 The V flag is unusable. The C flag may or may not be known but
2061 that's ok because alter_cond will change tests to use EQ/NE. */
b839e0b4 2062 CC_STATUS_INIT;
30c992ef 2063 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1617b5d2 2064 set = single_set (insn);
2065 cc_status.value1 = SET_SRC (set);
2066 if (SET_DEST (set) != cc0_rtx)
2067 cc_status.value2 = SET_DEST (set);
b839e0b4 2068 break;
2069
a618bce0 2070 case CC_SET_ZNV:
ed420a25 2071 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
a618bce0 2072 The C flag may or may not be known but that's ok because
2073 alter_cond will change tests to use EQ/NE. */
2074 CC_STATUS_INIT;
2075 cc_status.flags |= CC_NO_CARRY;
1617b5d2 2076 set = single_set (insn);
2077 cc_status.value1 = SET_SRC (set);
2078 if (SET_DEST (set) != cc0_rtx)
83e2d3b1 2079 {
2080 /* If the destination is STRICT_LOW_PART, strip off
2081 STRICT_LOW_PART. */
2082 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
2083 cc_status.value2 = XEXP (SET_DEST (set), 0);
2084 else
2085 cc_status.value2 = SET_DEST (set);
2086 }
a618bce0 2087 break;
2088
727c62dd 2089 case CC_COMPARE:
2090 /* The insn is a compare instruction. */
2091 CC_STATUS_INIT;
2092 cc_status.value1 = SET_SRC (body);
2093 break;
2094
2095 case CC_CLOBBER:
2096 /* Insn doesn't leave CC in a usable state. */
2097 CC_STATUS_INIT;
2098 break;
2099 }
2100}
727c62dd 2101\f
2102/* Given that X occurs in an address of the form (plus X constant),
2103 return the part of X that is expected to be a register. There are
2104 four kinds of addressing mode to recognize:
2105
2106 @(dd,Rn)
2107 @(dd,RnL.b)
2108 @(dd,Rn.w)
2109 @(dd,ERn.l)
2110
2111 If SIZE is nonnull, and the address is one of the last three forms,
2112 set *SIZE to the index multiplication factor. Set it to 0 for
2113 plain @(dd,Rn) addresses.
2114
2115 MODE is the mode of the value being accessed. It can be VOIDmode
2116 if the address is known to be valid, but its mode is unknown. */
2117
958f5301 2118static rtx
3754d046 2119h8300_get_index (rtx x, machine_mode mode, int *size)
727c62dd 2120{
2121 int dummy, factor;
2122
2123 if (size == 0)
2124 size = &dummy;
2125
2126 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
2127 if (TARGET_H8300SX
2128 && factor <= 4
2129 && (mode == VOIDmode
2130 || GET_MODE_CLASS (mode) == MODE_INT
2131 || GET_MODE_CLASS (mode) == MODE_FLOAT))
2132 {
2133 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
2134 {
2135 /* When accessing byte-sized values, the index can be
2136 a zero-extended QImode or HImode register. */
2137 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
2138 return XEXP (x, 0);
2139 }
2140 else
2141 {
2142 /* We're looking for addresses of the form:
2143
2144 (mult X I)
2145 or (mult (zero_extend X) I)
2146
2147 where I is the size of the operand being accessed.
2148 The canonical form of the second expression is:
2149
2150 (and (mult (subreg X) I) J)
2151
2152 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2153 rtx index;
2154
2155 if (GET_CODE (x) == AND
2156 && GET_CODE (XEXP (x, 1)) == CONST_INT
2157 && (factor == 0
2158 || INTVAL (XEXP (x, 1)) == 0xff * factor
2159 || INTVAL (XEXP (x, 1)) == 0xffff * factor))
2160 {
2161 index = XEXP (x, 0);
2162 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
2163 }
2164 else
2165 {
2166 index = x;
2167 *size = 4;
2168 }
2169
2170 if (GET_CODE (index) == MULT
2171 && GET_CODE (XEXP (index, 1)) == CONST_INT
2172 && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
2173 return XEXP (index, 0);
2174 }
2175 }
2176 *size = 0;
2177 return x;
2178}
2179\f
958f5301 2180/* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2181
2182 On the H8/300, the predecrement and postincrement address depend thus
2183 (the amount of decrement or increment being the length of the operand). */
2184
2185static bool
4e27ffd0 2186h8300_mode_dependent_address_p (const_rtx addr,
2187 addr_space_t as ATTRIBUTE_UNUSED)
958f5301 2188{
2189 if (GET_CODE (addr) == PLUS
2190 && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0))
2191 return true;
2192
2193 return false;
2194}
2195\f
727c62dd 2196static const h8300_length_table addb_length_table =
2197{
2198 /* #xx Rs @aa @Rs @xx */
2199 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2200 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2201 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2202 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2203};
2204
2205static const h8300_length_table addw_length_table =
2206{
2207 /* #xx Rs @aa @Rs @xx */
2208 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2209 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2210 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2211 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2212};
2213
2214static const h8300_length_table addl_length_table =
2215{
2216 /* #xx Rs @aa @Rs @xx */
2217 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2218 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2219 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2220 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2221};
2222
2223#define logicb_length_table addb_length_table
2224#define logicw_length_table addw_length_table
2225
2226static const h8300_length_table logicl_length_table =
2227{
2228 /* #xx Rs @aa @Rs @xx */
2229 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2230 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2231 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2232 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2233};
2234
2235static const h8300_length_table movb_length_table =
2236{
2237 /* #xx Rs @aa @Rs @xx */
2238 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2239 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2240 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2241 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2242};
2243
2244#define movw_length_table movb_length_table
2245
2246static const h8300_length_table movl_length_table =
2247{
2248 /* #xx Rs @aa @Rs @xx */
2249 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2250 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2251 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2252 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2253};
2254
2255/* Return the size of the given address or displacement constant. */
2256
2257static unsigned int
2258h8300_constant_length (rtx constant)
2259{
2260 /* Check for (@d:16,Reg). */
2261 if (GET_CODE (constant) == CONST_INT
2262 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
2263 return 2;
2264
2265 /* Check for (@d:16,Reg) in cases where the displacement is
2266 an absolute address. */
2267 if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
2268 return 2;
2269
2270 return 4;
2271}
2272
2273/* Return the size of a displacement field in address ADDR, which should
2274 have the form (plus X constant). SIZE is the number of bytes being
2275 accessed. */
2276
2277static unsigned int
2278h8300_displacement_length (rtx addr, int size)
2279{
2280 rtx offset;
2281
2282 offset = XEXP (addr, 1);
2283
2284 /* Check for @(d:2,Reg). */
2285 if (register_operand (XEXP (addr, 0), VOIDmode)
2286 && GET_CODE (offset) == CONST_INT
2287 && (INTVAL (offset) == size
2288 || INTVAL (offset) == size * 2
2289 || INTVAL (offset) == size * 3))
2290 return 0;
2291
2292 return h8300_constant_length (offset);
2293}
2294
8deb3959 2295/* Store the class of operand OP in *OPCLASS and return the length of any
2296 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
727c62dd 2297 can be null if only the length is needed. */
2298
2299static unsigned int
8deb3959 2300h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
727c62dd 2301{
2302 enum h8300_operand_class dummy;
2303
8deb3959 2304 if (opclass == 0)
2305 opclass = &dummy;
727c62dd 2306
2307 if (CONSTANT_P (op))
2308 {
8deb3959 2309 *opclass = H8OP_IMMEDIATE;
727c62dd 2310
2311 /* Byte-sized immediates are stored in the opcode fields. */
2312 if (size == 1)
2313 return 0;
2314
2315 /* If this is a 32-bit instruction, see whether the constant
2316 will fit into a 16-bit immediate field. */
2317 if (TARGET_H8300SX
2318 && size == 4
2319 && GET_CODE (op) == CONST_INT
2320 && IN_RANGE (INTVAL (op), 0, 0xffff))
2321 return 2;
2322
2323 return size;
2324 }
2325 else if (GET_CODE (op) == MEM)
2326 {
2327 op = XEXP (op, 0);
2328 if (CONSTANT_P (op))
2329 {
8deb3959 2330 *opclass = H8OP_MEM_ABSOLUTE;
727c62dd 2331 return h8300_constant_length (op);
2332 }
2333 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
2334 {
8deb3959 2335 *opclass = H8OP_MEM_COMPLEX;
727c62dd 2336 return h8300_displacement_length (op, size);
2337 }
2338 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
2339 {
8deb3959 2340 *opclass = H8OP_MEM_COMPLEX;
727c62dd 2341 return 0;
2342 }
2343 else if (register_operand (op, VOIDmode))
2344 {
8deb3959 2345 *opclass = H8OP_MEM_BASE;
727c62dd 2346 return 0;
2347 }
2348 }
3afe906b 2349 gcc_assert (register_operand (op, VOIDmode));
8deb3959 2350 *opclass = H8OP_REGISTER;
3afe906b 2351 return 0;
727c62dd 2352}
2353
2354/* Return the length of the instruction described by TABLE given that
2355 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2356 and OP2 must be an h8300_src_operand. */
2357
2358static unsigned int
2359h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
2360{
2361 enum h8300_operand_class op1_class, op2_class;
2362 unsigned int size, immediate_length;
2363
2364 size = GET_MODE_SIZE (GET_MODE (op1));
2365 immediate_length = (h8300_classify_operand (op1, size, &op1_class)
2366 + h8300_classify_operand (op2, size, &op2_class));
2367 return immediate_length + (*table)[op1_class - 1][op2_class];
2368}
2369
2370/* Return the length of a unary instruction such as neg or not given that
2371 its operand is OP. */
2372
2373unsigned int
2374h8300_unary_length (rtx op)
2375{
8deb3959 2376 enum h8300_operand_class opclass;
727c62dd 2377 unsigned int size, operand_length;
2378
2379 size = GET_MODE_SIZE (GET_MODE (op));
8deb3959 2380 operand_length = h8300_classify_operand (op, size, &opclass);
2381 switch (opclass)
727c62dd 2382 {
2383 case H8OP_REGISTER:
2384 return 2;
2385
2386 case H8OP_MEM_BASE:
2387 return (size == 4 ? 6 : 4);
2388
2389 case H8OP_MEM_ABSOLUTE:
2390 return operand_length + (size == 4 ? 6 : 4);
2391
2392 case H8OP_MEM_COMPLEX:
2393 return operand_length + 6;
2394
2395 default:
3afe906b 2396 gcc_unreachable ();
727c62dd 2397 }
2398}
2399
2400/* Likewise short immediate instructions such as add.w #xx:3,OP. */
2401
2402static unsigned int
2403h8300_short_immediate_length (rtx op)
2404{
8deb3959 2405 enum h8300_operand_class opclass;
727c62dd 2406 unsigned int size, operand_length;
2407
2408 size = GET_MODE_SIZE (GET_MODE (op));
8deb3959 2409 operand_length = h8300_classify_operand (op, size, &opclass);
727c62dd 2410
8deb3959 2411 switch (opclass)
727c62dd 2412 {
2413 case H8OP_REGISTER:
2414 return 2;
2415
2416 case H8OP_MEM_BASE:
2417 case H8OP_MEM_ABSOLUTE:
2418 case H8OP_MEM_COMPLEX:
2419 return 4 + operand_length;
2420
2421 default:
3afe906b 2422 gcc_unreachable ();
727c62dd 2423 }
2424}
2425
2426/* Likewise bitfield load and store instructions. */
b839e0b4 2427
727c62dd 2428static unsigned int
2429h8300_bitfield_length (rtx op, rtx op2)
2430{
8deb3959 2431 enum h8300_operand_class opclass;
727c62dd 2432 unsigned int size, operand_length;
2433
2434 if (GET_CODE (op) == REG)
2435 op = op2;
3afe906b 2436 gcc_assert (GET_CODE (op) != REG);
727c62dd 2437
2438 size = GET_MODE_SIZE (GET_MODE (op));
8deb3959 2439 operand_length = h8300_classify_operand (op, size, &opclass);
727c62dd 2440
8deb3959 2441 switch (opclass)
727c62dd 2442 {
2443 case H8OP_MEM_BASE:
2444 case H8OP_MEM_ABSOLUTE:
2445 case H8OP_MEM_COMPLEX:
2446 return 4 + operand_length;
2447
2448 default:
3afe906b 2449 gcc_unreachable ();
e1629549 2450 }
b839e0b4 2451}
2452
727c62dd 2453/* Calculate the length of general binary instruction INSN using TABLE. */
90e56b83 2454
727c62dd 2455static unsigned int
1a1ed145 2456h8300_binary_length (rtx_insn *insn, const h8300_length_table *table)
90e56b83 2457{
727c62dd 2458 rtx set;
2459
2460 set = single_set (insn);
3afe906b 2461 gcc_assert (set);
727c62dd 2462
2463 if (BINARY_P (SET_SRC (set)))
2464 return h8300_length_from_table (XEXP (SET_SRC (set), 0),
2465 XEXP (SET_SRC (set), 1), table);
727c62dd 2466 else
3afe906b 2467 {
2468 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
2469 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
2470 XEXP (XEXP (SET_SRC (set), 1), 1),
2471 table);
2472 }
90e56b83 2473}
2474
727c62dd 2475/* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2476 memory reference and either (1) it has the form @(d:16,Rn) or
2477 (2) its address has the code given by INC_CODE. */
90e56b83 2478
727c62dd 2479static bool
2480h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
90e56b83 2481{
727c62dd 2482 rtx addr;
2483 unsigned int size;
2484
2485 if (GET_CODE (op) != MEM)
2486 return false;
2487
2488 addr = XEXP (op, 0);
2489 size = GET_MODE_SIZE (GET_MODE (op));
2490 if (size != 1 && size != 2)
2491 return false;
2492
2493 return (GET_CODE (addr) == inc_code
2494 || (GET_CODE (addr) == PLUS
2495 && GET_CODE (XEXP (addr, 0)) == REG
2496 && h8300_displacement_length (addr, size) == 2));
90e56b83 2497}
2498
727c62dd 2499/* Calculate the length of move instruction INSN using the given length
2500 table. Although the tables are correct for most cases, there is some
2501 irregularity in the length of mov.b and mov.w. The following forms:
90e56b83 2502
727c62dd 2503 mov @ERs+, Rd
2504 mov @(d:16,ERs), Rd
2505 mov Rs, @-ERd
2506 mov Rs, @(d:16,ERd)
2507
2508 are two bytes shorter than most other "mov Rs, @complex" or
2509 "mov @complex,Rd" combinations. */
2510
2511static unsigned int
2512h8300_move_length (rtx *operands, const h8300_length_table *table)
90e56b83 2513{
727c62dd 2514 unsigned int size;
2515
2516 size = h8300_length_from_table (operands[0], operands[1], table);
2517 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
2518 size -= 2;
2519 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
2520 size -= 2;
2521 return size;
90e56b83 2522}
2523
727c62dd 2524/* Return the length of a mova instruction with the given operands.
2525 DEST is the register destination, SRC is the source address and
2526 OFFSET is the 16-bit or 32-bit displacement. */
0d565792 2527
727c62dd 2528static unsigned int
2529h8300_mova_length (rtx dest, rtx src, rtx offset)
0d565792 2530{
727c62dd 2531 unsigned int size;
2532
2533 size = (2
2534 + h8300_constant_length (offset)
2535 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
2536 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
2537 size += 2;
2538 return size;
0d565792 2539}
2540
727c62dd 2541/* Compute the length of INSN based on its length_table attribute.
2542 OPERANDS is the array of its operands. */
0d565792 2543
727c62dd 2544unsigned int
1a1ed145 2545h8300_insn_length_from_table (rtx_insn *insn, rtx * operands)
0d565792 2546{
727c62dd 2547 switch (get_attr_length_table (insn))
2548 {
2549 case LENGTH_TABLE_NONE:
3afe906b 2550 gcc_unreachable ();
727c62dd 2551
2552 case LENGTH_TABLE_ADDB:
2553 return h8300_binary_length (insn, &addb_length_table);
2554
2555 case LENGTH_TABLE_ADDW:
2556 return h8300_binary_length (insn, &addw_length_table);
2557
2558 case LENGTH_TABLE_ADDL:
2559 return h8300_binary_length (insn, &addl_length_table);
2560
2561 case LENGTH_TABLE_LOGICB:
2562 return h8300_binary_length (insn, &logicb_length_table);
2563
2564 case LENGTH_TABLE_MOVB:
2565 return h8300_move_length (operands, &movb_length_table);
2566
2567 case LENGTH_TABLE_MOVW:
2568 return h8300_move_length (operands, &movw_length_table);
2569
2570 case LENGTH_TABLE_MOVL:
2571 return h8300_move_length (operands, &movl_length_table);
2572
2573 case LENGTH_TABLE_MOVA:
2574 return h8300_mova_length (operands[0], operands[1], operands[2]);
2575
2576 case LENGTH_TABLE_MOVA_ZERO:
2577 return h8300_mova_length (operands[0], operands[1], const0_rtx);
2578
2579 case LENGTH_TABLE_UNARY:
2580 return h8300_unary_length (operands[0]);
2581
2582 case LENGTH_TABLE_MOV_IMM4:
2583 return 2 + h8300_classify_operand (operands[0], 0, 0);
2584
2585 case LENGTH_TABLE_SHORT_IMMEDIATE:
2586 return h8300_short_immediate_length (operands[0]);
2587
2588 case LENGTH_TABLE_BITFIELD:
2589 return h8300_bitfield_length (operands[0], operands[1]);
2590
2591 case LENGTH_TABLE_BITBRANCH:
2592 return h8300_bitfield_length (operands[1], operands[2]) - 2;
3afe906b 2593
2594 default:
2595 gcc_unreachable ();
727c62dd 2596 }
0d565792 2597}
2598
727c62dd 2599/* Return true if LHS and RHS are memory references that can be mapped
2600 to the same h8sx assembly operand. LHS appears as the destination of
2601 an instruction and RHS appears as a source.
079b5951 2602
727c62dd 2603 Three cases are allowed:
2604
2605 - RHS is @+Rn or @-Rn, LHS is @Rn
2606 - RHS is @Rn, LHS is @Rn+ or @Rn-
2607 - RHS and LHS have the same address and neither has side effects. */
2608
2609bool
2610h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
079b5951 2611{
727c62dd 2612 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
2613 {
2614 rhs = XEXP (rhs, 0);
2615 lhs = XEXP (lhs, 0);
2616
2617 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
2618 return rtx_equal_p (XEXP (rhs, 0), lhs);
2619
2620 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
2621 return rtx_equal_p (rhs, XEXP (lhs, 0));
2622
2623 if (rtx_equal_p (rhs, lhs))
2624 return true;
2625 }
2626 return false;
079b5951 2627}
2628
727c62dd 2629/* Return true if OPERANDS[1] can be mapped to the same assembly
2630 operand as OPERANDS[0]. */
079b5951 2631
727c62dd 2632bool
2633h8300_operands_match_p (rtx *operands)
079b5951 2634{
727c62dd 2635 if (register_operand (operands[0], VOIDmode)
2636 && register_operand (operands[1], VOIDmode))
2637 return true;
079b5951 2638
727c62dd 2639 if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
2640 return true;
2641
2642 return false;
079b5951 2643}
727c62dd 2644\f
2645/* Try using movmd to move LENGTH bytes from memory region SRC to memory
2646 region DEST. The two regions do not overlap and have the common
2647 alignment given by ALIGNMENT. Return true on success.
c6720edd 2648
727c62dd 2649 Using movmd for variable-length moves seems to involve some
2650 complex trade-offs. For instance:
4c924258 2651
727c62dd 2652 - Preparing for a movmd instruction is similar to preparing
2653 for a memcpy. The main difference is that the arguments
2654 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2655
2656 - Since movmd clobbers the frame pointer, we need to save
2657 and restore it somehow when frame_pointer_needed. This can
2658 sometimes make movmd sequences longer than calls to memcpy().
2659
2660 - The counter register is 16 bits, so the instruction is only
2661 suitable for variable-length moves when sizeof (size_t) == 2.
2662 That's only true in normal mode.
2663
2664 - We will often lack static alignment information. Falling back
2665 on movmd.b would likely be slower than calling memcpy(), at least
2666 for big moves.
2667
2668 This function therefore only uses movmd when the length is a
2669 known constant, and only then if -fomit-frame-pointer is in
2670 effect or if we're not optimizing for size.
2671
2672 At the moment the function uses movmd for all in-range constants,
2673 but it might be better to fall back on memcpy() for large moves
2674 if ALIGNMENT == 1. */
2675
2676bool
2677h8sx_emit_movmd (rtx dest, rtx src, rtx length,
2678 HOST_WIDE_INT alignment)
4c924258 2679{
727c62dd 2680 if (!flag_omit_frame_pointer && optimize_size)
2681 return false;
4c924258 2682
727c62dd 2683 if (GET_CODE (length) == CONST_INT)
2684 {
2685 rtx dest_reg, src_reg, first_dest, first_src;
2686 HOST_WIDE_INT n;
2687 int factor;
2688
2689 /* Use movmd.l if the alignment allows it, otherwise fall back
2690 on movmd.b. */
2691 factor = (alignment >= 2 ? 4 : 1);
2692
2693 /* Make sure the length is within range. We can handle counter
2694 values up to 65536, although HImode truncation will make
2695 the count appear negative in rtl dumps. */
2696 n = INTVAL (length);
2697 if (n <= 0 || n / factor > 65536)
2698 return false;
2699
2700 /* Create temporary registers for the source and destination
2701 pointers. Initialize them to the start of each region. */
2702 dest_reg = copy_addr_to_reg (XEXP (dest, 0));
2703 src_reg = copy_addr_to_reg (XEXP (src, 0));
2704
2705 /* Create references to the movmd source and destination blocks. */
2706 first_dest = replace_equiv_address (dest, dest_reg);
2707 first_src = replace_equiv_address (src, src_reg);
2708
5b2a69fa 2709 set_mem_size (first_dest, n & -factor);
2710 set_mem_size (first_src, n & -factor);
727c62dd 2711
2712 length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode));
2713 emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor)));
2714
2715 if ((n & -factor) != n)
2716 {
2717 /* Move SRC and DEST past the region we just copied.
2718 This is done to update the memory attributes. */
2719 dest = adjust_address (dest, BLKmode, n & -factor);
2720 src = adjust_address (src, BLKmode, n & -factor);
2721
2722 /* Replace the addresses with the source and destination
2723 registers, which movmd has left with the right values. */
2724 dest = replace_equiv_address (dest, dest_reg);
2725 src = replace_equiv_address (src, src_reg);
2726
2727 /* Mop up the left-over bytes. */
2728 if (n & 2)
2729 emit_move_insn (adjust_address (dest, HImode, 0),
2730 adjust_address (src, HImode, 0));
2731 if (n & 1)
2732 emit_move_insn (adjust_address (dest, QImode, n & 2),
2733 adjust_address (src, QImode, n & 2));
2734 }
2735 return true;
2736 }
2737 return false;
4c924258 2738}
2739
727c62dd 2740/* Move ADDR into er6 after pushing its old value onto the stack. */
b839e0b4 2741
727c62dd 2742void
2743h8300_swap_into_er6 (rtx addr)
b839e0b4 2744{
42231db5 2745 rtx insn = push (HARD_FRAME_POINTER_REGNUM, false);
a5c6cfdd 2746 if (frame_pointer_needed)
2747 add_reg_note (insn, REG_CFA_DEF_CFA,
29c05e22 2748 plus_constant (Pmode, gen_rtx_MEM (Pmode, stack_pointer_rtx),
a5c6cfdd 2749 2 * UNITS_PER_WORD));
2750 else
2751 add_reg_note (insn, REG_CFA_ADJUST_CFA,
d1f9b275 2752 gen_rtx_SET (stack_pointer_rtx,
29c05e22 2753 plus_constant (Pmode, stack_pointer_rtx, 4)));
a5c6cfdd 2754
727c62dd 2755 emit_move_insn (hard_frame_pointer_rtx, addr);
2756 if (REGNO (addr) == SP_REG)
2757 emit_move_insn (hard_frame_pointer_rtx,
29c05e22 2758 plus_constant (Pmode, hard_frame_pointer_rtx,
727c62dd 2759 GET_MODE_SIZE (word_mode)));
2760}
e1629549 2761
727c62dd 2762/* Move the current value of er6 into ADDR and pop its old value
2763 from the stack. */
2764
2765void
2766h8300_swap_out_of_er6 (rtx addr)
2767{
a5c6cfdd 2768 rtx insn;
2769
727c62dd 2770 if (REGNO (addr) != SP_REG)
2771 emit_move_insn (addr, hard_frame_pointer_rtx);
a5c6cfdd 2772
2773 insn = pop (HARD_FRAME_POINTER_REGNUM);
a5c6cfdd 2774 if (frame_pointer_needed)
2775 add_reg_note (insn, REG_CFA_DEF_CFA,
29c05e22 2776 plus_constant (Pmode, hard_frame_pointer_rtx,
2777 2 * UNITS_PER_WORD));
a5c6cfdd 2778 else
2779 add_reg_note (insn, REG_CFA_ADJUST_CFA,
d1f9b275 2780 gen_rtx_SET (stack_pointer_rtx,
29c05e22 2781 plus_constant (Pmode, stack_pointer_rtx, -4)));
e1629549 2782}
b839e0b4 2783\f
2e295ea4 2784/* Return the length of mov instruction. */
2785
2786unsigned int
2787compute_mov_length (rtx *operands)
2788{
2789 /* If the mov instruction involves a memory operand, we compute the
2790 length, assuming the largest addressing mode is used, and then
2791 adjust later in the function. Otherwise, we compute and return
2792 the exact length in one step. */
3754d046 2793 machine_mode mode = GET_MODE (operands[0]);
2e295ea4 2794 rtx dest = operands[0];
2795 rtx src = operands[1];
2796 rtx addr;
2797
2798 if (GET_CODE (src) == MEM)
2799 addr = XEXP (src, 0);
2800 else if (GET_CODE (dest) == MEM)
2801 addr = XEXP (dest, 0);
2802 else
2803 addr = NULL_RTX;
2804
2805 if (TARGET_H8300)
2806 {
2807 unsigned int base_length;
2808
2809 switch (mode)
2810 {
916ace94 2811 case E_QImode:
2e295ea4 2812 if (addr == NULL_RTX)
2813 return 2;
2814
2815 /* The eightbit addressing is available only in QImode, so
2816 go ahead and take care of it. */
2817 if (h8300_eightbit_constant_address_p (addr))
2818 return 2;
2819
2820 base_length = 4;
2821 break;
2822
916ace94 2823 case E_HImode:
2e295ea4 2824 if (addr == NULL_RTX)
2825 {
2826 if (REG_P (src))
2827 return 2;
2828
2829 if (src == const0_rtx)
2830 return 2;
2831
2832 return 4;
2833 }
2834
2835 base_length = 4;
2836 break;
2837
916ace94 2838 case E_SImode:
2e295ea4 2839 if (addr == NULL_RTX)
2840 {
2841 if (REG_P (src))
2842 return 4;
2843
2844 if (GET_CODE (src) == CONST_INT)
2845 {
2846 if (src == const0_rtx)
2847 return 4;
2848
2849 if ((INTVAL (src) & 0xffff) == 0)
2850 return 6;
2851
2852 if ((INTVAL (src) & 0xffff) == 0)
2853 return 6;
786637e0 2854
2855 if ((INTVAL (src) & 0xffff)
2856 == ((INTVAL (src) >> 16) & 0xffff))
2857 return 6;
2e295ea4 2858 }
2859 return 8;
2860 }
2861
2862 base_length = 8;
2863 break;
2864
916ace94 2865 case E_SFmode:
2e295ea4 2866 if (addr == NULL_RTX)
2867 {
2868 if (REG_P (src))
2869 return 4;
2870
424f5954 2871 if (satisfies_constraint_G (src))
f62378f4 2872 return 4;
2873
ead5f19f 2874 return 8;
2e295ea4 2875 }
2876
2877 base_length = 8;
2878 break;
2879
2880 default:
3afe906b 2881 gcc_unreachable ();
2e295ea4 2882 }
2883
2884 /* Adjust the length based on the addressing mode used.
2885 Specifically, we subtract the difference between the actual
2886 length and the longest one, which is @(d:16,Rs). For SImode
2887 and SFmode, we double the adjustment because two mov.w are
2888 used to do the job. */
2889
2890 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2891 if (GET_CODE (addr) == PRE_DEC
2892 || GET_CODE (addr) == POST_INC)
2893 {
2894 if (mode == QImode || mode == HImode)
2895 return base_length - 2;
2896 else
2897 /* In SImode and SFmode, we use two mov.w instructions, so
3c364971 2898 double the adjustment. */
2e295ea4 2899 return base_length - 4;
2900 }
2901
2902 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2903 in SImode and SFmode, the second mov.w involves an address
2904 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2905 only 2 bytes. */
2906 if (GET_CODE (addr) == REG)
2907 return base_length - 2;
2908
2909 return base_length;
2910 }
2911 else
2912 {
2913 unsigned int base_length;
2914
2915 switch (mode)
2916 {
916ace94 2917 case E_QImode:
2e295ea4 2918 if (addr == NULL_RTX)
2919 return 2;
2920
2921 /* The eightbit addressing is available only in QImode, so
2922 go ahead and take care of it. */
2923 if (h8300_eightbit_constant_address_p (addr))
2924 return 2;
2925
2926 base_length = 8;
2927 break;
2928
916ace94 2929 case E_HImode:
2e295ea4 2930 if (addr == NULL_RTX)
2931 {
2932 if (REG_P (src))
2933 return 2;
2934
2935 if (src == const0_rtx)
2936 return 2;
2937
2938 return 4;
2939 }
2940
2941 base_length = 8;
2942 break;
2943
916ace94 2944 case E_SImode:
2e295ea4 2945 if (addr == NULL_RTX)
2946 {
2947 if (REG_P (src))
2948 {
2949 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2950 return 4;
2951 else
2952 return 2;
2953 }
2954
2955 if (GET_CODE (src) == CONST_INT)
2956 {
2957 int val = INTVAL (src);
2958
2959 if (val == 0)
2960 return 2;
2961
2962 if (val == (val & 0x00ff) || val == (val & 0xff00))
2963 return 4;
6fe6e17a 2964
2e295ea4 2965 switch (val & 0xffffffff)
2966 {
2967 case 0xffffffff:
2968 case 0xfffffffe:
2969 case 0xfffffffc:
2970 case 0x0000ffff:
2971 case 0x0000fffe:
2972 case 0xffff0000:
2973 case 0xfffe0000:
2974 case 0x00010000:
2975 case 0x00020000:
2976 return 4;
2977 }
2978 }
2979 return 6;
2980 }
2981
2982 base_length = 10;
2983 break;
2984
916ace94 2985 case E_SFmode:
2e295ea4 2986 if (addr == NULL_RTX)
2987 {
2988 if (REG_P (src))
2989 return 2;
2990
424f5954 2991 if (satisfies_constraint_G (src))
2e295ea4 2992 return 2;
f62378f4 2993
2e295ea4 2994 return 6;
2995 }
2996
2997 base_length = 10;
2998 break;
2999
3000 default:
3afe906b 3001 gcc_unreachable ();
2e295ea4 3002 }
3003
3004 /* Adjust the length based on the addressing mode used.
3005 Specifically, we subtract the difference between the actual
3006 length and the longest one, which is @(d:24,ERs). */
3007
3008 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
3009 if (GET_CODE (addr) == PRE_DEC
3010 || GET_CODE (addr) == POST_INC)
3011 return base_length - 6;
3012
3013 /* @ERs and @ERd are 6 bytes shorter than the longest. */
3014 if (GET_CODE (addr) == REG)
3015 return base_length - 6;
3016
3017 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
3018 longest. */
3019 if (GET_CODE (addr) == PLUS
3020 && GET_CODE (XEXP (addr, 0)) == REG
3021 && GET_CODE (XEXP (addr, 1)) == CONST_INT
3022 && INTVAL (XEXP (addr, 1)) > -32768
3023 && INTVAL (XEXP (addr, 1)) < 32767)
3024 return base_length - 4;
3025
3026 /* @aa:16 is 4 bytes shorter than the longest. */
3027 if (h8300_tiny_constant_address_p (addr))
3028 return base_length - 4;
3029
3030 /* @aa:24 is 2 bytes shorter than the longest. */
3031 if (CONSTANT_P (addr))
3032 return base_length - 2;
3033
3034 return base_length;
3035 }
3036}
3037\f
cdfb02e8 3038/* Output an addition insn. */
3039
6a8a3fa3 3040const char *
230002f2 3041output_plussi (rtx *operands)
aa3382b1 3042{
3754d046 3043 machine_mode mode = GET_MODE (operands[0]);
aa3382b1 3044
3afe906b 3045 gcc_assert (mode == SImode);
aa3382b1 3046
3047 if (TARGET_H8300)
3048 {
469dc9d2 3049 if (GET_CODE (operands[2]) == REG)
3050 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3051
3052 if (GET_CODE (operands[2]) == CONST_INT)
3053 {
3054 HOST_WIDE_INT n = INTVAL (operands[2]);
3055
3056 if ((n & 0xffffff) == 0)
3057 return "add\t%z2,%z0";
3058 if ((n & 0xffff) == 0)
3059 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
3060 if ((n & 0xff) == 0)
3061 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3062 }
3063
3064 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
aa3382b1 3065 }
3066 else
3067 {
727c62dd 3068 if (GET_CODE (operands[2]) == CONST_INT
3069 && register_operand (operands[1], VOIDmode))
aa3382b1 3070 {
3071 HOST_WIDE_INT intval = INTVAL (operands[2]);
3072
727c62dd 3073 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3074 return "add.l\t%S2,%S0";
3075 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3076 return "sub.l\t%G2,%S0";
3077
aa3382b1 3078 /* See if we can finish with 2 bytes. */
3079
11233c59 3080 switch ((unsigned int) intval & 0xffffffff)
aa3382b1 3081 {
3082 case 0x00000001:
3083 case 0x00000002:
3084 case 0x00000004:
3085 return "adds\t%2,%S0";
3086
3087 case 0xffffffff:
3088 case 0xfffffffe:
3089 case 0xfffffffc:
3090 return "subs\t%G2,%S0";
3091
3092 case 0x00010000:
3093 case 0x00020000:
3094 operands[2] = GEN_INT (intval >> 16);
3095 return "inc.w\t%2,%e0";
3096
3097 case 0xffff0000:
3098 case 0xfffe0000:
3099 operands[2] = GEN_INT (intval >> 16);
3100 return "dec.w\t%G2,%e0";
3101 }
3102
3103 /* See if we can finish with 4 bytes. */
3104 if ((intval & 0xffff) == 0)
3105 {
3106 operands[2] = GEN_INT (intval >> 16);
3107 return "add.w\t%2,%e0";
3108 }
3109 }
3110
727c62dd 3111 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3112 {
3113 operands[2] = GEN_INT (-INTVAL (operands[2]));
3114 return "sub.l\t%S2,%S0";
3115 }
aa3382b1 3116 return "add.l\t%S2,%S0";
3117 }
3118}
3119
727c62dd 3120/* ??? It would be much easier to add the h8sx stuff if a single function
3121 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
cdfb02e8 3122/* Compute the length of an addition insn. */
3123
aa3382b1 3124unsigned int
230002f2 3125compute_plussi_length (rtx *operands)
aa3382b1 3126{
3754d046 3127 machine_mode mode = GET_MODE (operands[0]);
aa3382b1 3128
3afe906b 3129 gcc_assert (mode == SImode);
aa3382b1 3130
3131 if (TARGET_H8300)
3132 {
469dc9d2 3133 if (GET_CODE (operands[2]) == REG)
3134 return 6;
3135
3136 if (GET_CODE (operands[2]) == CONST_INT)
3137 {
3138 HOST_WIDE_INT n = INTVAL (operands[2]);
3139
3140 if ((n & 0xffffff) == 0)
3141 return 2;
3142 if ((n & 0xffff) == 0)
3143 return 4;
3144 if ((n & 0xff) == 0)
3145 return 6;
3146 }
3147
3148 return 8;
aa3382b1 3149 }
3150 else
3151 {
727c62dd 3152 if (GET_CODE (operands[2]) == CONST_INT
3153 && register_operand (operands[1], VOIDmode))
aa3382b1 3154 {
3155 HOST_WIDE_INT intval = INTVAL (operands[2]);
3156
727c62dd 3157 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3158 return 2;
3159 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3160 return 2;
3161
aa3382b1 3162 /* See if we can finish with 2 bytes. */
3163
11233c59 3164 switch ((unsigned int) intval & 0xffffffff)
aa3382b1 3165 {
3166 case 0x00000001:
3167 case 0x00000002:
3168 case 0x00000004:
3169 return 2;
3170
3171 case 0xffffffff:
3172 case 0xfffffffe:
3173 case 0xfffffffc:
3174 return 2;
3175
3176 case 0x00010000:
3177 case 0x00020000:
3178 return 2;
3179
3180 case 0xffff0000:
3181 case 0xfffe0000:
3182 return 2;
3183 }
3184
3185 /* See if we can finish with 4 bytes. */
3186 if ((intval & 0xffff) == 0)
3187 return 4;
3188 }
3189
727c62dd 3190 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3191 return h8300_length_from_table (operands[0],
3192 GEN_INT (-INTVAL (operands[2])),
3193 &addl_length_table);
3194 else
3195 return h8300_length_from_table (operands[0], operands[2],
3196 &addl_length_table);
aa3382b1 3197 return 6;
3198 }
3199}
3200
cdfb02e8 3201/* Compute which flag bits are valid after an addition insn. */
3202
539b539f 3203enum attr_cc
230002f2 3204compute_plussi_cc (rtx *operands)
aa3382b1 3205{
3754d046 3206 machine_mode mode = GET_MODE (operands[0]);
aa3382b1 3207
3afe906b 3208 gcc_assert (mode == SImode);
aa3382b1 3209
3210 if (TARGET_H8300)
3211 {
469dc9d2 3212 return CC_CLOBBER;
aa3382b1 3213 }
3214 else
3215 {
727c62dd 3216 if (GET_CODE (operands[2]) == CONST_INT
3217 && register_operand (operands[1], VOIDmode))
aa3382b1 3218 {
3219 HOST_WIDE_INT intval = INTVAL (operands[2]);
3220
727c62dd 3221 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3222 return CC_SET_ZN;
3223 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3224 return CC_SET_ZN;
3225
aa3382b1 3226 /* See if we can finish with 2 bytes. */
3227
11233c59 3228 switch ((unsigned int) intval & 0xffffffff)
aa3382b1 3229 {
3230 case 0x00000001:
3231 case 0x00000002:
3232 case 0x00000004:
3233 return CC_NONE_0HIT;
3234
3235 case 0xffffffff:
3236 case 0xfffffffe:
3237 case 0xfffffffc:
3238 return CC_NONE_0HIT;
3239
3240 case 0x00010000:
3241 case 0x00020000:
3242 return CC_CLOBBER;
3243
3244 case 0xffff0000:
3245 case 0xfffe0000:
3246 return CC_CLOBBER;
3247 }
3248
3249 /* See if we can finish with 4 bytes. */
3250 if ((intval & 0xffff) == 0)
3251 return CC_CLOBBER;
3252 }
3253
3254 return CC_SET_ZN;
3255 }
3256}
3257\f
cdfb02e8 3258/* Output a logical insn. */
3259
aa3382b1 3260const char *
3754d046 3261output_logical_op (machine_mode mode, rtx *operands)
6a8a3fa3 3262{
6ad7df02 3263 /* Figure out the logical op that we need to perform. */
3264 enum rtx_code code = GET_CODE (operands[3]);
6a8a3fa3 3265 /* Pretend that every byte is affected if both operands are registers. */
407921a5 3266 const unsigned HOST_WIDE_INT intval =
6a8a3fa3 3267 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
727c62dd 3268 /* Always use the full instruction if the
3269 first operand is in memory. It is better
3270 to use define_splits to generate the shorter
3271 sequence where valid. */
3272 && register_operand (operands[1], VOIDmode)
6a8a3fa3 3273 ? INTVAL (operands[2]) : 0x55555555);
3274 /* The determinant of the algorithm. If we perform an AND, 0
3275 affects a bit. Otherwise, 1 affects a bit. */
407921a5 3276 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
e6cf6c71 3277 /* Break up DET into pieces. */
3278 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3279 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
cdcf26ff 3280 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3281 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
e6cf6c71 3282 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3283 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3284 int lower_half_easy_p = 0;
3285 int upper_half_easy_p = 0;
6a8a3fa3 3286 /* The name of an insn. */
3287 const char *opname;
3288 char insn_buf[100];
3289
3290 switch (code)
3291 {
3292 case AND:
3293 opname = "and";
3294 break;
3295 case IOR:
3296 opname = "or";
3297 break;
3298 case XOR:
3299 opname = "xor";
3300 break;
3301 default:
3afe906b 3302 gcc_unreachable ();
6a8a3fa3 3303 }
3304
3305 switch (mode)
3306 {
916ace94 3307 case E_HImode:
6a8a3fa3 3308 /* First, see if we can finish with one insn. */
3309 if ((TARGET_H8300H || TARGET_H8300S)
cdcf26ff 3310 && b0 != 0
3311 && b1 != 0)
6a8a3fa3 3312 {
3313 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
3314 output_asm_insn (insn_buf, operands);
3315 }
3316 else
3317 {
3318 /* Take care of the lower byte. */
cdcf26ff 3319 if (b0 != 0)
6a8a3fa3 3320 {
3321 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
3322 output_asm_insn (insn_buf, operands);
3323 }
3324 /* Take care of the upper byte. */
cdcf26ff 3325 if (b1 != 0)
6a8a3fa3 3326 {
3327 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
3328 output_asm_insn (insn_buf, operands);
3329 }
3330 }
3331 break;
916ace94 3332 case E_SImode:
e6cf6c71 3333 if (TARGET_H8300H || TARGET_H8300S)
3334 {
3335 /* Determine if the lower half can be taken care of in no more
3336 than two bytes. */
3337 lower_half_easy_p = (b0 == 0
3338 || b1 == 0
3339 || (code != IOR && w0 == 0xffff));
3340
3341 /* Determine if the upper half can be taken care of in no more
3342 than two bytes. */
3343 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3344 || (code == AND && w1 == 0xff00));
3345 }
6a8a3fa3 3346
e6cf6c71 3347 /* Check if doing everything with one insn is no worse than
3348 using multiple insns. */
6a8a3fa3 3349 if ((TARGET_H8300H || TARGET_H8300S)
e6cf6c71 3350 && w0 != 0 && w1 != 0
0372ccb5 3351 && !(lower_half_easy_p && upper_half_easy_p)
3352 && !(code == IOR && w1 == 0xffff
3353 && (w0 & 0x8000) != 0 && lower_half_easy_p))
6a8a3fa3 3354 {
3355 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
3356 output_asm_insn (insn_buf, operands);
3357 }
3358 else
3359 {
3360 /* Take care of the lower and upper words individually. For
3361 each word, we try different methods in the order of
3362
3363 1) the special insn (in case of AND or XOR),
3364 2) the word-wise insn, and
3365 3) The byte-wise insn. */
cdcf26ff 3366 if (w0 == 0xffff
a9d986d9 3367 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
6a8a3fa3 3368 output_asm_insn ((code == AND)
b0422000 3369 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
6a8a3fa3 3370 operands);
3371 else if ((TARGET_H8300H || TARGET_H8300S)
cdcf26ff 3372 && (b0 != 0)
3373 && (b1 != 0))
6a8a3fa3 3374 {
3375 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
3376 output_asm_insn (insn_buf, operands);
3377 }
3378 else
3379 {
cdcf26ff 3380 if (b0 != 0)
6a8a3fa3 3381 {
3382 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
3383 output_asm_insn (insn_buf, operands);
3384 }
cdcf26ff 3385 if (b1 != 0)
6a8a3fa3 3386 {
3387 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
3388 output_asm_insn (insn_buf, operands);
3389 }
3390 }
3391
cdcf26ff 3392 if ((w1 == 0xffff)
a9d986d9 3393 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
6a8a3fa3 3394 output_asm_insn ((code == AND)
b0422000 3395 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
6a8a3fa3 3396 operands);
0372ccb5 3397 else if ((TARGET_H8300H || TARGET_H8300S)
3398 && code == IOR
3399 && w1 == 0xffff
3400 && (w0 & 0x8000) != 0)
3401 {
3402 output_asm_insn ("exts.l\t%S0", operands);
3403 }
f4bdef90 3404 else if ((TARGET_H8300H || TARGET_H8300S)
3405 && code == AND
cdcf26ff 3406 && w1 == 0xff00)
f4bdef90 3407 {
1c75fadf 3408 output_asm_insn ("extu.w\t%e0", operands);
f4bdef90 3409 }
6a8a3fa3 3410 else if (TARGET_H8300H || TARGET_H8300S)
3411 {
cdcf26ff 3412 if (w1 != 0)
6a8a3fa3 3413 {
3414 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
3415 output_asm_insn (insn_buf, operands);
3416 }
3417 }
3418 else
3419 {
cdcf26ff 3420 if (b2 != 0)
6a8a3fa3 3421 {
3422 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
3423 output_asm_insn (insn_buf, operands);
3424 }
cdcf26ff 3425 if (b3 != 0)
6a8a3fa3 3426 {
3427 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
3428 output_asm_insn (insn_buf, operands);
3429 }
3430 }
3431 }
3432 break;
3433 default:
3afe906b 3434 gcc_unreachable ();
6a8a3fa3 3435 }
3436 return "";
3437}
359e4f59 3438
cdfb02e8 3439/* Compute the length of a logical insn. */
3440
359e4f59 3441unsigned int
3754d046 3442compute_logical_op_length (machine_mode mode, rtx *operands)
359e4f59 3443{
6ad7df02 3444 /* Figure out the logical op that we need to perform. */
3445 enum rtx_code code = GET_CODE (operands[3]);
359e4f59 3446 /* Pretend that every byte is affected if both operands are registers. */
407921a5 3447 const unsigned HOST_WIDE_INT intval =
359e4f59 3448 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
727c62dd 3449 /* Always use the full instruction if the
3450 first operand is in memory. It is better
3451 to use define_splits to generate the shorter
3452 sequence where valid. */
3453 && register_operand (operands[1], VOIDmode)
359e4f59 3454 ? INTVAL (operands[2]) : 0x55555555);
3455 /* The determinant of the algorithm. If we perform an AND, 0
3456 affects a bit. Otherwise, 1 affects a bit. */
407921a5 3457 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
e6cf6c71 3458 /* Break up DET into pieces. */
3459 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3460 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
cdcf26ff 3461 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3462 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
e6cf6c71 3463 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3464 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3465 int lower_half_easy_p = 0;
3466 int upper_half_easy_p = 0;
359e4f59 3467 /* Insn length. */
3468 unsigned int length = 0;
3469
3470 switch (mode)
3471 {
916ace94 3472 case E_HImode:
359e4f59 3473 /* First, see if we can finish with one insn. */
3474 if ((TARGET_H8300H || TARGET_H8300S)
cdcf26ff 3475 && b0 != 0
3476 && b1 != 0)
359e4f59 3477 {
727c62dd 3478 length = h8300_length_from_table (operands[1], operands[2],
3479 &logicw_length_table);
359e4f59 3480 }
3481 else
3482 {
3483 /* Take care of the lower byte. */
cdcf26ff 3484 if (b0 != 0)
359e4f59 3485 length += 2;
3486
3487 /* Take care of the upper byte. */
cdcf26ff 3488 if (b1 != 0)
359e4f59 3489 length += 2;
3490 }
3491 break;
916ace94 3492 case E_SImode:
e6cf6c71 3493 if (TARGET_H8300H || TARGET_H8300S)
3494 {
3495 /* Determine if the lower half can be taken care of in no more
3496 than two bytes. */
3497 lower_half_easy_p = (b0 == 0
3498 || b1 == 0
3499 || (code != IOR && w0 == 0xffff));
3500
3501 /* Determine if the upper half can be taken care of in no more
3502 than two bytes. */
3503 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3504 || (code == AND && w1 == 0xff00));
3505 }
359e4f59 3506
e6cf6c71 3507 /* Check if doing everything with one insn is no worse than
3508 using multiple insns. */
359e4f59 3509 if ((TARGET_H8300H || TARGET_H8300S)
e6cf6c71 3510 && w0 != 0 && w1 != 0
0372ccb5 3511 && !(lower_half_easy_p && upper_half_easy_p)
3512 && !(code == IOR && w1 == 0xffff
3513 && (w0 & 0x8000) != 0 && lower_half_easy_p))
359e4f59 3514 {
727c62dd 3515 length = h8300_length_from_table (operands[1], operands[2],
3516 &logicl_length_table);
359e4f59 3517 }
3518 else
3519 {
3520 /* Take care of the lower and upper words individually. For
3521 each word, we try different methods in the order of
3522
3523 1) the special insn (in case of AND or XOR),
3524 2) the word-wise insn, and
3525 3) The byte-wise insn. */
cdcf26ff 3526 if (w0 == 0xffff
359e4f59 3527 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3528 {
3529 length += 2;
3530 }
3531 else if ((TARGET_H8300H || TARGET_H8300S)
cdcf26ff 3532 && (b0 != 0)
3533 && (b1 != 0))
359e4f59 3534 {
3535 length += 4;
3536 }
3537 else
3538 {
cdcf26ff 3539 if (b0 != 0)
359e4f59 3540 length += 2;
3541
cdcf26ff 3542 if (b1 != 0)
359e4f59 3543 length += 2;
3544 }
3545
cdcf26ff 3546 if (w1 == 0xffff
359e4f59 3547 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3548 {
3549 length += 2;
3550 }
0372ccb5 3551 else if ((TARGET_H8300H || TARGET_H8300S)
3552 && code == IOR
3553 && w1 == 0xffff
3554 && (w0 & 0x8000) != 0)
3555 {
3556 length += 2;
3557 }
f4bdef90 3558 else if ((TARGET_H8300H || TARGET_H8300S)
3559 && code == AND
cdcf26ff 3560 && w1 == 0xff00)
f4bdef90 3561 {
3562 length += 2;
3563 }
359e4f59 3564 else if (TARGET_H8300H || TARGET_H8300S)
3565 {
cdcf26ff 3566 if (w1 != 0)
359e4f59 3567 length += 4;
3568 }
3569 else
3570 {
cdcf26ff 3571 if (b2 != 0)
359e4f59 3572 length += 2;
3573
cdcf26ff 3574 if (b3 != 0)
359e4f59 3575 length += 2;
3576 }
3577 }
3578 break;
3579 default:
3afe906b 3580 gcc_unreachable ();
359e4f59 3581 }
3582 return length;
3583}
6ad7df02 3584
cdfb02e8 3585/* Compute which flag bits are valid after a logical insn. */
3586
539b539f 3587enum attr_cc
3754d046 3588compute_logical_op_cc (machine_mode mode, rtx *operands)
6ad7df02 3589{
3590 /* Figure out the logical op that we need to perform. */
3591 enum rtx_code code = GET_CODE (operands[3]);
3592 /* Pretend that every byte is affected if both operands are registers. */
407921a5 3593 const unsigned HOST_WIDE_INT intval =
6ad7df02 3594 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
727c62dd 3595 /* Always use the full instruction if the
3596 first operand is in memory. It is better
3597 to use define_splits to generate the shorter
3598 sequence where valid. */
3599 && register_operand (operands[1], VOIDmode)
6ad7df02 3600 ? INTVAL (operands[2]) : 0x55555555);
3601 /* The determinant of the algorithm. If we perform an AND, 0
3602 affects a bit. Otherwise, 1 affects a bit. */
407921a5 3603 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
e6cf6c71 3604 /* Break up DET into pieces. */
3605 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3606 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3607 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3608 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3609 int lower_half_easy_p = 0;
3610 int upper_half_easy_p = 0;
6ad7df02 3611 /* Condition code. */
3612 enum attr_cc cc = CC_CLOBBER;
3613
3614 switch (mode)
3615 {
916ace94 3616 case E_HImode:
6ad7df02 3617 /* First, see if we can finish with one insn. */
3618 if ((TARGET_H8300H || TARGET_H8300S)
cdcf26ff 3619 && b0 != 0
3620 && b1 != 0)
6ad7df02 3621 {
3622 cc = CC_SET_ZNV;
3623 }
3624 break;
916ace94 3625 case E_SImode:
e6cf6c71 3626 if (TARGET_H8300H || TARGET_H8300S)
3627 {
3628 /* Determine if the lower half can be taken care of in no more
3629 than two bytes. */
3630 lower_half_easy_p = (b0 == 0
3631 || b1 == 0
3632 || (code != IOR && w0 == 0xffff));
3633
3634 /* Determine if the upper half can be taken care of in no more
3635 than two bytes. */
3636 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3637 || (code == AND && w1 == 0xff00));
3638 }
6ad7df02 3639
e6cf6c71 3640 /* Check if doing everything with one insn is no worse than
3641 using multiple insns. */
6ad7df02 3642 if ((TARGET_H8300H || TARGET_H8300S)
e6cf6c71 3643 && w0 != 0 && w1 != 0
0372ccb5 3644 && !(lower_half_easy_p && upper_half_easy_p)
3645 && !(code == IOR && w1 == 0xffff
3646 && (w0 & 0x8000) != 0 && lower_half_easy_p))
6ad7df02 3647 {
3648 cc = CC_SET_ZNV;
3649 }
0372ccb5 3650 else
3651 {
3652 if ((TARGET_H8300H || TARGET_H8300S)
3653 && code == IOR
3654 && w1 == 0xffff
3655 && (w0 & 0x8000) != 0)
3656 {
3657 cc = CC_SET_ZNV;
3658 }
3659 }
6ad7df02 3660 break;
3661 default:
3afe906b 3662 gcc_unreachable ();
6ad7df02 3663 }
3664 return cc;
3665}
6a8a3fa3 3666\f
ab5a13fd 3667/* Expand a conditional branch. */
3668
3669void
74f4459c 3670h8300_expand_branch (rtx operands[])
ab5a13fd 3671{
74f4459c 3672 enum rtx_code code = GET_CODE (operands[0]);
3673 rtx op0 = operands[1];
3674 rtx op1 = operands[2];
3675 rtx label = operands[3];
ab5a13fd 3676 rtx tmp;
3677
74f4459c 3678 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
d1f9b275 3679 emit_insn (gen_rtx_SET (cc0_rtx, tmp));
74f4459c 3680
ab5a13fd 3681 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
3682 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
3683 gen_rtx_LABEL_REF (VOIDmode, label),
3684 pc_rtx);
d1f9b275 3685 emit_jump_insn (gen_rtx_SET (pc_rtx, tmp));
ab5a13fd 3686}
74f4459c 3687
3688
3689/* Expand a conditional store. */
3690
3691void
3692h8300_expand_store (rtx operands[])
3693{
3694 rtx dest = operands[0];
3695 enum rtx_code code = GET_CODE (operands[1]);
3696 rtx op0 = operands[2];
3697 rtx op1 = operands[3];
3698 rtx tmp;
3699
3700 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
d1f9b275 3701 emit_insn (gen_rtx_SET (cc0_rtx, tmp));
74f4459c 3702
3703 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx);
d1f9b275 3704 emit_insn (gen_rtx_SET (dest, tmp));
74f4459c 3705}
ab5a13fd 3706\f
b839e0b4 3707/* Shifts.
3708
f465f633 3709 We devote a fair bit of code to getting efficient shifts since we
3710 can only shift one bit at a time on the H8/300 and H8/300H and only
11f95d7c 3711 one or two bits at a time on the H8S.
f465f633 3712
3713 All shift code falls into one of the following ways of
3714 implementation:
3715
3716 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3717 when a straight line shift is about the same size or smaller than
3718 a loop.
3719
3720 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3721 off the bits we don't need. This is used when only a few of the
3722 bits in the original value will survive in the shifted value.
3723
3724 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3725 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3726 shifts can be added if the shift count is slightly more than 8 or
3727 16. This case also includes other oddballs that are not worth
cc72e60a 3728 explaining here.
f465f633 3729
11f95d7c 3730 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
f465f633 3731
140ee624 3732 For each shift count, we try to use code that has no trade-off
3733 between code size and speed whenever possible.
3734
3735 If the trade-off is unavoidable, we try to be reasonable.
3736 Specifically, the fastest version is one instruction longer than
3737 the shortest version, we take the fastest version. We also provide
3738 the use a way to switch back to the shortest version with -Os.
3739
3740 For the details of the shift algorithms for various shift counts,
3741 refer to shift_alg_[qhs]i. */
e1629549 3742
727c62dd 3743/* Classify a shift with the given mode and code. OP is the shift amount. */
3744
3745enum h8sx_shift_type
3754d046 3746h8sx_classify_shift (machine_mode mode, enum rtx_code code, rtx op)
727c62dd 3747{
3748 if (!TARGET_H8300SX)
3749 return H8SX_SHIFT_NONE;
3750
3751 switch (code)
3752 {
3753 case ASHIFT:
3754 case LSHIFTRT:
3755 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3756 if (GET_CODE (op) != CONST_INT)
3757 return H8SX_SHIFT_BINARY;
3758
3759 /* Reject out-of-range shift amounts. */
3760 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
3761 return H8SX_SHIFT_NONE;
3762
3763 /* Power-of-2 shifts are effectively unary operations. */
3764 if (exact_log2 (INTVAL (op)) >= 0)
3765 return H8SX_SHIFT_UNARY;
3766
3767 return H8SX_SHIFT_BINARY;
3768
3769 case ASHIFTRT:
3770 if (op == const1_rtx || op == const2_rtx)
3771 return H8SX_SHIFT_UNARY;
3772 return H8SX_SHIFT_NONE;
3773
3774 case ROTATE:
3775 if (GET_CODE (op) == CONST_INT
3776 && (INTVAL (op) == 1
3777 || INTVAL (op) == 2
3778 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
3779 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
3780 return H8SX_SHIFT_UNARY;
3781 return H8SX_SHIFT_NONE;
3782
3783 default:
3784 return H8SX_SHIFT_NONE;
3785 }
3786}
3787
727c62dd 3788/* Return the asm template for a single h8sx shift instruction.
3789 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3790 is the source and OPERANDS[3] is the shift. SUFFIX is the
87ad9aff 3791 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
727c62dd 3792 prefix for the destination operand. */
3793
3794const char *
3795output_h8sx_shift (rtx *operands, int suffix, int optype)
3796{
3797 static char buffer[16];
3798 const char *stem;
3799
3800 switch (GET_CODE (operands[3]))
3801 {
3802 case ASHIFT:
3803 stem = "shll";
3804 break;
3805
3806 case ASHIFTRT:
3807 stem = "shar";
3808 break;
3809
3810 case LSHIFTRT:
3811 stem = "shlr";
3812 break;
3813
3814 case ROTATE:
3815 stem = "rotl";
3816 if (INTVAL (operands[2]) > 2)
3817 {
3818 /* This is really a right rotate. */
3819 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
3820 - INTVAL (operands[2]));
3821 stem = "rotr";
3822 }
3823 break;
3824
3825 default:
3afe906b 3826 gcc_unreachable ();
727c62dd 3827 }
3828 if (operands[2] == const1_rtx)
3829 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
3830 else
3831 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
3832 return buffer;
3833}
b839e0b4 3834
6b07073d 3835/* Emit code to do shifts. */
b839e0b4 3836
727c62dd 3837bool
3754d046 3838expand_a_shift (machine_mode mode, enum rtx_code code, rtx operands[])
e1629549 3839{
727c62dd 3840 switch (h8sx_classify_shift (mode, code, operands[2]))
3841 {
3842 case H8SX_SHIFT_BINARY:
3843 operands[1] = force_reg (mode, operands[1]);
3844 return false;
3845
3846 case H8SX_SHIFT_UNARY:
3847 return false;
3848
3849 case H8SX_SHIFT_NONE:
3850 break;
3851 }
3852
d3652418 3853 emit_move_insn (copy_rtx (operands[0]), operands[1]);
e1629549 3854
eb2aa24e 3855 /* Need a loop to get all the bits we want - we generate the
3856 code at emit time, but need to allocate a scratch reg now. */
b839e0b4 3857
7014838c 3858 emit_insn (gen_rtx_PARALLEL
3859 (VOIDmode,
b839e0b4 3860 gen_rtvec (2,
d1f9b275 3861 gen_rtx_SET (copy_rtx (operands[0]),
dc55b8a9 3862 gen_rtx_fmt_ee (code, mode,
d3652418 3863 copy_rtx (operands[0]), operands[2])),
7014838c 3864 gen_rtx_CLOBBER (VOIDmode,
3865 gen_rtx_SCRATCH (QImode)))));
727c62dd 3866 return true;
b839e0b4 3867}
3868
b839e0b4 3869/* Symbols of the various modes which can be used as indices. */
3870
3871enum shift_mode
27276a3b 3872{
3873 QIshift, HIshift, SIshift
3874};
b839e0b4 3875
30c992ef 3876/* For single bit shift insns, record assembler and what bits of the
3877 condition code are valid afterwards (represented as various CC_FOO
3878 bits, 0 means CC isn't left in a usable state). */
b839e0b4 3879
3880struct shift_insn
3881{
e99c3a1d 3882 const char *const assembler;
539b539f 3883 const enum attr_cc cc_valid;
b839e0b4 3884};
3885
3886/* Assembler instruction shift table.
3887
3888 These tables are used to look up the basic shifts.
eb2aa24e 3889 They are indexed by cpu, shift_type, and mode. */
e1629549 3890
b839e0b4 3891static const struct shift_insn shift_one[2][3][3] =
3892{
3893/* H8/300 */
3894 {
3895/* SHIFT_ASHIFT */
3896 {
fd7729c5 3897 { "shll\t%X0", CC_SET_ZNV },
3898 { "add.w\t%T0,%T0", CC_SET_ZN },
3899 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
b839e0b4 3900 },
3901/* SHIFT_LSHIFTRT */
3902 {
fd7729c5 3903 { "shlr\t%X0", CC_SET_ZNV },
3904 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3905 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
b839e0b4 3906 },
3907/* SHIFT_ASHIFTRT */
3908 {
fd7729c5 3909 { "shar\t%X0", CC_SET_ZNV },
3910 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3911 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
b839e0b4 3912 }
3913 },
3914/* H8/300H */
3915 {
3916/* SHIFT_ASHIFT */
3917 {
fd7729c5 3918 { "shll.b\t%X0", CC_SET_ZNV },
3919 { "shll.w\t%T0", CC_SET_ZNV },
3920 { "shll.l\t%S0", CC_SET_ZNV }
b839e0b4 3921 },
3922/* SHIFT_LSHIFTRT */
3923 {
fd7729c5 3924 { "shlr.b\t%X0", CC_SET_ZNV },
3925 { "shlr.w\t%T0", CC_SET_ZNV },
3926 { "shlr.l\t%S0", CC_SET_ZNV }
b839e0b4 3927 },
3928/* SHIFT_ASHIFTRT */
3929 {
fd7729c5 3930 { "shar.b\t%X0", CC_SET_ZNV },
3931 { "shar.w\t%T0", CC_SET_ZNV },
3932 { "shar.l\t%S0", CC_SET_ZNV }
b839e0b4 3933 }
3934 }
3935};
e1629549 3936
52abe980 3937static const struct shift_insn shift_two[3][3] =
3938{
3939/* SHIFT_ASHIFT */
3940 {
fd7729c5 3941 { "shll.b\t#2,%X0", CC_SET_ZNV },
3942 { "shll.w\t#2,%T0", CC_SET_ZNV },
3943 { "shll.l\t#2,%S0", CC_SET_ZNV }
52abe980 3944 },
3945/* SHIFT_LSHIFTRT */
3946 {
fd7729c5 3947 { "shlr.b\t#2,%X0", CC_SET_ZNV },
3948 { "shlr.w\t#2,%T0", CC_SET_ZNV },
3949 { "shlr.l\t#2,%S0", CC_SET_ZNV }
52abe980 3950 },
3951/* SHIFT_ASHIFTRT */
3952 {
fd7729c5 3953 { "shar.b\t#2,%X0", CC_SET_ZNV },
3954 { "shar.w\t#2,%T0", CC_SET_ZNV },
3955 { "shar.l\t#2,%S0", CC_SET_ZNV }
52abe980 3956 }
3957};
3958
b839e0b4 3959/* Rotates are organized by which shift they'll be used in implementing.
3960 There's no need to record whether the cc is valid afterwards because
3961 it is the AND insn that will decide this. */
e1629549 3962
b839e0b4 3963static const char *const rotate_one[2][3][3] =
3964{
3965/* H8/300 */
3966 {
3967/* SHIFT_ASHIFT */
3968 {
52abe980 3969 "rotr\t%X0",
3970 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
b839e0b4 3971 0
3972 },
3973/* SHIFT_LSHIFTRT */
3974 {
52abe980 3975 "rotl\t%X0",
3976 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
b839e0b4 3977 0
3978 },
3979/* SHIFT_ASHIFTRT */
3980 {
52abe980 3981 "rotl\t%X0",
3982 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
b839e0b4 3983 0
e1629549 3984 }
b839e0b4 3985 },
3986/* H8/300H */
3987 {
3988/* SHIFT_ASHIFT */
3989 {
52abe980 3990 "rotr.b\t%X0",
3991 "rotr.w\t%T0",
3992 "rotr.l\t%S0"
b839e0b4 3993 },
3994/* SHIFT_LSHIFTRT */
e1629549 3995 {
52abe980 3996 "rotl.b\t%X0",
3997 "rotl.w\t%T0",
3998 "rotl.l\t%S0"
b839e0b4 3999 },
4000/* SHIFT_ASHIFTRT */
4001 {
52abe980 4002 "rotl.b\t%X0",
4003 "rotl.w\t%T0",
4004 "rotl.l\t%S0"
b839e0b4 4005 }
4006 }
4007};
4008
52abe980 4009static const char *const rotate_two[3][3] =
4010{
4011/* SHIFT_ASHIFT */
4012 {
4013 "rotr.b\t#2,%X0",
4014 "rotr.w\t#2,%T0",
4015 "rotr.l\t#2,%S0"
4016 },
4017/* SHIFT_LSHIFTRT */
4018 {
4019 "rotl.b\t#2,%X0",
4020 "rotl.w\t#2,%T0",
4021 "rotl.l\t#2,%S0"
4022 },
4023/* SHIFT_ASHIFTRT */
4024 {
4025 "rotl.b\t#2,%X0",
4026 "rotl.w\t#2,%T0",
4027 "rotl.l\t#2,%S0"
4028 }
4029};
4030
4765dbab 4031struct shift_info {
4032 /* Shift algorithm. */
4033 enum shift_alg alg;
4034
4035 /* The number of bits to be shifted by shift1 and shift2. Valid
4036 when ALG is SHIFT_SPECIAL. */
4037 unsigned int remainder;
4038
4039 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
4040 const char *special;
4041
4042 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
c46dc351 4043 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4765dbab 4044 const char *shift1;
4045
4046 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
c46dc351 4047 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4765dbab 4048 const char *shift2;
4049
fd7729c5 4050 /* CC status for SHIFT_INLINE. */
539b539f 4051 enum attr_cc cc_inline;
fd7729c5 4052
4053 /* CC status for SHIFT_SPECIAL. */
539b539f 4054 enum attr_cc cc_special;
4765dbab 4055};
4056
230002f2 4057static void get_shift_alg (enum shift_type,
4058 enum shift_mode, unsigned int,
4059 struct shift_info *);
9305fe33 4060
ec0b80c6 4061/* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
4062 best algorithm for doing the shift. The assembler code is stored
140ee624 4063 in the pointers in INFO. We achieve the maximum efficiency in most
4064 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
4065 SImode in particular have a lot of room to optimize.
4066
4067 We first determine the strategy of the shift algorithm by a table
4068 lookup. If that tells us to use a hand crafted assembly code, we
4069 go into the big switch statement to find what that is. Otherwise,
4070 we resort to a generic way, such as inlining. In either case, the
4071 result is returned through INFO. */
b839e0b4 4072
5a40b38e 4073static void
230002f2 4074get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
4075 unsigned int count, struct shift_info *info)
b839e0b4 4076{
5d822c00 4077 enum h8_cpu cpu;
58285553 4078
4079 /* Find the target CPU. */
4080 if (TARGET_H8300)
5d822c00 4081 cpu = H8_300;
acff2768 4082 else if (TARGET_H8300S)
5d822c00 4083 cpu = H8_S;
acff2768 4084 else
4085 cpu = H8_300H;
58285553 4086
ce8940f6 4087 /* Find the shift algorithm. */
5d822c00 4088 info->alg = SHIFT_LOOP;
b839e0b4 4089 switch (shift_mode)
4090 {
4091 case QIshift:
5d822c00 4092 if (count < GET_MODE_BITSIZE (QImode))
ce8940f6 4093 info->alg = shift_alg_qi[cpu][shift_type][count];
4094 break;
58285553 4095
ce8940f6 4096 case HIshift:
5d822c00 4097 if (count < GET_MODE_BITSIZE (HImode))
ce8940f6 4098 info->alg = shift_alg_hi[cpu][shift_type][count];
4099 break;
4100
4101 case SIshift:
5d822c00 4102 if (count < GET_MODE_BITSIZE (SImode))
ce8940f6 4103 info->alg = shift_alg_si[cpu][shift_type][count];
4104 break;
4105
4106 default:
3afe906b 4107 gcc_unreachable ();
ce8940f6 4108 }
4109
4110 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4111 switch (info->alg)
4112 {
4113 case SHIFT_INLINE:
4114 info->remainder = count;
4115 /* Fall through. */
4116
4117 case SHIFT_LOOP:
4118 /* It is up to the caller to know that looping clobbers cc. */
4119 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4120 info->shift2 = shift_two[shift_type][shift_mode].assembler;
fd7729c5 4121 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
ce8940f6 4122 goto end;
4123
4124 case SHIFT_ROT_AND:
4125 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
4126 info->shift2 = rotate_two[shift_type][shift_mode];
fd7729c5 4127 info->cc_inline = CC_CLOBBER;
ce8940f6 4128 goto end;
4129
4130 case SHIFT_SPECIAL:
4131 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4132 info->remainder = 0;
4133 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4134 info->shift2 = shift_two[shift_type][shift_mode].assembler;
fd7729c5 4135 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4136 info->cc_special = CC_CLOBBER;
ce8940f6 4137 break;
4138 }
52abe980 4139
ce8940f6 4140 /* Here we only deal with SHIFT_SPECIAL. */
4141 switch (shift_mode)
4142 {
4143 case QIshift:
58285553 4144 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4145 through the entire value. */
3afe906b 4146 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
4147 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
4148 goto end;
58285553 4149
4150 case HIshift:
58285553 4151 if (count == 7)
52abe980 4152 {
79b29436 4153 switch (shift_type)
52abe980 4154 {
79b29436 4155 case SHIFT_ASHIFT:
4156 if (TARGET_H8300)
4157 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4158 else
4159 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
606a6902 4160 goto end;
79b29436 4161 case SHIFT_LSHIFTRT:
4162 if (TARGET_H8300)
4163 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4164 else
4165 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
606a6902 4166 goto end;
79b29436 4167 case SHIFT_ASHIFTRT:
4765dbab 4168 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
606a6902 4169 goto end;
b839e0b4 4170 }
e1629549 4171 }
a033fe93 4172 else if ((8 <= count && count <= 13)
8796f52f 4173 || (TARGET_H8300S && count == 14))
e1629549 4174 {
8db8f925 4175 info->remainder = count - 8;
4176
52abe980 4177 switch (shift_type)
b839e0b4 4178 {
52abe980 4179 case SHIFT_ASHIFT:
4765dbab 4180 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
606a6902 4181 goto end;
52abe980 4182 case SHIFT_LSHIFTRT:
903ae79d 4183 if (TARGET_H8300)
4184 {
4185 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4186 info->shift1 = "shlr.b\t%s0";
fd7729c5 4187 info->cc_inline = CC_SET_ZNV;
903ae79d 4188 }
4189 else
4190 {
4191 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
fd7729c5 4192 info->cc_special = CC_SET_ZNV;
903ae79d 4193 }
606a6902 4194 goto end;
52abe980 4195 case SHIFT_ASHIFTRT:
4196 if (TARGET_H8300)
903ae79d 4197 {
4198 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4199 info->shift1 = "shar.b\t%s0";
903ae79d 4200 }
52abe980 4201 else
903ae79d 4202 {
4203 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
fd7729c5 4204 info->cc_special = CC_SET_ZNV;
903ae79d 4205 }
606a6902 4206 goto end;
52abe980 4207 }
4208 }
a0bbe9df 4209 else if (count == 14)
4210 {
4211 switch (shift_type)
4212 {
4213 case SHIFT_ASHIFT:
4214 if (TARGET_H8300)
4215 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4216 goto end;
4217 case SHIFT_LSHIFTRT:
4218 if (TARGET_H8300)
4219 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4220 goto end;
4221 case SHIFT_ASHIFTRT:
4222 if (TARGET_H8300)
4223 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4224 else if (TARGET_H8300H)
fd7729c5 4225 {
4226 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4227 info->cc_special = CC_SET_ZNV;
4228 }
a0bbe9df 4229 else /* TARGET_H8300S */
3afe906b 4230 gcc_unreachable ();
a0bbe9df 4231 goto end;
4232 }
4233 }
f76e2664 4234 else if (count == 15)
52abe980 4235 {
f76e2664 4236 switch (shift_type)
4237 {
4238 case SHIFT_ASHIFT:
4239 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4240 goto end;
4241 case SHIFT_LSHIFTRT:
4242 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4243 goto end;
4244 case SHIFT_ASHIFTRT:
4245 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4246 goto end;
4247 }
e1629549 4248 }
3afe906b 4249 gcc_unreachable ();
52abe980 4250
b839e0b4 4251 case SIshift:
f76e2664 4252 if (TARGET_H8300 && 8 <= count && count <= 9)
b839e0b4 4253 {
f76e2664 4254 info->remainder = count - 8;
4255
52abe980 4256 switch (shift_type)
b839e0b4 4257 {
52abe980 4258 case SHIFT_ASHIFT:
4765dbab 4259 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
606a6902 4260 goto end;
52abe980 4261 case SHIFT_LSHIFTRT:
4765dbab 4262 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
f76e2664 4263 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
606a6902 4264 goto end;
52abe980 4265 case SHIFT_ASHIFTRT:
4765dbab 4266 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
606a6902 4267 goto end;
b839e0b4 4268 }
b839e0b4 4269 }
9bbc06f2 4270 else if (count == 8 && !TARGET_H8300)
4271 {
4272 switch (shift_type)
4273 {
4274 case SHIFT_ASHIFT:
4765dbab 4275 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
606a6902 4276 goto end;
9bbc06f2 4277 case SHIFT_LSHIFTRT:
4765dbab 4278 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
606a6902 4279 goto end;
9bbc06f2 4280 case SHIFT_ASHIFTRT:
4765dbab 4281 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
606a6902 4282 goto end;
9bbc06f2 4283 }
4284 }
f76e2664 4285 else if (count == 15 && TARGET_H8300)
4286 {
4287 switch (shift_type)
4288 {
4289 case SHIFT_ASHIFT:
3afe906b 4290 gcc_unreachable ();
f76e2664 4291 case SHIFT_LSHIFTRT:
a6f6d86d 4292 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
f76e2664 4293 goto end;
4294 case SHIFT_ASHIFTRT:
a6f6d86d 4295 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
f76e2664 4296 goto end;
4297 }
4298 }
37e1f65a 4299 else if (count == 15 && !TARGET_H8300)
4300 {
4301 switch (shift_type)
4302 {
4303 case SHIFT_ASHIFT:
4304 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
fd7729c5 4305 info->cc_special = CC_SET_ZNV;
37e1f65a 4306 goto end;
4307 case SHIFT_LSHIFTRT:
d2079f6d 4308 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
fd7729c5 4309 info->cc_special = CC_SET_ZNV;
37e1f65a 4310 goto end;
7913b5f4 4311 case SHIFT_ASHIFTRT:
3afe906b 4312 gcc_unreachable ();
37e1f65a 4313 }
4314 }
f76e2664 4315 else if ((TARGET_H8300 && 16 <= count && count <= 20)
8db8f925 4316 || (TARGET_H8300H && 16 <= count && count <= 19)
776e0da8 4317 || (TARGET_H8300S && 16 <= count && count <= 21))
b839e0b4 4318 {
8db8f925 4319 info->remainder = count - 16;
4320
b839e0b4 4321 switch (shift_type)
4322 {
4323 case SHIFT_ASHIFT:
4765dbab 4324 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
f76e2664 4325 if (TARGET_H8300)
a033fe93 4326 info->shift1 = "add.w\t%e0,%e0";
606a6902 4327 goto end;
52abe980 4328 case SHIFT_LSHIFTRT:
f76e2664 4329 if (TARGET_H8300)
4330 {
903ae79d 4331 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4332 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
f76e2664 4333 }
4334 else
4335 {
903ae79d 4336 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
fd7729c5 4337 info->cc_special = CC_SET_ZNV;
f76e2664 4338 }
606a6902 4339 goto end;
52abe980 4340 case SHIFT_ASHIFTRT:
4341 if (TARGET_H8300)
f76e2664 4342 {
4343 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4344 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
4345 }
52abe980 4346 else
f76e2664 4347 {
4348 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
fd7729c5 4349 info->cc_special = CC_SET_ZNV;
f76e2664 4350 }
606a6902 4351 goto end;
52abe980 4352 }
4353 }
f76e2664 4354 else if (TARGET_H8300 && 24 <= count && count <= 28)
81c3eb11 4355 {
4356 info->remainder = count - 24;
f2702e8a 4357
81c3eb11 4358 switch (shift_type)
4359 {
4360 case SHIFT_ASHIFT:
4361 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4362 info->shift1 = "shll.b\t%z0";
fd7729c5 4363 info->cc_inline = CC_SET_ZNV;
81c3eb11 4364 goto end;
4365 case SHIFT_LSHIFTRT:
4366 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4367 info->shift1 = "shlr.b\t%w0";
fd7729c5 4368 info->cc_inline = CC_SET_ZNV;
81c3eb11 4369 goto end;
4370 case SHIFT_ASHIFTRT:
17b364c4 4371 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
81c3eb11 4372 info->shift1 = "shar.b\t%w0";
fd7729c5 4373 info->cc_inline = CC_SET_ZNV;
b44470aa 4374 goto end;
4375 }
4376 }
0d219270 4377 else if ((TARGET_H8300H && count == 24)
4378 || (TARGET_H8300S && 24 <= count && count <= 25))
9bbc06f2 4379 {
0d219270 4380 info->remainder = count - 24;
4381
9bbc06f2 4382 switch (shift_type)
4383 {
4384 case SHIFT_ASHIFT:
4765dbab 4385 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
606a6902 4386 goto end;
9bbc06f2 4387 case SHIFT_LSHIFTRT:
4765dbab 4388 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
fd7729c5 4389 info->cc_special = CC_SET_ZNV;
606a6902 4390 goto end;
9bbc06f2 4391 case SHIFT_ASHIFTRT:
4765dbab 4392 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
fd7729c5 4393 info->cc_special = CC_SET_ZNV;
606a6902 4394 goto end;
9bbc06f2 4395 }
4396 }
567c4b66 4397 else if (!TARGET_H8300 && count == 28)
4398 {
4399 switch (shift_type)
4400 {
4401 case SHIFT_ASHIFT:
4402 if (TARGET_H8300H)
4403 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4404 else
4405 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
567c4b66 4406 goto end;
4407 case SHIFT_LSHIFTRT:
4408 if (TARGET_H8300H)
fd7729c5 4409 {
4410 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4411 info->cc_special = CC_SET_ZNV;
4412 }
567c4b66 4413 else
903ae79d 4414 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
567c4b66 4415 goto end;
4416 case SHIFT_ASHIFTRT:
3afe906b 4417 gcc_unreachable ();
567c4b66 4418 }
4419 }
4420 else if (!TARGET_H8300 && count == 29)
4421 {
4422 switch (shift_type)
4423 {
4424 case SHIFT_ASHIFT:
4425 if (TARGET_H8300H)
4426 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4427 else
4428 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
567c4b66 4429 goto end;
4430 case SHIFT_LSHIFTRT:
4431 if (TARGET_H8300H)
fd7729c5 4432 {
4433 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4434 info->cc_special = CC_SET_ZNV;
4435 }
567c4b66 4436 else
fd7729c5 4437 {
4438 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4439 info->cc_special = CC_SET_ZNV;
4440 }
567c4b66 4441 goto end;
4442 case SHIFT_ASHIFTRT:
3afe906b 4443 gcc_unreachable ();
567c4b66 4444 }
4445 }
4446 else if (!TARGET_H8300 && count == 30)
4447 {
4448 switch (shift_type)
4449 {
4450 case SHIFT_ASHIFT:
4451 if (TARGET_H8300H)
4452 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4453 else
4454 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
567c4b66 4455 goto end;
4456 case SHIFT_LSHIFTRT:
4457 if (TARGET_H8300H)
903ae79d 4458 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
567c4b66 4459 else
903ae79d 4460 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
567c4b66 4461 goto end;
4462 case SHIFT_ASHIFTRT:
3afe906b 4463 gcc_unreachable ();
567c4b66 4464 }
4465 }
b839e0b4 4466 else if (count == 31)
4467 {
37e1f65a 4468 if (TARGET_H8300)
b839e0b4 4469 {
37e1f65a 4470 switch (shift_type)
4471 {
4472 case SHIFT_ASHIFT:
4473 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4474 goto end;
4475 case SHIFT_LSHIFTRT:
4476 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4477 goto end;
4478 case SHIFT_ASHIFTRT:
4479 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4480 goto end;
4481 }
b839e0b4 4482 }
4483 else
4484 {
37e1f65a 4485 switch (shift_type)
b839e0b4 4486 {
37e1f65a 4487 case SHIFT_ASHIFT:
4488 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
fd7729c5 4489 info->cc_special = CC_SET_ZNV;
37e1f65a 4490 goto end;
4491 case SHIFT_LSHIFTRT:
4492 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
fd7729c5 4493 info->cc_special = CC_SET_ZNV;
37e1f65a 4494 goto end;
4495 case SHIFT_ASHIFTRT:
903ae79d 4496 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
fd7729c5 4497 info->cc_special = CC_SET_ZNV;
606a6902 4498 goto end;
b839e0b4 4499 }
b839e0b4 4500 }
4501 }
3afe906b 4502 gcc_unreachable ();
52abe980 4503
b839e0b4 4504 default:
3afe906b 4505 gcc_unreachable ();
e1629549 4506 }
b839e0b4 4507
5a40b38e 4508 end:
4509 if (!TARGET_H8300S)
4510 info->shift2 = NULL;
e1629549 4511}
4512
6b30b2e6 4513/* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4514 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4515
4516int
3754d046 4517h8300_shift_needs_scratch_p (int count, machine_mode mode)
6b30b2e6 4518{
5d822c00 4519 enum h8_cpu cpu;
6b30b2e6 4520 int a, lr, ar;
4521
4522 if (GET_MODE_BITSIZE (mode) <= count)
4523 return 1;
4524
4525 /* Find out the target CPU. */
4526 if (TARGET_H8300)
5d822c00 4527 cpu = H8_300;
acff2768 4528 else if (TARGET_H8300S)
5d822c00 4529 cpu = H8_S;
acff2768 4530 else
4531 cpu = H8_300H;
6b30b2e6 4532
4533 /* Find the shift algorithm. */
4534 switch (mode)
4535 {
916ace94 4536 case E_QImode:
6b30b2e6 4537 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
4538 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
4539 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
4540 break;
4541
916ace94 4542 case E_HImode:
6b30b2e6 4543 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
4544 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
4545 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
4546 break;
4547
916ace94 4548 case E_SImode:
6b30b2e6 4549 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
4550 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
4551 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
4552 break;
4553
4554 default:
3afe906b 4555 gcc_unreachable ();
6b30b2e6 4556 }
4557
33a9c2d6 4558 /* On H8/300H, count == 8 uses a scratch register. */
6b30b2e6 4559 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
c6ff55c2 4560 || (TARGET_H8300H && mode == SImode && count == 8));
6b30b2e6 4561}
4562
cdfb02e8 4563/* Output the assembler code for doing shifts. */
b839e0b4 4564
9305fe33 4565const char *
230002f2 4566output_a_shift (rtx *operands)
e1629549 4567{
b839e0b4 4568 static int loopend_lab;
b839e0b4 4569 rtx shift = operands[3];
3754d046 4570 machine_mode mode = GET_MODE (shift);
b839e0b4 4571 enum rtx_code code = GET_CODE (shift);
4572 enum shift_type shift_type;
4573 enum shift_mode shift_mode;
4765dbab 4574 struct shift_info info;
3afe906b 4575 int n;
b839e0b4 4576
4577 loopend_lab++;
4578
4579 switch (mode)
4580 {
916ace94 4581 case E_QImode:
b839e0b4 4582 shift_mode = QIshift;
4583 break;
916ace94 4584 case E_HImode:
b839e0b4 4585 shift_mode = HIshift;
4586 break;
916ace94 4587 case E_SImode:
b839e0b4 4588 shift_mode = SIshift;
4589 break;
4590 default:
3afe906b 4591 gcc_unreachable ();
b839e0b4 4592 }
e1629549 4593
b839e0b4 4594 switch (code)
e1629549 4595 {
b839e0b4 4596 case ASHIFTRT:
4597 shift_type = SHIFT_ASHIFTRT;
4598 break;
4599 case LSHIFTRT:
4600 shift_type = SHIFT_LSHIFTRT;
4601 break;
4602 case ASHIFT:
4603 shift_type = SHIFT_ASHIFT;
4604 break;
4605 default:
3afe906b 4606 gcc_unreachable ();
b839e0b4 4607 }
e1629549 4608
3afe906b 4609 /* This case must be taken care of by one of the two splitters
4610 that convert a variable shift into a loop. */
4611 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4612
4613 n = INTVAL (operands[2]);
4614
4615 /* If the count is negative, make it 0. */
4616 if (n < 0)
4617 n = 0;
4618 /* If the count is too big, truncate it.
4619 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4620 do the intuitive thing. */
4621 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4622 n = GET_MODE_BITSIZE (mode);
4623
4624 get_shift_alg (shift_type, shift_mode, n, &info);
4625
4626 switch (info.alg)
b839e0b4 4627 {
3afe906b 4628 case SHIFT_SPECIAL:
4629 output_asm_insn (info.special, operands);
4630 /* Fall through. */
b839e0b4 4631
3afe906b 4632 case SHIFT_INLINE:
4633 n = info.remainder;
b839e0b4 4634
3afe906b 4635 /* Emit two bit shifts first. */
4636 if (info.shift2 != NULL)
b839e0b4 4637 {
3afe906b 4638 for (; n > 1; n -= 2)
4639 output_asm_insn (info.shift2, operands);
4640 }
52abe980 4641
3afe906b 4642 /* Now emit one bit shifts for any residual. */
4643 for (; n > 0; n--)
4644 output_asm_insn (info.shift1, operands);
4645 return "";
4646
4647 case SHIFT_ROT_AND:
4648 {
4649 int m = GET_MODE_BITSIZE (mode) - n;
4650 const int mask = (shift_type == SHIFT_ASHIFT
4651 ? ((1 << m) - 1) << n
4652 : (1 << m) - 1);
4653 char insn_buf[200];
4654
4655 /* Not all possibilities of rotate are supported. They shouldn't
4656 be generated, but let's watch for 'em. */
4657 gcc_assert (info.shift1);
4658
4659 /* Emit two bit rotates first. */
4660 if (info.shift2 != NULL)
b839e0b4 4661 {
3afe906b 4662 for (; m > 1; m -= 2)
4663 output_asm_insn (info.shift2, operands);
4664 }
4665
4666 /* Now single bit rotates for any residual. */
4667 for (; m > 0; m--)
4668 output_asm_insn (info.shift1, operands);
4669
4670 /* Now mask off the high bits. */
4671 switch (mode)
4672 {
916ace94 4673 case E_QImode:
3afe906b 4674 sprintf (insn_buf, "and\t#%d,%%X0", mask);
4675 break;
52abe980 4676
916ace94 4677 case E_HImode:
3afe906b 4678 gcc_assert (TARGET_H8300H || TARGET_H8300S);
4679 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
4680 break;
52abe980 4681
3afe906b 4682 default:
4683 gcc_unreachable ();
b839e0b4 4684 }
cb95c693 4685
3afe906b 4686 output_asm_insn (insn_buf, operands);
4687 return "";
4688 }
cb95c693 4689
3afe906b 4690 case SHIFT_LOOP:
4691 /* A loop to shift by a "large" constant value.
4692 If we have shift-by-2 insns, use them. */
4693 if (info.shift2 != NULL)
4694 {
4695 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
4696 names_big[REGNO (operands[4])]);
4697 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4698 output_asm_insn (info.shift2, operands);
4699 output_asm_insn ("add #0xff,%X4", operands);
4700 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4701 if (n % 2)
4702 output_asm_insn (info.shift1, operands);
4703 }
4704 else
4705 {
4706 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
4707 names_big[REGNO (operands[4])]);
4708 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4709 output_asm_insn (info.shift1, operands);
4710 output_asm_insn ("add #0xff,%X4", operands);
4711 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
52abe980 4712 }
3afe906b 4713 return "";
4714
4715 default:
4716 gcc_unreachable ();
e1629549 4717 }
e1629549 4718}
484c1e8d 4719
8deb3959 4720/* Count the number of assembly instructions in a string TEMPL. */
cdfb02e8 4721
484c1e8d 4722static unsigned int
8deb3959 4723h8300_asm_insn_count (const char *templ)
484c1e8d 4724{
4725 unsigned int count = 1;
4726
8deb3959 4727 for (; *templ; templ++)
4728 if (*templ == '\n')
484c1e8d 4729 count++;
4730
4731 return count;
4732}
4733
cdfb02e8 4734/* Compute the length of a shift insn. */
4735
484c1e8d 4736unsigned int
230002f2 4737compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
484c1e8d 4738{
4739 rtx shift = operands[3];
3754d046 4740 machine_mode mode = GET_MODE (shift);
484c1e8d 4741 enum rtx_code code = GET_CODE (shift);
4742 enum shift_type shift_type;
4743 enum shift_mode shift_mode;
4744 struct shift_info info;
4745 unsigned int wlength = 0;
4746
4747 switch (mode)
4748 {
916ace94 4749 case E_QImode:
484c1e8d 4750 shift_mode = QIshift;
4751 break;
916ace94 4752 case E_HImode:
484c1e8d 4753 shift_mode = HIshift;
4754 break;
916ace94 4755 case E_SImode:
484c1e8d 4756 shift_mode = SIshift;
4757 break;
4758 default:
3afe906b 4759 gcc_unreachable ();
484c1e8d 4760 }
4761
4762 switch (code)
4763 {
4764 case ASHIFTRT:
4765 shift_type = SHIFT_ASHIFTRT;
4766 break;
4767 case LSHIFTRT:
4768 shift_type = SHIFT_LSHIFTRT;
4769 break;
4770 case ASHIFT:
4771 shift_type = SHIFT_ASHIFT;
4772 break;
4773 default:
3afe906b 4774 gcc_unreachable ();
484c1e8d 4775 }
4776
4777 if (GET_CODE (operands[2]) != CONST_INT)
4778 {
4779 /* Get the assembler code to do one shift. */
4780 get_shift_alg (shift_type, shift_mode, 1, &info);
4781
4782 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
4783 }
4784 else
4785 {
4786 int n = INTVAL (operands[2]);
4787
4788 /* If the count is negative, make it 0. */
4789 if (n < 0)
4790 n = 0;
4791 /* If the count is too big, truncate it.
4792 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4793 do the intuitive thing. */
4794 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4795 n = GET_MODE_BITSIZE (mode);
4796
4797 get_shift_alg (shift_type, shift_mode, n, &info);
4798
4799 switch (info.alg)
4800 {
4801 case SHIFT_SPECIAL:
4802 wlength += h8300_asm_insn_count (info.special);
f56f0ed0 4803
4804 /* Every assembly instruction used in SHIFT_SPECIAL case
4805 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4806 see xor.l, we just pretend that xor.l counts as two insns
4807 so that the insn length will be computed correctly. */
4808 if (strstr (info.special, "xor.l") != NULL)
4809 wlength++;
4810
484c1e8d 4811 /* Fall through. */
4812
4813 case SHIFT_INLINE:
4814 n = info.remainder;
4815
4816 if (info.shift2 != NULL)
4817 {
4818 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
4819 n = n % 2;
4820 }
4821
4822 wlength += h8300_asm_insn_count (info.shift1) * n;
66b41076 4823
484c1e8d 4824 return 2 * wlength;
4825
4826 case SHIFT_ROT_AND:
4827 {
4828 int m = GET_MODE_BITSIZE (mode) - n;
4829
4830 /* Not all possibilities of rotate are supported. They shouldn't
4831 be generated, but let's watch for 'em. */
3afe906b 4832 gcc_assert (info.shift1);
484c1e8d 4833
4834 if (info.shift2 != NULL)
4835 {
4836 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
4837 m = m % 2;
4838 }
4839
4840 wlength += h8300_asm_insn_count (info.shift1) * m;
66b41076 4841
484c1e8d 4842 /* Now mask off the high bits. */
4843 switch (mode)
4844 {
916ace94 4845 case E_QImode:
484c1e8d 4846 wlength += 1;
4847 break;
916ace94 4848 case E_HImode:
484c1e8d 4849 wlength += 2;
4850 break;
916ace94 4851 case E_SImode:
3afe906b 4852 gcc_assert (!TARGET_H8300);
484c1e8d 4853 wlength += 3;
4854 break;
4855 default:
3afe906b 4856 gcc_unreachable ();
484c1e8d 4857 }
4858 return 2 * wlength;
4859 }
4860
4861 case SHIFT_LOOP:
4862 /* A loop to shift by a "large" constant value.
4863 If we have shift-by-2 insns, use them. */
4864 if (info.shift2 != NULL)
4865 {
4866 wlength += 3 + h8300_asm_insn_count (info.shift2);
4867 if (n % 2)
4868 wlength += h8300_asm_insn_count (info.shift1);
4869 }
4870 else
4871 {
4872 wlength += 3 + h8300_asm_insn_count (info.shift1);
4873 }
4874 return 2 * wlength;
4875
4876 default:
3afe906b 4877 gcc_unreachable ();
484c1e8d 4878 }
4879 }
4880}
fd7729c5 4881
cdfb02e8 4882/* Compute which flag bits are valid after a shift insn. */
4883
539b539f 4884enum attr_cc
230002f2 4885compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
fd7729c5 4886{
4887 rtx shift = operands[3];
3754d046 4888 machine_mode mode = GET_MODE (shift);
fd7729c5 4889 enum rtx_code code = GET_CODE (shift);
4890 enum shift_type shift_type;
4891 enum shift_mode shift_mode;
4892 struct shift_info info;
3afe906b 4893 int n;
4894
fd7729c5 4895 switch (mode)
4896 {
916ace94 4897 case E_QImode:
fd7729c5 4898 shift_mode = QIshift;
4899 break;
916ace94 4900 case E_HImode:
fd7729c5 4901 shift_mode = HIshift;
4902 break;
916ace94 4903 case E_SImode:
fd7729c5 4904 shift_mode = SIshift;
4905 break;
4906 default:
3afe906b 4907 gcc_unreachable ();
fd7729c5 4908 }
4909
4910 switch (code)
4911 {
4912 case ASHIFTRT:
4913 shift_type = SHIFT_ASHIFTRT;
4914 break;
4915 case LSHIFTRT:
4916 shift_type = SHIFT_LSHIFTRT;
4917 break;
4918 case ASHIFT:
4919 shift_type = SHIFT_ASHIFT;
4920 break;
4921 default:
3afe906b 4922 gcc_unreachable ();
fd7729c5 4923 }
4924
3afe906b 4925 /* This case must be taken care of by one of the two splitters
4926 that convert a variable shift into a loop. */
4927 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4928
4929 n = INTVAL (operands[2]);
4930
4931 /* If the count is negative, make it 0. */
4932 if (n < 0)
4933 n = 0;
4934 /* If the count is too big, truncate it.
4935 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4936 do the intuitive thing. */
4937 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4938 n = GET_MODE_BITSIZE (mode);
4939
4940 get_shift_alg (shift_type, shift_mode, n, &info);
4941
4942 switch (info.alg)
fd7729c5 4943 {
3afe906b 4944 case SHIFT_SPECIAL:
4945 if (info.remainder == 0)
4946 return info.cc_special;
fd7729c5 4947
3afe906b 4948 /* Fall through. */
fd7729c5 4949
3afe906b 4950 case SHIFT_INLINE:
4951 return info.cc_inline;
4952
4953 case SHIFT_ROT_AND:
4954 /* This case always ends with an and instruction. */
4955 return CC_SET_ZNV;
4956
4957 case SHIFT_LOOP:
4958 /* A loop to shift by a "large" constant value.
4959 If we have shift-by-2 insns, use them. */
4960 if (info.shift2 != NULL)
fd7729c5 4961 {
3afe906b 4962 if (n % 2)
4963 return info.cc_inline;
fd7729c5 4964 }
3afe906b 4965 return CC_CLOBBER;
4966
4967 default:
4968 gcc_unreachable ();
fd7729c5 4969 }
4970}
b839e0b4 4971\f
b4fa7cf2 4972/* A rotation by a non-constant will cause a loop to be generated, in
4973 which a rotation by one bit is used. A rotation by a constant,
4974 including the one in the loop, will be taken care of by
af63c5ce 4975 output_a_rotate () at the insn emit time. */
b4fa7cf2 4976
4977int
a620f9df 4978expand_a_rotate (rtx operands[])
b4fa7cf2 4979{
4980 rtx dst = operands[0];
4981 rtx src = operands[1];
4982 rtx rotate_amount = operands[2];
3754d046 4983 machine_mode mode = GET_MODE (dst);
b4fa7cf2 4984
727c62dd 4985 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
4986 return false;
4987
b4fa7cf2 4988 /* We rotate in place. */
4989 emit_move_insn (dst, src);
4990
4991 if (GET_CODE (rotate_amount) != CONST_INT)
4992 {
4993 rtx counter = gen_reg_rtx (QImode);
79f6a8ed 4994 rtx_code_label *start_label = gen_label_rtx ();
4995 rtx_code_label *end_label = gen_label_rtx ();
b4fa7cf2 4996
4997 /* If the rotate amount is less than or equal to 0,
4998 we go out of the loop. */
bcd9bd66 4999 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
7e69f45b 5000 QImode, 0, end_label);
b4fa7cf2 5001
5002 /* Initialize the loop counter. */
5003 emit_move_insn (counter, rotate_amount);
5004
5005 emit_label (start_label);
5006
5007 /* Rotate by one bit. */
18618acc 5008 switch (mode)
5009 {
916ace94 5010 case E_QImode:
18618acc 5011 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
5012 break;
916ace94 5013 case E_HImode:
18618acc 5014 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
5015 break;
916ace94 5016 case E_SImode:
18618acc 5017 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
5018 break;
5019 default:
3afe906b 5020 gcc_unreachable ();
18618acc 5021 }
b4fa7cf2 5022
5023 /* Decrement the counter by 1. */
18618acc 5024 emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
b4fa7cf2 5025
c46dc351 5026 /* If the loop counter is nonzero, we go back to the beginning
b4fa7cf2 5027 of the loop. */
bcd9bd66 5028 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
7e69f45b 5029 start_label);
b4fa7cf2 5030
5031 emit_label (end_label);
5032 }
5033 else
5034 {
5035 /* Rotate by AMOUNT bits. */
18618acc 5036 switch (mode)
5037 {
916ace94 5038 case E_QImode:
18618acc 5039 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
5040 break;
916ace94 5041 case E_HImode:
18618acc 5042 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
5043 break;
916ace94 5044 case E_SImode:
18618acc 5045 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
5046 break;
5047 default:
3afe906b 5048 gcc_unreachable ();
18618acc 5049 }
b4fa7cf2 5050 }
5051
5052 return 1;
5053}
5054
cdfb02e8 5055/* Output a rotate insn. */
b4fa7cf2 5056
5057const char *
af63c5ce 5058output_a_rotate (enum rtx_code code, rtx *operands)
b4fa7cf2 5059{
5060 rtx dst = operands[0];
5061 rtx rotate_amount = operands[2];
5062 enum shift_mode rotate_mode;
5063 enum shift_type rotate_type;
5064 const char *insn_buf;
5065 int bits;
5066 int amount;
3754d046 5067 machine_mode mode = GET_MODE (dst);
b4fa7cf2 5068
3afe906b 5069 gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
b4fa7cf2 5070
5071 switch (mode)
5072 {
916ace94 5073 case E_QImode:
b4fa7cf2 5074 rotate_mode = QIshift;
5075 break;
916ace94 5076 case E_HImode:
b4fa7cf2 5077 rotate_mode = HIshift;
5078 break;
916ace94 5079 case E_SImode:
b4fa7cf2 5080 rotate_mode = SIshift;
5081 break;
5082 default:
3afe906b 5083 gcc_unreachable ();
b4fa7cf2 5084 }
5085
5086 switch (code)
5087 {
5088 case ROTATERT:
5089 rotate_type = SHIFT_ASHIFT;
5090 break;
5091 case ROTATE:
5092 rotate_type = SHIFT_LSHIFTRT;
5093 break;
5094 default:
3afe906b 5095 gcc_unreachable ();
b4fa7cf2 5096 }
5097
5098 amount = INTVAL (rotate_amount);
5099
5100 /* Clean up AMOUNT. */
5101 if (amount < 0)
5102 amount = 0;
5103 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5104 amount = GET_MODE_BITSIZE (mode);
5105
5106 /* Determine the faster direction. After this phase, amount will be
5107 at most a half of GET_MODE_BITSIZE (mode). */
de8409f8 5108 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
b4fa7cf2 5109 {
5110 /* Flip the direction. */
5111 amount = GET_MODE_BITSIZE (mode) - amount;
5112 rotate_type =
5113 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5114 }
5115
5116 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5117 boost up the rotation. */
5118 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5119 || (mode == HImode && TARGET_H8300H && amount >= 6)
5120 || (mode == HImode && TARGET_H8300S && amount == 8)
5121 || (mode == SImode && TARGET_H8300H && amount >= 10)
5122 || (mode == SImode && TARGET_H8300S && amount >= 13))
5123 {
5124 switch (mode)
5125 {
916ace94 5126 case E_HImode:
b4fa7cf2 5127 /* This code works on any family. */
5128 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5129 output_asm_insn (insn_buf, operands);
5130 break;
5131
916ace94 5132 case E_SImode:
11f95d7c 5133 /* This code works on the H8/300H and H8S. */
b4fa7cf2 5134 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5135 output_asm_insn (insn_buf, operands);
5136 break;
5137
5138 default:
3afe906b 5139 gcc_unreachable ();
b4fa7cf2 5140 }
5141
5142 /* Adjust AMOUNT and flip the direction. */
5143 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5144 rotate_type =
5145 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5146 }
5147
18618acc 5148 /* Output rotate insns. */
b4fa7cf2 5149 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
5150 {
5151 if (bits == 2)
5152 insn_buf = rotate_two[rotate_type][rotate_mode];
5153 else
5154 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
a86fab2e 5155
b4fa7cf2 5156 for (; amount >= bits; amount -= bits)
5157 output_asm_insn (insn_buf, operands);
5158 }
5159
5160 return "";
5161}
af63c5ce 5162
cdfb02e8 5163/* Compute the length of a rotate insn. */
5164
af63c5ce 5165unsigned int
5166compute_a_rotate_length (rtx *operands)
5167{
5168 rtx src = operands[1];
3ab64e09 5169 rtx amount_rtx = operands[2];
3754d046 5170 machine_mode mode = GET_MODE (src);
af63c5ce 5171 int amount;
5172 unsigned int length = 0;
5173
3afe906b 5174 gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
af63c5ce 5175
3ab64e09 5176 amount = INTVAL (amount_rtx);
af63c5ce 5177
5178 /* Clean up AMOUNT. */
5179 if (amount < 0)
5180 amount = 0;
5181 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5182 amount = GET_MODE_BITSIZE (mode);
5183
5184 /* Determine the faster direction. After this phase, amount
5185 will be at most a half of GET_MODE_BITSIZE (mode). */
5186 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5187 /* Flip the direction. */
5188 amount = GET_MODE_BITSIZE (mode) - amount;
5189
5190 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5191 boost up the rotation. */
5192 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5193 || (mode == HImode && TARGET_H8300H && amount >= 6)
5194 || (mode == HImode && TARGET_H8300S && amount == 8)
5195 || (mode == SImode && TARGET_H8300H && amount >= 10)
5196 || (mode == SImode && TARGET_H8300S && amount >= 13))
5197 {
5198 /* Adjust AMOUNT and flip the direction. */
5199 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5200 length += 6;
5201 }
5202
5203 /* We use 2-bit rotations on the H8S. */
5204 if (TARGET_H8300S)
5205 amount = amount / 2 + amount % 2;
5206
5207 /* The H8/300 uses three insns to rotate one bit, taking 6
5208 length. */
5209 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
5210
5211 return length;
5212}
b4fa7cf2 5213\f
b839e0b4 5214/* Fix the operands of a gen_xxx so that it could become a bit
a86fab2e 5215 operating insn. */
e1629549 5216
5217int
eb53e102 5218fix_bit_operand (rtx *operands, enum rtx_code code)
e1629549 5219{
b090827b 5220 /* The bit_operand predicate accepts any memory during RTL generation, but
b839e0b4 5221 only 'U' memory afterwards, so if this is a MEM operand, we must force
5222 it to be valid for 'U' by reloading the address. */
e1629549 5223
eb53e102 5224 if (code == AND
5225 ? single_zero_operand (operands[2], QImode)
5226 : single_one_operand (operands[2], QImode))
e1629549 5227 {
c7619744 5228 /* OK to have a memory dest. */
5229 if (GET_CODE (operands[0]) == MEM
424f5954 5230 && !satisfies_constraint_U (operands[0]))
b839e0b4 5231 {
c7619744 5232 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
5233 copy_to_mode_reg (Pmode,
5234 XEXP (operands[0], 0)));
5235 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5236 operands[0] = mem;
5237 }
b839e0b4 5238
c7619744 5239 if (GET_CODE (operands[1]) == MEM
424f5954 5240 && !satisfies_constraint_U (operands[1]))
c7619744 5241 {
5242 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
5243 copy_to_mode_reg (Pmode,
5244 XEXP (operands[1], 0)));
5245 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5246 operands[1] = mem;
b839e0b4 5247 }
c7619744 5248 return 0;
b839e0b4 5249 }
e1629549 5250
b839e0b4 5251 /* Dest and src op must be register. */
e1629549 5252
b839e0b4 5253 operands[1] = force_reg (QImode, operands[1]);
5254 {
5255 rtx res = gen_reg_rtx (QImode);
bd80419e 5256 switch (code)
4b042441 5257 {
5258 case AND:
5259 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
5260 break;
5261 case IOR:
5262 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
5263 break;
5264 case XOR:
5265 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
5266 break;
5267 default:
3afe906b 5268 gcc_unreachable ();
4b042441 5269 }
5270 emit_insn (gen_movqi (operands[0], res));
b839e0b4 5271 }
5272 return 1;
e1629549 5273}
b11bfc61 5274
b11bfc61 5275/* Return nonzero if FUNC is an interrupt function as specified
5276 by the "interrupt" attribute. */
5277
5278static int
230002f2 5279h8300_interrupt_function_p (tree func)
b11bfc61 5280{
5281 tree a;
5282
5283 if (TREE_CODE (func) != FUNCTION_DECL)
5284 return 0;
5285
e3c541f0 5286 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
b11bfc61 5287 return a != NULL_TREE;
5288}
5289
5344805f 5290/* Return nonzero if FUNC is a saveall function as specified by the
5291 "saveall" attribute. */
5292
5293static int
5294h8300_saveall_function_p (tree func)
5295{
5296 tree a;
5297
5298 if (TREE_CODE (func) != FUNCTION_DECL)
5299 return 0;
5300
5301 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
5302 return a != NULL_TREE;
5303}
5304
09c48b9c 5305/* Return nonzero if FUNC is an OS_Task function as specified
5306 by the "OS_Task" attribute. */
5307
5308static int
230002f2 5309h8300_os_task_function_p (tree func)
09c48b9c 5310{
5311 tree a;
5312
5313 if (TREE_CODE (func) != FUNCTION_DECL)
5314 return 0;
5315
e3c541f0 5316 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
09c48b9c 5317 return a != NULL_TREE;
5318}
5319
5320/* Return nonzero if FUNC is a monitor function as specified
5321 by the "monitor" attribute. */
5322
5323static int
230002f2 5324h8300_monitor_function_p (tree func)
09c48b9c 5325{
5326 tree a;
5327
5328 if (TREE_CODE (func) != FUNCTION_DECL)
5329 return 0;
5330
e3c541f0 5331 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
09c48b9c 5332 return a != NULL_TREE;
5333}
5334
b11bfc61 5335/* Return nonzero if FUNC is a function that should be called
5336 through the function vector. */
5337
5338int
230002f2 5339h8300_funcvec_function_p (tree func)
b11bfc61 5340{
5341 tree a;
5342
5343 if (TREE_CODE (func) != FUNCTION_DECL)
5344 return 0;
5345
e3c541f0 5346 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
b11bfc61 5347 return a != NULL_TREE;
5348}
5349
27a0be8f 5350/* Return nonzero if DECL is a variable that's in the eight bit
2c7be643 5351 data area. */
5352
5353int
230002f2 5354h8300_eightbit_data_p (tree decl)
2c7be643 5355{
5356 tree a;
5357
5358 if (TREE_CODE (decl) != VAR_DECL)
5359 return 0;
5360
e3c541f0 5361 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
2c7be643 5362 return a != NULL_TREE;
5363}
5364
27a0be8f 5365/* Return nonzero if DECL is a variable that's in the tiny
5366 data area. */
5367
5368int
230002f2 5369h8300_tiny_data_p (tree decl)
27a0be8f 5370{
5371 tree a;
5372
5373 if (TREE_CODE (decl) != VAR_DECL)
5374 return 0;
5375
e3c541f0 5376 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
27a0be8f 5377 return a != NULL_TREE;
5378}
5379
5344805f 5380/* Generate an 'interrupt_handler' attribute for decls. We convert
5381 all the pragmas to corresponding attributes. */
ad7d09f6 5382
5383static void
230002f2 5384h8300_insert_attributes (tree node, tree *attributes)
ad7d09f6 5385{
5344805f 5386 if (TREE_CODE (node) == FUNCTION_DECL)
5387 {
5388 if (pragma_interrupt)
5389 {
5390 pragma_interrupt = 0;
ad7d09f6 5391
5344805f 5392 /* Add an 'interrupt_handler' attribute. */
5393 *attributes = tree_cons (get_identifier ("interrupt_handler"),
5394 NULL, *attributes);
5395 }
41ed3bcd 5396
5344805f 5397 if (pragma_saveall)
5398 {
5399 pragma_saveall = 0;
5400
5401 /* Add an 'saveall' attribute. */
5402 *attributes = tree_cons (get_identifier ("saveall"),
5403 NULL, *attributes);
5404 }
5405 }
ad7d09f6 5406}
5407
e3c541f0 5408/* Supported attributes:
b11bfc61 5409
bd297402 5410 interrupt_handler: output a prologue and epilogue suitable for an
b11bfc61 5411 interrupt handler.
5412
5344805f 5413 saveall: output a prologue and epilogue that saves and restores
5414 all registers except the stack pointer.
5415
bd297402 5416 function_vector: This function should be called through the
27a0be8f 5417 function vector.
5418
5419 eightbit_data: This variable lives in the 8-bit data area and can
5420 be referenced with 8-bit absolute memory addresses.
5421
5422 tiny_data: This variable lives in the tiny data area and can be
5423 referenced with 16-bit absolute memory references. */
b11bfc61 5424
cd819d2f 5425static const struct attribute_spec h8300_attribute_table[] =
b11bfc61 5426{
ac86af5d 5427 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
5428 affects_type_identity } */
5429 { "interrupt_handler", 0, 0, true, false, false,
5430 h8300_handle_fndecl_attribute, false },
5431 { "saveall", 0, 0, true, false, false,
5432 h8300_handle_fndecl_attribute, false },
5433 { "OS_Task", 0, 0, true, false, false,
5434 h8300_handle_fndecl_attribute, false },
5435 { "monitor", 0, 0, true, false, false,
5436 h8300_handle_fndecl_attribute, false },
5437 { "function_vector", 0, 0, true, false, false,
5438 h8300_handle_fndecl_attribute, false },
5439 { "eightbit_data", 0, 0, true, false, false,
5440 h8300_handle_eightbit_data_attribute, false },
5441 { "tiny_data", 0, 0, true, false, false,
5442 h8300_handle_tiny_data_attribute, false },
5443 { NULL, 0, 0, false, false, false, NULL, false }
e3c541f0 5444};
b11bfc61 5445
2c7be643 5446
e3c541f0 5447/* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5448 struct attribute_spec.handler. */
5449static tree
230002f2 5450h8300_handle_fndecl_attribute (tree *node, tree name,
5451 tree args ATTRIBUTE_UNUSED,
5452 int flags ATTRIBUTE_UNUSED,
5453 bool *no_add_attrs)
e3c541f0 5454{
5455 if (TREE_CODE (*node) != FUNCTION_DECL)
5456 {
67a779df 5457 warning (OPT_Wattributes, "%qE attribute only applies to functions",
5458 name);
e3c541f0 5459 *no_add_attrs = true;
5460 }
5461
5462 return NULL_TREE;
5463}
5464
5465/* Handle an "eightbit_data" attribute; arguments as in
5466 struct attribute_spec.handler. */
5467static tree
230002f2 5468h8300_handle_eightbit_data_attribute (tree *node, tree name,
5469 tree args ATTRIBUTE_UNUSED,
5470 int flags ATTRIBUTE_UNUSED,
5471 bool *no_add_attrs)
e3c541f0 5472{
5473 tree decl = *node;
5474
5475 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
2c7be643 5476 {
738a6bda 5477 set_decl_section_name (decl, ".eight");
e3c541f0 5478 }
5479 else
5480 {
67a779df 5481 warning (OPT_Wattributes, "%qE attribute ignored",
5482 name);
e3c541f0 5483 *no_add_attrs = true;
27a0be8f 5484 }
5485
e3c541f0 5486 return NULL_TREE;
5487}
5488
5489/* Handle an "tiny_data" attribute; arguments as in
5490 struct attribute_spec.handler. */
5491static tree
230002f2 5492h8300_handle_tiny_data_attribute (tree *node, tree name,
5493 tree args ATTRIBUTE_UNUSED,
5494 int flags ATTRIBUTE_UNUSED,
5495 bool *no_add_attrs)
e3c541f0 5496{
5497 tree decl = *node;
5498
5499 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
27a0be8f 5500 {
738a6bda 5501 set_decl_section_name (decl, ".tiny");
e3c541f0 5502 }
5503 else
5504 {
67a779df 5505 warning (OPT_Wattributes, "%qE attribute ignored",
5506 name);
e3c541f0 5507 *no_add_attrs = true;
2c7be643 5508 }
eb2aa24e 5509
e3c541f0 5510 return NULL_TREE;
b11bfc61 5511}
5512
d37aaac2 5513/* Mark function vectors, and various small data objects. */
7811991d 5514
5515static void
230002f2 5516h8300_encode_section_info (tree decl, rtx rtl, int first)
7811991d 5517{
d37aaac2 5518 int extra_flags = 0;
5519
2c129d70 5520 default_encode_section_info (decl, rtl, first);
d37aaac2 5521
7811991d 5522 if (TREE_CODE (decl) == FUNCTION_DECL
5523 && h8300_funcvec_function_p (decl))
d37aaac2 5524 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
7811991d 5525 else if (TREE_CODE (decl) == VAR_DECL
5526 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
5527 {
5528 if (h8300_eightbit_data_p (decl))
d37aaac2 5529 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
7811991d 5530 else if (first && h8300_tiny_data_p (decl))
d37aaac2 5531 extra_flags = SYMBOL_FLAG_TINY_DATA;
7811991d 5532 }
7b4a38a6 5533
d37aaac2 5534 if (extra_flags)
2c129d70 5535 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
7b4a38a6 5536}
5537
cdfb02e8 5538/* Output a single-bit extraction. */
5539
9305fe33 5540const char *
230002f2 5541output_simode_bld (int bild, rtx operands[])
92eae32b 5542{
7ef78393 5543 if (TARGET_H8300)
5544 {
5545 /* Clear the destination register. */
5546 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
5547
5548 /* Now output the bit load or bit inverse load, and store it in
5549 the destination. */
5550 if (bild)
5551 output_asm_insn ("bild\t%Z2,%Y1", operands);
5552 else
5553 output_asm_insn ("bld\t%Z2,%Y1", operands);
92eae32b 5554
7ef78393 5555 output_asm_insn ("bst\t#0,%w0", operands);
5556 }
92eae32b 5557 else
7ef78393 5558 {
7d3e46b8 5559 /* Determine if we can clear the destination first. */
5560 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
5561 && REGNO (operands[0]) != REGNO (operands[1]));
5562
5563 if (clear_first)
5564 output_asm_insn ("sub.l\t%S0,%S0", operands);
5565
7ef78393 5566 /* Output the bit load or bit inverse load. */
5567 if (bild)
5568 output_asm_insn ("bild\t%Z2,%Y1", operands);
5569 else
5570 output_asm_insn ("bld\t%Z2,%Y1", operands);
5571
7d3e46b8 5572 if (!clear_first)
5573 output_asm_insn ("xor.l\t%S0,%S0", operands);
5574
5575 /* Perform the bit store. */
04b5bef5 5576 output_asm_insn ("rotxl.l\t%S0", operands);
7ef78393 5577 }
92eae32b 5578
5579 /* All done. */
5580 return "";
5581}
fe19f1e0 5582
727c62dd 5583/* Delayed-branch scheduling is more effective if we have some idea
5584 how long each instruction will be. Use a shorten_branches pass
5585 to get an initial estimate. */
5586
5587static void
5588h8300_reorg (void)
5589{
5590 if (flag_delayed_branch)
5591 shorten_branches (get_insns ());
5592}
5593
6e4758ce 5594#ifndef OBJECT_FORMAT_ELF
2cb4ac60 5595static void
537cd941 5596h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED,
5597 tree decl)
2cb4ac60 5598{
5599 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5600 fprintf (asm_out_file, "\t.section %s\n", name);
5601}
6e4758ce 5602#endif /* ! OBJECT_FORMAT_ELF */
6c48c1e4 5603
e566129f 5604/* Nonzero if X is a constant address suitable as an 8-bit absolute,
5605 which is a special case of the 'R' operand. */
5606
6c48c1e4 5607int
230002f2 5608h8300_eightbit_constant_address_p (rtx x)
6c48c1e4 5609{
1d60d981 5610 /* The ranges of the 8-bit area. */
424064e7 5611 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
5612 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
6c48c1e4 5613 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
5614 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
5615 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
5616 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
5617
5618 unsigned HOST_WIDE_INT addr;
5619
e55c1a72 5620 /* We accept symbols declared with eightbit_data. */
d37aaac2 5621 if (GET_CODE (x) == SYMBOL_REF)
5622 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
e55c1a72 5623
817c5748 5624 if (GET_CODE (x) == CONST
5625 && GET_CODE (XEXP (x, 0)) == PLUS
5626 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
5627 && (SYMBOL_REF_FLAGS (XEXP (XEXP (x, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0)
5628 return 1;
5629
6c48c1e4 5630 if (GET_CODE (x) != CONST_INT)
5631 return 0;
5632
5633 addr = INTVAL (x);
5634
5635 return (0
35a462ce 5636 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
6c48c1e4 5637 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
5638 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
5639}
5640
e566129f 5641/* Nonzero if X is a constant address suitable as an 16-bit absolute
5642 on H8/300H and H8S. */
5643
6c48c1e4 5644int
230002f2 5645h8300_tiny_constant_address_p (rtx x)
6c48c1e4 5646{
462c2024 5647 /* The ranges of the 16-bit area. */
6c48c1e4 5648 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
5649 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
5650 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
5651 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
5652 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
5653 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
5654 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
5655 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
5656
5657 unsigned HOST_WIDE_INT addr;
5658
52d2fba2 5659 switch (GET_CODE (x))
5660 {
5661 case SYMBOL_REF:
abe5efd4 5662 /* In the normal mode, any symbol fits in the 16-bit absolute
5663 address range. We also accept symbols declared with
5664 tiny_data. */
5665 return (TARGET_NORMAL_MODE
5666 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
3696208f 5667
52d2fba2 5668 case CONST_INT:
5669 addr = INTVAL (x);
5670 return (TARGET_NORMAL_MODE
5671 || (TARGET_H8300H
5672 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
5673 || (TARGET_H8300S
5674 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
6c48c1e4 5675
abe5efd4 5676 case CONST:
5677 return TARGET_NORMAL_MODE;
5678
52d2fba2 5679 default:
5680 return 0;
5681 }
6c48c1e4 5682
6c48c1e4 5683}
e33ecec3 5684
cdfb02e8 5685/* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5686 locations that can be accessed as a 16-bit word. */
5687
e33ecec3 5688int
230002f2 5689byte_accesses_mergeable_p (rtx addr1, rtx addr2)
e33ecec3 5690{
5691 HOST_WIDE_INT offset1, offset2;
5692 rtx reg1, reg2;
5693
5694 if (REG_P (addr1))
5695 {
5696 reg1 = addr1;
5697 offset1 = 0;
5698 }
5699 else if (GET_CODE (addr1) == PLUS
5700 && REG_P (XEXP (addr1, 0))
5701 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
5702 {
5703 reg1 = XEXP (addr1, 0);
5704 offset1 = INTVAL (XEXP (addr1, 1));
5705 }
5706 else
5707 return 0;
5708
5709 if (REG_P (addr2))
5710 {
5711 reg2 = addr2;
5712 offset2 = 0;
5713 }
5714 else if (GET_CODE (addr2) == PLUS
5715 && REG_P (XEXP (addr2, 0))
5716 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
5717 {
5718 reg2 = XEXP (addr2, 0);
5719 offset2 = INTVAL (XEXP (addr2, 1));
5720 }
5721 else
5722 return 0;
5723
5724 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
5725 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
5726 && offset1 % 2 == 0
5727 && offset1 + 1 == offset2)
5728 return 1;
5729
5730 return 0;
5731}
8c71b4e9 5732
5733/* Return nonzero if we have the same comparison insn as I3 two insns
be002911 5734 before I3. I3 is assumed to be a comparison insn. */
8c71b4e9 5735
5736int
56d95ea5 5737same_cmp_preceding_p (rtx_insn *i3)
8c71b4e9 5738{
93ee8dfb 5739 rtx_insn *i1, *i2;
8c71b4e9 5740
5741 /* Make sure we have a sequence of three insns. */
5742 i2 = prev_nonnote_insn (i3);
93ee8dfb 5743 if (i2 == NULL)
8c71b4e9 5744 return 0;
5745 i1 = prev_nonnote_insn (i2);
93ee8dfb 5746 if (i1 == NULL)
8c71b4e9 5747 return 0;
5748
5749 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5750 && any_condjump_p (i2) && onlyjump_p (i2));
5751}
01272fdf 5752
5b9da921 5753/* Return nonzero if we have the same comparison insn as I1 two insns
5754 after I1. I1 is assumed to be a comparison insn. */
5755
5756int
56d95ea5 5757same_cmp_following_p (rtx_insn *i1)
5b9da921 5758{
93ee8dfb 5759 rtx_insn *i2, *i3;
5b9da921 5760
5761 /* Make sure we have a sequence of three insns. */
5762 i2 = next_nonnote_insn (i1);
93ee8dfb 5763 if (i2 == NULL)
5b9da921 5764 return 0;
5765 i3 = next_nonnote_insn (i2);
93ee8dfb 5766 if (i3 == NULL)
5b9da921 5767 return 0;
5768
5769 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5770 && any_condjump_p (i2) && onlyjump_p (i2));
5771}
5772
f41916c8 5773/* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
7bd28bba 5774 (or pops) N registers. OPERANDS are assumed to be an array of
f41916c8 5775 registers. */
5776
5777int
5778h8300_regs_ok_for_stm (int n, rtx operands[])
5779{
5780 switch (n)
5781 {
5782 case 2:
5783 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
5784 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
5785 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
5786 case 3:
5787 return ((REGNO (operands[0]) == 0
5788 && REGNO (operands[1]) == 1
5789 && REGNO (operands[2]) == 2)
5790 || (REGNO (operands[0]) == 4
5791 && REGNO (operands[1]) == 5
5792 && REGNO (operands[2]) == 6));
5793
5794 case 4:
5795 return (REGNO (operands[0]) == 0
5796 && REGNO (operands[1]) == 1
5797 && REGNO (operands[2]) == 2
5798 && REGNO (operands[3]) == 3);
3afe906b 5799 default:
5800 gcc_unreachable ();
f41916c8 5801 }
f41916c8 5802}
5803
01272fdf 5804/* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5805
5806int
5807h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5808 unsigned int new_reg)
5809{
5810 /* Interrupt functions can only use registers that have already been
5811 saved by the prologue, even if they would normally be
5812 call-clobbered. */
5813
5814 if (h8300_current_function_interrupt_function_p ()
3072d30e 5815 && !df_regs_ever_live_p (new_reg))
01272fdf 5816 return 0;
5817
6fe6e17a 5818 return 1;
01272fdf 5819}
9a5775fe 5820
cf695b54 5821/* Returns true if register REGNO is safe to be allocated as a scratch
5822 register in the current function. */
5823
5824static bool
5825h8300_hard_regno_scratch_ok (unsigned int regno)
5826{
5827 if (h8300_current_function_interrupt_function_p ()
5828 && ! WORD_REG_USED (regno))
5829 return false;
5830
5831 return true;
5832}
5833
5834
9a5775fe 5835/* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5836
5837static int
5838h8300_rtx_ok_for_base_p (rtx x, int strict)
5839{
5840 /* Strip off SUBREG if any. */
5841 if (GET_CODE (x) == SUBREG)
5842 x = SUBREG_REG (x);
5843
5844 return (REG_P (x)
5845 && (strict
5846 ? REG_OK_FOR_BASE_STRICT_P (x)
5847 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
5848}
5849
5850/* Return nozero if X is a legitimate address. On the H8/300, a
5851 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5852 CONSTANT_ADDRESS. */
5853
fd50b071 5854static bool
3754d046 5855h8300_legitimate_address_p (machine_mode mode, rtx x, bool strict)
9a5775fe 5856{
5857 /* The register indirect addresses like @er0 is always valid. */
5858 if (h8300_rtx_ok_for_base_p (x, strict))
5859 return 1;
5860
5861 if (CONSTANT_ADDRESS_P (x))
5862 return 1;
5863
727c62dd 5864 if (TARGET_H8300SX
5865 && ( GET_CODE (x) == PRE_INC
5866 || GET_CODE (x) == PRE_DEC
5867 || GET_CODE (x) == POST_INC
5868 || GET_CODE (x) == POST_DEC)
5869 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
5870 return 1;
5871
9a5775fe 5872 if (GET_CODE (x) == PLUS
5873 && CONSTANT_ADDRESS_P (XEXP (x, 1))
727c62dd 5874 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
5875 mode, 0), strict))
9a5775fe 5876 return 1;
5877
5878 return 0;
5879}
a578a1cc 5880
5881/* Worker function for HARD_REGNO_NREGS.
5882
5883 We pretend the MAC register is 32bits -- we don't have any data
5884 types on the H8 series to handle more than 32bits. */
5885
5886int
3754d046 5887h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, machine_mode mode)
a578a1cc 5888{
5889 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5890}
5891
b395382f 5892/* Implement TARGET_HARD_REGNO_MODE_OK. */
a578a1cc 5893
b395382f 5894static bool
5895h8300_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
a578a1cc 5896{
5897 if (TARGET_H8300)
5898 /* If an even reg, then anything goes. Otherwise the mode must be
5899 QI or HI. */
5900 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
5901 else
5902 /* MAC register can only be of SImode. Otherwise, anything
5903 goes. */
5904 return regno == MAC_REG ? mode == SImode : 1;
5905}
e8bd1224 5906
5907/* Helper function for the move patterns. Make sure a move is legitimate. */
5908
5909bool
5910h8300_move_ok (rtx dest, rtx src)
5911{
5912 rtx addr, other;
5913
5914 /* Validate that at least one operand is a register. */
5915 if (MEM_P (dest))
5916 {
5917 if (MEM_P (src) || CONSTANT_P (src))
5918 return false;
5919 addr = XEXP (dest, 0);
5920 other = src;
5921 }
5922 else if (MEM_P (src))
5923 {
5924 addr = XEXP (src, 0);
5925 other = dest;
5926 }
5927 else
5928 return true;
5929
5930 /* Validate that auto-inc doesn't affect OTHER. */
5931 if (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC)
5932 return true;
5933 addr = XEXP (addr, 0);
5934
5935 if (addr == stack_pointer_rtx)
5936 return register_no_sp_elim_operand (other, VOIDmode);
5937 else
5938 return !reg_overlap_mentioned_p(other, addr);
5939}
9fb90c4e 5940\f
f2f543a3 5941/* Perform target dependent optabs initialization. */
5942static void
5943h8300_init_libfuncs (void)
5944{
5945 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
5946 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
5947 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
5948 set_optab_libfunc (smod_optab, HImode, "__modhi3");
5949 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
5950}
5951\f
9f4cd859 5952/* Worker function for TARGET_FUNCTION_VALUE.
5953
5954 On the H8 the return value is in R0/R1. */
5955
5956static rtx
5957h8300_function_value (const_tree ret_type,
5958 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
5959 bool outgoing ATTRIBUTE_UNUSED)
5960{
5961 return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG);
5962}
5963
5964/* Worker function for TARGET_LIBCALL_VALUE.
5965
5966 On the H8 the return value is in R0/R1. */
5967
5968static rtx
3754d046 5969h8300_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
9f4cd859 5970{
5971 return gen_rtx_REG (mode, R0_REG);
5972}
5973
5974/* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5975
5976 On the H8, R0 is the only register thus used. */
5977
5978static bool
5979h8300_function_value_regno_p (const unsigned int regno)
5980{
5981 return (regno == R0_REG);
5982}
5983
cdfb02e8 5984/* Worker function for TARGET_RETURN_IN_MEMORY. */
5985
5c6c612a 5986static bool
fb80456a 5987h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5c6c612a 5988{
5989 return (TYPE_MODE (type) == BLKmode
5990 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
5991}
5992\f
70fe8eb7 5993/* We emit the entire trampoline here. Depending on the pointer size,
5994 we use a different trampoline.
5995
5996 Pmode == HImode
5997 vvvv context
5998 1 0000 7903xxxx mov.w #0x1234,r3
5999 2 0004 5A00xxxx jmp @0x1234
6000 ^^^^ function
6001
6002 Pmode == SImode
6003 vvvvvvvv context
6004 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
6005 3 0006 5Axxxxxx jmp @0x123456
6006 ^^^^^^ function
6007*/
6008
6009static void
6010h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
6011{
6012 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6013 rtx mem;
6014
6015 if (Pmode == HImode)
6016 {
6017 mem = adjust_address (m_tramp, HImode, 0);
6018 emit_move_insn (mem, GEN_INT (0x7903));
6019 mem = adjust_address (m_tramp, Pmode, 2);
6020 emit_move_insn (mem, cxt);
6021 mem = adjust_address (m_tramp, HImode, 4);
6022 emit_move_insn (mem, GEN_INT (0x5a00));
6023 mem = adjust_address (m_tramp, Pmode, 6);
6024 emit_move_insn (mem, fnaddr);
6025 }
6026 else
6027 {
6028 rtx tem;
6029
6030 mem = adjust_address (m_tramp, HImode, 0);
6031 emit_move_insn (mem, GEN_INT (0x7a03));
6032 mem = adjust_address (m_tramp, Pmode, 2);
6033 emit_move_insn (mem, cxt);
6034
6035 tem = copy_to_reg (fnaddr);
6036 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff)));
6037 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000)));
6038 mem = adjust_address (m_tramp, SImode, 6);
6039 emit_move_insn (mem, tem);
6040 }
6041}
6042\f
9fb90c4e 6043/* Initialize the GCC target structure. */
6044#undef TARGET_ATTRIBUTE_TABLE
6045#define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
6046
6047#undef TARGET_ASM_ALIGNED_HI_OP
6048#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
6049
92c473b8 6050#undef TARGET_ASM_FILE_START
6051#define TARGET_ASM_FILE_START h8300_file_start
6052#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
6053#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
6054
9fb90c4e 6055#undef TARGET_ASM_FILE_END
6056#define TARGET_ASM_FILE_END h8300_file_end
6057
87ad9aff 6058#undef TARGET_PRINT_OPERAND
6059#define TARGET_PRINT_OPERAND h8300_print_operand
6060#undef TARGET_PRINT_OPERAND_ADDRESS
6061#define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
6062#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
6063#define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
6064
9fb90c4e 6065#undef TARGET_ENCODE_SECTION_INFO
6066#define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
6067
6068#undef TARGET_INSERT_ATTRIBUTES
6069#define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
6070
87ad9aff 6071#undef TARGET_REGISTER_MOVE_COST
6072#define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
6073
9fb90c4e 6074#undef TARGET_RTX_COSTS
6075#define TARGET_RTX_COSTS h8300_rtx_costs
6076
f2f543a3 6077#undef TARGET_INIT_LIBFUNCS
6078#define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
6079
9f4cd859 6080#undef TARGET_FUNCTION_VALUE
6081#define TARGET_FUNCTION_VALUE h8300_function_value
6082
6083#undef TARGET_LIBCALL_VALUE
6084#define TARGET_LIBCALL_VALUE h8300_libcall_value
6085
6086#undef TARGET_FUNCTION_VALUE_REGNO_P
6087#define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
6088
5c6c612a 6089#undef TARGET_RETURN_IN_MEMORY
6090#define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
6091
e7489b8b 6092#undef TARGET_FUNCTION_ARG
6093#define TARGET_FUNCTION_ARG h8300_function_arg
6094
6095#undef TARGET_FUNCTION_ARG_ADVANCE
6096#define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
6097
727c62dd 6098#undef TARGET_MACHINE_DEPENDENT_REORG
6099#define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
6100
cf695b54 6101#undef TARGET_HARD_REGNO_SCRATCH_OK
6102#define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
6103
b395382f 6104#undef TARGET_HARD_REGNO_MODE_OK
6105#define TARGET_HARD_REGNO_MODE_OK h8300_hard_regno_mode_ok
6106
e46fbef5 6107#undef TARGET_LRA_P
6108#define TARGET_LRA_P hook_bool_void_false
6109
fd50b071 6110#undef TARGET_LEGITIMATE_ADDRESS_P
6111#define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
6112
cd90919d 6113#undef TARGET_CAN_ELIMINATE
6114#define TARGET_CAN_ELIMINATE h8300_can_eliminate
6115
b2d7ede1 6116#undef TARGET_CONDITIONAL_REGISTER_USAGE
6117#define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
6118
70fe8eb7 6119#undef TARGET_TRAMPOLINE_INIT
6120#define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6121
4c834714 6122#undef TARGET_OPTION_OVERRIDE
6123#define TARGET_OPTION_OVERRIDE h8300_option_override
6124
958f5301 6125#undef TARGET_MODE_DEPENDENT_ADDRESS_P
6126#define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6127
9fb90c4e 6128struct gcc_target targetm = TARGET_INITIALIZER;
Mirror of https://gcc.gnu.org/git/gcc.git