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bootstrap-ubsan.mk (POSTSTAGE1_LDFLAGS): Add -ldl.
[thirdparty/gcc.git] / gcc / config / h8300 / h8300.c
CommitLineData
340f6494 1/* Subroutines for insn-output.c for Renesas H8/300.
d1e082c2 2 Copyright (C) 1992-2013 Free Software Foundation, Inc.
48837e29
DE		 3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
07aae5c2 5
8aa063fb 6This file is part of GCC.
07aae5c2 7
8aa063fb 8GCC is free software; you can redistribute it and/or modify
07aae5c2 9it under the terms of the GNU General Public License as published by
2f83c7d6 10the Free Software Foundation; either version 3, or (at your option)
07aae5c2
SC		 11any later version.
12
8aa063fb 13GCC is distributed in the hope that it will be useful,
07aae5c2
SC		 14but WITHOUT ANY WARRANTY; without even the implied warranty of
15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
2f83c7d6
NC		 19along with GCC; see the file COPYING3. If not see
20<http://www.gnu.org/licenses/>. */
07aae5c2 21
07aae5c2 22#include "config.h"
c5c76735 23#include "system.h"
4977bab6
ZW		 24#include "coretypes.h"
25#include "tm.h"
07aae5c2 26#include "rtl.h"
bf6bb899 27#include "tree.h"
07aae5c2
SC		 28#include "regs.h"
29#include "hard-reg-set.h"
07aae5c2
SC		 30#include "insn-config.h"
31#include "conditions.h"
07aae5c2
SC		 32#include "output.h"
33#include "insn-attr.h"
34#include "flags.h"
35#include "recog.h"
36#include "expr.h"
bf6bb899 37#include "function.h"
c15c90bb 38#include "optabs.h"
718f9c0f 39#include "diagnostic-core.h"
39dabefd 40#include "c-family/c-pragma.h" /* ??? */
441d04c6 41#include "tm_p.h"
ceaaaeab 42#include "tm-constrs.h"
f2a9645f 43#include "ggc.h"
672a6f42
NB		 44#include "target.h"
45#include "target-def.h"
9690aa8e 46#include "df.h"
07aae5c2 47
beed8fc0
AO		 48/* Classifies a h8300_src_operand or h8300_dst_operand.
49
50 H8OP_IMMEDIATE
51 A constant operand of some sort.
52
53 H8OP_REGISTER
54 An ordinary register.
55
56 H8OP_MEM_ABSOLUTE
57 A memory reference with a constant address.
58
59 H8OP_MEM_BASE
60 A memory reference with a register as its address.
61
62 H8OP_MEM_COMPLEX
63 Some other kind of memory reference. */
64enum h8300_operand_class
65{
66 H8OP_IMMEDIATE,
67 H8OP_REGISTER,
68 H8OP_MEM_ABSOLUTE,
69 H8OP_MEM_BASE,
70 H8OP_MEM_COMPLEX,
71 NUM_H8OPS
72};
73
beed8fc0
AO		 74/* For a general two-operand instruction, element [X][Y] gives
75 the length of the opcode fields when the first operand has class
76 (X + 1) and the second has class Y. */
77typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
78
07aae5c2 79/* Forward declarations. */
cb713a8d
KH		 80static const char *byte_reg (rtx, int);
81static int h8300_interrupt_function_p (tree);
3cfa3702 82static int h8300_saveall_function_p (tree);
cb713a8d
KH		 83static int h8300_monitor_function_p (tree);
84static int h8300_os_task_function_p (tree);
c72ea086 85static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool);
e68d4dd1 86static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
cb713a8d 87static unsigned int compute_saved_regs (void);
cb713a8d
KH		 88static const char *cond_string (enum rtx_code);
89static unsigned int h8300_asm_insn_count (const char *);
cb713a8d
KH		 90static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
91static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
92static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
88cb339e
N		 93static void h8300_print_operand_address (FILE *, rtx);
94static void h8300_print_operand (FILE *, rtx, int);
95static bool h8300_print_operand_punct_valid_p (unsigned char code);
ede75ee8 96#ifndef OBJECT_FORMAT_ELF
c18a5b6c 97static void h8300_asm_named_section (const char *, unsigned int, tree);
ede75ee8 98#endif
88cb339e 99static int h8300_register_move_cost (enum machine_mode, reg_class_t, reg_class_t);
cb713a8d
KH		 100static int h8300_and_costs (rtx);
101static int h8300_shift_costs (rtx);
ac447f25 102static void h8300_push_pop (int, int, bool, bool);
beed8fc0
AO		 103static int h8300_stack_offset_p (rtx, int);
104static int h8300_ldm_stm_regno (rtx, int, int, int);
beed8fc0
AO		 105static void h8300_reorg (void);
106static unsigned int h8300_constant_length (rtx);
107static unsigned int h8300_displacement_length (rtx, int);
108static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *);
109static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *);
110static unsigned int h8300_unary_length (rtx);
111static unsigned int h8300_short_immediate_length (rtx);
112static unsigned int h8300_bitfield_length (rtx, rtx);
113static unsigned int h8300_binary_length (rtx, const h8300_length_table *);
114static bool h8300_short_move_mem_p (rtx, enum rtx_code);
115static unsigned int h8300_move_length (rtx *, const h8300_length_table *);
2e762884 116static bool h8300_hard_regno_scratch_ok (unsigned int);
f52d97da 117static rtx h8300_get_index (rtx, enum machine_mode mode, int *);
f5b65a56 118
48837e29
DE		 119/* CPU_TYPE, says what cpu we're compiling for. */
120int cpu_type;
121
e392d367
KH		 122/* True if a #pragma interrupt has been seen for the current function. */
123static int pragma_interrupt;
07aae5c2
SC		 124
125/* True if a #pragma saveall has been seen for the current function. */
0869f126 126static int pragma_saveall;
07aae5c2 127
441d04c6 128static const char *const names_big[] =
07e4d94e 129{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
48837e29 130
441d04c6 131static const char *const names_extended[] =
07e4d94e 132{ "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
48837e29 133
441d04c6 134static const char *const names_upper_extended[] =
07e4d94e 135{ "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
48837e29
DE		 136
137/* Points to one of the above. */
138/* ??? The above could be put in an array indexed by CPU_TYPE. */
441d04c6 139const char * const *h8_reg_names;
48837e29
DE		 140
141/* Various operations needed by the following, indexed by CPU_TYPE. */
48837e29 142
441d04c6 143const char *h8_push_op, *h8_pop_op, *h8_mov_op;
dc66a1c4 144
beed8fc0
AO		 145/* Value of MOVE_RATIO. */
146int h8300_move_ratio;
672a6f42 147\f
c4dfc70c
DD		 148/* See below where shifts are handled for explanation of this enum. */
149
150enum shift_alg
151{
152 SHIFT_INLINE,
153 SHIFT_ROT_AND,
154 SHIFT_SPECIAL,
155 SHIFT_LOOP
156};
157
158/* Symbols of the various shifts which can be used as indices. */
159
160enum shift_type
161{
162 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
163};
164
165/* Macros to keep the shift algorithm tables small. */
166#define INL SHIFT_INLINE
167#define ROT SHIFT_ROT_AND
168#define LOP SHIFT_LOOP
169#define SPC SHIFT_SPECIAL
170
171/* The shift algorithms for each machine, mode, shift type, and shift
172 count are defined below. The three tables below correspond to
173 QImode, HImode, and SImode, respectively. Each table is organized
f411c849 174 by, in the order of indices, machine, shift type, and shift count. */
c4dfc70c
DD		 175
176static enum shift_alg shift_alg_qi[3][3][8] = {
177 {
178 /* TARGET_H8300 */
179 /* 0 1 2 3 4 5 6 7 */
180 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
181 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
182 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
183 },
184 {
185 /* TARGET_H8300H */
186 /* 0 1 2 3 4 5 6 7 */
187 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
188 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
189 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
190 },
191 {
192 /* TARGET_H8300S */
193 /* 0 1 2 3 4 5 6 7 */
194 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
195 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
196 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
197 }
198};
199
200static enum shift_alg shift_alg_hi[3][3][16] = {
201 {
202 /* TARGET_H8300 */
203 /* 0 1 2 3 4 5 6 7 */
204 /* 8 9 10 11 12 13 14 15 */
205 { INL, INL, INL, INL, INL, INL, INL, SPC,
206 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
207 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
208 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
209 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
210 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
211 },
212 {
213 /* TARGET_H8300H */
214 /* 0 1 2 3 4 5 6 7 */
215 /* 8 9 10 11 12 13 14 15 */
216 { INL, INL, INL, INL, INL, INL, INL, SPC,
217 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
218 { INL, INL, INL, INL, INL, INL, INL, SPC,
219 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
220 { INL, INL, INL, INL, INL, INL, INL, SPC,
221 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
222 },
223 {
224 /* TARGET_H8300S */
225 /* 0 1 2 3 4 5 6 7 */
226 /* 8 9 10 11 12 13 14 15 */
227 { INL, INL, INL, INL, INL, INL, INL, INL,
228 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
229 { INL, INL, INL, INL, INL, INL, INL, INL,
230 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
231 { INL, INL, INL, INL, INL, INL, INL, INL,
232 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
233 }
234};
235
236static enum shift_alg shift_alg_si[3][3][32] = {
237 {
238 /* TARGET_H8300 */
239 /* 0 1 2 3 4 5 6 7 */
240 /* 8 9 10 11 12 13 14 15 */
241 /* 16 17 18 19 20 21 22 23 */
242 /* 24 25 26 27 28 29 30 31 */
243 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
244 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
245 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
246 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
247 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
248 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
249 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
250 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
251 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
252 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
253 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
254 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
255 },
256 {
257 /* TARGET_H8300H */
258 /* 0 1 2 3 4 5 6 7 */
259 /* 8 9 10 11 12 13 14 15 */
260 /* 16 17 18 19 20 21 22 23 */
261 /* 24 25 26 27 28 29 30 31 */
262 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
263 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
264 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
1e5bdc40 265 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
c4dfc70c
DD		 266 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
267 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
268 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
1e5bdc40 269 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
c4dfc70c
DD		 270 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
271 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
272 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
273 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
274 },
275 {
276 /* TARGET_H8300S */
277 /* 0 1 2 3 4 5 6 7 */
278 /* 8 9 10 11 12 13 14 15 */
279 /* 16 17 18 19 20 21 22 23 */
280 /* 24 25 26 27 28 29 30 31 */
281 { INL, INL, INL, INL, INL, INL, INL, INL,
282 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
283 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
1e5bdc40 284 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
c4dfc70c
DD		 285 { INL, INL, INL, INL, INL, INL, INL, INL,
286 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
287 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
1e5bdc40 288 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
c4dfc70c
DD		 289 { INL, INL, INL, INL, INL, INL, INL, INL,
290 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
291 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
292 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
293 }
294};
295
296#undef INL
297#undef ROT
298#undef LOP
299#undef SPC
300
301enum h8_cpu
302{
303 H8_300,
304 H8_300H,
305 H8_S
306};
307
48837e29
DE		 308/* Initialize various cpu specific globals at start up. */
309
c5387660
JM		 310static void
311h8300_option_override (void)
48837e29 312{
cbf1b2da
KH		 313 static const char *const h8_push_ops[2] = { "push" , "push.l" };
314 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
315 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
316
f4ea8112
SKS		 317#ifndef OBJECT_FORMAT_ELF
318 if (TARGET_H8300SX)
319 {
320 error ("-msx is not supported in coff");
321 target_flags |= MASK_H8300S;
322 }
323#endif
324
48837e29
DE		 325 if (TARGET_H8300)
326 {
327 cpu_type = (int) CPU_H8300;
328 h8_reg_names = names_big;
329 }
330 else
331 {
3db11b5c 332 /* For this we treat the H8/300H and H8S the same. */
48837e29
DE		 333 cpu_type = (int) CPU_H8300H;
334 h8_reg_names = names_extended;
335 }
336 h8_push_op = h8_push_ops[cpu_type];
337 h8_pop_op = h8_pop_ops[cpu_type];
338 h8_mov_op = h8_mov_ops[cpu_type];
17f0f8fa
KH		 339
340 if (!TARGET_H8300S && TARGET_MAC)
400500c4 341 {
c725bd79 342 error ("-ms2600 is used without -ms");
5463c726 343 target_flags |= MASK_H8300S_1;
400500c4 344 }
920e86b8 345
39ba95b5
VK		 346 if (TARGET_H8300 && TARGET_NORMAL_MODE)
347 {
f4ea8112 348 error ("-mn is used without -mh or -ms or -msx");
39ba95b5
VK		 349 target_flags ^= MASK_NORMAL_MODE;
350 }
c4dfc70c 351
f4ea8112
SKS		 352 if (! TARGET_H8300S && TARGET_EXR)
353 {
354 error ("-mexr is used without -ms");
355 target_flags |= MASK_H8300S_1;
356 }
357
358 if (TARGET_H8300 && TARGET_INT32)
359 {
360 error ("-mint32 is not supported for H8300 and H8300L targets");
361 target_flags ^= MASK_INT32;
362 }
363
364 if ((!TARGET_H8300S && TARGET_EXR) && (!TARGET_H8300SX && TARGET_EXR))
365 {
366 error ("-mexr is used without -ms or -msx");
367 target_flags |= MASK_H8300S_1;
368 }
369
370 if ((!TARGET_H8300S && TARGET_NEXR) && (!TARGET_H8300SX && TARGET_NEXR))
371 {
372 warning (OPT_mno_exr, "-mno-exr valid only with -ms or -msx \
373 - Option ignored!");
374 }
375
8bd06267 376 /* Some of the shifts are optimized for speed by default.
c4dfc70c 377 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
8bd06267 378 If optimizing for size, change shift_alg for those shift to
c4dfc70c 379 SHIFT_LOOP. */
b6894857 380 if (optimize_size)
c4dfc70c 381 {
b6894857
KH		 382 /* H8/300 */
383 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
384 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
385 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
386 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
c4dfc70c 387
b6894857
KH		 388 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
389 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
c4dfc70c 390
b6894857
KH		 391 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
392 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
c4dfc70c 393
b6894857
KH		 394 /* H8/300H */
395 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
396 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
c4dfc70c 397
b6894857
KH		 398 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
399 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
c4dfc70c 400
b6894857
KH		 401 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
402 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
403 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
404 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
c4dfc70c
DD		 405
406 /* H8S */
b6894857 407 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
c4dfc70c 408 }
beed8fc0
AO		 409
410 /* Work out a value for MOVE_RATIO. */
411 if (!TARGET_H8300SX)
412 {
413 /* Memory-memory moves are quite expensive without the
414 h8sx instructions. */
415 h8300_move_ratio = 3;
416 }
417 else if (flag_omit_frame_pointer)
418 {
419 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
420 sometimes be as short as two individual memory-to-memory moves,
421 but since they use all the call-saved registers, it seems better
422 to allow up to three moves here. */
423 h8300_move_ratio = 4;
424 }
425 else if (optimize_size)
426 {
427 /* In this case we don't use movmd sequences since they tend
428 to be longer than calls to memcpy(). Memory-to-memory
429 moves are cheaper than for !TARGET_H8300SX, so it makes
430 sense to have a slightly higher threshold. */
431 h8300_move_ratio = 4;
432 }
433 else
434 {
435 /* We use movmd sequences for some moves since it can be quicker
436 than calling memcpy(). The sequences will need to save and
437 restore er6 though, so bump up the cost. */
438 h8300_move_ratio = 6;
439 }
0685e770
DD		 440
441 /* This target defaults to strict volatile bitfields. */
36acc1a2 442 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
0685e770 443 flag_strict_volatile_bitfields = 1;
beed8fc0
AO		 444}
445
e9eba255
KH		 446/* Return the byte register name for a register rtx X. B should be 0
447 if you want a lower byte register. B should be 1 if you want an
448 upper byte register. */
449
9c188705 450static const char *
cb713a8d 451byte_reg (rtx x, int b)
07aae5c2 452{
9cbcd983
KH		 453 static const char *const names_small[] = {
454 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
455 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
456 };
07aae5c2 457
8c440872 458 gcc_assert (REG_P (x));
500fc80f 459
07aae5c2
SC		 460 return names_small[REGNO (x) * 2 + b];
461}
462
463/* REGNO must be saved/restored across calls if this macro is true. */
48837e29 464
9cbcd983 465#define WORD_REG_USED(regno) \
d60004ee 466 (regno < SP_REG \
9cbcd983
KH		 467 /* No need to save registers if this function will not return. */ \
468 && ! TREE_THIS_VOLATILE (current_function_decl) \
3cfa3702 469 && (h8300_saveall_function_p (current_function_decl) \
9cbcd983 470 /* Save any call saved register that was used. */ \
6fb5fa3c 471 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
9cbcd983 472 /* Save the frame pointer if it was used. */ \
6fb5fa3c 473 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
9cbcd983 474 /* Save any register used in an interrupt handler. */ \
e392d367 475 || (h8300_current_function_interrupt_function_p () \
6fb5fa3c 476 && df_regs_ever_live_p (regno)) \
9cbcd983
KH		 477 /* Save call clobbered registers in non-leaf interrupt \
478 handlers. */ \
e392d367 479 || (h8300_current_function_interrupt_function_p () \
9cbcd983 480 && call_used_regs[regno] \
416ff32e 481 && !crtl->is_leaf)))
07aae5c2 482
18674659
DD		 483/* We use this to wrap all emitted insns in the prologue. */
484static rtx
c72ea086 485F (rtx x, bool set_it)
18674659 486{
c72ea086
DD		 487 if (set_it)
488 RTX_FRAME_RELATED_P (x) = 1;
18674659
DD		 489 return x;
490}
491
492/* Mark all the subexpressions of the PARALLEL rtx PAR as
493 frame-related. Return PAR.
494
495 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
496 PARALLEL rtx other than the first if they do not have the
497 FRAME_RELATED flag set on them. */
498static rtx
499Fpa (rtx par)
500{
501 int len = XVECLEN (par, 0);
502 int i;
503
504 for (i = 0; i < len; i++)
c72ea086 505 F (XVECEXP (par, 0, i), true);
18674659
DD		 506
507 return par;
508}
509
07aae5c2 510/* Output assembly language to FILE for the operation OP with operand size
48837e29 511 SIZE to adjust the stack pointer. */
48837e29 512
07aae5c2 513static void
c72ea086 514h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue)
07aae5c2 515{
72b1de44
KH		 516 /* If the frame size is 0, we don't have anything to do. */
517 if (size == 0)
f8b58e56 518 return;
72b1de44 519
68ee6df6
KH		 520 /* H8/300 cannot add/subtract a large constant with a single
521 instruction. If a temporary register is available, load the
522 constant to it and then do the addition. */
523 if (TARGET_H8300
524 && size > 4
525 && !h8300_current_function_interrupt_function_p ()
6de9cd9a 526 && !(cfun->static_chain_decl != NULL && sign < 0))
f8f26adc 527 {
68ee6df6 528 rtx r3 = gen_rtx_REG (Pmode, 3);
c72ea086 529 F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue);
18674659 530 F (emit_insn (gen_addhi3 (stack_pointer_rtx,
c72ea086 531 stack_pointer_rtx, r3)), in_prologue);
7b3d4613
KH		 532 }
533 else
534 {
68ee6df6
KH		 535 /* The stack adjustment made here is further optimized by the
536 splitter. In case of H8/300, the splitter always splits the
18674659
DD		 537 addition emitted here to make the adjustment interrupt-safe.
538 FIXME: We don't always tag those, because we don't know what
539 the splitter will do. */
72b1de44 540 if (Pmode == HImode)
18674659
DD		 541 {
542 rtx x = emit_insn (gen_addhi3 (stack_pointer_rtx,
543 stack_pointer_rtx, GEN_INT (sign * size)));
544 if (size < 4)
c72ea086 545 F (x, in_prologue);
18674659 546 }
72b1de44 547 else
18674659 548 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
c72ea086 549 stack_pointer_rtx, GEN_INT (sign * size))), in_prologue);
07aae5c2
SC		 550 }
551}
552
8682223f
KH		 553/* Round up frame size SIZE. */
554
e68d4dd1
UB		 555static HOST_WIDE_INT
556round_frame_size (HOST_WIDE_INT size)
8682223f 557{
489eda65
KH		 558 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
559 & -STACK_BOUNDARY / BITS_PER_UNIT);
8682223f
KH		 560}
561
562/* Compute which registers to push/pop.
563 Return a bit vector of registers. */
564
565static unsigned int
cb713a8d 566compute_saved_regs (void)
8682223f
KH		 567{
568 unsigned int saved_regs = 0;
569 int regno;
570
571 /* Construct a bit vector of registers to be pushed/popped. */
1807b726 572 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
8682223f
KH		 573 {
574 if (WORD_REG_USED (regno))
575 saved_regs |= 1 << regno;
576 }
577
578 /* Don't push/pop the frame pointer as it is treated separately. */
579 if (frame_pointer_needed)
1807b726 580 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
8682223f
KH		 581
582 return saved_regs;
583}
584
68ee6df6 585/* Emit an insn to push register RN. */
8682223f 586
8f1594b2 587static rtx
cb713a8d 588push (int rn)
8682223f 589{
68ee6df6
KH		 590 rtx reg = gen_rtx_REG (word_mode, rn);
591 rtx x;
592
513f31eb 593 if (TARGET_H8300)
68ee6df6 594 x = gen_push_h8300 (reg);
f24f0897 595 else if (!TARGET_NORMAL_MODE)
32da7865 596 x = gen_push_h8300hs_advanced (reg);
f24f0897
KH		 597 else
598 x = gen_push_h8300hs_normal (reg);
ac447f25 599 x = F (emit_insn (x), true);
9690aa8e 600 add_reg_note (x, REG_INC, stack_pointer_rtx);
8f1594b2 601 return x;
8682223f
KH		 602}
603
68ee6df6 604/* Emit an insn to pop register RN. */
8682223f 605
8f1594b2 606static rtx
cb713a8d 607pop (int rn)
8682223f 608{
68ee6df6
KH		 609 rtx reg = gen_rtx_REG (word_mode, rn);
610 rtx x;
611
513f31eb 612 if (TARGET_H8300)
68ee6df6 613 x = gen_pop_h8300 (reg);
f24f0897 614 else if (!TARGET_NORMAL_MODE)
32da7865 615 x = gen_pop_h8300hs_advanced (reg);
f24f0897
KH		 616 else
617 x = gen_pop_h8300hs_normal (reg);
68ee6df6 618 x = emit_insn (x);
9690aa8e 619 add_reg_note (x, REG_INC, stack_pointer_rtx);
8f1594b2 620 return x;
8682223f 621}
07aae5c2 622
beed8fc0
AO		 623/* Emit an instruction to push or pop NREGS consecutive registers
624 starting at register REGNO. POP_P selects a pop rather than a
625 push and RETURN_P is true if the instruction should return.
626
627 It must be possible to do the requested operation in a single
628 instruction. If NREGS == 1 && !RETURN_P, use a normal push
629 or pop insn. Otherwise emit a parallel of the form:
630
631 (parallel
632 [(return) ;; if RETURN_P
633 (save or restore REGNO)
634 (save or restore REGNO + 1)
635 ...
636 (save or restore REGNO + NREGS - 1)
637 (set sp (plus sp (const_int adjust)))] */
638
639static void
ac447f25 640h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p)
beed8fc0
AO		 641{
642 int i, j;
643 rtvec vec;
18674659 644 rtx sp, offset, x;
beed8fc0
AO		 645
646 /* See whether we can use a simple push or pop. */
647 if (!return_p && nregs == 1)
648 {
649 if (pop_p)
650 pop (regno);
651 else
652 push (regno);
653 return;
654 }
655
656 /* We need one element for the return insn, if present, one for each
657 register, and one for stack adjustment. */
ac447f25 658 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1);
beed8fc0
AO		 659 sp = stack_pointer_rtx;
660 i = 0;
661
662 /* Add the return instruction. */
663 if (return_p)
664 {
3810076b 665 RTVEC_ELT (vec, i) = ret_rtx;
beed8fc0
AO		 666 i++;
667 }
668
669 /* Add the register moves. */
670 for (j = 0; j < nregs; j++)
671 {
672 rtx lhs, rhs;
673
674 if (pop_p)
675 {
676 /* Register REGNO + NREGS - 1 is popped first. Before the
677 stack adjustment, its slot is at address @sp. */
678 lhs = gen_rtx_REG (SImode, regno + j);
0a81f074
RS		 679 rhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp,
680 (nregs - j - 1) * 4));
beed8fc0
AO		 681 }
682 else
683 {
684 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
0a81f074 685 lhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, (j + 1) * -4));
beed8fc0
AO		 686 rhs = gen_rtx_REG (SImode, regno + j);
687 }
688 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, lhs, rhs);
689 }
690
691 /* Add the stack adjustment. */
692 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
693 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, sp,
694 gen_rtx_PLUS (Pmode, sp, offset));
695
18674659
DD		 696 x = gen_rtx_PARALLEL (VOIDmode, vec);
697 if (!pop_p)
698 x = Fpa (x);
ac447f25
NC		 699
700 if (return_p)
701 emit_jump_insn (x);
702 else
703 emit_insn (x);
beed8fc0
AO		 704}
705
706/* Return true if X has the value sp + OFFSET. */
707
708static int
709h8300_stack_offset_p (rtx x, int offset)
710{
711 if (offset == 0)
712 return x == stack_pointer_rtx;
713
714 return (GET_CODE (x) == PLUS
715 && XEXP (x, 0) == stack_pointer_rtx
716 && GET_CODE (XEXP (x, 1)) == CONST_INT
717 && INTVAL (XEXP (x, 1)) == offset);
718}
719
720/* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
721 something that may be an ldm or stm instruction. If it fits
722 the required template, return the register it loads or stores,
723 otherwise return -1.
724
725 LOAD_P is true if X should be a load, false if it should be a store.
726 NREGS is the number of registers that the whole instruction is expected
727 to load or store. INDEX is the index of the register that X should
728 load or store, relative to the lowest-numbered register. */
729
730static int
731h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
732{
733 int regindex, memindex, offset;
734
735 if (load_p)
736 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
737 else
738 memindex = 0, regindex = 1, offset = (index + 1) * -4;
739
740 if (GET_CODE (x) == SET
741 && GET_CODE (XEXP (x, regindex)) == REG
742 && GET_CODE (XEXP (x, memindex)) == MEM
743 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
744 return REGNO (XEXP (x, regindex));
745
746 return -1;
747}
748
749/* Return true if the elements of VEC starting at FIRST describe an
750 ldm or stm instruction (LOAD_P says which). */
751
981c7dce 752int
beed8fc0
AO		 753h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
754{
755 rtx last;
756 int nregs, i, regno, adjust;
757
758 /* There must be a stack adjustment, a register move, and at least one
759 other operation (a return or another register move). */
760 if (GET_NUM_ELEM (vec) < 3)
761 return false;
762
763 /* Get the range of registers to be pushed or popped. */
764 nregs = GET_NUM_ELEM (vec) - first - 1;
765 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
766
767 /* Check that the call to h8300_ldm_stm_regno succeeded and
768 that we're only dealing with GPRs. */
769 if (regno < 0 || regno + nregs > 8)
770 return false;
771
772 /* 2-register h8s instructions must start with an even-numbered register.
773 3- and 4-register instructions must start with er0 or er4. */
774 if (!TARGET_H8300SX)
775 {
776 if ((regno & 1) != 0)
777 return false;
778 if (nregs > 2 && (regno & 3) != 0)
779 return false;
780 }
781
782 /* Check the other loads or stores. */
783 for (i = 1; i < nregs; i++)
784 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
785 != regno + i)
786 return false;
787
788 /* Check the stack adjustment. */
789 last = RTVEC_ELT (vec, first + nregs);
790 adjust = (load_p ? nregs : -nregs) * 4;
791 return (GET_CODE (last) == SET
792 && SET_DEST (last) == stack_pointer_rtx
793 && h8300_stack_offset_p (SET_SRC (last), adjust));
794}
795
f0b6f9a6 796/* This is what the stack looks like after the prolog of
07aae5c2
SC		 797 a function with a frame has been set up:
798
48837e29
DE		 799 <args>
800 PC
801 FP <- fp
802 <locals>
8bd06267 803 <saved registers> <- sp
07aae5c2
SC		 804
805 This is what the stack looks like after the prolog of
806 a function which doesn't have a frame:
807
48837e29
DE		 808 <args>
809 PC
810 <locals>
8bd06267 811 <saved registers> <- sp
07aae5c2
SC		 812*/
813
68ee6df6 814/* Generate RTL code for the function prologue. */
8682223f 815
68ee6df6 816void
cb713a8d 817h8300_expand_prologue (void)
07aae5c2 818{
e651d484 819 int regno;
8682223f 820 int saved_regs;
cda4bd43 821 int n_regs;
07aae5c2 822
fabe72bb
JL		 823 /* If the current function has the OS_Task attribute set, then
824 we have a naked prologue. */
825 if (h8300_os_task_function_p (current_function_decl))
68ee6df6 826 return;
fabe72bb
JL		 827
828 if (h8300_monitor_function_p (current_function_decl))
f4ea8112
SKS		 829 /* The monitor function act as normal functions, which means it
830 can accept parameters and return values. In addition to this,
831 interrupts are masked in prologue and return with "rte" in epilogue. */
68ee6df6 832 emit_insn (gen_monitor_prologue ());
fabe72bb 833
48837e29
DE		 834 if (frame_pointer_needed)
835 {
07e4d94e 836 /* Push fp. */
1807b726 837 push (HARD_FRAME_POINTER_REGNUM);
ac447f25 838 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true);
a1616dd9 839 }
48837e29 840
8682223f
KH		 841 /* Push the rest of the registers in ascending order. */
842 saved_regs = compute_saved_regs ();
e651d484 843 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
cda4bd43 844 {
cda4bd43 845 n_regs = 1;
8682223f 846 if (saved_regs & (1 << regno))
a1616dd9
JL		 847 {
848 if (TARGET_H8300S)
849 {
cda4bd43 850 /* See how many registers we can push at the same time. */
beed8fc0 851 if ((!TARGET_H8300SX || (regno & 3) == 0)
8682223f 852 && ((saved_regs >> regno) & 0x0f) == 0x0f)
cda4bd43
KH		 853 n_regs = 4;
854
beed8fc0 855 else if ((!TARGET_H8300SX || (regno & 3) == 0)
8682223f 856 && ((saved_regs >> regno) & 0x07) == 0x07)
cda4bd43
KH		 857 n_regs = 3;
858
beed8fc0 859 else if ((!TARGET_H8300SX || (regno & 1) == 0)
8682223f 860 && ((saved_regs >> regno) & 0x03) == 0x03)
cda4bd43 861 n_regs = 2;
a1616dd9 862 }
cda4bd43 863
ac447f25 864 h8300_push_pop (regno, n_regs, false, false);
07aae5c2
SC		 865 }
866 }
1807b726
KH		 867
868 /* Leave room for locals. */
c72ea086 869 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
07aae5c2
SC		 870}
871
e9eba255
KH		 872/* Return nonzero if we can use "rts" for the function currently being
873 compiled. */
874
68ee6df6 875int
cb713a8d 876h8300_can_use_return_insn_p (void)
68ee6df6
KH		 877{
878 return (reload_completed
879 && !frame_pointer_needed
880 && get_frame_size () == 0
881 && compute_saved_regs () == 0);
882}
07aae5c2 883
68ee6df6
KH		 884/* Generate RTL code for the function epilogue. */
885
886void
cb713a8d 887h8300_expand_epilogue (void)
07aae5c2 888{
e651d484 889 int regno;
8682223f 890 int saved_regs;
cda4bd43 891 int n_regs;
beed8fc0
AO		 892 HOST_WIDE_INT frame_size;
893 bool returned_p;
07aae5c2 894
e392d367 895 if (h8300_os_task_function_p (current_function_decl))
68ee6df6
KH		 896 /* OS_Task epilogues are nearly naked -- they just have an
897 rts instruction. */
898 return;
07aae5c2 899
beed8fc0
AO		 900 frame_size = round_frame_size (get_frame_size ());
901 returned_p = false;
902
1807b726 903 /* Deallocate locals. */
c72ea086 904 h8300_emit_stack_adjustment (1, frame_size, false);
1807b726 905
8682223f
KH		 906 /* Pop the saved registers in descending order. */
907 saved_regs = compute_saved_regs ();
e651d484 908 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
cda4bd43 909 {
cda4bd43 910 n_regs = 1;
8682223f 911 if (saved_regs & (1 << regno))
07aae5c2 912 {
a1616dd9
JL		 913 if (TARGET_H8300S)
914 {
cda4bd43 915 /* See how many registers we can pop at the same time. */
beed8fc0
AO		 916 if ((TARGET_H8300SX || (regno & 3) == 3)
917 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
cda4bd43
KH		 918 n_regs = 4;
919
beed8fc0
AO		 920 else if ((TARGET_H8300SX || (regno & 3) == 2)
921 && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
cda4bd43
KH		 922 n_regs = 3;
923
beed8fc0
AO		 924 else if ((TARGET_H8300SX || (regno & 1) == 1)
925 && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
cda4bd43 926 n_regs = 2;
a1616dd9 927 }
cda4bd43 928
beed8fc0
AO		 929 /* See if this pop would be the last insn before the return.
930 If so, use rte/l or rts/l instead of pop or ldm.l. */
931 if (TARGET_H8300SX
932 && !frame_pointer_needed
933 && frame_size == 0
934 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
935 returned_p = true;
936
ac447f25 937 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p);
07aae5c2 938 }
07aae5c2 939 }
48837e29 940
07e4d94e 941 /* Pop frame pointer if we had one. */
a1616dd9 942 if (frame_pointer_needed)
beed8fc0
AO		 943 {
944 if (TARGET_H8300SX)
945 returned_p = true;
ac447f25 946 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p);
beed8fc0
AO		 947 }
948
949 if (!returned_p)
3810076b 950 emit_jump_insn (ret_rtx);
68ee6df6 951}
a1616dd9 952
e392d367
KH		 953/* Return nonzero if the current function is an interrupt
954 function. */
955
956int
cb713a8d 957h8300_current_function_interrupt_function_p (void)
e392d367 958{
f4ea8112
SKS		 959 return (h8300_interrupt_function_p (current_function_decl));
960}
961
962int
963h8300_current_function_monitor_function_p ()
964{
965 return (h8300_monitor_function_p (current_function_decl));
e392d367
KH		 966}
967
48837e29
DE		 968/* Output assembly code for the start of the file. */
969
1bc7c5b6
ZW		 970static void
971h8300_file_start (void)
48837e29 972{
1bc7c5b6 973 default_file_start ();
8bd06267 974
48837e29 975 if (TARGET_H8300H)
1bc7c5b6 976 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
beed8fc0
AO		 977 else if (TARGET_H8300SX)
978 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
a1616dd9 979 else if (TARGET_H8300S)
1bc7c5b6 980 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
48837e29
DE		 981}
982
983/* Output assembly language code for the end of file. */
984
a5fe455b 985static void
cb713a8d 986h8300_file_end (void)
48837e29 987{
a5fe455b 988 fputs ("\t.end\n", asm_out_file);
07aae5c2
SC		 989}
990\f
3cee1a78
KH		 991/* Split an add of a small constant into two adds/subs insns.
992
993 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
994 instead of adds/subs. */
009ac3d3
RH		 995
996void
cb713a8d 997split_adds_subs (enum machine_mode mode, rtx *operands)
3b7d443c 998{
009ac3d3
RH		 999 HOST_WIDE_INT val = INTVAL (operands[1]);
1000 rtx reg = operands[0];
9492393e
KH		 1001 HOST_WIDE_INT sign = 1;
1002 HOST_WIDE_INT amount;
590734b6 1003 rtx (*gen_add) (rtx, rtx, rtx);
3b7d443c 1004
9492393e
KH		 1005 /* Force VAL to be positive so that we do not have to consider the
1006 sign. */
1007 if (val < 0)
3b7d443c 1008 {
9492393e
KH		 1009 val = -val;
1010 sign = -1;
1011 }
3b7d443c 1012
3cee1a78
KH		 1013 switch (mode)
1014 {
1015 case HImode:
590734b6 1016 gen_add = gen_addhi3;
3cee1a78
KH		 1017 break;
1018
1019 case SImode:
590734b6 1020 gen_add = gen_addsi3;
3cee1a78
KH		 1021 break;
1022
1023 default:
8c440872 1024 gcc_unreachable ();
3cee1a78
KH		 1025 }
1026
9492393e
KH		 1027 /* Try different amounts in descending order. */
1028 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
1029 amount > 0;
1030 amount /= 2)
1031 {
1a63219b 1032 for (; val >= amount; val -= amount)
590734b6 1033 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
3b7d443c
JL		 1034 }
1035
9492393e 1036 return;
3b7d443c
JL		 1037}
1038
07aae5c2 1039/* Handle machine specific pragmas for compatibility with existing
48837e29 1040 compilers for the H8/300.
07aae5c2 1041
f411c849 1042 pragma saveall generates prologue/epilogue code which saves and
07aae5c2 1043 restores all the registers on function entry.
48837e29 1044
07aae5c2
SC		 1045 pragma interrupt saves and restores all registers, and exits with
1046 an rte instruction rather than an rts. A pointer to a function
1047 with this attribute may be safely used in an interrupt vector. */
48837e29 1048
8b97c5f8 1049void
cb713a8d 1050h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
07aae5c2 1051{
e392d367 1052 pragma_interrupt = 1;
8b97c5f8 1053}
05a81fe5 1054
8b97c5f8 1055void
cb713a8d 1056h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
8b97c5f8
ZW		 1057{
1058 pragma_saveall = 1;
07aae5c2 1059}
8b97c5f8 1060
64bead4c
KH		 1061/* If the next function argument with MODE and TYPE is to be passed in
1062 a register, return a reg RTX for the hard register in which to pass
1063 the argument. CUM represents the state after the last argument.
56f9413b 1064 If the argument is to be pushed, NULL_RTX is returned.
48837e29 1065
56f9413b
NF		 1066 On the H8/300 all normal args are pushed, unless -mquickcall in which
1067 case the first 3 arguments are passed in registers. */
1068
1069static rtx
d5cc9181 1070h8300_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
56f9413b 1071 const_tree type, bool named)
07aae5c2 1072{
d5cc9181
JR		 1073 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1074
0ea6f6a0
KH		 1075 static const char *const hand_list[] = {
1076 "__main",
1077 "__cmpsi2",
1078 "__divhi3",
1079 "__modhi3",
1080 "__udivhi3",
1081 "__umodhi3",
1082 "__divsi3",
1083 "__modsi3",
1084 "__udivsi3",
1085 "__umodsi3",
1086 "__mulhi3",
1087 "__mulsi3",
1088 "__reg_memcpy",
1089 "__reg_memset",
1090 "__ucmpsi2",
1091 0,
1092 };
1093
7192cbf1 1094 rtx result = NULL_RTX;
441d04c6 1095 const char *fname;
48837e29
DE		 1096 int regpass = 0;
1097
dd07092e
JL		 1098 /* Never pass unnamed arguments in registers. */
1099 if (!named)
7192cbf1 1100 return NULL_RTX;
dd07092e 1101
48837e29
DE		 1102 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1103 if (TARGET_QUICKCALL)
1104 regpass = 3;
1105
1106 /* If calling hand written assembler, use 4 regs of args. */
48837e29
DE		 1107 if (cum->libcall)
1108 {
441d04c6 1109 const char * const *p;
48837e29
DE		 1110
1111 fname = XSTR (cum->libcall, 0);
1112
1113 /* See if this libcall is one of the hand coded ones. */
48837e29
DE		 1114 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1115 ;
07aae5c2 1116
48837e29
DE		 1117 if (*p)
1118 regpass = 4;
1119 }
1120
1121 if (regpass)
1122 {
1123 int size;
1124
1125 if (mode == BLKmode)
1126 size = int_size_in_bytes (type);
1127 else
1128 size = GET_MODE_SIZE (mode);
1129
15e0e275
KH		 1130 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1131 && cum->nbytes / UNITS_PER_WORD <= 3)
1132 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
48837e29 1133 }
07aae5c2 1134
48837e29
DE		 1135 return result;
1136}
56f9413b
NF		 1137
1138/* Update the data in CUM to advance over an argument
1139 of mode MODE and data type TYPE.
1140 (TYPE is null for libcalls where that information may not be available.) */
1141
1142static void
d5cc9181 1143h8300_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
56f9413b
NF		 1144 const_tree type, bool named ATTRIBUTE_UNUSED)
1145{
d5cc9181
JR		 1146 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1147
56f9413b
NF		 1148 cum->nbytes += (mode != BLKmode
1149 ? (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD
1150 : (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD);
1151}
1152
48837e29 1153\f
88cb339e
N		 1154/* Implements TARGET_REGISTER_MOVE_COST.
1155
1156 Any SI register-to-register move may need to be reloaded,
1157 so inmplement h8300_register_move_cost to return > 2 so that reload never
1158 shortcuts. */
1159
1160static int
1161h8300_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1162 reg_class_t from, reg_class_t to)
1163{
1164 if (from == MAC_REGS || to == MAC_REG)
1165 return 6;
1166 else
1167 return 3;
1168}
1169
e9eba255
KH		 1170/* Compute the cost of an and insn. */
1171
3c50106f 1172static int
cb713a8d 1173h8300_and_costs (rtx x)
73cc75e9
KH		 1174{
1175 rtx operands[4];
1176
1177 if (GET_MODE (x) == QImode)
1178 return 1;
1179
1180 if (GET_MODE (x) != HImode
1181 && GET_MODE (x) != SImode)
1182 return 100;
1183
1184 operands[0] = NULL;
beed8fc0 1185 operands[1] = XEXP (x, 0);
73cc75e9
KH		 1186 operands[2] = XEXP (x, 1);
1187 operands[3] = x;
4f4ebda3 1188 return compute_logical_op_length (GET_MODE (x), operands) / 2;
73cc75e9
KH		 1189}
1190
e9eba255
KH		 1191/* Compute the cost of a shift insn. */
1192
3c50106f 1193static int
cb713a8d 1194h8300_shift_costs (rtx x)
ae557002
KH		 1195{
1196 rtx operands[4];
1197
1198 if (GET_MODE (x) != QImode
1199 && GET_MODE (x) != HImode
1200 && GET_MODE (x) != SImode)
1201 return 100;
1202
1203 operands[0] = NULL;
1204 operands[1] = NULL;
1205 operands[2] = XEXP (x, 1);
1206 operands[3] = x;
4f4ebda3 1207 return compute_a_shift_length (NULL, operands) / 2;
ae557002 1208}
3c50106f 1209
e9eba255
KH		 1210/* Worker function for TARGET_RTX_COSTS. */
1211
3c50106f 1212static bool
68f932c4
RS		 1213h8300_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
1214 int *total, bool speed)
3c50106f 1215{
beed8fc0
AO		 1216 if (TARGET_H8300SX && outer_code == MEM)
1217 {
1218 /* Estimate the number of execution states needed to calculate
1219 the address. */
1220 if (register_operand (x, VOIDmode)
1221 || GET_CODE (x) == POST_INC
1222 || GET_CODE (x) == POST_DEC
1223 || CONSTANT_P (x))
1224 *total = 0;
1225 else
1226 *total = COSTS_N_INSNS (1);
1227 return true;
1228 }
1229
3c50106f
RH		 1230 switch (code)
1231 {
08dca707
KH		 1232 case CONST_INT:
1233 {
1234 HOST_WIDE_INT n = INTVAL (x);
1235
beed8fc0
AO		 1236 if (TARGET_H8300SX)
1237 {
1238 /* Constant operands need the same number of processor
1239 states as register operands. Although we could try to
f40751dd 1240 use a size-based cost for !speed, the lack of
beed8fc0
AO		 1241 of a mode makes the results very unpredictable. */
1242 *total = 0;
1243 return true;
1244 }
358a11bb 1245 if (-4 <= n && n <= 4)
08dca707
KH		 1246 {
1247 switch ((int) n)
1248 {
1249 case 0:
1250 *total = 0;
1251 return true;
1252 case 1:
1253 case 2:
1254 case -1:
1255 case -2:
1256 *total = 0 + (outer_code == SET);
1257 return true;
1258 case 4:
1259 case -4:
1260 if (TARGET_H8300H || TARGET_H8300S)
1261 *total = 0 + (outer_code == SET);
1262 else
1263 *total = 1;
1264 return true;
1265 }
1266 }
1267 *total = 1;
1268 return true;
1269 }
1270
1271 case CONST:
1272 case LABEL_REF:
1273 case SYMBOL_REF:
beed8fc0
AO		 1274 if (TARGET_H8300SX)
1275 {
1276 /* See comment for CONST_INT. */
1277 *total = 0;
1278 return true;
1279 }
08dca707
KH		 1280 *total = 3;
1281 return true;
1282
1283 case CONST_DOUBLE:
1284 *total = 20;
1285 return true;
1286
f90b7a5a
PB		 1287 case COMPARE:
1288 if (XEXP (x, 1) == const0_rtx)
1289 *total = 0;
1290 return false;
1291
3c50106f 1292 case AND:
beed8fc0
AO		 1293 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
1294 || !h8300_src_operand (XEXP (x, 1), VOIDmode))
1295 return false;
3c50106f
RH		 1296 *total = COSTS_N_INSNS (h8300_and_costs (x));
1297 return true;
1298
1299 /* We say that MOD and DIV are so expensive because otherwise we'll
1300 generate some really horrible code for division of a power of two. */
1301 case MOD:
1302 case DIV:
beed8fc0
AO		 1303 case UMOD:
1304 case UDIV:
1305 if (TARGET_H8300SX)
1306 switch (GET_MODE (x))
1307 {
1308 case QImode:
1309 case HImode:
f40751dd 1310 *total = COSTS_N_INSNS (!speed ? 4 : 10);
beed8fc0
AO		 1311 return false;
1312
1313 case SImode:
f40751dd 1314 *total = COSTS_N_INSNS (!speed ? 4 : 18);
beed8fc0
AO		 1315 return false;
1316
1317 default:
1318 break;
1319 }
1320 *total = COSTS_N_INSNS (12);
3c50106f
RH		 1321 return true;
1322
1323 case MULT:
beed8fc0
AO		 1324 if (TARGET_H8300SX)
1325 switch (GET_MODE (x))
1326 {
1327 case QImode:
1328 case HImode:
1329 *total = COSTS_N_INSNS (2);
1330 return false;
1331
1332 case SImode:
1333 *total = COSTS_N_INSNS (5);
1334 return false;
1335
1336 default:
1337 break;
1338 }
1339 *total = COSTS_N_INSNS (4);
3c50106f
RH		 1340 return true;
1341
1342 case ASHIFT:
1343 case ASHIFTRT:
1344 case LSHIFTRT:
beed8fc0
AO		 1345 if (h8sx_binary_shift_operator (x, VOIDmode))
1346 {
1347 *total = COSTS_N_INSNS (2);
1348 return false;
1349 }
1350 else if (h8sx_unary_shift_operator (x, VOIDmode))
1351 {
1352 *total = COSTS_N_INSNS (1);
1353 return false;
1354 }
3c50106f
RH		 1355 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1356 return true;
1357
1358 case ROTATE:
1359 case ROTATERT:
1360 if (GET_MODE (x) == HImode)
1361 *total = 2;
1362 else
1363 *total = 8;
1364 return true;
1365
1366 default:
beed8fc0
AO		 1367 *total = COSTS_N_INSNS (1);
1368 return false;
3c50106f
RH		 1369 }
1370}
48837e29 1371\f
07aae5c2
SC		 1372/* Documentation for the machine specific operand escapes:
1373
48837e29
DE		 1374 'E' like s but negative.
1375 'F' like t but negative.
1376 'G' constant just the negative
15dc331e
JL		 1377 'R' print operand as a byte:8 address if appropriate, else fall back to
1378 'X' handling.
48837e29 1379 'S' print operand as a long word
07aae5c2 1380 'T' print operand as a word
48837e29
DE		 1381 'V' find the set bit, and print its number.
1382 'W' find the clear bit, and print its number.
1383 'X' print operand as a byte
07aae5c2 1384 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
15dc331e 1385 If this operand isn't a register, fall back to 'R' handling.
48837e29 1386 'Z' print int & 7.
b059c02a 1387 'c' print the opcode corresponding to rtl
da55315a 1388 'e' first word of 32-bit value - if reg, then least reg. if mem
48837e29 1389 then least. if const then most sig word
da55315a 1390 'f' second word of 32-bit value - if reg, then biggest reg. if mem
48837e29 1391 then +2. if const then least sig word
07aae5c2
SC		 1392 'j' print operand as condition code.
1393 'k' print operand as reverse condition code.
beed8fc0
AO		 1394 'm' convert an integer operand to a size suffix (.b, .w or .l)
1395 'o' print an integer without a leading '#'
da55315a
KH		 1396 's' print as low byte of 16-bit value
1397 't' print as high byte of 16-bit value
1398 'w' print as low byte of 32-bit value
1399 'x' print as 2nd byte of 32-bit value
1400 'y' print as 3rd byte of 32-bit value
1401 'z' print as msb of 32-bit value
48837e29 1402*/
07aae5c2
SC		 1403
1404/* Return assembly language string which identifies a comparison type. */
1405
441d04c6 1406static const char *
cb713a8d 1407cond_string (enum rtx_code code)
07aae5c2
SC		 1408{
1409 switch (code)
1410 {
1411 case NE:
1412 return "ne";
1413 case EQ:
1414 return "eq";
1415 case GE:
1416 return "ge";
1417 case GT:
1418 return "gt";
1419 case LE:
1420 return "le";
1421 case LT:
1422 return "lt";
1423 case GEU:
1424 return "hs";
1425 case GTU:
1426 return "hi";
1427 case LEU:
1428 return "ls";
1429 case LTU:
1430 return "lo";
1431 default:
8c440872 1432 gcc_unreachable ();
07aae5c2
SC		 1433 }
1434}
1435
1436/* Print operand X using operand code CODE to assembly language output file
1437 FILE. */
1438
88cb339e
N		 1439static void
1440h8300_print_operand (FILE *file, rtx x, int code)
07aae5c2 1441{
269c14e1 1442 /* This is used for communication between codes V,W,Z and Y. */
07aae5c2
SC		 1443 static int bitint;
1444
1445 switch (code)
1446 {
f46b8378
SKS		 1447 case 'C':
1448 if (h8300_constant_length (x) == 2)
1449 fprintf (file, ":16");
1450 else
1451 fprintf (file, ":32");
1452 return;
48837e29
DE		 1453 case 'E':
1454 switch (GET_CODE (x))
1455 {
1456 case REG:
1457 fprintf (file, "%sl", names_big[REGNO (x)]);
1458 break;
1459 case CONST_INT:
b47900aa 1460 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
48837e29
DE		 1461 break;
1462 default:
8c440872 1463 gcc_unreachable ();
48837e29
DE		 1464 }
1465 break;
1466 case 'F':
1467 switch (GET_CODE (x))
1468 {
1469 case REG:
1470 fprintf (file, "%sh", names_big[REGNO (x)]);
1471 break;
1472 case CONST_INT:
b47900aa 1473 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
48837e29
DE		 1474 break;
1475 default:
8c440872 1476 gcc_unreachable ();
48837e29
DE		 1477 }
1478 break;
07aae5c2 1479 case 'G':
8c440872 1480 gcc_assert (GET_CODE (x) == CONST_INT);
b47900aa 1481 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
07aae5c2 1482 break;
48837e29
DE		 1483 case 'S':
1484 if (GET_CODE (x) == REG)
1485 fprintf (file, "%s", names_extended[REGNO (x)]);
07aae5c2 1486 else
48837e29 1487 goto def;
07aae5c2 1488 break;
48837e29
DE		 1489 case 'T':
1490 if (GET_CODE (x) == REG)
1491 fprintf (file, "%s", names_big[REGNO (x)]);
07aae5c2 1492 else
48837e29 1493 goto def;
07aae5c2 1494 break;
48837e29 1495 case 'V':
0f6b820c
KP		 1496 bitint = (INTVAL (x) & 0xffff);
1497 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1)
1498 bitint = exact_log2 (bitint & 0xff);
1499 else
1500 bitint = exact_log2 ((bitint >> 8) & 0xff);
8c440872 1501 gcc_assert (bitint >= 0);
4d4d89e2 1502 fprintf (file, "#%d", bitint);
07aae5c2 1503 break;
48837e29 1504 case 'W':
0f6b820c
KP		 1505 bitint = ((~INTVAL (x)) & 0xffff);
1506 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 )
1507 bitint = exact_log2 (bitint & 0xff);
1508 else
1509 bitint = (exact_log2 ((bitint >> 8) & 0xff));
8c440872 1510 gcc_assert (bitint >= 0);
4d4d89e2 1511 fprintf (file, "#%d", bitint);
07aae5c2 1512 break;
15dc331e 1513 case 'R':
48837e29
DE		 1514 case 'X':
1515 if (GET_CODE (x) == REG)
1516 fprintf (file, "%s", byte_reg (x, 0));
1517 else
1518 goto def;
1519 break;
1520 case 'Y':
8c440872 1521 gcc_assert (bitint >= 0);
48837e29
DE		 1522 if (GET_CODE (x) == REG)
1523 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1524 else
88cb339e 1525 h8300_print_operand (file, x, 'R');
48837e29
DE		 1526 bitint = -1;
1527 break;
1528 case 'Z':
1529 bitint = INTVAL (x);
07aae5c2
SC		 1530 fprintf (file, "#%d", bitint & 7);
1531 break;
b059c02a
KH		 1532 case 'c':
1533 switch (GET_CODE (x))
1534 {
1535 case IOR:
1536 fprintf (file, "or");
1537 break;
1538 case XOR:
1539 fprintf (file, "xor");
1540 break;
5abfd1af
KH		 1541 case AND:
1542 fprintf (file, "and");
1543 break;
b059c02a
KH		 1544 default:
1545 break;
1546 }
1547 break;
07aae5c2
SC		 1548 case 'e':
1549 switch (GET_CODE (x))
1550 {
1551 case REG:
48837e29
DE		 1552 if (TARGET_H8300)
1553 fprintf (file, "%s", names_big[REGNO (x)]);
1554 else
1555 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
07aae5c2
SC		 1556 break;
1557 case MEM:
88cb339e 1558 h8300_print_operand (file, x, 0);
07aae5c2
SC		 1559 break;
1560 case CONST_INT:
b47900aa 1561 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
07aae5c2 1562 break;
808fbfac
JL		 1563 case CONST_DOUBLE:
1564 {
1565 long val;
1566 REAL_VALUE_TYPE rv;
1567 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1568 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
441d04c6 1569 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
808fbfac
JL		 1570 break;
1571 }
07aae5c2 1572 default:
8c440872 1573 gcc_unreachable ();
07aae5c2
SC		 1574 break;
1575 }
1576 break;
07aae5c2
SC		 1577 case 'f':
1578 switch (GET_CODE (x))
1579 {
1580 case REG:
48837e29
DE		 1581 if (TARGET_H8300)
1582 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1583 else
1584 fprintf (file, "%s", names_big[REGNO (x)]);
07aae5c2 1585 break;
07aae5c2 1586 case MEM:
b72f00af 1587 x = adjust_address (x, HImode, 2);
88cb339e 1588 h8300_print_operand (file, x, 0);
07aae5c2 1589 break;
07aae5c2 1590 case CONST_INT:
b47900aa 1591 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
07aae5c2 1592 break;
808fbfac
JL		 1593 case CONST_DOUBLE:
1594 {
1595 long val;
1596 REAL_VALUE_TYPE rv;
1597 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1598 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
441d04c6 1599 fprintf (file, "#%ld", (val & 0xffff));
808fbfac
JL		 1600 break;
1601 }
07aae5c2 1602 default:
8c440872 1603 gcc_unreachable ();
07aae5c2
SC		 1604 }
1605 break;
07aae5c2 1606 case 'j':
761c70aa 1607 fputs (cond_string (GET_CODE (x)), file);
07aae5c2 1608 break;
07aae5c2 1609 case 'k':
761c70aa 1610 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
07aae5c2 1611 break;
beed8fc0 1612 case 'm':
8c440872
NS		 1613 gcc_assert (GET_CODE (x) == CONST_INT);
1614 switch (INTVAL (x))
1615 {
1616 case 1:
1617 fputs (".b", file);
1618 break;
1619
1620 case 2:
1621 fputs (".w", file);
1622 break;
1623
1624 case 4:
1625 fputs (".l", file);
1626 break;
1627
1628 default:
1629 gcc_unreachable ();
1630 }
beed8fc0
AO		 1631 break;
1632 case 'o':
88cb339e 1633 h8300_print_operand_address (file, x);
beed8fc0 1634 break;
48837e29
DE		 1635 case 's':
1636 if (GET_CODE (x) == CONST_INT)
b47900aa 1637 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
48837e29
DE		 1638 else
1639 fprintf (file, "%s", byte_reg (x, 0));
1640 break;
1641 case 't':
1642 if (GET_CODE (x) == CONST_INT)
b47900aa 1643 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
48837e29
DE		 1644 else
1645 fprintf (file, "%s", byte_reg (x, 1));
1646 break;
48837e29
DE		 1647 case 'w':
1648 if (GET_CODE (x) == CONST_INT)
b47900aa 1649 fprintf (file, "#%ld", INTVAL (x) & 0xff);
48837e29 1650 else
a1616dd9
JL		 1651 fprintf (file, "%s",
1652 byte_reg (x, TARGET_H8300 ? 2 : 0));
48837e29
DE		 1653 break;
1654 case 'x':
1655 if (GET_CODE (x) == CONST_INT)
b47900aa 1656 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
48837e29 1657 else
a1616dd9
JL		 1658 fprintf (file, "%s",
1659 byte_reg (x, TARGET_H8300 ? 3 : 1));
48837e29
DE		 1660 break;
1661 case 'y':
1662 if (GET_CODE (x) == CONST_INT)
b47900aa 1663 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
48837e29
DE		 1664 else
1665 fprintf (file, "%s", byte_reg (x, 0));
1666 break;
1667 case 'z':
1668 if (GET_CODE (x) == CONST_INT)
b47900aa 1669 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
48837e29
DE		 1670 else
1671 fprintf (file, "%s", byte_reg (x, 1));
1672 break;
1673
07aae5c2 1674 default:
48837e29 1675 def:
07aae5c2
SC		 1676 switch (GET_CODE (x))
1677 {
1678 case REG:
48837e29
DE		 1679 switch (GET_MODE (x))
1680 {
1681 case QImode:
269c14e1 1682#if 0 /* Is it asm ("mov.b %0,r2l", ...) */
48837e29
DE		 1683 fprintf (file, "%s", byte_reg (x, 0));
1684#else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1685 fprintf (file, "%s", names_big[REGNO (x)]);
1686#endif
1687 break;
1688 case HImode:
1689 fprintf (file, "%s", names_big[REGNO (x)]);
1690 break;
1691 case SImode:
8977e8a7 1692 case SFmode:
48837e29
DE		 1693 fprintf (file, "%s", names_extended[REGNO (x)]);
1694 break;
1695 default:
8c440872 1696 gcc_unreachable ();
48837e29 1697 }
07aae5c2
SC		 1698 break;
1699
1700 case MEM:
87e4ee91
KH		 1701 {
1702 rtx addr = XEXP (x, 0);
1703
1704 fprintf (file, "@");
1705 output_address (addr);
1706
beed8fc0
AO		 1707 /* Add a length suffix to constant addresses. Although this
1708 is often unnecessary, it helps to avoid ambiguity in the
1709 syntax of mova. If we wrote an insn like:
1710
1711 mova/w.l @(1,@foo.b),er0
1712
1713 then .b would be considered part of the symbol name.
1714 Adding a length after foo will avoid this. */
1715 if (CONSTANT_P (addr))
1716 switch (code)
1717 {
1718 case 'R':
1719 /* Used for mov.b and bit operations. */
1720 if (h8300_eightbit_constant_address_p (addr))
1721 {
1722 fprintf (file, ":8");
1723 break;
1724 }
1725
1726 /* Fall through. We should not get here if we are
1727 processing bit operations on H8/300 or H8/300H
1728 because 'U' constraint does not allow bit
1729 operations on the tiny area on these machines. */
1730
1731 case 'X':
1732 case 'T':
1733 case 'S':
1734 if (h8300_constant_length (addr) == 2)
1735 fprintf (file, ":16");
1736 else
1737 fprintf (file, ":32");
1738 break;
1739 default:
1740 break;
1741 }
87e4ee91 1742 }
07aae5c2
SC		 1743 break;
1744
1745 case CONST_INT:
1746 case SYMBOL_REF:
1747 case CONST:
1748 case LABEL_REF:
1749 fprintf (file, "#");
88cb339e 1750 h8300_print_operand_address (file, x);
07aae5c2 1751 break;
808fbfac
JL		 1752 case CONST_DOUBLE:
1753 {
1754 long val;
1755 REAL_VALUE_TYPE rv;
1756 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1757 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
441d04c6 1758 fprintf (file, "#%ld", val);
808fbfac
JL		 1759 break;
1760 }
441d04c6
KG		 1761 default:
1762 break;
07aae5c2
SC		 1763 }
1764 }
1765}
1766
88cb339e
N		 1767/* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1768
1769static bool
1770h8300_print_operand_punct_valid_p (unsigned char code)
1771{
1772 return (code == '#');
1773}
1774
07aae5c2
SC		 1775/* Output assembly language output for the address ADDR to FILE. */
1776
88cb339e
N		 1777static void
1778h8300_print_operand_address (FILE *file, rtx addr)
07aae5c2 1779{
beed8fc0
AO		 1780 rtx index;
1781 int size;
1782
07aae5c2
SC		 1783 switch (GET_CODE (addr))
1784 {
1785 case REG:
48837e29 1786 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
07aae5c2
SC		 1787 break;
1788
1789 case PRE_DEC:
48837e29 1790 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
07aae5c2
SC		 1791 break;
1792
1793 case POST_INC:
48837e29 1794 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
07aae5c2
SC		 1795 break;
1796
beed8fc0
AO		 1797 case PRE_INC:
1798 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1799 break;
1800
1801 case POST_DEC:
1802 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
1803 break;
1804
07aae5c2
SC		 1805 case PLUS:
1806 fprintf (file, "(");
beed8fc0
AO		 1807
1808 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
1809 if (GET_CODE (index) == REG)
07aae5c2
SC		 1810 {
1811 /* reg,foo */
88cb339e 1812 h8300_print_operand_address (file, XEXP (addr, 1));
07aae5c2 1813 fprintf (file, ",");
beed8fc0
AO		 1814 switch (size)
1815 {
1816 case 0:
88cb339e 1817 h8300_print_operand_address (file, index);
beed8fc0
AO		 1818 break;
1819
1820 case 1:
88cb339e 1821 h8300_print_operand (file, index, 'X');
beed8fc0
AO		 1822 fputs (".b", file);
1823 break;
1824
1825 case 2:
88cb339e 1826 h8300_print_operand (file, index, 'T');
beed8fc0
AO		 1827 fputs (".w", file);
1828 break;
1829
1830 case 4:
88cb339e 1831 h8300_print_operand (file, index, 'S');
beed8fc0
AO		 1832 fputs (".l", file);
1833 break;
1834 }
88cb339e 1835 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
07aae5c2
SC		 1836 }
1837 else
1838 {
1839 /* foo+k */
88cb339e 1840 h8300_print_operand_address (file, XEXP (addr, 0));
07aae5c2 1841 fprintf (file, "+");
88cb339e 1842 h8300_print_operand_address (file, XEXP (addr, 1));
07aae5c2
SC		 1843 }
1844 fprintf (file, ")");
1845 break;
1846
1847 case CONST_INT:
48837e29 1848 {
da55315a 1849 /* Since the H8/300 only has 16-bit pointers, negative values are also
48837e29
DE		 1850 those >= 32768. This happens for example with pointer minus a
1851 constant. We don't want to turn (char *p - 2) into
1852 (char *p + 65534) because loop unrolling can build upon this
1853 (IE: char *p + 131068). */
1854 int n = INTVAL (addr);
1855 if (TARGET_H8300)
1856 n = (int) (short) n;
7a770d8b 1857 fprintf (file, "%d", n);
48837e29
DE		 1858 break;
1859 }
07aae5c2
SC		 1860
1861 default:
1862 output_addr_const (file, addr);
1863 break;
1864 }
1865}
1866\f
07aae5c2
SC		 1867/* Output all insn addresses and their sizes into the assembly language
1868 output file. This is helpful for debugging whether the length attributes
1869 in the md file are correct. This is not meant to be a user selectable
1870 option. */
1871
1872void
cb713a8d
KH		 1873final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1874 int num_operands ATTRIBUTE_UNUSED)
07aae5c2
SC		 1875{
1876 /* This holds the last insn address. */
1877 static int last_insn_address = 0;
1878
7798db98 1879 const int uid = INSN_UID (insn);
07aae5c2
SC		 1880
1881 if (TARGET_ADDRESSES)
1882 {
9d98a694
AO		 1883 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1884 INSN_ADDRESSES (uid) - last_insn_address);
1885 last_insn_address = INSN_ADDRESSES (uid);
07aae5c2
SC		 1886 }
1887}
1888
48837e29
DE		 1889/* Prepare for an SI sized move. */
1890
1891int
1a793acf 1892h8300_expand_movsi (rtx operands[])
07aae5c2 1893{
48837e29
DE		 1894 rtx src = operands[1];
1895 rtx dst = operands[0];
1896 if (!reload_in_progress && !reload_completed)
1897 {
1898 if (!register_operand (dst, GET_MODE (dst)))
1899 {
1900 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1901 emit_move_insn (tmp, src);
1902 operands[1] = tmp;
1903 }
1904 }
1905 return 0;
1906}
1907
7b5cbb57
AS		 1908/* Given FROM and TO register numbers, say whether this elimination is allowed.
1909 Frame pointer elimination is automatically handled.
1910
1911 For the h8300, if frame pointer elimination is being done, we would like to
1912 convert ap and rp into sp, not fp.
1913
1914 All other eliminations are valid. */
1915
1916static bool
1917h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
1918{
1919 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
1920}
1921
5efd84c5
NF		 1922/* Conditionally modify register usage based on target flags. */
1923
1924static void
1925h8300_conditional_register_usage (void)
1926{
1927 if (!TARGET_MAC)
1928 fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1;
1929}
1930
48837e29 1931/* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
07e4d94e
KH		 1932 Define the offset between two registers, one to be eliminated, and
1933 the other its replacement, at the start of a routine. */
07aae5c2 1934
48837e29 1935int
cb713a8d 1936h8300_initial_elimination_offset (int from, int to)
48837e29 1937{
d18ad191
KH		 1938 /* The number of bytes that the return address takes on the stack. */
1939 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
48837e29 1940
1807b726
KH		 1941 /* The number of bytes that the saved frame pointer takes on the stack. */
1942 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1943
1944 /* The number of bytes that the saved registers, excluding the frame
1945 pointer, take on the stack. */
1946 int saved_regs_size = 0;
48837e29 1947
1807b726
KH		 1948 /* The number of bytes that the locals takes on the stack. */
1949 int frame_size = round_frame_size (get_frame_size ());
48837e29 1950
1807b726 1951 int regno;
48837e29 1952
1807b726
KH		 1953 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1954 if (WORD_REG_USED (regno))
1955 saved_regs_size += UNITS_PER_WORD;
48837e29 1956
1807b726
KH		 1957 /* Adjust saved_regs_size because the above loop took the frame
1958 pointer int account. */
1959 saved_regs_size -= fp_size;
39ba95b5 1960
8c440872 1961 switch (to)
1807b726 1962 {
8c440872 1963 case HARD_FRAME_POINTER_REGNUM:
1807b726
KH		 1964 switch (from)
1965 {
1966 case ARG_POINTER_REGNUM:
1967 return pc_size + fp_size;
1968 case RETURN_ADDRESS_POINTER_REGNUM:
1969 return fp_size;
1970 case FRAME_POINTER_REGNUM:
1971 return -saved_regs_size;
1972 default:
8c440872 1973 gcc_unreachable ();
1807b726 1974 }
8c440872
NS		 1975 break;
1976 case STACK_POINTER_REGNUM:
1807b726
KH		 1977 switch (from)
1978 {
1979 case ARG_POINTER_REGNUM:
1980 return pc_size + saved_regs_size + frame_size;
1981 case RETURN_ADDRESS_POINTER_REGNUM:
1982 return saved_regs_size + frame_size;
1983 case FRAME_POINTER_REGNUM:
1984 return frame_size;
1985 default:
8c440872 1986 gcc_unreachable ();
1807b726 1987 }
8c440872
NS		 1988 break;
1989 default:
1990 gcc_unreachable ();
1807b726 1991 }
8c440872 1992 gcc_unreachable ();
48837e29
DE		 1993}
1994
e9eba255
KH		 1995/* Worker function for RETURN_ADDR_RTX. */
1996
1aae372e 1997rtx
cb713a8d 1998h8300_return_addr_rtx (int count, rtx frame)
1aae372e
JL		 1999{
2000 rtx ret;
2001
2002 if (count == 0)
2003 ret = gen_rtx_MEM (Pmode,
2004 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
2005 else if (flag_omit_frame_pointer)
2006 return (rtx) 0;
2007 else
2008 ret = gen_rtx_MEM (Pmode,
2009 memory_address (Pmode,
0a81f074
RS		 2010 plus_constant (Pmode, frame,
2011 UNITS_PER_WORD)));
1aae372e
JL		 2012 set_mem_alias_set (ret, get_frame_alias_set ());
2013 return ret;
2014}
2015
48837e29
DE		 2016/* Update the condition code from the insn. */
2017
441d04c6 2018void
cb713a8d 2019notice_update_cc (rtx body, rtx insn)
48837e29 2020{
d99c740f
KH		 2021 rtx set;
2022
48837e29
DE		 2023 switch (get_attr_cc (insn))
2024 {
2025 case CC_NONE:
269c14e1 2026 /* Insn does not affect CC at all. */
48837e29
DE		 2027 break;
2028
2029 case CC_NONE_0HIT:
269c14e1 2030 /* Insn does not change CC, but the 0'th operand has been changed. */
48837e29 2031 if (cc_status.value1 != 0
1ccbefce 2032 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
48837e29 2033 cc_status.value1 = 0;
d4d6d0ce
KH		 2034 if (cc_status.value2 != 0
2035 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
2036 cc_status.value2 = 0;
48837e29
DE		 2037 break;
2038
065bbfe6 2039 case CC_SET_ZN:
1ccbefce 2040 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
269c14e1
DE		 2041 The V flag is unusable. The C flag may or may not be known but
2042 that's ok because alter_cond will change tests to use EQ/NE. */
48837e29 2043 CC_STATUS_INIT;
269c14e1 2044 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
d99c740f
KH		 2045 set = single_set (insn);
2046 cc_status.value1 = SET_SRC (set);
2047 if (SET_DEST (set) != cc0_rtx)
2048 cc_status.value2 = SET_DEST (set);
48837e29
DE		 2049 break;
2050
065bbfe6 2051 case CC_SET_ZNV:
1ccbefce 2052 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
065bbfe6
JL		 2053 The C flag may or may not be known but that's ok because
2054 alter_cond will change tests to use EQ/NE. */
2055 CC_STATUS_INIT;
2056 cc_status.flags |= CC_NO_CARRY;
d99c740f
KH		 2057 set = single_set (insn);
2058 cc_status.value1 = SET_SRC (set);
2059 if (SET_DEST (set) != cc0_rtx)
c8fcf20c
KH		 2060 {
2061 /* If the destination is STRICT_LOW_PART, strip off
2062 STRICT_LOW_PART. */
2063 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
2064 cc_status.value2 = XEXP (SET_DEST (set), 0);
2065 else
2066 cc_status.value2 = SET_DEST (set);
2067 }
065bbfe6
JL		 2068 break;
2069
beed8fc0
AO		 2070 case CC_COMPARE:
2071 /* The insn is a compare instruction. */
2072 CC_STATUS_INIT;
2073 cc_status.value1 = SET_SRC (body);
2074 break;
2075
2076 case CC_CLOBBER:
2077 /* Insn doesn't leave CC in a usable state. */
2078 CC_STATUS_INIT;
2079 break;
2080 }
2081}
beed8fc0
AO		 2082\f
2083/* Given that X occurs in an address of the form (plus X constant),
2084 return the part of X that is expected to be a register. There are
2085 four kinds of addressing mode to recognize:
2086
2087 @(dd,Rn)
2088 @(dd,RnL.b)
2089 @(dd,Rn.w)
2090 @(dd,ERn.l)
2091
2092 If SIZE is nonnull, and the address is one of the last three forms,
2093 set *SIZE to the index multiplication factor. Set it to 0 for
2094 plain @(dd,Rn) addresses.
2095
2096 MODE is the mode of the value being accessed. It can be VOIDmode
2097 if the address is known to be valid, but its mode is unknown. */
2098
f52d97da 2099static rtx
beed8fc0
AO		 2100h8300_get_index (rtx x, enum machine_mode mode, int *size)
2101{
2102 int dummy, factor;
2103
2104 if (size == 0)
2105 size = &dummy;
2106
2107 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
2108 if (TARGET_H8300SX
2109 && factor <= 4
2110 && (mode == VOIDmode
2111 || GET_MODE_CLASS (mode) == MODE_INT
2112 || GET_MODE_CLASS (mode) == MODE_FLOAT))
2113 {
2114 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
2115 {
2116 /* When accessing byte-sized values, the index can be
2117 a zero-extended QImode or HImode register. */
2118 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
2119 return XEXP (x, 0);
2120 }
2121 else
2122 {
2123 /* We're looking for addresses of the form:
2124
2125 (mult X I)
2126 or (mult (zero_extend X) I)
2127
2128 where I is the size of the operand being accessed.
2129 The canonical form of the second expression is:
2130
2131 (and (mult (subreg X) I) J)
2132
2133 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2134 rtx index;
2135
2136 if (GET_CODE (x) == AND
2137 && GET_CODE (XEXP (x, 1)) == CONST_INT
2138 && (factor == 0
2139 || INTVAL (XEXP (x, 1)) == 0xff * factor
2140 || INTVAL (XEXP (x, 1)) == 0xffff * factor))
2141 {
2142 index = XEXP (x, 0);
2143 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
2144 }
2145 else
2146 {
2147 index = x;
2148 *size = 4;
2149 }
2150
2151 if (GET_CODE (index) == MULT
2152 && GET_CODE (XEXP (index, 1)) == CONST_INT
2153 && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
2154 return XEXP (index, 0);
2155 }
2156 }
2157 *size = 0;
2158 return x;
2159}
2160\f
f52d97da
AS		 2161/* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2162
2163 On the H8/300, the predecrement and postincrement address depend thus
2164 (the amount of decrement or increment being the length of the operand). */
2165
2166static bool
5bfed9a9
GJL		 2167h8300_mode_dependent_address_p (const_rtx addr,
2168 addr_space_t as ATTRIBUTE_UNUSED)
f52d97da
AS		 2169{
2170 if (GET_CODE (addr) == PLUS
2171 && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0))
2172 return true;
2173
2174 return false;
2175}
2176\f
beed8fc0
AO		 2177static const h8300_length_table addb_length_table =
2178{
2179 /* #xx Rs @aa @Rs @xx */
2180 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2181 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2182 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2183 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2184};
2185
2186static const h8300_length_table addw_length_table =
2187{
2188 /* #xx Rs @aa @Rs @xx */
2189 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2190 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2191 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2192 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2193};
2194
2195static const h8300_length_table addl_length_table =
2196{
2197 /* #xx Rs @aa @Rs @xx */
2198 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2199 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2200 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2201 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2202};
2203
2204#define logicb_length_table addb_length_table
2205#define logicw_length_table addw_length_table
2206
2207static const h8300_length_table logicl_length_table =
2208{
2209 /* #xx Rs @aa @Rs @xx */
2210 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2211 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2212 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2213 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2214};
2215
2216static const h8300_length_table movb_length_table =
2217{
2218 /* #xx Rs @aa @Rs @xx */
2219 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2220 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2221 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2222 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2223};
2224
2225#define movw_length_table movb_length_table
2226
2227static const h8300_length_table movl_length_table =
2228{
2229 /* #xx Rs @aa @Rs @xx */
2230 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2231 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2232 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2233 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2234};
2235
2236/* Return the size of the given address or displacement constant. */
2237
2238static unsigned int
2239h8300_constant_length (rtx constant)
2240{
2241 /* Check for (@d:16,Reg). */
2242 if (GET_CODE (constant) == CONST_INT
2243 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
2244 return 2;
2245
2246 /* Check for (@d:16,Reg) in cases where the displacement is
2247 an absolute address. */
2248 if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
2249 return 2;
2250
2251 return 4;
2252}
2253
2254/* Return the size of a displacement field in address ADDR, which should
2255 have the form (plus X constant). SIZE is the number of bytes being
2256 accessed. */
2257
2258static unsigned int
2259h8300_displacement_length (rtx addr, int size)
2260{
2261 rtx offset;
2262
2263 offset = XEXP (addr, 1);
2264
2265 /* Check for @(d:2,Reg). */
2266 if (register_operand (XEXP (addr, 0), VOIDmode)
2267 && GET_CODE (offset) == CONST_INT
2268 && (INTVAL (offset) == size
2269 || INTVAL (offset) == size * 2
2270 || INTVAL (offset) == size * 3))
2271 return 0;
2272
2273 return h8300_constant_length (offset);
2274}
2275
0a2aaacc
KG		 2276/* Store the class of operand OP in *OPCLASS and return the length of any
2277 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
beed8fc0
AO		 2278 can be null if only the length is needed. */
2279
2280static unsigned int
0a2aaacc 2281h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
beed8fc0
AO		 2282{
2283 enum h8300_operand_class dummy;
2284
0a2aaacc
KG		 2285 if (opclass == 0)
2286 opclass = &dummy;
beed8fc0
AO		 2287
2288 if (CONSTANT_P (op))
2289 {
0a2aaacc 2290 *opclass = H8OP_IMMEDIATE;
beed8fc0
AO		 2291
2292 /* Byte-sized immediates are stored in the opcode fields. */
2293 if (size == 1)
2294 return 0;
2295
2296 /* If this is a 32-bit instruction, see whether the constant
2297 will fit into a 16-bit immediate field. */
2298 if (TARGET_H8300SX
2299 && size == 4
2300 && GET_CODE (op) == CONST_INT
2301 && IN_RANGE (INTVAL (op), 0, 0xffff))
2302 return 2;
2303
2304 return size;
2305 }
2306 else if (GET_CODE (op) == MEM)
2307 {
2308 op = XEXP (op, 0);
2309 if (CONSTANT_P (op))
2310 {
0a2aaacc 2311 *opclass = H8OP_MEM_ABSOLUTE;
beed8fc0
AO		 2312 return h8300_constant_length (op);
2313 }
2314 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
2315 {
0a2aaacc 2316 *opclass = H8OP_MEM_COMPLEX;
beed8fc0
AO		 2317 return h8300_displacement_length (op, size);
2318 }
2319 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
2320 {
0a2aaacc 2321 *opclass = H8OP_MEM_COMPLEX;
beed8fc0
AO		 2322 return 0;
2323 }
2324 else if (register_operand (op, VOIDmode))
2325 {
0a2aaacc 2326 *opclass = H8OP_MEM_BASE;
beed8fc0
AO		 2327 return 0;
2328 }
2329 }
8c440872 2330 gcc_assert (register_operand (op, VOIDmode));
0a2aaacc 2331 *opclass = H8OP_REGISTER;
8c440872 2332 return 0;
beed8fc0
AO		 2333}
2334
2335/* Return the length of the instruction described by TABLE given that
2336 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2337 and OP2 must be an h8300_src_operand. */
2338
2339static unsigned int
2340h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
2341{
2342 enum h8300_operand_class op1_class, op2_class;
2343 unsigned int size, immediate_length;
2344
2345 size = GET_MODE_SIZE (GET_MODE (op1));
2346 immediate_length = (h8300_classify_operand (op1, size, &op1_class)
2347 + h8300_classify_operand (op2, size, &op2_class));
2348 return immediate_length + (*table)[op1_class - 1][op2_class];
2349}
2350
2351/* Return the length of a unary instruction such as neg or not given that
2352 its operand is OP. */
2353
2354unsigned int
2355h8300_unary_length (rtx op)
2356{
0a2aaacc 2357 enum h8300_operand_class opclass;
beed8fc0
AO		 2358 unsigned int size, operand_length;
2359
2360 size = GET_MODE_SIZE (GET_MODE (op));
0a2aaacc
KG		 2361 operand_length = h8300_classify_operand (op, size, &opclass);
2362 switch (opclass)
beed8fc0
AO		 2363 {
2364 case H8OP_REGISTER:
2365 return 2;
2366
2367 case H8OP_MEM_BASE:
2368 return (size == 4 ? 6 : 4);
2369
2370 case H8OP_MEM_ABSOLUTE:
2371 return operand_length + (size == 4 ? 6 : 4);
2372
2373 case H8OP_MEM_COMPLEX:
2374 return operand_length + 6;
2375
2376 default:
8c440872 2377 gcc_unreachable ();
beed8fc0
AO		 2378 }
2379}
2380
2381/* Likewise short immediate instructions such as add.w #xx:3,OP. */
2382
2383static unsigned int
2384h8300_short_immediate_length (rtx op)
2385{
0a2aaacc 2386 enum h8300_operand_class opclass;
beed8fc0
AO		 2387 unsigned int size, operand_length;
2388
2389 size = GET_MODE_SIZE (GET_MODE (op));
0a2aaacc 2390 operand_length = h8300_classify_operand (op, size, &opclass);
beed8fc0 2391
0a2aaacc 2392 switch (opclass)
beed8fc0
AO		 2393 {
2394 case H8OP_REGISTER:
2395 return 2;
2396
2397 case H8OP_MEM_BASE:
2398 case H8OP_MEM_ABSOLUTE:
2399 case H8OP_MEM_COMPLEX:
2400 return 4 + operand_length;
2401
2402 default:
8c440872 2403 gcc_unreachable ();
beed8fc0
AO		 2404 }
2405}
2406
2407/* Likewise bitfield load and store instructions. */
48837e29 2408
beed8fc0
AO		 2409static unsigned int
2410h8300_bitfield_length (rtx op, rtx op2)
2411{
0a2aaacc 2412 enum h8300_operand_class opclass;
beed8fc0
AO		 2413 unsigned int size, operand_length;
2414
2415 if (GET_CODE (op) == REG)
2416 op = op2;
8c440872 2417 gcc_assert (GET_CODE (op) != REG);
beed8fc0
AO		 2418
2419 size = GET_MODE_SIZE (GET_MODE (op));
0a2aaacc 2420 operand_length = h8300_classify_operand (op, size, &opclass);
beed8fc0 2421
0a2aaacc 2422 switch (opclass)
beed8fc0
AO		 2423 {
2424 case H8OP_MEM_BASE:
2425 case H8OP_MEM_ABSOLUTE:
2426 case H8OP_MEM_COMPLEX:
2427 return 4 + operand_length;
2428
2429 default:
8c440872 2430 gcc_unreachable ();
07aae5c2 2431 }
48837e29
DE		 2432}
2433
beed8fc0 2434/* Calculate the length of general binary instruction INSN using TABLE. */
8ccf5d5f 2435
beed8fc0
AO		 2436static unsigned int
2437h8300_binary_length (rtx insn, const h8300_length_table *table)
8ccf5d5f 2438{
beed8fc0
AO		 2439 rtx set;
2440
2441 set = single_set (insn);
8c440872 2442 gcc_assert (set);
beed8fc0
AO		 2443
2444 if (BINARY_P (SET_SRC (set)))
2445 return h8300_length_from_table (XEXP (SET_SRC (set), 0),
2446 XEXP (SET_SRC (set), 1), table);
beed8fc0 2447 else
8c440872
NS		 2448 {
2449 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
2450 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
2451 XEXP (XEXP (SET_SRC (set), 1), 1),
2452 table);
2453 }
8ccf5d5f
KH		 2454}
2455
beed8fc0
AO		 2456/* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2457 memory reference and either (1) it has the form @(d:16,Rn) or
2458 (2) its address has the code given by INC_CODE. */
8ccf5d5f 2459
beed8fc0
AO		 2460static bool
2461h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
8ccf5d5f 2462{
beed8fc0
AO		 2463 rtx addr;
2464 unsigned int size;
2465
2466 if (GET_CODE (op) != MEM)
2467 return false;
2468
2469 addr = XEXP (op, 0);
2470 size = GET_MODE_SIZE (GET_MODE (op));
2471 if (size != 1 && size != 2)
2472 return false;
2473
2474 return (GET_CODE (addr) == inc_code
2475 || (GET_CODE (addr) == PLUS
2476 && GET_CODE (XEXP (addr, 0)) == REG
2477 && h8300_displacement_length (addr, size) == 2));
8ccf5d5f
KH		 2478}
2479
beed8fc0
AO		 2480/* Calculate the length of move instruction INSN using the given length
2481 table. Although the tables are correct for most cases, there is some
2482 irregularity in the length of mov.b and mov.w. The following forms:
8ccf5d5f 2483
beed8fc0
AO		 2484 mov @ERs+, Rd
2485 mov @(d:16,ERs), Rd
2486 mov Rs, @-ERd
2487 mov Rs, @(d:16,ERd)
2488
2489 are two bytes shorter than most other "mov Rs, @complex" or
2490 "mov @complex,Rd" combinations. */
2491
2492static unsigned int
2493h8300_move_length (rtx *operands, const h8300_length_table *table)
8ccf5d5f 2494{
beed8fc0
AO		 2495 unsigned int size;
2496
2497 size = h8300_length_from_table (operands[0], operands[1], table);
2498 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
2499 size -= 2;
2500 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
2501 size -= 2;
2502 return size;
8ccf5d5f
KH		 2503}
2504
beed8fc0
AO		 2505/* Return the length of a mova instruction with the given operands.
2506 DEST is the register destination, SRC is the source address and
2507 OFFSET is the 16-bit or 32-bit displacement. */
2873836b 2508
beed8fc0
AO		 2509static unsigned int
2510h8300_mova_length (rtx dest, rtx src, rtx offset)
2873836b 2511{
beed8fc0
AO		 2512 unsigned int size;
2513
2514 size = (2
2515 + h8300_constant_length (offset)
2516 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
2517 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
2518 size += 2;
2519 return size;
2873836b
KH		 2520}
2521
beed8fc0
AO		 2522/* Compute the length of INSN based on its length_table attribute.
2523 OPERANDS is the array of its operands. */
2873836b 2524
beed8fc0
AO		 2525unsigned int
2526h8300_insn_length_from_table (rtx insn, rtx * operands)
2873836b 2527{
beed8fc0
AO		 2528 switch (get_attr_length_table (insn))
2529 {
2530 case LENGTH_TABLE_NONE:
8c440872 2531 gcc_unreachable ();
beed8fc0
AO		 2532
2533 case LENGTH_TABLE_ADDB:
2534 return h8300_binary_length (insn, &addb_length_table);
2535
2536 case LENGTH_TABLE_ADDW:
2537 return h8300_binary_length (insn, &addw_length_table);
2538
2539 case LENGTH_TABLE_ADDL:
2540 return h8300_binary_length (insn, &addl_length_table);
2541
2542 case LENGTH_TABLE_LOGICB:
2543 return h8300_binary_length (insn, &logicb_length_table);
2544
2545 case LENGTH_TABLE_MOVB:
2546 return h8300_move_length (operands, &movb_length_table);
2547
2548 case LENGTH_TABLE_MOVW:
2549 return h8300_move_length (operands, &movw_length_table);
2550
2551 case LENGTH_TABLE_MOVL:
2552 return h8300_move_length (operands, &movl_length_table);
2553
2554 case LENGTH_TABLE_MOVA:
2555 return h8300_mova_length (operands[0], operands[1], operands[2]);
2556
2557 case LENGTH_TABLE_MOVA_ZERO:
2558 return h8300_mova_length (operands[0], operands[1], const0_rtx);
2559
2560 case LENGTH_TABLE_UNARY:
2561 return h8300_unary_length (operands[0]);
2562
2563 case LENGTH_TABLE_MOV_IMM4:
2564 return 2 + h8300_classify_operand (operands[0], 0, 0);
2565
2566 case LENGTH_TABLE_SHORT_IMMEDIATE:
2567 return h8300_short_immediate_length (operands[0]);
2568
2569 case LENGTH_TABLE_BITFIELD:
2570 return h8300_bitfield_length (operands[0], operands[1]);
2571
2572 case LENGTH_TABLE_BITBRANCH:
2573 return h8300_bitfield_length (operands[1], operands[2]) - 2;
8c440872
NS		 2574
2575 default:
2576 gcc_unreachable ();
beed8fc0 2577 }
2873836b
KH		 2578}
2579
beed8fc0
AO		 2580/* Return true if LHS and RHS are memory references that can be mapped
2581 to the same h8sx assembly operand. LHS appears as the destination of
2582 an instruction and RHS appears as a source.
f9d2de4d 2583
beed8fc0
AO		 2584 Three cases are allowed:
2585
2586 - RHS is @+Rn or @-Rn, LHS is @Rn
2587 - RHS is @Rn, LHS is @Rn+ or @Rn-
2588 - RHS and LHS have the same address and neither has side effects. */
2589
2590bool
2591h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
f9d2de4d 2592{
beed8fc0
AO		 2593 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
2594 {
2595 rhs = XEXP (rhs, 0);
2596 lhs = XEXP (lhs, 0);
2597
2598 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
2599 return rtx_equal_p (XEXP (rhs, 0), lhs);
2600
2601 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
2602 return rtx_equal_p (rhs, XEXP (lhs, 0));
2603
2604 if (rtx_equal_p (rhs, lhs))
2605 return true;
2606 }
2607 return false;
f9d2de4d
KH		 2608}
2609
beed8fc0
AO		 2610/* Return true if OPERANDS[1] can be mapped to the same assembly
2611 operand as OPERANDS[0]. */
f9d2de4d 2612
beed8fc0
AO		 2613bool
2614h8300_operands_match_p (rtx *operands)
f9d2de4d 2615{
beed8fc0
AO		 2616 if (register_operand (operands[0], VOIDmode)
2617 && register_operand (operands[1], VOIDmode))
2618 return true;
f9d2de4d 2619
beed8fc0
AO		 2620 if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
2621 return true;
2622
2623 return false;
f9d2de4d 2624}
beed8fc0
AO		 2625\f
2626/* Try using movmd to move LENGTH bytes from memory region SRC to memory
2627 region DEST. The two regions do not overlap and have the common
2628 alignment given by ALIGNMENT. Return true on success.
717d8b71 2629
beed8fc0
AO		 2630 Using movmd for variable-length moves seems to involve some
2631 complex trade-offs. For instance:
b059c02a 2632
beed8fc0
AO		 2633 - Preparing for a movmd instruction is similar to preparing
2634 for a memcpy. The main difference is that the arguments
2635 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2636
2637 - Since movmd clobbers the frame pointer, we need to save
2638 and restore it somehow when frame_pointer_needed. This can
2639 sometimes make movmd sequences longer than calls to memcpy().
2640
2641 - The counter register is 16 bits, so the instruction is only
2642 suitable for variable-length moves when sizeof (size_t) == 2.
2643 That's only true in normal mode.
2644
2645 - We will often lack static alignment information. Falling back
2646 on movmd.b would likely be slower than calling memcpy(), at least
2647 for big moves.
2648
2649 This function therefore only uses movmd when the length is a
2650 known constant, and only then if -fomit-frame-pointer is in
2651 effect or if we're not optimizing for size.
2652
2653 At the moment the function uses movmd for all in-range constants,
2654 but it might be better to fall back on memcpy() for large moves
2655 if ALIGNMENT == 1. */
2656
2657bool
2658h8sx_emit_movmd (rtx dest, rtx src, rtx length,
2659 HOST_WIDE_INT alignment)
b059c02a 2660{
beed8fc0
AO		 2661 if (!flag_omit_frame_pointer && optimize_size)
2662 return false;
b059c02a 2663
beed8fc0
AO		 2664 if (GET_CODE (length) == CONST_INT)
2665 {
2666 rtx dest_reg, src_reg, first_dest, first_src;
2667 HOST_WIDE_INT n;
2668 int factor;
2669
2670 /* Use movmd.l if the alignment allows it, otherwise fall back
2671 on movmd.b. */
2672 factor = (alignment >= 2 ? 4 : 1);
2673
2674 /* Make sure the length is within range. We can handle counter
2675 values up to 65536, although HImode truncation will make
2676 the count appear negative in rtl dumps. */
2677 n = INTVAL (length);
2678 if (n <= 0 || n / factor > 65536)
2679 return false;
2680
2681 /* Create temporary registers for the source and destination
2682 pointers. Initialize them to the start of each region. */
2683 dest_reg = copy_addr_to_reg (XEXP (dest, 0));
2684 src_reg = copy_addr_to_reg (XEXP (src, 0));
2685
2686 /* Create references to the movmd source and destination blocks. */
2687 first_dest = replace_equiv_address (dest, dest_reg);
2688 first_src = replace_equiv_address (src, src_reg);
2689
f5541398
RS		 2690 set_mem_size (first_dest, n & -factor);
2691 set_mem_size (first_src, n & -factor);
beed8fc0
AO		 2692
2693 length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode));
2694 emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor)));
2695
2696 if ((n & -factor) != n)
2697 {
2698 /* Move SRC and DEST past the region we just copied.
2699 This is done to update the memory attributes. */
2700 dest = adjust_address (dest, BLKmode, n & -factor);
2701 src = adjust_address (src, BLKmode, n & -factor);
2702
2703 /* Replace the addresses with the source and destination
2704 registers, which movmd has left with the right values. */
2705 dest = replace_equiv_address (dest, dest_reg);
2706 src = replace_equiv_address (src, src_reg);
2707
2708 /* Mop up the left-over bytes. */
2709 if (n & 2)
2710 emit_move_insn (adjust_address (dest, HImode, 0),
2711 adjust_address (src, HImode, 0));
2712 if (n & 1)
2713 emit_move_insn (adjust_address (dest, QImode, n & 2),
2714 adjust_address (src, QImode, n & 2));
2715 }
2716 return true;
2717 }
2718 return false;
b059c02a
KH		 2719}
2720
beed8fc0 2721/* Move ADDR into er6 after pushing its old value onto the stack. */
48837e29 2722
beed8fc0
AO		 2723void
2724h8300_swap_into_er6 (rtx addr)
48837e29 2725{
8f1594b2
RH		 2726 rtx insn = push (HARD_FRAME_POINTER_REGNUM);
2727 if (frame_pointer_needed)
2728 add_reg_note (insn, REG_CFA_DEF_CFA,
0a81f074 2729 plus_constant (Pmode, gen_rtx_MEM (Pmode, stack_pointer_rtx),
8f1594b2
RH		 2730 2 * UNITS_PER_WORD));
2731 else
2732 add_reg_note (insn, REG_CFA_ADJUST_CFA,
2733 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
0a81f074 2734 plus_constant (Pmode, stack_pointer_rtx, 4)));
8f1594b2 2735
beed8fc0
AO		 2736 emit_move_insn (hard_frame_pointer_rtx, addr);
2737 if (REGNO (addr) == SP_REG)
2738 emit_move_insn (hard_frame_pointer_rtx,
0a81f074 2739 plus_constant (Pmode, hard_frame_pointer_rtx,
beed8fc0
AO		 2740 GET_MODE_SIZE (word_mode)));
2741}
07aae5c2 2742
beed8fc0
AO		 2743/* Move the current value of er6 into ADDR and pop its old value
2744 from the stack. */
2745
2746void
2747h8300_swap_out_of_er6 (rtx addr)
2748{
8f1594b2
RH		 2749 rtx insn;
2750
beed8fc0
AO		 2751 if (REGNO (addr) != SP_REG)
2752 emit_move_insn (addr, hard_frame_pointer_rtx);
8f1594b2
RH		 2753
2754 insn = pop (HARD_FRAME_POINTER_REGNUM);
2755 RTX_FRAME_RELATED_P (insn) = 1;
2756 if (frame_pointer_needed)
2757 add_reg_note (insn, REG_CFA_DEF_CFA,
0a81f074
RS		 2758 plus_constant (Pmode, hard_frame_pointer_rtx,
2759 2 * UNITS_PER_WORD));
8f1594b2
RH		 2760 else
2761 add_reg_note (insn, REG_CFA_ADJUST_CFA,
2762 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
0a81f074 2763 plus_constant (Pmode, stack_pointer_rtx, -4)));
07aae5c2 2764}
48837e29 2765\f
7948a9ea
KH		 2766/* Return the length of mov instruction. */
2767
2768unsigned int
2769compute_mov_length (rtx *operands)
2770{
2771 /* If the mov instruction involves a memory operand, we compute the
2772 length, assuming the largest addressing mode is used, and then
2773 adjust later in the function. Otherwise, we compute and return
2774 the exact length in one step. */
2775 enum machine_mode mode = GET_MODE (operands[0]);
2776 rtx dest = operands[0];
2777 rtx src = operands[1];
2778 rtx addr;
2779
2780 if (GET_CODE (src) == MEM)
2781 addr = XEXP (src, 0);
2782 else if (GET_CODE (dest) == MEM)
2783 addr = XEXP (dest, 0);
2784 else
2785 addr = NULL_RTX;
2786
2787 if (TARGET_H8300)
2788 {
2789 unsigned int base_length;
2790
2791 switch (mode)
2792 {
2793 case QImode:
2794 if (addr == NULL_RTX)
2795 return 2;
2796
2797 /* The eightbit addressing is available only in QImode, so
2798 go ahead and take care of it. */
2799 if (h8300_eightbit_constant_address_p (addr))
2800 return 2;
2801
2802 base_length = 4;
2803 break;
2804
2805 case HImode:
2806 if (addr == NULL_RTX)
2807 {
2808 if (REG_P (src))
2809 return 2;
2810
2811 if (src == const0_rtx)
2812 return 2;
2813
2814 return 4;
2815 }
2816
2817 base_length = 4;
2818 break;
2819
2820 case SImode:
2821 if (addr == NULL_RTX)
2822 {
2823 if (REG_P (src))
2824 return 4;
2825
2826 if (GET_CODE (src) == CONST_INT)
2827 {
2828 if (src == const0_rtx)
2829 return 4;
2830
2831 if ((INTVAL (src) & 0xffff) == 0)
2832 return 6;
2833
2834 if ((INTVAL (src) & 0xffff) == 0)
2835 return 6;
f5139cc5
KH		 2836
2837 if ((INTVAL (src) & 0xffff)
2838 == ((INTVAL (src) >> 16) & 0xffff))
2839 return 6;
7948a9ea
KH		 2840 }
2841 return 8;
2842 }
2843
2844 base_length = 8;
2845 break;
2846
2847 case SFmode:
2848 if (addr == NULL_RTX)
2849 {
2850 if (REG_P (src))
2851 return 4;
2852
ceaaaeab 2853 if (satisfies_constraint_G (src))
2c4a71b3
KH		 2854 return 4;
2855
81983b04 2856 return 8;
7948a9ea
KH		 2857 }
2858
2859 base_length = 8;
2860 break;
2861
2862 default:
8c440872 2863 gcc_unreachable ();
7948a9ea
KH		 2864 }
2865
2866 /* Adjust the length based on the addressing mode used.
2867 Specifically, we subtract the difference between the actual
2868 length and the longest one, which is @(d:16,Rs). For SImode
2869 and SFmode, we double the adjustment because two mov.w are
2870 used to do the job. */
2871
2872 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2873 if (GET_CODE (addr) == PRE_DEC
2874 || GET_CODE (addr) == POST_INC)
2875 {
2876 if (mode == QImode || mode == HImode)
2877 return base_length - 2;
2878 else
2879 /* In SImode and SFmode, we use two mov.w instructions, so
2a43945f 2880 double the adjustment. */
7948a9ea
KH		 2881 return base_length - 4;
2882 }
2883
2884 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2885 in SImode and SFmode, the second mov.w involves an address
2886 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2887 only 2 bytes. */
2888 if (GET_CODE (addr) == REG)
2889 return base_length - 2;
2890
2891 return base_length;
2892 }
2893 else
2894 {
2895 unsigned int base_length;
2896
2897 switch (mode)
2898 {
2899 case QImode:
2900 if (addr == NULL_RTX)
2901 return 2;
2902
2903 /* The eightbit addressing is available only in QImode, so
2904 go ahead and take care of it. */
2905 if (h8300_eightbit_constant_address_p (addr))
2906 return 2;
2907
2908 base_length = 8;
2909 break;
2910
2911 case HImode:
2912 if (addr == NULL_RTX)
2913 {
2914 if (REG_P (src))
2915 return 2;
2916
2917 if (src == const0_rtx)
2918 return 2;
2919
2920 return 4;
2921 }
2922
2923 base_length = 8;
2924 break;
2925
2926 case SImode:
2927 if (addr == NULL_RTX)
2928 {
2929 if (REG_P (src))
2930 {
2931 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2932 return 4;
2933 else
2934 return 2;
2935 }
2936
2937 if (GET_CODE (src) == CONST_INT)
2938 {
2939 int val = INTVAL (src);
2940
2941 if (val == 0)
2942 return 2;
2943
2944 if (val == (val & 0x00ff) || val == (val & 0xff00))
2945 return 4;
80e58519 2946
7948a9ea
KH		 2947 switch (val & 0xffffffff)
2948 {
2949 case 0xffffffff:
2950 case 0xfffffffe:
2951 case 0xfffffffc:
2952 case 0x0000ffff:
2953 case 0x0000fffe:
2954 case 0xffff0000:
2955 case 0xfffe0000:
2956 case 0x00010000:
2957 case 0x00020000:
2958 return 4;
2959 }
2960 }
2961 return 6;
2962 }
2963
2964 base_length = 10;
2965 break;
2966
2967 case SFmode:
2968 if (addr == NULL_RTX)
2969 {
2970 if (REG_P (src))
2971 return 2;
2972
ceaaaeab 2973 if (satisfies_constraint_G (src))
7948a9ea 2974 return 2;
2c4a71b3 2975
7948a9ea
KH		 2976 return 6;
2977 }
2978
2979 base_length = 10;
2980 break;
2981
2982 default:
8c440872 2983 gcc_unreachable ();
7948a9ea
KH		 2984 }
2985
2986 /* Adjust the length based on the addressing mode used.
2987 Specifically, we subtract the difference between the actual
2988 length and the longest one, which is @(d:24,ERs). */
2989
2990 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2991 if (GET_CODE (addr) == PRE_DEC
2992 || GET_CODE (addr) == POST_INC)
2993 return base_length - 6;
2994
2995 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2996 if (GET_CODE (addr) == REG)
2997 return base_length - 6;
2998
2999 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
3000 longest. */
3001 if (GET_CODE (addr) == PLUS
3002 && GET_CODE (XEXP (addr, 0)) == REG
3003 && GET_CODE (XEXP (addr, 1)) == CONST_INT
3004 && INTVAL (XEXP (addr, 1)) > -32768
3005 && INTVAL (XEXP (addr, 1)) < 32767)
3006 return base_length - 4;
3007
3008 /* @aa:16 is 4 bytes shorter than the longest. */
3009 if (h8300_tiny_constant_address_p (addr))
3010 return base_length - 4;
3011
3012 /* @aa:24 is 2 bytes shorter than the longest. */
3013 if (CONSTANT_P (addr))
3014 return base_length - 2;
3015
3016 return base_length;
3017 }
3018}
3019\f
e9eba255
KH		 3020/* Output an addition insn. */
3021
366a7b27 3022const char *
cb713a8d 3023output_plussi (rtx *operands)
7d6ac401
KH		 3024{
3025 enum machine_mode mode = GET_MODE (operands[0]);
3026
8c440872 3027 gcc_assert (mode == SImode);
7d6ac401
KH		 3028
3029 if (TARGET_H8300)
3030 {
cfedf91b
KH		 3031 if (GET_CODE (operands[2]) == REG)
3032 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3033
3034 if (GET_CODE (operands[2]) == CONST_INT)
3035 {
3036 HOST_WIDE_INT n = INTVAL (operands[2]);
3037
3038 if ((n & 0xffffff) == 0)
3039 return "add\t%z2,%z0";
3040 if ((n & 0xffff) == 0)
3041 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
3042 if ((n & 0xff) == 0)
3043 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3044 }
3045
3046 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
7d6ac401
KH		 3047 }
3048 else
3049 {
beed8fc0
AO		 3050 if (GET_CODE (operands[2]) == CONST_INT
3051 && register_operand (operands[1], VOIDmode))
7d6ac401
KH		 3052 {
3053 HOST_WIDE_INT intval = INTVAL (operands[2]);
3054
beed8fc0
AO		 3055 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3056 return "add.l\t%S2,%S0";
3057 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3058 return "sub.l\t%G2,%S0";
3059
7d6ac401
KH		 3060 /* See if we can finish with 2 bytes. */
3061
9ac7ebba 3062 switch ((unsigned int) intval & 0xffffffff)
7d6ac401
KH		 3063 {
3064 case 0x00000001:
3065 case 0x00000002:
3066 case 0x00000004:
3067 return "adds\t%2,%S0";
3068
3069 case 0xffffffff:
3070 case 0xfffffffe:
3071 case 0xfffffffc:
3072 return "subs\t%G2,%S0";
3073
3074 case 0x00010000:
3075 case 0x00020000:
3076 operands[2] = GEN_INT (intval >> 16);
3077 return "inc.w\t%2,%e0";
3078
3079 case 0xffff0000:
3080 case 0xfffe0000:
3081 operands[2] = GEN_INT (intval >> 16);
3082 return "dec.w\t%G2,%e0";
3083 }
3084
3085 /* See if we can finish with 4 bytes. */
3086 if ((intval & 0xffff) == 0)
3087 {
3088 operands[2] = GEN_INT (intval >> 16);
3089 return "add.w\t%2,%e0";
3090 }
3091 }
3092
beed8fc0
AO		 3093 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3094 {
3095 operands[2] = GEN_INT (-INTVAL (operands[2]));
3096 return "sub.l\t%S2,%S0";
3097 }
7d6ac401
KH		 3098 return "add.l\t%S2,%S0";
3099 }
3100}
3101
beed8fc0
AO		 3102/* ??? It would be much easier to add the h8sx stuff if a single function
3103 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
e9eba255
KH		 3104/* Compute the length of an addition insn. */
3105
7d6ac401 3106unsigned int
cb713a8d 3107compute_plussi_length (rtx *operands)
7d6ac401
KH		 3108{
3109 enum machine_mode mode = GET_MODE (operands[0]);
3110
8c440872 3111 gcc_assert (mode == SImode);
7d6ac401
KH		 3112
3113 if (TARGET_H8300)
3114 {
cfedf91b
KH		 3115 if (GET_CODE (operands[2]) == REG)
3116 return 6;
3117
3118 if (GET_CODE (operands[2]) == CONST_INT)
3119 {
3120 HOST_WIDE_INT n = INTVAL (operands[2]);
3121
3122 if ((n & 0xffffff) == 0)
3123 return 2;
3124 if ((n & 0xffff) == 0)
3125 return 4;
3126 if ((n & 0xff) == 0)
3127 return 6;
3128 }
3129
3130 return 8;
7d6ac401
KH		 3131 }
3132 else
3133 {
beed8fc0
AO		 3134 if (GET_CODE (operands[2]) == CONST_INT
3135 && register_operand (operands[1], VOIDmode))
7d6ac401
KH		 3136 {
3137 HOST_WIDE_INT intval = INTVAL (operands[2]);
3138
beed8fc0
AO		 3139 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3140 return 2;
3141 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3142 return 2;
3143
7d6ac401
KH		 3144 /* See if we can finish with 2 bytes. */
3145
9ac7ebba 3146 switch ((unsigned int) intval & 0xffffffff)
7d6ac401
KH		 3147 {
3148 case 0x00000001:
3149 case 0x00000002:
3150 case 0x00000004:
3151 return 2;
3152
3153 case 0xffffffff:
3154 case 0xfffffffe:
3155 case 0xfffffffc:
3156 return 2;
3157
3158 case 0x00010000:
3159 case 0x00020000:
3160 return 2;
3161
3162 case 0xffff0000:
3163 case 0xfffe0000:
3164 return 2;
3165 }
3166
3167 /* See if we can finish with 4 bytes. */
3168 if ((intval & 0xffff) == 0)
3169 return 4;
3170 }
3171
beed8fc0
AO		 3172 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3173 return h8300_length_from_table (operands[0],
3174 GEN_INT (-INTVAL (operands[2])),
3175 &addl_length_table);
3176 else
3177 return h8300_length_from_table (operands[0], operands[2],
3178 &addl_length_table);
7d6ac401
KH		 3179 return 6;
3180 }
3181}
3182
e9eba255
KH		 3183/* Compute which flag bits are valid after an addition insn. */
3184
9690aa8e 3185enum attr_cc
cb713a8d 3186compute_plussi_cc (rtx *operands)
7d6ac401
KH		 3187{
3188 enum machine_mode mode = GET_MODE (operands[0]);
3189
8c440872 3190 gcc_assert (mode == SImode);
7d6ac401
KH		 3191
3192 if (TARGET_H8300)
3193 {
cfedf91b 3194 return CC_CLOBBER;
7d6ac401
KH		 3195 }
3196 else
3197 {
beed8fc0
AO		 3198 if (GET_CODE (operands[2]) == CONST_INT
3199 && register_operand (operands[1], VOIDmode))
7d6ac401
KH		 3200 {
3201 HOST_WIDE_INT intval = INTVAL (operands[2]);
3202
beed8fc0
AO		 3203 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3204 return CC_SET_ZN;
3205 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3206 return CC_SET_ZN;
3207
7d6ac401
KH		 3208 /* See if we can finish with 2 bytes. */
3209
9ac7ebba 3210 switch ((unsigned int) intval & 0xffffffff)
7d6ac401
KH		 3211 {
3212 case 0x00000001:
3213 case 0x00000002:
3214 case 0x00000004:
3215 return CC_NONE_0HIT;
3216
3217 case 0xffffffff:
3218 case 0xfffffffe:
3219 case 0xfffffffc:
3220 return CC_NONE_0HIT;
3221
3222 case 0x00010000:
3223 case 0x00020000:
3224 return CC_CLOBBER;
3225
3226 case 0xffff0000:
3227 case 0xfffe0000:
3228 return CC_CLOBBER;
3229 }
3230
3231 /* See if we can finish with 4 bytes. */
3232 if ((intval & 0xffff) == 0)
3233 return CC_CLOBBER;
3234 }
3235
3236 return CC_SET_ZN;
3237 }
3238}
3239\f
e9eba255
KH		 3240/* Output a logical insn. */
3241
7d6ac401 3242const char *
cb713a8d 3243output_logical_op (enum machine_mode mode, rtx *operands)
366a7b27 3244{
b42cff6b
KH		 3245 /* Figure out the logical op that we need to perform. */
3246 enum rtx_code code = GET_CODE (operands[3]);
366a7b27 3247 /* Pretend that every byte is affected if both operands are registers. */
7798db98 3248 const unsigned HOST_WIDE_INT intval =
366a7b27 3249 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
beed8fc0
AO		 3250 /* Always use the full instruction if the
3251 first operand is in memory. It is better
3252 to use define_splits to generate the shorter
3253 sequence where valid. */
3254 && register_operand (operands[1], VOIDmode)
366a7b27
KH		 3255 ? INTVAL (operands[2]) : 0x55555555);
3256 /* The determinant of the algorithm. If we perform an AND, 0
3257 affects a bit. Otherwise, 1 affects a bit. */
7798db98 3258 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
f9ac2f95
KH		 3259 /* Break up DET into pieces. */
3260 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3261 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
c5e7ce43
KH		 3262 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3263 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
f9ac2f95
KH		 3264 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3265 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3266 int lower_half_easy_p = 0;
3267 int upper_half_easy_p = 0;
366a7b27
KH		 3268 /* The name of an insn. */
3269 const char *opname;
3270 char insn_buf[100];
3271
3272 switch (code)
3273 {
3274 case AND:
3275 opname = "and";
3276 break;
3277 case IOR:
3278 opname = "or";
3279 break;
3280 case XOR:
3281 opname = "xor";
3282 break;
3283 default:
8c440872 3284 gcc_unreachable ();
366a7b27
KH		 3285 }
3286
3287 switch (mode)
3288 {
3289 case HImode:
3290 /* First, see if we can finish with one insn. */
3291 if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 3292 && b0 != 0
3293 && b1 != 0)
366a7b27
KH		 3294 {
3295 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
3296 output_asm_insn (insn_buf, operands);
3297 }
3298 else
3299 {
3300 /* Take care of the lower byte. */
c5e7ce43 3301 if (b0 != 0)
366a7b27
KH		 3302 {
3303 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
3304 output_asm_insn (insn_buf, operands);
3305 }
3306 /* Take care of the upper byte. */
c5e7ce43 3307 if (b1 != 0)
366a7b27
KH		 3308 {
3309 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
3310 output_asm_insn (insn_buf, operands);
3311 }
3312 }
3313 break;
3314 case SImode:
f9ac2f95
KH		 3315 if (TARGET_H8300H || TARGET_H8300S)
3316 {
3317 /* Determine if the lower half can be taken care of in no more
3318 than two bytes. */
3319 lower_half_easy_p = (b0 == 0
3320 || b1 == 0
3321 || (code != IOR && w0 == 0xffff));
3322
3323 /* Determine if the upper half can be taken care of in no more
3324 than two bytes. */
3325 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3326 || (code == AND && w1 == 0xff00));
3327 }
366a7b27 3328
f9ac2f95
KH		 3329 /* Check if doing everything with one insn is no worse than
3330 using multiple insns. */
366a7b27 3331 if ((TARGET_H8300H || TARGET_H8300S)
f9ac2f95 3332 && w0 != 0 && w1 != 0
472f2723
KH		 3333 && !(lower_half_easy_p && upper_half_easy_p)
3334 && !(code == IOR && w1 == 0xffff
3335 && (w0 & 0x8000) != 0 && lower_half_easy_p))
366a7b27
KH		 3336 {
3337 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
3338 output_asm_insn (insn_buf, operands);
3339 }
3340 else
3341 {
3342 /* Take care of the lower and upper words individually. For
3343 each word, we try different methods in the order of
3344
3345 1) the special insn (in case of AND or XOR),
3346 2) the word-wise insn, and
3347 3) The byte-wise insn. */
c5e7ce43 3348 if (w0 == 0xffff
6dfa4005 3349 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
366a7b27 3350 output_asm_insn ((code == AND)
187462ac 3351 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
366a7b27
KH		 3352 operands);
3353 else if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 3354 && (b0 != 0)
3355 && (b1 != 0))
366a7b27
KH		 3356 {
3357 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
3358 output_asm_insn (insn_buf, operands);
3359 }
3360 else
3361 {
c5e7ce43 3362 if (b0 != 0)
366a7b27
KH		 3363 {
3364 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
3365 output_asm_insn (insn_buf, operands);
3366 }
c5e7ce43 3367 if (b1 != 0)
366a7b27
KH		 3368 {
3369 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
3370 output_asm_insn (insn_buf, operands);
3371 }
3372 }
3373
c5e7ce43 3374 if ((w1 == 0xffff)
6dfa4005 3375 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
366a7b27 3376 output_asm_insn ((code == AND)
187462ac 3377 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
366a7b27 3378 operands);
472f2723
KH		 3379 else if ((TARGET_H8300H || TARGET_H8300S)
3380 && code == IOR
3381 && w1 == 0xffff
3382 && (w0 & 0x8000) != 0)
3383 {
3384 output_asm_insn ("exts.l\t%S0", operands);
3385 }
a6e8d113
KH		 3386 else if ((TARGET_H8300H || TARGET_H8300S)
3387 && code == AND
c5e7ce43 3388 && w1 == 0xff00)
a6e8d113 3389 {
dc5f17ec 3390 output_asm_insn ("extu.w\t%e0", operands);
a6e8d113 3391 }
366a7b27
KH		 3392 else if (TARGET_H8300H || TARGET_H8300S)
3393 {
c5e7ce43 3394 if (w1 != 0)
366a7b27
KH		 3395 {
3396 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
3397 output_asm_insn (insn_buf, operands);
3398 }
3399 }
3400 else
3401 {
c5e7ce43 3402 if (b2 != 0)
366a7b27
KH		 3403 {
3404 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
3405 output_asm_insn (insn_buf, operands);
3406 }
c5e7ce43 3407 if (b3 != 0)
366a7b27
KH		 3408 {
3409 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
3410 output_asm_insn (insn_buf, operands);
3411 }
3412 }
3413 }
3414 break;
3415 default:
8c440872 3416 gcc_unreachable ();
366a7b27
KH		 3417 }
3418 return "";
3419}
40367e2d 3420
e9eba255
KH		 3421/* Compute the length of a logical insn. */
3422
40367e2d 3423unsigned int
cb713a8d 3424compute_logical_op_length (enum machine_mode mode, rtx *operands)
40367e2d 3425{
b42cff6b
KH		 3426 /* Figure out the logical op that we need to perform. */
3427 enum rtx_code code = GET_CODE (operands[3]);
40367e2d 3428 /* Pretend that every byte is affected if both operands are registers. */
7798db98 3429 const unsigned HOST_WIDE_INT intval =
40367e2d 3430 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
beed8fc0
AO		 3431 /* Always use the full instruction if the
3432 first operand is in memory. It is better
3433 to use define_splits to generate the shorter
3434 sequence where valid. */
3435 && register_operand (operands[1], VOIDmode)
40367e2d
KH		 3436 ? INTVAL (operands[2]) : 0x55555555);
3437 /* The determinant of the algorithm. If we perform an AND, 0
3438 affects a bit. Otherwise, 1 affects a bit. */
7798db98 3439 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
f9ac2f95
KH		 3440 /* Break up DET into pieces. */
3441 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3442 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
c5e7ce43
KH		 3443 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3444 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
f9ac2f95
KH		 3445 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3446 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3447 int lower_half_easy_p = 0;
3448 int upper_half_easy_p = 0;
40367e2d
KH		 3449 /* Insn length. */
3450 unsigned int length = 0;
3451
3452 switch (mode)
3453 {
3454 case HImode:
3455 /* First, see if we can finish with one insn. */
3456 if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 3457 && b0 != 0
3458 && b1 != 0)
40367e2d 3459 {
beed8fc0
AO		 3460 length = h8300_length_from_table (operands[1], operands[2],
3461 &logicw_length_table);
40367e2d
KH		 3462 }
3463 else
3464 {
3465 /* Take care of the lower byte. */
c5e7ce43 3466 if (b0 != 0)
40367e2d
KH		 3467 length += 2;
3468
3469 /* Take care of the upper byte. */
c5e7ce43 3470 if (b1 != 0)
40367e2d
KH		 3471 length += 2;
3472 }
3473 break;
3474 case SImode:
f9ac2f95
KH		 3475 if (TARGET_H8300H || TARGET_H8300S)
3476 {
3477 /* Determine if the lower half can be taken care of in no more
3478 than two bytes. */
3479 lower_half_easy_p = (b0 == 0
3480 || b1 == 0
3481 || (code != IOR && w0 == 0xffff));
3482
3483 /* Determine if the upper half can be taken care of in no more
3484 than two bytes. */
3485 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3486 || (code == AND && w1 == 0xff00));
3487 }
40367e2d 3488
f9ac2f95
KH		 3489 /* Check if doing everything with one insn is no worse than
3490 using multiple insns. */
40367e2d 3491 if ((TARGET_H8300H || TARGET_H8300S)
f9ac2f95 3492 && w0 != 0 && w1 != 0
472f2723
KH		 3493 && !(lower_half_easy_p && upper_half_easy_p)
3494 && !(code == IOR && w1 == 0xffff
3495 && (w0 & 0x8000) != 0 && lower_half_easy_p))
40367e2d 3496 {
beed8fc0
AO		 3497 length = h8300_length_from_table (operands[1], operands[2],
3498 &logicl_length_table);
40367e2d
KH		 3499 }
3500 else
3501 {
3502 /* Take care of the lower and upper words individually. For
3503 each word, we try different methods in the order of
3504
3505 1) the special insn (in case of AND or XOR),
3506 2) the word-wise insn, and
3507 3) The byte-wise insn. */
c5e7ce43 3508 if (w0 == 0xffff
40367e2d
KH		 3509 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3510 {
3511 length += 2;
3512 }
3513 else if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 3514 && (b0 != 0)
3515 && (b1 != 0))
40367e2d
KH		 3516 {
3517 length += 4;
3518 }
3519 else
3520 {
c5e7ce43 3521 if (b0 != 0)
40367e2d
KH		 3522 length += 2;
3523
c5e7ce43 3524 if (b1 != 0)
40367e2d
KH		 3525 length += 2;
3526 }
3527
c5e7ce43 3528 if (w1 == 0xffff
40367e2d
KH		 3529 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3530 {
3531 length += 2;
3532 }
472f2723
KH		 3533 else if ((TARGET_H8300H || TARGET_H8300S)
3534 && code == IOR
3535 && w1 == 0xffff
3536 && (w0 & 0x8000) != 0)
3537 {
3538 length += 2;
3539 }
a6e8d113
KH		 3540 else if ((TARGET_H8300H || TARGET_H8300S)
3541 && code == AND
c5e7ce43 3542 && w1 == 0xff00)
a6e8d113
KH		 3543 {
3544 length += 2;
3545 }
40367e2d
KH		 3546 else if (TARGET_H8300H || TARGET_H8300S)
3547 {
c5e7ce43 3548 if (w1 != 0)
40367e2d
KH		 3549 length += 4;
3550 }
3551 else
3552 {
c5e7ce43 3553 if (b2 != 0)
40367e2d
KH		 3554 length += 2;
3555
c5e7ce43 3556 if (b3 != 0)
40367e2d
KH		 3557 length += 2;
3558 }
3559 }
3560 break;
3561 default:
8c440872 3562 gcc_unreachable ();
40367e2d
KH		 3563 }
3564 return length;
3565}
b42cff6b 3566
e9eba255
KH		 3567/* Compute which flag bits are valid after a logical insn. */
3568
9690aa8e 3569enum attr_cc
cb713a8d 3570compute_logical_op_cc (enum machine_mode mode, rtx *operands)
b42cff6b
KH		 3571{
3572 /* Figure out the logical op that we need to perform. */
3573 enum rtx_code code = GET_CODE (operands[3]);
3574 /* Pretend that every byte is affected if both operands are registers. */
7798db98 3575 const unsigned HOST_WIDE_INT intval =
b42cff6b 3576 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
beed8fc0
AO		 3577 /* Always use the full instruction if the
3578 first operand is in memory. It is better
3579 to use define_splits to generate the shorter
3580 sequence where valid. */
3581 && register_operand (operands[1], VOIDmode)
b42cff6b
KH		 3582 ? INTVAL (operands[2]) : 0x55555555);
3583 /* The determinant of the algorithm. If we perform an AND, 0
3584 affects a bit. Otherwise, 1 affects a bit. */
7798db98 3585 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
f9ac2f95
KH		 3586 /* Break up DET into pieces. */
3587 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3588 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3589 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3590 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3591 int lower_half_easy_p = 0;
3592 int upper_half_easy_p = 0;
b42cff6b
KH		 3593 /* Condition code. */
3594 enum attr_cc cc = CC_CLOBBER;
3595
3596 switch (mode)
3597 {
3598 case HImode:
3599 /* First, see if we can finish with one insn. */
3600 if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 3601 && b0 != 0
3602 && b1 != 0)
b42cff6b
KH		 3603 {
3604 cc = CC_SET_ZNV;
3605 }
3606 break;
3607 case SImode:
f9ac2f95
KH		 3608 if (TARGET_H8300H || TARGET_H8300S)
3609 {
3610 /* Determine if the lower half can be taken care of in no more
3611 than two bytes. */
3612 lower_half_easy_p = (b0 == 0
3613 || b1 == 0
3614 || (code != IOR && w0 == 0xffff));
3615
3616 /* Determine if the upper half can be taken care of in no more
3617 than two bytes. */
3618 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3619 || (code == AND && w1 == 0xff00));
3620 }
b42cff6b 3621
f9ac2f95
KH		 3622 /* Check if doing everything with one insn is no worse than
3623 using multiple insns. */
b42cff6b 3624 if ((TARGET_H8300H || TARGET_H8300S)
f9ac2f95 3625 && w0 != 0 && w1 != 0
472f2723
KH		 3626 && !(lower_half_easy_p && upper_half_easy_p)
3627 && !(code == IOR && w1 == 0xffff
3628 && (w0 & 0x8000) != 0 && lower_half_easy_p))
b42cff6b
KH		 3629 {
3630 cc = CC_SET_ZNV;
3631 }
472f2723
KH		 3632 else
3633 {
3634 if ((TARGET_H8300H || TARGET_H8300S)
3635 && code == IOR
3636 && w1 == 0xffff
3637 && (w0 & 0x8000) != 0)
3638 {
3639 cc = CC_SET_ZNV;
3640 }
3641 }
b42cff6b
KH		 3642 break;
3643 default:
8c440872 3644 gcc_unreachable ();
b42cff6b
KH		 3645 }
3646 return cc;
3647}
366a7b27 3648\f
8981ecd3
KH		 3649/* Expand a conditional branch. */
3650
3651void
f90b7a5a 3652h8300_expand_branch (rtx operands[])
8981ecd3 3653{
f90b7a5a
PB		 3654 enum rtx_code code = GET_CODE (operands[0]);
3655 rtx op0 = operands[1];
3656 rtx op1 = operands[2];
3657 rtx label = operands[3];
8981ecd3
KH		 3658 rtx tmp;
3659
f90b7a5a
PB		 3660 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3661 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3662
8981ecd3
KH		 3663 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
3664 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
3665 gen_rtx_LABEL_REF (VOIDmode, label),
3666 pc_rtx);
3667 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
3668}
f90b7a5a
PB		 3669
3670
3671/* Expand a conditional store. */
3672
3673void
3674h8300_expand_store (rtx operands[])
3675{
3676 rtx dest = operands[0];
3677 enum rtx_code code = GET_CODE (operands[1]);
3678 rtx op0 = operands[2];
3679 rtx op1 = operands[3];
3680 rtx tmp;
3681
3682 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3683 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3684
3685 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx);
3686 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
3687}
8981ecd3 3688\f
48837e29
DE		 3689/* Shifts.
3690
005e3e05
KH		 3691 We devote a fair bit of code to getting efficient shifts since we
3692 can only shift one bit at a time on the H8/300 and H8/300H and only
3db11b5c 3693 one or two bits at a time on the H8S.
005e3e05
KH		 3694
3695 All shift code falls into one of the following ways of
3696 implementation:
3697
3698 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3699 when a straight line shift is about the same size or smaller than
3700 a loop.
3701
3702 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3703 off the bits we don't need. This is used when only a few of the
3704 bits in the original value will survive in the shifted value.
3705
3706 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3707 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3708 shifts can be added if the shift count is slightly more than 8 or
3709 16. This case also includes other oddballs that are not worth
f411c849 3710 explaining here.
005e3e05 3711
3db11b5c 3712 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
005e3e05 3713
5ec0b66e
KH		 3714 For each shift count, we try to use code that has no trade-off
3715 between code size and speed whenever possible.
3716
3717 If the trade-off is unavoidable, we try to be reasonable.
3718 Specifically, the fastest version is one instruction longer than
3719 the shortest version, we take the fastest version. We also provide
3720 the use a way to switch back to the shortest version with -Os.
3721
3722 For the details of the shift algorithms for various shift counts,
3723 refer to shift_alg_[qhs]i. */
07aae5c2 3724
beed8fc0
AO		 3725/* Classify a shift with the given mode and code. OP is the shift amount. */
3726
3727enum h8sx_shift_type
3728h8sx_classify_shift (enum machine_mode mode, enum rtx_code code, rtx op)
3729{
3730 if (!TARGET_H8300SX)
3731 return H8SX_SHIFT_NONE;
3732
3733 switch (code)
3734 {
3735 case ASHIFT:
3736 case LSHIFTRT:
3737 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3738 if (GET_CODE (op) != CONST_INT)
3739 return H8SX_SHIFT_BINARY;
3740
3741 /* Reject out-of-range shift amounts. */
3742 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
3743 return H8SX_SHIFT_NONE;
3744
3745 /* Power-of-2 shifts are effectively unary operations. */
3746 if (exact_log2 (INTVAL (op)) >= 0)
3747 return H8SX_SHIFT_UNARY;
3748
3749 return H8SX_SHIFT_BINARY;
3750
3751 case ASHIFTRT:
3752 if (op == const1_rtx || op == const2_rtx)
3753 return H8SX_SHIFT_UNARY;
3754 return H8SX_SHIFT_NONE;
3755
3756 case ROTATE:
3757 if (GET_CODE (op) == CONST_INT
3758 && (INTVAL (op) == 1
3759 || INTVAL (op) == 2
3760 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
3761 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
3762 return H8SX_SHIFT_UNARY;
3763 return H8SX_SHIFT_NONE;
3764
3765 default:
3766 return H8SX_SHIFT_NONE;
3767 }
3768}
3769
beed8fc0
AO		 3770/* Return the asm template for a single h8sx shift instruction.
3771 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3772 is the source and OPERANDS[3] is the shift. SUFFIX is the
88cb339e 3773 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
beed8fc0
AO		 3774 prefix for the destination operand. */
3775
3776const char *
3777output_h8sx_shift (rtx *operands, int suffix, int optype)
3778{
3779 static char buffer[16];
3780 const char *stem;
3781
3782 switch (GET_CODE (operands[3]))
3783 {
3784 case ASHIFT:
3785 stem = "shll";
3786 break;
3787
3788 case ASHIFTRT:
3789 stem = "shar";
3790 break;
3791
3792 case LSHIFTRT:
3793 stem = "shlr";
3794 break;
3795
3796 case ROTATE:
3797 stem = "rotl";
3798 if (INTVAL (operands[2]) > 2)
3799 {
3800 /* This is really a right rotate. */
3801 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
3802 - INTVAL (operands[2]));
3803 stem = "rotr";
3804 }
3805 break;
3806
3807 default:
8c440872 3808 gcc_unreachable ();
beed8fc0
AO		 3809 }
3810 if (operands[2] == const1_rtx)
3811 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
3812 else
3813 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
3814 return buffer;
3815}
48837e29 3816
317d21e9 3817/* Emit code to do shifts. */
48837e29 3818
beed8fc0 3819bool
9690aa8e 3820expand_a_shift (enum machine_mode mode, enum rtx_code code, rtx operands[])
07aae5c2 3821{
beed8fc0
AO		 3822 switch (h8sx_classify_shift (mode, code, operands[2]))
3823 {
3824 case H8SX_SHIFT_BINARY:
3825 operands[1] = force_reg (mode, operands[1]);
3826 return false;
3827
3828 case H8SX_SHIFT_UNARY:
3829 return false;
3830
3831 case H8SX_SHIFT_NONE:
3832 break;
3833 }
3834
bc9b880c 3835 emit_move_insn (copy_rtx (operands[0]), operands[1]);
07aae5c2 3836
07e4d94e
KH		 3837 /* Need a loop to get all the bits we want - we generate the
3838 code at emit time, but need to allocate a scratch reg now. */
48837e29 3839
c5c76735
JL		 3840 emit_insn (gen_rtx_PARALLEL
3841 (VOIDmode,
48837e29 3842 gen_rtvec (2,
bc9b880c 3843 gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
0f4c242b 3844 gen_rtx_fmt_ee (code, mode,
bc9b880c 3845 copy_rtx (operands[0]), operands[2])),
c5c76735
JL		 3846 gen_rtx_CLOBBER (VOIDmode,
3847 gen_rtx_SCRATCH (QImode)))));
beed8fc0 3848 return true;
48837e29
DE		 3849}
3850
48837e29
DE		 3851/* Symbols of the various modes which can be used as indices. */
3852
3853enum shift_mode
1a63219b
KH		 3854{
3855 QIshift, HIshift, SIshift
3856};
48837e29 3857
269c14e1
DE		 3858/* For single bit shift insns, record assembler and what bits of the
3859 condition code are valid afterwards (represented as various CC_FOO
3860 bits, 0 means CC isn't left in a usable state). */
48837e29
DE		 3861
3862struct shift_insn
3863{
8b60264b 3864 const char *const assembler;
9690aa8e 3865 const enum attr_cc cc_valid;
48837e29
DE		 3866};
3867
3868/* Assembler instruction shift table.
3869
3870 These tables are used to look up the basic shifts.
07e4d94e 3871 They are indexed by cpu, shift_type, and mode. */
07aae5c2 3872
48837e29
DE		 3873static const struct shift_insn shift_one[2][3][3] =
3874{
3875/* H8/300 */
3876 {
3877/* SHIFT_ASHIFT */
3878 {
45ca2106
KH		 3879 { "shll\t%X0", CC_SET_ZNV },
3880 { "add.w\t%T0,%T0", CC_SET_ZN },
3881 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
48837e29
DE		 3882 },
3883/* SHIFT_LSHIFTRT */
3884 {
45ca2106
KH		 3885 { "shlr\t%X0", CC_SET_ZNV },
3886 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3887 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
48837e29
DE		 3888 },
3889/* SHIFT_ASHIFTRT */
3890 {
45ca2106
KH		 3891 { "shar\t%X0", CC_SET_ZNV },
3892 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3893 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
48837e29
DE		 3894 }
3895 },
3896/* H8/300H */
3897 {
3898/* SHIFT_ASHIFT */
3899 {
45ca2106
KH		 3900 { "shll.b\t%X0", CC_SET_ZNV },
3901 { "shll.w\t%T0", CC_SET_ZNV },
3902 { "shll.l\t%S0", CC_SET_ZNV }
48837e29
DE		 3903 },
3904/* SHIFT_LSHIFTRT */
3905 {
45ca2106
KH		 3906 { "shlr.b\t%X0", CC_SET_ZNV },
3907 { "shlr.w\t%T0", CC_SET_ZNV },
3908 { "shlr.l\t%S0", CC_SET_ZNV }
48837e29
DE		 3909 },
3910/* SHIFT_ASHIFTRT */
3911 {
45ca2106
KH		 3912 { "shar.b\t%X0", CC_SET_ZNV },
3913 { "shar.w\t%T0", CC_SET_ZNV },
3914 { "shar.l\t%S0", CC_SET_ZNV }
48837e29
DE		 3915 }
3916 }
3917};
07aae5c2 3918
51c0c1d7
JL		 3919static const struct shift_insn shift_two[3][3] =
3920{
3921/* SHIFT_ASHIFT */
3922 {
45ca2106
KH		 3923 { "shll.b\t#2,%X0", CC_SET_ZNV },
3924 { "shll.w\t#2,%T0", CC_SET_ZNV },
3925 { "shll.l\t#2,%S0", CC_SET_ZNV }
51c0c1d7
JL		 3926 },
3927/* SHIFT_LSHIFTRT */
3928 {
45ca2106
KH		 3929 { "shlr.b\t#2,%X0", CC_SET_ZNV },
3930 { "shlr.w\t#2,%T0", CC_SET_ZNV },
3931 { "shlr.l\t#2,%S0", CC_SET_ZNV }
51c0c1d7
JL		 3932 },
3933/* SHIFT_ASHIFTRT */
3934 {
45ca2106
KH		 3935 { "shar.b\t#2,%X0", CC_SET_ZNV },
3936 { "shar.w\t#2,%T0", CC_SET_ZNV },
3937 { "shar.l\t#2,%S0", CC_SET_ZNV }
51c0c1d7
JL		 3938 }
3939};
3940
48837e29
DE		 3941/* Rotates are organized by which shift they'll be used in implementing.
3942 There's no need to record whether the cc is valid afterwards because
3943 it is the AND insn that will decide this. */
07aae5c2 3944
48837e29
DE		 3945static const char *const rotate_one[2][3][3] =
3946{
3947/* H8/300 */
3948 {
3949/* SHIFT_ASHIFT */
3950 {
51c0c1d7
JL		 3951 "rotr\t%X0",
3952 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
48837e29
DE		 3953 0
3954 },
3955/* SHIFT_LSHIFTRT */
3956 {
51c0c1d7
JL		 3957 "rotl\t%X0",
3958 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
48837e29
DE		 3959 0
3960 },
3961/* SHIFT_ASHIFTRT */
3962 {
51c0c1d7
JL		 3963 "rotl\t%X0",
3964 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
48837e29 3965 0
07aae5c2 3966 }
48837e29
DE		 3967 },
3968/* H8/300H */
3969 {
3970/* SHIFT_ASHIFT */
3971 {
51c0c1d7
JL		 3972 "rotr.b\t%X0",
3973 "rotr.w\t%T0",
3974 "rotr.l\t%S0"
48837e29
DE		 3975 },
3976/* SHIFT_LSHIFTRT */
07aae5c2 3977 {
51c0c1d7
JL		 3978 "rotl.b\t%X0",
3979 "rotl.w\t%T0",
3980 "rotl.l\t%S0"
48837e29
DE		 3981 },
3982/* SHIFT_ASHIFTRT */
3983 {
51c0c1d7
JL		 3984 "rotl.b\t%X0",
3985 "rotl.w\t%T0",
3986 "rotl.l\t%S0"
48837e29
DE		 3987 }
3988 }
3989};
3990
51c0c1d7
JL		 3991static const char *const rotate_two[3][3] =
3992{
3993/* SHIFT_ASHIFT */
3994 {
3995 "rotr.b\t#2,%X0",
3996 "rotr.w\t#2,%T0",
3997 "rotr.l\t#2,%S0"
3998 },
3999/* SHIFT_LSHIFTRT */
4000 {
4001 "rotl.b\t#2,%X0",
4002 "rotl.w\t#2,%T0",
4003 "rotl.l\t#2,%S0"
4004 },
4005/* SHIFT_ASHIFTRT */
4006 {
4007 "rotl.b\t#2,%X0",
4008 "rotl.w\t#2,%T0",
4009 "rotl.l\t#2,%S0"
4010 }
4011};
4012
35fb3d1f
KH		 4013struct shift_info {
4014 /* Shift algorithm. */
4015 enum shift_alg alg;
4016
4017 /* The number of bits to be shifted by shift1 and shift2. Valid
4018 when ALG is SHIFT_SPECIAL. */
4019 unsigned int remainder;
4020
4021 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
4022 const char *special;
4023
4024 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
9cd10576 4025 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
35fb3d1f
KH		 4026 const char *shift1;
4027
4028 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
9cd10576 4029 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
35fb3d1f
KH		 4030 const char *shift2;
4031
45ca2106 4032 /* CC status for SHIFT_INLINE. */
9690aa8e 4033 enum attr_cc cc_inline;
45ca2106
KH		 4034
4035 /* CC status for SHIFT_SPECIAL. */
9690aa8e 4036 enum attr_cc cc_special;
35fb3d1f
KH		 4037};
4038
cb713a8d
KH		 4039static void get_shift_alg (enum shift_type,
4040 enum shift_mode, unsigned int,
4041 struct shift_info *);
441d04c6 4042
c009a745
KH		 4043/* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
4044 best algorithm for doing the shift. The assembler code is stored
5ec0b66e
KH		 4045 in the pointers in INFO. We achieve the maximum efficiency in most
4046 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
4047 SImode in particular have a lot of room to optimize.
4048
4049 We first determine the strategy of the shift algorithm by a table
4050 lookup. If that tells us to use a hand crafted assembly code, we
4051 go into the big switch statement to find what that is. Otherwise,
4052 we resort to a generic way, such as inlining. In either case, the
4053 result is returned through INFO. */
48837e29 4054
cb33eb17 4055static void
cb713a8d
KH		 4056get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
4057 unsigned int count, struct shift_info *info)
48837e29 4058{
b9b575e6 4059 enum h8_cpu cpu;
769828ab
KH		 4060
4061 /* Find the target CPU. */
4062 if (TARGET_H8300)
b9b575e6 4063 cpu = H8_300;
769828ab 4064 else if (TARGET_H8300H)
b9b575e6 4065 cpu = H8_300H;
769828ab 4066 else
b9b575e6 4067 cpu = H8_S;
769828ab 4068
96eaf358 4069 /* Find the shift algorithm. */
b9b575e6 4070 info->alg = SHIFT_LOOP;
48837e29
DE		 4071 switch (shift_mode)
4072 {
4073 case QIshift:
b9b575e6 4074 if (count < GET_MODE_BITSIZE (QImode))
96eaf358
KH		 4075 info->alg = shift_alg_qi[cpu][shift_type][count];
4076 break;
769828ab 4077
96eaf358 4078 case HIshift:
b9b575e6 4079 if (count < GET_MODE_BITSIZE (HImode))
96eaf358
KH		 4080 info->alg = shift_alg_hi[cpu][shift_type][count];
4081 break;
4082
4083 case SIshift:
b9b575e6 4084 if (count < GET_MODE_BITSIZE (SImode))
96eaf358
KH		 4085 info->alg = shift_alg_si[cpu][shift_type][count];
4086 break;
4087
4088 default:
8c440872 4089 gcc_unreachable ();
96eaf358
KH		 4090 }
4091
4092 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4093 switch (info->alg)
4094 {
4095 case SHIFT_INLINE:
4096 info->remainder = count;
4097 /* Fall through. */
4098
4099 case SHIFT_LOOP:
4100 /* It is up to the caller to know that looping clobbers cc. */
4101 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4102 info->shift2 = shift_two[shift_type][shift_mode].assembler;
45ca2106 4103 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
96eaf358
KH		 4104 goto end;
4105
4106 case SHIFT_ROT_AND:
4107 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
4108 info->shift2 = rotate_two[shift_type][shift_mode];
45ca2106 4109 info->cc_inline = CC_CLOBBER;
96eaf358
KH		 4110 goto end;
4111
4112 case SHIFT_SPECIAL:
4113 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4114 info->remainder = 0;
4115 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4116 info->shift2 = shift_two[shift_type][shift_mode].assembler;
45ca2106
KH		 4117 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4118 info->cc_special = CC_CLOBBER;
96eaf358
KH		 4119 break;
4120 }
51c0c1d7 4121
96eaf358
KH		 4122 /* Here we only deal with SHIFT_SPECIAL. */
4123 switch (shift_mode)
4124 {
4125 case QIshift:
769828ab
KH		 4126 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4127 through the entire value. */
8c440872
NS		 4128 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
4129 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
4130 goto end;
769828ab
KH		 4131
4132 case HIshift:
769828ab 4133 if (count == 7)
51c0c1d7 4134 {
a77b1dbc 4135 switch (shift_type)
51c0c1d7 4136 {
a77b1dbc
KH		 4137 case SHIFT_ASHIFT:
4138 if (TARGET_H8300)
4139 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4140 else
4141 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
692b7eb3 4142 goto end;
a77b1dbc
KH		 4143 case SHIFT_LSHIFTRT:
4144 if (TARGET_H8300)
4145 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4146 else
4147 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
692b7eb3 4148 goto end;
a77b1dbc 4149 case SHIFT_ASHIFTRT:
35fb3d1f 4150 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
692b7eb3 4151 goto end;
48837e29 4152 }
07aae5c2 4153 }
b30686ec 4154 else if ((8 <= count && count <= 13)
a38b3eea 4155 || (TARGET_H8300S && count == 14))
07aae5c2 4156 {
a7812c0b
KH		 4157 info->remainder = count - 8;
4158
51c0c1d7 4159 switch (shift_type)
48837e29 4160 {
51c0c1d7 4161 case SHIFT_ASHIFT:
35fb3d1f 4162 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
692b7eb3 4163 goto end;
51c0c1d7 4164 case SHIFT_LSHIFTRT:
a7612343
KH		 4165 if (TARGET_H8300)
4166 {
4167 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4168 info->shift1 = "shlr.b\t%s0";
45ca2106 4169 info->cc_inline = CC_SET_ZNV;
a7612343
KH		 4170 }
4171 else
4172 {
4173 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
45ca2106 4174 info->cc_special = CC_SET_ZNV;
a7612343 4175 }
692b7eb3 4176 goto end;
51c0c1d7
JL		 4177 case SHIFT_ASHIFTRT:
4178 if (TARGET_H8300)
a7612343
KH		 4179 {
4180 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4181 info->shift1 = "shar.b\t%s0";
a7612343 4182 }
51c0c1d7 4183 else
a7612343
KH		 4184 {
4185 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
45ca2106 4186 info->cc_special = CC_SET_ZNV;
a7612343 4187 }
692b7eb3 4188 goto end;
51c0c1d7
JL		 4189 }
4190 }
5e98fba2
DD		 4191 else if (count == 14)
4192 {
4193 switch (shift_type)
4194 {
4195 case SHIFT_ASHIFT:
4196 if (TARGET_H8300)
4197 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4198 goto end;
4199 case SHIFT_LSHIFTRT:
4200 if (TARGET_H8300)
4201 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4202 goto end;
4203 case SHIFT_ASHIFTRT:
4204 if (TARGET_H8300)
4205 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4206 else if (TARGET_H8300H)
45ca2106
KH		 4207 {
4208 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4209 info->cc_special = CC_SET_ZNV;
4210 }
5e98fba2 4211 else /* TARGET_H8300S */
8c440872 4212 gcc_unreachable ();
5e98fba2
DD		 4213 goto end;
4214 }
4215 }
1e41e866 4216 else if (count == 15)
51c0c1d7 4217 {
1e41e866
KH		 4218 switch (shift_type)
4219 {
4220 case SHIFT_ASHIFT:
4221 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4222 goto end;
4223 case SHIFT_LSHIFTRT:
4224 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4225 goto end;
4226 case SHIFT_ASHIFTRT:
4227 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4228 goto end;
4229 }
07aae5c2 4230 }
8c440872 4231 gcc_unreachable ();
51c0c1d7 4232
48837e29 4233 case SIshift:
1e41e866 4234 if (TARGET_H8300 && 8 <= count && count <= 9)
48837e29 4235 {
1e41e866
KH		 4236 info->remainder = count - 8;
4237
51c0c1d7 4238 switch (shift_type)
48837e29 4239 {
51c0c1d7 4240 case SHIFT_ASHIFT:
35fb3d1f 4241 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
692b7eb3 4242 goto end;
51c0c1d7 4243 case SHIFT_LSHIFTRT:
35fb3d1f 4244 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
1e41e866 4245 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
692b7eb3 4246 goto end;
51c0c1d7 4247 case SHIFT_ASHIFTRT:
35fb3d1f 4248 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
692b7eb3 4249 goto end;
48837e29 4250 }
48837e29 4251 }
e6bcfef9
JS		 4252 else if (count == 8 && !TARGET_H8300)
4253 {
4254 switch (shift_type)
4255 {
4256 case SHIFT_ASHIFT:
35fb3d1f 4257 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
692b7eb3 4258 goto end;
e6bcfef9 4259 case SHIFT_LSHIFTRT:
35fb3d1f 4260 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
692b7eb3 4261 goto end;
e6bcfef9 4262 case SHIFT_ASHIFTRT:
35fb3d1f 4263 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
692b7eb3 4264 goto end;
e6bcfef9
JS		 4265 }
4266 }
1e41e866
KH		 4267 else if (count == 15 && TARGET_H8300)
4268 {
4269 switch (shift_type)
4270 {
4271 case SHIFT_ASHIFT:
8c440872 4272 gcc_unreachable ();
1e41e866 4273 case SHIFT_LSHIFTRT:
a35abc3c 4274 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
1e41e866
KH		 4275 goto end;
4276 case SHIFT_ASHIFTRT:
a35abc3c 4277 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
1e41e866
KH		 4278 goto end;
4279 }
4280 }
dd69e230
KH		 4281 else if (count == 15 && !TARGET_H8300)
4282 {
4283 switch (shift_type)
4284 {
4285 case SHIFT_ASHIFT:
4286 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
45ca2106 4287 info->cc_special = CC_SET_ZNV;
dd69e230
KH		 4288 goto end;
4289 case SHIFT_LSHIFTRT:
18cf8dda 4290 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
45ca2106 4291 info->cc_special = CC_SET_ZNV;
dd69e230 4292 goto end;
aefc5826 4293 case SHIFT_ASHIFTRT:
8c440872 4294 gcc_unreachable ();
dd69e230
KH		 4295 }
4296 }
1e41e866 4297 else if ((TARGET_H8300 && 16 <= count && count <= 20)
a7812c0b 4298 || (TARGET_H8300H && 16 <= count && count <= 19)
e0f19bd0 4299 || (TARGET_H8300S && 16 <= count && count <= 21))
48837e29 4300 {
a7812c0b
KH		 4301 info->remainder = count - 16;
4302
48837e29
DE		 4303 switch (shift_type)
4304 {
4305 case SHIFT_ASHIFT:
35fb3d1f 4306 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
1e41e866 4307 if (TARGET_H8300)
b30686ec 4308 info->shift1 = "add.w\t%e0,%e0";
692b7eb3 4309 goto end;
51c0c1d7 4310 case SHIFT_LSHIFTRT:
1e41e866
KH		 4311 if (TARGET_H8300)
4312 {
a7612343
KH		 4313 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4314 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
1e41e866
KH		 4315 }
4316 else
4317 {
a7612343 4318 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
45ca2106 4319 info->cc_special = CC_SET_ZNV;
1e41e866 4320 }
692b7eb3 4321 goto end;
51c0c1d7
JL		 4322 case SHIFT_ASHIFTRT:
4323 if (TARGET_H8300)
1e41e866
KH		 4324 {
4325 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4326 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
4327 }
51c0c1d7 4328 else
1e41e866
KH		 4329 {
4330 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
45ca2106 4331 info->cc_special = CC_SET_ZNV;
1e41e866 4332 }
692b7eb3 4333 goto end;
51c0c1d7
JL		 4334 }
4335 }
1e41e866 4336 else if (TARGET_H8300 && 24 <= count && count <= 28)
f9477efd
KH		 4337 {
4338 info->remainder = count - 24;
f0b6f9a6 4339
f9477efd
KH		 4340 switch (shift_type)
4341 {
4342 case SHIFT_ASHIFT:
4343 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4344 info->shift1 = "shll.b\t%z0";
45ca2106 4345 info->cc_inline = CC_SET_ZNV;
f9477efd
KH		 4346 goto end;
4347 case SHIFT_LSHIFTRT:
4348 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4349 info->shift1 = "shlr.b\t%w0";
45ca2106 4350 info->cc_inline = CC_SET_ZNV;
f9477efd
KH		 4351 goto end;
4352 case SHIFT_ASHIFTRT:
4353 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
4354 info->shift1 = "shar.b\t%w0";
45ca2106 4355 info->cc_inline = CC_SET_ZNV;
7f473594
KH		 4356 goto end;
4357 }
4358 }
4a4ae922
KH		 4359 else if ((TARGET_H8300H && count == 24)
4360 || (TARGET_H8300S && 24 <= count && count <= 25))
e6bcfef9 4361 {
4a4ae922
KH		 4362 info->remainder = count - 24;
4363
e6bcfef9
JS		 4364 switch (shift_type)
4365 {
4366 case SHIFT_ASHIFT:
35fb3d1f 4367 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
692b7eb3 4368 goto end;
e6bcfef9 4369 case SHIFT_LSHIFTRT:
35fb3d1f 4370 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
45ca2106 4371 info->cc_special = CC_SET_ZNV;
692b7eb3 4372 goto end;
e6bcfef9 4373 case SHIFT_ASHIFTRT:
35fb3d1f 4374 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
45ca2106 4375 info->cc_special = CC_SET_ZNV;
692b7eb3 4376 goto end;
e6bcfef9
JS		 4377 }
4378 }
1e5bdc40
KH		 4379 else if (!TARGET_H8300 && count == 28)
4380 {
4381 switch (shift_type)
4382 {
4383 case SHIFT_ASHIFT:
4384 if (TARGET_H8300H)
4385 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4386 else
4387 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
1e5bdc40
KH		 4388 goto end;
4389 case SHIFT_LSHIFTRT:
4390 if (TARGET_H8300H)
45ca2106
KH		 4391 {
4392 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4393 info->cc_special = CC_SET_ZNV;
4394 }
1e5bdc40 4395 else
a7612343 4396 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
1e5bdc40
KH		 4397 goto end;
4398 case SHIFT_ASHIFTRT:
8c440872 4399 gcc_unreachable ();
1e5bdc40
KH		 4400 }
4401 }
4402 else if (!TARGET_H8300 && count == 29)
4403 {
4404 switch (shift_type)
4405 {
4406 case SHIFT_ASHIFT:
4407 if (TARGET_H8300H)
4408 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4409 else
4410 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
1e5bdc40
KH		 4411 goto end;
4412 case SHIFT_LSHIFTRT:
4413 if (TARGET_H8300H)
45ca2106
KH		 4414 {
4415 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4416 info->cc_special = CC_SET_ZNV;
4417 }
1e5bdc40 4418 else
45ca2106
KH		 4419 {
4420 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4421 info->cc_special = CC_SET_ZNV;
4422 }
1e5bdc40
KH		 4423 goto end;
4424 case SHIFT_ASHIFTRT:
8c440872 4425 gcc_unreachable ();
1e5bdc40
KH		 4426 }
4427 }
4428 else if (!TARGET_H8300 && count == 30)
4429 {
4430 switch (shift_type)
4431 {
4432 case SHIFT_ASHIFT:
4433 if (TARGET_H8300H)
4434 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4435 else
4436 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
1e5bdc40
KH		 4437 goto end;
4438 case SHIFT_LSHIFTRT:
4439 if (TARGET_H8300H)
a7612343 4440 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
1e5bdc40 4441 else
a7612343 4442 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
1e5bdc40
KH		 4443 goto end;
4444 case SHIFT_ASHIFTRT:
8c440872 4445 gcc_unreachable ();
1e5bdc40
KH		 4446 }
4447 }
48837e29
DE		 4448 else if (count == 31)
4449 {
dd69e230 4450 if (TARGET_H8300)
48837e29 4451 {
dd69e230
KH		 4452 switch (shift_type)
4453 {
4454 case SHIFT_ASHIFT:
4455 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4456 goto end;
4457 case SHIFT_LSHIFTRT:
4458 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4459 goto end;
4460 case SHIFT_ASHIFTRT:
4461 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4462 goto end;
4463 }
48837e29
DE		 4464 }
4465 else
4466 {
dd69e230 4467 switch (shift_type)
48837e29 4468 {
dd69e230
KH		 4469 case SHIFT_ASHIFT:
4470 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
45ca2106 4471 info->cc_special = CC_SET_ZNV;
dd69e230
KH		 4472 goto end;
4473 case SHIFT_LSHIFTRT:
4474 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
45ca2106 4475 info->cc_special = CC_SET_ZNV;
dd69e230
KH		 4476 goto end;
4477 case SHIFT_ASHIFTRT:
a7612343 4478 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
45ca2106 4479 info->cc_special = CC_SET_ZNV;
692b7eb3 4480 goto end;
48837e29 4481 }
48837e29
DE		 4482 }
4483 }
8c440872 4484 gcc_unreachable ();
51c0c1d7 4485
48837e29 4486 default:
8c440872 4487 gcc_unreachable ();
07aae5c2 4488 }
48837e29 4489
cb33eb17
KH		 4490 end:
4491 if (!TARGET_H8300S)
4492 info->shift2 = NULL;
07aae5c2
SC		 4493}
4494
be1e06df
KH		 4495/* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4496 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4497
4498int
cb713a8d 4499h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
be1e06df 4500{
b9b575e6 4501 enum h8_cpu cpu;
be1e06df
KH		 4502 int a, lr, ar;
4503
4504 if (GET_MODE_BITSIZE (mode) <= count)
4505 return 1;
4506
4507 /* Find out the target CPU. */
4508 if (TARGET_H8300)
b9b575e6 4509 cpu = H8_300;
be1e06df 4510 else if (TARGET_H8300H)
b9b575e6 4511 cpu = H8_300H;
be1e06df 4512 else
b9b575e6 4513 cpu = H8_S;
be1e06df
KH		 4514
4515 /* Find the shift algorithm. */
4516 switch (mode)
4517 {
4518 case QImode:
4519 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
4520 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
4521 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
4522 break;
4523
4524 case HImode:
4525 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
4526 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
4527 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
4528 break;
4529
4530 case SImode:
4531 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
4532 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
4533 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
4534 break;
4535
4536 default:
8c440872 4537 gcc_unreachable ();
be1e06df
KH		 4538 }
4539
aa2fb4dd 4540 /* On H8/300H, count == 8 uses a scratch register. */
be1e06df 4541 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
75a3503b 4542 || (TARGET_H8300H && mode == SImode && count == 8));
be1e06df
KH		 4543}
4544
e9eba255 4545/* Output the assembler code for doing shifts. */
48837e29 4546
441d04c6 4547const char *
cb713a8d 4548output_a_shift (rtx *operands)
07aae5c2 4549{
48837e29 4550 static int loopend_lab;
48837e29
DE		 4551 rtx shift = operands[3];
4552 enum machine_mode mode = GET_MODE (shift);
4553 enum rtx_code code = GET_CODE (shift);
4554 enum shift_type shift_type;
4555 enum shift_mode shift_mode;
35fb3d1f 4556 struct shift_info info;
8c440872 4557 int n;
48837e29
DE		 4558
4559 loopend_lab++;
4560
4561 switch (mode)
4562 {
4563 case QImode:
4564 shift_mode = QIshift;
4565 break;
4566 case HImode:
4567 shift_mode = HIshift;
4568 break;
4569 case SImode:
4570 shift_mode = SIshift;
4571 break;
4572 default:
8c440872 4573 gcc_unreachable ();
48837e29 4574 }
07aae5c2 4575
48837e29 4576 switch (code)
07aae5c2 4577 {
48837e29
DE		 4578 case ASHIFTRT:
4579 shift_type = SHIFT_ASHIFTRT;
4580 break;
4581 case LSHIFTRT:
4582 shift_type = SHIFT_LSHIFTRT;
4583 break;
4584 case ASHIFT:
4585 shift_type = SHIFT_ASHIFT;
4586 break;
4587 default:
8c440872 4588 gcc_unreachable ();
48837e29 4589 }
07aae5c2 4590
8c440872
NS		 4591 /* This case must be taken care of by one of the two splitters
4592 that convert a variable shift into a loop. */
4593 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4594
4595 n = INTVAL (operands[2]);
4596
4597 /* If the count is negative, make it 0. */
4598 if (n < 0)
4599 n = 0;
4600 /* If the count is too big, truncate it.
4601 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4602 do the intuitive thing. */
4603 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4604 n = GET_MODE_BITSIZE (mode);
4605
4606 get_shift_alg (shift_type, shift_mode, n, &info);
4607
4608 switch (info.alg)
48837e29 4609 {
8c440872
NS		 4610 case SHIFT_SPECIAL:
4611 output_asm_insn (info.special, operands);
4612 /* Fall through. */
48837e29 4613
8c440872
NS		 4614 case SHIFT_INLINE:
4615 n = info.remainder;
48837e29 4616
8c440872
NS		 4617 /* Emit two bit shifts first. */
4618 if (info.shift2 != NULL)
48837e29 4619 {
8c440872
NS		 4620 for (; n > 1; n -= 2)
4621 output_asm_insn (info.shift2, operands);
4622 }
51c0c1d7 4623
8c440872
NS		 4624 /* Now emit one bit shifts for any residual. */
4625 for (; n > 0; n--)
4626 output_asm_insn (info.shift1, operands);
4627 return "";
4628
4629 case SHIFT_ROT_AND:
4630 {
4631 int m = GET_MODE_BITSIZE (mode) - n;
4632 const int mask = (shift_type == SHIFT_ASHIFT
4633 ? ((1 << m) - 1) << n
4634 : (1 << m) - 1);
4635 char insn_buf[200];
4636
4637 /* Not all possibilities of rotate are supported. They shouldn't
4638 be generated, but let's watch for 'em. */
4639 gcc_assert (info.shift1);
4640
4641 /* Emit two bit rotates first. */
4642 if (info.shift2 != NULL)
48837e29 4643 {
8c440872
NS		 4644 for (; m > 1; m -= 2)
4645 output_asm_insn (info.shift2, operands);
4646 }
4647
4648 /* Now single bit rotates for any residual. */
4649 for (; m > 0; m--)
4650 output_asm_insn (info.shift1, operands);
4651
4652 /* Now mask off the high bits. */
4653 switch (mode)
4654 {
4655 case QImode:
4656 sprintf (insn_buf, "and\t#%d,%%X0", mask);
4657 break;
51c0c1d7 4658
8c440872
NS		 4659 case HImode:
4660 gcc_assert (TARGET_H8300H || TARGET_H8300S);
4661 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
4662 break;
51c0c1d7 4663
8c440872
NS		 4664 default:
4665 gcc_unreachable ();
48837e29 4666 }
b5eaf9ba 4667
8c440872
NS		 4668 output_asm_insn (insn_buf, operands);
4669 return "";
4670 }
b5eaf9ba 4671
8c440872
NS		 4672 case SHIFT_LOOP:
4673 /* A loop to shift by a "large" constant value.
4674 If we have shift-by-2 insns, use them. */
4675 if (info.shift2 != NULL)
4676 {
4677 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
4678 names_big[REGNO (operands[4])]);
4679 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4680 output_asm_insn (info.shift2, operands);
4681 output_asm_insn ("add #0xff,%X4", operands);
4682 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4683 if (n % 2)
4684 output_asm_insn (info.shift1, operands);
4685 }
4686 else
4687 {
4688 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
4689 names_big[REGNO (operands[4])]);
4690 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4691 output_asm_insn (info.shift1, operands);
4692 output_asm_insn ("add #0xff,%X4", operands);
4693 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
51c0c1d7 4694 }
8c440872
NS		 4695 return "";
4696
4697 default:
4698 gcc_unreachable ();
07aae5c2 4699 }
07aae5c2 4700}
86855e8c 4701
0a2aaacc 4702/* Count the number of assembly instructions in a string TEMPL. */
e9eba255 4703
86855e8c 4704static unsigned int
0a2aaacc 4705h8300_asm_insn_count (const char *templ)
86855e8c
KH		 4706{
4707 unsigned int count = 1;
4708
0a2aaacc
KG		 4709 for (; *templ; templ++)
4710 if (*templ == '\n')
86855e8c
KH		 4711 count++;
4712
4713 return count;
4714}
4715
e9eba255
KH		 4716/* Compute the length of a shift insn. */
4717
86855e8c 4718unsigned int
cb713a8d 4719compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
86855e8c
KH		 4720{
4721 rtx shift = operands[3];
4722 enum machine_mode mode = GET_MODE (shift);
4723 enum rtx_code code = GET_CODE (shift);
4724 enum shift_type shift_type;
4725 enum shift_mode shift_mode;
4726 struct shift_info info;
4727 unsigned int wlength = 0;
4728
4729 switch (mode)
4730 {
4731 case QImode:
4732 shift_mode = QIshift;
4733 break;
4734 case HImode:
4735 shift_mode = HIshift;
4736 break;
4737 case SImode:
4738 shift_mode = SIshift;
4739 break;
4740 default:
8c440872 4741 gcc_unreachable ();
86855e8c
KH		 4742 }
4743
4744 switch (code)
4745 {
4746 case ASHIFTRT:
4747 shift_type = SHIFT_ASHIFTRT;
4748 break;
4749 case LSHIFTRT:
4750 shift_type = SHIFT_LSHIFTRT;
4751 break;
4752 case ASHIFT:
4753 shift_type = SHIFT_ASHIFT;
4754 break;
4755 default:
8c440872 4756 gcc_unreachable ();
86855e8c
KH		 4757 }
4758
4759 if (GET_CODE (operands[2]) != CONST_INT)
4760 {
4761 /* Get the assembler code to do one shift. */
4762 get_shift_alg (shift_type, shift_mode, 1, &info);
4763
4764 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
4765 }
4766 else
4767 {
4768 int n = INTVAL (operands[2]);
4769
4770 /* If the count is negative, make it 0. */
4771 if (n < 0)
4772 n = 0;
4773 /* If the count is too big, truncate it.
4774 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4775 do the intuitive thing. */
4776 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4777 n = GET_MODE_BITSIZE (mode);
4778
4779 get_shift_alg (shift_type, shift_mode, n, &info);
4780
4781 switch (info.alg)
4782 {
4783 case SHIFT_SPECIAL:
4784 wlength += h8300_asm_insn_count (info.special);
41c3eb5d
KH		 4785
4786 /* Every assembly instruction used in SHIFT_SPECIAL case
4787 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4788 see xor.l, we just pretend that xor.l counts as two insns
4789 so that the insn length will be computed correctly. */
4790 if (strstr (info.special, "xor.l") != NULL)
4791 wlength++;
4792
86855e8c
KH		 4793 /* Fall through. */
4794
4795 case SHIFT_INLINE:
4796 n = info.remainder;
4797
4798 if (info.shift2 != NULL)
4799 {
4800 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
4801 n = n % 2;
4802 }
4803
4804 wlength += h8300_asm_insn_count (info.shift1) * n;
6b148bd9 4805
86855e8c
KH		 4806 return 2 * wlength;
4807
4808 case SHIFT_ROT_AND:
4809 {
4810 int m = GET_MODE_BITSIZE (mode) - n;
4811
4812 /* Not all possibilities of rotate are supported. They shouldn't
4813 be generated, but let's watch for 'em. */
8c440872 4814 gcc_assert (info.shift1);
86855e8c
KH		 4815
4816 if (info.shift2 != NULL)
4817 {
4818 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
4819 m = m % 2;
4820 }
4821
4822 wlength += h8300_asm_insn_count (info.shift1) * m;
6b148bd9 4823
86855e8c
KH		 4824 /* Now mask off the high bits. */
4825 switch (mode)
4826 {
4827 case QImode:
4828 wlength += 1;
4829 break;
4830 case HImode:
4831 wlength += 2;
4832 break;
4833 case SImode:
8c440872 4834 gcc_assert (!TARGET_H8300);
86855e8c
KH		 4835 wlength += 3;
4836 break;
4837 default:
8c440872 4838 gcc_unreachable ();
86855e8c
KH		 4839 }
4840 return 2 * wlength;
4841 }
4842
4843 case SHIFT_LOOP:
4844 /* A loop to shift by a "large" constant value.
4845 If we have shift-by-2 insns, use them. */
4846 if (info.shift2 != NULL)
4847 {
4848 wlength += 3 + h8300_asm_insn_count (info.shift2);
4849 if (n % 2)
4850 wlength += h8300_asm_insn_count (info.shift1);
4851 }
4852 else
4853 {
4854 wlength += 3 + h8300_asm_insn_count (info.shift1);
4855 }
4856 return 2 * wlength;
4857
4858 default:
8c440872 4859 gcc_unreachable ();
86855e8c
KH		 4860 }
4861 }
4862}
45ca2106 4863
e9eba255
KH		 4864/* Compute which flag bits are valid after a shift insn. */
4865
9690aa8e 4866enum attr_cc
cb713a8d 4867compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
45ca2106
KH		 4868{
4869 rtx shift = operands[3];
4870 enum machine_mode mode = GET_MODE (shift);
4871 enum rtx_code code = GET_CODE (shift);
4872 enum shift_type shift_type;
4873 enum shift_mode shift_mode;
4874 struct shift_info info;
8c440872
NS		 4875 int n;
4876
45ca2106
KH		 4877 switch (mode)
4878 {
4879 case QImode:
4880 shift_mode = QIshift;
4881 break;
4882 case HImode:
4883 shift_mode = HIshift;
4884 break;
4885 case SImode:
4886 shift_mode = SIshift;
4887 break;
4888 default:
8c440872 4889 gcc_unreachable ();
45ca2106
KH		 4890 }
4891
4892 switch (code)
4893 {
4894 case ASHIFTRT:
4895 shift_type = SHIFT_ASHIFTRT;
4896 break;
4897 case LSHIFTRT:
4898 shift_type = SHIFT_LSHIFTRT;
4899 break;
4900 case ASHIFT:
4901 shift_type = SHIFT_ASHIFT;
4902 break;
4903 default:
8c440872 4904 gcc_unreachable ();
45ca2106
KH		 4905 }
4906
8c440872
NS		 4907 /* This case must be taken care of by one of the two splitters
4908 that convert a variable shift into a loop. */
4909 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4910
4911 n = INTVAL (operands[2]);
4912
4913 /* If the count is negative, make it 0. */
4914 if (n < 0)
4915 n = 0;
4916 /* If the count is too big, truncate it.
4917 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4918 do the intuitive thing. */
4919 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4920 n = GET_MODE_BITSIZE (mode);
4921
4922 get_shift_alg (shift_type, shift_mode, n, &info);
4923
4924 switch (info.alg)
45ca2106 4925 {
8c440872
NS		 4926 case SHIFT_SPECIAL:
4927 if (info.remainder == 0)
4928 return info.cc_special;
45ca2106 4929
8c440872 4930 /* Fall through. */
45ca2106 4931
8c440872
NS		 4932 case SHIFT_INLINE:
4933 return info.cc_inline;
4934
4935 case SHIFT_ROT_AND:
4936 /* This case always ends with an and instruction. */
4937 return CC_SET_ZNV;
4938
4939 case SHIFT_LOOP:
4940 /* A loop to shift by a "large" constant value.
4941 If we have shift-by-2 insns, use them. */
4942 if (info.shift2 != NULL)
45ca2106 4943 {
8c440872
NS		 4944 if (n % 2)
4945 return info.cc_inline;
45ca2106 4946 }
8c440872
NS		 4947 return CC_CLOBBER;
4948
4949 default:
4950 gcc_unreachable ();
45ca2106
KH		 4951 }
4952}
48837e29 4953\f
edd71f0f
KH		 4954/* A rotation by a non-constant will cause a loop to be generated, in
4955 which a rotation by one bit is used. A rotation by a constant,
4956 including the one in the loop, will be taken care of by
caf7f21a 4957 output_a_rotate () at the insn emit time. */
edd71f0f
KH		 4958
4959int
3d2e90d6 4960expand_a_rotate (rtx operands[])
edd71f0f
KH		 4961{
4962 rtx dst = operands[0];
4963 rtx src = operands[1];
4964 rtx rotate_amount = operands[2];
4965 enum machine_mode mode = GET_MODE (dst);
edd71f0f 4966
beed8fc0
AO		 4967 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
4968 return false;
4969
edd71f0f
KH		 4970 /* We rotate in place. */
4971 emit_move_insn (dst, src);
4972
4973 if (GET_CODE (rotate_amount) != CONST_INT)
4974 {
4975 rtx counter = gen_reg_rtx (QImode);
4976 rtx start_label = gen_label_rtx ();
4977 rtx end_label = gen_label_rtx ();
4978
4979 /* If the rotate amount is less than or equal to 0,
4980 we go out of the loop. */
a556fd39 4981 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
d43e0b7d 4982 QImode, 0, end_label);
edd71f0f
KH		 4983
4984 /* Initialize the loop counter. */
4985 emit_move_insn (counter, rotate_amount);
4986
4987 emit_label (start_label);
4988
4989 /* Rotate by one bit. */
01ab5574
KH		 4990 switch (mode)
4991 {
4992 case QImode:
4993 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
4994 break;
4995 case HImode:
4996 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
4997 break;
4998 case SImode:
4999 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
5000 break;
5001 default:
8c440872 5002 gcc_unreachable ();
01ab5574 5003 }
edd71f0f
KH		 5004
5005 /* Decrement the counter by 1. */
01ab5574 5006 emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
edd71f0f 5007
9cd10576 5008 /* If the loop counter is nonzero, we go back to the beginning
edd71f0f 5009 of the loop. */
a556fd39 5010 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
d43e0b7d 5011 start_label);
edd71f0f
KH		 5012
5013 emit_label (end_label);
5014 }
5015 else
5016 {
5017 /* Rotate by AMOUNT bits. */
01ab5574
KH		 5018 switch (mode)
5019 {
5020 case QImode:
5021 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
5022 break;
5023 case HImode:
5024 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
5025 break;
5026 case SImode:
5027 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
5028 break;
5029 default:
8c440872 5030 gcc_unreachable ();
01ab5574 5031 }
edd71f0f
KH		 5032 }
5033
5034 return 1;
5035}
5036
e9eba255 5037/* Output a rotate insn. */
edd71f0f
KH		 5038
5039const char *
caf7f21a 5040output_a_rotate (enum rtx_code code, rtx *operands)
edd71f0f
KH		 5041{
5042 rtx dst = operands[0];
5043 rtx rotate_amount = operands[2];
5044 enum shift_mode rotate_mode;
5045 enum shift_type rotate_type;
5046 const char *insn_buf;
5047 int bits;
5048 int amount;
5049 enum machine_mode mode = GET_MODE (dst);
5050
8c440872 5051 gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
edd71f0f
KH		 5052
5053 switch (mode)
5054 {
5055 case QImode:
5056 rotate_mode = QIshift;
5057 break;
5058 case HImode:
5059 rotate_mode = HIshift;
5060 break;
5061 case SImode:
5062 rotate_mode = SIshift;
5063 break;
5064 default:
8c440872 5065 gcc_unreachable ();
edd71f0f
KH		 5066 }
5067
5068 switch (code)
5069 {
5070 case ROTATERT:
5071 rotate_type = SHIFT_ASHIFT;
5072 break;
5073 case ROTATE:
5074 rotate_type = SHIFT_LSHIFTRT;
5075 break;
5076 default:
8c440872 5077 gcc_unreachable ();
edd71f0f
KH		 5078 }
5079
5080 amount = INTVAL (rotate_amount);
5081
5082 /* Clean up AMOUNT. */
5083 if (amount < 0)
5084 amount = 0;
5085 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5086 amount = GET_MODE_BITSIZE (mode);
5087
5088 /* Determine the faster direction. After this phase, amount will be
5089 at most a half of GET_MODE_BITSIZE (mode). */
e0c32c62 5090 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
edd71f0f
KH		 5091 {
5092 /* Flip the direction. */
5093 amount = GET_MODE_BITSIZE (mode) - amount;
5094 rotate_type =
5095 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5096 }
5097
5098 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5099 boost up the rotation. */
5100 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5101 || (mode == HImode && TARGET_H8300H && amount >= 6)
5102 || (mode == HImode && TARGET_H8300S && amount == 8)
5103 || (mode == SImode && TARGET_H8300H && amount >= 10)
5104 || (mode == SImode && TARGET_H8300S && amount >= 13))
5105 {
5106 switch (mode)
5107 {
5108 case HImode:
5109 /* This code works on any family. */
5110 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5111 output_asm_insn (insn_buf, operands);
5112 break;
5113
5114 case SImode:
3db11b5c 5115 /* This code works on the H8/300H and H8S. */
edd71f0f
KH		 5116 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5117 output_asm_insn (insn_buf, operands);
5118 break;
5119
5120 default:
8c440872 5121 gcc_unreachable ();
edd71f0f
KH		 5122 }
5123
5124 /* Adjust AMOUNT and flip the direction. */
5125 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5126 rotate_type =
5127 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5128 }
5129
01ab5574 5130 /* Output rotate insns. */
edd71f0f
KH		 5131 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
5132 {
5133 if (bits == 2)
5134 insn_buf = rotate_two[rotate_type][rotate_mode];
5135 else
5136 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
2c54abce 5137
edd71f0f
KH		 5138 for (; amount >= bits; amount -= bits)
5139 output_asm_insn (insn_buf, operands);
5140 }
5141
5142 return "";
5143}
caf7f21a 5144
e9eba255
KH		 5145/* Compute the length of a rotate insn. */
5146
caf7f21a
KH		 5147unsigned int
5148compute_a_rotate_length (rtx *operands)
5149{
5150 rtx src = operands[1];
343fd2c7 5151 rtx amount_rtx = operands[2];
caf7f21a
KH		 5152 enum machine_mode mode = GET_MODE (src);
5153 int amount;
5154 unsigned int length = 0;
5155
8c440872 5156 gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
caf7f21a 5157
343fd2c7 5158 amount = INTVAL (amount_rtx);
caf7f21a
KH		 5159
5160 /* Clean up AMOUNT. */
5161 if (amount < 0)
5162 amount = 0;
5163 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5164 amount = GET_MODE_BITSIZE (mode);
5165
5166 /* Determine the faster direction. After this phase, amount
5167 will be at most a half of GET_MODE_BITSIZE (mode). */
5168 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5169 /* Flip the direction. */
5170 amount = GET_MODE_BITSIZE (mode) - amount;
5171
5172 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5173 boost up the rotation. */
5174 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5175 || (mode == HImode && TARGET_H8300H && amount >= 6)
5176 || (mode == HImode && TARGET_H8300S && amount == 8)
5177 || (mode == SImode && TARGET_H8300H && amount >= 10)
5178 || (mode == SImode && TARGET_H8300S && amount >= 13))
5179 {
5180 /* Adjust AMOUNT and flip the direction. */
5181 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5182 length += 6;
5183 }
5184
5185 /* We use 2-bit rotations on the H8S. */
5186 if (TARGET_H8300S)
5187 amount = amount / 2 + amount % 2;
5188
5189 /* The H8/300 uses three insns to rotate one bit, taking 6
5190 length. */
5191 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
5192
5193 return length;
5194}
edd71f0f 5195\f
48837e29 5196/* Fix the operands of a gen_xxx so that it could become a bit
2c54abce 5197 operating insn. */
07aae5c2
SC		 5198
5199int
4093985c 5200fix_bit_operand (rtx *operands, enum rtx_code code)
07aae5c2 5201{
abc95ed3 5202 /* The bit_operand predicate accepts any memory during RTL generation, but
48837e29
DE		 5203 only 'U' memory afterwards, so if this is a MEM operand, we must force
5204 it to be valid for 'U' by reloading the address. */
07aae5c2 5205
4093985c
KH		 5206 if (code == AND
5207 ? single_zero_operand (operands[2], QImode)
5208 : single_one_operand (operands[2], QImode))
07aae5c2 5209 {
2e760b15
KH		 5210 /* OK to have a memory dest. */
5211 if (GET_CODE (operands[0]) == MEM
ceaaaeab 5212 && !satisfies_constraint_U (operands[0]))
48837e29 5213 {
2e760b15
KH		 5214 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
5215 copy_to_mode_reg (Pmode,
5216 XEXP (operands[0], 0)));
5217 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5218 operands[0] = mem;
5219 }
48837e29 5220
2e760b15 5221 if (GET_CODE (operands[1]) == MEM
ceaaaeab 5222 && !satisfies_constraint_U (operands[1]))
2e760b15
KH		 5223 {
5224 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
5225 copy_to_mode_reg (Pmode,
5226 XEXP (operands[1], 0)));
5227 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5228 operands[1] = mem;
48837e29 5229 }
2e760b15 5230 return 0;
48837e29 5231 }
07aae5c2 5232
48837e29 5233 /* Dest and src op must be register. */
07aae5c2 5234
48837e29
DE		 5235 operands[1] = force_reg (QImode, operands[1]);
5236 {
5237 rtx res = gen_reg_rtx (QImode);
fd57a6e4 5238 switch (code)
a3579575
KH		 5239 {
5240 case AND:
5241 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
5242 break;
5243 case IOR:
5244 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
5245 break;
5246 case XOR:
5247 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
5248 break;
5249 default:
8c440872 5250 gcc_unreachable ();
a3579575
KH		 5251 }
5252 emit_insn (gen_movqi (operands[0], res));
48837e29
DE		 5253 }
5254 return 1;
07aae5c2 5255}
f5b65a56 5256
f5b65a56
JL		 5257/* Return nonzero if FUNC is an interrupt function as specified
5258 by the "interrupt" attribute. */
5259
5260static int
cb713a8d 5261h8300_interrupt_function_p (tree func)
f5b65a56
JL		 5262{
5263 tree a;
5264
5265 if (TREE_CODE (func) != FUNCTION_DECL)
5266 return 0;
5267
91d231cb 5268 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
f5b65a56
JL		 5269 return a != NULL_TREE;
5270}
5271
3cfa3702
KH		 5272/* Return nonzero if FUNC is a saveall function as specified by the
5273 "saveall" attribute. */
5274
5275static int
5276h8300_saveall_function_p (tree func)
5277{
5278 tree a;
5279
5280 if (TREE_CODE (func) != FUNCTION_DECL)
5281 return 0;
5282
5283 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
5284 return a != NULL_TREE;
5285}
5286
fabe72bb
JL		 5287/* Return nonzero if FUNC is an OS_Task function as specified
5288 by the "OS_Task" attribute. */
5289
5290static int
cb713a8d 5291h8300_os_task_function_p (tree func)
fabe72bb
JL		 5292{
5293 tree a;
5294
5295 if (TREE_CODE (func) != FUNCTION_DECL)
5296 return 0;
5297
91d231cb 5298 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
fabe72bb
JL		 5299 return a != NULL_TREE;
5300}
5301
5302/* Return nonzero if FUNC is a monitor function as specified
5303 by the "monitor" attribute. */
5304
5305static int
cb713a8d 5306h8300_monitor_function_p (tree func)
fabe72bb
JL		 5307{
5308 tree a;
5309
5310 if (TREE_CODE (func) != FUNCTION_DECL)
5311 return 0;
5312
91d231cb 5313 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
fabe72bb
JL		 5314 return a != NULL_TREE;
5315}
5316
f5b65a56
JL		 5317/* Return nonzero if FUNC is a function that should be called
5318 through the function vector. */
5319
5320int
cb713a8d 5321h8300_funcvec_function_p (tree func)
f5b65a56
JL		 5322{
5323 tree a;
5324
5325 if (TREE_CODE (func) != FUNCTION_DECL)
5326 return 0;
5327
91d231cb 5328 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
f5b65a56
JL		 5329 return a != NULL_TREE;
5330}
5331
887a8bd9 5332/* Return nonzero if DECL is a variable that's in the eight bit
15dc331e
JL		 5333 data area. */
5334
5335int
cb713a8d 5336h8300_eightbit_data_p (tree decl)
15dc331e
JL		 5337{
5338 tree a;
5339
5340 if (TREE_CODE (decl) != VAR_DECL)
5341 return 0;
5342
91d231cb 5343 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
15dc331e
JL		 5344 return a != NULL_TREE;
5345}
5346
887a8bd9
JL		 5347/* Return nonzero if DECL is a variable that's in the tiny
5348 data area. */
5349
5350int
cb713a8d 5351h8300_tiny_data_p (tree decl)
887a8bd9
JL		 5352{
5353 tree a;
5354
5355 if (TREE_CODE (decl) != VAR_DECL)
5356 return 0;
5357
91d231cb 5358 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
887a8bd9
JL		 5359 return a != NULL_TREE;
5360}
5361
3cfa3702
KH		 5362/* Generate an 'interrupt_handler' attribute for decls. We convert
5363 all the pragmas to corresponding attributes. */
2c1d2fcb
DD		 5364
5365static void
cb713a8d 5366h8300_insert_attributes (tree node, tree *attributes)
2c1d2fcb 5367{
3cfa3702
KH		 5368 if (TREE_CODE (node) == FUNCTION_DECL)
5369 {
5370 if (pragma_interrupt)
5371 {
5372 pragma_interrupt = 0;
2c1d2fcb 5373
3cfa3702
KH		 5374 /* Add an 'interrupt_handler' attribute. */
5375 *attributes = tree_cons (get_identifier ("interrupt_handler"),
5376 NULL, *attributes);
5377 }
e392d367 5378
3cfa3702
KH		 5379 if (pragma_saveall)
5380 {
5381 pragma_saveall = 0;
5382
5383 /* Add an 'saveall' attribute. */
5384 *attributes = tree_cons (get_identifier ("saveall"),
5385 NULL, *attributes);
5386 }
5387 }
2c1d2fcb
DD		 5388}
5389
91d231cb 5390/* Supported attributes:
f5b65a56 5391
97c5ec1d 5392 interrupt_handler: output a prologue and epilogue suitable for an
f5b65a56
JL		 5393 interrupt handler.
5394
3cfa3702
KH		 5395 saveall: output a prologue and epilogue that saves and restores
5396 all registers except the stack pointer.
5397
97c5ec1d 5398 function_vector: This function should be called through the
887a8bd9
JL		 5399 function vector.
5400
5401 eightbit_data: This variable lives in the 8-bit data area and can
5402 be referenced with 8-bit absolute memory addresses.
5403
5404 tiny_data: This variable lives in the tiny data area and can be
5405 referenced with 16-bit absolute memory references. */
f5b65a56 5406
6bc7bc14 5407static const struct attribute_spec h8300_attribute_table[] =
f5b65a56 5408{
62d784f7
KT		 5409 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
5410 affects_type_identity } */
5411 { "interrupt_handler", 0, 0, true, false, false,
5412 h8300_handle_fndecl_attribute, false },
5413 { "saveall", 0, 0, true, false, false,
5414 h8300_handle_fndecl_attribute, false },
5415 { "OS_Task", 0, 0, true, false, false,
5416 h8300_handle_fndecl_attribute, false },
5417 { "monitor", 0, 0, true, false, false,
5418 h8300_handle_fndecl_attribute, false },
5419 { "function_vector", 0, 0, true, false, false,
5420 h8300_handle_fndecl_attribute, false },
5421 { "eightbit_data", 0, 0, true, false, false,
5422 h8300_handle_eightbit_data_attribute, false },
5423 { "tiny_data", 0, 0, true, false, false,
5424 h8300_handle_tiny_data_attribute, false },
5425 { NULL, 0, 0, false, false, false, NULL, false }
91d231cb 5426};
f5b65a56 5427
15dc331e 5428
91d231cb
JM		 5429/* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5430 struct attribute_spec.handler. */
5431static tree
cb713a8d
KH		 5432h8300_handle_fndecl_attribute (tree *node, tree name,
5433 tree args ATTRIBUTE_UNUSED,
5434 int flags ATTRIBUTE_UNUSED,
5435 bool *no_add_attrs)
91d231cb
JM		 5436{
5437 if (TREE_CODE (*node) != FUNCTION_DECL)
5438 {
29d08eba
JM		 5439 warning (OPT_Wattributes, "%qE attribute only applies to functions",
5440 name);
91d231cb
JM		 5441 *no_add_attrs = true;
5442 }
5443
5444 return NULL_TREE;
5445}
5446
5447/* Handle an "eightbit_data" attribute; arguments as in
5448 struct attribute_spec.handler. */
5449static tree
cb713a8d
KH		 5450h8300_handle_eightbit_data_attribute (tree *node, tree name,
5451 tree args ATTRIBUTE_UNUSED,
5452 int flags ATTRIBUTE_UNUSED,
5453 bool *no_add_attrs)
91d231cb
JM		 5454{
5455 tree decl = *node;
5456
5457 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
15dc331e 5458 {
64378c91 5459 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
91d231cb
JM		 5460 }
5461 else
5462 {
29d08eba
JM		 5463 warning (OPT_Wattributes, "%qE attribute ignored",
5464 name);
91d231cb 5465 *no_add_attrs = true;
887a8bd9
JL		 5466 }
5467
91d231cb
JM		 5468 return NULL_TREE;
5469}
5470
5471/* Handle an "tiny_data" attribute; arguments as in
5472 struct attribute_spec.handler. */
5473static tree
cb713a8d
KH		 5474h8300_handle_tiny_data_attribute (tree *node, tree name,
5475 tree args ATTRIBUTE_UNUSED,
5476 int flags ATTRIBUTE_UNUSED,
5477 bool *no_add_attrs)
91d231cb
JM		 5478{
5479 tree decl = *node;
5480
5481 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
887a8bd9 5482 {
64378c91 5483 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
91d231cb
JM		 5484 }
5485 else
5486 {
29d08eba
JM		 5487 warning (OPT_Wattributes, "%qE attribute ignored",
5488 name);
91d231cb 5489 *no_add_attrs = true;
15dc331e 5490 }
07e4d94e 5491
91d231cb 5492 return NULL_TREE;
f5b65a56
JL		 5493}
5494
dc66a1c4 5495/* Mark function vectors, and various small data objects. */
fb49053f
RH		 5496
5497static void
cb713a8d 5498h8300_encode_section_info (tree decl, rtx rtl, int first)
fb49053f 5499{
dc66a1c4
RH		 5500 int extra_flags = 0;
5501
c6a2438a 5502 default_encode_section_info (decl, rtl, first);
dc66a1c4 5503
fb49053f
RH		 5504 if (TREE_CODE (decl) == FUNCTION_DECL
5505 && h8300_funcvec_function_p (decl))
dc66a1c4 5506 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
fb49053f
RH		 5507 else if (TREE_CODE (decl) == VAR_DECL
5508 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
5509 {
5510 if (h8300_eightbit_data_p (decl))
dc66a1c4 5511 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
fb49053f 5512 else if (first && h8300_tiny_data_p (decl))
dc66a1c4 5513 extra_flags = SYMBOL_FLAG_TINY_DATA;
fb49053f 5514 }
772c5265 5515
dc66a1c4 5516 if (extra_flags)
c6a2438a 5517 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
772c5265
RH		 5518}
5519
e9eba255
KH		 5520/* Output a single-bit extraction. */
5521
441d04c6 5522const char *
cb713a8d 5523output_simode_bld (int bild, rtx operands[])
bd93f126 5524{
6be580c7
KH		 5525 if (TARGET_H8300)
5526 {
5527 /* Clear the destination register. */
5528 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
5529
5530 /* Now output the bit load or bit inverse load, and store it in
5531 the destination. */
5532 if (bild)
5533 output_asm_insn ("bild\t%Z2,%Y1", operands);
5534 else
5535 output_asm_insn ("bld\t%Z2,%Y1", operands);
bd93f126 5536
6be580c7
KH		 5537 output_asm_insn ("bst\t#0,%w0", operands);
5538 }
bd93f126 5539 else
6be580c7 5540 {
0eb933a0
KH		 5541 /* Determine if we can clear the destination first. */
5542 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
5543 && REGNO (operands[0]) != REGNO (operands[1]));
5544
5545 if (clear_first)
5546 output_asm_insn ("sub.l\t%S0,%S0", operands);
5547
6be580c7
KH		 5548 /* Output the bit load or bit inverse load. */
5549 if (bild)
5550 output_asm_insn ("bild\t%Z2,%Y1", operands);
5551 else
5552 output_asm_insn ("bld\t%Z2,%Y1", operands);
5553
0eb933a0
KH		 5554 if (!clear_first)
5555 output_asm_insn ("xor.l\t%S0,%S0", operands);
5556
5557 /* Perform the bit store. */
802a9907 5558 output_asm_insn ("rotxl.l\t%S0", operands);
6be580c7 5559 }
bd93f126
JL		 5560
5561 /* All done. */
5562 return "";
5563}
e6219736 5564
beed8fc0
AO		 5565/* Delayed-branch scheduling is more effective if we have some idea
5566 how long each instruction will be. Use a shorten_branches pass
5567 to get an initial estimate. */
5568
5569static void
5570h8300_reorg (void)
5571{
5572 if (flag_delayed_branch)
5573 shorten_branches (get_insns ());
5574}
5575
ede75ee8 5576#ifndef OBJECT_FORMAT_ELF
7c262518 5577static void
c18a5b6c
MM		 5578h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED,
5579 tree decl)
7c262518
RH		 5580{
5581 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5582 fprintf (asm_out_file, "\t.section %s\n", name);
5583}
ede75ee8 5584#endif /* ! OBJECT_FORMAT_ELF */
803d56f5 5585
7c143ed2
KH		 5586/* Nonzero if X is a constant address suitable as an 8-bit absolute,
5587 which is a special case of the 'R' operand. */
5588
803d56f5 5589int
cb713a8d 5590h8300_eightbit_constant_address_p (rtx x)
803d56f5 5591{
ff482c8d 5592 /* The ranges of the 8-bit area. */
d2d199a3
KH		 5593 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
5594 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
803d56f5
KH		 5595 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
5596 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
5597 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
5598 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
5599
5600 unsigned HOST_WIDE_INT addr;
5601
9675a91e 5602 /* We accept symbols declared with eightbit_data. */
dc66a1c4
RH		 5603 if (GET_CODE (x) == SYMBOL_REF)
5604 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
9675a91e 5605
803d56f5
KH		 5606 if (GET_CODE (x) != CONST_INT)
5607 return 0;
5608
5609 addr = INTVAL (x);
5610
5611 return (0
39ba95b5 5612 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
803d56f5
KH		 5613 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
5614 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
5615}
5616
7c143ed2
KH		 5617/* Nonzero if X is a constant address suitable as an 16-bit absolute
5618 on H8/300H and H8S. */
5619
803d56f5 5620int
cb713a8d 5621h8300_tiny_constant_address_p (rtx x)
803d56f5 5622{
3f7211f1 5623 /* The ranges of the 16-bit area. */
803d56f5
KH		 5624 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
5625 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
5626 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
5627 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
5628 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
5629 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
5630 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
5631 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
5632
5633 unsigned HOST_WIDE_INT addr;
5634
d6456562
KH		 5635 switch (GET_CODE (x))
5636 {
5637 case SYMBOL_REF:
a4bb41cc
KH		 5638 /* In the normal mode, any symbol fits in the 16-bit absolute
5639 address range. We also accept symbols declared with
5640 tiny_data. */
5641 return (TARGET_NORMAL_MODE
5642 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
56b8e164 5643
d6456562
KH		 5644 case CONST_INT:
5645 addr = INTVAL (x);
5646 return (TARGET_NORMAL_MODE
5647 || (TARGET_H8300H
5648 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
5649 || (TARGET_H8300S
5650 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
803d56f5 5651
a4bb41cc
KH		 5652 case CONST:
5653 return TARGET_NORMAL_MODE;
5654
d6456562
KH		 5655 default:
5656 return 0;
5657 }
803d56f5 5658
803d56f5 5659}
9b98dc74 5660
e9eba255
KH		 5661/* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5662 locations that can be accessed as a 16-bit word. */
5663
9b98dc74 5664int
cb713a8d 5665byte_accesses_mergeable_p (rtx addr1, rtx addr2)
9b98dc74
KH		 5666{
5667 HOST_WIDE_INT offset1, offset2;
5668 rtx reg1, reg2;
5669
5670 if (REG_P (addr1))
5671 {
5672 reg1 = addr1;
5673 offset1 = 0;
5674 }
5675 else if (GET_CODE (addr1) == PLUS
5676 && REG_P (XEXP (addr1, 0))
5677 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
5678 {
5679 reg1 = XEXP (addr1, 0);
5680 offset1 = INTVAL (XEXP (addr1, 1));
5681 }
5682 else
5683 return 0;
5684
5685 if (REG_P (addr2))
5686 {
5687 reg2 = addr2;
5688 offset2 = 0;
5689 }
5690 else if (GET_CODE (addr2) == PLUS
5691 && REG_P (XEXP (addr2, 0))
5692 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
5693 {
5694 reg2 = XEXP (addr2, 0);
5695 offset2 = INTVAL (XEXP (addr2, 1));
5696 }
5697 else
5698 return 0;
5699
5700 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
5701 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
5702 && offset1 % 2 == 0
5703 && offset1 + 1 == offset2)
5704 return 1;
5705
5706 return 0;
5707}
02529902
KH		 5708
5709/* Return nonzero if we have the same comparison insn as I3 two insns
19cff4db 5710 before I3. I3 is assumed to be a comparison insn. */
02529902
KH		 5711
5712int
5713same_cmp_preceding_p (rtx i3)
5714{
5715 rtx i1, i2;
5716
5717 /* Make sure we have a sequence of three insns. */
5718 i2 = prev_nonnote_insn (i3);
5719 if (i2 == NULL_RTX)
5720 return 0;
5721 i1 = prev_nonnote_insn (i2);
5722 if (i1 == NULL_RTX)
5723 return 0;
5724
5725 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5726 && any_condjump_p (i2) && onlyjump_p (i2));
5727}
c87ec0ba 5728
c06d5c85
KH		 5729/* Return nonzero if we have the same comparison insn as I1 two insns
5730 after I1. I1 is assumed to be a comparison insn. */
5731
5732int
5733same_cmp_following_p (rtx i1)
5734{
5735 rtx i2, i3;
5736
5737 /* Make sure we have a sequence of three insns. */
5738 i2 = next_nonnote_insn (i1);
5739 if (i2 == NULL_RTX)
5740 return 0;
5741 i3 = next_nonnote_insn (i2);
5742 if (i3 == NULL_RTX)
5743 return 0;
5744
5745 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5746 && any_condjump_p (i2) && onlyjump_p (i2));
5747}
5748
a466bea3 5749/* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
1ae58c30 5750 (or pops) N registers. OPERANDS are assumed to be an array of
a466bea3
KH		 5751 registers. */
5752
5753int
5754h8300_regs_ok_for_stm (int n, rtx operands[])
5755{
5756 switch (n)
5757 {
5758 case 2:
5759 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
5760 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
5761 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
5762 case 3:
5763 return ((REGNO (operands[0]) == 0
5764 && REGNO (operands[1]) == 1
5765 && REGNO (operands[2]) == 2)
5766 || (REGNO (operands[0]) == 4
5767 && REGNO (operands[1]) == 5
5768 && REGNO (operands[2]) == 6));
5769
5770 case 4:
5771 return (REGNO (operands[0]) == 0
5772 && REGNO (operands[1]) == 1
5773 && REGNO (operands[2]) == 2
5774 && REGNO (operands[3]) == 3);
8c440872
NS		 5775 default:
5776 gcc_unreachable ();
a466bea3 5777 }
a466bea3
KH		 5778}
5779
c87ec0ba
NY		 5780/* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5781
5782int
5783h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5784 unsigned int new_reg)
5785{
5786 /* Interrupt functions can only use registers that have already been
5787 saved by the prologue, even if they would normally be
5788 call-clobbered. */
5789
5790 if (h8300_current_function_interrupt_function_p ()
6fb5fa3c 5791 && !df_regs_ever_live_p (new_reg))
c87ec0ba
NY		 5792 return 0;
5793
80e58519 5794 return 1;
c87ec0ba 5795}
d0022200 5796
2e762884
DD		 5797/* Returns true if register REGNO is safe to be allocated as a scratch
5798 register in the current function. */
5799
5800static bool
5801h8300_hard_regno_scratch_ok (unsigned int regno)
5802{
5803 if (h8300_current_function_interrupt_function_p ()
5804 && ! WORD_REG_USED (regno))
5805 return false;
5806
5807 return true;
5808}
5809
5810
d0022200
KH		 5811/* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5812
5813static int
5814h8300_rtx_ok_for_base_p (rtx x, int strict)
5815{
5816 /* Strip off SUBREG if any. */
5817 if (GET_CODE (x) == SUBREG)
5818 x = SUBREG_REG (x);
5819
5820 return (REG_P (x)
5821 && (strict
5822 ? REG_OK_FOR_BASE_STRICT_P (x)
5823 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
5824}
5825
5826/* Return nozero if X is a legitimate address. On the H8/300, a
5827 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5828 CONSTANT_ADDRESS. */
5829
c6c3dba9
PB		 5830static bool
5831h8300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
d0022200
KH		 5832{
5833 /* The register indirect addresses like @er0 is always valid. */
5834 if (h8300_rtx_ok_for_base_p (x, strict))
5835 return 1;
5836
5837 if (CONSTANT_ADDRESS_P (x))
5838 return 1;
5839
beed8fc0
AO		 5840 if (TARGET_H8300SX
5841 && ( GET_CODE (x) == PRE_INC
5842 || GET_CODE (x) == PRE_DEC
5843 || GET_CODE (x) == POST_INC
5844 || GET_CODE (x) == POST_DEC)
5845 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
5846 return 1;
5847
d0022200
KH		 5848 if (GET_CODE (x) == PLUS
5849 && CONSTANT_ADDRESS_P (XEXP (x, 1))
beed8fc0
AO		 5850 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
5851 mode, 0), strict))
d0022200
KH		 5852 return 1;
5853
5854 return 0;
5855}
07ee3b58
KH		 5856
5857/* Worker function for HARD_REGNO_NREGS.
5858
5859 We pretend the MAC register is 32bits -- we don't have any data
5860 types on the H8 series to handle more than 32bits. */
5861
5862int
5863h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, enum machine_mode mode)
5864{
5865 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5866}
5867
5868/* Worker function for HARD_REGNO_MODE_OK. */
5869
5870int
5871h8300_hard_regno_mode_ok (int regno, enum machine_mode mode)
5872{
5873 if (TARGET_H8300)
5874 /* If an even reg, then anything goes. Otherwise the mode must be
5875 QI or HI. */
5876 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
5877 else
5878 /* MAC register can only be of SImode. Otherwise, anything
5879 goes. */
5880 return regno == MAC_REG ? mode == SImode : 1;
5881}
f9b4f8c1
RH		 5882
5883/* Helper function for the move patterns. Make sure a move is legitimate. */
5884
5885bool
5886h8300_move_ok (rtx dest, rtx src)
5887{
5888 rtx addr, other;
5889
5890 /* Validate that at least one operand is a register. */
5891 if (MEM_P (dest))
5892 {
5893 if (MEM_P (src) || CONSTANT_P (src))
5894 return false;
5895 addr = XEXP (dest, 0);
5896 other = src;
5897 }
5898 else if (MEM_P (src))
5899 {
5900 addr = XEXP (src, 0);
5901 other = dest;
5902 }
5903 else
5904 return true;
5905
5906 /* Validate that auto-inc doesn't affect OTHER. */
5907 if (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC)
5908 return true;
5909 addr = XEXP (addr, 0);
5910
5911 if (addr == stack_pointer_rtx)
5912 return register_no_sp_elim_operand (other, VOIDmode);
5913 else
5914 return !reg_overlap_mentioned_p(other, addr);
5915}
6e014ef3 5916\f
c15c90bb
ZW		 5917/* Perform target dependent optabs initialization. */
5918static void
5919h8300_init_libfuncs (void)
5920{
5921 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
5922 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
5923 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
5924 set_optab_libfunc (smod_optab, HImode, "__modhi3");
5925 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
5926}
5927\f
9eaa7740
AS		 5928/* Worker function for TARGET_FUNCTION_VALUE.
5929
5930 On the H8 the return value is in R0/R1. */
5931
5932static rtx
5933h8300_function_value (const_tree ret_type,
5934 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
5935 bool outgoing ATTRIBUTE_UNUSED)
5936{
5937 return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG);
5938}
5939
5940/* Worker function for TARGET_LIBCALL_VALUE.
5941
5942 On the H8 the return value is in R0/R1. */
5943
5944static rtx
5945h8300_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5946{
5947 return gen_rtx_REG (mode, R0_REG);
5948}
5949
5950/* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5951
5952 On the H8, R0 is the only register thus used. */
5953
5954static bool
5955h8300_function_value_regno_p (const unsigned int regno)
5956{
5957 return (regno == R0_REG);
5958}
5959
e9eba255
KH		 5960/* Worker function for TARGET_RETURN_IN_MEMORY. */
5961
34bf1fe3 5962static bool
586de218 5963h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
34bf1fe3
KH		 5964{
5965 return (TYPE_MODE (type) == BLKmode
5966 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
5967}
5968\f
9f6ef043
RH		 5969/* We emit the entire trampoline here. Depending on the pointer size,
5970 we use a different trampoline.
5971
5972 Pmode == HImode
5973 vvvv context
5974 1 0000 7903xxxx mov.w #0x1234,r3
5975 2 0004 5A00xxxx jmp @0x1234
5976 ^^^^ function
5977
5978 Pmode == SImode
5979 vvvvvvvv context
5980 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
5981 3 0006 5Axxxxxx jmp @0x123456
5982 ^^^^^^ function
5983*/
5984
5985static void
5986h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
5987{
5988 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
5989 rtx mem;
5990
5991 if (Pmode == HImode)
5992 {
5993 mem = adjust_address (m_tramp, HImode, 0);
5994 emit_move_insn (mem, GEN_INT (0x7903));
5995 mem = adjust_address (m_tramp, Pmode, 2);
5996 emit_move_insn (mem, cxt);
5997 mem = adjust_address (m_tramp, HImode, 4);
5998 emit_move_insn (mem, GEN_INT (0x5a00));
5999 mem = adjust_address (m_tramp, Pmode, 6);
6000 emit_move_insn (mem, fnaddr);
6001 }
6002 else
6003 {
6004 rtx tem;
6005
6006 mem = adjust_address (m_tramp, HImode, 0);
6007 emit_move_insn (mem, GEN_INT (0x7a03));
6008 mem = adjust_address (m_tramp, Pmode, 2);
6009 emit_move_insn (mem, cxt);
6010
6011 tem = copy_to_reg (fnaddr);
6012 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff)));
6013 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000)));
6014 mem = adjust_address (m_tramp, SImode, 6);
6015 emit_move_insn (mem, tem);
6016 }
6017}
6018\f
6e014ef3
KH		 6019/* Initialize the GCC target structure. */
6020#undef TARGET_ATTRIBUTE_TABLE
6021#define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
6022
6023#undef TARGET_ASM_ALIGNED_HI_OP
6024#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
6025
1bc7c5b6
ZW		 6026#undef TARGET_ASM_FILE_START
6027#define TARGET_ASM_FILE_START h8300_file_start
6028#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
6029#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
6030
6e014ef3
KH		 6031#undef TARGET_ASM_FILE_END
6032#define TARGET_ASM_FILE_END h8300_file_end
6033
88cb339e
N		 6034#undef TARGET_PRINT_OPERAND
6035#define TARGET_PRINT_OPERAND h8300_print_operand
6036#undef TARGET_PRINT_OPERAND_ADDRESS
6037#define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
6038#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
6039#define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
6040
6e014ef3
KH		 6041#undef TARGET_ENCODE_SECTION_INFO
6042#define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
6043
6044#undef TARGET_INSERT_ATTRIBUTES
6045#define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
6046
88cb339e
N		 6047#undef TARGET_REGISTER_MOVE_COST
6048#define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
6049
6e014ef3
KH		 6050#undef TARGET_RTX_COSTS
6051#define TARGET_RTX_COSTS h8300_rtx_costs
6052
c15c90bb
ZW		 6053#undef TARGET_INIT_LIBFUNCS
6054#define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
6055
9eaa7740
AS		 6056#undef TARGET_FUNCTION_VALUE
6057#define TARGET_FUNCTION_VALUE h8300_function_value
6058
6059#undef TARGET_LIBCALL_VALUE
6060#define TARGET_LIBCALL_VALUE h8300_libcall_value
6061
6062#undef TARGET_FUNCTION_VALUE_REGNO_P
6063#define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
6064
34bf1fe3
KH		 6065#undef TARGET_RETURN_IN_MEMORY
6066#define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
6067
56f9413b
NF		 6068#undef TARGET_FUNCTION_ARG
6069#define TARGET_FUNCTION_ARG h8300_function_arg
6070
6071#undef TARGET_FUNCTION_ARG_ADVANCE
6072#define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
6073
beed8fc0
AO		 6074#undef TARGET_MACHINE_DEPENDENT_REORG
6075#define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
6076
2e762884
DD		 6077#undef TARGET_HARD_REGNO_SCRATCH_OK
6078#define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
6079
c6c3dba9
PB		 6080#undef TARGET_LEGITIMATE_ADDRESS_P
6081#define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
6082
7b5cbb57
AS		 6083#undef TARGET_CAN_ELIMINATE
6084#define TARGET_CAN_ELIMINATE h8300_can_eliminate
6085
5efd84c5
NF		 6086#undef TARGET_CONDITIONAL_REGISTER_USAGE
6087#define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
6088
9f6ef043
RH		 6089#undef TARGET_TRAMPOLINE_INIT
6090#define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6091
c5387660
JM		 6092#undef TARGET_OPTION_OVERRIDE
6093#define TARGET_OPTION_OVERRIDE h8300_option_override
6094
f52d97da
AS		 6095#undef TARGET_MODE_DEPENDENT_ADDRESS_P
6096#define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6097
6e014ef3 6098struct gcc_target targetm = TARGET_INITIALIZER;
Mirror of https://gcc.gnu.org/git/gcc.git