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340f6494 | 1 | /* Subroutines for insn-output.c for Renesas H8/300. |
23a5b65a | 2 | Copyright (C) 1992-2014 Free Software Foundation, Inc. |
48837e29 DE |
3 | Contributed by Steve Chamberlain (sac@cygnus.com), |
4 | Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). | |
07aae5c2 | 5 | |
8aa063fb | 6 | This file is part of GCC. |
07aae5c2 | 7 | |
8aa063fb | 8 | GCC is free software; you can redistribute it and/or modify |
07aae5c2 | 9 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
07aae5c2 SC |
11 | any later version. |
12 | ||
8aa063fb | 13 | GCC is distributed in the hope that it will be useful, |
07aae5c2 SC |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
07aae5c2 | 21 | |
07aae5c2 | 22 | #include "config.h" |
c5c76735 | 23 | #include "system.h" |
4977bab6 ZW |
24 | #include "coretypes.h" |
25 | #include "tm.h" | |
07aae5c2 | 26 | #include "rtl.h" |
bf6bb899 | 27 | #include "tree.h" |
d8a2d370 DN |
28 | #include "stor-layout.h" |
29 | #include "varasm.h" | |
30 | #include "calls.h" | |
31 | #include "stringpool.h" | |
07aae5c2 SC |
32 | #include "regs.h" |
33 | #include "hard-reg-set.h" | |
07aae5c2 SC |
34 | #include "insn-config.h" |
35 | #include "conditions.h" | |
07aae5c2 SC |
36 | #include "output.h" |
37 | #include "insn-attr.h" | |
38 | #include "flags.h" | |
39 | #include "recog.h" | |
40 | #include "expr.h" | |
83685514 AM |
41 | #include "hashtab.h" |
42 | #include "hash-set.h" | |
43 | #include "vec.h" | |
44 | #include "machmode.h" | |
45 | #include "input.h" | |
bf6bb899 | 46 | #include "function.h" |
c15c90bb | 47 | #include "optabs.h" |
718f9c0f | 48 | #include "diagnostic-core.h" |
39dabefd | 49 | #include "c-family/c-pragma.h" /* ??? */ |
441d04c6 | 50 | #include "tm_p.h" |
ceaaaeab | 51 | #include "tm-constrs.h" |
f2a9645f | 52 | #include "ggc.h" |
672a6f42 NB |
53 | #include "target.h" |
54 | #include "target-def.h" | |
60393bbc AM |
55 | #include "dominance.h" |
56 | #include "cfg.h" | |
57 | #include "cfgrtl.h" | |
58 | #include "cfganal.h" | |
59 | #include "lcm.h" | |
60 | #include "cfgbuild.h" | |
61 | #include "cfgcleanup.h" | |
62 | #include "predict.h" | |
63 | #include "basic-block.h" | |
9690aa8e | 64 | #include "df.h" |
9b2b7279 | 65 | #include "builtins.h" |
07aae5c2 | 66 | |
beed8fc0 AO |
67 | /* Classifies a h8300_src_operand or h8300_dst_operand. |
68 | ||
69 | H8OP_IMMEDIATE | |
70 | A constant operand of some sort. | |
71 | ||
72 | H8OP_REGISTER | |
73 | An ordinary register. | |
74 | ||
75 | H8OP_MEM_ABSOLUTE | |
76 | A memory reference with a constant address. | |
77 | ||
78 | H8OP_MEM_BASE | |
79 | A memory reference with a register as its address. | |
80 | ||
81 | H8OP_MEM_COMPLEX | |
82 | Some other kind of memory reference. */ | |
83 | enum h8300_operand_class | |
84 | { | |
85 | H8OP_IMMEDIATE, | |
86 | H8OP_REGISTER, | |
87 | H8OP_MEM_ABSOLUTE, | |
88 | H8OP_MEM_BASE, | |
89 | H8OP_MEM_COMPLEX, | |
90 | NUM_H8OPS | |
91 | }; | |
92 | ||
beed8fc0 AO |
93 | /* For a general two-operand instruction, element [X][Y] gives |
94 | the length of the opcode fields when the first operand has class | |
95 | (X + 1) and the second has class Y. */ | |
96 | typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS]; | |
97 | ||
07aae5c2 | 98 | /* Forward declarations. */ |
cb713a8d KH |
99 | static const char *byte_reg (rtx, int); |
100 | static int h8300_interrupt_function_p (tree); | |
3cfa3702 | 101 | static int h8300_saveall_function_p (tree); |
cb713a8d KH |
102 | static int h8300_monitor_function_p (tree); |
103 | static int h8300_os_task_function_p (tree); | |
c72ea086 | 104 | static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool); |
e68d4dd1 | 105 | static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT); |
cb713a8d | 106 | static unsigned int compute_saved_regs (void); |
cb713a8d KH |
107 | static const char *cond_string (enum rtx_code); |
108 | static unsigned int h8300_asm_insn_count (const char *); | |
cb713a8d KH |
109 | static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *); |
110 | static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *); | |
111 | static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *); | |
88cb339e N |
112 | static void h8300_print_operand_address (FILE *, rtx); |
113 | static void h8300_print_operand (FILE *, rtx, int); | |
114 | static bool h8300_print_operand_punct_valid_p (unsigned char code); | |
ede75ee8 | 115 | #ifndef OBJECT_FORMAT_ELF |
c18a5b6c | 116 | static void h8300_asm_named_section (const char *, unsigned int, tree); |
ede75ee8 | 117 | #endif |
88cb339e | 118 | static int h8300_register_move_cost (enum machine_mode, reg_class_t, reg_class_t); |
cb713a8d KH |
119 | static int h8300_and_costs (rtx); |
120 | static int h8300_shift_costs (rtx); | |
ac447f25 | 121 | static void h8300_push_pop (int, int, bool, bool); |
beed8fc0 AO |
122 | static int h8300_stack_offset_p (rtx, int); |
123 | static int h8300_ldm_stm_regno (rtx, int, int, int); | |
beed8fc0 AO |
124 | static void h8300_reorg (void); |
125 | static unsigned int h8300_constant_length (rtx); | |
126 | static unsigned int h8300_displacement_length (rtx, int); | |
127 | static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *); | |
128 | static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *); | |
129 | static unsigned int h8300_unary_length (rtx); | |
130 | static unsigned int h8300_short_immediate_length (rtx); | |
131 | static unsigned int h8300_bitfield_length (rtx, rtx); | |
e7041fcc | 132 | static unsigned int h8300_binary_length (rtx_insn *, const h8300_length_table *); |
beed8fc0 AO |
133 | static bool h8300_short_move_mem_p (rtx, enum rtx_code); |
134 | static unsigned int h8300_move_length (rtx *, const h8300_length_table *); | |
2e762884 | 135 | static bool h8300_hard_regno_scratch_ok (unsigned int); |
f52d97da | 136 | static rtx h8300_get_index (rtx, enum machine_mode mode, int *); |
f5b65a56 | 137 | |
48837e29 DE |
138 | /* CPU_TYPE, says what cpu we're compiling for. */ |
139 | int cpu_type; | |
140 | ||
e392d367 KH |
141 | /* True if a #pragma interrupt has been seen for the current function. */ |
142 | static int pragma_interrupt; | |
07aae5c2 SC |
143 | |
144 | /* True if a #pragma saveall has been seen for the current function. */ | |
0869f126 | 145 | static int pragma_saveall; |
07aae5c2 | 146 | |
441d04c6 | 147 | static const char *const names_big[] = |
07e4d94e | 148 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" }; |
48837e29 | 149 | |
441d04c6 | 150 | static const char *const names_extended[] = |
07e4d94e | 151 | { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" }; |
48837e29 | 152 | |
441d04c6 | 153 | static const char *const names_upper_extended[] = |
07e4d94e | 154 | { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" }; |
48837e29 DE |
155 | |
156 | /* Points to one of the above. */ | |
157 | /* ??? The above could be put in an array indexed by CPU_TYPE. */ | |
441d04c6 | 158 | const char * const *h8_reg_names; |
48837e29 DE |
159 | |
160 | /* Various operations needed by the following, indexed by CPU_TYPE. */ | |
48837e29 | 161 | |
441d04c6 | 162 | const char *h8_push_op, *h8_pop_op, *h8_mov_op; |
dc66a1c4 | 163 | |
beed8fc0 AO |
164 | /* Value of MOVE_RATIO. */ |
165 | int h8300_move_ratio; | |
672a6f42 | 166 | \f |
c4dfc70c DD |
167 | /* See below where shifts are handled for explanation of this enum. */ |
168 | ||
169 | enum shift_alg | |
170 | { | |
171 | SHIFT_INLINE, | |
172 | SHIFT_ROT_AND, | |
173 | SHIFT_SPECIAL, | |
174 | SHIFT_LOOP | |
175 | }; | |
176 | ||
177 | /* Symbols of the various shifts which can be used as indices. */ | |
178 | ||
179 | enum shift_type | |
180 | { | |
181 | SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT | |
182 | }; | |
183 | ||
184 | /* Macros to keep the shift algorithm tables small. */ | |
185 | #define INL SHIFT_INLINE | |
186 | #define ROT SHIFT_ROT_AND | |
187 | #define LOP SHIFT_LOOP | |
188 | #define SPC SHIFT_SPECIAL | |
189 | ||
190 | /* The shift algorithms for each machine, mode, shift type, and shift | |
191 | count are defined below. The three tables below correspond to | |
192 | QImode, HImode, and SImode, respectively. Each table is organized | |
f411c849 | 193 | by, in the order of indices, machine, shift type, and shift count. */ |
c4dfc70c DD |
194 | |
195 | static enum shift_alg shift_alg_qi[3][3][8] = { | |
196 | { | |
197 | /* TARGET_H8300 */ | |
198 | /* 0 1 2 3 4 5 6 7 */ | |
199 | { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ | |
200 | { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ | |
201 | { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */ | |
202 | }, | |
203 | { | |
204 | /* TARGET_H8300H */ | |
205 | /* 0 1 2 3 4 5 6 7 */ | |
206 | { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ | |
207 | { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ | |
208 | { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */ | |
209 | }, | |
210 | { | |
211 | /* TARGET_H8300S */ | |
212 | /* 0 1 2 3 4 5 6 7 */ | |
213 | { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */ | |
214 | { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */ | |
215 | { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */ | |
216 | } | |
217 | }; | |
218 | ||
219 | static enum shift_alg shift_alg_hi[3][3][16] = { | |
220 | { | |
221 | /* TARGET_H8300 */ | |
222 | /* 0 1 2 3 4 5 6 7 */ | |
223 | /* 8 9 10 11 12 13 14 15 */ | |
224 | { INL, INL, INL, INL, INL, INL, INL, SPC, | |
225 | SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */ | |
226 | { INL, INL, INL, INL, INL, LOP, LOP, SPC, | |
227 | SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */ | |
228 | { INL, INL, INL, INL, INL, LOP, LOP, SPC, | |
229 | SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ | |
230 | }, | |
231 | { | |
232 | /* TARGET_H8300H */ | |
233 | /* 0 1 2 3 4 5 6 7 */ | |
234 | /* 8 9 10 11 12 13 14 15 */ | |
235 | { INL, INL, INL, INL, INL, INL, INL, SPC, | |
236 | SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ | |
237 | { INL, INL, INL, INL, INL, INL, INL, SPC, | |
238 | SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ | |
239 | { INL, INL, INL, INL, INL, INL, INL, SPC, | |
240 | SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ | |
241 | }, | |
242 | { | |
243 | /* TARGET_H8300S */ | |
244 | /* 0 1 2 3 4 5 6 7 */ | |
245 | /* 8 9 10 11 12 13 14 15 */ | |
246 | { INL, INL, INL, INL, INL, INL, INL, INL, | |
247 | SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ | |
248 | { INL, INL, INL, INL, INL, INL, INL, INL, | |
249 | SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ | |
250 | { INL, INL, INL, INL, INL, INL, INL, INL, | |
251 | SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ | |
252 | } | |
253 | }; | |
254 | ||
255 | static enum shift_alg shift_alg_si[3][3][32] = { | |
256 | { | |
257 | /* TARGET_H8300 */ | |
258 | /* 0 1 2 3 4 5 6 7 */ | |
259 | /* 8 9 10 11 12 13 14 15 */ | |
260 | /* 16 17 18 19 20 21 22 23 */ | |
261 | /* 24 25 26 27 28 29 30 31 */ | |
262 | { INL, INL, INL, LOP, LOP, LOP, LOP, LOP, | |
263 | SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP, | |
264 | SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP, | |
265 | SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */ | |
266 | { INL, INL, INL, LOP, LOP, LOP, LOP, LOP, | |
267 | SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC, | |
268 | SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP, | |
269 | SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */ | |
270 | { INL, INL, INL, LOP, LOP, LOP, LOP, LOP, | |
271 | SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, | |
272 | SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP, | |
273 | SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */ | |
274 | }, | |
275 | { | |
276 | /* TARGET_H8300H */ | |
277 | /* 0 1 2 3 4 5 6 7 */ | |
278 | /* 8 9 10 11 12 13 14 15 */ | |
279 | /* 16 17 18 19 20 21 22 23 */ | |
280 | /* 24 25 26 27 28 29 30 31 */ | |
281 | { INL, INL, INL, INL, INL, LOP, LOP, LOP, | |
282 | SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, | |
283 | SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP, | |
1e5bdc40 | 284 | SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */ |
c4dfc70c DD |
285 | { INL, INL, INL, INL, INL, LOP, LOP, LOP, |
286 | SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, | |
287 | SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP, | |
1e5bdc40 | 288 | SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */ |
c4dfc70c DD |
289 | { INL, INL, INL, INL, INL, LOP, LOP, LOP, |
290 | SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP, | |
291 | SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP, | |
292 | SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */ | |
293 | }, | |
294 | { | |
295 | /* TARGET_H8300S */ | |
296 | /* 0 1 2 3 4 5 6 7 */ | |
297 | /* 8 9 10 11 12 13 14 15 */ | |
298 | /* 16 17 18 19 20 21 22 23 */ | |
299 | /* 24 25 26 27 28 29 30 31 */ | |
300 | { INL, INL, INL, INL, INL, INL, INL, INL, | |
301 | INL, INL, INL, LOP, LOP, LOP, LOP, SPC, | |
302 | SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP, | |
1e5bdc40 | 303 | SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */ |
c4dfc70c DD |
304 | { INL, INL, INL, INL, INL, INL, INL, INL, |
305 | INL, INL, INL, LOP, LOP, LOP, LOP, SPC, | |
306 | SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP, | |
1e5bdc40 | 307 | SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */ |
c4dfc70c DD |
308 | { INL, INL, INL, INL, INL, INL, INL, INL, |
309 | INL, INL, INL, LOP, LOP, LOP, LOP, LOP, | |
310 | SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP, | |
311 | SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */ | |
312 | } | |
313 | }; | |
314 | ||
315 | #undef INL | |
316 | #undef ROT | |
317 | #undef LOP | |
318 | #undef SPC | |
319 | ||
320 | enum h8_cpu | |
321 | { | |
322 | H8_300, | |
323 | H8_300H, | |
324 | H8_S | |
325 | }; | |
326 | ||
48837e29 DE |
327 | /* Initialize various cpu specific globals at start up. */ |
328 | ||
c5387660 JM |
329 | static void |
330 | h8300_option_override (void) | |
48837e29 | 331 | { |
cbf1b2da KH |
332 | static const char *const h8_push_ops[2] = { "push" , "push.l" }; |
333 | static const char *const h8_pop_ops[2] = { "pop" , "pop.l" }; | |
334 | static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" }; | |
335 | ||
f4ea8112 SKS |
336 | #ifndef OBJECT_FORMAT_ELF |
337 | if (TARGET_H8300SX) | |
338 | { | |
339 | error ("-msx is not supported in coff"); | |
340 | target_flags |= MASK_H8300S; | |
341 | } | |
342 | #endif | |
343 | ||
48837e29 DE |
344 | if (TARGET_H8300) |
345 | { | |
346 | cpu_type = (int) CPU_H8300; | |
347 | h8_reg_names = names_big; | |
348 | } | |
349 | else | |
350 | { | |
3db11b5c | 351 | /* For this we treat the H8/300H and H8S the same. */ |
48837e29 DE |
352 | cpu_type = (int) CPU_H8300H; |
353 | h8_reg_names = names_extended; | |
354 | } | |
355 | h8_push_op = h8_push_ops[cpu_type]; | |
356 | h8_pop_op = h8_pop_ops[cpu_type]; | |
357 | h8_mov_op = h8_mov_ops[cpu_type]; | |
17f0f8fa KH |
358 | |
359 | if (!TARGET_H8300S && TARGET_MAC) | |
400500c4 | 360 | { |
c725bd79 | 361 | error ("-ms2600 is used without -ms"); |
5463c726 | 362 | target_flags |= MASK_H8300S_1; |
400500c4 | 363 | } |
920e86b8 | 364 | |
39ba95b5 VK |
365 | if (TARGET_H8300 && TARGET_NORMAL_MODE) |
366 | { | |
f4ea8112 | 367 | error ("-mn is used without -mh or -ms or -msx"); |
39ba95b5 VK |
368 | target_flags ^= MASK_NORMAL_MODE; |
369 | } | |
c4dfc70c | 370 | |
f4ea8112 SKS |
371 | if (! TARGET_H8300S && TARGET_EXR) |
372 | { | |
373 | error ("-mexr is used without -ms"); | |
374 | target_flags |= MASK_H8300S_1; | |
375 | } | |
376 | ||
377 | if (TARGET_H8300 && TARGET_INT32) | |
378 | { | |
379 | error ("-mint32 is not supported for H8300 and H8300L targets"); | |
380 | target_flags ^= MASK_INT32; | |
381 | } | |
382 | ||
383 | if ((!TARGET_H8300S && TARGET_EXR) && (!TARGET_H8300SX && TARGET_EXR)) | |
384 | { | |
385 | error ("-mexr is used without -ms or -msx"); | |
386 | target_flags |= MASK_H8300S_1; | |
387 | } | |
388 | ||
389 | if ((!TARGET_H8300S && TARGET_NEXR) && (!TARGET_H8300SX && TARGET_NEXR)) | |
390 | { | |
391 | warning (OPT_mno_exr, "-mno-exr valid only with -ms or -msx \ | |
392 | - Option ignored!"); | |
393 | } | |
394 | ||
8bd06267 | 395 | /* Some of the shifts are optimized for speed by default. |
c4dfc70c | 396 | See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html |
8bd06267 | 397 | If optimizing for size, change shift_alg for those shift to |
c4dfc70c | 398 | SHIFT_LOOP. */ |
b6894857 | 399 | if (optimize_size) |
c4dfc70c | 400 | { |
b6894857 KH |
401 | /* H8/300 */ |
402 | shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP; | |
403 | shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP; | |
404 | shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP; | |
405 | shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP; | |
c4dfc70c | 406 | |
b6894857 KH |
407 | shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP; |
408 | shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP; | |
c4dfc70c | 409 | |
b6894857 KH |
410 | shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP; |
411 | shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; | |
c4dfc70c | 412 | |
b6894857 KH |
413 | /* H8/300H */ |
414 | shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP; | |
415 | shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP; | |
c4dfc70c | 416 | |
b6894857 KH |
417 | shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP; |
418 | shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP; | |
c4dfc70c | 419 | |
b6894857 KH |
420 | shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP; |
421 | shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP; | |
422 | shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP; | |
423 | shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; | |
c4dfc70c DD |
424 | |
425 | /* H8S */ | |
b6894857 | 426 | shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; |
c4dfc70c | 427 | } |
beed8fc0 AO |
428 | |
429 | /* Work out a value for MOVE_RATIO. */ | |
430 | if (!TARGET_H8300SX) | |
431 | { | |
432 | /* Memory-memory moves are quite expensive without the | |
433 | h8sx instructions. */ | |
434 | h8300_move_ratio = 3; | |
435 | } | |
436 | else if (flag_omit_frame_pointer) | |
437 | { | |
438 | /* movmd sequences are fairly cheap when er6 isn't fixed. They can | |
439 | sometimes be as short as two individual memory-to-memory moves, | |
440 | but since they use all the call-saved registers, it seems better | |
441 | to allow up to three moves here. */ | |
442 | h8300_move_ratio = 4; | |
443 | } | |
444 | else if (optimize_size) | |
445 | { | |
446 | /* In this case we don't use movmd sequences since they tend | |
447 | to be longer than calls to memcpy(). Memory-to-memory | |
448 | moves are cheaper than for !TARGET_H8300SX, so it makes | |
449 | sense to have a slightly higher threshold. */ | |
450 | h8300_move_ratio = 4; | |
451 | } | |
452 | else | |
453 | { | |
454 | /* We use movmd sequences for some moves since it can be quicker | |
455 | than calling memcpy(). The sequences will need to save and | |
456 | restore er6 though, so bump up the cost. */ | |
457 | h8300_move_ratio = 6; | |
458 | } | |
0685e770 DD |
459 | |
460 | /* This target defaults to strict volatile bitfields. */ | |
36acc1a2 | 461 | if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2)) |
0685e770 | 462 | flag_strict_volatile_bitfields = 1; |
beed8fc0 AO |
463 | } |
464 | ||
e9eba255 KH |
465 | /* Return the byte register name for a register rtx X. B should be 0 |
466 | if you want a lower byte register. B should be 1 if you want an | |
467 | upper byte register. */ | |
468 | ||
9c188705 | 469 | static const char * |
cb713a8d | 470 | byte_reg (rtx x, int b) |
07aae5c2 | 471 | { |
9cbcd983 KH |
472 | static const char *const names_small[] = { |
473 | "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h", | |
474 | "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h" | |
475 | }; | |
07aae5c2 | 476 | |
8c440872 | 477 | gcc_assert (REG_P (x)); |
500fc80f | 478 | |
07aae5c2 SC |
479 | return names_small[REGNO (x) * 2 + b]; |
480 | } | |
481 | ||
482 | /* REGNO must be saved/restored across calls if this macro is true. */ | |
48837e29 | 483 | |
9cbcd983 | 484 | #define WORD_REG_USED(regno) \ |
d60004ee | 485 | (regno < SP_REG \ |
9cbcd983 KH |
486 | /* No need to save registers if this function will not return. */ \ |
487 | && ! TREE_THIS_VOLATILE (current_function_decl) \ | |
3cfa3702 | 488 | && (h8300_saveall_function_p (current_function_decl) \ |
9cbcd983 | 489 | /* Save any call saved register that was used. */ \ |
6fb5fa3c | 490 | || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \ |
9cbcd983 | 491 | /* Save the frame pointer if it was used. */ \ |
6fb5fa3c | 492 | || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \ |
9cbcd983 | 493 | /* Save any register used in an interrupt handler. */ \ |
e392d367 | 494 | || (h8300_current_function_interrupt_function_p () \ |
6fb5fa3c | 495 | && df_regs_ever_live_p (regno)) \ |
9cbcd983 KH |
496 | /* Save call clobbered registers in non-leaf interrupt \ |
497 | handlers. */ \ | |
e392d367 | 498 | || (h8300_current_function_interrupt_function_p () \ |
9cbcd983 | 499 | && call_used_regs[regno] \ |
416ff32e | 500 | && !crtl->is_leaf))) |
07aae5c2 | 501 | |
18674659 | 502 | /* We use this to wrap all emitted insns in the prologue. */ |
e7041fcc DM |
503 | static rtx_insn * |
504 | F (rtx_insn *x, bool set_it) | |
18674659 | 505 | { |
c72ea086 DD |
506 | if (set_it) |
507 | RTX_FRAME_RELATED_P (x) = 1; | |
18674659 DD |
508 | return x; |
509 | } | |
510 | ||
511 | /* Mark all the subexpressions of the PARALLEL rtx PAR as | |
512 | frame-related. Return PAR. | |
513 | ||
514 | dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a | |
515 | PARALLEL rtx other than the first if they do not have the | |
516 | FRAME_RELATED flag set on them. */ | |
517 | static rtx | |
518 | Fpa (rtx par) | |
519 | { | |
520 | int len = XVECLEN (par, 0); | |
521 | int i; | |
522 | ||
523 | for (i = 0; i < len; i++) | |
e7041fcc | 524 | F (as_a <rtx_insn *> (XVECEXP (par, 0, i)), true); |
18674659 DD |
525 | |
526 | return par; | |
527 | } | |
528 | ||
07aae5c2 | 529 | /* Output assembly language to FILE for the operation OP with operand size |
48837e29 | 530 | SIZE to adjust the stack pointer. */ |
48837e29 | 531 | |
07aae5c2 | 532 | static void |
c72ea086 | 533 | h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue) |
07aae5c2 | 534 | { |
72b1de44 KH |
535 | /* If the frame size is 0, we don't have anything to do. */ |
536 | if (size == 0) | |
f8b58e56 | 537 | return; |
72b1de44 | 538 | |
68ee6df6 KH |
539 | /* H8/300 cannot add/subtract a large constant with a single |
540 | instruction. If a temporary register is available, load the | |
541 | constant to it and then do the addition. */ | |
542 | if (TARGET_H8300 | |
543 | && size > 4 | |
544 | && !h8300_current_function_interrupt_function_p () | |
6de9cd9a | 545 | && !(cfun->static_chain_decl != NULL && sign < 0)) |
f8f26adc | 546 | { |
68ee6df6 | 547 | rtx r3 = gen_rtx_REG (Pmode, 3); |
c72ea086 | 548 | F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue); |
18674659 | 549 | F (emit_insn (gen_addhi3 (stack_pointer_rtx, |
c72ea086 | 550 | stack_pointer_rtx, r3)), in_prologue); |
7b3d4613 KH |
551 | } |
552 | else | |
553 | { | |
68ee6df6 KH |
554 | /* The stack adjustment made here is further optimized by the |
555 | splitter. In case of H8/300, the splitter always splits the | |
18674659 DD |
556 | addition emitted here to make the adjustment interrupt-safe. |
557 | FIXME: We don't always tag those, because we don't know what | |
558 | the splitter will do. */ | |
72b1de44 | 559 | if (Pmode == HImode) |
18674659 | 560 | { |
e7041fcc DM |
561 | rtx_insn *x = emit_insn (gen_addhi3 (stack_pointer_rtx, |
562 | stack_pointer_rtx, | |
563 | GEN_INT (sign * size))); | |
18674659 | 564 | if (size < 4) |
c72ea086 | 565 | F (x, in_prologue); |
18674659 | 566 | } |
72b1de44 | 567 | else |
18674659 | 568 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
c72ea086 | 569 | stack_pointer_rtx, GEN_INT (sign * size))), in_prologue); |
07aae5c2 SC |
570 | } |
571 | } | |
572 | ||
8682223f KH |
573 | /* Round up frame size SIZE. */ |
574 | ||
e68d4dd1 UB |
575 | static HOST_WIDE_INT |
576 | round_frame_size (HOST_WIDE_INT size) | |
8682223f | 577 | { |
489eda65 KH |
578 | return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1) |
579 | & -STACK_BOUNDARY / BITS_PER_UNIT); | |
8682223f KH |
580 | } |
581 | ||
582 | /* Compute which registers to push/pop. | |
583 | Return a bit vector of registers. */ | |
584 | ||
585 | static unsigned int | |
cb713a8d | 586 | compute_saved_regs (void) |
8682223f KH |
587 | { |
588 | unsigned int saved_regs = 0; | |
589 | int regno; | |
590 | ||
591 | /* Construct a bit vector of registers to be pushed/popped. */ | |
1807b726 | 592 | for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++) |
8682223f KH |
593 | { |
594 | if (WORD_REG_USED (regno)) | |
595 | saved_regs |= 1 << regno; | |
596 | } | |
597 | ||
598 | /* Don't push/pop the frame pointer as it is treated separately. */ | |
599 | if (frame_pointer_needed) | |
1807b726 | 600 | saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM); |
8682223f KH |
601 | |
602 | return saved_regs; | |
603 | } | |
604 | ||
68ee6df6 | 605 | /* Emit an insn to push register RN. */ |
8682223f | 606 | |
8f1594b2 | 607 | static rtx |
cb713a8d | 608 | push (int rn) |
8682223f | 609 | { |
68ee6df6 KH |
610 | rtx reg = gen_rtx_REG (word_mode, rn); |
611 | rtx x; | |
612 | ||
513f31eb | 613 | if (TARGET_H8300) |
68ee6df6 | 614 | x = gen_push_h8300 (reg); |
f24f0897 | 615 | else if (!TARGET_NORMAL_MODE) |
32da7865 | 616 | x = gen_push_h8300hs_advanced (reg); |
f24f0897 KH |
617 | else |
618 | x = gen_push_h8300hs_normal (reg); | |
ac447f25 | 619 | x = F (emit_insn (x), true); |
9690aa8e | 620 | add_reg_note (x, REG_INC, stack_pointer_rtx); |
8f1594b2 | 621 | return x; |
8682223f KH |
622 | } |
623 | ||
68ee6df6 | 624 | /* Emit an insn to pop register RN. */ |
8682223f | 625 | |
8f1594b2 | 626 | static rtx |
cb713a8d | 627 | pop (int rn) |
8682223f | 628 | { |
68ee6df6 KH |
629 | rtx reg = gen_rtx_REG (word_mode, rn); |
630 | rtx x; | |
631 | ||
513f31eb | 632 | if (TARGET_H8300) |
68ee6df6 | 633 | x = gen_pop_h8300 (reg); |
f24f0897 | 634 | else if (!TARGET_NORMAL_MODE) |
32da7865 | 635 | x = gen_pop_h8300hs_advanced (reg); |
f24f0897 KH |
636 | else |
637 | x = gen_pop_h8300hs_normal (reg); | |
68ee6df6 | 638 | x = emit_insn (x); |
9690aa8e | 639 | add_reg_note (x, REG_INC, stack_pointer_rtx); |
8f1594b2 | 640 | return x; |
8682223f | 641 | } |
07aae5c2 | 642 | |
beed8fc0 AO |
643 | /* Emit an instruction to push or pop NREGS consecutive registers |
644 | starting at register REGNO. POP_P selects a pop rather than a | |
645 | push and RETURN_P is true if the instruction should return. | |
646 | ||
647 | It must be possible to do the requested operation in a single | |
648 | instruction. If NREGS == 1 && !RETURN_P, use a normal push | |
649 | or pop insn. Otherwise emit a parallel of the form: | |
650 | ||
651 | (parallel | |
652 | [(return) ;; if RETURN_P | |
653 | (save or restore REGNO) | |
654 | (save or restore REGNO + 1) | |
655 | ... | |
656 | (save or restore REGNO + NREGS - 1) | |
657 | (set sp (plus sp (const_int adjust)))] */ | |
658 | ||
659 | static void | |
ac447f25 | 660 | h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p) |
beed8fc0 AO |
661 | { |
662 | int i, j; | |
663 | rtvec vec; | |
18674659 | 664 | rtx sp, offset, x; |
beed8fc0 AO |
665 | |
666 | /* See whether we can use a simple push or pop. */ | |
667 | if (!return_p && nregs == 1) | |
668 | { | |
669 | if (pop_p) | |
670 | pop (regno); | |
671 | else | |
672 | push (regno); | |
673 | return; | |
674 | } | |
675 | ||
676 | /* We need one element for the return insn, if present, one for each | |
677 | register, and one for stack adjustment. */ | |
ac447f25 | 678 | vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1); |
beed8fc0 AO |
679 | sp = stack_pointer_rtx; |
680 | i = 0; | |
681 | ||
682 | /* Add the return instruction. */ | |
683 | if (return_p) | |
684 | { | |
3810076b | 685 | RTVEC_ELT (vec, i) = ret_rtx; |
beed8fc0 AO |
686 | i++; |
687 | } | |
688 | ||
689 | /* Add the register moves. */ | |
690 | for (j = 0; j < nregs; j++) | |
691 | { | |
692 | rtx lhs, rhs; | |
693 | ||
694 | if (pop_p) | |
695 | { | |
696 | /* Register REGNO + NREGS - 1 is popped first. Before the | |
697 | stack adjustment, its slot is at address @sp. */ | |
698 | lhs = gen_rtx_REG (SImode, regno + j); | |
0a81f074 RS |
699 | rhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, |
700 | (nregs - j - 1) * 4)); | |
beed8fc0 AO |
701 | } |
702 | else | |
703 | { | |
704 | /* Register REGNO is pushed first and will be stored at @(-4,sp). */ | |
0a81f074 | 705 | lhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, (j + 1) * -4)); |
beed8fc0 AO |
706 | rhs = gen_rtx_REG (SImode, regno + j); |
707 | } | |
708 | RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, lhs, rhs); | |
709 | } | |
710 | ||
711 | /* Add the stack adjustment. */ | |
712 | offset = GEN_INT ((pop_p ? nregs : -nregs) * 4); | |
713 | RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, sp, | |
714 | gen_rtx_PLUS (Pmode, sp, offset)); | |
715 | ||
18674659 DD |
716 | x = gen_rtx_PARALLEL (VOIDmode, vec); |
717 | if (!pop_p) | |
718 | x = Fpa (x); | |
ac447f25 NC |
719 | |
720 | if (return_p) | |
721 | emit_jump_insn (x); | |
722 | else | |
723 | emit_insn (x); | |
beed8fc0 AO |
724 | } |
725 | ||
726 | /* Return true if X has the value sp + OFFSET. */ | |
727 | ||
728 | static int | |
729 | h8300_stack_offset_p (rtx x, int offset) | |
730 | { | |
731 | if (offset == 0) | |
732 | return x == stack_pointer_rtx; | |
733 | ||
734 | return (GET_CODE (x) == PLUS | |
735 | && XEXP (x, 0) == stack_pointer_rtx | |
736 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
737 | && INTVAL (XEXP (x, 1)) == offset); | |
738 | } | |
739 | ||
740 | /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in | |
741 | something that may be an ldm or stm instruction. If it fits | |
742 | the required template, return the register it loads or stores, | |
743 | otherwise return -1. | |
744 | ||
745 | LOAD_P is true if X should be a load, false if it should be a store. | |
746 | NREGS is the number of registers that the whole instruction is expected | |
747 | to load or store. INDEX is the index of the register that X should | |
748 | load or store, relative to the lowest-numbered register. */ | |
749 | ||
750 | static int | |
751 | h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs) | |
752 | { | |
753 | int regindex, memindex, offset; | |
754 | ||
755 | if (load_p) | |
756 | regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4; | |
757 | else | |
758 | memindex = 0, regindex = 1, offset = (index + 1) * -4; | |
759 | ||
760 | if (GET_CODE (x) == SET | |
761 | && GET_CODE (XEXP (x, regindex)) == REG | |
762 | && GET_CODE (XEXP (x, memindex)) == MEM | |
763 | && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset)) | |
764 | return REGNO (XEXP (x, regindex)); | |
765 | ||
766 | return -1; | |
767 | } | |
768 | ||
769 | /* Return true if the elements of VEC starting at FIRST describe an | |
770 | ldm or stm instruction (LOAD_P says which). */ | |
771 | ||
981c7dce | 772 | int |
beed8fc0 AO |
773 | h8300_ldm_stm_parallel (rtvec vec, int load_p, int first) |
774 | { | |
775 | rtx last; | |
776 | int nregs, i, regno, adjust; | |
777 | ||
778 | /* There must be a stack adjustment, a register move, and at least one | |
779 | other operation (a return or another register move). */ | |
780 | if (GET_NUM_ELEM (vec) < 3) | |
781 | return false; | |
782 | ||
783 | /* Get the range of registers to be pushed or popped. */ | |
784 | nregs = GET_NUM_ELEM (vec) - first - 1; | |
785 | regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs); | |
786 | ||
787 | /* Check that the call to h8300_ldm_stm_regno succeeded and | |
788 | that we're only dealing with GPRs. */ | |
789 | if (regno < 0 || regno + nregs > 8) | |
790 | return false; | |
791 | ||
792 | /* 2-register h8s instructions must start with an even-numbered register. | |
793 | 3- and 4-register instructions must start with er0 or er4. */ | |
794 | if (!TARGET_H8300SX) | |
795 | { | |
796 | if ((regno & 1) != 0) | |
797 | return false; | |
798 | if (nregs > 2 && (regno & 3) != 0) | |
799 | return false; | |
800 | } | |
801 | ||
802 | /* Check the other loads or stores. */ | |
803 | for (i = 1; i < nregs; i++) | |
804 | if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs) | |
805 | != regno + i) | |
806 | return false; | |
807 | ||
808 | /* Check the stack adjustment. */ | |
809 | last = RTVEC_ELT (vec, first + nregs); | |
810 | adjust = (load_p ? nregs : -nregs) * 4; | |
811 | return (GET_CODE (last) == SET | |
812 | && SET_DEST (last) == stack_pointer_rtx | |
813 | && h8300_stack_offset_p (SET_SRC (last), adjust)); | |
814 | } | |
815 | ||
f0b6f9a6 | 816 | /* This is what the stack looks like after the prolog of |
07aae5c2 SC |
817 | a function with a frame has been set up: |
818 | ||
48837e29 DE |
819 | <args> |
820 | PC | |
821 | FP <- fp | |
822 | <locals> | |
8bd06267 | 823 | <saved registers> <- sp |
07aae5c2 SC |
824 | |
825 | This is what the stack looks like after the prolog of | |
826 | a function which doesn't have a frame: | |
827 | ||
48837e29 DE |
828 | <args> |
829 | PC | |
830 | <locals> | |
8bd06267 | 831 | <saved registers> <- sp |
07aae5c2 SC |
832 | */ |
833 | ||
68ee6df6 | 834 | /* Generate RTL code for the function prologue. */ |
8682223f | 835 | |
68ee6df6 | 836 | void |
cb713a8d | 837 | h8300_expand_prologue (void) |
07aae5c2 | 838 | { |
e651d484 | 839 | int regno; |
8682223f | 840 | int saved_regs; |
cda4bd43 | 841 | int n_regs; |
07aae5c2 | 842 | |
fabe72bb JL |
843 | /* If the current function has the OS_Task attribute set, then |
844 | we have a naked prologue. */ | |
845 | if (h8300_os_task_function_p (current_function_decl)) | |
68ee6df6 | 846 | return; |
fabe72bb JL |
847 | |
848 | if (h8300_monitor_function_p (current_function_decl)) | |
f4ea8112 SKS |
849 | /* The monitor function act as normal functions, which means it |
850 | can accept parameters and return values. In addition to this, | |
851 | interrupts are masked in prologue and return with "rte" in epilogue. */ | |
68ee6df6 | 852 | emit_insn (gen_monitor_prologue ()); |
fabe72bb | 853 | |
48837e29 DE |
854 | if (frame_pointer_needed) |
855 | { | |
07e4d94e | 856 | /* Push fp. */ |
1807b726 | 857 | push (HARD_FRAME_POINTER_REGNUM); |
ac447f25 | 858 | F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true); |
a1616dd9 | 859 | } |
48837e29 | 860 | |
8682223f KH |
861 | /* Push the rest of the registers in ascending order. */ |
862 | saved_regs = compute_saved_regs (); | |
e651d484 | 863 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs) |
cda4bd43 | 864 | { |
cda4bd43 | 865 | n_regs = 1; |
8682223f | 866 | if (saved_regs & (1 << regno)) |
a1616dd9 JL |
867 | { |
868 | if (TARGET_H8300S) | |
869 | { | |
cda4bd43 | 870 | /* See how many registers we can push at the same time. */ |
beed8fc0 | 871 | if ((!TARGET_H8300SX || (regno & 3) == 0) |
8682223f | 872 | && ((saved_regs >> regno) & 0x0f) == 0x0f) |
cda4bd43 KH |
873 | n_regs = 4; |
874 | ||
beed8fc0 | 875 | else if ((!TARGET_H8300SX || (regno & 3) == 0) |
8682223f | 876 | && ((saved_regs >> regno) & 0x07) == 0x07) |
cda4bd43 KH |
877 | n_regs = 3; |
878 | ||
beed8fc0 | 879 | else if ((!TARGET_H8300SX || (regno & 1) == 0) |
8682223f | 880 | && ((saved_regs >> regno) & 0x03) == 0x03) |
cda4bd43 | 881 | n_regs = 2; |
a1616dd9 | 882 | } |
cda4bd43 | 883 | |
ac447f25 | 884 | h8300_push_pop (regno, n_regs, false, false); |
07aae5c2 SC |
885 | } |
886 | } | |
1807b726 KH |
887 | |
888 | /* Leave room for locals. */ | |
c72ea086 | 889 | h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true); |
07aae5c2 SC |
890 | } |
891 | ||
e9eba255 KH |
892 | /* Return nonzero if we can use "rts" for the function currently being |
893 | compiled. */ | |
894 | ||
68ee6df6 | 895 | int |
cb713a8d | 896 | h8300_can_use_return_insn_p (void) |
68ee6df6 KH |
897 | { |
898 | return (reload_completed | |
899 | && !frame_pointer_needed | |
900 | && get_frame_size () == 0 | |
901 | && compute_saved_regs () == 0); | |
902 | } | |
07aae5c2 | 903 | |
68ee6df6 KH |
904 | /* Generate RTL code for the function epilogue. */ |
905 | ||
906 | void | |
cb713a8d | 907 | h8300_expand_epilogue (void) |
07aae5c2 | 908 | { |
e651d484 | 909 | int regno; |
8682223f | 910 | int saved_regs; |
cda4bd43 | 911 | int n_regs; |
beed8fc0 AO |
912 | HOST_WIDE_INT frame_size; |
913 | bool returned_p; | |
07aae5c2 | 914 | |
e392d367 | 915 | if (h8300_os_task_function_p (current_function_decl)) |
68ee6df6 KH |
916 | /* OS_Task epilogues are nearly naked -- they just have an |
917 | rts instruction. */ | |
918 | return; | |
07aae5c2 | 919 | |
beed8fc0 AO |
920 | frame_size = round_frame_size (get_frame_size ()); |
921 | returned_p = false; | |
922 | ||
1807b726 | 923 | /* Deallocate locals. */ |
c72ea086 | 924 | h8300_emit_stack_adjustment (1, frame_size, false); |
1807b726 | 925 | |
8682223f KH |
926 | /* Pop the saved registers in descending order. */ |
927 | saved_regs = compute_saved_regs (); | |
e651d484 | 928 | for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs) |
cda4bd43 | 929 | { |
cda4bd43 | 930 | n_regs = 1; |
8682223f | 931 | if (saved_regs & (1 << regno)) |
07aae5c2 | 932 | { |
a1616dd9 JL |
933 | if (TARGET_H8300S) |
934 | { | |
cda4bd43 | 935 | /* See how many registers we can pop at the same time. */ |
beed8fc0 AO |
936 | if ((TARGET_H8300SX || (regno & 3) == 3) |
937 | && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f) | |
cda4bd43 KH |
938 | n_regs = 4; |
939 | ||
beed8fc0 AO |
940 | else if ((TARGET_H8300SX || (regno & 3) == 2) |
941 | && ((saved_regs << 2 >> regno) & 0x07) == 0x07) | |
cda4bd43 KH |
942 | n_regs = 3; |
943 | ||
beed8fc0 AO |
944 | else if ((TARGET_H8300SX || (regno & 1) == 1) |
945 | && ((saved_regs << 1 >> regno) & 0x03) == 0x03) | |
cda4bd43 | 946 | n_regs = 2; |
a1616dd9 | 947 | } |
cda4bd43 | 948 | |
beed8fc0 AO |
949 | /* See if this pop would be the last insn before the return. |
950 | If so, use rte/l or rts/l instead of pop or ldm.l. */ | |
951 | if (TARGET_H8300SX | |
952 | && !frame_pointer_needed | |
953 | && frame_size == 0 | |
954 | && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0) | |
955 | returned_p = true; | |
956 | ||
ac447f25 | 957 | h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p); |
07aae5c2 | 958 | } |
07aae5c2 | 959 | } |
48837e29 | 960 | |
07e4d94e | 961 | /* Pop frame pointer if we had one. */ |
a1616dd9 | 962 | if (frame_pointer_needed) |
beed8fc0 AO |
963 | { |
964 | if (TARGET_H8300SX) | |
965 | returned_p = true; | |
ac447f25 | 966 | h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p); |
beed8fc0 AO |
967 | } |
968 | ||
969 | if (!returned_p) | |
3810076b | 970 | emit_jump_insn (ret_rtx); |
68ee6df6 | 971 | } |
a1616dd9 | 972 | |
e392d367 KH |
973 | /* Return nonzero if the current function is an interrupt |
974 | function. */ | |
975 | ||
976 | int | |
cb713a8d | 977 | h8300_current_function_interrupt_function_p (void) |
e392d367 | 978 | { |
f4ea8112 SKS |
979 | return (h8300_interrupt_function_p (current_function_decl)); |
980 | } | |
981 | ||
982 | int | |
983 | h8300_current_function_monitor_function_p () | |
984 | { | |
985 | return (h8300_monitor_function_p (current_function_decl)); | |
e392d367 KH |
986 | } |
987 | ||
48837e29 DE |
988 | /* Output assembly code for the start of the file. */ |
989 | ||
1bc7c5b6 ZW |
990 | static void |
991 | h8300_file_start (void) | |
48837e29 | 992 | { |
1bc7c5b6 | 993 | default_file_start (); |
8bd06267 | 994 | |
48837e29 | 995 | if (TARGET_H8300H) |
1bc7c5b6 | 996 | fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file); |
beed8fc0 AO |
997 | else if (TARGET_H8300SX) |
998 | fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file); | |
a1616dd9 | 999 | else if (TARGET_H8300S) |
1bc7c5b6 | 1000 | fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file); |
48837e29 DE |
1001 | } |
1002 | ||
1003 | /* Output assembly language code for the end of file. */ | |
1004 | ||
a5fe455b | 1005 | static void |
cb713a8d | 1006 | h8300_file_end (void) |
48837e29 | 1007 | { |
a5fe455b | 1008 | fputs ("\t.end\n", asm_out_file); |
07aae5c2 SC |
1009 | } |
1010 | \f | |
3cee1a78 KH |
1011 | /* Split an add of a small constant into two adds/subs insns. |
1012 | ||
1013 | If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec | |
1014 | instead of adds/subs. */ | |
009ac3d3 RH |
1015 | |
1016 | void | |
cb713a8d | 1017 | split_adds_subs (enum machine_mode mode, rtx *operands) |
3b7d443c | 1018 | { |
009ac3d3 RH |
1019 | HOST_WIDE_INT val = INTVAL (operands[1]); |
1020 | rtx reg = operands[0]; | |
9492393e KH |
1021 | HOST_WIDE_INT sign = 1; |
1022 | HOST_WIDE_INT amount; | |
590734b6 | 1023 | rtx (*gen_add) (rtx, rtx, rtx); |
3b7d443c | 1024 | |
9492393e KH |
1025 | /* Force VAL to be positive so that we do not have to consider the |
1026 | sign. */ | |
1027 | if (val < 0) | |
3b7d443c | 1028 | { |
9492393e KH |
1029 | val = -val; |
1030 | sign = -1; | |
1031 | } | |
3b7d443c | 1032 | |
3cee1a78 KH |
1033 | switch (mode) |
1034 | { | |
1035 | case HImode: | |
590734b6 | 1036 | gen_add = gen_addhi3; |
3cee1a78 KH |
1037 | break; |
1038 | ||
1039 | case SImode: | |
590734b6 | 1040 | gen_add = gen_addsi3; |
3cee1a78 KH |
1041 | break; |
1042 | ||
1043 | default: | |
8c440872 | 1044 | gcc_unreachable (); |
3cee1a78 KH |
1045 | } |
1046 | ||
9492393e KH |
1047 | /* Try different amounts in descending order. */ |
1048 | for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2; | |
1049 | amount > 0; | |
1050 | amount /= 2) | |
1051 | { | |
1a63219b | 1052 | for (; val >= amount; val -= amount) |
590734b6 | 1053 | emit_insn (gen_add (reg, reg, GEN_INT (sign * amount))); |
3b7d443c JL |
1054 | } |
1055 | ||
9492393e | 1056 | return; |
3b7d443c JL |
1057 | } |
1058 | ||
07aae5c2 | 1059 | /* Handle machine specific pragmas for compatibility with existing |
48837e29 | 1060 | compilers for the H8/300. |
07aae5c2 | 1061 | |
f411c849 | 1062 | pragma saveall generates prologue/epilogue code which saves and |
07aae5c2 | 1063 | restores all the registers on function entry. |
48837e29 | 1064 | |
07aae5c2 SC |
1065 | pragma interrupt saves and restores all registers, and exits with |
1066 | an rte instruction rather than an rts. A pointer to a function | |
1067 | with this attribute may be safely used in an interrupt vector. */ | |
48837e29 | 1068 | |
8b97c5f8 | 1069 | void |
cb713a8d | 1070 | h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED) |
07aae5c2 | 1071 | { |
e392d367 | 1072 | pragma_interrupt = 1; |
8b97c5f8 | 1073 | } |
05a81fe5 | 1074 | |
8b97c5f8 | 1075 | void |
cb713a8d | 1076 | h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED) |
8b97c5f8 ZW |
1077 | { |
1078 | pragma_saveall = 1; | |
07aae5c2 | 1079 | } |
8b97c5f8 | 1080 | |
64bead4c KH |
1081 | /* If the next function argument with MODE and TYPE is to be passed in |
1082 | a register, return a reg RTX for the hard register in which to pass | |
1083 | the argument. CUM represents the state after the last argument. | |
56f9413b | 1084 | If the argument is to be pushed, NULL_RTX is returned. |
48837e29 | 1085 | |
56f9413b NF |
1086 | On the H8/300 all normal args are pushed, unless -mquickcall in which |
1087 | case the first 3 arguments are passed in registers. */ | |
1088 | ||
1089 | static rtx | |
d5cc9181 | 1090 | h8300_function_arg (cumulative_args_t cum_v, enum machine_mode mode, |
56f9413b | 1091 | const_tree type, bool named) |
07aae5c2 | 1092 | { |
d5cc9181 JR |
1093 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
1094 | ||
0ea6f6a0 KH |
1095 | static const char *const hand_list[] = { |
1096 | "__main", | |
1097 | "__cmpsi2", | |
1098 | "__divhi3", | |
1099 | "__modhi3", | |
1100 | "__udivhi3", | |
1101 | "__umodhi3", | |
1102 | "__divsi3", | |
1103 | "__modsi3", | |
1104 | "__udivsi3", | |
1105 | "__umodsi3", | |
1106 | "__mulhi3", | |
1107 | "__mulsi3", | |
1108 | "__reg_memcpy", | |
1109 | "__reg_memset", | |
1110 | "__ucmpsi2", | |
1111 | 0, | |
1112 | }; | |
1113 | ||
7192cbf1 | 1114 | rtx result = NULL_RTX; |
441d04c6 | 1115 | const char *fname; |
48837e29 DE |
1116 | int regpass = 0; |
1117 | ||
dd07092e JL |
1118 | /* Never pass unnamed arguments in registers. */ |
1119 | if (!named) | |
7192cbf1 | 1120 | return NULL_RTX; |
dd07092e | 1121 | |
48837e29 DE |
1122 | /* Pass 3 regs worth of data in regs when user asked on the command line. */ |
1123 | if (TARGET_QUICKCALL) | |
1124 | regpass = 3; | |
1125 | ||
1126 | /* If calling hand written assembler, use 4 regs of args. */ | |
48837e29 DE |
1127 | if (cum->libcall) |
1128 | { | |
441d04c6 | 1129 | const char * const *p; |
48837e29 DE |
1130 | |
1131 | fname = XSTR (cum->libcall, 0); | |
1132 | ||
1133 | /* See if this libcall is one of the hand coded ones. */ | |
48837e29 DE |
1134 | for (p = hand_list; *p && strcmp (*p, fname) != 0; p++) |
1135 | ; | |
07aae5c2 | 1136 | |
48837e29 DE |
1137 | if (*p) |
1138 | regpass = 4; | |
1139 | } | |
1140 | ||
1141 | if (regpass) | |
1142 | { | |
1143 | int size; | |
1144 | ||
1145 | if (mode == BLKmode) | |
1146 | size = int_size_in_bytes (type); | |
1147 | else | |
1148 | size = GET_MODE_SIZE (mode); | |
1149 | ||
15e0e275 KH |
1150 | if (size + cum->nbytes <= regpass * UNITS_PER_WORD |
1151 | && cum->nbytes / UNITS_PER_WORD <= 3) | |
1152 | result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD); | |
48837e29 | 1153 | } |
07aae5c2 | 1154 | |
48837e29 DE |
1155 | return result; |
1156 | } | |
56f9413b NF |
1157 | |
1158 | /* Update the data in CUM to advance over an argument | |
1159 | of mode MODE and data type TYPE. | |
1160 | (TYPE is null for libcalls where that information may not be available.) */ | |
1161 | ||
1162 | static void | |
d5cc9181 | 1163 | h8300_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode, |
56f9413b NF |
1164 | const_tree type, bool named ATTRIBUTE_UNUSED) |
1165 | { | |
d5cc9181 JR |
1166 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
1167 | ||
56f9413b NF |
1168 | cum->nbytes += (mode != BLKmode |
1169 | ? (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD | |
1170 | : (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD); | |
1171 | } | |
1172 | ||
48837e29 | 1173 | \f |
88cb339e N |
1174 | /* Implements TARGET_REGISTER_MOVE_COST. |
1175 | ||
1176 | Any SI register-to-register move may need to be reloaded, | |
1177 | so inmplement h8300_register_move_cost to return > 2 so that reload never | |
1178 | shortcuts. */ | |
1179 | ||
1180 | static int | |
1181 | h8300_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, | |
1182 | reg_class_t from, reg_class_t to) | |
1183 | { | |
1184 | if (from == MAC_REGS || to == MAC_REG) | |
1185 | return 6; | |
1186 | else | |
1187 | return 3; | |
1188 | } | |
1189 | ||
e9eba255 KH |
1190 | /* Compute the cost of an and insn. */ |
1191 | ||
3c50106f | 1192 | static int |
cb713a8d | 1193 | h8300_and_costs (rtx x) |
73cc75e9 KH |
1194 | { |
1195 | rtx operands[4]; | |
1196 | ||
1197 | if (GET_MODE (x) == QImode) | |
1198 | return 1; | |
1199 | ||
1200 | if (GET_MODE (x) != HImode | |
1201 | && GET_MODE (x) != SImode) | |
1202 | return 100; | |
1203 | ||
1204 | operands[0] = NULL; | |
beed8fc0 | 1205 | operands[1] = XEXP (x, 0); |
73cc75e9 KH |
1206 | operands[2] = XEXP (x, 1); |
1207 | operands[3] = x; | |
4f4ebda3 | 1208 | return compute_logical_op_length (GET_MODE (x), operands) / 2; |
73cc75e9 KH |
1209 | } |
1210 | ||
e9eba255 KH |
1211 | /* Compute the cost of a shift insn. */ |
1212 | ||
3c50106f | 1213 | static int |
cb713a8d | 1214 | h8300_shift_costs (rtx x) |
ae557002 KH |
1215 | { |
1216 | rtx operands[4]; | |
1217 | ||
1218 | if (GET_MODE (x) != QImode | |
1219 | && GET_MODE (x) != HImode | |
1220 | && GET_MODE (x) != SImode) | |
1221 | return 100; | |
1222 | ||
1223 | operands[0] = NULL; | |
1224 | operands[1] = NULL; | |
1225 | operands[2] = XEXP (x, 1); | |
1226 | operands[3] = x; | |
4f4ebda3 | 1227 | return compute_a_shift_length (NULL, operands) / 2; |
ae557002 | 1228 | } |
3c50106f | 1229 | |
e9eba255 KH |
1230 | /* Worker function for TARGET_RTX_COSTS. */ |
1231 | ||
3c50106f | 1232 | static bool |
68f932c4 RS |
1233 | h8300_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, |
1234 | int *total, bool speed) | |
3c50106f | 1235 | { |
beed8fc0 AO |
1236 | if (TARGET_H8300SX && outer_code == MEM) |
1237 | { | |
1238 | /* Estimate the number of execution states needed to calculate | |
1239 | the address. */ | |
1240 | if (register_operand (x, VOIDmode) | |
1241 | || GET_CODE (x) == POST_INC | |
1242 | || GET_CODE (x) == POST_DEC | |
1243 | || CONSTANT_P (x)) | |
1244 | *total = 0; | |
1245 | else | |
1246 | *total = COSTS_N_INSNS (1); | |
1247 | return true; | |
1248 | } | |
1249 | ||
3c50106f RH |
1250 | switch (code) |
1251 | { | |
08dca707 KH |
1252 | case CONST_INT: |
1253 | { | |
1254 | HOST_WIDE_INT n = INTVAL (x); | |
1255 | ||
beed8fc0 AO |
1256 | if (TARGET_H8300SX) |
1257 | { | |
1258 | /* Constant operands need the same number of processor | |
1259 | states as register operands. Although we could try to | |
f40751dd | 1260 | use a size-based cost for !speed, the lack of |
beed8fc0 AO |
1261 | of a mode makes the results very unpredictable. */ |
1262 | *total = 0; | |
1263 | return true; | |
1264 | } | |
358a11bb | 1265 | if (-4 <= n && n <= 4) |
08dca707 KH |
1266 | { |
1267 | switch ((int) n) | |
1268 | { | |
1269 | case 0: | |
1270 | *total = 0; | |
1271 | return true; | |
1272 | case 1: | |
1273 | case 2: | |
1274 | case -1: | |
1275 | case -2: | |
1276 | *total = 0 + (outer_code == SET); | |
1277 | return true; | |
1278 | case 4: | |
1279 | case -4: | |
1280 | if (TARGET_H8300H || TARGET_H8300S) | |
1281 | *total = 0 + (outer_code == SET); | |
1282 | else | |
1283 | *total = 1; | |
1284 | return true; | |
1285 | } | |
1286 | } | |
1287 | *total = 1; | |
1288 | return true; | |
1289 | } | |
1290 | ||
1291 | case CONST: | |
1292 | case LABEL_REF: | |
1293 | case SYMBOL_REF: | |
beed8fc0 AO |
1294 | if (TARGET_H8300SX) |
1295 | { | |
1296 | /* See comment for CONST_INT. */ | |
1297 | *total = 0; | |
1298 | return true; | |
1299 | } | |
08dca707 KH |
1300 | *total = 3; |
1301 | return true; | |
1302 | ||
1303 | case CONST_DOUBLE: | |
1304 | *total = 20; | |
1305 | return true; | |
1306 | ||
f90b7a5a PB |
1307 | case COMPARE: |
1308 | if (XEXP (x, 1) == const0_rtx) | |
1309 | *total = 0; | |
1310 | return false; | |
1311 | ||
3c50106f | 1312 | case AND: |
beed8fc0 AO |
1313 | if (!h8300_dst_operand (XEXP (x, 0), VOIDmode) |
1314 | || !h8300_src_operand (XEXP (x, 1), VOIDmode)) | |
1315 | return false; | |
3c50106f RH |
1316 | *total = COSTS_N_INSNS (h8300_and_costs (x)); |
1317 | return true; | |
1318 | ||
1319 | /* We say that MOD and DIV are so expensive because otherwise we'll | |
1320 | generate some really horrible code for division of a power of two. */ | |
1321 | case MOD: | |
1322 | case DIV: | |
beed8fc0 AO |
1323 | case UMOD: |
1324 | case UDIV: | |
1325 | if (TARGET_H8300SX) | |
1326 | switch (GET_MODE (x)) | |
1327 | { | |
1328 | case QImode: | |
1329 | case HImode: | |
f40751dd | 1330 | *total = COSTS_N_INSNS (!speed ? 4 : 10); |
beed8fc0 AO |
1331 | return false; |
1332 | ||
1333 | case SImode: | |
f40751dd | 1334 | *total = COSTS_N_INSNS (!speed ? 4 : 18); |
beed8fc0 AO |
1335 | return false; |
1336 | ||
1337 | default: | |
1338 | break; | |
1339 | } | |
1340 | *total = COSTS_N_INSNS (12); | |
3c50106f RH |
1341 | return true; |
1342 | ||
1343 | case MULT: | |
beed8fc0 AO |
1344 | if (TARGET_H8300SX) |
1345 | switch (GET_MODE (x)) | |
1346 | { | |
1347 | case QImode: | |
1348 | case HImode: | |
1349 | *total = COSTS_N_INSNS (2); | |
1350 | return false; | |
1351 | ||
1352 | case SImode: | |
1353 | *total = COSTS_N_INSNS (5); | |
1354 | return false; | |
1355 | ||
1356 | default: | |
1357 | break; | |
1358 | } | |
1359 | *total = COSTS_N_INSNS (4); | |
3c50106f RH |
1360 | return true; |
1361 | ||
1362 | case ASHIFT: | |
1363 | case ASHIFTRT: | |
1364 | case LSHIFTRT: | |
beed8fc0 AO |
1365 | if (h8sx_binary_shift_operator (x, VOIDmode)) |
1366 | { | |
1367 | *total = COSTS_N_INSNS (2); | |
1368 | return false; | |
1369 | } | |
1370 | else if (h8sx_unary_shift_operator (x, VOIDmode)) | |
1371 | { | |
1372 | *total = COSTS_N_INSNS (1); | |
1373 | return false; | |
1374 | } | |
3c50106f RH |
1375 | *total = COSTS_N_INSNS (h8300_shift_costs (x)); |
1376 | return true; | |
1377 | ||
1378 | case ROTATE: | |
1379 | case ROTATERT: | |
1380 | if (GET_MODE (x) == HImode) | |
1381 | *total = 2; | |
1382 | else | |
1383 | *total = 8; | |
1384 | return true; | |
1385 | ||
1386 | default: | |
beed8fc0 AO |
1387 | *total = COSTS_N_INSNS (1); |
1388 | return false; | |
3c50106f RH |
1389 | } |
1390 | } | |
48837e29 | 1391 | \f |
07aae5c2 SC |
1392 | /* Documentation for the machine specific operand escapes: |
1393 | ||
48837e29 DE |
1394 | 'E' like s but negative. |
1395 | 'F' like t but negative. | |
1396 | 'G' constant just the negative | |
15dc331e JL |
1397 | 'R' print operand as a byte:8 address if appropriate, else fall back to |
1398 | 'X' handling. | |
48837e29 | 1399 | 'S' print operand as a long word |
07aae5c2 | 1400 | 'T' print operand as a word |
48837e29 DE |
1401 | 'V' find the set bit, and print its number. |
1402 | 'W' find the clear bit, and print its number. | |
1403 | 'X' print operand as a byte | |
07aae5c2 | 1404 | 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8. |
15dc331e | 1405 | If this operand isn't a register, fall back to 'R' handling. |
48837e29 | 1406 | 'Z' print int & 7. |
b059c02a | 1407 | 'c' print the opcode corresponding to rtl |
da55315a | 1408 | 'e' first word of 32-bit value - if reg, then least reg. if mem |
48837e29 | 1409 | then least. if const then most sig word |
da55315a | 1410 | 'f' second word of 32-bit value - if reg, then biggest reg. if mem |
48837e29 | 1411 | then +2. if const then least sig word |
07aae5c2 SC |
1412 | 'j' print operand as condition code. |
1413 | 'k' print operand as reverse condition code. | |
beed8fc0 AO |
1414 | 'm' convert an integer operand to a size suffix (.b, .w or .l) |
1415 | 'o' print an integer without a leading '#' | |
da55315a KH |
1416 | 's' print as low byte of 16-bit value |
1417 | 't' print as high byte of 16-bit value | |
1418 | 'w' print as low byte of 32-bit value | |
1419 | 'x' print as 2nd byte of 32-bit value | |
1420 | 'y' print as 3rd byte of 32-bit value | |
1421 | 'z' print as msb of 32-bit value | |
48837e29 | 1422 | */ |
07aae5c2 SC |
1423 | |
1424 | /* Return assembly language string which identifies a comparison type. */ | |
1425 | ||
441d04c6 | 1426 | static const char * |
cb713a8d | 1427 | cond_string (enum rtx_code code) |
07aae5c2 SC |
1428 | { |
1429 | switch (code) | |
1430 | { | |
1431 | case NE: | |
1432 | return "ne"; | |
1433 | case EQ: | |
1434 | return "eq"; | |
1435 | case GE: | |
1436 | return "ge"; | |
1437 | case GT: | |
1438 | return "gt"; | |
1439 | case LE: | |
1440 | return "le"; | |
1441 | case LT: | |
1442 | return "lt"; | |
1443 | case GEU: | |
1444 | return "hs"; | |
1445 | case GTU: | |
1446 | return "hi"; | |
1447 | case LEU: | |
1448 | return "ls"; | |
1449 | case LTU: | |
1450 | return "lo"; | |
1451 | default: | |
8c440872 | 1452 | gcc_unreachable (); |
07aae5c2 SC |
1453 | } |
1454 | } | |
1455 | ||
1456 | /* Print operand X using operand code CODE to assembly language output file | |
1457 | FILE. */ | |
1458 | ||
88cb339e N |
1459 | static void |
1460 | h8300_print_operand (FILE *file, rtx x, int code) | |
07aae5c2 | 1461 | { |
269c14e1 | 1462 | /* This is used for communication between codes V,W,Z and Y. */ |
07aae5c2 SC |
1463 | static int bitint; |
1464 | ||
1465 | switch (code) | |
1466 | { | |
f46b8378 SKS |
1467 | case 'C': |
1468 | if (h8300_constant_length (x) == 2) | |
1469 | fprintf (file, ":16"); | |
1470 | else | |
1471 | fprintf (file, ":32"); | |
1472 | return; | |
48837e29 DE |
1473 | case 'E': |
1474 | switch (GET_CODE (x)) | |
1475 | { | |
1476 | case REG: | |
1477 | fprintf (file, "%sl", names_big[REGNO (x)]); | |
1478 | break; | |
1479 | case CONST_INT: | |
b47900aa | 1480 | fprintf (file, "#%ld", (-INTVAL (x)) & 0xff); |
48837e29 DE |
1481 | break; |
1482 | default: | |
8c440872 | 1483 | gcc_unreachable (); |
48837e29 DE |
1484 | } |
1485 | break; | |
1486 | case 'F': | |
1487 | switch (GET_CODE (x)) | |
1488 | { | |
1489 | case REG: | |
1490 | fprintf (file, "%sh", names_big[REGNO (x)]); | |
1491 | break; | |
1492 | case CONST_INT: | |
b47900aa | 1493 | fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8); |
48837e29 DE |
1494 | break; |
1495 | default: | |
8c440872 | 1496 | gcc_unreachable (); |
48837e29 DE |
1497 | } |
1498 | break; | |
07aae5c2 | 1499 | case 'G': |
8c440872 | 1500 | gcc_assert (GET_CODE (x) == CONST_INT); |
b47900aa | 1501 | fprintf (file, "#%ld", 0xff & (-INTVAL (x))); |
07aae5c2 | 1502 | break; |
48837e29 DE |
1503 | case 'S': |
1504 | if (GET_CODE (x) == REG) | |
1505 | fprintf (file, "%s", names_extended[REGNO (x)]); | |
07aae5c2 | 1506 | else |
48837e29 | 1507 | goto def; |
07aae5c2 | 1508 | break; |
48837e29 DE |
1509 | case 'T': |
1510 | if (GET_CODE (x) == REG) | |
1511 | fprintf (file, "%s", names_big[REGNO (x)]); | |
07aae5c2 | 1512 | else |
48837e29 | 1513 | goto def; |
07aae5c2 | 1514 | break; |
48837e29 | 1515 | case 'V': |
0f6b820c KP |
1516 | bitint = (INTVAL (x) & 0xffff); |
1517 | if ((exact_log2 ((bitint >> 8) & 0xff)) == -1) | |
1518 | bitint = exact_log2 (bitint & 0xff); | |
1519 | else | |
1520 | bitint = exact_log2 ((bitint >> 8) & 0xff); | |
8c440872 | 1521 | gcc_assert (bitint >= 0); |
4d4d89e2 | 1522 | fprintf (file, "#%d", bitint); |
07aae5c2 | 1523 | break; |
48837e29 | 1524 | case 'W': |
0f6b820c KP |
1525 | bitint = ((~INTVAL (x)) & 0xffff); |
1526 | if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 ) | |
1527 | bitint = exact_log2 (bitint & 0xff); | |
1528 | else | |
1529 | bitint = (exact_log2 ((bitint >> 8) & 0xff)); | |
8c440872 | 1530 | gcc_assert (bitint >= 0); |
4d4d89e2 | 1531 | fprintf (file, "#%d", bitint); |
07aae5c2 | 1532 | break; |
15dc331e | 1533 | case 'R': |
48837e29 DE |
1534 | case 'X': |
1535 | if (GET_CODE (x) == REG) | |
1536 | fprintf (file, "%s", byte_reg (x, 0)); | |
1537 | else | |
1538 | goto def; | |
1539 | break; | |
1540 | case 'Y': | |
8c440872 | 1541 | gcc_assert (bitint >= 0); |
48837e29 DE |
1542 | if (GET_CODE (x) == REG) |
1543 | fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l'); | |
1544 | else | |
88cb339e | 1545 | h8300_print_operand (file, x, 'R'); |
48837e29 DE |
1546 | bitint = -1; |
1547 | break; | |
1548 | case 'Z': | |
1549 | bitint = INTVAL (x); | |
07aae5c2 SC |
1550 | fprintf (file, "#%d", bitint & 7); |
1551 | break; | |
b059c02a KH |
1552 | case 'c': |
1553 | switch (GET_CODE (x)) | |
1554 | { | |
1555 | case IOR: | |
1556 | fprintf (file, "or"); | |
1557 | break; | |
1558 | case XOR: | |
1559 | fprintf (file, "xor"); | |
1560 | break; | |
5abfd1af KH |
1561 | case AND: |
1562 | fprintf (file, "and"); | |
1563 | break; | |
b059c02a KH |
1564 | default: |
1565 | break; | |
1566 | } | |
1567 | break; | |
07aae5c2 SC |
1568 | case 'e': |
1569 | switch (GET_CODE (x)) | |
1570 | { | |
1571 | case REG: | |
48837e29 DE |
1572 | if (TARGET_H8300) |
1573 | fprintf (file, "%s", names_big[REGNO (x)]); | |
1574 | else | |
1575 | fprintf (file, "%s", names_upper_extended[REGNO (x)]); | |
07aae5c2 SC |
1576 | break; |
1577 | case MEM: | |
88cb339e | 1578 | h8300_print_operand (file, x, 0); |
07aae5c2 SC |
1579 | break; |
1580 | case CONST_INT: | |
b47900aa | 1581 | fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff)); |
07aae5c2 | 1582 | break; |
808fbfac JL |
1583 | case CONST_DOUBLE: |
1584 | { | |
1585 | long val; | |
1586 | REAL_VALUE_TYPE rv; | |
1587 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
1588 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
441d04c6 | 1589 | fprintf (file, "#%ld", ((val >> 16) & 0xffff)); |
808fbfac JL |
1590 | break; |
1591 | } | |
07aae5c2 | 1592 | default: |
8c440872 | 1593 | gcc_unreachable (); |
07aae5c2 SC |
1594 | break; |
1595 | } | |
1596 | break; | |
07aae5c2 SC |
1597 | case 'f': |
1598 | switch (GET_CODE (x)) | |
1599 | { | |
1600 | case REG: | |
48837e29 DE |
1601 | if (TARGET_H8300) |
1602 | fprintf (file, "%s", names_big[REGNO (x) + 1]); | |
1603 | else | |
1604 | fprintf (file, "%s", names_big[REGNO (x)]); | |
07aae5c2 | 1605 | break; |
07aae5c2 | 1606 | case MEM: |
b72f00af | 1607 | x = adjust_address (x, HImode, 2); |
88cb339e | 1608 | h8300_print_operand (file, x, 0); |
07aae5c2 | 1609 | break; |
07aae5c2 | 1610 | case CONST_INT: |
b47900aa | 1611 | fprintf (file, "#%ld", INTVAL (x) & 0xffff); |
07aae5c2 | 1612 | break; |
808fbfac JL |
1613 | case CONST_DOUBLE: |
1614 | { | |
1615 | long val; | |
1616 | REAL_VALUE_TYPE rv; | |
1617 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
1618 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
441d04c6 | 1619 | fprintf (file, "#%ld", (val & 0xffff)); |
808fbfac JL |
1620 | break; |
1621 | } | |
07aae5c2 | 1622 | default: |
8c440872 | 1623 | gcc_unreachable (); |
07aae5c2 SC |
1624 | } |
1625 | break; | |
07aae5c2 | 1626 | case 'j': |
761c70aa | 1627 | fputs (cond_string (GET_CODE (x)), file); |
07aae5c2 | 1628 | break; |
07aae5c2 | 1629 | case 'k': |
761c70aa | 1630 | fputs (cond_string (reverse_condition (GET_CODE (x))), file); |
07aae5c2 | 1631 | break; |
beed8fc0 | 1632 | case 'm': |
8c440872 NS |
1633 | gcc_assert (GET_CODE (x) == CONST_INT); |
1634 | switch (INTVAL (x)) | |
1635 | { | |
1636 | case 1: | |
1637 | fputs (".b", file); | |
1638 | break; | |
1639 | ||
1640 | case 2: | |
1641 | fputs (".w", file); | |
1642 | break; | |
1643 | ||
1644 | case 4: | |
1645 | fputs (".l", file); | |
1646 | break; | |
1647 | ||
1648 | default: | |
1649 | gcc_unreachable (); | |
1650 | } | |
beed8fc0 AO |
1651 | break; |
1652 | case 'o': | |
88cb339e | 1653 | h8300_print_operand_address (file, x); |
beed8fc0 | 1654 | break; |
48837e29 DE |
1655 | case 's': |
1656 | if (GET_CODE (x) == CONST_INT) | |
b47900aa | 1657 | fprintf (file, "#%ld", (INTVAL (x)) & 0xff); |
48837e29 DE |
1658 | else |
1659 | fprintf (file, "%s", byte_reg (x, 0)); | |
1660 | break; | |
1661 | case 't': | |
1662 | if (GET_CODE (x) == CONST_INT) | |
b47900aa | 1663 | fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff); |
48837e29 DE |
1664 | else |
1665 | fprintf (file, "%s", byte_reg (x, 1)); | |
1666 | break; | |
48837e29 DE |
1667 | case 'w': |
1668 | if (GET_CODE (x) == CONST_INT) | |
b47900aa | 1669 | fprintf (file, "#%ld", INTVAL (x) & 0xff); |
48837e29 | 1670 | else |
a1616dd9 JL |
1671 | fprintf (file, "%s", |
1672 | byte_reg (x, TARGET_H8300 ? 2 : 0)); | |
48837e29 DE |
1673 | break; |
1674 | case 'x': | |
1675 | if (GET_CODE (x) == CONST_INT) | |
b47900aa | 1676 | fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff); |
48837e29 | 1677 | else |
a1616dd9 JL |
1678 | fprintf (file, "%s", |
1679 | byte_reg (x, TARGET_H8300 ? 3 : 1)); | |
48837e29 DE |
1680 | break; |
1681 | case 'y': | |
1682 | if (GET_CODE (x) == CONST_INT) | |
b47900aa | 1683 | fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff); |
48837e29 DE |
1684 | else |
1685 | fprintf (file, "%s", byte_reg (x, 0)); | |
1686 | break; | |
1687 | case 'z': | |
1688 | if (GET_CODE (x) == CONST_INT) | |
b47900aa | 1689 | fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff); |
48837e29 DE |
1690 | else |
1691 | fprintf (file, "%s", byte_reg (x, 1)); | |
1692 | break; | |
1693 | ||
07aae5c2 | 1694 | default: |
48837e29 | 1695 | def: |
07aae5c2 SC |
1696 | switch (GET_CODE (x)) |
1697 | { | |
1698 | case REG: | |
48837e29 DE |
1699 | switch (GET_MODE (x)) |
1700 | { | |
1701 | case QImode: | |
269c14e1 | 1702 | #if 0 /* Is it asm ("mov.b %0,r2l", ...) */ |
48837e29 DE |
1703 | fprintf (file, "%s", byte_reg (x, 0)); |
1704 | #else /* ... or is it asm ("mov.b %0l,r2l", ...) */ | |
1705 | fprintf (file, "%s", names_big[REGNO (x)]); | |
1706 | #endif | |
1707 | break; | |
1708 | case HImode: | |
1709 | fprintf (file, "%s", names_big[REGNO (x)]); | |
1710 | break; | |
1711 | case SImode: | |
8977e8a7 | 1712 | case SFmode: |
48837e29 DE |
1713 | fprintf (file, "%s", names_extended[REGNO (x)]); |
1714 | break; | |
1715 | default: | |
8c440872 | 1716 | gcc_unreachable (); |
48837e29 | 1717 | } |
07aae5c2 SC |
1718 | break; |
1719 | ||
1720 | case MEM: | |
87e4ee91 KH |
1721 | { |
1722 | rtx addr = XEXP (x, 0); | |
1723 | ||
1724 | fprintf (file, "@"); | |
1725 | output_address (addr); | |
1726 | ||
beed8fc0 AO |
1727 | /* Add a length suffix to constant addresses. Although this |
1728 | is often unnecessary, it helps to avoid ambiguity in the | |
1729 | syntax of mova. If we wrote an insn like: | |
1730 | ||
1731 | mova/w.l @(1,@foo.b),er0 | |
1732 | ||
1733 | then .b would be considered part of the symbol name. | |
1734 | Adding a length after foo will avoid this. */ | |
1735 | if (CONSTANT_P (addr)) | |
1736 | switch (code) | |
1737 | { | |
1738 | case 'R': | |
1739 | /* Used for mov.b and bit operations. */ | |
1740 | if (h8300_eightbit_constant_address_p (addr)) | |
1741 | { | |
1742 | fprintf (file, ":8"); | |
1743 | break; | |
1744 | } | |
1745 | ||
1746 | /* Fall through. We should not get here if we are | |
1747 | processing bit operations on H8/300 or H8/300H | |
1748 | because 'U' constraint does not allow bit | |
1749 | operations on the tiny area on these machines. */ | |
1750 | ||
1751 | case 'X': | |
1752 | case 'T': | |
1753 | case 'S': | |
1754 | if (h8300_constant_length (addr) == 2) | |
1755 | fprintf (file, ":16"); | |
1756 | else | |
1757 | fprintf (file, ":32"); | |
1758 | break; | |
1759 | default: | |
1760 | break; | |
1761 | } | |
87e4ee91 | 1762 | } |
07aae5c2 SC |
1763 | break; |
1764 | ||
1765 | case CONST_INT: | |
1766 | case SYMBOL_REF: | |
1767 | case CONST: | |
1768 | case LABEL_REF: | |
1769 | fprintf (file, "#"); | |
88cb339e | 1770 | h8300_print_operand_address (file, x); |
07aae5c2 | 1771 | break; |
808fbfac JL |
1772 | case CONST_DOUBLE: |
1773 | { | |
1774 | long val; | |
1775 | REAL_VALUE_TYPE rv; | |
1776 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
1777 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
441d04c6 | 1778 | fprintf (file, "#%ld", val); |
808fbfac JL |
1779 | break; |
1780 | } | |
441d04c6 KG |
1781 | default: |
1782 | break; | |
07aae5c2 SC |
1783 | } |
1784 | } | |
1785 | } | |
1786 | ||
88cb339e N |
1787 | /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */ |
1788 | ||
1789 | static bool | |
1790 | h8300_print_operand_punct_valid_p (unsigned char code) | |
1791 | { | |
1792 | return (code == '#'); | |
1793 | } | |
1794 | ||
07aae5c2 SC |
1795 | /* Output assembly language output for the address ADDR to FILE. */ |
1796 | ||
88cb339e N |
1797 | static void |
1798 | h8300_print_operand_address (FILE *file, rtx addr) | |
07aae5c2 | 1799 | { |
beed8fc0 AO |
1800 | rtx index; |
1801 | int size; | |
1802 | ||
07aae5c2 SC |
1803 | switch (GET_CODE (addr)) |
1804 | { | |
1805 | case REG: | |
48837e29 | 1806 | fprintf (file, "%s", h8_reg_names[REGNO (addr)]); |
07aae5c2 SC |
1807 | break; |
1808 | ||
1809 | case PRE_DEC: | |
48837e29 | 1810 | fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]); |
07aae5c2 SC |
1811 | break; |
1812 | ||
1813 | case POST_INC: | |
48837e29 | 1814 | fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]); |
07aae5c2 SC |
1815 | break; |
1816 | ||
beed8fc0 AO |
1817 | case PRE_INC: |
1818 | fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]); | |
1819 | break; | |
1820 | ||
1821 | case POST_DEC: | |
1822 | fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]); | |
1823 | break; | |
1824 | ||
07aae5c2 SC |
1825 | case PLUS: |
1826 | fprintf (file, "("); | |
beed8fc0 AO |
1827 | |
1828 | index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size); | |
1829 | if (GET_CODE (index) == REG) | |
07aae5c2 SC |
1830 | { |
1831 | /* reg,foo */ | |
88cb339e | 1832 | h8300_print_operand_address (file, XEXP (addr, 1)); |
07aae5c2 | 1833 | fprintf (file, ","); |
beed8fc0 AO |
1834 | switch (size) |
1835 | { | |
1836 | case 0: | |
88cb339e | 1837 | h8300_print_operand_address (file, index); |
beed8fc0 AO |
1838 | break; |
1839 | ||
1840 | case 1: | |
88cb339e | 1841 | h8300_print_operand (file, index, 'X'); |
beed8fc0 AO |
1842 | fputs (".b", file); |
1843 | break; | |
1844 | ||
1845 | case 2: | |
88cb339e | 1846 | h8300_print_operand (file, index, 'T'); |
beed8fc0 AO |
1847 | fputs (".w", file); |
1848 | break; | |
1849 | ||
1850 | case 4: | |
88cb339e | 1851 | h8300_print_operand (file, index, 'S'); |
beed8fc0 AO |
1852 | fputs (".l", file); |
1853 | break; | |
1854 | } | |
88cb339e | 1855 | /* h8300_print_operand_address (file, XEXP (addr, 0)); */ |
07aae5c2 SC |
1856 | } |
1857 | else | |
1858 | { | |
1859 | /* foo+k */ | |
88cb339e | 1860 | h8300_print_operand_address (file, XEXP (addr, 0)); |
07aae5c2 | 1861 | fprintf (file, "+"); |
88cb339e | 1862 | h8300_print_operand_address (file, XEXP (addr, 1)); |
07aae5c2 SC |
1863 | } |
1864 | fprintf (file, ")"); | |
1865 | break; | |
1866 | ||
1867 | case CONST_INT: | |
48837e29 | 1868 | { |
da55315a | 1869 | /* Since the H8/300 only has 16-bit pointers, negative values are also |
48837e29 DE |
1870 | those >= 32768. This happens for example with pointer minus a |
1871 | constant. We don't want to turn (char *p - 2) into | |
1872 | (char *p + 65534) because loop unrolling can build upon this | |
1873 | (IE: char *p + 131068). */ | |
1874 | int n = INTVAL (addr); | |
1875 | if (TARGET_H8300) | |
1876 | n = (int) (short) n; | |
7a770d8b | 1877 | fprintf (file, "%d", n); |
48837e29 DE |
1878 | break; |
1879 | } | |
07aae5c2 SC |
1880 | |
1881 | default: | |
1882 | output_addr_const (file, addr); | |
1883 | break; | |
1884 | } | |
1885 | } | |
1886 | \f | |
07aae5c2 SC |
1887 | /* Output all insn addresses and their sizes into the assembly language |
1888 | output file. This is helpful for debugging whether the length attributes | |
1889 | in the md file are correct. This is not meant to be a user selectable | |
1890 | option. */ | |
1891 | ||
1892 | void | |
e7041fcc | 1893 | final_prescan_insn (rtx_insn *insn, rtx *operand ATTRIBUTE_UNUSED, |
cb713a8d | 1894 | int num_operands ATTRIBUTE_UNUSED) |
07aae5c2 SC |
1895 | { |
1896 | /* This holds the last insn address. */ | |
1897 | static int last_insn_address = 0; | |
1898 | ||
7798db98 | 1899 | const int uid = INSN_UID (insn); |
07aae5c2 SC |
1900 | |
1901 | if (TARGET_ADDRESSES) | |
1902 | { | |
9d98a694 AO |
1903 | fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid), |
1904 | INSN_ADDRESSES (uid) - last_insn_address); | |
1905 | last_insn_address = INSN_ADDRESSES (uid); | |
07aae5c2 SC |
1906 | } |
1907 | } | |
1908 | ||
48837e29 DE |
1909 | /* Prepare for an SI sized move. */ |
1910 | ||
1911 | int | |
1a793acf | 1912 | h8300_expand_movsi (rtx operands[]) |
07aae5c2 | 1913 | { |
48837e29 DE |
1914 | rtx src = operands[1]; |
1915 | rtx dst = operands[0]; | |
1916 | if (!reload_in_progress && !reload_completed) | |
1917 | { | |
1918 | if (!register_operand (dst, GET_MODE (dst))) | |
1919 | { | |
1920 | rtx tmp = gen_reg_rtx (GET_MODE (dst)); | |
1921 | emit_move_insn (tmp, src); | |
1922 | operands[1] = tmp; | |
1923 | } | |
1924 | } | |
1925 | return 0; | |
1926 | } | |
1927 | ||
7b5cbb57 AS |
1928 | /* Given FROM and TO register numbers, say whether this elimination is allowed. |
1929 | Frame pointer elimination is automatically handled. | |
1930 | ||
1931 | For the h8300, if frame pointer elimination is being done, we would like to | |
1932 | convert ap and rp into sp, not fp. | |
1933 | ||
1934 | All other eliminations are valid. */ | |
1935 | ||
1936 | static bool | |
1937 | h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) | |
1938 | { | |
1939 | return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true); | |
1940 | } | |
1941 | ||
5efd84c5 NF |
1942 | /* Conditionally modify register usage based on target flags. */ |
1943 | ||
1944 | static void | |
1945 | h8300_conditional_register_usage (void) | |
1946 | { | |
1947 | if (!TARGET_MAC) | |
1948 | fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1; | |
1949 | } | |
1950 | ||
48837e29 | 1951 | /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET). |
07e4d94e KH |
1952 | Define the offset between two registers, one to be eliminated, and |
1953 | the other its replacement, at the start of a routine. */ | |
07aae5c2 | 1954 | |
48837e29 | 1955 | int |
cb713a8d | 1956 | h8300_initial_elimination_offset (int from, int to) |
48837e29 | 1957 | { |
d18ad191 KH |
1958 | /* The number of bytes that the return address takes on the stack. */ |
1959 | int pc_size = POINTER_SIZE / BITS_PER_UNIT; | |
48837e29 | 1960 | |
1807b726 KH |
1961 | /* The number of bytes that the saved frame pointer takes on the stack. */ |
1962 | int fp_size = frame_pointer_needed * UNITS_PER_WORD; | |
1963 | ||
1964 | /* The number of bytes that the saved registers, excluding the frame | |
1965 | pointer, take on the stack. */ | |
1966 | int saved_regs_size = 0; | |
48837e29 | 1967 | |
1807b726 KH |
1968 | /* The number of bytes that the locals takes on the stack. */ |
1969 | int frame_size = round_frame_size (get_frame_size ()); | |
48837e29 | 1970 | |
1807b726 | 1971 | int regno; |
48837e29 | 1972 | |
1807b726 KH |
1973 | for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++) |
1974 | if (WORD_REG_USED (regno)) | |
1975 | saved_regs_size += UNITS_PER_WORD; | |
48837e29 | 1976 | |
1807b726 KH |
1977 | /* Adjust saved_regs_size because the above loop took the frame |
1978 | pointer int account. */ | |
1979 | saved_regs_size -= fp_size; | |
39ba95b5 | 1980 | |
8c440872 | 1981 | switch (to) |
1807b726 | 1982 | { |
8c440872 | 1983 | case HARD_FRAME_POINTER_REGNUM: |
1807b726 KH |
1984 | switch (from) |
1985 | { | |
1986 | case ARG_POINTER_REGNUM: | |
1987 | return pc_size + fp_size; | |
1988 | case RETURN_ADDRESS_POINTER_REGNUM: | |
1989 | return fp_size; | |
1990 | case FRAME_POINTER_REGNUM: | |
1991 | return -saved_regs_size; | |
1992 | default: | |
8c440872 | 1993 | gcc_unreachable (); |
1807b726 | 1994 | } |
8c440872 NS |
1995 | break; |
1996 | case STACK_POINTER_REGNUM: | |
1807b726 KH |
1997 | switch (from) |
1998 | { | |
1999 | case ARG_POINTER_REGNUM: | |
2000 | return pc_size + saved_regs_size + frame_size; | |
2001 | case RETURN_ADDRESS_POINTER_REGNUM: | |
2002 | return saved_regs_size + frame_size; | |
2003 | case FRAME_POINTER_REGNUM: | |
2004 | return frame_size; | |
2005 | default: | |
8c440872 | 2006 | gcc_unreachable (); |
1807b726 | 2007 | } |
8c440872 NS |
2008 | break; |
2009 | default: | |
2010 | gcc_unreachable (); | |
1807b726 | 2011 | } |
8c440872 | 2012 | gcc_unreachable (); |
48837e29 DE |
2013 | } |
2014 | ||
e9eba255 KH |
2015 | /* Worker function for RETURN_ADDR_RTX. */ |
2016 | ||
1aae372e | 2017 | rtx |
cb713a8d | 2018 | h8300_return_addr_rtx (int count, rtx frame) |
1aae372e JL |
2019 | { |
2020 | rtx ret; | |
2021 | ||
2022 | if (count == 0) | |
2023 | ret = gen_rtx_MEM (Pmode, | |
2024 | gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM)); | |
2025 | else if (flag_omit_frame_pointer) | |
2026 | return (rtx) 0; | |
2027 | else | |
2028 | ret = gen_rtx_MEM (Pmode, | |
2029 | memory_address (Pmode, | |
0a81f074 RS |
2030 | plus_constant (Pmode, frame, |
2031 | UNITS_PER_WORD))); | |
1aae372e JL |
2032 | set_mem_alias_set (ret, get_frame_alias_set ()); |
2033 | return ret; | |
2034 | } | |
2035 | ||
48837e29 DE |
2036 | /* Update the condition code from the insn. */ |
2037 | ||
441d04c6 | 2038 | void |
e8a54173 | 2039 | notice_update_cc (rtx body, rtx_insn *insn) |
48837e29 | 2040 | { |
d99c740f KH |
2041 | rtx set; |
2042 | ||
48837e29 DE |
2043 | switch (get_attr_cc (insn)) |
2044 | { | |
2045 | case CC_NONE: | |
269c14e1 | 2046 | /* Insn does not affect CC at all. */ |
48837e29 DE |
2047 | break; |
2048 | ||
2049 | case CC_NONE_0HIT: | |
269c14e1 | 2050 | /* Insn does not change CC, but the 0'th operand has been changed. */ |
48837e29 | 2051 | if (cc_status.value1 != 0 |
1ccbefce | 2052 | && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1)) |
48837e29 | 2053 | cc_status.value1 = 0; |
d4d6d0ce KH |
2054 | if (cc_status.value2 != 0 |
2055 | && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2)) | |
2056 | cc_status.value2 = 0; | |
48837e29 DE |
2057 | break; |
2058 | ||
065bbfe6 | 2059 | case CC_SET_ZN: |
1ccbefce | 2060 | /* Insn sets the Z,N flags of CC to recog_data.operand[0]. |
269c14e1 DE |
2061 | The V flag is unusable. The C flag may or may not be known but |
2062 | that's ok because alter_cond will change tests to use EQ/NE. */ | |
48837e29 | 2063 | CC_STATUS_INIT; |
269c14e1 | 2064 | cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY; |
d99c740f KH |
2065 | set = single_set (insn); |
2066 | cc_status.value1 = SET_SRC (set); | |
2067 | if (SET_DEST (set) != cc0_rtx) | |
2068 | cc_status.value2 = SET_DEST (set); | |
48837e29 DE |
2069 | break; |
2070 | ||
065bbfe6 | 2071 | case CC_SET_ZNV: |
1ccbefce | 2072 | /* Insn sets the Z,N,V flags of CC to recog_data.operand[0]. |
065bbfe6 JL |
2073 | The C flag may or may not be known but that's ok because |
2074 | alter_cond will change tests to use EQ/NE. */ | |
2075 | CC_STATUS_INIT; | |
2076 | cc_status.flags |= CC_NO_CARRY; | |
d99c740f KH |
2077 | set = single_set (insn); |
2078 | cc_status.value1 = SET_SRC (set); | |
2079 | if (SET_DEST (set) != cc0_rtx) | |
c8fcf20c KH |
2080 | { |
2081 | /* If the destination is STRICT_LOW_PART, strip off | |
2082 | STRICT_LOW_PART. */ | |
2083 | if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) | |
2084 | cc_status.value2 = XEXP (SET_DEST (set), 0); | |
2085 | else | |
2086 | cc_status.value2 = SET_DEST (set); | |
2087 | } | |
065bbfe6 JL |
2088 | break; |
2089 | ||
beed8fc0 AO |
2090 | case CC_COMPARE: |
2091 | /* The insn is a compare instruction. */ | |
2092 | CC_STATUS_INIT; | |
2093 | cc_status.value1 = SET_SRC (body); | |
2094 | break; | |
2095 | ||
2096 | case CC_CLOBBER: | |
2097 | /* Insn doesn't leave CC in a usable state. */ | |
2098 | CC_STATUS_INIT; | |
2099 | break; | |
2100 | } | |
2101 | } | |
beed8fc0 AO |
2102 | \f |
2103 | /* Given that X occurs in an address of the form (plus X constant), | |
2104 | return the part of X that is expected to be a register. There are | |
2105 | four kinds of addressing mode to recognize: | |
2106 | ||
2107 | @(dd,Rn) | |
2108 | @(dd,RnL.b) | |
2109 | @(dd,Rn.w) | |
2110 | @(dd,ERn.l) | |
2111 | ||
2112 | If SIZE is nonnull, and the address is one of the last three forms, | |
2113 | set *SIZE to the index multiplication factor. Set it to 0 for | |
2114 | plain @(dd,Rn) addresses. | |
2115 | ||
2116 | MODE is the mode of the value being accessed. It can be VOIDmode | |
2117 | if the address is known to be valid, but its mode is unknown. */ | |
2118 | ||
f52d97da | 2119 | static rtx |
beed8fc0 AO |
2120 | h8300_get_index (rtx x, enum machine_mode mode, int *size) |
2121 | { | |
2122 | int dummy, factor; | |
2123 | ||
2124 | if (size == 0) | |
2125 | size = &dummy; | |
2126 | ||
2127 | factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode)); | |
2128 | if (TARGET_H8300SX | |
2129 | && factor <= 4 | |
2130 | && (mode == VOIDmode | |
2131 | || GET_MODE_CLASS (mode) == MODE_INT | |
2132 | || GET_MODE_CLASS (mode) == MODE_FLOAT)) | |
2133 | { | |
2134 | if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND) | |
2135 | { | |
2136 | /* When accessing byte-sized values, the index can be | |
2137 | a zero-extended QImode or HImode register. */ | |
2138 | *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0))); | |
2139 | return XEXP (x, 0); | |
2140 | } | |
2141 | else | |
2142 | { | |
2143 | /* We're looking for addresses of the form: | |
2144 | ||
2145 | (mult X I) | |
2146 | or (mult (zero_extend X) I) | |
2147 | ||
2148 | where I is the size of the operand being accessed. | |
2149 | The canonical form of the second expression is: | |
2150 | ||
2151 | (and (mult (subreg X) I) J) | |
2152 | ||
2153 | where J == GET_MODE_MASK (GET_MODE (X)) * I. */ | |
2154 | rtx index; | |
2155 | ||
2156 | if (GET_CODE (x) == AND | |
2157 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2158 | && (factor == 0 | |
2159 | || INTVAL (XEXP (x, 1)) == 0xff * factor | |
2160 | || INTVAL (XEXP (x, 1)) == 0xffff * factor)) | |
2161 | { | |
2162 | index = XEXP (x, 0); | |
2163 | *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1); | |
2164 | } | |
2165 | else | |
2166 | { | |
2167 | index = x; | |
2168 | *size = 4; | |
2169 | } | |
2170 | ||
2171 | if (GET_CODE (index) == MULT | |
2172 | && GET_CODE (XEXP (index, 1)) == CONST_INT | |
2173 | && (factor == 0 || factor == INTVAL (XEXP (index, 1)))) | |
2174 | return XEXP (index, 0); | |
2175 | } | |
2176 | } | |
2177 | *size = 0; | |
2178 | return x; | |
2179 | } | |
2180 | \f | |
f52d97da AS |
2181 | /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. |
2182 | ||
2183 | On the H8/300, the predecrement and postincrement address depend thus | |
2184 | (the amount of decrement or increment being the length of the operand). */ | |
2185 | ||
2186 | static bool | |
5bfed9a9 GJL |
2187 | h8300_mode_dependent_address_p (const_rtx addr, |
2188 | addr_space_t as ATTRIBUTE_UNUSED) | |
f52d97da AS |
2189 | { |
2190 | if (GET_CODE (addr) == PLUS | |
2191 | && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0)) | |
2192 | return true; | |
2193 | ||
2194 | return false; | |
2195 | } | |
2196 | \f | |
beed8fc0 AO |
2197 | static const h8300_length_table addb_length_table = |
2198 | { | |
2199 | /* #xx Rs @aa @Rs @xx */ | |
2200 | { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */ | |
2201 | { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */ | |
2202 | { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */ | |
2203 | { 6, 4, 4, 4, 6 } /* add.b xx,@xx */ | |
2204 | }; | |
2205 | ||
2206 | static const h8300_length_table addw_length_table = | |
2207 | { | |
2208 | /* #xx Rs @aa @Rs @xx */ | |
2209 | { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */ | |
2210 | { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */ | |
2211 | { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */ | |
2212 | { 4, 4, 4, 4, 6 } /* add.w xx,@xx */ | |
2213 | }; | |
2214 | ||
2215 | static const h8300_length_table addl_length_table = | |
2216 | { | |
2217 | /* #xx Rs @aa @Rs @xx */ | |
2218 | { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */ | |
2219 | { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */ | |
2220 | { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */ | |
2221 | { 4, 4, 6, 6, 6 } /* add.l xx,@xx */ | |
2222 | }; | |
2223 | ||
2224 | #define logicb_length_table addb_length_table | |
2225 | #define logicw_length_table addw_length_table | |
2226 | ||
2227 | static const h8300_length_table logicl_length_table = | |
2228 | { | |
2229 | /* #xx Rs @aa @Rs @xx */ | |
2230 | { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */ | |
2231 | { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */ | |
2232 | { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */ | |
2233 | { 4, 4, 6, 6, 6 } /* and.l xx,@xx */ | |
2234 | }; | |
2235 | ||
2236 | static const h8300_length_table movb_length_table = | |
2237 | { | |
2238 | /* #xx Rs @aa @Rs @xx */ | |
2239 | { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */ | |
2240 | { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */ | |
2241 | { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */ | |
2242 | { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */ | |
2243 | }; | |
2244 | ||
2245 | #define movw_length_table movb_length_table | |
2246 | ||
2247 | static const h8300_length_table movl_length_table = | |
2248 | { | |
2249 | /* #xx Rs @aa @Rs @xx */ | |
2250 | { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */ | |
2251 | { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */ | |
2252 | { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */ | |
2253 | { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */ | |
2254 | }; | |
2255 | ||
2256 | /* Return the size of the given address or displacement constant. */ | |
2257 | ||
2258 | static unsigned int | |
2259 | h8300_constant_length (rtx constant) | |
2260 | { | |
2261 | /* Check for (@d:16,Reg). */ | |
2262 | if (GET_CODE (constant) == CONST_INT | |
2263 | && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff)) | |
2264 | return 2; | |
2265 | ||
2266 | /* Check for (@d:16,Reg) in cases where the displacement is | |
2267 | an absolute address. */ | |
2268 | if (Pmode == HImode || h8300_tiny_constant_address_p (constant)) | |
2269 | return 2; | |
2270 | ||
2271 | return 4; | |
2272 | } | |
2273 | ||
2274 | /* Return the size of a displacement field in address ADDR, which should | |
2275 | have the form (plus X constant). SIZE is the number of bytes being | |
2276 | accessed. */ | |
2277 | ||
2278 | static unsigned int | |
2279 | h8300_displacement_length (rtx addr, int size) | |
2280 | { | |
2281 | rtx offset; | |
2282 | ||
2283 | offset = XEXP (addr, 1); | |
2284 | ||
2285 | /* Check for @(d:2,Reg). */ | |
2286 | if (register_operand (XEXP (addr, 0), VOIDmode) | |
2287 | && GET_CODE (offset) == CONST_INT | |
2288 | && (INTVAL (offset) == size | |
2289 | || INTVAL (offset) == size * 2 | |
2290 | || INTVAL (offset) == size * 3)) | |
2291 | return 0; | |
2292 | ||
2293 | return h8300_constant_length (offset); | |
2294 | } | |
2295 | ||
0a2aaacc KG |
2296 | /* Store the class of operand OP in *OPCLASS and return the length of any |
2297 | extra operand fields. SIZE is the number of bytes in OP. OPCLASS | |
beed8fc0 AO |
2298 | can be null if only the length is needed. */ |
2299 | ||
2300 | static unsigned int | |
0a2aaacc | 2301 | h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass) |
beed8fc0 AO |
2302 | { |
2303 | enum h8300_operand_class dummy; | |
2304 | ||
0a2aaacc KG |
2305 | if (opclass == 0) |
2306 | opclass = &dummy; | |
beed8fc0 AO |
2307 | |
2308 | if (CONSTANT_P (op)) | |
2309 | { | |
0a2aaacc | 2310 | *opclass = H8OP_IMMEDIATE; |
beed8fc0 AO |
2311 | |
2312 | /* Byte-sized immediates are stored in the opcode fields. */ | |
2313 | if (size == 1) | |
2314 | return 0; | |
2315 | ||
2316 | /* If this is a 32-bit instruction, see whether the constant | |
2317 | will fit into a 16-bit immediate field. */ | |
2318 | if (TARGET_H8300SX | |
2319 | && size == 4 | |
2320 | && GET_CODE (op) == CONST_INT | |
2321 | && IN_RANGE (INTVAL (op), 0, 0xffff)) | |
2322 | return 2; | |
2323 | ||
2324 | return size; | |
2325 | } | |
2326 | else if (GET_CODE (op) == MEM) | |
2327 | { | |
2328 | op = XEXP (op, 0); | |
2329 | if (CONSTANT_P (op)) | |
2330 | { | |
0a2aaacc | 2331 | *opclass = H8OP_MEM_ABSOLUTE; |
beed8fc0 AO |
2332 | return h8300_constant_length (op); |
2333 | } | |
2334 | else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1))) | |
2335 | { | |
0a2aaacc | 2336 | *opclass = H8OP_MEM_COMPLEX; |
beed8fc0 AO |
2337 | return h8300_displacement_length (op, size); |
2338 | } | |
2339 | else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC) | |
2340 | { | |
0a2aaacc | 2341 | *opclass = H8OP_MEM_COMPLEX; |
beed8fc0 AO |
2342 | return 0; |
2343 | } | |
2344 | else if (register_operand (op, VOIDmode)) | |
2345 | { | |
0a2aaacc | 2346 | *opclass = H8OP_MEM_BASE; |
beed8fc0 AO |
2347 | return 0; |
2348 | } | |
2349 | } | |
8c440872 | 2350 | gcc_assert (register_operand (op, VOIDmode)); |
0a2aaacc | 2351 | *opclass = H8OP_REGISTER; |
8c440872 | 2352 | return 0; |
beed8fc0 AO |
2353 | } |
2354 | ||
2355 | /* Return the length of the instruction described by TABLE given that | |
2356 | its operands are OP1 and OP2. OP1 must be an h8300_dst_operand | |
2357 | and OP2 must be an h8300_src_operand. */ | |
2358 | ||
2359 | static unsigned int | |
2360 | h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table) | |
2361 | { | |
2362 | enum h8300_operand_class op1_class, op2_class; | |
2363 | unsigned int size, immediate_length; | |
2364 | ||
2365 | size = GET_MODE_SIZE (GET_MODE (op1)); | |
2366 | immediate_length = (h8300_classify_operand (op1, size, &op1_class) | |
2367 | + h8300_classify_operand (op2, size, &op2_class)); | |
2368 | return immediate_length + (*table)[op1_class - 1][op2_class]; | |
2369 | } | |
2370 | ||
2371 | /* Return the length of a unary instruction such as neg or not given that | |
2372 | its operand is OP. */ | |
2373 | ||
2374 | unsigned int | |
2375 | h8300_unary_length (rtx op) | |
2376 | { | |
0a2aaacc | 2377 | enum h8300_operand_class opclass; |
beed8fc0 AO |
2378 | unsigned int size, operand_length; |
2379 | ||
2380 | size = GET_MODE_SIZE (GET_MODE (op)); | |
0a2aaacc KG |
2381 | operand_length = h8300_classify_operand (op, size, &opclass); |
2382 | switch (opclass) | |
beed8fc0 AO |
2383 | { |
2384 | case H8OP_REGISTER: | |
2385 | return 2; | |
2386 | ||
2387 | case H8OP_MEM_BASE: | |
2388 | return (size == 4 ? 6 : 4); | |
2389 | ||
2390 | case H8OP_MEM_ABSOLUTE: | |
2391 | return operand_length + (size == 4 ? 6 : 4); | |
2392 | ||
2393 | case H8OP_MEM_COMPLEX: | |
2394 | return operand_length + 6; | |
2395 | ||
2396 | default: | |
8c440872 | 2397 | gcc_unreachable (); |
beed8fc0 AO |
2398 | } |
2399 | } | |
2400 | ||
2401 | /* Likewise short immediate instructions such as add.w #xx:3,OP. */ | |
2402 | ||
2403 | static unsigned int | |
2404 | h8300_short_immediate_length (rtx op) | |
2405 | { | |
0a2aaacc | 2406 | enum h8300_operand_class opclass; |
beed8fc0 AO |
2407 | unsigned int size, operand_length; |
2408 | ||
2409 | size = GET_MODE_SIZE (GET_MODE (op)); | |
0a2aaacc | 2410 | operand_length = h8300_classify_operand (op, size, &opclass); |
beed8fc0 | 2411 | |
0a2aaacc | 2412 | switch (opclass) |
beed8fc0 AO |
2413 | { |
2414 | case H8OP_REGISTER: | |
2415 | return 2; | |
2416 | ||
2417 | case H8OP_MEM_BASE: | |
2418 | case H8OP_MEM_ABSOLUTE: | |
2419 | case H8OP_MEM_COMPLEX: | |
2420 | return 4 + operand_length; | |
2421 | ||
2422 | default: | |
8c440872 | 2423 | gcc_unreachable (); |
beed8fc0 AO |
2424 | } |
2425 | } | |
2426 | ||
2427 | /* Likewise bitfield load and store instructions. */ | |
48837e29 | 2428 | |
beed8fc0 AO |
2429 | static unsigned int |
2430 | h8300_bitfield_length (rtx op, rtx op2) | |
2431 | { | |
0a2aaacc | 2432 | enum h8300_operand_class opclass; |
beed8fc0 AO |
2433 | unsigned int size, operand_length; |
2434 | ||
2435 | if (GET_CODE (op) == REG) | |
2436 | op = op2; | |
8c440872 | 2437 | gcc_assert (GET_CODE (op) != REG); |
beed8fc0 AO |
2438 | |
2439 | size = GET_MODE_SIZE (GET_MODE (op)); | |
0a2aaacc | 2440 | operand_length = h8300_classify_operand (op, size, &opclass); |
beed8fc0 | 2441 | |
0a2aaacc | 2442 | switch (opclass) |
beed8fc0 AO |
2443 | { |
2444 | case H8OP_MEM_BASE: | |
2445 | case H8OP_MEM_ABSOLUTE: | |
2446 | case H8OP_MEM_COMPLEX: | |
2447 | return 4 + operand_length; | |
2448 | ||
2449 | default: | |
8c440872 | 2450 | gcc_unreachable (); |
07aae5c2 | 2451 | } |
48837e29 DE |
2452 | } |
2453 | ||
beed8fc0 | 2454 | /* Calculate the length of general binary instruction INSN using TABLE. */ |
8ccf5d5f | 2455 | |
beed8fc0 | 2456 | static unsigned int |
e7041fcc | 2457 | h8300_binary_length (rtx_insn *insn, const h8300_length_table *table) |
8ccf5d5f | 2458 | { |
beed8fc0 AO |
2459 | rtx set; |
2460 | ||
2461 | set = single_set (insn); | |
8c440872 | 2462 | gcc_assert (set); |
beed8fc0 AO |
2463 | |
2464 | if (BINARY_P (SET_SRC (set))) | |
2465 | return h8300_length_from_table (XEXP (SET_SRC (set), 0), | |
2466 | XEXP (SET_SRC (set), 1), table); | |
beed8fc0 | 2467 | else |
8c440872 NS |
2468 | { |
2469 | gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY); | |
2470 | return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0), | |
2471 | XEXP (XEXP (SET_SRC (set), 1), 1), | |
2472 | table); | |
2473 | } | |
8ccf5d5f KH |
2474 | } |
2475 | ||
beed8fc0 AO |
2476 | /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte |
2477 | memory reference and either (1) it has the form @(d:16,Rn) or | |
2478 | (2) its address has the code given by INC_CODE. */ | |
8ccf5d5f | 2479 | |
beed8fc0 AO |
2480 | static bool |
2481 | h8300_short_move_mem_p (rtx op, enum rtx_code inc_code) | |
8ccf5d5f | 2482 | { |
beed8fc0 AO |
2483 | rtx addr; |
2484 | unsigned int size; | |
2485 | ||
2486 | if (GET_CODE (op) != MEM) | |
2487 | return false; | |
2488 | ||
2489 | addr = XEXP (op, 0); | |
2490 | size = GET_MODE_SIZE (GET_MODE (op)); | |
2491 | if (size != 1 && size != 2) | |
2492 | return false; | |
2493 | ||
2494 | return (GET_CODE (addr) == inc_code | |
2495 | || (GET_CODE (addr) == PLUS | |
2496 | && GET_CODE (XEXP (addr, 0)) == REG | |
2497 | && h8300_displacement_length (addr, size) == 2)); | |
8ccf5d5f KH |
2498 | } |
2499 | ||
beed8fc0 AO |
2500 | /* Calculate the length of move instruction INSN using the given length |
2501 | table. Although the tables are correct for most cases, there is some | |
2502 | irregularity in the length of mov.b and mov.w. The following forms: | |
8ccf5d5f | 2503 | |
beed8fc0 AO |
2504 | mov @ERs+, Rd |
2505 | mov @(d:16,ERs), Rd | |
2506 | mov Rs, @-ERd | |
2507 | mov Rs, @(d:16,ERd) | |
2508 | ||
2509 | are two bytes shorter than most other "mov Rs, @complex" or | |
2510 | "mov @complex,Rd" combinations. */ | |
2511 | ||
2512 | static unsigned int | |
2513 | h8300_move_length (rtx *operands, const h8300_length_table *table) | |
8ccf5d5f | 2514 | { |
beed8fc0 AO |
2515 | unsigned int size; |
2516 | ||
2517 | size = h8300_length_from_table (operands[0], operands[1], table); | |
2518 | if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC)) | |
2519 | size -= 2; | |
2520 | if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC)) | |
2521 | size -= 2; | |
2522 | return size; | |
8ccf5d5f KH |
2523 | } |
2524 | ||
beed8fc0 AO |
2525 | /* Return the length of a mova instruction with the given operands. |
2526 | DEST is the register destination, SRC is the source address and | |
2527 | OFFSET is the 16-bit or 32-bit displacement. */ | |
2873836b | 2528 | |
beed8fc0 AO |
2529 | static unsigned int |
2530 | h8300_mova_length (rtx dest, rtx src, rtx offset) | |
2873836b | 2531 | { |
beed8fc0 AO |
2532 | unsigned int size; |
2533 | ||
2534 | size = (2 | |
2535 | + h8300_constant_length (offset) | |
2536 | + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0)); | |
2537 | if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest)) | |
2538 | size += 2; | |
2539 | return size; | |
2873836b KH |
2540 | } |
2541 | ||
beed8fc0 AO |
2542 | /* Compute the length of INSN based on its length_table attribute. |
2543 | OPERANDS is the array of its operands. */ | |
2873836b | 2544 | |
beed8fc0 | 2545 | unsigned int |
e7041fcc | 2546 | h8300_insn_length_from_table (rtx_insn *insn, rtx * operands) |
2873836b | 2547 | { |
beed8fc0 AO |
2548 | switch (get_attr_length_table (insn)) |
2549 | { | |
2550 | case LENGTH_TABLE_NONE: | |
8c440872 | 2551 | gcc_unreachable (); |
beed8fc0 AO |
2552 | |
2553 | case LENGTH_TABLE_ADDB: | |
2554 | return h8300_binary_length (insn, &addb_length_table); | |
2555 | ||
2556 | case LENGTH_TABLE_ADDW: | |
2557 | return h8300_binary_length (insn, &addw_length_table); | |
2558 | ||
2559 | case LENGTH_TABLE_ADDL: | |
2560 | return h8300_binary_length (insn, &addl_length_table); | |
2561 | ||
2562 | case LENGTH_TABLE_LOGICB: | |
2563 | return h8300_binary_length (insn, &logicb_length_table); | |
2564 | ||
2565 | case LENGTH_TABLE_MOVB: | |
2566 | return h8300_move_length (operands, &movb_length_table); | |
2567 | ||
2568 | case LENGTH_TABLE_MOVW: | |
2569 | return h8300_move_length (operands, &movw_length_table); | |
2570 | ||
2571 | case LENGTH_TABLE_MOVL: | |
2572 | return h8300_move_length (operands, &movl_length_table); | |
2573 | ||
2574 | case LENGTH_TABLE_MOVA: | |
2575 | return h8300_mova_length (operands[0], operands[1], operands[2]); | |
2576 | ||
2577 | case LENGTH_TABLE_MOVA_ZERO: | |
2578 | return h8300_mova_length (operands[0], operands[1], const0_rtx); | |
2579 | ||
2580 | case LENGTH_TABLE_UNARY: | |
2581 | return h8300_unary_length (operands[0]); | |
2582 | ||
2583 | case LENGTH_TABLE_MOV_IMM4: | |
2584 | return 2 + h8300_classify_operand (operands[0], 0, 0); | |
2585 | ||
2586 | case LENGTH_TABLE_SHORT_IMMEDIATE: | |
2587 | return h8300_short_immediate_length (operands[0]); | |
2588 | ||
2589 | case LENGTH_TABLE_BITFIELD: | |
2590 | return h8300_bitfield_length (operands[0], operands[1]); | |
2591 | ||
2592 | case LENGTH_TABLE_BITBRANCH: | |
2593 | return h8300_bitfield_length (operands[1], operands[2]) - 2; | |
8c440872 NS |
2594 | |
2595 | default: | |
2596 | gcc_unreachable (); | |
beed8fc0 | 2597 | } |
2873836b KH |
2598 | } |
2599 | ||
beed8fc0 AO |
2600 | /* Return true if LHS and RHS are memory references that can be mapped |
2601 | to the same h8sx assembly operand. LHS appears as the destination of | |
2602 | an instruction and RHS appears as a source. | |
f9d2de4d | 2603 | |
beed8fc0 AO |
2604 | Three cases are allowed: |
2605 | ||
2606 | - RHS is @+Rn or @-Rn, LHS is @Rn | |
2607 | - RHS is @Rn, LHS is @Rn+ or @Rn- | |
2608 | - RHS and LHS have the same address and neither has side effects. */ | |
2609 | ||
2610 | bool | |
2611 | h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs) | |
f9d2de4d | 2612 | { |
beed8fc0 AO |
2613 | if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM) |
2614 | { | |
2615 | rhs = XEXP (rhs, 0); | |
2616 | lhs = XEXP (lhs, 0); | |
2617 | ||
2618 | if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC) | |
2619 | return rtx_equal_p (XEXP (rhs, 0), lhs); | |
2620 | ||
2621 | if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC) | |
2622 | return rtx_equal_p (rhs, XEXP (lhs, 0)); | |
2623 | ||
2624 | if (rtx_equal_p (rhs, lhs)) | |
2625 | return true; | |
2626 | } | |
2627 | return false; | |
f9d2de4d KH |
2628 | } |
2629 | ||
beed8fc0 AO |
2630 | /* Return true if OPERANDS[1] can be mapped to the same assembly |
2631 | operand as OPERANDS[0]. */ | |
f9d2de4d | 2632 | |
beed8fc0 AO |
2633 | bool |
2634 | h8300_operands_match_p (rtx *operands) | |
f9d2de4d | 2635 | { |
beed8fc0 AO |
2636 | if (register_operand (operands[0], VOIDmode) |
2637 | && register_operand (operands[1], VOIDmode)) | |
2638 | return true; | |
f9d2de4d | 2639 | |
beed8fc0 AO |
2640 | if (h8sx_mergeable_memrefs_p (operands[0], operands[1])) |
2641 | return true; | |
2642 | ||
2643 | return false; | |
f9d2de4d | 2644 | } |
beed8fc0 AO |
2645 | \f |
2646 | /* Try using movmd to move LENGTH bytes from memory region SRC to memory | |
2647 | region DEST. The two regions do not overlap and have the common | |
2648 | alignment given by ALIGNMENT. Return true on success. | |
717d8b71 | 2649 | |
beed8fc0 AO |
2650 | Using movmd for variable-length moves seems to involve some |
2651 | complex trade-offs. For instance: | |
b059c02a | 2652 | |
beed8fc0 AO |
2653 | - Preparing for a movmd instruction is similar to preparing |
2654 | for a memcpy. The main difference is that the arguments | |
2655 | are moved into er4, er5 and er6 rather than er0, er1 and er2. | |
2656 | ||
2657 | - Since movmd clobbers the frame pointer, we need to save | |
2658 | and restore it somehow when frame_pointer_needed. This can | |
2659 | sometimes make movmd sequences longer than calls to memcpy(). | |
2660 | ||
2661 | - The counter register is 16 bits, so the instruction is only | |
2662 | suitable for variable-length moves when sizeof (size_t) == 2. | |
2663 | That's only true in normal mode. | |
2664 | ||
2665 | - We will often lack static alignment information. Falling back | |
2666 | on movmd.b would likely be slower than calling memcpy(), at least | |
2667 | for big moves. | |
2668 | ||
2669 | This function therefore only uses movmd when the length is a | |
2670 | known constant, and only then if -fomit-frame-pointer is in | |
2671 | effect or if we're not optimizing for size. | |
2672 | ||
2673 | At the moment the function uses movmd for all in-range constants, | |
2674 | but it might be better to fall back on memcpy() for large moves | |
2675 | if ALIGNMENT == 1. */ | |
2676 | ||
2677 | bool | |
2678 | h8sx_emit_movmd (rtx dest, rtx src, rtx length, | |
2679 | HOST_WIDE_INT alignment) | |
b059c02a | 2680 | { |
beed8fc0 AO |
2681 | if (!flag_omit_frame_pointer && optimize_size) |
2682 | return false; | |
b059c02a | 2683 | |
beed8fc0 AO |
2684 | if (GET_CODE (length) == CONST_INT) |
2685 | { | |
2686 | rtx dest_reg, src_reg, first_dest, first_src; | |
2687 | HOST_WIDE_INT n; | |
2688 | int factor; | |
2689 | ||
2690 | /* Use movmd.l if the alignment allows it, otherwise fall back | |
2691 | on movmd.b. */ | |
2692 | factor = (alignment >= 2 ? 4 : 1); | |
2693 | ||
2694 | /* Make sure the length is within range. We can handle counter | |
2695 | values up to 65536, although HImode truncation will make | |
2696 | the count appear negative in rtl dumps. */ | |
2697 | n = INTVAL (length); | |
2698 | if (n <= 0 || n / factor > 65536) | |
2699 | return false; | |
2700 | ||
2701 | /* Create temporary registers for the source and destination | |
2702 | pointers. Initialize them to the start of each region. */ | |
2703 | dest_reg = copy_addr_to_reg (XEXP (dest, 0)); | |
2704 | src_reg = copy_addr_to_reg (XEXP (src, 0)); | |
2705 | ||
2706 | /* Create references to the movmd source and destination blocks. */ | |
2707 | first_dest = replace_equiv_address (dest, dest_reg); | |
2708 | first_src = replace_equiv_address (src, src_reg); | |
2709 | ||
f5541398 RS |
2710 | set_mem_size (first_dest, n & -factor); |
2711 | set_mem_size (first_src, n & -factor); | |
beed8fc0 AO |
2712 | |
2713 | length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode)); | |
2714 | emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor))); | |
2715 | ||
2716 | if ((n & -factor) != n) | |
2717 | { | |
2718 | /* Move SRC and DEST past the region we just copied. | |
2719 | This is done to update the memory attributes. */ | |
2720 | dest = adjust_address (dest, BLKmode, n & -factor); | |
2721 | src = adjust_address (src, BLKmode, n & -factor); | |
2722 | ||
2723 | /* Replace the addresses with the source and destination | |
2724 | registers, which movmd has left with the right values. */ | |
2725 | dest = replace_equiv_address (dest, dest_reg); | |
2726 | src = replace_equiv_address (src, src_reg); | |
2727 | ||
2728 | /* Mop up the left-over bytes. */ | |
2729 | if (n & 2) | |
2730 | emit_move_insn (adjust_address (dest, HImode, 0), | |
2731 | adjust_address (src, HImode, 0)); | |
2732 | if (n & 1) | |
2733 | emit_move_insn (adjust_address (dest, QImode, n & 2), | |
2734 | adjust_address (src, QImode, n & 2)); | |
2735 | } | |
2736 | return true; | |
2737 | } | |
2738 | return false; | |
b059c02a KH |
2739 | } |
2740 | ||
beed8fc0 | 2741 | /* Move ADDR into er6 after pushing its old value onto the stack. */ |
48837e29 | 2742 | |
beed8fc0 AO |
2743 | void |
2744 | h8300_swap_into_er6 (rtx addr) | |
48837e29 | 2745 | { |
8f1594b2 RH |
2746 | rtx insn = push (HARD_FRAME_POINTER_REGNUM); |
2747 | if (frame_pointer_needed) | |
2748 | add_reg_note (insn, REG_CFA_DEF_CFA, | |
0a81f074 | 2749 | plus_constant (Pmode, gen_rtx_MEM (Pmode, stack_pointer_rtx), |
8f1594b2 RH |
2750 | 2 * UNITS_PER_WORD)); |
2751 | else | |
2752 | add_reg_note (insn, REG_CFA_ADJUST_CFA, | |
2753 | gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
0a81f074 | 2754 | plus_constant (Pmode, stack_pointer_rtx, 4))); |
8f1594b2 | 2755 | |
beed8fc0 AO |
2756 | emit_move_insn (hard_frame_pointer_rtx, addr); |
2757 | if (REGNO (addr) == SP_REG) | |
2758 | emit_move_insn (hard_frame_pointer_rtx, | |
0a81f074 | 2759 | plus_constant (Pmode, hard_frame_pointer_rtx, |
beed8fc0 AO |
2760 | GET_MODE_SIZE (word_mode))); |
2761 | } | |
07aae5c2 | 2762 | |
beed8fc0 AO |
2763 | /* Move the current value of er6 into ADDR and pop its old value |
2764 | from the stack. */ | |
2765 | ||
2766 | void | |
2767 | h8300_swap_out_of_er6 (rtx addr) | |
2768 | { | |
8f1594b2 RH |
2769 | rtx insn; |
2770 | ||
beed8fc0 AO |
2771 | if (REGNO (addr) != SP_REG) |
2772 | emit_move_insn (addr, hard_frame_pointer_rtx); | |
8f1594b2 RH |
2773 | |
2774 | insn = pop (HARD_FRAME_POINTER_REGNUM); | |
2775 | RTX_FRAME_RELATED_P (insn) = 1; | |
2776 | if (frame_pointer_needed) | |
2777 | add_reg_note (insn, REG_CFA_DEF_CFA, | |
0a81f074 RS |
2778 | plus_constant (Pmode, hard_frame_pointer_rtx, |
2779 | 2 * UNITS_PER_WORD)); | |
8f1594b2 RH |
2780 | else |
2781 | add_reg_note (insn, REG_CFA_ADJUST_CFA, | |
2782 | gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
0a81f074 | 2783 | plus_constant (Pmode, stack_pointer_rtx, -4))); |
07aae5c2 | 2784 | } |
48837e29 | 2785 | \f |
7948a9ea KH |
2786 | /* Return the length of mov instruction. */ |
2787 | ||
2788 | unsigned int | |
2789 | compute_mov_length (rtx *operands) | |
2790 | { | |
2791 | /* If the mov instruction involves a memory operand, we compute the | |
2792 | length, assuming the largest addressing mode is used, and then | |
2793 | adjust later in the function. Otherwise, we compute and return | |
2794 | the exact length in one step. */ | |
2795 | enum machine_mode mode = GET_MODE (operands[0]); | |
2796 | rtx dest = operands[0]; | |
2797 | rtx src = operands[1]; | |
2798 | rtx addr; | |
2799 | ||
2800 | if (GET_CODE (src) == MEM) | |
2801 | addr = XEXP (src, 0); | |
2802 | else if (GET_CODE (dest) == MEM) | |
2803 | addr = XEXP (dest, 0); | |
2804 | else | |
2805 | addr = NULL_RTX; | |
2806 | ||
2807 | if (TARGET_H8300) | |
2808 | { | |
2809 | unsigned int base_length; | |
2810 | ||
2811 | switch (mode) | |
2812 | { | |
2813 | case QImode: | |
2814 | if (addr == NULL_RTX) | |
2815 | return 2; | |
2816 | ||
2817 | /* The eightbit addressing is available only in QImode, so | |
2818 | go ahead and take care of it. */ | |
2819 | if (h8300_eightbit_constant_address_p (addr)) | |
2820 | return 2; | |
2821 | ||
2822 | base_length = 4; | |
2823 | break; | |
2824 | ||
2825 | case HImode: | |
2826 | if (addr == NULL_RTX) | |
2827 | { | |
2828 | if (REG_P (src)) | |
2829 | return 2; | |
2830 | ||
2831 | if (src == const0_rtx) | |
2832 | return 2; | |
2833 | ||
2834 | return 4; | |
2835 | } | |
2836 | ||
2837 | base_length = 4; | |
2838 | break; | |
2839 | ||
2840 | case SImode: | |
2841 | if (addr == NULL_RTX) | |
2842 | { | |
2843 | if (REG_P (src)) | |
2844 | return 4; | |
2845 | ||
2846 | if (GET_CODE (src) == CONST_INT) | |
2847 | { | |
2848 | if (src == const0_rtx) | |
2849 | return 4; | |
2850 | ||
2851 | if ((INTVAL (src) & 0xffff) == 0) | |
2852 | return 6; | |
2853 | ||
2854 | if ((INTVAL (src) & 0xffff) == 0) | |
2855 | return 6; | |
f5139cc5 KH |
2856 | |
2857 | if ((INTVAL (src) & 0xffff) | |
2858 | == ((INTVAL (src) >> 16) & 0xffff)) | |
2859 | return 6; | |
7948a9ea KH |
2860 | } |
2861 | return 8; | |
2862 | } | |
2863 | ||
2864 | base_length = 8; | |
2865 | break; | |
2866 | ||
2867 | case SFmode: | |
2868 | if (addr == NULL_RTX) | |
2869 | { | |
2870 | if (REG_P (src)) | |
2871 | return 4; | |
2872 | ||
ceaaaeab | 2873 | if (satisfies_constraint_G (src)) |
2c4a71b3 KH |
2874 | return 4; |
2875 | ||
81983b04 | 2876 | return 8; |
7948a9ea KH |
2877 | } |
2878 | ||
2879 | base_length = 8; | |
2880 | break; | |
2881 | ||
2882 | default: | |
8c440872 | 2883 | gcc_unreachable (); |
7948a9ea KH |
2884 | } |
2885 | ||
2886 | /* Adjust the length based on the addressing mode used. | |
2887 | Specifically, we subtract the difference between the actual | |
2888 | length and the longest one, which is @(d:16,Rs). For SImode | |
2889 | and SFmode, we double the adjustment because two mov.w are | |
2890 | used to do the job. */ | |
2891 | ||
2892 | /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */ | |
2893 | if (GET_CODE (addr) == PRE_DEC | |
2894 | || GET_CODE (addr) == POST_INC) | |
2895 | { | |
2896 | if (mode == QImode || mode == HImode) | |
2897 | return base_length - 2; | |
2898 | else | |
2899 | /* In SImode and SFmode, we use two mov.w instructions, so | |
2a43945f | 2900 | double the adjustment. */ |
7948a9ea KH |
2901 | return base_length - 4; |
2902 | } | |
2903 | ||
2904 | /* @Rs and @Rd are 2 bytes shorter than the longest. Note that | |
2905 | in SImode and SFmode, the second mov.w involves an address | |
2906 | with displacement, namely @(2,Rs) or @(2,Rd), so we subtract | |
2907 | only 2 bytes. */ | |
2908 | if (GET_CODE (addr) == REG) | |
2909 | return base_length - 2; | |
2910 | ||
2911 | return base_length; | |
2912 | } | |
2913 | else | |
2914 | { | |
2915 | unsigned int base_length; | |
2916 | ||
2917 | switch (mode) | |
2918 | { | |
2919 | case QImode: | |
2920 | if (addr == NULL_RTX) | |
2921 | return 2; | |
2922 | ||
2923 | /* The eightbit addressing is available only in QImode, so | |
2924 | go ahead and take care of it. */ | |
2925 | if (h8300_eightbit_constant_address_p (addr)) | |
2926 | return 2; | |
2927 | ||
2928 | base_length = 8; | |
2929 | break; | |
2930 | ||
2931 | case HImode: | |
2932 | if (addr == NULL_RTX) | |
2933 | { | |
2934 | if (REG_P (src)) | |
2935 | return 2; | |
2936 | ||
2937 | if (src == const0_rtx) | |
2938 | return 2; | |
2939 | ||
2940 | return 4; | |
2941 | } | |
2942 | ||
2943 | base_length = 8; | |
2944 | break; | |
2945 | ||
2946 | case SImode: | |
2947 | if (addr == NULL_RTX) | |
2948 | { | |
2949 | if (REG_P (src)) | |
2950 | { | |
2951 | if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG) | |
2952 | return 4; | |
2953 | else | |
2954 | return 2; | |
2955 | } | |
2956 | ||
2957 | if (GET_CODE (src) == CONST_INT) | |
2958 | { | |
2959 | int val = INTVAL (src); | |
2960 | ||
2961 | if (val == 0) | |
2962 | return 2; | |
2963 | ||
2964 | if (val == (val & 0x00ff) || val == (val & 0xff00)) | |
2965 | return 4; | |
80e58519 | 2966 | |
7948a9ea KH |
2967 | switch (val & 0xffffffff) |
2968 | { | |
2969 | case 0xffffffff: | |
2970 | case 0xfffffffe: | |
2971 | case 0xfffffffc: | |
2972 | case 0x0000ffff: | |
2973 | case 0x0000fffe: | |
2974 | case 0xffff0000: | |
2975 | case 0xfffe0000: | |
2976 | case 0x00010000: | |
2977 | case 0x00020000: | |
2978 | return 4; | |
2979 | } | |
2980 | } | |
2981 | return 6; | |
2982 | } | |
2983 | ||
2984 | base_length = 10; | |
2985 | break; | |
2986 | ||
2987 | case SFmode: | |
2988 | if (addr == NULL_RTX) | |
2989 | { | |
2990 | if (REG_P (src)) | |
2991 | return 2; | |
2992 | ||
ceaaaeab | 2993 | if (satisfies_constraint_G (src)) |
7948a9ea | 2994 | return 2; |
2c4a71b3 | 2995 | |
7948a9ea KH |
2996 | return 6; |
2997 | } | |
2998 | ||
2999 | base_length = 10; | |
3000 | break; | |
3001 | ||
3002 | default: | |
8c440872 | 3003 | gcc_unreachable (); |
7948a9ea KH |
3004 | } |
3005 | ||
3006 | /* Adjust the length based on the addressing mode used. | |
3007 | Specifically, we subtract the difference between the actual | |
3008 | length and the longest one, which is @(d:24,ERs). */ | |
3009 | ||
3010 | /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */ | |
3011 | if (GET_CODE (addr) == PRE_DEC | |
3012 | || GET_CODE (addr) == POST_INC) | |
3013 | return base_length - 6; | |
3014 | ||
3015 | /* @ERs and @ERd are 6 bytes shorter than the longest. */ | |
3016 | if (GET_CODE (addr) == REG) | |
3017 | return base_length - 6; | |
3018 | ||
3019 | /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the | |
3020 | longest. */ | |
3021 | if (GET_CODE (addr) == PLUS | |
3022 | && GET_CODE (XEXP (addr, 0)) == REG | |
3023 | && GET_CODE (XEXP (addr, 1)) == CONST_INT | |
3024 | && INTVAL (XEXP (addr, 1)) > -32768 | |
3025 | && INTVAL (XEXP (addr, 1)) < 32767) | |
3026 | return base_length - 4; | |
3027 | ||
3028 | /* @aa:16 is 4 bytes shorter than the longest. */ | |
3029 | if (h8300_tiny_constant_address_p (addr)) | |
3030 | return base_length - 4; | |
3031 | ||
3032 | /* @aa:24 is 2 bytes shorter than the longest. */ | |
3033 | if (CONSTANT_P (addr)) | |
3034 | return base_length - 2; | |
3035 | ||
3036 | return base_length; | |
3037 | } | |
3038 | } | |
3039 | \f | |
e9eba255 KH |
3040 | /* Output an addition insn. */ |
3041 | ||
366a7b27 | 3042 | const char * |
cb713a8d | 3043 | output_plussi (rtx *operands) |
7d6ac401 KH |
3044 | { |
3045 | enum machine_mode mode = GET_MODE (operands[0]); | |
3046 | ||
8c440872 | 3047 | gcc_assert (mode == SImode); |
7d6ac401 KH |
3048 | |
3049 | if (TARGET_H8300) | |
3050 | { | |
cfedf91b KH |
3051 | if (GET_CODE (operands[2]) == REG) |
3052 | return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0"; | |
3053 | ||
3054 | if (GET_CODE (operands[2]) == CONST_INT) | |
3055 | { | |
3056 | HOST_WIDE_INT n = INTVAL (operands[2]); | |
3057 | ||
3058 | if ((n & 0xffffff) == 0) | |
3059 | return "add\t%z2,%z0"; | |
3060 | if ((n & 0xffff) == 0) | |
3061 | return "add\t%y2,%y0\n\taddx\t%z2,%z0"; | |
3062 | if ((n & 0xff) == 0) | |
3063 | return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0"; | |
3064 | } | |
3065 | ||
3066 | return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0"; | |
7d6ac401 KH |
3067 | } |
3068 | else | |
3069 | { | |
beed8fc0 AO |
3070 | if (GET_CODE (operands[2]) == CONST_INT |
3071 | && register_operand (operands[1], VOIDmode)) | |
7d6ac401 KH |
3072 | { |
3073 | HOST_WIDE_INT intval = INTVAL (operands[2]); | |
3074 | ||
beed8fc0 AO |
3075 | if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) |
3076 | return "add.l\t%S2,%S0"; | |
3077 | if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) | |
3078 | return "sub.l\t%G2,%S0"; | |
3079 | ||
7d6ac401 KH |
3080 | /* See if we can finish with 2 bytes. */ |
3081 | ||
9ac7ebba | 3082 | switch ((unsigned int) intval & 0xffffffff) |
7d6ac401 KH |
3083 | { |
3084 | case 0x00000001: | |
3085 | case 0x00000002: | |
3086 | case 0x00000004: | |
3087 | return "adds\t%2,%S0"; | |
3088 | ||
3089 | case 0xffffffff: | |
3090 | case 0xfffffffe: | |
3091 | case 0xfffffffc: | |
3092 | return "subs\t%G2,%S0"; | |
3093 | ||
3094 | case 0x00010000: | |
3095 | case 0x00020000: | |
3096 | operands[2] = GEN_INT (intval >> 16); | |
3097 | return "inc.w\t%2,%e0"; | |
3098 | ||
3099 | case 0xffff0000: | |
3100 | case 0xfffe0000: | |
3101 | operands[2] = GEN_INT (intval >> 16); | |
3102 | return "dec.w\t%G2,%e0"; | |
3103 | } | |
3104 | ||
3105 | /* See if we can finish with 4 bytes. */ | |
3106 | if ((intval & 0xffff) == 0) | |
3107 | { | |
3108 | operands[2] = GEN_INT (intval >> 16); | |
3109 | return "add.w\t%2,%e0"; | |
3110 | } | |
3111 | } | |
3112 | ||
beed8fc0 AO |
3113 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) |
3114 | { | |
3115 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
3116 | return "sub.l\t%S2,%S0"; | |
3117 | } | |
7d6ac401 KH |
3118 | return "add.l\t%S2,%S0"; |
3119 | } | |
3120 | } | |
3121 | ||
beed8fc0 AO |
3122 | /* ??? It would be much easier to add the h8sx stuff if a single function |
3123 | classified the addition as either inc/dec, adds/subs, add.w or add.l. */ | |
e9eba255 KH |
3124 | /* Compute the length of an addition insn. */ |
3125 | ||
7d6ac401 | 3126 | unsigned int |
cb713a8d | 3127 | compute_plussi_length (rtx *operands) |
7d6ac401 KH |
3128 | { |
3129 | enum machine_mode mode = GET_MODE (operands[0]); | |
3130 | ||
8c440872 | 3131 | gcc_assert (mode == SImode); |
7d6ac401 KH |
3132 | |
3133 | if (TARGET_H8300) | |
3134 | { | |
cfedf91b KH |
3135 | if (GET_CODE (operands[2]) == REG) |
3136 | return 6; | |
3137 | ||
3138 | if (GET_CODE (operands[2]) == CONST_INT) | |
3139 | { | |
3140 | HOST_WIDE_INT n = INTVAL (operands[2]); | |
3141 | ||
3142 | if ((n & 0xffffff) == 0) | |
3143 | return 2; | |
3144 | if ((n & 0xffff) == 0) | |
3145 | return 4; | |
3146 | if ((n & 0xff) == 0) | |
3147 | return 6; | |
3148 | } | |
3149 | ||
3150 | return 8; | |
7d6ac401 KH |
3151 | } |
3152 | else | |
3153 | { | |
beed8fc0 AO |
3154 | if (GET_CODE (operands[2]) == CONST_INT |
3155 | && register_operand (operands[1], VOIDmode)) | |
7d6ac401 KH |
3156 | { |
3157 | HOST_WIDE_INT intval = INTVAL (operands[2]); | |
3158 | ||
beed8fc0 AO |
3159 | if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) |
3160 | return 2; | |
3161 | if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) | |
3162 | return 2; | |
3163 | ||
7d6ac401 KH |
3164 | /* See if we can finish with 2 bytes. */ |
3165 | ||
9ac7ebba | 3166 | switch ((unsigned int) intval & 0xffffffff) |
7d6ac401 KH |
3167 | { |
3168 | case 0x00000001: | |
3169 | case 0x00000002: | |
3170 | case 0x00000004: | |
3171 | return 2; | |
3172 | ||
3173 | case 0xffffffff: | |
3174 | case 0xfffffffe: | |
3175 | case 0xfffffffc: | |
3176 | return 2; | |
3177 | ||
3178 | case 0x00010000: | |
3179 | case 0x00020000: | |
3180 | return 2; | |
3181 | ||
3182 | case 0xffff0000: | |
3183 | case 0xfffe0000: | |
3184 | return 2; | |
3185 | } | |
3186 | ||
3187 | /* See if we can finish with 4 bytes. */ | |
3188 | if ((intval & 0xffff) == 0) | |
3189 | return 4; | |
3190 | } | |
3191 | ||
beed8fc0 AO |
3192 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) |
3193 | return h8300_length_from_table (operands[0], | |
3194 | GEN_INT (-INTVAL (operands[2])), | |
3195 | &addl_length_table); | |
3196 | else | |
3197 | return h8300_length_from_table (operands[0], operands[2], | |
3198 | &addl_length_table); | |
7d6ac401 KH |
3199 | return 6; |
3200 | } | |
3201 | } | |
3202 | ||
e9eba255 KH |
3203 | /* Compute which flag bits are valid after an addition insn. */ |
3204 | ||
9690aa8e | 3205 | enum attr_cc |
cb713a8d | 3206 | compute_plussi_cc (rtx *operands) |
7d6ac401 KH |
3207 | { |
3208 | enum machine_mode mode = GET_MODE (operands[0]); | |
3209 | ||
8c440872 | 3210 | gcc_assert (mode == SImode); |
7d6ac401 KH |
3211 | |
3212 | if (TARGET_H8300) | |
3213 | { | |
cfedf91b | 3214 | return CC_CLOBBER; |
7d6ac401 KH |
3215 | } |
3216 | else | |
3217 | { | |
beed8fc0 AO |
3218 | if (GET_CODE (operands[2]) == CONST_INT |
3219 | && register_operand (operands[1], VOIDmode)) | |
7d6ac401 KH |
3220 | { |
3221 | HOST_WIDE_INT intval = INTVAL (operands[2]); | |
3222 | ||
beed8fc0 AO |
3223 | if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) |
3224 | return CC_SET_ZN; | |
3225 | if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) | |
3226 | return CC_SET_ZN; | |
3227 | ||
7d6ac401 KH |
3228 | /* See if we can finish with 2 bytes. */ |
3229 | ||
9ac7ebba | 3230 | switch ((unsigned int) intval & 0xffffffff) |
7d6ac401 KH |
3231 | { |
3232 | case 0x00000001: | |
3233 | case 0x00000002: | |
3234 | case 0x00000004: | |
3235 | return CC_NONE_0HIT; | |
3236 | ||
3237 | case 0xffffffff: | |
3238 | case 0xfffffffe: | |
3239 | case 0xfffffffc: | |
3240 | return CC_NONE_0HIT; | |
3241 | ||
3242 | case 0x00010000: | |
3243 | case 0x00020000: | |
3244 | return CC_CLOBBER; | |
3245 | ||
3246 | case 0xffff0000: | |
3247 | case 0xfffe0000: | |
3248 | return CC_CLOBBER; | |
3249 | } | |
3250 | ||
3251 | /* See if we can finish with 4 bytes. */ | |
3252 | if ((intval & 0xffff) == 0) | |
3253 | return CC_CLOBBER; | |
3254 | } | |
3255 | ||
3256 | return CC_SET_ZN; | |
3257 | } | |
3258 | } | |
3259 | \f | |
e9eba255 KH |
3260 | /* Output a logical insn. */ |
3261 | ||
7d6ac401 | 3262 | const char * |
cb713a8d | 3263 | output_logical_op (enum machine_mode mode, rtx *operands) |
366a7b27 | 3264 | { |
b42cff6b KH |
3265 | /* Figure out the logical op that we need to perform. */ |
3266 | enum rtx_code code = GET_CODE (operands[3]); | |
366a7b27 | 3267 | /* Pretend that every byte is affected if both operands are registers. */ |
7798db98 | 3268 | const unsigned HOST_WIDE_INT intval = |
366a7b27 | 3269 | (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT) |
beed8fc0 AO |
3270 | /* Always use the full instruction if the |
3271 | first operand is in memory. It is better | |
3272 | to use define_splits to generate the shorter | |
3273 | sequence where valid. */ | |
3274 | && register_operand (operands[1], VOIDmode) | |
366a7b27 KH |
3275 | ? INTVAL (operands[2]) : 0x55555555); |
3276 | /* The determinant of the algorithm. If we perform an AND, 0 | |
3277 | affects a bit. Otherwise, 1 affects a bit. */ | |
7798db98 | 3278 | const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval; |
f9ac2f95 KH |
3279 | /* Break up DET into pieces. */ |
3280 | const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff; | |
3281 | const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff; | |
c5e7ce43 KH |
3282 | const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff; |
3283 | const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff; | |
f9ac2f95 KH |
3284 | const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff; |
3285 | const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff; | |
3286 | int lower_half_easy_p = 0; | |
3287 | int upper_half_easy_p = 0; | |
366a7b27 KH |
3288 | /* The name of an insn. */ |
3289 | const char *opname; | |
3290 | char insn_buf[100]; | |
3291 | ||
3292 | switch (code) | |
3293 | { | |
3294 | case AND: | |
3295 | opname = "and"; | |
3296 | break; | |
3297 | case IOR: | |
3298 | opname = "or"; | |
3299 | break; | |
3300 | case XOR: | |
3301 | opname = "xor"; | |
3302 | break; | |
3303 | default: | |
8c440872 | 3304 | gcc_unreachable (); |
366a7b27 KH |
3305 | } |
3306 | ||
3307 | switch (mode) | |
3308 | { | |
3309 | case HImode: | |
3310 | /* First, see if we can finish with one insn. */ | |
3311 | if ((TARGET_H8300H || TARGET_H8300S) | |
c5e7ce43 KH |
3312 | && b0 != 0 |
3313 | && b1 != 0) | |
366a7b27 KH |
3314 | { |
3315 | sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname); | |
3316 | output_asm_insn (insn_buf, operands); | |
3317 | } | |
3318 | else | |
3319 | { | |
3320 | /* Take care of the lower byte. */ | |
c5e7ce43 | 3321 | if (b0 != 0) |
366a7b27 KH |
3322 | { |
3323 | sprintf (insn_buf, "%s\t%%s2,%%s0", opname); | |
3324 | output_asm_insn (insn_buf, operands); | |
3325 | } | |
3326 | /* Take care of the upper byte. */ | |
c5e7ce43 | 3327 | if (b1 != 0) |
366a7b27 KH |
3328 | { |
3329 | sprintf (insn_buf, "%s\t%%t2,%%t0", opname); | |
3330 | output_asm_insn (insn_buf, operands); | |
3331 | } | |
3332 | } | |
3333 | break; | |
3334 | case SImode: | |
f9ac2f95 KH |
3335 | if (TARGET_H8300H || TARGET_H8300S) |
3336 | { | |
3337 | /* Determine if the lower half can be taken care of in no more | |
3338 | than two bytes. */ | |
3339 | lower_half_easy_p = (b0 == 0 | |
3340 | || b1 == 0 | |
3341 | || (code != IOR && w0 == 0xffff)); | |
3342 | ||
3343 | /* Determine if the upper half can be taken care of in no more | |
3344 | than two bytes. */ | |
3345 | upper_half_easy_p = ((code != IOR && w1 == 0xffff) | |
3346 | || (code == AND && w1 == 0xff00)); | |
3347 | } | |
366a7b27 | 3348 | |
f9ac2f95 KH |
3349 | /* Check if doing everything with one insn is no worse than |
3350 | using multiple insns. */ | |
366a7b27 | 3351 | if ((TARGET_H8300H || TARGET_H8300S) |
f9ac2f95 | 3352 | && w0 != 0 && w1 != 0 |
472f2723 KH |
3353 | && !(lower_half_easy_p && upper_half_easy_p) |
3354 | && !(code == IOR && w1 == 0xffff | |
3355 | && (w0 & 0x8000) != 0 && lower_half_easy_p)) | |
366a7b27 KH |
3356 | { |
3357 | sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname); | |
3358 | output_asm_insn (insn_buf, operands); | |
3359 | } | |
3360 | else | |
3361 | { | |
3362 | /* Take care of the lower and upper words individually. For | |
3363 | each word, we try different methods in the order of | |
3364 | ||
3365 | 1) the special insn (in case of AND or XOR), | |
3366 | 2) the word-wise insn, and | |
3367 | 3) The byte-wise insn. */ | |
c5e7ce43 | 3368 | if (w0 == 0xffff |
6dfa4005 | 3369 | && (TARGET_H8300 ? (code == AND) : (code != IOR))) |
366a7b27 | 3370 | output_asm_insn ((code == AND) |
187462ac | 3371 | ? "sub.w\t%f0,%f0" : "not.w\t%f0", |
366a7b27 KH |
3372 | operands); |
3373 | else if ((TARGET_H8300H || TARGET_H8300S) | |
c5e7ce43 KH |
3374 | && (b0 != 0) |
3375 | && (b1 != 0)) | |
366a7b27 KH |
3376 | { |
3377 | sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname); | |
3378 | output_asm_insn (insn_buf, operands); | |
3379 | } | |
3380 | else | |
3381 | { | |
c5e7ce43 | 3382 | if (b0 != 0) |
366a7b27 KH |
3383 | { |
3384 | sprintf (insn_buf, "%s\t%%w2,%%w0", opname); | |
3385 | output_asm_insn (insn_buf, operands); | |
3386 | } | |
c5e7ce43 | 3387 | if (b1 != 0) |
366a7b27 KH |
3388 | { |
3389 | sprintf (insn_buf, "%s\t%%x2,%%x0", opname); | |
3390 | output_asm_insn (insn_buf, operands); | |
3391 | } | |
3392 | } | |
3393 | ||
c5e7ce43 | 3394 | if ((w1 == 0xffff) |
6dfa4005 | 3395 | && (TARGET_H8300 ? (code == AND) : (code != IOR))) |
366a7b27 | 3396 | output_asm_insn ((code == AND) |
187462ac | 3397 | ? "sub.w\t%e0,%e0" : "not.w\t%e0", |
366a7b27 | 3398 | operands); |
472f2723 KH |
3399 | else if ((TARGET_H8300H || TARGET_H8300S) |
3400 | && code == IOR | |
3401 | && w1 == 0xffff | |
3402 | && (w0 & 0x8000) != 0) | |
3403 | { | |
3404 | output_asm_insn ("exts.l\t%S0", operands); | |
3405 | } | |
a6e8d113 KH |
3406 | else if ((TARGET_H8300H || TARGET_H8300S) |
3407 | && code == AND | |
c5e7ce43 | 3408 | && w1 == 0xff00) |
a6e8d113 | 3409 | { |
dc5f17ec | 3410 | output_asm_insn ("extu.w\t%e0", operands); |
a6e8d113 | 3411 | } |
366a7b27 KH |
3412 | else if (TARGET_H8300H || TARGET_H8300S) |
3413 | { | |
c5e7ce43 | 3414 | if (w1 != 0) |
366a7b27 KH |
3415 | { |
3416 | sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname); | |
3417 | output_asm_insn (insn_buf, operands); | |
3418 | } | |
3419 | } | |
3420 | else | |
3421 | { | |
c5e7ce43 | 3422 | if (b2 != 0) |
366a7b27 KH |
3423 | { |
3424 | sprintf (insn_buf, "%s\t%%y2,%%y0", opname); | |
3425 | output_asm_insn (insn_buf, operands); | |
3426 | } | |
c5e7ce43 | 3427 | if (b3 != 0) |
366a7b27 KH |
3428 | { |
3429 | sprintf (insn_buf, "%s\t%%z2,%%z0", opname); | |
3430 | output_asm_insn (insn_buf, operands); | |
3431 | } | |
3432 | } | |
3433 | } | |
3434 | break; | |
3435 | default: | |
8c440872 | 3436 | gcc_unreachable (); |
366a7b27 KH |
3437 | } |
3438 | return ""; | |
3439 | } | |
40367e2d | 3440 | |
e9eba255 KH |
3441 | /* Compute the length of a logical insn. */ |
3442 | ||
40367e2d | 3443 | unsigned int |
cb713a8d | 3444 | compute_logical_op_length (enum machine_mode mode, rtx *operands) |
40367e2d | 3445 | { |
b42cff6b KH |
3446 | /* Figure out the logical op that we need to perform. */ |
3447 | enum rtx_code code = GET_CODE (operands[3]); | |
40367e2d | 3448 | /* Pretend that every byte is affected if both operands are registers. */ |
7798db98 | 3449 | const unsigned HOST_WIDE_INT intval = |
40367e2d | 3450 | (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT) |
beed8fc0 AO |
3451 | /* Always use the full instruction if the |
3452 | first operand is in memory. It is better | |
3453 | to use define_splits to generate the shorter | |
3454 | sequence where valid. */ | |
3455 | && register_operand (operands[1], VOIDmode) | |
40367e2d KH |
3456 | ? INTVAL (operands[2]) : 0x55555555); |
3457 | /* The determinant of the algorithm. If we perform an AND, 0 | |
3458 | affects a bit. Otherwise, 1 affects a bit. */ | |
7798db98 | 3459 | const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval; |
f9ac2f95 KH |
3460 | /* Break up DET into pieces. */ |
3461 | const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff; | |
3462 | const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff; | |
c5e7ce43 KH |
3463 | const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff; |
3464 | const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff; | |
f9ac2f95 KH |
3465 | const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff; |
3466 | const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff; | |
3467 | int lower_half_easy_p = 0; | |
3468 | int upper_half_easy_p = 0; | |
40367e2d KH |
3469 | /* Insn length. */ |
3470 | unsigned int length = 0; | |
3471 | ||
3472 | switch (mode) | |
3473 | { | |
3474 | case HImode: | |
3475 | /* First, see if we can finish with one insn. */ | |
3476 | if ((TARGET_H8300H || TARGET_H8300S) | |
c5e7ce43 KH |
3477 | && b0 != 0 |
3478 | && b1 != 0) | |
40367e2d | 3479 | { |
beed8fc0 AO |
3480 | length = h8300_length_from_table (operands[1], operands[2], |
3481 | &logicw_length_table); | |
40367e2d KH |
3482 | } |
3483 | else | |
3484 | { | |
3485 | /* Take care of the lower byte. */ | |
c5e7ce43 | 3486 | if (b0 != 0) |
40367e2d KH |
3487 | length += 2; |
3488 | ||
3489 | /* Take care of the upper byte. */ | |
c5e7ce43 | 3490 | if (b1 != 0) |
40367e2d KH |
3491 | length += 2; |
3492 | } | |
3493 | break; | |
3494 | case SImode: | |
f9ac2f95 KH |
3495 | if (TARGET_H8300H || TARGET_H8300S) |
3496 | { | |
3497 | /* Determine if the lower half can be taken care of in no more | |
3498 | than two bytes. */ | |
3499 | lower_half_easy_p = (b0 == 0 | |
3500 | || b1 == 0 | |
3501 | || (code != IOR && w0 == 0xffff)); | |
3502 | ||
3503 | /* Determine if the upper half can be taken care of in no more | |
3504 | than two bytes. */ | |
3505 | upper_half_easy_p = ((code != IOR && w1 == 0xffff) | |
3506 | || (code == AND && w1 == 0xff00)); | |
3507 | } | |
40367e2d | 3508 | |
f9ac2f95 KH |
3509 | /* Check if doing everything with one insn is no worse than |
3510 | using multiple insns. */ | |
40367e2d | 3511 | if ((TARGET_H8300H || TARGET_H8300S) |
f9ac2f95 | 3512 | && w0 != 0 && w1 != 0 |
472f2723 KH |
3513 | && !(lower_half_easy_p && upper_half_easy_p) |
3514 | && !(code == IOR && w1 == 0xffff | |
3515 | && (w0 & 0x8000) != 0 && lower_half_easy_p)) | |
40367e2d | 3516 | { |
beed8fc0 AO |
3517 | length = h8300_length_from_table (operands[1], operands[2], |
3518 | &logicl_length_table); | |
40367e2d KH |
3519 | } |
3520 | else | |
3521 | { | |
3522 | /* Take care of the lower and upper words individually. For | |
3523 | each word, we try different methods in the order of | |
3524 | ||
3525 | 1) the special insn (in case of AND or XOR), | |
3526 | 2) the word-wise insn, and | |
3527 | 3) The byte-wise insn. */ | |
c5e7ce43 | 3528 | if (w0 == 0xffff |
40367e2d KH |
3529 | && (TARGET_H8300 ? (code == AND) : (code != IOR))) |
3530 | { | |
3531 | length += 2; | |
3532 | } | |
3533 | else if ((TARGET_H8300H || TARGET_H8300S) | |
c5e7ce43 KH |
3534 | && (b0 != 0) |
3535 | && (b1 != 0)) | |
40367e2d KH |
3536 | { |
3537 | length += 4; | |
3538 | } | |
3539 | else | |
3540 | { | |
c5e7ce43 | 3541 | if (b0 != 0) |
40367e2d KH |
3542 | length += 2; |
3543 | ||
c5e7ce43 | 3544 | if (b1 != 0) |
40367e2d KH |
3545 | length += 2; |
3546 | } | |
3547 | ||
c5e7ce43 | 3548 | if (w1 == 0xffff |
40367e2d KH |
3549 | && (TARGET_H8300 ? (code == AND) : (code != IOR))) |
3550 | { | |
3551 | length += 2; | |
3552 | } | |
472f2723 KH |
3553 | else if ((TARGET_H8300H || TARGET_H8300S) |
3554 | && code == IOR | |
3555 | && w1 == 0xffff | |
3556 | && (w0 & 0x8000) != 0) | |
3557 | { | |
3558 | length += 2; | |
3559 | } | |
a6e8d113 KH |
3560 | else if ((TARGET_H8300H || TARGET_H8300S) |
3561 | && code == AND | |
c5e7ce43 | 3562 | && w1 == 0xff00) |
a6e8d113 KH |
3563 | { |
3564 | length += 2; | |
3565 | } | |
40367e2d KH |
3566 | else if (TARGET_H8300H || TARGET_H8300S) |
3567 | { | |
c5e7ce43 | 3568 | if (w1 != 0) |
40367e2d KH |
3569 | length += 4; |
3570 | } | |
3571 | else | |
3572 | { | |
c5e7ce43 | 3573 | if (b2 != 0) |
40367e2d KH |
3574 | length += 2; |
3575 | ||
c5e7ce43 | 3576 | if (b3 != 0) |
40367e2d KH |
3577 | length += 2; |
3578 | } | |
3579 | } | |
3580 | break; | |
3581 | default: | |
8c440872 | 3582 | gcc_unreachable (); |
40367e2d KH |
3583 | } |
3584 | return length; | |
3585 | } | |
b42cff6b | 3586 | |
e9eba255 KH |
3587 | /* Compute which flag bits are valid after a logical insn. */ |
3588 | ||
9690aa8e | 3589 | enum attr_cc |
cb713a8d | 3590 | compute_logical_op_cc (enum machine_mode mode, rtx *operands) |
b42cff6b KH |
3591 | { |
3592 | /* Figure out the logical op that we need to perform. */ | |
3593 | enum rtx_code code = GET_CODE (operands[3]); | |
3594 | /* Pretend that every byte is affected if both operands are registers. */ | |
7798db98 | 3595 | const unsigned HOST_WIDE_INT intval = |
b42cff6b | 3596 | (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT) |
beed8fc0 AO |
3597 | /* Always use the full instruction if the |
3598 | first operand is in memory. It is better | |
3599 | to use define_splits to generate the shorter | |
3600 | sequence where valid. */ | |
3601 | && register_operand (operands[1], VOIDmode) | |
b42cff6b KH |
3602 | ? INTVAL (operands[2]) : 0x55555555); |
3603 | /* The determinant of the algorithm. If we perform an AND, 0 | |
3604 | affects a bit. Otherwise, 1 affects a bit. */ | |
7798db98 | 3605 | const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval; |
f9ac2f95 KH |
3606 | /* Break up DET into pieces. */ |
3607 | const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff; | |
3608 | const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff; | |
3609 | const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff; | |
3610 | const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff; | |
3611 | int lower_half_easy_p = 0; | |
3612 | int upper_half_easy_p = 0; | |
b42cff6b KH |
3613 | /* Condition code. */ |
3614 | enum attr_cc cc = CC_CLOBBER; | |
3615 | ||
3616 | switch (mode) | |
3617 | { | |
3618 | case HImode: | |
3619 | /* First, see if we can finish with one insn. */ | |
3620 | if ((TARGET_H8300H || TARGET_H8300S) | |
c5e7ce43 KH |
3621 | && b0 != 0 |
3622 | && b1 != 0) | |
b42cff6b KH |
3623 | { |
3624 | cc = CC_SET_ZNV; | |
3625 | } | |
3626 | break; | |
3627 | case SImode: | |
f9ac2f95 KH |
3628 | if (TARGET_H8300H || TARGET_H8300S) |
3629 | { | |
3630 | /* Determine if the lower half can be taken care of in no more | |
3631 | than two bytes. */ | |
3632 | lower_half_easy_p = (b0 == 0 | |
3633 | || b1 == 0 | |
3634 | || (code != IOR && w0 == 0xffff)); | |
3635 | ||
3636 | /* Determine if the upper half can be taken care of in no more | |
3637 | than two bytes. */ | |
3638 | upper_half_easy_p = ((code != IOR && w1 == 0xffff) | |
3639 | || (code == AND && w1 == 0xff00)); | |
3640 | } | |
b42cff6b | 3641 | |
f9ac2f95 KH |
3642 | /* Check if doing everything with one insn is no worse than |
3643 | using multiple insns. */ | |
b42cff6b | 3644 | if ((TARGET_H8300H || TARGET_H8300S) |
f9ac2f95 | 3645 | && w0 != 0 && w1 != 0 |
472f2723 KH |
3646 | && !(lower_half_easy_p && upper_half_easy_p) |
3647 | && !(code == IOR && w1 == 0xffff | |
3648 | && (w0 & 0x8000) != 0 && lower_half_easy_p)) | |
b42cff6b KH |
3649 | { |
3650 | cc = CC_SET_ZNV; | |
3651 | } | |
472f2723 KH |
3652 | else |
3653 | { | |
3654 | if ((TARGET_H8300H || TARGET_H8300S) | |
3655 | && code == IOR | |
3656 | && w1 == 0xffff | |
3657 | && (w0 & 0x8000) != 0) | |
3658 | { | |
3659 | cc = CC_SET_ZNV; | |
3660 | } | |
3661 | } | |
b42cff6b KH |
3662 | break; |
3663 | default: | |
8c440872 | 3664 | gcc_unreachable (); |
b42cff6b KH |
3665 | } |
3666 | return cc; | |
3667 | } | |
366a7b27 | 3668 | \f |
8981ecd3 KH |
3669 | /* Expand a conditional branch. */ |
3670 | ||
3671 | void | |
f90b7a5a | 3672 | h8300_expand_branch (rtx operands[]) |
8981ecd3 | 3673 | { |
f90b7a5a PB |
3674 | enum rtx_code code = GET_CODE (operands[0]); |
3675 | rtx op0 = operands[1]; | |
3676 | rtx op1 = operands[2]; | |
3677 | rtx label = operands[3]; | |
8981ecd3 KH |
3678 | rtx tmp; |
3679 | ||
f90b7a5a PB |
3680 | tmp = gen_rtx_COMPARE (VOIDmode, op0, op1); |
3681 | emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp)); | |
3682 | ||
8981ecd3 KH |
3683 | tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx); |
3684 | tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, | |
3685 | gen_rtx_LABEL_REF (VOIDmode, label), | |
3686 | pc_rtx); | |
3687 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp)); | |
3688 | } | |
f90b7a5a PB |
3689 | |
3690 | ||
3691 | /* Expand a conditional store. */ | |
3692 | ||
3693 | void | |
3694 | h8300_expand_store (rtx operands[]) | |
3695 | { | |
3696 | rtx dest = operands[0]; | |
3697 | enum rtx_code code = GET_CODE (operands[1]); | |
3698 | rtx op0 = operands[2]; | |
3699 | rtx op1 = operands[3]; | |
3700 | rtx tmp; | |
3701 | ||
3702 | tmp = gen_rtx_COMPARE (VOIDmode, op0, op1); | |
3703 | emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp)); | |
3704 | ||
3705 | tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx); | |
3706 | emit_insn (gen_rtx_SET (VOIDmode, dest, tmp)); | |
3707 | } | |
8981ecd3 | 3708 | \f |
48837e29 DE |
3709 | /* Shifts. |
3710 | ||
005e3e05 KH |
3711 | We devote a fair bit of code to getting efficient shifts since we |
3712 | can only shift one bit at a time on the H8/300 and H8/300H and only | |
3db11b5c | 3713 | one or two bits at a time on the H8S. |
005e3e05 KH |
3714 | |
3715 | All shift code falls into one of the following ways of | |
3716 | implementation: | |
3717 | ||
3718 | o SHIFT_INLINE: Emit straight line code for the shift; this is used | |
3719 | when a straight line shift is about the same size or smaller than | |
3720 | a loop. | |
3721 | ||
3722 | o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask | |
3723 | off the bits we don't need. This is used when only a few of the | |
3724 | bits in the original value will survive in the shifted value. | |
3725 | ||
3726 | o SHIFT_SPECIAL: Often it's possible to move a byte or a word to | |
3727 | simulate a shift by 8, 16, or 24 bits. Once moved, a few inline | |
3728 | shifts can be added if the shift count is slightly more than 8 or | |
3729 | 16. This case also includes other oddballs that are not worth | |
f411c849 | 3730 | explaining here. |
005e3e05 | 3731 | |
3db11b5c | 3732 | o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts. |
005e3e05 | 3733 | |
5ec0b66e KH |
3734 | For each shift count, we try to use code that has no trade-off |
3735 | between code size and speed whenever possible. | |
3736 | ||
3737 | If the trade-off is unavoidable, we try to be reasonable. | |
3738 | Specifically, the fastest version is one instruction longer than | |
3739 | the shortest version, we take the fastest version. We also provide | |
3740 | the use a way to switch back to the shortest version with -Os. | |
3741 | ||
3742 | For the details of the shift algorithms for various shift counts, | |
3743 | refer to shift_alg_[qhs]i. */ | |
07aae5c2 | 3744 | |
beed8fc0 AO |
3745 | /* Classify a shift with the given mode and code. OP is the shift amount. */ |
3746 | ||
3747 | enum h8sx_shift_type | |
3748 | h8sx_classify_shift (enum machine_mode mode, enum rtx_code code, rtx op) | |
3749 | { | |
3750 | if (!TARGET_H8300SX) | |
3751 | return H8SX_SHIFT_NONE; | |
3752 | ||
3753 | switch (code) | |
3754 | { | |
3755 | case ASHIFT: | |
3756 | case LSHIFTRT: | |
3757 | /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */ | |
3758 | if (GET_CODE (op) != CONST_INT) | |
3759 | return H8SX_SHIFT_BINARY; | |
3760 | ||
3761 | /* Reject out-of-range shift amounts. */ | |
3762 | if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode)) | |
3763 | return H8SX_SHIFT_NONE; | |
3764 | ||
3765 | /* Power-of-2 shifts are effectively unary operations. */ | |
3766 | if (exact_log2 (INTVAL (op)) >= 0) | |
3767 | return H8SX_SHIFT_UNARY; | |
3768 | ||
3769 | return H8SX_SHIFT_BINARY; | |
3770 | ||
3771 | case ASHIFTRT: | |
3772 | if (op == const1_rtx || op == const2_rtx) | |
3773 | return H8SX_SHIFT_UNARY; | |
3774 | return H8SX_SHIFT_NONE; | |
3775 | ||
3776 | case ROTATE: | |
3777 | if (GET_CODE (op) == CONST_INT | |
3778 | && (INTVAL (op) == 1 | |
3779 | || INTVAL (op) == 2 | |
3780 | || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2 | |
3781 | || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1)) | |
3782 | return H8SX_SHIFT_UNARY; | |
3783 | return H8SX_SHIFT_NONE; | |
3784 | ||
3785 | default: | |
3786 | return H8SX_SHIFT_NONE; | |
3787 | } | |
3788 | } | |
3789 | ||
beed8fc0 AO |
3790 | /* Return the asm template for a single h8sx shift instruction. |
3791 | OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2] | |
3792 | is the source and OPERANDS[3] is the shift. SUFFIX is the | |
88cb339e | 3793 | size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand |
beed8fc0 AO |
3794 | prefix for the destination operand. */ |
3795 | ||
3796 | const char * | |
3797 | output_h8sx_shift (rtx *operands, int suffix, int optype) | |
3798 | { | |
3799 | static char buffer[16]; | |
3800 | const char *stem; | |
3801 | ||
3802 | switch (GET_CODE (operands[3])) | |
3803 | { | |
3804 | case ASHIFT: | |
3805 | stem = "shll"; | |
3806 | break; | |
3807 | ||
3808 | case ASHIFTRT: | |
3809 | stem = "shar"; | |
3810 | break; | |
3811 | ||
3812 | case LSHIFTRT: | |
3813 | stem = "shlr"; | |
3814 | break; | |
3815 | ||
3816 | case ROTATE: | |
3817 | stem = "rotl"; | |
3818 | if (INTVAL (operands[2]) > 2) | |
3819 | { | |
3820 | /* This is really a right rotate. */ | |
3821 | operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0])) | |
3822 | - INTVAL (operands[2])); | |
3823 | stem = "rotr"; | |
3824 | } | |
3825 | break; | |
3826 | ||
3827 | default: | |
8c440872 | 3828 | gcc_unreachable (); |
beed8fc0 AO |
3829 | } |
3830 | if (operands[2] == const1_rtx) | |
3831 | sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype); | |
3832 | else | |
3833 | sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype); | |
3834 | return buffer; | |
3835 | } | |
48837e29 | 3836 | |
317d21e9 | 3837 | /* Emit code to do shifts. */ |
48837e29 | 3838 | |
beed8fc0 | 3839 | bool |
9690aa8e | 3840 | expand_a_shift (enum machine_mode mode, enum rtx_code code, rtx operands[]) |
07aae5c2 | 3841 | { |
beed8fc0 AO |
3842 | switch (h8sx_classify_shift (mode, code, operands[2])) |
3843 | { | |
3844 | case H8SX_SHIFT_BINARY: | |
3845 | operands[1] = force_reg (mode, operands[1]); | |
3846 | return false; | |
3847 | ||
3848 | case H8SX_SHIFT_UNARY: | |
3849 | return false; | |
3850 | ||
3851 | case H8SX_SHIFT_NONE: | |
3852 | break; | |
3853 | } | |
3854 | ||
bc9b880c | 3855 | emit_move_insn (copy_rtx (operands[0]), operands[1]); |
07aae5c2 | 3856 | |
07e4d94e KH |
3857 | /* Need a loop to get all the bits we want - we generate the |
3858 | code at emit time, but need to allocate a scratch reg now. */ | |
48837e29 | 3859 | |
c5c76735 JL |
3860 | emit_insn (gen_rtx_PARALLEL |
3861 | (VOIDmode, | |
48837e29 | 3862 | gen_rtvec (2, |
bc9b880c | 3863 | gen_rtx_SET (VOIDmode, copy_rtx (operands[0]), |
0f4c242b | 3864 | gen_rtx_fmt_ee (code, mode, |
bc9b880c | 3865 | copy_rtx (operands[0]), operands[2])), |
c5c76735 JL |
3866 | gen_rtx_CLOBBER (VOIDmode, |
3867 | gen_rtx_SCRATCH (QImode))))); | |
beed8fc0 | 3868 | return true; |
48837e29 DE |
3869 | } |
3870 | ||
48837e29 DE |
3871 | /* Symbols of the various modes which can be used as indices. */ |
3872 | ||
3873 | enum shift_mode | |
1a63219b KH |
3874 | { |
3875 | QIshift, HIshift, SIshift | |
3876 | }; | |
48837e29 | 3877 | |
269c14e1 DE |
3878 | /* For single bit shift insns, record assembler and what bits of the |
3879 | condition code are valid afterwards (represented as various CC_FOO | |
3880 | bits, 0 means CC isn't left in a usable state). */ | |
48837e29 DE |
3881 | |
3882 | struct shift_insn | |
3883 | { | |
8b60264b | 3884 | const char *const assembler; |
9690aa8e | 3885 | const enum attr_cc cc_valid; |
48837e29 DE |
3886 | }; |
3887 | ||
3888 | /* Assembler instruction shift table. | |
3889 | ||
3890 | These tables are used to look up the basic shifts. | |
07e4d94e | 3891 | They are indexed by cpu, shift_type, and mode. */ |
07aae5c2 | 3892 | |
48837e29 DE |
3893 | static const struct shift_insn shift_one[2][3][3] = |
3894 | { | |
3895 | /* H8/300 */ | |
3896 | { | |
3897 | /* SHIFT_ASHIFT */ | |
3898 | { | |
45ca2106 KH |
3899 | { "shll\t%X0", CC_SET_ZNV }, |
3900 | { "add.w\t%T0,%T0", CC_SET_ZN }, | |
3901 | { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER } | |
48837e29 DE |
3902 | }, |
3903 | /* SHIFT_LSHIFTRT */ | |
3904 | { | |
45ca2106 KH |
3905 | { "shlr\t%X0", CC_SET_ZNV }, |
3906 | { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER }, | |
3907 | { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER } | |
48837e29 DE |
3908 | }, |
3909 | /* SHIFT_ASHIFTRT */ | |
3910 | { | |
45ca2106 KH |
3911 | { "shar\t%X0", CC_SET_ZNV }, |
3912 | { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER }, | |
3913 | { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER } | |
48837e29 DE |
3914 | } |
3915 | }, | |
3916 | /* H8/300H */ | |
3917 | { | |
3918 | /* SHIFT_ASHIFT */ | |
3919 | { | |
45ca2106 KH |
3920 | { "shll.b\t%X0", CC_SET_ZNV }, |
3921 | { "shll.w\t%T0", CC_SET_ZNV }, | |
3922 | { "shll.l\t%S0", CC_SET_ZNV } | |
48837e29 DE |
3923 | }, |
3924 | /* SHIFT_LSHIFTRT */ | |
3925 | { | |
45ca2106 KH |
3926 | { "shlr.b\t%X0", CC_SET_ZNV }, |
3927 | { "shlr.w\t%T0", CC_SET_ZNV }, | |
3928 | { "shlr.l\t%S0", CC_SET_ZNV } | |
48837e29 DE |
3929 | }, |
3930 | /* SHIFT_ASHIFTRT */ | |
3931 | { | |
45ca2106 KH |
3932 | { "shar.b\t%X0", CC_SET_ZNV }, |
3933 | { "shar.w\t%T0", CC_SET_ZNV }, | |
3934 | { "shar.l\t%S0", CC_SET_ZNV } | |
48837e29 DE |
3935 | } |
3936 | } | |
3937 | }; | |
07aae5c2 | 3938 | |
51c0c1d7 JL |
3939 | static const struct shift_insn shift_two[3][3] = |
3940 | { | |
3941 | /* SHIFT_ASHIFT */ | |
3942 | { | |
45ca2106 KH |
3943 | { "shll.b\t#2,%X0", CC_SET_ZNV }, |
3944 | { "shll.w\t#2,%T0", CC_SET_ZNV }, | |
3945 | { "shll.l\t#2,%S0", CC_SET_ZNV } | |
51c0c1d7 JL |
3946 | }, |
3947 | /* SHIFT_LSHIFTRT */ | |
3948 | { | |
45ca2106 KH |
3949 | { "shlr.b\t#2,%X0", CC_SET_ZNV }, |
3950 | { "shlr.w\t#2,%T0", CC_SET_ZNV }, | |
3951 | { "shlr.l\t#2,%S0", CC_SET_ZNV } | |
51c0c1d7 JL |
3952 | }, |
3953 | /* SHIFT_ASHIFTRT */ | |
3954 | { | |
45ca2106 KH |
3955 | { "shar.b\t#2,%X0", CC_SET_ZNV }, |
3956 | { "shar.w\t#2,%T0", CC_SET_ZNV }, | |
3957 | { "shar.l\t#2,%S0", CC_SET_ZNV } | |
51c0c1d7 JL |
3958 | } |
3959 | }; | |
3960 | ||
48837e29 DE |
3961 | /* Rotates are organized by which shift they'll be used in implementing. |
3962 | There's no need to record whether the cc is valid afterwards because | |
3963 | it is the AND insn that will decide this. */ | |
07aae5c2 | 3964 | |
48837e29 DE |
3965 | static const char *const rotate_one[2][3][3] = |
3966 | { | |
3967 | /* H8/300 */ | |
3968 | { | |
3969 | /* SHIFT_ASHIFT */ | |
3970 | { | |
51c0c1d7 JL |
3971 | "rotr\t%X0", |
3972 | "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0", | |
48837e29 DE |
3973 | 0 |
3974 | }, | |
3975 | /* SHIFT_LSHIFTRT */ | |
3976 | { | |
51c0c1d7 JL |
3977 | "rotl\t%X0", |
3978 | "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0", | |
48837e29 DE |
3979 | 0 |
3980 | }, | |
3981 | /* SHIFT_ASHIFTRT */ | |
3982 | { | |
51c0c1d7 JL |
3983 | "rotl\t%X0", |
3984 | "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0", | |
48837e29 | 3985 | 0 |
07aae5c2 | 3986 | } |
48837e29 DE |
3987 | }, |
3988 | /* H8/300H */ | |
3989 | { | |
3990 | /* SHIFT_ASHIFT */ | |
3991 | { | |
51c0c1d7 JL |
3992 | "rotr.b\t%X0", |
3993 | "rotr.w\t%T0", | |
3994 | "rotr.l\t%S0" | |
48837e29 DE |
3995 | }, |
3996 | /* SHIFT_LSHIFTRT */ | |
07aae5c2 | 3997 | { |
51c0c1d7 JL |
3998 | "rotl.b\t%X0", |
3999 | "rotl.w\t%T0", | |
4000 | "rotl.l\t%S0" | |
48837e29 DE |
4001 | }, |
4002 | /* SHIFT_ASHIFTRT */ | |
4003 | { | |
51c0c1d7 JL |
4004 | "rotl.b\t%X0", |
4005 | "rotl.w\t%T0", | |
4006 | "rotl.l\t%S0" | |
48837e29 DE |
4007 | } |
4008 | } | |
4009 | }; | |
4010 | ||
51c0c1d7 JL |
4011 | static const char *const rotate_two[3][3] = |
4012 | { | |
4013 | /* SHIFT_ASHIFT */ | |
4014 | { | |
4015 | "rotr.b\t#2,%X0", | |
4016 | "rotr.w\t#2,%T0", | |
4017 | "rotr.l\t#2,%S0" | |
4018 | }, | |
4019 | /* SHIFT_LSHIFTRT */ | |
4020 | { | |
4021 | "rotl.b\t#2,%X0", | |
4022 | "rotl.w\t#2,%T0", | |
4023 | "rotl.l\t#2,%S0" | |
4024 | }, | |
4025 | /* SHIFT_ASHIFTRT */ | |
4026 | { | |
4027 | "rotl.b\t#2,%X0", | |
4028 | "rotl.w\t#2,%T0", | |
4029 | "rotl.l\t#2,%S0" | |
4030 | } | |
4031 | }; | |
4032 | ||
35fb3d1f KH |
4033 | struct shift_info { |
4034 | /* Shift algorithm. */ | |
4035 | enum shift_alg alg; | |
4036 | ||
4037 | /* The number of bits to be shifted by shift1 and shift2. Valid | |
4038 | when ALG is SHIFT_SPECIAL. */ | |
4039 | unsigned int remainder; | |
4040 | ||
4041 | /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */ | |
4042 | const char *special; | |
4043 | ||
4044 | /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE | |
9cd10576 | 4045 | or SHIFT_SPECIAL, and REMAINDER is nonzero. */ |
35fb3d1f KH |
4046 | const char *shift1; |
4047 | ||
4048 | /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE | |
9cd10576 | 4049 | or SHIFT_SPECIAL, and REMAINDER is nonzero. */ |
35fb3d1f KH |
4050 | const char *shift2; |
4051 | ||
45ca2106 | 4052 | /* CC status for SHIFT_INLINE. */ |
9690aa8e | 4053 | enum attr_cc cc_inline; |
45ca2106 KH |
4054 | |
4055 | /* CC status for SHIFT_SPECIAL. */ | |
9690aa8e | 4056 | enum attr_cc cc_special; |
35fb3d1f KH |
4057 | }; |
4058 | ||
cb713a8d KH |
4059 | static void get_shift_alg (enum shift_type, |
4060 | enum shift_mode, unsigned int, | |
4061 | struct shift_info *); | |
441d04c6 | 4062 | |
c009a745 KH |
4063 | /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the |
4064 | best algorithm for doing the shift. The assembler code is stored | |
5ec0b66e KH |
4065 | in the pointers in INFO. We achieve the maximum efficiency in most |
4066 | cases when !TARGET_H8300. In case of TARGET_H8300, shifts in | |
4067 | SImode in particular have a lot of room to optimize. | |
4068 | ||
4069 | We first determine the strategy of the shift algorithm by a table | |
4070 | lookup. If that tells us to use a hand crafted assembly code, we | |
4071 | go into the big switch statement to find what that is. Otherwise, | |
4072 | we resort to a generic way, such as inlining. In either case, the | |
4073 | result is returned through INFO. */ | |
48837e29 | 4074 | |
cb33eb17 | 4075 | static void |
cb713a8d KH |
4076 | get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode, |
4077 | unsigned int count, struct shift_info *info) | |
48837e29 | 4078 | { |
b9b575e6 | 4079 | enum h8_cpu cpu; |
769828ab KH |
4080 | |
4081 | /* Find the target CPU. */ | |
4082 | if (TARGET_H8300) | |
b9b575e6 | 4083 | cpu = H8_300; |
769828ab | 4084 | else if (TARGET_H8300H) |
b9b575e6 | 4085 | cpu = H8_300H; |
769828ab | 4086 | else |
b9b575e6 | 4087 | cpu = H8_S; |
769828ab | 4088 | |
96eaf358 | 4089 | /* Find the shift algorithm. */ |
b9b575e6 | 4090 | info->alg = SHIFT_LOOP; |
48837e29 DE |
4091 | switch (shift_mode) |
4092 | { | |
4093 | case QIshift: | |
b9b575e6 | 4094 | if (count < GET_MODE_BITSIZE (QImode)) |
96eaf358 KH |
4095 | info->alg = shift_alg_qi[cpu][shift_type][count]; |
4096 | break; | |
769828ab | 4097 | |
96eaf358 | 4098 | case HIshift: |
b9b575e6 | 4099 | if (count < GET_MODE_BITSIZE (HImode)) |
96eaf358 KH |
4100 | info->alg = shift_alg_hi[cpu][shift_type][count]; |
4101 | break; | |
4102 | ||
4103 | case SIshift: | |
b9b575e6 | 4104 | if (count < GET_MODE_BITSIZE (SImode)) |
96eaf358 KH |
4105 | info->alg = shift_alg_si[cpu][shift_type][count]; |
4106 | break; | |
4107 | ||
4108 | default: | |
8c440872 | 4109 | gcc_unreachable (); |
96eaf358 KH |
4110 | } |
4111 | ||
4112 | /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */ | |
4113 | switch (info->alg) | |
4114 | { | |
4115 | case SHIFT_INLINE: | |
4116 | info->remainder = count; | |
4117 | /* Fall through. */ | |
4118 | ||
4119 | case SHIFT_LOOP: | |
4120 | /* It is up to the caller to know that looping clobbers cc. */ | |
4121 | info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler; | |
4122 | info->shift2 = shift_two[shift_type][shift_mode].assembler; | |
45ca2106 | 4123 | info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid; |
96eaf358 KH |
4124 | goto end; |
4125 | ||
4126 | case SHIFT_ROT_AND: | |
4127 | info->shift1 = rotate_one[cpu_type][shift_type][shift_mode]; | |
4128 | info->shift2 = rotate_two[shift_type][shift_mode]; | |
45ca2106 | 4129 | info->cc_inline = CC_CLOBBER; |
96eaf358 KH |
4130 | goto end; |
4131 | ||
4132 | case SHIFT_SPECIAL: | |
4133 | /* REMAINDER is 0 for most cases, so initialize it to 0. */ | |
4134 | info->remainder = 0; | |
4135 | info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler; | |
4136 | info->shift2 = shift_two[shift_type][shift_mode].assembler; | |
45ca2106 KH |
4137 | info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid; |
4138 | info->cc_special = CC_CLOBBER; | |
96eaf358 KH |
4139 | break; |
4140 | } | |
51c0c1d7 | 4141 | |
96eaf358 KH |
4142 | /* Here we only deal with SHIFT_SPECIAL. */ |
4143 | switch (shift_mode) | |
4144 | { | |
4145 | case QIshift: | |
769828ab KH |
4146 | /* For ASHIFTRT by 7 bits, the sign bit is simply replicated |
4147 | through the entire value. */ | |
8c440872 NS |
4148 | gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7); |
4149 | info->special = "shll\t%X0\n\tsubx\t%X0,%X0"; | |
4150 | goto end; | |
769828ab KH |
4151 | |
4152 | case HIshift: | |
769828ab | 4153 | if (count == 7) |
51c0c1d7 | 4154 | { |
a77b1dbc | 4155 | switch (shift_type) |
51c0c1d7 | 4156 | { |
a77b1dbc KH |
4157 | case SHIFT_ASHIFT: |
4158 | if (TARGET_H8300) | |
4159 | info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0"; | |
4160 | else | |
4161 | info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0"; | |
692b7eb3 | 4162 | goto end; |
a77b1dbc KH |
4163 | case SHIFT_LSHIFTRT: |
4164 | if (TARGET_H8300) | |
4165 | info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0"; | |
4166 | else | |
4167 | info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0"; | |
692b7eb3 | 4168 | goto end; |
a77b1dbc | 4169 | case SHIFT_ASHIFTRT: |
35fb3d1f | 4170 | info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0"; |
692b7eb3 | 4171 | goto end; |
48837e29 | 4172 | } |
07aae5c2 | 4173 | } |
b30686ec | 4174 | else if ((8 <= count && count <= 13) |
a38b3eea | 4175 | || (TARGET_H8300S && count == 14)) |
07aae5c2 | 4176 | { |
a7812c0b KH |
4177 | info->remainder = count - 8; |
4178 | ||
51c0c1d7 | 4179 | switch (shift_type) |
48837e29 | 4180 | { |
51c0c1d7 | 4181 | case SHIFT_ASHIFT: |
35fb3d1f | 4182 | info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0"; |
692b7eb3 | 4183 | goto end; |
51c0c1d7 | 4184 | case SHIFT_LSHIFTRT: |
a7612343 KH |
4185 | if (TARGET_H8300) |
4186 | { | |
4187 | info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0"; | |
4188 | info->shift1 = "shlr.b\t%s0"; | |
45ca2106 | 4189 | info->cc_inline = CC_SET_ZNV; |
a7612343 KH |
4190 | } |
4191 | else | |
4192 | { | |
4193 | info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0"; | |
45ca2106 | 4194 | info->cc_special = CC_SET_ZNV; |
a7612343 | 4195 | } |
692b7eb3 | 4196 | goto end; |
51c0c1d7 JL |
4197 | case SHIFT_ASHIFTRT: |
4198 | if (TARGET_H8300) | |
a7612343 KH |
4199 | { |
4200 | info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0"; | |
4201 | info->shift1 = "shar.b\t%s0"; | |
a7612343 | 4202 | } |
51c0c1d7 | 4203 | else |
a7612343 KH |
4204 | { |
4205 | info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0"; | |
45ca2106 | 4206 | info->cc_special = CC_SET_ZNV; |
a7612343 | 4207 | } |
692b7eb3 | 4208 | goto end; |
51c0c1d7 JL |
4209 | } |
4210 | } | |
5e98fba2 DD |
4211 | else if (count == 14) |
4212 | { | |
4213 | switch (shift_type) | |
4214 | { | |
4215 | case SHIFT_ASHIFT: | |
4216 | if (TARGET_H8300) | |
4217 | info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0"; | |
4218 | goto end; | |
4219 | case SHIFT_LSHIFTRT: | |
4220 | if (TARGET_H8300) | |
4221 | info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0"; | |
4222 | goto end; | |
4223 | case SHIFT_ASHIFTRT: | |
4224 | if (TARGET_H8300) | |
4225 | info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0"; | |
4226 | else if (TARGET_H8300H) | |
45ca2106 KH |
4227 | { |
4228 | info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0"; | |
4229 | info->cc_special = CC_SET_ZNV; | |
4230 | } | |
5e98fba2 | 4231 | else /* TARGET_H8300S */ |
8c440872 | 4232 | gcc_unreachable (); |
5e98fba2 DD |
4233 | goto end; |
4234 | } | |
4235 | } | |
1e41e866 | 4236 | else if (count == 15) |
51c0c1d7 | 4237 | { |
1e41e866 KH |
4238 | switch (shift_type) |
4239 | { | |
4240 | case SHIFT_ASHIFT: | |
4241 | info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0"; | |
4242 | goto end; | |
4243 | case SHIFT_LSHIFTRT: | |
4244 | info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0"; | |
4245 | goto end; | |
4246 | case SHIFT_ASHIFTRT: | |
4247 | info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0"; | |
4248 | goto end; | |
4249 | } | |
07aae5c2 | 4250 | } |
8c440872 | 4251 | gcc_unreachable (); |
51c0c1d7 | 4252 | |
48837e29 | 4253 | case SIshift: |
1e41e866 | 4254 | if (TARGET_H8300 && 8 <= count && count <= 9) |
48837e29 | 4255 | { |
1e41e866 KH |
4256 | info->remainder = count - 8; |
4257 | ||
51c0c1d7 | 4258 | switch (shift_type) |
48837e29 | 4259 | { |
51c0c1d7 | 4260 | case SHIFT_ASHIFT: |
35fb3d1f | 4261 | info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0"; |
692b7eb3 | 4262 | goto end; |
51c0c1d7 | 4263 | case SHIFT_LSHIFTRT: |
35fb3d1f | 4264 | info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0"; |
1e41e866 | 4265 | info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0"; |
692b7eb3 | 4266 | goto end; |
51c0c1d7 | 4267 | case SHIFT_ASHIFTRT: |
35fb3d1f | 4268 | info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0"; |
692b7eb3 | 4269 | goto end; |
48837e29 | 4270 | } |
48837e29 | 4271 | } |
e6bcfef9 JS |
4272 | else if (count == 8 && !TARGET_H8300) |
4273 | { | |
4274 | switch (shift_type) | |
4275 | { | |
4276 | case SHIFT_ASHIFT: | |
35fb3d1f | 4277 | info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0"; |
692b7eb3 | 4278 | goto end; |
e6bcfef9 | 4279 | case SHIFT_LSHIFTRT: |
35fb3d1f | 4280 | info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0"; |
692b7eb3 | 4281 | goto end; |
e6bcfef9 | 4282 | case SHIFT_ASHIFTRT: |
35fb3d1f | 4283 | info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0"; |
692b7eb3 | 4284 | goto end; |
e6bcfef9 JS |
4285 | } |
4286 | } | |
1e41e866 KH |
4287 | else if (count == 15 && TARGET_H8300) |
4288 | { | |
4289 | switch (shift_type) | |
4290 | { | |
4291 | case SHIFT_ASHIFT: | |
8c440872 | 4292 | gcc_unreachable (); |
1e41e866 | 4293 | case SHIFT_LSHIFTRT: |
a35abc3c | 4294 | info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0"; |
1e41e866 KH |
4295 | goto end; |
4296 | case SHIFT_ASHIFTRT: | |
a35abc3c | 4297 | info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0"; |
1e41e866 KH |
4298 | goto end; |
4299 | } | |
4300 | } | |
dd69e230 KH |
4301 | else if (count == 15 && !TARGET_H8300) |
4302 | { | |
4303 | switch (shift_type) | |
4304 | { | |
4305 | case SHIFT_ASHIFT: | |
4306 | info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0"; | |
45ca2106 | 4307 | info->cc_special = CC_SET_ZNV; |
dd69e230 KH |
4308 | goto end; |
4309 | case SHIFT_LSHIFTRT: | |
18cf8dda | 4310 | info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0"; |
45ca2106 | 4311 | info->cc_special = CC_SET_ZNV; |
dd69e230 | 4312 | goto end; |
aefc5826 | 4313 | case SHIFT_ASHIFTRT: |
8c440872 | 4314 | gcc_unreachable (); |
dd69e230 KH |
4315 | } |
4316 | } | |
1e41e866 | 4317 | else if ((TARGET_H8300 && 16 <= count && count <= 20) |
a7812c0b | 4318 | || (TARGET_H8300H && 16 <= count && count <= 19) |
e0f19bd0 | 4319 | || (TARGET_H8300S && 16 <= count && count <= 21)) |
48837e29 | 4320 | { |
a7812c0b KH |
4321 | info->remainder = count - 16; |
4322 | ||
48837e29 DE |
4323 | switch (shift_type) |
4324 | { | |
4325 | case SHIFT_ASHIFT: | |
35fb3d1f | 4326 | info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0"; |
1e41e866 | 4327 | if (TARGET_H8300) |
b30686ec | 4328 | info->shift1 = "add.w\t%e0,%e0"; |
692b7eb3 | 4329 | goto end; |
51c0c1d7 | 4330 | case SHIFT_LSHIFTRT: |
1e41e866 KH |
4331 | if (TARGET_H8300) |
4332 | { | |
a7612343 KH |
4333 | info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0"; |
4334 | info->shift1 = "shlr\t%x0\n\trotxr\t%w0"; | |
1e41e866 KH |
4335 | } |
4336 | else | |
4337 | { | |
a7612343 | 4338 | info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0"; |
45ca2106 | 4339 | info->cc_special = CC_SET_ZNV; |
1e41e866 | 4340 | } |
692b7eb3 | 4341 | goto end; |
51c0c1d7 JL |
4342 | case SHIFT_ASHIFTRT: |
4343 | if (TARGET_H8300) | |
1e41e866 KH |
4344 | { |
4345 | info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0"; | |
4346 | info->shift1 = "shar\t%x0\n\trotxr\t%w0"; | |
4347 | } | |
51c0c1d7 | 4348 | else |
1e41e866 KH |
4349 | { |
4350 | info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0"; | |
45ca2106 | 4351 | info->cc_special = CC_SET_ZNV; |
1e41e866 | 4352 | } |
692b7eb3 | 4353 | goto end; |
51c0c1d7 JL |
4354 | } |
4355 | } | |
1e41e866 | 4356 | else if (TARGET_H8300 && 24 <= count && count <= 28) |
f9477efd KH |
4357 | { |
4358 | info->remainder = count - 24; | |
f0b6f9a6 | 4359 | |
f9477efd KH |
4360 | switch (shift_type) |
4361 | { | |
4362 | case SHIFT_ASHIFT: | |
4363 | info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0"; | |
4364 | info->shift1 = "shll.b\t%z0"; | |
45ca2106 | 4365 | info->cc_inline = CC_SET_ZNV; |
f9477efd KH |
4366 | goto end; |
4367 | case SHIFT_LSHIFTRT: | |
4368 | info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0"; | |
4369 | info->shift1 = "shlr.b\t%w0"; | |
45ca2106 | 4370 | info->cc_inline = CC_SET_ZNV; |
f9477efd KH |
4371 | goto end; |
4372 | case SHIFT_ASHIFTRT: | |
4373 | info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0"; | |
4374 | info->shift1 = "shar.b\t%w0"; | |
45ca2106 | 4375 | info->cc_inline = CC_SET_ZNV; |
7f473594 KH |
4376 | goto end; |
4377 | } | |
4378 | } | |
4a4ae922 KH |
4379 | else if ((TARGET_H8300H && count == 24) |
4380 | || (TARGET_H8300S && 24 <= count && count <= 25)) | |
e6bcfef9 | 4381 | { |
4a4ae922 KH |
4382 | info->remainder = count - 24; |
4383 | ||
e6bcfef9 JS |
4384 | switch (shift_type) |
4385 | { | |
4386 | case SHIFT_ASHIFT: | |
35fb3d1f | 4387 | info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0"; |
692b7eb3 | 4388 | goto end; |
e6bcfef9 | 4389 | case SHIFT_LSHIFTRT: |
35fb3d1f | 4390 | info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0"; |
45ca2106 | 4391 | info->cc_special = CC_SET_ZNV; |
692b7eb3 | 4392 | goto end; |
e6bcfef9 | 4393 | case SHIFT_ASHIFTRT: |
35fb3d1f | 4394 | info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0"; |
45ca2106 | 4395 | info->cc_special = CC_SET_ZNV; |
692b7eb3 | 4396 | goto end; |
e6bcfef9 JS |
4397 | } |
4398 | } | |
1e5bdc40 KH |
4399 | else if (!TARGET_H8300 && count == 28) |
4400 | { | |
4401 | switch (shift_type) | |
4402 | { | |
4403 | case SHIFT_ASHIFT: | |
4404 | if (TARGET_H8300H) | |
4405 | info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; | |
4406 | else | |
4407 | info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0"; | |
1e5bdc40 KH |
4408 | goto end; |
4409 | case SHIFT_LSHIFTRT: | |
4410 | if (TARGET_H8300H) | |
45ca2106 KH |
4411 | { |
4412 | info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; | |
4413 | info->cc_special = CC_SET_ZNV; | |
4414 | } | |
1e5bdc40 | 4415 | else |
a7612343 | 4416 | info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0"; |
1e5bdc40 KH |
4417 | goto end; |
4418 | case SHIFT_ASHIFTRT: | |
8c440872 | 4419 | gcc_unreachable (); |
1e5bdc40 KH |
4420 | } |
4421 | } | |
4422 | else if (!TARGET_H8300 && count == 29) | |
4423 | { | |
4424 | switch (shift_type) | |
4425 | { | |
4426 | case SHIFT_ASHIFT: | |
4427 | if (TARGET_H8300H) | |
4428 | info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; | |
4429 | else | |
4430 | info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; | |
1e5bdc40 KH |
4431 | goto end; |
4432 | case SHIFT_LSHIFTRT: | |
4433 | if (TARGET_H8300H) | |
45ca2106 KH |
4434 | { |
4435 | info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; | |
4436 | info->cc_special = CC_SET_ZNV; | |
4437 | } | |
1e5bdc40 | 4438 | else |
45ca2106 KH |
4439 | { |
4440 | info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; | |
4441 | info->cc_special = CC_SET_ZNV; | |
4442 | } | |
1e5bdc40 KH |
4443 | goto end; |
4444 | case SHIFT_ASHIFTRT: | |
8c440872 | 4445 | gcc_unreachable (); |
1e5bdc40 KH |
4446 | } |
4447 | } | |
4448 | else if (!TARGET_H8300 && count == 30) | |
4449 | { | |
4450 | switch (shift_type) | |
4451 | { | |
4452 | case SHIFT_ASHIFT: | |
4453 | if (TARGET_H8300H) | |
4454 | info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; | |
4455 | else | |
4456 | info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0"; | |
1e5bdc40 KH |
4457 | goto end; |
4458 | case SHIFT_LSHIFTRT: | |
4459 | if (TARGET_H8300H) | |
a7612343 | 4460 | info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; |
1e5bdc40 | 4461 | else |
a7612343 | 4462 | info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0"; |
1e5bdc40 KH |
4463 | goto end; |
4464 | case SHIFT_ASHIFTRT: | |
8c440872 | 4465 | gcc_unreachable (); |
1e5bdc40 KH |
4466 | } |
4467 | } | |
48837e29 DE |
4468 | else if (count == 31) |
4469 | { | |
dd69e230 | 4470 | if (TARGET_H8300) |
48837e29 | 4471 | { |
dd69e230 KH |
4472 | switch (shift_type) |
4473 | { | |
4474 | case SHIFT_ASHIFT: | |
4475 | info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0"; | |
4476 | goto end; | |
4477 | case SHIFT_LSHIFTRT: | |
4478 | info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0"; | |
4479 | goto end; | |
4480 | case SHIFT_ASHIFTRT: | |
4481 | info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0"; | |
4482 | goto end; | |
4483 | } | |
48837e29 DE |
4484 | } |
4485 | else | |
4486 | { | |
dd69e230 | 4487 | switch (shift_type) |
48837e29 | 4488 | { |
dd69e230 KH |
4489 | case SHIFT_ASHIFT: |
4490 | info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0"; | |
45ca2106 | 4491 | info->cc_special = CC_SET_ZNV; |
dd69e230 KH |
4492 | goto end; |
4493 | case SHIFT_LSHIFTRT: | |
4494 | info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0"; | |
45ca2106 | 4495 | info->cc_special = CC_SET_ZNV; |
dd69e230 KH |
4496 | goto end; |
4497 | case SHIFT_ASHIFTRT: | |
a7612343 | 4498 | info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0"; |
45ca2106 | 4499 | info->cc_special = CC_SET_ZNV; |
692b7eb3 | 4500 | goto end; |
48837e29 | 4501 | } |
48837e29 DE |
4502 | } |
4503 | } | |
8c440872 | 4504 | gcc_unreachable (); |
51c0c1d7 | 4505 | |
48837e29 | 4506 | default: |
8c440872 | 4507 | gcc_unreachable (); |
07aae5c2 | 4508 | } |
48837e29 | 4509 | |
cb33eb17 KH |
4510 | end: |
4511 | if (!TARGET_H8300S) | |
4512 | info->shift2 = NULL; | |
07aae5c2 SC |
4513 | } |
4514 | ||
be1e06df KH |
4515 | /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be |
4516 | needed for some shift with COUNT and MODE. Return 0 otherwise. */ | |
4517 | ||
4518 | int | |
cb713a8d | 4519 | h8300_shift_needs_scratch_p (int count, enum machine_mode mode) |
be1e06df | 4520 | { |
b9b575e6 | 4521 | enum h8_cpu cpu; |
be1e06df KH |
4522 | int a, lr, ar; |
4523 | ||
4524 | if (GET_MODE_BITSIZE (mode) <= count) | |
4525 | return 1; | |
4526 | ||
4527 | /* Find out the target CPU. */ | |
4528 | if (TARGET_H8300) | |
b9b575e6 | 4529 | cpu = H8_300; |
be1e06df | 4530 | else if (TARGET_H8300H) |
b9b575e6 | 4531 | cpu = H8_300H; |
be1e06df | 4532 | else |
b9b575e6 | 4533 | cpu = H8_S; |
be1e06df KH |
4534 | |
4535 | /* Find the shift algorithm. */ | |
4536 | switch (mode) | |
4537 | { | |
4538 | case QImode: | |
4539 | a = shift_alg_qi[cpu][SHIFT_ASHIFT][count]; | |
4540 | lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count]; | |
4541 | ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count]; | |
4542 | break; | |
4543 | ||
4544 | case HImode: | |
4545 | a = shift_alg_hi[cpu][SHIFT_ASHIFT][count]; | |
4546 | lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count]; | |
4547 | ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count]; | |
4548 | break; | |
4549 | ||
4550 | case SImode: | |
4551 | a = shift_alg_si[cpu][SHIFT_ASHIFT][count]; | |
4552 | lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count]; | |
4553 | ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count]; | |
4554 | break; | |
4555 | ||
4556 | default: | |
8c440872 | 4557 | gcc_unreachable (); |
be1e06df KH |
4558 | } |
4559 | ||
aa2fb4dd | 4560 | /* On H8/300H, count == 8 uses a scratch register. */ |
be1e06df | 4561 | return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP |
75a3503b | 4562 | || (TARGET_H8300H && mode == SImode && count == 8)); |
be1e06df KH |
4563 | } |
4564 | ||
e9eba255 | 4565 | /* Output the assembler code for doing shifts. */ |
48837e29 | 4566 | |
441d04c6 | 4567 | const char * |
cb713a8d | 4568 | output_a_shift (rtx *operands) |
07aae5c2 | 4569 | { |
48837e29 | 4570 | static int loopend_lab; |
48837e29 DE |
4571 | rtx shift = operands[3]; |
4572 | enum machine_mode mode = GET_MODE (shift); | |
4573 | enum rtx_code code = GET_CODE (shift); | |
4574 | enum shift_type shift_type; | |
4575 | enum shift_mode shift_mode; | |
35fb3d1f | 4576 | struct shift_info info; |
8c440872 | 4577 | int n; |
48837e29 DE |
4578 | |
4579 | loopend_lab++; | |
4580 | ||
4581 | switch (mode) | |
4582 | { | |
4583 | case QImode: | |
4584 | shift_mode = QIshift; | |
4585 | break; | |
4586 | case HImode: | |
4587 | shift_mode = HIshift; | |
4588 | break; | |
4589 | case SImode: | |
4590 | shift_mode = SIshift; | |
4591 | break; | |
4592 | default: | |
8c440872 | 4593 | gcc_unreachable (); |
48837e29 | 4594 | } |
07aae5c2 | 4595 | |
48837e29 | 4596 | switch (code) |
07aae5c2 | 4597 | { |
48837e29 DE |
4598 | case ASHIFTRT: |
4599 | shift_type = SHIFT_ASHIFTRT; | |
4600 | break; | |
4601 | case LSHIFTRT: | |
4602 | shift_type = SHIFT_LSHIFTRT; | |
4603 | break; | |
4604 | case ASHIFT: | |
4605 | shift_type = SHIFT_ASHIFT; | |
4606 | break; | |
4607 | default: | |
8c440872 | 4608 | gcc_unreachable (); |
48837e29 | 4609 | } |
07aae5c2 | 4610 | |
8c440872 NS |
4611 | /* This case must be taken care of by one of the two splitters |
4612 | that convert a variable shift into a loop. */ | |
4613 | gcc_assert (GET_CODE (operands[2]) == CONST_INT); | |
4614 | ||
4615 | n = INTVAL (operands[2]); | |
4616 | ||
4617 | /* If the count is negative, make it 0. */ | |
4618 | if (n < 0) | |
4619 | n = 0; | |
4620 | /* If the count is too big, truncate it. | |
4621 | ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to | |
4622 | do the intuitive thing. */ | |
4623 | else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) | |
4624 | n = GET_MODE_BITSIZE (mode); | |
4625 | ||
4626 | get_shift_alg (shift_type, shift_mode, n, &info); | |
4627 | ||
4628 | switch (info.alg) | |
48837e29 | 4629 | { |
8c440872 NS |
4630 | case SHIFT_SPECIAL: |
4631 | output_asm_insn (info.special, operands); | |
4632 | /* Fall through. */ | |
48837e29 | 4633 | |
8c440872 NS |
4634 | case SHIFT_INLINE: |
4635 | n = info.remainder; | |
48837e29 | 4636 | |
8c440872 NS |
4637 | /* Emit two bit shifts first. */ |
4638 | if (info.shift2 != NULL) | |
48837e29 | 4639 | { |
8c440872 NS |
4640 | for (; n > 1; n -= 2) |
4641 | output_asm_insn (info.shift2, operands); | |
4642 | } | |
51c0c1d7 | 4643 | |
8c440872 NS |
4644 | /* Now emit one bit shifts for any residual. */ |
4645 | for (; n > 0; n--) | |
4646 | output_asm_insn (info.shift1, operands); | |
4647 | return ""; | |
4648 | ||
4649 | case SHIFT_ROT_AND: | |
4650 | { | |
4651 | int m = GET_MODE_BITSIZE (mode) - n; | |
4652 | const int mask = (shift_type == SHIFT_ASHIFT | |
4653 | ? ((1 << m) - 1) << n | |
4654 | : (1 << m) - 1); | |
4655 | char insn_buf[200]; | |
4656 | ||
4657 | /* Not all possibilities of rotate are supported. They shouldn't | |
4658 | be generated, but let's watch for 'em. */ | |
4659 | gcc_assert (info.shift1); | |
4660 | ||
4661 | /* Emit two bit rotates first. */ | |
4662 | if (info.shift2 != NULL) | |
48837e29 | 4663 | { |
8c440872 NS |
4664 | for (; m > 1; m -= 2) |
4665 | output_asm_insn (info.shift2, operands); | |
4666 | } | |
4667 | ||
4668 | /* Now single bit rotates for any residual. */ | |
4669 | for (; m > 0; m--) | |
4670 | output_asm_insn (info.shift1, operands); | |
4671 | ||
4672 | /* Now mask off the high bits. */ | |
4673 | switch (mode) | |
4674 | { | |
4675 | case QImode: | |
4676 | sprintf (insn_buf, "and\t#%d,%%X0", mask); | |
4677 | break; | |
51c0c1d7 | 4678 | |
8c440872 NS |
4679 | case HImode: |
4680 | gcc_assert (TARGET_H8300H || TARGET_H8300S); | |
4681 | sprintf (insn_buf, "and.w\t#%d,%%T0", mask); | |
4682 | break; | |
51c0c1d7 | 4683 | |
8c440872 NS |
4684 | default: |
4685 | gcc_unreachable (); | |
48837e29 | 4686 | } |
b5eaf9ba | 4687 | |
8c440872 NS |
4688 | output_asm_insn (insn_buf, operands); |
4689 | return ""; | |
4690 | } | |
b5eaf9ba | 4691 | |
8c440872 NS |
4692 | case SHIFT_LOOP: |
4693 | /* A loop to shift by a "large" constant value. | |
4694 | If we have shift-by-2 insns, use them. */ | |
4695 | if (info.shift2 != NULL) | |
4696 | { | |
4697 | fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2, | |
4698 | names_big[REGNO (operands[4])]); | |
4699 | fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); | |
4700 | output_asm_insn (info.shift2, operands); | |
4701 | output_asm_insn ("add #0xff,%X4", operands); | |
4702 | fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); | |
4703 | if (n % 2) | |
4704 | output_asm_insn (info.shift1, operands); | |
4705 | } | |
4706 | else | |
4707 | { | |
4708 | fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n, | |
4709 | names_big[REGNO (operands[4])]); | |
4710 | fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); | |
4711 | output_asm_insn (info.shift1, operands); | |
4712 | output_asm_insn ("add #0xff,%X4", operands); | |
4713 | fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); | |
51c0c1d7 | 4714 | } |
8c440872 NS |
4715 | return ""; |
4716 | ||
4717 | default: | |
4718 | gcc_unreachable (); | |
07aae5c2 | 4719 | } |
07aae5c2 | 4720 | } |
86855e8c | 4721 | |
0a2aaacc | 4722 | /* Count the number of assembly instructions in a string TEMPL. */ |
e9eba255 | 4723 | |
86855e8c | 4724 | static unsigned int |
0a2aaacc | 4725 | h8300_asm_insn_count (const char *templ) |
86855e8c KH |
4726 | { |
4727 | unsigned int count = 1; | |
4728 | ||
0a2aaacc KG |
4729 | for (; *templ; templ++) |
4730 | if (*templ == '\n') | |
86855e8c KH |
4731 | count++; |
4732 | ||
4733 | return count; | |
4734 | } | |
4735 | ||
e9eba255 KH |
4736 | /* Compute the length of a shift insn. */ |
4737 | ||
86855e8c | 4738 | unsigned int |
cb713a8d | 4739 | compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands) |
86855e8c KH |
4740 | { |
4741 | rtx shift = operands[3]; | |
4742 | enum machine_mode mode = GET_MODE (shift); | |
4743 | enum rtx_code code = GET_CODE (shift); | |
4744 | enum shift_type shift_type; | |
4745 | enum shift_mode shift_mode; | |
4746 | struct shift_info info; | |
4747 | unsigned int wlength = 0; | |
4748 | ||
4749 | switch (mode) | |
4750 | { | |
4751 | case QImode: | |
4752 | shift_mode = QIshift; | |
4753 | break; | |
4754 | case HImode: | |
4755 | shift_mode = HIshift; | |
4756 | break; | |
4757 | case SImode: | |
4758 | shift_mode = SIshift; | |
4759 | break; | |
4760 | default: | |
8c440872 | 4761 | gcc_unreachable (); |
86855e8c KH |
4762 | } |
4763 | ||
4764 | switch (code) | |
4765 | { | |
4766 | case ASHIFTRT: | |
4767 | shift_type = SHIFT_ASHIFTRT; | |
4768 | break; | |
4769 | case LSHIFTRT: | |
4770 | shift_type = SHIFT_LSHIFTRT; | |
4771 | break; | |
4772 | case ASHIFT: | |
4773 | shift_type = SHIFT_ASHIFT; | |
4774 | break; | |
4775 | default: | |
8c440872 | 4776 | gcc_unreachable (); |
86855e8c KH |
4777 | } |
4778 | ||
4779 | if (GET_CODE (operands[2]) != CONST_INT) | |
4780 | { | |
4781 | /* Get the assembler code to do one shift. */ | |
4782 | get_shift_alg (shift_type, shift_mode, 1, &info); | |
4783 | ||
4784 | return (4 + h8300_asm_insn_count (info.shift1)) * 2; | |
4785 | } | |
4786 | else | |
4787 | { | |
4788 | int n = INTVAL (operands[2]); | |
4789 | ||
4790 | /* If the count is negative, make it 0. */ | |
4791 | if (n < 0) | |
4792 | n = 0; | |
4793 | /* If the count is too big, truncate it. | |
4794 | ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to | |
4795 | do the intuitive thing. */ | |
4796 | else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) | |
4797 | n = GET_MODE_BITSIZE (mode); | |
4798 | ||
4799 | get_shift_alg (shift_type, shift_mode, n, &info); | |
4800 | ||
4801 | switch (info.alg) | |
4802 | { | |
4803 | case SHIFT_SPECIAL: | |
4804 | wlength += h8300_asm_insn_count (info.special); | |
41c3eb5d KH |
4805 | |
4806 | /* Every assembly instruction used in SHIFT_SPECIAL case | |
4807 | takes 2 bytes except xor.l, which takes 4 bytes, so if we | |
4808 | see xor.l, we just pretend that xor.l counts as two insns | |
4809 | so that the insn length will be computed correctly. */ | |
4810 | if (strstr (info.special, "xor.l") != NULL) | |
4811 | wlength++; | |
4812 | ||
86855e8c KH |
4813 | /* Fall through. */ |
4814 | ||
4815 | case SHIFT_INLINE: | |
4816 | n = info.remainder; | |
4817 | ||
4818 | if (info.shift2 != NULL) | |
4819 | { | |
4820 | wlength += h8300_asm_insn_count (info.shift2) * (n / 2); | |
4821 | n = n % 2; | |
4822 | } | |
4823 | ||
4824 | wlength += h8300_asm_insn_count (info.shift1) * n; | |
6b148bd9 | 4825 | |
86855e8c KH |
4826 | return 2 * wlength; |
4827 | ||
4828 | case SHIFT_ROT_AND: | |
4829 | { | |
4830 | int m = GET_MODE_BITSIZE (mode) - n; | |
4831 | ||
4832 | /* Not all possibilities of rotate are supported. They shouldn't | |
4833 | be generated, but let's watch for 'em. */ | |
8c440872 | 4834 | gcc_assert (info.shift1); |
86855e8c KH |
4835 | |
4836 | if (info.shift2 != NULL) | |
4837 | { | |
4838 | wlength += h8300_asm_insn_count (info.shift2) * (m / 2); | |
4839 | m = m % 2; | |
4840 | } | |
4841 | ||
4842 | wlength += h8300_asm_insn_count (info.shift1) * m; | |
6b148bd9 | 4843 | |
86855e8c KH |
4844 | /* Now mask off the high bits. */ |
4845 | switch (mode) | |
4846 | { | |
4847 | case QImode: | |
4848 | wlength += 1; | |
4849 | break; | |
4850 | case HImode: | |
4851 | wlength += 2; | |
4852 | break; | |
4853 | case SImode: | |
8c440872 | 4854 | gcc_assert (!TARGET_H8300); |
86855e8c KH |
4855 | wlength += 3; |
4856 | break; | |
4857 | default: | |
8c440872 | 4858 | gcc_unreachable (); |
86855e8c KH |
4859 | } |
4860 | return 2 * wlength; | |
4861 | } | |
4862 | ||
4863 | case SHIFT_LOOP: | |
4864 | /* A loop to shift by a "large" constant value. | |
4865 | If we have shift-by-2 insns, use them. */ | |
4866 | if (info.shift2 != NULL) | |
4867 | { | |
4868 | wlength += 3 + h8300_asm_insn_count (info.shift2); | |
4869 | if (n % 2) | |
4870 | wlength += h8300_asm_insn_count (info.shift1); | |
4871 | } | |
4872 | else | |
4873 | { | |
4874 | wlength += 3 + h8300_asm_insn_count (info.shift1); | |
4875 | } | |
4876 | return 2 * wlength; | |
4877 | ||
4878 | default: | |
8c440872 | 4879 | gcc_unreachable (); |
86855e8c KH |
4880 | } |
4881 | } | |
4882 | } | |
45ca2106 | 4883 | |
e9eba255 KH |
4884 | /* Compute which flag bits are valid after a shift insn. */ |
4885 | ||
9690aa8e | 4886 | enum attr_cc |
cb713a8d | 4887 | compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands) |
45ca2106 KH |
4888 | { |
4889 | rtx shift = operands[3]; | |
4890 | enum machine_mode mode = GET_MODE (shift); | |
4891 | enum rtx_code code = GET_CODE (shift); | |
4892 | enum shift_type shift_type; | |
4893 | enum shift_mode shift_mode; | |
4894 | struct shift_info info; | |
8c440872 NS |
4895 | int n; |
4896 | ||
45ca2106 KH |
4897 | switch (mode) |
4898 | { | |
4899 | case QImode: | |
4900 | shift_mode = QIshift; | |
4901 | break; | |
4902 | case HImode: | |
4903 | shift_mode = HIshift; | |
4904 | break; | |
4905 | case SImode: | |
4906 | shift_mode = SIshift; | |
4907 | break; | |
4908 | default: | |
8c440872 | 4909 | gcc_unreachable (); |
45ca2106 KH |
4910 | } |
4911 | ||
4912 | switch (code) | |
4913 | { | |
4914 | case ASHIFTRT: | |
4915 | shift_type = SHIFT_ASHIFTRT; | |
4916 | break; | |
4917 | case LSHIFTRT: | |
4918 | shift_type = SHIFT_LSHIFTRT; | |
4919 | break; | |
4920 | case ASHIFT: | |
4921 | shift_type = SHIFT_ASHIFT; | |
4922 | break; | |
4923 | default: | |
8c440872 | 4924 | gcc_unreachable (); |
45ca2106 KH |
4925 | } |
4926 | ||
8c440872 NS |
4927 | /* This case must be taken care of by one of the two splitters |
4928 | that convert a variable shift into a loop. */ | |
4929 | gcc_assert (GET_CODE (operands[2]) == CONST_INT); | |
4930 | ||
4931 | n = INTVAL (operands[2]); | |
4932 | ||
4933 | /* If the count is negative, make it 0. */ | |
4934 | if (n < 0) | |
4935 | n = 0; | |
4936 | /* If the count is too big, truncate it. | |
4937 | ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to | |
4938 | do the intuitive thing. */ | |
4939 | else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) | |
4940 | n = GET_MODE_BITSIZE (mode); | |
4941 | ||
4942 | get_shift_alg (shift_type, shift_mode, n, &info); | |
4943 | ||
4944 | switch (info.alg) | |
45ca2106 | 4945 | { |
8c440872 NS |
4946 | case SHIFT_SPECIAL: |
4947 | if (info.remainder == 0) | |
4948 | return info.cc_special; | |
45ca2106 | 4949 | |
8c440872 | 4950 | /* Fall through. */ |
45ca2106 | 4951 | |
8c440872 NS |
4952 | case SHIFT_INLINE: |
4953 | return info.cc_inline; | |
4954 | ||
4955 | case SHIFT_ROT_AND: | |
4956 | /* This case always ends with an and instruction. */ | |
4957 | return CC_SET_ZNV; | |
4958 | ||
4959 | case SHIFT_LOOP: | |
4960 | /* A loop to shift by a "large" constant value. | |
4961 | If we have shift-by-2 insns, use them. */ | |
4962 | if (info.shift2 != NULL) | |
45ca2106 | 4963 | { |
8c440872 NS |
4964 | if (n % 2) |
4965 | return info.cc_inline; | |
45ca2106 | 4966 | } |
8c440872 NS |
4967 | return CC_CLOBBER; |
4968 | ||
4969 | default: | |
4970 | gcc_unreachable (); | |
45ca2106 KH |
4971 | } |
4972 | } | |
48837e29 | 4973 | \f |
edd71f0f KH |
4974 | /* A rotation by a non-constant will cause a loop to be generated, in |
4975 | which a rotation by one bit is used. A rotation by a constant, | |
4976 | including the one in the loop, will be taken care of by | |
caf7f21a | 4977 | output_a_rotate () at the insn emit time. */ |
edd71f0f KH |
4978 | |
4979 | int | |
3d2e90d6 | 4980 | expand_a_rotate (rtx operands[]) |
edd71f0f KH |
4981 | { |
4982 | rtx dst = operands[0]; | |
4983 | rtx src = operands[1]; | |
4984 | rtx rotate_amount = operands[2]; | |
4985 | enum machine_mode mode = GET_MODE (dst); | |
edd71f0f | 4986 | |
beed8fc0 AO |
4987 | if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY) |
4988 | return false; | |
4989 | ||
edd71f0f KH |
4990 | /* We rotate in place. */ |
4991 | emit_move_insn (dst, src); | |
4992 | ||
4993 | if (GET_CODE (rotate_amount) != CONST_INT) | |
4994 | { | |
4995 | rtx counter = gen_reg_rtx (QImode); | |
19f8b229 TS |
4996 | rtx_code_label *start_label = gen_label_rtx (); |
4997 | rtx_code_label *end_label = gen_label_rtx (); | |
edd71f0f KH |
4998 | |
4999 | /* If the rotate amount is less than or equal to 0, | |
5000 | we go out of the loop. */ | |
a556fd39 | 5001 | emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX, |
d43e0b7d | 5002 | QImode, 0, end_label); |
edd71f0f KH |
5003 | |
5004 | /* Initialize the loop counter. */ | |
5005 | emit_move_insn (counter, rotate_amount); | |
5006 | ||
5007 | emit_label (start_label); | |
5008 | ||
5009 | /* Rotate by one bit. */ | |
01ab5574 KH |
5010 | switch (mode) |
5011 | { | |
5012 | case QImode: | |
5013 | emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx)); | |
5014 | break; | |
5015 | case HImode: | |
5016 | emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx)); | |
5017 | break; | |
5018 | case SImode: | |
5019 | emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx)); | |
5020 | break; | |
5021 | default: | |
8c440872 | 5022 | gcc_unreachable (); |
01ab5574 | 5023 | } |
edd71f0f KH |
5024 | |
5025 | /* Decrement the counter by 1. */ | |
01ab5574 | 5026 | emit_insn (gen_addqi3 (counter, counter, constm1_rtx)); |
edd71f0f | 5027 | |
9cd10576 | 5028 | /* If the loop counter is nonzero, we go back to the beginning |
edd71f0f | 5029 | of the loop. */ |
a556fd39 | 5030 | emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1, |
d43e0b7d | 5031 | start_label); |
edd71f0f KH |
5032 | |
5033 | emit_label (end_label); | |
5034 | } | |
5035 | else | |
5036 | { | |
5037 | /* Rotate by AMOUNT bits. */ | |
01ab5574 KH |
5038 | switch (mode) |
5039 | { | |
5040 | case QImode: | |
5041 | emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount)); | |
5042 | break; | |
5043 | case HImode: | |
5044 | emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount)); | |
5045 | break; | |
5046 | case SImode: | |
5047 | emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount)); | |
5048 | break; | |
5049 | default: | |
8c440872 | 5050 | gcc_unreachable (); |
01ab5574 | 5051 | } |
edd71f0f KH |
5052 | } |
5053 | ||
5054 | return 1; | |
5055 | } | |
5056 | ||
e9eba255 | 5057 | /* Output a rotate insn. */ |
edd71f0f KH |
5058 | |
5059 | const char * | |
caf7f21a | 5060 | output_a_rotate (enum rtx_code code, rtx *operands) |
edd71f0f KH |
5061 | { |
5062 | rtx dst = operands[0]; | |
5063 | rtx rotate_amount = operands[2]; | |
5064 | enum shift_mode rotate_mode; | |
5065 | enum shift_type rotate_type; | |
5066 | const char *insn_buf; | |
5067 | int bits; | |
5068 | int amount; | |
5069 | enum machine_mode mode = GET_MODE (dst); | |
5070 | ||
8c440872 | 5071 | gcc_assert (GET_CODE (rotate_amount) == CONST_INT); |
edd71f0f KH |
5072 | |
5073 | switch (mode) | |
5074 | { | |
5075 | case QImode: | |
5076 | rotate_mode = QIshift; | |
5077 | break; | |
5078 | case HImode: | |
5079 | rotate_mode = HIshift; | |
5080 | break; | |
5081 | case SImode: | |
5082 | rotate_mode = SIshift; | |
5083 | break; | |
5084 | default: | |
8c440872 | 5085 | gcc_unreachable (); |
edd71f0f KH |
5086 | } |
5087 | ||
5088 | switch (code) | |
5089 | { | |
5090 | case ROTATERT: | |
5091 | rotate_type = SHIFT_ASHIFT; | |
5092 | break; | |
5093 | case ROTATE: | |
5094 | rotate_type = SHIFT_LSHIFTRT; | |
5095 | break; | |
5096 | default: | |
8c440872 | 5097 | gcc_unreachable (); |
edd71f0f KH |
5098 | } |
5099 | ||
5100 | amount = INTVAL (rotate_amount); | |
5101 | ||
5102 | /* Clean up AMOUNT. */ | |
5103 | if (amount < 0) | |
5104 | amount = 0; | |
5105 | if ((unsigned int) amount > GET_MODE_BITSIZE (mode)) | |
5106 | amount = GET_MODE_BITSIZE (mode); | |
5107 | ||
5108 | /* Determine the faster direction. After this phase, amount will be | |
5109 | at most a half of GET_MODE_BITSIZE (mode). */ | |
e0c32c62 | 5110 | if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2) |
edd71f0f KH |
5111 | { |
5112 | /* Flip the direction. */ | |
5113 | amount = GET_MODE_BITSIZE (mode) - amount; | |
5114 | rotate_type = | |
5115 | (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT; | |
5116 | } | |
5117 | ||
5118 | /* See if a byte swap (in HImode) or a word swap (in SImode) can | |
5119 | boost up the rotation. */ | |
5120 | if ((mode == HImode && TARGET_H8300 && amount >= 5) | |
5121 | || (mode == HImode && TARGET_H8300H && amount >= 6) | |
5122 | || (mode == HImode && TARGET_H8300S && amount == 8) | |
5123 | || (mode == SImode && TARGET_H8300H && amount >= 10) | |
5124 | || (mode == SImode && TARGET_H8300S && amount >= 13)) | |
5125 | { | |
5126 | switch (mode) | |
5127 | { | |
5128 | case HImode: | |
5129 | /* This code works on any family. */ | |
5130 | insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0"; | |
5131 | output_asm_insn (insn_buf, operands); | |
5132 | break; | |
5133 | ||
5134 | case SImode: | |
3db11b5c | 5135 | /* This code works on the H8/300H and H8S. */ |
edd71f0f KH |
5136 | insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0"; |
5137 | output_asm_insn (insn_buf, operands); | |
5138 | break; | |
5139 | ||
5140 | default: | |
8c440872 | 5141 | gcc_unreachable (); |
edd71f0f KH |
5142 | } |
5143 | ||
5144 | /* Adjust AMOUNT and flip the direction. */ | |
5145 | amount = GET_MODE_BITSIZE (mode) / 2 - amount; | |
5146 | rotate_type = | |
5147 | (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT; | |
5148 | } | |
5149 | ||
01ab5574 | 5150 | /* Output rotate insns. */ |
edd71f0f KH |
5151 | for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2) |
5152 | { | |
5153 | if (bits == 2) | |
5154 | insn_buf = rotate_two[rotate_type][rotate_mode]; | |
5155 | else | |
5156 | insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode]; | |
2c54abce | 5157 | |
edd71f0f KH |
5158 | for (; amount >= bits; amount -= bits) |
5159 | output_asm_insn (insn_buf, operands); | |
5160 | } | |
5161 | ||
5162 | return ""; | |
5163 | } | |
caf7f21a | 5164 | |
e9eba255 KH |
5165 | /* Compute the length of a rotate insn. */ |
5166 | ||
caf7f21a KH |
5167 | unsigned int |
5168 | compute_a_rotate_length (rtx *operands) | |
5169 | { | |
5170 | rtx src = operands[1]; | |
343fd2c7 | 5171 | rtx amount_rtx = operands[2]; |
caf7f21a KH |
5172 | enum machine_mode mode = GET_MODE (src); |
5173 | int amount; | |
5174 | unsigned int length = 0; | |
5175 | ||
8c440872 | 5176 | gcc_assert (GET_CODE (amount_rtx) == CONST_INT); |
caf7f21a | 5177 | |
343fd2c7 | 5178 | amount = INTVAL (amount_rtx); |
caf7f21a KH |
5179 | |
5180 | /* Clean up AMOUNT. */ | |
5181 | if (amount < 0) | |
5182 | amount = 0; | |
5183 | if ((unsigned int) amount > GET_MODE_BITSIZE (mode)) | |
5184 | amount = GET_MODE_BITSIZE (mode); | |
5185 | ||
5186 | /* Determine the faster direction. After this phase, amount | |
5187 | will be at most a half of GET_MODE_BITSIZE (mode). */ | |
5188 | if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2) | |
5189 | /* Flip the direction. */ | |
5190 | amount = GET_MODE_BITSIZE (mode) - amount; | |
5191 | ||
5192 | /* See if a byte swap (in HImode) or a word swap (in SImode) can | |
5193 | boost up the rotation. */ | |
5194 | if ((mode == HImode && TARGET_H8300 && amount >= 5) | |
5195 | || (mode == HImode && TARGET_H8300H && amount >= 6) | |
5196 | || (mode == HImode && TARGET_H8300S && amount == 8) | |
5197 | || (mode == SImode && TARGET_H8300H && amount >= 10) | |
5198 | || (mode == SImode && TARGET_H8300S && amount >= 13)) | |
5199 | { | |
5200 | /* Adjust AMOUNT and flip the direction. */ | |
5201 | amount = GET_MODE_BITSIZE (mode) / 2 - amount; | |
5202 | length += 6; | |
5203 | } | |
5204 | ||
5205 | /* We use 2-bit rotations on the H8S. */ | |
5206 | if (TARGET_H8300S) | |
5207 | amount = amount / 2 + amount % 2; | |
5208 | ||
5209 | /* The H8/300 uses three insns to rotate one bit, taking 6 | |
5210 | length. */ | |
5211 | length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2); | |
5212 | ||
5213 | return length; | |
5214 | } | |
edd71f0f | 5215 | \f |
48837e29 | 5216 | /* Fix the operands of a gen_xxx so that it could become a bit |
2c54abce | 5217 | operating insn. */ |
07aae5c2 SC |
5218 | |
5219 | int | |
4093985c | 5220 | fix_bit_operand (rtx *operands, enum rtx_code code) |
07aae5c2 | 5221 | { |
abc95ed3 | 5222 | /* The bit_operand predicate accepts any memory during RTL generation, but |
48837e29 DE |
5223 | only 'U' memory afterwards, so if this is a MEM operand, we must force |
5224 | it to be valid for 'U' by reloading the address. */ | |
07aae5c2 | 5225 | |
4093985c KH |
5226 | if (code == AND |
5227 | ? single_zero_operand (operands[2], QImode) | |
5228 | : single_one_operand (operands[2], QImode)) | |
07aae5c2 | 5229 | { |
2e760b15 KH |
5230 | /* OK to have a memory dest. */ |
5231 | if (GET_CODE (operands[0]) == MEM | |
ceaaaeab | 5232 | && !satisfies_constraint_U (operands[0])) |
48837e29 | 5233 | { |
2e760b15 KH |
5234 | rtx mem = gen_rtx_MEM (GET_MODE (operands[0]), |
5235 | copy_to_mode_reg (Pmode, | |
5236 | XEXP (operands[0], 0))); | |
5237 | MEM_COPY_ATTRIBUTES (mem, operands[0]); | |
5238 | operands[0] = mem; | |
5239 | } | |
48837e29 | 5240 | |
2e760b15 | 5241 | if (GET_CODE (operands[1]) == MEM |
ceaaaeab | 5242 | && !satisfies_constraint_U (operands[1])) |
2e760b15 KH |
5243 | { |
5244 | rtx mem = gen_rtx_MEM (GET_MODE (operands[1]), | |
5245 | copy_to_mode_reg (Pmode, | |
5246 | XEXP (operands[1], 0))); | |
5247 | MEM_COPY_ATTRIBUTES (mem, operands[0]); | |
5248 | operands[1] = mem; | |
48837e29 | 5249 | } |
2e760b15 | 5250 | return 0; |
48837e29 | 5251 | } |
07aae5c2 | 5252 | |
48837e29 | 5253 | /* Dest and src op must be register. */ |
07aae5c2 | 5254 | |
48837e29 DE |
5255 | operands[1] = force_reg (QImode, operands[1]); |
5256 | { | |
5257 | rtx res = gen_reg_rtx (QImode); | |
fd57a6e4 | 5258 | switch (code) |
a3579575 KH |
5259 | { |
5260 | case AND: | |
5261 | emit_insn (gen_andqi3_1 (res, operands[1], operands[2])); | |
5262 | break; | |
5263 | case IOR: | |
5264 | emit_insn (gen_iorqi3_1 (res, operands[1], operands[2])); | |
5265 | break; | |
5266 | case XOR: | |
5267 | emit_insn (gen_xorqi3_1 (res, operands[1], operands[2])); | |
5268 | break; | |
5269 | default: | |
8c440872 | 5270 | gcc_unreachable (); |
a3579575 KH |
5271 | } |
5272 | emit_insn (gen_movqi (operands[0], res)); | |
48837e29 DE |
5273 | } |
5274 | return 1; | |
07aae5c2 | 5275 | } |
f5b65a56 | 5276 | |
f5b65a56 JL |
5277 | /* Return nonzero if FUNC is an interrupt function as specified |
5278 | by the "interrupt" attribute. */ | |
5279 | ||
5280 | static int | |
cb713a8d | 5281 | h8300_interrupt_function_p (tree func) |
f5b65a56 JL |
5282 | { |
5283 | tree a; | |
5284 | ||
5285 | if (TREE_CODE (func) != FUNCTION_DECL) | |
5286 | return 0; | |
5287 | ||
91d231cb | 5288 | a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func)); |
f5b65a56 JL |
5289 | return a != NULL_TREE; |
5290 | } | |
5291 | ||
3cfa3702 KH |
5292 | /* Return nonzero if FUNC is a saveall function as specified by the |
5293 | "saveall" attribute. */ | |
5294 | ||
5295 | static int | |
5296 | h8300_saveall_function_p (tree func) | |
5297 | { | |
5298 | tree a; | |
5299 | ||
5300 | if (TREE_CODE (func) != FUNCTION_DECL) | |
5301 | return 0; | |
5302 | ||
5303 | a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func)); | |
5304 | return a != NULL_TREE; | |
5305 | } | |
5306 | ||
fabe72bb JL |
5307 | /* Return nonzero if FUNC is an OS_Task function as specified |
5308 | by the "OS_Task" attribute. */ | |
5309 | ||
5310 | static int | |
cb713a8d | 5311 | h8300_os_task_function_p (tree func) |
fabe72bb JL |
5312 | { |
5313 | tree a; | |
5314 | ||
5315 | if (TREE_CODE (func) != FUNCTION_DECL) | |
5316 | return 0; | |
5317 | ||
91d231cb | 5318 | a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func)); |
fabe72bb JL |
5319 | return a != NULL_TREE; |
5320 | } | |
5321 | ||
5322 | /* Return nonzero if FUNC is a monitor function as specified | |
5323 | by the "monitor" attribute. */ | |
5324 | ||
5325 | static int | |
cb713a8d | 5326 | h8300_monitor_function_p (tree func) |
fabe72bb JL |
5327 | { |
5328 | tree a; | |
5329 | ||
5330 | if (TREE_CODE (func) != FUNCTION_DECL) | |
5331 | return 0; | |
5332 | ||
91d231cb | 5333 | a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func)); |
fabe72bb JL |
5334 | return a != NULL_TREE; |
5335 | } | |
5336 | ||
f5b65a56 JL |
5337 | /* Return nonzero if FUNC is a function that should be called |
5338 | through the function vector. */ | |
5339 | ||
5340 | int | |
cb713a8d | 5341 | h8300_funcvec_function_p (tree func) |
f5b65a56 JL |
5342 | { |
5343 | tree a; | |
5344 | ||
5345 | if (TREE_CODE (func) != FUNCTION_DECL) | |
5346 | return 0; | |
5347 | ||
91d231cb | 5348 | a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func)); |
f5b65a56 JL |
5349 | return a != NULL_TREE; |
5350 | } | |
5351 | ||
887a8bd9 | 5352 | /* Return nonzero if DECL is a variable that's in the eight bit |
15dc331e JL |
5353 | data area. */ |
5354 | ||
5355 | int | |
cb713a8d | 5356 | h8300_eightbit_data_p (tree decl) |
15dc331e JL |
5357 | { |
5358 | tree a; | |
5359 | ||
5360 | if (TREE_CODE (decl) != VAR_DECL) | |
5361 | return 0; | |
5362 | ||
91d231cb | 5363 | a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl)); |
15dc331e JL |
5364 | return a != NULL_TREE; |
5365 | } | |
5366 | ||
887a8bd9 JL |
5367 | /* Return nonzero if DECL is a variable that's in the tiny |
5368 | data area. */ | |
5369 | ||
5370 | int | |
cb713a8d | 5371 | h8300_tiny_data_p (tree decl) |
887a8bd9 JL |
5372 | { |
5373 | tree a; | |
5374 | ||
5375 | if (TREE_CODE (decl) != VAR_DECL) | |
5376 | return 0; | |
5377 | ||
91d231cb | 5378 | a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl)); |
887a8bd9 JL |
5379 | return a != NULL_TREE; |
5380 | } | |
5381 | ||
3cfa3702 KH |
5382 | /* Generate an 'interrupt_handler' attribute for decls. We convert |
5383 | all the pragmas to corresponding attributes. */ | |
2c1d2fcb DD |
5384 | |
5385 | static void | |
cb713a8d | 5386 | h8300_insert_attributes (tree node, tree *attributes) |
2c1d2fcb | 5387 | { |
3cfa3702 KH |
5388 | if (TREE_CODE (node) == FUNCTION_DECL) |
5389 | { | |
5390 | if (pragma_interrupt) | |
5391 | { | |
5392 | pragma_interrupt = 0; | |
2c1d2fcb | 5393 | |
3cfa3702 KH |
5394 | /* Add an 'interrupt_handler' attribute. */ |
5395 | *attributes = tree_cons (get_identifier ("interrupt_handler"), | |
5396 | NULL, *attributes); | |
5397 | } | |
e392d367 | 5398 | |
3cfa3702 KH |
5399 | if (pragma_saveall) |
5400 | { | |
5401 | pragma_saveall = 0; | |
5402 | ||
5403 | /* Add an 'saveall' attribute. */ | |
5404 | *attributes = tree_cons (get_identifier ("saveall"), | |
5405 | NULL, *attributes); | |
5406 | } | |
5407 | } | |
2c1d2fcb DD |
5408 | } |
5409 | ||
91d231cb | 5410 | /* Supported attributes: |
f5b65a56 | 5411 | |
97c5ec1d | 5412 | interrupt_handler: output a prologue and epilogue suitable for an |
f5b65a56 JL |
5413 | interrupt handler. |
5414 | ||
3cfa3702 KH |
5415 | saveall: output a prologue and epilogue that saves and restores |
5416 | all registers except the stack pointer. | |
5417 | ||
97c5ec1d | 5418 | function_vector: This function should be called through the |
887a8bd9 JL |
5419 | function vector. |
5420 | ||
5421 | eightbit_data: This variable lives in the 8-bit data area and can | |
5422 | be referenced with 8-bit absolute memory addresses. | |
5423 | ||
5424 | tiny_data: This variable lives in the tiny data area and can be | |
5425 | referenced with 16-bit absolute memory references. */ | |
f5b65a56 | 5426 | |
6bc7bc14 | 5427 | static const struct attribute_spec h8300_attribute_table[] = |
f5b65a56 | 5428 | { |
62d784f7 KT |
5429 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler, |
5430 | affects_type_identity } */ | |
5431 | { "interrupt_handler", 0, 0, true, false, false, | |
5432 | h8300_handle_fndecl_attribute, false }, | |
5433 | { "saveall", 0, 0, true, false, false, | |
5434 | h8300_handle_fndecl_attribute, false }, | |
5435 | { "OS_Task", 0, 0, true, false, false, | |
5436 | h8300_handle_fndecl_attribute, false }, | |
5437 | { "monitor", 0, 0, true, false, false, | |
5438 | h8300_handle_fndecl_attribute, false }, | |
5439 | { "function_vector", 0, 0, true, false, false, | |
5440 | h8300_handle_fndecl_attribute, false }, | |
5441 | { "eightbit_data", 0, 0, true, false, false, | |
5442 | h8300_handle_eightbit_data_attribute, false }, | |
5443 | { "tiny_data", 0, 0, true, false, false, | |
5444 | h8300_handle_tiny_data_attribute, false }, | |
5445 | { NULL, 0, 0, false, false, false, NULL, false } | |
91d231cb | 5446 | }; |
f5b65a56 | 5447 | |
15dc331e | 5448 | |
91d231cb JM |
5449 | /* Handle an attribute requiring a FUNCTION_DECL; arguments as in |
5450 | struct attribute_spec.handler. */ | |
5451 | static tree | |
cb713a8d KH |
5452 | h8300_handle_fndecl_attribute (tree *node, tree name, |
5453 | tree args ATTRIBUTE_UNUSED, | |
5454 | int flags ATTRIBUTE_UNUSED, | |
5455 | bool *no_add_attrs) | |
91d231cb JM |
5456 | { |
5457 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
5458 | { | |
29d08eba JM |
5459 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
5460 | name); | |
91d231cb JM |
5461 | *no_add_attrs = true; |
5462 | } | |
5463 | ||
5464 | return NULL_TREE; | |
5465 | } | |
5466 | ||
5467 | /* Handle an "eightbit_data" attribute; arguments as in | |
5468 | struct attribute_spec.handler. */ | |
5469 | static tree | |
cb713a8d KH |
5470 | h8300_handle_eightbit_data_attribute (tree *node, tree name, |
5471 | tree args ATTRIBUTE_UNUSED, | |
5472 | int flags ATTRIBUTE_UNUSED, | |
5473 | bool *no_add_attrs) | |
91d231cb JM |
5474 | { |
5475 | tree decl = *node; | |
5476 | ||
5477 | if (TREE_STATIC (decl) || DECL_EXTERNAL (decl)) | |
15dc331e | 5478 | { |
f961457f | 5479 | set_decl_section_name (decl, ".eight"); |
91d231cb JM |
5480 | } |
5481 | else | |
5482 | { | |
29d08eba JM |
5483 | warning (OPT_Wattributes, "%qE attribute ignored", |
5484 | name); | |
91d231cb | 5485 | *no_add_attrs = true; |
887a8bd9 JL |
5486 | } |
5487 | ||
91d231cb JM |
5488 | return NULL_TREE; |
5489 | } | |
5490 | ||
5491 | /* Handle an "tiny_data" attribute; arguments as in | |
5492 | struct attribute_spec.handler. */ | |
5493 | static tree | |
cb713a8d KH |
5494 | h8300_handle_tiny_data_attribute (tree *node, tree name, |
5495 | tree args ATTRIBUTE_UNUSED, | |
5496 | int flags ATTRIBUTE_UNUSED, | |
5497 | bool *no_add_attrs) | |
91d231cb JM |
5498 | { |
5499 | tree decl = *node; | |
5500 | ||
5501 | if (TREE_STATIC (decl) || DECL_EXTERNAL (decl)) | |
887a8bd9 | 5502 | { |
f961457f | 5503 | set_decl_section_name (decl, ".tiny"); |
91d231cb JM |
5504 | } |
5505 | else | |
5506 | { | |
29d08eba JM |
5507 | warning (OPT_Wattributes, "%qE attribute ignored", |
5508 | name); | |
91d231cb | 5509 | *no_add_attrs = true; |
15dc331e | 5510 | } |
07e4d94e | 5511 | |
91d231cb | 5512 | return NULL_TREE; |
f5b65a56 JL |
5513 | } |
5514 | ||
dc66a1c4 | 5515 | /* Mark function vectors, and various small data objects. */ |
fb49053f RH |
5516 | |
5517 | static void | |
cb713a8d | 5518 | h8300_encode_section_info (tree decl, rtx rtl, int first) |
fb49053f | 5519 | { |
dc66a1c4 RH |
5520 | int extra_flags = 0; |
5521 | ||
c6a2438a | 5522 | default_encode_section_info (decl, rtl, first); |
dc66a1c4 | 5523 | |
fb49053f RH |
5524 | if (TREE_CODE (decl) == FUNCTION_DECL |
5525 | && h8300_funcvec_function_p (decl)) | |
dc66a1c4 | 5526 | extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION; |
fb49053f RH |
5527 | else if (TREE_CODE (decl) == VAR_DECL |
5528 | && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))) | |
5529 | { | |
5530 | if (h8300_eightbit_data_p (decl)) | |
dc66a1c4 | 5531 | extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA; |
fb49053f | 5532 | else if (first && h8300_tiny_data_p (decl)) |
dc66a1c4 | 5533 | extra_flags = SYMBOL_FLAG_TINY_DATA; |
fb49053f | 5534 | } |
772c5265 | 5535 | |
dc66a1c4 | 5536 | if (extra_flags) |
c6a2438a | 5537 | SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags; |
772c5265 RH |
5538 | } |
5539 | ||
e9eba255 KH |
5540 | /* Output a single-bit extraction. */ |
5541 | ||
441d04c6 | 5542 | const char * |
cb713a8d | 5543 | output_simode_bld (int bild, rtx operands[]) |
bd93f126 | 5544 | { |
6be580c7 KH |
5545 | if (TARGET_H8300) |
5546 | { | |
5547 | /* Clear the destination register. */ | |
5548 | output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands); | |
5549 | ||
5550 | /* Now output the bit load or bit inverse load, and store it in | |
5551 | the destination. */ | |
5552 | if (bild) | |
5553 | output_asm_insn ("bild\t%Z2,%Y1", operands); | |
5554 | else | |
5555 | output_asm_insn ("bld\t%Z2,%Y1", operands); | |
bd93f126 | 5556 | |
6be580c7 KH |
5557 | output_asm_insn ("bst\t#0,%w0", operands); |
5558 | } | |
bd93f126 | 5559 | else |
6be580c7 | 5560 | { |
0eb933a0 KH |
5561 | /* Determine if we can clear the destination first. */ |
5562 | int clear_first = (REG_P (operands[0]) && REG_P (operands[1]) | |
5563 | && REGNO (operands[0]) != REGNO (operands[1])); | |
5564 | ||
5565 | if (clear_first) | |
5566 | output_asm_insn ("sub.l\t%S0,%S0", operands); | |
5567 | ||
6be580c7 KH |
5568 | /* Output the bit load or bit inverse load. */ |
5569 | if (bild) | |
5570 | output_asm_insn ("bild\t%Z2,%Y1", operands); | |
5571 | else | |
5572 | output_asm_insn ("bld\t%Z2,%Y1", operands); | |
5573 | ||
0eb933a0 KH |
5574 | if (!clear_first) |
5575 | output_asm_insn ("xor.l\t%S0,%S0", operands); | |
5576 | ||
5577 | /* Perform the bit store. */ | |
802a9907 | 5578 | output_asm_insn ("rotxl.l\t%S0", operands); |
6be580c7 | 5579 | } |
bd93f126 JL |
5580 | |
5581 | /* All done. */ | |
5582 | return ""; | |
5583 | } | |
e6219736 | 5584 | |
beed8fc0 AO |
5585 | /* Delayed-branch scheduling is more effective if we have some idea |
5586 | how long each instruction will be. Use a shorten_branches pass | |
5587 | to get an initial estimate. */ | |
5588 | ||
5589 | static void | |
5590 | h8300_reorg (void) | |
5591 | { | |
5592 | if (flag_delayed_branch) | |
5593 | shorten_branches (get_insns ()); | |
5594 | } | |
5595 | ||
ede75ee8 | 5596 | #ifndef OBJECT_FORMAT_ELF |
7c262518 | 5597 | static void |
c18a5b6c MM |
5598 | h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED, |
5599 | tree decl) | |
7c262518 RH |
5600 | { |
5601 | /* ??? Perhaps we should be using default_coff_asm_named_section. */ | |
5602 | fprintf (asm_out_file, "\t.section %s\n", name); | |
5603 | } | |
ede75ee8 | 5604 | #endif /* ! OBJECT_FORMAT_ELF */ |
803d56f5 | 5605 | |
7c143ed2 KH |
5606 | /* Nonzero if X is a constant address suitable as an 8-bit absolute, |
5607 | which is a special case of the 'R' operand. */ | |
5608 | ||
803d56f5 | 5609 | int |
cb713a8d | 5610 | h8300_eightbit_constant_address_p (rtx x) |
803d56f5 | 5611 | { |
ff482c8d | 5612 | /* The ranges of the 8-bit area. */ |
d2d199a3 KH |
5613 | const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode); |
5614 | const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode); | |
803d56f5 KH |
5615 | const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode); |
5616 | const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode); | |
5617 | const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode); | |
5618 | const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode); | |
5619 | ||
5620 | unsigned HOST_WIDE_INT addr; | |
5621 | ||
9675a91e | 5622 | /* We accept symbols declared with eightbit_data. */ |
dc66a1c4 RH |
5623 | if (GET_CODE (x) == SYMBOL_REF) |
5624 | return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0; | |
9675a91e | 5625 | |
803d56f5 KH |
5626 | if (GET_CODE (x) != CONST_INT) |
5627 | return 0; | |
5628 | ||
5629 | addr = INTVAL (x); | |
5630 | ||
5631 | return (0 | |
39ba95b5 | 5632 | || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2)) |
803d56f5 KH |
5633 | || (TARGET_H8300H && IN_RANGE (addr, h1, h2)) |
5634 | || (TARGET_H8300S && IN_RANGE (addr, s1, s2))); | |
5635 | } | |
5636 | ||
7c143ed2 KH |
5637 | /* Nonzero if X is a constant address suitable as an 16-bit absolute |
5638 | on H8/300H and H8S. */ | |
5639 | ||
803d56f5 | 5640 | int |
cb713a8d | 5641 | h8300_tiny_constant_address_p (rtx x) |
803d56f5 | 5642 | { |
3f7211f1 | 5643 | /* The ranges of the 16-bit area. */ |
803d56f5 KH |
5644 | const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode); |
5645 | const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode); | |
5646 | const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode); | |
5647 | const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode); | |
5648 | const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode); | |
5649 | const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode); | |
5650 | const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode); | |
5651 | const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode); | |
5652 | ||
5653 | unsigned HOST_WIDE_INT addr; | |
5654 | ||
d6456562 KH |
5655 | switch (GET_CODE (x)) |
5656 | { | |
5657 | case SYMBOL_REF: | |
a4bb41cc KH |
5658 | /* In the normal mode, any symbol fits in the 16-bit absolute |
5659 | address range. We also accept symbols declared with | |
5660 | tiny_data. */ | |
5661 | return (TARGET_NORMAL_MODE | |
5662 | || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0); | |
56b8e164 | 5663 | |
d6456562 KH |
5664 | case CONST_INT: |
5665 | addr = INTVAL (x); | |
5666 | return (TARGET_NORMAL_MODE | |
5667 | || (TARGET_H8300H | |
5668 | && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4))) | |
5669 | || (TARGET_H8300S | |
5670 | && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4)))); | |
803d56f5 | 5671 | |
a4bb41cc KH |
5672 | case CONST: |
5673 | return TARGET_NORMAL_MODE; | |
5674 | ||
d6456562 KH |
5675 | default: |
5676 | return 0; | |
5677 | } | |
803d56f5 | 5678 | |
803d56f5 | 5679 | } |
9b98dc74 | 5680 | |
e9eba255 KH |
5681 | /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory |
5682 | locations that can be accessed as a 16-bit word. */ | |
5683 | ||
9b98dc74 | 5684 | int |
cb713a8d | 5685 | byte_accesses_mergeable_p (rtx addr1, rtx addr2) |
9b98dc74 KH |
5686 | { |
5687 | HOST_WIDE_INT offset1, offset2; | |
5688 | rtx reg1, reg2; | |
5689 | ||
5690 | if (REG_P (addr1)) | |
5691 | { | |
5692 | reg1 = addr1; | |
5693 | offset1 = 0; | |
5694 | } | |
5695 | else if (GET_CODE (addr1) == PLUS | |
5696 | && REG_P (XEXP (addr1, 0)) | |
5697 | && GET_CODE (XEXP (addr1, 1)) == CONST_INT) | |
5698 | { | |
5699 | reg1 = XEXP (addr1, 0); | |
5700 | offset1 = INTVAL (XEXP (addr1, 1)); | |
5701 | } | |
5702 | else | |
5703 | return 0; | |
5704 | ||
5705 | if (REG_P (addr2)) | |
5706 | { | |
5707 | reg2 = addr2; | |
5708 | offset2 = 0; | |
5709 | } | |
5710 | else if (GET_CODE (addr2) == PLUS | |
5711 | && REG_P (XEXP (addr2, 0)) | |
5712 | && GET_CODE (XEXP (addr2, 1)) == CONST_INT) | |
5713 | { | |
5714 | reg2 = XEXP (addr2, 0); | |
5715 | offset2 = INTVAL (XEXP (addr2, 1)); | |
5716 | } | |
5717 | else | |
5718 | return 0; | |
5719 | ||
5720 | if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx) | |
5721 | || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx)) | |
5722 | && offset1 % 2 == 0 | |
5723 | && offset1 + 1 == offset2) | |
5724 | return 1; | |
5725 | ||
5726 | return 0; | |
5727 | } | |
02529902 KH |
5728 | |
5729 | /* Return nonzero if we have the same comparison insn as I3 two insns | |
19cff4db | 5730 | before I3. I3 is assumed to be a comparison insn. */ |
02529902 KH |
5731 | |
5732 | int | |
5733 | same_cmp_preceding_p (rtx i3) | |
5734 | { | |
68a1a6c0 | 5735 | rtx_insn *i1, *i2; |
02529902 KH |
5736 | |
5737 | /* Make sure we have a sequence of three insns. */ | |
5738 | i2 = prev_nonnote_insn (i3); | |
68a1a6c0 | 5739 | if (i2 == NULL) |
02529902 KH |
5740 | return 0; |
5741 | i1 = prev_nonnote_insn (i2); | |
68a1a6c0 | 5742 | if (i1 == NULL) |
02529902 KH |
5743 | return 0; |
5744 | ||
5745 | return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3)) | |
5746 | && any_condjump_p (i2) && onlyjump_p (i2)); | |
5747 | } | |
c87ec0ba | 5748 | |
c06d5c85 KH |
5749 | /* Return nonzero if we have the same comparison insn as I1 two insns |
5750 | after I1. I1 is assumed to be a comparison insn. */ | |
5751 | ||
5752 | int | |
5753 | same_cmp_following_p (rtx i1) | |
5754 | { | |
68a1a6c0 | 5755 | rtx_insn *i2, *i3; |
c06d5c85 KH |
5756 | |
5757 | /* Make sure we have a sequence of three insns. */ | |
5758 | i2 = next_nonnote_insn (i1); | |
68a1a6c0 | 5759 | if (i2 == NULL) |
c06d5c85 KH |
5760 | return 0; |
5761 | i3 = next_nonnote_insn (i2); | |
68a1a6c0 | 5762 | if (i3 == NULL) |
c06d5c85 KH |
5763 | return 0; |
5764 | ||
5765 | return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3)) | |
5766 | && any_condjump_p (i2) && onlyjump_p (i2)); | |
5767 | } | |
5768 | ||
a466bea3 | 5769 | /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes |
1ae58c30 | 5770 | (or pops) N registers. OPERANDS are assumed to be an array of |
a466bea3 KH |
5771 | registers. */ |
5772 | ||
5773 | int | |
5774 | h8300_regs_ok_for_stm (int n, rtx operands[]) | |
5775 | { | |
5776 | switch (n) | |
5777 | { | |
5778 | case 2: | |
5779 | return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1) | |
5780 | || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3) | |
5781 | || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5)); | |
5782 | case 3: | |
5783 | return ((REGNO (operands[0]) == 0 | |
5784 | && REGNO (operands[1]) == 1 | |
5785 | && REGNO (operands[2]) == 2) | |
5786 | || (REGNO (operands[0]) == 4 | |
5787 | && REGNO (operands[1]) == 5 | |
5788 | && REGNO (operands[2]) == 6)); | |
5789 | ||
5790 | case 4: | |
5791 | return (REGNO (operands[0]) == 0 | |
5792 | && REGNO (operands[1]) == 1 | |
5793 | && REGNO (operands[2]) == 2 | |
5794 | && REGNO (operands[3]) == 3); | |
8c440872 NS |
5795 | default: |
5796 | gcc_unreachable (); | |
a466bea3 | 5797 | } |
a466bea3 KH |
5798 | } |
5799 | ||
c87ec0ba NY |
5800 | /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */ |
5801 | ||
5802 | int | |
5803 | h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, | |
5804 | unsigned int new_reg) | |
5805 | { | |
5806 | /* Interrupt functions can only use registers that have already been | |
5807 | saved by the prologue, even if they would normally be | |
5808 | call-clobbered. */ | |
5809 | ||
5810 | if (h8300_current_function_interrupt_function_p () | |
6fb5fa3c | 5811 | && !df_regs_ever_live_p (new_reg)) |
c87ec0ba NY |
5812 | return 0; |
5813 | ||
80e58519 | 5814 | return 1; |
c87ec0ba | 5815 | } |
d0022200 | 5816 | |
2e762884 DD |
5817 | /* Returns true if register REGNO is safe to be allocated as a scratch |
5818 | register in the current function. */ | |
5819 | ||
5820 | static bool | |
5821 | h8300_hard_regno_scratch_ok (unsigned int regno) | |
5822 | { | |
5823 | if (h8300_current_function_interrupt_function_p () | |
5824 | && ! WORD_REG_USED (regno)) | |
5825 | return false; | |
5826 | ||
5827 | return true; | |
5828 | } | |
5829 | ||
5830 | ||
d0022200 KH |
5831 | /* Return nonzero if X is a REG or SUBREG suitable as a base register. */ |
5832 | ||
5833 | static int | |
5834 | h8300_rtx_ok_for_base_p (rtx x, int strict) | |
5835 | { | |
5836 | /* Strip off SUBREG if any. */ | |
5837 | if (GET_CODE (x) == SUBREG) | |
5838 | x = SUBREG_REG (x); | |
5839 | ||
5840 | return (REG_P (x) | |
5841 | && (strict | |
5842 | ? REG_OK_FOR_BASE_STRICT_P (x) | |
5843 | : REG_OK_FOR_BASE_NONSTRICT_P (x))); | |
5844 | } | |
5845 | ||
5846 | /* Return nozero if X is a legitimate address. On the H8/300, a | |
5847 | legitimate address has the form REG, REG+CONSTANT_ADDRESS or | |
5848 | CONSTANT_ADDRESS. */ | |
5849 | ||
c6c3dba9 PB |
5850 | static bool |
5851 | h8300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) | |
d0022200 KH |
5852 | { |
5853 | /* The register indirect addresses like @er0 is always valid. */ | |
5854 | if (h8300_rtx_ok_for_base_p (x, strict)) | |
5855 | return 1; | |
5856 | ||
5857 | if (CONSTANT_ADDRESS_P (x)) | |
5858 | return 1; | |
5859 | ||
beed8fc0 AO |
5860 | if (TARGET_H8300SX |
5861 | && ( GET_CODE (x) == PRE_INC | |
5862 | || GET_CODE (x) == PRE_DEC | |
5863 | || GET_CODE (x) == POST_INC | |
5864 | || GET_CODE (x) == POST_DEC) | |
5865 | && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict)) | |
5866 | return 1; | |
5867 | ||
d0022200 KH |
5868 | if (GET_CODE (x) == PLUS |
5869 | && CONSTANT_ADDRESS_P (XEXP (x, 1)) | |
beed8fc0 AO |
5870 | && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0), |
5871 | mode, 0), strict)) | |
d0022200 KH |
5872 | return 1; |
5873 | ||
5874 | return 0; | |
5875 | } | |
07ee3b58 KH |
5876 | |
5877 | /* Worker function for HARD_REGNO_NREGS. | |
5878 | ||
5879 | We pretend the MAC register is 32bits -- we don't have any data | |
5880 | types on the H8 series to handle more than 32bits. */ | |
5881 | ||
5882 | int | |
5883 | h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, enum machine_mode mode) | |
5884 | { | |
5885 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
5886 | } | |
5887 | ||
5888 | /* Worker function for HARD_REGNO_MODE_OK. */ | |
5889 | ||
5890 | int | |
5891 | h8300_hard_regno_mode_ok (int regno, enum machine_mode mode) | |
5892 | { | |
5893 | if (TARGET_H8300) | |
5894 | /* If an even reg, then anything goes. Otherwise the mode must be | |
5895 | QI or HI. */ | |
5896 | return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode); | |
5897 | else | |
5898 | /* MAC register can only be of SImode. Otherwise, anything | |
5899 | goes. */ | |
5900 | return regno == MAC_REG ? mode == SImode : 1; | |
5901 | } | |
f9b4f8c1 RH |
5902 | |
5903 | /* Helper function for the move patterns. Make sure a move is legitimate. */ | |
5904 | ||
5905 | bool | |
5906 | h8300_move_ok (rtx dest, rtx src) | |
5907 | { | |
5908 | rtx addr, other; | |
5909 | ||
5910 | /* Validate that at least one operand is a register. */ | |
5911 | if (MEM_P (dest)) | |
5912 | { | |
5913 | if (MEM_P (src) || CONSTANT_P (src)) | |
5914 | return false; | |
5915 | addr = XEXP (dest, 0); | |
5916 | other = src; | |
5917 | } | |
5918 | else if (MEM_P (src)) | |
5919 | { | |
5920 | addr = XEXP (src, 0); | |
5921 | other = dest; | |
5922 | } | |
5923 | else | |
5924 | return true; | |
5925 | ||
5926 | /* Validate that auto-inc doesn't affect OTHER. */ | |
5927 | if (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC) | |
5928 | return true; | |
5929 | addr = XEXP (addr, 0); | |
5930 | ||
5931 | if (addr == stack_pointer_rtx) | |
5932 | return register_no_sp_elim_operand (other, VOIDmode); | |
5933 | else | |
5934 | return !reg_overlap_mentioned_p(other, addr); | |
5935 | } | |
6e014ef3 | 5936 | \f |
c15c90bb ZW |
5937 | /* Perform target dependent optabs initialization. */ |
5938 | static void | |
5939 | h8300_init_libfuncs (void) | |
5940 | { | |
5941 | set_optab_libfunc (smul_optab, HImode, "__mulhi3"); | |
5942 | set_optab_libfunc (sdiv_optab, HImode, "__divhi3"); | |
5943 | set_optab_libfunc (udiv_optab, HImode, "__udivhi3"); | |
5944 | set_optab_libfunc (smod_optab, HImode, "__modhi3"); | |
5945 | set_optab_libfunc (umod_optab, HImode, "__umodhi3"); | |
5946 | } | |
5947 | \f | |
9eaa7740 AS |
5948 | /* Worker function for TARGET_FUNCTION_VALUE. |
5949 | ||
5950 | On the H8 the return value is in R0/R1. */ | |
5951 | ||
5952 | static rtx | |
5953 | h8300_function_value (const_tree ret_type, | |
5954 | const_tree fn_decl_or_type ATTRIBUTE_UNUSED, | |
5955 | bool outgoing ATTRIBUTE_UNUSED) | |
5956 | { | |
5957 | return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG); | |
5958 | } | |
5959 | ||
5960 | /* Worker function for TARGET_LIBCALL_VALUE. | |
5961 | ||
5962 | On the H8 the return value is in R0/R1. */ | |
5963 | ||
5964 | static rtx | |
5965 | h8300_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) | |
5966 | { | |
5967 | return gen_rtx_REG (mode, R0_REG); | |
5968 | } | |
5969 | ||
5970 | /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P. | |
5971 | ||
5972 | On the H8, R0 is the only register thus used. */ | |
5973 | ||
5974 | static bool | |
5975 | h8300_function_value_regno_p (const unsigned int regno) | |
5976 | { | |
5977 | return (regno == R0_REG); | |
5978 | } | |
5979 | ||
e9eba255 KH |
5980 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
5981 | ||
34bf1fe3 | 5982 | static bool |
586de218 | 5983 | h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
34bf1fe3 KH |
5984 | { |
5985 | return (TYPE_MODE (type) == BLKmode | |
5986 | || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8)); | |
5987 | } | |
5988 | \f | |
9f6ef043 RH |
5989 | /* We emit the entire trampoline here. Depending on the pointer size, |
5990 | we use a different trampoline. | |
5991 | ||
5992 | Pmode == HImode | |
5993 | vvvv context | |
5994 | 1 0000 7903xxxx mov.w #0x1234,r3 | |
5995 | 2 0004 5A00xxxx jmp @0x1234 | |
5996 | ^^^^ function | |
5997 | ||
5998 | Pmode == SImode | |
5999 | vvvvvvvv context | |
6000 | 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3 | |
6001 | 3 0006 5Axxxxxx jmp @0x123456 | |
6002 | ^^^^^^ function | |
6003 | */ | |
6004 | ||
6005 | static void | |
6006 | h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt) | |
6007 | { | |
6008 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
6009 | rtx mem; | |
6010 | ||
6011 | if (Pmode == HImode) | |
6012 | { | |
6013 | mem = adjust_address (m_tramp, HImode, 0); | |
6014 | emit_move_insn (mem, GEN_INT (0x7903)); | |
6015 | mem = adjust_address (m_tramp, Pmode, 2); | |
6016 | emit_move_insn (mem, cxt); | |
6017 | mem = adjust_address (m_tramp, HImode, 4); | |
6018 | emit_move_insn (mem, GEN_INT (0x5a00)); | |
6019 | mem = adjust_address (m_tramp, Pmode, 6); | |
6020 | emit_move_insn (mem, fnaddr); | |
6021 | } | |
6022 | else | |
6023 | { | |
6024 | rtx tem; | |
6025 | ||
6026 | mem = adjust_address (m_tramp, HImode, 0); | |
6027 | emit_move_insn (mem, GEN_INT (0x7a03)); | |
6028 | mem = adjust_address (m_tramp, Pmode, 2); | |
6029 | emit_move_insn (mem, cxt); | |
6030 | ||
6031 | tem = copy_to_reg (fnaddr); | |
6032 | emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff))); | |
6033 | emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000))); | |
6034 | mem = adjust_address (m_tramp, SImode, 6); | |
6035 | emit_move_insn (mem, tem); | |
6036 | } | |
6037 | } | |
6038 | \f | |
6e014ef3 KH |
6039 | /* Initialize the GCC target structure. */ |
6040 | #undef TARGET_ATTRIBUTE_TABLE | |
6041 | #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table | |
6042 | ||
6043 | #undef TARGET_ASM_ALIGNED_HI_OP | |
6044 | #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
6045 | ||
1bc7c5b6 ZW |
6046 | #undef TARGET_ASM_FILE_START |
6047 | #define TARGET_ASM_FILE_START h8300_file_start | |
6048 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
6049 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
6050 | ||
6e014ef3 KH |
6051 | #undef TARGET_ASM_FILE_END |
6052 | #define TARGET_ASM_FILE_END h8300_file_end | |
6053 | ||
88cb339e N |
6054 | #undef TARGET_PRINT_OPERAND |
6055 | #define TARGET_PRINT_OPERAND h8300_print_operand | |
6056 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
6057 | #define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address | |
6058 | #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P | |
6059 | #define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p | |
6060 | ||
6e014ef3 KH |
6061 | #undef TARGET_ENCODE_SECTION_INFO |
6062 | #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info | |
6063 | ||
6064 | #undef TARGET_INSERT_ATTRIBUTES | |
6065 | #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes | |
6066 | ||
88cb339e N |
6067 | #undef TARGET_REGISTER_MOVE_COST |
6068 | #define TARGET_REGISTER_MOVE_COST h8300_register_move_cost | |
6069 | ||
6e014ef3 KH |
6070 | #undef TARGET_RTX_COSTS |
6071 | #define TARGET_RTX_COSTS h8300_rtx_costs | |
6072 | ||
c15c90bb ZW |
6073 | #undef TARGET_INIT_LIBFUNCS |
6074 | #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs | |
6075 | ||
9eaa7740 AS |
6076 | #undef TARGET_FUNCTION_VALUE |
6077 | #define TARGET_FUNCTION_VALUE h8300_function_value | |
6078 | ||
6079 | #undef TARGET_LIBCALL_VALUE | |
6080 | #define TARGET_LIBCALL_VALUE h8300_libcall_value | |
6081 | ||
6082 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
6083 | #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p | |
6084 | ||
34bf1fe3 KH |
6085 | #undef TARGET_RETURN_IN_MEMORY |
6086 | #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory | |
6087 | ||
56f9413b NF |
6088 | #undef TARGET_FUNCTION_ARG |
6089 | #define TARGET_FUNCTION_ARG h8300_function_arg | |
6090 | ||
6091 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
6092 | #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance | |
6093 | ||
beed8fc0 AO |
6094 | #undef TARGET_MACHINE_DEPENDENT_REORG |
6095 | #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg | |
6096 | ||
2e762884 DD |
6097 | #undef TARGET_HARD_REGNO_SCRATCH_OK |
6098 | #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok | |
6099 | ||
c6c3dba9 PB |
6100 | #undef TARGET_LEGITIMATE_ADDRESS_P |
6101 | #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p | |
6102 | ||
7b5cbb57 AS |
6103 | #undef TARGET_CAN_ELIMINATE |
6104 | #define TARGET_CAN_ELIMINATE h8300_can_eliminate | |
6105 | ||
5efd84c5 NF |
6106 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
6107 | #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage | |
6108 | ||
9f6ef043 RH |
6109 | #undef TARGET_TRAMPOLINE_INIT |
6110 | #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init | |
6111 | ||
c5387660 JM |
6112 | #undef TARGET_OPTION_OVERRIDE |
6113 | #define TARGET_OPTION_OVERRIDE h8300_option_override | |
6114 | ||
f52d97da AS |
6115 | #undef TARGET_MODE_DEPENDENT_ADDRESS_P |
6116 | #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p | |
6117 | ||
6e014ef3 | 6118 | struct gcc_target targetm = TARGET_INITIALIZER; |