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Factor unrelated declarations out of tree.h.
[thirdparty/gcc.git] / gcc / config / h8300 / h8300.c
CommitLineData
340f6494 1/* Subroutines for insn-output.c for Renesas H8/300.
d1e082c2 2 Copyright (C) 1992-2013 Free Software Foundation, Inc.
48837e29
DE		 3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
07aae5c2 5
8aa063fb 6This file is part of GCC.
07aae5c2 7
8aa063fb 8GCC is free software; you can redistribute it and/or modify
07aae5c2 9it under the terms of the GNU General Public License as published by
2f83c7d6 10the Free Software Foundation; either version 3, or (at your option)
07aae5c2
SC		 11any later version.
12
8aa063fb 13GCC is distributed in the hope that it will be useful,
07aae5c2
SC		 14but WITHOUT ANY WARRANTY; without even the implied warranty of
15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
2f83c7d6
NC		 19along with GCC; see the file COPYING3. If not see
20<http://www.gnu.org/licenses/>. */
07aae5c2 21
07aae5c2 22#include "config.h"
c5c76735 23#include "system.h"
4977bab6
ZW		 24#include "coretypes.h"
25#include "tm.h"
07aae5c2 26#include "rtl.h"
bf6bb899 27#include "tree.h"
d8a2d370
DN		 28#include "stor-layout.h"
29#include "varasm.h"
30#include "calls.h"
31#include "stringpool.h"
07aae5c2
SC		 32#include "regs.h"
33#include "hard-reg-set.h"
07aae5c2
SC		 34#include "insn-config.h"
35#include "conditions.h"
07aae5c2
SC		 36#include "output.h"
37#include "insn-attr.h"
38#include "flags.h"
39#include "recog.h"
40#include "expr.h"
bf6bb899 41#include "function.h"
c15c90bb 42#include "optabs.h"
718f9c0f 43#include "diagnostic-core.h"
39dabefd 44#include "c-family/c-pragma.h" /* ??? */
441d04c6 45#include "tm_p.h"
ceaaaeab 46#include "tm-constrs.h"
f2a9645f 47#include "ggc.h"
672a6f42
NB		 48#include "target.h"
49#include "target-def.h"
9690aa8e 50#include "df.h"
07aae5c2 51
beed8fc0
AO		 52/* Classifies a h8300_src_operand or h8300_dst_operand.
53
54 H8OP_IMMEDIATE
55 A constant operand of some sort.
56
57 H8OP_REGISTER
58 An ordinary register.
59
60 H8OP_MEM_ABSOLUTE
61 A memory reference with a constant address.
62
63 H8OP_MEM_BASE
64 A memory reference with a register as its address.
65
66 H8OP_MEM_COMPLEX
67 Some other kind of memory reference. */
68enum h8300_operand_class
69{
70 H8OP_IMMEDIATE,
71 H8OP_REGISTER,
72 H8OP_MEM_ABSOLUTE,
73 H8OP_MEM_BASE,
74 H8OP_MEM_COMPLEX,
75 NUM_H8OPS
76};
77
beed8fc0
AO		 78/* For a general two-operand instruction, element [X][Y] gives
79 the length of the opcode fields when the first operand has class
80 (X + 1) and the second has class Y. */
81typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
82
07aae5c2 83/* Forward declarations. */
cb713a8d
KH		 84static const char *byte_reg (rtx, int);
85static int h8300_interrupt_function_p (tree);
3cfa3702 86static int h8300_saveall_function_p (tree);
cb713a8d
KH		 87static int h8300_monitor_function_p (tree);
88static int h8300_os_task_function_p (tree);
c72ea086 89static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool);
e68d4dd1 90static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
cb713a8d 91static unsigned int compute_saved_regs (void);
cb713a8d
KH		 92static const char *cond_string (enum rtx_code);
93static unsigned int h8300_asm_insn_count (const char *);
cb713a8d
KH		 94static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
95static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
96static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
88cb339e
N		 97static void h8300_print_operand_address (FILE *, rtx);
98static void h8300_print_operand (FILE *, rtx, int);
99static bool h8300_print_operand_punct_valid_p (unsigned char code);
ede75ee8 100#ifndef OBJECT_FORMAT_ELF
c18a5b6c 101static void h8300_asm_named_section (const char *, unsigned int, tree);
ede75ee8 102#endif
88cb339e 103static int h8300_register_move_cost (enum machine_mode, reg_class_t, reg_class_t);
cb713a8d
KH		 104static int h8300_and_costs (rtx);
105static int h8300_shift_costs (rtx);
ac447f25 106static void h8300_push_pop (int, int, bool, bool);
beed8fc0
AO		 107static int h8300_stack_offset_p (rtx, int);
108static int h8300_ldm_stm_regno (rtx, int, int, int);
beed8fc0
AO		 109static void h8300_reorg (void);
110static unsigned int h8300_constant_length (rtx);
111static unsigned int h8300_displacement_length (rtx, int);
112static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *);
113static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *);
114static unsigned int h8300_unary_length (rtx);
115static unsigned int h8300_short_immediate_length (rtx);
116static unsigned int h8300_bitfield_length (rtx, rtx);
117static unsigned int h8300_binary_length (rtx, const h8300_length_table *);
118static bool h8300_short_move_mem_p (rtx, enum rtx_code);
119static unsigned int h8300_move_length (rtx *, const h8300_length_table *);
2e762884 120static bool h8300_hard_regno_scratch_ok (unsigned int);
f52d97da 121static rtx h8300_get_index (rtx, enum machine_mode mode, int *);
f5b65a56 122
48837e29
DE		 123/* CPU_TYPE, says what cpu we're compiling for. */
124int cpu_type;
125
e392d367
KH		 126/* True if a #pragma interrupt has been seen for the current function. */
127static int pragma_interrupt;
07aae5c2
SC		 128
129/* True if a #pragma saveall has been seen for the current function. */
0869f126 130static int pragma_saveall;
07aae5c2 131
441d04c6 132static const char *const names_big[] =
07e4d94e 133{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
48837e29 134
441d04c6 135static const char *const names_extended[] =
07e4d94e 136{ "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
48837e29 137
441d04c6 138static const char *const names_upper_extended[] =
07e4d94e 139{ "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
48837e29
DE		 140
141/* Points to one of the above. */
142/* ??? The above could be put in an array indexed by CPU_TYPE. */
441d04c6 143const char * const *h8_reg_names;
48837e29
DE		 144
145/* Various operations needed by the following, indexed by CPU_TYPE. */
48837e29 146
441d04c6 147const char *h8_push_op, *h8_pop_op, *h8_mov_op;
dc66a1c4 148
beed8fc0
AO		 149/* Value of MOVE_RATIO. */
150int h8300_move_ratio;
672a6f42 151\f
c4dfc70c
DD		 152/* See below where shifts are handled for explanation of this enum. */
153
154enum shift_alg
155{
156 SHIFT_INLINE,
157 SHIFT_ROT_AND,
158 SHIFT_SPECIAL,
159 SHIFT_LOOP
160};
161
162/* Symbols of the various shifts which can be used as indices. */
163
164enum shift_type
165{
166 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
167};
168
169/* Macros to keep the shift algorithm tables small. */
170#define INL SHIFT_INLINE
171#define ROT SHIFT_ROT_AND
172#define LOP SHIFT_LOOP
173#define SPC SHIFT_SPECIAL
174
175/* The shift algorithms for each machine, mode, shift type, and shift
176 count are defined below. The three tables below correspond to
177 QImode, HImode, and SImode, respectively. Each table is organized
f411c849 178 by, in the order of indices, machine, shift type, and shift count. */
c4dfc70c
DD		 179
180static enum shift_alg shift_alg_qi[3][3][8] = {
181 {
182 /* TARGET_H8300 */
183 /* 0 1 2 3 4 5 6 7 */
184 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
185 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
186 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
187 },
188 {
189 /* TARGET_H8300H */
190 /* 0 1 2 3 4 5 6 7 */
191 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
192 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
193 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
194 },
195 {
196 /* TARGET_H8300S */
197 /* 0 1 2 3 4 5 6 7 */
198 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
199 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
200 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
201 }
202};
203
204static enum shift_alg shift_alg_hi[3][3][16] = {
205 {
206 /* TARGET_H8300 */
207 /* 0 1 2 3 4 5 6 7 */
208 /* 8 9 10 11 12 13 14 15 */
209 { INL, INL, INL, INL, INL, INL, INL, SPC,
210 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
211 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
212 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
213 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
214 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
215 },
216 {
217 /* TARGET_H8300H */
218 /* 0 1 2 3 4 5 6 7 */
219 /* 8 9 10 11 12 13 14 15 */
220 { INL, INL, INL, INL, INL, INL, INL, SPC,
221 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
222 { INL, INL, INL, INL, INL, INL, INL, SPC,
223 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
224 { INL, INL, INL, INL, INL, INL, INL, SPC,
225 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
226 },
227 {
228 /* TARGET_H8300S */
229 /* 0 1 2 3 4 5 6 7 */
230 /* 8 9 10 11 12 13 14 15 */
231 { INL, INL, INL, INL, INL, INL, INL, INL,
232 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
233 { INL, INL, INL, INL, INL, INL, INL, INL,
234 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
235 { INL, INL, INL, INL, INL, INL, INL, INL,
236 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
237 }
238};
239
240static enum shift_alg shift_alg_si[3][3][32] = {
241 {
242 /* TARGET_H8300 */
243 /* 0 1 2 3 4 5 6 7 */
244 /* 8 9 10 11 12 13 14 15 */
245 /* 16 17 18 19 20 21 22 23 */
246 /* 24 25 26 27 28 29 30 31 */
247 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
248 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
249 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
250 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
251 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
252 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
253 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
254 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
255 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
256 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
257 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
258 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
259 },
260 {
261 /* TARGET_H8300H */
262 /* 0 1 2 3 4 5 6 7 */
263 /* 8 9 10 11 12 13 14 15 */
264 /* 16 17 18 19 20 21 22 23 */
265 /* 24 25 26 27 28 29 30 31 */
266 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
267 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
268 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
1e5bdc40 269 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
c4dfc70c
DD		 270 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
271 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
272 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
1e5bdc40 273 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
c4dfc70c
DD		 274 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
275 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
276 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
277 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
278 },
279 {
280 /* TARGET_H8300S */
281 /* 0 1 2 3 4 5 6 7 */
282 /* 8 9 10 11 12 13 14 15 */
283 /* 16 17 18 19 20 21 22 23 */
284 /* 24 25 26 27 28 29 30 31 */
285 { INL, INL, INL, INL, INL, INL, INL, INL,
286 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
287 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
1e5bdc40 288 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
c4dfc70c
DD		 289 { INL, INL, INL, INL, INL, INL, INL, INL,
290 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
291 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
1e5bdc40 292 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
c4dfc70c
DD		 293 { INL, INL, INL, INL, INL, INL, INL, INL,
294 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
295 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
296 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
297 }
298};
299
300#undef INL
301#undef ROT
302#undef LOP
303#undef SPC
304
305enum h8_cpu
306{
307 H8_300,
308 H8_300H,
309 H8_S
310};
311
48837e29
DE		 312/* Initialize various cpu specific globals at start up. */
313
c5387660
JM		 314static void
315h8300_option_override (void)
48837e29 316{
cbf1b2da
KH		 317 static const char *const h8_push_ops[2] = { "push" , "push.l" };
318 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
319 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
320
f4ea8112
SKS		 321#ifndef OBJECT_FORMAT_ELF
322 if (TARGET_H8300SX)
323 {
324 error ("-msx is not supported in coff");
325 target_flags |= MASK_H8300S;
326 }
327#endif
328
48837e29
DE		 329 if (TARGET_H8300)
330 {
331 cpu_type = (int) CPU_H8300;
332 h8_reg_names = names_big;
333 }
334 else
335 {
3db11b5c 336 /* For this we treat the H8/300H and H8S the same. */
48837e29
DE		 337 cpu_type = (int) CPU_H8300H;
338 h8_reg_names = names_extended;
339 }
340 h8_push_op = h8_push_ops[cpu_type];
341 h8_pop_op = h8_pop_ops[cpu_type];
342 h8_mov_op = h8_mov_ops[cpu_type];
17f0f8fa
KH		 343
344 if (!TARGET_H8300S && TARGET_MAC)
400500c4 345 {
c725bd79 346 error ("-ms2600 is used without -ms");
5463c726 347 target_flags |= MASK_H8300S_1;
400500c4 348 }
920e86b8 349
39ba95b5
VK		 350 if (TARGET_H8300 && TARGET_NORMAL_MODE)
351 {
f4ea8112 352 error ("-mn is used without -mh or -ms or -msx");
39ba95b5
VK		 353 target_flags ^= MASK_NORMAL_MODE;
354 }
c4dfc70c 355
f4ea8112
SKS		 356 if (! TARGET_H8300S && TARGET_EXR)
357 {
358 error ("-mexr is used without -ms");
359 target_flags |= MASK_H8300S_1;
360 }
361
362 if (TARGET_H8300 && TARGET_INT32)
363 {
364 error ("-mint32 is not supported for H8300 and H8300L targets");
365 target_flags ^= MASK_INT32;
366 }
367
368 if ((!TARGET_H8300S && TARGET_EXR) && (!TARGET_H8300SX && TARGET_EXR))
369 {
370 error ("-mexr is used without -ms or -msx");
371 target_flags |= MASK_H8300S_1;
372 }
373
374 if ((!TARGET_H8300S && TARGET_NEXR) && (!TARGET_H8300SX && TARGET_NEXR))
375 {
376 warning (OPT_mno_exr, "-mno-exr valid only with -ms or -msx \
377 - Option ignored!");
378 }
379
8bd06267 380 /* Some of the shifts are optimized for speed by default.
c4dfc70c 381 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
8bd06267 382 If optimizing for size, change shift_alg for those shift to
c4dfc70c 383 SHIFT_LOOP. */
b6894857 384 if (optimize_size)
c4dfc70c 385 {
b6894857
KH		 386 /* H8/300 */
387 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
388 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
389 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
390 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
c4dfc70c 391
b6894857
KH		 392 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
393 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
c4dfc70c 394
b6894857
KH		 395 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
396 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
c4dfc70c 397
b6894857
KH		 398 /* H8/300H */
399 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
400 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
c4dfc70c 401
b6894857
KH		 402 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
403 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
c4dfc70c 404
b6894857
KH		 405 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
406 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
407 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
408 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
c4dfc70c
DD		 409
410 /* H8S */
b6894857 411 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
c4dfc70c 412 }
beed8fc0
AO		 413
414 /* Work out a value for MOVE_RATIO. */
415 if (!TARGET_H8300SX)
416 {
417 /* Memory-memory moves are quite expensive without the
418 h8sx instructions. */
419 h8300_move_ratio = 3;
420 }
421 else if (flag_omit_frame_pointer)
422 {
423 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
424 sometimes be as short as two individual memory-to-memory moves,
425 but since they use all the call-saved registers, it seems better
426 to allow up to three moves here. */
427 h8300_move_ratio = 4;
428 }
429 else if (optimize_size)
430 {
431 /* In this case we don't use movmd sequences since they tend
432 to be longer than calls to memcpy(). Memory-to-memory
433 moves are cheaper than for !TARGET_H8300SX, so it makes
434 sense to have a slightly higher threshold. */
435 h8300_move_ratio = 4;
436 }
437 else
438 {
439 /* We use movmd sequences for some moves since it can be quicker
440 than calling memcpy(). The sequences will need to save and
441 restore er6 though, so bump up the cost. */
442 h8300_move_ratio = 6;
443 }
0685e770
DD		 444
445 /* This target defaults to strict volatile bitfields. */
36acc1a2 446 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
0685e770 447 flag_strict_volatile_bitfields = 1;
beed8fc0
AO		 448}
449
e9eba255
KH		 450/* Return the byte register name for a register rtx X. B should be 0
451 if you want a lower byte register. B should be 1 if you want an
452 upper byte register. */
453
9c188705 454static const char *
cb713a8d 455byte_reg (rtx x, int b)
07aae5c2 456{
9cbcd983
KH		 457 static const char *const names_small[] = {
458 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
459 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
460 };
07aae5c2 461
8c440872 462 gcc_assert (REG_P (x));
500fc80f 463
07aae5c2
SC		 464 return names_small[REGNO (x) * 2 + b];
465}
466
467/* REGNO must be saved/restored across calls if this macro is true. */
48837e29 468
9cbcd983 469#define WORD_REG_USED(regno) \
d60004ee 470 (regno < SP_REG \
9cbcd983
KH		 471 /* No need to save registers if this function will not return. */ \
472 && ! TREE_THIS_VOLATILE (current_function_decl) \
3cfa3702 473 && (h8300_saveall_function_p (current_function_decl) \
9cbcd983 474 /* Save any call saved register that was used. */ \
6fb5fa3c 475 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
9cbcd983 476 /* Save the frame pointer if it was used. */ \
6fb5fa3c 477 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
9cbcd983 478 /* Save any register used in an interrupt handler. */ \
e392d367 479 || (h8300_current_function_interrupt_function_p () \
6fb5fa3c 480 && df_regs_ever_live_p (regno)) \
9cbcd983
KH		 481 /* Save call clobbered registers in non-leaf interrupt \
482 handlers. */ \
e392d367 483 || (h8300_current_function_interrupt_function_p () \
9cbcd983 484 && call_used_regs[regno] \
416ff32e 485 && !crtl->is_leaf)))
07aae5c2 486
18674659
DD		 487/* We use this to wrap all emitted insns in the prologue. */
488static rtx
c72ea086 489F (rtx x, bool set_it)
18674659 490{
c72ea086
DD		 491 if (set_it)
492 RTX_FRAME_RELATED_P (x) = 1;
18674659
DD		 493 return x;
494}
495
496/* Mark all the subexpressions of the PARALLEL rtx PAR as
497 frame-related. Return PAR.
498
499 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
500 PARALLEL rtx other than the first if they do not have the
501 FRAME_RELATED flag set on them. */
502static rtx
503Fpa (rtx par)
504{
505 int len = XVECLEN (par, 0);
506 int i;
507
508 for (i = 0; i < len; i++)
c72ea086 509 F (XVECEXP (par, 0, i), true);
18674659
DD		 510
511 return par;
512}
513
07aae5c2 514/* Output assembly language to FILE for the operation OP with operand size
48837e29 515 SIZE to adjust the stack pointer. */
48837e29 516
07aae5c2 517static void
c72ea086 518h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue)
07aae5c2 519{
72b1de44
KH		 520 /* If the frame size is 0, we don't have anything to do. */
521 if (size == 0)
f8b58e56 522 return;
72b1de44 523
68ee6df6
KH		 524 /* H8/300 cannot add/subtract a large constant with a single
525 instruction. If a temporary register is available, load the
526 constant to it and then do the addition. */
527 if (TARGET_H8300
528 && size > 4
529 && !h8300_current_function_interrupt_function_p ()
6de9cd9a 530 && !(cfun->static_chain_decl != NULL && sign < 0))
f8f26adc 531 {
68ee6df6 532 rtx r3 = gen_rtx_REG (Pmode, 3);
c72ea086 533 F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue);
18674659 534 F (emit_insn (gen_addhi3 (stack_pointer_rtx,
c72ea086 535 stack_pointer_rtx, r3)), in_prologue);
7b3d4613
KH		 536 }
537 else
538 {
68ee6df6
KH		 539 /* The stack adjustment made here is further optimized by the
540 splitter. In case of H8/300, the splitter always splits the
18674659
DD		 541 addition emitted here to make the adjustment interrupt-safe.
542 FIXME: We don't always tag those, because we don't know what
543 the splitter will do. */
72b1de44 544 if (Pmode == HImode)
18674659
DD		 545 {
546 rtx x = emit_insn (gen_addhi3 (stack_pointer_rtx,
547 stack_pointer_rtx, GEN_INT (sign * size)));
548 if (size < 4)
c72ea086 549 F (x, in_prologue);
18674659 550 }
72b1de44 551 else
18674659 552 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
c72ea086 553 stack_pointer_rtx, GEN_INT (sign * size))), in_prologue);
07aae5c2
SC		 554 }
555}
556
8682223f
KH		 557/* Round up frame size SIZE. */
558
e68d4dd1
UB		 559static HOST_WIDE_INT
560round_frame_size (HOST_WIDE_INT size)
8682223f 561{
489eda65
KH		 562 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
563 & -STACK_BOUNDARY / BITS_PER_UNIT);
8682223f
KH		 564}
565
566/* Compute which registers to push/pop.
567 Return a bit vector of registers. */
568
569static unsigned int
cb713a8d 570compute_saved_regs (void)
8682223f
KH		 571{
572 unsigned int saved_regs = 0;
573 int regno;
574
575 /* Construct a bit vector of registers to be pushed/popped. */
1807b726 576 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
8682223f
KH		 577 {
578 if (WORD_REG_USED (regno))
579 saved_regs |= 1 << regno;
580 }
581
582 /* Don't push/pop the frame pointer as it is treated separately. */
583 if (frame_pointer_needed)
1807b726 584 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
8682223f
KH		 585
586 return saved_regs;
587}
588
68ee6df6 589/* Emit an insn to push register RN. */
8682223f 590
8f1594b2 591static rtx
cb713a8d 592push (int rn)
8682223f 593{
68ee6df6
KH		 594 rtx reg = gen_rtx_REG (word_mode, rn);
595 rtx x;
596
513f31eb 597 if (TARGET_H8300)
68ee6df6 598 x = gen_push_h8300 (reg);
f24f0897 599 else if (!TARGET_NORMAL_MODE)
32da7865 600 x = gen_push_h8300hs_advanced (reg);
f24f0897
KH		 601 else
602 x = gen_push_h8300hs_normal (reg);
ac447f25 603 x = F (emit_insn (x), true);
9690aa8e 604 add_reg_note (x, REG_INC, stack_pointer_rtx);
8f1594b2 605 return x;
8682223f
KH		 606}
607
68ee6df6 608/* Emit an insn to pop register RN. */
8682223f 609
8f1594b2 610static rtx
cb713a8d 611pop (int rn)
8682223f 612{
68ee6df6
KH		 613 rtx reg = gen_rtx_REG (word_mode, rn);
614 rtx x;
615
513f31eb 616 if (TARGET_H8300)
68ee6df6 617 x = gen_pop_h8300 (reg);
f24f0897 618 else if (!TARGET_NORMAL_MODE)
32da7865 619 x = gen_pop_h8300hs_advanced (reg);
f24f0897
KH		 620 else
621 x = gen_pop_h8300hs_normal (reg);
68ee6df6 622 x = emit_insn (x);
9690aa8e 623 add_reg_note (x, REG_INC, stack_pointer_rtx);
8f1594b2 624 return x;
8682223f 625}
07aae5c2 626
beed8fc0
AO		 627/* Emit an instruction to push or pop NREGS consecutive registers
628 starting at register REGNO. POP_P selects a pop rather than a
629 push and RETURN_P is true if the instruction should return.
630
631 It must be possible to do the requested operation in a single
632 instruction. If NREGS == 1 && !RETURN_P, use a normal push
633 or pop insn. Otherwise emit a parallel of the form:
634
635 (parallel
636 [(return) ;; if RETURN_P
637 (save or restore REGNO)
638 (save or restore REGNO + 1)
639 ...
640 (save or restore REGNO + NREGS - 1)
641 (set sp (plus sp (const_int adjust)))] */
642
643static void
ac447f25 644h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p)
beed8fc0
AO		 645{
646 int i, j;
647 rtvec vec;
18674659 648 rtx sp, offset, x;
beed8fc0
AO		 649
650 /* See whether we can use a simple push or pop. */
651 if (!return_p && nregs == 1)
652 {
653 if (pop_p)
654 pop (regno);
655 else
656 push (regno);
657 return;
658 }
659
660 /* We need one element for the return insn, if present, one for each
661 register, and one for stack adjustment. */
ac447f25 662 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1);
beed8fc0
AO		 663 sp = stack_pointer_rtx;
664 i = 0;
665
666 /* Add the return instruction. */
667 if (return_p)
668 {
3810076b 669 RTVEC_ELT (vec, i) = ret_rtx;
beed8fc0
AO		 670 i++;
671 }
672
673 /* Add the register moves. */
674 for (j = 0; j < nregs; j++)
675 {
676 rtx lhs, rhs;
677
678 if (pop_p)
679 {
680 /* Register REGNO + NREGS - 1 is popped first. Before the
681 stack adjustment, its slot is at address @sp. */
682 lhs = gen_rtx_REG (SImode, regno + j);
0a81f074
RS		 683 rhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp,
684 (nregs - j - 1) * 4));
beed8fc0
AO		 685 }
686 else
687 {
688 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
0a81f074 689 lhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, (j + 1) * -4));
beed8fc0
AO		 690 rhs = gen_rtx_REG (SImode, regno + j);
691 }
692 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, lhs, rhs);
693 }
694
695 /* Add the stack adjustment. */
696 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
697 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, sp,
698 gen_rtx_PLUS (Pmode, sp, offset));
699
18674659
DD		 700 x = gen_rtx_PARALLEL (VOIDmode, vec);
701 if (!pop_p)
702 x = Fpa (x);
ac447f25
NC		 703
704 if (return_p)
705 emit_jump_insn (x);
706 else
707 emit_insn (x);
beed8fc0
AO		 708}
709
710/* Return true if X has the value sp + OFFSET. */
711
712static int
713h8300_stack_offset_p (rtx x, int offset)
714{
715 if (offset == 0)
716 return x == stack_pointer_rtx;
717
718 return (GET_CODE (x) == PLUS
719 && XEXP (x, 0) == stack_pointer_rtx
720 && GET_CODE (XEXP (x, 1)) == CONST_INT
721 && INTVAL (XEXP (x, 1)) == offset);
722}
723
724/* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
725 something that may be an ldm or stm instruction. If it fits
726 the required template, return the register it loads or stores,
727 otherwise return -1.
728
729 LOAD_P is true if X should be a load, false if it should be a store.
730 NREGS is the number of registers that the whole instruction is expected
731 to load or store. INDEX is the index of the register that X should
732 load or store, relative to the lowest-numbered register. */
733
734static int
735h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
736{
737 int regindex, memindex, offset;
738
739 if (load_p)
740 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
741 else
742 memindex = 0, regindex = 1, offset = (index + 1) * -4;
743
744 if (GET_CODE (x) == SET
745 && GET_CODE (XEXP (x, regindex)) == REG
746 && GET_CODE (XEXP (x, memindex)) == MEM
747 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
748 return REGNO (XEXP (x, regindex));
749
750 return -1;
751}
752
753/* Return true if the elements of VEC starting at FIRST describe an
754 ldm or stm instruction (LOAD_P says which). */
755
981c7dce 756int
beed8fc0
AO		 757h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
758{
759 rtx last;
760 int nregs, i, regno, adjust;
761
762 /* There must be a stack adjustment, a register move, and at least one
763 other operation (a return or another register move). */
764 if (GET_NUM_ELEM (vec) < 3)
765 return false;
766
767 /* Get the range of registers to be pushed or popped. */
768 nregs = GET_NUM_ELEM (vec) - first - 1;
769 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
770
771 /* Check that the call to h8300_ldm_stm_regno succeeded and
772 that we're only dealing with GPRs. */
773 if (regno < 0 || regno + nregs > 8)
774 return false;
775
776 /* 2-register h8s instructions must start with an even-numbered register.
777 3- and 4-register instructions must start with er0 or er4. */
778 if (!TARGET_H8300SX)
779 {
780 if ((regno & 1) != 0)
781 return false;
782 if (nregs > 2 && (regno & 3) != 0)
783 return false;
784 }
785
786 /* Check the other loads or stores. */
787 for (i = 1; i < nregs; i++)
788 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
789 != regno + i)
790 return false;
791
792 /* Check the stack adjustment. */
793 last = RTVEC_ELT (vec, first + nregs);
794 adjust = (load_p ? nregs : -nregs) * 4;
795 return (GET_CODE (last) == SET
796 && SET_DEST (last) == stack_pointer_rtx
797 && h8300_stack_offset_p (SET_SRC (last), adjust));
798}
799
f0b6f9a6 800/* This is what the stack looks like after the prolog of
07aae5c2
SC		 801 a function with a frame has been set up:
802
48837e29
DE		 803 <args>
804 PC
805 FP <- fp
806 <locals>
8bd06267 807 <saved registers> <- sp
07aae5c2
SC		 808
809 This is what the stack looks like after the prolog of
810 a function which doesn't have a frame:
811
48837e29
DE		 812 <args>
813 PC
814 <locals>
8bd06267 815 <saved registers> <- sp
07aae5c2
SC		 816*/
817
68ee6df6 818/* Generate RTL code for the function prologue. */
8682223f 819
68ee6df6 820void
cb713a8d 821h8300_expand_prologue (void)
07aae5c2 822{
e651d484 823 int regno;
8682223f 824 int saved_regs;
cda4bd43 825 int n_regs;
07aae5c2 826
fabe72bb
JL		 827 /* If the current function has the OS_Task attribute set, then
828 we have a naked prologue. */
829 if (h8300_os_task_function_p (current_function_decl))
68ee6df6 830 return;
fabe72bb
JL		 831
832 if (h8300_monitor_function_p (current_function_decl))
f4ea8112
SKS		 833 /* The monitor function act as normal functions, which means it
834 can accept parameters and return values. In addition to this,
835 interrupts are masked in prologue and return with "rte" in epilogue. */
68ee6df6 836 emit_insn (gen_monitor_prologue ());
fabe72bb 837
48837e29
DE		 838 if (frame_pointer_needed)
839 {
07e4d94e 840 /* Push fp. */
1807b726 841 push (HARD_FRAME_POINTER_REGNUM);
ac447f25 842 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true);
a1616dd9 843 }
48837e29 844
8682223f
KH		 845 /* Push the rest of the registers in ascending order. */
846 saved_regs = compute_saved_regs ();
e651d484 847 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
cda4bd43 848 {
cda4bd43 849 n_regs = 1;
8682223f 850 if (saved_regs & (1 << regno))
a1616dd9
JL		 851 {
852 if (TARGET_H8300S)
853 {
cda4bd43 854 /* See how many registers we can push at the same time. */
beed8fc0 855 if ((!TARGET_H8300SX || (regno & 3) == 0)
8682223f 856 && ((saved_regs >> regno) & 0x0f) == 0x0f)
cda4bd43
KH		 857 n_regs = 4;
858
beed8fc0 859 else if ((!TARGET_H8300SX || (regno & 3) == 0)
8682223f 860 && ((saved_regs >> regno) & 0x07) == 0x07)
cda4bd43
KH		 861 n_regs = 3;
862
beed8fc0 863 else if ((!TARGET_H8300SX || (regno & 1) == 0)
8682223f 864 && ((saved_regs >> regno) & 0x03) == 0x03)
cda4bd43 865 n_regs = 2;
a1616dd9 866 }
cda4bd43 867
ac447f25 868 h8300_push_pop (regno, n_regs, false, false);
07aae5c2
SC		 869 }
870 }
1807b726
KH		 871
872 /* Leave room for locals. */
c72ea086 873 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
07aae5c2
SC		 874}
875
e9eba255
KH		 876/* Return nonzero if we can use "rts" for the function currently being
877 compiled. */
878
68ee6df6 879int
cb713a8d 880h8300_can_use_return_insn_p (void)
68ee6df6
KH		 881{
882 return (reload_completed
883 && !frame_pointer_needed
884 && get_frame_size () == 0
885 && compute_saved_regs () == 0);
886}
07aae5c2 887
68ee6df6
KH		 888/* Generate RTL code for the function epilogue. */
889
890void
cb713a8d 891h8300_expand_epilogue (void)
07aae5c2 892{
e651d484 893 int regno;
8682223f 894 int saved_regs;
cda4bd43 895 int n_regs;
beed8fc0
AO		 896 HOST_WIDE_INT frame_size;
897 bool returned_p;
07aae5c2 898
e392d367 899 if (h8300_os_task_function_p (current_function_decl))
68ee6df6
KH		 900 /* OS_Task epilogues are nearly naked -- they just have an
901 rts instruction. */
902 return;
07aae5c2 903
beed8fc0
AO		 904 frame_size = round_frame_size (get_frame_size ());
905 returned_p = false;
906
1807b726 907 /* Deallocate locals. */
c72ea086 908 h8300_emit_stack_adjustment (1, frame_size, false);
1807b726 909
8682223f
KH		 910 /* Pop the saved registers in descending order. */
911 saved_regs = compute_saved_regs ();
e651d484 912 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
cda4bd43 913 {
cda4bd43 914 n_regs = 1;
8682223f 915 if (saved_regs & (1 << regno))
07aae5c2 916 {
a1616dd9
JL		 917 if (TARGET_H8300S)
918 {
cda4bd43 919 /* See how many registers we can pop at the same time. */
beed8fc0
AO		 920 if ((TARGET_H8300SX || (regno & 3) == 3)
921 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
cda4bd43
KH		 922 n_regs = 4;
923
beed8fc0
AO		 924 else if ((TARGET_H8300SX || (regno & 3) == 2)
925 && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
cda4bd43
KH		 926 n_regs = 3;
927
beed8fc0
AO		 928 else if ((TARGET_H8300SX || (regno & 1) == 1)
929 && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
cda4bd43 930 n_regs = 2;
a1616dd9 931 }
cda4bd43 932
beed8fc0
AO		 933 /* See if this pop would be the last insn before the return.
934 If so, use rte/l or rts/l instead of pop or ldm.l. */
935 if (TARGET_H8300SX
936 && !frame_pointer_needed
937 && frame_size == 0
938 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
939 returned_p = true;
940
ac447f25 941 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p);
07aae5c2 942 }
07aae5c2 943 }
48837e29 944
07e4d94e 945 /* Pop frame pointer if we had one. */
a1616dd9 946 if (frame_pointer_needed)
beed8fc0
AO		 947 {
948 if (TARGET_H8300SX)
949 returned_p = true;
ac447f25 950 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p);
beed8fc0
AO		 951 }
952
953 if (!returned_p)
3810076b 954 emit_jump_insn (ret_rtx);
68ee6df6 955}
a1616dd9 956
e392d367
KH		 957/* Return nonzero if the current function is an interrupt
958 function. */
959
960int
cb713a8d 961h8300_current_function_interrupt_function_p (void)
e392d367 962{
f4ea8112
SKS		 963 return (h8300_interrupt_function_p (current_function_decl));
964}
965
966int
967h8300_current_function_monitor_function_p ()
968{
969 return (h8300_monitor_function_p (current_function_decl));
e392d367
KH		 970}
971
48837e29
DE		 972/* Output assembly code for the start of the file. */
973
1bc7c5b6
ZW		 974static void
975h8300_file_start (void)
48837e29 976{
1bc7c5b6 977 default_file_start ();
8bd06267 978
48837e29 979 if (TARGET_H8300H)
1bc7c5b6 980 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
beed8fc0
AO		 981 else if (TARGET_H8300SX)
982 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
a1616dd9 983 else if (TARGET_H8300S)
1bc7c5b6 984 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
48837e29
DE		 985}
986
987/* Output assembly language code for the end of file. */
988
a5fe455b 989static void
cb713a8d 990h8300_file_end (void)
48837e29 991{
a5fe455b 992 fputs ("\t.end\n", asm_out_file);
07aae5c2
SC		 993}
994\f
3cee1a78
KH		 995/* Split an add of a small constant into two adds/subs insns.
996
997 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
998 instead of adds/subs. */
009ac3d3
RH		 999
1000void
cb713a8d 1001split_adds_subs (enum machine_mode mode, rtx *operands)
3b7d443c 1002{
009ac3d3
RH		 1003 HOST_WIDE_INT val = INTVAL (operands[1]);
1004 rtx reg = operands[0];
9492393e
KH		 1005 HOST_WIDE_INT sign = 1;
1006 HOST_WIDE_INT amount;
590734b6 1007 rtx (*gen_add) (rtx, rtx, rtx);
3b7d443c 1008
9492393e
KH		 1009 /* Force VAL to be positive so that we do not have to consider the
1010 sign. */
1011 if (val < 0)
3b7d443c 1012 {
9492393e
KH		 1013 val = -val;
1014 sign = -1;
1015 }
3b7d443c 1016
3cee1a78
KH		 1017 switch (mode)
1018 {
1019 case HImode:
590734b6 1020 gen_add = gen_addhi3;
3cee1a78
KH		 1021 break;
1022
1023 case SImode:
590734b6 1024 gen_add = gen_addsi3;
3cee1a78
KH		 1025 break;
1026
1027 default:
8c440872 1028 gcc_unreachable ();
3cee1a78
KH		 1029 }
1030
9492393e
KH		 1031 /* Try different amounts in descending order. */
1032 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
1033 amount > 0;
1034 amount /= 2)
1035 {
1a63219b 1036 for (; val >= amount; val -= amount)
590734b6 1037 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
3b7d443c
JL		 1038 }
1039
9492393e 1040 return;
3b7d443c
JL		 1041}
1042
07aae5c2 1043/* Handle machine specific pragmas for compatibility with existing
48837e29 1044 compilers for the H8/300.
07aae5c2 1045
f411c849 1046 pragma saveall generates prologue/epilogue code which saves and
07aae5c2 1047 restores all the registers on function entry.
48837e29 1048
07aae5c2
SC		 1049 pragma interrupt saves and restores all registers, and exits with
1050 an rte instruction rather than an rts. A pointer to a function
1051 with this attribute may be safely used in an interrupt vector. */
48837e29 1052
8b97c5f8 1053void
cb713a8d 1054h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
07aae5c2 1055{
e392d367 1056 pragma_interrupt = 1;
8b97c5f8 1057}
05a81fe5 1058
8b97c5f8 1059void
cb713a8d 1060h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
8b97c5f8
ZW		 1061{
1062 pragma_saveall = 1;
07aae5c2 1063}
8b97c5f8 1064
64bead4c
KH		 1065/* If the next function argument with MODE and TYPE is to be passed in
1066 a register, return a reg RTX for the hard register in which to pass
1067 the argument. CUM represents the state after the last argument.
56f9413b 1068 If the argument is to be pushed, NULL_RTX is returned.
48837e29 1069
56f9413b
NF		 1070 On the H8/300 all normal args are pushed, unless -mquickcall in which
1071 case the first 3 arguments are passed in registers. */
1072
1073static rtx
d5cc9181 1074h8300_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
56f9413b 1075 const_tree type, bool named)
07aae5c2 1076{
d5cc9181
JR		 1077 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1078
0ea6f6a0
KH		 1079 static const char *const hand_list[] = {
1080 "__main",
1081 "__cmpsi2",
1082 "__divhi3",
1083 "__modhi3",
1084 "__udivhi3",
1085 "__umodhi3",
1086 "__divsi3",
1087 "__modsi3",
1088 "__udivsi3",
1089 "__umodsi3",
1090 "__mulhi3",
1091 "__mulsi3",
1092 "__reg_memcpy",
1093 "__reg_memset",
1094 "__ucmpsi2",
1095 0,
1096 };
1097
7192cbf1 1098 rtx result = NULL_RTX;
441d04c6 1099 const char *fname;
48837e29
DE		 1100 int regpass = 0;
1101
dd07092e
JL		 1102 /* Never pass unnamed arguments in registers. */
1103 if (!named)
7192cbf1 1104 return NULL_RTX;
dd07092e 1105
48837e29
DE		 1106 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1107 if (TARGET_QUICKCALL)
1108 regpass = 3;
1109
1110 /* If calling hand written assembler, use 4 regs of args. */
48837e29
DE		 1111 if (cum->libcall)
1112 {
441d04c6 1113 const char * const *p;
48837e29
DE		 1114
1115 fname = XSTR (cum->libcall, 0);
1116
1117 /* See if this libcall is one of the hand coded ones. */
48837e29
DE		 1118 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1119 ;
07aae5c2 1120
48837e29
DE		 1121 if (*p)
1122 regpass = 4;
1123 }
1124
1125 if (regpass)
1126 {
1127 int size;
1128
1129 if (mode == BLKmode)
1130 size = int_size_in_bytes (type);
1131 else
1132 size = GET_MODE_SIZE (mode);
1133
15e0e275
KH		 1134 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1135 && cum->nbytes / UNITS_PER_WORD <= 3)
1136 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
48837e29 1137 }
07aae5c2 1138
48837e29
DE		 1139 return result;
1140}
56f9413b
NF		 1141
1142/* Update the data in CUM to advance over an argument
1143 of mode MODE and data type TYPE.
1144 (TYPE is null for libcalls where that information may not be available.) */
1145
1146static void
d5cc9181 1147h8300_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
56f9413b
NF		 1148 const_tree type, bool named ATTRIBUTE_UNUSED)
1149{
d5cc9181
JR		 1150 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1151
56f9413b
NF		 1152 cum->nbytes += (mode != BLKmode
1153 ? (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD
1154 : (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD);
1155}
1156
48837e29 1157\f
88cb339e
N		 1158/* Implements TARGET_REGISTER_MOVE_COST.
1159
1160 Any SI register-to-register move may need to be reloaded,
1161 so inmplement h8300_register_move_cost to return > 2 so that reload never
1162 shortcuts. */
1163
1164static int
1165h8300_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1166 reg_class_t from, reg_class_t to)
1167{
1168 if (from == MAC_REGS || to == MAC_REG)
1169 return 6;
1170 else
1171 return 3;
1172}
1173
e9eba255
KH		 1174/* Compute the cost of an and insn. */
1175
3c50106f 1176static int
cb713a8d 1177h8300_and_costs (rtx x)
73cc75e9
KH		 1178{
1179 rtx operands[4];
1180
1181 if (GET_MODE (x) == QImode)
1182 return 1;
1183
1184 if (GET_MODE (x) != HImode
1185 && GET_MODE (x) != SImode)
1186 return 100;
1187
1188 operands[0] = NULL;
beed8fc0 1189 operands[1] = XEXP (x, 0);
73cc75e9
KH		 1190 operands[2] = XEXP (x, 1);
1191 operands[3] = x;
4f4ebda3 1192 return compute_logical_op_length (GET_MODE (x), operands) / 2;
73cc75e9
KH		 1193}
1194
e9eba255
KH		 1195/* Compute the cost of a shift insn. */
1196
3c50106f 1197static int
cb713a8d 1198h8300_shift_costs (rtx x)
ae557002
KH		 1199{
1200 rtx operands[4];
1201
1202 if (GET_MODE (x) != QImode
1203 && GET_MODE (x) != HImode
1204 && GET_MODE (x) != SImode)
1205 return 100;
1206
1207 operands[0] = NULL;
1208 operands[1] = NULL;
1209 operands[2] = XEXP (x, 1);
1210 operands[3] = x;
4f4ebda3 1211 return compute_a_shift_length (NULL, operands) / 2;
ae557002 1212}
3c50106f 1213
e9eba255
KH		 1214/* Worker function for TARGET_RTX_COSTS. */
1215
3c50106f 1216static bool
68f932c4
RS		 1217h8300_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
1218 int *total, bool speed)
3c50106f 1219{
beed8fc0
AO		 1220 if (TARGET_H8300SX && outer_code == MEM)
1221 {
1222 /* Estimate the number of execution states needed to calculate
1223 the address. */
1224 if (register_operand (x, VOIDmode)
1225 || GET_CODE (x) == POST_INC
1226 || GET_CODE (x) == POST_DEC
1227 || CONSTANT_P (x))
1228 *total = 0;
1229 else
1230 *total = COSTS_N_INSNS (1);
1231 return true;
1232 }
1233
3c50106f
RH		 1234 switch (code)
1235 {
08dca707
KH		 1236 case CONST_INT:
1237 {
1238 HOST_WIDE_INT n = INTVAL (x);
1239
beed8fc0
AO		 1240 if (TARGET_H8300SX)
1241 {
1242 /* Constant operands need the same number of processor
1243 states as register operands. Although we could try to
f40751dd 1244 use a size-based cost for !speed, the lack of
beed8fc0
AO		 1245 of a mode makes the results very unpredictable. */
1246 *total = 0;
1247 return true;
1248 }
358a11bb 1249 if (-4 <= n && n <= 4)
08dca707
KH		 1250 {
1251 switch ((int) n)
1252 {
1253 case 0:
1254 *total = 0;
1255 return true;
1256 case 1:
1257 case 2:
1258 case -1:
1259 case -2:
1260 *total = 0 + (outer_code == SET);
1261 return true;
1262 case 4:
1263 case -4:
1264 if (TARGET_H8300H || TARGET_H8300S)
1265 *total = 0 + (outer_code == SET);
1266 else
1267 *total = 1;
1268 return true;
1269 }
1270 }
1271 *total = 1;
1272 return true;
1273 }
1274
1275 case CONST:
1276 case LABEL_REF:
1277 case SYMBOL_REF:
beed8fc0
AO		 1278 if (TARGET_H8300SX)
1279 {
1280 /* See comment for CONST_INT. */
1281 *total = 0;
1282 return true;
1283 }
08dca707
KH		 1284 *total = 3;
1285 return true;
1286
1287 case CONST_DOUBLE:
1288 *total = 20;
1289 return true;
1290
f90b7a5a
PB		 1291 case COMPARE:
1292 if (XEXP (x, 1) == const0_rtx)
1293 *total = 0;
1294 return false;
1295
3c50106f 1296 case AND:
beed8fc0
AO		 1297 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
1298 || !h8300_src_operand (XEXP (x, 1), VOIDmode))
1299 return false;
3c50106f
RH		 1300 *total = COSTS_N_INSNS (h8300_and_costs (x));
1301 return true;
1302
1303 /* We say that MOD and DIV are so expensive because otherwise we'll
1304 generate some really horrible code for division of a power of two. */
1305 case MOD:
1306 case DIV:
beed8fc0
AO		 1307 case UMOD:
1308 case UDIV:
1309 if (TARGET_H8300SX)
1310 switch (GET_MODE (x))
1311 {
1312 case QImode:
1313 case HImode:
f40751dd 1314 *total = COSTS_N_INSNS (!speed ? 4 : 10);
beed8fc0
AO		 1315 return false;
1316
1317 case SImode:
f40751dd 1318 *total = COSTS_N_INSNS (!speed ? 4 : 18);
beed8fc0
AO		 1319 return false;
1320
1321 default:
1322 break;
1323 }
1324 *total = COSTS_N_INSNS (12);
3c50106f
RH		 1325 return true;
1326
1327 case MULT:
beed8fc0
AO		 1328 if (TARGET_H8300SX)
1329 switch (GET_MODE (x))
1330 {
1331 case QImode:
1332 case HImode:
1333 *total = COSTS_N_INSNS (2);
1334 return false;
1335
1336 case SImode:
1337 *total = COSTS_N_INSNS (5);
1338 return false;
1339
1340 default:
1341 break;
1342 }
1343 *total = COSTS_N_INSNS (4);
3c50106f
RH		 1344 return true;
1345
1346 case ASHIFT:
1347 case ASHIFTRT:
1348 case LSHIFTRT:
beed8fc0
AO		 1349 if (h8sx_binary_shift_operator (x, VOIDmode))
1350 {
1351 *total = COSTS_N_INSNS (2);
1352 return false;
1353 }
1354 else if (h8sx_unary_shift_operator (x, VOIDmode))
1355 {
1356 *total = COSTS_N_INSNS (1);
1357 return false;
1358 }
3c50106f
RH		 1359 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1360 return true;
1361
1362 case ROTATE:
1363 case ROTATERT:
1364 if (GET_MODE (x) == HImode)
1365 *total = 2;
1366 else
1367 *total = 8;
1368 return true;
1369
1370 default:
beed8fc0
AO		 1371 *total = COSTS_N_INSNS (1);
1372 return false;
3c50106f
RH		 1373 }
1374}
48837e29 1375\f
07aae5c2
SC		 1376/* Documentation for the machine specific operand escapes:
1377
48837e29
DE		 1378 'E' like s but negative.
1379 'F' like t but negative.
1380 'G' constant just the negative
15dc331e
JL		 1381 'R' print operand as a byte:8 address if appropriate, else fall back to
1382 'X' handling.
48837e29 1383 'S' print operand as a long word
07aae5c2 1384 'T' print operand as a word
48837e29
DE		 1385 'V' find the set bit, and print its number.
1386 'W' find the clear bit, and print its number.
1387 'X' print operand as a byte
07aae5c2 1388 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
15dc331e 1389 If this operand isn't a register, fall back to 'R' handling.
48837e29 1390 'Z' print int & 7.
b059c02a 1391 'c' print the opcode corresponding to rtl
da55315a 1392 'e' first word of 32-bit value - if reg, then least reg. if mem
48837e29 1393 then least. if const then most sig word
da55315a 1394 'f' second word of 32-bit value - if reg, then biggest reg. if mem
48837e29 1395 then +2. if const then least sig word
07aae5c2
SC		 1396 'j' print operand as condition code.
1397 'k' print operand as reverse condition code.
beed8fc0
AO		 1398 'm' convert an integer operand to a size suffix (.b, .w or .l)
1399 'o' print an integer without a leading '#'
da55315a
KH		 1400 's' print as low byte of 16-bit value
1401 't' print as high byte of 16-bit value
1402 'w' print as low byte of 32-bit value
1403 'x' print as 2nd byte of 32-bit value
1404 'y' print as 3rd byte of 32-bit value
1405 'z' print as msb of 32-bit value
48837e29 1406*/
07aae5c2
SC		 1407
1408/* Return assembly language string which identifies a comparison type. */
1409
441d04c6 1410static const char *
cb713a8d 1411cond_string (enum rtx_code code)
07aae5c2
SC		 1412{
1413 switch (code)
1414 {
1415 case NE:
1416 return "ne";
1417 case EQ:
1418 return "eq";
1419 case GE:
1420 return "ge";
1421 case GT:
1422 return "gt";
1423 case LE:
1424 return "le";
1425 case LT:
1426 return "lt";
1427 case GEU:
1428 return "hs";
1429 case GTU:
1430 return "hi";
1431 case LEU:
1432 return "ls";
1433 case LTU:
1434 return "lo";
1435 default:
8c440872 1436 gcc_unreachable ();
07aae5c2
SC		 1437 }
1438}
1439
1440/* Print operand X using operand code CODE to assembly language output file
1441 FILE. */
1442
88cb339e
N		 1443static void
1444h8300_print_operand (FILE *file, rtx x, int code)
07aae5c2 1445{
269c14e1 1446 /* This is used for communication between codes V,W,Z and Y. */
07aae5c2
SC		 1447 static int bitint;
1448
1449 switch (code)
1450 {
f46b8378
SKS		 1451 case 'C':
1452 if (h8300_constant_length (x) == 2)
1453 fprintf (file, ":16");
1454 else
1455 fprintf (file, ":32");
1456 return;
48837e29
DE		 1457 case 'E':
1458 switch (GET_CODE (x))
1459 {
1460 case REG:
1461 fprintf (file, "%sl", names_big[REGNO (x)]);
1462 break;
1463 case CONST_INT:
b47900aa 1464 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
48837e29
DE		 1465 break;
1466 default:
8c440872 1467 gcc_unreachable ();
48837e29
DE		 1468 }
1469 break;
1470 case 'F':
1471 switch (GET_CODE (x))
1472 {
1473 case REG:
1474 fprintf (file, "%sh", names_big[REGNO (x)]);
1475 break;
1476 case CONST_INT:
b47900aa 1477 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
48837e29
DE		 1478 break;
1479 default:
8c440872 1480 gcc_unreachable ();
48837e29
DE		 1481 }
1482 break;
07aae5c2 1483 case 'G':
8c440872 1484 gcc_assert (GET_CODE (x) == CONST_INT);
b47900aa 1485 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
07aae5c2 1486 break;
48837e29
DE		 1487 case 'S':
1488 if (GET_CODE (x) == REG)
1489 fprintf (file, "%s", names_extended[REGNO (x)]);
07aae5c2 1490 else
48837e29 1491 goto def;
07aae5c2 1492 break;
48837e29
DE		 1493 case 'T':
1494 if (GET_CODE (x) == REG)
1495 fprintf (file, "%s", names_big[REGNO (x)]);
07aae5c2 1496 else
48837e29 1497 goto def;
07aae5c2 1498 break;
48837e29 1499 case 'V':
0f6b820c
KP		 1500 bitint = (INTVAL (x) & 0xffff);
1501 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1)
1502 bitint = exact_log2 (bitint & 0xff);
1503 else
1504 bitint = exact_log2 ((bitint >> 8) & 0xff);
8c440872 1505 gcc_assert (bitint >= 0);
4d4d89e2 1506 fprintf (file, "#%d", bitint);
07aae5c2 1507 break;
48837e29 1508 case 'W':
0f6b820c
KP		 1509 bitint = ((~INTVAL (x)) & 0xffff);
1510 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 )
1511 bitint = exact_log2 (bitint & 0xff);
1512 else
1513 bitint = (exact_log2 ((bitint >> 8) & 0xff));
8c440872 1514 gcc_assert (bitint >= 0);
4d4d89e2 1515 fprintf (file, "#%d", bitint);
07aae5c2 1516 break;
15dc331e 1517 case 'R':
48837e29
DE		 1518 case 'X':
1519 if (GET_CODE (x) == REG)
1520 fprintf (file, "%s", byte_reg (x, 0));
1521 else
1522 goto def;
1523 break;
1524 case 'Y':
8c440872 1525 gcc_assert (bitint >= 0);
48837e29
DE		 1526 if (GET_CODE (x) == REG)
1527 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1528 else
88cb339e 1529 h8300_print_operand (file, x, 'R');
48837e29
DE		 1530 bitint = -1;
1531 break;
1532 case 'Z':
1533 bitint = INTVAL (x);
07aae5c2
SC		 1534 fprintf (file, "#%d", bitint & 7);
1535 break;
b059c02a
KH		 1536 case 'c':
1537 switch (GET_CODE (x))
1538 {
1539 case IOR:
1540 fprintf (file, "or");
1541 break;
1542 case XOR:
1543 fprintf (file, "xor");
1544 break;
5abfd1af
KH		 1545 case AND:
1546 fprintf (file, "and");
1547 break;
b059c02a
KH		 1548 default:
1549 break;
1550 }
1551 break;
07aae5c2
SC		 1552 case 'e':
1553 switch (GET_CODE (x))
1554 {
1555 case REG:
48837e29
DE		 1556 if (TARGET_H8300)
1557 fprintf (file, "%s", names_big[REGNO (x)]);
1558 else
1559 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
07aae5c2
SC		 1560 break;
1561 case MEM:
88cb339e 1562 h8300_print_operand (file, x, 0);
07aae5c2
SC		 1563 break;
1564 case CONST_INT:
b47900aa 1565 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
07aae5c2 1566 break;
808fbfac
JL		 1567 case CONST_DOUBLE:
1568 {
1569 long val;
1570 REAL_VALUE_TYPE rv;
1571 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1572 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
441d04c6 1573 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
808fbfac
JL		 1574 break;
1575 }
07aae5c2 1576 default:
8c440872 1577 gcc_unreachable ();
07aae5c2
SC		 1578 break;
1579 }
1580 break;
07aae5c2
SC		 1581 case 'f':
1582 switch (GET_CODE (x))
1583 {
1584 case REG:
48837e29
DE		 1585 if (TARGET_H8300)
1586 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1587 else
1588 fprintf (file, "%s", names_big[REGNO (x)]);
07aae5c2 1589 break;
07aae5c2 1590 case MEM:
b72f00af 1591 x = adjust_address (x, HImode, 2);
88cb339e 1592 h8300_print_operand (file, x, 0);
07aae5c2 1593 break;
07aae5c2 1594 case CONST_INT:
b47900aa 1595 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
07aae5c2 1596 break;
808fbfac
JL		 1597 case CONST_DOUBLE:
1598 {
1599 long val;
1600 REAL_VALUE_TYPE rv;
1601 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1602 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
441d04c6 1603 fprintf (file, "#%ld", (val & 0xffff));
808fbfac
JL		 1604 break;
1605 }
07aae5c2 1606 default:
8c440872 1607 gcc_unreachable ();
07aae5c2
SC		 1608 }
1609 break;
07aae5c2 1610 case 'j':
761c70aa 1611 fputs (cond_string (GET_CODE (x)), file);
07aae5c2 1612 break;
07aae5c2 1613 case 'k':
761c70aa 1614 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
07aae5c2 1615 break;
beed8fc0 1616 case 'm':
8c440872
NS		 1617 gcc_assert (GET_CODE (x) == CONST_INT);
1618 switch (INTVAL (x))
1619 {
1620 case 1:
1621 fputs (".b", file);
1622 break;
1623
1624 case 2:
1625 fputs (".w", file);
1626 break;
1627
1628 case 4:
1629 fputs (".l", file);
1630 break;
1631
1632 default:
1633 gcc_unreachable ();
1634 }
beed8fc0
AO		 1635 break;
1636 case 'o':
88cb339e 1637 h8300_print_operand_address (file, x);
beed8fc0 1638 break;
48837e29
DE		 1639 case 's':
1640 if (GET_CODE (x) == CONST_INT)
b47900aa 1641 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
48837e29
DE		 1642 else
1643 fprintf (file, "%s", byte_reg (x, 0));
1644 break;
1645 case 't':
1646 if (GET_CODE (x) == CONST_INT)
b47900aa 1647 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
48837e29
DE		 1648 else
1649 fprintf (file, "%s", byte_reg (x, 1));
1650 break;
48837e29
DE		 1651 case 'w':
1652 if (GET_CODE (x) == CONST_INT)
b47900aa 1653 fprintf (file, "#%ld", INTVAL (x) & 0xff);
48837e29 1654 else
a1616dd9
JL		 1655 fprintf (file, "%s",
1656 byte_reg (x, TARGET_H8300 ? 2 : 0));
48837e29
DE		 1657 break;
1658 case 'x':
1659 if (GET_CODE (x) == CONST_INT)
b47900aa 1660 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
48837e29 1661 else
a1616dd9
JL		 1662 fprintf (file, "%s",
1663 byte_reg (x, TARGET_H8300 ? 3 : 1));
48837e29
DE		 1664 break;
1665 case 'y':
1666 if (GET_CODE (x) == CONST_INT)
b47900aa 1667 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
48837e29
DE		 1668 else
1669 fprintf (file, "%s", byte_reg (x, 0));
1670 break;
1671 case 'z':
1672 if (GET_CODE (x) == CONST_INT)
b47900aa 1673 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
48837e29
DE		 1674 else
1675 fprintf (file, "%s", byte_reg (x, 1));
1676 break;
1677
07aae5c2 1678 default:
48837e29 1679 def:
07aae5c2
SC		 1680 switch (GET_CODE (x))
1681 {
1682 case REG:
48837e29
DE		 1683 switch (GET_MODE (x))
1684 {
1685 case QImode:
269c14e1 1686#if 0 /* Is it asm ("mov.b %0,r2l", ...) */
48837e29
DE		 1687 fprintf (file, "%s", byte_reg (x, 0));
1688#else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1689 fprintf (file, "%s", names_big[REGNO (x)]);
1690#endif
1691 break;
1692 case HImode:
1693 fprintf (file, "%s", names_big[REGNO (x)]);
1694 break;
1695 case SImode:
8977e8a7 1696 case SFmode:
48837e29
DE		 1697 fprintf (file, "%s", names_extended[REGNO (x)]);
1698 break;
1699 default:
8c440872 1700 gcc_unreachable ();
48837e29 1701 }
07aae5c2
SC		 1702 break;
1703
1704 case MEM:
87e4ee91
KH		 1705 {
1706 rtx addr = XEXP (x, 0);
1707
1708 fprintf (file, "@");
1709 output_address (addr);
1710
beed8fc0
AO		 1711 /* Add a length suffix to constant addresses. Although this
1712 is often unnecessary, it helps to avoid ambiguity in the
1713 syntax of mova. If we wrote an insn like:
1714
1715 mova/w.l @(1,@foo.b),er0
1716
1717 then .b would be considered part of the symbol name.
1718 Adding a length after foo will avoid this. */
1719 if (CONSTANT_P (addr))
1720 switch (code)
1721 {
1722 case 'R':
1723 /* Used for mov.b and bit operations. */
1724 if (h8300_eightbit_constant_address_p (addr))
1725 {
1726 fprintf (file, ":8");
1727 break;
1728 }
1729
1730 /* Fall through. We should not get here if we are
1731 processing bit operations on H8/300 or H8/300H
1732 because 'U' constraint does not allow bit
1733 operations on the tiny area on these machines. */
1734
1735 case 'X':
1736 case 'T':
1737 case 'S':
1738 if (h8300_constant_length (addr) == 2)
1739 fprintf (file, ":16");
1740 else
1741 fprintf (file, ":32");
1742 break;
1743 default:
1744 break;
1745 }
87e4ee91 1746 }
07aae5c2
SC		 1747 break;
1748
1749 case CONST_INT:
1750 case SYMBOL_REF:
1751 case CONST:
1752 case LABEL_REF:
1753 fprintf (file, "#");
88cb339e 1754 h8300_print_operand_address (file, x);
07aae5c2 1755 break;
808fbfac
JL		 1756 case CONST_DOUBLE:
1757 {
1758 long val;
1759 REAL_VALUE_TYPE rv;
1760 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1761 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
441d04c6 1762 fprintf (file, "#%ld", val);
808fbfac
JL		 1763 break;
1764 }
441d04c6
KG		 1765 default:
1766 break;
07aae5c2
SC		 1767 }
1768 }
1769}
1770
88cb339e
N		 1771/* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1772
1773static bool
1774h8300_print_operand_punct_valid_p (unsigned char code)
1775{
1776 return (code == '#');
1777}
1778
07aae5c2
SC		 1779/* Output assembly language output for the address ADDR to FILE. */
1780
88cb339e
N		 1781static void
1782h8300_print_operand_address (FILE *file, rtx addr)
07aae5c2 1783{
beed8fc0
AO		 1784 rtx index;
1785 int size;
1786
07aae5c2
SC		 1787 switch (GET_CODE (addr))
1788 {
1789 case REG:
48837e29 1790 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
07aae5c2
SC		 1791 break;
1792
1793 case PRE_DEC:
48837e29 1794 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
07aae5c2
SC		 1795 break;
1796
1797 case POST_INC:
48837e29 1798 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
07aae5c2
SC		 1799 break;
1800
beed8fc0
AO		 1801 case PRE_INC:
1802 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1803 break;
1804
1805 case POST_DEC:
1806 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
1807 break;
1808
07aae5c2
SC		 1809 case PLUS:
1810 fprintf (file, "(");
beed8fc0
AO		 1811
1812 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
1813 if (GET_CODE (index) == REG)
07aae5c2
SC		 1814 {
1815 /* reg,foo */
88cb339e 1816 h8300_print_operand_address (file, XEXP (addr, 1));
07aae5c2 1817 fprintf (file, ",");
beed8fc0
AO		 1818 switch (size)
1819 {
1820 case 0:
88cb339e 1821 h8300_print_operand_address (file, index);
beed8fc0
AO		 1822 break;
1823
1824 case 1:
88cb339e 1825 h8300_print_operand (file, index, 'X');
beed8fc0
AO		 1826 fputs (".b", file);
1827 break;
1828
1829 case 2:
88cb339e 1830 h8300_print_operand (file, index, 'T');
beed8fc0
AO		 1831 fputs (".w", file);
1832 break;
1833
1834 case 4:
88cb339e 1835 h8300_print_operand (file, index, 'S');
beed8fc0
AO		 1836 fputs (".l", file);
1837 break;
1838 }
88cb339e 1839 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
07aae5c2
SC		 1840 }
1841 else
1842 {
1843 /* foo+k */
88cb339e 1844 h8300_print_operand_address (file, XEXP (addr, 0));
07aae5c2 1845 fprintf (file, "+");
88cb339e 1846 h8300_print_operand_address (file, XEXP (addr, 1));
07aae5c2
SC		 1847 }
1848 fprintf (file, ")");
1849 break;
1850
1851 case CONST_INT:
48837e29 1852 {
da55315a 1853 /* Since the H8/300 only has 16-bit pointers, negative values are also
48837e29
DE		 1854 those >= 32768. This happens for example with pointer minus a
1855 constant. We don't want to turn (char *p - 2) into
1856 (char *p + 65534) because loop unrolling can build upon this
1857 (IE: char *p + 131068). */
1858 int n = INTVAL (addr);
1859 if (TARGET_H8300)
1860 n = (int) (short) n;
7a770d8b 1861 fprintf (file, "%d", n);
48837e29
DE		 1862 break;
1863 }
07aae5c2
SC		 1864
1865 default:
1866 output_addr_const (file, addr);
1867 break;
1868 }
1869}
1870\f
07aae5c2
SC		 1871/* Output all insn addresses and their sizes into the assembly language
1872 output file. This is helpful for debugging whether the length attributes
1873 in the md file are correct. This is not meant to be a user selectable
1874 option. */
1875
1876void
cb713a8d
KH		 1877final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1878 int num_operands ATTRIBUTE_UNUSED)
07aae5c2
SC		 1879{
1880 /* This holds the last insn address. */
1881 static int last_insn_address = 0;
1882
7798db98 1883 const int uid = INSN_UID (insn);
07aae5c2
SC		 1884
1885 if (TARGET_ADDRESSES)
1886 {
9d98a694
AO		 1887 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1888 INSN_ADDRESSES (uid) - last_insn_address);
1889 last_insn_address = INSN_ADDRESSES (uid);
07aae5c2
SC		 1890 }
1891}
1892
48837e29
DE		 1893/* Prepare for an SI sized move. */
1894
1895int
1a793acf 1896h8300_expand_movsi (rtx operands[])
07aae5c2 1897{
48837e29
DE		 1898 rtx src = operands[1];
1899 rtx dst = operands[0];
1900 if (!reload_in_progress && !reload_completed)
1901 {
1902 if (!register_operand (dst, GET_MODE (dst)))
1903 {
1904 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1905 emit_move_insn (tmp, src);
1906 operands[1] = tmp;
1907 }
1908 }
1909 return 0;
1910}
1911
7b5cbb57
AS		 1912/* Given FROM and TO register numbers, say whether this elimination is allowed.
1913 Frame pointer elimination is automatically handled.
1914
1915 For the h8300, if frame pointer elimination is being done, we would like to
1916 convert ap and rp into sp, not fp.
1917
1918 All other eliminations are valid. */
1919
1920static bool
1921h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
1922{
1923 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
1924}
1925
5efd84c5
NF		 1926/* Conditionally modify register usage based on target flags. */
1927
1928static void
1929h8300_conditional_register_usage (void)
1930{
1931 if (!TARGET_MAC)
1932 fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1;
1933}
1934
48837e29 1935/* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
07e4d94e
KH		 1936 Define the offset between two registers, one to be eliminated, and
1937 the other its replacement, at the start of a routine. */
07aae5c2 1938
48837e29 1939int
cb713a8d 1940h8300_initial_elimination_offset (int from, int to)
48837e29 1941{
d18ad191
KH		 1942 /* The number of bytes that the return address takes on the stack. */
1943 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
48837e29 1944
1807b726
KH		 1945 /* The number of bytes that the saved frame pointer takes on the stack. */
1946 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1947
1948 /* The number of bytes that the saved registers, excluding the frame
1949 pointer, take on the stack. */
1950 int saved_regs_size = 0;
48837e29 1951
1807b726
KH		 1952 /* The number of bytes that the locals takes on the stack. */
1953 int frame_size = round_frame_size (get_frame_size ());
48837e29 1954
1807b726 1955 int regno;
48837e29 1956
1807b726
KH		 1957 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1958 if (WORD_REG_USED (regno))
1959 saved_regs_size += UNITS_PER_WORD;
48837e29 1960
1807b726
KH		 1961 /* Adjust saved_regs_size because the above loop took the frame
1962 pointer int account. */
1963 saved_regs_size -= fp_size;
39ba95b5 1964
8c440872 1965 switch (to)
1807b726 1966 {
8c440872 1967 case HARD_FRAME_POINTER_REGNUM:
1807b726
KH		 1968 switch (from)
1969 {
1970 case ARG_POINTER_REGNUM:
1971 return pc_size + fp_size;
1972 case RETURN_ADDRESS_POINTER_REGNUM:
1973 return fp_size;
1974 case FRAME_POINTER_REGNUM:
1975 return -saved_regs_size;
1976 default:
8c440872 1977 gcc_unreachable ();
1807b726 1978 }
8c440872
NS		 1979 break;
1980 case STACK_POINTER_REGNUM:
1807b726
KH		 1981 switch (from)
1982 {
1983 case ARG_POINTER_REGNUM:
1984 return pc_size + saved_regs_size + frame_size;
1985 case RETURN_ADDRESS_POINTER_REGNUM:
1986 return saved_regs_size + frame_size;
1987 case FRAME_POINTER_REGNUM:
1988 return frame_size;
1989 default:
8c440872 1990 gcc_unreachable ();
1807b726 1991 }
8c440872
NS		 1992 break;
1993 default:
1994 gcc_unreachable ();
1807b726 1995 }
8c440872 1996 gcc_unreachable ();
48837e29
DE		 1997}
1998
e9eba255
KH		 1999/* Worker function for RETURN_ADDR_RTX. */
2000
1aae372e 2001rtx
cb713a8d 2002h8300_return_addr_rtx (int count, rtx frame)
1aae372e
JL		 2003{
2004 rtx ret;
2005
2006 if (count == 0)
2007 ret = gen_rtx_MEM (Pmode,
2008 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
2009 else if (flag_omit_frame_pointer)
2010 return (rtx) 0;
2011 else
2012 ret = gen_rtx_MEM (Pmode,
2013 memory_address (Pmode,
0a81f074
RS		 2014 plus_constant (Pmode, frame,
2015 UNITS_PER_WORD)));
1aae372e
JL		 2016 set_mem_alias_set (ret, get_frame_alias_set ());
2017 return ret;
2018}
2019
48837e29
DE		 2020/* Update the condition code from the insn. */
2021
441d04c6 2022void
cb713a8d 2023notice_update_cc (rtx body, rtx insn)
48837e29 2024{
d99c740f
KH		 2025 rtx set;
2026
48837e29
DE		 2027 switch (get_attr_cc (insn))
2028 {
2029 case CC_NONE:
269c14e1 2030 /* Insn does not affect CC at all. */
48837e29
DE		 2031 break;
2032
2033 case CC_NONE_0HIT:
269c14e1 2034 /* Insn does not change CC, but the 0'th operand has been changed. */
48837e29 2035 if (cc_status.value1 != 0
1ccbefce 2036 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
48837e29 2037 cc_status.value1 = 0;
d4d6d0ce
KH		 2038 if (cc_status.value2 != 0
2039 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
2040 cc_status.value2 = 0;
48837e29
DE		 2041 break;
2042
065bbfe6 2043 case CC_SET_ZN:
1ccbefce 2044 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
269c14e1
DE		 2045 The V flag is unusable. The C flag may or may not be known but
2046 that's ok because alter_cond will change tests to use EQ/NE. */
48837e29 2047 CC_STATUS_INIT;
269c14e1 2048 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
d99c740f
KH		 2049 set = single_set (insn);
2050 cc_status.value1 = SET_SRC (set);
2051 if (SET_DEST (set) != cc0_rtx)
2052 cc_status.value2 = SET_DEST (set);
48837e29
DE		 2053 break;
2054
065bbfe6 2055 case CC_SET_ZNV:
1ccbefce 2056 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
065bbfe6
JL		 2057 The C flag may or may not be known but that's ok because
2058 alter_cond will change tests to use EQ/NE. */
2059 CC_STATUS_INIT;
2060 cc_status.flags |= CC_NO_CARRY;
d99c740f
KH		 2061 set = single_set (insn);
2062 cc_status.value1 = SET_SRC (set);
2063 if (SET_DEST (set) != cc0_rtx)
c8fcf20c
KH		 2064 {
2065 /* If the destination is STRICT_LOW_PART, strip off
2066 STRICT_LOW_PART. */
2067 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
2068 cc_status.value2 = XEXP (SET_DEST (set), 0);
2069 else
2070 cc_status.value2 = SET_DEST (set);
2071 }
065bbfe6
JL		 2072 break;
2073
beed8fc0
AO		 2074 case CC_COMPARE:
2075 /* The insn is a compare instruction. */
2076 CC_STATUS_INIT;
2077 cc_status.value1 = SET_SRC (body);
2078 break;
2079
2080 case CC_CLOBBER:
2081 /* Insn doesn't leave CC in a usable state. */
2082 CC_STATUS_INIT;
2083 break;
2084 }
2085}
beed8fc0
AO		 2086\f
2087/* Given that X occurs in an address of the form (plus X constant),
2088 return the part of X that is expected to be a register. There are
2089 four kinds of addressing mode to recognize:
2090
2091 @(dd,Rn)
2092 @(dd,RnL.b)
2093 @(dd,Rn.w)
2094 @(dd,ERn.l)
2095
2096 If SIZE is nonnull, and the address is one of the last three forms,
2097 set *SIZE to the index multiplication factor. Set it to 0 for
2098 plain @(dd,Rn) addresses.
2099
2100 MODE is the mode of the value being accessed. It can be VOIDmode
2101 if the address is known to be valid, but its mode is unknown. */
2102
f52d97da 2103static rtx
beed8fc0
AO		 2104h8300_get_index (rtx x, enum machine_mode mode, int *size)
2105{
2106 int dummy, factor;
2107
2108 if (size == 0)
2109 size = &dummy;
2110
2111 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
2112 if (TARGET_H8300SX
2113 && factor <= 4
2114 && (mode == VOIDmode
2115 || GET_MODE_CLASS (mode) == MODE_INT
2116 || GET_MODE_CLASS (mode) == MODE_FLOAT))
2117 {
2118 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
2119 {
2120 /* When accessing byte-sized values, the index can be
2121 a zero-extended QImode or HImode register. */
2122 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
2123 return XEXP (x, 0);
2124 }
2125 else
2126 {
2127 /* We're looking for addresses of the form:
2128
2129 (mult X I)
2130 or (mult (zero_extend X) I)
2131
2132 where I is the size of the operand being accessed.
2133 The canonical form of the second expression is:
2134
2135 (and (mult (subreg X) I) J)
2136
2137 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2138 rtx index;
2139
2140 if (GET_CODE (x) == AND
2141 && GET_CODE (XEXP (x, 1)) == CONST_INT
2142 && (factor == 0
2143 || INTVAL (XEXP (x, 1)) == 0xff * factor
2144 || INTVAL (XEXP (x, 1)) == 0xffff * factor))
2145 {
2146 index = XEXP (x, 0);
2147 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
2148 }
2149 else
2150 {
2151 index = x;
2152 *size = 4;
2153 }
2154
2155 if (GET_CODE (index) == MULT
2156 && GET_CODE (XEXP (index, 1)) == CONST_INT
2157 && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
2158 return XEXP (index, 0);
2159 }
2160 }
2161 *size = 0;
2162 return x;
2163}
2164\f
f52d97da
AS		 2165/* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2166
2167 On the H8/300, the predecrement and postincrement address depend thus
2168 (the amount of decrement or increment being the length of the operand). */
2169
2170static bool
5bfed9a9
GJL		 2171h8300_mode_dependent_address_p (const_rtx addr,
2172 addr_space_t as ATTRIBUTE_UNUSED)
f52d97da
AS		 2173{
2174 if (GET_CODE (addr) == PLUS
2175 && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0))
2176 return true;
2177
2178 return false;
2179}
2180\f
beed8fc0
AO		 2181static const h8300_length_table addb_length_table =
2182{
2183 /* #xx Rs @aa @Rs @xx */
2184 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2185 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2186 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2187 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2188};
2189
2190static const h8300_length_table addw_length_table =
2191{
2192 /* #xx Rs @aa @Rs @xx */
2193 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2194 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2195 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2196 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2197};
2198
2199static const h8300_length_table addl_length_table =
2200{
2201 /* #xx Rs @aa @Rs @xx */
2202 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2203 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2204 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2205 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2206};
2207
2208#define logicb_length_table addb_length_table
2209#define logicw_length_table addw_length_table
2210
2211static const h8300_length_table logicl_length_table =
2212{
2213 /* #xx Rs @aa @Rs @xx */
2214 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2215 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2216 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2217 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2218};
2219
2220static const h8300_length_table movb_length_table =
2221{
2222 /* #xx Rs @aa @Rs @xx */
2223 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2224 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2225 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2226 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2227};
2228
2229#define movw_length_table movb_length_table
2230
2231static const h8300_length_table movl_length_table =
2232{
2233 /* #xx Rs @aa @Rs @xx */
2234 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2235 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2236 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2237 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2238};
2239
2240/* Return the size of the given address or displacement constant. */
2241
2242static unsigned int
2243h8300_constant_length (rtx constant)
2244{
2245 /* Check for (@d:16,Reg). */
2246 if (GET_CODE (constant) == CONST_INT
2247 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
2248 return 2;
2249
2250 /* Check for (@d:16,Reg) in cases where the displacement is
2251 an absolute address. */
2252 if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
2253 return 2;
2254
2255 return 4;
2256}
2257
2258/* Return the size of a displacement field in address ADDR, which should
2259 have the form (plus X constant). SIZE is the number of bytes being
2260 accessed. */
2261
2262static unsigned int
2263h8300_displacement_length (rtx addr, int size)
2264{
2265 rtx offset;
2266
2267 offset = XEXP (addr, 1);
2268
2269 /* Check for @(d:2,Reg). */
2270 if (register_operand (XEXP (addr, 0), VOIDmode)
2271 && GET_CODE (offset) == CONST_INT
2272 && (INTVAL (offset) == size
2273 || INTVAL (offset) == size * 2
2274 || INTVAL (offset) == size * 3))
2275 return 0;
2276
2277 return h8300_constant_length (offset);
2278}
2279
0a2aaacc
KG		 2280/* Store the class of operand OP in *OPCLASS and return the length of any
2281 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
beed8fc0
AO		 2282 can be null if only the length is needed. */
2283
2284static unsigned int
0a2aaacc 2285h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
beed8fc0
AO		 2286{
2287 enum h8300_operand_class dummy;
2288
0a2aaacc
KG		 2289 if (opclass == 0)
2290 opclass = &dummy;
beed8fc0
AO		 2291
2292 if (CONSTANT_P (op))
2293 {
0a2aaacc 2294 *opclass = H8OP_IMMEDIATE;
beed8fc0
AO		 2295
2296 /* Byte-sized immediates are stored in the opcode fields. */
2297 if (size == 1)
2298 return 0;
2299
2300 /* If this is a 32-bit instruction, see whether the constant
2301 will fit into a 16-bit immediate field. */
2302 if (TARGET_H8300SX
2303 && size == 4
2304 && GET_CODE (op) == CONST_INT
2305 && IN_RANGE (INTVAL (op), 0, 0xffff))
2306 return 2;
2307
2308 return size;
2309 }
2310 else if (GET_CODE (op) == MEM)
2311 {
2312 op = XEXP (op, 0);
2313 if (CONSTANT_P (op))
2314 {
0a2aaacc 2315 *opclass = H8OP_MEM_ABSOLUTE;
beed8fc0
AO		 2316 return h8300_constant_length (op);
2317 }
2318 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
2319 {
0a2aaacc 2320 *opclass = H8OP_MEM_COMPLEX;
beed8fc0
AO		 2321 return h8300_displacement_length (op, size);
2322 }
2323 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
2324 {
0a2aaacc 2325 *opclass = H8OP_MEM_COMPLEX;
beed8fc0
AO		 2326 return 0;
2327 }
2328 else if (register_operand (op, VOIDmode))
2329 {
0a2aaacc 2330 *opclass = H8OP_MEM_BASE;
beed8fc0
AO		 2331 return 0;
2332 }
2333 }
8c440872 2334 gcc_assert (register_operand (op, VOIDmode));
0a2aaacc 2335 *opclass = H8OP_REGISTER;
8c440872 2336 return 0;
beed8fc0
AO		 2337}
2338
2339/* Return the length of the instruction described by TABLE given that
2340 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2341 and OP2 must be an h8300_src_operand. */
2342
2343static unsigned int
2344h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
2345{
2346 enum h8300_operand_class op1_class, op2_class;
2347 unsigned int size, immediate_length;
2348
2349 size = GET_MODE_SIZE (GET_MODE (op1));
2350 immediate_length = (h8300_classify_operand (op1, size, &op1_class)
2351 + h8300_classify_operand (op2, size, &op2_class));
2352 return immediate_length + (*table)[op1_class - 1][op2_class];
2353}
2354
2355/* Return the length of a unary instruction such as neg or not given that
2356 its operand is OP. */
2357
2358unsigned int
2359h8300_unary_length (rtx op)
2360{
0a2aaacc 2361 enum h8300_operand_class opclass;
beed8fc0
AO		 2362 unsigned int size, operand_length;
2363
2364 size = GET_MODE_SIZE (GET_MODE (op));
0a2aaacc
KG		 2365 operand_length = h8300_classify_operand (op, size, &opclass);
2366 switch (opclass)
beed8fc0
AO		 2367 {
2368 case H8OP_REGISTER:
2369 return 2;
2370
2371 case H8OP_MEM_BASE:
2372 return (size == 4 ? 6 : 4);
2373
2374 case H8OP_MEM_ABSOLUTE:
2375 return operand_length + (size == 4 ? 6 : 4);
2376
2377 case H8OP_MEM_COMPLEX:
2378 return operand_length + 6;
2379
2380 default:
8c440872 2381 gcc_unreachable ();
beed8fc0
AO		 2382 }
2383}
2384
2385/* Likewise short immediate instructions such as add.w #xx:3,OP. */
2386
2387static unsigned int
2388h8300_short_immediate_length (rtx op)
2389{
0a2aaacc 2390 enum h8300_operand_class opclass;
beed8fc0
AO		 2391 unsigned int size, operand_length;
2392
2393 size = GET_MODE_SIZE (GET_MODE (op));
0a2aaacc 2394 operand_length = h8300_classify_operand (op, size, &opclass);
beed8fc0 2395
0a2aaacc 2396 switch (opclass)
beed8fc0
AO		 2397 {
2398 case H8OP_REGISTER:
2399 return 2;
2400
2401 case H8OP_MEM_BASE:
2402 case H8OP_MEM_ABSOLUTE:
2403 case H8OP_MEM_COMPLEX:
2404 return 4 + operand_length;
2405
2406 default:
8c440872 2407 gcc_unreachable ();
beed8fc0
AO		 2408 }
2409}
2410
2411/* Likewise bitfield load and store instructions. */
48837e29 2412
beed8fc0
AO		 2413static unsigned int
2414h8300_bitfield_length (rtx op, rtx op2)
2415{
0a2aaacc 2416 enum h8300_operand_class opclass;
beed8fc0
AO		 2417 unsigned int size, operand_length;
2418
2419 if (GET_CODE (op) == REG)
2420 op = op2;
8c440872 2421 gcc_assert (GET_CODE (op) != REG);
beed8fc0
AO		 2422
2423 size = GET_MODE_SIZE (GET_MODE (op));
0a2aaacc 2424 operand_length = h8300_classify_operand (op, size, &opclass);
beed8fc0 2425
0a2aaacc 2426 switch (opclass)
beed8fc0
AO		 2427 {
2428 case H8OP_MEM_BASE:
2429 case H8OP_MEM_ABSOLUTE:
2430 case H8OP_MEM_COMPLEX:
2431 return 4 + operand_length;
2432
2433 default:
8c440872 2434 gcc_unreachable ();
07aae5c2 2435 }
48837e29
DE		 2436}
2437
beed8fc0 2438/* Calculate the length of general binary instruction INSN using TABLE. */
8ccf5d5f 2439
beed8fc0
AO		 2440static unsigned int
2441h8300_binary_length (rtx insn, const h8300_length_table *table)
8ccf5d5f 2442{
beed8fc0
AO		 2443 rtx set;
2444
2445 set = single_set (insn);
8c440872 2446 gcc_assert (set);
beed8fc0
AO		 2447
2448 if (BINARY_P (SET_SRC (set)))
2449 return h8300_length_from_table (XEXP (SET_SRC (set), 0),
2450 XEXP (SET_SRC (set), 1), table);
beed8fc0 2451 else
8c440872
NS		 2452 {
2453 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
2454 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
2455 XEXP (XEXP (SET_SRC (set), 1), 1),
2456 table);
2457 }
8ccf5d5f
KH		 2458}
2459
beed8fc0
AO		 2460/* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2461 memory reference and either (1) it has the form @(d:16,Rn) or
2462 (2) its address has the code given by INC_CODE. */
8ccf5d5f 2463
beed8fc0
AO		 2464static bool
2465h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
8ccf5d5f 2466{
beed8fc0
AO		 2467 rtx addr;
2468 unsigned int size;
2469
2470 if (GET_CODE (op) != MEM)
2471 return false;
2472
2473 addr = XEXP (op, 0);
2474 size = GET_MODE_SIZE (GET_MODE (op));
2475 if (size != 1 && size != 2)
2476 return false;
2477
2478 return (GET_CODE (addr) == inc_code
2479 || (GET_CODE (addr) == PLUS
2480 && GET_CODE (XEXP (addr, 0)) == REG
2481 && h8300_displacement_length (addr, size) == 2));
8ccf5d5f
KH		 2482}
2483
beed8fc0
AO		 2484/* Calculate the length of move instruction INSN using the given length
2485 table. Although the tables are correct for most cases, there is some
2486 irregularity in the length of mov.b and mov.w. The following forms:
8ccf5d5f 2487
beed8fc0
AO		 2488 mov @ERs+, Rd
2489 mov @(d:16,ERs), Rd
2490 mov Rs, @-ERd
2491 mov Rs, @(d:16,ERd)
2492
2493 are two bytes shorter than most other "mov Rs, @complex" or
2494 "mov @complex,Rd" combinations. */
2495
2496static unsigned int
2497h8300_move_length (rtx *operands, const h8300_length_table *table)
8ccf5d5f 2498{
beed8fc0
AO		 2499 unsigned int size;
2500
2501 size = h8300_length_from_table (operands[0], operands[1], table);
2502 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
2503 size -= 2;
2504 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
2505 size -= 2;
2506 return size;
8ccf5d5f
KH		 2507}
2508
beed8fc0
AO		 2509/* Return the length of a mova instruction with the given operands.
2510 DEST is the register destination, SRC is the source address and
2511 OFFSET is the 16-bit or 32-bit displacement. */
2873836b 2512
beed8fc0
AO		 2513static unsigned int
2514h8300_mova_length (rtx dest, rtx src, rtx offset)
2873836b 2515{
beed8fc0
AO		 2516 unsigned int size;
2517
2518 size = (2
2519 + h8300_constant_length (offset)
2520 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
2521 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
2522 size += 2;
2523 return size;
2873836b
KH		 2524}
2525
beed8fc0
AO		 2526/* Compute the length of INSN based on its length_table attribute.
2527 OPERANDS is the array of its operands. */
2873836b 2528
beed8fc0
AO		 2529unsigned int
2530h8300_insn_length_from_table (rtx insn, rtx * operands)
2873836b 2531{
beed8fc0
AO		 2532 switch (get_attr_length_table (insn))
2533 {
2534 case LENGTH_TABLE_NONE:
8c440872 2535 gcc_unreachable ();
beed8fc0
AO		 2536
2537 case LENGTH_TABLE_ADDB:
2538 return h8300_binary_length (insn, &addb_length_table);
2539
2540 case LENGTH_TABLE_ADDW:
2541 return h8300_binary_length (insn, &addw_length_table);
2542
2543 case LENGTH_TABLE_ADDL:
2544 return h8300_binary_length (insn, &addl_length_table);
2545
2546 case LENGTH_TABLE_LOGICB:
2547 return h8300_binary_length (insn, &logicb_length_table);
2548
2549 case LENGTH_TABLE_MOVB:
2550 return h8300_move_length (operands, &movb_length_table);
2551
2552 case LENGTH_TABLE_MOVW:
2553 return h8300_move_length (operands, &movw_length_table);
2554
2555 case LENGTH_TABLE_MOVL:
2556 return h8300_move_length (operands, &movl_length_table);
2557
2558 case LENGTH_TABLE_MOVA:
2559 return h8300_mova_length (operands[0], operands[1], operands[2]);
2560
2561 case LENGTH_TABLE_MOVA_ZERO:
2562 return h8300_mova_length (operands[0], operands[1], const0_rtx);
2563
2564 case LENGTH_TABLE_UNARY:
2565 return h8300_unary_length (operands[0]);
2566
2567 case LENGTH_TABLE_MOV_IMM4:
2568 return 2 + h8300_classify_operand (operands[0], 0, 0);
2569
2570 case LENGTH_TABLE_SHORT_IMMEDIATE:
2571 return h8300_short_immediate_length (operands[0]);
2572
2573 case LENGTH_TABLE_BITFIELD:
2574 return h8300_bitfield_length (operands[0], operands[1]);
2575
2576 case LENGTH_TABLE_BITBRANCH:
2577 return h8300_bitfield_length (operands[1], operands[2]) - 2;
8c440872
NS		 2578
2579 default:
2580 gcc_unreachable ();
beed8fc0 2581 }
2873836b
KH		 2582}
2583
beed8fc0
AO		 2584/* Return true if LHS and RHS are memory references that can be mapped
2585 to the same h8sx assembly operand. LHS appears as the destination of
2586 an instruction and RHS appears as a source.
f9d2de4d 2587
beed8fc0
AO		 2588 Three cases are allowed:
2589
2590 - RHS is @+Rn or @-Rn, LHS is @Rn
2591 - RHS is @Rn, LHS is @Rn+ or @Rn-
2592 - RHS and LHS have the same address and neither has side effects. */
2593
2594bool
2595h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
f9d2de4d 2596{
beed8fc0
AO		 2597 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
2598 {
2599 rhs = XEXP (rhs, 0);
2600 lhs = XEXP (lhs, 0);
2601
2602 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
2603 return rtx_equal_p (XEXP (rhs, 0), lhs);
2604
2605 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
2606 return rtx_equal_p (rhs, XEXP (lhs, 0));
2607
2608 if (rtx_equal_p (rhs, lhs))
2609 return true;
2610 }
2611 return false;
f9d2de4d
KH		 2612}
2613
beed8fc0
AO		 2614/* Return true if OPERANDS[1] can be mapped to the same assembly
2615 operand as OPERANDS[0]. */
f9d2de4d 2616
beed8fc0
AO		 2617bool
2618h8300_operands_match_p (rtx *operands)
f9d2de4d 2619{
beed8fc0
AO		 2620 if (register_operand (operands[0], VOIDmode)
2621 && register_operand (operands[1], VOIDmode))
2622 return true;
f9d2de4d 2623
beed8fc0
AO		 2624 if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
2625 return true;
2626
2627 return false;
f9d2de4d 2628}
beed8fc0
AO		 2629\f
2630/* Try using movmd to move LENGTH bytes from memory region SRC to memory
2631 region DEST. The two regions do not overlap and have the common
2632 alignment given by ALIGNMENT. Return true on success.
717d8b71 2633
beed8fc0
AO		 2634 Using movmd for variable-length moves seems to involve some
2635 complex trade-offs. For instance:
b059c02a 2636
beed8fc0
AO		 2637 - Preparing for a movmd instruction is similar to preparing
2638 for a memcpy. The main difference is that the arguments
2639 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2640
2641 - Since movmd clobbers the frame pointer, we need to save
2642 and restore it somehow when frame_pointer_needed. This can
2643 sometimes make movmd sequences longer than calls to memcpy().
2644
2645 - The counter register is 16 bits, so the instruction is only
2646 suitable for variable-length moves when sizeof (size_t) == 2.
2647 That's only true in normal mode.
2648
2649 - We will often lack static alignment information. Falling back
2650 on movmd.b would likely be slower than calling memcpy(), at least
2651 for big moves.
2652
2653 This function therefore only uses movmd when the length is a
2654 known constant, and only then if -fomit-frame-pointer is in
2655 effect or if we're not optimizing for size.
2656
2657 At the moment the function uses movmd for all in-range constants,
2658 but it might be better to fall back on memcpy() for large moves
2659 if ALIGNMENT == 1. */
2660
2661bool
2662h8sx_emit_movmd (rtx dest, rtx src, rtx length,
2663 HOST_WIDE_INT alignment)
b059c02a 2664{
beed8fc0
AO		 2665 if (!flag_omit_frame_pointer && optimize_size)
2666 return false;
b059c02a 2667
beed8fc0
AO		 2668 if (GET_CODE (length) == CONST_INT)
2669 {
2670 rtx dest_reg, src_reg, first_dest, first_src;
2671 HOST_WIDE_INT n;
2672 int factor;
2673
2674 /* Use movmd.l if the alignment allows it, otherwise fall back
2675 on movmd.b. */
2676 factor = (alignment >= 2 ? 4 : 1);
2677
2678 /* Make sure the length is within range. We can handle counter
2679 values up to 65536, although HImode truncation will make
2680 the count appear negative in rtl dumps. */
2681 n = INTVAL (length);
2682 if (n <= 0 || n / factor > 65536)
2683 return false;
2684
2685 /* Create temporary registers for the source and destination
2686 pointers. Initialize them to the start of each region. */
2687 dest_reg = copy_addr_to_reg (XEXP (dest, 0));
2688 src_reg = copy_addr_to_reg (XEXP (src, 0));
2689
2690 /* Create references to the movmd source and destination blocks. */
2691 first_dest = replace_equiv_address (dest, dest_reg);
2692 first_src = replace_equiv_address (src, src_reg);
2693
f5541398
RS		 2694 set_mem_size (first_dest, n & -factor);
2695 set_mem_size (first_src, n & -factor);
beed8fc0
AO		 2696
2697 length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode));
2698 emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor)));
2699
2700 if ((n & -factor) != n)
2701 {
2702 /* Move SRC and DEST past the region we just copied.
2703 This is done to update the memory attributes. */
2704 dest = adjust_address (dest, BLKmode, n & -factor);
2705 src = adjust_address (src, BLKmode, n & -factor);
2706
2707 /* Replace the addresses with the source and destination
2708 registers, which movmd has left with the right values. */
2709 dest = replace_equiv_address (dest, dest_reg);
2710 src = replace_equiv_address (src, src_reg);
2711
2712 /* Mop up the left-over bytes. */
2713 if (n & 2)
2714 emit_move_insn (adjust_address (dest, HImode, 0),
2715 adjust_address (src, HImode, 0));
2716 if (n & 1)
2717 emit_move_insn (adjust_address (dest, QImode, n & 2),
2718 adjust_address (src, QImode, n & 2));
2719 }
2720 return true;
2721 }
2722 return false;
b059c02a
KH		 2723}
2724
beed8fc0 2725/* Move ADDR into er6 after pushing its old value onto the stack. */
48837e29 2726
beed8fc0
AO		 2727void
2728h8300_swap_into_er6 (rtx addr)
48837e29 2729{
8f1594b2
RH		 2730 rtx insn = push (HARD_FRAME_POINTER_REGNUM);
2731 if (frame_pointer_needed)
2732 add_reg_note (insn, REG_CFA_DEF_CFA,
0a81f074 2733 plus_constant (Pmode, gen_rtx_MEM (Pmode, stack_pointer_rtx),
8f1594b2
RH		 2734 2 * UNITS_PER_WORD));
2735 else
2736 add_reg_note (insn, REG_CFA_ADJUST_CFA,
2737 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
0a81f074 2738 plus_constant (Pmode, stack_pointer_rtx, 4)));
8f1594b2 2739
beed8fc0
AO		 2740 emit_move_insn (hard_frame_pointer_rtx, addr);
2741 if (REGNO (addr) == SP_REG)
2742 emit_move_insn (hard_frame_pointer_rtx,
0a81f074 2743 plus_constant (Pmode, hard_frame_pointer_rtx,
beed8fc0
AO		 2744 GET_MODE_SIZE (word_mode)));
2745}
07aae5c2 2746
beed8fc0
AO		 2747/* Move the current value of er6 into ADDR and pop its old value
2748 from the stack. */
2749
2750void
2751h8300_swap_out_of_er6 (rtx addr)
2752{
8f1594b2
RH		 2753 rtx insn;
2754
beed8fc0
AO		 2755 if (REGNO (addr) != SP_REG)
2756 emit_move_insn (addr, hard_frame_pointer_rtx);
8f1594b2
RH		 2757
2758 insn = pop (HARD_FRAME_POINTER_REGNUM);
2759 RTX_FRAME_RELATED_P (insn) = 1;
2760 if (frame_pointer_needed)
2761 add_reg_note (insn, REG_CFA_DEF_CFA,
0a81f074
RS		 2762 plus_constant (Pmode, hard_frame_pointer_rtx,
2763 2 * UNITS_PER_WORD));
8f1594b2
RH		 2764 else
2765 add_reg_note (insn, REG_CFA_ADJUST_CFA,
2766 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
0a81f074 2767 plus_constant (Pmode, stack_pointer_rtx, -4)));
07aae5c2 2768}
48837e29 2769\f
7948a9ea
KH		 2770/* Return the length of mov instruction. */
2771
2772unsigned int
2773compute_mov_length (rtx *operands)
2774{
2775 /* If the mov instruction involves a memory operand, we compute the
2776 length, assuming the largest addressing mode is used, and then
2777 adjust later in the function. Otherwise, we compute and return
2778 the exact length in one step. */
2779 enum machine_mode mode = GET_MODE (operands[0]);
2780 rtx dest = operands[0];
2781 rtx src = operands[1];
2782 rtx addr;
2783
2784 if (GET_CODE (src) == MEM)
2785 addr = XEXP (src, 0);
2786 else if (GET_CODE (dest) == MEM)
2787 addr = XEXP (dest, 0);
2788 else
2789 addr = NULL_RTX;
2790
2791 if (TARGET_H8300)
2792 {
2793 unsigned int base_length;
2794
2795 switch (mode)
2796 {
2797 case QImode:
2798 if (addr == NULL_RTX)
2799 return 2;
2800
2801 /* The eightbit addressing is available only in QImode, so
2802 go ahead and take care of it. */
2803 if (h8300_eightbit_constant_address_p (addr))
2804 return 2;
2805
2806 base_length = 4;
2807 break;
2808
2809 case HImode:
2810 if (addr == NULL_RTX)
2811 {
2812 if (REG_P (src))
2813 return 2;
2814
2815 if (src == const0_rtx)
2816 return 2;
2817
2818 return 4;
2819 }
2820
2821 base_length = 4;
2822 break;
2823
2824 case SImode:
2825 if (addr == NULL_RTX)
2826 {
2827 if (REG_P (src))
2828 return 4;
2829
2830 if (GET_CODE (src) == CONST_INT)
2831 {
2832 if (src == const0_rtx)
2833 return 4;
2834
2835 if ((INTVAL (src) & 0xffff) == 0)
2836 return 6;
2837
2838 if ((INTVAL (src) & 0xffff) == 0)
2839 return 6;
f5139cc5
KH		 2840
2841 if ((INTVAL (src) & 0xffff)
2842 == ((INTVAL (src) >> 16) & 0xffff))
2843 return 6;
7948a9ea
KH		 2844 }
2845 return 8;
2846 }
2847
2848 base_length = 8;
2849 break;
2850
2851 case SFmode:
2852 if (addr == NULL_RTX)
2853 {
2854 if (REG_P (src))
2855 return 4;
2856
ceaaaeab 2857 if (satisfies_constraint_G (src))
2c4a71b3
KH		 2858 return 4;
2859
81983b04 2860 return 8;
7948a9ea
KH		 2861 }
2862
2863 base_length = 8;
2864 break;
2865
2866 default:
8c440872 2867 gcc_unreachable ();
7948a9ea
KH		 2868 }
2869
2870 /* Adjust the length based on the addressing mode used.
2871 Specifically, we subtract the difference between the actual
2872 length and the longest one, which is @(d:16,Rs). For SImode
2873 and SFmode, we double the adjustment because two mov.w are
2874 used to do the job. */
2875
2876 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2877 if (GET_CODE (addr) == PRE_DEC
2878 || GET_CODE (addr) == POST_INC)
2879 {
2880 if (mode == QImode || mode == HImode)
2881 return base_length - 2;
2882 else
2883 /* In SImode and SFmode, we use two mov.w instructions, so
2a43945f 2884 double the adjustment. */
7948a9ea
KH		 2885 return base_length - 4;
2886 }
2887
2888 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2889 in SImode and SFmode, the second mov.w involves an address
2890 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2891 only 2 bytes. */
2892 if (GET_CODE (addr) == REG)
2893 return base_length - 2;
2894
2895 return base_length;
2896 }
2897 else
2898 {
2899 unsigned int base_length;
2900
2901 switch (mode)
2902 {
2903 case QImode:
2904 if (addr == NULL_RTX)
2905 return 2;
2906
2907 /* The eightbit addressing is available only in QImode, so
2908 go ahead and take care of it. */
2909 if (h8300_eightbit_constant_address_p (addr))
2910 return 2;
2911
2912 base_length = 8;
2913 break;
2914
2915 case HImode:
2916 if (addr == NULL_RTX)
2917 {
2918 if (REG_P (src))
2919 return 2;
2920
2921 if (src == const0_rtx)
2922 return 2;
2923
2924 return 4;
2925 }
2926
2927 base_length = 8;
2928 break;
2929
2930 case SImode:
2931 if (addr == NULL_RTX)
2932 {
2933 if (REG_P (src))
2934 {
2935 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2936 return 4;
2937 else
2938 return 2;
2939 }
2940
2941 if (GET_CODE (src) == CONST_INT)
2942 {
2943 int val = INTVAL (src);
2944
2945 if (val == 0)
2946 return 2;
2947
2948 if (val == (val & 0x00ff) || val == (val & 0xff00))
2949 return 4;
80e58519 2950
7948a9ea
KH		 2951 switch (val & 0xffffffff)
2952 {
2953 case 0xffffffff:
2954 case 0xfffffffe:
2955 case 0xfffffffc:
2956 case 0x0000ffff:
2957 case 0x0000fffe:
2958 case 0xffff0000:
2959 case 0xfffe0000:
2960 case 0x00010000:
2961 case 0x00020000:
2962 return 4;
2963 }
2964 }
2965 return 6;
2966 }
2967
2968 base_length = 10;
2969 break;
2970
2971 case SFmode:
2972 if (addr == NULL_RTX)
2973 {
2974 if (REG_P (src))
2975 return 2;
2976
ceaaaeab 2977 if (satisfies_constraint_G (src))
7948a9ea 2978 return 2;
2c4a71b3 2979
7948a9ea
KH		 2980 return 6;
2981 }
2982
2983 base_length = 10;
2984 break;
2985
2986 default:
8c440872 2987 gcc_unreachable ();
7948a9ea
KH		 2988 }
2989
2990 /* Adjust the length based on the addressing mode used.
2991 Specifically, we subtract the difference between the actual
2992 length and the longest one, which is @(d:24,ERs). */
2993
2994 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2995 if (GET_CODE (addr) == PRE_DEC
2996 || GET_CODE (addr) == POST_INC)
2997 return base_length - 6;
2998
2999 /* @ERs and @ERd are 6 bytes shorter than the longest. */
3000 if (GET_CODE (addr) == REG)
3001 return base_length - 6;
3002
3003 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
3004 longest. */
3005 if (GET_CODE (addr) == PLUS
3006 && GET_CODE (XEXP (addr, 0)) == REG
3007 && GET_CODE (XEXP (addr, 1)) == CONST_INT
3008 && INTVAL (XEXP (addr, 1)) > -32768
3009 && INTVAL (XEXP (addr, 1)) < 32767)
3010 return base_length - 4;
3011
3012 /* @aa:16 is 4 bytes shorter than the longest. */
3013 if (h8300_tiny_constant_address_p (addr))
3014 return base_length - 4;
3015
3016 /* @aa:24 is 2 bytes shorter than the longest. */
3017 if (CONSTANT_P (addr))
3018 return base_length - 2;
3019
3020 return base_length;
3021 }
3022}
3023\f
e9eba255
KH		 3024/* Output an addition insn. */
3025
366a7b27 3026const char *
cb713a8d 3027output_plussi (rtx *operands)
7d6ac401
KH		 3028{
3029 enum machine_mode mode = GET_MODE (operands[0]);
3030
8c440872 3031 gcc_assert (mode == SImode);
7d6ac401
KH		 3032
3033 if (TARGET_H8300)
3034 {
cfedf91b
KH		 3035 if (GET_CODE (operands[2]) == REG)
3036 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3037
3038 if (GET_CODE (operands[2]) == CONST_INT)
3039 {
3040 HOST_WIDE_INT n = INTVAL (operands[2]);
3041
3042 if ((n & 0xffffff) == 0)
3043 return "add\t%z2,%z0";
3044 if ((n & 0xffff) == 0)
3045 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
3046 if ((n & 0xff) == 0)
3047 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3048 }
3049
3050 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
7d6ac401
KH		 3051 }
3052 else
3053 {
beed8fc0
AO		 3054 if (GET_CODE (operands[2]) == CONST_INT
3055 && register_operand (operands[1], VOIDmode))
7d6ac401
KH		 3056 {
3057 HOST_WIDE_INT intval = INTVAL (operands[2]);
3058
beed8fc0
AO		 3059 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3060 return "add.l\t%S2,%S0";
3061 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3062 return "sub.l\t%G2,%S0";
3063
7d6ac401
KH		 3064 /* See if we can finish with 2 bytes. */
3065
9ac7ebba 3066 switch ((unsigned int) intval & 0xffffffff)
7d6ac401
KH		 3067 {
3068 case 0x00000001:
3069 case 0x00000002:
3070 case 0x00000004:
3071 return "adds\t%2,%S0";
3072
3073 case 0xffffffff:
3074 case 0xfffffffe:
3075 case 0xfffffffc:
3076 return "subs\t%G2,%S0";
3077
3078 case 0x00010000:
3079 case 0x00020000:
3080 operands[2] = GEN_INT (intval >> 16);
3081 return "inc.w\t%2,%e0";
3082
3083 case 0xffff0000:
3084 case 0xfffe0000:
3085 operands[2] = GEN_INT (intval >> 16);
3086 return "dec.w\t%G2,%e0";
3087 }
3088
3089 /* See if we can finish with 4 bytes. */
3090 if ((intval & 0xffff) == 0)
3091 {
3092 operands[2] = GEN_INT (intval >> 16);
3093 return "add.w\t%2,%e0";
3094 }
3095 }
3096
beed8fc0
AO		 3097 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3098 {
3099 operands[2] = GEN_INT (-INTVAL (operands[2]));
3100 return "sub.l\t%S2,%S0";
3101 }
7d6ac401
KH		 3102 return "add.l\t%S2,%S0";
3103 }
3104}
3105
beed8fc0
AO		 3106/* ??? It would be much easier to add the h8sx stuff if a single function
3107 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
e9eba255
KH		 3108/* Compute the length of an addition insn. */
3109
7d6ac401 3110unsigned int
cb713a8d 3111compute_plussi_length (rtx *operands)
7d6ac401
KH		 3112{
3113 enum machine_mode mode = GET_MODE (operands[0]);
3114
8c440872 3115 gcc_assert (mode == SImode);
7d6ac401
KH		 3116
3117 if (TARGET_H8300)
3118 {
cfedf91b
KH		 3119 if (GET_CODE (operands[2]) == REG)
3120 return 6;
3121
3122 if (GET_CODE (operands[2]) == CONST_INT)
3123 {
3124 HOST_WIDE_INT n = INTVAL (operands[2]);
3125
3126 if ((n & 0xffffff) == 0)
3127 return 2;
3128 if ((n & 0xffff) == 0)
3129 return 4;
3130 if ((n & 0xff) == 0)
3131 return 6;
3132 }
3133
3134 return 8;
7d6ac401
KH		 3135 }
3136 else
3137 {
beed8fc0
AO		 3138 if (GET_CODE (operands[2]) == CONST_INT
3139 && register_operand (operands[1], VOIDmode))
7d6ac401
KH		 3140 {
3141 HOST_WIDE_INT intval = INTVAL (operands[2]);
3142
beed8fc0
AO		 3143 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3144 return 2;
3145 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3146 return 2;
3147
7d6ac401
KH		 3148 /* See if we can finish with 2 bytes. */
3149
9ac7ebba 3150 switch ((unsigned int) intval & 0xffffffff)
7d6ac401
KH		 3151 {
3152 case 0x00000001:
3153 case 0x00000002:
3154 case 0x00000004:
3155 return 2;
3156
3157 case 0xffffffff:
3158 case 0xfffffffe:
3159 case 0xfffffffc:
3160 return 2;
3161
3162 case 0x00010000:
3163 case 0x00020000:
3164 return 2;
3165
3166 case 0xffff0000:
3167 case 0xfffe0000:
3168 return 2;
3169 }
3170
3171 /* See if we can finish with 4 bytes. */
3172 if ((intval & 0xffff) == 0)
3173 return 4;
3174 }
3175
beed8fc0
AO		 3176 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3177 return h8300_length_from_table (operands[0],
3178 GEN_INT (-INTVAL (operands[2])),
3179 &addl_length_table);
3180 else
3181 return h8300_length_from_table (operands[0], operands[2],
3182 &addl_length_table);
7d6ac401
KH		 3183 return 6;
3184 }
3185}
3186
e9eba255
KH		 3187/* Compute which flag bits are valid after an addition insn. */
3188
9690aa8e 3189enum attr_cc
cb713a8d 3190compute_plussi_cc (rtx *operands)
7d6ac401
KH		 3191{
3192 enum machine_mode mode = GET_MODE (operands[0]);
3193
8c440872 3194 gcc_assert (mode == SImode);
7d6ac401
KH		 3195
3196 if (TARGET_H8300)
3197 {
cfedf91b 3198 return CC_CLOBBER;
7d6ac401
KH		 3199 }
3200 else
3201 {
beed8fc0
AO		 3202 if (GET_CODE (operands[2]) == CONST_INT
3203 && register_operand (operands[1], VOIDmode))
7d6ac401
KH		 3204 {
3205 HOST_WIDE_INT intval = INTVAL (operands[2]);
3206
beed8fc0
AO		 3207 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3208 return CC_SET_ZN;
3209 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3210 return CC_SET_ZN;
3211
7d6ac401
KH		 3212 /* See if we can finish with 2 bytes. */
3213
9ac7ebba 3214 switch ((unsigned int) intval & 0xffffffff)
7d6ac401
KH		 3215 {
3216 case 0x00000001:
3217 case 0x00000002:
3218 case 0x00000004:
3219 return CC_NONE_0HIT;
3220
3221 case 0xffffffff:
3222 case 0xfffffffe:
3223 case 0xfffffffc:
3224 return CC_NONE_0HIT;
3225
3226 case 0x00010000:
3227 case 0x00020000:
3228 return CC_CLOBBER;
3229
3230 case 0xffff0000:
3231 case 0xfffe0000:
3232 return CC_CLOBBER;
3233 }
3234
3235 /* See if we can finish with 4 bytes. */
3236 if ((intval & 0xffff) == 0)
3237 return CC_CLOBBER;
3238 }
3239
3240 return CC_SET_ZN;
3241 }
3242}
3243\f
e9eba255
KH		 3244/* Output a logical insn. */
3245
7d6ac401 3246const char *
cb713a8d 3247output_logical_op (enum machine_mode mode, rtx *operands)
366a7b27 3248{
b42cff6b
KH		 3249 /* Figure out the logical op that we need to perform. */
3250 enum rtx_code code = GET_CODE (operands[3]);
366a7b27 3251 /* Pretend that every byte is affected if both operands are registers. */
7798db98 3252 const unsigned HOST_WIDE_INT intval =
366a7b27 3253 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
beed8fc0
AO		 3254 /* Always use the full instruction if the
3255 first operand is in memory. It is better
3256 to use define_splits to generate the shorter
3257 sequence where valid. */
3258 && register_operand (operands[1], VOIDmode)
366a7b27
KH		 3259 ? INTVAL (operands[2]) : 0x55555555);
3260 /* The determinant of the algorithm. If we perform an AND, 0
3261 affects a bit. Otherwise, 1 affects a bit. */
7798db98 3262 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
f9ac2f95
KH		 3263 /* Break up DET into pieces. */
3264 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3265 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
c5e7ce43
KH		 3266 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3267 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
f9ac2f95
KH		 3268 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3269 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3270 int lower_half_easy_p = 0;
3271 int upper_half_easy_p = 0;
366a7b27
KH		 3272 /* The name of an insn. */
3273 const char *opname;
3274 char insn_buf[100];
3275
3276 switch (code)
3277 {
3278 case AND:
3279 opname = "and";
3280 break;
3281 case IOR:
3282 opname = "or";
3283 break;
3284 case XOR:
3285 opname = "xor";
3286 break;
3287 default:
8c440872 3288 gcc_unreachable ();
366a7b27
KH		 3289 }
3290
3291 switch (mode)
3292 {
3293 case HImode:
3294 /* First, see if we can finish with one insn. */
3295 if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 3296 && b0 != 0
3297 && b1 != 0)
366a7b27
KH		 3298 {
3299 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
3300 output_asm_insn (insn_buf, operands);
3301 }
3302 else
3303 {
3304 /* Take care of the lower byte. */
c5e7ce43 3305 if (b0 != 0)
366a7b27
KH		 3306 {
3307 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
3308 output_asm_insn (insn_buf, operands);
3309 }
3310 /* Take care of the upper byte. */
c5e7ce43 3311 if (b1 != 0)
366a7b27
KH		 3312 {
3313 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
3314 output_asm_insn (insn_buf, operands);
3315 }
3316 }
3317 break;
3318 case SImode:
f9ac2f95
KH		 3319 if (TARGET_H8300H || TARGET_H8300S)
3320 {
3321 /* Determine if the lower half can be taken care of in no more
3322 than two bytes. */
3323 lower_half_easy_p = (b0 == 0
3324 || b1 == 0
3325 || (code != IOR && w0 == 0xffff));
3326
3327 /* Determine if the upper half can be taken care of in no more
3328 than two bytes. */
3329 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3330 || (code == AND && w1 == 0xff00));
3331 }
366a7b27 3332
f9ac2f95
KH		 3333 /* Check if doing everything with one insn is no worse than
3334 using multiple insns. */
366a7b27 3335 if ((TARGET_H8300H || TARGET_H8300S)
f9ac2f95 3336 && w0 != 0 && w1 != 0
472f2723
KH		 3337 && !(lower_half_easy_p && upper_half_easy_p)
3338 && !(code == IOR && w1 == 0xffff
3339 && (w0 & 0x8000) != 0 && lower_half_easy_p))
366a7b27
KH		 3340 {
3341 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
3342 output_asm_insn (insn_buf, operands);
3343 }
3344 else
3345 {
3346 /* Take care of the lower and upper words individually. For
3347 each word, we try different methods in the order of
3348
3349 1) the special insn (in case of AND or XOR),
3350 2) the word-wise insn, and
3351 3) The byte-wise insn. */
c5e7ce43 3352 if (w0 == 0xffff
6dfa4005 3353 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
366a7b27 3354 output_asm_insn ((code == AND)
187462ac 3355 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
366a7b27
KH		 3356 operands);
3357 else if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 3358 && (b0 != 0)
3359 && (b1 != 0))
366a7b27
KH		 3360 {
3361 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
3362 output_asm_insn (insn_buf, operands);
3363 }
3364 else
3365 {
c5e7ce43 3366 if (b0 != 0)
366a7b27
KH		 3367 {
3368 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
3369 output_asm_insn (insn_buf, operands);
3370 }
c5e7ce43 3371 if (b1 != 0)
366a7b27
KH		 3372 {
3373 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
3374 output_asm_insn (insn_buf, operands);
3375 }
3376 }
3377
c5e7ce43 3378 if ((w1 == 0xffff)
6dfa4005 3379 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
366a7b27 3380 output_asm_insn ((code == AND)
187462ac 3381 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
366a7b27 3382 operands);
472f2723
KH		 3383 else if ((TARGET_H8300H || TARGET_H8300S)
3384 && code == IOR
3385 && w1 == 0xffff
3386 && (w0 & 0x8000) != 0)
3387 {
3388 output_asm_insn ("exts.l\t%S0", operands);
3389 }
a6e8d113
KH		 3390 else if ((TARGET_H8300H || TARGET_H8300S)
3391 && code == AND
c5e7ce43 3392 && w1 == 0xff00)
a6e8d113 3393 {
dc5f17ec 3394 output_asm_insn ("extu.w\t%e0", operands);
a6e8d113 3395 }
366a7b27
KH		 3396 else if (TARGET_H8300H || TARGET_H8300S)
3397 {
c5e7ce43 3398 if (w1 != 0)
366a7b27
KH		 3399 {
3400 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
3401 output_asm_insn (insn_buf, operands);
3402 }
3403 }
3404 else
3405 {
c5e7ce43 3406 if (b2 != 0)
366a7b27
KH		 3407 {
3408 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
3409 output_asm_insn (insn_buf, operands);
3410 }
c5e7ce43 3411 if (b3 != 0)
366a7b27
KH		 3412 {
3413 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
3414 output_asm_insn (insn_buf, operands);
3415 }
3416 }
3417 }
3418 break;
3419 default:
8c440872 3420 gcc_unreachable ();
366a7b27
KH		 3421 }
3422 return "";
3423}
40367e2d 3424
e9eba255
KH		 3425/* Compute the length of a logical insn. */
3426
40367e2d 3427unsigned int
cb713a8d 3428compute_logical_op_length (enum machine_mode mode, rtx *operands)
40367e2d 3429{
b42cff6b
KH		 3430 /* Figure out the logical op that we need to perform. */
3431 enum rtx_code code = GET_CODE (operands[3]);
40367e2d 3432 /* Pretend that every byte is affected if both operands are registers. */
7798db98 3433 const unsigned HOST_WIDE_INT intval =
40367e2d 3434 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
beed8fc0
AO		 3435 /* Always use the full instruction if the
3436 first operand is in memory. It is better
3437 to use define_splits to generate the shorter
3438 sequence where valid. */
3439 && register_operand (operands[1], VOIDmode)
40367e2d
KH		 3440 ? INTVAL (operands[2]) : 0x55555555);
3441 /* The determinant of the algorithm. If we perform an AND, 0
3442 affects a bit. Otherwise, 1 affects a bit. */
7798db98 3443 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
f9ac2f95
KH		 3444 /* Break up DET into pieces. */
3445 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3446 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
c5e7ce43
KH		 3447 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3448 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
f9ac2f95
KH		 3449 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3450 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3451 int lower_half_easy_p = 0;
3452 int upper_half_easy_p = 0;
40367e2d
KH		 3453 /* Insn length. */
3454 unsigned int length = 0;
3455
3456 switch (mode)
3457 {
3458 case HImode:
3459 /* First, see if we can finish with one insn. */
3460 if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 3461 && b0 != 0
3462 && b1 != 0)
40367e2d 3463 {
beed8fc0
AO		 3464 length = h8300_length_from_table (operands[1], operands[2],
3465 &logicw_length_table);
40367e2d
KH		 3466 }
3467 else
3468 {
3469 /* Take care of the lower byte. */
c5e7ce43 3470 if (b0 != 0)
40367e2d
KH		 3471 length += 2;
3472
3473 /* Take care of the upper byte. */
c5e7ce43 3474 if (b1 != 0)
40367e2d
KH		 3475 length += 2;
3476 }
3477 break;
3478 case SImode:
f9ac2f95
KH		 3479 if (TARGET_H8300H || TARGET_H8300S)
3480 {
3481 /* Determine if the lower half can be taken care of in no more
3482 than two bytes. */
3483 lower_half_easy_p = (b0 == 0
3484 || b1 == 0
3485 || (code != IOR && w0 == 0xffff));
3486
3487 /* Determine if the upper half can be taken care of in no more
3488 than two bytes. */
3489 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3490 || (code == AND && w1 == 0xff00));
3491 }
40367e2d 3492
f9ac2f95
KH		 3493 /* Check if doing everything with one insn is no worse than
3494 using multiple insns. */
40367e2d 3495 if ((TARGET_H8300H || TARGET_H8300S)
f9ac2f95 3496 && w0 != 0 && w1 != 0
472f2723
KH		 3497 && !(lower_half_easy_p && upper_half_easy_p)
3498 && !(code == IOR && w1 == 0xffff
3499 && (w0 & 0x8000) != 0 && lower_half_easy_p))
40367e2d 3500 {
beed8fc0
AO		 3501 length = h8300_length_from_table (operands[1], operands[2],
3502 &logicl_length_table);
40367e2d
KH		 3503 }
3504 else
3505 {
3506 /* Take care of the lower and upper words individually. For
3507 each word, we try different methods in the order of
3508
3509 1) the special insn (in case of AND or XOR),
3510 2) the word-wise insn, and
3511 3) The byte-wise insn. */
c5e7ce43 3512 if (w0 == 0xffff
40367e2d
KH		 3513 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3514 {
3515 length += 2;
3516 }
3517 else if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 3518 && (b0 != 0)
3519 && (b1 != 0))
40367e2d
KH		 3520 {
3521 length += 4;
3522 }
3523 else
3524 {
c5e7ce43 3525 if (b0 != 0)
40367e2d
KH		 3526 length += 2;
3527
c5e7ce43 3528 if (b1 != 0)
40367e2d
KH		 3529 length += 2;
3530 }
3531
c5e7ce43 3532 if (w1 == 0xffff
40367e2d
KH		 3533 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3534 {
3535 length += 2;
3536 }
472f2723
KH		 3537 else if ((TARGET_H8300H || TARGET_H8300S)
3538 && code == IOR
3539 && w1 == 0xffff
3540 && (w0 & 0x8000) != 0)
3541 {
3542 length += 2;
3543 }
a6e8d113
KH		 3544 else if ((TARGET_H8300H || TARGET_H8300S)
3545 && code == AND
c5e7ce43 3546 && w1 == 0xff00)
a6e8d113
KH		 3547 {
3548 length += 2;
3549 }
40367e2d
KH		 3550 else if (TARGET_H8300H || TARGET_H8300S)
3551 {
c5e7ce43 3552 if (w1 != 0)
40367e2d
KH		 3553 length += 4;
3554 }
3555 else
3556 {
c5e7ce43 3557 if (b2 != 0)
40367e2d
KH		 3558 length += 2;
3559
c5e7ce43 3560 if (b3 != 0)
40367e2d
KH		 3561 length += 2;
3562 }
3563 }
3564 break;
3565 default:
8c440872 3566 gcc_unreachable ();
40367e2d
KH		 3567 }
3568 return length;
3569}
b42cff6b 3570
e9eba255
KH		 3571/* Compute which flag bits are valid after a logical insn. */
3572
9690aa8e 3573enum attr_cc
cb713a8d 3574compute_logical_op_cc (enum machine_mode mode, rtx *operands)
b42cff6b
KH		 3575{
3576 /* Figure out the logical op that we need to perform. */
3577 enum rtx_code code = GET_CODE (operands[3]);
3578 /* Pretend that every byte is affected if both operands are registers. */
7798db98 3579 const unsigned HOST_WIDE_INT intval =
b42cff6b 3580 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
beed8fc0
AO		 3581 /* Always use the full instruction if the
3582 first operand is in memory. It is better
3583 to use define_splits to generate the shorter
3584 sequence where valid. */
3585 && register_operand (operands[1], VOIDmode)
b42cff6b
KH		 3586 ? INTVAL (operands[2]) : 0x55555555);
3587 /* The determinant of the algorithm. If we perform an AND, 0
3588 affects a bit. Otherwise, 1 affects a bit. */
7798db98 3589 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
f9ac2f95
KH		 3590 /* Break up DET into pieces. */
3591 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3592 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3593 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3594 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3595 int lower_half_easy_p = 0;
3596 int upper_half_easy_p = 0;
b42cff6b
KH		 3597 /* Condition code. */
3598 enum attr_cc cc = CC_CLOBBER;
3599
3600 switch (mode)
3601 {
3602 case HImode:
3603 /* First, see if we can finish with one insn. */
3604 if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 3605 && b0 != 0
3606 && b1 != 0)
b42cff6b
KH		 3607 {
3608 cc = CC_SET_ZNV;
3609 }
3610 break;
3611 case SImode:
f9ac2f95
KH		 3612 if (TARGET_H8300H || TARGET_H8300S)
3613 {
3614 /* Determine if the lower half can be taken care of in no more
3615 than two bytes. */
3616 lower_half_easy_p = (b0 == 0
3617 || b1 == 0
3618 || (code != IOR && w0 == 0xffff));
3619
3620 /* Determine if the upper half can be taken care of in no more
3621 than two bytes. */
3622 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3623 || (code == AND && w1 == 0xff00));
3624 }
b42cff6b 3625
f9ac2f95
KH		 3626 /* Check if doing everything with one insn is no worse than
3627 using multiple insns. */
b42cff6b 3628 if ((TARGET_H8300H || TARGET_H8300S)
f9ac2f95 3629 && w0 != 0 && w1 != 0
472f2723
KH		 3630 && !(lower_half_easy_p && upper_half_easy_p)
3631 && !(code == IOR && w1 == 0xffff
3632 && (w0 & 0x8000) != 0 && lower_half_easy_p))
b42cff6b
KH		 3633 {
3634 cc = CC_SET_ZNV;
3635 }
472f2723
KH		 3636 else
3637 {
3638 if ((TARGET_H8300H || TARGET_H8300S)
3639 && code == IOR
3640 && w1 == 0xffff
3641 && (w0 & 0x8000) != 0)
3642 {
3643 cc = CC_SET_ZNV;
3644 }
3645 }
b42cff6b
KH		 3646 break;
3647 default:
8c440872 3648 gcc_unreachable ();
b42cff6b
KH		 3649 }
3650 return cc;
3651}
366a7b27 3652\f
8981ecd3
KH		 3653/* Expand a conditional branch. */
3654
3655void
f90b7a5a 3656h8300_expand_branch (rtx operands[])
8981ecd3 3657{
f90b7a5a
PB		 3658 enum rtx_code code = GET_CODE (operands[0]);
3659 rtx op0 = operands[1];
3660 rtx op1 = operands[2];
3661 rtx label = operands[3];
8981ecd3
KH		 3662 rtx tmp;
3663
f90b7a5a
PB		 3664 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3665 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3666
8981ecd3
KH		 3667 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
3668 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
3669 gen_rtx_LABEL_REF (VOIDmode, label),
3670 pc_rtx);
3671 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
3672}
f90b7a5a
PB		 3673
3674
3675/* Expand a conditional store. */
3676
3677void
3678h8300_expand_store (rtx operands[])
3679{
3680 rtx dest = operands[0];
3681 enum rtx_code code = GET_CODE (operands[1]);
3682 rtx op0 = operands[2];
3683 rtx op1 = operands[3];
3684 rtx tmp;
3685
3686 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3687 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3688
3689 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx);
3690 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
3691}
8981ecd3 3692\f
48837e29
DE		 3693/* Shifts.
3694
005e3e05
KH		 3695 We devote a fair bit of code to getting efficient shifts since we
3696 can only shift one bit at a time on the H8/300 and H8/300H and only
3db11b5c 3697 one or two bits at a time on the H8S.
005e3e05
KH		 3698
3699 All shift code falls into one of the following ways of
3700 implementation:
3701
3702 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3703 when a straight line shift is about the same size or smaller than
3704 a loop.
3705
3706 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3707 off the bits we don't need. This is used when only a few of the
3708 bits in the original value will survive in the shifted value.
3709
3710 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3711 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3712 shifts can be added if the shift count is slightly more than 8 or
3713 16. This case also includes other oddballs that are not worth
f411c849 3714 explaining here.
005e3e05 3715
3db11b5c 3716 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
005e3e05 3717
5ec0b66e
KH		 3718 For each shift count, we try to use code that has no trade-off
3719 between code size and speed whenever possible.
3720
3721 If the trade-off is unavoidable, we try to be reasonable.
3722 Specifically, the fastest version is one instruction longer than
3723 the shortest version, we take the fastest version. We also provide
3724 the use a way to switch back to the shortest version with -Os.
3725
3726 For the details of the shift algorithms for various shift counts,
3727 refer to shift_alg_[qhs]i. */
07aae5c2 3728
beed8fc0
AO		 3729/* Classify a shift with the given mode and code. OP is the shift amount. */
3730
3731enum h8sx_shift_type
3732h8sx_classify_shift (enum machine_mode mode, enum rtx_code code, rtx op)
3733{
3734 if (!TARGET_H8300SX)
3735 return H8SX_SHIFT_NONE;
3736
3737 switch (code)
3738 {
3739 case ASHIFT:
3740 case LSHIFTRT:
3741 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3742 if (GET_CODE (op) != CONST_INT)
3743 return H8SX_SHIFT_BINARY;
3744
3745 /* Reject out-of-range shift amounts. */
3746 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
3747 return H8SX_SHIFT_NONE;
3748
3749 /* Power-of-2 shifts are effectively unary operations. */
3750 if (exact_log2 (INTVAL (op)) >= 0)
3751 return H8SX_SHIFT_UNARY;
3752
3753 return H8SX_SHIFT_BINARY;
3754
3755 case ASHIFTRT:
3756 if (op == const1_rtx || op == const2_rtx)
3757 return H8SX_SHIFT_UNARY;
3758 return H8SX_SHIFT_NONE;
3759
3760 case ROTATE:
3761 if (GET_CODE (op) == CONST_INT
3762 && (INTVAL (op) == 1
3763 || INTVAL (op) == 2
3764 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
3765 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
3766 return H8SX_SHIFT_UNARY;
3767 return H8SX_SHIFT_NONE;
3768
3769 default:
3770 return H8SX_SHIFT_NONE;
3771 }
3772}
3773
beed8fc0
AO		 3774/* Return the asm template for a single h8sx shift instruction.
3775 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3776 is the source and OPERANDS[3] is the shift. SUFFIX is the
88cb339e 3777 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
beed8fc0
AO		 3778 prefix for the destination operand. */
3779
3780const char *
3781output_h8sx_shift (rtx *operands, int suffix, int optype)
3782{
3783 static char buffer[16];
3784 const char *stem;
3785
3786 switch (GET_CODE (operands[3]))
3787 {
3788 case ASHIFT:
3789 stem = "shll";
3790 break;
3791
3792 case ASHIFTRT:
3793 stem = "shar";
3794 break;
3795
3796 case LSHIFTRT:
3797 stem = "shlr";
3798 break;
3799
3800 case ROTATE:
3801 stem = "rotl";
3802 if (INTVAL (operands[2]) > 2)
3803 {
3804 /* This is really a right rotate. */
3805 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
3806 - INTVAL (operands[2]));
3807 stem = "rotr";
3808 }
3809 break;
3810
3811 default:
8c440872 3812 gcc_unreachable ();
beed8fc0
AO		 3813 }
3814 if (operands[2] == const1_rtx)
3815 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
3816 else
3817 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
3818 return buffer;
3819}
48837e29 3820
317d21e9 3821/* Emit code to do shifts. */
48837e29 3822
beed8fc0 3823bool
9690aa8e 3824expand_a_shift (enum machine_mode mode, enum rtx_code code, rtx operands[])
07aae5c2 3825{
beed8fc0
AO		 3826 switch (h8sx_classify_shift (mode, code, operands[2]))
3827 {
3828 case H8SX_SHIFT_BINARY:
3829 operands[1] = force_reg (mode, operands[1]);
3830 return false;
3831
3832 case H8SX_SHIFT_UNARY:
3833 return false;
3834
3835 case H8SX_SHIFT_NONE:
3836 break;
3837 }
3838
bc9b880c 3839 emit_move_insn (copy_rtx (operands[0]), operands[1]);
07aae5c2 3840
07e4d94e
KH		 3841 /* Need a loop to get all the bits we want - we generate the
3842 code at emit time, but need to allocate a scratch reg now. */
48837e29 3843
c5c76735
JL		 3844 emit_insn (gen_rtx_PARALLEL
3845 (VOIDmode,
48837e29 3846 gen_rtvec (2,
bc9b880c 3847 gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
0f4c242b 3848 gen_rtx_fmt_ee (code, mode,
bc9b880c 3849 copy_rtx (operands[0]), operands[2])),
c5c76735
JL		 3850 gen_rtx_CLOBBER (VOIDmode,
3851 gen_rtx_SCRATCH (QImode)))));
beed8fc0 3852 return true;
48837e29
DE		 3853}
3854
48837e29
DE		 3855/* Symbols of the various modes which can be used as indices. */
3856
3857enum shift_mode
1a63219b
KH		 3858{
3859 QIshift, HIshift, SIshift
3860};
48837e29 3861
269c14e1
DE		 3862/* For single bit shift insns, record assembler and what bits of the
3863 condition code are valid afterwards (represented as various CC_FOO
3864 bits, 0 means CC isn't left in a usable state). */
48837e29
DE		 3865
3866struct shift_insn
3867{
8b60264b 3868 const char *const assembler;
9690aa8e 3869 const enum attr_cc cc_valid;
48837e29
DE		 3870};
3871
3872/* Assembler instruction shift table.
3873
3874 These tables are used to look up the basic shifts.
07e4d94e 3875 They are indexed by cpu, shift_type, and mode. */
07aae5c2 3876
48837e29
DE		 3877static const struct shift_insn shift_one[2][3][3] =
3878{
3879/* H8/300 */
3880 {
3881/* SHIFT_ASHIFT */
3882 {
45ca2106
KH		 3883 { "shll\t%X0", CC_SET_ZNV },
3884 { "add.w\t%T0,%T0", CC_SET_ZN },
3885 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
48837e29
DE		 3886 },
3887/* SHIFT_LSHIFTRT */
3888 {
45ca2106
KH		 3889 { "shlr\t%X0", CC_SET_ZNV },
3890 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3891 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
48837e29
DE		 3892 },
3893/* SHIFT_ASHIFTRT */
3894 {
45ca2106
KH		 3895 { "shar\t%X0", CC_SET_ZNV },
3896 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3897 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
48837e29
DE		 3898 }
3899 },
3900/* H8/300H */
3901 {
3902/* SHIFT_ASHIFT */
3903 {
45ca2106
KH		 3904 { "shll.b\t%X0", CC_SET_ZNV },
3905 { "shll.w\t%T0", CC_SET_ZNV },
3906 { "shll.l\t%S0", CC_SET_ZNV }
48837e29
DE		 3907 },
3908/* SHIFT_LSHIFTRT */
3909 {
45ca2106
KH		 3910 { "shlr.b\t%X0", CC_SET_ZNV },
3911 { "shlr.w\t%T0", CC_SET_ZNV },
3912 { "shlr.l\t%S0", CC_SET_ZNV }
48837e29
DE		 3913 },
3914/* SHIFT_ASHIFTRT */
3915 {
45ca2106
KH		 3916 { "shar.b\t%X0", CC_SET_ZNV },
3917 { "shar.w\t%T0", CC_SET_ZNV },
3918 { "shar.l\t%S0", CC_SET_ZNV }
48837e29
DE		 3919 }
3920 }
3921};
07aae5c2 3922
51c0c1d7
JL		 3923static const struct shift_insn shift_two[3][3] =
3924{
3925/* SHIFT_ASHIFT */
3926 {
45ca2106
KH		 3927 { "shll.b\t#2,%X0", CC_SET_ZNV },
3928 { "shll.w\t#2,%T0", CC_SET_ZNV },
3929 { "shll.l\t#2,%S0", CC_SET_ZNV }
51c0c1d7
JL		 3930 },
3931/* SHIFT_LSHIFTRT */
3932 {
45ca2106
KH		 3933 { "shlr.b\t#2,%X0", CC_SET_ZNV },
3934 { "shlr.w\t#2,%T0", CC_SET_ZNV },
3935 { "shlr.l\t#2,%S0", CC_SET_ZNV }
51c0c1d7
JL		 3936 },
3937/* SHIFT_ASHIFTRT */
3938 {
45ca2106
KH		 3939 { "shar.b\t#2,%X0", CC_SET_ZNV },
3940 { "shar.w\t#2,%T0", CC_SET_ZNV },
3941 { "shar.l\t#2,%S0", CC_SET_ZNV }
51c0c1d7
JL		 3942 }
3943};
3944
48837e29
DE		 3945/* Rotates are organized by which shift they'll be used in implementing.
3946 There's no need to record whether the cc is valid afterwards because
3947 it is the AND insn that will decide this. */
07aae5c2 3948
48837e29
DE		 3949static const char *const rotate_one[2][3][3] =
3950{
3951/* H8/300 */
3952 {
3953/* SHIFT_ASHIFT */
3954 {
51c0c1d7
JL		 3955 "rotr\t%X0",
3956 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
48837e29
DE		 3957 0
3958 },
3959/* SHIFT_LSHIFTRT */
3960 {
51c0c1d7
JL		 3961 "rotl\t%X0",
3962 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
48837e29
DE		 3963 0
3964 },
3965/* SHIFT_ASHIFTRT */
3966 {
51c0c1d7
JL		 3967 "rotl\t%X0",
3968 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
48837e29 3969 0
07aae5c2 3970 }
48837e29
DE		 3971 },
3972/* H8/300H */
3973 {
3974/* SHIFT_ASHIFT */
3975 {
51c0c1d7
JL		 3976 "rotr.b\t%X0",
3977 "rotr.w\t%T0",
3978 "rotr.l\t%S0"
48837e29
DE		 3979 },
3980/* SHIFT_LSHIFTRT */
07aae5c2 3981 {
51c0c1d7
JL		 3982 "rotl.b\t%X0",
3983 "rotl.w\t%T0",
3984 "rotl.l\t%S0"
48837e29
DE		 3985 },
3986/* SHIFT_ASHIFTRT */
3987 {
51c0c1d7
JL		 3988 "rotl.b\t%X0",
3989 "rotl.w\t%T0",
3990 "rotl.l\t%S0"
48837e29
DE		 3991 }
3992 }
3993};
3994
51c0c1d7
JL		 3995static const char *const rotate_two[3][3] =
3996{
3997/* SHIFT_ASHIFT */
3998 {
3999 "rotr.b\t#2,%X0",
4000 "rotr.w\t#2,%T0",
4001 "rotr.l\t#2,%S0"
4002 },
4003/* SHIFT_LSHIFTRT */
4004 {
4005 "rotl.b\t#2,%X0",
4006 "rotl.w\t#2,%T0",
4007 "rotl.l\t#2,%S0"
4008 },
4009/* SHIFT_ASHIFTRT */
4010 {
4011 "rotl.b\t#2,%X0",
4012 "rotl.w\t#2,%T0",
4013 "rotl.l\t#2,%S0"
4014 }
4015};
4016
35fb3d1f
KH		 4017struct shift_info {
4018 /* Shift algorithm. */
4019 enum shift_alg alg;
4020
4021 /* The number of bits to be shifted by shift1 and shift2. Valid
4022 when ALG is SHIFT_SPECIAL. */
4023 unsigned int remainder;
4024
4025 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
4026 const char *special;
4027
4028 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
9cd10576 4029 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
35fb3d1f
KH		 4030 const char *shift1;
4031
4032 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
9cd10576 4033 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
35fb3d1f
KH		 4034 const char *shift2;
4035
45ca2106 4036 /* CC status for SHIFT_INLINE. */
9690aa8e 4037 enum attr_cc cc_inline;
45ca2106
KH		 4038
4039 /* CC status for SHIFT_SPECIAL. */
9690aa8e 4040 enum attr_cc cc_special;
35fb3d1f
KH		 4041};
4042
cb713a8d
KH		 4043static void get_shift_alg (enum shift_type,
4044 enum shift_mode, unsigned int,
4045 struct shift_info *);
441d04c6 4046
c009a745
KH		 4047/* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
4048 best algorithm for doing the shift. The assembler code is stored
5ec0b66e
KH		 4049 in the pointers in INFO. We achieve the maximum efficiency in most
4050 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
4051 SImode in particular have a lot of room to optimize.
4052
4053 We first determine the strategy of the shift algorithm by a table
4054 lookup. If that tells us to use a hand crafted assembly code, we
4055 go into the big switch statement to find what that is. Otherwise,
4056 we resort to a generic way, such as inlining. In either case, the
4057 result is returned through INFO. */
48837e29 4058
cb33eb17 4059static void
cb713a8d
KH		 4060get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
4061 unsigned int count, struct shift_info *info)
48837e29 4062{
b9b575e6 4063 enum h8_cpu cpu;
769828ab
KH		 4064
4065 /* Find the target CPU. */
4066 if (TARGET_H8300)
b9b575e6 4067 cpu = H8_300;
769828ab 4068 else if (TARGET_H8300H)
b9b575e6 4069 cpu = H8_300H;
769828ab 4070 else
b9b575e6 4071 cpu = H8_S;
769828ab 4072
96eaf358 4073 /* Find the shift algorithm. */
b9b575e6 4074 info->alg = SHIFT_LOOP;
48837e29
DE		 4075 switch (shift_mode)
4076 {
4077 case QIshift:
b9b575e6 4078 if (count < GET_MODE_BITSIZE (QImode))
96eaf358
KH		 4079 info->alg = shift_alg_qi[cpu][shift_type][count];
4080 break;
769828ab 4081
96eaf358 4082 case HIshift:
b9b575e6 4083 if (count < GET_MODE_BITSIZE (HImode))
96eaf358
KH		 4084 info->alg = shift_alg_hi[cpu][shift_type][count];
4085 break;
4086
4087 case SIshift:
b9b575e6 4088 if (count < GET_MODE_BITSIZE (SImode))
96eaf358
KH		 4089 info->alg = shift_alg_si[cpu][shift_type][count];
4090 break;
4091
4092 default:
8c440872 4093 gcc_unreachable ();
96eaf358
KH		 4094 }
4095
4096 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4097 switch (info->alg)
4098 {
4099 case SHIFT_INLINE:
4100 info->remainder = count;
4101 /* Fall through. */
4102
4103 case SHIFT_LOOP:
4104 /* It is up to the caller to know that looping clobbers cc. */
4105 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4106 info->shift2 = shift_two[shift_type][shift_mode].assembler;
45ca2106 4107 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
96eaf358
KH		 4108 goto end;
4109
4110 case SHIFT_ROT_AND:
4111 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
4112 info->shift2 = rotate_two[shift_type][shift_mode];
45ca2106 4113 info->cc_inline = CC_CLOBBER;
96eaf358
KH		 4114 goto end;
4115
4116 case SHIFT_SPECIAL:
4117 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4118 info->remainder = 0;
4119 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4120 info->shift2 = shift_two[shift_type][shift_mode].assembler;
45ca2106
KH		 4121 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4122 info->cc_special = CC_CLOBBER;
96eaf358
KH		 4123 break;
4124 }
51c0c1d7 4125
96eaf358
KH		 4126 /* Here we only deal with SHIFT_SPECIAL. */
4127 switch (shift_mode)
4128 {
4129 case QIshift:
769828ab
KH		 4130 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4131 through the entire value. */
8c440872
NS		 4132 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
4133 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
4134 goto end;
769828ab
KH		 4135
4136 case HIshift:
769828ab 4137 if (count == 7)
51c0c1d7 4138 {
a77b1dbc 4139 switch (shift_type)
51c0c1d7 4140 {
a77b1dbc
KH		 4141 case SHIFT_ASHIFT:
4142 if (TARGET_H8300)
4143 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4144 else
4145 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
692b7eb3 4146 goto end;
a77b1dbc
KH		 4147 case SHIFT_LSHIFTRT:
4148 if (TARGET_H8300)
4149 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4150 else
4151 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
692b7eb3 4152 goto end;
a77b1dbc 4153 case SHIFT_ASHIFTRT:
35fb3d1f 4154 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
692b7eb3 4155 goto end;
48837e29 4156 }
07aae5c2 4157 }
b30686ec 4158 else if ((8 <= count && count <= 13)
a38b3eea 4159 || (TARGET_H8300S && count == 14))
07aae5c2 4160 {
a7812c0b
KH		 4161 info->remainder = count - 8;
4162
51c0c1d7 4163 switch (shift_type)
48837e29 4164 {
51c0c1d7 4165 case SHIFT_ASHIFT:
35fb3d1f 4166 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
692b7eb3 4167 goto end;
51c0c1d7 4168 case SHIFT_LSHIFTRT:
a7612343
KH		 4169 if (TARGET_H8300)
4170 {
4171 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4172 info->shift1 = "shlr.b\t%s0";
45ca2106 4173 info->cc_inline = CC_SET_ZNV;
a7612343
KH		 4174 }
4175 else
4176 {
4177 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
45ca2106 4178 info->cc_special = CC_SET_ZNV;
a7612343 4179 }
692b7eb3 4180 goto end;
51c0c1d7
JL		 4181 case SHIFT_ASHIFTRT:
4182 if (TARGET_H8300)
a7612343
KH		 4183 {
4184 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4185 info->shift1 = "shar.b\t%s0";
a7612343 4186 }
51c0c1d7 4187 else
a7612343
KH		 4188 {
4189 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
45ca2106 4190 info->cc_special = CC_SET_ZNV;
a7612343 4191 }
692b7eb3 4192 goto end;
51c0c1d7
JL		 4193 }
4194 }
5e98fba2
DD		 4195 else if (count == 14)
4196 {
4197 switch (shift_type)
4198 {
4199 case SHIFT_ASHIFT:
4200 if (TARGET_H8300)
4201 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4202 goto end;
4203 case SHIFT_LSHIFTRT:
4204 if (TARGET_H8300)
4205 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4206 goto end;
4207 case SHIFT_ASHIFTRT:
4208 if (TARGET_H8300)
4209 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4210 else if (TARGET_H8300H)
45ca2106
KH		 4211 {
4212 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4213 info->cc_special = CC_SET_ZNV;
4214 }
5e98fba2 4215 else /* TARGET_H8300S */
8c440872 4216 gcc_unreachable ();
5e98fba2
DD		 4217 goto end;
4218 }
4219 }
1e41e866 4220 else if (count == 15)
51c0c1d7 4221 {
1e41e866
KH		 4222 switch (shift_type)
4223 {
4224 case SHIFT_ASHIFT:
4225 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4226 goto end;
4227 case SHIFT_LSHIFTRT:
4228 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4229 goto end;
4230 case SHIFT_ASHIFTRT:
4231 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4232 goto end;
4233 }
07aae5c2 4234 }
8c440872 4235 gcc_unreachable ();
51c0c1d7 4236
48837e29 4237 case SIshift:
1e41e866 4238 if (TARGET_H8300 && 8 <= count && count <= 9)
48837e29 4239 {
1e41e866
KH		 4240 info->remainder = count - 8;
4241
51c0c1d7 4242 switch (shift_type)
48837e29 4243 {
51c0c1d7 4244 case SHIFT_ASHIFT:
35fb3d1f 4245 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
692b7eb3 4246 goto end;
51c0c1d7 4247 case SHIFT_LSHIFTRT:
35fb3d1f 4248 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
1e41e866 4249 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
692b7eb3 4250 goto end;
51c0c1d7 4251 case SHIFT_ASHIFTRT:
35fb3d1f 4252 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
692b7eb3 4253 goto end;
48837e29 4254 }
48837e29 4255 }
e6bcfef9
JS		 4256 else if (count == 8 && !TARGET_H8300)
4257 {
4258 switch (shift_type)
4259 {
4260 case SHIFT_ASHIFT:
35fb3d1f 4261 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
692b7eb3 4262 goto end;
e6bcfef9 4263 case SHIFT_LSHIFTRT:
35fb3d1f 4264 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
692b7eb3 4265 goto end;
e6bcfef9 4266 case SHIFT_ASHIFTRT:
35fb3d1f 4267 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
692b7eb3 4268 goto end;
e6bcfef9
JS		 4269 }
4270 }
1e41e866
KH		 4271 else if (count == 15 && TARGET_H8300)
4272 {
4273 switch (shift_type)
4274 {
4275 case SHIFT_ASHIFT:
8c440872 4276 gcc_unreachable ();
1e41e866 4277 case SHIFT_LSHIFTRT:
a35abc3c 4278 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
1e41e866
KH		 4279 goto end;
4280 case SHIFT_ASHIFTRT:
a35abc3c 4281 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
1e41e866
KH		 4282 goto end;
4283 }
4284 }
dd69e230
KH		 4285 else if (count == 15 && !TARGET_H8300)
4286 {
4287 switch (shift_type)
4288 {
4289 case SHIFT_ASHIFT:
4290 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
45ca2106 4291 info->cc_special = CC_SET_ZNV;
dd69e230
KH		 4292 goto end;
4293 case SHIFT_LSHIFTRT:
18cf8dda 4294 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
45ca2106 4295 info->cc_special = CC_SET_ZNV;
dd69e230 4296 goto end;
aefc5826 4297 case SHIFT_ASHIFTRT:
8c440872 4298 gcc_unreachable ();
dd69e230
KH		 4299 }
4300 }
1e41e866 4301 else if ((TARGET_H8300 && 16 <= count && count <= 20)
a7812c0b 4302 || (TARGET_H8300H && 16 <= count && count <= 19)
e0f19bd0 4303 || (TARGET_H8300S && 16 <= count && count <= 21))
48837e29 4304 {
a7812c0b
KH		 4305 info->remainder = count - 16;
4306
48837e29
DE		 4307 switch (shift_type)
4308 {
4309 case SHIFT_ASHIFT:
35fb3d1f 4310 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
1e41e866 4311 if (TARGET_H8300)
b30686ec 4312 info->shift1 = "add.w\t%e0,%e0";
692b7eb3 4313 goto end;
51c0c1d7 4314 case SHIFT_LSHIFTRT:
1e41e866
KH		 4315 if (TARGET_H8300)
4316 {
a7612343
KH		 4317 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4318 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
1e41e866
KH		 4319 }
4320 else
4321 {
a7612343 4322 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
45ca2106 4323 info->cc_special = CC_SET_ZNV;
1e41e866 4324 }
692b7eb3 4325 goto end;
51c0c1d7
JL		 4326 case SHIFT_ASHIFTRT:
4327 if (TARGET_H8300)
1e41e866
KH		 4328 {
4329 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4330 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
4331 }
51c0c1d7 4332 else
1e41e866
KH		 4333 {
4334 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
45ca2106 4335 info->cc_special = CC_SET_ZNV;
1e41e866 4336 }
692b7eb3 4337 goto end;
51c0c1d7
JL		 4338 }
4339 }
1e41e866 4340 else if (TARGET_H8300 && 24 <= count && count <= 28)
f9477efd
KH		 4341 {
4342 info->remainder = count - 24;
f0b6f9a6 4343
f9477efd
KH		 4344 switch (shift_type)
4345 {
4346 case SHIFT_ASHIFT:
4347 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4348 info->shift1 = "shll.b\t%z0";
45ca2106 4349 info->cc_inline = CC_SET_ZNV;
f9477efd
KH		 4350 goto end;
4351 case SHIFT_LSHIFTRT:
4352 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4353 info->shift1 = "shlr.b\t%w0";
45ca2106 4354 info->cc_inline = CC_SET_ZNV;
f9477efd
KH		 4355 goto end;
4356 case SHIFT_ASHIFTRT:
4357 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
4358 info->shift1 = "shar.b\t%w0";
45ca2106 4359 info->cc_inline = CC_SET_ZNV;
7f473594
KH		 4360 goto end;
4361 }
4362 }
4a4ae922
KH		 4363 else if ((TARGET_H8300H && count == 24)
4364 || (TARGET_H8300S && 24 <= count && count <= 25))
e6bcfef9 4365 {
4a4ae922
KH		 4366 info->remainder = count - 24;
4367
e6bcfef9
JS		 4368 switch (shift_type)
4369 {
4370 case SHIFT_ASHIFT:
35fb3d1f 4371 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
692b7eb3 4372 goto end;
e6bcfef9 4373 case SHIFT_LSHIFTRT:
35fb3d1f 4374 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
45ca2106 4375 info->cc_special = CC_SET_ZNV;
692b7eb3 4376 goto end;
e6bcfef9 4377 case SHIFT_ASHIFTRT:
35fb3d1f 4378 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
45ca2106 4379 info->cc_special = CC_SET_ZNV;
692b7eb3 4380 goto end;
e6bcfef9
JS		 4381 }
4382 }
1e5bdc40
KH		 4383 else if (!TARGET_H8300 && count == 28)
4384 {
4385 switch (shift_type)
4386 {
4387 case SHIFT_ASHIFT:
4388 if (TARGET_H8300H)
4389 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4390 else
4391 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
1e5bdc40
KH		 4392 goto end;
4393 case SHIFT_LSHIFTRT:
4394 if (TARGET_H8300H)
45ca2106
KH		 4395 {
4396 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4397 info->cc_special = CC_SET_ZNV;
4398 }
1e5bdc40 4399 else
a7612343 4400 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
1e5bdc40
KH		 4401 goto end;
4402 case SHIFT_ASHIFTRT:
8c440872 4403 gcc_unreachable ();
1e5bdc40
KH		 4404 }
4405 }
4406 else if (!TARGET_H8300 && count == 29)
4407 {
4408 switch (shift_type)
4409 {
4410 case SHIFT_ASHIFT:
4411 if (TARGET_H8300H)
4412 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4413 else
4414 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
1e5bdc40
KH		 4415 goto end;
4416 case SHIFT_LSHIFTRT:
4417 if (TARGET_H8300H)
45ca2106
KH		 4418 {
4419 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4420 info->cc_special = CC_SET_ZNV;
4421 }
1e5bdc40 4422 else
45ca2106
KH		 4423 {
4424 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4425 info->cc_special = CC_SET_ZNV;
4426 }
1e5bdc40
KH		 4427 goto end;
4428 case SHIFT_ASHIFTRT:
8c440872 4429 gcc_unreachable ();
1e5bdc40
KH		 4430 }
4431 }
4432 else if (!TARGET_H8300 && count == 30)
4433 {
4434 switch (shift_type)
4435 {
4436 case SHIFT_ASHIFT:
4437 if (TARGET_H8300H)
4438 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4439 else
4440 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
1e5bdc40
KH		 4441 goto end;
4442 case SHIFT_LSHIFTRT:
4443 if (TARGET_H8300H)
a7612343 4444 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
1e5bdc40 4445 else
a7612343 4446 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
1e5bdc40
KH		 4447 goto end;
4448 case SHIFT_ASHIFTRT:
8c440872 4449 gcc_unreachable ();
1e5bdc40
KH		 4450 }
4451 }
48837e29
DE		 4452 else if (count == 31)
4453 {
dd69e230 4454 if (TARGET_H8300)
48837e29 4455 {
dd69e230
KH		 4456 switch (shift_type)
4457 {
4458 case SHIFT_ASHIFT:
4459 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4460 goto end;
4461 case SHIFT_LSHIFTRT:
4462 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4463 goto end;
4464 case SHIFT_ASHIFTRT:
4465 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4466 goto end;
4467 }
48837e29
DE		 4468 }
4469 else
4470 {
dd69e230 4471 switch (shift_type)
48837e29 4472 {
dd69e230
KH		 4473 case SHIFT_ASHIFT:
4474 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
45ca2106 4475 info->cc_special = CC_SET_ZNV;
dd69e230
KH		 4476 goto end;
4477 case SHIFT_LSHIFTRT:
4478 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
45ca2106 4479 info->cc_special = CC_SET_ZNV;
dd69e230
KH		 4480 goto end;
4481 case SHIFT_ASHIFTRT:
a7612343 4482 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
45ca2106 4483 info->cc_special = CC_SET_ZNV;
692b7eb3 4484 goto end;
48837e29 4485 }
48837e29
DE		 4486 }
4487 }
8c440872 4488 gcc_unreachable ();
51c0c1d7 4489
48837e29 4490 default:
8c440872 4491 gcc_unreachable ();
07aae5c2 4492 }
48837e29 4493
cb33eb17
KH		 4494 end:
4495 if (!TARGET_H8300S)
4496 info->shift2 = NULL;
07aae5c2
SC		 4497}
4498
be1e06df
KH		 4499/* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4500 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4501
4502int
cb713a8d 4503h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
be1e06df 4504{
b9b575e6 4505 enum h8_cpu cpu;
be1e06df
KH		 4506 int a, lr, ar;
4507
4508 if (GET_MODE_BITSIZE (mode) <= count)
4509 return 1;
4510
4511 /* Find out the target CPU. */
4512 if (TARGET_H8300)
b9b575e6 4513 cpu = H8_300;
be1e06df 4514 else if (TARGET_H8300H)
b9b575e6 4515 cpu = H8_300H;
be1e06df 4516 else
b9b575e6 4517 cpu = H8_S;
be1e06df
KH		 4518
4519 /* Find the shift algorithm. */
4520 switch (mode)
4521 {
4522 case QImode:
4523 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
4524 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
4525 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
4526 break;
4527
4528 case HImode:
4529 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
4530 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
4531 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
4532 break;
4533
4534 case SImode:
4535 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
4536 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
4537 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
4538 break;
4539
4540 default:
8c440872 4541 gcc_unreachable ();
be1e06df
KH		 4542 }
4543
aa2fb4dd 4544 /* On H8/300H, count == 8 uses a scratch register. */
be1e06df 4545 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
75a3503b 4546 || (TARGET_H8300H && mode == SImode && count == 8));
be1e06df
KH		 4547}
4548
e9eba255 4549/* Output the assembler code for doing shifts. */
48837e29 4550
441d04c6 4551const char *
cb713a8d 4552output_a_shift (rtx *operands)
07aae5c2 4553{
48837e29 4554 static int loopend_lab;
48837e29
DE		 4555 rtx shift = operands[3];
4556 enum machine_mode mode = GET_MODE (shift);
4557 enum rtx_code code = GET_CODE (shift);
4558 enum shift_type shift_type;
4559 enum shift_mode shift_mode;
35fb3d1f 4560 struct shift_info info;
8c440872 4561 int n;
48837e29
DE		 4562
4563 loopend_lab++;
4564
4565 switch (mode)
4566 {
4567 case QImode:
4568 shift_mode = QIshift;
4569 break;
4570 case HImode:
4571 shift_mode = HIshift;
4572 break;
4573 case SImode:
4574 shift_mode = SIshift;
4575 break;
4576 default:
8c440872 4577 gcc_unreachable ();
48837e29 4578 }
07aae5c2 4579
48837e29 4580 switch (code)
07aae5c2 4581 {
48837e29
DE		 4582 case ASHIFTRT:
4583 shift_type = SHIFT_ASHIFTRT;
4584 break;
4585 case LSHIFTRT:
4586 shift_type = SHIFT_LSHIFTRT;
4587 break;
4588 case ASHIFT:
4589 shift_type = SHIFT_ASHIFT;
4590 break;
4591 default:
8c440872 4592 gcc_unreachable ();
48837e29 4593 }
07aae5c2 4594
8c440872
NS		 4595 /* This case must be taken care of by one of the two splitters
4596 that convert a variable shift into a loop. */
4597 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4598
4599 n = INTVAL (operands[2]);
4600
4601 /* If the count is negative, make it 0. */
4602 if (n < 0)
4603 n = 0;
4604 /* If the count is too big, truncate it.
4605 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4606 do the intuitive thing. */
4607 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4608 n = GET_MODE_BITSIZE (mode);
4609
4610 get_shift_alg (shift_type, shift_mode, n, &info);
4611
4612 switch (info.alg)
48837e29 4613 {
8c440872
NS		 4614 case SHIFT_SPECIAL:
4615 output_asm_insn (info.special, operands);
4616 /* Fall through. */
48837e29 4617
8c440872
NS		 4618 case SHIFT_INLINE:
4619 n = info.remainder;
48837e29 4620
8c440872
NS		 4621 /* Emit two bit shifts first. */
4622 if (info.shift2 != NULL)
48837e29 4623 {
8c440872
NS		 4624 for (; n > 1; n -= 2)
4625 output_asm_insn (info.shift2, operands);
4626 }
51c0c1d7 4627
8c440872
NS		 4628 /* Now emit one bit shifts for any residual. */
4629 for (; n > 0; n--)
4630 output_asm_insn (info.shift1, operands);
4631 return "";
4632
4633 case SHIFT_ROT_AND:
4634 {
4635 int m = GET_MODE_BITSIZE (mode) - n;
4636 const int mask = (shift_type == SHIFT_ASHIFT
4637 ? ((1 << m) - 1) << n
4638 : (1 << m) - 1);
4639 char insn_buf[200];
4640
4641 /* Not all possibilities of rotate are supported. They shouldn't
4642 be generated, but let's watch for 'em. */
4643 gcc_assert (info.shift1);
4644
4645 /* Emit two bit rotates first. */
4646 if (info.shift2 != NULL)
48837e29 4647 {
8c440872
NS		 4648 for (; m > 1; m -= 2)
4649 output_asm_insn (info.shift2, operands);
4650 }
4651
4652 /* Now single bit rotates for any residual. */
4653 for (; m > 0; m--)
4654 output_asm_insn (info.shift1, operands);
4655
4656 /* Now mask off the high bits. */
4657 switch (mode)
4658 {
4659 case QImode:
4660 sprintf (insn_buf, "and\t#%d,%%X0", mask);
4661 break;
51c0c1d7 4662
8c440872
NS		 4663 case HImode:
4664 gcc_assert (TARGET_H8300H || TARGET_H8300S);
4665 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
4666 break;
51c0c1d7 4667
8c440872
NS		 4668 default:
4669 gcc_unreachable ();
48837e29 4670 }
b5eaf9ba 4671
8c440872
NS		 4672 output_asm_insn (insn_buf, operands);
4673 return "";
4674 }
b5eaf9ba 4675
8c440872
NS		 4676 case SHIFT_LOOP:
4677 /* A loop to shift by a "large" constant value.
4678 If we have shift-by-2 insns, use them. */
4679 if (info.shift2 != NULL)
4680 {
4681 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
4682 names_big[REGNO (operands[4])]);
4683 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4684 output_asm_insn (info.shift2, operands);
4685 output_asm_insn ("add #0xff,%X4", operands);
4686 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4687 if (n % 2)
4688 output_asm_insn (info.shift1, operands);
4689 }
4690 else
4691 {
4692 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
4693 names_big[REGNO (operands[4])]);
4694 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4695 output_asm_insn (info.shift1, operands);
4696 output_asm_insn ("add #0xff,%X4", operands);
4697 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
51c0c1d7 4698 }
8c440872
NS		 4699 return "";
4700
4701 default:
4702 gcc_unreachable ();
07aae5c2 4703 }
07aae5c2 4704}
86855e8c 4705
0a2aaacc 4706/* Count the number of assembly instructions in a string TEMPL. */
e9eba255 4707
86855e8c 4708static unsigned int
0a2aaacc 4709h8300_asm_insn_count (const char *templ)
86855e8c
KH		 4710{
4711 unsigned int count = 1;
4712
0a2aaacc
KG		 4713 for (; *templ; templ++)
4714 if (*templ == '\n')
86855e8c
KH		 4715 count++;
4716
4717 return count;
4718}
4719
e9eba255
KH		 4720/* Compute the length of a shift insn. */
4721
86855e8c 4722unsigned int
cb713a8d 4723compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
86855e8c
KH		 4724{
4725 rtx shift = operands[3];
4726 enum machine_mode mode = GET_MODE (shift);
4727 enum rtx_code code = GET_CODE (shift);
4728 enum shift_type shift_type;
4729 enum shift_mode shift_mode;
4730 struct shift_info info;
4731 unsigned int wlength = 0;
4732
4733 switch (mode)
4734 {
4735 case QImode:
4736 shift_mode = QIshift;
4737 break;
4738 case HImode:
4739 shift_mode = HIshift;
4740 break;
4741 case SImode:
4742 shift_mode = SIshift;
4743 break;
4744 default:
8c440872 4745 gcc_unreachable ();
86855e8c
KH		 4746 }
4747
4748 switch (code)
4749 {
4750 case ASHIFTRT:
4751 shift_type = SHIFT_ASHIFTRT;
4752 break;
4753 case LSHIFTRT:
4754 shift_type = SHIFT_LSHIFTRT;
4755 break;
4756 case ASHIFT:
4757 shift_type = SHIFT_ASHIFT;
4758 break;
4759 default:
8c440872 4760 gcc_unreachable ();
86855e8c
KH		 4761 }
4762
4763 if (GET_CODE (operands[2]) != CONST_INT)
4764 {
4765 /* Get the assembler code to do one shift. */
4766 get_shift_alg (shift_type, shift_mode, 1, &info);
4767
4768 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
4769 }
4770 else
4771 {
4772 int n = INTVAL (operands[2]);
4773
4774 /* If the count is negative, make it 0. */
4775 if (n < 0)
4776 n = 0;
4777 /* If the count is too big, truncate it.
4778 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4779 do the intuitive thing. */
4780 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4781 n = GET_MODE_BITSIZE (mode);
4782
4783 get_shift_alg (shift_type, shift_mode, n, &info);
4784
4785 switch (info.alg)
4786 {
4787 case SHIFT_SPECIAL:
4788 wlength += h8300_asm_insn_count (info.special);
41c3eb5d
KH		 4789
4790 /* Every assembly instruction used in SHIFT_SPECIAL case
4791 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4792 see xor.l, we just pretend that xor.l counts as two insns
4793 so that the insn length will be computed correctly. */
4794 if (strstr (info.special, "xor.l") != NULL)
4795 wlength++;
4796
86855e8c
KH		 4797 /* Fall through. */
4798
4799 case SHIFT_INLINE:
4800 n = info.remainder;
4801
4802 if (info.shift2 != NULL)
4803 {
4804 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
4805 n = n % 2;
4806 }
4807
4808 wlength += h8300_asm_insn_count (info.shift1) * n;
6b148bd9 4809
86855e8c
KH		 4810 return 2 * wlength;
4811
4812 case SHIFT_ROT_AND:
4813 {
4814 int m = GET_MODE_BITSIZE (mode) - n;
4815
4816 /* Not all possibilities of rotate are supported. They shouldn't
4817 be generated, but let's watch for 'em. */
8c440872 4818 gcc_assert (info.shift1);
86855e8c
KH		 4819
4820 if (info.shift2 != NULL)
4821 {
4822 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
4823 m = m % 2;
4824 }
4825
4826 wlength += h8300_asm_insn_count (info.shift1) * m;
6b148bd9 4827
86855e8c
KH		 4828 /* Now mask off the high bits. */
4829 switch (mode)
4830 {
4831 case QImode:
4832 wlength += 1;
4833 break;
4834 case HImode:
4835 wlength += 2;
4836 break;
4837 case SImode:
8c440872 4838 gcc_assert (!TARGET_H8300);
86855e8c
KH		 4839 wlength += 3;
4840 break;
4841 default:
8c440872 4842 gcc_unreachable ();
86855e8c
KH		 4843 }
4844 return 2 * wlength;
4845 }
4846
4847 case SHIFT_LOOP:
4848 /* A loop to shift by a "large" constant value.
4849 If we have shift-by-2 insns, use them. */
4850 if (info.shift2 != NULL)
4851 {
4852 wlength += 3 + h8300_asm_insn_count (info.shift2);
4853 if (n % 2)
4854 wlength += h8300_asm_insn_count (info.shift1);
4855 }
4856 else
4857 {
4858 wlength += 3 + h8300_asm_insn_count (info.shift1);
4859 }
4860 return 2 * wlength;
4861
4862 default:
8c440872 4863 gcc_unreachable ();
86855e8c
KH		 4864 }
4865 }
4866}
45ca2106 4867
e9eba255
KH		 4868/* Compute which flag bits are valid after a shift insn. */
4869
9690aa8e 4870enum attr_cc
cb713a8d 4871compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
45ca2106
KH		 4872{
4873 rtx shift = operands[3];
4874 enum machine_mode mode = GET_MODE (shift);
4875 enum rtx_code code = GET_CODE (shift);
4876 enum shift_type shift_type;
4877 enum shift_mode shift_mode;
4878 struct shift_info info;
8c440872
NS		 4879 int n;
4880
45ca2106
KH		 4881 switch (mode)
4882 {
4883 case QImode:
4884 shift_mode = QIshift;
4885 break;
4886 case HImode:
4887 shift_mode = HIshift;
4888 break;
4889 case SImode:
4890 shift_mode = SIshift;
4891 break;
4892 default:
8c440872 4893 gcc_unreachable ();
45ca2106
KH		 4894 }
4895
4896 switch (code)
4897 {
4898 case ASHIFTRT:
4899 shift_type = SHIFT_ASHIFTRT;
4900 break;
4901 case LSHIFTRT:
4902 shift_type = SHIFT_LSHIFTRT;
4903 break;
4904 case ASHIFT:
4905 shift_type = SHIFT_ASHIFT;
4906 break;
4907 default:
8c440872 4908 gcc_unreachable ();
45ca2106
KH		 4909 }
4910
8c440872
NS		 4911 /* This case must be taken care of by one of the two splitters
4912 that convert a variable shift into a loop. */
4913 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4914
4915 n = INTVAL (operands[2]);
4916
4917 /* If the count is negative, make it 0. */
4918 if (n < 0)
4919 n = 0;
4920 /* If the count is too big, truncate it.
4921 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4922 do the intuitive thing. */
4923 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4924 n = GET_MODE_BITSIZE (mode);
4925
4926 get_shift_alg (shift_type, shift_mode, n, &info);
4927
4928 switch (info.alg)
45ca2106 4929 {
8c440872
NS		 4930 case SHIFT_SPECIAL:
4931 if (info.remainder == 0)
4932 return info.cc_special;
45ca2106 4933
8c440872 4934 /* Fall through. */
45ca2106 4935
8c440872
NS		 4936 case SHIFT_INLINE:
4937 return info.cc_inline;
4938
4939 case SHIFT_ROT_AND:
4940 /* This case always ends with an and instruction. */
4941 return CC_SET_ZNV;
4942
4943 case SHIFT_LOOP:
4944 /* A loop to shift by a "large" constant value.
4945 If we have shift-by-2 insns, use them. */
4946 if (info.shift2 != NULL)
45ca2106 4947 {
8c440872
NS		 4948 if (n % 2)
4949 return info.cc_inline;
45ca2106 4950 }
8c440872
NS		 4951 return CC_CLOBBER;
4952
4953 default:
4954 gcc_unreachable ();
45ca2106
KH		 4955 }
4956}
48837e29 4957\f
edd71f0f
KH		 4958/* A rotation by a non-constant will cause a loop to be generated, in
4959 which a rotation by one bit is used. A rotation by a constant,
4960 including the one in the loop, will be taken care of by
caf7f21a 4961 output_a_rotate () at the insn emit time. */
edd71f0f
KH		 4962
4963int
3d2e90d6 4964expand_a_rotate (rtx operands[])
edd71f0f
KH		 4965{
4966 rtx dst = operands[0];
4967 rtx src = operands[1];
4968 rtx rotate_amount = operands[2];
4969 enum machine_mode mode = GET_MODE (dst);
edd71f0f 4970
beed8fc0
AO		 4971 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
4972 return false;
4973
edd71f0f
KH		 4974 /* We rotate in place. */
4975 emit_move_insn (dst, src);
4976
4977 if (GET_CODE (rotate_amount) != CONST_INT)
4978 {
4979 rtx counter = gen_reg_rtx (QImode);
4980 rtx start_label = gen_label_rtx ();
4981 rtx end_label = gen_label_rtx ();
4982
4983 /* If the rotate amount is less than or equal to 0,
4984 we go out of the loop. */
a556fd39 4985 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
d43e0b7d 4986 QImode, 0, end_label);
edd71f0f
KH		 4987
4988 /* Initialize the loop counter. */
4989 emit_move_insn (counter, rotate_amount);
4990
4991 emit_label (start_label);
4992
4993 /* Rotate by one bit. */
01ab5574
KH		 4994 switch (mode)
4995 {
4996 case QImode:
4997 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
4998 break;
4999 case HImode:
5000 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
5001 break;
5002 case SImode:
5003 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
5004 break;
5005 default:
8c440872 5006 gcc_unreachable ();
01ab5574 5007 }
edd71f0f
KH		 5008
5009 /* Decrement the counter by 1. */
01ab5574 5010 emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
edd71f0f 5011
9cd10576 5012 /* If the loop counter is nonzero, we go back to the beginning
edd71f0f 5013 of the loop. */
a556fd39 5014 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
d43e0b7d 5015 start_label);
edd71f0f
KH		 5016
5017 emit_label (end_label);
5018 }
5019 else
5020 {
5021 /* Rotate by AMOUNT bits. */
01ab5574
KH		 5022 switch (mode)
5023 {
5024 case QImode:
5025 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
5026 break;
5027 case HImode:
5028 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
5029 break;
5030 case SImode:
5031 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
5032 break;
5033 default:
8c440872 5034 gcc_unreachable ();
01ab5574 5035 }
edd71f0f
KH		 5036 }
5037
5038 return 1;
5039}
5040
e9eba255 5041/* Output a rotate insn. */
edd71f0f
KH		 5042
5043const char *
caf7f21a 5044output_a_rotate (enum rtx_code code, rtx *operands)
edd71f0f
KH		 5045{
5046 rtx dst = operands[0];
5047 rtx rotate_amount = operands[2];
5048 enum shift_mode rotate_mode;
5049 enum shift_type rotate_type;
5050 const char *insn_buf;
5051 int bits;
5052 int amount;
5053 enum machine_mode mode = GET_MODE (dst);
5054
8c440872 5055 gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
edd71f0f
KH		 5056
5057 switch (mode)
5058 {
5059 case QImode:
5060 rotate_mode = QIshift;
5061 break;
5062 case HImode:
5063 rotate_mode = HIshift;
5064 break;
5065 case SImode:
5066 rotate_mode = SIshift;
5067 break;
5068 default:
8c440872 5069 gcc_unreachable ();
edd71f0f
KH		 5070 }
5071
5072 switch (code)
5073 {
5074 case ROTATERT:
5075 rotate_type = SHIFT_ASHIFT;
5076 break;
5077 case ROTATE:
5078 rotate_type = SHIFT_LSHIFTRT;
5079 break;
5080 default:
8c440872 5081 gcc_unreachable ();
edd71f0f
KH		 5082 }
5083
5084 amount = INTVAL (rotate_amount);
5085
5086 /* Clean up AMOUNT. */
5087 if (amount < 0)
5088 amount = 0;
5089 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5090 amount = GET_MODE_BITSIZE (mode);
5091
5092 /* Determine the faster direction. After this phase, amount will be
5093 at most a half of GET_MODE_BITSIZE (mode). */
e0c32c62 5094 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
edd71f0f
KH		 5095 {
5096 /* Flip the direction. */
5097 amount = GET_MODE_BITSIZE (mode) - amount;
5098 rotate_type =
5099 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5100 }
5101
5102 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5103 boost up the rotation. */
5104 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5105 || (mode == HImode && TARGET_H8300H && amount >= 6)
5106 || (mode == HImode && TARGET_H8300S && amount == 8)
5107 || (mode == SImode && TARGET_H8300H && amount >= 10)
5108 || (mode == SImode && TARGET_H8300S && amount >= 13))
5109 {
5110 switch (mode)
5111 {
5112 case HImode:
5113 /* This code works on any family. */
5114 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5115 output_asm_insn (insn_buf, operands);
5116 break;
5117
5118 case SImode:
3db11b5c 5119 /* This code works on the H8/300H and H8S. */
edd71f0f
KH		 5120 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5121 output_asm_insn (insn_buf, operands);
5122 break;
5123
5124 default:
8c440872 5125 gcc_unreachable ();
edd71f0f
KH		 5126 }
5127
5128 /* Adjust AMOUNT and flip the direction. */
5129 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5130 rotate_type =
5131 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5132 }
5133
01ab5574 5134 /* Output rotate insns. */
edd71f0f
KH		 5135 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
5136 {
5137 if (bits == 2)
5138 insn_buf = rotate_two[rotate_type][rotate_mode];
5139 else
5140 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
2c54abce 5141
edd71f0f
KH		 5142 for (; amount >= bits; amount -= bits)
5143 output_asm_insn (insn_buf, operands);
5144 }
5145
5146 return "";
5147}
caf7f21a 5148
e9eba255
KH		 5149/* Compute the length of a rotate insn. */
5150
caf7f21a
KH		 5151unsigned int
5152compute_a_rotate_length (rtx *operands)
5153{
5154 rtx src = operands[1];
343fd2c7 5155 rtx amount_rtx = operands[2];
caf7f21a
KH		 5156 enum machine_mode mode = GET_MODE (src);
5157 int amount;
5158 unsigned int length = 0;
5159
8c440872 5160 gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
caf7f21a 5161
343fd2c7 5162 amount = INTVAL (amount_rtx);
caf7f21a
KH		 5163
5164 /* Clean up AMOUNT. */
5165 if (amount < 0)
5166 amount = 0;
5167 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5168 amount = GET_MODE_BITSIZE (mode);
5169
5170 /* Determine the faster direction. After this phase, amount
5171 will be at most a half of GET_MODE_BITSIZE (mode). */
5172 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5173 /* Flip the direction. */
5174 amount = GET_MODE_BITSIZE (mode) - amount;
5175
5176 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5177 boost up the rotation. */
5178 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5179 || (mode == HImode && TARGET_H8300H && amount >= 6)
5180 || (mode == HImode && TARGET_H8300S && amount == 8)
5181 || (mode == SImode && TARGET_H8300H && amount >= 10)
5182 || (mode == SImode && TARGET_H8300S && amount >= 13))
5183 {
5184 /* Adjust AMOUNT and flip the direction. */
5185 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5186 length += 6;
5187 }
5188
5189 /* We use 2-bit rotations on the H8S. */
5190 if (TARGET_H8300S)
5191 amount = amount / 2 + amount % 2;
5192
5193 /* The H8/300 uses three insns to rotate one bit, taking 6
5194 length. */
5195 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
5196
5197 return length;
5198}
edd71f0f 5199\f
48837e29 5200/* Fix the operands of a gen_xxx so that it could become a bit
2c54abce 5201 operating insn. */
07aae5c2
SC		 5202
5203int
4093985c 5204fix_bit_operand (rtx *operands, enum rtx_code code)
07aae5c2 5205{
abc95ed3 5206 /* The bit_operand predicate accepts any memory during RTL generation, but
48837e29
DE		 5207 only 'U' memory afterwards, so if this is a MEM operand, we must force
5208 it to be valid for 'U' by reloading the address. */
07aae5c2 5209
4093985c
KH		 5210 if (code == AND
5211 ? single_zero_operand (operands[2], QImode)
5212 : single_one_operand (operands[2], QImode))
07aae5c2 5213 {
2e760b15
KH		 5214 /* OK to have a memory dest. */
5215 if (GET_CODE (operands[0]) == MEM
ceaaaeab 5216 && !satisfies_constraint_U (operands[0]))
48837e29 5217 {
2e760b15
KH		 5218 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
5219 copy_to_mode_reg (Pmode,
5220 XEXP (operands[0], 0)));
5221 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5222 operands[0] = mem;
5223 }
48837e29 5224
2e760b15 5225 if (GET_CODE (operands[1]) == MEM
ceaaaeab 5226 && !satisfies_constraint_U (operands[1]))
2e760b15
KH		 5227 {
5228 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
5229 copy_to_mode_reg (Pmode,
5230 XEXP (operands[1], 0)));
5231 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5232 operands[1] = mem;
48837e29 5233 }
2e760b15 5234 return 0;
48837e29 5235 }
07aae5c2 5236
48837e29 5237 /* Dest and src op must be register. */
07aae5c2 5238
48837e29
DE		 5239 operands[1] = force_reg (QImode, operands[1]);
5240 {
5241 rtx res = gen_reg_rtx (QImode);
fd57a6e4 5242 switch (code)
a3579575
KH		 5243 {
5244 case AND:
5245 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
5246 break;
5247 case IOR:
5248 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
5249 break;
5250 case XOR:
5251 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
5252 break;
5253 default:
8c440872 5254 gcc_unreachable ();
a3579575
KH		 5255 }
5256 emit_insn (gen_movqi (operands[0], res));
48837e29
DE		 5257 }
5258 return 1;
07aae5c2 5259}
f5b65a56 5260
f5b65a56
JL		 5261/* Return nonzero if FUNC is an interrupt function as specified
5262 by the "interrupt" attribute. */
5263
5264static int
cb713a8d 5265h8300_interrupt_function_p (tree func)
f5b65a56
JL		 5266{
5267 tree a;
5268
5269 if (TREE_CODE (func) != FUNCTION_DECL)
5270 return 0;
5271
91d231cb 5272 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
f5b65a56
JL		 5273 return a != NULL_TREE;
5274}
5275
3cfa3702
KH		 5276/* Return nonzero if FUNC is a saveall function as specified by the
5277 "saveall" attribute. */
5278
5279static int
5280h8300_saveall_function_p (tree func)
5281{
5282 tree a;
5283
5284 if (TREE_CODE (func) != FUNCTION_DECL)
5285 return 0;
5286
5287 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
5288 return a != NULL_TREE;
5289}
5290
fabe72bb
JL		 5291/* Return nonzero if FUNC is an OS_Task function as specified
5292 by the "OS_Task" attribute. */
5293
5294static int
cb713a8d 5295h8300_os_task_function_p (tree func)
fabe72bb
JL		 5296{
5297 tree a;
5298
5299 if (TREE_CODE (func) != FUNCTION_DECL)
5300 return 0;
5301
91d231cb 5302 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
fabe72bb
JL		 5303 return a != NULL_TREE;
5304}
5305
5306/* Return nonzero if FUNC is a monitor function as specified
5307 by the "monitor" attribute. */
5308
5309static int
cb713a8d 5310h8300_monitor_function_p (tree func)
fabe72bb
JL		 5311{
5312 tree a;
5313
5314 if (TREE_CODE (func) != FUNCTION_DECL)
5315 return 0;
5316
91d231cb 5317 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
fabe72bb
JL		 5318 return a != NULL_TREE;
5319}
5320
f5b65a56
JL		 5321/* Return nonzero if FUNC is a function that should be called
5322 through the function vector. */
5323
5324int
cb713a8d 5325h8300_funcvec_function_p (tree func)
f5b65a56
JL		 5326{
5327 tree a;
5328
5329 if (TREE_CODE (func) != FUNCTION_DECL)
5330 return 0;
5331
91d231cb 5332 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
f5b65a56
JL		 5333 return a != NULL_TREE;
5334}
5335
887a8bd9 5336/* Return nonzero if DECL is a variable that's in the eight bit
15dc331e
JL		 5337 data area. */
5338
5339int
cb713a8d 5340h8300_eightbit_data_p (tree decl)
15dc331e
JL		 5341{
5342 tree a;
5343
5344 if (TREE_CODE (decl) != VAR_DECL)
5345 return 0;
5346
91d231cb 5347 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
15dc331e
JL		 5348 return a != NULL_TREE;
5349}
5350
887a8bd9
JL		 5351/* Return nonzero if DECL is a variable that's in the tiny
5352 data area. */
5353
5354int
cb713a8d 5355h8300_tiny_data_p (tree decl)
887a8bd9
JL		 5356{
5357 tree a;
5358
5359 if (TREE_CODE (decl) != VAR_DECL)
5360 return 0;
5361
91d231cb 5362 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
887a8bd9
JL		 5363 return a != NULL_TREE;
5364}
5365
3cfa3702
KH		 5366/* Generate an 'interrupt_handler' attribute for decls. We convert
5367 all the pragmas to corresponding attributes. */
2c1d2fcb
DD		 5368
5369static void
cb713a8d 5370h8300_insert_attributes (tree node, tree *attributes)
2c1d2fcb 5371{
3cfa3702
KH		 5372 if (TREE_CODE (node) == FUNCTION_DECL)
5373 {
5374 if (pragma_interrupt)
5375 {
5376 pragma_interrupt = 0;
2c1d2fcb 5377
3cfa3702
KH		 5378 /* Add an 'interrupt_handler' attribute. */
5379 *attributes = tree_cons (get_identifier ("interrupt_handler"),
5380 NULL, *attributes);
5381 }
e392d367 5382
3cfa3702
KH		 5383 if (pragma_saveall)
5384 {
5385 pragma_saveall = 0;
5386
5387 /* Add an 'saveall' attribute. */
5388 *attributes = tree_cons (get_identifier ("saveall"),
5389 NULL, *attributes);
5390 }
5391 }
2c1d2fcb
DD		 5392}
5393
91d231cb 5394/* Supported attributes:
f5b65a56 5395
97c5ec1d 5396 interrupt_handler: output a prologue and epilogue suitable for an
f5b65a56
JL		 5397 interrupt handler.
5398
3cfa3702
KH		 5399 saveall: output a prologue and epilogue that saves and restores
5400 all registers except the stack pointer.
5401
97c5ec1d 5402 function_vector: This function should be called through the
887a8bd9
JL		 5403 function vector.
5404
5405 eightbit_data: This variable lives in the 8-bit data area and can
5406 be referenced with 8-bit absolute memory addresses.
5407
5408 tiny_data: This variable lives in the tiny data area and can be
5409 referenced with 16-bit absolute memory references. */
f5b65a56 5410
6bc7bc14 5411static const struct attribute_spec h8300_attribute_table[] =
f5b65a56 5412{
62d784f7
KT		 5413 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
5414 affects_type_identity } */
5415 { "interrupt_handler", 0, 0, true, false, false,
5416 h8300_handle_fndecl_attribute, false },
5417 { "saveall", 0, 0, true, false, false,
5418 h8300_handle_fndecl_attribute, false },
5419 { "OS_Task", 0, 0, true, false, false,
5420 h8300_handle_fndecl_attribute, false },
5421 { "monitor", 0, 0, true, false, false,
5422 h8300_handle_fndecl_attribute, false },
5423 { "function_vector", 0, 0, true, false, false,
5424 h8300_handle_fndecl_attribute, false },
5425 { "eightbit_data", 0, 0, true, false, false,
5426 h8300_handle_eightbit_data_attribute, false },
5427 { "tiny_data", 0, 0, true, false, false,
5428 h8300_handle_tiny_data_attribute, false },
5429 { NULL, 0, 0, false, false, false, NULL, false }
91d231cb 5430};
f5b65a56 5431
15dc331e 5432
91d231cb
JM		 5433/* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5434 struct attribute_spec.handler. */
5435static tree
cb713a8d
KH		 5436h8300_handle_fndecl_attribute (tree *node, tree name,
5437 tree args ATTRIBUTE_UNUSED,
5438 int flags ATTRIBUTE_UNUSED,
5439 bool *no_add_attrs)
91d231cb
JM		 5440{
5441 if (TREE_CODE (*node) != FUNCTION_DECL)
5442 {
29d08eba
JM		 5443 warning (OPT_Wattributes, "%qE attribute only applies to functions",
5444 name);
91d231cb
JM		 5445 *no_add_attrs = true;
5446 }
5447
5448 return NULL_TREE;
5449}
5450
5451/* Handle an "eightbit_data" attribute; arguments as in
5452 struct attribute_spec.handler. */
5453static tree
cb713a8d
KH		 5454h8300_handle_eightbit_data_attribute (tree *node, tree name,
5455 tree args ATTRIBUTE_UNUSED,
5456 int flags ATTRIBUTE_UNUSED,
5457 bool *no_add_attrs)
91d231cb
JM		 5458{
5459 tree decl = *node;
5460
5461 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
15dc331e 5462 {
64378c91 5463 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
91d231cb
JM		 5464 }
5465 else
5466 {
29d08eba
JM		 5467 warning (OPT_Wattributes, "%qE attribute ignored",
5468 name);
91d231cb 5469 *no_add_attrs = true;
887a8bd9
JL		 5470 }
5471
91d231cb
JM		 5472 return NULL_TREE;
5473}
5474
5475/* Handle an "tiny_data" attribute; arguments as in
5476 struct attribute_spec.handler. */
5477static tree
cb713a8d
KH		 5478h8300_handle_tiny_data_attribute (tree *node, tree name,
5479 tree args ATTRIBUTE_UNUSED,
5480 int flags ATTRIBUTE_UNUSED,
5481 bool *no_add_attrs)
91d231cb
JM		 5482{
5483 tree decl = *node;
5484
5485 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
887a8bd9 5486 {
64378c91 5487 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
91d231cb
JM		 5488 }
5489 else
5490 {
29d08eba
JM		 5491 warning (OPT_Wattributes, "%qE attribute ignored",
5492 name);
91d231cb 5493 *no_add_attrs = true;
15dc331e 5494 }
07e4d94e 5495
91d231cb 5496 return NULL_TREE;
f5b65a56
JL		 5497}
5498
dc66a1c4 5499/* Mark function vectors, and various small data objects. */
fb49053f
RH		 5500
5501static void
cb713a8d 5502h8300_encode_section_info (tree decl, rtx rtl, int first)
fb49053f 5503{
dc66a1c4
RH		 5504 int extra_flags = 0;
5505
c6a2438a 5506 default_encode_section_info (decl, rtl, first);
dc66a1c4 5507
fb49053f
RH		 5508 if (TREE_CODE (decl) == FUNCTION_DECL
5509 && h8300_funcvec_function_p (decl))
dc66a1c4 5510 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
fb49053f
RH		 5511 else if (TREE_CODE (decl) == VAR_DECL
5512 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
5513 {
5514 if (h8300_eightbit_data_p (decl))
dc66a1c4 5515 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
fb49053f 5516 else if (first && h8300_tiny_data_p (decl))
dc66a1c4 5517 extra_flags = SYMBOL_FLAG_TINY_DATA;
fb49053f 5518 }
772c5265 5519
dc66a1c4 5520 if (extra_flags)
c6a2438a 5521 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
772c5265
RH		 5522}
5523
e9eba255
KH		 5524/* Output a single-bit extraction. */
5525
441d04c6 5526const char *
cb713a8d 5527output_simode_bld (int bild, rtx operands[])
bd93f126 5528{
6be580c7
KH		 5529 if (TARGET_H8300)
5530 {
5531 /* Clear the destination register. */
5532 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
5533
5534 /* Now output the bit load or bit inverse load, and store it in
5535 the destination. */
5536 if (bild)
5537 output_asm_insn ("bild\t%Z2,%Y1", operands);
5538 else
5539 output_asm_insn ("bld\t%Z2,%Y1", operands);
bd93f126 5540
6be580c7
KH		 5541 output_asm_insn ("bst\t#0,%w0", operands);
5542 }
bd93f126 5543 else
6be580c7 5544 {
0eb933a0
KH		 5545 /* Determine if we can clear the destination first. */
5546 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
5547 && REGNO (operands[0]) != REGNO (operands[1]));
5548
5549 if (clear_first)
5550 output_asm_insn ("sub.l\t%S0,%S0", operands);
5551
6be580c7
KH		 5552 /* Output the bit load or bit inverse load. */
5553 if (bild)
5554 output_asm_insn ("bild\t%Z2,%Y1", operands);
5555 else
5556 output_asm_insn ("bld\t%Z2,%Y1", operands);
5557
0eb933a0
KH		 5558 if (!clear_first)
5559 output_asm_insn ("xor.l\t%S0,%S0", operands);
5560
5561 /* Perform the bit store. */
802a9907 5562 output_asm_insn ("rotxl.l\t%S0", operands);
6be580c7 5563 }
bd93f126
JL		 5564
5565 /* All done. */
5566 return "";
5567}
e6219736 5568
beed8fc0
AO		 5569/* Delayed-branch scheduling is more effective if we have some idea
5570 how long each instruction will be. Use a shorten_branches pass
5571 to get an initial estimate. */
5572
5573static void
5574h8300_reorg (void)
5575{
5576 if (flag_delayed_branch)
5577 shorten_branches (get_insns ());
5578}
5579
ede75ee8 5580#ifndef OBJECT_FORMAT_ELF
7c262518 5581static void
c18a5b6c
MM		 5582h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED,
5583 tree decl)
7c262518
RH		 5584{
5585 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5586 fprintf (asm_out_file, "\t.section %s\n", name);
5587}
ede75ee8 5588#endif /* ! OBJECT_FORMAT_ELF */
803d56f5 5589
7c143ed2
KH		 5590/* Nonzero if X is a constant address suitable as an 8-bit absolute,
5591 which is a special case of the 'R' operand. */
5592
803d56f5 5593int
cb713a8d 5594h8300_eightbit_constant_address_p (rtx x)
803d56f5 5595{
ff482c8d 5596 /* The ranges of the 8-bit area. */
d2d199a3
KH		 5597 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
5598 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
803d56f5
KH		 5599 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
5600 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
5601 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
5602 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
5603
5604 unsigned HOST_WIDE_INT addr;
5605
9675a91e 5606 /* We accept symbols declared with eightbit_data. */
dc66a1c4
RH		 5607 if (GET_CODE (x) == SYMBOL_REF)
5608 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
9675a91e 5609
803d56f5
KH		 5610 if (GET_CODE (x) != CONST_INT)
5611 return 0;
5612
5613 addr = INTVAL (x);
5614
5615 return (0
39ba95b5 5616 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
803d56f5
KH		 5617 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
5618 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
5619}
5620
7c143ed2
KH		 5621/* Nonzero if X is a constant address suitable as an 16-bit absolute
5622 on H8/300H and H8S. */
5623
803d56f5 5624int
cb713a8d 5625h8300_tiny_constant_address_p (rtx x)
803d56f5 5626{
3f7211f1 5627 /* The ranges of the 16-bit area. */
803d56f5
KH		 5628 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
5629 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
5630 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
5631 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
5632 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
5633 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
5634 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
5635 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
5636
5637 unsigned HOST_WIDE_INT addr;
5638
d6456562
KH		 5639 switch (GET_CODE (x))
5640 {
5641 case SYMBOL_REF:
a4bb41cc
KH		 5642 /* In the normal mode, any symbol fits in the 16-bit absolute
5643 address range. We also accept symbols declared with
5644 tiny_data. */
5645 return (TARGET_NORMAL_MODE
5646 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
56b8e164 5647
d6456562
KH		 5648 case CONST_INT:
5649 addr = INTVAL (x);
5650 return (TARGET_NORMAL_MODE
5651 || (TARGET_H8300H
5652 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
5653 || (TARGET_H8300S
5654 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
803d56f5 5655
a4bb41cc
KH		 5656 case CONST:
5657 return TARGET_NORMAL_MODE;
5658
d6456562
KH		 5659 default:
5660 return 0;
5661 }
803d56f5 5662
803d56f5 5663}
9b98dc74 5664
e9eba255
KH		 5665/* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5666 locations that can be accessed as a 16-bit word. */
5667
9b98dc74 5668int
cb713a8d 5669byte_accesses_mergeable_p (rtx addr1, rtx addr2)
9b98dc74
KH		 5670{
5671 HOST_WIDE_INT offset1, offset2;
5672 rtx reg1, reg2;
5673
5674 if (REG_P (addr1))
5675 {
5676 reg1 = addr1;
5677 offset1 = 0;
5678 }
5679 else if (GET_CODE (addr1) == PLUS
5680 && REG_P (XEXP (addr1, 0))
5681 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
5682 {
5683 reg1 = XEXP (addr1, 0);
5684 offset1 = INTVAL (XEXP (addr1, 1));
5685 }
5686 else
5687 return 0;
5688
5689 if (REG_P (addr2))
5690 {
5691 reg2 = addr2;
5692 offset2 = 0;
5693 }
5694 else if (GET_CODE (addr2) == PLUS
5695 && REG_P (XEXP (addr2, 0))
5696 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
5697 {
5698 reg2 = XEXP (addr2, 0);
5699 offset2 = INTVAL (XEXP (addr2, 1));
5700 }
5701 else
5702 return 0;
5703
5704 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
5705 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
5706 && offset1 % 2 == 0
5707 && offset1 + 1 == offset2)
5708 return 1;
5709
5710 return 0;
5711}
02529902
KH		 5712
5713/* Return nonzero if we have the same comparison insn as I3 two insns
19cff4db 5714 before I3. I3 is assumed to be a comparison insn. */
02529902
KH		 5715
5716int
5717same_cmp_preceding_p (rtx i3)
5718{
5719 rtx i1, i2;
5720
5721 /* Make sure we have a sequence of three insns. */
5722 i2 = prev_nonnote_insn (i3);
5723 if (i2 == NULL_RTX)
5724 return 0;
5725 i1 = prev_nonnote_insn (i2);
5726 if (i1 == NULL_RTX)
5727 return 0;
5728
5729 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5730 && any_condjump_p (i2) && onlyjump_p (i2));
5731}
c87ec0ba 5732
c06d5c85
KH		 5733/* Return nonzero if we have the same comparison insn as I1 two insns
5734 after I1. I1 is assumed to be a comparison insn. */
5735
5736int
5737same_cmp_following_p (rtx i1)
5738{
5739 rtx i2, i3;
5740
5741 /* Make sure we have a sequence of three insns. */
5742 i2 = next_nonnote_insn (i1);
5743 if (i2 == NULL_RTX)
5744 return 0;
5745 i3 = next_nonnote_insn (i2);
5746 if (i3 == NULL_RTX)
5747 return 0;
5748
5749 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5750 && any_condjump_p (i2) && onlyjump_p (i2));
5751}
5752
a466bea3 5753/* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
1ae58c30 5754 (or pops) N registers. OPERANDS are assumed to be an array of
a466bea3
KH		 5755 registers. */
5756
5757int
5758h8300_regs_ok_for_stm (int n, rtx operands[])
5759{
5760 switch (n)
5761 {
5762 case 2:
5763 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
5764 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
5765 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
5766 case 3:
5767 return ((REGNO (operands[0]) == 0
5768 && REGNO (operands[1]) == 1
5769 && REGNO (operands[2]) == 2)
5770 || (REGNO (operands[0]) == 4
5771 && REGNO (operands[1]) == 5
5772 && REGNO (operands[2]) == 6));
5773
5774 case 4:
5775 return (REGNO (operands[0]) == 0
5776 && REGNO (operands[1]) == 1
5777 && REGNO (operands[2]) == 2
5778 && REGNO (operands[3]) == 3);
8c440872
NS		 5779 default:
5780 gcc_unreachable ();
a466bea3 5781 }
a466bea3
KH		 5782}
5783
c87ec0ba
NY		 5784/* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5785
5786int
5787h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5788 unsigned int new_reg)
5789{
5790 /* Interrupt functions can only use registers that have already been
5791 saved by the prologue, even if they would normally be
5792 call-clobbered. */
5793
5794 if (h8300_current_function_interrupt_function_p ()
6fb5fa3c 5795 && !df_regs_ever_live_p (new_reg))
c87ec0ba
NY		 5796 return 0;
5797
80e58519 5798 return 1;
c87ec0ba 5799}
d0022200 5800
2e762884
DD		 5801/* Returns true if register REGNO is safe to be allocated as a scratch
5802 register in the current function. */
5803
5804static bool
5805h8300_hard_regno_scratch_ok (unsigned int regno)
5806{
5807 if (h8300_current_function_interrupt_function_p ()
5808 && ! WORD_REG_USED (regno))
5809 return false;
5810
5811 return true;
5812}
5813
5814
d0022200
KH		 5815/* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5816
5817static int
5818h8300_rtx_ok_for_base_p (rtx x, int strict)
5819{
5820 /* Strip off SUBREG if any. */
5821 if (GET_CODE (x) == SUBREG)
5822 x = SUBREG_REG (x);
5823
5824 return (REG_P (x)
5825 && (strict
5826 ? REG_OK_FOR_BASE_STRICT_P (x)
5827 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
5828}
5829
5830/* Return nozero if X is a legitimate address. On the H8/300, a
5831 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5832 CONSTANT_ADDRESS. */
5833
c6c3dba9
PB		 5834static bool
5835h8300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
d0022200
KH		 5836{
5837 /* The register indirect addresses like @er0 is always valid. */
5838 if (h8300_rtx_ok_for_base_p (x, strict))
5839 return 1;
5840
5841 if (CONSTANT_ADDRESS_P (x))
5842 return 1;
5843
beed8fc0
AO		 5844 if (TARGET_H8300SX
5845 && ( GET_CODE (x) == PRE_INC
5846 || GET_CODE (x) == PRE_DEC
5847 || GET_CODE (x) == POST_INC
5848 || GET_CODE (x) == POST_DEC)
5849 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
5850 return 1;
5851
d0022200
KH		 5852 if (GET_CODE (x) == PLUS
5853 && CONSTANT_ADDRESS_P (XEXP (x, 1))
beed8fc0
AO		 5854 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
5855 mode, 0), strict))
d0022200
KH		 5856 return 1;
5857
5858 return 0;
5859}
07ee3b58
KH		 5860
5861/* Worker function for HARD_REGNO_NREGS.
5862
5863 We pretend the MAC register is 32bits -- we don't have any data
5864 types on the H8 series to handle more than 32bits. */
5865
5866int
5867h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, enum machine_mode mode)
5868{
5869 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5870}
5871
5872/* Worker function for HARD_REGNO_MODE_OK. */
5873
5874int
5875h8300_hard_regno_mode_ok (int regno, enum machine_mode mode)
5876{
5877 if (TARGET_H8300)
5878 /* If an even reg, then anything goes. Otherwise the mode must be
5879 QI or HI. */
5880 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
5881 else
5882 /* MAC register can only be of SImode. Otherwise, anything
5883 goes. */
5884 return regno == MAC_REG ? mode == SImode : 1;
5885}
f9b4f8c1
RH		 5886
5887/* Helper function for the move patterns. Make sure a move is legitimate. */
5888
5889bool
5890h8300_move_ok (rtx dest, rtx src)
5891{
5892 rtx addr, other;
5893
5894 /* Validate that at least one operand is a register. */
5895 if (MEM_P (dest))
5896 {
5897 if (MEM_P (src) || CONSTANT_P (src))
5898 return false;
5899 addr = XEXP (dest, 0);
5900 other = src;
5901 }
5902 else if (MEM_P (src))
5903 {
5904 addr = XEXP (src, 0);
5905 other = dest;
5906 }
5907 else
5908 return true;
5909
5910 /* Validate that auto-inc doesn't affect OTHER. */
5911 if (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC)
5912 return true;
5913 addr = XEXP (addr, 0);
5914
5915 if (addr == stack_pointer_rtx)
5916 return register_no_sp_elim_operand (other, VOIDmode);
5917 else
5918 return !reg_overlap_mentioned_p(other, addr);
5919}
6e014ef3 5920\f
c15c90bb
ZW		 5921/* Perform target dependent optabs initialization. */
5922static void
5923h8300_init_libfuncs (void)
5924{
5925 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
5926 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
5927 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
5928 set_optab_libfunc (smod_optab, HImode, "__modhi3");
5929 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
5930}
5931\f
9eaa7740
AS		 5932/* Worker function for TARGET_FUNCTION_VALUE.
5933
5934 On the H8 the return value is in R0/R1. */
5935
5936static rtx
5937h8300_function_value (const_tree ret_type,
5938 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
5939 bool outgoing ATTRIBUTE_UNUSED)
5940{
5941 return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG);
5942}
5943
5944/* Worker function for TARGET_LIBCALL_VALUE.
5945
5946 On the H8 the return value is in R0/R1. */
5947
5948static rtx
5949h8300_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5950{
5951 return gen_rtx_REG (mode, R0_REG);
5952}
5953
5954/* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5955
5956 On the H8, R0 is the only register thus used. */
5957
5958static bool
5959h8300_function_value_regno_p (const unsigned int regno)
5960{
5961 return (regno == R0_REG);
5962}
5963
e9eba255
KH		 5964/* Worker function for TARGET_RETURN_IN_MEMORY. */
5965
34bf1fe3 5966static bool
586de218 5967h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
34bf1fe3
KH		 5968{
5969 return (TYPE_MODE (type) == BLKmode
5970 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
5971}
5972\f
9f6ef043
RH		 5973/* We emit the entire trampoline here. Depending on the pointer size,
5974 we use a different trampoline.
5975
5976 Pmode == HImode
5977 vvvv context
5978 1 0000 7903xxxx mov.w #0x1234,r3
5979 2 0004 5A00xxxx jmp @0x1234
5980 ^^^^ function
5981
5982 Pmode == SImode
5983 vvvvvvvv context
5984 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
5985 3 0006 5Axxxxxx jmp @0x123456
5986 ^^^^^^ function
5987*/
5988
5989static void
5990h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
5991{
5992 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
5993 rtx mem;
5994
5995 if (Pmode == HImode)
5996 {
5997 mem = adjust_address (m_tramp, HImode, 0);
5998 emit_move_insn (mem, GEN_INT (0x7903));
5999 mem = adjust_address (m_tramp, Pmode, 2);
6000 emit_move_insn (mem, cxt);
6001 mem = adjust_address (m_tramp, HImode, 4);
6002 emit_move_insn (mem, GEN_INT (0x5a00));
6003 mem = adjust_address (m_tramp, Pmode, 6);
6004 emit_move_insn (mem, fnaddr);
6005 }
6006 else
6007 {
6008 rtx tem;
6009
6010 mem = adjust_address (m_tramp, HImode, 0);
6011 emit_move_insn (mem, GEN_INT (0x7a03));
6012 mem = adjust_address (m_tramp, Pmode, 2);
6013 emit_move_insn (mem, cxt);
6014
6015 tem = copy_to_reg (fnaddr);
6016 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff)));
6017 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000)));
6018 mem = adjust_address (m_tramp, SImode, 6);
6019 emit_move_insn (mem, tem);
6020 }
6021}
6022\f
6e014ef3
KH		 6023/* Initialize the GCC target structure. */
6024#undef TARGET_ATTRIBUTE_TABLE
6025#define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
6026
6027#undef TARGET_ASM_ALIGNED_HI_OP
6028#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
6029
1bc7c5b6
ZW		 6030#undef TARGET_ASM_FILE_START
6031#define TARGET_ASM_FILE_START h8300_file_start
6032#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
6033#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
6034
6e014ef3
KH		 6035#undef TARGET_ASM_FILE_END
6036#define TARGET_ASM_FILE_END h8300_file_end
6037
88cb339e
N		 6038#undef TARGET_PRINT_OPERAND
6039#define TARGET_PRINT_OPERAND h8300_print_operand
6040#undef TARGET_PRINT_OPERAND_ADDRESS
6041#define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
6042#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
6043#define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
6044
6e014ef3
KH		 6045#undef TARGET_ENCODE_SECTION_INFO
6046#define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
6047
6048#undef TARGET_INSERT_ATTRIBUTES
6049#define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
6050
88cb339e
N		 6051#undef TARGET_REGISTER_MOVE_COST
6052#define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
6053
6e014ef3
KH		 6054#undef TARGET_RTX_COSTS
6055#define TARGET_RTX_COSTS h8300_rtx_costs
6056
c15c90bb
ZW		 6057#undef TARGET_INIT_LIBFUNCS
6058#define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
6059
9eaa7740
AS		 6060#undef TARGET_FUNCTION_VALUE
6061#define TARGET_FUNCTION_VALUE h8300_function_value
6062
6063#undef TARGET_LIBCALL_VALUE
6064#define TARGET_LIBCALL_VALUE h8300_libcall_value
6065
6066#undef TARGET_FUNCTION_VALUE_REGNO_P
6067#define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
6068
34bf1fe3
KH		 6069#undef TARGET_RETURN_IN_MEMORY
6070#define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
6071
56f9413b
NF		 6072#undef TARGET_FUNCTION_ARG
6073#define TARGET_FUNCTION_ARG h8300_function_arg
6074
6075#undef TARGET_FUNCTION_ARG_ADVANCE
6076#define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
6077
beed8fc0
AO		 6078#undef TARGET_MACHINE_DEPENDENT_REORG
6079#define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
6080
2e762884
DD		 6081#undef TARGET_HARD_REGNO_SCRATCH_OK
6082#define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
6083
c6c3dba9
PB		 6084#undef TARGET_LEGITIMATE_ADDRESS_P
6085#define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
6086
7b5cbb57
AS		 6087#undef TARGET_CAN_ELIMINATE
6088#define TARGET_CAN_ELIMINATE h8300_can_eliminate
6089
5efd84c5
NF		 6090#undef TARGET_CONDITIONAL_REGISTER_USAGE
6091#define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
6092
9f6ef043
RH		 6093#undef TARGET_TRAMPOLINE_INIT
6094#define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6095
c5387660
JM		 6096#undef TARGET_OPTION_OVERRIDE
6097#define TARGET_OPTION_OVERRIDE h8300_option_override
6098
f52d97da
AS		 6099#undef TARGET_MODE_DEPENDENT_ADDRESS_P
6100#define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6101
6e014ef3 6102struct gcc_target targetm = TARGET_INITIALIZER;
Mirror of https://gcc.gnu.org/git/gcc.git