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hash-map-traits.h (simple_hashmap_traits::key_type): New typedef.
[thirdparty/gcc.git] / gcc / config / h8300 / h8300.c
CommitLineData
340f6494 1/* Subroutines for insn-output.c for Renesas H8/300.
5624e564 2 Copyright (C) 1992-2015 Free Software Foundation, Inc.
48837e29
DE		 3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
07aae5c2 5
8aa063fb 6This file is part of GCC.
07aae5c2 7
8aa063fb 8GCC is free software; you can redistribute it and/or modify
07aae5c2 9it under the terms of the GNU General Public License as published by
2f83c7d6 10the Free Software Foundation; either version 3, or (at your option)
07aae5c2
SC		 11any later version.
12
8aa063fb 13GCC is distributed in the hope that it will be useful,
07aae5c2
SC		 14but WITHOUT ANY WARRANTY; without even the implied warranty of
15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
2f83c7d6
NC		 19along with GCC; see the file COPYING3. If not see
20<http://www.gnu.org/licenses/>. */
07aae5c2 21
07aae5c2 22#include "config.h"
c5c76735 23#include "system.h"
4977bab6
ZW		 24#include "coretypes.h"
25#include "tm.h"
07aae5c2 26#include "rtl.h"
40e23961
MC		 27#include "alias.h"
28#include "symtab.h"
bf6bb899 29#include "tree.h"
d8a2d370
DN		 30#include "stor-layout.h"
31#include "varasm.h"
32#include "calls.h"
33#include "stringpool.h"
07aae5c2
SC		 34#include "regs.h"
35#include "hard-reg-set.h"
07aae5c2
SC		 36#include "insn-config.h"
37#include "conditions.h"
07aae5c2
SC		 38#include "output.h"
39#include "insn-attr.h"
40#include "flags.h"
41#include "recog.h"
bf6bb899 42#include "function.h"
36566b39
PK		 43#include "expmed.h"
44#include "dojump.h"
45#include "explow.h"
46#include "emit-rtl.h"
47#include "stmt.h"
48#include "expr.h"
b0710fe1 49#include "insn-codes.h"
c15c90bb 50#include "optabs.h"
718f9c0f 51#include "diagnostic-core.h"
39dabefd 52#include "c-family/c-pragma.h" /* ??? */
441d04c6 53#include "tm_p.h"
ceaaaeab 54#include "tm-constrs.h"
672a6f42
NB		 55#include "target.h"
56#include "target-def.h"
60393bbc
AM		 57#include "dominance.h"
58#include "cfg.h"
59#include "cfgrtl.h"
60#include "cfganal.h"
61#include "lcm.h"
62#include "cfgbuild.h"
63#include "cfgcleanup.h"
64#include "predict.h"
65#include "basic-block.h"
9690aa8e 66#include "df.h"
9b2b7279 67#include "builtins.h"
07aae5c2 68
beed8fc0
AO		 69/* Classifies a h8300_src_operand or h8300_dst_operand.
70
71 H8OP_IMMEDIATE
72 A constant operand of some sort.
73
74 H8OP_REGISTER
75 An ordinary register.
76
77 H8OP_MEM_ABSOLUTE
78 A memory reference with a constant address.
79
80 H8OP_MEM_BASE
81 A memory reference with a register as its address.
82
83 H8OP_MEM_COMPLEX
84 Some other kind of memory reference. */
85enum h8300_operand_class
86{
87 H8OP_IMMEDIATE,
88 H8OP_REGISTER,
89 H8OP_MEM_ABSOLUTE,
90 H8OP_MEM_BASE,
91 H8OP_MEM_COMPLEX,
92 NUM_H8OPS
93};
94
beed8fc0
AO		 95/* For a general two-operand instruction, element [X][Y] gives
96 the length of the opcode fields when the first operand has class
97 (X + 1) and the second has class Y. */
98typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
99
07aae5c2 100/* Forward declarations. */
cb713a8d
KH		 101static const char *byte_reg (rtx, int);
102static int h8300_interrupt_function_p (tree);
3cfa3702 103static int h8300_saveall_function_p (tree);
cb713a8d
KH		 104static int h8300_monitor_function_p (tree);
105static int h8300_os_task_function_p (tree);
c72ea086 106static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool);
e68d4dd1 107static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
cb713a8d 108static unsigned int compute_saved_regs (void);
cb713a8d
KH		 109static const char *cond_string (enum rtx_code);
110static unsigned int h8300_asm_insn_count (const char *);
cb713a8d
KH		 111static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
112static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
113static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
88cb339e
N		 114static void h8300_print_operand_address (FILE *, rtx);
115static void h8300_print_operand (FILE *, rtx, int);
116static bool h8300_print_operand_punct_valid_p (unsigned char code);
ede75ee8 117#ifndef OBJECT_FORMAT_ELF
c18a5b6c 118static void h8300_asm_named_section (const char *, unsigned int, tree);
ede75ee8 119#endif
ef4bddc2 120static int h8300_register_move_cost (machine_mode, reg_class_t, reg_class_t);
cb713a8d
KH		 121static int h8300_and_costs (rtx);
122static int h8300_shift_costs (rtx);
ac447f25 123static void h8300_push_pop (int, int, bool, bool);
beed8fc0
AO		 124static int h8300_stack_offset_p (rtx, int);
125static int h8300_ldm_stm_regno (rtx, int, int, int);
beed8fc0
AO		 126static void h8300_reorg (void);
127static unsigned int h8300_constant_length (rtx);
128static unsigned int h8300_displacement_length (rtx, int);
129static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *);
130static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *);
131static unsigned int h8300_unary_length (rtx);
132static unsigned int h8300_short_immediate_length (rtx);
133static unsigned int h8300_bitfield_length (rtx, rtx);
e7041fcc 134static unsigned int h8300_binary_length (rtx_insn *, const h8300_length_table *);
beed8fc0
AO		 135static bool h8300_short_move_mem_p (rtx, enum rtx_code);
136static unsigned int h8300_move_length (rtx *, const h8300_length_table *);
2e762884 137static bool h8300_hard_regno_scratch_ok (unsigned int);
ef4bddc2 138static rtx h8300_get_index (rtx, machine_mode mode, int *);
f5b65a56 139
48837e29
DE		 140/* CPU_TYPE, says what cpu we're compiling for. */
141int cpu_type;
142
e392d367
KH		 143/* True if a #pragma interrupt has been seen for the current function. */
144static int pragma_interrupt;
07aae5c2
SC		 145
146/* True if a #pragma saveall has been seen for the current function. */
0869f126 147static int pragma_saveall;
07aae5c2 148
441d04c6 149static const char *const names_big[] =
07e4d94e 150{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
48837e29 151
441d04c6 152static const char *const names_extended[] =
07e4d94e 153{ "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
48837e29 154
441d04c6 155static const char *const names_upper_extended[] =
07e4d94e 156{ "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
48837e29
DE		 157
158/* Points to one of the above. */
159/* ??? The above could be put in an array indexed by CPU_TYPE. */
441d04c6 160const char * const *h8_reg_names;
48837e29
DE		 161
162/* Various operations needed by the following, indexed by CPU_TYPE. */
48837e29 163
441d04c6 164const char *h8_push_op, *h8_pop_op, *h8_mov_op;
dc66a1c4 165
beed8fc0
AO		 166/* Value of MOVE_RATIO. */
167int h8300_move_ratio;
672a6f42 168\f
c4dfc70c
DD		 169/* See below where shifts are handled for explanation of this enum. */
170
171enum shift_alg
172{
173 SHIFT_INLINE,
174 SHIFT_ROT_AND,
175 SHIFT_SPECIAL,
176 SHIFT_LOOP
177};
178
179/* Symbols of the various shifts which can be used as indices. */
180
181enum shift_type
182{
183 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
184};
185
186/* Macros to keep the shift algorithm tables small. */
187#define INL SHIFT_INLINE
188#define ROT SHIFT_ROT_AND
189#define LOP SHIFT_LOOP
190#define SPC SHIFT_SPECIAL
191
192/* The shift algorithms for each machine, mode, shift type, and shift
193 count are defined below. The three tables below correspond to
194 QImode, HImode, and SImode, respectively. Each table is organized
f411c849 195 by, in the order of indices, machine, shift type, and shift count. */
c4dfc70c
DD		 196
197static enum shift_alg shift_alg_qi[3][3][8] = {
198 {
199 /* TARGET_H8300 */
200 /* 0 1 2 3 4 5 6 7 */
201 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
202 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
203 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
204 },
205 {
206 /* TARGET_H8300H */
207 /* 0 1 2 3 4 5 6 7 */
208 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
209 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
210 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
211 },
212 {
213 /* TARGET_H8300S */
214 /* 0 1 2 3 4 5 6 7 */
215 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
216 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
217 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
218 }
219};
220
221static enum shift_alg shift_alg_hi[3][3][16] = {
222 {
223 /* TARGET_H8300 */
224 /* 0 1 2 3 4 5 6 7 */
225 /* 8 9 10 11 12 13 14 15 */
226 { INL, INL, INL, INL, INL, INL, INL, SPC,
227 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
228 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
229 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
230 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
231 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
232 },
233 {
234 /* TARGET_H8300H */
235 /* 0 1 2 3 4 5 6 7 */
236 /* 8 9 10 11 12 13 14 15 */
237 { INL, INL, INL, INL, INL, INL, INL, SPC,
238 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
239 { INL, INL, INL, INL, INL, INL, INL, SPC,
240 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
241 { INL, INL, INL, INL, INL, INL, INL, SPC,
242 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
243 },
244 {
245 /* TARGET_H8300S */
246 /* 0 1 2 3 4 5 6 7 */
247 /* 8 9 10 11 12 13 14 15 */
248 { INL, INL, INL, INL, INL, INL, INL, INL,
249 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
250 { INL, INL, INL, INL, INL, INL, INL, INL,
251 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
252 { INL, INL, INL, INL, INL, INL, INL, INL,
253 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
254 }
255};
256
257static enum shift_alg shift_alg_si[3][3][32] = {
258 {
259 /* TARGET_H8300 */
260 /* 0 1 2 3 4 5 6 7 */
261 /* 8 9 10 11 12 13 14 15 */
262 /* 16 17 18 19 20 21 22 23 */
263 /* 24 25 26 27 28 29 30 31 */
264 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
265 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
266 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
267 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
268 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
269 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
270 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
271 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
272 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
273 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
274 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
275 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
276 },
277 {
278 /* TARGET_H8300H */
279 /* 0 1 2 3 4 5 6 7 */
280 /* 8 9 10 11 12 13 14 15 */
281 /* 16 17 18 19 20 21 22 23 */
282 /* 24 25 26 27 28 29 30 31 */
283 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
284 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
285 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
1e5bdc40 286 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
c4dfc70c
DD		 287 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
288 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
289 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
1e5bdc40 290 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
c4dfc70c
DD		 291 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
292 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
293 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
294 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
295 },
296 {
297 /* TARGET_H8300S */
298 /* 0 1 2 3 4 5 6 7 */
299 /* 8 9 10 11 12 13 14 15 */
300 /* 16 17 18 19 20 21 22 23 */
301 /* 24 25 26 27 28 29 30 31 */
302 { INL, INL, INL, INL, INL, INL, INL, INL,
303 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
304 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
1e5bdc40 305 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
c4dfc70c
DD		 306 { INL, INL, INL, INL, INL, INL, INL, INL,
307 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
308 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
1e5bdc40 309 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
c4dfc70c
DD		 310 { INL, INL, INL, INL, INL, INL, INL, INL,
311 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
312 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
313 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
314 }
315};
316
317#undef INL
318#undef ROT
319#undef LOP
320#undef SPC
321
322enum h8_cpu
323{
324 H8_300,
325 H8_300H,
326 H8_S
327};
328
48837e29
DE		 329/* Initialize various cpu specific globals at start up. */
330
c5387660
JM		 331static void
332h8300_option_override (void)
48837e29 333{
cbf1b2da
KH		 334 static const char *const h8_push_ops[2] = { "push" , "push.l" };
335 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
336 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
337
f4ea8112
SKS		 338#ifndef OBJECT_FORMAT_ELF
339 if (TARGET_H8300SX)
340 {
341 error ("-msx is not supported in coff");
342 target_flags |= MASK_H8300S;
343 }
344#endif
345
48837e29
DE		 346 if (TARGET_H8300)
347 {
348 cpu_type = (int) CPU_H8300;
349 h8_reg_names = names_big;
350 }
351 else
352 {
3db11b5c 353 /* For this we treat the H8/300H and H8S the same. */
48837e29
DE		 354 cpu_type = (int) CPU_H8300H;
355 h8_reg_names = names_extended;
356 }
357 h8_push_op = h8_push_ops[cpu_type];
358 h8_pop_op = h8_pop_ops[cpu_type];
359 h8_mov_op = h8_mov_ops[cpu_type];
17f0f8fa
KH		 360
361 if (!TARGET_H8300S && TARGET_MAC)
400500c4 362 {
c725bd79 363 error ("-ms2600 is used without -ms");
5463c726 364 target_flags |= MASK_H8300S_1;
400500c4 365 }
920e86b8 366
39ba95b5
VK		 367 if (TARGET_H8300 && TARGET_NORMAL_MODE)
368 {
f4ea8112 369 error ("-mn is used without -mh or -ms or -msx");
39ba95b5
VK		 370 target_flags ^= MASK_NORMAL_MODE;
371 }
c4dfc70c 372
f4ea8112
SKS		 373 if (! TARGET_H8300S && TARGET_EXR)
374 {
375 error ("-mexr is used without -ms");
376 target_flags |= MASK_H8300S_1;
377 }
378
379 if (TARGET_H8300 && TARGET_INT32)
380 {
381 error ("-mint32 is not supported for H8300 and H8300L targets");
382 target_flags ^= MASK_INT32;
383 }
384
385 if ((!TARGET_H8300S && TARGET_EXR) && (!TARGET_H8300SX && TARGET_EXR))
386 {
387 error ("-mexr is used without -ms or -msx");
388 target_flags |= MASK_H8300S_1;
389 }
390
391 if ((!TARGET_H8300S && TARGET_NEXR) && (!TARGET_H8300SX && TARGET_NEXR))
392 {
393 warning (OPT_mno_exr, "-mno-exr valid only with -ms or -msx \
394 - Option ignored!");
395 }
396
2f6bd6eb
YS		 397#ifdef H8300_LINUX
398 if ((TARGET_NORMAL_MODE))
399 {
400 error ("-mn is not supported for linux targets");
401 target_flags ^= MASK_NORMAL_MODE;
402 }
403#endif
404
8bd06267 405 /* Some of the shifts are optimized for speed by default.
c4dfc70c 406 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
8bd06267 407 If optimizing for size, change shift_alg for those shift to
c4dfc70c 408 SHIFT_LOOP. */
b6894857 409 if (optimize_size)
c4dfc70c 410 {
b6894857
KH		 411 /* H8/300 */
412 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
413 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
414 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
415 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
c4dfc70c 416
b6894857
KH		 417 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
418 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
c4dfc70c 419
b6894857
KH		 420 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
421 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
c4dfc70c 422
b6894857
KH		 423 /* H8/300H */
424 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
425 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
c4dfc70c 426
b6894857
KH		 427 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
428 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
c4dfc70c 429
b6894857
KH		 430 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
431 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
432 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
433 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
c4dfc70c
DD		 434
435 /* H8S */
b6894857 436 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
c4dfc70c 437 }
beed8fc0
AO		 438
439 /* Work out a value for MOVE_RATIO. */
440 if (!TARGET_H8300SX)
441 {
442 /* Memory-memory moves are quite expensive without the
443 h8sx instructions. */
444 h8300_move_ratio = 3;
445 }
446 else if (flag_omit_frame_pointer)
447 {
448 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
449 sometimes be as short as two individual memory-to-memory moves,
450 but since they use all the call-saved registers, it seems better
451 to allow up to three moves here. */
452 h8300_move_ratio = 4;
453 }
454 else if (optimize_size)
455 {
456 /* In this case we don't use movmd sequences since they tend
457 to be longer than calls to memcpy(). Memory-to-memory
458 moves are cheaper than for !TARGET_H8300SX, so it makes
459 sense to have a slightly higher threshold. */
460 h8300_move_ratio = 4;
461 }
462 else
463 {
464 /* We use movmd sequences for some moves since it can be quicker
465 than calling memcpy(). The sequences will need to save and
466 restore er6 though, so bump up the cost. */
467 h8300_move_ratio = 6;
468 }
0685e770
DD		 469
470 /* This target defaults to strict volatile bitfields. */
36acc1a2 471 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
0685e770 472 flag_strict_volatile_bitfields = 1;
beed8fc0
AO		 473}
474
e9eba255
KH		 475/* Return the byte register name for a register rtx X. B should be 0
476 if you want a lower byte register. B should be 1 if you want an
477 upper byte register. */
478
9c188705 479static const char *
cb713a8d 480byte_reg (rtx x, int b)
07aae5c2 481{
9cbcd983
KH		 482 static const char *const names_small[] = {
483 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
484 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
485 };
07aae5c2 486
8c440872 487 gcc_assert (REG_P (x));
500fc80f 488
07aae5c2
SC		 489 return names_small[REGNO (x) * 2 + b];
490}
491
492/* REGNO must be saved/restored across calls if this macro is true. */
48837e29 493
9cbcd983 494#define WORD_REG_USED(regno) \
d60004ee 495 (regno < SP_REG \
9cbcd983
KH		 496 /* No need to save registers if this function will not return. */ \
497 && ! TREE_THIS_VOLATILE (current_function_decl) \
3cfa3702 498 && (h8300_saveall_function_p (current_function_decl) \
9cbcd983 499 /* Save any call saved register that was used. */ \
6fb5fa3c 500 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
9cbcd983 501 /* Save the frame pointer if it was used. */ \
6fb5fa3c 502 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
9cbcd983 503 /* Save any register used in an interrupt handler. */ \
e392d367 504 || (h8300_current_function_interrupt_function_p () \
6fb5fa3c 505 && df_regs_ever_live_p (regno)) \
9cbcd983
KH		 506 /* Save call clobbered registers in non-leaf interrupt \
507 handlers. */ \
e392d367 508 || (h8300_current_function_interrupt_function_p () \
9cbcd983 509 && call_used_regs[regno] \
416ff32e 510 && !crtl->is_leaf)))
07aae5c2 511
18674659 512/* We use this to wrap all emitted insns in the prologue. */
e7041fcc
DM		 513static rtx_insn *
514F (rtx_insn *x, bool set_it)
18674659 515{
c72ea086
DD		 516 if (set_it)
517 RTX_FRAME_RELATED_P (x) = 1;
18674659
DD		 518 return x;
519}
520
521/* Mark all the subexpressions of the PARALLEL rtx PAR as
522 frame-related. Return PAR.
523
524 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
525 PARALLEL rtx other than the first if they do not have the
526 FRAME_RELATED flag set on them. */
527static rtx
528Fpa (rtx par)
529{
530 int len = XVECLEN (par, 0);
531 int i;
532
533 for (i = 0; i < len; i++)
f698a4b1 534 RTX_FRAME_RELATED_P (XVECEXP (par, 0, i)) = 1;
18674659
DD		 535
536 return par;
537}
538
07aae5c2 539/* Output assembly language to FILE for the operation OP with operand size
48837e29 540 SIZE to adjust the stack pointer. */
48837e29 541
07aae5c2 542static void
c72ea086 543h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue)
07aae5c2 544{
72b1de44
KH		 545 /* If the frame size is 0, we don't have anything to do. */
546 if (size == 0)
f8b58e56 547 return;
72b1de44 548
68ee6df6
KH		 549 /* H8/300 cannot add/subtract a large constant with a single
550 instruction. If a temporary register is available, load the
551 constant to it and then do the addition. */
552 if (TARGET_H8300
553 && size > 4
554 && !h8300_current_function_interrupt_function_p ()
6de9cd9a 555 && !(cfun->static_chain_decl != NULL && sign < 0))
f8f26adc 556 {
68ee6df6 557 rtx r3 = gen_rtx_REG (Pmode, 3);
c72ea086 558 F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue);
18674659 559 F (emit_insn (gen_addhi3 (stack_pointer_rtx,
c72ea086 560 stack_pointer_rtx, r3)), in_prologue);
7b3d4613
KH		 561 }
562 else
563 {
68ee6df6
KH		 564 /* The stack adjustment made here is further optimized by the
565 splitter. In case of H8/300, the splitter always splits the
18674659
DD		 566 addition emitted here to make the adjustment interrupt-safe.
567 FIXME: We don't always tag those, because we don't know what
568 the splitter will do. */
72b1de44 569 if (Pmode == HImode)
18674659 570 {
e7041fcc
DM		 571 rtx_insn *x = emit_insn (gen_addhi3 (stack_pointer_rtx,
572 stack_pointer_rtx,
573 GEN_INT (sign * size)));
18674659 574 if (size < 4)
c72ea086 575 F (x, in_prologue);
18674659 576 }
72b1de44 577 else
18674659 578 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
c72ea086 579 stack_pointer_rtx, GEN_INT (sign * size))), in_prologue);
07aae5c2
SC		 580 }
581}
582
8682223f
KH		 583/* Round up frame size SIZE. */
584
e68d4dd1
UB		 585static HOST_WIDE_INT
586round_frame_size (HOST_WIDE_INT size)
8682223f 587{
489eda65
KH		 588 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
589 & -STACK_BOUNDARY / BITS_PER_UNIT);
8682223f
KH		 590}
591
592/* Compute which registers to push/pop.
593 Return a bit vector of registers. */
594
595static unsigned int
cb713a8d 596compute_saved_regs (void)
8682223f
KH		 597{
598 unsigned int saved_regs = 0;
599 int regno;
600
601 /* Construct a bit vector of registers to be pushed/popped. */
1807b726 602 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
8682223f
KH		 603 {
604 if (WORD_REG_USED (regno))
605 saved_regs |= 1 << regno;
606 }
607
608 /* Don't push/pop the frame pointer as it is treated separately. */
609 if (frame_pointer_needed)
1807b726 610 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
8682223f
KH		 611
612 return saved_regs;
613}
614
68ee6df6 615/* Emit an insn to push register RN. */
8682223f 616
8f1594b2 617static rtx
1901e8d6 618push (int rn, bool in_prologue)
8682223f 619{
68ee6df6
KH		 620 rtx reg = gen_rtx_REG (word_mode, rn);
621 rtx x;
622
513f31eb 623 if (TARGET_H8300)
68ee6df6 624 x = gen_push_h8300 (reg);
f24f0897 625 else if (!TARGET_NORMAL_MODE)
32da7865 626 x = gen_push_h8300hs_advanced (reg);
f24f0897
KH		 627 else
628 x = gen_push_h8300hs_normal (reg);
1901e8d6 629 x = F (emit_insn (x), in_prologue);
9690aa8e 630 add_reg_note (x, REG_INC, stack_pointer_rtx);
8f1594b2 631 return x;
8682223f
KH		 632}
633
68ee6df6 634/* Emit an insn to pop register RN. */
8682223f 635
8f1594b2 636static rtx
cb713a8d 637pop (int rn)
8682223f 638{
68ee6df6
KH		 639 rtx reg = gen_rtx_REG (word_mode, rn);
640 rtx x;
641
513f31eb 642 if (TARGET_H8300)
68ee6df6 643 x = gen_pop_h8300 (reg);
f24f0897 644 else if (!TARGET_NORMAL_MODE)
32da7865 645 x = gen_pop_h8300hs_advanced (reg);
f24f0897
KH		 646 else
647 x = gen_pop_h8300hs_normal (reg);
68ee6df6 648 x = emit_insn (x);
9690aa8e 649 add_reg_note (x, REG_INC, stack_pointer_rtx);
8f1594b2 650 return x;
8682223f 651}
07aae5c2 652
beed8fc0
AO		 653/* Emit an instruction to push or pop NREGS consecutive registers
654 starting at register REGNO. POP_P selects a pop rather than a
655 push and RETURN_P is true if the instruction should return.
656
657 It must be possible to do the requested operation in a single
658 instruction. If NREGS == 1 && !RETURN_P, use a normal push
659 or pop insn. Otherwise emit a parallel of the form:
660
661 (parallel
662 [(return) ;; if RETURN_P
663 (save or restore REGNO)
664 (save or restore REGNO + 1)
665 ...
666 (save or restore REGNO + NREGS - 1)
667 (set sp (plus sp (const_int adjust)))] */
668
669static void
ac447f25 670h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p)
beed8fc0
AO		 671{
672 int i, j;
673 rtvec vec;
18674659 674 rtx sp, offset, x;
beed8fc0
AO		 675
676 /* See whether we can use a simple push or pop. */
677 if (!return_p && nregs == 1)
678 {
679 if (pop_p)
680 pop (regno);
681 else
1901e8d6 682 push (regno, false);
beed8fc0
AO		 683 return;
684 }
685
686 /* We need one element for the return insn, if present, one for each
687 register, and one for stack adjustment. */
ac447f25 688 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1);
beed8fc0
AO		 689 sp = stack_pointer_rtx;
690 i = 0;
691
692 /* Add the return instruction. */
693 if (return_p)
694 {
3810076b 695 RTVEC_ELT (vec, i) = ret_rtx;
beed8fc0
AO		 696 i++;
697 }
698
699 /* Add the register moves. */
700 for (j = 0; j < nregs; j++)
701 {
702 rtx lhs, rhs;
703
704 if (pop_p)
705 {
706 /* Register REGNO + NREGS - 1 is popped first. Before the
707 stack adjustment, its slot is at address @sp. */
708 lhs = gen_rtx_REG (SImode, regno + j);
0a81f074
RS		 709 rhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp,
710 (nregs - j - 1) * 4));
beed8fc0
AO		 711 }
712 else
713 {
714 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
0a81f074 715 lhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, (j + 1) * -4));
beed8fc0
AO		 716 rhs = gen_rtx_REG (SImode, regno + j);
717 }
f7df4a84 718 RTVEC_ELT (vec, i + j) = gen_rtx_SET (lhs, rhs);
beed8fc0
AO		 719 }
720
721 /* Add the stack adjustment. */
722 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
f7df4a84 723 RTVEC_ELT (vec, i + j) = gen_rtx_SET (sp, gen_rtx_PLUS (Pmode, sp, offset));
beed8fc0 724
18674659
DD		 725 x = gen_rtx_PARALLEL (VOIDmode, vec);
726 if (!pop_p)
727 x = Fpa (x);
ac447f25
NC		 728
729 if (return_p)
730 emit_jump_insn (x);
731 else
732 emit_insn (x);
beed8fc0
AO		 733}
734
735/* Return true if X has the value sp + OFFSET. */
736
737static int
738h8300_stack_offset_p (rtx x, int offset)
739{
740 if (offset == 0)
741 return x == stack_pointer_rtx;
742
743 return (GET_CODE (x) == PLUS
744 && XEXP (x, 0) == stack_pointer_rtx
745 && GET_CODE (XEXP (x, 1)) == CONST_INT
746 && INTVAL (XEXP (x, 1)) == offset);
747}
748
749/* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
750 something that may be an ldm or stm instruction. If it fits
751 the required template, return the register it loads or stores,
752 otherwise return -1.
753
754 LOAD_P is true if X should be a load, false if it should be a store.
755 NREGS is the number of registers that the whole instruction is expected
756 to load or store. INDEX is the index of the register that X should
757 load or store, relative to the lowest-numbered register. */
758
759static int
760h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
761{
762 int regindex, memindex, offset;
763
764 if (load_p)
765 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
766 else
767 memindex = 0, regindex = 1, offset = (index + 1) * -4;
768
769 if (GET_CODE (x) == SET
770 && GET_CODE (XEXP (x, regindex)) == REG
771 && GET_CODE (XEXP (x, memindex)) == MEM
772 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
773 return REGNO (XEXP (x, regindex));
774
775 return -1;
776}
777
778/* Return true if the elements of VEC starting at FIRST describe an
779 ldm or stm instruction (LOAD_P says which). */
780
981c7dce 781int
beed8fc0
AO		 782h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
783{
784 rtx last;
785 int nregs, i, regno, adjust;
786
787 /* There must be a stack adjustment, a register move, and at least one
788 other operation (a return or another register move). */
789 if (GET_NUM_ELEM (vec) < 3)
790 return false;
791
792 /* Get the range of registers to be pushed or popped. */
793 nregs = GET_NUM_ELEM (vec) - first - 1;
794 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
795
796 /* Check that the call to h8300_ldm_stm_regno succeeded and
797 that we're only dealing with GPRs. */
798 if (regno < 0 || regno + nregs > 8)
799 return false;
800
801 /* 2-register h8s instructions must start with an even-numbered register.
802 3- and 4-register instructions must start with er0 or er4. */
803 if (!TARGET_H8300SX)
804 {
805 if ((regno & 1) != 0)
806 return false;
807 if (nregs > 2 && (regno & 3) != 0)
808 return false;
809 }
810
811 /* Check the other loads or stores. */
812 for (i = 1; i < nregs; i++)
813 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
814 != regno + i)
815 return false;
816
817 /* Check the stack adjustment. */
818 last = RTVEC_ELT (vec, first + nregs);
819 adjust = (load_p ? nregs : -nregs) * 4;
820 return (GET_CODE (last) == SET
821 && SET_DEST (last) == stack_pointer_rtx
822 && h8300_stack_offset_p (SET_SRC (last), adjust));
823}
824
f0b6f9a6 825/* This is what the stack looks like after the prolog of
07aae5c2
SC		 826 a function with a frame has been set up:
827
48837e29
DE		 828 <args>
829 PC
830 FP <- fp
831 <locals>
8bd06267 832 <saved registers> <- sp
07aae5c2
SC		 833
834 This is what the stack looks like after the prolog of
835 a function which doesn't have a frame:
836
48837e29
DE		 837 <args>
838 PC
839 <locals>
8bd06267 840 <saved registers> <- sp
07aae5c2
SC		 841*/
842
68ee6df6 843/* Generate RTL code for the function prologue. */
8682223f 844
68ee6df6 845void
cb713a8d 846h8300_expand_prologue (void)
07aae5c2 847{
e651d484 848 int regno;
8682223f 849 int saved_regs;
cda4bd43 850 int n_regs;
07aae5c2 851
fabe72bb
JL		 852 /* If the current function has the OS_Task attribute set, then
853 we have a naked prologue. */
854 if (h8300_os_task_function_p (current_function_decl))
68ee6df6 855 return;
fabe72bb
JL		 856
857 if (h8300_monitor_function_p (current_function_decl))
f4ea8112
SKS		 858 /* The monitor function act as normal functions, which means it
859 can accept parameters and return values. In addition to this,
860 interrupts are masked in prologue and return with "rte" in epilogue. */
68ee6df6 861 emit_insn (gen_monitor_prologue ());
fabe72bb 862
48837e29
DE		 863 if (frame_pointer_needed)
864 {
07e4d94e 865 /* Push fp. */
1901e8d6 866 push (HARD_FRAME_POINTER_REGNUM, true);
ac447f25 867 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true);
a1616dd9 868 }
48837e29 869
8682223f
KH		 870 /* Push the rest of the registers in ascending order. */
871 saved_regs = compute_saved_regs ();
e651d484 872 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
cda4bd43 873 {
cda4bd43 874 n_regs = 1;
8682223f 875 if (saved_regs & (1 << regno))
a1616dd9
JL		 876 {
877 if (TARGET_H8300S)
878 {
cda4bd43 879 /* See how many registers we can push at the same time. */
beed8fc0 880 if ((!TARGET_H8300SX || (regno & 3) == 0)
8682223f 881 && ((saved_regs >> regno) & 0x0f) == 0x0f)
cda4bd43
KH		 882 n_regs = 4;
883
beed8fc0 884 else if ((!TARGET_H8300SX || (regno & 3) == 0)
8682223f 885 && ((saved_regs >> regno) & 0x07) == 0x07)
cda4bd43
KH		 886 n_regs = 3;
887
beed8fc0 888 else if ((!TARGET_H8300SX || (regno & 1) == 0)
8682223f 889 && ((saved_regs >> regno) & 0x03) == 0x03)
cda4bd43 890 n_regs = 2;
a1616dd9 891 }
cda4bd43 892
ac447f25 893 h8300_push_pop (regno, n_regs, false, false);
07aae5c2
SC		 894 }
895 }
1807b726
KH		 896
897 /* Leave room for locals. */
c72ea086 898 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
ed1332ee
NC		 899
900 if (flag_stack_usage_info)
901 current_function_static_stack_size
902 = round_frame_size (get_frame_size ())
903 + (__builtin_popcount (saved_regs) * UNITS_PER_WORD)
904 + (frame_pointer_needed ? UNITS_PER_WORD : 0);
07aae5c2
SC		 905}
906
e9eba255
KH		 907/* Return nonzero if we can use "rts" for the function currently being
908 compiled. */
909
68ee6df6 910int
cb713a8d 911h8300_can_use_return_insn_p (void)
68ee6df6
KH		 912{
913 return (reload_completed
914 && !frame_pointer_needed
915 && get_frame_size () == 0
916 && compute_saved_regs () == 0);
917}
07aae5c2 918
68ee6df6
KH		 919/* Generate RTL code for the function epilogue. */
920
921void
cb713a8d 922h8300_expand_epilogue (void)
07aae5c2 923{
e651d484 924 int regno;
8682223f 925 int saved_regs;
cda4bd43 926 int n_regs;
beed8fc0
AO		 927 HOST_WIDE_INT frame_size;
928 bool returned_p;
07aae5c2 929
e392d367 930 if (h8300_os_task_function_p (current_function_decl))
68ee6df6
KH		 931 /* OS_Task epilogues are nearly naked -- they just have an
932 rts instruction. */
933 return;
07aae5c2 934
beed8fc0
AO		 935 frame_size = round_frame_size (get_frame_size ());
936 returned_p = false;
937
1807b726 938 /* Deallocate locals. */
c72ea086 939 h8300_emit_stack_adjustment (1, frame_size, false);
1807b726 940
8682223f
KH		 941 /* Pop the saved registers in descending order. */
942 saved_regs = compute_saved_regs ();
e651d484 943 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
cda4bd43 944 {
cda4bd43 945 n_regs = 1;
8682223f 946 if (saved_regs & (1 << regno))
07aae5c2 947 {
a1616dd9
JL		 948 if (TARGET_H8300S)
949 {
cda4bd43 950 /* See how many registers we can pop at the same time. */
beed8fc0
AO		 951 if ((TARGET_H8300SX || (regno & 3) == 3)
952 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
cda4bd43
KH		 953 n_regs = 4;
954
beed8fc0
AO		 955 else if ((TARGET_H8300SX || (regno & 3) == 2)
956 && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
cda4bd43
KH		 957 n_regs = 3;
958
beed8fc0
AO		 959 else if ((TARGET_H8300SX || (regno & 1) == 1)
960 && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
cda4bd43 961 n_regs = 2;
a1616dd9 962 }
cda4bd43 963
beed8fc0
AO		 964 /* See if this pop would be the last insn before the return.
965 If so, use rte/l or rts/l instead of pop or ldm.l. */
966 if (TARGET_H8300SX
967 && !frame_pointer_needed
968 && frame_size == 0
969 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
970 returned_p = true;
971
ac447f25 972 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p);
07aae5c2 973 }
07aae5c2 974 }
48837e29 975
07e4d94e 976 /* Pop frame pointer if we had one. */
a1616dd9 977 if (frame_pointer_needed)
beed8fc0
AO		 978 {
979 if (TARGET_H8300SX)
980 returned_p = true;
ac447f25 981 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p);
beed8fc0
AO		 982 }
983
984 if (!returned_p)
3810076b 985 emit_jump_insn (ret_rtx);
68ee6df6 986}
a1616dd9 987
e392d367
KH		 988/* Return nonzero if the current function is an interrupt
989 function. */
990
991int
cb713a8d 992h8300_current_function_interrupt_function_p (void)
e392d367 993{
f4ea8112
SKS		 994 return (h8300_interrupt_function_p (current_function_decl));
995}
996
997int
998h8300_current_function_monitor_function_p ()
999{
1000 return (h8300_monitor_function_p (current_function_decl));
e392d367
KH		 1001}
1002
48837e29
DE		 1003/* Output assembly code for the start of the file. */
1004
1bc7c5b6
ZW		 1005static void
1006h8300_file_start (void)
48837e29 1007{
1bc7c5b6 1008 default_file_start ();
8bd06267 1009
2f6bd6eb 1010 if (TARGET_H8300SX)
beed8fc0 1011 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
a1616dd9 1012 else if (TARGET_H8300S)
1bc7c5b6 1013 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
2f6bd6eb
YS		 1014 else if (TARGET_H8300H)
1015 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
48837e29
DE		 1016}
1017
1018/* Output assembly language code for the end of file. */
1019
a5fe455b 1020static void
cb713a8d 1021h8300_file_end (void)
48837e29 1022{
a5fe455b 1023 fputs ("\t.end\n", asm_out_file);
07aae5c2
SC		 1024}
1025\f
3cee1a78
KH		 1026/* Split an add of a small constant into two adds/subs insns.
1027
1028 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1029 instead of adds/subs. */
009ac3d3
RH		 1030
1031void
ef4bddc2 1032split_adds_subs (machine_mode mode, rtx *operands)
3b7d443c 1033{
009ac3d3
RH		 1034 HOST_WIDE_INT val = INTVAL (operands[1]);
1035 rtx reg = operands[0];
9492393e
KH		 1036 HOST_WIDE_INT sign = 1;
1037 HOST_WIDE_INT amount;
590734b6 1038 rtx (*gen_add) (rtx, rtx, rtx);
3b7d443c 1039
9492393e
KH		 1040 /* Force VAL to be positive so that we do not have to consider the
1041 sign. */
1042 if (val < 0)
3b7d443c 1043 {
9492393e
KH		 1044 val = -val;
1045 sign = -1;
1046 }
3b7d443c 1047
3cee1a78
KH		 1048 switch (mode)
1049 {
1050 case HImode:
590734b6 1051 gen_add = gen_addhi3;
3cee1a78
KH		 1052 break;
1053
1054 case SImode:
590734b6 1055 gen_add = gen_addsi3;
3cee1a78
KH		 1056 break;
1057
1058 default:
8c440872 1059 gcc_unreachable ();
3cee1a78
KH		 1060 }
1061
9492393e
KH		 1062 /* Try different amounts in descending order. */
1063 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
1064 amount > 0;
1065 amount /= 2)
1066 {
1a63219b 1067 for (; val >= amount; val -= amount)
590734b6 1068 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
3b7d443c
JL		 1069 }
1070
9492393e 1071 return;
3b7d443c
JL		 1072}
1073
07aae5c2 1074/* Handle machine specific pragmas for compatibility with existing
48837e29 1075 compilers for the H8/300.
07aae5c2 1076
f411c849 1077 pragma saveall generates prologue/epilogue code which saves and
07aae5c2 1078 restores all the registers on function entry.
48837e29 1079
07aae5c2
SC		 1080 pragma interrupt saves and restores all registers, and exits with
1081 an rte instruction rather than an rts. A pointer to a function
1082 with this attribute may be safely used in an interrupt vector. */
48837e29 1083
8b97c5f8 1084void
cb713a8d 1085h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
07aae5c2 1086{
e392d367 1087 pragma_interrupt = 1;
8b97c5f8 1088}
05a81fe5 1089
8b97c5f8 1090void
cb713a8d 1091h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
8b97c5f8
ZW		 1092{
1093 pragma_saveall = 1;
07aae5c2 1094}
8b97c5f8 1095
64bead4c
KH		 1096/* If the next function argument with MODE and TYPE is to be passed in
1097 a register, return a reg RTX for the hard register in which to pass
1098 the argument. CUM represents the state after the last argument.
56f9413b 1099 If the argument is to be pushed, NULL_RTX is returned.
48837e29 1100
56f9413b
NF		 1101 On the H8/300 all normal args are pushed, unless -mquickcall in which
1102 case the first 3 arguments are passed in registers. */
1103
1104static rtx
ef4bddc2 1105h8300_function_arg (cumulative_args_t cum_v, machine_mode mode,
56f9413b 1106 const_tree type, bool named)
07aae5c2 1107{
d5cc9181
JR		 1108 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1109
0ea6f6a0
KH		 1110 static const char *const hand_list[] = {
1111 "__main",
1112 "__cmpsi2",
1113 "__divhi3",
1114 "__modhi3",
1115 "__udivhi3",
1116 "__umodhi3",
1117 "__divsi3",
1118 "__modsi3",
1119 "__udivsi3",
1120 "__umodsi3",
1121 "__mulhi3",
1122 "__mulsi3",
1123 "__reg_memcpy",
1124 "__reg_memset",
1125 "__ucmpsi2",
1126 0,
1127 };
1128
7192cbf1 1129 rtx result = NULL_RTX;
441d04c6 1130 const char *fname;
48837e29
DE		 1131 int regpass = 0;
1132
dd07092e
JL		 1133 /* Never pass unnamed arguments in registers. */
1134 if (!named)
7192cbf1 1135 return NULL_RTX;
dd07092e 1136
48837e29
DE		 1137 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1138 if (TARGET_QUICKCALL)
1139 regpass = 3;
1140
1141 /* If calling hand written assembler, use 4 regs of args. */
48837e29
DE		 1142 if (cum->libcall)
1143 {
441d04c6 1144 const char * const *p;
48837e29
DE		 1145
1146 fname = XSTR (cum->libcall, 0);
1147
1148 /* See if this libcall is one of the hand coded ones. */
48837e29
DE		 1149 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1150 ;
07aae5c2 1151
48837e29
DE		 1152 if (*p)
1153 regpass = 4;
1154 }
1155
1156 if (regpass)
1157 {
1158 int size;
1159
1160 if (mode == BLKmode)
1161 size = int_size_in_bytes (type);
1162 else
1163 size = GET_MODE_SIZE (mode);
1164
15e0e275
KH		 1165 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1166 && cum->nbytes / UNITS_PER_WORD <= 3)
1167 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
48837e29 1168 }
07aae5c2 1169
48837e29
DE		 1170 return result;
1171}
56f9413b
NF		 1172
1173/* Update the data in CUM to advance over an argument
1174 of mode MODE and data type TYPE.
1175 (TYPE is null for libcalls where that information may not be available.) */
1176
1177static void
ef4bddc2 1178h8300_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
56f9413b
NF		 1179 const_tree type, bool named ATTRIBUTE_UNUSED)
1180{
d5cc9181
JR		 1181 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1182
56f9413b
NF		 1183 cum->nbytes += (mode != BLKmode
1184 ? (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD
1185 : (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD);
1186}
1187
48837e29 1188\f
88cb339e
N		 1189/* Implements TARGET_REGISTER_MOVE_COST.
1190
1191 Any SI register-to-register move may need to be reloaded,
1192 so inmplement h8300_register_move_cost to return > 2 so that reload never
1193 shortcuts. */
1194
1195static int
ef4bddc2 1196h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
88cb339e
N		 1197 reg_class_t from, reg_class_t to)
1198{
1199 if (from == MAC_REGS || to == MAC_REG)
1200 return 6;
1201 else
1202 return 3;
1203}
1204
e9eba255
KH		 1205/* Compute the cost of an and insn. */
1206
3c50106f 1207static int
cb713a8d 1208h8300_and_costs (rtx x)
73cc75e9
KH		 1209{
1210 rtx operands[4];
1211
1212 if (GET_MODE (x) == QImode)
1213 return 1;
1214
1215 if (GET_MODE (x) != HImode
1216 && GET_MODE (x) != SImode)
1217 return 100;
1218
1219 operands[0] = NULL;
beed8fc0 1220 operands[1] = XEXP (x, 0);
73cc75e9
KH		 1221 operands[2] = XEXP (x, 1);
1222 operands[3] = x;
4f4ebda3 1223 return compute_logical_op_length (GET_MODE (x), operands) / 2;
73cc75e9
KH		 1224}
1225
e9eba255
KH		 1226/* Compute the cost of a shift insn. */
1227
3c50106f 1228static int
cb713a8d 1229h8300_shift_costs (rtx x)
ae557002
KH		 1230{
1231 rtx operands[4];
1232
1233 if (GET_MODE (x) != QImode
1234 && GET_MODE (x) != HImode
1235 && GET_MODE (x) != SImode)
1236 return 100;
1237
1238 operands[0] = NULL;
1239 operands[1] = NULL;
1240 operands[2] = XEXP (x, 1);
1241 operands[3] = x;
4f4ebda3 1242 return compute_a_shift_length (NULL, operands) / 2;
ae557002 1243}
3c50106f 1244
e9eba255
KH		 1245/* Worker function for TARGET_RTX_COSTS. */
1246
3c50106f 1247static bool
68f932c4
RS		 1248h8300_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
1249 int *total, bool speed)
3c50106f 1250{
beed8fc0
AO		 1251 if (TARGET_H8300SX && outer_code == MEM)
1252 {
1253 /* Estimate the number of execution states needed to calculate
1254 the address. */
1255 if (register_operand (x, VOIDmode)
1256 || GET_CODE (x) == POST_INC
1257 || GET_CODE (x) == POST_DEC
1258 || CONSTANT_P (x))
1259 *total = 0;
1260 else
1261 *total = COSTS_N_INSNS (1);
1262 return true;
1263 }
1264
3c50106f
RH		 1265 switch (code)
1266 {
08dca707
KH		 1267 case CONST_INT:
1268 {
1269 HOST_WIDE_INT n = INTVAL (x);
1270
beed8fc0
AO		 1271 if (TARGET_H8300SX)
1272 {
1273 /* Constant operands need the same number of processor
1274 states as register operands. Although we could try to
f40751dd 1275 use a size-based cost for !speed, the lack of
beed8fc0
AO		 1276 of a mode makes the results very unpredictable. */
1277 *total = 0;
1278 return true;
1279 }
358a11bb 1280 if (-4 <= n && n <= 4)
08dca707
KH		 1281 {
1282 switch ((int) n)
1283 {
1284 case 0:
1285 *total = 0;
1286 return true;
1287 case 1:
1288 case 2:
1289 case -1:
1290 case -2:
1291 *total = 0 + (outer_code == SET);
1292 return true;
1293 case 4:
1294 case -4:
1295 if (TARGET_H8300H || TARGET_H8300S)
1296 *total = 0 + (outer_code == SET);
1297 else
1298 *total = 1;
1299 return true;
1300 }
1301 }
1302 *total = 1;
1303 return true;
1304 }
1305
1306 case CONST:
1307 case LABEL_REF:
1308 case SYMBOL_REF:
beed8fc0
AO		 1309 if (TARGET_H8300SX)
1310 {
1311 /* See comment for CONST_INT. */
1312 *total = 0;
1313 return true;
1314 }
08dca707
KH		 1315 *total = 3;
1316 return true;
1317
1318 case CONST_DOUBLE:
1319 *total = 20;
1320 return true;
1321
f90b7a5a
PB		 1322 case COMPARE:
1323 if (XEXP (x, 1) == const0_rtx)
1324 *total = 0;
1325 return false;
1326
3c50106f 1327 case AND:
beed8fc0
AO		 1328 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
1329 || !h8300_src_operand (XEXP (x, 1), VOIDmode))
1330 return false;
3c50106f
RH		 1331 *total = COSTS_N_INSNS (h8300_and_costs (x));
1332 return true;
1333
1334 /* We say that MOD and DIV are so expensive because otherwise we'll
1335 generate some really horrible code for division of a power of two. */
1336 case MOD:
1337 case DIV:
beed8fc0
AO		 1338 case UMOD:
1339 case UDIV:
1340 if (TARGET_H8300SX)
1341 switch (GET_MODE (x))
1342 {
1343 case QImode:
1344 case HImode:
f40751dd 1345 *total = COSTS_N_INSNS (!speed ? 4 : 10);
beed8fc0
AO		 1346 return false;
1347
1348 case SImode:
f40751dd 1349 *total = COSTS_N_INSNS (!speed ? 4 : 18);
beed8fc0
AO		 1350 return false;
1351
1352 default:
1353 break;
1354 }
1355 *total = COSTS_N_INSNS (12);
3c50106f
RH		 1356 return true;
1357
1358 case MULT:
beed8fc0
AO		 1359 if (TARGET_H8300SX)
1360 switch (GET_MODE (x))
1361 {
1362 case QImode:
1363 case HImode:
1364 *total = COSTS_N_INSNS (2);
1365 return false;
1366
1367 case SImode:
1368 *total = COSTS_N_INSNS (5);
1369 return false;
1370
1371 default:
1372 break;
1373 }
1374 *total = COSTS_N_INSNS (4);
3c50106f
RH		 1375 return true;
1376
1377 case ASHIFT:
1378 case ASHIFTRT:
1379 case LSHIFTRT:
beed8fc0
AO		 1380 if (h8sx_binary_shift_operator (x, VOIDmode))
1381 {
1382 *total = COSTS_N_INSNS (2);
1383 return false;
1384 }
1385 else if (h8sx_unary_shift_operator (x, VOIDmode))
1386 {
1387 *total = COSTS_N_INSNS (1);
1388 return false;
1389 }
3c50106f
RH		 1390 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1391 return true;
1392
1393 case ROTATE:
1394 case ROTATERT:
1395 if (GET_MODE (x) == HImode)
1396 *total = 2;
1397 else
1398 *total = 8;
1399 return true;
1400
1401 default:
beed8fc0
AO		 1402 *total = COSTS_N_INSNS (1);
1403 return false;
3c50106f
RH		 1404 }
1405}
48837e29 1406\f
07aae5c2
SC		 1407/* Documentation for the machine specific operand escapes:
1408
48837e29
DE		 1409 'E' like s but negative.
1410 'F' like t but negative.
1411 'G' constant just the negative
15dc331e
JL		 1412 'R' print operand as a byte:8 address if appropriate, else fall back to
1413 'X' handling.
48837e29 1414 'S' print operand as a long word
07aae5c2 1415 'T' print operand as a word
48837e29
DE		 1416 'V' find the set bit, and print its number.
1417 'W' find the clear bit, and print its number.
1418 'X' print operand as a byte
07aae5c2 1419 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
15dc331e 1420 If this operand isn't a register, fall back to 'R' handling.
48837e29 1421 'Z' print int & 7.
b059c02a 1422 'c' print the opcode corresponding to rtl
da55315a 1423 'e' first word of 32-bit value - if reg, then least reg. if mem
48837e29 1424 then least. if const then most sig word
da55315a 1425 'f' second word of 32-bit value - if reg, then biggest reg. if mem
48837e29 1426 then +2. if const then least sig word
07aae5c2
SC		 1427 'j' print operand as condition code.
1428 'k' print operand as reverse condition code.
beed8fc0
AO		 1429 'm' convert an integer operand to a size suffix (.b, .w or .l)
1430 'o' print an integer without a leading '#'
da55315a
KH		 1431 's' print as low byte of 16-bit value
1432 't' print as high byte of 16-bit value
1433 'w' print as low byte of 32-bit value
1434 'x' print as 2nd byte of 32-bit value
1435 'y' print as 3rd byte of 32-bit value
1436 'z' print as msb of 32-bit value
48837e29 1437*/
07aae5c2
SC		 1438
1439/* Return assembly language string which identifies a comparison type. */
1440
441d04c6 1441static const char *
cb713a8d 1442cond_string (enum rtx_code code)
07aae5c2
SC		 1443{
1444 switch (code)
1445 {
1446 case NE:
1447 return "ne";
1448 case EQ:
1449 return "eq";
1450 case GE:
1451 return "ge";
1452 case GT:
1453 return "gt";
1454 case LE:
1455 return "le";
1456 case LT:
1457 return "lt";
1458 case GEU:
1459 return "hs";
1460 case GTU:
1461 return "hi";
1462 case LEU:
1463 return "ls";
1464 case LTU:
1465 return "lo";
1466 default:
8c440872 1467 gcc_unreachable ();
07aae5c2
SC		 1468 }
1469}
1470
1471/* Print operand X using operand code CODE to assembly language output file
1472 FILE. */
1473
88cb339e
N		 1474static void
1475h8300_print_operand (FILE *file, rtx x, int code)
07aae5c2 1476{
269c14e1 1477 /* This is used for communication between codes V,W,Z and Y. */
07aae5c2
SC		 1478 static int bitint;
1479
1480 switch (code)
1481 {
f46b8378
SKS		 1482 case 'C':
1483 if (h8300_constant_length (x) == 2)
1484 fprintf (file, ":16");
1485 else
1486 fprintf (file, ":32");
1487 return;
48837e29
DE		 1488 case 'E':
1489 switch (GET_CODE (x))
1490 {
1491 case REG:
1492 fprintf (file, "%sl", names_big[REGNO (x)]);
1493 break;
1494 case CONST_INT:
b47900aa 1495 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
48837e29
DE		 1496 break;
1497 default:
8c440872 1498 gcc_unreachable ();
48837e29
DE		 1499 }
1500 break;
1501 case 'F':
1502 switch (GET_CODE (x))
1503 {
1504 case REG:
1505 fprintf (file, "%sh", names_big[REGNO (x)]);
1506 break;
1507 case CONST_INT:
b47900aa 1508 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
48837e29
DE		 1509 break;
1510 default:
8c440872 1511 gcc_unreachable ();
48837e29
DE		 1512 }
1513 break;
07aae5c2 1514 case 'G':
8c440872 1515 gcc_assert (GET_CODE (x) == CONST_INT);
b47900aa 1516 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
07aae5c2 1517 break;
48837e29
DE		 1518 case 'S':
1519 if (GET_CODE (x) == REG)
1520 fprintf (file, "%s", names_extended[REGNO (x)]);
07aae5c2 1521 else
48837e29 1522 goto def;
07aae5c2 1523 break;
48837e29
DE		 1524 case 'T':
1525 if (GET_CODE (x) == REG)
1526 fprintf (file, "%s", names_big[REGNO (x)]);
07aae5c2 1527 else
48837e29 1528 goto def;
07aae5c2 1529 break;
48837e29 1530 case 'V':
0f6b820c
KP		 1531 bitint = (INTVAL (x) & 0xffff);
1532 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1)
1533 bitint = exact_log2 (bitint & 0xff);
1534 else
1535 bitint = exact_log2 ((bitint >> 8) & 0xff);
8c440872 1536 gcc_assert (bitint >= 0);
4d4d89e2 1537 fprintf (file, "#%d", bitint);
07aae5c2 1538 break;
48837e29 1539 case 'W':
0f6b820c
KP		 1540 bitint = ((~INTVAL (x)) & 0xffff);
1541 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 )
1542 bitint = exact_log2 (bitint & 0xff);
1543 else
1544 bitint = (exact_log2 ((bitint >> 8) & 0xff));
8c440872 1545 gcc_assert (bitint >= 0);
4d4d89e2 1546 fprintf (file, "#%d", bitint);
07aae5c2 1547 break;
15dc331e 1548 case 'R':
48837e29
DE		 1549 case 'X':
1550 if (GET_CODE (x) == REG)
1551 fprintf (file, "%s", byte_reg (x, 0));
1552 else
1553 goto def;
1554 break;
1555 case 'Y':
8c440872 1556 gcc_assert (bitint >= 0);
48837e29
DE		 1557 if (GET_CODE (x) == REG)
1558 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1559 else
88cb339e 1560 h8300_print_operand (file, x, 'R');
48837e29
DE		 1561 bitint = -1;
1562 break;
1563 case 'Z':
1564 bitint = INTVAL (x);
07aae5c2
SC		 1565 fprintf (file, "#%d", bitint & 7);
1566 break;
b059c02a
KH		 1567 case 'c':
1568 switch (GET_CODE (x))
1569 {
1570 case IOR:
1571 fprintf (file, "or");
1572 break;
1573 case XOR:
1574 fprintf (file, "xor");
1575 break;
5abfd1af
KH		 1576 case AND:
1577 fprintf (file, "and");
1578 break;
b059c02a
KH		 1579 default:
1580 break;
1581 }
1582 break;
07aae5c2
SC		 1583 case 'e':
1584 switch (GET_CODE (x))
1585 {
1586 case REG:
48837e29
DE		 1587 if (TARGET_H8300)
1588 fprintf (file, "%s", names_big[REGNO (x)]);
1589 else
1590 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
07aae5c2
SC		 1591 break;
1592 case MEM:
88cb339e 1593 h8300_print_operand (file, x, 0);
07aae5c2
SC		 1594 break;
1595 case CONST_INT:
b47900aa 1596 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
07aae5c2 1597 break;
808fbfac
JL		 1598 case CONST_DOUBLE:
1599 {
1600 long val;
1601 REAL_VALUE_TYPE rv;
1602 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1603 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
441d04c6 1604 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
808fbfac
JL		 1605 break;
1606 }
07aae5c2 1607 default:
8c440872 1608 gcc_unreachable ();
07aae5c2
SC		 1609 break;
1610 }
1611 break;
07aae5c2
SC		 1612 case 'f':
1613 switch (GET_CODE (x))
1614 {
1615 case REG:
48837e29
DE		 1616 if (TARGET_H8300)
1617 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1618 else
1619 fprintf (file, "%s", names_big[REGNO (x)]);
07aae5c2 1620 break;
07aae5c2 1621 case MEM:
b72f00af 1622 x = adjust_address (x, HImode, 2);
88cb339e 1623 h8300_print_operand (file, x, 0);
07aae5c2 1624 break;
07aae5c2 1625 case CONST_INT:
b47900aa 1626 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
07aae5c2 1627 break;
808fbfac
JL		 1628 case CONST_DOUBLE:
1629 {
1630 long val;
1631 REAL_VALUE_TYPE rv;
1632 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1633 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
441d04c6 1634 fprintf (file, "#%ld", (val & 0xffff));
808fbfac
JL		 1635 break;
1636 }
07aae5c2 1637 default:
8c440872 1638 gcc_unreachable ();
07aae5c2
SC		 1639 }
1640 break;
07aae5c2 1641 case 'j':
761c70aa 1642 fputs (cond_string (GET_CODE (x)), file);
07aae5c2 1643 break;
07aae5c2 1644 case 'k':
761c70aa 1645 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
07aae5c2 1646 break;
beed8fc0 1647 case 'm':
8c440872
NS		 1648 gcc_assert (GET_CODE (x) == CONST_INT);
1649 switch (INTVAL (x))
1650 {
1651 case 1:
1652 fputs (".b", file);
1653 break;
1654
1655 case 2:
1656 fputs (".w", file);
1657 break;
1658
1659 case 4:
1660 fputs (".l", file);
1661 break;
1662
1663 default:
1664 gcc_unreachable ();
1665 }
beed8fc0
AO		 1666 break;
1667 case 'o':
88cb339e 1668 h8300_print_operand_address (file, x);
beed8fc0 1669 break;
48837e29
DE		 1670 case 's':
1671 if (GET_CODE (x) == CONST_INT)
b47900aa 1672 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
48837e29
DE		 1673 else
1674 fprintf (file, "%s", byte_reg (x, 0));
1675 break;
1676 case 't':
1677 if (GET_CODE (x) == CONST_INT)
b47900aa 1678 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
48837e29
DE		 1679 else
1680 fprintf (file, "%s", byte_reg (x, 1));
1681 break;
48837e29
DE		 1682 case 'w':
1683 if (GET_CODE (x) == CONST_INT)
b47900aa 1684 fprintf (file, "#%ld", INTVAL (x) & 0xff);
48837e29 1685 else
a1616dd9
JL		 1686 fprintf (file, "%s",
1687 byte_reg (x, TARGET_H8300 ? 2 : 0));
48837e29
DE		 1688 break;
1689 case 'x':
1690 if (GET_CODE (x) == CONST_INT)
b47900aa 1691 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
48837e29 1692 else
a1616dd9
JL		 1693 fprintf (file, "%s",
1694 byte_reg (x, TARGET_H8300 ? 3 : 1));
48837e29
DE		 1695 break;
1696 case 'y':
1697 if (GET_CODE (x) == CONST_INT)
b47900aa 1698 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
48837e29
DE		 1699 else
1700 fprintf (file, "%s", byte_reg (x, 0));
1701 break;
1702 case 'z':
1703 if (GET_CODE (x) == CONST_INT)
b47900aa 1704 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
48837e29
DE		 1705 else
1706 fprintf (file, "%s", byte_reg (x, 1));
1707 break;
1708
07aae5c2 1709 default:
48837e29 1710 def:
07aae5c2
SC		 1711 switch (GET_CODE (x))
1712 {
1713 case REG:
48837e29
DE		 1714 switch (GET_MODE (x))
1715 {
1716 case QImode:
269c14e1 1717#if 0 /* Is it asm ("mov.b %0,r2l", ...) */
48837e29
DE		 1718 fprintf (file, "%s", byte_reg (x, 0));
1719#else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1720 fprintf (file, "%s", names_big[REGNO (x)]);
1721#endif
1722 break;
1723 case HImode:
1724 fprintf (file, "%s", names_big[REGNO (x)]);
1725 break;
1726 case SImode:
8977e8a7 1727 case SFmode:
48837e29
DE		 1728 fprintf (file, "%s", names_extended[REGNO (x)]);
1729 break;
1730 default:
8c440872 1731 gcc_unreachable ();
48837e29 1732 }
07aae5c2
SC		 1733 break;
1734
1735 case MEM:
87e4ee91
KH		 1736 {
1737 rtx addr = XEXP (x, 0);
1738
1739 fprintf (file, "@");
1740 output_address (addr);
1741
beed8fc0
AO		 1742 /* Add a length suffix to constant addresses. Although this
1743 is often unnecessary, it helps to avoid ambiguity in the
1744 syntax of mova. If we wrote an insn like:
1745
1746 mova/w.l @(1,@foo.b),er0
1747
1748 then .b would be considered part of the symbol name.
1749 Adding a length after foo will avoid this. */
1750 if (CONSTANT_P (addr))
1751 switch (code)
1752 {
1753 case 'R':
1754 /* Used for mov.b and bit operations. */
1755 if (h8300_eightbit_constant_address_p (addr))
1756 {
1757 fprintf (file, ":8");
1758 break;
1759 }
1760
1761 /* Fall through. We should not get here if we are
1762 processing bit operations on H8/300 or H8/300H
1763 because 'U' constraint does not allow bit
1764 operations on the tiny area on these machines. */
1765
1766 case 'X':
1767 case 'T':
1768 case 'S':
1769 if (h8300_constant_length (addr) == 2)
1770 fprintf (file, ":16");
1771 else
1772 fprintf (file, ":32");
1773 break;
1774 default:
1775 break;
1776 }
87e4ee91 1777 }
07aae5c2
SC		 1778 break;
1779
1780 case CONST_INT:
1781 case SYMBOL_REF:
1782 case CONST:
1783 case LABEL_REF:
1784 fprintf (file, "#");
88cb339e 1785 h8300_print_operand_address (file, x);
07aae5c2 1786 break;
808fbfac
JL		 1787 case CONST_DOUBLE:
1788 {
1789 long val;
1790 REAL_VALUE_TYPE rv;
1791 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1792 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
441d04c6 1793 fprintf (file, "#%ld", val);
808fbfac
JL		 1794 break;
1795 }
441d04c6
KG		 1796 default:
1797 break;
07aae5c2
SC		 1798 }
1799 }
1800}
1801
88cb339e
N		 1802/* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1803
1804static bool
1805h8300_print_operand_punct_valid_p (unsigned char code)
1806{
1807 return (code == '#');
1808}
1809
07aae5c2
SC		 1810/* Output assembly language output for the address ADDR to FILE. */
1811
88cb339e
N		 1812static void
1813h8300_print_operand_address (FILE *file, rtx addr)
07aae5c2 1814{
beed8fc0
AO		 1815 rtx index;
1816 int size;
1817
07aae5c2
SC		 1818 switch (GET_CODE (addr))
1819 {
1820 case REG:
48837e29 1821 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
07aae5c2
SC		 1822 break;
1823
1824 case PRE_DEC:
48837e29 1825 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
07aae5c2
SC		 1826 break;
1827
1828 case POST_INC:
48837e29 1829 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
07aae5c2
SC		 1830 break;
1831
beed8fc0
AO		 1832 case PRE_INC:
1833 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1834 break;
1835
1836 case POST_DEC:
1837 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
1838 break;
1839
07aae5c2
SC		 1840 case PLUS:
1841 fprintf (file, "(");
beed8fc0
AO		 1842
1843 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
1844 if (GET_CODE (index) == REG)
07aae5c2
SC		 1845 {
1846 /* reg,foo */
88cb339e 1847 h8300_print_operand_address (file, XEXP (addr, 1));
07aae5c2 1848 fprintf (file, ",");
beed8fc0
AO		 1849 switch (size)
1850 {
1851 case 0:
88cb339e 1852 h8300_print_operand_address (file, index);
beed8fc0
AO		 1853 break;
1854
1855 case 1:
88cb339e 1856 h8300_print_operand (file, index, 'X');
beed8fc0
AO		 1857 fputs (".b", file);
1858 break;
1859
1860 case 2:
88cb339e 1861 h8300_print_operand (file, index, 'T');
beed8fc0
AO		 1862 fputs (".w", file);
1863 break;
1864
1865 case 4:
88cb339e 1866 h8300_print_operand (file, index, 'S');
beed8fc0
AO		 1867 fputs (".l", file);
1868 break;
1869 }
88cb339e 1870 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
07aae5c2
SC		 1871 }
1872 else
1873 {
1874 /* foo+k */
88cb339e 1875 h8300_print_operand_address (file, XEXP (addr, 0));
07aae5c2 1876 fprintf (file, "+");
88cb339e 1877 h8300_print_operand_address (file, XEXP (addr, 1));
07aae5c2
SC		 1878 }
1879 fprintf (file, ")");
1880 break;
1881
1882 case CONST_INT:
48837e29 1883 {
da55315a 1884 /* Since the H8/300 only has 16-bit pointers, negative values are also
48837e29
DE		 1885 those >= 32768. This happens for example with pointer minus a
1886 constant. We don't want to turn (char *p - 2) into
1887 (char *p + 65534) because loop unrolling can build upon this
1888 (IE: char *p + 131068). */
1889 int n = INTVAL (addr);
1890 if (TARGET_H8300)
1891 n = (int) (short) n;
7a770d8b 1892 fprintf (file, "%d", n);
48837e29
DE		 1893 break;
1894 }
07aae5c2
SC		 1895
1896 default:
1897 output_addr_const (file, addr);
1898 break;
1899 }
1900}
1901\f
07aae5c2
SC		 1902/* Output all insn addresses and their sizes into the assembly language
1903 output file. This is helpful for debugging whether the length attributes
1904 in the md file are correct. This is not meant to be a user selectable
1905 option. */
1906
1907void
e7041fcc 1908final_prescan_insn (rtx_insn *insn, rtx *operand ATTRIBUTE_UNUSED,
cb713a8d 1909 int num_operands ATTRIBUTE_UNUSED)
07aae5c2
SC		 1910{
1911 /* This holds the last insn address. */
1912 static int last_insn_address = 0;
1913
7798db98 1914 const int uid = INSN_UID (insn);
07aae5c2
SC		 1915
1916 if (TARGET_ADDRESSES)
1917 {
9d98a694
AO		 1918 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1919 INSN_ADDRESSES (uid) - last_insn_address);
1920 last_insn_address = INSN_ADDRESSES (uid);
07aae5c2
SC		 1921 }
1922}
1923
48837e29
DE		 1924/* Prepare for an SI sized move. */
1925
1926int
1a793acf 1927h8300_expand_movsi (rtx operands[])
07aae5c2 1928{
48837e29
DE		 1929 rtx src = operands[1];
1930 rtx dst = operands[0];
1931 if (!reload_in_progress && !reload_completed)
1932 {
1933 if (!register_operand (dst, GET_MODE (dst)))
1934 {
1935 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1936 emit_move_insn (tmp, src);
1937 operands[1] = tmp;
1938 }
1939 }
1940 return 0;
1941}
1942
7b5cbb57
AS		 1943/* Given FROM and TO register numbers, say whether this elimination is allowed.
1944 Frame pointer elimination is automatically handled.
1945
1946 For the h8300, if frame pointer elimination is being done, we would like to
1947 convert ap and rp into sp, not fp.
1948
1949 All other eliminations are valid. */
1950
1951static bool
1952h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
1953{
1954 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
1955}
1956
5efd84c5
NF		 1957/* Conditionally modify register usage based on target flags. */
1958
1959static void
1960h8300_conditional_register_usage (void)
1961{
1962 if (!TARGET_MAC)
1963 fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1;
1964}
1965
48837e29 1966/* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
07e4d94e
KH		 1967 Define the offset between two registers, one to be eliminated, and
1968 the other its replacement, at the start of a routine. */
07aae5c2 1969
48837e29 1970int
cb713a8d 1971h8300_initial_elimination_offset (int from, int to)
48837e29 1972{
d18ad191
KH		 1973 /* The number of bytes that the return address takes on the stack. */
1974 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
48837e29 1975
1807b726
KH		 1976 /* The number of bytes that the saved frame pointer takes on the stack. */
1977 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1978
1979 /* The number of bytes that the saved registers, excluding the frame
1980 pointer, take on the stack. */
1981 int saved_regs_size = 0;
48837e29 1982
1807b726
KH		 1983 /* The number of bytes that the locals takes on the stack. */
1984 int frame_size = round_frame_size (get_frame_size ());
48837e29 1985
1807b726 1986 int regno;
48837e29 1987
1807b726
KH		 1988 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1989 if (WORD_REG_USED (regno))
1990 saved_regs_size += UNITS_PER_WORD;
48837e29 1991
1807b726
KH		 1992 /* Adjust saved_regs_size because the above loop took the frame
1993 pointer int account. */
1994 saved_regs_size -= fp_size;
39ba95b5 1995
8c440872 1996 switch (to)
1807b726 1997 {
8c440872 1998 case HARD_FRAME_POINTER_REGNUM:
1807b726
KH		 1999 switch (from)
2000 {
2001 case ARG_POINTER_REGNUM:
2002 return pc_size + fp_size;
2003 case RETURN_ADDRESS_POINTER_REGNUM:
2004 return fp_size;
2005 case FRAME_POINTER_REGNUM:
2006 return -saved_regs_size;
2007 default:
8c440872 2008 gcc_unreachable ();
1807b726 2009 }
8c440872
NS		 2010 break;
2011 case STACK_POINTER_REGNUM:
1807b726
KH		 2012 switch (from)
2013 {
2014 case ARG_POINTER_REGNUM:
2015 return pc_size + saved_regs_size + frame_size;
2016 case RETURN_ADDRESS_POINTER_REGNUM:
2017 return saved_regs_size + frame_size;
2018 case FRAME_POINTER_REGNUM:
2019 return frame_size;
2020 default:
8c440872 2021 gcc_unreachable ();
1807b726 2022 }
8c440872
NS		 2023 break;
2024 default:
2025 gcc_unreachable ();
1807b726 2026 }
8c440872 2027 gcc_unreachable ();
48837e29
DE		 2028}
2029
e9eba255
KH		 2030/* Worker function for RETURN_ADDR_RTX. */
2031
1aae372e 2032rtx
cb713a8d 2033h8300_return_addr_rtx (int count, rtx frame)
1aae372e
JL		 2034{
2035 rtx ret;
2036
2037 if (count == 0)
2038 ret = gen_rtx_MEM (Pmode,
2039 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
2040 else if (flag_omit_frame_pointer)
2041 return (rtx) 0;
2042 else
2043 ret = gen_rtx_MEM (Pmode,
2044 memory_address (Pmode,
0a81f074
RS		 2045 plus_constant (Pmode, frame,
2046 UNITS_PER_WORD)));
1aae372e
JL		 2047 set_mem_alias_set (ret, get_frame_alias_set ());
2048 return ret;
2049}
2050
48837e29
DE		 2051/* Update the condition code from the insn. */
2052
441d04c6 2053void
e8a54173 2054notice_update_cc (rtx body, rtx_insn *insn)
48837e29 2055{
d99c740f
KH		 2056 rtx set;
2057
48837e29
DE		 2058 switch (get_attr_cc (insn))
2059 {
2060 case CC_NONE:
269c14e1 2061 /* Insn does not affect CC at all. */
48837e29
DE		 2062 break;
2063
2064 case CC_NONE_0HIT:
269c14e1 2065 /* Insn does not change CC, but the 0'th operand has been changed. */
48837e29 2066 if (cc_status.value1 != 0
1ccbefce 2067 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
48837e29 2068 cc_status.value1 = 0;
d4d6d0ce
KH		 2069 if (cc_status.value2 != 0
2070 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
2071 cc_status.value2 = 0;
48837e29
DE		 2072 break;
2073
065bbfe6 2074 case CC_SET_ZN:
1ccbefce 2075 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
269c14e1
DE		 2076 The V flag is unusable. The C flag may or may not be known but
2077 that's ok because alter_cond will change tests to use EQ/NE. */
48837e29 2078 CC_STATUS_INIT;
269c14e1 2079 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
d99c740f
KH		 2080 set = single_set (insn);
2081 cc_status.value1 = SET_SRC (set);
2082 if (SET_DEST (set) != cc0_rtx)
2083 cc_status.value2 = SET_DEST (set);
48837e29
DE		 2084 break;
2085
065bbfe6 2086 case CC_SET_ZNV:
1ccbefce 2087 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
065bbfe6
JL		 2088 The C flag may or may not be known but that's ok because
2089 alter_cond will change tests to use EQ/NE. */
2090 CC_STATUS_INIT;
2091 cc_status.flags |= CC_NO_CARRY;
d99c740f
KH		 2092 set = single_set (insn);
2093 cc_status.value1 = SET_SRC (set);
2094 if (SET_DEST (set) != cc0_rtx)
c8fcf20c
KH		 2095 {
2096 /* If the destination is STRICT_LOW_PART, strip off
2097 STRICT_LOW_PART. */
2098 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
2099 cc_status.value2 = XEXP (SET_DEST (set), 0);
2100 else
2101 cc_status.value2 = SET_DEST (set);
2102 }
065bbfe6
JL		 2103 break;
2104
beed8fc0
AO		 2105 case CC_COMPARE:
2106 /* The insn is a compare instruction. */
2107 CC_STATUS_INIT;
2108 cc_status.value1 = SET_SRC (body);
2109 break;
2110
2111 case CC_CLOBBER:
2112 /* Insn doesn't leave CC in a usable state. */
2113 CC_STATUS_INIT;
2114 break;
2115 }
2116}
beed8fc0
AO		 2117\f
2118/* Given that X occurs in an address of the form (plus X constant),
2119 return the part of X that is expected to be a register. There are
2120 four kinds of addressing mode to recognize:
2121
2122 @(dd,Rn)
2123 @(dd,RnL.b)
2124 @(dd,Rn.w)
2125 @(dd,ERn.l)
2126
2127 If SIZE is nonnull, and the address is one of the last three forms,
2128 set *SIZE to the index multiplication factor. Set it to 0 for
2129 plain @(dd,Rn) addresses.
2130
2131 MODE is the mode of the value being accessed. It can be VOIDmode
2132 if the address is known to be valid, but its mode is unknown. */
2133
f52d97da 2134static rtx
ef4bddc2 2135h8300_get_index (rtx x, machine_mode mode, int *size)
beed8fc0
AO		 2136{
2137 int dummy, factor;
2138
2139 if (size == 0)
2140 size = &dummy;
2141
2142 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
2143 if (TARGET_H8300SX
2144 && factor <= 4
2145 && (mode == VOIDmode
2146 || GET_MODE_CLASS (mode) == MODE_INT
2147 || GET_MODE_CLASS (mode) == MODE_FLOAT))
2148 {
2149 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
2150 {
2151 /* When accessing byte-sized values, the index can be
2152 a zero-extended QImode or HImode register. */
2153 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
2154 return XEXP (x, 0);
2155 }
2156 else
2157 {
2158 /* We're looking for addresses of the form:
2159
2160 (mult X I)
2161 or (mult (zero_extend X) I)
2162
2163 where I is the size of the operand being accessed.
2164 The canonical form of the second expression is:
2165
2166 (and (mult (subreg X) I) J)
2167
2168 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2169 rtx index;
2170
2171 if (GET_CODE (x) == AND
2172 && GET_CODE (XEXP (x, 1)) == CONST_INT
2173 && (factor == 0
2174 || INTVAL (XEXP (x, 1)) == 0xff * factor
2175 || INTVAL (XEXP (x, 1)) == 0xffff * factor))
2176 {
2177 index = XEXP (x, 0);
2178 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
2179 }
2180 else
2181 {
2182 index = x;
2183 *size = 4;
2184 }
2185
2186 if (GET_CODE (index) == MULT
2187 && GET_CODE (XEXP (index, 1)) == CONST_INT
2188 && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
2189 return XEXP (index, 0);
2190 }
2191 }
2192 *size = 0;
2193 return x;
2194}
2195\f
f52d97da
AS		 2196/* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2197
2198 On the H8/300, the predecrement and postincrement address depend thus
2199 (the amount of decrement or increment being the length of the operand). */
2200
2201static bool
5bfed9a9
GJL		 2202h8300_mode_dependent_address_p (const_rtx addr,
2203 addr_space_t as ATTRIBUTE_UNUSED)
f52d97da
AS		 2204{
2205 if (GET_CODE (addr) == PLUS
2206 && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0))
2207 return true;
2208
2209 return false;
2210}
2211\f
beed8fc0
AO		 2212static const h8300_length_table addb_length_table =
2213{
2214 /* #xx Rs @aa @Rs @xx */
2215 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2216 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2217 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2218 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2219};
2220
2221static const h8300_length_table addw_length_table =
2222{
2223 /* #xx Rs @aa @Rs @xx */
2224 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2225 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2226 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2227 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2228};
2229
2230static const h8300_length_table addl_length_table =
2231{
2232 /* #xx Rs @aa @Rs @xx */
2233 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2234 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2235 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2236 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2237};
2238
2239#define logicb_length_table addb_length_table
2240#define logicw_length_table addw_length_table
2241
2242static const h8300_length_table logicl_length_table =
2243{
2244 /* #xx Rs @aa @Rs @xx */
2245 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2246 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2247 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2248 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2249};
2250
2251static const h8300_length_table movb_length_table =
2252{
2253 /* #xx Rs @aa @Rs @xx */
2254 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2255 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2256 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2257 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2258};
2259
2260#define movw_length_table movb_length_table
2261
2262static const h8300_length_table movl_length_table =
2263{
2264 /* #xx Rs @aa @Rs @xx */
2265 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2266 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2267 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2268 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2269};
2270
2271/* Return the size of the given address or displacement constant. */
2272
2273static unsigned int
2274h8300_constant_length (rtx constant)
2275{
2276 /* Check for (@d:16,Reg). */
2277 if (GET_CODE (constant) == CONST_INT
2278 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
2279 return 2;
2280
2281 /* Check for (@d:16,Reg) in cases where the displacement is
2282 an absolute address. */
2283 if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
2284 return 2;
2285
2286 return 4;
2287}
2288
2289/* Return the size of a displacement field in address ADDR, which should
2290 have the form (plus X constant). SIZE is the number of bytes being
2291 accessed. */
2292
2293static unsigned int
2294h8300_displacement_length (rtx addr, int size)
2295{
2296 rtx offset;
2297
2298 offset = XEXP (addr, 1);
2299
2300 /* Check for @(d:2,Reg). */
2301 if (register_operand (XEXP (addr, 0), VOIDmode)
2302 && GET_CODE (offset) == CONST_INT
2303 && (INTVAL (offset) == size
2304 || INTVAL (offset) == size * 2
2305 || INTVAL (offset) == size * 3))
2306 return 0;
2307
2308 return h8300_constant_length (offset);
2309}
2310
0a2aaacc
KG		 2311/* Store the class of operand OP in *OPCLASS and return the length of any
2312 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
beed8fc0
AO		 2313 can be null if only the length is needed. */
2314
2315static unsigned int
0a2aaacc 2316h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
beed8fc0
AO		 2317{
2318 enum h8300_operand_class dummy;
2319
0a2aaacc
KG		 2320 if (opclass == 0)
2321 opclass = &dummy;
beed8fc0
AO		 2322
2323 if (CONSTANT_P (op))
2324 {
0a2aaacc 2325 *opclass = H8OP_IMMEDIATE;
beed8fc0
AO		 2326
2327 /* Byte-sized immediates are stored in the opcode fields. */
2328 if (size == 1)
2329 return 0;
2330
2331 /* If this is a 32-bit instruction, see whether the constant
2332 will fit into a 16-bit immediate field. */
2333 if (TARGET_H8300SX
2334 && size == 4
2335 && GET_CODE (op) == CONST_INT
2336 && IN_RANGE (INTVAL (op), 0, 0xffff))
2337 return 2;
2338
2339 return size;
2340 }
2341 else if (GET_CODE (op) == MEM)
2342 {
2343 op = XEXP (op, 0);
2344 if (CONSTANT_P (op))
2345 {
0a2aaacc 2346 *opclass = H8OP_MEM_ABSOLUTE;
beed8fc0
AO		 2347 return h8300_constant_length (op);
2348 }
2349 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
2350 {
0a2aaacc 2351 *opclass = H8OP_MEM_COMPLEX;
beed8fc0
AO		 2352 return h8300_displacement_length (op, size);
2353 }
2354 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
2355 {
0a2aaacc 2356 *opclass = H8OP_MEM_COMPLEX;
beed8fc0
AO		 2357 return 0;
2358 }
2359 else if (register_operand (op, VOIDmode))
2360 {
0a2aaacc 2361 *opclass = H8OP_MEM_BASE;
beed8fc0
AO		 2362 return 0;
2363 }
2364 }
8c440872 2365 gcc_assert (register_operand (op, VOIDmode));
0a2aaacc 2366 *opclass = H8OP_REGISTER;
8c440872 2367 return 0;
beed8fc0
AO		 2368}
2369
2370/* Return the length of the instruction described by TABLE given that
2371 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2372 and OP2 must be an h8300_src_operand. */
2373
2374static unsigned int
2375h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
2376{
2377 enum h8300_operand_class op1_class, op2_class;
2378 unsigned int size, immediate_length;
2379
2380 size = GET_MODE_SIZE (GET_MODE (op1));
2381 immediate_length = (h8300_classify_operand (op1, size, &op1_class)
2382 + h8300_classify_operand (op2, size, &op2_class));
2383 return immediate_length + (*table)[op1_class - 1][op2_class];
2384}
2385
2386/* Return the length of a unary instruction such as neg or not given that
2387 its operand is OP. */
2388
2389unsigned int
2390h8300_unary_length (rtx op)
2391{
0a2aaacc 2392 enum h8300_operand_class opclass;
beed8fc0
AO		 2393 unsigned int size, operand_length;
2394
2395 size = GET_MODE_SIZE (GET_MODE (op));
0a2aaacc
KG		 2396 operand_length = h8300_classify_operand (op, size, &opclass);
2397 switch (opclass)
beed8fc0
AO		 2398 {
2399 case H8OP_REGISTER:
2400 return 2;
2401
2402 case H8OP_MEM_BASE:
2403 return (size == 4 ? 6 : 4);
2404
2405 case H8OP_MEM_ABSOLUTE:
2406 return operand_length + (size == 4 ? 6 : 4);
2407
2408 case H8OP_MEM_COMPLEX:
2409 return operand_length + 6;
2410
2411 default:
8c440872 2412 gcc_unreachable ();
beed8fc0
AO		 2413 }
2414}
2415
2416/* Likewise short immediate instructions such as add.w #xx:3,OP. */
2417
2418static unsigned int
2419h8300_short_immediate_length (rtx op)
2420{
0a2aaacc 2421 enum h8300_operand_class opclass;
beed8fc0
AO		 2422 unsigned int size, operand_length;
2423
2424 size = GET_MODE_SIZE (GET_MODE (op));
0a2aaacc 2425 operand_length = h8300_classify_operand (op, size, &opclass);
beed8fc0 2426
0a2aaacc 2427 switch (opclass)
beed8fc0
AO		 2428 {
2429 case H8OP_REGISTER:
2430 return 2;
2431
2432 case H8OP_MEM_BASE:
2433 case H8OP_MEM_ABSOLUTE:
2434 case H8OP_MEM_COMPLEX:
2435 return 4 + operand_length;
2436
2437 default:
8c440872 2438 gcc_unreachable ();
beed8fc0
AO		 2439 }
2440}
2441
2442/* Likewise bitfield load and store instructions. */
48837e29 2443
beed8fc0
AO		 2444static unsigned int
2445h8300_bitfield_length (rtx op, rtx op2)
2446{
0a2aaacc 2447 enum h8300_operand_class opclass;
beed8fc0
AO		 2448 unsigned int size, operand_length;
2449
2450 if (GET_CODE (op) == REG)
2451 op = op2;
8c440872 2452 gcc_assert (GET_CODE (op) != REG);
beed8fc0
AO		 2453
2454 size = GET_MODE_SIZE (GET_MODE (op));
0a2aaacc 2455 operand_length = h8300_classify_operand (op, size, &opclass);
beed8fc0 2456
0a2aaacc 2457 switch (opclass)
beed8fc0
AO		 2458 {
2459 case H8OP_MEM_BASE:
2460 case H8OP_MEM_ABSOLUTE:
2461 case H8OP_MEM_COMPLEX:
2462 return 4 + operand_length;
2463
2464 default:
8c440872 2465 gcc_unreachable ();
07aae5c2 2466 }
48837e29
DE		 2467}
2468
beed8fc0 2469/* Calculate the length of general binary instruction INSN using TABLE. */
8ccf5d5f 2470
beed8fc0 2471static unsigned int
e7041fcc 2472h8300_binary_length (rtx_insn *insn, const h8300_length_table *table)
8ccf5d5f 2473{
beed8fc0
AO		 2474 rtx set;
2475
2476 set = single_set (insn);
8c440872 2477 gcc_assert (set);
beed8fc0
AO		 2478
2479 if (BINARY_P (SET_SRC (set)))
2480 return h8300_length_from_table (XEXP (SET_SRC (set), 0),
2481 XEXP (SET_SRC (set), 1), table);
beed8fc0 2482 else
8c440872
NS		 2483 {
2484 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
2485 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
2486 XEXP (XEXP (SET_SRC (set), 1), 1),
2487 table);
2488 }
8ccf5d5f
KH		 2489}
2490
beed8fc0
AO		 2491/* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2492 memory reference and either (1) it has the form @(d:16,Rn) or
2493 (2) its address has the code given by INC_CODE. */
8ccf5d5f 2494
beed8fc0
AO		 2495static bool
2496h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
8ccf5d5f 2497{
beed8fc0
AO		 2498 rtx addr;
2499 unsigned int size;
2500
2501 if (GET_CODE (op) != MEM)
2502 return false;
2503
2504 addr = XEXP (op, 0);
2505 size = GET_MODE_SIZE (GET_MODE (op));
2506 if (size != 1 && size != 2)
2507 return false;
2508
2509 return (GET_CODE (addr) == inc_code
2510 || (GET_CODE (addr) == PLUS
2511 && GET_CODE (XEXP (addr, 0)) == REG
2512 && h8300_displacement_length (addr, size) == 2));
8ccf5d5f
KH		 2513}
2514
beed8fc0
AO		 2515/* Calculate the length of move instruction INSN using the given length
2516 table. Although the tables are correct for most cases, there is some
2517 irregularity in the length of mov.b and mov.w. The following forms:
8ccf5d5f 2518
beed8fc0
AO		 2519 mov @ERs+, Rd
2520 mov @(d:16,ERs), Rd
2521 mov Rs, @-ERd
2522 mov Rs, @(d:16,ERd)
2523
2524 are two bytes shorter than most other "mov Rs, @complex" or
2525 "mov @complex,Rd" combinations. */
2526
2527static unsigned int
2528h8300_move_length (rtx *operands, const h8300_length_table *table)
8ccf5d5f 2529{
beed8fc0
AO		 2530 unsigned int size;
2531
2532 size = h8300_length_from_table (operands[0], operands[1], table);
2533 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
2534 size -= 2;
2535 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
2536 size -= 2;
2537 return size;
8ccf5d5f
KH		 2538}
2539
beed8fc0
AO		 2540/* Return the length of a mova instruction with the given operands.
2541 DEST is the register destination, SRC is the source address and
2542 OFFSET is the 16-bit or 32-bit displacement. */
2873836b 2543
beed8fc0
AO		 2544static unsigned int
2545h8300_mova_length (rtx dest, rtx src, rtx offset)
2873836b 2546{
beed8fc0
AO		 2547 unsigned int size;
2548
2549 size = (2
2550 + h8300_constant_length (offset)
2551 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
2552 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
2553 size += 2;
2554 return size;
2873836b
KH		 2555}
2556
beed8fc0
AO		 2557/* Compute the length of INSN based on its length_table attribute.
2558 OPERANDS is the array of its operands. */
2873836b 2559
beed8fc0 2560unsigned int
e7041fcc 2561h8300_insn_length_from_table (rtx_insn *insn, rtx * operands)
2873836b 2562{
beed8fc0
AO		 2563 switch (get_attr_length_table (insn))
2564 {
2565 case LENGTH_TABLE_NONE:
8c440872 2566 gcc_unreachable ();
beed8fc0
AO		 2567
2568 case LENGTH_TABLE_ADDB:
2569 return h8300_binary_length (insn, &addb_length_table);
2570
2571 case LENGTH_TABLE_ADDW:
2572 return h8300_binary_length (insn, &addw_length_table);
2573
2574 case LENGTH_TABLE_ADDL:
2575 return h8300_binary_length (insn, &addl_length_table);
2576
2577 case LENGTH_TABLE_LOGICB:
2578 return h8300_binary_length (insn, &logicb_length_table);
2579
2580 case LENGTH_TABLE_MOVB:
2581 return h8300_move_length (operands, &movb_length_table);
2582
2583 case LENGTH_TABLE_MOVW:
2584 return h8300_move_length (operands, &movw_length_table);
2585
2586 case LENGTH_TABLE_MOVL:
2587 return h8300_move_length (operands, &movl_length_table);
2588
2589 case LENGTH_TABLE_MOVA:
2590 return h8300_mova_length (operands[0], operands[1], operands[2]);
2591
2592 case LENGTH_TABLE_MOVA_ZERO:
2593 return h8300_mova_length (operands[0], operands[1], const0_rtx);
2594
2595 case LENGTH_TABLE_UNARY:
2596 return h8300_unary_length (operands[0]);
2597
2598 case LENGTH_TABLE_MOV_IMM4:
2599 return 2 + h8300_classify_operand (operands[0], 0, 0);
2600
2601 case LENGTH_TABLE_SHORT_IMMEDIATE:
2602 return h8300_short_immediate_length (operands[0]);
2603
2604 case LENGTH_TABLE_BITFIELD:
2605 return h8300_bitfield_length (operands[0], operands[1]);
2606
2607 case LENGTH_TABLE_BITBRANCH:
2608 return h8300_bitfield_length (operands[1], operands[2]) - 2;
8c440872
NS		 2609
2610 default:
2611 gcc_unreachable ();
beed8fc0 2612 }
2873836b
KH		 2613}
2614
beed8fc0
AO		 2615/* Return true if LHS and RHS are memory references that can be mapped
2616 to the same h8sx assembly operand. LHS appears as the destination of
2617 an instruction and RHS appears as a source.
f9d2de4d 2618
beed8fc0
AO		 2619 Three cases are allowed:
2620
2621 - RHS is @+Rn or @-Rn, LHS is @Rn
2622 - RHS is @Rn, LHS is @Rn+ or @Rn-
2623 - RHS and LHS have the same address and neither has side effects. */
2624
2625bool
2626h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
f9d2de4d 2627{
beed8fc0
AO		 2628 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
2629 {
2630 rhs = XEXP (rhs, 0);
2631 lhs = XEXP (lhs, 0);
2632
2633 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
2634 return rtx_equal_p (XEXP (rhs, 0), lhs);
2635
2636 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
2637 return rtx_equal_p (rhs, XEXP (lhs, 0));
2638
2639 if (rtx_equal_p (rhs, lhs))
2640 return true;
2641 }
2642 return false;
f9d2de4d
KH		 2643}
2644
beed8fc0
AO		 2645/* Return true if OPERANDS[1] can be mapped to the same assembly
2646 operand as OPERANDS[0]. */
f9d2de4d 2647
beed8fc0
AO		 2648bool
2649h8300_operands_match_p (rtx *operands)
f9d2de4d 2650{
beed8fc0
AO		 2651 if (register_operand (operands[0], VOIDmode)
2652 && register_operand (operands[1], VOIDmode))
2653 return true;
f9d2de4d 2654
beed8fc0
AO		 2655 if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
2656 return true;
2657
2658 return false;
f9d2de4d 2659}
beed8fc0
AO		 2660\f
2661/* Try using movmd to move LENGTH bytes from memory region SRC to memory
2662 region DEST. The two regions do not overlap and have the common
2663 alignment given by ALIGNMENT. Return true on success.
717d8b71 2664
beed8fc0
AO		 2665 Using movmd for variable-length moves seems to involve some
2666 complex trade-offs. For instance:
b059c02a 2667
beed8fc0
AO		 2668 - Preparing for a movmd instruction is similar to preparing
2669 for a memcpy. The main difference is that the arguments
2670 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2671
2672 - Since movmd clobbers the frame pointer, we need to save
2673 and restore it somehow when frame_pointer_needed. This can
2674 sometimes make movmd sequences longer than calls to memcpy().
2675
2676 - The counter register is 16 bits, so the instruction is only
2677 suitable for variable-length moves when sizeof (size_t) == 2.
2678 That's only true in normal mode.
2679
2680 - We will often lack static alignment information. Falling back
2681 on movmd.b would likely be slower than calling memcpy(), at least
2682 for big moves.
2683
2684 This function therefore only uses movmd when the length is a
2685 known constant, and only then if -fomit-frame-pointer is in
2686 effect or if we're not optimizing for size.
2687
2688 At the moment the function uses movmd for all in-range constants,
2689 but it might be better to fall back on memcpy() for large moves
2690 if ALIGNMENT == 1. */
2691
2692bool
2693h8sx_emit_movmd (rtx dest, rtx src, rtx length,
2694 HOST_WIDE_INT alignment)
b059c02a 2695{
beed8fc0
AO		 2696 if (!flag_omit_frame_pointer && optimize_size)
2697 return false;
b059c02a 2698
beed8fc0
AO		 2699 if (GET_CODE (length) == CONST_INT)
2700 {
2701 rtx dest_reg, src_reg, first_dest, first_src;
2702 HOST_WIDE_INT n;
2703 int factor;
2704
2705 /* Use movmd.l if the alignment allows it, otherwise fall back
2706 on movmd.b. */
2707 factor = (alignment >= 2 ? 4 : 1);
2708
2709 /* Make sure the length is within range. We can handle counter
2710 values up to 65536, although HImode truncation will make
2711 the count appear negative in rtl dumps. */
2712 n = INTVAL (length);
2713 if (n <= 0 || n / factor > 65536)
2714 return false;
2715
2716 /* Create temporary registers for the source and destination
2717 pointers. Initialize them to the start of each region. */
2718 dest_reg = copy_addr_to_reg (XEXP (dest, 0));
2719 src_reg = copy_addr_to_reg (XEXP (src, 0));
2720
2721 /* Create references to the movmd source and destination blocks. */
2722 first_dest = replace_equiv_address (dest, dest_reg);
2723 first_src = replace_equiv_address (src, src_reg);
2724
f5541398
RS		 2725 set_mem_size (first_dest, n & -factor);
2726 set_mem_size (first_src, n & -factor);
beed8fc0
AO		 2727
2728 length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode));
2729 emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor)));
2730
2731 if ((n & -factor) != n)
2732 {
2733 /* Move SRC and DEST past the region we just copied.
2734 This is done to update the memory attributes. */
2735 dest = adjust_address (dest, BLKmode, n & -factor);
2736 src = adjust_address (src, BLKmode, n & -factor);
2737
2738 /* Replace the addresses with the source and destination
2739 registers, which movmd has left with the right values. */
2740 dest = replace_equiv_address (dest, dest_reg);
2741 src = replace_equiv_address (src, src_reg);
2742
2743 /* Mop up the left-over bytes. */
2744 if (n & 2)
2745 emit_move_insn (adjust_address (dest, HImode, 0),
2746 adjust_address (src, HImode, 0));
2747 if (n & 1)
2748 emit_move_insn (adjust_address (dest, QImode, n & 2),
2749 adjust_address (src, QImode, n & 2));
2750 }
2751 return true;
2752 }
2753 return false;
b059c02a
KH		 2754}
2755
beed8fc0 2756/* Move ADDR into er6 after pushing its old value onto the stack. */
48837e29 2757
beed8fc0
AO		 2758void
2759h8300_swap_into_er6 (rtx addr)
48837e29 2760{
1901e8d6 2761 rtx insn = push (HARD_FRAME_POINTER_REGNUM, false);
8f1594b2
RH		 2762 if (frame_pointer_needed)
2763 add_reg_note (insn, REG_CFA_DEF_CFA,
0a81f074 2764 plus_constant (Pmode, gen_rtx_MEM (Pmode, stack_pointer_rtx),
8f1594b2
RH		 2765 2 * UNITS_PER_WORD));
2766 else
2767 add_reg_note (insn, REG_CFA_ADJUST_CFA,
f7df4a84 2768 gen_rtx_SET (stack_pointer_rtx,
0a81f074 2769 plus_constant (Pmode, stack_pointer_rtx, 4)));
8f1594b2 2770
beed8fc0
AO		 2771 emit_move_insn (hard_frame_pointer_rtx, addr);
2772 if (REGNO (addr) == SP_REG)
2773 emit_move_insn (hard_frame_pointer_rtx,
0a81f074 2774 plus_constant (Pmode, hard_frame_pointer_rtx,
beed8fc0
AO		 2775 GET_MODE_SIZE (word_mode)));
2776}
07aae5c2 2777
beed8fc0
AO		 2778/* Move the current value of er6 into ADDR and pop its old value
2779 from the stack. */
2780
2781void
2782h8300_swap_out_of_er6 (rtx addr)
2783{
8f1594b2
RH		 2784 rtx insn;
2785
beed8fc0
AO		 2786 if (REGNO (addr) != SP_REG)
2787 emit_move_insn (addr, hard_frame_pointer_rtx);
8f1594b2
RH		 2788
2789 insn = pop (HARD_FRAME_POINTER_REGNUM);
8f1594b2
RH		 2790 if (frame_pointer_needed)
2791 add_reg_note (insn, REG_CFA_DEF_CFA,
0a81f074
RS		 2792 plus_constant (Pmode, hard_frame_pointer_rtx,
2793 2 * UNITS_PER_WORD));
8f1594b2
RH		 2794 else
2795 add_reg_note (insn, REG_CFA_ADJUST_CFA,
f7df4a84 2796 gen_rtx_SET (stack_pointer_rtx,
0a81f074 2797 plus_constant (Pmode, stack_pointer_rtx, -4)));
07aae5c2 2798}
48837e29 2799\f
7948a9ea
KH		 2800/* Return the length of mov instruction. */
2801
2802unsigned int
2803compute_mov_length (rtx *operands)
2804{
2805 /* If the mov instruction involves a memory operand, we compute the
2806 length, assuming the largest addressing mode is used, and then
2807 adjust later in the function. Otherwise, we compute and return
2808 the exact length in one step. */
ef4bddc2 2809 machine_mode mode = GET_MODE (operands[0]);
7948a9ea
KH		 2810 rtx dest = operands[0];
2811 rtx src = operands[1];
2812 rtx addr;
2813
2814 if (GET_CODE (src) == MEM)
2815 addr = XEXP (src, 0);
2816 else if (GET_CODE (dest) == MEM)
2817 addr = XEXP (dest, 0);
2818 else
2819 addr = NULL_RTX;
2820
2821 if (TARGET_H8300)
2822 {
2823 unsigned int base_length;
2824
2825 switch (mode)
2826 {
2827 case QImode:
2828 if (addr == NULL_RTX)
2829 return 2;
2830
2831 /* The eightbit addressing is available only in QImode, so
2832 go ahead and take care of it. */
2833 if (h8300_eightbit_constant_address_p (addr))
2834 return 2;
2835
2836 base_length = 4;
2837 break;
2838
2839 case HImode:
2840 if (addr == NULL_RTX)
2841 {
2842 if (REG_P (src))
2843 return 2;
2844
2845 if (src == const0_rtx)
2846 return 2;
2847
2848 return 4;
2849 }
2850
2851 base_length = 4;
2852 break;
2853
2854 case SImode:
2855 if (addr == NULL_RTX)
2856 {
2857 if (REG_P (src))
2858 return 4;
2859
2860 if (GET_CODE (src) == CONST_INT)
2861 {
2862 if (src == const0_rtx)
2863 return 4;
2864
2865 if ((INTVAL (src) & 0xffff) == 0)
2866 return 6;
2867
2868 if ((INTVAL (src) & 0xffff) == 0)
2869 return 6;
f5139cc5
KH		 2870
2871 if ((INTVAL (src) & 0xffff)
2872 == ((INTVAL (src) >> 16) & 0xffff))
2873 return 6;
7948a9ea
KH		 2874 }
2875 return 8;
2876 }
2877
2878 base_length = 8;
2879 break;
2880
2881 case SFmode:
2882 if (addr == NULL_RTX)
2883 {
2884 if (REG_P (src))
2885 return 4;
2886
ceaaaeab 2887 if (satisfies_constraint_G (src))
2c4a71b3
KH		 2888 return 4;
2889
81983b04 2890 return 8;
7948a9ea
KH		 2891 }
2892
2893 base_length = 8;
2894 break;
2895
2896 default:
8c440872 2897 gcc_unreachable ();
7948a9ea
KH		 2898 }
2899
2900 /* Adjust the length based on the addressing mode used.
2901 Specifically, we subtract the difference between the actual
2902 length and the longest one, which is @(d:16,Rs). For SImode
2903 and SFmode, we double the adjustment because two mov.w are
2904 used to do the job. */
2905
2906 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2907 if (GET_CODE (addr) == PRE_DEC
2908 || GET_CODE (addr) == POST_INC)
2909 {
2910 if (mode == QImode || mode == HImode)
2911 return base_length - 2;
2912 else
2913 /* In SImode and SFmode, we use two mov.w instructions, so
2a43945f 2914 double the adjustment. */
7948a9ea
KH		 2915 return base_length - 4;
2916 }
2917
2918 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2919 in SImode and SFmode, the second mov.w involves an address
2920 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2921 only 2 bytes. */
2922 if (GET_CODE (addr) == REG)
2923 return base_length - 2;
2924
2925 return base_length;
2926 }
2927 else
2928 {
2929 unsigned int base_length;
2930
2931 switch (mode)
2932 {
2933 case QImode:
2934 if (addr == NULL_RTX)
2935 return 2;
2936
2937 /* The eightbit addressing is available only in QImode, so
2938 go ahead and take care of it. */
2939 if (h8300_eightbit_constant_address_p (addr))
2940 return 2;
2941
2942 base_length = 8;
2943 break;
2944
2945 case HImode:
2946 if (addr == NULL_RTX)
2947 {
2948 if (REG_P (src))
2949 return 2;
2950
2951 if (src == const0_rtx)
2952 return 2;
2953
2954 return 4;
2955 }
2956
2957 base_length = 8;
2958 break;
2959
2960 case SImode:
2961 if (addr == NULL_RTX)
2962 {
2963 if (REG_P (src))
2964 {
2965 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2966 return 4;
2967 else
2968 return 2;
2969 }
2970
2971 if (GET_CODE (src) == CONST_INT)
2972 {
2973 int val = INTVAL (src);
2974
2975 if (val == 0)
2976 return 2;
2977
2978 if (val == (val & 0x00ff) || val == (val & 0xff00))
2979 return 4;
80e58519 2980
7948a9ea
KH		 2981 switch (val & 0xffffffff)
2982 {
2983 case 0xffffffff:
2984 case 0xfffffffe:
2985 case 0xfffffffc:
2986 case 0x0000ffff:
2987 case 0x0000fffe:
2988 case 0xffff0000:
2989 case 0xfffe0000:
2990 case 0x00010000:
2991 case 0x00020000:
2992 return 4;
2993 }
2994 }
2995 return 6;
2996 }
2997
2998 base_length = 10;
2999 break;
3000
3001 case SFmode:
3002 if (addr == NULL_RTX)
3003 {
3004 if (REG_P (src))
3005 return 2;
3006
ceaaaeab 3007 if (satisfies_constraint_G (src))
7948a9ea 3008 return 2;
2c4a71b3 3009
7948a9ea
KH		 3010 return 6;
3011 }
3012
3013 base_length = 10;
3014 break;
3015
3016 default:
8c440872 3017 gcc_unreachable ();
7948a9ea
KH		 3018 }
3019
3020 /* Adjust the length based on the addressing mode used.
3021 Specifically, we subtract the difference between the actual
3022 length and the longest one, which is @(d:24,ERs). */
3023
3024 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
3025 if (GET_CODE (addr) == PRE_DEC
3026 || GET_CODE (addr) == POST_INC)
3027 return base_length - 6;
3028
3029 /* @ERs and @ERd are 6 bytes shorter than the longest. */
3030 if (GET_CODE (addr) == REG)
3031 return base_length - 6;
3032
3033 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
3034 longest. */
3035 if (GET_CODE (addr) == PLUS
3036 && GET_CODE (XEXP (addr, 0)) == REG
3037 && GET_CODE (XEXP (addr, 1)) == CONST_INT
3038 && INTVAL (XEXP (addr, 1)) > -32768
3039 && INTVAL (XEXP (addr, 1)) < 32767)
3040 return base_length - 4;
3041
3042 /* @aa:16 is 4 bytes shorter than the longest. */
3043 if (h8300_tiny_constant_address_p (addr))
3044 return base_length - 4;
3045
3046 /* @aa:24 is 2 bytes shorter than the longest. */
3047 if (CONSTANT_P (addr))
3048 return base_length - 2;
3049
3050 return base_length;
3051 }
3052}
3053\f
e9eba255
KH		 3054/* Output an addition insn. */
3055
366a7b27 3056const char *
cb713a8d 3057output_plussi (rtx *operands)
7d6ac401 3058{
ef4bddc2 3059 machine_mode mode = GET_MODE (operands[0]);
7d6ac401 3060
8c440872 3061 gcc_assert (mode == SImode);
7d6ac401
KH		 3062
3063 if (TARGET_H8300)
3064 {
cfedf91b
KH		 3065 if (GET_CODE (operands[2]) == REG)
3066 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3067
3068 if (GET_CODE (operands[2]) == CONST_INT)
3069 {
3070 HOST_WIDE_INT n = INTVAL (operands[2]);
3071
3072 if ((n & 0xffffff) == 0)
3073 return "add\t%z2,%z0";
3074 if ((n & 0xffff) == 0)
3075 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
3076 if ((n & 0xff) == 0)
3077 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3078 }
3079
3080 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
7d6ac401
KH		 3081 }
3082 else
3083 {
beed8fc0
AO		 3084 if (GET_CODE (operands[2]) == CONST_INT
3085 && register_operand (operands[1], VOIDmode))
7d6ac401
KH		 3086 {
3087 HOST_WIDE_INT intval = INTVAL (operands[2]);
3088
beed8fc0
AO		 3089 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3090 return "add.l\t%S2,%S0";
3091 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3092 return "sub.l\t%G2,%S0";
3093
7d6ac401
KH		 3094 /* See if we can finish with 2 bytes. */
3095
9ac7ebba 3096 switch ((unsigned int) intval & 0xffffffff)
7d6ac401
KH		 3097 {
3098 case 0x00000001:
3099 case 0x00000002:
3100 case 0x00000004:
3101 return "adds\t%2,%S0";
3102
3103 case 0xffffffff:
3104 case 0xfffffffe:
3105 case 0xfffffffc:
3106 return "subs\t%G2,%S0";
3107
3108 case 0x00010000:
3109 case 0x00020000:
3110 operands[2] = GEN_INT (intval >> 16);
3111 return "inc.w\t%2,%e0";
3112
3113 case 0xffff0000:
3114 case 0xfffe0000:
3115 operands[2] = GEN_INT (intval >> 16);
3116 return "dec.w\t%G2,%e0";
3117 }
3118
3119 /* See if we can finish with 4 bytes. */
3120 if ((intval & 0xffff) == 0)
3121 {
3122 operands[2] = GEN_INT (intval >> 16);
3123 return "add.w\t%2,%e0";
3124 }
3125 }
3126
beed8fc0
AO		 3127 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3128 {
3129 operands[2] = GEN_INT (-INTVAL (operands[2]));
3130 return "sub.l\t%S2,%S0";
3131 }
7d6ac401
KH		 3132 return "add.l\t%S2,%S0";
3133 }
3134}
3135
beed8fc0
AO		 3136/* ??? It would be much easier to add the h8sx stuff if a single function
3137 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
e9eba255
KH		 3138/* Compute the length of an addition insn. */
3139
7d6ac401 3140unsigned int
cb713a8d 3141compute_plussi_length (rtx *operands)
7d6ac401 3142{
ef4bddc2 3143 machine_mode mode = GET_MODE (operands[0]);
7d6ac401 3144
8c440872 3145 gcc_assert (mode == SImode);
7d6ac401
KH		 3146
3147 if (TARGET_H8300)
3148 {
cfedf91b
KH		 3149 if (GET_CODE (operands[2]) == REG)
3150 return 6;
3151
3152 if (GET_CODE (operands[2]) == CONST_INT)
3153 {
3154 HOST_WIDE_INT n = INTVAL (operands[2]);
3155
3156 if ((n & 0xffffff) == 0)
3157 return 2;
3158 if ((n & 0xffff) == 0)
3159 return 4;
3160 if ((n & 0xff) == 0)
3161 return 6;
3162 }
3163
3164 return 8;
7d6ac401
KH		 3165 }
3166 else
3167 {
beed8fc0
AO		 3168 if (GET_CODE (operands[2]) == CONST_INT
3169 && register_operand (operands[1], VOIDmode))
7d6ac401
KH		 3170 {
3171 HOST_WIDE_INT intval = INTVAL (operands[2]);
3172
beed8fc0
AO		 3173 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3174 return 2;
3175 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3176 return 2;
3177
7d6ac401
KH		 3178 /* See if we can finish with 2 bytes. */
3179
9ac7ebba 3180 switch ((unsigned int) intval & 0xffffffff)
7d6ac401
KH		 3181 {
3182 case 0x00000001:
3183 case 0x00000002:
3184 case 0x00000004:
3185 return 2;
3186
3187 case 0xffffffff:
3188 case 0xfffffffe:
3189 case 0xfffffffc:
3190 return 2;
3191
3192 case 0x00010000:
3193 case 0x00020000:
3194 return 2;
3195
3196 case 0xffff0000:
3197 case 0xfffe0000:
3198 return 2;
3199 }
3200
3201 /* See if we can finish with 4 bytes. */
3202 if ((intval & 0xffff) == 0)
3203 return 4;
3204 }
3205
beed8fc0
AO		 3206 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3207 return h8300_length_from_table (operands[0],
3208 GEN_INT (-INTVAL (operands[2])),
3209 &addl_length_table);
3210 else
3211 return h8300_length_from_table (operands[0], operands[2],
3212 &addl_length_table);
7d6ac401
KH		 3213 return 6;
3214 }
3215}
3216
e9eba255
KH		 3217/* Compute which flag bits are valid after an addition insn. */
3218
9690aa8e 3219enum attr_cc
cb713a8d 3220compute_plussi_cc (rtx *operands)
7d6ac401 3221{
ef4bddc2 3222 machine_mode mode = GET_MODE (operands[0]);
7d6ac401 3223
8c440872 3224 gcc_assert (mode == SImode);
7d6ac401
KH		 3225
3226 if (TARGET_H8300)
3227 {
cfedf91b 3228 return CC_CLOBBER;
7d6ac401
KH		 3229 }
3230 else
3231 {
beed8fc0
AO		 3232 if (GET_CODE (operands[2]) == CONST_INT
3233 && register_operand (operands[1], VOIDmode))
7d6ac401
KH		 3234 {
3235 HOST_WIDE_INT intval = INTVAL (operands[2]);
3236
beed8fc0
AO		 3237 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3238 return CC_SET_ZN;
3239 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3240 return CC_SET_ZN;
3241
7d6ac401
KH		 3242 /* See if we can finish with 2 bytes. */
3243
9ac7ebba 3244 switch ((unsigned int) intval & 0xffffffff)
7d6ac401
KH		 3245 {
3246 case 0x00000001:
3247 case 0x00000002:
3248 case 0x00000004:
3249 return CC_NONE_0HIT;
3250
3251 case 0xffffffff:
3252 case 0xfffffffe:
3253 case 0xfffffffc:
3254 return CC_NONE_0HIT;
3255
3256 case 0x00010000:
3257 case 0x00020000:
3258 return CC_CLOBBER;
3259
3260 case 0xffff0000:
3261 case 0xfffe0000:
3262 return CC_CLOBBER;
3263 }
3264
3265 /* See if we can finish with 4 bytes. */
3266 if ((intval & 0xffff) == 0)
3267 return CC_CLOBBER;
3268 }
3269
3270 return CC_SET_ZN;
3271 }
3272}
3273\f
e9eba255
KH		 3274/* Output a logical insn. */
3275
7d6ac401 3276const char *
ef4bddc2 3277output_logical_op (machine_mode mode, rtx *operands)
366a7b27 3278{
b42cff6b
KH		 3279 /* Figure out the logical op that we need to perform. */
3280 enum rtx_code code = GET_CODE (operands[3]);
366a7b27 3281 /* Pretend that every byte is affected if both operands are registers. */
7798db98 3282 const unsigned HOST_WIDE_INT intval =
366a7b27 3283 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
beed8fc0
AO		 3284 /* Always use the full instruction if the
3285 first operand is in memory. It is better
3286 to use define_splits to generate the shorter
3287 sequence where valid. */
3288 && register_operand (operands[1], VOIDmode)
366a7b27
KH		 3289 ? INTVAL (operands[2]) : 0x55555555);
3290 /* The determinant of the algorithm. If we perform an AND, 0
3291 affects a bit. Otherwise, 1 affects a bit. */
7798db98 3292 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
f9ac2f95
KH		 3293 /* Break up DET into pieces. */
3294 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3295 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
c5e7ce43
KH		 3296 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3297 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
f9ac2f95
KH		 3298 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3299 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3300 int lower_half_easy_p = 0;
3301 int upper_half_easy_p = 0;
366a7b27
KH		 3302 /* The name of an insn. */
3303 const char *opname;
3304 char insn_buf[100];
3305
3306 switch (code)
3307 {
3308 case AND:
3309 opname = "and";
3310 break;
3311 case IOR:
3312 opname = "or";
3313 break;
3314 case XOR:
3315 opname = "xor";
3316 break;
3317 default:
8c440872 3318 gcc_unreachable ();
366a7b27
KH		 3319 }
3320
3321 switch (mode)
3322 {
3323 case HImode:
3324 /* First, see if we can finish with one insn. */
3325 if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 3326 && b0 != 0
3327 && b1 != 0)
366a7b27
KH		 3328 {
3329 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
3330 output_asm_insn (insn_buf, operands);
3331 }
3332 else
3333 {
3334 /* Take care of the lower byte. */
c5e7ce43 3335 if (b0 != 0)
366a7b27
KH		 3336 {
3337 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
3338 output_asm_insn (insn_buf, operands);
3339 }
3340 /* Take care of the upper byte. */
c5e7ce43 3341 if (b1 != 0)
366a7b27
KH		 3342 {
3343 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
3344 output_asm_insn (insn_buf, operands);
3345 }
3346 }
3347 break;
3348 case SImode:
f9ac2f95
KH		 3349 if (TARGET_H8300H || TARGET_H8300S)
3350 {
3351 /* Determine if the lower half can be taken care of in no more
3352 than two bytes. */
3353 lower_half_easy_p = (b0 == 0
3354 || b1 == 0
3355 || (code != IOR && w0 == 0xffff));
3356
3357 /* Determine if the upper half can be taken care of in no more
3358 than two bytes. */
3359 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3360 || (code == AND && w1 == 0xff00));
3361 }
366a7b27 3362
f9ac2f95
KH		 3363 /* Check if doing everything with one insn is no worse than
3364 using multiple insns. */
366a7b27 3365 if ((TARGET_H8300H || TARGET_H8300S)
f9ac2f95 3366 && w0 != 0 && w1 != 0
472f2723
KH		 3367 && !(lower_half_easy_p && upper_half_easy_p)
3368 && !(code == IOR && w1 == 0xffff
3369 && (w0 & 0x8000) != 0 && lower_half_easy_p))
366a7b27
KH		 3370 {
3371 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
3372 output_asm_insn (insn_buf, operands);
3373 }
3374 else
3375 {
3376 /* Take care of the lower and upper words individually. For
3377 each word, we try different methods in the order of
3378
3379 1) the special insn (in case of AND or XOR),
3380 2) the word-wise insn, and
3381 3) The byte-wise insn. */
c5e7ce43 3382 if (w0 == 0xffff
6dfa4005 3383 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
366a7b27 3384 output_asm_insn ((code == AND)
187462ac 3385 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
366a7b27
KH		 3386 operands);
3387 else if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 3388 && (b0 != 0)
3389 && (b1 != 0))
366a7b27
KH		 3390 {
3391 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
3392 output_asm_insn (insn_buf, operands);
3393 }
3394 else
3395 {
c5e7ce43 3396 if (b0 != 0)
366a7b27
KH		 3397 {
3398 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
3399 output_asm_insn (insn_buf, operands);
3400 }
c5e7ce43 3401 if (b1 != 0)
366a7b27
KH		 3402 {
3403 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
3404 output_asm_insn (insn_buf, operands);
3405 }
3406 }
3407
c5e7ce43 3408 if ((w1 == 0xffff)
6dfa4005 3409 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
366a7b27 3410 output_asm_insn ((code == AND)
187462ac 3411 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
366a7b27 3412 operands);
472f2723
KH		 3413 else if ((TARGET_H8300H || TARGET_H8300S)
3414 && code == IOR
3415 && w1 == 0xffff
3416 && (w0 & 0x8000) != 0)
3417 {
3418 output_asm_insn ("exts.l\t%S0", operands);
3419 }
a6e8d113
KH		 3420 else if ((TARGET_H8300H || TARGET_H8300S)
3421 && code == AND
c5e7ce43 3422 && w1 == 0xff00)
a6e8d113 3423 {
dc5f17ec 3424 output_asm_insn ("extu.w\t%e0", operands);
a6e8d113 3425 }
366a7b27
KH		 3426 else if (TARGET_H8300H || TARGET_H8300S)
3427 {
c5e7ce43 3428 if (w1 != 0)
366a7b27
KH		 3429 {
3430 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
3431 output_asm_insn (insn_buf, operands);
3432 }
3433 }
3434 else
3435 {
c5e7ce43 3436 if (b2 != 0)
366a7b27
KH		 3437 {
3438 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
3439 output_asm_insn (insn_buf, operands);
3440 }
c5e7ce43 3441 if (b3 != 0)
366a7b27
KH		 3442 {
3443 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
3444 output_asm_insn (insn_buf, operands);
3445 }
3446 }
3447 }
3448 break;
3449 default:
8c440872 3450 gcc_unreachable ();
366a7b27
KH		 3451 }
3452 return "";
3453}
40367e2d 3454
e9eba255
KH		 3455/* Compute the length of a logical insn. */
3456
40367e2d 3457unsigned int
ef4bddc2 3458compute_logical_op_length (machine_mode mode, rtx *operands)
40367e2d 3459{
b42cff6b
KH		 3460 /* Figure out the logical op that we need to perform. */
3461 enum rtx_code code = GET_CODE (operands[3]);
40367e2d 3462 /* Pretend that every byte is affected if both operands are registers. */
7798db98 3463 const unsigned HOST_WIDE_INT intval =
40367e2d 3464 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
beed8fc0
AO		 3465 /* Always use the full instruction if the
3466 first operand is in memory. It is better
3467 to use define_splits to generate the shorter
3468 sequence where valid. */
3469 && register_operand (operands[1], VOIDmode)
40367e2d
KH		 3470 ? INTVAL (operands[2]) : 0x55555555);
3471 /* The determinant of the algorithm. If we perform an AND, 0
3472 affects a bit. Otherwise, 1 affects a bit. */
7798db98 3473 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
f9ac2f95
KH		 3474 /* Break up DET into pieces. */
3475 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3476 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
c5e7ce43
KH		 3477 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3478 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
f9ac2f95
KH		 3479 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3480 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3481 int lower_half_easy_p = 0;
3482 int upper_half_easy_p = 0;
40367e2d
KH		 3483 /* Insn length. */
3484 unsigned int length = 0;
3485
3486 switch (mode)
3487 {
3488 case HImode:
3489 /* First, see if we can finish with one insn. */
3490 if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 3491 && b0 != 0
3492 && b1 != 0)
40367e2d 3493 {
beed8fc0
AO		 3494 length = h8300_length_from_table (operands[1], operands[2],
3495 &logicw_length_table);
40367e2d
KH		 3496 }
3497 else
3498 {
3499 /* Take care of the lower byte. */
c5e7ce43 3500 if (b0 != 0)
40367e2d
KH		 3501 length += 2;
3502
3503 /* Take care of the upper byte. */
c5e7ce43 3504 if (b1 != 0)
40367e2d
KH		 3505 length += 2;
3506 }
3507 break;
3508 case SImode:
f9ac2f95
KH		 3509 if (TARGET_H8300H || TARGET_H8300S)
3510 {
3511 /* Determine if the lower half can be taken care of in no more
3512 than two bytes. */
3513 lower_half_easy_p = (b0 == 0
3514 || b1 == 0
3515 || (code != IOR && w0 == 0xffff));
3516
3517 /* Determine if the upper half can be taken care of in no more
3518 than two bytes. */
3519 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3520 || (code == AND && w1 == 0xff00));
3521 }
40367e2d 3522
f9ac2f95
KH		 3523 /* Check if doing everything with one insn is no worse than
3524 using multiple insns. */
40367e2d 3525 if ((TARGET_H8300H || TARGET_H8300S)
f9ac2f95 3526 && w0 != 0 && w1 != 0
472f2723
KH		 3527 && !(lower_half_easy_p && upper_half_easy_p)
3528 && !(code == IOR && w1 == 0xffff
3529 && (w0 & 0x8000) != 0 && lower_half_easy_p))
40367e2d 3530 {
beed8fc0
AO		 3531 length = h8300_length_from_table (operands[1], operands[2],
3532 &logicl_length_table);
40367e2d
KH		 3533 }
3534 else
3535 {
3536 /* Take care of the lower and upper words individually. For
3537 each word, we try different methods in the order of
3538
3539 1) the special insn (in case of AND or XOR),
3540 2) the word-wise insn, and
3541 3) The byte-wise insn. */
c5e7ce43 3542 if (w0 == 0xffff
40367e2d
KH		 3543 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3544 {
3545 length += 2;
3546 }
3547 else if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 3548 && (b0 != 0)
3549 && (b1 != 0))
40367e2d
KH		 3550 {
3551 length += 4;
3552 }
3553 else
3554 {
c5e7ce43 3555 if (b0 != 0)
40367e2d
KH		 3556 length += 2;
3557
c5e7ce43 3558 if (b1 != 0)
40367e2d
KH		 3559 length += 2;
3560 }
3561
c5e7ce43 3562 if (w1 == 0xffff
40367e2d
KH		 3563 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3564 {
3565 length += 2;
3566 }
472f2723
KH		 3567 else if ((TARGET_H8300H || TARGET_H8300S)
3568 && code == IOR
3569 && w1 == 0xffff
3570 && (w0 & 0x8000) != 0)
3571 {
3572 length += 2;
3573 }
a6e8d113
KH		 3574 else if ((TARGET_H8300H || TARGET_H8300S)
3575 && code == AND
c5e7ce43 3576 && w1 == 0xff00)
a6e8d113
KH		 3577 {
3578 length += 2;
3579 }
40367e2d
KH		 3580 else if (TARGET_H8300H || TARGET_H8300S)
3581 {
c5e7ce43 3582 if (w1 != 0)
40367e2d
KH		 3583 length += 4;
3584 }
3585 else
3586 {
c5e7ce43 3587 if (b2 != 0)
40367e2d
KH		 3588 length += 2;
3589
c5e7ce43 3590 if (b3 != 0)
40367e2d
KH		 3591 length += 2;
3592 }
3593 }
3594 break;
3595 default:
8c440872 3596 gcc_unreachable ();
40367e2d
KH		 3597 }
3598 return length;
3599}
b42cff6b 3600
e9eba255
KH		 3601/* Compute which flag bits are valid after a logical insn. */
3602
9690aa8e 3603enum attr_cc
ef4bddc2 3604compute_logical_op_cc (machine_mode mode, rtx *operands)
b42cff6b
KH		 3605{
3606 /* Figure out the logical op that we need to perform. */
3607 enum rtx_code code = GET_CODE (operands[3]);
3608 /* Pretend that every byte is affected if both operands are registers. */
7798db98 3609 const unsigned HOST_WIDE_INT intval =
b42cff6b 3610 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
beed8fc0
AO		 3611 /* Always use the full instruction if the
3612 first operand is in memory. It is better
3613 to use define_splits to generate the shorter
3614 sequence where valid. */
3615 && register_operand (operands[1], VOIDmode)
b42cff6b
KH		 3616 ? INTVAL (operands[2]) : 0x55555555);
3617 /* The determinant of the algorithm. If we perform an AND, 0
3618 affects a bit. Otherwise, 1 affects a bit. */
7798db98 3619 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
f9ac2f95
KH		 3620 /* Break up DET into pieces. */
3621 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3622 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3623 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3624 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3625 int lower_half_easy_p = 0;
3626 int upper_half_easy_p = 0;
b42cff6b
KH		 3627 /* Condition code. */
3628 enum attr_cc cc = CC_CLOBBER;
3629
3630 switch (mode)
3631 {
3632 case HImode:
3633 /* First, see if we can finish with one insn. */
3634 if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 3635 && b0 != 0
3636 && b1 != 0)
b42cff6b
KH		 3637 {
3638 cc = CC_SET_ZNV;
3639 }
3640 break;
3641 case SImode:
f9ac2f95
KH		 3642 if (TARGET_H8300H || TARGET_H8300S)
3643 {
3644 /* Determine if the lower half can be taken care of in no more
3645 than two bytes. */
3646 lower_half_easy_p = (b0 == 0
3647 || b1 == 0
3648 || (code != IOR && w0 == 0xffff));
3649
3650 /* Determine if the upper half can be taken care of in no more
3651 than two bytes. */
3652 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3653 || (code == AND && w1 == 0xff00));
3654 }
b42cff6b 3655
f9ac2f95
KH		 3656 /* Check if doing everything with one insn is no worse than
3657 using multiple insns. */
b42cff6b 3658 if ((TARGET_H8300H || TARGET_H8300S)
f9ac2f95 3659 && w0 != 0 && w1 != 0
472f2723
KH		 3660 && !(lower_half_easy_p && upper_half_easy_p)
3661 && !(code == IOR && w1 == 0xffff
3662 && (w0 & 0x8000) != 0 && lower_half_easy_p))
b42cff6b
KH		 3663 {
3664 cc = CC_SET_ZNV;
3665 }
472f2723
KH		 3666 else
3667 {
3668 if ((TARGET_H8300H || TARGET_H8300S)
3669 && code == IOR
3670 && w1 == 0xffff
3671 && (w0 & 0x8000) != 0)
3672 {
3673 cc = CC_SET_ZNV;
3674 }
3675 }
b42cff6b
KH		 3676 break;
3677 default:
8c440872 3678 gcc_unreachable ();
b42cff6b
KH		 3679 }
3680 return cc;
3681}
366a7b27 3682\f
8981ecd3
KH		 3683/* Expand a conditional branch. */
3684
3685void
f90b7a5a 3686h8300_expand_branch (rtx operands[])
8981ecd3 3687{
f90b7a5a
PB		 3688 enum rtx_code code = GET_CODE (operands[0]);
3689 rtx op0 = operands[1];
3690 rtx op1 = operands[2];
3691 rtx label = operands[3];
8981ecd3
KH		 3692 rtx tmp;
3693
f90b7a5a 3694 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
f7df4a84 3695 emit_insn (gen_rtx_SET (cc0_rtx, tmp));
f90b7a5a 3696
8981ecd3
KH		 3697 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
3698 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
3699 gen_rtx_LABEL_REF (VOIDmode, label),
3700 pc_rtx);
f7df4a84 3701 emit_jump_insn (gen_rtx_SET (pc_rtx, tmp));
8981ecd3 3702}
f90b7a5a
PB		 3703
3704
3705/* Expand a conditional store. */
3706
3707void
3708h8300_expand_store (rtx operands[])
3709{
3710 rtx dest = operands[0];
3711 enum rtx_code code = GET_CODE (operands[1]);
3712 rtx op0 = operands[2];
3713 rtx op1 = operands[3];
3714 rtx tmp;
3715
3716 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
f7df4a84 3717 emit_insn (gen_rtx_SET (cc0_rtx, tmp));
f90b7a5a
PB		 3718
3719 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx);
f7df4a84 3720 emit_insn (gen_rtx_SET (dest, tmp));
f90b7a5a 3721}
8981ecd3 3722\f
48837e29
DE		 3723/* Shifts.
3724
005e3e05
KH		 3725 We devote a fair bit of code to getting efficient shifts since we
3726 can only shift one bit at a time on the H8/300 and H8/300H and only
3db11b5c 3727 one or two bits at a time on the H8S.
005e3e05
KH		 3728
3729 All shift code falls into one of the following ways of
3730 implementation:
3731
3732 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3733 when a straight line shift is about the same size or smaller than
3734 a loop.
3735
3736 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3737 off the bits we don't need. This is used when only a few of the
3738 bits in the original value will survive in the shifted value.
3739
3740 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3741 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3742 shifts can be added if the shift count is slightly more than 8 or
3743 16. This case also includes other oddballs that are not worth
f411c849 3744 explaining here.
005e3e05 3745
3db11b5c 3746 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
005e3e05 3747
5ec0b66e
KH		 3748 For each shift count, we try to use code that has no trade-off
3749 between code size and speed whenever possible.
3750
3751 If the trade-off is unavoidable, we try to be reasonable.
3752 Specifically, the fastest version is one instruction longer than
3753 the shortest version, we take the fastest version. We also provide
3754 the use a way to switch back to the shortest version with -Os.
3755
3756 For the details of the shift algorithms for various shift counts,
3757 refer to shift_alg_[qhs]i. */
07aae5c2 3758
beed8fc0
AO		 3759/* Classify a shift with the given mode and code. OP is the shift amount. */
3760
3761enum h8sx_shift_type
ef4bddc2 3762h8sx_classify_shift (machine_mode mode, enum rtx_code code, rtx op)
beed8fc0
AO		 3763{
3764 if (!TARGET_H8300SX)
3765 return H8SX_SHIFT_NONE;
3766
3767 switch (code)
3768 {
3769 case ASHIFT:
3770 case LSHIFTRT:
3771 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3772 if (GET_CODE (op) != CONST_INT)
3773 return H8SX_SHIFT_BINARY;
3774
3775 /* Reject out-of-range shift amounts. */
3776 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
3777 return H8SX_SHIFT_NONE;
3778
3779 /* Power-of-2 shifts are effectively unary operations. */
3780 if (exact_log2 (INTVAL (op)) >= 0)
3781 return H8SX_SHIFT_UNARY;
3782
3783 return H8SX_SHIFT_BINARY;
3784
3785 case ASHIFTRT:
3786 if (op == const1_rtx || op == const2_rtx)
3787 return H8SX_SHIFT_UNARY;
3788 return H8SX_SHIFT_NONE;
3789
3790 case ROTATE:
3791 if (GET_CODE (op) == CONST_INT
3792 && (INTVAL (op) == 1
3793 || INTVAL (op) == 2
3794 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
3795 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
3796 return H8SX_SHIFT_UNARY;
3797 return H8SX_SHIFT_NONE;
3798
3799 default:
3800 return H8SX_SHIFT_NONE;
3801 }
3802}
3803
beed8fc0
AO		 3804/* Return the asm template for a single h8sx shift instruction.
3805 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3806 is the source and OPERANDS[3] is the shift. SUFFIX is the
88cb339e 3807 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
beed8fc0
AO		 3808 prefix for the destination operand. */
3809
3810const char *
3811output_h8sx_shift (rtx *operands, int suffix, int optype)
3812{
3813 static char buffer[16];
3814 const char *stem;
3815
3816 switch (GET_CODE (operands[3]))
3817 {
3818 case ASHIFT:
3819 stem = "shll";
3820 break;
3821
3822 case ASHIFTRT:
3823 stem = "shar";
3824 break;
3825
3826 case LSHIFTRT:
3827 stem = "shlr";
3828 break;
3829
3830 case ROTATE:
3831 stem = "rotl";
3832 if (INTVAL (operands[2]) > 2)
3833 {
3834 /* This is really a right rotate. */
3835 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
3836 - INTVAL (operands[2]));
3837 stem = "rotr";
3838 }
3839 break;
3840
3841 default:
8c440872 3842 gcc_unreachable ();
beed8fc0
AO		 3843 }
3844 if (operands[2] == const1_rtx)
3845 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
3846 else
3847 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
3848 return buffer;
3849}
48837e29 3850
317d21e9 3851/* Emit code to do shifts. */
48837e29 3852
beed8fc0 3853bool
ef4bddc2 3854expand_a_shift (machine_mode mode, enum rtx_code code, rtx operands[])
07aae5c2 3855{
beed8fc0
AO		 3856 switch (h8sx_classify_shift (mode, code, operands[2]))
3857 {
3858 case H8SX_SHIFT_BINARY:
3859 operands[1] = force_reg (mode, operands[1]);
3860 return false;
3861
3862 case H8SX_SHIFT_UNARY:
3863 return false;
3864
3865 case H8SX_SHIFT_NONE:
3866 break;
3867 }
3868
bc9b880c 3869 emit_move_insn (copy_rtx (operands[0]), operands[1]);
07aae5c2 3870
07e4d94e
KH		 3871 /* Need a loop to get all the bits we want - we generate the
3872 code at emit time, but need to allocate a scratch reg now. */
48837e29 3873
c5c76735
JL		 3874 emit_insn (gen_rtx_PARALLEL
3875 (VOIDmode,
48837e29 3876 gen_rtvec (2,
f7df4a84 3877 gen_rtx_SET (copy_rtx (operands[0]),
0f4c242b 3878 gen_rtx_fmt_ee (code, mode,
bc9b880c 3879 copy_rtx (operands[0]), operands[2])),
c5c76735
JL		 3880 gen_rtx_CLOBBER (VOIDmode,
3881 gen_rtx_SCRATCH (QImode)))));
beed8fc0 3882 return true;
48837e29
DE		 3883}
3884
48837e29
DE		 3885/* Symbols of the various modes which can be used as indices. */
3886
3887enum shift_mode
1a63219b
KH		 3888{
3889 QIshift, HIshift, SIshift
3890};
48837e29 3891
269c14e1
DE		 3892/* For single bit shift insns, record assembler and what bits of the
3893 condition code are valid afterwards (represented as various CC_FOO
3894 bits, 0 means CC isn't left in a usable state). */
48837e29
DE		 3895
3896struct shift_insn
3897{
8b60264b 3898 const char *const assembler;
9690aa8e 3899 const enum attr_cc cc_valid;
48837e29
DE		 3900};
3901
3902/* Assembler instruction shift table.
3903
3904 These tables are used to look up the basic shifts.
07e4d94e 3905 They are indexed by cpu, shift_type, and mode. */
07aae5c2 3906
48837e29
DE		 3907static const struct shift_insn shift_one[2][3][3] =
3908{
3909/* H8/300 */
3910 {
3911/* SHIFT_ASHIFT */
3912 {
45ca2106
KH		 3913 { "shll\t%X0", CC_SET_ZNV },
3914 { "add.w\t%T0,%T0", CC_SET_ZN },
3915 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
48837e29
DE		 3916 },
3917/* SHIFT_LSHIFTRT */
3918 {
45ca2106
KH		 3919 { "shlr\t%X0", CC_SET_ZNV },
3920 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3921 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
48837e29
DE		 3922 },
3923/* SHIFT_ASHIFTRT */
3924 {
45ca2106
KH		 3925 { "shar\t%X0", CC_SET_ZNV },
3926 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3927 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
48837e29
DE		 3928 }
3929 },
3930/* H8/300H */
3931 {
3932/* SHIFT_ASHIFT */
3933 {
45ca2106
KH		 3934 { "shll.b\t%X0", CC_SET_ZNV },
3935 { "shll.w\t%T0", CC_SET_ZNV },
3936 { "shll.l\t%S0", CC_SET_ZNV }
48837e29
DE		 3937 },
3938/* SHIFT_LSHIFTRT */
3939 {
45ca2106
KH		 3940 { "shlr.b\t%X0", CC_SET_ZNV },
3941 { "shlr.w\t%T0", CC_SET_ZNV },
3942 { "shlr.l\t%S0", CC_SET_ZNV }
48837e29
DE		 3943 },
3944/* SHIFT_ASHIFTRT */
3945 {
45ca2106
KH		 3946 { "shar.b\t%X0", CC_SET_ZNV },
3947 { "shar.w\t%T0", CC_SET_ZNV },
3948 { "shar.l\t%S0", CC_SET_ZNV }
48837e29
DE		 3949 }
3950 }
3951};
07aae5c2 3952
51c0c1d7
JL		 3953static const struct shift_insn shift_two[3][3] =
3954{
3955/* SHIFT_ASHIFT */
3956 {
45ca2106
KH		 3957 { "shll.b\t#2,%X0", CC_SET_ZNV },
3958 { "shll.w\t#2,%T0", CC_SET_ZNV },
3959 { "shll.l\t#2,%S0", CC_SET_ZNV }
51c0c1d7
JL		 3960 },
3961/* SHIFT_LSHIFTRT */
3962 {
45ca2106
KH		 3963 { "shlr.b\t#2,%X0", CC_SET_ZNV },
3964 { "shlr.w\t#2,%T0", CC_SET_ZNV },
3965 { "shlr.l\t#2,%S0", CC_SET_ZNV }
51c0c1d7
JL		 3966 },
3967/* SHIFT_ASHIFTRT */
3968 {
45ca2106
KH		 3969 { "shar.b\t#2,%X0", CC_SET_ZNV },
3970 { "shar.w\t#2,%T0", CC_SET_ZNV },
3971 { "shar.l\t#2,%S0", CC_SET_ZNV }
51c0c1d7
JL		 3972 }
3973};
3974
48837e29
DE		 3975/* Rotates are organized by which shift they'll be used in implementing.
3976 There's no need to record whether the cc is valid afterwards because
3977 it is the AND insn that will decide this. */
07aae5c2 3978
48837e29
DE		 3979static const char *const rotate_one[2][3][3] =
3980{
3981/* H8/300 */
3982 {
3983/* SHIFT_ASHIFT */
3984 {
51c0c1d7
JL		 3985 "rotr\t%X0",
3986 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
48837e29
DE		 3987 0
3988 },
3989/* SHIFT_LSHIFTRT */
3990 {
51c0c1d7
JL		 3991 "rotl\t%X0",
3992 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
48837e29
DE		 3993 0
3994 },
3995/* SHIFT_ASHIFTRT */
3996 {
51c0c1d7
JL		 3997 "rotl\t%X0",
3998 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
48837e29 3999 0
07aae5c2 4000 }
48837e29
DE		 4001 },
4002/* H8/300H */
4003 {
4004/* SHIFT_ASHIFT */
4005 {
51c0c1d7
JL		 4006 "rotr.b\t%X0",
4007 "rotr.w\t%T0",
4008 "rotr.l\t%S0"
48837e29
DE		 4009 },
4010/* SHIFT_LSHIFTRT */
07aae5c2 4011 {
51c0c1d7
JL		 4012 "rotl.b\t%X0",
4013 "rotl.w\t%T0",
4014 "rotl.l\t%S0"
48837e29
DE		 4015 },
4016/* SHIFT_ASHIFTRT */
4017 {
51c0c1d7
JL		 4018 "rotl.b\t%X0",
4019 "rotl.w\t%T0",
4020 "rotl.l\t%S0"
48837e29
DE		 4021 }
4022 }
4023};
4024
51c0c1d7
JL		 4025static const char *const rotate_two[3][3] =
4026{
4027/* SHIFT_ASHIFT */
4028 {
4029 "rotr.b\t#2,%X0",
4030 "rotr.w\t#2,%T0",
4031 "rotr.l\t#2,%S0"
4032 },
4033/* SHIFT_LSHIFTRT */
4034 {
4035 "rotl.b\t#2,%X0",
4036 "rotl.w\t#2,%T0",
4037 "rotl.l\t#2,%S0"
4038 },
4039/* SHIFT_ASHIFTRT */
4040 {
4041 "rotl.b\t#2,%X0",
4042 "rotl.w\t#2,%T0",
4043 "rotl.l\t#2,%S0"
4044 }
4045};
4046
35fb3d1f
KH		 4047struct shift_info {
4048 /* Shift algorithm. */
4049 enum shift_alg alg;
4050
4051 /* The number of bits to be shifted by shift1 and shift2. Valid
4052 when ALG is SHIFT_SPECIAL. */
4053 unsigned int remainder;
4054
4055 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
4056 const char *special;
4057
4058 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
9cd10576 4059 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
35fb3d1f
KH		 4060 const char *shift1;
4061
4062 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
9cd10576 4063 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
35fb3d1f
KH		 4064 const char *shift2;
4065
45ca2106 4066 /* CC status for SHIFT_INLINE. */
9690aa8e 4067 enum attr_cc cc_inline;
45ca2106
KH		 4068
4069 /* CC status for SHIFT_SPECIAL. */
9690aa8e 4070 enum attr_cc cc_special;
35fb3d1f
KH		 4071};
4072
cb713a8d
KH		 4073static void get_shift_alg (enum shift_type,
4074 enum shift_mode, unsigned int,
4075 struct shift_info *);
441d04c6 4076
c009a745
KH		 4077/* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
4078 best algorithm for doing the shift. The assembler code is stored
5ec0b66e
KH		 4079 in the pointers in INFO. We achieve the maximum efficiency in most
4080 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
4081 SImode in particular have a lot of room to optimize.
4082
4083 We first determine the strategy of the shift algorithm by a table
4084 lookup. If that tells us to use a hand crafted assembly code, we
4085 go into the big switch statement to find what that is. Otherwise,
4086 we resort to a generic way, such as inlining. In either case, the
4087 result is returned through INFO. */
48837e29 4088
cb33eb17 4089static void
cb713a8d
KH		 4090get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
4091 unsigned int count, struct shift_info *info)
48837e29 4092{
b9b575e6 4093 enum h8_cpu cpu;
769828ab
KH		 4094
4095 /* Find the target CPU. */
4096 if (TARGET_H8300)
b9b575e6 4097 cpu = H8_300;
2f6bd6eb 4098 else if (TARGET_H8300S)
b9b575e6 4099 cpu = H8_S;
2f6bd6eb
YS		 4100 else
4101 cpu = H8_300H;
769828ab 4102
96eaf358 4103 /* Find the shift algorithm. */
b9b575e6 4104 info->alg = SHIFT_LOOP;
48837e29
DE		 4105 switch (shift_mode)
4106 {
4107 case QIshift:
b9b575e6 4108 if (count < GET_MODE_BITSIZE (QImode))
96eaf358
KH		 4109 info->alg = shift_alg_qi[cpu][shift_type][count];
4110 break;
769828ab 4111
96eaf358 4112 case HIshift:
b9b575e6 4113 if (count < GET_MODE_BITSIZE (HImode))
96eaf358
KH		 4114 info->alg = shift_alg_hi[cpu][shift_type][count];
4115 break;
4116
4117 case SIshift:
b9b575e6 4118 if (count < GET_MODE_BITSIZE (SImode))
96eaf358
KH		 4119 info->alg = shift_alg_si[cpu][shift_type][count];
4120 break;
4121
4122 default:
8c440872 4123 gcc_unreachable ();
96eaf358
KH		 4124 }
4125
4126 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4127 switch (info->alg)
4128 {
4129 case SHIFT_INLINE:
4130 info->remainder = count;
4131 /* Fall through. */
4132
4133 case SHIFT_LOOP:
4134 /* It is up to the caller to know that looping clobbers cc. */
4135 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4136 info->shift2 = shift_two[shift_type][shift_mode].assembler;
45ca2106 4137 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
96eaf358
KH		 4138 goto end;
4139
4140 case SHIFT_ROT_AND:
4141 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
4142 info->shift2 = rotate_two[shift_type][shift_mode];
45ca2106 4143 info->cc_inline = CC_CLOBBER;
96eaf358
KH		 4144 goto end;
4145
4146 case SHIFT_SPECIAL:
4147 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4148 info->remainder = 0;
4149 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4150 info->shift2 = shift_two[shift_type][shift_mode].assembler;
45ca2106
KH		 4151 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4152 info->cc_special = CC_CLOBBER;
96eaf358
KH		 4153 break;
4154 }
51c0c1d7 4155
96eaf358
KH		 4156 /* Here we only deal with SHIFT_SPECIAL. */
4157 switch (shift_mode)
4158 {
4159 case QIshift:
769828ab
KH		 4160 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4161 through the entire value. */
8c440872
NS		 4162 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
4163 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
4164 goto end;
769828ab
KH		 4165
4166 case HIshift:
769828ab 4167 if (count == 7)
51c0c1d7 4168 {
a77b1dbc 4169 switch (shift_type)
51c0c1d7 4170 {
a77b1dbc
KH		 4171 case SHIFT_ASHIFT:
4172 if (TARGET_H8300)
4173 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4174 else
4175 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
692b7eb3 4176 goto end;
a77b1dbc
KH		 4177 case SHIFT_LSHIFTRT:
4178 if (TARGET_H8300)
4179 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4180 else
4181 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
692b7eb3 4182 goto end;
a77b1dbc 4183 case SHIFT_ASHIFTRT:
35fb3d1f 4184 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
692b7eb3 4185 goto end;
48837e29 4186 }
07aae5c2 4187 }
b30686ec 4188 else if ((8 <= count && count <= 13)
a38b3eea 4189 || (TARGET_H8300S && count == 14))
07aae5c2 4190 {
a7812c0b
KH		 4191 info->remainder = count - 8;
4192
51c0c1d7 4193 switch (shift_type)
48837e29 4194 {
51c0c1d7 4195 case SHIFT_ASHIFT:
35fb3d1f 4196 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
692b7eb3 4197 goto end;
51c0c1d7 4198 case SHIFT_LSHIFTRT:
a7612343
KH		 4199 if (TARGET_H8300)
4200 {
4201 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4202 info->shift1 = "shlr.b\t%s0";
45ca2106 4203 info->cc_inline = CC_SET_ZNV;
a7612343
KH		 4204 }
4205 else
4206 {
4207 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
45ca2106 4208 info->cc_special = CC_SET_ZNV;
a7612343 4209 }
692b7eb3 4210 goto end;
51c0c1d7
JL		 4211 case SHIFT_ASHIFTRT:
4212 if (TARGET_H8300)
a7612343
KH		 4213 {
4214 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4215 info->shift1 = "shar.b\t%s0";
a7612343 4216 }
51c0c1d7 4217 else
a7612343
KH		 4218 {
4219 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
45ca2106 4220 info->cc_special = CC_SET_ZNV;
a7612343 4221 }
692b7eb3 4222 goto end;
51c0c1d7
JL		 4223 }
4224 }
5e98fba2
DD		 4225 else if (count == 14)
4226 {
4227 switch (shift_type)
4228 {
4229 case SHIFT_ASHIFT:
4230 if (TARGET_H8300)
4231 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4232 goto end;
4233 case SHIFT_LSHIFTRT:
4234 if (TARGET_H8300)
4235 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4236 goto end;
4237 case SHIFT_ASHIFTRT:
4238 if (TARGET_H8300)
4239 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4240 else if (TARGET_H8300H)
45ca2106
KH		 4241 {
4242 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4243 info->cc_special = CC_SET_ZNV;
4244 }
5e98fba2 4245 else /* TARGET_H8300S */
8c440872 4246 gcc_unreachable ();
5e98fba2
DD		 4247 goto end;
4248 }
4249 }
1e41e866 4250 else if (count == 15)
51c0c1d7 4251 {
1e41e866
KH		 4252 switch (shift_type)
4253 {
4254 case SHIFT_ASHIFT:
4255 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4256 goto end;
4257 case SHIFT_LSHIFTRT:
4258 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4259 goto end;
4260 case SHIFT_ASHIFTRT:
4261 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4262 goto end;
4263 }
07aae5c2 4264 }
8c440872 4265 gcc_unreachable ();
51c0c1d7 4266
48837e29 4267 case SIshift:
1e41e866 4268 if (TARGET_H8300 && 8 <= count && count <= 9)
48837e29 4269 {
1e41e866
KH		 4270 info->remainder = count - 8;
4271
51c0c1d7 4272 switch (shift_type)
48837e29 4273 {
51c0c1d7 4274 case SHIFT_ASHIFT:
35fb3d1f 4275 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
692b7eb3 4276 goto end;
51c0c1d7 4277 case SHIFT_LSHIFTRT:
35fb3d1f 4278 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
1e41e866 4279 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
692b7eb3 4280 goto end;
51c0c1d7 4281 case SHIFT_ASHIFTRT:
35fb3d1f 4282 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
692b7eb3 4283 goto end;
48837e29 4284 }
48837e29 4285 }
e6bcfef9
JS		 4286 else if (count == 8 && !TARGET_H8300)
4287 {
4288 switch (shift_type)
4289 {
4290 case SHIFT_ASHIFT:
35fb3d1f 4291 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
692b7eb3 4292 goto end;
e6bcfef9 4293 case SHIFT_LSHIFTRT:
35fb3d1f 4294 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
692b7eb3 4295 goto end;
e6bcfef9 4296 case SHIFT_ASHIFTRT:
35fb3d1f 4297 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
692b7eb3 4298 goto end;
e6bcfef9
JS		 4299 }
4300 }
1e41e866
KH		 4301 else if (count == 15 && TARGET_H8300)
4302 {
4303 switch (shift_type)
4304 {
4305 case SHIFT_ASHIFT:
8c440872 4306 gcc_unreachable ();
1e41e866 4307 case SHIFT_LSHIFTRT:
a35abc3c 4308 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
1e41e866
KH		 4309 goto end;
4310 case SHIFT_ASHIFTRT:
a35abc3c 4311 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
1e41e866
KH		 4312 goto end;
4313 }
4314 }
dd69e230
KH		 4315 else if (count == 15 && !TARGET_H8300)
4316 {
4317 switch (shift_type)
4318 {
4319 case SHIFT_ASHIFT:
4320 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
45ca2106 4321 info->cc_special = CC_SET_ZNV;
dd69e230
KH		 4322 goto end;
4323 case SHIFT_LSHIFTRT:
18cf8dda 4324 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
45ca2106 4325 info->cc_special = CC_SET_ZNV;
dd69e230 4326 goto end;
aefc5826 4327 case SHIFT_ASHIFTRT:
8c440872 4328 gcc_unreachable ();
dd69e230
KH		 4329 }
4330 }
1e41e866 4331 else if ((TARGET_H8300 && 16 <= count && count <= 20)
a7812c0b 4332 || (TARGET_H8300H && 16 <= count && count <= 19)
e0f19bd0 4333 || (TARGET_H8300S && 16 <= count && count <= 21))
48837e29 4334 {
a7812c0b
KH		 4335 info->remainder = count - 16;
4336
48837e29
DE		 4337 switch (shift_type)
4338 {
4339 case SHIFT_ASHIFT:
35fb3d1f 4340 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
1e41e866 4341 if (TARGET_H8300)
b30686ec 4342 info->shift1 = "add.w\t%e0,%e0";
692b7eb3 4343 goto end;
51c0c1d7 4344 case SHIFT_LSHIFTRT:
1e41e866
KH		 4345 if (TARGET_H8300)
4346 {
a7612343
KH		 4347 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4348 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
1e41e866
KH		 4349 }
4350 else
4351 {
a7612343 4352 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
45ca2106 4353 info->cc_special = CC_SET_ZNV;
1e41e866 4354 }
692b7eb3 4355 goto end;
51c0c1d7
JL		 4356 case SHIFT_ASHIFTRT:
4357 if (TARGET_H8300)
1e41e866
KH		 4358 {
4359 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4360 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
4361 }
51c0c1d7 4362 else
1e41e866
KH		 4363 {
4364 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
45ca2106 4365 info->cc_special = CC_SET_ZNV;
1e41e866 4366 }
692b7eb3 4367 goto end;
51c0c1d7
JL		 4368 }
4369 }
1e41e866 4370 else if (TARGET_H8300 && 24 <= count && count <= 28)
f9477efd
KH		 4371 {
4372 info->remainder = count - 24;
f0b6f9a6 4373
f9477efd
KH		 4374 switch (shift_type)
4375 {
4376 case SHIFT_ASHIFT:
4377 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4378 info->shift1 = "shll.b\t%z0";
45ca2106 4379 info->cc_inline = CC_SET_ZNV;
f9477efd
KH		 4380 goto end;
4381 case SHIFT_LSHIFTRT:
4382 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4383 info->shift1 = "shlr.b\t%w0";
45ca2106 4384 info->cc_inline = CC_SET_ZNV;
f9477efd
KH		 4385 goto end;
4386 case SHIFT_ASHIFTRT:
d00f6ca6 4387 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
f9477efd 4388 info->shift1 = "shar.b\t%w0";
45ca2106 4389 info->cc_inline = CC_SET_ZNV;
7f473594
KH		 4390 goto end;
4391 }
4392 }
4a4ae922
KH		 4393 else if ((TARGET_H8300H && count == 24)
4394 || (TARGET_H8300S && 24 <= count && count <= 25))
e6bcfef9 4395 {
4a4ae922
KH		 4396 info->remainder = count - 24;
4397
e6bcfef9
JS		 4398 switch (shift_type)
4399 {
4400 case SHIFT_ASHIFT:
35fb3d1f 4401 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
692b7eb3 4402 goto end;
e6bcfef9 4403 case SHIFT_LSHIFTRT:
35fb3d1f 4404 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
45ca2106 4405 info->cc_special = CC_SET_ZNV;
692b7eb3 4406 goto end;
e6bcfef9 4407 case SHIFT_ASHIFTRT:
35fb3d1f 4408 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
45ca2106 4409 info->cc_special = CC_SET_ZNV;
692b7eb3 4410 goto end;
e6bcfef9
JS		 4411 }
4412 }
1e5bdc40
KH		 4413 else if (!TARGET_H8300 && count == 28)
4414 {
4415 switch (shift_type)
4416 {
4417 case SHIFT_ASHIFT:
4418 if (TARGET_H8300H)
4419 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4420 else
4421 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
1e5bdc40
KH		 4422 goto end;
4423 case SHIFT_LSHIFTRT:
4424 if (TARGET_H8300H)
45ca2106
KH		 4425 {
4426 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4427 info->cc_special = CC_SET_ZNV;
4428 }
1e5bdc40 4429 else
a7612343 4430 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
1e5bdc40
KH		 4431 goto end;
4432 case SHIFT_ASHIFTRT:
8c440872 4433 gcc_unreachable ();
1e5bdc40
KH		 4434 }
4435 }
4436 else if (!TARGET_H8300 && count == 29)
4437 {
4438 switch (shift_type)
4439 {
4440 case SHIFT_ASHIFT:
4441 if (TARGET_H8300H)
4442 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4443 else
4444 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
1e5bdc40
KH		 4445 goto end;
4446 case SHIFT_LSHIFTRT:
4447 if (TARGET_H8300H)
45ca2106
KH		 4448 {
4449 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4450 info->cc_special = CC_SET_ZNV;
4451 }
1e5bdc40 4452 else
45ca2106
KH		 4453 {
4454 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4455 info->cc_special = CC_SET_ZNV;
4456 }
1e5bdc40
KH		 4457 goto end;
4458 case SHIFT_ASHIFTRT:
8c440872 4459 gcc_unreachable ();
1e5bdc40
KH		 4460 }
4461 }
4462 else if (!TARGET_H8300 && count == 30)
4463 {
4464 switch (shift_type)
4465 {
4466 case SHIFT_ASHIFT:
4467 if (TARGET_H8300H)
4468 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4469 else
4470 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
1e5bdc40
KH		 4471 goto end;
4472 case SHIFT_LSHIFTRT:
4473 if (TARGET_H8300H)
a7612343 4474 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
1e5bdc40 4475 else
a7612343 4476 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
1e5bdc40
KH		 4477 goto end;
4478 case SHIFT_ASHIFTRT:
8c440872 4479 gcc_unreachable ();
1e5bdc40
KH		 4480 }
4481 }
48837e29
DE		 4482 else if (count == 31)
4483 {
dd69e230 4484 if (TARGET_H8300)
48837e29 4485 {
dd69e230
KH		 4486 switch (shift_type)
4487 {
4488 case SHIFT_ASHIFT:
4489 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4490 goto end;
4491 case SHIFT_LSHIFTRT:
4492 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4493 goto end;
4494 case SHIFT_ASHIFTRT:
4495 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4496 goto end;
4497 }
48837e29
DE		 4498 }
4499 else
4500 {
dd69e230 4501 switch (shift_type)
48837e29 4502 {
dd69e230
KH		 4503 case SHIFT_ASHIFT:
4504 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
45ca2106 4505 info->cc_special = CC_SET_ZNV;
dd69e230
KH		 4506 goto end;
4507 case SHIFT_LSHIFTRT:
4508 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
45ca2106 4509 info->cc_special = CC_SET_ZNV;
dd69e230
KH		 4510 goto end;
4511 case SHIFT_ASHIFTRT:
a7612343 4512 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
45ca2106 4513 info->cc_special = CC_SET_ZNV;
692b7eb3 4514 goto end;
48837e29 4515 }
48837e29
DE		 4516 }
4517 }
8c440872 4518 gcc_unreachable ();
51c0c1d7 4519
48837e29 4520 default:
8c440872 4521 gcc_unreachable ();
07aae5c2 4522 }
48837e29 4523
cb33eb17
KH		 4524 end:
4525 if (!TARGET_H8300S)
4526 info->shift2 = NULL;
07aae5c2
SC		 4527}
4528
be1e06df
KH		 4529/* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4530 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4531
4532int
ef4bddc2 4533h8300_shift_needs_scratch_p (int count, machine_mode mode)
be1e06df 4534{
b9b575e6 4535 enum h8_cpu cpu;
be1e06df
KH		 4536 int a, lr, ar;
4537
4538 if (GET_MODE_BITSIZE (mode) <= count)
4539 return 1;
4540
4541 /* Find out the target CPU. */
4542 if (TARGET_H8300)
b9b575e6 4543 cpu = H8_300;
2f6bd6eb 4544 else if (TARGET_H8300S)
b9b575e6 4545 cpu = H8_S;
2f6bd6eb
YS		 4546 else
4547 cpu = H8_300H;
be1e06df
KH		 4548
4549 /* Find the shift algorithm. */
4550 switch (mode)
4551 {
4552 case QImode:
4553 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
4554 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
4555 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
4556 break;
4557
4558 case HImode:
4559 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
4560 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
4561 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
4562 break;
4563
4564 case SImode:
4565 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
4566 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
4567 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
4568 break;
4569
4570 default:
8c440872 4571 gcc_unreachable ();
be1e06df
KH		 4572 }
4573
aa2fb4dd 4574 /* On H8/300H, count == 8 uses a scratch register. */
be1e06df 4575 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
75a3503b 4576 || (TARGET_H8300H && mode == SImode && count == 8));
be1e06df
KH		 4577}
4578
e9eba255 4579/* Output the assembler code for doing shifts. */
48837e29 4580
441d04c6 4581const char *
cb713a8d 4582output_a_shift (rtx *operands)
07aae5c2 4583{
48837e29 4584 static int loopend_lab;
48837e29 4585 rtx shift = operands[3];
ef4bddc2 4586 machine_mode mode = GET_MODE (shift);
48837e29
DE		 4587 enum rtx_code code = GET_CODE (shift);
4588 enum shift_type shift_type;
4589 enum shift_mode shift_mode;
35fb3d1f 4590 struct shift_info info;
8c440872 4591 int n;
48837e29
DE		 4592
4593 loopend_lab++;
4594
4595 switch (mode)
4596 {
4597 case QImode:
4598 shift_mode = QIshift;
4599 break;
4600 case HImode:
4601 shift_mode = HIshift;
4602 break;
4603 case SImode:
4604 shift_mode = SIshift;
4605 break;
4606 default:
8c440872 4607 gcc_unreachable ();
48837e29 4608 }
07aae5c2 4609
48837e29 4610 switch (code)
07aae5c2 4611 {
48837e29
DE		 4612 case ASHIFTRT:
4613 shift_type = SHIFT_ASHIFTRT;
4614 break;
4615 case LSHIFTRT:
4616 shift_type = SHIFT_LSHIFTRT;
4617 break;
4618 case ASHIFT:
4619 shift_type = SHIFT_ASHIFT;
4620 break;
4621 default:
8c440872 4622 gcc_unreachable ();
48837e29 4623 }
07aae5c2 4624
8c440872
NS		 4625 /* This case must be taken care of by one of the two splitters
4626 that convert a variable shift into a loop. */
4627 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4628
4629 n = INTVAL (operands[2]);
4630
4631 /* If the count is negative, make it 0. */
4632 if (n < 0)
4633 n = 0;
4634 /* If the count is too big, truncate it.
4635 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4636 do the intuitive thing. */
4637 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4638 n = GET_MODE_BITSIZE (mode);
4639
4640 get_shift_alg (shift_type, shift_mode, n, &info);
4641
4642 switch (info.alg)
48837e29 4643 {
8c440872
NS		 4644 case SHIFT_SPECIAL:
4645 output_asm_insn (info.special, operands);
4646 /* Fall through. */
48837e29 4647
8c440872
NS		 4648 case SHIFT_INLINE:
4649 n = info.remainder;
48837e29 4650
8c440872
NS		 4651 /* Emit two bit shifts first. */
4652 if (info.shift2 != NULL)
48837e29 4653 {
8c440872
NS		 4654 for (; n > 1; n -= 2)
4655 output_asm_insn (info.shift2, operands);
4656 }
51c0c1d7 4657
8c440872
NS		 4658 /* Now emit one bit shifts for any residual. */
4659 for (; n > 0; n--)
4660 output_asm_insn (info.shift1, operands);
4661 return "";
4662
4663 case SHIFT_ROT_AND:
4664 {
4665 int m = GET_MODE_BITSIZE (mode) - n;
4666 const int mask = (shift_type == SHIFT_ASHIFT
4667 ? ((1 << m) - 1) << n
4668 : (1 << m) - 1);
4669 char insn_buf[200];
4670
4671 /* Not all possibilities of rotate are supported. They shouldn't
4672 be generated, but let's watch for 'em. */
4673 gcc_assert (info.shift1);
4674
4675 /* Emit two bit rotates first. */
4676 if (info.shift2 != NULL)
48837e29 4677 {
8c440872
NS		 4678 for (; m > 1; m -= 2)
4679 output_asm_insn (info.shift2, operands);
4680 }
4681
4682 /* Now single bit rotates for any residual. */
4683 for (; m > 0; m--)
4684 output_asm_insn (info.shift1, operands);
4685
4686 /* Now mask off the high bits. */
4687 switch (mode)
4688 {
4689 case QImode:
4690 sprintf (insn_buf, "and\t#%d,%%X0", mask);
4691 break;
51c0c1d7 4692
8c440872
NS		 4693 case HImode:
4694 gcc_assert (TARGET_H8300H || TARGET_H8300S);
4695 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
4696 break;
51c0c1d7 4697
8c440872
NS		 4698 default:
4699 gcc_unreachable ();
48837e29 4700 }
b5eaf9ba 4701
8c440872
NS		 4702 output_asm_insn (insn_buf, operands);
4703 return "";
4704 }
b5eaf9ba 4705
8c440872
NS		 4706 case SHIFT_LOOP:
4707 /* A loop to shift by a "large" constant value.
4708 If we have shift-by-2 insns, use them. */
4709 if (info.shift2 != NULL)
4710 {
4711 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
4712 names_big[REGNO (operands[4])]);
4713 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4714 output_asm_insn (info.shift2, operands);
4715 output_asm_insn ("add #0xff,%X4", operands);
4716 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4717 if (n % 2)
4718 output_asm_insn (info.shift1, operands);
4719 }
4720 else
4721 {
4722 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
4723 names_big[REGNO (operands[4])]);
4724 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4725 output_asm_insn (info.shift1, operands);
4726 output_asm_insn ("add #0xff,%X4", operands);
4727 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
51c0c1d7 4728 }
8c440872
NS		 4729 return "";
4730
4731 default:
4732 gcc_unreachable ();
07aae5c2 4733 }
07aae5c2 4734}
86855e8c 4735
0a2aaacc 4736/* Count the number of assembly instructions in a string TEMPL. */
e9eba255 4737
86855e8c 4738static unsigned int
0a2aaacc 4739h8300_asm_insn_count (const char *templ)
86855e8c
KH		 4740{
4741 unsigned int count = 1;
4742
0a2aaacc
KG		 4743 for (; *templ; templ++)
4744 if (*templ == '\n')
86855e8c
KH		 4745 count++;
4746
4747 return count;
4748}
4749
e9eba255
KH		 4750/* Compute the length of a shift insn. */
4751
86855e8c 4752unsigned int
cb713a8d 4753compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
86855e8c
KH		 4754{
4755 rtx shift = operands[3];
ef4bddc2 4756 machine_mode mode = GET_MODE (shift);
86855e8c
KH		 4757 enum rtx_code code = GET_CODE (shift);
4758 enum shift_type shift_type;
4759 enum shift_mode shift_mode;
4760 struct shift_info info;
4761 unsigned int wlength = 0;
4762
4763 switch (mode)
4764 {
4765 case QImode:
4766 shift_mode = QIshift;
4767 break;
4768 case HImode:
4769 shift_mode = HIshift;
4770 break;
4771 case SImode:
4772 shift_mode = SIshift;
4773 break;
4774 default:
8c440872 4775 gcc_unreachable ();
86855e8c
KH		 4776 }
4777
4778 switch (code)
4779 {
4780 case ASHIFTRT:
4781 shift_type = SHIFT_ASHIFTRT;
4782 break;
4783 case LSHIFTRT:
4784 shift_type = SHIFT_LSHIFTRT;
4785 break;
4786 case ASHIFT:
4787 shift_type = SHIFT_ASHIFT;
4788 break;
4789 default:
8c440872 4790 gcc_unreachable ();
86855e8c
KH		 4791 }
4792
4793 if (GET_CODE (operands[2]) != CONST_INT)
4794 {
4795 /* Get the assembler code to do one shift. */
4796 get_shift_alg (shift_type, shift_mode, 1, &info);
4797
4798 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
4799 }
4800 else
4801 {
4802 int n = INTVAL (operands[2]);
4803
4804 /* If the count is negative, make it 0. */
4805 if (n < 0)
4806 n = 0;
4807 /* If the count is too big, truncate it.
4808 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4809 do the intuitive thing. */
4810 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4811 n = GET_MODE_BITSIZE (mode);
4812
4813 get_shift_alg (shift_type, shift_mode, n, &info);
4814
4815 switch (info.alg)
4816 {
4817 case SHIFT_SPECIAL:
4818 wlength += h8300_asm_insn_count (info.special);
41c3eb5d
KH		 4819
4820 /* Every assembly instruction used in SHIFT_SPECIAL case
4821 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4822 see xor.l, we just pretend that xor.l counts as two insns
4823 so that the insn length will be computed correctly. */
4824 if (strstr (info.special, "xor.l") != NULL)
4825 wlength++;
4826
86855e8c
KH		 4827 /* Fall through. */
4828
4829 case SHIFT_INLINE:
4830 n = info.remainder;
4831
4832 if (info.shift2 != NULL)
4833 {
4834 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
4835 n = n % 2;
4836 }
4837
4838 wlength += h8300_asm_insn_count (info.shift1) * n;
6b148bd9 4839
86855e8c
KH		 4840 return 2 * wlength;
4841
4842 case SHIFT_ROT_AND:
4843 {
4844 int m = GET_MODE_BITSIZE (mode) - n;
4845
4846 /* Not all possibilities of rotate are supported. They shouldn't
4847 be generated, but let's watch for 'em. */
8c440872 4848 gcc_assert (info.shift1);
86855e8c
KH		 4849
4850 if (info.shift2 != NULL)
4851 {
4852 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
4853 m = m % 2;
4854 }
4855
4856 wlength += h8300_asm_insn_count (info.shift1) * m;
6b148bd9 4857
86855e8c
KH		 4858 /* Now mask off the high bits. */
4859 switch (mode)
4860 {
4861 case QImode:
4862 wlength += 1;
4863 break;
4864 case HImode:
4865 wlength += 2;
4866 break;
4867 case SImode:
8c440872 4868 gcc_assert (!TARGET_H8300);
86855e8c
KH		 4869 wlength += 3;
4870 break;
4871 default:
8c440872 4872 gcc_unreachable ();
86855e8c
KH		 4873 }
4874 return 2 * wlength;
4875 }
4876
4877 case SHIFT_LOOP:
4878 /* A loop to shift by a "large" constant value.
4879 If we have shift-by-2 insns, use them. */
4880 if (info.shift2 != NULL)
4881 {
4882 wlength += 3 + h8300_asm_insn_count (info.shift2);
4883 if (n % 2)
4884 wlength += h8300_asm_insn_count (info.shift1);
4885 }
4886 else
4887 {
4888 wlength += 3 + h8300_asm_insn_count (info.shift1);
4889 }
4890 return 2 * wlength;
4891
4892 default:
8c440872 4893 gcc_unreachable ();
86855e8c
KH		 4894 }
4895 }
4896}
45ca2106 4897
e9eba255
KH		 4898/* Compute which flag bits are valid after a shift insn. */
4899
9690aa8e 4900enum attr_cc
cb713a8d 4901compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
45ca2106
KH		 4902{
4903 rtx shift = operands[3];
ef4bddc2 4904 machine_mode mode = GET_MODE (shift);
45ca2106
KH		 4905 enum rtx_code code = GET_CODE (shift);
4906 enum shift_type shift_type;
4907 enum shift_mode shift_mode;
4908 struct shift_info info;
8c440872
NS		 4909 int n;
4910
45ca2106
KH		 4911 switch (mode)
4912 {
4913 case QImode:
4914 shift_mode = QIshift;
4915 break;
4916 case HImode:
4917 shift_mode = HIshift;
4918 break;
4919 case SImode:
4920 shift_mode = SIshift;
4921 break;
4922 default:
8c440872 4923 gcc_unreachable ();
45ca2106
KH		 4924 }
4925
4926 switch (code)
4927 {
4928 case ASHIFTRT:
4929 shift_type = SHIFT_ASHIFTRT;
4930 break;
4931 case LSHIFTRT:
4932 shift_type = SHIFT_LSHIFTRT;
4933 break;
4934 case ASHIFT:
4935 shift_type = SHIFT_ASHIFT;
4936 break;
4937 default:
8c440872 4938 gcc_unreachable ();
45ca2106
KH		 4939 }
4940
8c440872
NS		 4941 /* This case must be taken care of by one of the two splitters
4942 that convert a variable shift into a loop. */
4943 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4944
4945 n = INTVAL (operands[2]);
4946
4947 /* If the count is negative, make it 0. */
4948 if (n < 0)
4949 n = 0;
4950 /* If the count is too big, truncate it.
4951 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4952 do the intuitive thing. */
4953 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4954 n = GET_MODE_BITSIZE (mode);
4955
4956 get_shift_alg (shift_type, shift_mode, n, &info);
4957
4958 switch (info.alg)
45ca2106 4959 {
8c440872
NS		 4960 case SHIFT_SPECIAL:
4961 if (info.remainder == 0)
4962 return info.cc_special;
45ca2106 4963
8c440872 4964 /* Fall through. */
45ca2106 4965
8c440872
NS		 4966 case SHIFT_INLINE:
4967 return info.cc_inline;
4968
4969 case SHIFT_ROT_AND:
4970 /* This case always ends with an and instruction. */
4971 return CC_SET_ZNV;
4972
4973 case SHIFT_LOOP:
4974 /* A loop to shift by a "large" constant value.
4975 If we have shift-by-2 insns, use them. */
4976 if (info.shift2 != NULL)
45ca2106 4977 {
8c440872
NS		 4978 if (n % 2)
4979 return info.cc_inline;
45ca2106 4980 }
8c440872
NS		 4981 return CC_CLOBBER;
4982
4983 default:
4984 gcc_unreachable ();
45ca2106
KH		 4985 }
4986}
48837e29 4987\f
edd71f0f
KH		 4988/* A rotation by a non-constant will cause a loop to be generated, in
4989 which a rotation by one bit is used. A rotation by a constant,
4990 including the one in the loop, will be taken care of by
caf7f21a 4991 output_a_rotate () at the insn emit time. */
edd71f0f
KH		 4992
4993int
3d2e90d6 4994expand_a_rotate (rtx operands[])
edd71f0f
KH		 4995{
4996 rtx dst = operands[0];
4997 rtx src = operands[1];
4998 rtx rotate_amount = operands[2];
ef4bddc2 4999 machine_mode mode = GET_MODE (dst);
edd71f0f 5000
beed8fc0
AO		 5001 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
5002 return false;
5003
edd71f0f
KH		 5004 /* We rotate in place. */
5005 emit_move_insn (dst, src);
5006
5007 if (GET_CODE (rotate_amount) != CONST_INT)
5008 {
5009 rtx counter = gen_reg_rtx (QImode);
19f8b229
TS		 5010 rtx_code_label *start_label = gen_label_rtx ();
5011 rtx_code_label *end_label = gen_label_rtx ();
edd71f0f
KH		 5012
5013 /* If the rotate amount is less than or equal to 0,
5014 we go out of the loop. */
a556fd39 5015 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
d43e0b7d 5016 QImode, 0, end_label);
edd71f0f
KH		 5017
5018 /* Initialize the loop counter. */
5019 emit_move_insn (counter, rotate_amount);
5020
5021 emit_label (start_label);
5022
5023 /* Rotate by one bit. */
01ab5574
KH		 5024 switch (mode)
5025 {
5026 case QImode:
5027 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
5028 break;
5029 case HImode:
5030 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
5031 break;
5032 case SImode:
5033 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
5034 break;
5035 default:
8c440872 5036 gcc_unreachable ();
01ab5574 5037 }
edd71f0f
KH		 5038
5039 /* Decrement the counter by 1. */
01ab5574 5040 emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
edd71f0f 5041
9cd10576 5042 /* If the loop counter is nonzero, we go back to the beginning
edd71f0f 5043 of the loop. */
a556fd39 5044 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
d43e0b7d 5045 start_label);
edd71f0f
KH		 5046
5047 emit_label (end_label);
5048 }
5049 else
5050 {
5051 /* Rotate by AMOUNT bits. */
01ab5574
KH		 5052 switch (mode)
5053 {
5054 case QImode:
5055 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
5056 break;
5057 case HImode:
5058 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
5059 break;
5060 case SImode:
5061 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
5062 break;
5063 default:
8c440872 5064 gcc_unreachable ();
01ab5574 5065 }
edd71f0f
KH		 5066 }
5067
5068 return 1;
5069}
5070
e9eba255 5071/* Output a rotate insn. */
edd71f0f
KH		 5072
5073const char *
caf7f21a 5074output_a_rotate (enum rtx_code code, rtx *operands)
edd71f0f
KH		 5075{
5076 rtx dst = operands[0];
5077 rtx rotate_amount = operands[2];
5078 enum shift_mode rotate_mode;
5079 enum shift_type rotate_type;
5080 const char *insn_buf;
5081 int bits;
5082 int amount;
ef4bddc2 5083 machine_mode mode = GET_MODE (dst);
edd71f0f 5084
8c440872 5085 gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
edd71f0f
KH		 5086
5087 switch (mode)
5088 {
5089 case QImode:
5090 rotate_mode = QIshift;
5091 break;
5092 case HImode:
5093 rotate_mode = HIshift;
5094 break;
5095 case SImode:
5096 rotate_mode = SIshift;
5097 break;
5098 default:
8c440872 5099 gcc_unreachable ();
edd71f0f
KH		 5100 }
5101
5102 switch (code)
5103 {
5104 case ROTATERT:
5105 rotate_type = SHIFT_ASHIFT;
5106 break;
5107 case ROTATE:
5108 rotate_type = SHIFT_LSHIFTRT;
5109 break;
5110 default:
8c440872 5111 gcc_unreachable ();
edd71f0f
KH		 5112 }
5113
5114 amount = INTVAL (rotate_amount);
5115
5116 /* Clean up AMOUNT. */
5117 if (amount < 0)
5118 amount = 0;
5119 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5120 amount = GET_MODE_BITSIZE (mode);
5121
5122 /* Determine the faster direction. After this phase, amount will be
5123 at most a half of GET_MODE_BITSIZE (mode). */
e0c32c62 5124 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
edd71f0f
KH		 5125 {
5126 /* Flip the direction. */
5127 amount = GET_MODE_BITSIZE (mode) - amount;
5128 rotate_type =
5129 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5130 }
5131
5132 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5133 boost up the rotation. */
5134 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5135 || (mode == HImode && TARGET_H8300H && amount >= 6)
5136 || (mode == HImode && TARGET_H8300S && amount == 8)
5137 || (mode == SImode && TARGET_H8300H && amount >= 10)
5138 || (mode == SImode && TARGET_H8300S && amount >= 13))
5139 {
5140 switch (mode)
5141 {
5142 case HImode:
5143 /* This code works on any family. */
5144 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5145 output_asm_insn (insn_buf, operands);
5146 break;
5147
5148 case SImode:
3db11b5c 5149 /* This code works on the H8/300H and H8S. */
edd71f0f
KH		 5150 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5151 output_asm_insn (insn_buf, operands);
5152 break;
5153
5154 default:
8c440872 5155 gcc_unreachable ();
edd71f0f
KH		 5156 }
5157
5158 /* Adjust AMOUNT and flip the direction. */
5159 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5160 rotate_type =
5161 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5162 }
5163
01ab5574 5164 /* Output rotate insns. */
edd71f0f
KH		 5165 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
5166 {
5167 if (bits == 2)
5168 insn_buf = rotate_two[rotate_type][rotate_mode];
5169 else
5170 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
2c54abce 5171
edd71f0f
KH		 5172 for (; amount >= bits; amount -= bits)
5173 output_asm_insn (insn_buf, operands);
5174 }
5175
5176 return "";
5177}
caf7f21a 5178
e9eba255
KH		 5179/* Compute the length of a rotate insn. */
5180
caf7f21a
KH		 5181unsigned int
5182compute_a_rotate_length (rtx *operands)
5183{
5184 rtx src = operands[1];
343fd2c7 5185 rtx amount_rtx = operands[2];
ef4bddc2 5186 machine_mode mode = GET_MODE (src);
caf7f21a
KH		 5187 int amount;
5188 unsigned int length = 0;
5189
8c440872 5190 gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
caf7f21a 5191
343fd2c7 5192 amount = INTVAL (amount_rtx);
caf7f21a
KH		 5193
5194 /* Clean up AMOUNT. */
5195 if (amount < 0)
5196 amount = 0;
5197 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5198 amount = GET_MODE_BITSIZE (mode);
5199
5200 /* Determine the faster direction. After this phase, amount
5201 will be at most a half of GET_MODE_BITSIZE (mode). */
5202 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5203 /* Flip the direction. */
5204 amount = GET_MODE_BITSIZE (mode) - amount;
5205
5206 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5207 boost up the rotation. */
5208 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5209 || (mode == HImode && TARGET_H8300H && amount >= 6)
5210 || (mode == HImode && TARGET_H8300S && amount == 8)
5211 || (mode == SImode && TARGET_H8300H && amount >= 10)
5212 || (mode == SImode && TARGET_H8300S && amount >= 13))
5213 {
5214 /* Adjust AMOUNT and flip the direction. */
5215 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5216 length += 6;
5217 }
5218
5219 /* We use 2-bit rotations on the H8S. */
5220 if (TARGET_H8300S)
5221 amount = amount / 2 + amount % 2;
5222
5223 /* The H8/300 uses three insns to rotate one bit, taking 6
5224 length. */
5225 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
5226
5227 return length;
5228}
edd71f0f 5229\f
48837e29 5230/* Fix the operands of a gen_xxx so that it could become a bit
2c54abce 5231 operating insn. */
07aae5c2
SC		 5232
5233int
4093985c 5234fix_bit_operand (rtx *operands, enum rtx_code code)
07aae5c2 5235{
abc95ed3 5236 /* The bit_operand predicate accepts any memory during RTL generation, but
48837e29
DE		 5237 only 'U' memory afterwards, so if this is a MEM operand, we must force
5238 it to be valid for 'U' by reloading the address. */
07aae5c2 5239
4093985c
KH		 5240 if (code == AND
5241 ? single_zero_operand (operands[2], QImode)
5242 : single_one_operand (operands[2], QImode))
07aae5c2 5243 {
2e760b15
KH		 5244 /* OK to have a memory dest. */
5245 if (GET_CODE (operands[0]) == MEM
ceaaaeab 5246 && !satisfies_constraint_U (operands[0]))
48837e29 5247 {
2e760b15
KH		 5248 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
5249 copy_to_mode_reg (Pmode,
5250 XEXP (operands[0], 0)));
5251 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5252 operands[0] = mem;
5253 }
48837e29 5254
2e760b15 5255 if (GET_CODE (operands[1]) == MEM
ceaaaeab 5256 && !satisfies_constraint_U (operands[1]))
2e760b15
KH		 5257 {
5258 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
5259 copy_to_mode_reg (Pmode,
5260 XEXP (operands[1], 0)));
5261 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5262 operands[1] = mem;
48837e29 5263 }
2e760b15 5264 return 0;
48837e29 5265 }
07aae5c2 5266
48837e29 5267 /* Dest and src op must be register. */
07aae5c2 5268
48837e29
DE		 5269 operands[1] = force_reg (QImode, operands[1]);
5270 {
5271 rtx res = gen_reg_rtx (QImode);
fd57a6e4 5272 switch (code)
a3579575
KH		 5273 {
5274 case AND:
5275 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
5276 break;
5277 case IOR:
5278 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
5279 break;
5280 case XOR:
5281 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
5282 break;
5283 default:
8c440872 5284 gcc_unreachable ();
a3579575
KH		 5285 }
5286 emit_insn (gen_movqi (operands[0], res));
48837e29
DE		 5287 }
5288 return 1;
07aae5c2 5289}
f5b65a56 5290
f5b65a56
JL		 5291/* Return nonzero if FUNC is an interrupt function as specified
5292 by the "interrupt" attribute. */
5293
5294static int
cb713a8d 5295h8300_interrupt_function_p (tree func)
f5b65a56
JL		 5296{
5297 tree a;
5298
5299 if (TREE_CODE (func) != FUNCTION_DECL)
5300 return 0;
5301
91d231cb 5302 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
f5b65a56
JL		 5303 return a != NULL_TREE;
5304}
5305
3cfa3702
KH		 5306/* Return nonzero if FUNC is a saveall function as specified by the
5307 "saveall" attribute. */
5308
5309static int
5310h8300_saveall_function_p (tree func)
5311{
5312 tree a;
5313
5314 if (TREE_CODE (func) != FUNCTION_DECL)
5315 return 0;
5316
5317 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
5318 return a != NULL_TREE;
5319}
5320
fabe72bb
JL		 5321/* Return nonzero if FUNC is an OS_Task function as specified
5322 by the "OS_Task" attribute. */
5323
5324static int
cb713a8d 5325h8300_os_task_function_p (tree func)
fabe72bb
JL		 5326{
5327 tree a;
5328
5329 if (TREE_CODE (func) != FUNCTION_DECL)
5330 return 0;
5331
91d231cb 5332 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
fabe72bb
JL		 5333 return a != NULL_TREE;
5334}
5335
5336/* Return nonzero if FUNC is a monitor function as specified
5337 by the "monitor" attribute. */
5338
5339static int
cb713a8d 5340h8300_monitor_function_p (tree func)
fabe72bb
JL		 5341{
5342 tree a;
5343
5344 if (TREE_CODE (func) != FUNCTION_DECL)
5345 return 0;
5346
91d231cb 5347 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
fabe72bb
JL		 5348 return a != NULL_TREE;
5349}
5350
f5b65a56
JL		 5351/* Return nonzero if FUNC is a function that should be called
5352 through the function vector. */
5353
5354int
cb713a8d 5355h8300_funcvec_function_p (tree func)
f5b65a56
JL		 5356{
5357 tree a;
5358
5359 if (TREE_CODE (func) != FUNCTION_DECL)
5360 return 0;
5361
91d231cb 5362 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
f5b65a56
JL		 5363 return a != NULL_TREE;
5364}
5365
887a8bd9 5366/* Return nonzero if DECL is a variable that's in the eight bit
15dc331e
JL		 5367 data area. */
5368
5369int
cb713a8d 5370h8300_eightbit_data_p (tree decl)
15dc331e
JL		 5371{
5372 tree a;
5373
5374 if (TREE_CODE (decl) != VAR_DECL)
5375 return 0;
5376
91d231cb 5377 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
15dc331e
JL		 5378 return a != NULL_TREE;
5379}
5380
887a8bd9
JL		 5381/* Return nonzero if DECL is a variable that's in the tiny
5382 data area. */
5383
5384int
cb713a8d 5385h8300_tiny_data_p (tree decl)
887a8bd9
JL		 5386{
5387 tree a;
5388
5389 if (TREE_CODE (decl) != VAR_DECL)
5390 return 0;
5391
91d231cb 5392 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
887a8bd9
JL		 5393 return a != NULL_TREE;
5394}
5395
3cfa3702
KH		 5396/* Generate an 'interrupt_handler' attribute for decls. We convert
5397 all the pragmas to corresponding attributes. */
2c1d2fcb
DD		 5398
5399static void
cb713a8d 5400h8300_insert_attributes (tree node, tree *attributes)
2c1d2fcb 5401{
3cfa3702
KH		 5402 if (TREE_CODE (node) == FUNCTION_DECL)
5403 {
5404 if (pragma_interrupt)
5405 {
5406 pragma_interrupt = 0;
2c1d2fcb 5407
3cfa3702
KH		 5408 /* Add an 'interrupt_handler' attribute. */
5409 *attributes = tree_cons (get_identifier ("interrupt_handler"),
5410 NULL, *attributes);
5411 }
e392d367 5412
3cfa3702
KH		 5413 if (pragma_saveall)
5414 {
5415 pragma_saveall = 0;
5416
5417 /* Add an 'saveall' attribute. */
5418 *attributes = tree_cons (get_identifier ("saveall"),
5419 NULL, *attributes);
5420 }
5421 }
2c1d2fcb
DD		 5422}
5423
91d231cb 5424/* Supported attributes:
f5b65a56 5425
97c5ec1d 5426 interrupt_handler: output a prologue and epilogue suitable for an
f5b65a56
JL		 5427 interrupt handler.
5428
3cfa3702
KH		 5429 saveall: output a prologue and epilogue that saves and restores
5430 all registers except the stack pointer.
5431
97c5ec1d 5432 function_vector: This function should be called through the
887a8bd9
JL		 5433 function vector.
5434
5435 eightbit_data: This variable lives in the 8-bit data area and can
5436 be referenced with 8-bit absolute memory addresses.
5437
5438 tiny_data: This variable lives in the tiny data area and can be
5439 referenced with 16-bit absolute memory references. */
f5b65a56 5440
6bc7bc14 5441static const struct attribute_spec h8300_attribute_table[] =
f5b65a56 5442{
62d784f7
KT		 5443 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
5444 affects_type_identity } */
5445 { "interrupt_handler", 0, 0, true, false, false,
5446 h8300_handle_fndecl_attribute, false },
5447 { "saveall", 0, 0, true, false, false,
5448 h8300_handle_fndecl_attribute, false },
5449 { "OS_Task", 0, 0, true, false, false,
5450 h8300_handle_fndecl_attribute, false },
5451 { "monitor", 0, 0, true, false, false,
5452 h8300_handle_fndecl_attribute, false },
5453 { "function_vector", 0, 0, true, false, false,
5454 h8300_handle_fndecl_attribute, false },
5455 { "eightbit_data", 0, 0, true, false, false,
5456 h8300_handle_eightbit_data_attribute, false },
5457 { "tiny_data", 0, 0, true, false, false,
5458 h8300_handle_tiny_data_attribute, false },
5459 { NULL, 0, 0, false, false, false, NULL, false }
91d231cb 5460};
f5b65a56 5461
15dc331e 5462
91d231cb
JM		 5463/* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5464 struct attribute_spec.handler. */
5465static tree
cb713a8d
KH		 5466h8300_handle_fndecl_attribute (tree *node, tree name,
5467 tree args ATTRIBUTE_UNUSED,
5468 int flags ATTRIBUTE_UNUSED,
5469 bool *no_add_attrs)
91d231cb
JM		 5470{
5471 if (TREE_CODE (*node) != FUNCTION_DECL)
5472 {
29d08eba
JM		 5473 warning (OPT_Wattributes, "%qE attribute only applies to functions",
5474 name);
91d231cb
JM		 5475 *no_add_attrs = true;
5476 }
5477
5478 return NULL_TREE;
5479}
5480
5481/* Handle an "eightbit_data" attribute; arguments as in
5482 struct attribute_spec.handler. */
5483static tree
cb713a8d
KH		 5484h8300_handle_eightbit_data_attribute (tree *node, tree name,
5485 tree args ATTRIBUTE_UNUSED,
5486 int flags ATTRIBUTE_UNUSED,
5487 bool *no_add_attrs)
91d231cb
JM		 5488{
5489 tree decl = *node;
5490
5491 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
15dc331e 5492 {
f961457f 5493 set_decl_section_name (decl, ".eight");
91d231cb
JM		 5494 }
5495 else
5496 {
29d08eba
JM		 5497 warning (OPT_Wattributes, "%qE attribute ignored",
5498 name);
91d231cb 5499 *no_add_attrs = true;
887a8bd9
JL		 5500 }
5501
91d231cb
JM		 5502 return NULL_TREE;
5503}
5504
5505/* Handle an "tiny_data" attribute; arguments as in
5506 struct attribute_spec.handler. */
5507static tree
cb713a8d
KH		 5508h8300_handle_tiny_data_attribute (tree *node, tree name,
5509 tree args ATTRIBUTE_UNUSED,
5510 int flags ATTRIBUTE_UNUSED,
5511 bool *no_add_attrs)
91d231cb
JM		 5512{
5513 tree decl = *node;
5514
5515 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
887a8bd9 5516 {
f961457f 5517 set_decl_section_name (decl, ".tiny");
91d231cb
JM		 5518 }
5519 else
5520 {
29d08eba
JM		 5521 warning (OPT_Wattributes, "%qE attribute ignored",
5522 name);
91d231cb 5523 *no_add_attrs = true;
15dc331e 5524 }
07e4d94e 5525
91d231cb 5526 return NULL_TREE;
f5b65a56
JL		 5527}
5528
dc66a1c4 5529/* Mark function vectors, and various small data objects. */
fb49053f
RH		 5530
5531static void
cb713a8d 5532h8300_encode_section_info (tree decl, rtx rtl, int first)
fb49053f 5533{
dc66a1c4
RH		 5534 int extra_flags = 0;
5535
c6a2438a 5536 default_encode_section_info (decl, rtl, first);
dc66a1c4 5537
fb49053f
RH		 5538 if (TREE_CODE (decl) == FUNCTION_DECL
5539 && h8300_funcvec_function_p (decl))
dc66a1c4 5540 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
fb49053f
RH		 5541 else if (TREE_CODE (decl) == VAR_DECL
5542 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
5543 {
5544 if (h8300_eightbit_data_p (decl))
dc66a1c4 5545 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
fb49053f 5546 else if (first && h8300_tiny_data_p (decl))
dc66a1c4 5547 extra_flags = SYMBOL_FLAG_TINY_DATA;
fb49053f 5548 }
772c5265 5549
dc66a1c4 5550 if (extra_flags)
c6a2438a 5551 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
772c5265
RH		 5552}
5553
e9eba255
KH		 5554/* Output a single-bit extraction. */
5555
441d04c6 5556const char *
cb713a8d 5557output_simode_bld (int bild, rtx operands[])
bd93f126 5558{
6be580c7
KH		 5559 if (TARGET_H8300)
5560 {
5561 /* Clear the destination register. */
5562 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
5563
5564 /* Now output the bit load or bit inverse load, and store it in
5565 the destination. */
5566 if (bild)
5567 output_asm_insn ("bild\t%Z2,%Y1", operands);
5568 else
5569 output_asm_insn ("bld\t%Z2,%Y1", operands);
bd93f126 5570
6be580c7
KH		 5571 output_asm_insn ("bst\t#0,%w0", operands);
5572 }
bd93f126 5573 else
6be580c7 5574 {
0eb933a0
KH		 5575 /* Determine if we can clear the destination first. */
5576 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
5577 && REGNO (operands[0]) != REGNO (operands[1]));
5578
5579 if (clear_first)
5580 output_asm_insn ("sub.l\t%S0,%S0", operands);
5581
6be580c7
KH		 5582 /* Output the bit load or bit inverse load. */
5583 if (bild)
5584 output_asm_insn ("bild\t%Z2,%Y1", operands);
5585 else
5586 output_asm_insn ("bld\t%Z2,%Y1", operands);
5587
0eb933a0
KH		 5588 if (!clear_first)
5589 output_asm_insn ("xor.l\t%S0,%S0", operands);
5590
5591 /* Perform the bit store. */
802a9907 5592 output_asm_insn ("rotxl.l\t%S0", operands);
6be580c7 5593 }
bd93f126
JL		 5594
5595 /* All done. */
5596 return "";
5597}
e6219736 5598
beed8fc0
AO		 5599/* Delayed-branch scheduling is more effective if we have some idea
5600 how long each instruction will be. Use a shorten_branches pass
5601 to get an initial estimate. */
5602
5603static void
5604h8300_reorg (void)
5605{
5606 if (flag_delayed_branch)
5607 shorten_branches (get_insns ());
5608}
5609
ede75ee8 5610#ifndef OBJECT_FORMAT_ELF
7c262518 5611static void
c18a5b6c
MM		 5612h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED,
5613 tree decl)
7c262518
RH		 5614{
5615 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5616 fprintf (asm_out_file, "\t.section %s\n", name);
5617}
ede75ee8 5618#endif /* ! OBJECT_FORMAT_ELF */
803d56f5 5619
7c143ed2
KH		 5620/* Nonzero if X is a constant address suitable as an 8-bit absolute,
5621 which is a special case of the 'R' operand. */
5622
803d56f5 5623int
cb713a8d 5624h8300_eightbit_constant_address_p (rtx x)
803d56f5 5625{
ff482c8d 5626 /* The ranges of the 8-bit area. */
d2d199a3
KH		 5627 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
5628 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
803d56f5
KH		 5629 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
5630 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
5631 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
5632 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
5633
5634 unsigned HOST_WIDE_INT addr;
5635
9675a91e 5636 /* We accept symbols declared with eightbit_data. */
dc66a1c4
RH		 5637 if (GET_CODE (x) == SYMBOL_REF)
5638 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
9675a91e 5639
9f9ab303
JL		 5640 if (GET_CODE (x) == CONST
5641 && GET_CODE (XEXP (x, 0)) == PLUS
5642 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
5643 && (SYMBOL_REF_FLAGS (XEXP (XEXP (x, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0)
5644 return 1;
5645
803d56f5
KH		 5646 if (GET_CODE (x) != CONST_INT)
5647 return 0;
5648
5649 addr = INTVAL (x);
5650
5651 return (0
39ba95b5 5652 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
803d56f5
KH		 5653 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
5654 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
5655}
5656
7c143ed2
KH		 5657/* Nonzero if X is a constant address suitable as an 16-bit absolute
5658 on H8/300H and H8S. */
5659
803d56f5 5660int
cb713a8d 5661h8300_tiny_constant_address_p (rtx x)
803d56f5 5662{
3f7211f1 5663 /* The ranges of the 16-bit area. */
803d56f5
KH		 5664 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
5665 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
5666 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
5667 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
5668 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
5669 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
5670 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
5671 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
5672
5673 unsigned HOST_WIDE_INT addr;
5674
d6456562
KH		 5675 switch (GET_CODE (x))
5676 {
5677 case SYMBOL_REF:
a4bb41cc
KH		 5678 /* In the normal mode, any symbol fits in the 16-bit absolute
5679 address range. We also accept symbols declared with
5680 tiny_data. */
5681 return (TARGET_NORMAL_MODE
5682 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
56b8e164 5683
d6456562
KH		 5684 case CONST_INT:
5685 addr = INTVAL (x);
5686 return (TARGET_NORMAL_MODE
5687 || (TARGET_H8300H
5688 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
5689 || (TARGET_H8300S
5690 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
803d56f5 5691
a4bb41cc
KH		 5692 case CONST:
5693 return TARGET_NORMAL_MODE;
5694
d6456562
KH		 5695 default:
5696 return 0;
5697 }
803d56f5 5698
803d56f5 5699}
9b98dc74 5700
e9eba255
KH		 5701/* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5702 locations that can be accessed as a 16-bit word. */
5703
9b98dc74 5704int
cb713a8d 5705byte_accesses_mergeable_p (rtx addr1, rtx addr2)
9b98dc74
KH		 5706{
5707 HOST_WIDE_INT offset1, offset2;
5708 rtx reg1, reg2;
5709
5710 if (REG_P (addr1))
5711 {
5712 reg1 = addr1;
5713 offset1 = 0;
5714 }
5715 else if (GET_CODE (addr1) == PLUS
5716 && REG_P (XEXP (addr1, 0))
5717 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
5718 {
5719 reg1 = XEXP (addr1, 0);
5720 offset1 = INTVAL (XEXP (addr1, 1));
5721 }
5722 else
5723 return 0;
5724
5725 if (REG_P (addr2))
5726 {
5727 reg2 = addr2;
5728 offset2 = 0;
5729 }
5730 else if (GET_CODE (addr2) == PLUS
5731 && REG_P (XEXP (addr2, 0))
5732 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
5733 {
5734 reg2 = XEXP (addr2, 0);
5735 offset2 = INTVAL (XEXP (addr2, 1));
5736 }
5737 else
5738 return 0;
5739
5740 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
5741 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
5742 && offset1 % 2 == 0
5743 && offset1 + 1 == offset2)
5744 return 1;
5745
5746 return 0;
5747}
02529902
KH		 5748
5749/* Return nonzero if we have the same comparison insn as I3 two insns
19cff4db 5750 before I3. I3 is assumed to be a comparison insn. */
02529902
KH		 5751
5752int
5753same_cmp_preceding_p (rtx i3)
5754{
68a1a6c0 5755 rtx_insn *i1, *i2;
02529902
KH		 5756
5757 /* Make sure we have a sequence of three insns. */
5758 i2 = prev_nonnote_insn (i3);
68a1a6c0 5759 if (i2 == NULL)
02529902
KH		 5760 return 0;
5761 i1 = prev_nonnote_insn (i2);
68a1a6c0 5762 if (i1 == NULL)
02529902
KH		 5763 return 0;
5764
5765 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5766 && any_condjump_p (i2) && onlyjump_p (i2));
5767}
c87ec0ba 5768
c06d5c85
KH		 5769/* Return nonzero if we have the same comparison insn as I1 two insns
5770 after I1. I1 is assumed to be a comparison insn. */
5771
5772int
5773same_cmp_following_p (rtx i1)
5774{
68a1a6c0 5775 rtx_insn *i2, *i3;
c06d5c85
KH		 5776
5777 /* Make sure we have a sequence of three insns. */
5778 i2 = next_nonnote_insn (i1);
68a1a6c0 5779 if (i2 == NULL)
c06d5c85
KH		 5780 return 0;
5781 i3 = next_nonnote_insn (i2);
68a1a6c0 5782 if (i3 == NULL)
c06d5c85
KH		 5783 return 0;
5784
5785 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5786 && any_condjump_p (i2) && onlyjump_p (i2));
5787}
5788
a466bea3 5789/* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
1ae58c30 5790 (or pops) N registers. OPERANDS are assumed to be an array of
a466bea3
KH		 5791 registers. */
5792
5793int
5794h8300_regs_ok_for_stm (int n, rtx operands[])
5795{
5796 switch (n)
5797 {
5798 case 2:
5799 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
5800 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
5801 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
5802 case 3:
5803 return ((REGNO (operands[0]) == 0
5804 && REGNO (operands[1]) == 1
5805 && REGNO (operands[2]) == 2)
5806 || (REGNO (operands[0]) == 4
5807 && REGNO (operands[1]) == 5
5808 && REGNO (operands[2]) == 6));
5809
5810 case 4:
5811 return (REGNO (operands[0]) == 0
5812 && REGNO (operands[1]) == 1
5813 && REGNO (operands[2]) == 2
5814 && REGNO (operands[3]) == 3);
8c440872
NS		 5815 default:
5816 gcc_unreachable ();
a466bea3 5817 }
a466bea3
KH		 5818}
5819
c87ec0ba
NY		 5820/* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5821
5822int
5823h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5824 unsigned int new_reg)
5825{
5826 /* Interrupt functions can only use registers that have already been
5827 saved by the prologue, even if they would normally be
5828 call-clobbered. */
5829
5830 if (h8300_current_function_interrupt_function_p ()
6fb5fa3c 5831 && !df_regs_ever_live_p (new_reg))
c87ec0ba
NY		 5832 return 0;
5833
80e58519 5834 return 1;
c87ec0ba 5835}
d0022200 5836
2e762884
DD		 5837/* Returns true if register REGNO is safe to be allocated as a scratch
5838 register in the current function. */
5839
5840static bool
5841h8300_hard_regno_scratch_ok (unsigned int regno)
5842{
5843 if (h8300_current_function_interrupt_function_p ()
5844 && ! WORD_REG_USED (regno))
5845 return false;
5846
5847 return true;
5848}
5849
5850
d0022200
KH		 5851/* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5852
5853static int
5854h8300_rtx_ok_for_base_p (rtx x, int strict)
5855{
5856 /* Strip off SUBREG if any. */
5857 if (GET_CODE (x) == SUBREG)
5858 x = SUBREG_REG (x);
5859
5860 return (REG_P (x)
5861 && (strict
5862 ? REG_OK_FOR_BASE_STRICT_P (x)
5863 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
5864}
5865
5866/* Return nozero if X is a legitimate address. On the H8/300, a
5867 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5868 CONSTANT_ADDRESS. */
5869
c6c3dba9 5870static bool
ef4bddc2 5871h8300_legitimate_address_p (machine_mode mode, rtx x, bool strict)
d0022200
KH		 5872{
5873 /* The register indirect addresses like @er0 is always valid. */
5874 if (h8300_rtx_ok_for_base_p (x, strict))
5875 return 1;
5876
5877 if (CONSTANT_ADDRESS_P (x))
5878 return 1;
5879
beed8fc0
AO		 5880 if (TARGET_H8300SX
5881 && ( GET_CODE (x) == PRE_INC
5882 || GET_CODE (x) == PRE_DEC
5883 || GET_CODE (x) == POST_INC
5884 || GET_CODE (x) == POST_DEC)
5885 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
5886 return 1;
5887
d0022200
KH		 5888 if (GET_CODE (x) == PLUS
5889 && CONSTANT_ADDRESS_P (XEXP (x, 1))
beed8fc0
AO		 5890 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
5891 mode, 0), strict))
d0022200
KH		 5892 return 1;
5893
5894 return 0;
5895}
07ee3b58
KH		 5896
5897/* Worker function for HARD_REGNO_NREGS.
5898
5899 We pretend the MAC register is 32bits -- we don't have any data
5900 types on the H8 series to handle more than 32bits. */
5901
5902int
ef4bddc2 5903h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, machine_mode mode)
07ee3b58
KH		 5904{
5905 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5906}
5907
5908/* Worker function for HARD_REGNO_MODE_OK. */
5909
5910int
ef4bddc2 5911h8300_hard_regno_mode_ok (int regno, machine_mode mode)
07ee3b58
KH		 5912{
5913 if (TARGET_H8300)
5914 /* If an even reg, then anything goes. Otherwise the mode must be
5915 QI or HI. */
5916 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
5917 else
5918 /* MAC register can only be of SImode. Otherwise, anything
5919 goes. */
5920 return regno == MAC_REG ? mode == SImode : 1;
5921}
f9b4f8c1
RH		 5922
5923/* Helper function for the move patterns. Make sure a move is legitimate. */
5924
5925bool
5926h8300_move_ok (rtx dest, rtx src)
5927{
5928 rtx addr, other;
5929
5930 /* Validate that at least one operand is a register. */
5931 if (MEM_P (dest))
5932 {
5933 if (MEM_P (src) || CONSTANT_P (src))
5934 return false;
5935 addr = XEXP (dest, 0);
5936 other = src;
5937 }
5938 else if (MEM_P (src))
5939 {
5940 addr = XEXP (src, 0);
5941 other = dest;
5942 }
5943 else
5944 return true;
5945
5946 /* Validate that auto-inc doesn't affect OTHER. */
5947 if (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC)
5948 return true;
5949 addr = XEXP (addr, 0);
5950
5951 if (addr == stack_pointer_rtx)
5952 return register_no_sp_elim_operand (other, VOIDmode);
5953 else
5954 return !reg_overlap_mentioned_p(other, addr);
5955}
6e014ef3 5956\f
c15c90bb
ZW		 5957/* Perform target dependent optabs initialization. */
5958static void
5959h8300_init_libfuncs (void)
5960{
5961 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
5962 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
5963 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
5964 set_optab_libfunc (smod_optab, HImode, "__modhi3");
5965 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
5966}
5967\f
9eaa7740
AS		 5968/* Worker function for TARGET_FUNCTION_VALUE.
5969
5970 On the H8 the return value is in R0/R1. */
5971
5972static rtx
5973h8300_function_value (const_tree ret_type,
5974 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
5975 bool outgoing ATTRIBUTE_UNUSED)
5976{
5977 return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG);
5978}
5979
5980/* Worker function for TARGET_LIBCALL_VALUE.
5981
5982 On the H8 the return value is in R0/R1. */
5983
5984static rtx
ef4bddc2 5985h8300_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
9eaa7740
AS		 5986{
5987 return gen_rtx_REG (mode, R0_REG);
5988}
5989
5990/* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5991
5992 On the H8, R0 is the only register thus used. */
5993
5994static bool
5995h8300_function_value_regno_p (const unsigned int regno)
5996{
5997 return (regno == R0_REG);
5998}
5999
e9eba255
KH		 6000/* Worker function for TARGET_RETURN_IN_MEMORY. */
6001
34bf1fe3 6002static bool
586de218 6003h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
34bf1fe3
KH		 6004{
6005 return (TYPE_MODE (type) == BLKmode
6006 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
6007}
6008\f
9f6ef043
RH		 6009/* We emit the entire trampoline here. Depending on the pointer size,
6010 we use a different trampoline.
6011
6012 Pmode == HImode
6013 vvvv context
6014 1 0000 7903xxxx mov.w #0x1234,r3
6015 2 0004 5A00xxxx jmp @0x1234
6016 ^^^^ function
6017
6018 Pmode == SImode
6019 vvvvvvvv context
6020 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
6021 3 0006 5Axxxxxx jmp @0x123456
6022 ^^^^^^ function
6023*/
6024
6025static void
6026h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
6027{
6028 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6029 rtx mem;
6030
6031 if (Pmode == HImode)
6032 {
6033 mem = adjust_address (m_tramp, HImode, 0);
6034 emit_move_insn (mem, GEN_INT (0x7903));
6035 mem = adjust_address (m_tramp, Pmode, 2);
6036 emit_move_insn (mem, cxt);
6037 mem = adjust_address (m_tramp, HImode, 4);
6038 emit_move_insn (mem, GEN_INT (0x5a00));
6039 mem = adjust_address (m_tramp, Pmode, 6);
6040 emit_move_insn (mem, fnaddr);
6041 }
6042 else
6043 {
6044 rtx tem;
6045
6046 mem = adjust_address (m_tramp, HImode, 0);
6047 emit_move_insn (mem, GEN_INT (0x7a03));
6048 mem = adjust_address (m_tramp, Pmode, 2);
6049 emit_move_insn (mem, cxt);
6050
6051 tem = copy_to_reg (fnaddr);
6052 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff)));
6053 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000)));
6054 mem = adjust_address (m_tramp, SImode, 6);
6055 emit_move_insn (mem, tem);
6056 }
6057}
6058\f
6e014ef3
KH		 6059/* Initialize the GCC target structure. */
6060#undef TARGET_ATTRIBUTE_TABLE
6061#define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
6062
6063#undef TARGET_ASM_ALIGNED_HI_OP
6064#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
6065
1bc7c5b6
ZW		 6066#undef TARGET_ASM_FILE_START
6067#define TARGET_ASM_FILE_START h8300_file_start
6068#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
6069#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
6070
6e014ef3
KH		 6071#undef TARGET_ASM_FILE_END
6072#define TARGET_ASM_FILE_END h8300_file_end
6073
88cb339e
N		 6074#undef TARGET_PRINT_OPERAND
6075#define TARGET_PRINT_OPERAND h8300_print_operand
6076#undef TARGET_PRINT_OPERAND_ADDRESS
6077#define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
6078#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
6079#define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
6080
6e014ef3
KH		 6081#undef TARGET_ENCODE_SECTION_INFO
6082#define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
6083
6084#undef TARGET_INSERT_ATTRIBUTES
6085#define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
6086
88cb339e
N		 6087#undef TARGET_REGISTER_MOVE_COST
6088#define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
6089
6e014ef3
KH		 6090#undef TARGET_RTX_COSTS
6091#define TARGET_RTX_COSTS h8300_rtx_costs
6092
c15c90bb
ZW		 6093#undef TARGET_INIT_LIBFUNCS
6094#define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
6095
9eaa7740
AS		 6096#undef TARGET_FUNCTION_VALUE
6097#define TARGET_FUNCTION_VALUE h8300_function_value
6098
6099#undef TARGET_LIBCALL_VALUE
6100#define TARGET_LIBCALL_VALUE h8300_libcall_value
6101
6102#undef TARGET_FUNCTION_VALUE_REGNO_P
6103#define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
6104
34bf1fe3
KH		 6105#undef TARGET_RETURN_IN_MEMORY
6106#define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
6107
56f9413b
NF		 6108#undef TARGET_FUNCTION_ARG
6109#define TARGET_FUNCTION_ARG h8300_function_arg
6110
6111#undef TARGET_FUNCTION_ARG_ADVANCE
6112#define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
6113
beed8fc0
AO		 6114#undef TARGET_MACHINE_DEPENDENT_REORG
6115#define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
6116
2e762884
DD		 6117#undef TARGET_HARD_REGNO_SCRATCH_OK
6118#define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
6119
c6c3dba9
PB		 6120#undef TARGET_LEGITIMATE_ADDRESS_P
6121#define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
6122
7b5cbb57
AS		 6123#undef TARGET_CAN_ELIMINATE
6124#define TARGET_CAN_ELIMINATE h8300_can_eliminate
6125
5efd84c5
NF		 6126#undef TARGET_CONDITIONAL_REGISTER_USAGE
6127#define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
6128
9f6ef043
RH		 6129#undef TARGET_TRAMPOLINE_INIT
6130#define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6131
c5387660
JM		 6132#undef TARGET_OPTION_OVERRIDE
6133#define TARGET_OPTION_OVERRIDE h8300_option_override
6134
f52d97da
AS		 6135#undef TARGET_MODE_DEPENDENT_ADDRESS_P
6136#define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6137
6e014ef3 6138struct gcc_target targetm = TARGET_INITIALIZER;
Mirror of https://gcc.gnu.org/git/gcc.git