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f0b6f9a6 | 1 | /* Definitions of target machine for GNU compiler. |
340f6494 | 2 | Renesas H8/300 (generic) |
cf011243 | 3 | Copyright (C) 1992, 1993, 1994, 1995, 1996, 1996, 1997, 1998, 1999, |
2f83c7d6 | 4 | 2000, 2001, 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc. |
7bc8cb2b DE |
5 | Contributed by Steve Chamberlain (sac@cygnus.com), |
6 | Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). | |
07aae5c2 | 7 | |
8aa063fb | 8 | This file is part of GCC. |
07aae5c2 | 9 | |
8aa063fb | 10 | GCC is free software; you can redistribute it and/or modify |
07aae5c2 | 11 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 12 | the Free Software Foundation; either version 3, or (at your option) |
07aae5c2 SC |
13 | any later version. |
14 | ||
8aa063fb | 15 | GCC is distributed in the hope that it will be useful, |
07aae5c2 SC |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
21 | along with GCC; see the file COPYING3. If not see |
22 | <http://www.gnu.org/licenses/>. */ | |
07aae5c2 | 23 | |
8b97c5f8 ZW |
24 | #ifndef GCC_H8300_H |
25 | #define GCC_H8300_H | |
26 | ||
2c54abce | 27 | /* Which CPU to compile for. |
7bc8cb2b DE |
28 | We use int for CPU_TYPE to avoid lots of casts. */ |
29 | #if 0 /* defined in insn-attr.h, here for documentation */ | |
30 | enum attr_cpu { CPU_H8300, CPU_H8300H }; | |
31 | #endif | |
32 | extern int cpu_type; | |
33 | ||
34 | /* Various globals defined in h8300.c. */ | |
35 | ||
07e4d94e | 36 | extern const char *h8_push_op, *h8_pop_op, *h8_mov_op; |
441d04c6 | 37 | extern const char * const *h8_reg_names; |
7bc8cb2b | 38 | |
537fc532 NB |
39 | /* Target CPU builtins. */ |
40 | #define TARGET_CPU_CPP_BUILTINS() \ | |
41 | do \ | |
42 | { \ | |
43 | if (TARGET_H8300H) \ | |
920e86b8 | 44 | { \ |
537fc532 NB |
45 | builtin_define ("__H8300H__"); \ |
46 | builtin_assert ("cpu=h8300h"); \ | |
47 | builtin_assert ("machine=h8300h"); \ | |
39ba95b5 VK |
48 | if (TARGET_NORMAL_MODE) \ |
49 | { \ | |
50 | builtin_define ("__NORMAL_MODE__"); \ | |
51 | } \ | |
537fc532 | 52 | } \ |
beed8fc0 AO |
53 | else if (TARGET_H8300SX) \ |
54 | { \ | |
55 | builtin_define ("__H8300SX__"); \ | |
56 | if (TARGET_NORMAL_MODE) \ | |
57 | { \ | |
58 | builtin_define ("__NORMAL_MODE__"); \ | |
59 | } \ | |
60 | } \ | |
537fc532 | 61 | else if (TARGET_H8300S) \ |
920e86b8 | 62 | { \ |
537fc532 NB |
63 | builtin_define ("__H8300S__"); \ |
64 | builtin_assert ("cpu=h8300s"); \ | |
65 | builtin_assert ("machine=h8300s"); \ | |
39ba95b5 VK |
66 | if (TARGET_NORMAL_MODE) \ |
67 | { \ | |
68 | builtin_define ("__NORMAL_MODE__"); \ | |
69 | } \ | |
537fc532 NB |
70 | } \ |
71 | else \ | |
920e86b8 | 72 | { \ |
537fc532 NB |
73 | builtin_define ("__H8300__"); \ |
74 | builtin_assert ("cpu=h8300"); \ | |
75 | builtin_assert ("machine=h8300"); \ | |
76 | } \ | |
537fc532 NB |
77 | } \ |
78 | while (0) | |
7bc8cb2b | 79 | |
5c29d24c | 80 | #define LINK_SPEC "%{mh:%{mn:-m h8300hn}} %{mh:%{!mn:-m h8300h}} %{ms:%{mn:-m h8300sn}} %{ms:%{!mn:-m h8300s}}" |
7bc8cb2b DE |
81 | |
82 | #define LIB_SPEC "%{mrelax:-relax} %{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}" | |
07aae5c2 | 83 | |
920e86b8 KH |
84 | #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ |
85 | do \ | |
86 | { \ | |
87 | /* Basic block reordering is only beneficial on targets with cache \ | |
88 | and/or variable-cycle branches where (cycle count taken != \ | |
89 | cycle count not taken). */ \ | |
90 | flag_reorder_blocks = 0; \ | |
91 | } \ | |
25a533a0 TM |
92 | while (0) |
93 | ||
07aae5c2 | 94 | /* Print subsidiary information on the compiler version in use. */ |
7bc8cb2b | 95 | |
340f6494 | 96 | #define TARGET_VERSION fprintf (stderr, " (Renesas H8/300)"); |
7bc8cb2b | 97 | |
07aae5c2 SC |
98 | /* Macros used in the machine description to test the flags. */ |
99 | ||
1898584f | 100 | /* Select between the H8/300 and H8/300H CPUs. */ |
a1616dd9 | 101 | #define TARGET_H8300 (! TARGET_H8300H && ! TARGET_H8300S) |
5463c726 | 102 | #define TARGET_H8300S (TARGET_H8300S_1 || TARGET_H8300SX) |
beed8fc0 AO |
103 | /* Some multiply instructions are not available in all H8SX variants. |
104 | Use this macro instead of TARGET_H8300SX to indicate this, even | |
105 | though we don't actually generate different code for now. */ | |
106 | #define TARGET_H8300SXMUL TARGET_H8300SX | |
07aae5c2 | 107 | |
996ed075 JJ |
108 | #ifdef IN_LIBGCC2 |
109 | #undef TARGET_H8300H | |
110 | #undef TARGET_H8300S | |
39ba95b5 | 111 | #undef TARGET_NORMAL_MODE |
996ed075 JJ |
112 | /* If compiling libgcc2, make these compile time constants based on what |
113 | flags are we actually compiling with. */ | |
114 | #ifdef __H8300H__ | |
115 | #define TARGET_H8300H 1 | |
116 | #else | |
117 | #define TARGET_H8300H 0 | |
118 | #endif | |
119 | #ifdef __H8300S__ | |
120 | #define TARGET_H8300S 1 | |
121 | #else | |
122 | #define TARGET_H8300S 0 | |
123 | #endif | |
39ba95b5 VK |
124 | #ifdef __NORMAL_MODE__ |
125 | #define TARGET_NORMAL_MODE 1 | |
126 | #else | |
127 | #define TARGET_NORMAL_MODE 0 | |
128 | #endif | |
996ed075 JJ |
129 | #endif /* !IN_LIBGCC2 */ |
130 | ||
43074b10 | 131 | /* Do things that must be done once at start up. */ |
3511415d | 132 | |
2c54abce KH |
133 | #define OVERRIDE_OPTIONS \ |
134 | do \ | |
135 | { \ | |
136 | h8300_init_once (); \ | |
137 | } \ | |
138 | while (0) | |
7bc8cb2b DE |
139 | |
140 | /* Default target_flags if no switches specified. */ | |
141 | ||
142 | #ifndef TARGET_DEFAULT | |
3950794d | 143 | #define TARGET_DEFAULT (MASK_QUICKCALL) |
7bc8cb2b DE |
144 | #endif |
145 | ||
faa2075e | 146 | /* Show we can debug even without a frame pointer. */ |
7bc8cb2b | 147 | /* #define CAN_DEBUG_WITHOUT_FP */ |
07aae5c2 | 148 | |
faa2075e RK |
149 | /* Define this if addresses of constant functions |
150 | shouldn't be put through pseudo regs where they can be cse'd. | |
151 | Desirable on machines where ordinary constants are expensive | |
f0b6f9a6 | 152 | but a CALL with constant address is cheap. |
bd93f126 JL |
153 | |
154 | Calls through a register are cheaper than calls to named | |
155 | functions; however, the register pressure this causes makes | |
156 | CSEing of function addresses generally a lose. */ | |
07e4d94e | 157 | #define NO_FUNCTION_CSE |
07aae5c2 | 158 | \f |
7bc8cb2b DE |
159 | /* Target machine storage layout */ |
160 | ||
07aae5c2 SC |
161 | /* Define this if most significant bit is lowest numbered |
162 | in instructions that operate on numbered bit-fields. | |
163 | This is not true on the H8/300. */ | |
164 | #define BITS_BIG_ENDIAN 0 | |
165 | ||
166 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
167 | /* That is true on the H8/300. */ | |
168 | #define BYTES_BIG_ENDIAN 1 | |
169 | ||
170 | /* Define this if most significant word of a multiword number is lowest | |
3f69c502 | 171 | numbered. */ |
07aae5c2 SC |
172 | #define WORDS_BIG_ENDIAN 1 |
173 | ||
7bc8cb2b | 174 | #define MAX_BITS_PER_WORD 32 |
07aae5c2 SC |
175 | |
176 | /* Width of a word, in units (bytes). */ | |
a1616dd9 | 177 | #define UNITS_PER_WORD (TARGET_H8300H || TARGET_H8300S ? 4 : 2) |
ef0e53ce | 178 | #define MIN_UNITS_PER_WORD 2 |
07aae5c2 | 179 | |
f9477efd KH |
180 | #define SHORT_TYPE_SIZE 16 |
181 | #define INT_TYPE_SIZE (TARGET_INT32 ? 32 : 16) | |
182 | #define LONG_TYPE_SIZE 32 | |
5d39821d | 183 | #define LONG_LONG_TYPE_SIZE 64 |
f9477efd KH |
184 | #define FLOAT_TYPE_SIZE 32 |
185 | #define DOUBLE_TYPE_SIZE 32 | |
186 | #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE | |
07aae5c2 | 187 | |
f9477efd | 188 | #define MAX_FIXED_MODE_SIZE 32 |
07aae5c2 SC |
189 | |
190 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
a1616dd9 | 191 | #define PARM_BOUNDARY (TARGET_H8300H || TARGET_H8300S ? 32 : 16) |
07aae5c2 SC |
192 | |
193 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
194 | #define FUNCTION_BOUNDARY 16 | |
195 | ||
196 | /* Alignment of field after `int : 0' in a structure. */ | |
da55315a KH |
197 | /* One can argue this should be 32 for -mint32, but since 32-bit ints only |
198 | need 16-bit alignment, this is left as is so that -mint32 doesn't change | |
a6cc0d48 | 199 | structure layouts. */ |
7bc8cb2b | 200 | #define EMPTY_FIELD_BOUNDARY 16 |
07aae5c2 | 201 | |
a6cc0d48 | 202 | /* No data type wants to be aligned rounder than this. |
da55315a | 203 | 32-bit values are aligned as such on the H8/300H and H8S for speed. */ |
20d1e666 | 204 | #define BIGGEST_ALIGNMENT \ |
a1616dd9 | 205 | (((TARGET_H8300H || TARGET_H8300S) && ! TARGET_ALIGN_300) ? 32 : 16) |
07aae5c2 | 206 | |
7bc8cb2b DE |
207 | /* The stack goes in 16/32 bit lumps. */ |
208 | #define STACK_BOUNDARY (TARGET_H8300 ? 16 : 32) | |
07aae5c2 SC |
209 | |
210 | /* Define this if move instructions will actually fail to work | |
211 | when given unaligned data. */ | |
7bc8cb2b DE |
212 | /* On the H8/300, longs can be aligned on halfword boundaries, but not |
213 | byte boundaries. */ | |
07aae5c2 SC |
214 | #define STRICT_ALIGNMENT 1 |
215 | \f | |
216 | /* Standard register usage. */ | |
217 | ||
218 | /* Number of actual hardware registers. | |
219 | The hardware registers are assigned numbers for the compiler | |
220 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
221 | ||
222 | All registers that the compiler knows about must be given numbers, | |
f0b6f9a6 | 223 | even those that are not normally considered general registers. |
07aae5c2 | 224 | |
7d9f07f4 | 225 | Reg 9 does not correspond to any hardware register, but instead |
07aae5c2 SC |
226 | appears in the RTL as an argument pointer prior to reload, and is |
227 | eliminated during reloading in favor of either the stack or frame | |
228 | pointer. */ | |
7bc8cb2b | 229 | |
1807b726 | 230 | #define FIRST_PSEUDO_REGISTER 12 |
07aae5c2 SC |
231 | |
232 | /* 1 for registers that have pervasive standard uses | |
7bc8cb2b | 233 | and are not available for the register allocator. */ |
07aae5c2 | 234 | |
ef3f573f KH |
235 | #define FIXED_REGISTERS \ |
236 | /* r0 r1 r2 r3 r4 r5 r6 r7 mac ap rap fp */ \ | |
237 | { 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1 } | |
07aae5c2 SC |
238 | |
239 | /* 1 for registers not available across function calls. | |
240 | These must include the FIXED_REGISTERS and also any | |
241 | registers that can be used without being saved. | |
242 | The latter must include the registers where values are returned | |
243 | and the register where structure-value addresses are passed. | |
244 | Aside from that, you can include as many other registers as you | |
f0b6f9a6 | 245 | like. |
07aae5c2 | 246 | |
2c54abce | 247 | H8 destroys r0,r1,r2,r3. */ |
07aae5c2 | 248 | |
ef3f573f KH |
249 | #define CALL_USED_REGISTERS \ |
250 | /* r0 r1 r2 r3 r4 r5 r6 r7 mac ap rap fp */ \ | |
251 | { 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1 } | |
07aae5c2 | 252 | |
ef3f573f KH |
253 | #define REG_ALLOC_ORDER \ |
254 | /* r0 r1 r2 r3 r4 r5 r6 r7 mac ap rap fp */ \ | |
255 | { 2, 3, 0, 1, 4, 5, 6, 8, 7, 9, 10, 11 } | |
7d9f07f4 | 256 | |
1c11abc4 KH |
257 | #define CONDITIONAL_REGISTER_USAGE \ |
258 | { \ | |
259 | if (!TARGET_MAC) \ | |
260 | fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1; \ | |
7d9f07f4 | 261 | } |
07aae5c2 | 262 | |
07ee3b58 KH |
263 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
264 | h8300_hard_regno_nregs ((REGNO), (MODE)) | |
07aae5c2 | 265 | |
07ee3b58 KH |
266 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
267 | h8300_hard_regno_mode_ok ((REGNO), (MODE)) | |
07aae5c2 SC |
268 | |
269 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
270 | when one has mode MODE1 and one has mode MODE2. | |
271 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
272 | for any hard reg, then this must be 0 for correct output. */ | |
c283e63f KH |
273 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
274 | ((MODE1) == (MODE2) \ | |
275 | || (((MODE1) == QImode || (MODE1) == HImode \ | |
276 | || ((TARGET_H8300H || TARGET_H8300S) && (MODE1) == SImode)) \ | |
277 | && ((MODE2) == QImode || (MODE2) == HImode \ | |
278 | || ((TARGET_H8300H || TARGET_H8300S) && (MODE2) == SImode)))) | |
07aae5c2 | 279 | |
c87ec0ba NY |
280 | /* A C expression that is nonzero if hard register NEW_REG can be |
281 | considered for use as a rename register for OLD_REG register */ | |
282 | ||
283 | #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ | |
284 | h8300_hard_regno_rename_ok (OLD_REG, NEW_REG) | |
285 | ||
07aae5c2 SC |
286 | /* Specify the registers used for certain standard purposes. |
287 | The values of these macros are register numbers. */ | |
288 | ||
289 | /* H8/300 pc is not overloaded on a register. */ | |
7bc8cb2b | 290 | |
07aae5c2 SC |
291 | /*#define PC_REGNUM 15*/ |
292 | ||
293 | /* Register to use for pushing function arguments. */ | |
72431aef | 294 | #define STACK_POINTER_REGNUM SP_REG |
07aae5c2 | 295 | |
1807b726 KH |
296 | /* Base register for access to local variables of the function. */ |
297 | #define HARD_FRAME_POINTER_REGNUM HFP_REG | |
298 | ||
07aae5c2 | 299 | /* Base register for access to local variables of the function. */ |
72431aef | 300 | #define FRAME_POINTER_REGNUM FP_REG |
07aae5c2 SC |
301 | |
302 | /* Value should be nonzero if functions must have frame pointers. | |
303 | Zero means the frame pointer need not be set up (and parms | |
304 | may be accessed via the stack pointer) in functions that seem suitable. | |
305 | This is computed in `reload', in reload1.c. */ | |
306 | #define FRAME_POINTER_REQUIRED 0 | |
307 | ||
308 | /* Base register for access to arguments of the function. */ | |
1c11abc4 | 309 | #define ARG_POINTER_REGNUM AP_REG |
07aae5c2 SC |
310 | |
311 | /* Register in which static-chain is passed to a function. */ | |
1c11abc4 | 312 | #define STATIC_CHAIN_REGNUM SC_REG |
1aae372e JL |
313 | |
314 | /* Fake register that holds the address on the stack of the | |
315 | current function's return address. */ | |
1c11abc4 | 316 | #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG |
1aae372e JL |
317 | |
318 | /* A C expression whose value is RTL representing the value of the return | |
319 | address for the frame COUNT steps up from the current frame. | |
320 | FRAMEADDR is already the frame pointer of the COUNT frame, assuming | |
321 | a stack layout with the frame pointer as the first saved register. */ | |
322 | #define RETURN_ADDR_RTX(COUNT, FRAME) h8300_return_addr_rtx ((COUNT), (FRAME)) | |
07aae5c2 SC |
323 | \f |
324 | /* Define the classes of registers for register constraints in the | |
325 | machine description. Also define ranges of constants. | |
326 | ||
327 | One of the classes must always be named ALL_REGS and include all hard regs. | |
328 | If there is more than one class, another class must be named NO_REGS | |
329 | and contain no registers. | |
330 | ||
331 | The name GENERAL_REGS must be the name of a class (or an alias for | |
332 | another name such as ALL_REGS). This is the class of registers | |
333 | that is allowed by "g" or "r" in a register constraint. | |
334 | Also, registers outside this class are allocated only when | |
335 | instructions express preferences for them. | |
336 | ||
337 | The classes must be numbered in nondecreasing order; that is, | |
338 | a larger-numbered class must never be contained completely | |
339 | in a smaller-numbered class. | |
340 | ||
341 | For any two classes, it is very desirable that there be another | |
342 | class that represents their union. */ | |
07e4d94e | 343 | |
269c14e1 | 344 | enum reg_class { |
beed8fc0 AO |
345 | NO_REGS, COUNTER_REGS, SOURCE_REGS, DESTINATION_REGS, |
346 | GENERAL_REGS, MAC_REGS, ALL_REGS, LIM_REG_CLASSES | |
269c14e1 | 347 | }; |
07aae5c2 | 348 | |
2918c993 | 349 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) |
07aae5c2 | 350 | |
ed168e45 | 351 | /* Give names of register classes as strings for dump file. */ |
07aae5c2 SC |
352 | |
353 | #define REG_CLASS_NAMES \ | |
beed8fc0 AO |
354 | { "NO_REGS", "COUNTER_REGS", "SOURCE_REGS", "DESTINATION_REGS", \ |
355 | "GENERAL_REGS", "MAC_REGS", "ALL_REGS", "LIM_REGS" } | |
07aae5c2 SC |
356 | |
357 | /* Define which registers fit in which classes. | |
358 | This is an initializer for a vector of HARD_REG_SET | |
359 | of length N_REG_CLASSES. */ | |
360 | ||
f9477efd | 361 | #define REG_CLASS_CONTENTS \ |
441d04c6 | 362 | { {0}, /* No regs */ \ |
beed8fc0 AO |
363 | {0x010}, /* COUNTER_REGS */ \ |
364 | {0x020}, /* SOURCE_REGS */ \ | |
365 | {0x040}, /* DESTINATION_REGS */ \ | |
ef3f573f | 366 | {0xeff}, /* GENERAL_REGS */ \ |
beed8fc0 | 367 | {0x100}, /* MAC_REGS */ \ |
ef3f573f | 368 | {0xfff}, /* ALL_REGS */ \ |
07aae5c2 SC |
369 | } |
370 | ||
7bc8cb2b DE |
371 | /* The same information, inverted: |
372 | Return the class number of the smallest class containing | |
373 | reg number REGNO. This could be a conditional expression | |
7d9f07f4 | 374 | or could index an array. */ |
bd93f126 | 375 | |
beed8fc0 AO |
376 | #define REGNO_REG_CLASS(REGNO) \ |
377 | ((REGNO) == MAC_REG ? MAC_REGS \ | |
378 | : (REGNO) == COUNTER_REG ? COUNTER_REGS \ | |
379 | : (REGNO) == SOURCE_REG ? SOURCE_REGS \ | |
380 | : (REGNO) == DESTINATION_REG ? DESTINATION_REGS \ | |
381 | : GENERAL_REGS) | |
07aae5c2 SC |
382 | |
383 | /* The class value for index registers, and the one for base regs. */ | |
384 | ||
beed8fc0 | 385 | #define INDEX_REG_CLASS (TARGET_H8300SX ? GENERAL_REGS : NO_REGS) |
07aae5c2 SC |
386 | #define BASE_REG_CLASS GENERAL_REGS |
387 | ||
f0b6f9a6 | 388 | /* Get reg_class from a letter such as appears in the machine description. |
7d9f07f4 JL |
389 | |
390 | 'a' is the MAC register. */ | |
07aae5c2 | 391 | |
beed8fc0 | 392 | #define REG_CLASS_FROM_LETTER(C) (h8300_reg_class_from_letter (C)) |
07aae5c2 SC |
393 | |
394 | /* The letters I, J, K, L, M, N, O, P in a register constraint string | |
395 | can be used to stand for particular ranges of immediate operands. | |
396 | This macro defines what the ranges are. | |
397 | C is the letter, and VALUE is a constant value. | |
398 | Return 1 if VALUE is in the range specified by C. */ | |
399 | ||
7bc8cb2b | 400 | #define CONST_OK_FOR_I(VALUE) ((VALUE) == 0) |
8cc5359b | 401 | #define CONST_OK_FOR_J(VALUE) (((VALUE) & 0xff) == 0) |
1a63219b KH |
402 | #define CONST_OK_FOR_L(VALUE) \ |
403 | (TARGET_H8300H || TARGET_H8300S \ | |
404 | ? (VALUE) == 1 || (VALUE) == 2 || (VALUE) == 4 \ | |
009ac3d3 | 405 | : (VALUE) == 1 || (VALUE) == 2) |
f9d2de4d KH |
406 | #define CONST_OK_FOR_M(VALUE) \ |
407 | ((VALUE) == 1 || (VALUE) == 2) | |
1a63219b KH |
408 | #define CONST_OK_FOR_N(VALUE) \ |
409 | (TARGET_H8300H || TARGET_H8300S \ | |
410 | ? (VALUE) == -1 || (VALUE) == -2 || (VALUE) == -4 \ | |
009ac3d3 | 411 | : (VALUE) == -1 || (VALUE) == -2) |
f9d2de4d KH |
412 | #define CONST_OK_FOR_O(VALUE) \ |
413 | ((VALUE) == -1 || (VALUE) == -2) | |
7bc8cb2b | 414 | |
beed8fc0 AO |
415 | /* Multi-letter constraints for constant are always started with P |
416 | (just because it was the only letter in the range left. New | |
417 | constraints for constants should be added here. */ | |
418 | #define CONST_OK_FOR_Ppositive(VALUE, NBITS) \ | |
419 | ((VALUE) > 0 && (VALUE) < (1 << (NBITS))) | |
420 | #define CONST_OK_FOR_Pnegative(VALUE, NBITS) \ | |
421 | ((VALUE) < 0 && (VALUE) > -(1 << (NBITS))) | |
422 | #define CONST_OK_FOR_P(VALUE, STR) \ | |
423 | ((STR)[1] >= '1' && (STR)[1] <= '9' && (STR)[2] == '<' \ | |
424 | ? (((STR)[3] == '0' || ((STR)[3] == 'X' && TARGET_H8300SX)) \ | |
425 | && CONST_OK_FOR_Pnegative ((VALUE), (STR)[1] - '0')) \ | |
426 | : ((STR)[1] >= '1' && (STR)[1] <= '9' && (STR)[2] == '>') \ | |
427 | ? (((STR)[3] == '0' || ((STR)[3] == 'X' && TARGET_H8300SX)) \ | |
428 | && CONST_OK_FOR_Ppositive ((VALUE), (STR)[1] - '0')) \ | |
429 | : 0) | |
430 | #define CONSTRAINT_LEN_FOR_P(STR) \ | |
431 | ((((STR)[1] >= '1' && (STR)[1] <= '9') \ | |
432 | && ((STR)[2] == '<' || (STR)[2] == '>') \ | |
433 | && ((STR)[3] == 'X' || (STR)[3] == '0')) ? 4 \ | |
434 | : 0) | |
435 | ||
436 | #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \ | |
437 | ((C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR)) \ | |
438 | : CONST_OK_FOR_LETTER_P ((VALUE), (C))) | |
439 | ||
1a63219b KH |
440 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ |
441 | ((C) == 'I' ? CONST_OK_FOR_I (VALUE) : \ | |
8cc5359b | 442 | (C) == 'J' ? CONST_OK_FOR_J (VALUE) : \ |
1a63219b | 443 | (C) == 'L' ? CONST_OK_FOR_L (VALUE) : \ |
f9d2de4d | 444 | (C) == 'M' ? CONST_OK_FOR_M (VALUE) : \ |
1a63219b | 445 | (C) == 'N' ? CONST_OK_FOR_N (VALUE) : \ |
f9d2de4d | 446 | (C) == 'O' ? CONST_OK_FOR_O (VALUE) : \ |
07aae5c2 SC |
447 | 0) |
448 | ||
449 | /* Similar, but for floating constants, and defining letters G and H. | |
f0b6f9a6 KH |
450 | Here VALUE is the CONST_DOUBLE rtx itself. |
451 | ||
7bc8cb2b | 452 | `G' is a floating-point zero. */ |
07aae5c2 | 453 | |
1a63219b | 454 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ |
fad37371 | 455 | ((C) == 'G' ? (VALUE) == CONST0_RTX (SFmode) \ |
07aae5c2 SC |
456 | : 0) |
457 | ||
458 | /* Given an rtx X being reloaded into a reg required to be | |
459 | in class CLASS, return the class of reg to actually use. | |
460 | In general this is just CLASS; but on some machines | |
461 | in some cases it is preferable to use a more restrictive class. */ | |
7bc8cb2b | 462 | |
f48f56b1 | 463 | #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS) |
07aae5c2 SC |
464 | |
465 | /* Return the maximum number of consecutive registers | |
466 | needed to represent mode MODE in a register of class CLASS. */ | |
467 | ||
7bc8cb2b DE |
468 | /* On the H8, this is the size of MODE in words. */ |
469 | ||
07aae5c2 SC |
470 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
471 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
472 | ||
f0b6f9a6 | 473 | /* Any SI register-to-register move may need to be reloaded, |
07aae5c2 SC |
474 | so define REGISTER_MOVE_COST to be > 2 so that reload never |
475 | shortcuts. */ | |
7bc8cb2b | 476 | |
cf011243 | 477 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
7d9f07f4 | 478 | (CLASS1 == MAC_REGS || CLASS2 == MAC_REGS ? 6 : 3) |
07aae5c2 SC |
479 | \f |
480 | /* Stack layout; function entry, exit and calling. */ | |
481 | ||
482 | /* Define this if pushing a word on the stack | |
483 | makes the stack pointer a smaller address. */ | |
7bc8cb2b | 484 | |
07aae5c2 SC |
485 | #define STACK_GROWS_DOWNWARD |
486 | ||
a4d05547 | 487 | /* Define this to nonzero if the nominal address of the stack frame |
07aae5c2 SC |
488 | is at the high-address end of the local variables; |
489 | that is, each additional local variable allocated | |
490 | goes at a more negative offset in the frame. */ | |
7bc8cb2b | 491 | |
f62c8a5c | 492 | #define FRAME_GROWS_DOWNWARD 1 |
07aae5c2 SC |
493 | |
494 | /* Offset within stack frame to start allocating local variables at. | |
495 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
496 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
497 | of the first local allocated. */ | |
7bc8cb2b | 498 | |
07aae5c2 SC |
499 | #define STARTING_FRAME_OFFSET 0 |
500 | ||
501 | /* If we generate an insn to push BYTES bytes, | |
502 | this says how many the stack pointer really advances by. | |
503 | ||
504 | On the H8/300, @-sp really pushes a byte if you ask it to - but that's | |
505 | dangerous, so we claim that it always pushes a word, then we catch | |
7bc8cb2b | 506 | the mov.b rx,@-sp and turn it into a mov.w rx,@-sp on output. |
07aae5c2 | 507 | |
1120a1d3 KH |
508 | On the H8/300H, we simplify TARGET_QUICKCALL by setting this to 4 |
509 | and doing a similar thing. */ | |
07aae5c2 | 510 | |
7bc8cb2b | 511 | #define PUSH_ROUNDING(BYTES) \ |
1120a1d3 | 512 | (((BYTES) + PARM_BOUNDARY / 8 - 1) & -PARM_BOUNDARY / 8) |
7bc8cb2b DE |
513 | |
514 | /* Offset of first parameter from the argument pointer register value. */ | |
07aae5c2 SC |
515 | /* Is equal to the size of the saved fp + pc, even if an fp isn't |
516 | saved since the value is used before we know. */ | |
7bc8cb2b | 517 | |
07aae5c2 SC |
518 | #define FIRST_PARM_OFFSET(FNDECL) 0 |
519 | ||
520 | /* Value is the number of bytes of arguments automatically | |
521 | popped when returning from a subroutine call. | |
8b109b37 | 522 | FUNDECL is the declaration node of the function (as a tree), |
07aae5c2 SC |
523 | FUNTYPE is the data type of the function (as a tree), |
524 | or for a library call it is an identifier node for the subroutine name. | |
525 | SIZE is the number of bytes of arguments passed on the stack. | |
526 | ||
7bc8cb2b DE |
527 | On the H8 the return does not pop anything. */ |
528 | ||
f48f56b1 | 529 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 |
07aae5c2 SC |
530 | |
531 | /* Definitions for register eliminations. | |
532 | ||
533 | This is an array of structures. Each structure initializes one pair | |
534 | of eliminable registers. The "from" register number is given first, | |
535 | followed by "to". Eliminations of the same "from" register are listed | |
536 | in order of preference. | |
537 | ||
7e920754 KH |
538 | We have three registers that can be eliminated on the h8300. |
539 | First, the frame pointer register can often be eliminated in favor | |
540 | of the stack pointer register. Secondly, the argument pointer | |
541 | register and the return address pointer register are always | |
542 | eliminated; they are replaced with either the stack or frame | |
543 | pointer. */ | |
7bc8cb2b | 544 | |
1807b726 KH |
545 | #define ELIMINABLE_REGS \ |
546 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
547 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
548 | { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
549 | { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
550 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
551 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} | |
07aae5c2 | 552 | |
7bc8cb2b DE |
553 | /* Given FROM and TO register numbers, say whether this elimination is allowed. |
554 | Frame pointer elimination is automatically handled. | |
555 | ||
556 | For the h8300, if frame pointer elimination is being done, we would like to | |
1aae372e | 557 | convert ap and rp into sp, not fp. |
7bc8cb2b DE |
558 | |
559 | All other eliminations are valid. */ | |
560 | ||
07aae5c2 | 561 | #define CAN_ELIMINATE(FROM, TO) \ |
616dc555 | 562 | ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) |
07aae5c2 SC |
563 | |
564 | /* Define the offset between two registers, one to be eliminated, and the other | |
565 | its replacement, at the start of a routine. */ | |
7bc8cb2b | 566 | |
d7af42bc KH |
567 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
568 | ((OFFSET) = h8300_initial_elimination_offset ((FROM), (TO))) | |
07aae5c2 SC |
569 | |
570 | /* Define how to find the value returned by a function. | |
571 | VALTYPE is the data type of the value (as a tree). | |
572 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
f0b6f9a6 KH |
573 | otherwise, FUNC is 0. |
574 | ||
7bc8cb2b DE |
575 | On the H8 the return value is in R0/R1. */ |
576 | ||
07aae5c2 | 577 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
ef3b9941 | 578 | gen_rtx_REG (TYPE_MODE (VALTYPE), R0_REG) |
07aae5c2 SC |
579 | |
580 | /* Define how to find the value returned by a library function | |
581 | assuming the value has mode MODE. */ | |
582 | ||
1120a1d3 | 583 | /* On the H8 the return value is in R0/R1. */ |
7bc8cb2b | 584 | |
07aae5c2 | 585 | #define LIBCALL_VALUE(MODE) \ |
a1dce8d1 | 586 | gen_rtx_REG (MODE, R0_REG) |
07aae5c2 SC |
587 | |
588 | /* 1 if N is a possible register number for a function value. | |
7bc8cb2b DE |
589 | On the H8, R0 is the only register thus used. */ |
590 | ||
ef3b9941 | 591 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == R0_REG) |
07aae5c2 SC |
592 | |
593 | /* Define this if PCC uses the nonreentrant convention for returning | |
594 | structure and union values. */ | |
7bc8cb2b DE |
595 | |
596 | /*#define PCC_STATIC_STRUCT_RETURN*/ | |
07aae5c2 SC |
597 | |
598 | /* 1 if N is a possible register number for function argument passing. | |
7bc8cb2b | 599 | On the H8, no registers are used in this way. */ |
7bc8cb2b | 600 | |
3b7d443c | 601 | #define FUNCTION_ARG_REGNO_P(N) (TARGET_QUICKCALL ? N < 3 : 0) |
07aae5c2 | 602 | |
07aae5c2 SC |
603 | /* When defined, the compiler allows registers explicitly used in the |
604 | rtl to be used as spill registers but prevents the compiler from | |
9bf7ec4e | 605 | extending the lifetime of these registers. */ |
7bc8cb2b | 606 | |
2922fe9e | 607 | #define SMALL_REGISTER_CLASSES 1 |
07aae5c2 SC |
608 | \f |
609 | /* Define a data type for recording info about an argument list | |
610 | during the scan of that argument list. This data type should | |
7bc8cb2b | 611 | hold all necessary information about the function itself |
07aae5c2 SC |
612 | and about the args processed so far, enough to enable macros |
613 | such as FUNCTION_ARG to determine where the next arg should go. | |
614 | ||
1120a1d3 KH |
615 | On the H8/300, this is a two item struct, the first is the number |
616 | of bytes scanned so far and the second is the rtx of the called | |
617 | library function if any. */ | |
07aae5c2 SC |
618 | |
619 | #define CUMULATIVE_ARGS struct cum_arg | |
07e4d94e KH |
620 | struct cum_arg |
621 | { | |
622 | int nbytes; | |
623 | struct rtx_def *libcall; | |
624 | }; | |
07aae5c2 SC |
625 | |
626 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
627 | for a call to a function whose data type is FNTYPE. | |
628 | For a library call, FNTYPE is 0. | |
629 | ||
630 | On the H8/300, the offset starts at 0. */ | |
7bc8cb2b | 631 | |
0f6937fe | 632 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ |
7bc8cb2b | 633 | ((CUM).nbytes = 0, (CUM).libcall = LIBNAME) |
07aae5c2 SC |
634 | |
635 | /* Update the data in CUM to advance over an argument | |
636 | of mode MODE and data type TYPE. | |
7bc8cb2b | 637 | (TYPE is null for libcalls where that information may not be available.) */ |
07aae5c2 | 638 | |
1a63219b KH |
639 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
640 | ((CUM).nbytes += ((MODE) != BLKmode \ | |
7bc8cb2b DE |
641 | ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD \ |
642 | : (int_size_in_bytes (TYPE) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD)) | |
07aae5c2 SC |
643 | |
644 | /* Define where to put the arguments to a function. | |
645 | Value is zero to push the argument on the stack, | |
646 | or a hard register in which to store the argument. | |
647 | ||
648 | MODE is the argument's machine mode. | |
649 | TYPE is the data type of the argument (as a tree). | |
650 | This is null for libcalls where that information may | |
651 | not be available. | |
652 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
653 | the preceding args and about the function being called. | |
654 | NAMED is nonzero if this argument is a named parameter | |
655 | (otherwise it is an extra parameter matching an ellipsis). */ | |
656 | ||
7bc8cb2b DE |
657 | /* On the H8/300 all normal args are pushed, unless -mquickcall in which |
658 | case the first 3 arguments are passed in registers. | |
659 | See function `function_arg'. */ | |
07aae5c2 | 660 | |
07aae5c2 SC |
661 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
662 | function_arg (&CUM, MODE, TYPE, NAMED) | |
663 | ||
07aae5c2 SC |
664 | /* Output assembler code to FILE to increment profiler label # LABELNO |
665 | for profiling a function entry. */ | |
666 | ||
7bc8cb2b DE |
667 | #define FUNCTION_PROFILER(FILE, LABELNO) \ |
668 | fprintf (FILE, "\t%s\t#LP%d,%s\n\tjsr @mcount\n", \ | |
669 | h8_mov_op, (LABELNO), h8_reg_names[0]); | |
07aae5c2 | 670 | |
07aae5c2 SC |
671 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
672 | the stack pointer does not matter. The value is tested only in | |
673 | functions that have frame pointers. | |
674 | No definition is equivalent to always zero. */ | |
675 | ||
676 | #define EXIT_IGNORE_STACK 0 | |
677 | ||
9e56a932 KH |
678 | /* We emit the entire trampoline with INITIALIZE_TRAMPOLINE. |
679 | Depending on the pointer size, we use a different trampoline. | |
7bc8cb2b | 680 | |
9e56a932 | 681 | Pmode == HImode |
7bc8cb2b | 682 | vvvv context |
59d7c857 | 683 | 1 0000 7903xxxx mov.w #0x1234,r3 |
8bd06267 | 684 | 2 0004 5A00xxxx jmp @0x1234 |
7bc8cb2b DE |
685 | ^^^^ function |
686 | ||
9e56a932 | 687 | Pmode == SImode |
7bc8cb2b | 688 | vvvvvvvv context |
59d7c857 | 689 | 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3 |
8bd06267 | 690 | 3 0006 5Axxxxxx jmp @0x123456 |
7bc8cb2b DE |
691 | ^^^^^^ function |
692 | */ | |
693 | ||
07aae5c2 SC |
694 | /* Length in units of the trampoline for entering a nested function. */ |
695 | ||
32da7865 | 696 | #define TRAMPOLINE_SIZE ((Pmode == HImode) ? 8 : 12) |
07aae5c2 | 697 | |
9e56a932 | 698 | /* Emit RTL insns to build a trampoline. |
07aae5c2 SC |
699 | FNADDR is an RTX for the address of the function's pure code. |
700 | CXT is an RTX for the static chain value for the function. */ | |
701 | ||
3494f1b4 | 702 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
9e56a932 KH |
703 | do \ |
704 | { \ | |
705 | if (Pmode == HImode) \ | |
706 | { \ | |
707 | emit_move_insn (gen_rtx_MEM (HImode, (TRAMP)), GEN_INT (0x7903)); \ | |
708 | emit_move_insn (gen_rtx_MEM (Pmode, plus_constant ((TRAMP), 2)), \ | |
709 | (CXT)); \ | |
710 | emit_move_insn (gen_rtx_MEM (Pmode, plus_constant ((TRAMP), 4)), \ | |
711 | GEN_INT (0x5a00)); \ | |
712 | emit_move_insn (gen_rtx_MEM (Pmode, plus_constant ((TRAMP), 6)), \ | |
713 | (FNADDR)); \ | |
714 | } \ | |
715 | else \ | |
716 | { \ | |
717 | rtx tem = gen_reg_rtx (Pmode); \ | |
718 | \ | |
719 | emit_move_insn (gen_rtx_MEM (HImode, (TRAMP)), GEN_INT (0x7a03)); \ | |
720 | emit_move_insn (gen_rtx_MEM (Pmode, plus_constant ((TRAMP), 2)), \ | |
721 | (CXT)); \ | |
722 | emit_move_insn (tem, (FNADDR)); \ | |
723 | emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff))); \ | |
724 | emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000))); \ | |
725 | emit_move_insn (gen_rtx_MEM (Pmode, plus_constant ((TRAMP), 6)), \ | |
726 | tem); \ | |
727 | } \ | |
728 | } \ | |
729 | while (0) | |
07aae5c2 | 730 | \f |
7bc8cb2b | 731 | /* Addressing modes, and classification of registers for them. */ |
07aae5c2 | 732 | |
940da324 | 733 | #define HAVE_POST_INCREMENT 1 |
940da324 | 734 | #define HAVE_PRE_DECREMENT 1 |
beed8fc0 AO |
735 | #define HAVE_POST_DECREMENT TARGET_H8300SX |
736 | #define HAVE_PRE_INCREMENT TARGET_H8300SX | |
07aae5c2 SC |
737 | |
738 | /* Macros to check register numbers against specific register classes. */ | |
739 | ||
740 | /* These assume that REGNO is a hard or pseudo reg number. | |
741 | They give nonzero only if REGNO is a hard reg of the suitable class | |
742 | or a pseudo reg currently allocated to a suitable hard reg. | |
743 | Since they use reg_renumber, they are safe only once reg_renumber | |
744 | has been allocated, which happens in local-alloc.c. */ | |
07e4d94e | 745 | |
7bc8cb2b | 746 | #define REGNO_OK_FOR_INDEX_P(regno) 0 |
07aae5c2 | 747 | |
d60004ee KH |
748 | #define REGNO_OK_FOR_BASE_P(regno) \ |
749 | (((regno) < FIRST_PSEUDO_REGISTER && regno != MAC_REG) \ | |
750 | || reg_renumber[regno] >= 0) | |
07aae5c2 SC |
751 | \f |
752 | /* Maximum number of registers that can appear in a valid memory address. */ | |
753 | ||
754 | #define MAX_REGS_PER_ADDRESS 1 | |
755 | ||
756 | /* 1 if X is an rtx for a constant that is a valid address. */ | |
757 | ||
1a63219b | 758 | #define CONSTANT_ADDRESS_P(X) \ |
7bc8cb2b DE |
759 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ |
760 | || (GET_CODE (X) == CONST_INT \ | |
761 | /* We handle signed and unsigned offsets here. */ \ | |
762 | && INTVAL (X) > (TARGET_H8300 ? -0x10000 : -0x1000000) \ | |
763 | && INTVAL (X) < (TARGET_H8300 ? 0x10000 : 0x1000000)) \ | |
eb8a8ec4 | 764 | || (GET_CODE (X) == HIGH || GET_CODE (X) == CONST)) |
07aae5c2 SC |
765 | |
766 | /* Nonzero if the constant value X is a legitimate general operand. | |
767 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
768 | ||
d0022200 | 769 | #define LEGITIMATE_CONSTANT_P(X) (h8300_legitimate_constant_p (X)) |
07aae5c2 SC |
770 | |
771 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
772 | and check its validity for a certain class. | |
773 | We have two alternate definitions for each of them. | |
774 | The usual definition accepts all pseudo regs; the other rejects | |
775 | them unless they have been allocated suitable hard regs. | |
776 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
777 | ||
778 | Most source files want to accept pseudo regs in the hope that | |
779 | they will get allocated to the class that the insn wants them to be in. | |
780 | Source files for reload pass need to be strict. | |
781 | After reload, it makes no difference, since pseudo regs have | |
782 | been eliminated by then. */ | |
783 | ||
ca04c5a9 KH |
784 | /* Non-strict versions. */ |
785 | #define REG_OK_FOR_INDEX_NONSTRICT_P(X) 0 | |
786 | /* Don't use REGNO_OK_FOR_BASE_P here because it uses reg_renumber. */ | |
787 | #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ | |
2dca8ddb | 788 | (REGNO (X) >= FIRST_PSEUDO_REGISTER || REGNO (X) != MAC_REG) |
ca04c5a9 KH |
789 | |
790 | /* Strict versions. */ | |
791 | #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
792 | #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
793 | ||
07aae5c2 SC |
794 | #ifndef REG_OK_STRICT |
795 | ||
ca04c5a9 KH |
796 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) |
797 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) | |
07aae5c2 SC |
798 | |
799 | #else | |
800 | ||
ca04c5a9 KH |
801 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) |
802 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) | |
07aae5c2 SC |
803 | |
804 | #endif | |
7bc8cb2b | 805 | |
c59ff527 KH |
806 | /* Extra constraints. */ |
807 | ||
beed8fc0 AO |
808 | #define OK_FOR_Q(OP) \ |
809 | (TARGET_H8300SX && memory_operand ((OP), VOIDmode)) | |
810 | ||
be1e06df KH |
811 | #define OK_FOR_R(OP) \ |
812 | (GET_CODE (OP) == CONST_INT \ | |
813 | ? !h8300_shift_needs_scratch_p (INTVAL (OP), QImode) \ | |
814 | : 0) | |
815 | ||
816 | #define OK_FOR_S(OP) \ | |
817 | (GET_CODE (OP) == CONST_INT \ | |
818 | ? !h8300_shift_needs_scratch_p (INTVAL (OP), HImode) \ | |
819 | : 0) | |
820 | ||
821 | #define OK_FOR_T(OP) \ | |
822 | (GET_CODE (OP) == CONST_INT \ | |
823 | ? !h8300_shift_needs_scratch_p (INTVAL (OP), SImode) \ | |
824 | : 0) | |
825 | ||
0a02170f | 826 | /* 'U' if valid for a bset destination; |
c59ff527 KH |
827 | i.e. a register, register indirect, or the eightbit memory region |
828 | (a SYMBOL_REF with an SYMBOL_REF_FLAG set). | |
c05330a9 | 829 | |
3db11b5c | 830 | On the H8S 'U' can also be a 16bit or 32bit absolute. */ |
cda4bd43 KH |
831 | #define OK_FOR_U(OP) \ |
832 | ((GET_CODE (OP) == REG && REG_OK_FOR_BASE_P (OP)) \ | |
833 | || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \ | |
834 | && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \ | |
835 | || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ | |
9675a91e | 836 | && TARGET_H8300S) \ |
f248423a KH |
837 | || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == CONST \ |
838 | && GET_CODE (XEXP (XEXP (OP, 0), 0)) == PLUS \ | |
839 | && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 0)) == SYMBOL_REF \ | |
840 | && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 1)) == CONST_INT \ | |
920e86b8 KH |
841 | && (TARGET_H8300S \ |
842 | || SYMBOL_REF_FLAG (XEXP (XEXP (XEXP (OP, 0), 0), 0)))) \ | |
9f9f0e4f | 843 | || (GET_CODE (OP) == MEM \ |
7c143ed2 | 844 | && h8300_eightbit_constant_address_p (XEXP (OP, 0))) \ |
cda4bd43 | 845 | || (GET_CODE (OP) == MEM && TARGET_H8300S \ |
e8205901 | 846 | && GET_CODE (XEXP (OP, 0)) == CONST_INT)) |
07e4d94e | 847 | |
beed8fc0 AO |
848 | /* Multi-letter constraints starting with W are to be used for |
849 | operands that require a memory operand, i.e,. that are never used | |
850 | along with register constraints (see EXTRA_MEMORY_CONSTRAINTS). | |
851 | For operands that require a memory operand (or not) but that always | |
852 | accept a register, a multi-letter constraint starting with Y should | |
853 | be used instead. */ | |
854 | ||
855 | #define OK_FOR_WU(OP) \ | |
856 | (GET_CODE (OP) == MEM && OK_FOR_U (OP)) | |
857 | ||
858 | #define OK_FOR_W(OP, STR) \ | |
859 | ((STR)[1] == 'U' ? OK_FOR_WU (OP) \ | |
860 | : 0) | |
861 | ||
862 | #define CONSTRAINT_LEN_FOR_W(STR) \ | |
863 | ((STR)[1] == 'U' ? 2 \ | |
864 | : 0) | |
865 | ||
866 | /* We don't have any constraint starting with Y yet, but before | |
867 | someone uses it for a one-letter constraint and we're left without | |
868 | any upper-case constraints left, we reserve it for extensions | |
869 | here. */ | |
870 | #define OK_FOR_Y(OP, STR) \ | |
871 | (0) | |
872 | ||
873 | #define CONSTRAINT_LEN_FOR_Y(STR) \ | |
874 | (0) | |
875 | ||
876 | #define OK_FOR_Z(OP) \ | |
877 | (TARGET_H8300SX \ | |
878 | && GET_CODE (OP) == MEM \ | |
879 | && CONSTANT_P (XEXP ((OP), 0))) | |
880 | ||
881 | #define EXTRA_CONSTRAINT_STR(OP, C, STR) \ | |
882 | ((C) == 'Q' ? OK_FOR_Q (OP) : \ | |
883 | (C) == 'R' ? OK_FOR_R (OP) : \ | |
be1e06df KH |
884 | (C) == 'S' ? OK_FOR_S (OP) : \ |
885 | (C) == 'T' ? OK_FOR_T (OP) : \ | |
886 | (C) == 'U' ? OK_FOR_U (OP) : \ | |
beed8fc0 AO |
887 | (C) == 'W' ? OK_FOR_W ((OP), (STR)) : \ |
888 | (C) == 'Y' ? OK_FOR_Y ((OP), (STR)) : \ | |
889 | (C) == 'Z' ? OK_FOR_Z (OP) : \ | |
c59ff527 | 890 | 0) |
beed8fc0 AO |
891 | |
892 | #define CONSTRAINT_LEN(C, STR) \ | |
893 | ((C) == 'P' ? CONSTRAINT_LEN_FOR_P (STR) \ | |
894 | : (C) == 'W' ? CONSTRAINT_LEN_FOR_W (STR) \ | |
895 | : (C) == 'Y' ? CONSTRAINT_LEN_FOR_Y (STR) \ | |
896 | : DEFAULT_CONSTRAINT_LEN ((C), (STR))) | |
897 | ||
898 | /* Experiments suggest that it's better not add 'Q' or 'U' here. No | |
899 | patterns need it for correctness (no patterns use 'Q' and 'U' | |
900 | without also providing a register alternative). And defining it | |
901 | will mean that a spilled pseudo could be replaced by its frame | |
902 | location in several consecutive insns. | |
903 | ||
904 | Instead, it seems to be better to force pseudos to be reloaded | |
905 | into registers and then use peepholes to recombine insns when | |
906 | beneficial. | |
907 | ||
908 | Unfortunately, for WU (unlike plain U, that matches regs as well), | |
909 | we must require a memory address. In fact, all multi-letter | |
910 | constraints started with W are supposed to have this property, so | |
911 | we just test for W here. */ | |
912 | #define EXTRA_MEMORY_CONSTRAINT(C, STR) \ | |
913 | ((C) == 'W') | |
914 | ||
07aae5c2 | 915 | \f |
d0022200 KH |
916 | #ifndef REG_OK_STRICT |
917 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
918 | do \ | |
919 | { \ | |
beed8fc0 | 920 | if (h8300_legitimate_address_p ((MODE), (X), 0)) \ |
d0022200 KH |
921 | goto ADDR; \ |
922 | } \ | |
923 | while (0) | |
924 | #else | |
925 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
926 | do \ | |
927 | { \ | |
beed8fc0 | 928 | if (h8300_legitimate_address_p ((MODE), (X), 1)) \ |
d0022200 KH |
929 | goto ADDR; \ |
930 | } \ | |
931 | while (0) | |
932 | #endif | |
07aae5c2 | 933 | \f |
07aae5c2 SC |
934 | /* Go to LABEL if ADDR (a legitimate address expression) |
935 | has an effect that depends on the machine mode it is used for. | |
936 | ||
937 | On the H8/300, the predecrement and postincrement address depend thus | |
18543a22 | 938 | (the amount of decrement or increment being the length of the operand). */ |
07aae5c2 | 939 | |
f48f56b1 | 940 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ |
beed8fc0 AO |
941 | if (GET_CODE (ADDR) == PLUS \ |
942 | && h8300_get_index (XEXP (ADDR, 0), VOIDmode, 0) != XEXP (ADDR, 0)) \ | |
943 | goto LABEL; | |
07aae5c2 SC |
944 | \f |
945 | /* Specify the machine mode that this machine uses | |
946 | for the index in the tablejump instruction. */ | |
7bc8cb2b | 947 | #define CASE_VECTOR_MODE Pmode |
07aae5c2 | 948 | |
07aae5c2 SC |
949 | /* Define this as 1 if `char' should by default be signed; else as 0. |
950 | ||
951 | On the H8/300, sign extension is expensive, so we'll say that chars | |
952 | are unsigned. */ | |
953 | #define DEFAULT_SIGNED_CHAR 0 | |
954 | ||
955 | /* This flag, if defined, says the same insns that convert to a signed fixnum | |
956 | also convert validly to an unsigned one. */ | |
957 | #define FIXUNS_TRUNC_LIKE_FIX_TRUNC | |
958 | ||
959 | /* Max number of bytes we can move from memory to memory | |
960 | in one reasonably fast instruction. */ | |
a1616dd9 | 961 | #define MOVE_MAX (TARGET_H8300H || TARGET_H8300S ? 4 : 2) |
7bc8cb2b | 962 | #define MAX_MOVE_MAX 4 |
07aae5c2 | 963 | |
07aae5c2 SC |
964 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
965 | #define SLOW_BYTE_ACCESS TARGET_SLOWBYTE | |
966 | ||
967 | /* Define if shifts truncate the shift count | |
968 | which implies one can omit a sign-extension or zero-extension | |
969 | of a shift count. */ | |
970 | /* #define SHIFT_COUNT_TRUNCATED */ | |
971 | ||
972 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
973 | is done just by pretending it is already truncated. */ | |
974 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
975 | ||
976 | /* Specify the machine mode that pointers have. | |
977 | After generation of rtl, the compiler makes no further distinction | |
978 | between pointers and any other objects of this machine mode. */ | |
39ba95b5 VK |
979 | #define Pmode \ |
980 | ((TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE ? SImode : HImode) | |
7bc8cb2b DE |
981 | |
982 | /* ANSI C types. | |
46eefac4 | 983 | We use longs for the H8/300H and the H8S because ints can be 16 or 32. |
7bc8cb2b | 984 | GCC requires SIZE_TYPE to be the same size as pointers. */ |
39ba95b5 | 985 | #define SIZE_TYPE \ |
beed8fc0 | 986 | (TARGET_H8300 || TARGET_NORMAL_MODE ? TARGET_INT32 ? "short unsigned int" : "unsigned int" : "long unsigned int") |
39ba95b5 | 987 | #define PTRDIFF_TYPE \ |
beed8fc0 | 988 | (TARGET_H8300 || TARGET_NORMAL_MODE ? TARGET_INT32 ? "short int" : "int" : "long int") |
39ba95b5 VK |
989 | |
990 | #define POINTER_SIZE \ | |
991 | ((TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE ? 32 : 16) | |
07aae5c2 | 992 | |
7bc8cb2b DE |
993 | #define WCHAR_TYPE "short unsigned int" |
994 | #define WCHAR_TYPE_SIZE 16 | |
07aae5c2 SC |
995 | |
996 | /* A function address in a call instruction | |
997 | is a byte address (for indexing purposes) | |
998 | so give the MEM rtx a byte's mode. */ | |
999 | #define FUNCTION_MODE QImode | |
1000 | ||
beed8fc0 AO |
1001 | /* Return the length of JUMP's delay slot insn (0 if it has none). |
1002 | If JUMP is a delayed branch, NEXT_INSN (PREV_INSN (JUMP)) will | |
1003 | be the containing SEQUENCE, not JUMP itself. */ | |
1004 | #define DELAY_SLOT_LENGTH(JUMP) \ | |
1005 | (NEXT_INSN (PREV_INSN (JUMP)) == JUMP ? 0 : 2) | |
1006 | ||
7bc8cb2b DE |
1007 | #define BRANCH_COST 0 |
1008 | ||
07aae5c2 | 1009 | /* Tell final.c how to eliminate redundant test instructions. */ |
7bc8cb2b DE |
1010 | |
1011 | /* Here we define machine-dependent flags and fields in cc_status | |
18543a22 | 1012 | (see `conditions.h'). No extra ones are needed for the h8300. */ |
7bc8cb2b DE |
1013 | |
1014 | /* Store in cc_status the expressions | |
1015 | that the condition codes will describe | |
1016 | after execution of an instruction whose pattern is EXP. | |
1017 | Do not alter them if the instruction would not alter the cc's. */ | |
1018 | ||
f48f56b1 | 1019 | #define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc (EXP, INSN) |
7bc8cb2b | 1020 | |
269c14e1 DE |
1021 | /* The add insns don't set overflow in a usable way. */ |
1022 | #define CC_OVERFLOW_UNUSABLE 01000 | |
f48f56b1 | 1023 | /* The mov,and,or,xor insns don't set carry. That's OK though as the |
269c14e1 DE |
1024 | Z bit is all we need when doing unsigned comparisons on the result of |
1025 | these insns (since they're always with 0). However, conditions.h has | |
1026 | CC_NO_OVERFLOW defined for this purpose. Rename it to something more | |
1027 | understandable. */ | |
1028 | #define CC_NO_CARRY CC_NO_OVERFLOW | |
07aae5c2 SC |
1029 | \f |
1030 | /* Control the assembler format that we output. */ | |
1031 | ||
07aae5c2 SC |
1032 | /* Output to assembler file text saying following lines |
1033 | may contain character constants, extra white space, comments, etc. */ | |
1034 | ||
7bc8cb2b | 1035 | #define ASM_APP_ON "; #APP\n" |
07aae5c2 SC |
1036 | |
1037 | /* Output to assembler file text saying following lines | |
1038 | no longer contain unusual constructs. */ | |
1039 | ||
7bc8cb2b | 1040 | #define ASM_APP_OFF "; #NO_APP\n" |
07aae5c2 | 1041 | |
7bc8cb2b | 1042 | #define FILE_ASM_OP "\t.file\n" |
7bc8cb2b DE |
1043 | |
1044 | /* The assembler op to get a word, 2 bytes for the H8/300, 4 for H8/300H. */ | |
39ba95b5 VK |
1045 | #define ASM_WORD_OP \ |
1046 | (TARGET_H8300 || TARGET_NORMAL_MODE ? "\t.word\t" : "\t.long\t") | |
07aae5c2 | 1047 | |
07aae5c2 SC |
1048 | #define TEXT_SECTION_ASM_OP "\t.section .text" |
1049 | #define DATA_SECTION_ASM_OP "\t.section .data" | |
7bc8cb2b | 1050 | #define BSS_SECTION_ASM_OP "\t.section .bss" |
7bc8cb2b | 1051 | |
07e4d94e | 1052 | #undef DO_GLOBAL_CTORS_BODY |
7bc8cb2b DE |
1053 | #define DO_GLOBAL_CTORS_BODY \ |
1054 | { \ | |
4cd0866d KH |
1055 | extern func_ptr __ctors[]; \ |
1056 | extern func_ptr __ctors_end[]; \ | |
1057 | func_ptr *p; \ | |
c1fe41cb | 1058 | for (p = __ctors_end; p > __ctors; ) \ |
7bc8cb2b | 1059 | { \ |
c1fe41cb | 1060 | (*--p)(); \ |
7bc8cb2b | 1061 | } \ |
07e4d94e | 1062 | } |
7bc8cb2b | 1063 | |
07e4d94e | 1064 | #undef DO_GLOBAL_DTORS_BODY |
2cc07db4 | 1065 | #define DO_GLOBAL_DTORS_BODY \ |
7bc8cb2b | 1066 | { \ |
4cd0866d KH |
1067 | extern func_ptr __dtors[]; \ |
1068 | extern func_ptr __dtors_end[]; \ | |
1069 | func_ptr *p; \ | |
7bc8cb2b DE |
1070 | for (p = __dtors; p < __dtors_end; p++) \ |
1071 | { \ | |
1072 | (*p)(); \ | |
1073 | } \ | |
07e4d94e | 1074 | } |
07aae5c2 SC |
1075 | |
1076 | /* How to refer to registers in assembler output. | |
1077 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
1078 | ||
1079 | #define REGISTER_NAMES \ | |
1807b726 | 1080 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "sp", "mac", "ap", "rap", "fp" } |
3511415d | 1081 | |
8b05263d JL |
1082 | #define ADDITIONAL_REGISTER_NAMES \ |
1083 | { {"er0", 0}, {"er1", 1}, {"er2", 2}, {"er3", 3}, {"er4", 4}, \ | |
1084 | {"er5", 5}, {"er6", 6}, {"er7", 7}, {"r7", 7} } | |
07aae5c2 | 1085 | |
506a61b1 KG |
1086 | /* Globalizing directive for a label. */ |
1087 | #define GLOBAL_ASM_OP "\t.global " | |
07aae5c2 | 1088 | |
7bc8cb2b | 1089 | #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ |
da1775d6 | 1090 | ASM_OUTPUT_LABEL (FILE, NAME) |
07aae5c2 | 1091 | |
9bf7ec4e | 1092 | /* The prefix to add to user-visible assembler symbols. */ |
fa8cc22d | 1093 | |
4e0c8ad2 | 1094 | #define USER_LABEL_PREFIX "_" |
07aae5c2 | 1095 | |
07aae5c2 SC |
1096 | /* This is how to store into the string LABEL |
1097 | the symbol_ref name of an internal numbered label where | |
1098 | PREFIX is the class of label and NUM is the number within the class. | |
cb713a8d | 1099 | This is suitable for output with `assemble_name'. |
07aae5c2 | 1100 | |
4977bab6 ZW |
1101 | N.B.: The h8300.md branch_true and branch_false patterns also know |
1102 | how to generate internal labels. */ | |
07aae5c2 | 1103 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ |
74eda121 | 1104 | sprintf (LABEL, "*.%s%lu", PREFIX, (unsigned long)(NUM)) |
07aae5c2 | 1105 | |
07aae5c2 SC |
1106 | /* This is how to output an insn to push a register on the stack. |
1107 | It need not be very fast code. */ | |
7bc8cb2b DE |
1108 | |
1109 | #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ | |
1110 | fprintf (FILE, "\t%s\t%s\n", h8_push_op, h8_reg_names[REGNO]) | |
07aae5c2 SC |
1111 | |
1112 | /* This is how to output an insn to pop a register from the stack. | |
1113 | It need not be very fast code. */ | |
07aae5c2 | 1114 | |
f48f56b1 | 1115 | #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ |
7bc8cb2b DE |
1116 | fprintf (FILE, "\t%s\t%s\n", h8_pop_op, h8_reg_names[REGNO]) |
1117 | ||
1118 | /* This is how to output an element of a case-vector that is absolute. */ | |
1119 | ||
1120 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
761c70aa | 1121 | fprintf (FILE, "%s.L%d\n", ASM_WORD_OP, VALUE) |
07aae5c2 SC |
1122 | |
1123 | /* This is how to output an element of a case-vector that is relative. */ | |
7bc8cb2b | 1124 | |
33f7f353 | 1125 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
f0ca81d2 | 1126 | fprintf (FILE, "%s.L%d-.L%d\n", ASM_WORD_OP, VALUE, REL) |
07aae5c2 SC |
1127 | |
1128 | /* This is how to output an assembler line | |
1129 | that says to advance the location counter | |
1130 | to a multiple of 2**LOG bytes. */ | |
7bc8cb2b | 1131 | |
f48f56b1 | 1132 | #define ASM_OUTPUT_ALIGN(FILE, LOG) \ |
1a63219b | 1133 | if ((LOG) != 0) \ |
3511415d | 1134 | fprintf (FILE, "\t.align %d\n", (LOG)) |
07aae5c2 | 1135 | |
7bc8cb2b | 1136 | #define ASM_OUTPUT_SKIP(FILE, SIZE) \ |
58e15542 | 1137 | fprintf (FILE, "\t.space %d\n", (int)(SIZE)) |
07aae5c2 SC |
1138 | |
1139 | /* This says how to output an assembler line | |
1140 | to define a global common symbol. */ | |
7bc8cb2b | 1141 | |
1a63219b KH |
1142 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ |
1143 | ( fputs ("\t.comm ", (FILE)), \ | |
1144 | assemble_name ((FILE), (NAME)), \ | |
74eda121 | 1145 | fprintf ((FILE), ",%lu\n", (unsigned long)(SIZE))) |
07aae5c2 | 1146 | |
f4778f92 DE |
1147 | /* This says how to output the assembler to define a global |
1148 | uninitialized but not common symbol. | |
1149 | Try to use asm_output_bss to implement this macro. */ | |
1150 | ||
1a63219b | 1151 | #define ASM_OUTPUT_BSS(FILE, DECL, NAME, SIZE, ROUNDED) \ |
fbbc7519 | 1152 | asm_output_bss ((FILE), (DECL), (NAME), (SIZE), (ROUNDED)) |
f4778f92 | 1153 | |
6cdd2721 DD |
1154 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ |
1155 | asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) | |
1156 | ||
07aae5c2 SC |
1157 | /* This says how to output an assembler line |
1158 | to define a local common symbol. */ | |
7bc8cb2b | 1159 | |
f48f56b1 | 1160 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ |
07aae5c2 SC |
1161 | ( fputs ("\t.lcomm ", (FILE)), \ |
1162 | assemble_name ((FILE), (NAME)), \ | |
58e15542 | 1163 | fprintf ((FILE), ",%d\n", (int)(SIZE))) |
07aae5c2 | 1164 | |
4977bab6 | 1165 | #define ASM_PN_FORMAT "%s___%lu" |
07aae5c2 | 1166 | |
7bc8cb2b | 1167 | /* Print an instruction operand X on file FILE. |
1120a1d3 | 1168 | Look in h8300.c for details. */ |
7bc8cb2b DE |
1169 | |
1170 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ | |
07aae5c2 SC |
1171 | ((CODE) == '#') |
1172 | ||
f48f56b1 | 1173 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) |
07aae5c2 SC |
1174 | |
1175 | /* Print a memory operand whose address is X, on file FILE. | |
18543a22 | 1176 | This uses a function in h8300.c. */ |
07aae5c2 | 1177 | |
7bc8cb2b | 1178 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) |
07aae5c2 | 1179 | |
8b97c5f8 | 1180 | /* H8300 specific pragmas. */ |
c58b209a NB |
1181 | #define REGISTER_TARGET_PRAGMAS() \ |
1182 | do \ | |
1183 | { \ | |
1184 | c_register_pragma (0, "saveall", h8300_pr_saveall); \ | |
1185 | c_register_pragma (0, "interrupt", h8300_pr_interrupt); \ | |
1186 | } \ | |
1120a1d3 | 1187 | while (0) |
07aae5c2 | 1188 | |
1120a1d3 KH |
1189 | #define FINAL_PRESCAN_INSN(insn, operand, nop) \ |
1190 | final_prescan_insn (insn, operand, nop) | |
07aae5c2 | 1191 | |
07aae5c2 | 1192 | #define MOVE_RATIO 3 |
beed8fc0 AO |
1193 | extern int h8300_move_ratio; |
1194 | #undef MOVE_RATIO | |
1195 | #define MOVE_RATIO h8300_move_ratio | |
8b97c5f8 | 1196 | |
981c7dce KH |
1197 | /* Machine-specific symbol_ref flags. */ |
1198 | #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0) | |
1199 | #define SYMBOL_FLAG_EIGHTBIT_DATA (SYMBOL_FLAG_MACH_DEP << 1) | |
1200 | #define SYMBOL_FLAG_TINY_DATA (SYMBOL_FLAG_MACH_DEP << 2) | |
3b1c9927 | 1201 | |
88657302 | 1202 | #endif /* ! GCC_H8300_H */ |