projects / thirdparty / gcc.git / blame
| Commit | Line | Data |
|---|---|---|
| af2728a4 | 1 | ;; AMD Athlon Scheduling |
| af2728a4 | 2 | ;; |
| af2728a4 JL |
3 | ;; The Athlon does contain three pipelined FP units, three integer units and |
| 4 | ;; three address generation units. | |
| 5 | ;; | |
| 6 | ;; The predecode logic is determining boundaries of instructions in the 64 | |
| 7 | ;; byte cache line. So the cache line straddling problem of K6 might be issue | |
| 8 | ;; here as well, but it is not noted in the documentation. | |
| 9 | ;; | |
| 10 | ;; Three DirectPath instructions decoders and only one VectorPath decoder | |
| 11 | ;; is available. They can decode three DirectPath instructions or one VectorPath | |
| 12 | ;; instruction per cycle. | |
| 13 | ;; Decoded macro instructions are then passed to 72 entry instruction control | |
| 14 | ;; unit, that passes | |
| 15 | ;; it to the specialized integer (18 entry) and fp (36 entry) schedulers. | |
| 16 | ;; | |
| 17 | ;; The load/store queue unit is not attached to the schedulers but | |
| 18 | ;; communicates with all the execution units separately instead. | |
| 19 | ||
| 4977bab6 ZW |
20 | (define_attr "athlon_decode" "direct,vector" |
| 21 | (cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,cld,leave") | |
| 22 | (const_string "vector") | |
| 23 | (and (eq_attr "type" "push") | |
| 24 | (match_operand 1 "memory_operand" "")) | |
| 25 | (const_string "vector") | |
| af2728a4 | 26 | (and (eq_attr "type" "fmov") |
| 4977bab6 ZW |
27 | (and (eq_attr "memory" "load,store") |
| 28 | (eq_attr "mode" "XF"))) | |
| 29 | (const_string "vector")] | |
| 30 | (const_string "direct"))) | |
| af2728a4 | 31 | |
| 4977bab6 ZW |
32 | ;; |
| 33 | ;; decode0 decode1 decode2 | |
| 34 | ;; \ | / | |
| 35 | ;; instruction control unit (72 entry scheduler) | |
| 36 | ;; | | | |
| 37 | ;; integer scheduler (18) stack map | |
| 38 | ;; / | | | | \ stack rename | |
| 39 | ;; ieu0 agu0 ieu1 agu1 ieu2 agu2 scheduler | |
| 40 | ;; | agu0 | agu1 agu2 register file | |
| 41 | ;; | \ | | / | | | | |
| 42 | ;; \ /\ | / fadd fmul fstore | |
| 43 | ;; \ / \ | / fadd fmul fstore | |
| 44 | ;; imul load/store (2x) fadd fmul fstore | |
| af2728a4 | 45 | |
| 4977bab6 ZW |
46 | (define_automaton "athlon,athlon_load,athlon_mult,athlon_fp") |
| 47 | (define_cpu_unit "athlon-decode0" "athlon") | |
| 48 | (define_cpu_unit "athlon-decode1" "athlon") | |
| 49 | (define_cpu_unit "athlon-decode2" "athlon") | |
| 50 | (define_cpu_unit "athlon-decodev" "athlon") | |
| 51 | ;; Model the fact that double decoded instruction may take 2 cycles | |
| 52 | ;; to decode when decoder2 and decoder0 in next cycle | |
| 53 | ;; is used (this is needed to allow troughput of 1.5 double decoded | |
| 54 | ;; instructions per cycle). | |
| 55 | ;; | |
| 56 | ;; In order to avoid dependnece between reservation of decoder | |
| 57 | ;; and other units, we model decoder as two stage fully pipelined unit | |
| 58 | ;; and only double decoded instruction may occupy unit in the first cycle. | |
| 59 | ;; With this scheme however two double instructions can be issued cycle0. | |
| 60 | ;; | |
| 61 | ;; Avoid this by using presence set requiring decoder0 to be allocated | |
| 62 | ;; too. Vector decoded instructions then can't be issued when | |
| 63 | ;; modeled as consuming decoder0+decoder1+decoder2. | |
| 64 | ;; We solve that by specialized vector decoder unit and exclusion set. | |
| 65 | (presence_set "athlon-decode2" "athlon-decode0") | |
| 66 | (exclusion_set "athlon-decodev" "athlon-decode0,athlon-decode1,athlon-decode2") | |
| 67 | (define_reservation "athlon-vector" "nothing,athlon-decodev") | |
| 68 | (define_reservation "athlon-direct0" "nothing,athlon-decode0") | |
| 69 | (define_reservation "athlon-direct" "nothing, | |
| 70 | (athlon-decode0 | athlon-decode1 | |
| 71 | | athlon-decode2)") | |
| 72 | ;; Double instructions behaves like two direct instructions. | |
| 73 | (define_reservation "athlon-double" "((athlon-decode2, athlon-decode0) | |
| 74 | | (nothing,(athlon-decode0 + athlon-decode1)) | |
| 75 | | (nothing,(athlon-decode1 + athlon-decode2)))") | |
| af2728a4 | 76 | |
| 4977bab6 ZW |
77 | ;; Agu and ieu unit results in extremly large automatons and |
| 78 | ;; in our approximation they are hardly filled in. Only ieu | |
| 79 | ;; unit can, as issue rate is 3 and agu unit is always used | |
| 80 | ;; first in the insn reservations. Skip the models. | |
| af2728a4 | 81 | |
| 4977bab6 ZW |
82 | ;(define_cpu_unit "athlon-ieu0" "athlon_ieu") |
| 83 | ;(define_cpu_unit "athlon-ieu1" "athlon_ieu") | |
| 84 | ;(define_cpu_unit "athlon-ieu2" "athlon_ieu") | |
| 85 | ;(define_reservation "athlon-ieu" "(athlon-ieu0 | athlon-ieu1 | athlon-ieu2)") | |
| 86 | (define_reservation "athlon-ieu" "nothing") | |
| 87 | (define_cpu_unit "athlon-ieu0" "athlon") | |
| 88 | ;(define_cpu_unit "athlon-agu0" "athlon_agu") | |
| 89 | ;(define_cpu_unit "athlon-agu1" "athlon_agu") | |
| 90 | ;(define_cpu_unit "athlon-agu2" "athlon_agu") | |
| 91 | ;(define_reservation "athlon-agu" "(athlon-agu0 | athlon-agu1 | athlon-agu2)") | |
| 92 | (define_reservation "athlon-agu" "nothing,nothing") | |
| af2728a4 | 93 | |
| 4977bab6 | 94 | (define_cpu_unit "athlon-mult" "athlon_mult") |
| af2728a4 | 95 | |
| 4977bab6 ZW |
96 | (define_cpu_unit "athlon-load0" "athlon_load") |
| 97 | (define_cpu_unit "athlon-load1" "athlon_load") | |
| 98 | (define_reservation "athlon-load" "athlon-agu, | |
| 99 | (athlon-load0 | athlon-load1)") | |
| 100 | (define_reservation "athlon-store" "nothing") | |
| af2728a4 | 101 | |
| 4977bab6 ZW |
102 | ;; The three fp units are fully pipelined with latency of 3 |
| 103 | (define_cpu_unit "athlon-fadd" "athlon_fp") | |
| 104 | (define_cpu_unit "athlon-fmul" "athlon_fp") | |
| 105 | (define_cpu_unit "athlon-fstore" "athlon_fp") | |
| 106 | (define_reservation "athlon-fany" "(athlon-fadd | athlon-fmul | athlon-fstore)") | |
| 107 | (define_reservation "athlon-faddmul" "(athlon-fadd | athlon-fmul)") | |
| af2728a4 | 108 | |
| af2728a4 | 109 | |
| 4977bab6 ZW |
110 | ;; Jump instructions are executed in the branch unit compltetely transparent to us |
| 111 | (define_insn_reservation "athlon_branch" 0 | |
| 112 | (and (eq_attr "cpu" "athlon,k8") | |
| 113 | (eq_attr "type" "ibr")) | |
| 114 | "athlon-direct") | |
| 115 | (define_insn_reservation "athlon_call" 0 | |
| 116 | (and (eq_attr "cpu" "athlon,k8") | |
| 117 | (eq_attr "type" "call,callv")) | |
| 118 | "athlon-vector") | |
| af2728a4 | 119 | |
| 4977bab6 ZW |
120 | ;; Latency of push operation is 3 cycles, but ESP value is available |
| 121 | ;; earlier | |
| 122 | (define_insn_reservation "athlon_push" 2 | |
| 123 | (and (eq_attr "cpu" "athlon,k8") | |
| 124 | (eq_attr "type" "push")) | |
| 125 | "athlon-direct,nothing,athlon-store") | |
| 126 | (define_insn_reservation "athlon_pop" 4 | |
| 127 | (and (eq_attr "cpu" "athlon,k8") | |
| 128 | (eq_attr "type" "pop")) | |
| 129 | "athlon-vector,athlon-ieu,athlon-load") | |
| 130 | (define_insn_reservation "athlon_pop_k8" 3 | |
| 131 | (and (eq_attr "cpu" "k8") | |
| 132 | (eq_attr "type" "pop")) | |
| 133 | "athlon-double,athlon-ieu,athlon-load") | |
| 134 | (define_insn_reservation "athlon_leave" 3 | |
| 135 | (and (eq_attr "cpu" "athlon") | |
| 136 | (eq_attr "type" "leave")) | |
| 137 | "athlon-vector,athlon-load") | |
| 138 | (define_insn_reservation "athlon_leave_k8" 3 | |
| 139 | (and (eq_attr "cpu" "k8") | |
| 140 | (eq_attr "type" "leave")) | |
| 141 | "athlon-double,athlon-load") | |
| af2728a4 | 142 | |
| 4977bab6 ZW |
143 | ;; Lea executes in AGU unit with 2 cycles latency. |
| 144 | (define_insn_reservation "athlon_lea" 2 | |
| 145 | (and (eq_attr "cpu" "athlon,k8") | |
| 146 | (eq_attr "type" "lea")) | |
| 147 | "athlon-direct,athlon-agu") | |
| af2728a4 | 148 | |
| 4977bab6 ZW |
149 | ;; Mul executes in special multiplier unit attached to IEU0 |
| 150 | (define_insn_reservation "athlon_imul" 5 | |
| 151 | (and (eq_attr "cpu" "athlon") | |
| 152 | (and (eq_attr "type" "imul") | |
| 153 | (eq_attr "memory" "none,unknown"))) | |
| 154 | "athlon-vector,athlon-ieu0,athlon-mult,nothing,nothing,athlon-ieu0") | |
| 155 | ;; ??? Widening multiply is vector or double. | |
| 156 | (define_insn_reservation "athlon_imul_k8_DI" 4 | |
| 157 | (and (eq_attr "cpu" "k8") | |
| 158 | (and (eq_attr "type" "imul") | |
| 159 | (and (eq_attr "mode" "DI") | |
| 160 | (eq_attr "memory" "none,unknown")))) | |
| 161 | "athlon-direct0,athlon-ieu0,athlon-mult,nothing,athlon-ieu0") | |
| 162 | (define_insn_reservation "athlon_imul_k8" 3 | |
| 163 | (and (eq_attr "cpu" "k8") | |
| 164 | (and (eq_attr "type" "imul") | |
| 165 | (eq_attr "memory" "none,unknown"))) | |
| 166 | "athlon-direct0,athlon-ieu0,athlon-mult,athlon-ieu0") | |
| 167 | (define_insn_reservation "athlon_imul_mem" 8 | |
| 168 | (and (eq_attr "cpu" "athlon") | |
| 169 | (and (eq_attr "type" "imul") | |
| 170 | (eq_attr "memory" "load,both"))) | |
| 171 | "athlon-vector,athlon-load,athlon-ieu,athlon-mult,nothing,nothing,athlon-ieu") | |
| 172 | (define_insn_reservation "athlon_imul_mem_k8_DI" 7 | |
| 173 | (and (eq_attr "cpu" "k8") | |
| 174 | (and (eq_attr "type" "imul") | |
| 175 | (and (eq_attr "mode" "DI") | |
| 176 | (eq_attr "memory" "load,both")))) | |
| 177 | "athlon-vector,athlon-load,athlon-ieu,athlon-mult,nothing,athlon-ieu") | |
| 178 | (define_insn_reservation "athlon_imul_mem_k8" 6 | |
| 179 | (and (eq_attr "cpu" "k8") | |
| 180 | (and (eq_attr "type" "imul") | |
| 181 | (eq_attr "memory" "load,both"))) | |
| 182 | "athlon-vector,athlon-load,athlon-ieu,athlon-mult,athlon-ieu") | |
| 183 | (define_insn_reservation "athlon_idiv" 42 | |
| 184 | (and (eq_attr "cpu" "athlon,k8") | |
| 185 | (and (eq_attr "type" "idiv") | |
| 186 | (eq_attr "memory" "none,unknown"))) | |
| 187 | "athlon-vector,athlon-ieu*42") | |
| 188 | (define_insn_reservation "athlon_idiv_mem" 45 | |
| 189 | (and (eq_attr "cpu" "athlon,k8") | |
| 190 | (and (eq_attr "type" "idiv") | |
| 191 | (eq_attr "memory" "load,both"))) | |
| 192 | "athlon-vector,athlon-load,athlon-ieu*42") | |
| 193 | (define_insn_reservation "athlon_str" 15 | |
| 194 | (and (eq_attr "cpu" "athlon,k8") | |
| 195 | (and (eq_attr "type" "str") | |
| 196 | (eq_attr "memory" "load,both,store"))) | |
| 197 | "athlon-vector,athlon-load,athlon-ieu*10") | |
| af2728a4 | 198 | |
| 4977bab6 ZW |
199 | (define_insn_reservation "athlon_idirect" 1 |
| 200 | (and (eq_attr "cpu" "athlon,k8") | |
| 201 | (and (eq_attr "athlon_decode" "direct") | |
| 202 | (and (eq_attr "unit" "integer,unknown") | |
| 203 | (eq_attr "memory" "none,unknown")))) | |
| 204 | "athlon-direct,athlon-ieu") | |
| 205 | (define_insn_reservation "athlon_ivector" 2 | |
| 206 | (and (eq_attr "cpu" "athlon,k8") | |
| 207 | (and (eq_attr "athlon_decode" "vector") | |
| 208 | (and (eq_attr "unit" "integer,unknown") | |
| 209 | (eq_attr "memory" "none,unknown")))) | |
| 210 | "athlon-vector,athlon-ieu,athlon-ieu") | |
| 211 | (define_insn_reservation "athlon_idirect_loadmov" 3 | |
| 212 | (and (eq_attr "cpu" "athlon,k8") | |
| 213 | (and (eq_attr "type" "imov") | |
| 214 | (eq_attr "memory" "load"))) | |
| 215 | "athlon-direct,athlon-load") | |
| 216 | (define_insn_reservation "athlon_idirect_load" 4 | |
| 217 | (and (eq_attr "cpu" "athlon,k8") | |
| 218 | (and (eq_attr "athlon_decode" "direct") | |
| 219 | (and (eq_attr "unit" "integer,unknown") | |
| 220 | (eq_attr "memory" "load")))) | |
| 221 | "athlon-direct,athlon-load,athlon-ieu") | |
| 222 | (define_insn_reservation "athlon_ivector_load" 6 | |
| 223 | (and (eq_attr "cpu" "athlon,k8") | |
| 224 | (and (eq_attr "athlon_decode" "vector") | |
| 225 | (and (eq_attr "unit" "integer,unknown") | |
| 226 | (eq_attr "memory" "load")))) | |
| 227 | "athlon-vector,athlon-load,athlon-ieu,athlon-ieu") | |
| 228 | (define_insn_reservation "athlon_idirect_movstore" 1 | |
| 229 | (and (eq_attr "cpu" "athlon,k8") | |
| 230 | (and (eq_attr "type" "imov") | |
| 231 | (eq_attr "memory" "store"))) | |
| 232 | "athlon-direct,athlon-agu,athlon-store") | |
| 233 | (define_insn_reservation "athlon_idirect_both" 4 | |
| 234 | (and (eq_attr "cpu" "athlon,k8") | |
| 235 | (and (eq_attr "athlon_decode" "direct") | |
| 236 | (and (eq_attr "unit" "integer,unknown") | |
| 237 | (eq_attr "memory" "both")))) | |
| 238 | "athlon-direct,athlon-load,athlon-ieu, | |
| 239 | athlon-store") | |
| 240 | (define_insn_reservation "athlon_ivector_both" 6 | |
| 241 | (and (eq_attr "cpu" "athlon,k8") | |
| 242 | (and (eq_attr "athlon_decode" "vector") | |
| 243 | (and (eq_attr "unit" "integer,unknown") | |
| 244 | (eq_attr "memory" "both")))) | |
| 245 | "athlon-vector,athlon-load,athlon-ieu,athlon-ieu, | |
| 246 | athlon-store") | |
| 247 | (define_insn_reservation "athlon_idirect_store" 1 | |
| 248 | (and (eq_attr "cpu" "athlon,k8") | |
| 249 | (and (eq_attr "athlon_decode" "direct") | |
| 250 | (and (eq_attr "unit" "integer,unknown") | |
| 251 | (eq_attr "memory" "store")))) | |
| 252 | "athlon-direct,athlon-ieu, | |
| 253 | athlon-store") | |
| 254 | (define_insn_reservation "athlon_ivector_store" 2 | |
| 255 | (and (eq_attr "cpu" "athlon,k8") | |
| 256 | (and (eq_attr "athlon_decode" "vector") | |
| 257 | (and (eq_attr "unit" "integer,unknown") | |
| 258 | (eq_attr "memory" "store")))) | |
| 259 | "athlon-vector,athlon-ieu,athlon-ieu, | |
| 260 | athlon-store") | |
| af2728a4 | 261 | |
| 4977bab6 ZW |
262 | ;; Athlon floatin point unit |
| 263 | (define_insn_reservation "athlon_fldxf" 12 | |
| 264 | (and (eq_attr "cpu" "athlon") | |
| 265 | (and (eq_attr "type" "fmov") | |
| 266 | (and (eq_attr "memory" "load") | |
| 267 | (eq_attr "mode" "XF")))) | |
| 268 | "athlon-vector,athlon-fany") | |
| 269 | (define_insn_reservation "athlon_fldxf_k8" 13 | |
| 270 | (and (eq_attr "cpu" "k8") | |
| 271 | (and (eq_attr "type" "fmov") | |
| 272 | (and (eq_attr "memory" "load") | |
| 273 | (eq_attr "mode" "XF")))) | |
| 274 | "athlon-vector,athlon-fany") | |
| 275 | (define_insn_reservation "athlon_fld" 6 | |
| 276 | (and (eq_attr "cpu" "athlon") | |
| 277 | (and (eq_attr "type" "fmov") | |
| 278 | (eq_attr "memory" "load"))) | |
| 279 | "athlon-direct,athlon-fany,nothing,athlon-load") | |
| 280 | (define_insn_reservation "athlon_fld_k8" 4 | |
| 281 | (and (eq_attr "cpu" "k8") | |
| 282 | (and (eq_attr "type" "fmov") | |
| 283 | (eq_attr "memory" "load"))) | |
| 284 | "athlon-direct,athlon-fany,athlon-load") | |
| 285 | (define_insn_reservation "athlon_fstxf" 10 | |
| 286 | (and (eq_attr "cpu" "athlon") | |
| 287 | (and (eq_attr "type" "fmov") | |
| 288 | (and (eq_attr "memory" "store,both") | |
| 289 | (eq_attr "mode" "XF")))) | |
| 290 | "athlon-vector,athlon-fstore") | |
| 291 | (define_insn_reservation "athlon_fstxf_k8" 8 | |
| 292 | (and (eq_attr "cpu" "k8") | |
| 293 | (and (eq_attr "type" "fmov") | |
| 294 | (and (eq_attr "memory" "store,both") | |
| 295 | (eq_attr "mode" "XF")))) | |
| 296 | "athlon-vector,athlon-fstore") | |
| 297 | (define_insn_reservation "athlon_fst" 4 | |
| 298 | (and (eq_attr "cpu" "athlon") | |
| 299 | (and (eq_attr "type" "fmov") | |
| 300 | (eq_attr "memory" "store,both"))) | |
| 301 | "athlon-direct,athlon-fstore,nothing,athlon-store") | |
| 302 | (define_insn_reservation "athlon_fst_k8" 2 | |
| 303 | (and (eq_attr "cpu" "k8") | |
| 304 | (and (eq_attr "type" "fmov") | |
| 305 | (eq_attr "memory" "store,both"))) | |
| 306 | "athlon-direct,athlon-fstore,athlon-store") | |
| 307 | (define_insn_reservation "athlon_fist" 4 | |
| 308 | (and (eq_attr "cpu" "athlon,k8") | |
| 309 | (eq_attr "type" "fistp")) | |
| 310 | "athlon-direct,athlon-fstore,nothing") | |
| 311 | (define_insn_reservation "athlon_fmov" 2 | |
| 312 | (and (eq_attr "cpu" "athlon,k8") | |
| 313 | (eq_attr "type" "fmov")) | |
| 314 | "athlon-direct,athlon-faddmul") | |
| 315 | (define_insn_reservation "athlon_fadd_load" 7 | |
| 316 | (and (eq_attr "cpu" "athlon") | |
| 317 | (and (eq_attr "type" "fop") | |
| 318 | (eq_attr "memory" "load"))) | |
| 319 | "athlon-direct,athlon-load,athlon-fadd") | |
| 320 | (define_insn_reservation "athlon_fadd_load_k8" 6 | |
| 321 | (and (eq_attr "cpu" "k8") | |
| 322 | (and (eq_attr "type" "fop") | |
| 323 | (eq_attr "memory" "load"))) | |
| 324 | "athlon-direct,athlon-load,athlon-fadd") | |
| 325 | (define_insn_reservation "athlon_fadd" 4 | |
| 326 | (and (eq_attr "cpu" "athlon,k8") | |
| 327 | (eq_attr "type" "fop")) | |
| 328 | "athlon-direct,athlon-fadd") | |
| 329 | (define_insn_reservation "athlon_fmul_load" 7 | |
| 330 | (and (eq_attr "cpu" "athlon") | |
| 331 | (and (eq_attr "type" "fmul") | |
| 332 | (eq_attr "memory" "load"))) | |
| 333 | "athlon-direct,athlon-load,athlon-fmul") | |
| 334 | (define_insn_reservation "athlon_fmul_load_k8" 6 | |
| 335 | (and (eq_attr "cpu" "k8") | |
| 336 | (and (eq_attr "type" "fmul") | |
| 337 | (eq_attr "memory" "load"))) | |
| 338 | "athlon-direct,athlon-load,athlon-fmul") | |
| 339 | (define_insn_reservation "athlon_fmul" 4 | |
| 340 | (and (eq_attr "cpu" "athlon,k8") | |
| 341 | (eq_attr "type" "fmul")) | |
| 342 | "athlon-direct,athlon-fmul") | |
| 343 | (define_insn_reservation "athlon_fsgn" 2 | |
| 344 | (and (eq_attr "cpu" "athlon,k8") | |
| 345 | (eq_attr "type" "fsgn")) | |
| 346 | "athlon-direct,athlon-fmul") | |
| 347 | (define_insn_reservation "athlon_fdiv_load" 24 | |
| 348 | (and (eq_attr "cpu" "athlon") | |
| 349 | (and (eq_attr "type" "fdiv") | |
| 350 | (eq_attr "memory" "load"))) | |
| 351 | "athlon-direct,athlon-load,athlon-fmul") | |
| 352 | (define_insn_reservation "athlon_fdiv_load_k8" 13 | |
| 353 | (and (eq_attr "cpu" "k8") | |
| 354 | (and (eq_attr "type" "fdiv") | |
| 355 | (eq_attr "memory" "load"))) | |
| 356 | "athlon-direct,athlon-load,athlon-fmul") | |
| 357 | (define_insn_reservation "athlon_fdiv" 24 | |
| 358 | (and (eq_attr "cpu" "athlon") | |
| 359 | (eq_attr "type" "fdiv")) | |
| 360 | "athlon-direct,athlon-fmul") | |
| 361 | (define_insn_reservation "athlon_fdiv_k8" 11 | |
| 362 | (and (eq_attr "cpu" "k8") | |
| 363 | (eq_attr "type" "fdiv")) | |
| 364 | "athlon-direct,athlon-fmul") | |
| 365 | (define_insn_reservation "athlon_fpspc_load" 103 | |
| 366 | (and (eq_attr "cpu" "athlon,k8") | |
| 367 | (and (eq_attr "type" "fpspc") | |
| 368 | (eq_attr "memory" "load"))) | |
| 369 | "athlon-vector,athlon-load,athlon-fmul") | |
| 370 | (define_insn_reservation "athlon_fpspc" 100 | |
| 371 | (and (eq_attr "cpu" "athlon,k8") | |
| 372 | (eq_attr "type" "fpspc")) | |
| 373 | "athlon-vector,athlon-fmul") | |
| 374 | (define_insn_reservation "athlon_fcmov_load" 10 | |
| 375 | (and (eq_attr "cpu" "athlon") | |
| 376 | (and (eq_attr "type" "fcmov") | |
| 377 | (eq_attr "memory" "load"))) | |
| 378 | "athlon-vector,athlon-load,athlon-fmul") | |
| 379 | (define_insn_reservation "athlon_fcmov" 7 | |
| 380 | (and (eq_attr "cpu" "athlon") | |
| 381 | (eq_attr "type" "fcmov")) | |
| 382 | "athlon-vector,athlon-fmul") | |
| 383 | (define_insn_reservation "athlon_fcmov_load_k8" 17 | |
| 384 | (and (eq_attr "cpu" "k8") | |
| 385 | (and (eq_attr "type" "fcmov") | |
| 386 | (eq_attr "memory" "load"))) | |
| 387 | "athlon-vector,athlon-load,athlon-fmul") | |
| 388 | (define_insn_reservation "athlon_fcmov_k8" 15 | |
| 389 | (and (eq_attr "cpu" "k8") | |
| 390 | (eq_attr "type" "fcmov")) | |
| 391 | "athlon-vector,athlon-fmul") | |
| 392 | (define_insn_reservation "athlon_fcomi_load" 6 | |
| 393 | (and (eq_attr "cpu" "athlon") | |
| 394 | (and (eq_attr "type" "fcmp") | |
| 395 | (and (eq_attr "athlon_decode" "vector") | |
| 396 | (eq_attr "memory" "load")))) | |
| 397 | "athlon-vector,athlon-load,athlon-fadd") | |
| 398 | (define_insn_reservation "athlon_fcomi" 3 | |
| 399 | (and (eq_attr "cpu" "athlon,k8") | |
| 400 | (and (eq_attr "athlon_decode" "vector") | |
| 401 | (eq_attr "type" "fcmp"))) | |
| 402 | "athlon-vector,athlon-fadd") | |
| 403 | (define_insn_reservation "athlon_fcom_load" 5 | |
| 404 | (and (eq_attr "cpu" "athlon,k8") | |
| 405 | (and (eq_attr "type" "fcmp") | |
| 406 | (eq_attr "memory" "load"))) | |
| 407 | "athlon-direct,athlon-load,athlon-fadd") | |
| 408 | (define_insn_reservation "athlon_fcom" 2 | |
| 409 | (and (eq_attr "cpu" "athlon,k8") | |
| 410 | (eq_attr "type" "fcmp")) | |
| 411 | "athlon-direct,athlon-fadd") | |
| 412 | (define_insn_reservation "athlon_fxch" 2 | |
| 413 | (and (eq_attr "cpu" "athlon,k8") | |
| 414 | (eq_attr "type" "fxch")) | |
| 415 | "athlon-direct,athlon-fany") | |
| 416 | ;; Athlon handle MMX operations in the FPU unit with shorter latencies | |
| 417 | (define_insn_reservation "athlon_movlpd_load" 4 | |
| 418 | (and (eq_attr "cpu" "athlon,k8") | |
| 419 | (and (eq_attr "type" "ssemov") | |
| 420 | (match_operand:DF 1 "memory_operand" ""))) | |
| 421 | "athlon-direct,athlon-load") | |
| 422 | (define_insn_reservation "athlon_movaps_load" 4 | |
| 423 | (and (eq_attr "cpu" "athlon,k8") | |
| 424 | (and (eq_attr "type" "ssemov") | |
| 425 | (and (eq_attr "mode" "V4SF,V2DF,TI") | |
| 426 | (eq_attr "memory" "load")))) | |
| 427 | "athlon-double,athlon-load") | |
| 428 | (define_insn_reservation "athlon_movss_load" 3 | |
| 429 | (and (eq_attr "cpu" "athlon,k8") | |
| 430 | (and (eq_attr "type" "ssemov") | |
| 431 | (and (eq_attr "mode" "SF,DI") | |
| 432 | (eq_attr "memory" "load")))) | |
| 433 | "athlon-double,athlon-load") | |
| 434 | (define_insn_reservation "athlon_mmxsseld" 4 | |
| 435 | (and (eq_attr "cpu" "athlon,k8") | |
| 436 | (and (eq_attr "type" "mmxmov,ssemov") | |
| 437 | (eq_attr "memory" "load"))) | |
| 438 | "athlon-direct,athlon-fany,athlon-load") | |
| 439 | (define_insn_reservation "athlon_mmxssest" 3 | |
| 440 | (and (eq_attr "cpu" "k8") | |
| 441 | (and (eq_attr "type" "mmxmov,ssemov") | |
| 442 | (and (eq_attr "mode" "V4SF,V2DF,TI") | |
| 443 | (eq_attr "memory" "store,both")))) | |
| 444 | "athlon-double,athlon-store") | |
| 445 | (define_insn_reservation "athlon_mmxssest_k8" 2 | |
| 446 | (and (eq_attr "cpu" "athlon,k8") | |
| 447 | (and (eq_attr "type" "mmxmov,ssemov") | |
| 448 | (eq_attr "memory" "store,both"))) | |
| 449 | "athlon-direct,athlon-store") | |
| 450 | (define_insn_reservation "athlon_movaps" 2 | |
| 451 | (and (eq_attr "cpu" "k8") | |
| 452 | (and (eq_attr "type" "ssemov") | |
| 453 | (eq_attr "mode" "V4SF,V2DF"))) | |
| 454 | "athlon-double,athlon-faddmul,athlon-faddmul") | |
| 455 | (define_insn_reservation "athlon_mmxssemov" 2 | |
| 456 | (and (eq_attr "cpu" "athlon,k8") | |
| 457 | (eq_attr "type" "mmxmov,ssemov")) | |
| 458 | "athlon-direct,athlon-faddmul") | |
| 459 | (define_insn_reservation "athlon_mmxmul_load" 6 | |
| 460 | (and (eq_attr "cpu" "athlon,k8") | |
| 461 | (and (eq_attr "type" "mmxmul") | |
| 462 | (eq_attr "memory" "load"))) | |
| 463 | "athlon-direct,athlon-load,athlon-fmul") | |
| 464 | (define_insn_reservation "athlon_mmxmul" 3 | |
| 465 | (and (eq_attr "cpu" "athlon,k8") | |
| 466 | (eq_attr "type" "mmxmul")) | |
| 467 | "athlon-direct,athlon-fmul") | |
| 468 | (define_insn_reservation "athlon_mmx_load" 5 | |
| 469 | (and (eq_attr "cpu" "athlon,k8") | |
| 470 | (and (eq_attr "unit" "mmx") | |
| 471 | (eq_attr "memory" "load"))) | |
| 472 | "athlon-direct,athlon-load,athlon-faddmul") | |
| 473 | (define_insn_reservation "athlon_mmx" 2 | |
| 474 | (and (eq_attr "cpu" "athlon,k8") | |
| 475 | (eq_attr "unit" "mmx")) | |
| 476 | "athlon-direct,athlon-faddmul") | |
| 477 | ;; SSE operations are handled by the i387 unit as well. The latnecy | |
| 478 | ;; is same as for i387 operations for scalar operations | |
| 479 | (define_insn_reservation "athlon_sselog_load" 6 | |
| 480 | (and (eq_attr "cpu" "athlon") | |
| 481 | (and (eq_attr "type" "sselog") | |
| 482 | (eq_attr "memory" "load"))) | |
| 483 | "athlon-vector,athlon-load,athlon-fmul") | |
| 484 | (define_insn_reservation "athlon_sselog_load_k8" 5 | |
| 485 | (and (eq_attr "cpu" "k8") | |
| 486 | (and (eq_attr "type" "sselog") | |
| 487 | (eq_attr "memory" "load"))) | |
| 488 | "athlon-double,athlon-load,athlon-fmul") | |
| 489 | (define_insn_reservation "athlon_sselog" 3 | |
| 490 | (and (eq_attr "cpu" "athlon") | |
| 491 | (eq_attr "type" "sselog")) | |
| 492 | "athlon-vector,athlon-fmul") | |
| 493 | (define_insn_reservation "athlon_sselog_k8" 3 | |
| 494 | (and (eq_attr "cpu" "k8") | |
| 495 | (eq_attr "type" "sselog")) | |
| 496 | "athlon-double,athlon-fmul") | |
| 497 | (define_insn_reservation "athlon_ssecmp_load" 5 | |
| 498 | (and (eq_attr "cpu" "athlon,k8") | |
| 499 | (and (eq_attr "type" "ssecmp") | |
| 500 | (and (eq_attr "mode" "SF,DF") | |
| 501 | (eq_attr "memory" "load")))) | |
| 502 | "athlon-vector,athlon-load,athlon-fadd") | |
| 503 | (define_insn_reservation "athlon_ssecmp" 2 | |
| 504 | (and (eq_attr "cpu" "athlon,k8") | |
| 505 | (and (eq_attr "type" "ssecmp") | |
| 506 | (eq_attr "mode" "SF,DF"))) | |
| 507 | "athlon-direct,athlon-fadd") | |
| 508 | (define_insn_reservation "athlon_ssecmpvector_load" 6 | |
| 509 | (and (eq_attr "cpu" "athlon") | |
| 510 | (and (eq_attr "type" "ssecmp") | |
| 511 | (eq_attr "memory" "load"))) | |
| 512 | "athlon-vector,athlon-fadd") | |
| 513 | (define_insn_reservation "athlon_ssecmpvector_load_k8" 5 | |
| 514 | (and (eq_attr "cpu" "k8") | |
| 515 | (and (eq_attr "type" "ssecmp") | |
| 516 | (eq_attr "memory" "load"))) | |
| 517 | "athlon-double,athlon-fadd") | |
| 518 | (define_insn_reservation "athlon_ssecmpvector" 3 | |
| 519 | (and (eq_attr "cpu" "athlon") | |
| 520 | (eq_attr "type" "ssecmp")) | |
| 521 | "athlon-vector,athlon-fadd") | |
| 522 | (define_insn_reservation "athlon_ssecmpvector_k8" 3 | |
| 523 | (and (eq_attr "cpu" "k8") | |
| 524 | (eq_attr "type" "ssecmp")) | |
| 525 | "athlon-double,athlon-fadd") | |
| 526 | (define_insn_reservation "athlon_sseadd_load" 7 | |
| 527 | (and (eq_attr "cpu" "athlon") | |
| 528 | (and (eq_attr "type" "sseadd") | |
| 529 | (and (eq_attr "mode" "SF,DF") | |
| 530 | (eq_attr "memory" "load")))) | |
| 531 | "athlon-direct,athlon-load,athlon-fadd") | |
| 532 | (define_insn_reservation "athlon_sseadd_load_k8" 6 | |
| 533 | (and (eq_attr "cpu" "k8") | |
| 534 | (and (eq_attr "type" "sseadd") | |
| 535 | (and (eq_attr "mode" "SF,DF") | |
| 536 | (eq_attr "memory" "load")))) | |
| 537 | "athlon-direct,athlon-load,athlon-fadd") | |
| 538 | (define_insn_reservation "athlon_sseadd" 4 | |
| 539 | (and (eq_attr "cpu" "athlon,k8") | |
| 540 | (and (eq_attr "type" "sseadd") | |
| 541 | (eq_attr "mode" "SF,DF"))) | |
| 542 | "athlon-direct,athlon-fadd") | |
| 543 | (define_insn_reservation "athlon_sseaddvector_load" 8 | |
| 544 | (and (eq_attr "cpu" "athlon") | |
| 545 | (and (eq_attr "type" "sseadd") | |
| 546 | (eq_attr "memory" "load"))) | |
| 547 | "athlon-vector,athlon-load,athlon-fadd") | |
| 548 | (define_insn_reservation "athlon_sseaddvector_load_k8" 7 | |
| 549 | (and (eq_attr "cpu" "k8") | |
| 550 | (and (eq_attr "type" "sseadd") | |
| 551 | (eq_attr "memory" "load"))) | |
| 552 | "athlon-vector,athlon-load,athlon-fadd") | |
| 553 | (define_insn_reservation "athlon_sseaddvector" 5 | |
| 554 | (and (eq_attr "cpu" "athlon") | |
| 555 | (eq_attr "type" "sseadd")) | |
| 556 | "athlon-vector,athlon-fadd") | |
| 557 | (define_insn_reservation "athlon_sseaddvector_k8" 4 | |
| 558 | (and (eq_attr "cpu" "k8") | |
| 559 | (eq_attr "type" "sseadd")) | |
| 560 | "athlon-vector,athlon-fadd") | |
| 561 | (define_insn_reservation "athlon_ssecvt_load" 5 | |
| 562 | (and (eq_attr "cpu" "athlon") | |
| 563 | (and (eq_attr "type" "ssecvt") | |
| 564 | (and (eq_attr "mode" "SF,DF") | |
| 565 | (eq_attr "memory" "load")))) | |
| 566 | "athlon-direct,athlon-load,athlon-fadd") | |
| 567 | (define_insn_reservation "athlon_ssecvt_load_k8" 4 | |
| 568 | (and (eq_attr "cpu" "k8") | |
| 569 | (and (eq_attr "type" "ssecvt") | |
| 570 | (and (eq_attr "mode" "SF,DF") | |
| 571 | (eq_attr "memory" "load")))) | |
| 572 | "athlon-direct,athlon-load,athlon-fadd") | |
| 573 | (define_insn_reservation "athlon_ssecvt" 2 | |
| 574 | (and (eq_attr "cpu" "athlon,k8") | |
| 575 | (and (eq_attr "type" "ssecvt") | |
| 576 | (eq_attr "mode" "SF,DF"))) | |
| 577 | "athlon-direct,athlon-fadd") | |
| 578 | (define_insn_reservation "athlon_ssecvtvector_load" 6 | |
| 579 | (and (eq_attr "cpu" "athlon") | |
| 580 | (and (eq_attr "type" "ssecvt") | |
| 581 | (eq_attr "memory" "load"))) | |
| 582 | "athlon-vector,athlon-load,athlon-fadd") | |
| 583 | (define_insn_reservation "athlon_ssecvtvector_load_k8" 5 | |
| 584 | (and (eq_attr "cpu" "k8") | |
| 585 | (and (eq_attr "type" "ssecvt") | |
| 586 | (eq_attr "memory" "load"))) | |
| 587 | "athlon-vector,athlon-load,athlon-fadd") | |
| 588 | (define_insn_reservation "athlon_ssecvtvector" 5 | |
| 589 | (and (eq_attr "cpu" "athlon") | |
| 590 | (eq_attr "type" "ssecvt")) | |
| 591 | "athlon-vector,athlon-fadd") | |
| 592 | (define_insn_reservation "athlon_ssecvtvector_k8" 3 | |
| 593 | (and (eq_attr "cpu" "k8") | |
| 594 | (eq_attr "type" "ssecvt")) | |
| 595 | "athlon-vector,athlon-fadd") | |
| 596 | (define_insn_reservation "athlon_ssemul_load" 7 | |
| 597 | (and (eq_attr "cpu" "athlon") | |
| 598 | (and (eq_attr "type" "ssemul") | |
| 599 | (and (eq_attr "mode" "SF,DF") | |
| 600 | (eq_attr "memory" "load")))) | |
| 601 | "athlon-direct,athlon-load,athlon-fmul") | |
| 602 | (define_insn_reservation "athlon_ssemul_load_k8" 6 | |
| 603 | (and (eq_attr "cpu" "k8") | |
| 604 | (and (eq_attr "type" "ssemul") | |
| 605 | (and (eq_attr "mode" "SF,DF") | |
| 606 | (eq_attr "memory" "load")))) | |
| 607 | "athlon-direct,athlon-load,athlon-fmul") | |
| 608 | (define_insn_reservation "athlon_ssemul" 4 | |
| 609 | (and (eq_attr "cpu" "athlon,k8") | |
| 610 | (and (eq_attr "type" "ssemul") | |
| 611 | (eq_attr "mode" "SF,DF"))) | |
| 612 | "athlon-direct,athlon-fmul") | |
| 613 | (define_insn_reservation "athlon_ssemulvector_load" 8 | |
| 614 | (and (eq_attr "cpu" "athlon") | |
| 615 | (and (eq_attr "type" "ssemul") | |
| 616 | (eq_attr "memory" "load"))) | |
| 617 | "athlon-vector,athlon-load,athlon-fmul") | |
| 618 | (define_insn_reservation "athlon_ssemulvector_load_k8" 7 | |
| 619 | (and (eq_attr "cpu" "k8") | |
| 620 | (and (eq_attr "type" "ssemul") | |
| 621 | (eq_attr "memory" "load"))) | |
| 622 | "athlon-double,athlon-load,athlon-fmul") | |
| 623 | (define_insn_reservation "athlon_ssemulvector" 5 | |
| 624 | (and (eq_attr "cpu" "athlon") | |
| 625 | (eq_attr "type" "ssemul")) | |
| 626 | "athlon-vector,athlon-fmul") | |
| 627 | (define_insn_reservation "athlon_ssemulvector_k8" 5 | |
| 628 | (and (eq_attr "cpu" "k8") | |
| 629 | (eq_attr "type" "ssemul")) | |
| 630 | "athlon-double,athlon-fmul") | |
| 631 | (define_insn_reservation "athlon_ssediv_load" 19 | |
| 632 | (and (eq_attr "cpu" "athlon") | |
| 633 | (and (eq_attr "type" "ssediv") | |
| 634 | (and (eq_attr "mode" "SF,DF") | |
| 635 | (eq_attr "memory" "load")))) | |
| 636 | "athlon-direct,athlon-load,athlon-fmul") | |
| 637 | (define_insn_reservation "athlon_ssediv_load_k8" 18 | |
| 638 | (and (eq_attr "cpu" "k8") | |
| 639 | (and (eq_attr "type" "ssediv") | |
| 640 | (and (eq_attr "mode" "SF,DF") | |
| 641 | (eq_attr "memory" "load")))) | |
| 642 | "athlon-direct,athlon-load,athlon-fmul") | |
| 643 | (define_insn_reservation "athlon_ssediv" 16 | |
| 644 | (and (eq_attr "cpu" "athlon,k8") | |
| 645 | (and (eq_attr "type" "ssediv") | |
| 646 | (eq_attr "mode" "SF,DF"))) | |
| 647 | "athlon-direct,athlon-fmul") | |
| 648 | (define_insn_reservation "athlon_ssedivvector_load" 32 | |
| 649 | (and (eq_attr "cpu" "athlon") | |
| 650 | (and (eq_attr "type" "ssediv") | |
| 651 | (eq_attr "memory" "load"))) | |
| 652 | "athlon-vector,athlon-load,athlon-fmul") | |
| 653 | (define_insn_reservation "athlon_ssedivvector_load_k8" 35 | |
| 654 | (and (eq_attr "cpu" "k8") | |
| 655 | (and (eq_attr "type" "ssediv") | |
| 656 | (eq_attr "memory" "load"))) | |
| 657 | "athlon-vector,athlon-load,athlon-fmul") | |
| 658 | (define_insn_reservation "athlon_ssedivvector" 29 | |
| 659 | (and (eq_attr "cpu" "athlon") | |
| 660 | (eq_attr "type" "ssediv")) | |
| 661 | "athlon-vector,athlon-fmul") | |
| 662 | (define_insn_reservation "athlon_ssedivvector_k8" 33 | |
| 663 | (and (eq_attr "cpu" "k8") | |
| 664 | (eq_attr "type" "ssediv")) | |
| 665 | "athlon-vector,athlon-fmul") |