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fbd26352 1;; Copyright (C) 2002-2019 Free Software Foundation, Inc.
7dfbd804 2;;
3;; This file is part of GCC.
4;;
5;; GCC is free software; you can redistribute it and/or modify
6;; it under the terms of the GNU General Public License as published by
7;; the Free Software Foundation; either version 3, or (at your option)
8;; any later version.
9;;
10;; GCC is distributed in the hope that it will be useful,
11;; but WITHOUT ANY WARRANTY; without even the implied warranty of
12;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13;; GNU General Public License for more details.
14;;
15;; You should have received a copy of the GNU General Public License
16;; along with GCC; see the file COPYING3. If not see
17;; <http://www.gnu.org/licenses/>.
18;;
9a999200 19;; AMD Athlon Scheduling
9a999200 20;;
9a999200 21;; The Athlon does contain three pipelined FP units, three integer units and
009b318f 22;; three address generation units.
9a999200 23;;
24;; The predecode logic is determining boundaries of instructions in the 64
25;; byte cache line. So the cache line straddling problem of K6 might be issue
26;; here as well, but it is not noted in the documentation.
27;;
28;; Three DirectPath instructions decoders and only one VectorPath decoder
29;; is available. They can decode three DirectPath instructions or one VectorPath
30;; instruction per cycle.
31;; Decoded macro instructions are then passed to 72 entry instruction control
32;; unit, that passes
33;; it to the specialized integer (18 entry) and fp (36 entry) schedulers.
34;;
35;; The load/store queue unit is not attached to the schedulers but
36;; communicates with all the execution units separately instead.
37
aadef98c 38(define_attr "athlon_decode" "direct,vector,double"
69858f81 39 (cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,leave")
805e22b2 40 (const_string "vector")
41 (and (eq_attr "type" "push")
abd4f58b 42 (match_operand 1 "memory_operand"))
805e22b2 43 (const_string "vector")
9a999200 44 (and (eq_attr "type" "fmov")
805e22b2 45 (and (eq_attr "memory" "load,store")
46 (eq_attr "mode" "XF")))
47 (const_string "vector")]
48 (const_string "direct")))
9a999200 49
3d775f8e 50(define_attr "amdfam10_decode" "direct,vector,double"
51 (const_string "direct"))
805e22b2 52;;
53;; decode0 decode1 decode2
54;; \ | /
55;; instruction control unit (72 entry scheduler)
56;; | |
57;; integer scheduler (18) stack map
58;; / | | | | \ stack rename
59;; ieu0 agu0 ieu1 agu1 ieu2 agu2 scheduler
60;; | agu0 | agu1 agu2 register file
61;; | \ | | / | | |
62;; \ /\ | / fadd fmul fstore
63;; \ / \ | / fadd fmul fstore
64;; imul load/store (2x) fadd fmul fstore
9a999200 65
805e22b2 66(define_automaton "athlon,athlon_load,athlon_mult,athlon_fp")
67(define_cpu_unit "athlon-decode0" "athlon")
68(define_cpu_unit "athlon-decode1" "athlon")
69(define_cpu_unit "athlon-decode2" "athlon")
70(define_cpu_unit "athlon-decodev" "athlon")
71;; Model the fact that double decoded instruction may take 2 cycles
72;; to decode when decoder2 and decoder0 in next cycle
73;; is used (this is needed to allow troughput of 1.5 double decoded
74;; instructions per cycle).
75;;
fcbfedc7 76;; In order to avoid dependence between reservation of decoder
805e22b2 77;; and other units, we model decoder as two stage fully pipelined unit
78;; and only double decoded instruction may occupy unit in the first cycle.
79;; With this scheme however two double instructions can be issued cycle0.
80;;
81;; Avoid this by using presence set requiring decoder0 to be allocated
82;; too. Vector decoded instructions then can't be issued when
83;; modeled as consuming decoder0+decoder1+decoder2.
84;; We solve that by specialized vector decoder unit and exclusion set.
85(presence_set "athlon-decode2" "athlon-decode0")
86(exclusion_set "athlon-decodev" "athlon-decode0,athlon-decode1,athlon-decode2")
87(define_reservation "athlon-vector" "nothing,athlon-decodev")
88(define_reservation "athlon-direct0" "nothing,athlon-decode0")
89(define_reservation "athlon-direct" "nothing,
90 (athlon-decode0 | athlon-decode1
91 | athlon-decode2)")
92;; Double instructions behaves like two direct instructions.
93(define_reservation "athlon-double" "((athlon-decode2, athlon-decode0)
94 | (nothing,(athlon-decode0 + athlon-decode1))
95 | (nothing,(athlon-decode1 + athlon-decode2)))")
9a999200 96
fcbfedc7 97;; Agu and ieu unit results in extremely large automatons and
805e22b2 98;; in our approximation they are hardly filled in. Only ieu
99;; unit can, as issue rate is 3 and agu unit is always used
100;; first in the insn reservations. Skip the models.
9a999200 101
805e22b2 102;(define_cpu_unit "athlon-ieu0" "athlon_ieu")
103;(define_cpu_unit "athlon-ieu1" "athlon_ieu")
104;(define_cpu_unit "athlon-ieu2" "athlon_ieu")
105;(define_reservation "athlon-ieu" "(athlon-ieu0 | athlon-ieu1 | athlon-ieu2)")
106(define_reservation "athlon-ieu" "nothing")
107(define_cpu_unit "athlon-ieu0" "athlon")
108;(define_cpu_unit "athlon-agu0" "athlon_agu")
109;(define_cpu_unit "athlon-agu1" "athlon_agu")
110;(define_cpu_unit "athlon-agu2" "athlon_agu")
111;(define_reservation "athlon-agu" "(athlon-agu0 | athlon-agu1 | athlon-agu2)")
5e69cae4 112(define_reservation "athlon-agu" "nothing")
9a999200 113
805e22b2 114(define_cpu_unit "athlon-mult" "athlon_mult")
9a999200 115
805e22b2 116(define_cpu_unit "athlon-load0" "athlon_load")
117(define_cpu_unit "athlon-load1" "athlon_load")
118(define_reservation "athlon-load" "athlon-agu,
5e69cae4 119 (athlon-load0 | athlon-load1),nothing")
120;; 128bit SSE instructions issue two loads at once
121(define_reservation "athlon-load2" "athlon-agu,
122 (athlon-load0 + athlon-load1),nothing")
123
124(define_reservation "athlon-store" "(athlon-load0 | athlon-load1)")
125;; 128bit SSE instructions issue two stores at once
126(define_reservation "athlon-store2" "(athlon-load0 + athlon-load1)")
127
128
129;; The FP operations start to execute at stage 12 in the pipeline, while
130;; integer operations start to execute at stage 9 for Athlon and 11 for K8
131;; Compensate the difference for Athlon because it results in significantly
132;; smaller automata.
133(define_reservation "athlon-fpsched" "nothing,nothing,nothing")
134;; The floating point loads.
135(define_reservation "athlon-fpload" "(athlon-fpsched + athlon-load)")
136(define_reservation "athlon-fpload2" "(athlon-fpsched + athlon-load2)")
137(define_reservation "athlon-fploadk8" "(athlon-fpsched + athlon-load)")
138(define_reservation "athlon-fpload2k8" "(athlon-fpsched + athlon-load2)")
139
9a999200 140
805e22b2 141;; The three fp units are fully pipelined with latency of 3
142(define_cpu_unit "athlon-fadd" "athlon_fp")
143(define_cpu_unit "athlon-fmul" "athlon_fp")
144(define_cpu_unit "athlon-fstore" "athlon_fp")
5e69cae4 145(define_reservation "athlon-fany" "(athlon-fstore | athlon-fmul | athlon-fadd)")
9db3d688 146(define_reservation "athlon-faddmul" "(athlon-fadd | athlon-fmul)")
5e69cae4 147
148;; Vector operations usually consume many of pipes.
149(define_reservation "athlon-fvector" "(athlon-fadd + athlon-fmul + athlon-fstore)")
9a999200 150
9a999200 151
fcbfedc7 152;; Jump instructions are executed in the branch unit completely transparent to us
805e22b2 153(define_insn_reservation "athlon_branch" 0
ec970ca7 154 (and (eq_attr "cpu" "athlon,k8,amdfam10")
805e22b2 155 (eq_attr "type" "ibr"))
5e69cae4 156 "athlon-direct,athlon-ieu")
805e22b2 157(define_insn_reservation "athlon_call" 0
ec970ca7 158 (and (eq_attr "cpu" "athlon,k8")
805e22b2 159 (eq_attr "type" "call,callv"))
5e69cae4 160 "athlon-vector,athlon-ieu")
3d775f8e 161(define_insn_reservation "athlon_call_amdfam10" 0
162 (and (eq_attr "cpu" "amdfam10")
163 (eq_attr "type" "call,callv"))
164 "athlon-double,athlon-ieu")
9a999200 165
805e22b2 166;; Latency of push operation is 3 cycles, but ESP value is available
167;; earlier
168(define_insn_reservation "athlon_push" 2
ec970ca7 169 (and (eq_attr "cpu" "athlon,k8,amdfam10")
805e22b2 170 (eq_attr "type" "push"))
5e69cae4 171 "athlon-direct,athlon-agu,athlon-store")
805e22b2 172(define_insn_reservation "athlon_pop" 4
ec970ca7 173 (and (eq_attr "cpu" "athlon,k8")
805e22b2 174 (eq_attr "type" "pop"))
5e69cae4 175 "athlon-vector,athlon-load,athlon-ieu")
805e22b2 176(define_insn_reservation "athlon_pop_k8" 3
ec970ca7 177 (and (eq_attr "cpu" "k8")
805e22b2 178 (eq_attr "type" "pop"))
5e69cae4 179 "athlon-double,(athlon-ieu+athlon-load)")
3d775f8e 180(define_insn_reservation "athlon_pop_amdfam10" 3
181 (and (eq_attr "cpu" "amdfam10")
182 (eq_attr "type" "pop"))
183 "athlon-direct,(athlon-ieu+athlon-load)")
805e22b2 184(define_insn_reservation "athlon_leave" 3
185 (and (eq_attr "cpu" "athlon")
186 (eq_attr "type" "leave"))
5e69cae4 187 "athlon-vector,(athlon-ieu+athlon-load)")
805e22b2 188(define_insn_reservation "athlon_leave_k8" 3
ec970ca7 189 (and (eq_attr "cpu" "k8,amdfam10")
805e22b2 190 (eq_attr "type" "leave"))
5e69cae4 191 "athlon-double,(athlon-ieu+athlon-load)")
9a999200 192
805e22b2 193;; Lea executes in AGU unit with 2 cycles latency.
194(define_insn_reservation "athlon_lea" 2
ec970ca7 195 (and (eq_attr "cpu" "athlon,k8")
805e22b2 196 (eq_attr "type" "lea"))
5e69cae4 197 "athlon-direct,athlon-agu,nothing")
3d775f8e 198;; Lea executes in AGU unit with 1 cycle latency on AMDFAM10
199(define_insn_reservation "athlon_lea_amdfam10" 1
200 (and (eq_attr "cpu" "amdfam10")
201 (eq_attr "type" "lea"))
202 "athlon-direct,athlon-agu,nothing")
9a999200 203
805e22b2 204;; Mul executes in special multiplier unit attached to IEU0
205(define_insn_reservation "athlon_imul" 5
206 (and (eq_attr "cpu" "athlon")
207 (and (eq_attr "type" "imul")
208 (eq_attr "memory" "none,unknown")))
209 "athlon-vector,athlon-ieu0,athlon-mult,nothing,nothing,athlon-ieu0")
210;; ??? Widening multiply is vector or double.
211(define_insn_reservation "athlon_imul_k8_DI" 4
ec970ca7 212 (and (eq_attr "cpu" "k8,amdfam10")
805e22b2 213 (and (eq_attr "type" "imul")
214 (and (eq_attr "mode" "DI")
215 (eq_attr "memory" "none,unknown"))))
216 "athlon-direct0,athlon-ieu0,athlon-mult,nothing,athlon-ieu0")
217(define_insn_reservation "athlon_imul_k8" 3
ec970ca7 218 (and (eq_attr "cpu" "k8,amdfam10")
805e22b2 219 (and (eq_attr "type" "imul")
220 (eq_attr "memory" "none,unknown")))
221 "athlon-direct0,athlon-ieu0,athlon-mult,athlon-ieu0")
3d775f8e 222(define_insn_reservation "athlon_imul_amdfam10_HI" 4
223 (and (eq_attr "cpu" "amdfam10")
224 (and (eq_attr "type" "imul")
225 (and (eq_attr "mode" "HI")
226 (eq_attr "memory" "none,unknown"))))
009b318f 227 "athlon-vector,athlon-ieu0,athlon-mult,nothing,athlon-ieu0")
805e22b2 228(define_insn_reservation "athlon_imul_mem" 8
229 (and (eq_attr "cpu" "athlon")
230 (and (eq_attr "type" "imul")
231 (eq_attr "memory" "load,both")))
232 "athlon-vector,athlon-load,athlon-ieu,athlon-mult,nothing,nothing,athlon-ieu")
233(define_insn_reservation "athlon_imul_mem_k8_DI" 7
ec970ca7 234 (and (eq_attr "cpu" "k8,amdfam10")
805e22b2 235 (and (eq_attr "type" "imul")
236 (and (eq_attr "mode" "DI")
237 (eq_attr "memory" "load,both"))))
238 "athlon-vector,athlon-load,athlon-ieu,athlon-mult,nothing,athlon-ieu")
239(define_insn_reservation "athlon_imul_mem_k8" 6
ec970ca7 240 (and (eq_attr "cpu" "k8,amdfam10")
805e22b2 241 (and (eq_attr "type" "imul")
242 (eq_attr "memory" "load,both")))
243 "athlon-vector,athlon-load,athlon-ieu,athlon-mult,athlon-ieu")
5e69cae4 244
33f88b1c 245;; Idiv cannot execute in parallel with other instructions. Dealing with it
5e69cae4 246;; as with short latency vector instruction is good approximation avoiding
247;; scheduler from trying too hard to can hide it's latency by overlap with
248;; other instructions.
249;; ??? Experiments show that the idiv can overlap with roughly 6 cycles
250;; of the other code
3d775f8e 251;; Using the same heuristics for amdfam10 as K8 with idiv
5e69cae4 252
253(define_insn_reservation "athlon_idiv" 6
ec970ca7 254 (and (eq_attr "cpu" "athlon,k8,amdfam10")
805e22b2 255 (and (eq_attr "type" "idiv")
256 (eq_attr "memory" "none,unknown")))
5e69cae4 257 "athlon-vector,(athlon-ieu0*6+(athlon-fpsched,athlon-fvector))")
258(define_insn_reservation "athlon_idiv_mem" 9
ec970ca7 259 (and (eq_attr "cpu" "athlon,k8,amdfam10")
805e22b2 260 (and (eq_attr "type" "idiv")
261 (eq_attr "memory" "load,both")))
5e69cae4 262 "athlon-vector,((athlon-load,athlon-ieu0*6)+(athlon-fpsched,athlon-fvector))")
efee20da 263;; The parallelism of string instructions is not documented. Model it same way
5e69cae4 264;; as idiv to create smaller automata. This probably does not matter much.
3d775f8e 265;; Using the same heuristics for amdfam10 as K8 with idiv
5e69cae4 266(define_insn_reservation "athlon_str" 6
ec970ca7 267 (and (eq_attr "cpu" "athlon,k8,amdfam10")
805e22b2 268 (and (eq_attr "type" "str")
269 (eq_attr "memory" "load,both,store")))
5e69cae4 270 "athlon-vector,athlon-load,athlon-ieu0*6")
9a999200 271
805e22b2 272(define_insn_reservation "athlon_idirect" 1
ec970ca7 273 (and (eq_attr "cpu" "athlon,k8")
805e22b2 274 (and (eq_attr "athlon_decode" "direct")
275 (and (eq_attr "unit" "integer,unknown")
276 (eq_attr "memory" "none,unknown"))))
277 "athlon-direct,athlon-ieu")
3d775f8e 278(define_insn_reservation "athlon_idirect_amdfam10" 1
279 (and (eq_attr "cpu" "amdfam10")
280 (and (eq_attr "amdfam10_decode" "direct")
281 (and (eq_attr "unit" "integer,unknown")
282 (eq_attr "memory" "none,unknown"))))
283 "athlon-direct,athlon-ieu")
805e22b2 284(define_insn_reservation "athlon_ivector" 2
ec970ca7 285 (and (eq_attr "cpu" "athlon,k8")
805e22b2 286 (and (eq_attr "athlon_decode" "vector")
287 (and (eq_attr "unit" "integer,unknown")
288 (eq_attr "memory" "none,unknown"))))
289 "athlon-vector,athlon-ieu,athlon-ieu")
3d775f8e 290(define_insn_reservation "athlon_ivector_amdfam10" 2
291 (and (eq_attr "cpu" "amdfam10")
292 (and (eq_attr "amdfam10_decode" "vector")
293 (and (eq_attr "unit" "integer,unknown")
294 (eq_attr "memory" "none,unknown"))))
295 "athlon-vector,athlon-ieu,athlon-ieu")
296
805e22b2 297(define_insn_reservation "athlon_idirect_loadmov" 3
ec970ca7 298 (and (eq_attr "cpu" "athlon,k8,amdfam10")
805e22b2 299 (and (eq_attr "type" "imov")
300 (eq_attr "memory" "load")))
301 "athlon-direct,athlon-load")
3d775f8e 302
805e22b2 303(define_insn_reservation "athlon_idirect_load" 4
ec970ca7 304 (and (eq_attr "cpu" "athlon,k8")
805e22b2 305 (and (eq_attr "athlon_decode" "direct")
306 (and (eq_attr "unit" "integer,unknown")
307 (eq_attr "memory" "load"))))
308 "athlon-direct,athlon-load,athlon-ieu")
3d775f8e 309(define_insn_reservation "athlon_idirect_load_amdfam10" 4
310 (and (eq_attr "cpu" "amdfam10")
311 (and (eq_attr "amdfam10_decode" "direct")
312 (and (eq_attr "unit" "integer,unknown")
313 (eq_attr "memory" "load"))))
314 "athlon-direct,athlon-load,athlon-ieu")
805e22b2 315(define_insn_reservation "athlon_ivector_load" 6
ec970ca7 316 (and (eq_attr "cpu" "athlon,k8")
805e22b2 317 (and (eq_attr "athlon_decode" "vector")
318 (and (eq_attr "unit" "integer,unknown")
319 (eq_attr "memory" "load"))))
320 "athlon-vector,athlon-load,athlon-ieu,athlon-ieu")
3d775f8e 321(define_insn_reservation "athlon_ivector_load_amdfam10" 6
322 (and (eq_attr "cpu" "amdfam10")
323 (and (eq_attr "amdfam10_decode" "vector")
324 (and (eq_attr "unit" "integer,unknown")
325 (eq_attr "memory" "load"))))
326 "athlon-vector,athlon-load,athlon-ieu,athlon-ieu")
327
805e22b2 328(define_insn_reservation "athlon_idirect_movstore" 1
ec970ca7 329 (and (eq_attr "cpu" "athlon,k8,amdfam10")
805e22b2 330 (and (eq_attr "type" "imov")
331 (eq_attr "memory" "store")))
332 "athlon-direct,athlon-agu,athlon-store")
3d775f8e 333
805e22b2 334(define_insn_reservation "athlon_idirect_both" 4
ec970ca7 335 (and (eq_attr "cpu" "athlon,k8")
805e22b2 336 (and (eq_attr "athlon_decode" "direct")
337 (and (eq_attr "unit" "integer,unknown")
338 (eq_attr "memory" "both"))))
5e69cae4 339 "athlon-direct,athlon-load,
340 athlon-ieu,athlon-store,
805e22b2 341 athlon-store")
3d775f8e 342(define_insn_reservation "athlon_idirect_both_amdfam10" 4
343 (and (eq_attr "cpu" "amdfam10")
344 (and (eq_attr "amdfam10_decode" "direct")
345 (and (eq_attr "unit" "integer,unknown")
346 (eq_attr "memory" "both"))))
347 "athlon-direct,athlon-load,
348 athlon-ieu,athlon-store,
009b318f 349 athlon-store")
3d775f8e 350
805e22b2 351(define_insn_reservation "athlon_ivector_both" 6
ec970ca7 352 (and (eq_attr "cpu" "athlon,k8")
805e22b2 353 (and (eq_attr "athlon_decode" "vector")
354 (and (eq_attr "unit" "integer,unknown")
355 (eq_attr "memory" "both"))))
5e69cae4 356 "athlon-vector,athlon-load,
357 athlon-ieu,
358 athlon-ieu,
805e22b2 359 athlon-store")
3d775f8e 360(define_insn_reservation "athlon_ivector_both_amdfam10" 6
361 (and (eq_attr "cpu" "amdfam10")
362 (and (eq_attr "amdfam10_decode" "vector")
363 (and (eq_attr "unit" "integer,unknown")
364 (eq_attr "memory" "both"))))
365 "athlon-vector,athlon-load,
366 athlon-ieu,
367 athlon-ieu,
368 athlon-store")
369
805e22b2 370(define_insn_reservation "athlon_idirect_store" 1
ec970ca7 371 (and (eq_attr "cpu" "athlon,k8")
805e22b2 372 (and (eq_attr "athlon_decode" "direct")
373 (and (eq_attr "unit" "integer,unknown")
374 (eq_attr "memory" "store"))))
5e69cae4 375 "athlon-direct,(athlon-ieu+athlon-agu),
805e22b2 376 athlon-store")
3d775f8e 377(define_insn_reservation "athlon_idirect_store_amdfam10" 1
378 (and (eq_attr "cpu" "amdfam10")
379 (and (eq_attr "amdfam10_decode" "direct")
380 (and (eq_attr "unit" "integer,unknown")
381 (eq_attr "memory" "store"))))
382 "athlon-direct,(athlon-ieu+athlon-agu),
383 athlon-store")
384
805e22b2 385(define_insn_reservation "athlon_ivector_store" 2
ec970ca7 386 (and (eq_attr "cpu" "athlon,k8")
805e22b2 387 (and (eq_attr "athlon_decode" "vector")
388 (and (eq_attr "unit" "integer,unknown")
389 (eq_attr "memory" "store"))))
5e69cae4 390 "athlon-vector,(athlon-ieu+athlon-agu),athlon-ieu,
805e22b2 391 athlon-store")
3d775f8e 392(define_insn_reservation "athlon_ivector_store_amdfam10" 2
393 (and (eq_attr "cpu" "amdfam10")
394 (and (eq_attr "amdfam10_decode" "vector")
395 (and (eq_attr "unit" "integer,unknown")
396 (eq_attr "memory" "store"))))
397 "athlon-vector,(athlon-ieu+athlon-agu),athlon-ieu,
398 athlon-store")
9a999200 399
805e22b2 400;; Athlon floatin point unit
401(define_insn_reservation "athlon_fldxf" 12
402 (and (eq_attr "cpu" "athlon")
403 (and (eq_attr "type" "fmov")
404 (and (eq_attr "memory" "load")
405 (eq_attr "mode" "XF"))))
5e69cae4 406 "athlon-vector,athlon-fpload2,athlon-fvector*9")
805e22b2 407(define_insn_reservation "athlon_fldxf_k8" 13
ec970ca7 408 (and (eq_attr "cpu" "k8,amdfam10")
805e22b2 409 (and (eq_attr "type" "fmov")
410 (and (eq_attr "memory" "load")
411 (eq_attr "mode" "XF"))))
5e69cae4 412 "athlon-vector,athlon-fpload2k8,athlon-fvector*9")
413;; Assume superforwarding to take place so effective latency of fany op is 0.
414(define_insn_reservation "athlon_fld" 0
805e22b2 415 (and (eq_attr "cpu" "athlon")
416 (and (eq_attr "type" "fmov")
417 (eq_attr "memory" "load")))
5e69cae4 418 "athlon-direct,athlon-fpload,athlon-fany")
419(define_insn_reservation "athlon_fld_k8" 2
ec970ca7 420 (and (eq_attr "cpu" "k8,amdfam10")
805e22b2 421 (and (eq_attr "type" "fmov")
422 (eq_attr "memory" "load")))
5e69cae4 423 "athlon-direct,athlon-fploadk8,athlon-fstore")
424
805e22b2 425(define_insn_reservation "athlon_fstxf" 10
426 (and (eq_attr "cpu" "athlon")
427 (and (eq_attr "type" "fmov")
428 (and (eq_attr "memory" "store,both")
429 (eq_attr "mode" "XF"))))
5e69cae4 430 "athlon-vector,(athlon-fpsched+athlon-agu),(athlon-store2+(athlon-fvector*7))")
805e22b2 431(define_insn_reservation "athlon_fstxf_k8" 8
ec970ca7 432 (and (eq_attr "cpu" "k8,amdfam10")
805e22b2 433 (and (eq_attr "type" "fmov")
434 (and (eq_attr "memory" "store,both")
435 (eq_attr "mode" "XF"))))
5e69cae4 436 "athlon-vector,(athlon-fpsched+athlon-agu),(athlon-store2+(athlon-fvector*6))")
805e22b2 437(define_insn_reservation "athlon_fst" 4
438 (and (eq_attr "cpu" "athlon")
439 (and (eq_attr "type" "fmov")
440 (eq_attr "memory" "store,both")))
5e69cae4 441 "athlon-direct,(athlon-fpsched+athlon-agu),(athlon-fstore+athlon-store)")
805e22b2 442(define_insn_reservation "athlon_fst_k8" 2
ec970ca7 443 (and (eq_attr "cpu" "k8,amdfam10")
805e22b2 444 (and (eq_attr "type" "fmov")
445 (eq_attr "memory" "store,both")))
5e69cae4 446 "athlon-direct,(athlon-fpsched+athlon-agu),(athlon-fstore+athlon-store)")
805e22b2 447(define_insn_reservation "athlon_fist" 4
ec970ca7 448 (and (eq_attr "cpu" "athlon,k8,amdfam10")
33f5c1b6 449 (eq_attr "type" "fistp,fisttp"))
5e69cae4 450 "athlon-direct,(athlon-fpsched+athlon-agu),(athlon-fstore+athlon-store)")
805e22b2 451(define_insn_reservation "athlon_fmov" 2
ec970ca7 452 (and (eq_attr "cpu" "athlon,k8,amdfam10")
805e22b2 453 (eq_attr "type" "fmov"))
5e69cae4 454 "athlon-direct,athlon-fpsched,athlon-faddmul")
455(define_insn_reservation "athlon_fadd_load" 4
805e22b2 456 (and (eq_attr "cpu" "athlon")
457 (and (eq_attr "type" "fop")
458 (eq_attr "memory" "load")))
5e69cae4 459 "athlon-direct,athlon-fpload,athlon-fadd")
805e22b2 460(define_insn_reservation "athlon_fadd_load_k8" 6
ec970ca7 461 (and (eq_attr "cpu" "k8,amdfam10")
805e22b2 462 (and (eq_attr "type" "fop")
463 (eq_attr "memory" "load")))
5e69cae4 464 "athlon-direct,athlon-fploadk8,athlon-fadd")
805e22b2 465(define_insn_reservation "athlon_fadd" 4
ec970ca7 466 (and (eq_attr "cpu" "athlon,k8,amdfam10")
805e22b2 467 (eq_attr "type" "fop"))
5e69cae4 468 "athlon-direct,athlon-fpsched,athlon-fadd")
469(define_insn_reservation "athlon_fmul_load" 4
805e22b2 470 (and (eq_attr "cpu" "athlon")
471 (and (eq_attr "type" "fmul")
472 (eq_attr "memory" "load")))
5e69cae4 473 "athlon-direct,athlon-fpload,athlon-fmul")
805e22b2 474(define_insn_reservation "athlon_fmul_load_k8" 6
ec970ca7 475 (and (eq_attr "cpu" "k8,amdfam10")
805e22b2 476 (and (eq_attr "type" "fmul")
477 (eq_attr "memory" "load")))
5e69cae4 478 "athlon-direct,athlon-fploadk8,athlon-fmul")
805e22b2 479(define_insn_reservation "athlon_fmul" 4
ec970ca7 480 (and (eq_attr "cpu" "athlon,k8,amdfam10")
805e22b2 481 (eq_attr "type" "fmul"))
5e69cae4 482 "athlon-direct,athlon-fpsched,athlon-fmul")
805e22b2 483(define_insn_reservation "athlon_fsgn" 2
ec970ca7 484 (and (eq_attr "cpu" "athlon,k8,amdfam10")
805e22b2 485 (eq_attr "type" "fsgn"))
5e69cae4 486 "athlon-direct,athlon-fpsched,athlon-fmul")
805e22b2 487(define_insn_reservation "athlon_fdiv_load" 24
488 (and (eq_attr "cpu" "athlon")
489 (and (eq_attr "type" "fdiv")
490 (eq_attr "memory" "load")))
5e69cae4 491 "athlon-direct,athlon-fpload,athlon-fmul")
805e22b2 492(define_insn_reservation "athlon_fdiv_load_k8" 13
ec970ca7 493 (and (eq_attr "cpu" "k8,amdfam10")
805e22b2 494 (and (eq_attr "type" "fdiv")
495 (eq_attr "memory" "load")))
5e69cae4 496 "athlon-direct,athlon-fploadk8,athlon-fmul")
805e22b2 497(define_insn_reservation "athlon_fdiv" 24
498 (and (eq_attr "cpu" "athlon")
499 (eq_attr "type" "fdiv"))
5e69cae4 500 "athlon-direct,athlon-fpsched,athlon-fmul")
805e22b2 501(define_insn_reservation "athlon_fdiv_k8" 11
ec970ca7 502 (and (eq_attr "cpu" "k8,amdfam10")
805e22b2 503 (eq_attr "type" "fdiv"))
5e69cae4 504 "athlon-direct,athlon-fpsched,athlon-fmul")
805e22b2 505(define_insn_reservation "athlon_fpspc_load" 103
ec970ca7 506 (and (eq_attr "cpu" "athlon,k8,amdfam10")
805e22b2 507 (and (eq_attr "type" "fpspc")
508 (eq_attr "memory" "load")))
5e69cae4 509 "athlon-vector,athlon-fpload,athlon-fvector")
805e22b2 510(define_insn_reservation "athlon_fpspc" 100
ec970ca7 511 (and (eq_attr "cpu" "athlon,k8,amdfam10")
805e22b2 512 (eq_attr "type" "fpspc"))
5e69cae4 513 "athlon-vector,athlon-fpsched,athlon-fvector")
514(define_insn_reservation "athlon_fcmov_load" 7
805e22b2 515 (and (eq_attr "cpu" "athlon")
516 (and (eq_attr "type" "fcmov")
517 (eq_attr "memory" "load")))
5e69cae4 518 "athlon-vector,athlon-fpload,athlon-fvector")
805e22b2 519(define_insn_reservation "athlon_fcmov" 7
520 (and (eq_attr "cpu" "athlon")
521 (eq_attr "type" "fcmov"))
5e69cae4 522 "athlon-vector,athlon-fpsched,athlon-fvector")
805e22b2 523(define_insn_reservation "athlon_fcmov_load_k8" 17
ec970ca7 524 (and (eq_attr "cpu" "k8,amdfam10")
805e22b2 525 (and (eq_attr "type" "fcmov")
526 (eq_attr "memory" "load")))
5e69cae4 527 "athlon-vector,athlon-fploadk8,athlon-fvector")
805e22b2 528(define_insn_reservation "athlon_fcmov_k8" 15
ec970ca7 529 (and (eq_attr "cpu" "k8,amdfam10")
805e22b2 530 (eq_attr "type" "fcmov"))
5e69cae4 531 "athlon-vector,athlon-fpsched,athlon-fvector")
532;; fcomi is vector decoded by uses only one pipe.
533(define_insn_reservation "athlon_fcomi_load" 3
805e22b2 534 (and (eq_attr "cpu" "athlon")
535 (and (eq_attr "type" "fcmp")
536 (and (eq_attr "athlon_decode" "vector")
537 (eq_attr "memory" "load"))))
5e69cae4 538 "athlon-vector,athlon-fpload,athlon-fadd")
539(define_insn_reservation "athlon_fcomi_load_k8" 5
ec970ca7 540 (and (eq_attr "cpu" "k8,amdfam10")
5e69cae4 541 (and (eq_attr "type" "fcmp")
542 (and (eq_attr "athlon_decode" "vector")
543 (eq_attr "memory" "load"))))
544 "athlon-vector,athlon-fploadk8,athlon-fadd")
805e22b2 545(define_insn_reservation "athlon_fcomi" 3
ec970ca7 546 (and (eq_attr "cpu" "athlon,k8,amdfam10")
805e22b2 547 (and (eq_attr "athlon_decode" "vector")
548 (eq_attr "type" "fcmp")))
5e69cae4 549 "athlon-vector,athlon-fpsched,athlon-fadd")
550(define_insn_reservation "athlon_fcom_load" 2
551 (and (eq_attr "cpu" "athlon")
552 (and (eq_attr "type" "fcmp")
553 (eq_attr "memory" "load")))
554 "athlon-direct,athlon-fpload,athlon-fadd")
555(define_insn_reservation "athlon_fcom_load_k8" 4
ec970ca7 556 (and (eq_attr "cpu" "k8,amdfam10")
805e22b2 557 (and (eq_attr "type" "fcmp")
558 (eq_attr "memory" "load")))
5e69cae4 559 "athlon-direct,athlon-fploadk8,athlon-fadd")
805e22b2 560(define_insn_reservation "athlon_fcom" 2
ec970ca7 561 (and (eq_attr "cpu" "athlon,k8,amdfam10")
805e22b2 562 (eq_attr "type" "fcmp"))
5e69cae4 563 "athlon-direct,athlon-fpsched,athlon-fadd")
564;; Never seen by the scheduler because we still don't do post reg-stack
565;; scheduling.
566;(define_insn_reservation "athlon_fxch" 2
ec970ca7 567; (and (eq_attr "cpu" "athlon,k8,amdfam10")
5e69cae4 568; (eq_attr "type" "fxch"))
569; "athlon-direct,athlon-fpsched,athlon-fany")
570
805e22b2 571;; Athlon handle MMX operations in the FPU unit with shorter latencies
5e69cae4 572
573(define_insn_reservation "athlon_movlpd_load" 0
574 (and (eq_attr "cpu" "athlon")
805e22b2 575 (and (eq_attr "type" "ssemov")
abd4f58b 576 (match_operand:DF 1 "memory_operand")))
5e69cae4 577 "athlon-direct,athlon-fpload,athlon-fany")
578(define_insn_reservation "athlon_movlpd_load_k8" 2
579 (and (eq_attr "cpu" "k8")
580 (and (eq_attr "type" "ssemov")
abd4f58b 581 (match_operand:DF 1 "memory_operand")))
5e69cae4 582 "athlon-direct,athlon-fploadk8,athlon-fstore")
583(define_insn_reservation "athlon_movaps_load_k8" 2
ec970ca7 584 (and (eq_attr "cpu" "k8")
805e22b2 585 (and (eq_attr "type" "ssemov")
586 (and (eq_attr "mode" "V4SF,V2DF,TI")
587 (eq_attr "memory" "load"))))
5e69cae4 588 "athlon-double,athlon-fpload2k8,athlon-fstore,athlon-fstore")
589(define_insn_reservation "athlon_movaps_load" 0
590 (and (eq_attr "cpu" "athlon")
591 (and (eq_attr "type" "ssemov")
592 (and (eq_attr "mode" "V4SF,V2DF,TI")
593 (eq_attr "memory" "load"))))
594 "athlon-vector,athlon-fpload2,(athlon-fany+athlon-fany)")
595(define_insn_reservation "athlon_movss_load" 1
596 (and (eq_attr "cpu" "athlon")
805e22b2 597 (and (eq_attr "type" "ssemov")
598 (and (eq_attr "mode" "SF,DI")
599 (eq_attr "memory" "load"))))
5e69cae4 600 "athlon-vector,athlon-fpload,(athlon-fany*2)")
601(define_insn_reservation "athlon_movss_load_k8" 1
ec970ca7 602 (and (eq_attr "cpu" "k8")
5e69cae4 603 (and (eq_attr "type" "ssemov")
604 (and (eq_attr "mode" "SF,DI")
605 (eq_attr "memory" "load"))))
606 "athlon-double,athlon-fploadk8,(athlon-fstore+athlon-fany)")
607(define_insn_reservation "athlon_mmxsseld" 0
608 (and (eq_attr "cpu" "athlon")
805e22b2 609 (and (eq_attr "type" "mmxmov,ssemov")
610 (eq_attr "memory" "load")))
5e69cae4 611 "athlon-direct,athlon-fpload,athlon-fany")
612(define_insn_reservation "athlon_mmxsseld_k8" 2
ec970ca7 613 (and (eq_attr "cpu" "k8")
5e69cae4 614 (and (eq_attr "type" "mmxmov,ssemov")
615 (eq_attr "memory" "load")))
616 "athlon-direct,athlon-fploadk8,athlon-fstore")
3d775f8e 617;; On AMDFAM10 all double, single and integer packed and scalar SSEx data
618;; loads generated are direct path, latency of 2 and do not use any FP
85694bac 619;; executions units. No separate entries for movlpx/movhpx loads, which
3d775f8e 620;; are direct path, latency of 4 and use the FADD/FMUL FP execution units,
621;; as they will not be generated.
622(define_insn_reservation "athlon_sseld_amdfam10" 2
623 (and (eq_attr "cpu" "amdfam10")
624 (and (eq_attr "type" "ssemov")
625 (eq_attr "memory" "load")))
626 "athlon-direct,athlon-fploadk8")
627;; On AMDFAM10 MMX data loads generated are direct path, latency of 4
628;; and can use any FP executions units
629(define_insn_reservation "athlon_mmxld_amdfam10" 4
630 (and (eq_attr "cpu" "amdfam10")
631 (and (eq_attr "type" "mmxmov")
632 (eq_attr "memory" "load")))
009b318f 633 "athlon-direct,athlon-fploadk8, athlon-fany")
805e22b2 634(define_insn_reservation "athlon_mmxssest" 3
ec970ca7 635 (and (eq_attr "cpu" "k8")
805e22b2 636 (and (eq_attr "type" "mmxmov,ssemov")
637 (and (eq_attr "mode" "V4SF,V2DF,TI")
638 (eq_attr "memory" "store,both"))))
5e69cae4 639 "athlon-vector,(athlon-fpsched+athlon-agu),((athlon-fstore+athlon-store2)*2)")
640(define_insn_reservation "athlon_mmxssest_k8" 3
ec970ca7 641 (and (eq_attr "cpu" "k8")
5e69cae4 642 (and (eq_attr "type" "mmxmov,ssemov")
643 (and (eq_attr "mode" "V4SF,V2DF,TI")
644 (eq_attr "memory" "store,both"))))
645 "athlon-double,(athlon-fpsched+athlon-agu),((athlon-fstore+athlon-store2)*2)")
646(define_insn_reservation "athlon_mmxssest_short" 2
ec970ca7 647 (and (eq_attr "cpu" "athlon,k8")
805e22b2 648 (and (eq_attr "type" "mmxmov,ssemov")
649 (eq_attr "memory" "store,both")))
5e69cae4 650 "athlon-direct,(athlon-fpsched+athlon-agu),(athlon-fstore+athlon-store)")
3d775f8e 651;; On AMDFAM10 all double, single and integer packed SSEx data stores
652;; generated are all double path, latency of 2 and use the FSTORE FP
85694bac 653;; execution unit. No entries separate for movupx/movdqu, which are
3d775f8e 654;; vector path, latency of 3 and use the FSTORE*2 FP execution unit,
655;; as they will not be generated.
656(define_insn_reservation "athlon_ssest_amdfam10" 2
657 (and (eq_attr "cpu" "amdfam10")
658 (and (eq_attr "type" "ssemov")
659 (and (eq_attr "mode" "V4SF,V2DF,TI")
660 (eq_attr "memory" "store,both"))))
661 "athlon-double,(athlon-fpsched+athlon-agu),((athlon-fstore+athlon-store)*2)")
662;; On AMDFAM10 all double, single and integer scalar SSEx and MMX
663;; data stores generated are all direct path, latency of 2 and use
664;; the FSTORE FP execution unit
665(define_insn_reservation "athlon_mmxssest_short_amdfam10" 2
666 (and (eq_attr "cpu" "amdfam10")
667 (and (eq_attr "type" "mmxmov,ssemov")
668 (eq_attr "memory" "store,both")))
669 "athlon-direct,(athlon-fpsched+athlon-agu),(athlon-fstore+athlon-store)")
9db3d688 670(define_insn_reservation "athlon_movaps_k8" 2
ec970ca7 671 (and (eq_attr "cpu" "k8")
805e22b2 672 (and (eq_attr "type" "ssemov")
5e69cae4 673 (eq_attr "mode" "V4SF,V2DF,TI")))
9db3d688 674 "athlon-double,athlon-fpsched,((athlon-faddmul+athlon-faddmul) | (athlon-faddmul, athlon-faddmul))")
675(define_insn_reservation "athlon_movaps" 2
5e69cae4 676 (and (eq_attr "cpu" "athlon")
677 (and (eq_attr "type" "ssemov")
678 (eq_attr "mode" "V4SF,V2DF,TI")))
679 "athlon-vector,athlon-fpsched,(athlon-faddmul+athlon-faddmul)")
805e22b2 680(define_insn_reservation "athlon_mmxssemov" 2
ec970ca7 681 (and (eq_attr "cpu" "athlon,k8")
805e22b2 682 (eq_attr "type" "mmxmov,ssemov"))
5e69cae4 683 "athlon-direct,athlon-fpsched,athlon-faddmul")
684(define_insn_reservation "athlon_mmxmul_load" 4
ec970ca7 685 (and (eq_attr "cpu" "athlon,k8")
805e22b2 686 (and (eq_attr "type" "mmxmul")
687 (eq_attr "memory" "load")))
5e69cae4 688 "athlon-direct,athlon-fpload,athlon-fmul")
805e22b2 689(define_insn_reservation "athlon_mmxmul" 3
ec970ca7 690 (and (eq_attr "cpu" "athlon,k8")
805e22b2 691 (eq_attr "type" "mmxmul"))
5e69cae4 692 "athlon-direct,athlon-fpsched,athlon-fmul")
693(define_insn_reservation "athlon_mmx_load" 3
ec970ca7 694 (and (eq_attr "cpu" "athlon,k8")
805e22b2 695 (and (eq_attr "unit" "mmx")
696 (eq_attr "memory" "load")))
5e69cae4 697 "athlon-direct,athlon-fpload,athlon-faddmul")
805e22b2 698(define_insn_reservation "athlon_mmx" 2
ec970ca7 699 (and (eq_attr "cpu" "athlon,k8")
805e22b2 700 (eq_attr "unit" "mmx"))
5e69cae4 701 "athlon-direct,athlon-fpsched,athlon-faddmul")
fcbfedc7 702;; SSE operations are handled by the i387 unit as well. The latency
805e22b2 703;; is same as for i387 operations for scalar operations
5e69cae4 704
705(define_insn_reservation "athlon_sselog_load" 3
805e22b2 706 (and (eq_attr "cpu" "athlon")
77aff08f 707 (and (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1")
805e22b2 708 (eq_attr "memory" "load")))
5e69cae4 709 "athlon-vector,athlon-fpload2,(athlon-fmul*2)")
805e22b2 710(define_insn_reservation "athlon_sselog_load_k8" 5
ec970ca7 711 (and (eq_attr "cpu" "k8")
77aff08f 712 (and (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1")
805e22b2 713 (eq_attr "memory" "load")))
5e69cae4 714 "athlon-double,athlon-fpload2k8,(athlon-fmul*2)")
3d775f8e 715(define_insn_reservation "athlon_sselog_load_amdfam10" 4
716 (and (eq_attr "cpu" "amdfam10")
77aff08f 717 (and (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1")
3d775f8e 718 (eq_attr "memory" "load")))
719 "athlon-direct,athlon-fploadk8,(athlon-fadd|athlon-fmul)")
805e22b2 720(define_insn_reservation "athlon_sselog" 3
721 (and (eq_attr "cpu" "athlon")
77aff08f 722 (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1"))
5e69cae4 723 "athlon-vector,athlon-fpsched,athlon-fmul*2")
805e22b2 724(define_insn_reservation "athlon_sselog_k8" 3
ec970ca7 725 (and (eq_attr "cpu" "k8")
77aff08f 726 (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1"))
5e69cae4 727 "athlon-double,athlon-fpsched,athlon-fmul")
3d775f8e 728(define_insn_reservation "athlon_sselog_amdfam10" 2
729 (and (eq_attr "cpu" "amdfam10")
77aff08f 730 (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1"))
3d775f8e 731 "athlon-direct,athlon-fpsched,(athlon-fadd|athlon-fmul)")
732
4cad3320 733;; ??? pcmp executes in addmul, probably not worthwhile to bother about that.
5e69cae4 734(define_insn_reservation "athlon_ssecmp_load" 2
735 (and (eq_attr "cpu" "athlon")
736 (and (eq_attr "type" "ssecmp")
737 (and (eq_attr "mode" "SF,DF,DI")
738 (eq_attr "memory" "load"))))
739 "athlon-direct,athlon-fpload,athlon-fadd")
740(define_insn_reservation "athlon_ssecmp_load_k8" 4
ec970ca7 741 (and (eq_attr "cpu" "k8,amdfam10")
5e69cae4 742 (and (eq_attr "type" "ssecmp")
743 (and (eq_attr "mode" "SF,DF,DI,TI")
805e22b2 744 (eq_attr "memory" "load"))))
5e69cae4 745 "athlon-direct,athlon-fploadk8,athlon-fadd")
805e22b2 746(define_insn_reservation "athlon_ssecmp" 2
ec970ca7 747 (and (eq_attr "cpu" "athlon,k8,amdfam10")
5e69cae4 748 (and (eq_attr "type" "ssecmp")
749 (eq_attr "mode" "SF,DF,DI,TI")))
750 "athlon-direct,athlon-fpsched,athlon-fadd")
751(define_insn_reservation "athlon_ssecmpvector_load" 3
805e22b2 752 (and (eq_attr "cpu" "athlon")
5e69cae4 753 (and (eq_attr "type" "ssecmp")
805e22b2 754 (eq_attr "memory" "load")))
5e69cae4 755 "athlon-vector,athlon-fpload2,(athlon-fadd*2)")
805e22b2 756(define_insn_reservation "athlon_ssecmpvector_load_k8" 5
ec970ca7 757 (and (eq_attr "cpu" "k8")
5e69cae4 758 (and (eq_attr "type" "ssecmp")
805e22b2 759 (eq_attr "memory" "load")))
5e69cae4 760 "athlon-double,athlon-fpload2k8,(athlon-fadd*2)")
3d775f8e 761(define_insn_reservation "athlon_ssecmpvector_load_amdfam10" 4
762 (and (eq_attr "cpu" "amdfam10")
763 (and (eq_attr "type" "ssecmp")
764 (eq_attr "memory" "load")))
765 "athlon-direct,athlon-fploadk8,athlon-fadd")
805e22b2 766(define_insn_reservation "athlon_ssecmpvector" 3
767 (and (eq_attr "cpu" "athlon")
5e69cae4 768 (eq_attr "type" "ssecmp"))
769 "athlon-vector,athlon-fpsched,(athlon-fadd*2)")
805e22b2 770(define_insn_reservation "athlon_ssecmpvector_k8" 3
ec970ca7 771 (and (eq_attr "cpu" "k8")
5e69cae4 772 (eq_attr "type" "ssecmp"))
773 "athlon-double,athlon-fpsched,(athlon-fadd*2)")
3d775f8e 774(define_insn_reservation "athlon_ssecmpvector_amdfam10" 2
775 (and (eq_attr "cpu" "amdfam10")
776 (eq_attr "type" "ssecmp"))
777 "athlon-direct,athlon-fpsched,athlon-fadd")
5e69cae4 778(define_insn_reservation "athlon_ssecomi_load" 4
779 (and (eq_attr "cpu" "athlon")
780 (and (eq_attr "type" "ssecomi")
781 (eq_attr "memory" "load")))
782 "athlon-vector,athlon-fpload,athlon-fadd")
783(define_insn_reservation "athlon_ssecomi_load_k8" 6
ec970ca7 784 (and (eq_attr "cpu" "k8")
5e69cae4 785 (and (eq_attr "type" "ssecomi")
786 (eq_attr "memory" "load")))
787 "athlon-vector,athlon-fploadk8,athlon-fadd")
3d775f8e 788(define_insn_reservation "athlon_ssecomi_load_amdfam10" 5
789 (and (eq_attr "cpu" "amdfam10")
790 (and (eq_attr "type" "ssecomi")
791 (eq_attr "memory" "load")))
792 "athlon-direct,athlon-fploadk8,athlon-fadd")
5e69cae4 793(define_insn_reservation "athlon_ssecomi" 4
ec970ca7 794 (and (eq_attr "cpu" "athlon,k8")
680bc122 795 (eq_attr "type" "ssecomi"))
5e69cae4 796 "athlon-vector,athlon-fpsched,athlon-fadd")
3d775f8e 797(define_insn_reservation "athlon_ssecomi_amdfam10" 3
798 (and (eq_attr "cpu" "amdfam10")
799;; It seems athlon_ssecomi has a bug in the attr_type, fixed for amdfam10
800 (eq_attr "type" "ssecomi"))
801 "athlon-direct,athlon-fpsched,athlon-fadd")
5e69cae4 802(define_insn_reservation "athlon_sseadd_load" 4
805e22b2 803 (and (eq_attr "cpu" "athlon")
6095368e 804 (and (eq_attr "type" "sseadd,sseadd1")
5e69cae4 805 (and (eq_attr "mode" "SF,DF,DI")
805e22b2 806 (eq_attr "memory" "load"))))
5e69cae4 807 "athlon-direct,athlon-fpload,athlon-fadd")
805e22b2 808(define_insn_reservation "athlon_sseadd_load_k8" 6
ec970ca7 809 (and (eq_attr "cpu" "k8,amdfam10")
6095368e 810 (and (eq_attr "type" "sseadd,sseadd1")
5e69cae4 811 (and (eq_attr "mode" "SF,DF,DI")
805e22b2 812 (eq_attr "memory" "load"))))
5e69cae4 813 "athlon-direct,athlon-fploadk8,athlon-fadd")
805e22b2 814(define_insn_reservation "athlon_sseadd" 4
ec970ca7 815 (and (eq_attr "cpu" "athlon,k8,amdfam10")
6095368e 816 (and (eq_attr "type" "sseadd,sseadd1")
5e69cae4 817 (eq_attr "mode" "SF,DF,DI")))
818 "athlon-direct,athlon-fpsched,athlon-fadd")
819(define_insn_reservation "athlon_sseaddvector_load" 5
805e22b2 820 (and (eq_attr "cpu" "athlon")
6095368e 821 (and (eq_attr "type" "sseadd,sseadd1")
805e22b2 822 (eq_attr "memory" "load")))
5e69cae4 823 "athlon-vector,athlon-fpload2,(athlon-fadd*2)")
805e22b2 824(define_insn_reservation "athlon_sseaddvector_load_k8" 7
ec970ca7 825 (and (eq_attr "cpu" "k8")
6095368e 826 (and (eq_attr "type" "sseadd,sseadd1")
805e22b2 827 (eq_attr "memory" "load")))
5e69cae4 828 "athlon-double,athlon-fpload2k8,(athlon-fadd*2)")
3d775f8e 829(define_insn_reservation "athlon_sseaddvector_load_amdfam10" 6
830 (and (eq_attr "cpu" "amdfam10")
6095368e 831 (and (eq_attr "type" "sseadd,sseadd1")
3d775f8e 832 (eq_attr "memory" "load")))
833 "athlon-direct,athlon-fploadk8,athlon-fadd")
805e22b2 834(define_insn_reservation "athlon_sseaddvector" 5
835 (and (eq_attr "cpu" "athlon")
6095368e 836 (eq_attr "type" "sseadd,sseadd1"))
5e69cae4 837 "athlon-vector,athlon-fpsched,(athlon-fadd*2)")
838(define_insn_reservation "athlon_sseaddvector_k8" 5
ec970ca7 839 (and (eq_attr "cpu" "k8")
6095368e 840 (eq_attr "type" "sseadd,sseadd1"))
5e69cae4 841 "athlon-double,athlon-fpsched,(athlon-fadd*2)")
3d775f8e 842(define_insn_reservation "athlon_sseaddvector_amdfam10" 4
843 (and (eq_attr "cpu" "amdfam10")
6095368e 844 (eq_attr "type" "sseadd,sseadd1"))
3d775f8e 845 "athlon-direct,athlon-fpsched,athlon-fadd")
5e69cae4 846
3c364971 847;; Conversions behaves very irregularly and the scheduling is critical here.
5e69cae4 848;; Take each instruction separately. Assume that the mode is always set to the
849;; destination one and athlon_decode is set to the K8 versions.
850
851;; cvtss2sd
852(define_insn_reservation "athlon_ssecvt_cvtss2sd_load_k8" 4
ec970ca7 853 (and (eq_attr "cpu" "k8,athlon")
805e22b2 854 (and (eq_attr "type" "ssecvt")
5e69cae4 855 (and (eq_attr "athlon_decode" "direct")
856 (and (eq_attr "mode" "DF")
857 (eq_attr "memory" "load")))))
858 "athlon-direct,athlon-fploadk8,athlon-fstore")
3d775f8e 859(define_insn_reservation "athlon_ssecvt_cvtss2sd_load_amdfam10" 7
860 (and (eq_attr "cpu" "amdfam10")
861 (and (eq_attr "type" "ssecvt")
862 (and (eq_attr "amdfam10_decode" "double")
863 (and (eq_attr "mode" "DF")
864 (eq_attr "memory" "load")))))
865 "athlon-double,athlon-fploadk8,(athlon-faddmul+athlon-fstore)")
5e69cae4 866(define_insn_reservation "athlon_ssecvt_cvtss2sd" 2
ec970ca7 867 (and (eq_attr "cpu" "athlon,k8")
805e22b2 868 (and (eq_attr "type" "ssecvt")
5e69cae4 869 (and (eq_attr "athlon_decode" "direct")
870 (eq_attr "mode" "DF"))))
871 "athlon-direct,athlon-fpsched,athlon-fstore")
3d775f8e 872(define_insn_reservation "athlon_ssecvt_cvtss2sd_amdfam10" 7
873 (and (eq_attr "cpu" "amdfam10")
874 (and (eq_attr "type" "ssecvt")
875 (and (eq_attr "amdfam10_decode" "vector")
876 (eq_attr "mode" "DF"))))
877 "athlon-vector,athlon-fpsched,athlon-faddmul,(athlon-fstore*2)")
5e69cae4 878;; cvtps2pd. Model same way the other double decoded FP conversions.
879(define_insn_reservation "athlon_ssecvt_cvtps2pd_load_k8" 5
ec970ca7 880 (and (eq_attr "cpu" "k8,athlon")
5e69cae4 881 (and (eq_attr "type" "ssecvt")
882 (and (eq_attr "athlon_decode" "double")
883 (and (eq_attr "mode" "V2DF,V4SF,TI")
884 (eq_attr "memory" "load")))))
885 "athlon-double,athlon-fpload2k8,(athlon-fstore*2)")
3d775f8e 886(define_insn_reservation "athlon_ssecvt_cvtps2pd_load_amdfam10" 4
887 (and (eq_attr "cpu" "amdfam10")
888 (and (eq_attr "type" "ssecvt")
889 (and (eq_attr "amdfam10_decode" "direct")
890 (and (eq_attr "mode" "V2DF,V4SF,TI")
891 (eq_attr "memory" "load")))))
892 "athlon-direct,athlon-fploadk8,athlon-fstore")
5e69cae4 893(define_insn_reservation "athlon_ssecvt_cvtps2pd_k8" 3
ec970ca7 894 (and (eq_attr "cpu" "k8,athlon")
5e69cae4 895 (and (eq_attr "type" "ssecvt")
896 (and (eq_attr "athlon_decode" "double")
897 (eq_attr "mode" "V2DF,V4SF,TI"))))
898 "athlon-double,athlon-fpsched,athlon-fstore,athlon-fstore")
3d775f8e 899(define_insn_reservation "athlon_ssecvt_cvtps2pd_amdfam10" 2
900 (and (eq_attr "cpu" "amdfam10")
901 (and (eq_attr "type" "ssecvt")
902 (and (eq_attr "amdfam10_decode" "direct")
903 (eq_attr "mode" "V2DF,V4SF,TI"))))
904 "athlon-direct,athlon-fpsched,athlon-fstore")
5e69cae4 905;; cvtsi2sd mem,reg is directpath path (cvtsi2sd reg,reg is doublepath)
906;; cvtsi2sd has troughput 1 and is executed in store unit with latency of 6
907(define_insn_reservation "athlon_sseicvt_cvtsi2sd_load" 6
908 (and (eq_attr "cpu" "athlon,k8")
909 (and (eq_attr "type" "sseicvt")
910 (and (eq_attr "athlon_decode" "direct")
911 (and (eq_attr "mode" "SF,DF")
912 (eq_attr "memory" "load")))))
913 "athlon-direct,athlon-fploadk8,athlon-fstore")
3d775f8e 914(define_insn_reservation "athlon_sseicvt_cvtsi2sd_load_amdfam10" 9
915 (and (eq_attr "cpu" "amdfam10")
916 (and (eq_attr "type" "sseicvt")
917 (and (eq_attr "amdfam10_decode" "double")
918 (and (eq_attr "mode" "SF,DF")
919 (eq_attr "memory" "load")))))
920 "athlon-double,athlon-fploadk8,(athlon-faddmul+athlon-fstore)")
5e69cae4 921;; cvtsi2ss mem, reg is doublepath
922(define_insn_reservation "athlon_sseicvt_cvtsi2ss_load" 9
805e22b2 923 (and (eq_attr "cpu" "athlon")
5e69cae4 924 (and (eq_attr "type" "sseicvt")
925 (and (eq_attr "athlon_decode" "double")
926 (and (eq_attr "mode" "SF,DF")
927 (eq_attr "memory" "load")))))
928 "athlon-vector,athlon-fpload,(athlon-fstore*2)")
929(define_insn_reservation "athlon_sseicvt_cvtsi2ss_load_k8" 9
ec970ca7 930 (and (eq_attr "cpu" "k8")
5e69cae4 931 (and (eq_attr "type" "sseicvt")
932 (and (eq_attr "athlon_decode" "double")
933 (and (eq_attr "mode" "SF,DF")
934 (eq_attr "memory" "load")))))
935 "athlon-double,athlon-fploadk8,(athlon-fstore*2)")
3d775f8e 936(define_insn_reservation "athlon_sseicvt_cvtsi2ss_load_amdfam10" 9
937 (and (eq_attr "cpu" "amdfam10")
938 (and (eq_attr "type" "sseicvt")
939 (and (eq_attr "amdfam10_decode" "double")
940 (and (eq_attr "mode" "SF,DF")
941 (eq_attr "memory" "load")))))
009b318f 942 "athlon-double,athlon-fploadk8,(athlon-faddmul+athlon-fstore)")
5e69cae4 943;; cvtsi2sd reg,reg is double decoded (vector on Athlon)
944(define_insn_reservation "athlon_sseicvt_cvtsi2sd_k8" 11
ec970ca7 945 (and (eq_attr "cpu" "k8,athlon")
5e69cae4 946 (and (eq_attr "type" "sseicvt")
947 (and (eq_attr "athlon_decode" "double")
948 (and (eq_attr "mode" "SF,DF")
949 (eq_attr "memory" "none")))))
950 "athlon-double,athlon-fploadk8,athlon-fstore")
3d775f8e 951(define_insn_reservation "athlon_sseicvt_cvtsi2sd_amdfam10" 14
952 (and (eq_attr "cpu" "amdfam10")
953 (and (eq_attr "type" "sseicvt")
954 (and (eq_attr "amdfam10_decode" "vector")
955 (and (eq_attr "mode" "SF,DF")
956 (eq_attr "memory" "none")))))
957 "athlon-vector,athlon-fploadk8,(athlon-faddmul+athlon-fstore)")
5e69cae4 958;; cvtsi2ss reg, reg is doublepath
959(define_insn_reservation "athlon_sseicvt_cvtsi2ss" 14
ec970ca7 960 (and (eq_attr "cpu" "athlon,k8")
5e69cae4 961 (and (eq_attr "type" "sseicvt")
962 (and (eq_attr "athlon_decode" "vector")
963 (and (eq_attr "mode" "SF,DF")
964 (eq_attr "memory" "none")))))
965 "athlon-vector,athlon-fploadk8,(athlon-fvector*2)")
3d775f8e 966(define_insn_reservation "athlon_sseicvt_cvtsi2ss_amdfam10" 14
967 (and (eq_attr "cpu" "amdfam10")
968 (and (eq_attr "type" "sseicvt")
969 (and (eq_attr "amdfam10_decode" "vector")
970 (and (eq_attr "mode" "SF,DF")
971 (eq_attr "memory" "none")))))
972 "athlon-vector,athlon-fploadk8,(athlon-faddmul+athlon-fstore)")
5e69cae4 973;; cvtsd2ss mem,reg is doublepath, troughput unknown, latency 9
974(define_insn_reservation "athlon_ssecvt_cvtsd2ss_load_k8" 9
ec970ca7 975 (and (eq_attr "cpu" "k8,athlon")
805e22b2 976 (and (eq_attr "type" "ssecvt")
5e69cae4 977 (and (eq_attr "athlon_decode" "double")
978 (and (eq_attr "mode" "SF")
979 (eq_attr "memory" "load")))))
980 "athlon-double,athlon-fploadk8,(athlon-fstore*3)")
3d775f8e 981(define_insn_reservation "athlon_ssecvt_cvtsd2ss_load_amdfam10" 9
982 (and (eq_attr "cpu" "amdfam10")
983 (and (eq_attr "type" "ssecvt")
984 (and (eq_attr "amdfam10_decode" "double")
985 (and (eq_attr "mode" "SF")
986 (eq_attr "memory" "load")))))
987 "athlon-double,athlon-fploadk8,(athlon-faddmul+athlon-fstore)")
5e69cae4 988;; cvtsd2ss reg,reg is vectorpath, troughput unknown, latency 12
989(define_insn_reservation "athlon_ssecvt_cvtsd2ss" 12
ec970ca7 990 (and (eq_attr "cpu" "athlon,k8")
805e22b2 991 (and (eq_attr "type" "ssecvt")
5e69cae4 992 (and (eq_attr "athlon_decode" "vector")
993 (and (eq_attr "mode" "SF")
994 (eq_attr "memory" "none")))))
995 "athlon-vector,athlon-fpsched,(athlon-fvector*3)")
3d775f8e 996(define_insn_reservation "athlon_ssecvt_cvtsd2ss_amdfam10" 8
997 (and (eq_attr "cpu" "amdfam10")
998 (and (eq_attr "type" "ssecvt")
999 (and (eq_attr "amdfam10_decode" "vector")
1000 (and (eq_attr "mode" "SF")
1001 (eq_attr "memory" "none")))))
1002 "athlon-vector,athlon-fpsched,athlon-faddmul,(athlon-fstore*2)")
5e69cae4 1003(define_insn_reservation "athlon_ssecvt_cvtpd2ps_load_k8" 8
ec970ca7 1004 (and (eq_attr "cpu" "athlon,k8")
5e69cae4 1005 (and (eq_attr "type" "ssecvt")
1006 (and (eq_attr "athlon_decode" "vector")
1007 (and (eq_attr "mode" "V4SF,V2DF,TI")
1008 (eq_attr "memory" "load")))))
1009 "athlon-double,athlon-fpload2k8,(athlon-fstore*3)")
3d775f8e 1010(define_insn_reservation "athlon_ssecvt_cvtpd2ps_load_amdfam10" 9
1011 (and (eq_attr "cpu" "amdfam10")
1012 (and (eq_attr "type" "ssecvt")
1013 (and (eq_attr "amdfam10_decode" "double")
1014 (and (eq_attr "mode" "V4SF,V2DF,TI")
1015 (eq_attr "memory" "load")))))
1016 "athlon-double,athlon-fploadk8,(athlon-faddmul+athlon-fstore)")
5e69cae4 1017;; cvtpd2ps mem,reg is vectorpath, troughput unknown, latency 10
1018;; ??? Why it is fater than cvtsd2ss?
1019(define_insn_reservation "athlon_ssecvt_cvtpd2ps" 8
ec970ca7 1020 (and (eq_attr "cpu" "athlon,k8")
5e69cae4 1021 (and (eq_attr "type" "ssecvt")
1022 (and (eq_attr "athlon_decode" "vector")
1023 (and (eq_attr "mode" "V4SF,V2DF,TI")
1024 (eq_attr "memory" "none")))))
1025 "athlon-vector,athlon-fpsched,athlon-fvector*2")
3d775f8e 1026(define_insn_reservation "athlon_ssecvt_cvtpd2ps_amdfam10" 7
1027 (and (eq_attr "cpu" "amdfam10")
1028 (and (eq_attr "type" "ssecvt")
1029 (and (eq_attr "amdfam10_decode" "double")
1030 (and (eq_attr "mode" "V4SF,V2DF,TI")
1031 (eq_attr "memory" "none")))))
1032 "athlon-double,athlon-fpsched,(athlon-faddmul+athlon-fstore)")
5e69cae4 1033;; cvtsd2si mem,reg is doublepath, troughput 1, latency 9
1034(define_insn_reservation "athlon_secvt_cvtsX2si_load" 9
ec970ca7 1035 (and (eq_attr "cpu" "athlon,k8")
5e69cae4 1036 (and (eq_attr "type" "sseicvt")
1037 (and (eq_attr "athlon_decode" "vector")
1038 (and (eq_attr "mode" "SI,DI")
1039 (eq_attr "memory" "load")))))
1040 "athlon-vector,athlon-fploadk8,athlon-fvector")
3d775f8e 1041(define_insn_reservation "athlon_secvt_cvtsX2si_load_amdfam10" 10
1042 (and (eq_attr "cpu" "amdfam10")
1043 (and (eq_attr "type" "sseicvt")
1044 (and (eq_attr "amdfam10_decode" "double")
1045 (and (eq_attr "mode" "SI,DI")
1046 (eq_attr "memory" "load")))))
1047 "athlon-double,athlon-fploadk8,(athlon-fadd+athlon-fstore)")
5e69cae4 1048;; cvtsd2si reg,reg is doublepath, troughput 1, latency 9
1049(define_insn_reservation "athlon_ssecvt_cvtsX2si" 9
805e22b2 1050 (and (eq_attr "cpu" "athlon")
5e69cae4 1051 (and (eq_attr "type" "sseicvt")
1052 (and (eq_attr "athlon_decode" "double")
1053 (and (eq_attr "mode" "SI,DI")
1054 (eq_attr "memory" "none")))))
1055 "athlon-vector,athlon-fpsched,athlon-fvector")
1056(define_insn_reservation "athlon_ssecvt_cvtsX2si_k8" 9
ec970ca7 1057 (and (eq_attr "cpu" "k8")
5e69cae4 1058 (and (eq_attr "type" "sseicvt")
1059 (and (eq_attr "athlon_decode" "double")
1060 (and (eq_attr "mode" "SI,DI")
1061 (eq_attr "memory" "none")))))
1062 "athlon-double,athlon-fpsched,athlon-fstore")
3d775f8e 1063(define_insn_reservation "athlon_ssecvt_cvtsX2si_amdfam10" 8
1064 (and (eq_attr "cpu" "amdfam10")
1065 (and (eq_attr "type" "sseicvt")
1066 (and (eq_attr "amdfam10_decode" "double")
1067 (and (eq_attr "mode" "SI,DI")
1068 (eq_attr "memory" "none")))))
1069 "athlon-double,athlon-fpsched,(athlon-fadd+athlon-fstore)")
1070;; cvtpd2dq reg,mem is doublepath, troughput 1, latency 9 on amdfam10
1071(define_insn_reservation "athlon_sseicvt_cvtpd2dq_load_amdfam10" 9
1072 (and (eq_attr "cpu" "amdfam10")
1073 (and (eq_attr "type" "sseicvt")
1074 (and (eq_attr "amdfam10_decode" "double")
1075 (and (eq_attr "mode" "TI")
1076 (eq_attr "memory" "load")))))
1077 "athlon-double,athlon-fploadk8,(athlon-faddmul+athlon-fstore)")
1078;; cvtpd2dq reg,mem is doublepath, troughput 1, latency 7 on amdfam10
1079(define_insn_reservation "athlon_sseicvt_cvtpd2dq_amdfam10" 7
1080 (and (eq_attr "cpu" "amdfam10")
1081 (and (eq_attr "type" "sseicvt")
1082 (and (eq_attr "amdfam10_decode" "double")
1083 (and (eq_attr "mode" "TI")
1084 (eq_attr "memory" "none")))))
1085 "athlon-double,athlon-fpsched,(athlon-faddmul+athlon-fstore)")
5e69cae4 1086
1087
1088(define_insn_reservation "athlon_ssemul_load" 4
805e22b2 1089 (and (eq_attr "cpu" "athlon")
1090 (and (eq_attr "type" "ssemul")
1091 (and (eq_attr "mode" "SF,DF")
1092 (eq_attr "memory" "load"))))
5e69cae4 1093 "athlon-direct,athlon-fpload,athlon-fmul")
805e22b2 1094(define_insn_reservation "athlon_ssemul_load_k8" 6
ec970ca7 1095 (and (eq_attr "cpu" "k8,amdfam10")
805e22b2 1096 (and (eq_attr "type" "ssemul")
1097 (and (eq_attr "mode" "SF,DF")
1098 (eq_attr "memory" "load"))))
5e69cae4 1099 "athlon-direct,athlon-fploadk8,athlon-fmul")
805e22b2 1100(define_insn_reservation "athlon_ssemul" 4
ec970ca7 1101 (and (eq_attr "cpu" "athlon,k8,amdfam10")
805e22b2 1102 (and (eq_attr "type" "ssemul")
1103 (eq_attr "mode" "SF,DF")))
5e69cae4 1104 "athlon-direct,athlon-fpsched,athlon-fmul")
1105(define_insn_reservation "athlon_ssemulvector_load" 5
805e22b2 1106 (and (eq_attr "cpu" "athlon")
1107 (and (eq_attr "type" "ssemul")
1108 (eq_attr "memory" "load")))
5e69cae4 1109 "athlon-vector,athlon-fpload2,(athlon-fmul*2)")
805e22b2 1110(define_insn_reservation "athlon_ssemulvector_load_k8" 7
ec970ca7 1111 (and (eq_attr "cpu" "k8")
805e22b2 1112 (and (eq_attr "type" "ssemul")
1113 (eq_attr "memory" "load")))
5e69cae4 1114 "athlon-double,athlon-fpload2k8,(athlon-fmul*2)")
3d775f8e 1115(define_insn_reservation "athlon_ssemulvector_load_amdfam10" 6
1116 (and (eq_attr "cpu" "amdfam10")
1117 (and (eq_attr "type" "ssemul")
1118 (eq_attr "memory" "load")))
1119 "athlon-direct,athlon-fploadk8,athlon-fmul")
805e22b2 1120(define_insn_reservation "athlon_ssemulvector" 5
1121 (and (eq_attr "cpu" "athlon")
1122 (eq_attr "type" "ssemul"))
5e69cae4 1123 "athlon-vector,athlon-fpsched,(athlon-fmul*2)")
805e22b2 1124(define_insn_reservation "athlon_ssemulvector_k8" 5
ec970ca7 1125 (and (eq_attr "cpu" "k8")
805e22b2 1126 (eq_attr "type" "ssemul"))
5e69cae4 1127 "athlon-double,athlon-fpsched,(athlon-fmul*2)")
3d775f8e 1128(define_insn_reservation "athlon_ssemulvector_amdfam10" 4
1129 (and (eq_attr "cpu" "amdfam10")
1130 (eq_attr "type" "ssemul"))
009b318f 1131 "athlon-direct,athlon-fpsched,athlon-fmul")
efee20da 1132;; divsd timings. divss is faster
5e69cae4 1133(define_insn_reservation "athlon_ssediv_load" 20
805e22b2 1134 (and (eq_attr "cpu" "athlon")
1135 (and (eq_attr "type" "ssediv")
1136 (and (eq_attr "mode" "SF,DF")
1137 (eq_attr "memory" "load"))))
5e69cae4 1138 "athlon-direct,athlon-fpload,athlon-fmul*17")
1139(define_insn_reservation "athlon_ssediv_load_k8" 22
ec970ca7 1140 (and (eq_attr "cpu" "k8,amdfam10")
805e22b2 1141 (and (eq_attr "type" "ssediv")
1142 (and (eq_attr "mode" "SF,DF")
1143 (eq_attr "memory" "load"))))
5e69cae4 1144 "athlon-direct,athlon-fploadk8,athlon-fmul*17")
1145(define_insn_reservation "athlon_ssediv" 20
ec970ca7 1146 (and (eq_attr "cpu" "athlon,k8,amdfam10")
805e22b2 1147 (and (eq_attr "type" "ssediv")
1148 (eq_attr "mode" "SF,DF")))
5e69cae4 1149 "athlon-direct,athlon-fpsched,athlon-fmul*17")
1150(define_insn_reservation "athlon_ssedivvector_load" 39
805e22b2 1151 (and (eq_attr "cpu" "athlon")
1152 (and (eq_attr "type" "ssediv")
1153 (eq_attr "memory" "load")))
5e69cae4 1154 "athlon-vector,athlon-fpload2,athlon-fmul*34")
805e22b2 1155(define_insn_reservation "athlon_ssedivvector_load_k8" 35
ec970ca7 1156 (and (eq_attr "cpu" "k8")
805e22b2 1157 (and (eq_attr "type" "ssediv")
1158 (eq_attr "memory" "load")))
5e69cae4 1159 "athlon-double,athlon-fpload2k8,athlon-fmul*34")
3d775f8e 1160(define_insn_reservation "athlon_ssedivvector_load_amdfam10" 22
1161 (and (eq_attr "cpu" "amdfam10")
1162 (and (eq_attr "type" "ssediv")
1163 (eq_attr "memory" "load")))
009b318f 1164 "athlon-direct,athlon-fploadk8,athlon-fmul*17")
5e69cae4 1165(define_insn_reservation "athlon_ssedivvector" 39
805e22b2 1166 (and (eq_attr "cpu" "athlon")
1167 (eq_attr "type" "ssediv"))
5e69cae4 1168 "athlon-vector,athlon-fmul*34")
1169(define_insn_reservation "athlon_ssedivvector_k8" 39
ec970ca7 1170 (and (eq_attr "cpu" "k8")
805e22b2 1171 (eq_attr "type" "ssediv"))
5e69cae4 1172 "athlon-double,athlon-fmul*34")
3d775f8e 1173(define_insn_reservation "athlon_ssedivvector_amdfam10" 20
1174 (and (eq_attr "cpu" "amdfam10")
1175 (eq_attr "type" "ssediv"))
1176 "athlon-direct,athlon-fmul*17")
1177(define_insn_reservation "athlon_sseins_amdfam10" 5
1178 (and (eq_attr "cpu" "amdfam10")
1179 (and (eq_attr "type" "sseins")
1180 (eq_attr "mode" "TI")))
1181 "athlon-vector,athlon-fpsched,athlon-faddmul")
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