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08b1e29a | 1 | ;; Constraint definitions for IA-32 and x86-64. |
d1e082c2 | 2 | ;; Copyright (C) 2006-2013 Free Software Foundation, Inc. |
08b1e29a RS |
3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
2f83c7d6 | 8 | ;; the Free Software Foundation; either version 3, or (at your option) |
08b1e29a RS |
9 | ;; any later version. |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
17 | ;; along with GCC; see the file COPYING3. If not see |
18 | ;; <http://www.gnu.org/licenses/>. | |
08b1e29a RS |
19 | |
20 | ;;; Unused letters: | |
66d6cbaa | 21 | ;;; H |
85a77221 | 22 | ;;; h j |
08b1e29a RS |
23 | |
24 | ;; Integer register constraints. | |
25 | ;; It is not necessary to define 'r' here. | |
26 | (define_register_constraint "R" "LEGACY_REGS" | |
27 | "Legacy register---the eight integer registers available on all | |
28 | i386 processors (@code{a}, @code{b}, @code{c}, @code{d}, | |
29 | @code{si}, @code{di}, @code{bp}, @code{sp}).") | |
30 | ||
31 | (define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS" | |
32 | "Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a}, | |
33 | @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.") | |
34 | ||
35 | (define_register_constraint "Q" "Q_REGS" | |
36 | "Any register accessible as @code{@var{r}h}: @code{a}, @code{b}, | |
37 | @code{c}, and @code{d}.") | |
38 | ||
39 | (define_register_constraint "l" "INDEX_REGS" | |
40 | "@internal Any register that can be used as the index in a base+index | |
41 | memory access: that is, any general register except the stack pointer.") | |
42 | ||
43 | (define_register_constraint "a" "AREG" | |
44 | "The @code{a} register.") | |
45 | ||
46 | (define_register_constraint "b" "BREG" | |
47 | "The @code{b} register.") | |
48 | ||
49 | (define_register_constraint "c" "CREG" | |
50 | "The @code{c} register.") | |
51 | ||
52 | (define_register_constraint "d" "DREG" | |
53 | "The @code{d} register.") | |
54 | ||
55 | (define_register_constraint "S" "SIREG" | |
56 | "The @code{si} register.") | |
57 | ||
58 | (define_register_constraint "D" "DIREG" | |
59 | "The @code{di} register.") | |
60 | ||
61 | (define_register_constraint "A" "AD_REGS" | |
62 | "The @code{a} and @code{d} registers, as a pair (for instructions | |
63 | that return half the result in one and half in the other).") | |
64 | ||
ac2e563f RH |
65 | (define_register_constraint "U" "CLOBBERED_REGS" |
66 | "The call-clobbered integer registers.") | |
67 | ||
08b1e29a RS |
68 | ;; Floating-point register constraints. |
69 | (define_register_constraint "f" | |
70 | "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FLOAT_REGS : NO_REGS" | |
71 | "Any 80387 floating-point (stack) register.") | |
72 | ||
73 | (define_register_constraint "t" | |
74 | "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_TOP_REG : NO_REGS" | |
75 | "Top of 80387 floating-point stack (@code{%st(0)}).") | |
76 | ||
77 | (define_register_constraint "u" | |
78 | "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS" | |
79 | "Second from top of 80387 floating-point stack (@code{%st(1)}).") | |
80 | ||
85a77221 AI |
81 | (define_register_constraint "k" "TARGET_AVX512F ? MASK_EVEX_REGS : NO_REGS" |
82 | "@internal Any mask register that can be used as predicate, i.e. k1-k7.") | |
83 | ||
84 | (define_register_constraint "Yk" "TARGET_AVX512F ? MASK_REGS : NO_REGS" | |
85 | "@internal Any mask register.") | |
86 | ||
08b1e29a RS |
87 | ;; Vector registers (also used for plain floating point nowadays). |
88 | (define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS" | |
89 | "Any MMX register.") | |
90 | ||
91 | (define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS" | |
92 | "Any SSE register.") | |
93 | ||
66d6cbaa IE |
94 | (define_register_constraint "B" "TARGET_MPX ? BND_REGS : NO_REGS" |
95 | "@internal Any bound register.") | |
96 | ||
50961141 | 97 | ;; We use the Y prefix to denote any number of conditional register sets: |
e2520c41 | 98 | ;; z First SSE register. |
00fcb892 UB |
99 | ;; i SSE2 inter-unit moves to SSE register enabled |
100 | ;; j SSE2 inter-unit moves from SSE register enabled | |
101 | ;; m MMX inter-unit moves to MMX register enabled | |
102 | ;; n MMX inter-unit moves from MMX register enabled | |
904eea2c | 103 | ;; a Integer register when zero extensions with AND are disabled |
78d8c16c | 104 | ;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled |
479fecd3 UB |
105 | ;; d Integer register when integer DFmode moves are enabled |
106 | ;; x Integer register when integer XFmode moves are enabled | |
593c0ddd | 107 | ;; f x87 register when 80387 floating point arithmetic is enabled |
50961141 | 108 | |
e2520c41 | 109 | (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS" |
c3b9a8d6 L |
110 | "First SSE register (@code{%xmm0}).") |
111 | ||
50961141 | 112 | (define_register_constraint "Yi" |
3f97cb0b | 113 | "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC ? ALL_SSE_REGS : NO_REGS" |
00fcb892 UB |
114 | "@internal Any SSE register, when SSE2 and inter-unit moves to vector registers are enabled.") |
115 | ||
116 | (define_register_constraint "Yj" | |
3f97cb0b | 117 | "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_FROM_VEC ? ALL_SSE_REGS : NO_REGS" |
00fcb892 | 118 | "@internal Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled.") |
08b1e29a | 119 | |
ed69105c | 120 | (define_register_constraint "Ym" |
00fcb892 UB |
121 | "TARGET_MMX && TARGET_INTER_UNIT_MOVES_TO_VEC ? MMX_REGS : NO_REGS" |
122 | "@internal Any MMX register, when inter-unit moves to vector registers are enabled.") | |
123 | ||
124 | (define_register_constraint "Yn" | |
125 | "TARGET_MMX && TARGET_INTER_UNIT_MOVES_FROM_VEC ? MMX_REGS : NO_REGS" | |
126 | "@internal Any MMX register, when inter-unit moves from vector registers are enabled.") | |
ed69105c | 127 | |
78d8c16c UB |
128 | (define_register_constraint "Yp" |
129 | "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS" | |
130 | "@internal Any integer register when TARGET_PARTIAL_REG_STALL is disabled.") | |
131 | ||
904eea2c UB |
132 | (define_register_constraint "Ya" |
133 | "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun) | |
134 | ? NO_REGS : GENERAL_REGS" | |
135 | "@internal Any integer register when zero extensions with AND are disabled.") | |
136 | ||
479fecd3 | 137 | (define_register_constraint "Yd" |
286fb677 | 138 | "TARGET_INTEGER_DFMODE_MOVES && optimize_function_for_speed_p (cfun) |
b17d5426 | 139 | ? GENERAL_REGS : NO_REGS" |
479fecd3 UB |
140 | "@internal Any integer register when integer DFmode moves are enabled.") |
141 | ||
142 | (define_register_constraint "Yx" | |
143 | "optimize_function_for_speed_p (cfun) ? GENERAL_REGS : NO_REGS" | |
144 | "@internal Any integer register when integer XFmode moves are enabled.") | |
145 | ||
593c0ddd UB |
146 | (define_register_constraint "Yf" |
147 | "(ix86_fpmath & FPMATH_387) ? FLOAT_REGS : NO_REGS" | |
148 | "@internal Any x87 register when 80387 FP arithmetic is enabled.") | |
149 | ||
3f97cb0b AI |
150 | (define_register_constraint "v" "TARGET_SSE ? ALL_SSE_REGS : NO_REGS" |
151 | "Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).") | |
152 | ||
f6449011 | 153 | (define_constraint "z" |
4bc2a7a7 | 154 | "@internal Constant call address operand." |
f6449011 UB |
155 | (match_operand 0 "constant_call_address_operand")) |
156 | ||
6025b127 L |
157 | (define_constraint "w" |
158 | "@internal Call memory operand." | |
67b2c493 | 159 | (and (not (match_test "TARGET_X32")) |
6025b127 L |
160 | (match_operand 0 "memory_operand"))) |
161 | ||
08b1e29a RS |
162 | ;; Integer constant constraints. |
163 | (define_constraint "I" | |
164 | "Integer constant in the range 0 @dots{} 31, for 32-bit shifts." | |
165 | (and (match_code "const_int") | |
8dde5924 | 166 | (match_test "IN_RANGE (ival, 0, 31)"))) |
08b1e29a RS |
167 | |
168 | (define_constraint "J" | |
169 | "Integer constant in the range 0 @dots{} 63, for 64-bit shifts." | |
170 | (and (match_code "const_int") | |
8dde5924 | 171 | (match_test "IN_RANGE (ival, 0, 63)"))) |
08b1e29a RS |
172 | |
173 | (define_constraint "K" | |
174 | "Signed 8-bit integer constant." | |
175 | (and (match_code "const_int") | |
8dde5924 | 176 | (match_test "IN_RANGE (ival, -128, 127)"))) |
08b1e29a RS |
177 | |
178 | (define_constraint "L" | |
f148a434 UB |
179 | "@code{0xFF}, @code{0xFFFF} or @code{0xFFFFFFFF} |
180 | for AND as a zero-extending move." | |
08b1e29a | 181 | (and (match_code "const_int") |
f148a434 UB |
182 | (match_test "ival == 0xff || ival == 0xffff |
183 | || ival == (HOST_WIDE_INT) 0xffffffff"))) | |
08b1e29a RS |
184 | |
185 | (define_constraint "M" | |
186 | "0, 1, 2, or 3 (shifts for the @code{lea} instruction)." | |
187 | (and (match_code "const_int") | |
8dde5924 | 188 | (match_test "IN_RANGE (ival, 0, 3)"))) |
08b1e29a RS |
189 | |
190 | (define_constraint "N" | |
4f3f76e6 | 191 | "Unsigned 8-bit integer constant (for @code{in} and @code{out} |
08b1e29a RS |
192 | instructions)." |
193 | (and (match_code "const_int") | |
8dde5924 | 194 | (match_test "IN_RANGE (ival, 0, 255)"))) |
08b1e29a RS |
195 | |
196 | (define_constraint "O" | |
197 | "@internal Integer constant in the range 0 @dots{} 127, for 128-bit shifts." | |
198 | (and (match_code "const_int") | |
8dde5924 | 199 | (match_test "IN_RANGE (ival, 0, 127)"))) |
08b1e29a RS |
200 | |
201 | ;; Floating-point constant constraints. | |
202 | ;; We allow constants even if TARGET_80387 isn't set, because the | |
203 | ;; stack register converter may need to load 0.0 into the function | |
204 | ;; value register (top of stack). | |
205 | (define_constraint "G" | |
206 | "Standard 80387 floating point constant." | |
207 | (and (match_code "const_double") | |
479fecd3 | 208 | (match_test "standard_80387_constant_p (op) > 0"))) |
08b1e29a RS |
209 | |
210 | ;; This can theoretically be any mode's CONST0_RTX. | |
211 | (define_constraint "C" | |
212 | "Standard SSE floating point constant." | |
213 | (match_test "standard_sse_constant_p (op)")) | |
214 | ||
215 | ;; Constant-or-symbol-reference constraints. | |
216 | ||
217 | (define_constraint "e" | |
218 | "32-bit signed integer constant, or a symbolic reference known | |
219 | to fit that range (for immediate operands in sign-extending x86-64 | |
220 | instructions)." | |
221 | (match_operand 0 "x86_64_immediate_operand")) | |
222 | ||
3cb2b15b UB |
223 | ;; We use W prefix to denote any number of |
224 | ;; constant-or-symbol-reference constraints | |
225 | ||
226 | (define_constraint "Wz" | |
227 | "32-bit unsigned integer constant, or a symbolic reference known | |
228 | to fit that range (for zero-extending conversion operations that | |
229 | require non-VOIDmode immediate operands)." | |
230 | (and (match_operand 0 "x86_64_zext_immediate_operand") | |
231 | (match_test "GET_MODE (op) != VOIDmode"))) | |
232 | ||
08b1e29a RS |
233 | (define_constraint "Z" |
234 | "32-bit unsigned integer constant, or a symbolic reference known | |
235 | to fit that range (for immediate operands in zero-extending x86-64 | |
236 | instructions)." | |
237 | (match_operand 0 "x86_64_zext_immediate_operand")) | |
66d6cbaa IE |
238 | |
239 | ;; T prefix is used for different address constraints | |
240 | ;; i - address with no index and no rip | |
241 | ;; b - address with no base and no rip | |
242 | ||
243 | (define_address_constraint "Ti" | |
244 | "MPX address operand without index" | |
245 | (match_operand 0 "address_mpx_no_index_operand")) | |
246 | ||
247 | (define_address_constraint "Tb" | |
248 | "MPX address operand without base" | |
249 | (match_operand 0 "address_mpx_no_base_operand")) |