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08b1e29a | 1 | ;; Constraint definitions for IA-32 and x86-64. |
818ab71a | 2 | ;; Copyright (C) 2006-2016 Free Software Foundation, Inc. |
08b1e29a RS |
3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
2f83c7d6 | 8 | ;; the Free Software Foundation; either version 3, or (at your option) |
08b1e29a RS |
9 | ;; any later version. |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
17 | ;; along with GCC; see the file COPYING3. If not see |
18 | ;; <http://www.gnu.org/licenses/>. | |
08b1e29a RS |
19 | |
20 | ;;; Unused letters: | |
6041d142 | 21 | ;;; H |
d5e254e1 | 22 | ;;; h j z |
08b1e29a RS |
23 | |
24 | ;; Integer register constraints. | |
25 | ;; It is not necessary to define 'r' here. | |
26 | (define_register_constraint "R" "LEGACY_REGS" | |
27 | "Legacy register---the eight integer registers available on all | |
28 | i386 processors (@code{a}, @code{b}, @code{c}, @code{d}, | |
29 | @code{si}, @code{di}, @code{bp}, @code{sp}).") | |
30 | ||
31 | (define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS" | |
32 | "Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a}, | |
33 | @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.") | |
34 | ||
35 | (define_register_constraint "Q" "Q_REGS" | |
36 | "Any register accessible as @code{@var{r}h}: @code{a}, @code{b}, | |
37 | @code{c}, and @code{d}.") | |
38 | ||
39 | (define_register_constraint "l" "INDEX_REGS" | |
40 | "@internal Any register that can be used as the index in a base+index | |
41 | memory access: that is, any general register except the stack pointer.") | |
42 | ||
43 | (define_register_constraint "a" "AREG" | |
44 | "The @code{a} register.") | |
45 | ||
46 | (define_register_constraint "b" "BREG" | |
47 | "The @code{b} register.") | |
48 | ||
49 | (define_register_constraint "c" "CREG" | |
50 | "The @code{c} register.") | |
51 | ||
52 | (define_register_constraint "d" "DREG" | |
53 | "The @code{d} register.") | |
54 | ||
55 | (define_register_constraint "S" "SIREG" | |
56 | "The @code{si} register.") | |
57 | ||
58 | (define_register_constraint "D" "DIREG" | |
59 | "The @code{di} register.") | |
60 | ||
61 | (define_register_constraint "A" "AD_REGS" | |
62 | "The @code{a} and @code{d} registers, as a pair (for instructions | |
63 | that return half the result in one and half in the other).") | |
64 | ||
ac2e563f RH |
65 | (define_register_constraint "U" "CLOBBERED_REGS" |
66 | "The call-clobbered integer registers.") | |
67 | ||
08b1e29a RS |
68 | ;; Floating-point register constraints. |
69 | (define_register_constraint "f" | |
70 | "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FLOAT_REGS : NO_REGS" | |
71 | "Any 80387 floating-point (stack) register.") | |
72 | ||
73 | (define_register_constraint "t" | |
74 | "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_TOP_REG : NO_REGS" | |
75 | "Top of 80387 floating-point stack (@code{%st(0)}).") | |
76 | ||
77 | (define_register_constraint "u" | |
78 | "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS" | |
79 | "Second from top of 80387 floating-point stack (@code{%st(1)}).") | |
80 | ||
be792bce | 81 | (define_register_constraint "Yk" "TARGET_AVX512F ? MASK_EVEX_REGS : NO_REGS" |
85a77221 AI |
82 | "@internal Any mask register that can be used as predicate, i.e. k1-k7.") |
83 | ||
be792bce | 84 | (define_register_constraint "k" "TARGET_AVX512F ? MASK_REGS : NO_REGS" |
85a77221 AI |
85 | "@internal Any mask register.") |
86 | ||
08b1e29a RS |
87 | ;; Vector registers (also used for plain floating point nowadays). |
88 | (define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS" | |
89 | "Any MMX register.") | |
90 | ||
91 | (define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS" | |
92 | "Any SSE register.") | |
93 | ||
1828d3e6 UB |
94 | (define_register_constraint "v" "TARGET_SSE ? ALL_SSE_REGS : NO_REGS" |
95 | "Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).") | |
96 | ||
d5e254e1 IE |
97 | (define_register_constraint "w" "TARGET_MPX ? BND_REGS : NO_REGS" |
98 | "@internal Any bound register.") | |
99 | ||
50961141 | 100 | ;; We use the Y prefix to denote any number of conditional register sets: |
e2520c41 | 101 | ;; z First SSE register. |
00fcb892 UB |
102 | ;; i SSE2 inter-unit moves to SSE register enabled |
103 | ;; j SSE2 inter-unit moves from SSE register enabled | |
104 | ;; m MMX inter-unit moves to MMX register enabled | |
105 | ;; n MMX inter-unit moves from MMX register enabled | |
904eea2c | 106 | ;; a Integer register when zero extensions with AND are disabled |
78d8c16c | 107 | ;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled |
593c0ddd | 108 | ;; f x87 register when 80387 floating point arithmetic is enabled |
45392c76 IE |
109 | ;; r SSE regs not requiring REX prefix when prefixes avoidance is enabled |
110 | ;; and all SSE regs otherwise | |
50961141 | 111 | |
e2520c41 | 112 | (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS" |
c3b9a8d6 L |
113 | "First SSE register (@code{%xmm0}).") |
114 | ||
50961141 | 115 | (define_register_constraint "Yi" |
3f97cb0b | 116 | "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC ? ALL_SSE_REGS : NO_REGS" |
00fcb892 UB |
117 | "@internal Any SSE register, when SSE2 and inter-unit moves to vector registers are enabled.") |
118 | ||
119 | (define_register_constraint "Yj" | |
3f97cb0b | 120 | "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_FROM_VEC ? ALL_SSE_REGS : NO_REGS" |
00fcb892 | 121 | "@internal Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled.") |
08b1e29a | 122 | |
ed69105c | 123 | (define_register_constraint "Ym" |
00fcb892 UB |
124 | "TARGET_MMX && TARGET_INTER_UNIT_MOVES_TO_VEC ? MMX_REGS : NO_REGS" |
125 | "@internal Any MMX register, when inter-unit moves to vector registers are enabled.") | |
126 | ||
127 | (define_register_constraint "Yn" | |
128 | "TARGET_MMX && TARGET_INTER_UNIT_MOVES_FROM_VEC ? MMX_REGS : NO_REGS" | |
129 | "@internal Any MMX register, when inter-unit moves from vector registers are enabled.") | |
ed69105c | 130 | |
78d8c16c UB |
131 | (define_register_constraint "Yp" |
132 | "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS" | |
133 | "@internal Any integer register when TARGET_PARTIAL_REG_STALL is disabled.") | |
134 | ||
904eea2c UB |
135 | (define_register_constraint "Ya" |
136 | "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun) | |
137 | ? NO_REGS : GENERAL_REGS" | |
138 | "@internal Any integer register when zero extensions with AND are disabled.") | |
139 | ||
593c0ddd UB |
140 | (define_register_constraint "Yf" |
141 | "(ix86_fpmath & FPMATH_387) ? FLOAT_REGS : NO_REGS" | |
142 | "@internal Any x87 register when 80387 FP arithmetic is enabled.") | |
143 | ||
45392c76 IE |
144 | (define_register_constraint "Yr" |
145 | "TARGET_SSE ? (X86_TUNE_AVOID_4BYTE_PREFIXES ? NO_REX_SSE_REGS : ALL_SSE_REGS) : NO_REGS" | |
146 | "@internal Lower SSE register when avoiding REX prefix and all SSE registers otherwise.") | |
147 | ||
40bd4bf9 JJ |
148 | (define_register_constraint "Yv" |
149 | "TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS" | |
150 | "@internal For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), otherwise any SSE register.") | |
151 | ||
1828d3e6 | 152 | ;; We use the B prefix to denote any number of internal operands: |
f767f583 | 153 | ;; f FLAGS_REG |
f70d27e0 | 154 | ;; g GOT memory operand. |
3f50525d | 155 | ;; m Vector memory operand |
1828d3e6 UB |
156 | ;; s Sibcall memory operand, not valid for TARGET_X32 |
157 | ;; w Call memory operand, not valid for TARGET_X32 | |
158 | ;; z Constant call address operand. | |
aec0b19e | 159 | ;; C SSE constant operand. |
6041d142 | 160 | |
f767f583 RH |
161 | (define_constraint "Bf" |
162 | "@internal Flags register operand." | |
163 | (match_operand 0 "flags_reg_operand")) | |
164 | ||
f70d27e0 L |
165 | (define_constraint "Bg" |
166 | "@internal GOT memory operand." | |
167 | (match_operand 0 "GOT_memory_operand")) | |
168 | ||
9eb1ca69 | 169 | (define_special_memory_constraint "Bm" |
3f50525d L |
170 | "@internal Vector memory operand." |
171 | (match_operand 0 "vector_memory_operand")) | |
172 | ||
6041d142 KT |
173 | (define_constraint "Bs" |
174 | "@internal Sibcall memory operand." | |
fa87d16d L |
175 | (ior (and (not (match_test "TARGET_X32")) |
176 | (match_operand 0 "sibcall_memory_operand")) | |
177 | (and (match_test "TARGET_X32 && Pmode == DImode") | |
178 | (match_operand 0 "GOT_memory_operand")))) | |
6041d142 | 179 | |
1828d3e6 | 180 | (define_constraint "Bw" |
6025b127 | 181 | "@internal Call memory operand." |
fa87d16d L |
182 | (ior (and (not (match_test "TARGET_X32")) |
183 | (match_operand 0 "memory_operand")) | |
184 | (and (match_test "TARGET_X32 && Pmode == DImode") | |
185 | (match_operand 0 "GOT_memory_operand")))) | |
6025b127 | 186 | |
1828d3e6 UB |
187 | (define_constraint "Bz" |
188 | "@internal Constant call address operand." | |
189 | (match_operand 0 "constant_call_address_operand")) | |
190 | ||
aec0b19e | 191 | (define_constraint "BC" |
90f82260 | 192 | "@internal SSE constant -1 operand." |
55284a77 | 193 | (and (match_test "TARGET_SSE") |
90f82260 | 194 | (ior (match_test "op == constm1_rtx") |
55284a77 | 195 | (match_operand 0 "vector_all_ones_operand")))) |
aec0b19e | 196 | |
08b1e29a RS |
197 | ;; Integer constant constraints. |
198 | (define_constraint "I" | |
199 | "Integer constant in the range 0 @dots{} 31, for 32-bit shifts." | |
200 | (and (match_code "const_int") | |
8dde5924 | 201 | (match_test "IN_RANGE (ival, 0, 31)"))) |
08b1e29a RS |
202 | |
203 | (define_constraint "J" | |
204 | "Integer constant in the range 0 @dots{} 63, for 64-bit shifts." | |
205 | (and (match_code "const_int") | |
8dde5924 | 206 | (match_test "IN_RANGE (ival, 0, 63)"))) |
08b1e29a RS |
207 | |
208 | (define_constraint "K" | |
209 | "Signed 8-bit integer constant." | |
210 | (and (match_code "const_int") | |
8dde5924 | 211 | (match_test "IN_RANGE (ival, -128, 127)"))) |
08b1e29a RS |
212 | |
213 | (define_constraint "L" | |
f148a434 UB |
214 | "@code{0xFF}, @code{0xFFFF} or @code{0xFFFFFFFF} |
215 | for AND as a zero-extending move." | |
08b1e29a | 216 | (and (match_code "const_int") |
f148a434 UB |
217 | (match_test "ival == 0xff || ival == 0xffff |
218 | || ival == (HOST_WIDE_INT) 0xffffffff"))) | |
08b1e29a RS |
219 | |
220 | (define_constraint "M" | |
221 | "0, 1, 2, or 3 (shifts for the @code{lea} instruction)." | |
222 | (and (match_code "const_int") | |
8dde5924 | 223 | (match_test "IN_RANGE (ival, 0, 3)"))) |
08b1e29a RS |
224 | |
225 | (define_constraint "N" | |
4f3f76e6 | 226 | "Unsigned 8-bit integer constant (for @code{in} and @code{out} |
08b1e29a RS |
227 | instructions)." |
228 | (and (match_code "const_int") | |
8dde5924 | 229 | (match_test "IN_RANGE (ival, 0, 255)"))) |
08b1e29a RS |
230 | |
231 | (define_constraint "O" | |
232 | "@internal Integer constant in the range 0 @dots{} 127, for 128-bit shifts." | |
233 | (and (match_code "const_int") | |
8dde5924 | 234 | (match_test "IN_RANGE (ival, 0, 127)"))) |
08b1e29a RS |
235 | |
236 | ;; Floating-point constant constraints. | |
237 | ;; We allow constants even if TARGET_80387 isn't set, because the | |
238 | ;; stack register converter may need to load 0.0 into the function | |
239 | ;; value register (top of stack). | |
240 | (define_constraint "G" | |
241 | "Standard 80387 floating point constant." | |
242 | (and (match_code "const_double") | |
479fecd3 | 243 | (match_test "standard_80387_constant_p (op) > 0"))) |
08b1e29a RS |
244 | |
245 | ;; This can theoretically be any mode's CONST0_RTX. | |
246 | (define_constraint "C" | |
aec0b19e | 247 | "SSE constant zero operand." |
55284a77 UB |
248 | (and (match_test "TARGET_SSE") |
249 | (ior (match_test "op == const0_rtx") | |
250 | (match_operand 0 "const0_operand")))) | |
08b1e29a RS |
251 | |
252 | ;; Constant-or-symbol-reference constraints. | |
253 | ||
254 | (define_constraint "e" | |
255 | "32-bit signed integer constant, or a symbolic reference known | |
256 | to fit that range (for immediate operands in sign-extending x86-64 | |
257 | instructions)." | |
258 | (match_operand 0 "x86_64_immediate_operand")) | |
259 | ||
3cb2b15b UB |
260 | ;; We use W prefix to denote any number of |
261 | ;; constant-or-symbol-reference constraints | |
262 | ||
d1873c57 JJ |
263 | (define_constraint "We" |
264 | "32-bit signed integer constant, or a symbolic reference known | |
265 | to fit that range (for sign-extending conversion operations that | |
266 | require non-VOIDmode immediate operands)." | |
267 | (and (match_operand 0 "x86_64_immediate_operand") | |
268 | (match_test "GET_MODE (op) != VOIDmode"))) | |
269 | ||
3cb2b15b UB |
270 | (define_constraint "Wz" |
271 | "32-bit unsigned integer constant, or a symbolic reference known | |
272 | to fit that range (for zero-extending conversion operations that | |
273 | require non-VOIDmode immediate operands)." | |
274 | (and (match_operand 0 "x86_64_zext_immediate_operand") | |
275 | (match_test "GET_MODE (op) != VOIDmode"))) | |
276 | ||
31ed1665 JJ |
277 | (define_constraint "Wd" |
278 | "128-bit integer constant where both the high and low 64-bit word | |
279 | of it satisfies the e constraint." | |
280 | (match_operand 0 "x86_64_hilo_int_operand")) | |
281 | ||
08b1e29a RS |
282 | (define_constraint "Z" |
283 | "32-bit unsigned integer constant, or a symbolic reference known | |
284 | to fit that range (for immediate operands in zero-extending x86-64 | |
285 | instructions)." | |
286 | (match_operand 0 "x86_64_zext_immediate_operand")) | |
66d6cbaa IE |
287 | |
288 | ;; T prefix is used for different address constraints | |
65e95828 UB |
289 | ;; v - VSIB address |
290 | ;; s - address with no segment register | |
d5e254e1 IE |
291 | ;; i - address with no index and no rip |
292 | ;; b - address with no base and no rip | |
66d6cbaa | 293 | |
65e95828 UB |
294 | (define_address_constraint "Tv" |
295 | "VSIB address operand" | |
296 | (match_operand 0 "vsib_address_operand")) | |
297 | ||
298 | (define_address_constraint "Ts" | |
299 | "Address operand without segment register" | |
300 | (match_operand 0 "address_no_seg_operand")) | |
d5e254e1 IE |
301 | |
302 | (define_address_constraint "Ti" | |
303 | "MPX address operand without index" | |
304 | (match_operand 0 "address_mpx_no_index_operand")) | |
305 | ||
306 | (define_address_constraint "Tb" | |
307 | "MPX address operand without base" | |
308 | (match_operand 0 "address_mpx_no_base_operand")) |