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c60dcd8c | 1 | ;; Constraint definitions for IA-32 and x86-64. |
fbd26352 | 2 | ;; Copyright (C) 2006-2019 Free Software Foundation, Inc. |
c60dcd8c | 3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
038d1e19 | 8 | ;; the Free Software Foundation; either version 3, or (at your option) |
c60dcd8c | 9 | ;; any later version. |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
038d1e19 | 17 | ;; along with GCC; see the file COPYING3. If not see |
18 | ;; <http://www.gnu.org/licenses/>. | |
c60dcd8c | 19 | |
20 | ;;; Unused letters: | |
31916c59 | 21 | ;;; H |
058a1b7a | 22 | ;;; h j z |
c60dcd8c | 23 | |
24 | ;; Integer register constraints. | |
25 | ;; It is not necessary to define 'r' here. | |
26 | (define_register_constraint "R" "LEGACY_REGS" | |
27 | "Legacy register---the eight integer registers available on all | |
28 | i386 processors (@code{a}, @code{b}, @code{c}, @code{d}, | |
29 | @code{si}, @code{di}, @code{bp}, @code{sp}).") | |
30 | ||
31 | (define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS" | |
32 | "Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a}, | |
33 | @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.") | |
34 | ||
35 | (define_register_constraint "Q" "Q_REGS" | |
36 | "Any register accessible as @code{@var{r}h}: @code{a}, @code{b}, | |
37 | @code{c}, and @code{d}.") | |
38 | ||
39 | (define_register_constraint "l" "INDEX_REGS" | |
40 | "@internal Any register that can be used as the index in a base+index | |
41 | memory access: that is, any general register except the stack pointer.") | |
42 | ||
43 | (define_register_constraint "a" "AREG" | |
44 | "The @code{a} register.") | |
45 | ||
46 | (define_register_constraint "b" "BREG" | |
47 | "The @code{b} register.") | |
48 | ||
49 | (define_register_constraint "c" "CREG" | |
50 | "The @code{c} register.") | |
51 | ||
52 | (define_register_constraint "d" "DREG" | |
53 | "The @code{d} register.") | |
54 | ||
55 | (define_register_constraint "S" "SIREG" | |
56 | "The @code{si} register.") | |
57 | ||
58 | (define_register_constraint "D" "DIREG" | |
59 | "The @code{di} register.") | |
60 | ||
61 | (define_register_constraint "A" "AD_REGS" | |
62 | "The @code{a} and @code{d} registers, as a pair (for instructions | |
63 | that return half the result in one and half in the other).") | |
64 | ||
fd0652b1 | 65 | (define_register_constraint "U" "CLOBBERED_REGS" |
66 | "The call-clobbered integer registers.") | |
67 | ||
c60dcd8c | 68 | ;; Floating-point register constraints. |
69 | (define_register_constraint "f" | |
70 | "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FLOAT_REGS : NO_REGS" | |
71 | "Any 80387 floating-point (stack) register.") | |
72 | ||
73 | (define_register_constraint "t" | |
74 | "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_TOP_REG : NO_REGS" | |
75 | "Top of 80387 floating-point stack (@code{%st(0)}).") | |
76 | ||
77 | (define_register_constraint "u" | |
78 | "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS" | |
79 | "Second from top of 80387 floating-point stack (@code{%st(1)}).") | |
80 | ||
d115beab | 81 | (define_register_constraint "Yk" "TARGET_AVX512F ? MASK_REGS : NO_REGS" |
28dccb9a | 82 | "@internal Any mask register that can be used as predicate, i.e. k1-k7.") |
83 | ||
d115beab | 84 | (define_register_constraint "k" "TARGET_AVX512F ? ALL_MASK_REGS : NO_REGS" |
28dccb9a | 85 | "@internal Any mask register.") |
86 | ||
c60dcd8c | 87 | ;; Vector registers (also used for plain floating point nowadays). |
88 | (define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS" | |
89 | "Any MMX register.") | |
90 | ||
91 | (define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS" | |
92 | "Any SSE register.") | |
93 | ||
bfc603d6 | 94 | (define_register_constraint "v" "TARGET_SSE ? ALL_SSE_REGS : NO_REGS" |
95 | "Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).") | |
96 | ||
7e777250 | 97 | ;; We use the Y prefix to denote any number of conditional register sets: |
50c9119e | 98 | ;; z First SSE register. |
5b34cd30 | 99 | ;; d any EVEX encodable SSE register for AVX512DQ target or |
cfd918c2 | 100 | ;; any SSE register for SSE4_1 target. |
c8bc2197 | 101 | ;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled |
ad797097 | 102 | ;; a Integer register when zero extensions with AND are disabled |
c7f16cfa | 103 | ;; b Any register that can be used as the GOT base when calling |
104 | ;; ___tls_get_addr: that is, any general register except EAX | |
105 | ;; and ESP, for -fno-plt if linker supports it. Otherwise, | |
106 | ;; EBX. | |
80946863 | 107 | ;; f x87 register when 80387 floating point arithmetic is enabled |
0a32b282 | 108 | ;; r SSE regs not requiring REX prefix when prefixes avoidance is enabled |
109 | ;; and all SSE regs otherwise | |
c8bc2197 | 110 | ;; v any EVEX encodable SSE register for AVX512VL target, |
111 | ;; otherwise any SSE register | |
112 | ;; h EVEX encodable SSE register with number factor of four | |
facda5c9 | 113 | ;; w any EVEX encodable SSE register for AVX512BW with TARGET_AVX512VL |
114 | ;; target. | |
7e777250 | 115 | |
50c9119e | 116 | (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS" |
24f794d7 | 117 | "First SSE register (@code{%xmm0}).") |
118 | ||
c8bc2197 | 119 | (define_register_constraint "Yd" |
cfd918c2 | 120 | "TARGET_AVX512DQ ? ALL_SSE_REGS : TARGET_SSE4_1 ? SSE_REGS : NO_REGS" |
121 | "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target.") | |
c8bc2197 | 122 | |
4480cad1 | 123 | (define_register_constraint "Yp" |
124 | "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS" | |
125 | "@internal Any integer register when TARGET_PARTIAL_REG_STALL is disabled.") | |
126 | ||
ad797097 | 127 | (define_register_constraint "Ya" |
128 | "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun) | |
129 | ? NO_REGS : GENERAL_REGS" | |
130 | "@internal Any integer register when zero extensions with AND are disabled.") | |
131 | ||
c7f16cfa | 132 | (define_register_constraint "Yb" |
133 | "(!flag_plt && HAVE_AS_IX86_TLS_GET_ADDR_GOT) ? TLS_GOTBASE_REGS : BREG" | |
134 | "@internal Any register that can be used as the GOT base when calling | |
135 | ___tls_get_addr: that is, any general register except @code{a} and | |
136 | @code{sp} registers, for -fno-plt if linker supports it. Otherwise, | |
137 | @code{b} register.") | |
138 | ||
80946863 | 139 | (define_register_constraint "Yf" |
140 | "(ix86_fpmath & FPMATH_387) ? FLOAT_REGS : NO_REGS" | |
141 | "@internal Any x87 register when 80387 FP arithmetic is enabled.") | |
142 | ||
0a32b282 | 143 | (define_register_constraint "Yr" |
83dd281d | 144 | "TARGET_SSE ? (TARGET_AVOID_4BYTE_PREFIXES ? NO_REX_SSE_REGS : ALL_SSE_REGS) : NO_REGS" |
0a32b282 | 145 | "@internal Lower SSE register when avoiding REX prefix and all SSE registers otherwise.") |
146 | ||
e10946d5 | 147 | (define_register_constraint "Yv" |
148 | "TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS" | |
149 | "@internal For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), otherwise any SSE register.") | |
150 | ||
facda5c9 | 151 | (define_register_constraint "Yw" |
152 | "TARGET_AVX512BW && TARGET_AVX512VL ? ALL_SSE_REGS : NO_REGS" | |
153 | "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW with TARGET_AVX512VL target.") | |
154 | ||
bfc603d6 | 155 | ;; We use the B prefix to denote any number of internal operands: |
2b40f9ba | 156 | ;; f FLAGS_REG |
38e98f58 | 157 | ;; g GOT memory operand. |
ea87c5e3 | 158 | ;; m Vector memory operand |
4e254cac | 159 | ;; c Constant memory operand |
5512cec3 | 160 | ;; n Memory operand without REX prefix |
bfc603d6 | 161 | ;; s Sibcall memory operand, not valid for TARGET_X32 |
162 | ;; w Call memory operand, not valid for TARGET_X32 | |
163 | ;; z Constant call address operand. | |
f11bb279 | 164 | ;; C SSE constant operand. |
31916c59 | 165 | |
2b40f9ba | 166 | (define_constraint "Bf" |
167 | "@internal Flags register operand." | |
168 | (match_operand 0 "flags_reg_operand")) | |
169 | ||
38e98f58 | 170 | (define_constraint "Bg" |
171 | "@internal GOT memory operand." | |
172 | (match_operand 0 "GOT_memory_operand")) | |
173 | ||
6b3b345a | 174 | (define_special_memory_constraint "Bm" |
ea87c5e3 | 175 | "@internal Vector memory operand." |
176 | (match_operand 0 "vector_memory_operand")) | |
177 | ||
4e254cac | 178 | (define_special_memory_constraint "Bc" |
179 | "@internal Constant memory operand." | |
180 | (and (match_operand 0 "memory_operand") | |
181 | (match_test "constant_address_p (XEXP (op, 0))"))) | |
182 | ||
5512cec3 | 183 | (define_special_memory_constraint "Bn" |
184 | "@internal Memory operand without REX prefix." | |
185 | (match_operand 0 "norex_memory_operand")) | |
186 | ||
31916c59 | 187 | (define_constraint "Bs" |
188 | "@internal Sibcall memory operand." | |
3984c138 | 189 | (ior (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER")) |
208fd77a | 190 | (not (match_test "TARGET_X32")) |
e21f9587 | 191 | (match_operand 0 "sibcall_memory_operand")) |
208fd77a | 192 | (and (match_test "TARGET_X32 && Pmode == DImode") |
e21f9587 | 193 | (match_operand 0 "GOT_memory_operand")))) |
31916c59 | 194 | |
bfc603d6 | 195 | (define_constraint "Bw" |
9636738d | 196 | "@internal Call memory operand." |
3984c138 | 197 | (ior (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER")) |
208fd77a | 198 | (not (match_test "TARGET_X32")) |
e21f9587 | 199 | (match_operand 0 "memory_operand")) |
208fd77a | 200 | (and (match_test "TARGET_X32 && Pmode == DImode") |
e21f9587 | 201 | (match_operand 0 "GOT_memory_operand")))) |
9636738d | 202 | |
bfc603d6 | 203 | (define_constraint "Bz" |
204 | "@internal Constant call address operand." | |
205 | (match_operand 0 "constant_call_address_operand")) | |
206 | ||
f11bb279 | 207 | (define_constraint "BC" |
f0dc3286 | 208 | "@internal SSE constant -1 operand." |
d89423c1 | 209 | (and (match_test "TARGET_SSE") |
f0dc3286 | 210 | (ior (match_test "op == constm1_rtx") |
d89423c1 | 211 | (match_operand 0 "vector_all_ones_operand")))) |
f11bb279 | 212 | |
c60dcd8c | 213 | ;; Integer constant constraints. |
214 | (define_constraint "I" | |
215 | "Integer constant in the range 0 @dots{} 31, for 32-bit shifts." | |
216 | (and (match_code "const_int") | |
4e9abdcc | 217 | (match_test "IN_RANGE (ival, 0, 31)"))) |
c60dcd8c | 218 | |
219 | (define_constraint "J" | |
220 | "Integer constant in the range 0 @dots{} 63, for 64-bit shifts." | |
221 | (and (match_code "const_int") | |
4e9abdcc | 222 | (match_test "IN_RANGE (ival, 0, 63)"))) |
c60dcd8c | 223 | |
224 | (define_constraint "K" | |
225 | "Signed 8-bit integer constant." | |
226 | (and (match_code "const_int") | |
4e9abdcc | 227 | (match_test "IN_RANGE (ival, -128, 127)"))) |
c60dcd8c | 228 | |
229 | (define_constraint "L" | |
553c4d0b | 230 | "@code{0xFF}, @code{0xFFFF} or @code{0xFFFFFFFF} |
231 | for AND as a zero-extending move." | |
c60dcd8c | 232 | (and (match_code "const_int") |
553c4d0b | 233 | (match_test "ival == 0xff || ival == 0xffff |
234 | || ival == (HOST_WIDE_INT) 0xffffffff"))) | |
c60dcd8c | 235 | |
236 | (define_constraint "M" | |
237 | "0, 1, 2, or 3 (shifts for the @code{lea} instruction)." | |
238 | (and (match_code "const_int") | |
4e9abdcc | 239 | (match_test "IN_RANGE (ival, 0, 3)"))) |
c60dcd8c | 240 | |
241 | (define_constraint "N" | |
009b318f | 242 | "Unsigned 8-bit integer constant (for @code{in} and @code{out} |
c60dcd8c | 243 | instructions)." |
244 | (and (match_code "const_int") | |
4e9abdcc | 245 | (match_test "IN_RANGE (ival, 0, 255)"))) |
c60dcd8c | 246 | |
247 | (define_constraint "O" | |
248 | "@internal Integer constant in the range 0 @dots{} 127, for 128-bit shifts." | |
249 | (and (match_code "const_int") | |
4e9abdcc | 250 | (match_test "IN_RANGE (ival, 0, 127)"))) |
c60dcd8c | 251 | |
252 | ;; Floating-point constant constraints. | |
253 | ;; We allow constants even if TARGET_80387 isn't set, because the | |
254 | ;; stack register converter may need to load 0.0 into the function | |
255 | ;; value register (top of stack). | |
256 | (define_constraint "G" | |
257 | "Standard 80387 floating point constant." | |
258 | (and (match_code "const_double") | |
ec679bd0 | 259 | (match_test "standard_80387_constant_p (op) > 0"))) |
c60dcd8c | 260 | |
261 | ;; This can theoretically be any mode's CONST0_RTX. | |
262 | (define_constraint "C" | |
a31a2e24 | 263 | "Constant zero operand." |
264 | (ior (match_test "op == const0_rtx") | |
265 | (match_operand 0 "const0_operand"))) | |
c60dcd8c | 266 | |
267 | ;; Constant-or-symbol-reference constraints. | |
268 | ||
269 | (define_constraint "e" | |
270 | "32-bit signed integer constant, or a symbolic reference known | |
271 | to fit that range (for immediate operands in sign-extending x86-64 | |
272 | instructions)." | |
273 | (match_operand 0 "x86_64_immediate_operand")) | |
274 | ||
259ad1be | 275 | ;; We use W prefix to denote any number of |
276 | ;; constant-or-symbol-reference constraints | |
277 | ||
d1eb2d97 | 278 | (define_constraint "We" |
279 | "32-bit signed integer constant, or a symbolic reference known | |
280 | to fit that range (for sign-extending conversion operations that | |
281 | require non-VOIDmode immediate operands)." | |
282 | (and (match_operand 0 "x86_64_immediate_operand") | |
283 | (match_test "GET_MODE (op) != VOIDmode"))) | |
284 | ||
259ad1be | 285 | (define_constraint "Wz" |
286 | "32-bit unsigned integer constant, or a symbolic reference known | |
287 | to fit that range (for zero-extending conversion operations that | |
288 | require non-VOIDmode immediate operands)." | |
289 | (and (match_operand 0 "x86_64_zext_immediate_operand") | |
290 | (match_test "GET_MODE (op) != VOIDmode"))) | |
291 | ||
fe69bcb9 | 292 | (define_constraint "Wd" |
293 | "128-bit integer constant where both the high and low 64-bit word | |
294 | of it satisfies the e constraint." | |
295 | (match_operand 0 "x86_64_hilo_int_operand")) | |
296 | ||
e3f64b6a | 297 | (define_constraint "Wf" |
298 | "32-bit signed integer constant zero extended from word size | |
299 | to double word size." | |
300 | (match_operand 0 "x86_64_dwzext_immediate_operand")) | |
301 | ||
c60dcd8c | 302 | (define_constraint "Z" |
303 | "32-bit unsigned integer constant, or a symbolic reference known | |
304 | to fit that range (for immediate operands in zero-extending x86-64 | |
305 | instructions)." | |
306 | (match_operand 0 "x86_64_zext_immediate_operand")) | |
0b177abb | 307 | |
308 | ;; T prefix is used for different address constraints | |
1e662e65 | 309 | ;; v - VSIB address |
310 | ;; s - address with no segment register | |
058a1b7a | 311 | ;; i - address with no index and no rip |
312 | ;; b - address with no base and no rip | |
0b177abb | 313 | |
1e662e65 | 314 | (define_address_constraint "Tv" |
315 | "VSIB address operand" | |
316 | (match_operand 0 "vsib_address_operand")) | |
317 | ||
318 | (define_address_constraint "Ts" | |
319 | "Address operand without segment register" | |
320 | (match_operand 0 "address_no_seg_operand")) |