[thirdparty/gcc.git] / gcc / config / i386 / cpuid.h

/*
 * Copyright (C) 2007-2020 Free Software Foundation, Inc.
 *
 * This file is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 3, or (at your option) any
 * later version.
 * 
 * This file is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 * 
 * Under Section 7 of GPL version 3, you are granted additional
 * permissions described in the GCC Runtime Library Exception, version
 * 3.1, as published by the Free Software Foundation.
 * 
 * You should have received a copy of the GNU General Public License and
 * a copy of the GCC Runtime Library Exception along with this program;
 * see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 * <http://www.gnu.org/licenses/>.
 */

/* %eax */
#define bit_AVX512BF16	(1 << 5)

/* %ecx */
#define bit_SSE3	(1 << 0)
#define bit_PCLMUL	(1 << 1)
#define bit_LZCNT	(1 << 5)
#define bit_SSSE3	(1 << 9)
#define bit_FMA		(1 << 12)
#define bit_CMPXCHG16B	(1 << 13)
#define bit_SSE4_1	(1 << 19)
#define bit_SSE4_2	(1 << 20)
#define bit_MOVBE	(1 << 22)
#define bit_POPCNT	(1 << 23)
#define bit_AES		(1 << 25)
#define bit_XSAVE	(1 << 26)
#define bit_OSXSAVE	(1 << 27)
#define bit_AVX		(1 << 28)
#define bit_F16C	(1 << 29)
#define bit_RDRND	(1 << 30)

/* %edx */
#define bit_CMPXCHG8B	(1 << 8)
#define bit_CMOV	(1 << 15)
#define bit_MMX		(1 << 23)
#define bit_FXSAVE	(1 << 24)
#define bit_SSE		(1 << 25)
#define bit_SSE2	(1 << 26)

/* Extended Features (%eax == 0x80000001) */
/* %ecx */
#define bit_LAHF_LM	(1 << 0)
#define bit_ABM		(1 << 5)
#define bit_SSE4a	(1 << 6)
#define bit_PRFCHW	(1 << 8)
#define bit_XOP         (1 << 11)
#define bit_LWP 	(1 << 15)
#define bit_FMA4        (1 << 16)
#define bit_TBM         (1 << 21)
#define bit_MWAITX      (1 << 29)

/* %edx */
#define bit_MMXEXT	(1 << 22)
#define bit_LM		(1 << 29)
#define bit_3DNOWP	(1 << 30)
#define bit_3DNOW	(1u << 31)

/* %ebx  */
#define bit_CLZERO	(1 << 0)
#define bit_WBNOINVD	(1 << 9)

/* Extended Features (%eax == 7) */
/* %ebx */
#define bit_FSGSBASE	(1 << 0)
#define bit_SGX (1 << 2)
#define bit_BMI	(1 << 3)
#define bit_HLE	(1 << 4)
#define bit_AVX2	(1 << 5)
#define bit_BMI2	(1 << 8)
#define bit_RTM	(1 << 11)
#define bit_MPX	(1 << 14)
#define bit_AVX512F	(1 << 16)
#define bit_AVX512DQ	(1 << 17)
#define bit_RDSEED	(1 << 18)
#define bit_ADX	(1 << 19)
#define bit_AVX512IFMA	(1 << 21)
#define bit_CLFLUSHOPT	(1 << 23)
#define bit_CLWB	(1 << 24)
#define bit_AVX512PF	(1 << 26)
#define bit_AVX512ER	(1 << 27)
#define bit_AVX512CD	(1 << 28)
#define bit_SHA		(1 << 29)
#define bit_AVX512BW	(1 << 30)
#define bit_AVX512VL	(1u << 31)

/* %ecx */
#define bit_PREFETCHWT1	  (1 << 0)
#define bit_AVX512VBMI	(1 << 1)
#define bit_PKU	(1 << 3)
#define bit_OSPKE	(1 << 4)
#define bit_WAITPKG	(1 << 5)
#define bit_AVX512VBMI2	(1 << 6)
#define bit_SHSTK	(1 << 7)
#define bit_GFNI	(1 << 8)
#define bit_VAES	(1 << 9)
#define bit_AVX512VNNI	(1 << 11)
#define bit_VPCLMULQDQ	(1 << 10)
#define bit_AVX512BITALG	(1 << 12)
#define bit_AVX512VPOPCNTDQ	(1 << 14)
#define bit_RDPID	(1 << 22)
#define bit_MOVDIRI	(1 << 27)
#define bit_MOVDIR64B	(1 << 28)
#define bit_ENQCMD	(1 << 29)
#define bit_CLDEMOTE	(1 << 25)

/* %edx */
#define bit_AVX5124VNNIW (1 << 2)
#define bit_AVX5124FMAPS (1 << 3)
#define bit_AVX512VP2INTERSECT	(1 << 8)
#define bit_IBT	(1 << 20)
#define bit_PCONFIG	(1 << 18)
/* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */
#define bit_BNDREGS     (1 << 3)
#define bit_BNDCSR      (1 << 4)

/* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
#define bit_XSAVEOPT	(1 << 0)
#define bit_XSAVEC	(1 << 1)
#define bit_XSAVES	(1 << 3)

/* PT sub leaf (%eax == 14, %ecx == 0) */
/* %ebx */
#define bit_PTWRITE	(1 << 4)

/* Signatures for different CPU implementations as returned in uses
   of cpuid with level 0.  */
#define signature_AMD_ebx	0x68747541
#define signature_AMD_ecx	0x444d4163
#define signature_AMD_edx	0x69746e65

#define signature_CENTAUR_ebx	0x746e6543
#define signature_CENTAUR_ecx	0x736c7561
#define signature_CENTAUR_edx	0x48727561

#define signature_CYRIX_ebx	0x69727943
#define signature_CYRIX_ecx	0x64616574
#define signature_CYRIX_edx	0x736e4978

#define signature_INTEL_ebx	0x756e6547
#define signature_INTEL_ecx	0x6c65746e
#define signature_INTEL_edx	0x49656e69

#define signature_TM1_ebx	0x6e617254
#define signature_TM1_ecx	0x55504361
#define signature_TM1_edx	0x74656d73

#define signature_TM2_ebx	0x756e6547
#define signature_TM2_ecx	0x3638784d
#define signature_TM2_edx	0x54656e69

#define signature_NSC_ebx	0x646f6547
#define signature_NSC_ecx	0x43534e20
#define signature_NSC_edx	0x79622065

#define signature_NEXGEN_ebx	0x4778654e
#define signature_NEXGEN_ecx	0x6e657669
#define signature_NEXGEN_edx	0x72446e65

#define signature_RISE_ebx	0x65736952
#define signature_RISE_ecx	0x65736952
#define signature_RISE_edx	0x65736952

#define signature_SIS_ebx	0x20536953
#define signature_SIS_ecx	0x20536953
#define signature_SIS_edx	0x20536953

#define signature_UMC_ebx	0x20434d55
#define signature_UMC_ecx	0x20434d55
#define signature_UMC_edx	0x20434d55

#define signature_VIA_ebx	0x20414956
#define signature_VIA_ecx	0x20414956
#define signature_VIA_edx	0x20414956

#define signature_VORTEX_ebx	0x74726f56
#define signature_VORTEX_ecx	0x436f5320
#define signature_VORTEX_edx	0x36387865

#ifndef __x86_64__
/* At least one cpu (Winchip 2) does not set %ebx and %ecx
   for cpuid leaf 1. Forcibly zero the two registers before
   calling cpuid as a precaution.  */
#define __cpuid(level, a, b, c, d)			\
  do {							\
    if (__builtin_constant_p (level) && (level) != 1)	\
      __asm__ ("cpuid\n\t"				\
	      : "=a" (a), "=b" (b), "=c" (c), "=d" (d)	\
	      : "0" (level));				\
    else						\
      __asm__ ("cpuid\n\t"				\
	      : "=a" (a), "=b" (b), "=c" (c), "=d" (d)	\
	      : "0" (level), "1" (0), "2" (0));		\
  } while (0)
#else
#define __cpuid(level, a, b, c, d)			\
  __asm__ ("cpuid\n\t"					\
	   : "=a" (a), "=b" (b), "=c" (c), "=d" (d)	\
	   : "0" (level))
#endif

#define __cpuid_count(level, count, a, b, c, d)		\
  __asm__ ("cpuid\n\t"					\
	   : "=a" (a), "=b" (b), "=c" (c), "=d" (d)	\
	   : "0" (level), "2" (count))


/* Return highest supported input value for cpuid instruction.  ext can
   be either 0x0 or 0x80000000 to return highest supported value for
   basic or extended cpuid information.  Function returns 0 if cpuid
   is not supported or whatever cpuid returns in eax register.  If sig
   pointer is non-null, then first four bytes of the signature
   (as found in ebx register) are returned in location pointed by sig.  */

static __inline unsigned int
__get_cpuid_max (unsigned int __ext, unsigned int *__sig)
{
  unsigned int __eax, __ebx, __ecx, __edx;

#ifndef __x86_64__
  /* See if we can use cpuid.  On AMD64 we always can.  */
#if __GNUC__ >= 3
  __asm__ ("pushf{l|d}\n\t"
	   "pushf{l|d}\n\t"
	   "pop{l}\t%0\n\t"
	   "mov{l}\t{%0, %1|%1, %0}\n\t"
	   "xor{l}\t{%2, %0|%0, %2}\n\t"
	   "push{l}\t%0\n\t"
	   "popf{l|d}\n\t"
	   "pushf{l|d}\n\t"
	   "pop{l}\t%0\n\t"
	   "popf{l|d}\n\t"
	   : "=&r" (__eax), "=&r" (__ebx)
	   : "i" (0x00200000));
#else
/* Host GCCs older than 3.0 weren't supporting Intel asm syntax
   nor alternatives in i386 code.  */
  __asm__ ("pushfl\n\t"
	   "pushfl\n\t"
	   "popl\t%0\n\t"
	   "movl\t%0, %1\n\t"
	   "xorl\t%2, %0\n\t"
	   "pushl\t%0\n\t"
	   "popfl\n\t"
	   "pushfl\n\t"
	   "popl\t%0\n\t"
	   "popfl\n\t"
	   : "=&r" (__eax), "=&r" (__ebx)
	   : "i" (0x00200000));
#endif

  if (!((__eax ^ __ebx) & 0x00200000))
    return 0;
#endif

  /* Host supports cpuid.  Return highest supported cpuid input value.  */
  __cpuid (__ext, __eax, __ebx, __ecx, __edx);

  if (__sig)
    *__sig = __ebx;

  return __eax;
}

/* Return cpuid data for requested cpuid leaf, as found in returned
   eax, ebx, ecx and edx registers.  The function checks if cpuid is
   supported and returns 1 for valid cpuid information or 0 for
   unsupported cpuid leaf.  All pointers are required to be non-null.  */

static __inline int
__get_cpuid (unsigned int __leaf,
	     unsigned int *__eax, unsigned int *__ebx,
	     unsigned int *__ecx, unsigned int *__edx)
{
  unsigned int __ext = __leaf & 0x80000000;
  unsigned int __maxlevel = __get_cpuid_max (__ext, 0);

  if (__maxlevel == 0 || __maxlevel < __leaf)
    return 0;

  __cpuid (__leaf, *__eax, *__ebx, *__ecx, *__edx);
  return 1;
}

/* Same as above, but sub-leaf can be specified.  */

static __inline int
__get_cpuid_count (unsigned int __leaf, unsigned int __subleaf,
		   unsigned int *__eax, unsigned int *__ebx,
		   unsigned int *__ecx, unsigned int *__edx)
{
  unsigned int __ext = __leaf & 0x80000000;
  unsigned int __maxlevel = __get_cpuid_max (__ext, 0);

  if (__maxlevel == 0 || __maxlevel < __leaf)
    return 0;

  __cpuid_count (__leaf, __subleaf, *__eax, *__ebx, *__ecx, *__edx);
  return 1;
}
Commit	Line	Data
b3172cab	1	/*
8d9254fc	2	* Copyright (C) 2007-2020 Free Software Foundation, Inc.
b3172cab UB	3	*
	4	* This file is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License as published by the
748086b7	6	* Free Software Foundation; either version 3, or (at your option) any
b3172cab UB	7	* later version.
b3172cab UB	8	*
b3172cab UB	9	* This file is distributed in the hope that it will be useful, but
	10	* WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	12	* General Public License for more details.
	13	*
748086b7 JJ	14	* Under Section 7 of GPL version 3, you are granted additional
	15	* permissions described in the GCC Runtime Library Exception, version
	16	* 3.1, as published by the Free Software Foundation.
b3172cab	17	*
748086b7 JJ	18	* You should have received a copy of the GNU General Public License and
	19	* a copy of the GCC Runtime Library Exception along with this program;
	20	* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
	21	* <http://www.gnu.org/licenses/>.
b3172cab UB	22	*/
b3172cab UB	23
4f0e90fa HL	24	/* %eax */
	25	#define bit_AVX512BF16 (1 << 5)
	26
b3172cab UB	27	/* %ecx */
b3172cab UB	28	#define bit_SSE3 (1 << 0)
8b96a312	29	#define bit_PCLMUL (1 << 1)
5fcafa60	30	#define bit_LZCNT (1 << 5)
b3172cab	31	#define bit_SSSE3 (1 << 9)
95879c72	32	#define bit_FMA (1 << 12)
b3172cab UB	33	#define bit_CMPXCHG16B (1 << 13)
	34	#define bit_SSE4_1 (1 << 19)
	35	#define bit_SSE4_2 (1 << 20)
cabf85c3	36	#define bit_MOVBE (1 << 22)
b3172cab	37	#define bit_POPCNT (1 << 23)
8b96a312	38	#define bit_AES (1 << 25)
95879c72 L	39	#define bit_XSAVE (1 << 26)
	40	#define bit_OSXSAVE (1 << 27)
	41	#define bit_AVX (1 << 28)
4ee89d5f L	42	#define bit_F16C (1 << 29)
4ee89d5f L	43	#define bit_RDRND (1 << 30)
b3172cab UB	44
	45	/* %edx */
	46	#define bit_CMPXCHG8B (1 << 8)
	47	#define bit_CMOV (1 << 15)
	48	#define bit_MMX (1 << 23)
	49	#define bit_FXSAVE (1 << 24)
	50	#define bit_SSE (1 << 25)
	51	#define bit_SSE2 (1 << 26)
	52
fbed6f36	53	/* Extended Features (%eax == 0x80000001) */
b3172cab UB	54	/* %ecx */
b3172cab UB	55	#define bit_LAHF_LM (1 << 0)
c3d34a78	56	#define bit_ABM (1 << 5)
b3172cab	57	#define bit_SSE4a (1 << 6)
9006f7f3	58	#define bit_PRFCHW (1 << 8)
43a8b705	59	#define bit_XOP (1 << 11)
c3d34a78 SP	60	#define bit_LWP (1 << 15)
c3d34a78 SP	61	#define bit_FMA4 (1 << 16)
94d13ad1	62	#define bit_TBM (1 << 21)
500a08b2	63	#define bit_MWAITX (1 << 29)
b3172cab UB	64
b3172cab UB	65	/* %edx */
ef230b38	66	#define bit_MMXEXT (1 << 22)
b3172cab UB	67	#define bit_LM (1 << 29)
b3172cab UB	68	#define bit_3DNOWP (1 << 30)
f3ffa342	69	#define bit_3DNOW (1u << 31)
b3172cab	70
fbed6f36	71	/* %ebx */
9ce29eb0	72	#define bit_CLZERO (1 << 0)
13b93d4b	73	#define bit_WBNOINVD (1 << 9)
9ce29eb0	74
4ee89d5f	75	/* Extended Features (%eax == 7) */
43b3f52f	76	/* %ebx */
4ee89d5f	77	#define bit_FSGSBASE (1 << 0)
73e32c47	78	#define bit_SGX (1 << 2)
e61c94dd KY	79	#define bit_BMI (1 << 3)
e61c94dd KY	80	#define bit_HLE (1 << 4)
7afac110	81	#define bit_AVX2 (1 << 5)
82feeb8d	82	#define bit_BMI2 (1 << 8)
e61c94dd	83	#define bit_RTM (1 << 11)
c17eac85	84	#define bit_MPX (1 << 14)
3f97cb0b	85	#define bit_AVX512F (1 << 16)
07165dd7	86	#define bit_AVX512DQ (1 << 17)
e61c94dd KY	87	#define bit_RDSEED (1 << 18)
e61c94dd KY	88	#define bit_ADX (1 << 19)
4190ea38	89	#define bit_AVX512IFMA (1 << 21)
9cdea277	90	#define bit_CLFLUSHOPT (1 << 23)
9c3bca11	91	#define bit_CLWB (1 << 24)
3f97cb0b AI	92	#define bit_AVX512PF (1 << 26)
	93	#define bit_AVX512ER (1 << 27)
	94	#define bit_AVX512CD (1 << 28)
c1618f82	95	#define bit_SHA (1 << 29)
b525d943	96	#define bit_AVX512BW (1 << 30)
852a63c5	97	#define bit_AVX512VL (1u << 31)
b3172cab	98
43b3f52f IT	99	/* %ecx */
43b3f52f IT	100	#define bit_PREFETCHWT1 (1 << 0)
3dcc8af5	101	#define bit_AVX512VBMI (1 << 1)
41a4ef22 KY	102	#define bit_PKU (1 << 3)
41a4ef22 KY	103	#define bit_OSPKE (1 << 4)
55f31ed1	104	#define bit_WAITPKG (1 << 5)
fca51879	105	#define bit_AVX512VBMI2 (1 << 6)
2a25448c	106	#define bit_SHSTK (1 << 7)
b8cca31c	107	#define bit_GFNI (1 << 8)
b7b0a4fa	108	#define bit_VAES (1 << 9)
98966963	109	#define bit_AVX512VNNI (1 << 11)
6557be99	110	#define bit_VPCLMULQDQ (1 << 10)
e2a29465	111	#define bit_AVX512BITALG (1 << 12)
fbed6f36	112	#define bit_AVX512VPOPCNTDQ (1 << 14)
1d516992	113	#define bit_RDPID (1 << 22)
37d51c75 SP	114	#define bit_MOVDIRI (1 << 27)
37d51c75 SP	115	#define bit_MOVDIR64B (1 << 28)
6a10feda	116	#define bit_ENQCMD (1 << 29)
f8d9957e	117	#define bit_CLDEMOTE (1 << 25)
fbed6f36 UB	118
	119	/* %edx */
	120	#define bit_AVX5124VNNIW (1 << 2)
	121	#define bit_AVX5124FMAPS (1 << 3)
e21b52af	122	#define bit_AVX512VP2INTERSECT (1 << 8)
2a25448c	123	#define bit_IBT (1 << 20)
13b93d4b	124	#define bit_PCONFIG (1 << 18)
c17eac85 IT	125	/* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */
	126	#define bit_BNDREGS (1 << 3)
	127	#define bit_BNDCSR (1 << 4)
	128
3a0d99bb AI	129	/* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
3a0d99bb AI	130	#define bit_XSAVEOPT (1 << 0)
9cdea277 IT	131	#define bit_XSAVEC (1 << 1)
9cdea277 IT	132	#define bit_XSAVES (1 << 3)
3a0d99bb	133
41f8d1fc AK	134	/* PT sub leaf (%eax == 14, %ecx == 0) */
	135	/* %ebx */
	136	#define bit_PTWRITE (1 << 4)
	137
ef64d158 UD	138	/* Signatures for different CPU implementations as returned in uses
	139	of cpuid with level 0. */
	140	#define signature_AMD_ebx 0x68747541
	141	#define signature_AMD_ecx 0x444d4163
	142	#define signature_AMD_edx 0x69746e65
	143
	144	#define signature_CENTAUR_ebx 0x746e6543
	145	#define signature_CENTAUR_ecx 0x736c7561
	146	#define signature_CENTAUR_edx 0x48727561
	147
	148	#define signature_CYRIX_ebx 0x69727943
	149	#define signature_CYRIX_ecx 0x64616574
	150	#define signature_CYRIX_edx 0x736e4978
	151
	152	#define signature_INTEL_ebx 0x756e6547
	153	#define signature_INTEL_ecx 0x6c65746e
	154	#define signature_INTEL_edx 0x49656e69
	155
	156	#define signature_TM1_ebx 0x6e617254
	157	#define signature_TM1_ecx 0x55504361
	158	#define signature_TM1_edx 0x74656d73
	159
	160	#define signature_TM2_ebx 0x756e6547
	161	#define signature_TM2_ecx 0x3638784d
	162	#define signature_TM2_edx 0x54656e69
	163
	164	#define signature_NSC_ebx 0x646f6547
	165	#define signature_NSC_ecx 0x43534e20
	166	#define signature_NSC_edx 0x79622065
	167
	168	#define signature_NEXGEN_ebx 0x4778654e
	169	#define signature_NEXGEN_ecx 0x6e657669
	170	#define signature_NEXGEN_edx 0x72446e65
	171
	172	#define signature_RISE_ebx 0x65736952
	173	#define signature_RISE_ecx 0x65736952
	174	#define signature_RISE_edx 0x65736952
	175
	176	#define signature_SIS_ebx 0x20536953
	177	#define signature_SIS_ecx 0x20536953
	178	#define signature_SIS_edx 0x20536953
	179
	180	#define signature_UMC_ebx 0x20434d55
	181	#define signature_UMC_ecx 0x20434d55
	182	#define signature_UMC_edx 0x20434d55
	183
	184	#define signature_VIA_ebx 0x20414956
	185	#define signature_VIA_ecx 0x20414956
	186	#define signature_VIA_edx 0x20414956
	187
	188	#define signature_VORTEX_ebx 0x74726f56
	189	#define signature_VORTEX_ecx 0x436f5320
	190	#define signature_VORTEX_edx 0x36387865
	191
8c365be6 UB	192	#ifndef __x86_64__
	193	/* At least one cpu (Winchip 2) does not set %ebx and %ecx
	194	for cpuid leaf 1. Forcibly zero the two registers before
	195	calling cpuid as a precaution. */
	196	#define __cpuid(level, a, b, c, d) \
	197	do { \
	198	if (__builtin_constant_p (level) && (level) != 1) \
	199	__asm__ ("cpuid\n\t" \
	200	: "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
	201	: "0" (level)); \
	202	else \
	203	__asm__ ("cpuid\n\t" \
	204	: "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
	205	: "0" (level), "1" (0), "2" (0)); \
	206	} while (0)
	207	#else
b3172cab UB	208	#define __cpuid(level, a, b, c, d) \
	209	__asm__ ("cpuid\n\t" \
	210	: "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
	211	: "0" (level))
8c365be6	212	#endif
cb0dee88 UB	213
	214	#define __cpuid_count(level, count, a, b, c, d) \
	215	__asm__ ("cpuid\n\t" \
	216	: "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
	217	: "0" (level), "2" (count))
02147868	218
b3172cab UB	219
b3172cab UB	220	/* Return highest supported input value for cpuid instruction. ext can
c9f16151	221	be either 0x0 or 0x80000000 to return highest supported value for
b3172cab UB	222	basic or extended cpuid information. Function returns 0 if cpuid
	223	is not supported or whatever cpuid returns in eax register. If sig
	224	pointer is non-null, then first four bytes of the signature
	225	(as found in ebx register) are returned in location pointed by sig. */
	226
	227	static __inline unsigned int
	228	__get_cpuid_max (unsigned int __ext, unsigned int *__sig)
	229	{
	230	unsigned int __eax, __ebx, __ecx, __edx;
	231
	232	#ifndef __x86_64__
	233	/* See if we can use cpuid. On AMD64 we always can. */
93234e58	234	#if __GNUC__ >= 3
9ad5e54f RIL	235	__asm__ ("pushf{l\|d}\n\t"
	236	"pushf{l\|d}\n\t"
	237	"pop{l}\t%0\n\t"
	238	"mov{l}\t{%0, %1\|%1, %0}\n\t"
	239	"xor{l}\t{%2, %0\|%0, %2}\n\t"
	240	"push{l}\t%0\n\t"
	241	"popf{l\|d}\n\t"
	242	"pushf{l\|d}\n\t"
	243	"pop{l}\t%0\n\t"
	244	"popf{l\|d}\n\t"
b3172cab UB	245	: "=&r" (__eax), "=&r" (__ebx)
b3172cab UB	246	: "i" (0x00200000));
2e834acb JJ	247	#else
	248	/* Host GCCs older than 3.0 weren't supporting Intel asm syntax
	249	nor alternatives in i386 code. */
	250	__asm__ ("pushfl\n\t"
	251	"pushfl\n\t"
	252	"popl\t%0\n\t"
	253	"movl\t%0, %1\n\t"
	254	"xorl\t%2, %0\n\t"
	255	"pushl\t%0\n\t"
	256	"popfl\n\t"
	257	"pushfl\n\t"
	258	"popl\t%0\n\t"
	259	"popfl\n\t"
	260	: "=&r" (__eax), "=&r" (__ebx)
	261	: "i" (0x00200000));
	262	#endif
b3172cab UB	263
	264	if (!((__eax ^ __ebx) & 0x00200000))
	265	return 0;
	266	#endif
	267
	268	/* Host supports cpuid. Return highest supported cpuid input value. */
	269	__cpuid (__ext, __eax, __ebx, __ecx, __edx);
	270
	271	if (__sig)
	272	*__sig = __ebx;
	273
	274	return __eax;
	275	}
	276
2488ebe5	277	/* Return cpuid data for requested cpuid leaf, as found in returned
b3172cab UB	278	eax, ebx, ecx and edx registers. The function checks if cpuid is
b3172cab UB	279	supported and returns 1 for valid cpuid information or 0 for
2488ebe5	280	unsupported cpuid leaf. All pointers are required to be non-null. */
b3172cab UB	281
b3172cab UB	282	static __inline int
2488ebe5	283	__get_cpuid (unsigned int __leaf,
b3172cab UB	284	unsigned int __eax, unsigned int __ebx,
	285	unsigned int __ecx, unsigned int __edx)
	286	{
2488ebe5	287	unsigned int __ext = __leaf & 0x80000000;
a6c78ea3	288	unsigned int __maxlevel = __get_cpuid_max (__ext, 0);
b3172cab	289
a6c78ea3	290	if (__maxlevel == 0 \|\| __maxlevel < __leaf)
b3172cab UB	291	return 0;
b3172cab UB	292
2488ebe5 UB	293	__cpuid (__leaf, __eax, __ebx, __ecx, __edx);
	294	return 1;
	295	}
	296
	297	/* Same as above, but sub-leaf can be specified. */
	298
	299	static __inline int
	300	__get_cpuid_count (unsigned int __leaf, unsigned int __subleaf,
	301	unsigned int __eax, unsigned int __ebx,
	302	unsigned int __ecx, unsigned int __edx)
	303	{
	304	unsigned int __ext = __leaf & 0x80000000;
a6c78ea3	305	unsigned int __maxlevel = __get_cpuid_max (__ext, 0);
2488ebe5	306
a6c78ea3	307	if (__maxlevel == 0 \|\| __maxlevel < __leaf)
2488ebe5 UB	308	return 0;
	309
	310	__cpuid_count (__leaf, __subleaf, __eax, __ebx, __ecx, __edx);
b3172cab UB	311	return 1;
b3172cab UB	312	}